Boot log: qemu_arm64-virt-gicv3
- Errors: 0
- Kernel Errors: 0
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 4
1 10:51:54.224801 lava-dispatcher, installed at version: 2023.01
2 10:51:54.225000 start: 0 validate
3 10:51:54.225112 Start time: 2023-06-05 10:51:54.225106+00:00 (UTC)
4 10:51:54.226218 Validating that http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1298-g61395b9756bd5/arm64/defconfig/gcc-10/kernel/Image exists
5 10:51:54.584891 Validating that http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230527.0/arm64/rootfs.cpio.gz exists
6 10:51:54.764023 cmd: ['docker', 'pull', 'kernelci/qemu']
7 10:51:54.764267 Calling: 'nice' 'docker' 'pull' 'kernelci/qemu'
8 10:51:54.924034 >> Using default tag: latest
9 10:51:56.049057 >> latest: Pulling from kernelci/qemu
10 10:51:56.080726 >> Digest: sha256:fc85786d1b429cf64a5683fdc5d697be0f1ce54a15ccbe3e596ab02286b2b909
11 10:51:56.080925 >> Status: Image is up to date for kernelci/qemu:latest
12 10:51:56.114067 >> docker.io/kernelci/qemu:latest
13 10:51:56.117720 Returned 0 in 1 seconds
14 10:51:56.251834 cmd: ['docker', 'run', '--rm', '--init', 'kernelci/qemu', 'qemu-system-aarch64', '--version']
15 10:51:56.252139 Calling: 'nice' 'docker' 'run' '--rm' '--init' 'kernelci/qemu' 'qemu-system-aarch64' '--version'
16 10:51:57.962474 >> QEMU emulator version 7.2.2 (Debian 1:7.2+dfsg-7~bpo11+1)
17 10:51:57.962840 >> Copyright (c) 2003-2022 Fabrice Bellard and the QEMU Project developers
18 10:51:59.006797 Returned 0 in 2 seconds
19 10:51:59.108004 validate duration: 4.88
21 10:51:59.108483 start: 1 deployimages (timeout 00:03:00) [common]
22 10:51:59.108654 start: 1.1 lava-overlay (timeout 00:03:00) [common]
23 10:51:59.109142 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/562531/lava-overlay-0wkrcev0
24 10:51:59.109402 makedir: /var/lib/lava/dispatcher/tmp/562531/lava-overlay-0wkrcev0/lava-562531/bin
25 10:51:59.109604 makedir: /var/lib/lava/dispatcher/tmp/562531/lava-overlay-0wkrcev0/lava-562531/tests
26 10:51:59.109813 makedir: /var/lib/lava/dispatcher/tmp/562531/lava-overlay-0wkrcev0/lava-562531/results
27 10:51:59.110012 Creating /var/lib/lava/dispatcher/tmp/562531/lava-overlay-0wkrcev0/lava-562531/bin/lava-add-keys
28 10:51:59.110269 Creating /var/lib/lava/dispatcher/tmp/562531/lava-overlay-0wkrcev0/lava-562531/bin/lava-add-sources
29 10:51:59.110508 Creating /var/lib/lava/dispatcher/tmp/562531/lava-overlay-0wkrcev0/lava-562531/bin/lava-background-process-start
30 10:51:59.110742 Creating /var/lib/lava/dispatcher/tmp/562531/lava-overlay-0wkrcev0/lava-562531/bin/lava-background-process-stop
31 10:51:59.110974 Creating /var/lib/lava/dispatcher/tmp/562531/lava-overlay-0wkrcev0/lava-562531/bin/lava-common-functions
32 10:51:59.111197 Creating /var/lib/lava/dispatcher/tmp/562531/lava-overlay-0wkrcev0/lava-562531/bin/lava-echo-ipv4
33 10:51:59.111426 Creating /var/lib/lava/dispatcher/tmp/562531/lava-overlay-0wkrcev0/lava-562531/bin/lava-install-packages
34 10:51:59.111654 Creating /var/lib/lava/dispatcher/tmp/562531/lava-overlay-0wkrcev0/lava-562531/bin/lava-installed-packages
35 10:51:59.111874 Creating /var/lib/lava/dispatcher/tmp/562531/lava-overlay-0wkrcev0/lava-562531/bin/lava-os-build
36 10:51:59.112102 Creating /var/lib/lava/dispatcher/tmp/562531/lava-overlay-0wkrcev0/lava-562531/bin/lava-probe-channel
37 10:51:59.112327 Creating /var/lib/lava/dispatcher/tmp/562531/lava-overlay-0wkrcev0/lava-562531/bin/lava-probe-ip
38 10:51:59.112553 Creating /var/lib/lava/dispatcher/tmp/562531/lava-overlay-0wkrcev0/lava-562531/bin/lava-target-ip
39 10:51:59.112776 Creating /var/lib/lava/dispatcher/tmp/562531/lava-overlay-0wkrcev0/lava-562531/bin/lava-target-mac
40 10:51:59.113002 Creating /var/lib/lava/dispatcher/tmp/562531/lava-overlay-0wkrcev0/lava-562531/bin/lava-target-storage
41 10:51:59.113232 Creating /var/lib/lava/dispatcher/tmp/562531/lava-overlay-0wkrcev0/lava-562531/bin/lava-test-case
42 10:51:59.113456 Creating /var/lib/lava/dispatcher/tmp/562531/lava-overlay-0wkrcev0/lava-562531/bin/lava-test-event
43 10:51:59.113708 Creating /var/lib/lava/dispatcher/tmp/562531/lava-overlay-0wkrcev0/lava-562531/bin/lava-test-feedback
44 10:51:59.113943 Creating /var/lib/lava/dispatcher/tmp/562531/lava-overlay-0wkrcev0/lava-562531/bin/lava-test-raise
45 10:51:59.114174 Creating /var/lib/lava/dispatcher/tmp/562531/lava-overlay-0wkrcev0/lava-562531/bin/lava-test-reference
46 10:51:59.114400 Creating /var/lib/lava/dispatcher/tmp/562531/lava-overlay-0wkrcev0/lava-562531/bin/lava-test-runner
47 10:51:59.114623 Creating /var/lib/lava/dispatcher/tmp/562531/lava-overlay-0wkrcev0/lava-562531/bin/lava-test-set
48 10:51:59.114846 Creating /var/lib/lava/dispatcher/tmp/562531/lava-overlay-0wkrcev0/lava-562531/bin/lava-test-shell
49 10:51:59.115079 Updating /var/lib/lava/dispatcher/tmp/562531/lava-overlay-0wkrcev0/lava-562531/bin/lava-install-packages (oe)
50 10:51:59.115348 Updating /var/lib/lava/dispatcher/tmp/562531/lava-overlay-0wkrcev0/lava-562531/bin/lava-installed-packages (oe)
51 10:51:59.115577 Creating /var/lib/lava/dispatcher/tmp/562531/lava-overlay-0wkrcev0/lava-562531/environment
52 10:51:59.115766 LAVA metadata
53 10:51:59.115899 - LAVA_JOB_ID=562531
54 10:51:59.116024 - LAVA_DISPATCHER_IP=172.27.0.2
55 10:51:59.116209 start: 1.1.1 lava-vland-overlay (timeout 00:03:00) [common]
56 10:51:59.116339 skipped lava-vland-overlay
57 10:51:59.116486 end: 1.1.1 lava-vland-overlay (duration 00:00:00) [common]
58 10:51:59.116643 start: 1.1.2 lava-multinode-overlay (timeout 00:03:00) [common]
59 10:51:59.116771 skipped lava-multinode-overlay
60 10:51:59.116911 end: 1.1.2 lava-multinode-overlay (duration 00:00:00) [common]
61 10:51:59.117061 start: 1.1.3 test-definition (timeout 00:03:00) [common]
62 10:51:59.117206 Loading test definitions
63 10:51:59.117382 start: 1.1.3.1 inline-repo-action (timeout 00:03:00) [common]
64 10:51:59.117524 Using /lava-562531 at stage 0
65 10:51:59.118113 uuid=562531_1.1.3.1 testdef=None
66 10:51:59.118292 end: 1.1.3.1 inline-repo-action (duration 00:00:00) [common]
67 10:51:59.118449 start: 1.1.3.2 test-overlay (timeout 00:03:00) [common]
68 10:51:59.119332 end: 1.1.3.2 test-overlay (duration 00:00:00) [common]
70 10:51:59.119794 start: 1.1.3.3 test-install-overlay (timeout 00:03:00) [common]
71 10:51:59.120856 end: 1.1.3.3 test-install-overlay (duration 00:00:00) [common]
73 10:51:59.121328 start: 1.1.3.4 test-runscript-overlay (timeout 00:03:00) [common]
74 10:51:59.122329 runner path: /var/lib/lava/dispatcher/tmp/562531/lava-overlay-0wkrcev0/lava-562531/0/tests/0_timesync-off test_uuid 562531_1.1.3.1
75 10:51:59.122608 end: 1.1.3.4 test-runscript-overlay (duration 00:00:00) [common]
77 10:51:59.123061 start: 1.1.3.5 git-repo-action (timeout 00:03:00) [common]
78 10:51:59.123196 Using /lava-562531 at stage 0
79 10:51:59.123380 Fetching tests from https://github.com/kernelci/test-definitions.git
80 10:51:59.123525 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/562531/lava-overlay-0wkrcev0/lava-562531/0/tests/1_kselftest-arm64_qemu'
81 10:52:02.545869 Running '/usr/bin/git checkout kernelci.org
82 10:52:02.710203 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/562531/lava-overlay-0wkrcev0/lava-562531/0/tests/1_kselftest-arm64_qemu/automated/linux/kselftest/kselftest.yaml
83 10:52:02.711373 uuid=562531_1.1.3.5 testdef=None
84 10:52:02.711627 end: 1.1.3.5 git-repo-action (duration 00:00:04) [common]
86 10:52:02.712122 start: 1.1.3.6 test-overlay (timeout 00:02:56) [common]
87 10:52:02.713757 end: 1.1.3.6 test-overlay (duration 00:00:00) [common]
89 10:52:02.714438 start: 1.1.3.7 test-install-overlay (timeout 00:02:56) [common]
90 10:52:02.717353 end: 1.1.3.7 test-install-overlay (duration 00:00:00) [common]
92 10:52:02.718089 start: 1.1.3.8 test-runscript-overlay (timeout 00:02:56) [common]
93 10:52:02.739118 runner path: /var/lib/lava/dispatcher/tmp/562531/lava-overlay-0wkrcev0/lava-562531/0/tests/1_kselftest-arm64_qemu test_uuid 562531_1.1.3.5
94 10:52:02.739395 BOARD='qemu_arm64-virt-gicv3'
95 10:52:02.739560 BRANCH='cip-gitlab'
96 10:52:02.739738 SKIPFILE='/dev/null'
97 10:52:02.739895 SKIP_INSTALL='True'
98 10:52:02.740044 TESTPROG_URL='http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1298-g61395b9756bd5/arm64/defconfig/gcc-10/kselftest.tar.xz'
99 10:52:02.740196 TST_CASENAME=''
100 10:52:02.740341 TST_CMDFILES='arm64'
101 10:52:02.740710 end: 1.1.3.8 test-runscript-overlay (duration 00:00:00) [common]
103 10:52:02.741231 Creating lava-test-runner.conf files
104 10:52:02.741391 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/562531/lava-overlay-0wkrcev0/lava-562531/0 for stage 0
105 10:52:02.741614 - 0_timesync-off
106 10:52:02.741790 - 1_kselftest-arm64_qemu
107 10:52:02.742018 end: 1.1.3 test-definition (duration 00:00:04) [common]
108 10:52:02.742218 start: 1.1.4 compress-overlay (timeout 00:02:56) [common]
109 10:52:11.485092 end: 1.1.4 compress-overlay (duration 00:00:09) [common]
110 10:52:11.485284 start: 1.1.5 persistent-nfs-overlay (timeout 00:02:48) [common]
111 10:52:11.485383 end: 1.1.5 persistent-nfs-overlay (duration 00:00:00) [common]
112 10:52:11.485490 end: 1.1 lava-overlay (duration 00:00:12) [common]
113 10:52:11.485580 start: 1.2 apply-overlay-guest (timeout 00:02:48) [common]
114 10:52:11.485704 Overlay: /var/lib/lava/dispatcher/tmp/562531/compress-overlay-prx03rag/overlay-1.1.4.tar.gz
115 10:52:27.221263 end: 1.2 apply-overlay-guest (duration 00:00:16) [common]
117 10:52:27.222066 start: 1.3 deploy-device-env (timeout 00:02:32) [common]
118 10:52:27.222244 end: 1.3 deploy-device-env (duration 00:00:00) [common]
119 10:52:27.222423 start: 1.4 download-retry (timeout 00:02:32) [common]
120 10:52:27.222647 start: 1.4.1 http-download (timeout 00:02:32) [common]
121 10:52:27.223001 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1298-g61395b9756bd5/arm64/defconfig/gcc-10/kernel/Image
122 10:52:27.223153 saving as /var/lib/lava/dispatcher/tmp/562531/deployimages-utwxp42y/kernel/Image
123 10:52:27.223283 total size: 37356032 (35MB)
124 10:52:27.223407 No compression specified
125 10:52:27.580396 progress 0% (0MB)
126 10:52:28.644116 progress 5% (1MB)
127 10:52:29.000819 progress 10% (3MB)
128 10:52:29.015548 progress 15% (5MB)
129 10:52:29.197109 progress 20% (7MB)
130 10:52:29.560189 progress 25% (8MB)
131 10:52:29.733873 progress 30% (10MB)
132 10:52:29.926746 progress 35% (12MB)
133 10:52:30.098374 progress 40% (14MB)
134 10:52:30.457101 progress 45% (16MB)
135 10:52:30.796565 progress 50% (17MB)
136 10:52:30.990878 progress 55% (19MB)
137 10:52:31.329590 progress 60% (21MB)
138 10:52:31.523402 progress 65% (23MB)
139 10:52:31.860518 progress 70% (24MB)
140 10:52:32.058929 progress 75% (26MB)
141 10:52:32.386829 progress 80% (28MB)
142 10:52:32.589553 progress 85% (30MB)
143 10:52:32.772041 progress 90% (32MB)
144 10:52:33.107155 progress 95% (33MB)
145 10:52:33.301969 progress 100% (35MB)
146 10:52:33.302229 35MB downloaded in 6.08s (5.86MB/s)
147 10:52:33.302513 end: 1.4.1 http-download (duration 00:00:06) [common]
149 10:52:33.303008 end: 1.4 download-retry (duration 00:00:06) [common]
150 10:52:33.303173 start: 1.5 download-retry (timeout 00:02:26) [common]
151 10:52:33.303328 start: 1.5.1 http-download (timeout 00:02:26) [common]
152 10:52:33.303562 Not decompressing ramdisk as can be used compressed.
153 10:52:33.303729 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230527.0/arm64/rootfs.cpio.gz
154 10:52:33.303857 saving as /var/lib/lava/dispatcher/tmp/562531/deployimages-utwxp42y/ramdisk/rootfs.cpio.gz
155 10:52:33.303977 total size: 88976554 (84MB)
156 10:52:33.304095 No compression specified
157 10:52:33.482988 progress 0% (0MB)
158 10:52:34.019537 progress 5% (4MB)
159 10:52:34.554942 progress 10% (8MB)
160 10:52:35.095120 progress 15% (12MB)
161 10:52:35.798847 progress 20% (17MB)
162 10:52:36.436699 progress 25% (21MB)
163 10:52:36.911060 progress 30% (25MB)
164 10:52:37.447995 progress 35% (29MB)
165 10:52:37.997469 progress 40% (33MB)
166 10:52:38.643802 progress 45% (38MB)
167 10:52:39.238016 progress 50% (42MB)
168 10:52:39.788786 progress 55% (46MB)
169 10:52:40.326052 progress 60% (50MB)
170 10:52:40.860498 progress 65% (55MB)
171 10:52:41.400252 progress 70% (59MB)
172 10:52:42.085350 progress 75% (63MB)
173 10:52:42.619016 progress 80% (67MB)
174 10:52:43.160936 progress 85% (72MB)
175 10:52:43.692335 progress 90% (76MB)
176 10:52:44.228041 progress 95% (80MB)
177 10:52:44.603327 progress 100% (84MB)
178 10:52:44.603724 84MB downloaded in 11.30s (7.51MB/s)
179 10:52:44.604006 end: 1.5.1 http-download (duration 00:00:11) [common]
181 10:52:44.604525 end: 1.5 download-retry (duration 00:00:11) [common]
182 10:52:44.604693 end: 1 deployimages (duration 00:00:45) [common]
183 10:52:44.604866 start: 2 boot-image-retry (timeout 00:05:00) [common]
184 10:52:44.605034 start: 2.1 boot-qemu-image (timeout 00:05:00) [common]
185 10:52:44.605206 start: 2.1.1 execute-qemu (timeout 00:05:00) [common]
186 10:52:44.605579 Extending command line for qcow2 test overlay
187 10:52:44.606248 Pulling docker image
188 10:52:44.606420 cmd: ['docker', 'pull', 'kernelci/qemu']
189 10:52:44.606561 Calling: 'nice' 'docker' 'pull' 'kernelci/qemu'
190 10:52:44.747246 >> Using default tag: latest
191 10:52:45.844899 >> latest: Pulling from kernelci/qemu
192 10:52:45.876658 >> Digest: sha256:fc85786d1b429cf64a5683fdc5d697be0f1ce54a15ccbe3e596ab02286b2b909
193 10:52:45.876878 >> Status: Image is up to date for kernelci/qemu:latest
194 10:52:45.956917 >> docker.io/kernelci/qemu:latest
195 10:52:45.961143 Returned 0 in 1 seconds
196 10:52:46.093681 Boot command: docker run --network=host --cap-add=NET_ADMIN --interactive --tty --rm --init --name=lava-docker-qemu-562531-2.1.1-qhtg20u02p --mount=type=bind,source=/var/lib/lava/dispatcher/tmp,destination=/var/lib/lava/dispatcher/tmp kernelci/qemu qemu-system-aarch64 -cpu max,pauth-impdef=on -machine virt,gic-version=3,mte=on,accel=tcg -nographic -net nic,model=virtio,macaddr=52:54:00:12:34:58 -net user -m 1g -monitor none -kernel /var/lib/lava/dispatcher/tmp/562531/deployimages-utwxp42y/kernel/Image -append "console=ttyAMA0,115200 root=/dev/ram0 debug verbose console_msg_format=syslog earlycon" -initrd /var/lib/lava/dispatcher/tmp/562531/deployimages-utwxp42y/ramdisk/rootfs.cpio.gz -drive format=qcow2,file=/var/lib/lava/dispatcher/tmp/562531/apply-overlay-guest-7qz0h004/lava-guest.qcow2,media=disk,if=virtio,id=lavatest
197 10:52:46.213997 started a shell command
198 10:52:46.214675 end: 2.1.1 execute-qemu (duration 00:00:02) [common]
199 10:52:46.214910 end: 2.1 boot-qemu-image (duration 00:00:02) [common]
200 10:52:46.215126 start: 2.2 auto-login-action (timeout 00:04:58) [common]
201 10:52:46.215331 Setting prompt string to ['Linux version [0-9]']
202 10:52:46.215495 auto-login-action: Wait for prompt ['Linux version [0-9]'] (timeout 00:05:00)
203 10:52:48.361799 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x000f0510]
204 10:52:48.362598 start: 2.2.1 login-action (timeout 00:04:56) [common]
205 10:52:48.362777 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
206 10:52:48.362957 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
207 10:52:48.363117 Using line separator: #'\n'#
208 10:52:48.363248 No login prompt set.
209 10:52:48.363398 Parsing kernel messages
210 10:52:48.363556 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
211 10:52:48.363864 [login-action] Waiting for messages, (timeout 00:04:56)
212 10:52:48.365281 [ 0.000000] Linux version 6.1.31 (KernelCI@build-j1609074-arm64-gcc-10-defconfig-2tgzl) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Mon Jun 5 10:37:40 UTC 2023
213 10:52:48.365454 [ 0.000000] random: crng init done
214 10:52:48.365582 [ 0.000000] Machine model: linux,dummy-virt
215 10:52:48.365727 [ 0.000000] efi: UEFI not found.
216 10:52:48.365854 [ 0.000000] earlycon: pl11 at MMIO 0x0000000009000000 (options '')
217 10:52:48.365971 [ 0.000000] printk: bootconsole [pl11] enabled
218 10:52:48.371756 [ 0.000000] NUMA: No NUMA configuration found
219 10:52:48.372308 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000007fffffff]
220 10:52:48.373315 [ 0.000000] NUMA: NODE_DATA [mem 0x7fdf2a00-0x7fdf4fff]
221 10:52:48.377475 [ 0.000000] Zone ranges:
222 10:52:48.378559 [ 0.000000] DMA [mem 0x0000000040000000-0x000000007fffffff]
223 10:52:48.379000 [ 0.000000] DMA32 empty
224 10:52:48.379222 [ 0.000000] Normal empty
225 10:52:48.379429 [ 0.000000] Movable zone start for each node
226 10:52:48.379640 [ 0.000000] Early memory node ranges
227 10:52:48.379868 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000007fffffff]
228 10:52:48.380067 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000007fffffff]
229 10:52:48.395145 [ 0.000000] cma: Reserved 32 MiB at 0x000000007cc00000
230 10:52:48.396401 [ 0.000000] psci: probing for conduit method from DT.
231 10:52:48.396615 [ 0.000000] psci: PSCIv1.1 detected in firmware.
232 10:52:48.396809 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
233 10:52:48.397019 [ 0.000000] psci: Trusted OS migration not required
234 10:52:48.397167 [ 0.000000] psci: SMC Calling Convention v1.0
235 10:52:48.399098 [ 0.000000] percpu: Embedded 20 pages/cpu s44840 r8192 d28888 u81920
236 10:52:48.399538 [ 0.000000] pcpu-alloc: s44840 r8192 d28888 u81920 alloc=20*4096
237 10:52:48.399764 [ 0.000000] pcpu-alloc: [0] 0
238 10:52:48.401006 [ 0.000000] Detected PIPT I-cache on CPU0
239 10:52:48.406520 [ 0.000000] CPU features: detected: Address authentication (IMP DEF algorithm)
240 10:52:48.407040 [ 0.000000] CPU features: detected: GIC system register CPU interface
241 10:52:48.407511 [ 0.000000] CPU features: detected: Hardware dirty bit management
242 10:52:48.407686 [ 0.000000] CPU features: detected: Memory Tagging Extension
243 10:52:48.407925 [ 0.000000] CPU features: detected: Asymmetric MTE Tag Check Fault
244 10:52:48.408089 [ 0.000000] CPU features: detected: Spectre-v4
245 10:52:48.411663 [ 0.000000] alternatives: applying boot alternatives
246 10:52:48.414503 [ 0.000000] Fallback order for Node 0: 0
247 10:52:48.414966 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 258048
248 10:52:48.415146 [ 0.000000] Policy zone: DMA
249 10:52:48.415338 [ 0.000000] Kernel command line: console=ttyAMA0,115200 root=/dev/ram0 debug verbose console_msg_format=syslog earlycon
250 10:52:48.417770 <5>[ 0.000000] Unknown kernel command line parameters \"verbose\", will be passed to user space.
251 10:52:48.420540 <6>[ 0.000000] Dentry cache hash table entries: 131072 (order: 8, 1048576 bytes, linear)
252 10:52:48.420757 <6>[ 0.000000] Inode-cache hash table entries: 65536 (order: 7, 524288 bytes, linear)
253 10:52:48.421172 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
254 10:52:48.430389 <6>[ 0.000000] Memory: 870672K/1048576K available (16192K kernel code, 3712K rwdata, 8856K rodata, 7552K init, 609K bss, 145136K reserved, 32768K cma-reserved)
255 10:52:48.436186 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
256 10:52:48.442821 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
257 10:52:48.443149 <6>[ 0.000000] rcu: RCU event tracing is enabled.
258 10:52:48.443252 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=1.
259 10:52:48.443429 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
260 10:52:48.443547 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
261 10:52:48.443859 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
262 10:52:48.443974 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=1
263 10:52:48.444786 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
264 10:52:48.451770 <6>[ 0.000000] GICv3: 224 SPIs implemented
265 10:52:48.452088 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
266 10:52:48.453630 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
267 10:52:48.453968 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
268 10:52:48.454623 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x00000000080a0000
269 10:52:48.459413 <6>[ 0.000000] ITS [mem 0x08080000-0x0809ffff]
270 10:52:48.460368 <6>[ 0.000000] ITS@0x0000000008080000: allocated 8192 Devices @42830000 (indirect, esz 8, psz 64K, shr 1)
271 10:52:48.460545 <6>[ 0.000000] ITS@0x0000000008080000: allocated 8192 Interrupt Collections @42840000 (flat, esz 8, psz 64K, shr 1)
272 10:52:48.461055 <6>[ 0.000000] GICv3: using LPI property table @0x0000000042850000
273 10:52:48.461967 <6>[ 0.000000] GICv3: CPU0: using allocated LPI pending table @0x0000000042860000
274 10:52:48.463002 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
275 10:52:48.471507 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 62.50MHz (virt).
276 10:52:48.471988 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0x1ffffffffffffff max_cycles: 0x1cd42e208c, max_idle_ns: 881590405314 ns
277 10:52:48.472515 <6>[ 0.000077] sched_clock: 57 bits at 63MHz, resolution 16ns, wraps every 4398046511096ns
278 10:52:48.490176 <6>[ 0.015143] Console: colour dummy device 80x25
279 10:52:48.494447 <6>[ 0.021508] Calibrating delay loop (skipped), value calculated using timer frequency.. 125.00 BogoMIPS (lpj=250000)
280 10:52:48.494888 <6>[ 0.022718] pid_max: default: 32768 minimum: 301
281 10:52:48.496100 <6>[ 0.023995] LSM: Security Framework initializing
282 10:52:48.500582 <6>[ 0.028215] Mount-cache hash table entries: 2048 (order: 2, 16384 bytes, linear)
283 10:52:48.500835 <6>[ 0.028495] Mountpoint-cache hash table entries: 2048 (order: 2, 16384 bytes, linear)
284 10:52:48.534360 <4>[ 0.062160] cacheinfo: Unable to detect cache hierarchy for CPU 0
285 10:52:48.541198 <6>[ 0.068772] cblist_init_generic: Setting adjustable number of callback queues.
286 10:52:48.541409 <6>[ 0.069089] cblist_init_generic: Setting shift to 0 and lim to 1.
287 10:52:48.541856 <6>[ 0.069637] cblist_init_generic: Setting shift to 0 and lim to 1.
288 10:52:48.543522 <6>[ 0.071409] rcu: Hierarchical SRCU implementation.
289 10:52:48.543861 <6>[ 0.071580] rcu: Max phase no-delay instances is 1000.
290 10:52:48.549633 <6>[ 0.077489] Platform MSI: its@8080000 domain created
291 10:52:48.550489 <6>[ 0.078180] PCI/MSI: /intc@8000000/its@8080000 domain created
292 10:52:48.550948 <6>[ 0.078728] fsl-mc MSI: its@8080000 domain created
293 10:52:48.554029 <6>[ 0.081879] EFI services will not be available.
294 10:52:48.555130 <6>[ 0.083012] smp: Bringing up secondary CPUs ...
295 10:52:48.555604 <6>[ 0.083224] smp: Brought up 1 node, 1 CPU
296 10:52:48.555817 <6>[ 0.083341] SMP: Total of 1 processors activated.
297 10:52:48.556027 <6>[ 0.083653] CPU features: detected: Branch Target Identification
298 10:52:48.556193 <6>[ 0.083824] CPU features: detected: 32-bit EL0 Support
299 10:52:48.556369 <6>[ 0.083959] CPU features: detected: 32-bit EL1 Support
300 10:52:48.556551 <6>[ 0.084067] CPU features: detected: ARMv8.4 Translation Table Level
301 10:52:48.556786 <6>[ 0.084216] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
302 10:52:48.556967 <6>[ 0.084429] CPU features: detected: Common not Private translations
303 10:52:48.557142 <6>[ 0.084556] CPU features: detected: CRC32 instructions
304 10:52:48.557342 <6>[ 0.084804] CPU features: detected: E0PD
305 10:52:48.557522 <6>[ 0.084965] CPU features: detected: Generic authentication (IMP DEF algorithm)
306 10:52:48.557758 <6>[ 0.085102] CPU features: detected: RCpc load-acquire (LDAPR)
307 10:52:48.557996 <6>[ 0.085221] CPU features: detected: LSE atomic instructions
308 10:52:48.558206 <6>[ 0.085330] CPU features: detected: Privileged Access Never
309 10:52:48.558398 <6>[ 0.085441] CPU features: detected: RAS Extension Support
310 10:52:48.558619 <6>[ 0.085555] CPU features: detected: Random Number Generator
311 10:52:48.558797 <6>[ 0.085660] CPU features: detected: Speculation barrier (SB)
312 10:52:48.558949 <6>[ 0.085791] CPU features: detected: Stage-2 Force Write-Back
313 10:52:48.559139 <6>[ 0.085909] CPU features: detected: TLB range maintenance instructions
314 10:52:48.559279 <6>[ 0.086092] CPU features: detected: Scalable Matrix Extension
315 10:52:48.559427 <6>[ 0.086204] CPU features: detected: FA64
316 10:52:48.559572 <6>[ 0.086288] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
317 10:52:48.559717 <6>[ 0.086420] CPU features: detected: Scalable Vector Extension
318 10:52:48.571009 <6>[ 0.096115] SVE: maximum available vector length 256 bytes per vector
319 10:52:48.571360 <6>[ 0.099204] SVE: default vector length 64 bytes per vector
320 10:52:48.573401 <6>[ 0.101154] SME: minimum available vector length 16 bytes per vector
321 10:52:48.573784 <6>[ 0.101320] SME: maximum available vector length 256 bytes per vector
322 10:52:48.574003 <6>[ 0.101445] SME: default vector length 32 bytes per vector
323 10:52:48.574193 <6>[ 0.101849] CPU: All CPU(s) started at EL1
324 10:52:48.574386 <6>[ 0.102173] alternatives: applying system-wide alternatives
325 10:52:48.626855 <6>[ 0.154598] devtmpfs: initialized
326 10:52:48.647317 <6>[ 0.174691] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
327 10:52:48.647783 <6>[ 0.175476] futex hash table entries: 256 (order: 2, 16384 bytes, linear)
328 10:52:48.653526 <6>[ 0.181402] pinctrl core: initialized pinctrl subsystem
329 10:52:48.664873 <6>[ 0.192722] DMI not present or invalid.
330 10:52:48.674069 <6>[ 0.201898] NET: Registered PF_NETLINK/PF_ROUTE protocol family
331 10:52:48.686103 <6>[ 0.213534] DMA: preallocated 128 KiB GFP_KERNEL pool for atomic allocations
332 10:52:48.686556 <6>[ 0.214355] DMA: preallocated 128 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
333 10:52:48.687037 <6>[ 0.214748] DMA: preallocated 128 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
334 10:52:48.687515 <6>[ 0.215166] audit: initializing netlink subsys (disabled)
335 10:52:48.693230 <5>[ 0.221049] audit: type=2000 audit(0.180:1): state=initialized audit_enabled=0 res=1
336 10:52:48.695176 <6>[ 0.222969] thermal_sys: Registered thermal governor 'step_wise'
337 10:52:48.695815 <6>[ 0.223041] thermal_sys: Registered thermal governor 'power_allocator'
338 10:52:48.695977 <6>[ 0.223582] cpuidle: using governor menu
339 10:52:48.697394 <6>[ 0.225240] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
340 10:52:48.697967 <6>[ 0.225802] ASID allocator initialised with 65536 entries
341 10:52:48.703899 <6>[ 0.231755] Serial: AMBA PL011 UART driver
342 10:52:48.753483 <6>[ 0.281263] 9000000.pl011: ttyAMA0 at MMIO 0x9000000 (irq = 13, base_baud = 0) is a PL011 rev1
343 10:52:48.755479 <6>[ 0.282969] printk: console [ttyAMA0] enabled
344 10:52:48.755666 <6>[ 0.282969] printk: console [ttyAMA0] enabled
345 10:52:48.755862 <6>[ 0.283507] printk: bootconsole [pl11] disabled
346 10:52:48.756002 <6>[ 0.283507] printk: bootconsole [pl11] disabled
347 10:52:48.766971 <6>[ 0.294805] KASLR enabled
348 10:52:48.800501 <6>[ 0.328251] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
349 10:52:48.800995 <6>[ 0.328501] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
350 10:52:48.801110 <6>[ 0.328742] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
351 10:52:48.801223 <6>[ 0.328959] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
352 10:52:48.801558 <6>[ 0.329170] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
353 10:52:48.801660 <6>[ 0.329401] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
354 10:52:48.801999 <6>[ 0.329547] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
355 10:52:48.802103 <6>[ 0.329793] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
356 10:52:48.812302 <6>[ 0.339885] ACPI: Interpreter disabled.
357 10:52:48.821113 <6>[ 0.348863] iommu: Default domain type: Translated
358 10:52:48.821604 <6>[ 0.349075] iommu: DMA domain TLB invalidation policy: strict mode
359 10:52:48.823215 <5>[ 0.351055] SCSI subsystem initialized
360 10:52:48.824394 <7>[ 0.352074] libata version 3.00 loaded.
361 10:52:48.825897 <6>[ 0.353571] usbcore: registered new interface driver usbfs
362 10:52:48.826260 <6>[ 0.354025] usbcore: registered new interface driver hub
363 10:52:48.826652 <6>[ 0.354448] usbcore: registered new device driver usb
364 10:52:48.829985 <6>[ 0.357594] pps_core: LinuxPPS API ver. 1 registered
365 10:52:48.830239 <6>[ 0.357768] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
366 10:52:48.830412 <6>[ 0.358111] PTP clock support registered
367 10:52:48.830866 <6>[ 0.358745] EDAC MC: Ver: 3.0.0
368 10:52:48.836888 <6>[ 0.364685] FPGA manager framework
369 10:52:48.837962 <6>[ 0.365554] Advanced Linux Sound Architecture Driver Initialized.
370 10:52:48.847271 <6>[ 0.375055] vgaarb: loaded
371 10:52:48.851689 <6>[ 0.379187] clocksource: Switched to clocksource arch_sys_counter
372 10:52:48.854524 <5>[ 0.382034] VFS: Disk quotas dquot_6.6.0
373 10:52:48.854772 <6>[ 0.382373] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
374 10:52:48.856907 <6>[ 0.384600] pnp: PnP ACPI: disabled
375 10:52:48.875184 <6>[ 0.403013] NET: Registered PF_INET protocol family
376 10:52:48.877751 <6>[ 0.405300] IP idents hash table entries: 16384 (order: 5, 131072 bytes, linear)
377 10:52:48.883172 <6>[ 0.410607] tcp_listen_portaddr_hash hash table entries: 512 (order: 1, 8192 bytes, linear)
378 10:52:48.883407 <6>[ 0.410991] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
379 10:52:48.883617 <6>[ 0.411255] TCP established hash table entries: 8192 (order: 4, 65536 bytes, linear)
380 10:52:48.884078 <6>[ 0.411699] TCP bind hash table entries: 8192 (order: 6, 262144 bytes, linear)
381 10:52:48.884494 <6>[ 0.412263] TCP: Hash tables configured (established 8192 bind 8192)
382 10:52:48.885782 <6>[ 0.413450] UDP hash table entries: 512 (order: 2, 16384 bytes, linear)
383 10:52:48.886249 <6>[ 0.413882] UDP-Lite hash table entries: 512 (order: 2, 16384 bytes, linear)
384 10:52:48.887647 <6>[ 0.415240] NET: Registered PF_UNIX/PF_LOCAL protocol family
385 10:52:48.889984 <6>[ 0.417628] RPC: Registered named UNIX socket transport module.
386 10:52:48.890102 <6>[ 0.417889] RPC: Registered udp transport module.
387 10:52:48.890199 <6>[ 0.418049] RPC: Registered tcp transport module.
388 10:52:48.890517 <6>[ 0.418207] RPC: Registered tcp NFSv4.1 backchannel transport module.
389 10:52:48.890844 <6>[ 0.418547] PCI: CLS 0 bytes, default 64
390 10:52:48.894887 <6>[ 0.422721] Unpacking initramfs...
391 10:52:48.903823 <6>[ 0.431418] hw perfevents: enabled with armv8_pmuv3 PMU driver, 7 counters available
392 10:52:48.904568 <6>[ 0.432250] kvm [1]: HYP mode not available
393 10:52:48.909360 <5>[ 0.437173] Initialise system trusted keyrings
394 10:52:48.916710 <6>[ 0.444287] workingset: timestamp_bits=42 max_order=18 bucket_order=0
395 10:52:48.958917 <6>[ 0.486645] squashfs: version 4.0 (2009/01/31) Phillip Lougher
396 10:52:48.969831 <5>[ 0.497338] NFS: Registering the id_resolver key type
397 10:52:48.970292 <5>[ 0.498064] Key type id_resolver registered
398 10:52:48.970505 <5>[ 0.498312] Key type id_legacy registered
399 10:52:48.975588 <6>[ 0.503126] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
400 10:52:48.975848 <6>[ 0.503428] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
401 10:52:48.976842 <6>[ 0.504530] 9p: Installing v9fs 9p2000 file system support
402 10:52:49.048183 <5>[ 0.575853] Key type asymmetric registered
403 10:52:49.048717 <5>[ 0.576143] Asymmetric key parser 'x509' registered
404 10:52:49.049270 <6>[ 0.576748] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 245)
405 10:52:49.049533 <6>[ 0.577147] io scheduler mq-deadline registered
406 10:52:49.049745 <6>[ 0.577391] io scheduler kyber registered
407 10:52:49.116176 <6>[ 0.643586] pl061_gpio 9030000.pl061: PL061 GPIO chip registered
408 10:52:49.126747 <6>[ 0.654394] pci-host-generic 4010000000.pcie: host bridge /pcie@10000000 ranges:
409 10:52:49.132110 <6>[ 0.659543] pci-host-generic 4010000000.pcie: IO 0x003eff0000..0x003effffff -> 0x0000000000
410 10:52:49.132580 <6>[ 0.660371] pci-host-generic 4010000000.pcie: MEM 0x0010000000..0x003efeffff -> 0x0010000000
411 10:52:49.133133 <6>[ 0.660658] pci-host-generic 4010000000.pcie: MEM 0x8000000000..0xffffffffff -> 0x8000000000
412 10:52:49.133577 <4>[ 0.661348] pci-host-generic 4010000000.pcie: Memory resource size exceeds max for 32 bits
413 10:52:49.134656 <6>[ 0.662168] pci-host-generic 4010000000.pcie: ECAM at [mem 0x4010000000-0x401fffffff] for [bus 00-ff]
414 10:52:49.140345 <6>[ 0.667924] pci-host-generic 4010000000.pcie: PCI host bridge to bus 0000:00
415 10:52:49.140572 <6>[ 0.668369] pci_bus 0000:00: root bus resource [bus 00-ff]
416 10:52:49.141092 <6>[ 0.668612] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]
417 10:52:49.141276 <6>[ 0.668836] pci_bus 0000:00: root bus resource [mem 0x10000000-0x3efeffff]
418 10:52:49.141488 <6>[ 0.669026] pci_bus 0000:00: root bus resource [mem 0x8000000000-0xffffffffff]
419 10:52:49.142955 <6>[ 0.670618] pci 0000:00:00.0: [1b36:0008] type 00 class 0x060000
420 10:52:49.150619 <6>[ 0.678268] pci 0000:00:01.0: [1af4:1000] type 00 class 0x020000
421 10:52:49.150859 <6>[ 0.678706] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x001f]
422 10:52:49.155320 <6>[ 0.682971] pci 0000:00:01.0: reg 0x14: [mem 0x00000000-0x00000fff]
423 10:52:49.155554 <6>[ 0.683221] pci 0000:00:01.0: reg 0x20: [mem 0x00000000-0x00003fff 64bit pref]
424 10:52:49.155761 <6>[ 0.683497] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x0003ffff pref]
425 10:52:49.156232 <6>[ 0.684095] pci 0000:00:02.0: [1af4:1001] type 00 class 0x010000
426 10:52:49.156436 <6>[ 0.684293] pci 0000:00:02.0: reg 0x10: [io 0x0000-0x007f]
427 10:52:49.156643 <6>[ 0.684440] pci 0000:00:02.0: reg 0x14: [mem 0x00000000-0x00000fff]
428 10:52:49.156873 <6>[ 0.684620] pci 0000:00:02.0: reg 0x20: [mem 0x00000000-0x00003fff 64bit pref]
429 10:52:49.163855 <6>[ 0.691472] pci 0000:00:01.0: BAR 6: assigned [mem 0x10000000-0x1003ffff pref]
430 10:52:49.164373 <6>[ 0.691958] pci 0000:00:01.0: BAR 4: assigned [mem 0x8000000000-0x8000003fff 64bit pref]
431 10:52:49.164618 <6>[ 0.692297] pci 0000:00:02.0: BAR 4: assigned [mem 0x8000004000-0x8000007fff 64bit pref]
432 10:52:49.164790 <6>[ 0.692547] pci 0000:00:01.0: BAR 1: assigned [mem 0x10040000-0x10040fff]
433 10:52:49.165199 <6>[ 0.692813] pci 0000:00:02.0: BAR 1: assigned [mem 0x10041000-0x10041fff]
434 10:52:49.165341 <6>[ 0.693013] pci 0000:00:02.0: BAR 0: assigned [io 0x1000-0x107f]
435 10:52:49.165442 <6>[ 0.693220] pci 0000:00:01.0: BAR 0: assigned [io 0x1080-0x109f]
436 10:52:49.180195 <6>[ 0.708078] EINJ: ACPI disabled.
437 10:52:49.262635 <6>[ 0.790172] virtio-pci 0000:00:01.0: enabling device (0000 -> 0003)
438 10:52:49.269521 <6>[ 0.797082] virtio-pci 0000:00:02.0: enabling device (0000 -> 0003)
439 10:52:49.299546 <6>[ 0.827314] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
440 10:52:49.312320 <6>[ 0.840151] SuperH (H)SCI(F) driver initialized
441 10:52:49.313724 <6>[ 0.841555] msm_serial: driver initialized
442 10:52:49.322429 <4>[ 0.850186] cacheinfo: Unable to detect cache hierarchy for CPU 0
443 10:52:49.360227 <6>[ 0.887958] loop: module loaded
444 10:52:49.361173 <6>[ 0.888948] virtio_blk virtio1: 1/0/0 default/read/poll queues
445 10:52:49.378463 <5>[ 0.906102] virtio_blk virtio1: [vda] 1048576 512-byte logical blocks (537 MB/512 MiB)
446 10:52:49.409473 <6>[ 0.937180] megasas: 07.719.03.00-rc1
447 10:52:49.427981 <5>[ 0.955616] physmap-flash 0.flash: physmap platform flash device: [mem 0x00000000-0x03ffffff]
448 10:52:49.429690 <6>[ 0.957305] 0.flash: Found 2 x16 devices at 0x0 in 32-bit bank. Manufacturer ID 0x000000 Chip ID 0x000000
449 10:52:49.430595 <6>[ 0.958102] Intel/Sharp Extended Query Table at 0x0031
450 10:52:49.435341 <6>[ 0.963146] Using buffer write method
451 10:52:49.435858 <7>[ 0.963585] erase region 0: offset=0x0,size=0x40000,blocks=256
452 10:52:49.436376 <5>[ 0.963984] physmap-flash 0.flash: physmap platform flash device: [mem 0x04000000-0x07ffffff]
453 10:52:49.437251 <6>[ 0.964727] 0.flash: Found 2 x16 devices at 0x0 in 32-bit bank. Manufacturer ID 0x000000 Chip ID 0x000000
454 10:52:49.437417 <6>[ 0.965028] Intel/Sharp Extended Query Table at 0x0031
455 10:52:49.437830 <6>[ 0.965627] Using buffer write method
456 10:52:49.438000 <7>[ 0.965802] erase region 0: offset=0x0,size=0x40000,blocks=256
457 10:52:49.438163 <5>[ 0.966056] Concatenating MTD devices:
458 10:52:49.438321 <5>[ 0.966203] (0): \"0.flash\"
459 10:52:49.438441 <5>[ 0.966325] (1): \"0.flash\"
460 10:52:49.438784 <5>[ 0.966477] into device \"0.flash\"
461 10:52:54.148988 <6>[ 5.676697] Freeing initrd memory: 86888K
462 10:52:54.260774 <6>[ 5.788504] tun: Universal TUN/TAP device driver, 1.6
463 10:52:54.270280 <6>[ 5.798127] thunder_xcv, ver 1.0
464 10:52:54.270803 <6>[ 5.798373] thunder_bgx, ver 1.0
465 10:52:54.270963 <6>[ 5.798643] nicpf, ver 1.0
466 10:52:54.274306 <6>[ 5.801891] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
467 10:52:54.274513 <6>[ 5.802117] hns3: Copyright (c) 2017 Huawei Corporation.
468 10:52:54.274827 <6>[ 5.802572] hclge is initializing
469 10:52:54.275149 <6>[ 5.802834] e1000: Intel(R) PRO/1000 Network Driver
470 10:52:54.275250 <6>[ 5.803095] e1000: Copyright (c) 1999-2006 Intel Corporation.
471 10:52:54.275771 <6>[ 5.803415] e1000e: Intel(R) PRO/1000 Network Driver
472 10:52:54.275858 <6>[ 5.803581] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
473 10:52:54.276161 <6>[ 5.803955] igb: Intel(R) Gigabit Ethernet Network Driver
474 10:52:54.276475 <6>[ 5.804120] igb: Copyright (c) 2007-2014 Intel Corporation.
475 10:52:54.276797 <6>[ 5.804437] igbvf: Intel(R) Gigabit Virtual Function Network Driver
476 10:52:54.276911 <6>[ 5.804622] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
477 10:52:54.277992 <6>[ 5.805624] sky2: driver version 1.30
478 10:52:54.280850 <6>[ 5.808455] VFIO - User Level meta-driver version: 0.3
479 10:52:54.289389 <6>[ 5.817024] usbcore: registered new interface driver usb-storage
480 10:52:54.298289 <6>[ 5.825962] rtc-pl031 9010000.pl031: registered as rtc0
481 10:52:54.299396 <6>[ 5.826787] rtc-pl031 9010000.pl031: setting system clock to 2023-06-05T10:52:54 UTC (1685962374)
482 10:52:54.301070 <6>[ 5.828922] i2c_dev: i2c /dev entries driver
483 10:52:54.316104 <6>[ 5.843949] sdhci: Secure Digital Host Controller Interface driver
484 10:52:54.316603 <6>[ 5.844125] sdhci: Copyright(c) Pierre Ossman
485 10:52:54.318389 <6>[ 5.846026] Synopsys Designware Multimedia Card Interface Driver
486 10:52:54.320738 <6>[ 5.848395] sdhci-pltfm: SDHCI platform and OF driver helper
487 10:52:54.325372 <6>[ 5.853018] ledtrig-cpu: registered to indicate activity on CPUs
488 10:52:54.330796 <6>[ 5.858403] usbcore: registered new interface driver usbhid
489 10:52:54.330965 <6>[ 5.858594] usbhid: USB HID core driver
490 10:52:54.346720 <6>[ 5.874323] NET: Registered PF_PACKET protocol family
491 10:52:54.347614 <6>[ 5.875511] 9pnet: Installing 9P2000 support
492 10:52:54.348062 <5>[ 5.875878] Key type dns_resolver registered
493 10:52:54.349120 <6>[ 5.877014] registered taskstats version 1
494 10:52:54.349550 <5>[ 5.877362] Loading compiled-in X.509 certificates
495 10:52:54.370005 <6>[ 5.897575] input: gpio-keys as /devices/platform/gpio-keys/input/input0
496 10:52:54.377013 <6>[ 5.904634] ALSA device list:
497 10:52:54.377194 <6>[ 5.904812] No soundcards found.
498 10:52:54.379948 <6>[ 5.907586] uart-pl011 9000000.pl011: no DMA platform data
499 10:52:54.435388 <6>[ 5.963173] Freeing unused kernel memory: 7552K
500 10:52:54.436238 <6>[ 5.964029] Run /init as init process
501 10:52:54.436439 <7>[ 5.964144] with arguments:
502 10:52:54.436892 <7>[ 5.964252] /init
503 10:52:54.437052 <7>[ 5.964341] verbose
504 10:52:54.437181 <7>[ 5.964433] with environment:
505 10:52:54.437303 <7>[ 5.964556] HOME=/
506 10:52:54.437422 <7>[ 5.964655] TERM=linux
507 10:52:54.568199 <30>[ 6.095586] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
508 10:52:54.569202 <31>[ 6.096900] systemd[1]: No virtualization found in DMI
509 10:52:54.570128 <31>[ 6.097851] systemd[1]: UML virtualization not found in /proc/cpuinfo.
510 10:52:54.570242 <31>[ 6.098133] systemd[1]: No virtualization found in CPUID
511 10:52:54.570756 <31>[ 6.098421] systemd[1]: Virtualization XEN not found, /proc/xen does not exist
512 10:52:54.572309 <31>[ 6.099887] systemd[1]: Virtualization QEMU: \"fw-cfg\" present in /proc/device-tree/fw-cfg@9020000
513 10:52:54.572498 <31>[ 6.100280] systemd[1]: Found VM virtualization qemu
514 10:52:54.572669 <30>[ 6.100489] systemd[1]: Detected virtualization qemu.
515 10:52:54.573071 <30>[ 6.100833] systemd[1]: Detected architecture arm64.
516 10:52:54.573473 <31>[ 6.101234] systemd[1]: Detected initialized system, this is not the first boot.
517 10:52:54.577506
518 10:52:54.577908 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
519 10:52:54.578069
520 10:52:54.579969 <30>[ 6.107632] systemd[1]: Set hostname to <debian-bullseye-arm64>.
521 10:52:54.598658 <31>[ 6.126221] systemd[1]: Successfully added address 127.0.0.1 to loopback interface
522 10:52:54.599844 <31>[ 6.127527] systemd[1]: Failed to add address ::1 to loopback interface: Operation not supported
523 10:52:54.600284 <31>[ 6.128095] systemd[1]: Successfully brought loopback interface up
524 10:52:54.604953 <31>[ 6.132611] systemd[1]: Setting 'fs/file-max' to '9223372036854775807'.
525 10:52:54.616540 <31>[ 6.144202] systemd[1]: Found cgroup2 on /sys/fs/cgroup/, full unified hierarchy
526 10:52:54.616885 <31>[ 6.144492] systemd[1]: Unified cgroup hierarchy is located at /sys/fs/cgroup.
527 10:52:54.658224 <31>[ 6.185681] systemd[1]: Got EBADF when using BPF_F_ALLOW_MULTI, which indicates it is supported. Yay!
528 10:52:54.660007 <31>[ 6.187596] systemd[1]: Controller 'cpu' supported: yes
529 10:52:54.660173 <31>[ 6.187841] systemd[1]: Controller 'cpuacct' supported: no
530 10:52:54.660511 <31>[ 6.188062] systemd[1]: Controller 'cpuset' supported: yes
531 10:52:54.660878 <31>[ 6.188296] systemd[1]: Controller 'io' supported: yes
532 10:52:54.660974 <31>[ 6.188546] systemd[1]: Controller 'blkio' supported: no
533 10:52:54.661453 <31>[ 6.188771] systemd[1]: Controller 'memory' supported: yes
534 10:52:54.661645 <31>[ 6.189019] systemd[1]: Controller 'devices' supported: no
535 10:52:54.661768 <31>[ 6.189255] systemd[1]: Controller 'pids' supported: yes
536 10:52:54.661869 <31>[ 6.189471] systemd[1]: Controller 'bpf-firewall' supported: yes
537 10:52:54.661959 <31>[ 6.189699] systemd[1]: Controller 'bpf-devices' supported: yes
538 10:52:54.663615 <31>[ 6.191261] systemd[1]: Set up TFD_TIMER_CANCEL_ON_SET timerfd.
539 10:52:54.663998 <31>[ 6.191701] systemd[1]: Failed to stat /etc/localtime, ignoring: No such file or directory
540 10:52:54.664710 <31>[ 6.192340] systemd[1]: /etc/localtime doesn't exist yet, watching /etc instead.
541 10:52:54.673253 <31>[ 6.200852] systemd[1]: Enabling (yes) showing of status (commandline).
542 10:52:54.681196 <31>[ 6.208787] systemd[1]: Successfully forked off '(sd-executor)' as PID 94.
543 10:52:54.690696 <31>[ 6.218318] systemd[94]: Successfully forked off '(direxec)' as PID 95.
544 10:52:54.692819 <31>[ 6.220539] systemd[94]: Successfully forked off '(direxec)' as PID 96.
545 10:52:54.694761 <31>[ 6.222435] systemd[94]: Successfully forked off '(direxec)' as PID 97.
546 10:52:54.712139 <31>[ 6.239747] systemd[94]: Successfully forked off '(direxec)' as PID 98.
547 10:52:54.714067 <31>[ 6.241766] systemd[94]: Successfully forked off '(direxec)' as PID 99.
548 10:52:54.894070 <31>[ 6.421515] systemd-bless-boot-generator[95]: Skipping generator, not an EFI boot.
549 10:52:54.900735 <31>[ 6.428275] systemd-fstab-generator[96]: Parsing /etc/fstab...
550 10:52:54.902726 <31>[ 6.430349] systemd-fstab-generator[96]: Found entry what=/dev/disk/by-uuid/ffe0be16-960b-4f4f-abe2-c028c6995c76 where=/ type=ext4 makefs=no growfs=no noauto=no nofail=no
551 10:52:54.911728 <31>[ 6.439362] systemd-getty-generator[97]: Automatically adding serial getty for /dev/ttyAMA0.
552 10:52:54.913060 <31>[ 6.440701] systemd-getty-generator[97]: SELinux enabled state cached to: disabled
553 10:52:54.925577 <31>[ 6.453170] systemd-fstab-generator[96]: Checking was requested for /dev/disk/by-uuid/ffe0be16-960b-4f4f-abe2-c028c6995c76, but fsck.ext4 does not exist.
554 10:52:54.930867 <31>[ 6.458478] systemd[94]: /usr/lib/systemd/system-generators/systemd-getty-generator succeeded.
555 10:52:54.933253 <31>[ 6.461060] systemd-fstab-generator[96]: SELinux enabled state cached to: disabled
556 10:52:54.938568 <31>[ 6.466169] systemd[94]: /usr/lib/systemd/system-generators/systemd-fstab-generator succeeded.
557 10:52:54.938804 <31>[ 6.466566] systemd[94]: /usr/lib/systemd/system-generators/systemd-run-generator succeeded.
558 10:52:54.939830 <31>[ 6.467392] systemd[94]: /usr/lib/systemd/system-generators/systemd-veritysetup-generator succeeded.
559 10:52:54.940065 <31>[ 6.467816] systemd[94]: /usr/lib/systemd/system-generators/systemd-bless-boot-generator succeeded.
560 10:52:54.942735 <31>[ 6.470346] systemd[1]: (sd-executor) succeeded.
561 10:52:54.944613 <31>[ 6.472269] systemd[1]: Looking for unit files in (higher priority first):
562 10:52:54.944724 <31>[ 6.472497] systemd[1]: /etc/systemd/system.control
563 10:52:54.944827 <31>[ 6.472665] systemd[1]: /run/systemd/system.control
564 10:52:54.945156 <31>[ 6.472834] systemd[1]: /run/systemd/transient
565 10:52:54.945259 <31>[ 6.472992] systemd[1]: /run/systemd/generator.early
566 10:52:54.945355 <31>[ 6.473134] systemd[1]: /etc/systemd/system
567 10:52:54.945499 <31>[ 6.473305] systemd[1]: /etc/systemd/system.attached
568 10:52:54.946047 <31>[ 6.473474] systemd[1]: /run/systemd/system
569 10:52:54.946315 <31>[ 6.473635] systemd[1]: /run/systemd/system.attached
570 10:52:54.946547 <31>[ 6.473825] systemd[1]: /run/systemd/generator
571 10:52:54.946741 <31>[ 6.474000] systemd[1]: /usr/local/lib/systemd/system
572 10:52:54.946928 <31>[ 6.474169] systemd[1]: /lib/systemd/system
573 10:52:54.947108 <31>[ 6.474324] systemd[1]: /usr/lib/systemd/system
574 10:52:54.947316 <31>[ 6.474453] systemd[1]: /run/systemd/generator.late
575 10:52:54.981700 <31>[ 6.509221] systemd[1]: Modification times have changed, need to update cache.
576 10:52:54.983141 <31>[ 6.510758] systemd[1]: unit_file_build_name_map: alias: /etc/systemd/system/dbus-org.freedesktop.network1.service → systemd-networkd.service
577 10:52:54.984676 <31>[ 6.512276] systemd[1]: unit_file_build_name_map: alias: /etc/systemd/system/dbus-org.freedesktop.timesync1.service → systemd-timesyncd.service
578 10:52:54.985457 <31>[ 6.513045] systemd[1]: unit_file_build_name_map: alias: /etc/systemd/system/dbus-org.freedesktop.resolve1.service → systemd-resolved.service
579 10:52:54.986345 <31>[ 6.514004] systemd[1]: unit_file_build_name_map: normal unit file: /run/systemd/generator/-.mount
580 10:52:54.987227 <31>[ 6.514814] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-journald@.service
581 10:52:54.987949 <31>[ 6.515509] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/console-getty.service
582 10:52:54.988168 <31>[ 6.515911] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/fstrim.timer
583 10:52:54.988641 <31>[ 6.516280] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-ask-password-wall.path
584 10:52:54.989187 <31>[ 6.516656] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-rfkill.service
585 10:52:54.989378 <31>[ 6.517002] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/poweroff.target
586 10:52:54.989893 <31>[ 6.517401] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/network-pre.target
587 10:52:54.990714 <31>[ 6.518107] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/runlevel4.target → multi-user.target
588 10:52:54.990905 <31>[ 6.518478] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/suspend-then-hibernate.target
589 10:52:54.991720 <31>[ 6.519203] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/network.target
590 10:52:54.992548 <31>[ 6.519939] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/runlevel5.target → graphical.target
591 10:52:54.992748 <31>[ 6.520277] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-journald.service
592 10:52:54.992929 <31>[ 6.520582] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-update-utmp-runlevel.service
593 10:52:54.993448 <31>[ 6.520942] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/initrd-root-fs.target
594 10:52:54.993628 <31>[ 6.521283] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/slices.target
595 10:52:54.994400 <31>[ 6.521910] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/kmod.service → systemd-modules-load.service
596 10:52:54.994615 <31>[ 6.522276] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-update-utmp.service
597 10:52:54.995561 <31>[ 6.523138] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/runlevel1.target → rescue.target
598 10:52:54.995793 <31>[ 6.523500] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/cryptsetup-pre.target
599 10:52:54.996357 <31>[ 6.523810] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/system-update-pre.target
600 10:52:54.996554 <31>[ 6.524143] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/machine.slice
601 10:52:54.997053 <31>[ 6.524497] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/remote-fs-pre.target
602 10:52:54.997236 <31>[ 6.524810] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-tmpfiles-clean.service
603 10:52:54.997733 <31>[ 6.525447] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/runlevel3.target → multi-user.target
604 10:52:54.998510 <31>[ 6.526065] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/dbus-org.freedesktop.timedate1.service → systemd-timedated.service
605 10:52:54.998985 <31>[ 6.526466] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/dbus.service
606 10:52:54.999219 <31>[ 6.526855] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/reboot.target
607 10:52:55.000119 <31>[ 6.527570] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-journald-audit.socket
608 10:52:55.000332 <31>[ 6.527875] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/getty@.service
609 10:52:55.000518 <31>[ 6.528178] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/kexec.target
610 10:52:55.000709 <31>[ 6.528438] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/system-systemd\x2dcryptsetup.slice
611 10:52:55.001211 <31>[ 6.528755] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-timedated.service
612 10:52:55.001315 <31>[ 6.529008] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/initrd-root-device.target
613 10:52:55.001643 <31>[ 6.529238] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/initrd-parse-etc.service
614 10:52:55.001764 <31>[ 6.529476] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/initrd.target
615 10:52:55.002120 <31>[ 6.529696] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/e2scrub_all.timer
616 10:52:55.002234 <31>[ 6.529983] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-binfmt.service
617 10:52:55.002588 <31>[ 6.530252] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/local-fs-pre.target
618 10:52:55.002704 <31>[ 6.530522] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/e2scrub_all.service
619 10:52:55.003101 <31>[ 6.530793] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/paths.target
620 10:52:55.003924 <31>[ 6.531377] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/modprobe@.service
621 10:52:55.004498 <31>[ 6.531970] systemd[1]: unit_file_build_name_map: linked unit file: /lib/systemd/system/rc.service → /dev/null
622 10:52:55.004745 <31>[ 6.532307] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/getty-static.service
623 10:52:55.005429 <31>[ 6.532942] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/runlevel2.target → multi-user.target
624 10:52:55.005692 <31>[ 6.533308] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-modules-load.service
625 10:52:55.005963 <31>[ 6.533708] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/suspend.target
626 10:52:55.006507 <31>[ 6.534038] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/sys-kernel-debug.mount
627 10:52:55.006676 <31>[ 6.534371] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-sysusers.service
628 10:52:55.007529 <31>[ 6.535273] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/default.target → graphical.target
629 10:52:55.007967 <31>[ 6.535597] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-poweroff.service
630 10:52:55.008498 <31>[ 6.535919] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/initrd-switch-root.target
631 10:52:55.008698 <31>[ 6.536282] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-sysctl.service
632 10:52:55.009226 <31>[ 6.536947] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/procps.service → systemd-sysctl.service
633 10:52:55.009788 <31>[ 6.537330] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-time-wait-sync.service
634 10:52:55.009990 <31>[ 6.537643] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/user@.service
635 10:52:55.010485 <31>[ 6.538191] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/udev.service → systemd-udevd.service
636 10:52:55.010775 <31>[ 6.538469] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/system-update-cleanup.service
637 10:52:55.011051 <31>[ 6.538755] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/nss-lookup.target
638 10:52:55.011589 <31>[ 6.539315] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/umount.target
639 10:52:55.012159 <31>[ 6.539655] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/initrd-udevadm-cleanup-db.service
640 10:52:55.012389 <31>[ 6.539979] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/sys-kernel-tracing.mount
641 10:52:55.012580 <31>[ 6.540298] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-initctl.socket
642 10:52:55.012835 <31>[ 6.540564] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-timesyncd.service
643 10:52:55.013390 <31>[ 6.540894] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-journald.socket
644 10:52:55.013595 <31>[ 6.541226] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/printer.target
645 10:52:55.013800 <31>[ 6.541536] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/network-online.target
646 10:52:55.014338 <31>[ 6.541877] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/usb-gadget.target
647 10:52:55.014561 <31>[ 6.542208] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-hybrid-sleep.service
648 10:52:55.014746 <31>[ 6.542483] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-reboot.service
649 10:52:55.015253 <31>[ 6.542785] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/quotaon.service
650 10:52:55.016231 <31>[ 6.543667] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/bluetooth.target
651 10:52:55.016538 <31>[ 6.543960] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/rescue.service
652 10:52:55.016708 <31>[ 6.544246] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-backlight@.service
653 10:52:55.017183 <31>[ 6.544838] systemd[1]: unit_file_build_name_map: linked unit file: /lib/systemd/system/cryptdisks-early.service → /dev/null
654 10:52:55.017776 <31>[ 6.545187] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/dev-hugepages.mount
655 10:52:55.017996 <31>[ 6.545521] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/remote-cryptsetup.target
656 10:52:55.018213 <31>[ 6.545858] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-pstore.service
657 10:52:55.018977 <31>[ 6.546315] systemd[1]: unit_file_build_name_map: linked unit file: /lib/systemd/system/x11-common.service → /dev/null
658 10:52:55.019525 <31>[ 6.547206] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/dbus-org.freedesktop.locale1.service → systemd-localed.service
659 10:52:55.020082 <31>[ 6.547597] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/timers.target
660 10:52:55.020268 <31>[ 6.547894] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/proc-sys-fs-binfmt_misc.automount
661 10:52:55.020470 <31>[ 6.548221] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-ask-password-console.service
662 10:52:55.020674 <31>[ 6.548489] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-rfkill.socket
663 10:52:55.021287 <31>[ 6.548751] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/user.slice
664 10:52:55.021507 <31>[ 6.549080] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-tmpfiles-setup.service
665 10:52:55.021763 <31>[ 6.549435] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-fsck-root.service
666 10:52:55.022350 <31>[ 6.549784] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-quotacheck.service
667 10:52:55.022528 <31>[ 6.550117] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-kexec.service
668 10:52:55.022759 <31>[ 6.550417] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/graphical.target
669 10:52:55.023015 <31>[ 6.550720] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-tmpfiles-clean.timer
670 10:52:55.023558 <31>[ 6.551281] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/exit.target
671 10:52:55.024168 <31>[ 6.551606] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/initrd-fs.target
672 10:52:55.024351 <31>[ 6.551876] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-boot-system-token.service
673 10:52:55.024881 <31>[ 6.552409] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-journald-varlink@.socket
674 10:52:55.025083 <31>[ 6.552733] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-udevd.service
675 10:52:55.025255 <31>[ 6.553027] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/rpcbind.target
676 10:52:55.026181 <31>[ 6.553699] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/dbus-org.freedesktop.hostname1.service → systemd-hostnamed.service
677 10:52:55.026420 <31>[ 6.554100] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/syslog.socket
678 10:52:55.027030 <31>[ 6.554427] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-user-sessions.service
679 10:52:55.027271 <31>[ 6.554791] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-volatile-root.service
680 10:52:55.028443 <31>[ 6.556079] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/user-runtime-dir@.service
681 10:52:55.028914 <31>[ 6.556508] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/kmod-static-nodes.service
682 10:52:55.029387 <31>[ 6.556974] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-logind.service
683 10:52:55.030050 <31>[ 6.557441] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-udevd-control.socket
684 10:52:55.030426 <31>[ 6.557930] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-bless-boot.service
685 10:52:55.030793 <31>[ 6.558310] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-networkd.service
686 10:52:55.030938 <31>[ 6.558655] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-journal-flush.service
687 10:52:55.031533 <31>[ 6.559146] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/getty-pre.target
688 10:52:55.031915 <31>[ 6.559448] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/getty.target
689 10:52:55.032281 <31>[ 6.559789] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-network-generator.service
690 10:52:55.032398 <31>[ 6.560169] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/system-update.target
691 10:52:55.032748 <31>[ 6.560458] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/multi-user.target
692 10:52:55.033113 <31>[ 6.560763] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-suspend.service
693 10:52:55.033490 <31>[ 6.561128] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-initctl.service
694 10:52:55.033868 <31>[ 6.561535] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/initrd-cleanup.service
695 10:52:55.034315 <31>[ 6.561923] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/basic.target
696 10:52:55.034860 <31>[ 6.562268] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/emergency.target
697 10:52:55.035092 <31>[ 6.562637] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-suspend-then-hibernate.service
698 10:52:55.035306 <31>[ 6.563077] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-hibernate-resume@.service
699 10:52:55.035866 <31>[ 6.563389] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-udevd-kernel.socket
700 10:52:55.036087 <31>[ 6.563708] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-journald-dev-log.socket
701 10:52:55.036355 <31>[ 6.564039] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-machine-id-commit.service
702 10:52:55.036594 <31>[ 6.564373] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/serial-getty@.service
703 10:52:55.037105 <31>[ 6.564666] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/initrd-switch-root.service
704 10:52:55.037295 <31>[ 6.564991] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/e2scrub_reap.service
705 10:52:55.037499 <31>[ 6.565262] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/sockets.target
706 10:52:55.038316 <31>[ 6.565784] systemd[1]: unit_file_build_name_map: linked unit file: /lib/systemd/system/cryptdisks.service → /dev/null
707 10:52:55.038500 <31>[ 6.566114] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/hybrid-sleep.target
708 10:52:55.039266 <31>[ 6.566812] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/dbus-org.freedesktop.login1.service → systemd-logind.service
709 10:52:55.039808 <31>[ 6.567389] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/sleep.target
710 10:52:55.040010 <31>[ 6.567697] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-hibernate.service
711 10:52:55.040256 <31>[ 6.568016] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-halt.service
712 10:52:55.040757 <31>[ 6.568316] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/halt.target
713 10:52:55.040953 <31>[ 6.568596] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/sigpwr.target
714 10:52:55.041446 <31>[ 6.568908] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-tmpfiles-setup-dev.service
715 10:52:55.041601 <31>[ 6.569268] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/sound.target
716 10:52:55.042067 <31>[ 6.569563] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/time-set.target
717 10:52:55.042216 <31>[ 6.569892] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-udev-settle.service
718 10:52:55.042623 <31>[ 6.570202] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/dbus.socket
719 10:52:55.043069 <31>[ 6.570665] systemd[1]: unit_file_build_name_map: linked unit file: /lib/systemd/system/hwclock.service → /dev/null
720 10:52:55.043606 <31>[ 6.571393] systemd[1]: unit_file_build_name_map: linked unit file: /lib/systemd/system/rcS.service → /dev/null
721 10:52:55.043975 <31>[ 6.571673] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/hibernate.target
722 10:52:55.044128 <31>[ 6.571913] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-random-seed.service
723 10:52:55.044488 <31>[ 6.572162] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/cryptsetup.target
724 10:52:55.044601 <31>[ 6.572409] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/boot-complete.target
725 10:52:55.044976 <31>[ 6.572635] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/blockdev@.target
726 10:52:55.045102 <31>[ 6.572885] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-networkd-wait-online.service
727 10:52:55.438971 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
728 10:52:55.443413 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
729 10:52:55.446495 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
730 10:52:55.449671 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
731 10:52:55.453224 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
732 10:52:55.454421 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
733 10:52:55.456881 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
734 10:52:55.457782 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
735 10:52:55.458498 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
736 10:52:55.459299 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
737 10:52:55.460294 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
738 10:52:55.464033 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
739 10:52:55.468172 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
740 10:52:55.470601 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
741 10:52:55.472914 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
742 10:52:55.475605 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
743 10:52:55.477856 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
744 10:52:55.480147 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
745 10:52:55.505340 Mounting [0;1;39mHuge Pages File System[0m...
746 10:52:55.528260 Mounting [0;1;39mPOSIX Message Queue File System[0m...
747 10:52:55.560325 Mounting [0;1;39mKernel Debug File System[0m...
748 10:52:55.617228 Starting [0;1;39mLoad Kernel Module configfs[0m...
749 10:52:55.656807 Starting [0;1;39mLoad Kernel Module drm[0m...
750 10:52:55.713017 Starting [0;1;39mJournal Service[0m...
751 10:52:55.745021 Starting [0;1;39mLoad Kernel Modules[0m...
752 10:52:55.773390 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
753 10:52:55.836690 Starting [0;1;39mColdplug All udev Devices[0m...
754 10:52:55.920961 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
755 10:52:55.937574 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
756 10:52:55.941026 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
757 10:52:55.991592 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
758 10:52:56.052301 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
759 10:52:56.071962 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
760 10:52:56.132663 Mounting [0;1;39mKernel Configuration File System[0m...
761 10:52:56.268599 Starting [0;1;39mApply Kernel Variables[0m...
762 10:52:56.317547 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
763 10:52:56.374077 <47>[ 7.901785] systemd-journald[105]: SELinux enabled state cached to: disabled
764 10:52:56.383797 <47>[ 7.911293] systemd-journald[105]: Auditing in kernel turned off.
765 10:52:56.408504 <47>[ 7.935974] systemd-journald[105]: Found cgroup2 on /sys/fs/cgroup/, full unified hierarchy
766 10:52:56.464591 <47>[ 7.992214] systemd-journald[105]: Journal effective settings seal=no keyed_hash=no compress=yes compress_threshold_bytes=512B
767 10:52:56.467086 <47>[ 7.994656] systemd-journald[105]: Fixed min_use=3.8M max_use=19.4M max_size=2.4M min_size=512.0K keep_free=9.7M n_max_files=100
768 10:52:56.468518 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
769 10:52:56.469038 See 'systemctl status systemd-remount-fs.service' for details.
770 10:52:56.481304 <47>[ 8.008860] systemd-journald[105]: Reserving 333 entries in field hash table.
771 10:52:56.501473 Starting [0;1;39mLoad/Save Random Seed[0m...
772 10:52:56.516358 <47>[ 8.044169] systemd-journald[105]: Reserving 4437 entries in data hash table.
773 10:52:56.518302 <47>[ 8.045975] systemd-journald[105]: Vacuuming...
774 10:52:56.518908 <47>[ 8.046560] systemd-journald[105]: Vacuuming done, freed 0B of archived journals from /run/log/journal/938dcdc227b64155a30c60b8906c70ae.
775 10:52:56.531816 <47>[ 8.059626] systemd-journald[105]: Flushing /dev/kmsg...
776 10:52:56.564585 Starting [0;1;39mCreate System Users[0m...
777 10:52:56.595981 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
778 10:52:56.708414 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
779 10:52:56.877347 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
780 10:52:56.921094 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
781 10:52:57.034067 <47>[ 8.561596] systemd-journald[105]: systemd-journald running as PID 105 for the system.
782 10:52:57.051642 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
783 10:52:57.059652 <47>[ 8.587193] systemd-journald[105]: Sent READY=1 notification.
784 10:52:57.059846 <47>[ 8.587583] systemd-journald[105]: Sent WATCHDOG=1 notification.
785 10:52:57.093642 <47>[ 8.621228] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
786 10:52:57.105205 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
787 10:52:57.121362 <47>[ 8.649009] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
788 10:52:57.139431 <47>[ 8.667066] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
789 10:52:57.151647 <47>[ 8.679125] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
790 10:52:57.171688 <47>[ 8.699178] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
791 10:52:57.176724 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
792 10:52:57.180628 <47>[ 8.708162] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
793 10:52:57.182741 <47>[ 8.710352] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
794 10:52:57.196301 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
795 10:52:57.200247 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
796 10:52:57.214715 <47>[ 8.742247] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
797 10:52:57.229237 <47>[ 8.756850] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
798 10:52:57.230834 <47>[ 8.758460] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
799 10:52:57.245146 <47>[ 8.772681] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
800 10:52:57.247030 <47>[ 8.774592] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
801 10:52:57.262165 <47>[ 8.789763] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
802 10:52:57.275449 <47>[ 8.803324] systemd-journald[105]: n/a: New incoming connection.
803 10:52:57.276188 <47>[ 8.803829] systemd-journald[105]: varlink-21: varlink: setting state idle-server
804 10:52:57.278772 <47>[ 8.806310] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
805 10:52:57.284632 <47>[ 8.812192] systemd-journald[105]: varlink-21: New incoming message: {\"method\":\"io.systemd.Journal.FlushToVar\",\"parameters\":{}}
806 10:52:57.286627 <47>[ 8.814247] systemd-journald[105]: varlink-21: varlink: changing state idle-server → processing-method
807 10:52:57.286848 <46>[ 8.814632] systemd-journald[105]: Received client request to flush runtime journal.
808 10:52:57.289761 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
809 10:52:57.307973 <47>[ 8.835538] systemd-journald[105]: Journal effective settings seal=yes keyed_hash=no compress=yes compress_threshold_bytes=512B
810 10:52:57.308754 <47>[ 8.836372] systemd-journald[105]: Vacuuming...
811 10:52:57.309284 <47>[ 8.836762] systemd-journald[105]: Vacuuming done, freed 0B of archived journals from /run/log/journal/938dcdc227b64155a30c60b8906c70ae.
812 10:52:57.310428 <47>[ 8.837992] systemd-journald[105]: varlink-21: Sending message: {\"parameters\":{}}
813 10:52:57.310628 <47>[ 8.838259] systemd-journald[105]: varlink-21: varlink: changing state processing-method → processed-method
814 10:52:57.311098 <47>[ 8.838659] systemd-journald[105]: varlink-21: varlink: changing state processed-method → idle-server
815 10:52:57.327748 <47>[ 8.855252] systemd-journald[105]: varlink-21: varlink: changing state idle-server → pending-disconnect
816 10:52:57.328009 <47>[ 8.855617] systemd-journald[105]: varlink-21: varlink: changing state pending-disconnect → processing-disconnect
817 10:52:57.328432 <47>[ 8.855957] systemd-journald[105]: varlink-21: varlink: changing state processing-disconnect → disconnected
818 10:52:57.347588 <47>[ 8.875278] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
819 10:52:57.360020 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
820 10:52:57.413310 Starting [0;1;39mCreate Volatile Files and Directories[0m...
821 10:52:57.435699 <47>[ 8.963234] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
822 10:52:57.869438 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
823 10:52:57.948706 Starting [0;1;39mNetwork Service[0m...
824 10:52:57.982260 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
825 10:52:57.985366 <47>[ 9.512961] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
826 10:52:58.077479 Starting [0;1;39mNetwork Time Synchronization[0m...
827 10:52:58.118083 <47>[ 9.645512] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
828 10:52:58.158011 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
829 10:52:58.191835 <47>[ 9.719232] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
830 10:52:58.597089 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
831 10:52:59.538161 <47>[ 11.065411] systemd-journald[105]: Data hash table of /run/log/journal/938dcdc227b64155a30c60b8906c70ae/system.journal has a fill level at 75.0 (3329 of 4437 items, 2555904 file size, 767 bytes per hash table item), suggesting rotation.
832 10:52:59.538518 <47>[ 11.066033] systemd-journald[105]: /run/log/journal/938dcdc227b64155a30c60b8906c70ae/system.journal: Journal header limits reached or header out-of-date, rotating.
833 10:52:59.538705 <47>[ 11.066561] systemd-journald[105]: Rotating...
834 10:52:59.552413 <47>[ 11.079876] systemd-journald[105]: Journal effective settings seal=no keyed_hash=no compress=yes compress_threshold_bytes=512B
835 10:52:59.553854 <47>[ 11.081455] systemd-journald[105]: Reserving 333 entries in field hash table.
836 10:52:59.616369 <47>[ 11.144014] systemd-journald[105]: Reserving 4437 entries in data hash table.
837 10:52:59.631636 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
838 10:52:59.636762 <47>[ 11.164465] systemd-journald[105]: Vacuuming...
839 10:52:59.638673 <47>[ 11.166262] systemd-journald[105]: Vacuuming done, freed 0B of archived journals from /run/log/journal/938dcdc227b64155a30c60b8906c70ae.
840 10:52:59.753910 Starting [0;1;39mNetwork Name Resolution[0m...
841 10:52:59.783630 <47>[ 11.311072] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
842 10:53:00.026437 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
843 10:53:00.028643 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
844 10:53:00.031965 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
845 10:53:00.118143 <47>[ 11.645885] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
846 10:53:01.333177 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
847 10:53:01.344086 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
848 10:53:01.367020 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
849 10:53:01.387508 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
850 10:53:01.396718 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
851 10:53:01.405354 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
852 10:53:01.433376 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
853 10:53:01.434044 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
854 10:53:01.434880 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
855 10:53:01.501392 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
856 10:53:01.513699 <47>[ 13.041170] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
857 10:53:01.656620 <47>[ 13.184120] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
858 10:53:01.660359 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
859 10:53:01.877988 Starting [0;1;39mUser Login Management[0m...
860 10:53:01.885530 <47>[ 13.413160] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
861 10:53:02.160243 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
862 10:53:02.162235 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
863 10:53:02.164163 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
864 10:53:02.306108 Starting [0;1;39mPermit User Sessions[0m...
865 10:53:02.343891 <47>[ 13.871402] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
866 10:53:02.570145 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
867 10:53:02.636088 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
868 10:53:02.708333 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
869 10:53:03.100350 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
870 10:53:05.117500 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyAMA0[0m.
871 10:53:05.173692 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyAMA0[0m.
872 10:53:05.196440 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
873 10:53:05.213211 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
874 10:53:05.220692 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
875 10:53:05.272327 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
876 10:53:05.280971 <47>[ 16.808717] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
877 10:53:05.418624 <6>[ 16.946351] virtio_net virtio0 enp0s1: renamed from eth0
878 10:53:05.480446 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
879 10:53:05.536248 <47>[ 17.063739] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
880 10:53:05.536754 <47>[ 17.064560] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
881 10:53:05.625585
882 10:53:05.626116 Debian GNU/Linux 11 debian-bullseye-arm64 ttyAMA0
883 10:53:05.626305
884 10:53:05.626485 debian-bullseye-arm64 login: root (automatic login)
885 10:53:05.626675
886 10:53:05.834125 Linux debian-bullseye-arm64 6.1.31 #1 SMP PREEMPT Mon Jun 5 10:37:40 UTC 2023 aarch64
887 10:53:05.834815
888 10:53:05.834998 The programs included with the Debian GNU/Linux system are free software;
889 10:53:05.835180 the exact distribution terms for each program are described in the
890 10:53:05.835335 individual files in /usr/share/doc/*/copyright.
891 10:53:05.835482
892 10:53:05.835627 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
893 10:53:05.835772 permitted by applicable law.
894 10:53:06.361585 <47>[ 17.889253] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
895 10:53:06.527501 <47>[ 18.054800] systemd-journald[105]: Data hash table of /run/log/journal/938dcdc227b64155a30c60b8906c70ae/system.journal has a fill level at 75.0 (3328 of 4437 items, 2555904 file size, 768 bytes per hash table item), suggesting rotation.
896 10:53:06.528136 <47>[ 18.055378] systemd-journald[105]: /run/log/journal/938dcdc227b64155a30c60b8906c70ae/system.journal: Journal header limits reached or header out-of-date, rotating.
897 10:53:06.528300 <47>[ 18.055713] systemd-journald[105]: Rotating...
898 10:53:06.529396 <47>[ 18.057003] systemd-journald[105]: Reserving 333 entries in field hash table.
899 10:53:06.557879 <47>[ 18.085389] systemd-journald[105]: Reserving 4437 entries in data hash table.
900 10:53:06.575776 <47>[ 18.103608] systemd-journald[105]: Vacuuming...
901 10:53:06.577069 <47>[ 18.104653] systemd-journald[105]: Vacuuming done, freed 0B of archived journals from /run/log/journal/938dcdc227b64155a30c60b8906c70ae.
902 10:53:06.730279 <47>[ 18.257771] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
903 10:53:08.451856 <47>[ 19.979525] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
904 10:53:08.724884 Matched prompt #10: / #
906 10:53:08.725478 Setting prompt string to ['/ #']
907 10:53:08.725678 end: 2.2.1 login-action (duration 00:00:20) [common]
909 10:53:08.726105 end: 2.2 auto-login-action (duration 00:00:23) [common]
910 10:53:08.726280 start: 2.3 expect-shell-connection (timeout 00:04:36) [common]
911 10:53:08.726425 Setting prompt string to ['/ #']
912 10:53:08.726550 Forcing a shell prompt, looking for ['/ #']
914 10:53:08.777139 / #
915 10:53:08.777440 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
916 10:53:08.777661 Waiting using forced prompt support (timeout 00:02:30)
917 10:53:08.780796
918 10:53:08.791967 end: 2.3 expect-shell-connection (duration 00:00:00) [common]
919 10:53:08.792214 start: 2.4 export-device-env (timeout 00:04:36) [common]
920 10:53:08.792403 end: 2.4 export-device-env (duration 00:00:00) [common]
921 10:53:08.792603 end: 2 boot-image-retry (duration 00:00:24) [common]
922 10:53:08.792858 start: 3 lava-test-retry (timeout 00:08:50) [common]
923 10:53:08.793069 start: 3.1 lava-test-shell (timeout 00:08:50) [common]
924 10:53:08.793233 Using namespace: common
926 10:53:08.894196 / # #
927 10:53:08.894541 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
928 10:53:08.895368 #
930 10:53:09.003690 / # mkdir /lava-562531
931 10:53:09.004524 mkdir /lava-562531
933 10:53:09.143904 / # mount /dev/disk/by-uuid/c08e052c-3c53-456e-9587-09146bb4bba6 -t ext2 /lava-562531
934 10:53:09.144879 mount /dev/disk/by-uuid/c08e052c-3c53-456e-9587-09146bb4bba6 -t ext2 /lava-562531
935 10:53:09.184087 <4>[ 20.711483] ext2 filesystem being mounted at /lava-562531 supports timestamps until 2038 (0x7fffffff)
937 10:53:09.332382 / # ls -la /lava-562531/bin/lava-test-runner
938 10:53:09.332984 ls -la /lava-562531/bin/lava-test-runner
939 10:53:09.372483 -rwxr-xr-x 1 root root 1039 Jun 5 10:51 /lava-562531/bin/lava-test-runner
940 10:53:09.384154 Using /lava-562531
942 10:53:09.485170 / # export SHELL=/bin/sh
943 10:53:09.486092 export SHELL=/bin/sh
945 10:53:09.594611 / # . /lava-562531/environment
946 10:53:09.595436 . /lava-562531/environment
948 10:53:09.706868 / # /lava-562531/bin/lava-test-runner /lava-562531/0
949 10:53:09.707199 Test shell timeout: 10s (minimum of the action and connection timeout)
950 10:53:09.707952 /lava-562531/bin/lava-test-runner /lava-562531/0
951 10:53:09.862631 + export TESTRUN_ID=0_timesync-off
952 10:53:09.863126 + cd /lava-562531/0/tests/0_timesync-off
953 10:53:09.864505 + cat uuid
954 10:53:09.871880 + UUID=562531_1.1.3.1
955 10:53:09.872062 + set +x
956 10:53:09.872424 <LAVA_SIGNAL_STARTRUN 0_timesync-off 562531_1.1.3.1>
957 10:53:09.872799 Received signal: <STARTRUN> 0_timesync-off 562531_1.1.3.1
958 10:53:09.872953 Starting test lava.0_timesync-off (562531_1.1.3.1)
959 10:53:09.873122 Skipping test definition patterns.
960 10:53:09.873322 + systemctl stop systemd-timesyncd
961 10:53:10.102455 + set +x
962 10:53:10.102726 <LAVA_SIGNAL_ENDRUN 0_timesync-off 562531_1.1.3.1>
963 10:53:10.103062 Received signal: <ENDRUN> 0_timesync-off 562531_1.1.3.1
964 10:53:10.103279 Ending use of test pattern.
965 10:53:10.103419 Ending test lava.0_timesync-off (562531_1.1.3.1), duration 0.23
967 10:53:10.142347 + export TESTRUN_ID=1_kselftest-arm64_qemu
968 10:53:10.142561 + cd /lava-562531/0/tests/1_kselftest-arm64_qemu
969 10:53:10.144801 + cat uuid
970 10:53:10.152449 + UUID=562531_1.1.3.5
971 10:53:10.152701 + set +x
972 10:53:10.153024 Received signal: <STARTRUN> 1_kselftest-arm64_qemu 562531_1.1.3.5
973 10:53:10.153148 Starting test lava.1_kselftest-arm64_qemu (562531_1.1.3.5)
974 10:53:10.153276 Skipping test definition patterns.
975 10:53:10.153435 <LAVA_SIGNAL_STARTRUN 1_kselftest-arm64_qemu 562531_1.1.3.5>
976 10:53:10.153532 + cd ./automated/linux/kselftest/
977 10:53:10.158251 + ./kselftest.sh -c arm64 -T -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1298-g61395b9756bd5/arm64/defconfig/gcc-10/kselftest.tar.xz -L -S /dev/null -b qemu_arm64-virt-gicv3 -g cip-gitlab -e -p /opt/kselftests/mainline/ -n 1 -i 1
978 10:53:10.249701 INFO: install_deps skipped
979 10:53:10.282062 --2023-06-05 10:53:10-- http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1298-g61395b9756bd5/arm64/defconfig/gcc-10/kselftest.tar.xz
980 10:53:10.408799 Resolving storage.kernelci.org (storage.kernelci.org)... 52.250.1.28
981 10:53:10.616941 Connecting to storage.kernelci.org (storage.kernelci.org)|52.250.1.28|:80... connected.
982 10:53:10.811128 HTTP request sent, awaiting response... 200 OK
983 10:53:10.813642 Length: 2700360 (2.6M) [application/octet-stream]
984 10:53:10.815882 Saving to: 'kselftest.tar.xz'
985 10:53:10.817100
986 10:53:12.099532 kselftest.tar.xz 0%[ ] 0 --.-KB/s kselftest.tar.xz 1%[ ] 50.15K 150KB/s kselftest.tar.xz 8%[> ] 219.84K 321KB/s kselftest.tar.xz 34%[=====> ] 898.59K 872KB/s kselftest.tar.xz 76%[==============> ] 1.97M 1.60MB/s kselftest.tar.xz 100%[===================>] 2.58M 2.05MB/s in 1.3s
987 10:53:12.099851
988 10:53:12.104653 2023-06-05 10:53:12 (2.05 MB/s) - 'kselftest.tar.xz' saved [2700360/2700360]
989 10:53:12.104830
990 10:53:15.077520 skiplist:
991 10:53:15.078006 ========================================
992 10:53:15.078732 ========================================
993 10:53:15.131421 arm64:tags_test
994 10:53:15.131723 arm64:run_tags_test.sh
995 10:53:15.132077 arm64:fake_sigreturn_bad_magic
996 10:53:15.132194 arm64:fake_sigreturn_bad_size
997 10:53:15.132289 arm64:fake_sigreturn_bad_size_for_magic0
998 10:53:15.132379 arm64:fake_sigreturn_duplicated_fpsimd
999 10:53:15.132467 arm64:fake_sigreturn_misaligned_sp
1000 10:53:15.132554 arm64:fake_sigreturn_missing_fpsimd
1001 10:53:15.132642 arm64:fake_sigreturn_sme_change_vl
1002 10:53:15.132730 arm64:fake_sigreturn_sve_change_vl
1003 10:53:15.132818 arm64:mangle_pstate_invalid_compat_toggle
1004 10:53:15.132907 arm64:mangle_pstate_invalid_daif_bits
1005 10:53:15.133014 arm64:mangle_pstate_invalid_mode_el1h
1006 10:53:15.133106 arm64:mangle_pstate_invalid_mode_el1t
1007 10:53:15.133195 arm64:mangle_pstate_invalid_mode_el2h
1008 10:53:15.133284 arm64:mangle_pstate_invalid_mode_el2t
1009 10:53:15.133372 arm64:mangle_pstate_invalid_mode_el3h
1010 10:53:15.133459 arm64:mangle_pstate_invalid_mode_el3t
1011 10:53:15.133547 arm64:sme_trap_no_sm
1012 10:53:15.133635 arm64:sme_trap_non_streaming
1013 10:53:15.133749 arm64:sme_trap_za
1014 10:53:15.133836 arm64:sme_vl
1015 10:53:15.133923 arm64:ssve_regs
1016 10:53:15.134010 arm64:sve_regs
1017 10:53:15.134121 arm64:sve_vl
1018 10:53:15.134211 arm64:za_no_regs
1019 10:53:15.134299 arm64:za_regs
1020 10:53:15.134386 arm64:pac
1021 10:53:15.134474 arm64:fp-stress
1022 10:53:15.134560 arm64:sve-ptrace
1023 10:53:15.134645 arm64:sve-probe-vls
1024 10:53:15.134735 arm64:vec-syscfg
1025 10:53:15.134835 arm64:za-fork
1026 10:53:15.134926 arm64:za-ptrace
1027 10:53:15.135014 arm64:check_buffer_fill
1028 10:53:15.135101 arm64:check_child_memory
1029 10:53:15.135188 arm64:check_gcr_el1_cswitch
1030 10:53:15.135274 arm64:check_ksm_options
1031 10:53:15.135360 arm64:check_mmap_options
1032 10:53:15.135445 arm64:check_prctl
1033 10:53:15.135527 arm64:check_tags_inclusion
1034 10:53:15.135608 arm64:check_user_mem
1035 10:53:15.135707 arm64:btitest
1036 10:53:15.135790 arm64:nobtitest
1037 10:53:15.135871 arm64:hwcap
1038 10:53:15.135951 arm64:ptrace
1039 10:53:15.136033 arm64:syscall-abi
1040 10:53:15.136114 arm64:tpidr2
1041 10:53:15.146906 ============== Tests to run ===============
1042 10:53:15.152399 arm64:tags_test
1043 10:53:15.152796 arm64:run_tags_test.sh
1044 10:53:15.152900 arm64:fake_sigreturn_bad_magic
1045 10:53:15.152991 arm64:fake_sigreturn_bad_size
1046 10:53:15.153080 arm64:fake_sigreturn_bad_size_for_magic0
1047 10:53:15.153189 arm64:fake_sigreturn_duplicated_fpsimd
1048 10:53:15.153275 arm64:fake_sigreturn_misaligned_sp
1049 10:53:15.153381 arm64:fake_sigreturn_missing_fpsimd
1050 10:53:15.153555 arm64:fake_sigreturn_sme_change_vl
1051 10:53:15.153741 arm64:fake_sigreturn_sve_change_vl
1052 10:53:15.153829 arm64:mangle_pstate_invalid_compat_toggle
1053 10:53:15.153913 arm64:mangle_pstate_invalid_daif_bits
1054 10:53:15.153997 arm64:mangle_pstate_invalid_mode_el1h
1055 10:53:15.154143 arm64:mangle_pstate_invalid_mode_el1t
1056 10:53:15.154234 arm64:mangle_pstate_invalid_mode_el2h
1057 10:53:15.154318 arm64:mangle_pstate_invalid_mode_el2t
1058 10:53:15.154403 arm64:mangle_pstate_invalid_mode_el3h
1059 10:53:15.154505 arm64:mangle_pstate_invalid_mode_el3t
1060 10:53:15.154592 arm64:sme_trap_no_sm
1061 10:53:15.154676 arm64:sme_trap_non_streaming
1062 10:53:15.154760 arm64:sme_trap_za
1063 10:53:15.154861 arm64:sme_vl
1064 10:53:15.154947 arm64:ssve_regs
1065 10:53:15.155032 arm64:sve_regs
1066 10:53:15.155119 arm64:sve_vl
1067 10:53:15.155205 arm64:za_no_regs
1068 10:53:15.155291 arm64:za_regs
1069 10:53:15.155378 arm64:pac
1070 10:53:15.155482 arm64:fp-stress
1071 10:53:15.155571 arm64:sve-ptrace
1072 10:53:15.155658 arm64:sve-probe-vls
1073 10:53:15.155743 arm64:vec-syscfg
1074 10:53:15.155844 arm64:za-fork
1075 10:53:15.155931 arm64:za-ptrace
1076 10:53:15.156031 arm64:check_buffer_fill
1077 10:53:15.156122 arm64:check_child_memory
1078 10:53:15.156206 arm64:check_gcr_el1_cswitch
1079 10:53:15.156305 arm64:check_ksm_options
1080 10:53:15.156392 arm64:check_mmap_options
1081 10:53:15.156476 arm64:check_prctl
1082 10:53:15.156575 arm64:check_tags_inclusion
1083 10:53:15.156661 arm64:check_user_mem
1084 10:53:15.156747 arm64:btitest
1085 10:53:15.156849 arm64:nobtitest
1086 10:53:15.156936 arm64:hwcap
1087 10:53:15.157025 arm64:ptrace
1088 10:53:15.157109 arm64:syscall-abi
1089 10:53:15.157192 arm64:tpidr2
1090 10:53:15.158687 ===========End Tests to run ===============
1091 10:53:16.078573 <12>[ 27.606364] kselftest: Running tests in arm64
1092 10:53:16.107082 TAP version 13
1093 10:53:16.128899 1..48
1094 10:53:16.176539 # selftests: arm64: tags_test
1095 10:53:16.229082 ok 1 selftests: arm64: tags_test
1096 10:53:16.275884 # selftests: arm64: run_tags_test.sh
1097 10:53:16.324443 # --------------------
1098 10:53:16.324617 # running tags test
1099 10:53:16.324949 # --------------------
1100 10:53:16.325078 # [PASS]
1101 10:53:16.332792 ok 2 selftests: arm64: run_tags_test.sh
1102 10:53:16.376829 # selftests: arm64: fake_sigreturn_bad_magic
1103 10:53:16.425163 # Registered handlers for all signals.
1104 10:53:16.425408 # Detected MINSTKSIGSZ:10000
1105 10:53:16.425708 # Testcase initialized.
1106 10:53:16.425812 # uc context validated.
1107 10:53:16.425903 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1108 10:53:16.425991 # Handled SIG_COPYCTX
1109 10:53:16.426077 # Available space:3536
1110 10:53:16.426177 # Using badly built context - ERR: BAD MAGIC !
1111 10:53:16.426266 # SIG_OK -- SP:0xFFFFC19E15A0 si_addr@:0xffffc19e15a0 si_code:2 token@:0xffffc19e0340 offset:-4704
1112 10:53:16.426353 # ==>> completed. PASS(1)
1113 10:53:16.426456 # # FAKE_SIGRETURN_BAD_MAGIC :: Trigger a sigreturn with a sigframe with a bad magic
1114 10:53:16.426561 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFC19E0340
1115 10:53:16.434566 ok 3 selftests: arm64: fake_sigreturn_bad_magic
1116 10:53:16.477966 # selftests: arm64: fake_sigreturn_bad_size
1117 10:53:16.525124 # Registered handlers for all signals.
1118 10:53:16.525440 # Detected MINSTKSIGSZ:10000
1119 10:53:16.525923 # Testcase initialized.
1120 10:53:16.526089 # uc context validated.
1121 10:53:16.526226 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1122 10:53:16.526356 # Handled SIG_COPYCTX
1123 10:53:16.526479 # Available space:3536
1124 10:53:16.526603 # uc context validated.
1125 10:53:16.526728 # Using badly built context - ERR: Bad size for esr_context
1126 10:53:16.526851 # SIG_OK -- SP:0xFFFFD0DF7810 si_addr@:0xffffd0df7810 si_code:2 token@:0xffffd0df65b0 offset:-4704
1127 10:53:16.526977 # ==>> completed. PASS(1)
1128 10:53:16.527749 # # FAKE_SIGRETURN_BAD_SIZE :: Triggers a sigreturn with a overrun __reserved area
1129 10:53:16.528143 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFD0DF65B0
1130 10:53:16.533222 ok 4 selftests: arm64: fake_sigreturn_bad_size
1131 10:53:16.576583 # selftests: arm64: fake_sigreturn_bad_size_for_magic0
1132 10:53:16.623113 # Registered handlers for all signals.
1133 10:53:16.623356 # Detected MINSTKSIGSZ:10000
1134 10:53:16.623786 # Testcase initialized.
1135 10:53:16.623974 # uc context validated.
1136 10:53:16.624105 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1137 10:53:16.624225 # Handled SIG_COPYCTX
1138 10:53:16.624341 # Available space:3536
1139 10:53:16.624458 # Using badly built context - ERR: Bad size for terminator
1140 10:53:16.624574 # SIG_OK -- SP:0xFFFFFA22D4F0 si_addr@:0xfffffa22d4f0 si_code:2 token@:0xfffffa22c290 offset:-4704
1141 10:53:16.624691 # ==>> completed. PASS(1)
1142 10:53:16.624832 # # FAKE_SIGRETURN_BAD_SIZE_FOR_TERMINATOR :: Trigger a sigreturn using non-zero size terminator
1143 10:53:16.624960 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFFA22C290
1144 10:53:16.632763 ok 5 selftests: arm64: fake_sigreturn_bad_size_for_magic0
1145 10:53:16.675782 # selftests: arm64: fake_sigreturn_duplicated_fpsimd
1146 10:53:16.724184 # Registered handlers for all signals.
1147 10:53:16.724688 # Detected MINSTKSIGSZ:10000
1148 10:53:16.724907 # Testcase initialized.
1149 10:53:16.725097 # uc context validated.
1150 10:53:16.725238 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1151 10:53:16.725362 # Handled SIG_COPYCTX
1152 10:53:16.725484 # Available space:3536
1153 10:53:16.725605 # Using badly built context - ERR: Multiple FPSIMD_MAGIC
1154 10:53:16.725770 # SIG_OK -- SP:0xFFFFEEAD25E0 si_addr@:0xffffeead25e0 si_code:2 token@:0xffffeead1380 offset:-4704
1155 10:53:16.725907 # ==>> completed. PASS(1)
1156 10:53:16.726033 # # FAKE_SIGRETURN_DUPLICATED_FPSIMD :: Triggers a sigreturn including two fpsimd_context
1157 10:53:16.726158 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFEEAD1380
1158 10:53:16.732754 ok 6 selftests: arm64: fake_sigreturn_duplicated_fpsimd
1159 10:53:16.775138 # selftests: arm64: fake_sigreturn_misaligned_sp
1160 10:53:16.820352 # Registered handlers for all signals.
1161 10:53:16.820843 # Detected MINSTKSIGSZ:10000
1162 10:53:16.821000 # Testcase initialized.
1163 10:53:16.821123 # uc context validated.
1164 10:53:16.821239 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1165 10:53:16.821358 # Handled SIG_COPYCTX
1166 10:53:16.821471 # SIG_OK -- SP:0xFFFFE0412D83 si_addr@:0xffffe0412d83 si_code:2 token@:0xffffe0412d83 offset:0
1167 10:53:16.822214 # ==>> completed. PASS(1)
1168 10:53:16.822660 # # FAKE_SIGRETURN_MISALIGNED_SP :: Triggers a sigreturn with a misaligned sigframe
1169 10:53:16.822822 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFE0412D83
1170 10:53:16.828209 ok 7 selftests: arm64: fake_sigreturn_misaligned_sp
1171 10:53:16.870927 # selftests: arm64: fake_sigreturn_missing_fpsimd
1172 10:53:16.918052 # Registered handlers for all signals.
1173 10:53:16.918276 # Detected MINSTKSIGSZ:10000
1174 10:53:16.918446 # Testcase initialized.
1175 10:53:16.918832 # uc context validated.
1176 10:53:16.918943 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1177 10:53:16.919032 # Handled SIG_COPYCTX
1178 10:53:16.919114 # Mangling template header. Spare space:4096
1179 10:53:16.919194 # Using badly built context - ERR: Missing FPSIMD
1180 10:53:16.919275 # SIG_OK -- SP:0xFFFFE2C866E0 si_addr@:0xffffe2c866e0 si_code:2 token@:0xffffe2c85480 offset:-4704
1181 10:53:16.919356 # ==>> completed. PASS(1)
1182 10:53:16.919434 # # FAKE_SIGRETURN_MISSING_FPSIMD :: Triggers a sigreturn with a missing fpsimd_context
1183 10:53:16.919530 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFE2C85480
1184 10:53:16.926893 ok 8 selftests: arm64: fake_sigreturn_missing_fpsimd
1185 10:53:16.969703 # selftests: arm64: fake_sigreturn_sme_change_vl
1186 10:53:17.017448 # Registered handlers for all signals.
1187 10:53:17.017707 # Detected MINSTKSIGSZ:10000
1188 10:53:17.017794 # Required Features: [ SME ] supported
1189 10:53:17.017875 # Incompatible Features: [] absent
1190 10:53:17.017954 # Testcase initialized.
1191 10:53:17.018050 # uc context validated.
1192 10:53:17.018131 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1193 10:53:17.018211 # Handled SIG_COPYCTX
1194 10:53:17.018289 # Attempting to change VL from 16 to 256
1195 10:53:17.018383 # SIG_OK -- SP:0xFFFFEA127F90 si_addr@:0xffffea127f90 si_code:2 token@:0xffffea126d30 offset:-4704
1196 10:53:17.018466 # ==>> completed. PASS(1)
1197 10:53:17.018544 # # FAKE_SIGRETURN_SSVE_CHANGE :: Attempt to change Streaming SVE VL
1198 10:53:17.018622 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFEA126D30
1199 10:53:17.023655 ok 9 selftests: arm64: fake_sigreturn_sme_change_vl
1200 10:53:17.067658 # selftests: arm64: fake_sigreturn_sve_change_vl
1201 10:53:17.115379 # Registered handlers for all signals.
1202 10:53:17.117003 # Detected MINSTKSIGSZ:10000
1203 10:53:17.117139 # Required Features: [ SVE ] supported
1204 10:53:17.117223 # Incompatible Features: [] absent
1205 10:53:17.117301 # Testcase initialized.
1206 10:53:17.117583 # uc context validated.
1207 10:53:17.117693 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1208 10:53:17.117777 # Handled SIG_COPYCTX
1209 10:53:17.117859 # Attempting to change VL from 16 to 256
1210 10:53:17.117937 # SIG_OK -- SP:0xFFFFCB159AA0 si_addr@:0xffffcb159aa0 si_code:2 token@:0xffffcb158840 offset:-4704
1211 10:53:17.118033 # ==>> completed. PASS(1)
1212 10:53:17.118114 # # FAKE_SIGRETURN_SVE_CHANGE :: Attempt to change SVE VL
1213 10:53:17.118193 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFCB158840
1214 10:53:17.123477 ok 10 selftests: arm64: fake_sigreturn_sve_change_vl
1215 10:53:17.167229 # selftests: arm64: mangle_pstate_invalid_compat_toggle
1216 10:53:17.215426 # Registered handlers for all signals.
1217 10:53:17.215697 # Detected MINSTKSIGSZ:10000
1218 10:53:17.215823 # Testcase initialized.
1219 10:53:17.215938 # uc context validated.
1220 10:53:17.216055 # Handled SIG_TRIG
1221 10:53:17.216402 # SIG_OK -- SP:0xFFFFEE58AE70 si_addr@:0xffffee58ae70 si_code:2 token@:(nil) offset:-281474680532592
1222 10:53:17.216560 # ==>> completed. PASS(1)
1223 10:53:17.216680 # # MANGLE_PSTATE_INVALID_STATE_TOGGLE :: Mangling uc_mcontext with INVALID STATE_TOGGLE
1224 10:53:17.221434 ok 11 selftests: arm64: mangle_pstate_invalid_compat_toggle
1225 10:53:17.267042 # selftests: arm64: mangle_pstate_invalid_daif_bits
1226 10:53:17.315531 # Registered handlers for all signals.
1227 10:53:17.315855 # Detected MINSTKSIGSZ:10000
1228 10:53:17.316263 # Testcase initialized.
1229 10:53:17.316430 # uc context validated.
1230 10:53:17.316565 # Handled SIG_TRIG
1231 10:53:17.316691 # SIG_OK -- SP:0xFFFFE68907E0 si_addr@:0xffffe68907e0 si_code:2 token@:(nil) offset:-281474549483488
1232 10:53:17.316820 # ==>> completed. PASS(1)
1233 10:53:17.316944 # # MANGLE_PSTATE_INVALID_DAIF_BITS :: Mangling uc_mcontext with INVALID DAIF_BITS
1234 10:53:17.324420 ok 12 selftests: arm64: mangle_pstate_invalid_daif_bits
1235 10:53:17.371848 # selftests: arm64: mangle_pstate_invalid_mode_el1h
1236 10:53:17.427520 # Registered handlers for all signals.
1237 10:53:17.427795 # Detected MINSTKSIGSZ:10000
1238 10:53:17.427992 # Testcase initialized.
1239 10:53:17.428121 # uc context validated.
1240 10:53:17.428212 # Handled SIG_TRIG
1241 10:53:17.428295 # SIG_OK -- SP:0xFFFFEE47F090 si_addr@:0xffffee47f090 si_code:2 token@:(nil) offset:-281474679435408
1242 10:53:17.428380 # ==>> completed. PASS(1)
1243 10:53:17.428461 # # MANGLE_PSTATE_INVALID_MODE_EL1h :: Mangling uc_mcontext INVALID MODE EL1h
1244 10:53:17.436359 ok 13 selftests: arm64: mangle_pstate_invalid_mode_el1h
1245 10:53:17.482093 # selftests: arm64: mangle_pstate_invalid_mode_el1t
1246 10:53:17.531020 # Registered handlers for all signals.
1247 10:53:17.531273 # Detected MINSTKSIGSZ:10000
1248 10:53:17.531374 # Testcase initialized.
1249 10:53:17.532609 # uc context validated.
1250 10:53:17.532767 # Handled SIG_TRIG
1251 10:53:17.533116 # SIG_OK -- SP:0xFFFFD0D4C5D0 si_addr@:0xffffd0d4c5d0 si_code:2 token@:(nil) offset:-281474185348560
1252 10:53:17.533217 # ==>> completed. PASS(1)
1253 10:53:17.533301 # # MANGLE_PSTATE_INVALID_MODE_EL1t :: Mangling uc_mcontext INVALID MODE EL1t
1254 10:53:17.538821 ok 14 selftests: arm64: mangle_pstate_invalid_mode_el1t
1255 10:53:17.585438 # selftests: arm64: mangle_pstate_invalid_mode_el2h
1256 10:53:17.630927 # Registered handlers for all signals.
1257 10:53:17.631355 # Detected MINSTKSIGSZ:10000
1258 10:53:17.631447 # Testcase initialized.
1259 10:53:17.631529 # uc context validated.
1260 10:53:17.631608 # Handled SIG_TRIG
1261 10:53:17.631702 # SIG_OK -- SP:0xFFFFCB2AA4C0 si_addr@:0xffffcb2aa4c0 si_code:2 token@:(nil) offset:-281474090312896
1262 10:53:17.631786 # ==>> completed. PASS(1)
1263 10:53:17.631865 # # MANGLE_PSTATE_INVALID_MODE_EL2h :: Mangling uc_mcontext INVALID MODE EL2h
1264 10:53:17.639062 ok 15 selftests: arm64: mangle_pstate_invalid_mode_el2h
1265 10:53:17.685023 # selftests: arm64: mangle_pstate_invalid_mode_el2t
1266 10:53:17.737520 # Registered handlers for all signals.
1267 10:53:17.738058 # Detected MINSTKSIGSZ:10000
1268 10:53:17.738277 # Testcase initialized.
1269 10:53:17.738425 # uc context validated.
1270 10:53:17.738549 # Handled SIG_TRIG
1271 10:53:17.738900 # SIG_OK -- SP:0xFFFFD6DA8430 si_addr@:0xffffd6da8430 si_code:2 token@:(nil) offset:-281474286388272
1272 10:53:17.739063 # ==>> completed. PASS(1)
1273 10:53:17.739189 # # MANGLE_PSTATE_INVALID_MODE_EL2t :: Mangling uc_mcontext INVALID MODE EL2t
1274 10:53:17.746509 ok 16 selftests: arm64: mangle_pstate_invalid_mode_el2t
1275 10:53:17.789823 # selftests: arm64: mangle_pstate_invalid_mode_el3h
1276 10:53:17.836281 # Registered handlers for all signals.
1277 10:53:17.836555 # Detected MINSTKSIGSZ:10000
1278 10:53:17.836737 # Testcase initialized.
1279 10:53:17.837124 # uc context validated.
1280 10:53:17.837269 # Handled SIG_TRIG
1281 10:53:17.837400 # SIG_OK -- SP:0xFFFFD16CF020 si_addr@:0xffffd16cf020 si_code:2 token@:(nil) offset:-281474195320864
1282 10:53:17.837527 # ==>> completed. PASS(1)
1283 10:53:17.837662 # # MANGLE_PSTATE_INVALID_MODE_EL3h :: Mangling uc_mcontext INVALID MODE EL3h
1284 10:53:17.844266 ok 17 selftests: arm64: mangle_pstate_invalid_mode_el3h
1285 10:53:17.887162 # selftests: arm64: mangle_pstate_invalid_mode_el3t
1286 10:53:17.938999 # Registered handlers for all signals.
1287 10:53:17.939237 # Detected MINSTKSIGSZ:10000
1288 10:53:17.939548 # Testcase initialized.
1289 10:53:17.939674 # uc context validated.
1290 10:53:17.939772 # Handled SIG_TRIG
1291 10:53:17.939857 # SIG_OK -- SP:0xFFFFE8874630 si_addr@:0xffffe8874630 si_code:2 token@:(nil) offset:-281474582922800
1292 10:53:17.939940 # ==>> completed. PASS(1)
1293 10:53:17.940225 # # MANGLE_PSTATE_INVALID_MODE_EL3t :: Mangling uc_mcontext INVALID MODE EL3t
1294 10:53:17.948820 ok 18 selftests: arm64: mangle_pstate_invalid_mode_el3t
1295 10:53:17.998294 # selftests: arm64: sme_trap_no_sm
1296 10:53:18.114260 # Registered handlers for all signals.
1297 10:53:18.114846 # Detected MINSTKSIGSZ:10000
1298 10:53:18.115053 # Required Features: [ SME ] supported
1299 10:53:18.115240 # Incompatible Features: [] absent
1300 10:53:18.115387 # Testcase initialized.
1301 10:53:18.115534 # SIG_OK -- SP:0xFFFFD6898BF0 si_addr@:0xaaaabfb92514 si_code:1 token@:(nil) offset:-187650337744148
1302 10:53:18.115657 # ==>> completed. PASS(1)
1303 10:53:18.115772 # # SME trap without SM :: Check that we get a SIGILL if we use streaming mode without enabling it
1304 10:53:18.140647 ok 19 selftests: arm64: sme_trap_no_sm
1305 10:53:18.235435 # selftests: arm64: sme_trap_non_streaming
1306 10:53:18.292450 # Registered handlers for all signals.
1307 10:53:18.292956 # Detected MINSTKSIGSZ:10000
1308 10:53:18.293123 # Required Features: [] NOT supported
1309 10:53:18.293253 # Incompatible Features: [] supported
1310 10:53:18.293372 # ==>> completed. SKIP.
1311 10:53:18.293525 # # SME SM trap unsupported instruction :: Check that we get a SIGILL if we use an unsupported instruction in streaming mode
1312 10:53:18.301183 ok 20 selftests: arm64: sme_trap_non_streaming # SKIP
1313 10:53:18.350581 # selftests: arm64: sme_trap_za
1314 10:53:18.401151 # Registered handlers for all signals.
1315 10:53:18.401470 # Detected MINSTKSIGSZ:10000
1316 10:53:18.401604 # Testcase initialized.
1317 10:53:18.401960 # SIG_OK -- SP:0xFFFFE6A59C70 si_addr@:0xaaaab4ce2510 si_code:1 token@:(nil) offset:-187650154571024
1318 10:53:18.402090 # ==>> completed. PASS(1)
1319 10:53:18.402207 # # SME ZA trap :: Check that we get a SIGILL if we access ZA without enabling
1320 10:53:18.409383 ok 21 selftests: arm64: sme_trap_za
1321 10:53:18.457306 # selftests: arm64: sme_vl
1322 10:53:18.509912 # Registered handlers for all signals.
1323 10:53:18.510239 # Detected MINSTKSIGSZ:10000
1324 10:53:18.510421 # Required Features: [ SME ] supported
1325 10:53:18.510609 # Incompatible Features: [] absent
1326 10:53:18.510745 # Testcase initialized.
1327 10:53:18.510919 # uc context validated.
1328 10:53:18.511067 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1329 10:53:18.511209 # Handled SIG_COPYCTX
1330 10:53:18.511351 # got expected VL 32
1331 10:53:18.511493 # ==>> completed. PASS(1)
1332 10:53:18.511633 # # SME VL :: Check that we get the right SME VL reported
1333 10:53:18.518380 ok 22 selftests: arm64: sme_vl
1334 10:53:18.569190 # selftests: arm64: ssve_regs
1335 10:53:18.751227 # Registered handlers for all signals.
1336 10:53:18.751540 # Detected MINSTKSIGSZ:10000
1337 10:53:18.751926 # Required Features: [ SME FA64 ] supported
1338 10:53:18.752069 # Incompatible Features: [] absent
1339 10:53:18.752213 # Testcase initialized.
1340 10:53:18.752341 # Testing VL 256
1341 10:53:18.752499 # Validating EXTRA...
1342 10:53:18.752646 # uc context validated.
1343 10:53:18.752777 # 9360 byte GOOD CONTEXT grabbed from sig_copyctx handler
1344 10:53:18.752890 # Handled SIG_COPYCTX
1345 10:53:18.752987 # Got expected size 8752 and VL 256
1346 10:53:18.753078 # Testing VL 128
1347 10:53:18.753168 # Validating EXTRA...
1348 10:53:18.753282 # uc context validated.
1349 10:53:18.753377 # 4992 byte GOOD CONTEXT grabbed from sig_copyctx handler
1350 10:53:18.753468 # Handled SIG_COPYCTX
1351 10:53:18.753559 # Got expected size 4384 and VL 128
1352 10:53:18.753658 # Testing VL 64
1353 10:53:18.753751 # uc context validated.
1354 10:53:18.753842 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1355 10:53:18.753935 # Handled SIG_COPYCTX
1356 10:53:18.754061 # Got expected size 2208 and VL 64
1357 10:53:18.754161 # Testing VL 32
1358 10:53:18.759812 # uc context validated.
1359 10:53:18.760127 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1360 10:53:18.760230 # Handled SIG_COPYCTX
1361 10:53:18.760313 # Got expected size 1120 and VL 32
1362 10:53:18.760392 # Testing VL 16
1363 10:53:18.760486 # uc context validated.
1364 10:53:18.760640 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1365 10:53:18.760728 # Handled SIG_COPYCTX
1366 10:53:18.760824 # Got expected size 576 and VL 16
1367 10:53:18.760905 # ==>> completed. PASS(1)
1368 10:53:18.760984 # # Streaming SVE registers :: Check that we get the right Streaming SVE registers reported
1369 10:53:18.761807 ok 23 selftests: arm64: ssve_regs
1370 10:53:18.805632 # selftests: arm64: sve_regs
1371 10:53:19.199033 # Registered handlers for all signals.
1372 10:53:19.199394 # Detected MINSTKSIGSZ:10000
1373 10:53:19.199868 # Required Features: [ SVE ] supported
1374 10:53:19.200031 # Incompatible Features: [] absent
1375 10:53:19.200163 # Testcase initialized.
1376 10:53:19.200323 # Testing VL 256
1377 10:53:19.200454 # Validating EXTRA...
1378 10:53:19.200569 # uc context validated.
1379 10:53:19.200683 # 9360 byte GOOD CONTEXT grabbed from sig_copyctx handler
1380 10:53:19.200799 # Handled SIG_COPYCTX
1381 10:53:19.200913 # Got expected size 8752 and VL 256
1382 10:53:19.201053 # Testing VL 240
1383 10:53:19.201484 # Validating EXTRA...
1384 10:53:19.201711 # uc context validated.
1385 10:53:19.202191 # 8816 byte GOOD CONTEXT grabbed from sig_copyctx handler
1386 10:53:19.202394 # Handled SIG_COPYCTX
1387 10:53:19.202569 # Got expected size 8208 and VL 240
1388 10:53:19.202734 # Testing VL 224
1389 10:53:19.202888 # Validating EXTRA...
1390 10:53:19.203046 # uc context validated.
1391 10:53:19.203202 # 8272 byte GOOD CONTEXT grabbed from sig_copyctx handler
1392 10:53:19.203355 # Handled SIG_COPYCTX
1393 10:53:19.203536 # Got expected size 7664 and VL 224
1394 10:53:19.203700 # Testing VL 208
1395 10:53:19.203860 # Validating EXTRA...
1396 10:53:19.203989 # uc context validated.
1397 10:53:19.204103 # 7728 byte GOOD CONTEXT grabbed from sig_copyctx handler
1398 10:53:19.204216 # Handled SIG_COPYCTX
1399 10:53:19.204328 # Got expected size 7120 and VL 208
1400 10:53:19.204439 # Testing VL 192
1401 10:53:19.204550 # Validating EXTRA...
1402 10:53:19.204660 # uc context validated.
1403 10:53:19.204774 # 7184 byte GOOD CONTEXT grabbed from sig_copyctx handler
1404 10:53:19.204886 # Handled SIG_COPYCTX
1405 10:53:19.204997 # Got expected size 6576 and VL 192
1406 10:53:19.205109 # Testing VL 176
1407 10:53:19.205221 # Validating EXTRA...
1408 10:53:19.205332 # uc context validated.
1409 10:53:19.205444 # 6640 byte GOOD CONTEXT grabbed from sig_copyctx handler
1410 10:53:19.205589 # Handled SIG_COPYCTX
1411 10:53:19.205737 # Got expected size 6032 and VL 176
1412 10:53:19.205856 # Testing VL 160
1413 10:53:19.205966 # Validating EXTRA...
1414 10:53:19.206076 # uc context validated.
1415 10:53:19.210274 # 6096 byte GOOD CONTEXT grabbed from sig_copyctx handler
1416 10:53:19.210674 # Handled SIG_COPYCTX
1417 10:53:19.210859 # Got expected size 5488 and VL 160
1418 10:53:19.211025 # Testing VL 144
1419 10:53:19.211185 # Validating EXTRA...
1420 10:53:19.211342 # uc context validated.
1421 10:53:19.211488 # 5552 byte GOOD CONTEXT grabbed from sig_copyctx handler
1422 10:53:19.211650 # Handled SIG_COPYCTX
1423 10:53:19.211827 # Got expected size 4944 and VL 144
1424 10:53:19.211964 # Testing VL 128
1425 10:53:19.212081 # Validating EXTRA...
1426 10:53:19.212209 # uc context validated.
1427 10:53:19.212372 # 4992 byte GOOD CONTEXT grabbed from sig_copyctx handler
1428 10:53:19.212503 # Handled SIG_COPYCTX
1429 10:53:19.212620 # Got expected size 4384 and VL 128
1430 10:53:19.212736 # Testing VL 112
1431 10:53:19.212863 # Validating EXTRA...
1432 10:53:19.213004 # uc context validated.
1433 10:53:19.213138 # 4448 byte GOOD CONTEXT grabbed from sig_copyctx handler
1434 10:53:19.213252 # Handled SIG_COPYCTX
1435 10:53:19.213365 # Got expected size 3840 and VL 112
1436 10:53:19.213477 # Testing VL 96
1437 10:53:19.213635 # uc context validated.
1438 10:53:19.213901 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1439 10:53:19.214100 # Handled SIG_COPYCTX
1440 10:53:19.214286 # Got expected size 3296 and VL 96
1441 10:53:19.214467 # Testing VL 80
1442 10:53:19.214612 # uc context validated.
1443 10:53:19.214754 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1444 10:53:19.214898 # Handled SIG_COPYCTX
1445 10:53:19.215039 # Got expected size 2752 and VL 80
1446 10:53:19.215179 # Testing VL 64
1447 10:53:19.215319 # uc context validated.
1448 10:53:19.215459 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1449 10:53:19.215599 # Handled SIG_COPYCTX
1450 10:53:19.215739 # Got expected size 2208 and VL 64
1451 10:53:19.215882 # Testing VL 48
1452 10:53:19.216022 # uc context validated.
1453 10:53:19.216162 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1454 10:53:19.216302 # Handled SIG_COPYCTX
1455 10:53:19.216441 # Got expected size 1664 and VL 48
1456 10:53:19.216581 # Testing VL 32
1457 10:53:19.216720 # uc context validated.
1458 10:53:19.216863 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1459 10:53:19.217003 # Handled SIG_COPYCTX
1460 10:53:19.217143 # Got expected size 1120 and VL 32
1461 10:53:19.217282 # Testing VL 16
1462 10:53:19.217461 # uc context validated.
1463 10:53:19.217594 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1464 10:53:19.217747 # Handled SIG_COPYCTX
1465 10:53:19.217891 # Got expected size 576 and VL 16
1466 10:53:19.218033 # ==>> completed. PASS(1)
1467 10:53:19.218173 # # SVE registers :: Check that we get the right SVE registers reported
1468 10:53:19.218314 ok 24 selftests: arm64: sve_regs
1469 10:53:19.260855 # selftests: arm64: sve_vl
1470 10:53:19.309056 # Registered handlers for all signals.
1471 10:53:19.309579 # Detected MINSTKSIGSZ:10000
1472 10:53:19.309792 # Required Features: [ SVE ] supported
1473 10:53:19.309966 # Incompatible Features: [] absent
1474 10:53:19.310115 # Testcase initialized.
1475 10:53:19.310257 # uc context validated.
1476 10:53:19.310400 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1477 10:53:19.310578 # Handled SIG_COPYCTX
1478 10:53:19.310715 # got expected VL 64
1479 10:53:19.310858 # ==>> completed. PASS(1)
1480 10:53:19.311002 # # SVE VL :: Check that we get the right SVE VL reported
1481 10:53:19.318761 ok 25 selftests: arm64: sve_vl
1482 10:53:19.363883 # selftests: arm64: za_no_regs
1483 10:53:19.423264 # Registered handlers for all signals.
1484 10:53:19.423807 # Detected MINSTKSIGSZ:10000
1485 10:53:19.423967 # Required Features: [ SME ] supported
1486 10:53:19.424119 # Incompatible Features: [] absent
1487 10:53:19.424264 # Testcase initialized.
1488 10:53:19.424409 # Testing VL 256
1489 10:53:19.424551 # uc context validated.
1490 10:53:19.424733 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1491 10:53:19.424870 # Handled SIG_COPYCTX
1492 10:53:19.425014 # Got expected size 16 and VL 256
1493 10:53:19.425157 # Testing VL 128
1494 10:53:19.425304 # uc context validated.
1495 10:53:19.425433 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1496 10:53:19.425550 # Handled SIG_COPYCTX
1497 10:53:19.425682 # Got expected size 16 and VL 128
1498 10:53:19.425860 # Testing VL 64
1499 10:53:19.426003 # uc context validated.
1500 10:53:19.426148 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1501 10:53:19.426292 # Handled SIG_COPYCTX
1502 10:53:19.426433 # Got expected size 16 and VL 64
1503 10:53:19.426576 # Testing VL 32
1504 10:53:19.426716 # uc context validated.
1505 10:53:19.426858 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1506 10:53:19.427000 # Handled SIG_COPYCTX
1507 10:53:19.427181 # Got expected size 16 and VL 32
1508 10:53:19.427316 # Testing VL 16
1509 10:53:19.427458 # uc context validated.
1510 10:53:19.427599 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1511 10:53:19.427743 # Handled SIG_COPYCTX
1512 10:53:19.427886 # Got expected size 16 and VL 16
1513 10:53:19.428027 # ==>> completed. PASS(1)
1514 10:53:19.432508 # # ZA registers - ZA disabled :: Check ZA context with ZA disabled
1515 10:53:19.432898 ok 26 selftests: arm64: za_no_regs
1516 10:53:19.476923 # selftests: arm64: za_regs
1517 10:53:19.670991 # Registered handlers for all signals.
1518 10:53:19.672477 # Detected MINSTKSIGSZ:10000
1519 10:53:19.672742 # Required Features: [ SME ] supported
1520 10:53:19.672817 # Incompatible Features: [] absent
1521 10:53:19.672897 # Testcase initialized.
1522 10:53:19.672991 # Testing VL 256
1523 10:53:19.673112 # Validating EXTRA...
1524 10:53:19.673207 # uc context validated.
1525 10:53:19.673280 # 66160 byte GOOD CONTEXT grabbed from sig_copyctx handler
1526 10:53:19.673343 # Handled SIG_COPYCTX
1527 10:53:19.673427 # Got expected size 65552 and VL 256
1528 10:53:19.673519 # Testing VL 128
1529 10:53:19.673599 # Validating EXTRA...
1530 10:53:19.673685 # uc context validated.
1531 10:53:19.673770 # 17008 byte GOOD CONTEXT grabbed from sig_copyctx handler
1532 10:53:19.673863 # Handled SIG_COPYCTX
1533 10:53:19.673934 # Got expected size 16400 and VL 128
1534 10:53:19.674014 # Testing VL 64
1535 10:53:19.674081 # Validating EXTRA...
1536 10:53:19.674155 # uc context validated.
1537 10:53:19.674217 # 4720 byte GOOD CONTEXT grabbed from sig_copyctx handler
1538 10:53:19.674291 # Handled SIG_COPYCTX
1539 10:53:19.674353 # Got expected size 4112 and VL 64
1540 10:53:19.674412 # Testing VL 32
1541 10:53:19.674470 # uc context validated.
1542 10:53:19.674529 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1543 10:53:19.674587 # Handled SIG_COPYCTX
1544 10:53:19.674658 # Got expected size 1040 and VL 32
1545 10:53:19.674720 # Testing VL 16
1546 10:53:19.674779 # uc context validated.
1547 10:53:19.674837 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1548 10:53:19.674895 # Handled SIG_COPYCTX
1549 10:53:19.674966 # Got expected size 272 and VL 16
1550 10:53:19.675027 # ==>> completed. PASS(1)
1551 10:53:19.675085 # # ZA register :: Check that we get the right ZA registers reported
1552 10:53:19.681370 ok 27 selftests: arm64: za_regs
1553 10:53:19.725460 # selftests: arm64: pac
1554 10:53:19.881751 # TAP version 13
1555 10:53:19.882041 # 1..7
1556 10:53:19.882226 # # Starting 7 tests from 1 test cases.
1557 10:53:19.882605 # # RUN global.corrupt_pac ...
1558 10:53:19.882746 # # OK global.corrupt_pac
1559 10:53:19.882893 # ok 1 global.corrupt_pac
1560 10:53:19.883040 # # RUN global.pac_instructions_not_nop ...
1561 10:53:19.883184 # # OK global.pac_instructions_not_nop
1562 10:53:19.883326 # ok 2 global.pac_instructions_not_nop
1563 10:53:19.883468 # # RUN global.pac_instructions_not_nop_generic ...
1564 10:53:19.883611 # # OK global.pac_instructions_not_nop_generic
1565 10:53:19.883795 # ok 3 global.pac_instructions_not_nop_generic
1566 10:53:19.883930 # # RUN global.single_thread_different_keys ...
1567 10:53:19.884076 # # OK global.single_thread_different_keys
1568 10:53:19.884217 # ok 4 global.single_thread_different_keys
1569 10:53:19.884364 # # RUN global.exec_changed_keys ...
1570 10:53:19.884506 # # OK global.exec_changed_keys
1571 10:53:19.884648 # ok 5 global.exec_changed_keys
1572 10:53:19.884789 # # RUN global.context_switch_keep_keys ...
1573 10:53:19.884931 # # OK global.context_switch_keep_keys
1574 10:53:19.885072 # ok 6 global.context_switch_keep_keys
1575 10:53:19.885214 # # RUN global.context_switch_keep_keys_generic ...
1576 10:53:19.885357 # # OK global.context_switch_keep_keys_generic
1577 10:53:19.885497 # ok 7 global.context_switch_keep_keys_generic
1578 10:53:19.885684 # # PASSED: 7 / 7 tests passed.
1579 10:53:19.885824 # # Totals: pass:7 fail:0 xfail:0 xpass:0 skip:0 error:0
1580 10:53:19.898619 ok 28 selftests: arm64: pac
1581 10:53:19.988915 # selftests: arm64: fp-stress
1582 10:53:37.756692 # TAP version 13
1583 10:53:37.757124 # 1..27
1584 10:53:37.757223 # # 1 CPUs, 16 SVE VLs, 5 SME VLs
1585 10:53:37.757331 # # Will run for 10s
1586 10:53:37.757420 # # Started FPSIMD-0-0
1587 10:53:37.757507 # # Started SVE-VL-256-0
1588 10:53:37.757593 # # Started SVE-VL-240-0
1589 10:53:37.757684 # # Started SVE-VL-224-0
1590 10:53:37.757787 # # Started SVE-VL-208-0
1591 10:53:37.757873 # # Started SVE-VL-192-0
1592 10:53:37.757961 # # Started SVE-VL-176-0
1593 10:53:37.758045 # # Started SVE-VL-160-0
1594 10:53:37.758130 # # Started SVE-VL-144-0
1595 10:53:37.758214 # # Started SVE-VL-128-0
1596 10:53:37.758297 # # Started SVE-VL-112-0
1597 10:53:37.758399 # # Started SVE-VL-96-0
1598 10:53:37.758484 # # Started SVE-VL-80-0
1599 10:53:37.758568 # # Started SVE-VL-64-0
1600 10:53:37.758651 # # Started SVE-VL-48-0
1601 10:53:37.758735 # # Started SVE-VL-32-0
1602 10:53:37.758818 # # Started SVE-VL-16-0
1603 10:53:37.758901 # # Started SSVE-VL-256-0
1604 10:53:37.759006 # # Started ZA-VL-256-0
1605 10:53:37.759091 # # Started SSVE-VL-128-0
1606 10:53:37.759171 # # Started ZA-VL-128-0
1607 10:53:37.759246 # # Started SSVE-VL-64-0
1608 10:53:37.759352 # # Started ZA-VL-64-0
1609 10:53:37.759430 # # Started SSVE-VL-32-0
1610 10:53:37.759519 # # Started ZA-VL-32-0
1611 10:53:37.759595 # # Started SSVE-VL-16-0
1612 10:53:37.759667 # # Started ZA-VL-16-0
1613 10:53:37.765219 # # SVE-VL-256-0: Vector length: 2048 bits
1614 10:53:37.765418 # # SVE-VL-256-0: PID: 909
1615 10:53:37.765510 # # SVE-VL-224-0: Vector length: 1792 bits
1616 10:53:37.765613 # # SVE-VL-224-0: PID: 911
1617 10:53:37.765706 # # SVE-VL-240-0: Vector length: 1920 bits
1618 10:53:37.765792 # # SVE-VL-240-0: PID: 910
1619 10:53:37.765875 # # SVE-VL-208-0: Vector length: 1664 bits
1620 10:53:37.765980 # # SVE-VL-208-0: PID: 912
1621 10:53:37.766066 # # SVE-VL-160-0: Vector length: 1280 bits
1622 10:53:37.766149 # # SVE-VL-160-0: PID: 915
1623 10:53:37.766250 # # SVE-VL-176-0: Vector length: 1408 bits
1624 10:53:37.766335 # # SVE-VL-176-0: PID: 914
1625 10:53:37.766420 # # SVE-VL-128-0: Vector length: 1024 bits
1626 10:53:37.766519 # # SVE-VL-128-0: PID: 917
1627 10:53:37.766607 # # SVE-VL-112-0: Vector length: 896 bits
1628 10:53:37.766707 # # SVE-VL-112-0: PID: 918
1629 10:53:37.766792 # # SVE-VL-96-0: Vector length: 768 bits
1630 10:53:37.766892 # # SVE-VL-96-0: PID: 919
1631 10:53:37.766983 # # FPSIMD-0-0: Vector length: 128 bits
1632 10:53:37.767082 # # FPSIMD-0-0: PID: 908
1633 10:53:37.772752 # # SVE-VL-48-0: Vector length: 384 bits
1634 10:53:37.772961 # # SVE-VL-48-0: PID: 922
1635 10:53:37.773079 # # SVE-VL-32-0: Vector length: 256 bits
1636 10:53:37.773170 # # SSVE-VL-32-0: Streaming mode Vector length: 256 bits
1637 10:53:37.773254 # # SSVE-VL-32-0: PID: 931
1638 10:53:37.773342 # # SVE-VL-32-0: PID: 923
1639 10:53:37.773444 # # SSVE-VL-256-0: Streaming mode Vector length: 2048 bits
1640 10:53:37.773717 # # SSVE-VL-256-0: PID: 925
1641 10:53:37.773813 # # SVE-VL-144-0: Vector length: 1152 bits
1642 10:53:37.773913 # # SVE-VL-144-0: PID: 916
1643 10:53:37.774209 # # SVE-VL-64-0: Vector length: 512 bits
1644 10:53:37.774305 # # SVE-VL-64-0: PID: 921
1645 10:53:37.774404 # # SVE-VL-80-0: Vector length: 640 bits
1646 10:53:37.774486 # # SVE-VL-80-0: PID: 920
1647 10:53:37.774578 # # SSVE-VL-128-0: Streaming mode Vector length: 1024 bits
1648 10:53:37.774646 # # SSVE-VL-128-0: PID: 927
1649 10:53:37.774923 # # SVE-VL-16-0: Vector length: 128 bits
1650 10:53:37.775096 # # SVE-VL-16-0: PID: 924
1651 10:53:37.799894 # # ZA-VL-32-0: Streaming mode vector length: 256 bits
1652 10:53:37.800339 # # ZA-VL-128-0: Streaming mode vector length: 1024 bits
1653 10:53:37.800422 # # SSVE-VL-64-0: Streaming mode Vector length: 512 bits
1654 10:53:37.800502 # # SSVE-VL-64-0: PID: 929
1655 10:53:37.800578 # # ZA-VL-16-0: Streaming mode vector length: 128 bits
1656 10:53:37.800653 # # ZA-VL-16-0: PID: 934
1657 10:53:37.800747 # # ZA-VL-32-0: PID: 932
1658 10:53:37.800818 # # ZA-VL-64-0: Streaming mode vector length: 512 bits
1659 10:53:37.800893 # # ZA-VL-64-0: PID: 930
1660 10:53:37.800967 # # ZA-VL-128-0: PID: 928
1661 10:53:37.801047 # # ZA-VL-256-0: Streaming mode vector length: 2048 bits
1662 10:53:37.801142 # # ZA-VL-256-0: PID: 926
1663 10:53:37.801213 # # SVE-VL-192-0: Vector length: 1536 bits
1664 10:53:37.801288 # # SVE-VL-192-0: PID: 913
1665 10:53:37.801363 # # SSVE-VL-16-0: Streaming mode Vector length: 128 bits
1666 10:53:37.801437 # # SSVE-VL-16-0: PID: 933
1667 10:53:37.801529 # # Finishing up...
1668 10:53:37.801599 # ok 1 FPSIMD-0-0
1669 10:53:37.801686 # ok 2 SVE-VL-256-0
1670 10:53:37.801762 # ok 3 SVE-VL-240-0
1671 10:53:37.801837 # ok 4 SVE-VL-224-0
1672 10:53:37.801910 # ok 5 SVE-VL-208-0
1673 10:53:37.801984 # ok 6 SVE-VL-192-0
1674 10:53:37.802078 # ok 7 SVE-VL-176-0
1675 10:53:37.802185 # ok 8 SVE-VL-160-0
1676 10:53:37.802272 # ok 9 SVE-VL-144-0
1677 10:53:37.802394 # ok 10 SVE-VL-128-0
1678 10:53:37.802486 # ok 11 SVE-VL-112-0
1679 10:53:37.802575 # ok 12 SVE-VL-96-0
1680 10:53:37.802651 # ok 13 SVE-VL-80-0
1681 10:53:37.802725 # ok 14 SVE-VL-64-0
1682 10:53:37.802816 # ok 15 SVE-VL-48-0
1683 10:53:37.802913 # ok 16 SVE-VL-32-0
1684 10:53:37.803010 # ok 17 SVE-VL-16-0
1685 10:53:37.803156 # ok 18 SSVE-VL-256-0
1686 10:53:37.803244 # ok 19 ZA-VL-256-0
1687 10:53:37.803324 # ok 20 SSVE-VL-128-0
1688 10:53:37.803407 # ok 21 ZA-VL-128-0
1689 10:53:37.803489 # ok 22 SSVE-VL-64-0
1690 10:53:37.803575 # ok 23 ZA-VL-64-0
1691 10:53:37.803658 # ok 24 SSVE-VL-32-0
1692 10:53:37.803748 # ok 25 ZA-VL-32-0
1693 10:53:37.803840 # ok 26 SSVE-VL-16-0
1694 10:53:37.803930 # ok 27 ZA-VL-16-0
1695 10:53:37.804014 # # ZA-VL-32-0: Terminated by signal 15, no error, iterations=2049, signals=9
1696 10:53:37.804079 # # SVE-VL-224-0: Terminated by signal 15, no error, iterations=3088, signals=9
1697 10:53:37.804146 # # SVE-VL-128-0: Terminated by signal 15, no error, iterations=4878, signals=9
1698 10:53:37.804210 # # ZA-VL-16-0: Terminated by signal 15, no error, iterations=2218, signals=9
1699 10:53:37.804273 # # SSVE-VL-16-0: Terminated by signal 15, no error, iterations=9325, signals=9
1700 10:53:37.804346 # # FPSIMD-0-0: Terminated by signal 15, no error, iterations=4074, signals=9
1701 10:53:37.804419 # # SVE-VL-16-0: Terminated by signal 15, no error, iterations=12569, signals=9
1702 10:53:37.804480 # # SSVE-VL-128-0: Terminated by signal 15, no error, iterations=4511, signals=9
1703 10:53:37.843213 # # ZA-VL-256-0: Terminated by signal 15, no error, iterations=153, signals=9
1704 10:53:37.843428 # # SVE-VL-32-0: Terminated by signal 15, no error, iterations=10331, signals=9
1705 10:53:37.915016 # # ZA-VL-64-0: Terminated by signal 15, no error, iterations=1460, signals=9
1706 10:53:37.915241 # # ZA-VL-128-0: Terminated by signal 15, no error, iterations=734, signals=9
1707 10:53:37.915330 # # SVE-VL-112-0: Terminated by signal 15, no error, iterations=5449, signals=9
1708 10:53:37.915430 # # SVE-VL-240-0: Terminated by signal 15, no error, iterations=3025, signals=9
1709 10:53:37.920985 # # SVE-VL-80-0: Terminated by signal 15, no error, iterations=5842, signals=9
1710 10:53:37.921321 # # SVE-VL-48-0: Terminated by signal 15, no error, iterations=8377, signals=9
1711 10:53:37.921442 # # SVE-VL-64-0: Terminated by signal 15, no error, iterations=6561, signals=9
1712 10:53:37.921548 # # SVE-VL-192-0: Terminated by signal 15, no error, iterations=1957, signals=9
1713 10:53:37.921656 # # SVE-VL-256-0: Terminated by signal 15, no error, iterations=2964, signals=9
1714 10:53:37.922013 # # SSVE-VL-32-0: Terminated by signal 15, no error, iterations=10831, signals=9
1715 10:53:37.922118 # # SSVE-VL-256-0: Terminated by signal 15, no error, iterations=2966, signals=9
1716 10:53:37.922223 # # SVE-VL-208-0: Terminated by signal 15, no error, iterations=3419, signals=9
1717 10:53:37.922311 # # SVE-VL-96-0: Terminated by signal 15, no error, iterations=5531, signals=9
1718 10:53:37.922602 # # SVE-VL-176-0: Terminated by signal 15, no error, iterations=3712, signals=9
1719 10:53:37.922714 # # SSVE-VL-64-0: Terminated by signal 15, no error, iterations=6820, signals=9
1720 10:53:37.922816 # # SVE-VL-160-0: Terminated by signal 15, no error, iterations=4025, signals=9
1721 10:53:37.922916 # # SVE-VL-144-0: Terminated by signal 15, no error, iterations=4270, signals=9
1722 10:53:37.923000 # # Totals: pass:27 fail:0 xfail:0 xpass:0 skip:0 error:0
1723 10:53:37.945507 ok 29 selftests: arm64: fp-stress
1724 10:53:38.138391 # selftests: arm64: sve-ptrace
1725 10:53:38.290643 # TAP version 13
1726 10:53:38.290891 # 1..4104
1727 10:53:38.290979 # # Parent is 951, child is 952
1728 10:53:38.291068 # ok 1 SVE FPSIMD set via SVE: 0
1729 10:53:38.291147 # ok 2 SVE get_fpsimd() gave same state
1730 10:53:38.291442 # ok 3 SVE SVE_PT_VL_INHERIT set
1731 10:53:38.291546 # ok 4 SVE SVE_PT_VL_INHERIT cleared
1732 10:53:38.291630 # ok 5 Set SVE VL 16
1733 10:53:38.291710 # ok 6 Set and get SVE data for VL 16
1734 10:53:38.291789 # ok 7 Set and get FPSIMD data for SVE VL 16
1735 10:53:38.291869 # ok 8 Set FPSIMD, read via SVE for SVE VL 16
1736 10:53:38.291954 # ok 9 Set SVE VL 32
1737 10:53:38.292034 # ok 10 Set and get SVE data for VL 32
1738 10:53:38.292111 # ok 11 Set and get FPSIMD data for SVE VL 32
1739 10:53:38.292189 # ok 12 Set FPSIMD, read via SVE for SVE VL 32
1740 10:53:38.292266 # ok 13 Set SVE VL 48
1741 10:53:38.292343 # ok 14 Set and get SVE data for VL 48
1742 10:53:38.292437 # ok 15 Set and get FPSIMD data for SVE VL 48
1743 10:53:38.292518 # ok 16 Set FPSIMD, read via SVE for SVE VL 48
1744 10:53:38.292596 # ok 17 Set SVE VL 64
1745 10:53:38.292672 # ok 18 Set and get SVE data for VL 64
1746 10:53:38.292749 # ok 19 Set and get FPSIMD data for SVE VL 64
1747 10:53:38.292827 # ok 20 Set FPSIMD, read via SVE for SVE VL 64
1748 10:53:38.292905 # ok 21 Set SVE VL 80
1749 10:53:38.292998 # ok 22 Set and get SVE data for VL 80
1750 10:53:38.293079 # ok 23 Set and get FPSIMD data for SVE VL 80
1751 10:53:38.293156 # ok 24 Set FPSIMD, read via SVE for SVE VL 80
1752 10:53:38.293232 # ok 25 Set SVE VL 96
1753 10:53:38.293321 # ok 26 Set and get SVE data for VL 96
1754 10:53:38.293401 # ok 27 Set and get FPSIMD data for SVE VL 96
1755 10:53:38.293500 # ok 28 Set FPSIMD, read via SVE for SVE VL 96
1756 10:53:38.293583 # ok 29 Set SVE VL 112
1757 10:53:38.293669 # ok 30 Set and get SVE data for VL 112
1758 10:53:38.293749 # ok 31 Set and get FPSIMD data for SVE VL 112
1759 10:53:38.293828 # ok 32 Set FPSIMD, read via SVE for SVE VL 112
1760 10:53:38.293921 # ok 33 Set SVE VL 128
1761 10:53:38.294002 # ok 34 Set and get SVE data for VL 128
1762 10:53:38.294080 # ok 35 Set and get FPSIMD data for SVE VL 128
1763 10:53:38.294158 # ok 36 Set FPSIMD, read via SVE for SVE VL 128
1764 10:53:38.294251 # ok 37 Set SVE VL 144
1765 10:53:38.294331 # ok 38 Set and get SVE data for VL 144
1766 10:53:38.294424 # ok 39 Set and get FPSIMD data for SVE VL 144
1767 10:53:38.294505 # ok 40 Set FPSIMD, read via SVE for SVE VL 144
1768 10:53:38.294583 # ok 41 Set SVE VL 160
1769 10:53:38.294674 # ok 42 Set and get SVE data for VL 160
1770 10:53:38.294758 # ok 43 Set and get FPSIMD data for SVE VL 160
1771 10:53:38.294850 # ok 44 Set FPSIMD, read via SVE for SVE VL 160
1772 10:53:38.294930 # ok 45 Set SVE VL 176
1773 10:53:38.295022 # ok 46 Set and get SVE data for VL 176
1774 10:53:38.295102 # ok 47 Set and get FPSIMD data for SVE VL 176
1775 10:53:38.295390 # ok 48 Set FPSIMD, read via SVE for SVE VL 176
1776 10:53:38.295494 # ok 49 Set SVE VL 192
1777 10:53:38.295577 # ok 50 Set and get SVE data for VL 192
1778 10:53:38.295657 # ok 51 Set and get FPSIMD data for SVE VL 192
1779 10:53:38.300367 # ok 52 Set FPSIMD, read via SVE for SVE VL 192
1780 10:53:38.300473 # ok 53 Set SVE VL 208
1781 10:53:38.300556 # ok 54 Set and get SVE data for VL 208
1782 10:53:38.300650 # ok 55 Set and get FPSIMD data for SVE VL 208
1783 10:53:38.300731 # ok 56 Set FPSIMD, read via SVE for SVE VL 208
1784 10:53:38.300809 # ok 57 Set SVE VL 224
1785 10:53:38.300886 # ok 58 Set and get SVE data for VL 224
1786 10:53:38.300979 # ok 59 Set and get FPSIMD data for SVE VL 224
1787 10:53:38.301059 # ok 60 Set FPSIMD, read via SVE for SVE VL 224
1788 10:53:38.301137 # ok 61 Set SVE VL 240
1789 10:53:38.301229 # ok 62 Set and get SVE data for VL 240
1790 10:53:38.301309 # ok 63 Set and get FPSIMD data for SVE VL 240
1791 10:53:38.301388 # ok 64 Set FPSIMD, read via SVE for SVE VL 240
1792 10:53:38.301480 # ok 65 Set SVE VL 256
1793 10:53:38.301560 # ok 66 Set and get SVE data for VL 256
1794 10:53:38.301638 # ok 67 Set and get FPSIMD data for SVE VL 256
1795 10:53:38.301743 # ok 68 Set FPSIMD, read via SVE for SVE VL 256
1796 10:53:38.301823 # ok 69 Set SVE VL 272
1797 10:53:38.301914 # ok 70 # SKIP SVE set SVE get SVE for VL 272
1798 10:53:38.302004 # ok 71 # SKIP SVE set SVE get FPSIMD for VL 272
1799 10:53:38.302098 # ok 72 # SKIP SVE set FPSIMD get SVE for VL 272
1800 10:53:38.302181 # ok 73 Set SVE VL 288
1801 10:53:38.302273 # ok 74 # SKIP SVE set SVE get SVE for VL 288
1802 10:53:38.302356 # ok 75 # SKIP SVE set SVE get FPSIMD for VL 288
1803 10:53:38.302450 # ok 76 # SKIP SVE set FPSIMD get SVE for VL 288
1804 10:53:38.302545 # ok 77 Set SVE VL 304
1805 10:53:38.302628 # ok 78 # SKIP SVE set SVE get SVE for VL 304
1806 10:53:38.302722 # ok 79 # SKIP SVE set SVE get FPSIMD for VL 304
1807 10:53:38.303014 # ok 80 # SKIP SVE set FPSIMD get SVE for VL 304
1808 10:53:38.303117 # ok 81 Set SVE VL 320
1809 10:53:38.303200 # ok 82 # SKIP SVE set SVE get SVE for VL 320
1810 10:53:38.303294 # ok 83 # SKIP SVE set SVE get FPSIMD for VL 320
1811 10:53:38.303374 # ok 84 # SKIP SVE set FPSIMD get SVE for VL 320
1812 10:53:38.303453 # ok 85 Set SVE VL 336
1813 10:53:38.303530 # ok 86 # SKIP SVE set SVE get SVE for VL 336
1814 10:53:38.310573 # ok 87 # SKIP SVE set SVE get FPSIMD for VL 336
1815 10:53:38.310903 # ok 88 # SKIP SVE set FPSIMD get SVE for VL 336
1816 10:53:38.311038 # ok 89 Set SVE VL 352
1817 10:53:38.311127 # ok 90 # SKIP SVE set SVE get SVE for VL 352
1818 10:53:38.311206 # ok 91 # SKIP SVE set SVE get FPSIMD for VL 352
1819 10:53:38.311301 # ok 92 # SKIP SVE set FPSIMD get SVE for VL 352
1820 10:53:38.311382 # ok 93 Set SVE VL 368
1821 10:53:38.311460 # ok 94 # SKIP SVE set SVE get SVE for VL 368
1822 10:53:38.311553 # ok 95 # SKIP SVE set SVE get FPSIMD for VL 368
1823 10:53:38.312011 # ok 96 # SKIP SVE set FPSIMD get SVE for VL 368
1824 10:53:38.312331 # ok 97 Set SVE VL 384
1825 10:53:38.312438 # ok 98 # SKIP SVE set SVE get SVE for VL 384
1826 10:53:38.312520 # ok 99 # SKIP SVE set SVE get FPSIMD for VL 384
1827 10:53:38.312613 # ok 100 # SKIP SVE set FPSIMD get SVE for VL 384
1828 10:53:38.312693 # ok 101 Set SVE VL 400
1829 10:53:38.313669 # ok 102 # SKIP SVE set SVE get SVE for VL 400
1830 10:53:38.313788 # ok 103 # SKIP SVE set SVE get FPSIMD for VL 400
1831 10:53:38.313875 # ok 104 # SKIP SVE set FPSIMD get SVE for VL 400
1832 10:53:38.313973 # ok 105 Set SVE VL 416
1833 10:53:38.314059 # ok 106 # SKIP SVE set SVE get SVE for VL 416
1834 10:53:38.314151 # ok 107 # SKIP SVE set SVE get FPSIMD for VL 416
1835 10:53:38.314245 # ok 108 # SKIP SVE set FPSIMD get SVE for VL 416
1836 10:53:38.314326 # ok 109 Set SVE VL 432
1837 10:53:38.314417 # ok 110 # SKIP SVE set SVE get SVE for VL 432
1838 10:53:38.314514 # ok 111 # SKIP SVE set SVE get FPSIMD for VL 432
1839 10:53:38.314606 # ok 112 # SKIP SVE set FPSIMD get SVE for VL 432
1840 10:53:38.314698 # ok 113 Set SVE VL 448
1841 10:53:38.314790 # ok 114 # SKIP SVE set SVE get SVE for VL 448
1842 10:53:38.315128 # ok 115 # SKIP SVE set SVE get FPSIMD for VL 448
1843 10:53:38.315336 # ok 116 # SKIP SVE set FPSIMD get SVE for VL 448
1844 10:53:38.315548 # ok 117 Set SVE VL 464
1845 10:53:38.315710 # ok 118 # SKIP SVE set SVE get SVE for VL 464
1846 10:53:38.315842 # ok 119 # SKIP SVE set SVE get FPSIMD for VL 464
1847 10:53:38.322488 # ok 120 # SKIP SVE set FPSIMD get SVE for VL 464
1848 10:53:38.322779 # ok 121 Set SVE VL 480
1849 10:53:38.322881 # ok 122 # SKIP SVE set SVE get SVE for VL 480
1850 10:53:38.322965 # ok 123 # SKIP SVE set SVE get FPSIMD for VL 480
1851 10:53:38.323060 # ok 124 # SKIP SVE set FPSIMD get SVE for VL 480
1852 10:53:38.323144 # ok 125 Set SVE VL 496
1853 10:53:38.323239 # ok 126 # SKIP SVE set SVE get SVE for VL 496
1854 10:53:38.323321 # ok 127 # SKIP SVE set SVE get FPSIMD for VL 496
1855 10:53:38.323412 # ok 128 # SKIP SVE set FPSIMD get SVE for VL 496
1856 10:53:38.323987 # ok 129 Set SVE VL 512
1857 10:53:38.324297 # ok 130 # SKIP SVE set SVE get SVE for VL 512
1858 10:53:38.324400 # ok 131 # SKIP SVE set SVE get FPSIMD for VL 512
1859 10:53:38.324484 # ok 132 # SKIP SVE set FPSIMD get SVE for VL 512
1860 10:53:38.324564 # ok 133 Set SVE VL 528
1861 10:53:38.324660 # ok 134 # SKIP SVE set SVE get SVE for VL 528
1862 10:53:38.324741 # ok 135 # SKIP SVE set SVE get FPSIMD for VL 528
1863 10:53:38.324834 # ok 136 # SKIP SVE set FPSIMD get SVE for VL 528
1864 10:53:38.324915 # ok 137 Set SVE VL 544
1865 10:53:38.325008 # ok 138 # SKIP SVE set SVE get SVE for VL 544
1866 10:53:38.325100 # ok 139 # SKIP SVE set SVE get FPSIMD for VL 544
1867 10:53:38.325394 # ok 140 # SKIP SVE set FPSIMD get SVE for VL 544
1868 10:53:38.325497 # ok 141 Set SVE VL 560
1869 10:53:38.325594 # ok 142 # SKIP SVE set SVE get SVE for VL 560
1870 10:53:38.325685 # ok 143 # SKIP SVE set SVE get FPSIMD for VL 560
1871 10:53:38.325779 # ok 144 # SKIP SVE set FPSIMD get SVE for VL 560
1872 10:53:38.326051 # ok 145 Set SVE VL 576
1873 10:53:38.326137 # ok 146 # SKIP SVE set SVE get SVE for VL 576
1874 10:53:38.326231 # ok 147 # SKIP SVE set SVE get FPSIMD for VL 576
1875 10:53:38.326313 # ok 148 # SKIP SVE set FPSIMD get SVE for VL 576
1876 10:53:38.326392 # ok 149 Set SVE VL 592
1877 10:53:38.326485 # ok 150 # SKIP SVE set SVE get SVE for VL 592
1878 10:53:38.326567 # ok 151 # SKIP SVE set SVE get FPSIMD for VL 592
1879 10:53:38.326843 # ok 152 # SKIP SVE set FPSIMD get SVE for VL 592
1880 10:53:38.326929 # ok 153 Set SVE VL 608
1881 10:53:38.327028 # ok 154 # SKIP SVE set SVE get SVE for VL 608
1882 10:53:38.327120 # ok 155 # SKIP SVE set SVE get FPSIMD for VL 608
1883 10:53:38.327202 # ok 156 # SKIP SVE set FPSIMD get SVE for VL 608
1884 10:53:38.327296 # ok 157 Set SVE VL 624
1885 10:53:38.327393 # ok 158 # SKIP SVE set SVE get SVE for VL 624
1886 10:53:38.334398 # ok 159 # SKIP SVE set SVE get FPSIMD for VL 624
1887 10:53:38.334813 # ok 160 # SKIP SVE set FPSIMD get SVE for VL 624
1888 10:53:38.334917 # ok 161 Set SVE VL 640
1889 10:53:38.335010 # ok 162 # SKIP SVE set SVE get SVE for VL 640
1890 10:53:38.335106 # ok 163 # SKIP SVE set SVE get FPSIMD for VL 640
1891 10:53:38.335212 # ok 164 # SKIP SVE set FPSIMD get SVE for VL 640
1892 10:53:38.335306 # ok 165 Set SVE VL 656
1893 10:53:38.335393 # ok 166 # SKIP SVE set SVE get SVE for VL 656
1894 10:53:38.335489 # ok 167 # SKIP SVE set SVE get FPSIMD for VL 656
1895 10:53:38.335570 # ok 168 # SKIP SVE set FPSIMD get SVE for VL 656
1896 10:53:38.336105 # ok 169 Set SVE VL 672
1897 10:53:38.336552 # ok 170 # SKIP SVE set SVE get SVE for VL 672
1898 10:53:38.336758 # ok 171 # SKIP SVE set SVE get FPSIMD for VL 672
1899 10:53:38.336961 # ok 172 # SKIP SVE set FPSIMD get SVE for VL 672
1900 10:53:38.337148 # ok 173 Set SVE VL 688
1901 10:53:38.337609 # ok 174 # SKIP SVE set SVE get SVE for VL 688
1902 10:53:38.337827 # ok 175 # SKIP SVE set SVE get FPSIMD for VL 688
1903 10:53:38.338010 # ok 176 # SKIP SVE set FPSIMD get SVE for VL 688
1904 10:53:38.338187 # ok 177 Set SVE VL 704
1905 10:53:38.338364 # ok 178 # SKIP SVE set SVE get SVE for VL 704
1906 10:53:38.338535 # ok 179 # SKIP SVE set SVE get FPSIMD for VL 704
1907 10:53:38.338702 # ok 180 # SKIP SVE set FPSIMD get SVE for VL 704
1908 10:53:38.338867 # ok 181 Set SVE VL 720
1909 10:53:38.339021 # ok 182 # SKIP SVE set SVE get SVE for VL 720
1910 10:53:38.339184 # ok 183 # SKIP SVE set SVE get FPSIMD for VL 720
1911 10:53:38.339394 # ok 184 # SKIP SVE set FPSIMD get SVE for VL 720
1912 10:53:38.339542 # ok 185 Set SVE VL 736
1913 10:53:38.339662 # ok 186 # SKIP SVE set SVE get SVE for VL 736
1914 10:53:38.339778 # ok 187 # SKIP SVE set SVE get FPSIMD for VL 736
1915 10:53:38.339891 # ok 188 # SKIP SVE set FPSIMD get SVE for VL 736
1916 10:53:38.340026 # ok 189 Set SVE VL 752
1917 10:53:38.340223 # ok 190 # SKIP SVE set SVE get SVE for VL 752
1918 10:53:38.340382 # ok 191 # SKIP SVE set SVE get FPSIMD for VL 752
1919 10:53:38.340509 # ok 192 # SKIP SVE set FPSIMD get SVE for VL 752
1920 10:53:38.340632 # ok 193 Set SVE VL 768
1921 10:53:38.340782 # ok 194 # SKIP SVE set SVE get SVE for VL 768
1922 10:53:38.340986 # ok 195 # SKIP SVE set SVE get FPSIMD for VL 768
1923 10:53:38.341174 # ok 196 # SKIP SVE set FPSIMD get SVE for VL 768
1924 10:53:38.341309 # ok 197 Set SVE VL 784
1925 10:53:38.341432 # ok 198 # SKIP SVE set SVE get SVE for VL 784
1926 10:53:38.341555 # ok 199 # SKIP SVE set SVE get FPSIMD for VL 784
1927 10:53:38.341781 # ok 200 # SKIP SVE set FPSIMD get SVE for VL 784
1928 10:53:38.341981 # ok 201 Set SVE VL 800
1929 10:53:38.347360 # ok 202 # SKIP SVE set SVE get SVE for VL 800
1930 10:53:38.347834 # ok 203 # SKIP SVE set SVE get FPSIMD for VL 800
1931 10:53:38.348220 # ok 204 # SKIP SVE set FPSIMD get SVE for VL 800
1932 10:53:38.348329 # ok 205 Set SVE VL 816
1933 10:53:38.348435 # ok 206 # SKIP SVE set SVE get SVE for VL 816
1934 10:53:38.348523 # ok 207 # SKIP SVE set SVE get FPSIMD for VL 816
1935 10:53:38.348625 # ok 208 # SKIP SVE set FPSIMD get SVE for VL 816
1936 10:53:38.348710 # ok 209 Set SVE VL 832
1937 10:53:38.348811 # ok 210 # SKIP SVE set SVE get SVE for VL 832
1938 10:53:38.348913 # ok 211 # SKIP SVE set SVE get FPSIMD for VL 832
1939 10:53:38.349016 # ok 212 # SKIP SVE set FPSIMD get SVE for VL 832
1940 10:53:38.349117 # ok 213 Set SVE VL 848
1941 10:53:38.349219 # ok 214 # SKIP SVE set SVE get SVE for VL 848
1942 10:53:38.349327 # ok 215 # SKIP SVE set SVE get FPSIMD for VL 848
1943 10:53:38.349692 # ok 216 # SKIP SVE set FPSIMD get SVE for VL 848
1944 10:53:38.349797 # ok 217 Set SVE VL 864
1945 10:53:38.349901 # ok 218 # SKIP SVE set SVE get SVE for VL 864
1946 10:53:38.350006 # ok 219 # SKIP SVE set SVE get FPSIMD for VL 864
1947 10:53:38.350112 # ok 220 # SKIP SVE set FPSIMD get SVE for VL 864
1948 10:53:38.350215 # ok 221 Set SVE VL 880
1949 10:53:38.350334 # ok 222 # SKIP SVE set SVE get SVE for VL 880
1950 10:53:38.350444 # ok 223 # SKIP SVE set SVE get FPSIMD for VL 880
1951 10:53:38.350785 # ok 224 # SKIP SVE set FPSIMD get SVE for VL 880
1952 10:53:38.350994 # ok 225 Set SVE VL 896
1953 10:53:38.351172 # ok 226 # SKIP SVE set SVE get SVE for VL 896
1954 10:53:38.351378 # ok 227 # SKIP SVE set SVE get FPSIMD for VL 896
1955 10:53:38.351521 # ok 228 # SKIP SVE set FPSIMD get SVE for VL 896
1956 10:53:38.351640 # ok 229 Set SVE VL 912
1957 10:53:38.351754 # ok 230 # SKIP SVE set SVE get SVE for VL 912
1958 10:53:38.351865 # ok 231 # SKIP SVE set SVE get FPSIMD for VL 912
1959 10:53:38.351999 # ok 232 # SKIP SVE set FPSIMD get SVE for VL 912
1960 10:53:38.359010 # ok 233 Set SVE VL 928
1961 10:53:38.359450 # ok 234 # SKIP SVE set SVE get SVE for VL 928
1962 10:53:38.359634 # ok 235 # SKIP SVE set SVE get FPSIMD for VL 928
1963 10:53:38.359811 # ok 236 # SKIP SVE set FPSIMD get SVE for VL 928
1964 10:53:38.359999 # ok 237 Set SVE VL 944
1965 10:53:38.360221 # ok 238 # SKIP SVE set SVE get SVE for VL 944
1966 10:53:38.360381 # ok 239 # SKIP SVE set SVE get FPSIMD for VL 944
1967 10:53:38.360569 # ok 240 # SKIP SVE set FPSIMD get SVE for VL 944
1968 10:53:38.360758 # ok 241 Set SVE VL 960
1969 10:53:38.360969 # ok 242 # SKIP SVE set SVE get SVE for VL 960
1970 10:53:38.361147 # ok 243 # SKIP SVE set SVE get FPSIMD for VL 960
1971 10:53:38.361300 # ok 244 # SKIP SVE set FPSIMD get SVE for VL 960
1972 10:53:38.361457 # ok 245 Set SVE VL 976
1973 10:53:38.361625 # ok 246 # SKIP SVE set SVE get SVE for VL 976
1974 10:53:38.361901 # ok 247 # SKIP SVE set SVE get FPSIMD for VL 976
1975 10:53:38.362109 # ok 248 # SKIP SVE set FPSIMD get SVE for VL 976
1976 10:53:38.362329 # ok 249 Set SVE VL 992
1977 10:53:38.362548 # ok 250 # SKIP SVE set SVE get SVE for VL 992
1978 10:53:38.362743 # ok 251 # SKIP SVE set SVE get FPSIMD for VL 992
1979 10:53:38.362935 # ok 252 # SKIP SVE set FPSIMD get SVE for VL 992
1980 10:53:38.363091 # ok 253 Set SVE VL 1008
1981 10:53:38.363259 # ok 254 # SKIP SVE set SVE get SVE for VL 1008
1982 10:53:38.363430 # ok 255 # SKIP SVE set SVE get FPSIMD for VL 1008
1983 10:53:38.363598 # ok 256 # SKIP SVE set FPSIMD get SVE for VL 1008
1984 10:53:38.363723 # ok 257 Set SVE VL 1024
1985 10:53:38.363839 # ok 258 # SKIP SVE set SVE get SVE for VL 1024
1986 10:53:38.363957 # ok 259 # SKIP SVE set SVE get FPSIMD for VL 1024
1987 10:53:38.364074 # ok 260 # SKIP SVE set FPSIMD get SVE for VL 1024
1988 10:53:38.364189 # ok 261 Set SVE VL 1040
1989 10:53:38.364303 # ok 262 # SKIP SVE set SVE get SVE for VL 1040
1990 10:53:38.364419 # ok 263 # SKIP SVE set SVE get FPSIMD for VL 1040
1991 10:53:38.364534 # ok 264 # SKIP SVE set FPSIMD get SVE for VL 1040
1992 10:53:38.364650 # ok 265 Set SVE VL 1056
1993 10:53:38.364764 # ok 266 # SKIP SVE set SVE get SVE for VL 1056
1994 10:53:38.364878 # ok 267 # SKIP SVE set SVE get FPSIMD for VL 1056
1995 10:53:38.364994 # ok 268 # SKIP SVE set FPSIMD get SVE for VL 1056
1996 10:53:38.365114 # ok 269 Set SVE VL 1072
1997 10:53:38.365228 # ok 270 # SKIP SVE set SVE get SVE for VL 1072
1998 10:53:38.365343 # ok 271 # SKIP SVE set SVE get FPSIMD for VL 1072
1999 10:53:38.365459 # ok 272 # SKIP SVE set FPSIMD get SVE for VL 1072
2000 10:53:38.365574 # ok 273 Set SVE VL 1088
2001 10:53:38.372217 # ok 274 # SKIP SVE set SVE get SVE for VL 1088
2002 10:53:38.372662 # ok 275 # SKIP SVE set SVE get FPSIMD for VL 1088
2003 10:53:38.372773 # ok 276 # SKIP SVE set FPSIMD get SVE for VL 1088
2004 10:53:38.372872 # ok 277 Set SVE VL 1104
2005 10:53:38.372982 # ok 278 # SKIP SVE set SVE get SVE for VL 1104
2006 10:53:38.373079 # ok 279 # SKIP SVE set SVE get FPSIMD for VL 1104
2007 10:53:38.373176 # ok 280 # SKIP SVE set FPSIMD get SVE for VL 1104
2008 10:53:38.373265 # ok 281 Set SVE VL 1120
2009 10:53:38.373374 # ok 282 # SKIP SVE set SVE get SVE for VL 1120
2010 10:53:38.373480 # ok 283 # SKIP SVE set SVE get FPSIMD for VL 1120
2011 10:53:38.373575 # ok 284 # SKIP SVE set FPSIMD get SVE for VL 1120
2012 10:53:38.373677 # ok 285 Set SVE VL 1136
2013 10:53:38.373785 # ok 286 # SKIP SVE set SVE get SVE for VL 1136
2014 10:53:38.373874 # ok 287 # SKIP SVE set SVE get FPSIMD for VL 1136
2015 10:53:38.373983 # ok 288 # SKIP SVE set FPSIMD get SVE for VL 1136
2016 10:53:38.374074 # ok 289 Set SVE VL 1152
2017 10:53:38.374179 # ok 290 # SKIP SVE set SVE get SVE for VL 1152
2018 10:53:38.374284 # ok 291 # SKIP SVE set SVE get FPSIMD for VL 1152
2019 10:53:38.374389 # ok 292 # SKIP SVE set FPSIMD get SVE for VL 1152
2020 10:53:38.384384 # ok 293 Set SVE VL 1168
2021 10:53:38.384693 # ok 294 # SKIP SVE set SVE get SVE for VL 1168
2022 10:53:38.384869 # ok 295 # SKIP SVE set SVE get FPSIMD for VL 1168
2023 10:53:38.385026 # ok 296 # SKIP SVE set FPSIMD get SVE for VL 1168
2024 10:53:38.385180 # ok 297 Set SVE VL 1184
2025 10:53:38.385337 # ok 298 # SKIP SVE set SVE get SVE for VL 1184
2026 10:53:38.385562 # ok 299 # SKIP SVE set SVE get FPSIMD for VL 1184
2027 10:53:38.385792 # ok 300 # SKIP SVE set FPSIMD get SVE for VL 1184
2028 10:53:38.386009 # ok 301 Set SVE VL 1200
2029 10:53:38.386266 # ok 302 # SKIP SVE set SVE get SVE for VL 1200
2030 10:53:38.386484 # ok 303 # SKIP SVE set SVE get FPSIMD for VL 1200
2031 10:53:38.386688 # ok 304 # SKIP SVE set FPSIMD get SVE for VL 1200
2032 10:53:38.386860 # ok 305 Set SVE VL 1216
2033 10:53:38.387013 # ok 306 # SKIP SVE set SVE get SVE for VL 1216
2034 10:53:38.387233 # ok 307 # SKIP SVE set SVE get FPSIMD for VL 1216
2035 10:53:38.387475 # ok 308 # SKIP SVE set FPSIMD get SVE for VL 1216
2036 10:53:38.387664 # ok 309 Set SVE VL 1232
2037 10:53:38.387867 # ok 310 # SKIP SVE set SVE get SVE for VL 1232
2038 10:53:38.388080 # ok 311 # SKIP SVE set SVE get FPSIMD for VL 1232
2039 10:53:38.388305 # ok 312 # SKIP SVE set FPSIMD get SVE for VL 1232
2040 10:53:38.388537 # ok 313 Set SVE VL 1248
2041 10:53:38.388764 # ok 314 # SKIP SVE set SVE get SVE for VL 1248
2042 10:53:38.388985 # ok 315 # SKIP SVE set SVE get FPSIMD for VL 1248
2043 10:53:38.389209 # ok 316 # SKIP SVE set FPSIMD get SVE for VL 1248
2044 10:53:38.389447 # ok 317 Set SVE VL 1264
2045 10:53:38.389637 # ok 318 # SKIP SVE set SVE get SVE for VL 1264
2046 10:53:38.390439 # ok 319 # SKIP SVE set SVE get FPSIMD for VL 1264
2047 10:53:38.390657 # ok 320 # SKIP SVE set FPSIMD get SVE for VL 1264
2048 10:53:38.390814 # ok 321 Set SVE VL 1280
2049 10:53:38.390982 # ok 322 # SKIP SVE set SVE get SVE for VL 1280
2050 10:53:38.391140 # ok 323 # SKIP SVE set SVE get FPSIMD for VL 1280
2051 10:53:38.391366 # ok 324 # SKIP SVE set FPSIMD get SVE for VL 1280
2052 10:53:38.391586 # ok 325 Set SVE VL 1296
2053 10:53:38.391726 # ok 326 # SKIP SVE set SVE get SVE for VL 1296
2054 10:53:38.391878 # ok 327 # SKIP SVE set SVE get FPSIMD for VL 1296
2055 10:53:38.392003 # ok 328 # SKIP SVE set FPSIMD get SVE for VL 1296
2056 10:53:38.392121 # ok 329 Set SVE VL 1312
2057 10:53:38.392237 # ok 330 # SKIP SVE set SVE get SVE for VL 1312
2058 10:53:38.392353 # ok 331 # SKIP SVE set SVE get FPSIMD for VL 1312
2059 10:53:38.392467 # ok 332 # SKIP SVE set FPSIMD get SVE for VL 1312
2060 10:53:38.392583 # ok 333 Set SVE VL 1328
2061 10:53:38.392699 # ok 334 # SKIP SVE set SVE get SVE for VL 1328
2062 10:53:38.392815 # ok 335 # SKIP SVE set SVE get FPSIMD for VL 1328
2063 10:53:38.392928 # ok 336 # SKIP SVE set FPSIMD get SVE for VL 1328
2064 10:53:38.393263 # ok 337 Set SVE VL 1344
2065 10:53:38.393371 # ok 338 # SKIP SVE set SVE get SVE for VL 1344
2066 10:53:38.393465 # ok 339 # SKIP SVE set SVE get FPSIMD for VL 1344
2067 10:53:38.393555 # ok 340 # SKIP SVE set FPSIMD get SVE for VL 1344
2068 10:53:38.393632 # ok 341 Set SVE VL 1360
2069 10:53:38.393727 # ok 342 # SKIP SVE set SVE get SVE for VL 1360
2070 10:53:38.393819 # ok 343 # SKIP SVE set SVE get FPSIMD for VL 1360
2071 10:53:38.393908 # ok 344 # SKIP SVE set FPSIMD get SVE for VL 1360
2072 10:53:38.393999 # ok 345 Set SVE VL 1376
2073 10:53:38.394088 # ok 346 # SKIP SVE set SVE get SVE for VL 1376
2074 10:53:38.394178 # ok 347 # SKIP SVE set SVE get FPSIMD for VL 1376
2075 10:53:38.394266 # ok 348 # SKIP SVE set FPSIMD get SVE for VL 1376
2076 10:53:38.394356 # ok 349 Set SVE VL 1392
2077 10:53:38.394444 # ok 350 # SKIP SVE set SVE get SVE for VL 1392
2078 10:53:38.394532 # ok 351 # SKIP SVE set SVE get FPSIMD for VL 1392
2079 10:53:38.394622 # ok 352 # SKIP SVE set FPSIMD get SVE for VL 1392
2080 10:53:38.394711 # ok 353 Set SVE VL 1408
2081 10:53:38.394800 # ok 354 # SKIP SVE set SVE get SVE for VL 1408
2082 10:53:38.394888 # ok 355 # SKIP SVE set SVE get FPSIMD for VL 1408
2083 10:53:38.394977 # ok 356 # SKIP SVE set FPSIMD get SVE for VL 1408
2084 10:53:38.395066 # ok 357 Set SVE VL 1424
2085 10:53:38.395164 # ok 358 # SKIP SVE set SVE get SVE for VL 1424
2086 10:53:38.395254 # ok 359 # SKIP SVE set SVE get FPSIMD for VL 1424
2087 10:53:38.395344 # ok 360 # SKIP SVE set FPSIMD get SVE for VL 1424
2088 10:53:38.395427 # ok 361 Set SVE VL 1440
2089 10:53:38.395503 # ok 362 # SKIP SVE set SVE get SVE for VL 1440
2090 10:53:38.395576 # ok 363 # SKIP SVE set SVE get FPSIMD for VL 1440
2091 10:53:38.396383 # ok 364 # SKIP SVE set FPSIMD get SVE for VL 1440
2092 10:53:38.396725 # ok 365 Set SVE VL 1456
2093 10:53:38.396915 # ok 366 # SKIP SVE set SVE get SVE for VL 1456
2094 10:53:38.397130 # ok 367 # SKIP SVE set SVE get FPSIMD for VL 1456
2095 10:53:38.397309 # ok 368 # SKIP SVE set FPSIMD get SVE for VL 1456
2096 10:53:38.397435 # ok 369 Set SVE VL 1472
2097 10:53:38.397584 # ok 370 # SKIP SVE set SVE get SVE for VL 1472
2098 10:53:38.397775 # ok 371 # SKIP SVE set SVE get FPSIMD for VL 1472
2099 10:53:38.397957 # ok 372 # SKIP SVE set FPSIMD get SVE for VL 1472
2100 10:53:38.398167 # ok 373 Set SVE VL 1488
2101 10:53:38.398365 # ok 374 # SKIP SVE set SVE get SVE for VL 1488
2102 10:53:38.398560 # ok 375 # SKIP SVE set SVE get FPSIMD for VL 1488
2103 10:53:38.398777 # ok 376 # SKIP SVE set FPSIMD get SVE for VL 1488
2104 10:53:38.398977 # ok 377 Set SVE VL 1504
2105 10:53:38.399146 # ok 378 # SKIP SVE set SVE get SVE for VL 1504
2106 10:53:38.399318 # ok 379 # SKIP SVE set SVE get FPSIMD for VL 1504
2107 10:53:38.399488 # ok 380 # SKIP SVE set FPSIMD get SVE for VL 1504
2108 10:53:38.399613 # ok 381 Set SVE VL 1520
2109 10:53:38.399727 # ok 382 # SKIP SVE set SVE get SVE for VL 1520
2110 10:53:38.399841 # ok 383 # SKIP SVE set SVE get FPSIMD for VL 1520
2111 10:53:38.399955 # ok 384 # SKIP SVE set FPSIMD get SVE for VL 1520
2112 10:53:38.400070 # ok 385 Set SVE VL 1536
2113 10:53:38.400214 # ok 386 # SKIP SVE set SVE get SVE for VL 1536
2114 10:53:38.400336 # ok 387 # SKIP SVE set SVE get FPSIMD for VL 1536
2115 10:53:38.400451 # ok 388 # SKIP SVE set FPSIMD get SVE for VL 1536
2116 10:53:38.400566 # ok 389 Set SVE VL 1552
2117 10:53:38.404632 # ok 390 # SKIP SVE set SVE get SVE for VL 1552
2118 10:53:38.405308 # ok 391 # SKIP SVE set SVE get FPSIMD for VL 1552
2119 10:53:38.405550 # ok 392 # SKIP SVE set FPSIMD get SVE for VL 1552
2120 10:53:38.405735 # ok 393 Set SVE VL 1568
2121 10:53:38.405950 # ok 394 # SKIP SVE set SVE get SVE for VL 1568
2122 10:53:38.406163 # ok 395 # SKIP SVE set SVE get FPSIMD for VL 1568
2123 10:53:38.406409 # ok 396 # SKIP SVE set FPSIMD get SVE for VL 1568
2124 10:53:38.406610 # ok 397 Set SVE VL 1584
2125 10:53:38.406791 # ok 398 # SKIP SVE set SVE get SVE for VL 1584
2126 10:53:38.406985 # ok 399 # SKIP SVE set SVE get FPSIMD for VL 1584
2127 10:53:38.407517 # ok 400 # SKIP SVE set FPSIMD get SVE for VL 1584
2128 10:53:38.407687 # ok 401 Set SVE VL 1600
2129 10:53:38.407818 # ok 402 # SKIP SVE set SVE get SVE for VL 1600
2130 10:53:38.407937 # ok 403 # SKIP SVE set SVE get FPSIMD for VL 1600
2131 10:53:38.408085 # ok 404 # SKIP SVE set FPSIMD get SVE for VL 1600
2132 10:53:38.408254 # ok 405 Set SVE VL 1616
2133 10:53:38.408386 # ok 406 # SKIP SVE set SVE get SVE for VL 1616
2134 10:53:38.408504 # ok 407 # SKIP SVE set SVE get FPSIMD for VL 1616
2135 10:53:38.408620 # ok 408 # SKIP SVE set FPSIMD get SVE for VL 1616
2136 10:53:38.408738 # ok 409 Set SVE VL 1632
2137 10:53:38.408855 # ok 410 # SKIP SVE set SVE get SVE for VL 1632
2138 10:53:38.408973 # ok 411 # SKIP SVE set SVE get FPSIMD for VL 1632
2139 10:53:38.409088 # ok 412 # SKIP SVE set FPSIMD get SVE for VL 1632
2140 10:53:38.412387 # ok 413 Set SVE VL 1648
2141 10:53:38.412883 # ok 414 # SKIP SVE set SVE get SVE for VL 1648
2142 10:53:38.413086 # ok 415 # SKIP SVE set SVE get FPSIMD for VL 1648
2143 10:53:38.413258 # ok 416 # SKIP SVE set FPSIMD get SVE for VL 1648
2144 10:53:38.413423 # ok 417 Set SVE VL 1664
2145 10:53:38.413623 # ok 418 # SKIP SVE set SVE get SVE for VL 1664
2146 10:53:38.413799 # ok 419 # SKIP SVE set SVE get FPSIMD for VL 1664
2147 10:53:38.413984 # ok 420 # SKIP SVE set FPSIMD get SVE for VL 1664
2148 10:53:38.414205 # ok 421 Set SVE VL 1680
2149 10:53:38.414409 # ok 422 # SKIP SVE set SVE get SVE for VL 1680
2150 10:53:38.414665 # ok 423 # SKIP SVE set SVE get FPSIMD for VL 1680
2151 10:53:38.414888 # ok 424 # SKIP SVE set FPSIMD get SVE for VL 1680
2152 10:53:38.415079 # ok 425 Set SVE VL 1696
2153 10:53:38.415250 # ok 426 # SKIP SVE set SVE get SVE for VL 1696
2154 10:53:38.415425 # ok 427 # SKIP SVE set SVE get FPSIMD for VL 1696
2155 10:53:38.415605 # ok 428 # SKIP SVE set FPSIMD get SVE for VL 1696
2156 10:53:38.415736 # ok 429 Set SVE VL 1712
2157 10:53:38.415851 # ok 430 # SKIP SVE set SVE get SVE for VL 1712
2158 10:53:38.416032 # ok 431 # SKIP SVE set SVE get FPSIMD for VL 1712
2159 10:53:38.416167 # ok 432 # SKIP SVE set FPSIMD get SVE for VL 1712
2160 10:53:38.416286 # ok 433 Set SVE VL 1728
2161 10:53:38.416399 # ok 434 # SKIP SVE set SVE get SVE for VL 1728
2162 10:53:38.416512 # ok 435 # SKIP SVE set SVE get FPSIMD for VL 1728
2163 10:53:38.416625 # ok 436 # SKIP SVE set FPSIMD get SVE for VL 1728
2164 10:53:38.416738 # ok 437 Set SVE VL 1744
2165 10:53:38.420570 # ok 438 # SKIP SVE set SVE get SVE for VL 1744
2166 10:53:38.421031 # ok 439 # SKIP SVE set SVE get FPSIMD for VL 1744
2167 10:53:38.421223 # ok 440 # SKIP SVE set FPSIMD get SVE for VL 1744
2168 10:53:38.421521 # ok 441 Set SVE VL 1760
2169 10:53:38.421691 # ok 442 # SKIP SVE set SVE get SVE for VL 1760
2170 10:53:38.421944 # ok 443 # SKIP SVE set SVE get FPSIMD for VL 1760
2171 10:53:38.422133 # ok 444 # SKIP SVE set FPSIMD get SVE for VL 1760
2172 10:53:38.422294 # ok 445 Set SVE VL 1776
2173 10:53:38.422449 # ok 446 # SKIP SVE set SVE get SVE for VL 1776
2174 10:53:38.422636 # ok 447 # SKIP SVE set SVE get FPSIMD for VL 1776
2175 10:53:38.422807 # ok 448 # SKIP SVE set FPSIMD get SVE for VL 1776
2176 10:53:38.422971 # ok 449 Set SVE VL 1792
2177 10:53:38.423192 # ok 450 # SKIP SVE set SVE get SVE for VL 1792
2178 10:53:38.423375 # ok 451 # SKIP SVE set SVE get FPSIMD for VL 1792
2179 10:53:38.423528 # ok 452 # SKIP SVE set FPSIMD get SVE for VL 1792
2180 10:53:38.423648 # ok 453 Set SVE VL 1808
2181 10:53:38.423762 # ok 454 # SKIP SVE set SVE get SVE for VL 1808
2182 10:53:38.423878 # ok 455 # SKIP SVE set SVE get FPSIMD for VL 1808
2183 10:53:38.423993 # ok 456 # SKIP SVE set FPSIMD get SVE for VL 1808
2184 10:53:38.424107 # ok 457 Set SVE VL 1824
2185 10:53:38.424220 # ok 458 # SKIP SVE set SVE get SVE for VL 1824
2186 10:53:38.424334 # ok 459 # SKIP SVE set SVE get FPSIMD for VL 1824
2187 10:53:38.424478 # ok 460 # SKIP SVE set FPSIMD get SVE for VL 1824
2188 10:53:38.424601 # ok 461 Set SVE VL 1840
2189 10:53:38.428283 # ok 462 # SKIP SVE set SVE get SVE for VL 1840
2190 10:53:38.428732 # ok 463 # SKIP SVE set SVE get FPSIMD for VL 1840
2191 10:53:38.428934 # ok 464 # SKIP SVE set FPSIMD get SVE for VL 1840
2192 10:53:38.429093 # ok 465 Set SVE VL 1856
2193 10:53:38.429333 # ok 466 # SKIP SVE set SVE get SVE for VL 1856
2194 10:53:38.429553 # ok 467 # SKIP SVE set SVE get FPSIMD for VL 1856
2195 10:53:38.429787 # ok 468 # SKIP SVE set FPSIMD get SVE for VL 1856
2196 10:53:38.430004 # ok 469 Set SVE VL 1872
2197 10:53:38.430221 # ok 470 # SKIP SVE set SVE get SVE for VL 1872
2198 10:53:38.430423 # ok 471 # SKIP SVE set SVE get FPSIMD for VL 1872
2199 10:53:38.430622 # ok 472 # SKIP SVE set FPSIMD get SVE for VL 1872
2200 10:53:38.430759 # ok 473 Set SVE VL 1888
2201 10:53:38.430877 # ok 474 # SKIP SVE set SVE get SVE for VL 1888
2202 10:53:38.430994 # ok 475 # SKIP SVE set SVE get FPSIMD for VL 1888
2203 10:53:38.431110 # ok 476 # SKIP SVE set FPSIMD get SVE for VL 1888
2204 10:53:38.431227 # ok 477 Set SVE VL 1904
2205 10:53:38.431371 # ok 478 # SKIP SVE set SVE get SVE for VL 1904
2206 10:53:38.431504 # ok 479 # SKIP SVE set SVE get FPSIMD for VL 1904
2207 10:53:38.444293 # ok 480 # SKIP SVE set FPSIMD get SVE for VL 1904
2208 10:53:38.444510 # ok 481 Set SVE VL 1920
2209 10:53:38.444601 # ok 482 # SKIP SVE set SVE get SVE for VL 1920
2210 10:53:38.444707 # ok 483 # SKIP SVE set SVE get FPSIMD for VL 1920
2211 10:53:38.444796 # ok 484 # SKIP SVE set FPSIMD get SVE for VL 1920
2212 10:53:38.445078 # ok 485 Set SVE VL 1936
2213 10:53:38.445189 # ok 486 # SKIP SVE set SVE get SVE for VL 1936
2214 10:53:38.445282 # ok 487 # SKIP SVE set SVE get FPSIMD for VL 1936
2215 10:53:38.445383 # ok 488 # SKIP SVE set FPSIMD get SVE for VL 1936
2216 10:53:38.445470 # ok 489 Set SVE VL 1952
2217 10:53:38.445775 # ok 490 # SKIP SVE set SVE get SVE for VL 1952
2218 10:53:38.445878 # ok 491 # SKIP SVE set SVE get FPSIMD for VL 1952
2219 10:53:38.445964 # ok 492 # SKIP SVE set FPSIMD get SVE for VL 1952
2220 10:53:38.446049 # ok 493 Set SVE VL 1968
2221 10:53:38.446152 # ok 494 # SKIP SVE set SVE get SVE for VL 1968
2222 10:53:38.446238 # ok 495 # SKIP SVE set SVE get FPSIMD for VL 1968
2223 10:53:38.446344 # ok 496 # SKIP SVE set FPSIMD get SVE for VL 1968
2224 10:53:38.446431 # ok 497 Set SVE VL 1984
2225 10:53:38.446532 # ok 498 # SKIP SVE set SVE get SVE for VL 1984
2226 10:53:38.446634 # ok 499 # SKIP SVE set SVE get FPSIMD for VL 1984
2227 10:53:38.446909 # ok 500 # SKIP SVE set FPSIMD get SVE for VL 1984
2228 10:53:38.447028 # ok 501 Set SVE VL 2000
2229 10:53:38.447133 # ok 502 # SKIP SVE set SVE get SVE for VL 2000
2230 10:53:38.447234 # ok 503 # SKIP SVE set SVE get FPSIMD for VL 2000
2231 10:53:38.447336 # ok 504 # SKIP SVE set FPSIMD get SVE for VL 2000
2232 10:53:38.447520 # ok 505 Set SVE VL 2016
2233 10:53:38.452144 # ok 506 # SKIP SVE set SVE get SVE for VL 2016
2234 10:53:38.452527 # ok 507 # SKIP SVE set SVE get FPSIMD for VL 2016
2235 10:53:38.452636 # ok 508 # SKIP SVE set FPSIMD get SVE for VL 2016
2236 10:53:38.452733 # ok 509 Set SVE VL 2032
2237 10:53:38.452837 # ok 510 # SKIP SVE set SVE get SVE for VL 2032
2238 10:53:38.452926 # ok 511 # SKIP SVE set SVE get FPSIMD for VL 2032
2239 10:53:38.453025 # ok 512 # SKIP SVE set FPSIMD get SVE for VL 2032
2240 10:53:38.453127 # ok 513 Set SVE VL 2048
2241 10:53:38.453230 # ok 514 # SKIP SVE set SVE get SVE for VL 2048
2242 10:53:38.453340 # ok 515 # SKIP SVE set SVE get FPSIMD for VL 2048
2243 10:53:38.453429 # ok 516 # SKIP SVE set FPSIMD get SVE for VL 2048
2244 10:53:38.453530 # ok 517 Set SVE VL 2064
2245 10:53:38.453617 # ok 518 # SKIP SVE set SVE get SVE for VL 2064
2246 10:53:38.453956 # ok 519 # SKIP SVE set SVE get FPSIMD for VL 2064
2247 10:53:38.454063 # ok 520 # SKIP SVE set FPSIMD get SVE for VL 2064
2248 10:53:38.454152 # ok 521 Set SVE VL 2080
2249 10:53:38.454258 # ok 522 # SKIP SVE set SVE get SVE for VL 2080
2250 10:53:38.454347 # ok 523 # SKIP SVE set SVE get FPSIMD for VL 2080
2251 10:53:38.454449 # ok 524 # SKIP SVE set FPSIMD get SVE for VL 2080
2252 10:53:38.454538 # ok 525 Set SVE VL 2096
2253 10:53:38.454638 # ok 526 # SKIP SVE set SVE get SVE for VL 2096
2254 10:53:38.454936 # ok 527 # SKIP SVE set SVE get FPSIMD for VL 2096
2255 10:53:38.455051 # ok 528 # SKIP SVE set FPSIMD get SVE for VL 2096
2256 10:53:38.455155 # ok 529 Set SVE VL 2112
2257 10:53:38.455241 # ok 530 # SKIP SVE set SVE get SVE for VL 2112
2258 10:53:38.455341 # ok 531 # SKIP SVE set SVE get FPSIMD for VL 2112
2259 10:53:38.455443 # ok 532 # SKIP SVE set FPSIMD get SVE for VL 2112
2260 10:53:38.455545 # ok 533 Set SVE VL 2128
2261 10:53:38.460324 # ok 534 # SKIP SVE set SVE get SVE for VL 2128
2262 10:53:38.460803 # ok 535 # SKIP SVE set SVE get FPSIMD for VL 2128
2263 10:53:38.461037 # ok 536 # SKIP SVE set FPSIMD get SVE for VL 2128
2264 10:53:38.461248 # ok 537 Set SVE VL 2144
2265 10:53:38.461434 # ok 538 # SKIP SVE set SVE get SVE for VL 2144
2266 10:53:38.461636 # ok 539 # SKIP SVE set SVE get FPSIMD for VL 2144
2267 10:53:38.461819 # ok 540 # SKIP SVE set FPSIMD get SVE for VL 2144
2268 10:53:38.461974 # ok 541 Set SVE VL 2160
2269 10:53:38.462103 # ok 542 # SKIP SVE set SVE get SVE for VL 2160
2270 10:53:38.462247 # ok 543 # SKIP SVE set SVE get FPSIMD for VL 2160
2271 10:53:38.462404 # ok 544 # SKIP SVE set FPSIMD get SVE for VL 2160
2272 10:53:38.462581 # ok 545 Set SVE VL 2176
2273 10:53:38.462737 # ok 546 # SKIP SVE set SVE get SVE for VL 2176
2274 10:53:38.462883 # ok 547 # SKIP SVE set SVE get FPSIMD for VL 2176
2275 10:53:38.463035 # ok 548 # SKIP SVE set FPSIMD get SVE for VL 2176
2276 10:53:38.463190 # ok 549 Set SVE VL 2192
2277 10:53:38.463344 # ok 550 # SKIP SVE set SVE get SVE for VL 2192
2278 10:53:38.463528 # ok 551 # SKIP SVE set SVE get FPSIMD for VL 2192
2279 10:53:38.463666 # ok 552 # SKIP SVE set FPSIMD get SVE for VL 2192
2280 10:53:38.463785 # ok 553 Set SVE VL 2208
2281 10:53:38.463923 # ok 554 # SKIP SVE set SVE get SVE for VL 2208
2282 10:53:38.464067 # ok 555 # SKIP SVE set SVE get FPSIMD for VL 2208
2283 10:53:38.464218 # ok 556 # SKIP SVE set FPSIMD get SVE for VL 2208
2284 10:53:38.464345 # ok 557 Set SVE VL 2224
2285 10:53:38.464464 # ok 558 # SKIP SVE set SVE get SVE for VL 2224
2286 10:53:38.464580 # ok 559 # SKIP SVE set SVE get FPSIMD for VL 2224
2287 10:53:38.464697 # ok 560 # SKIP SVE set FPSIMD get SVE for VL 2224
2288 10:53:38.464811 # ok 561 Set SVE VL 2240
2289 10:53:38.464925 # ok 562 # SKIP SVE set SVE get SVE for VL 2240
2290 10:53:38.465039 # ok 563 # SKIP SVE set SVE get FPSIMD for VL 2240
2291 10:53:38.465154 # ok 564 # SKIP SVE set FPSIMD get SVE for VL 2240
2292 10:53:38.465271 # ok 565 Set SVE VL 2256
2293 10:53:38.468136 # ok 566 # SKIP SVE set SVE get SVE for VL 2256
2294 10:53:38.468535 # ok 567 # SKIP SVE set SVE get FPSIMD for VL 2256
2295 10:53:38.468637 # ok 568 # SKIP SVE set FPSIMD get SVE for VL 2256
2296 10:53:38.468718 # ok 569 Set SVE VL 2272
2297 10:53:38.468808 # ok 570 # SKIP SVE set SVE get SVE for VL 2272
2298 10:53:38.468885 # ok 571 # SKIP SVE set SVE get FPSIMD for VL 2272
2299 10:53:38.468959 # ok 572 # SKIP SVE set FPSIMD get SVE for VL 2272
2300 10:53:38.469033 # ok 573 Set SVE VL 2288
2301 10:53:38.469120 # ok 574 # SKIP SVE set SVE get SVE for VL 2288
2302 10:53:38.469196 # ok 575 # SKIP SVE set SVE get FPSIMD for VL 2288
2303 10:53:38.469270 # ok 576 # SKIP SVE set FPSIMD get SVE for VL 2288
2304 10:53:38.469343 # ok 577 Set SVE VL 2304
2305 10:53:38.469438 # ok 578 # SKIP SVE set SVE get SVE for VL 2304
2306 10:53:38.469514 # ok 579 # SKIP SVE set SVE get FPSIMD for VL 2304
2307 10:53:38.469588 # ok 580 # SKIP SVE set FPSIMD get SVE for VL 2304
2308 10:53:38.469668 # ok 581 Set SVE VL 2320
2309 10:53:38.469758 # ok 582 # SKIP SVE set SVE get SVE for VL 2320
2310 10:53:38.469835 # ok 583 # SKIP SVE set SVE get FPSIMD for VL 2320
2311 10:53:38.469922 # ok 584 # SKIP SVE set FPSIMD get SVE for VL 2320
2312 10:53:38.469999 # ok 585 Set SVE VL 2336
2313 10:53:38.470085 # ok 586 # SKIP SVE set SVE get SVE for VL 2336
2314 10:53:38.470161 # ok 587 # SKIP SVE set SVE get FPSIMD for VL 2336
2315 10:53:38.470248 # ok 588 # SKIP SVE set FPSIMD get SVE for VL 2336
2316 10:53:38.470324 # ok 589 Set SVE VL 2352
2317 10:53:38.470413 # ok 590 # SKIP SVE set SVE get SVE for VL 2352
2318 10:53:38.470842 # ok 591 # SKIP SVE set SVE get FPSIMD for VL 2352
2319 10:53:38.470943 # ok 592 # SKIP SVE set FPSIMD get SVE for VL 2352
2320 10:53:38.471021 # ok 593 Set SVE VL 2368
2321 10:53:38.471111 # ok 594 # SKIP SVE set SVE get SVE for VL 2368
2322 10:53:38.471189 # ok 595 # SKIP SVE set SVE get FPSIMD for VL 2368
2323 10:53:38.471276 # ok 596 # SKIP SVE set FPSIMD get SVE for VL 2368
2324 10:53:38.471352 # ok 597 Set SVE VL 2384
2325 10:53:38.471446 # ok 598 # SKIP SVE set SVE get SVE for VL 2384
2326 10:53:38.471533 # ok 599 # SKIP SVE set SVE get FPSIMD for VL 2384
2327 10:53:38.476327 # ok 600 # SKIP SVE set FPSIMD get SVE for VL 2384
2328 10:53:38.476624 # ok 601 Set SVE VL 2400
2329 10:53:38.476721 # ok 602 # SKIP SVE set SVE get SVE for VL 2400
2330 10:53:38.476812 # ok 603 # SKIP SVE set SVE get FPSIMD for VL 2400
2331 10:53:38.476890 # ok 604 # SKIP SVE set FPSIMD get SVE for VL 2400
2332 10:53:38.476978 # ok 605 Set SVE VL 2416
2333 10:53:38.477069 # ok 606 # SKIP SVE set SVE get SVE for VL 2416
2334 10:53:38.477358 # ok 607 # SKIP SVE set SVE get FPSIMD for VL 2416
2335 10:53:38.477577 # ok 608 # SKIP SVE set FPSIMD get SVE for VL 2416
2336 10:53:38.477692 # ok 609 Set SVE VL 2432
2337 10:53:38.477803 # ok 610 # SKIP SVE set SVE get SVE for VL 2432
2338 10:53:38.477895 # ok 611 # SKIP SVE set SVE get FPSIMD for VL 2432
2339 10:53:38.477994 # ok 612 # SKIP SVE set FPSIMD get SVE for VL 2432
2340 10:53:38.478079 # ok 613 Set SVE VL 2448
2341 10:53:38.478173 # ok 614 # SKIP SVE set SVE get SVE for VL 2448
2342 10:53:38.478271 # ok 615 # SKIP SVE set SVE get FPSIMD for VL 2448
2343 10:53:38.478369 # ok 616 # SKIP SVE set FPSIMD get SVE for VL 2448
2344 10:53:38.478463 # ok 617 Set SVE VL 2464
2345 10:53:38.478564 # ok 618 # SKIP SVE set SVE get SVE for VL 2464
2346 10:53:38.478665 # ok 619 # SKIP SVE set SVE get FPSIMD for VL 2464
2347 10:53:38.478971 # ok 620 # SKIP SVE set FPSIMD get SVE for VL 2464
2348 10:53:38.479077 # ok 621 Set SVE VL 2480
2349 10:53:38.479183 # ok 622 # SKIP SVE set SVE get SVE for VL 2480
2350 10:53:38.479273 # ok 623 # SKIP SVE set SVE get FPSIMD for VL 2480
2351 10:53:38.479384 # ok 624 # SKIP SVE set FPSIMD get SVE for VL 2480
2352 10:53:38.479485 # ok 625 Set SVE VL 2496
2353 10:53:38.484108 # ok 626 # SKIP SVE set SVE get SVE for VL 2496
2354 10:53:38.484512 # ok 627 # SKIP SVE set SVE get FPSIMD for VL 2496
2355 10:53:38.484672 # ok 628 # SKIP SVE set FPSIMD get SVE for VL 2496
2356 10:53:38.484826 # ok 629 Set SVE VL 2512
2357 10:53:38.484979 # ok 630 # SKIP SVE set SVE get SVE for VL 2512
2358 10:53:38.485104 # ok 631 # SKIP SVE set SVE get FPSIMD for VL 2512
2359 10:53:38.485251 # ok 632 # SKIP SVE set FPSIMD get SVE for VL 2512
2360 10:53:38.485447 # ok 633 Set SVE VL 2528
2361 10:53:38.485612 # ok 634 # SKIP SVE set SVE get SVE for VL 2528
2362 10:53:38.485762 # ok 635 # SKIP SVE set SVE get FPSIMD for VL 2528
2363 10:53:38.485896 # ok 636 # SKIP SVE set FPSIMD get SVE for VL 2528
2364 10:53:38.486053 # ok 637 Set SVE VL 2544
2365 10:53:38.486193 # ok 638 # SKIP SVE set SVE get SVE for VL 2544
2366 10:53:38.486324 # ok 639 # SKIP SVE set SVE get FPSIMD for VL 2544
2367 10:53:38.486457 # ok 640 # SKIP SVE set FPSIMD get SVE for VL 2544
2368 10:53:38.486612 # ok 641 Set SVE VL 2560
2369 10:53:38.486791 # ok 642 # SKIP SVE set SVE get SVE for VL 2560
2370 10:53:38.486929 # ok 643 # SKIP SVE set SVE get FPSIMD for VL 2560
2371 10:53:38.487069 # ok 644 # SKIP SVE set FPSIMD get SVE for VL 2560
2372 10:53:38.487204 # ok 645 Set SVE VL 2576
2373 10:53:38.487330 # ok 646 # SKIP SVE set SVE get SVE for VL 2576
2374 10:53:38.487498 # ok 647 # SKIP SVE set SVE get FPSIMD for VL 2576
2375 10:53:38.487640 # ok 648 # SKIP SVE set FPSIMD get SVE for VL 2576
2376 10:53:38.487759 # ok 649 Set SVE VL 2592
2377 10:53:38.487875 # ok 650 # SKIP SVE set SVE get SVE for VL 2592
2378 10:53:38.487990 # ok 651 # SKIP SVE set SVE get FPSIMD for VL 2592
2379 10:53:38.488106 # ok 652 # SKIP SVE set FPSIMD get SVE for VL 2592
2380 10:53:38.488245 # ok 653 Set SVE VL 2608
2381 10:53:38.488772 # ok 654 # SKIP SVE set SVE get SVE for VL 2608
2382 10:53:38.489166 # ok 655 # SKIP SVE set SVE get FPSIMD for VL 2608
2383 10:53:38.489273 # ok 656 # SKIP SVE set FPSIMD get SVE for VL 2608
2384 10:53:38.489364 # ok 657 Set SVE VL 2624
2385 10:53:38.489470 # ok 658 # SKIP SVE set SVE get SVE for VL 2624
2386 10:53:38.489560 # ok 659 # SKIP SVE set SVE get FPSIMD for VL 2624
2387 10:53:38.489669 # ok 660 # SKIP SVE set FPSIMD get SVE for VL 2624
2388 10:53:38.490327 # ok 661 Set SVE VL 2640
2389 10:53:38.490455 # ok 662 # SKIP SVE set SVE get SVE for VL 2640
2390 10:53:38.490549 # ok 663 # SKIP SVE set SVE get FPSIMD for VL 2640
2391 10:53:38.490629 # ok 664 # SKIP SVE set FPSIMD get SVE for VL 2640
2392 10:53:38.490719 # ok 665 Set SVE VL 2656
2393 10:53:38.490803 # ok 666 # SKIP SVE set SVE get SVE for VL 2656
2394 10:53:38.508440 # ok 667 # SKIP SVE set SVE get FPSIMD for VL 2656
2395 10:53:38.508669 # ok 668 # SKIP SVE set FPSIMD get SVE for VL 2656
2396 10:53:38.509101 # ok 669 Set SVE VL 2672
2397 10:53:38.509205 # ok 670 # SKIP SVE set SVE get SVE for VL 2672
2398 10:53:38.509289 # ok 671 # SKIP SVE set SVE get FPSIMD for VL 2672
2399 10:53:38.509367 # ok 672 # SKIP SVE set FPSIMD get SVE for VL 2672
2400 10:53:38.509443 # ok 673 Set SVE VL 2688
2401 10:53:38.509519 # ok 674 # SKIP SVE set SVE get SVE for VL 2688
2402 10:53:38.509610 # ok 675 # SKIP SVE set SVE get FPSIMD for VL 2688
2403 10:53:38.509696 # ok 676 # SKIP SVE set FPSIMD get SVE for VL 2688
2404 10:53:38.509773 # ok 677 Set SVE VL 2704
2405 10:53:38.509848 # ok 678 # SKIP SVE set SVE get SVE for VL 2704
2406 10:53:38.509941 # ok 679 # SKIP SVE set SVE get FPSIMD for VL 2704
2407 10:53:38.510028 # ok 680 # SKIP SVE set FPSIMD get SVE for VL 2704
2408 10:53:38.510114 # ok 681 Set SVE VL 2720
2409 10:53:38.510215 # ok 682 # SKIP SVE set SVE get SVE for VL 2720
2410 10:53:38.510318 # ok 683 # SKIP SVE set SVE get FPSIMD for VL 2720
2411 10:53:38.510413 # ok 684 # SKIP SVE set FPSIMD get SVE for VL 2720
2412 10:53:38.510494 # ok 685 Set SVE VL 2736
2413 10:53:38.510585 # ok 686 # SKIP SVE set SVE get SVE for VL 2736
2414 10:53:38.510663 # ok 687 # SKIP SVE set SVE get FPSIMD for VL 2736
2415 10:53:38.510752 # ok 688 # SKIP SVE set FPSIMD get SVE for VL 2736
2416 10:53:38.510830 # ok 689 Set SVE VL 2752
2417 10:53:38.510918 # ok 690 # SKIP SVE set SVE get SVE for VL 2752
2418 10:53:38.511351 # ok 691 # SKIP SVE set SVE get FPSIMD for VL 2752
2419 10:53:38.511452 # ok 692 # SKIP SVE set FPSIMD get SVE for VL 2752
2420 10:53:38.511531 # ok 693 Set SVE VL 2768
2421 10:53:38.511607 # ok 694 # SKIP SVE set SVE get SVE for VL 2768
2422 10:53:38.511696 # ok 695 # SKIP SVE set SVE get FPSIMD for VL 2768
2423 10:53:38.511775 # ok 696 # SKIP SVE set FPSIMD get SVE for VL 2768
2424 10:53:38.514448 # ok 697 Set SVE VL 2784
2425 10:53:38.514751 # ok 698 # SKIP SVE set SVE get SVE for VL 2784
2426 10:53:38.514866 # ok 699 # SKIP SVE set SVE get FPSIMD for VL 2784
2427 10:53:38.514964 # ok 700 # SKIP SVE set FPSIMD get SVE for VL 2784
2428 10:53:38.515046 # ok 701 Set SVE VL 2800
2429 10:53:38.515136 # ok 702 # SKIP SVE set SVE get SVE for VL 2800
2430 10:53:38.515229 # ok 703 # SKIP SVE set SVE get FPSIMD for VL 2800
2431 10:53:38.515518 # ok 704 # SKIP SVE set FPSIMD get SVE for VL 2800
2432 10:53:38.515623 # ok 705 Set SVE VL 2816
2433 10:53:38.515727 # ok 706 # SKIP SVE set SVE get SVE for VL 2816
2434 10:53:38.515827 # ok 707 # SKIP SVE set SVE get FPSIMD for VL 2816
2435 10:53:38.516597 # ok 708 # SKIP SVE set FPSIMD get SVE for VL 2816
2436 10:53:38.516703 # ok 709 Set SVE VL 2832
2437 10:53:38.516792 # ok 710 # SKIP SVE set SVE get SVE for VL 2832
2438 10:53:38.516895 # ok 711 # SKIP SVE set SVE get FPSIMD for VL 2832
2439 10:53:38.516981 # ok 712 # SKIP SVE set FPSIMD get SVE for VL 2832
2440 10:53:38.517077 # ok 713 Set SVE VL 2848
2441 10:53:38.517169 # ok 714 # SKIP SVE set SVE get SVE for VL 2848
2442 10:53:38.517461 # ok 715 # SKIP SVE set SVE get FPSIMD for VL 2848
2443 10:53:38.517564 # ok 716 # SKIP SVE set FPSIMD get SVE for VL 2848
2444 10:53:38.517684 # ok 717 Set SVE VL 2864
2445 10:53:38.517775 # ok 718 # SKIP SVE set SVE get SVE for VL 2864
2446 10:53:38.517877 # ok 719 # SKIP SVE set SVE get FPSIMD for VL 2864
2447 10:53:38.517964 # ok 720 # SKIP SVE set FPSIMD get SVE for VL 2864
2448 10:53:38.518065 # ok 721 Set SVE VL 2880
2449 10:53:38.518154 # ok 722 # SKIP SVE set SVE get SVE for VL 2880
2450 10:53:38.518254 # ok 723 # SKIP SVE set SVE get FPSIMD for VL 2880
2451 10:53:38.518552 # ok 724 # SKIP SVE set FPSIMD get SVE for VL 2880
2452 10:53:38.518659 # ok 725 Set SVE VL 2896
2453 10:53:38.518758 # ok 726 # SKIP SVE set SVE get SVE for VL 2896
2454 10:53:38.518841 # ok 727 # SKIP SVE set SVE get FPSIMD for VL 2896
2455 10:53:38.518932 # ok 728 # SKIP SVE set FPSIMD get SVE for VL 2896
2456 10:53:38.519214 # ok 729 Set SVE VL 2912
2457 10:53:38.519344 # ok 730 # SKIP SVE set SVE get SVE for VL 2912
2458 10:53:38.519456 # ok 731 # SKIP SVE set SVE get FPSIMD for VL 2912
2459 10:53:38.519743 # ok 732 # SKIP SVE set FPSIMD get SVE for VL 2912
2460 10:53:38.519848 # ok 733 Set SVE VL 2928
2461 10:53:38.519944 # ok 734 # SKIP SVE set SVE get SVE for VL 2928
2462 10:53:38.520262 # ok 735 # SKIP SVE set SVE get FPSIMD for VL 2928
2463 10:53:38.520366 # ok 736 # SKIP SVE set FPSIMD get SVE for VL 2928
2464 10:53:38.520450 # ok 737 Set SVE VL 2944
2465 10:53:38.520547 # ok 738 # SKIP SVE set SVE get SVE for VL 2944
2466 10:53:38.520629 # ok 739 # SKIP SVE set SVE get FPSIMD for VL 2944
2467 10:53:38.520834 # ok 740 # SKIP SVE set FPSIMD get SVE for VL 2944
2468 10:53:38.520938 # ok 741 Set SVE VL 2960
2469 10:53:38.521020 # ok 742 # SKIP SVE set SVE get SVE for VL 2960
2470 10:53:38.521122 # ok 743 # SKIP SVE set SVE get FPSIMD for VL 2960
2471 10:53:38.521205 # ok 744 # SKIP SVE set FPSIMD get SVE for VL 2960
2472 10:53:38.521298 # ok 745 Set SVE VL 2976
2473 10:53:38.521381 # ok 746 # SKIP SVE set SVE get SVE for VL 2976
2474 10:53:38.521472 # ok 747 # SKIP SVE set SVE get FPSIMD for VL 2976
2475 10:53:38.521781 # ok 748 # SKIP SVE set FPSIMD get SVE for VL 2976
2476 10:53:38.521885 # ok 749 Set SVE VL 2992
2477 10:53:38.521980 # ok 750 # SKIP SVE set SVE get SVE for VL 2992
2478 10:53:38.522074 # ok 751 # SKIP SVE set SVE get FPSIMD for VL 2992
2479 10:53:38.522153 # ok 752 # SKIP SVE set FPSIMD get SVE for VL 2992
2480 10:53:38.522245 # ok 753 Set SVE VL 3008
2481 10:53:38.522341 # ok 754 # SKIP SVE set SVE get SVE for VL 3008
2482 10:53:38.522434 # ok 755 # SKIP SVE set SVE get FPSIMD for VL 3008
2483 10:53:38.522716 # ok 756 # SKIP SVE set FPSIMD get SVE for VL 3008
2484 10:53:38.522831 # ok 757 Set SVE VL 3024
2485 10:53:38.522914 # ok 758 # SKIP SVE set SVE get SVE for VL 3024
2486 10:53:38.523011 # ok 759 # SKIP SVE set SVE get FPSIMD for VL 3024
2487 10:53:38.523340 # ok 760 # SKIP SVE set FPSIMD get SVE for VL 3024
2488 10:53:38.523547 # ok 761 Set SVE VL 3040
2489 10:53:38.523700 # ok 762 # SKIP SVE set SVE get SVE for VL 3040
2490 10:53:38.523880 # ok 763 # SKIP SVE set SVE get FPSIMD for VL 3040
2491 10:53:38.524044 # ok 764 # SKIP SVE set FPSIMD get SVE for VL 3040
2492 10:53:38.524189 # ok 765 Set SVE VL 3056
2493 10:53:38.524345 # ok 766 # SKIP SVE set SVE get SVE for VL 3056
2494 10:53:38.524510 # ok 767 # SKIP SVE set SVE get FPSIMD for VL 3056
2495 10:53:38.524673 # ok 768 # SKIP SVE set FPSIMD get SVE for VL 3056
2496 10:53:38.524850 # ok 769 Set SVE VL 3072
2497 10:53:38.525026 # ok 770 # SKIP SVE set SVE get SVE for VL 3072
2498 10:53:38.525182 # ok 771 # SKIP SVE set SVE get FPSIMD for VL 3072
2499 10:53:38.525337 # ok 772 # SKIP SVE set FPSIMD get SVE for VL 3072
2500 10:53:38.525488 # ok 773 Set SVE VL 3088
2501 10:53:38.525675 # ok 774 # SKIP SVE set SVE get SVE for VL 3088
2502 10:53:38.525881 # ok 775 # SKIP SVE set SVE get FPSIMD for VL 3088
2503 10:53:38.526052 # ok 776 # SKIP SVE set FPSIMD get SVE for VL 3088
2504 10:53:38.526218 # ok 777 Set SVE VL 3104
2505 10:53:38.526372 # ok 778 # SKIP SVE set SVE get SVE for VL 3104
2506 10:53:38.526514 # ok 779 # SKIP SVE set SVE get FPSIMD for VL 3104
2507 10:53:38.526680 # ok 780 # SKIP SVE set FPSIMD get SVE for VL 3104
2508 10:53:38.526842 # ok 781 Set SVE VL 3120
2509 10:53:38.526989 # ok 782 # SKIP SVE set SVE get SVE for VL 3120
2510 10:53:38.527145 # ok 783 # SKIP SVE set SVE get FPSIMD for VL 3120
2511 10:53:38.527303 # ok 784 # SKIP SVE set FPSIMD get SVE for VL 3120
2512 10:53:38.527469 # ok 785 Set SVE VL 3136
2513 10:53:38.527609 # ok 786 # SKIP SVE set SVE get SVE for VL 3136
2514 10:53:38.527740 # ok 787 # SKIP SVE set SVE get FPSIMD for VL 3136
2515 10:53:38.527925 # ok 788 # SKIP SVE set FPSIMD get SVE for VL 3136
2516 10:53:38.528084 # ok 789 Set SVE VL 3152
2517 10:53:38.528241 # ok 790 # SKIP SVE set SVE get SVE for VL 3152
2518 10:53:38.528393 # ok 791 # SKIP SVE set SVE get FPSIMD for VL 3152
2519 10:53:38.528542 # ok 792 # SKIP SVE set FPSIMD get SVE for VL 3152
2520 10:53:38.528688 # ok 793 Set SVE VL 3168
2521 10:53:38.528836 # ok 794 # SKIP SVE set SVE get SVE for VL 3168
2522 10:53:38.528996 # ok 795 # SKIP SVE set SVE get FPSIMD for VL 3168
2523 10:53:38.529188 # ok 796 # SKIP SVE set FPSIMD get SVE for VL 3168
2524 10:53:38.529347 # ok 797 Set SVE VL 3184
2525 10:53:38.529505 # ok 798 # SKIP SVE set SVE get SVE for VL 3184
2526 10:53:38.530101 # ok 799 # SKIP SVE set SVE get FPSIMD for VL 3184
2527 10:53:38.530302 # ok 800 # SKIP SVE set FPSIMD get SVE for VL 3184
2528 10:53:38.530482 # ok 801 Set SVE VL 3200
2529 10:53:38.530710 # ok 802 # SKIP SVE set SVE get SVE for VL 3200
2530 10:53:38.530930 # ok 803 # SKIP SVE set SVE get FPSIMD for VL 3200
2531 10:53:38.531398 # ok 804 # SKIP SVE set FPSIMD get SVE for VL 3200
2532 10:53:38.531583 # ok 805 Set SVE VL 3216
2533 10:53:38.531745 # ok 806 # SKIP SVE set SVE get SVE for VL 3216
2534 10:53:38.531944 # ok 807 # SKIP SVE set SVE get FPSIMD for VL 3216
2535 10:53:38.532148 # ok 808 # SKIP SVE set FPSIMD get SVE for VL 3216
2536 10:53:38.532312 # ok 809 Set SVE VL 3232
2537 10:53:38.532502 # ok 810 # SKIP SVE set SVE get SVE for VL 3232
2538 10:53:38.532707 # ok 811 # SKIP SVE set SVE get FPSIMD for VL 3232
2539 10:53:38.532935 # ok 812 # SKIP SVE set FPSIMD get SVE for VL 3232
2540 10:53:38.533161 # ok 813 Set SVE VL 3248
2541 10:53:38.533362 # ok 814 # SKIP SVE set SVE get SVE for VL 3248
2542 10:53:38.533579 # ok 815 # SKIP SVE set SVE get FPSIMD for VL 3248
2543 10:53:38.533805 # ok 816 # SKIP SVE set FPSIMD get SVE for VL 3248
2544 10:53:38.534036 # ok 817 Set SVE VL 3264
2545 10:53:38.534243 # ok 818 # SKIP SVE set SVE get SVE for VL 3264
2546 10:53:38.534447 # ok 819 # SKIP SVE set SVE get FPSIMD for VL 3264
2547 10:53:38.534674 # ok 820 # SKIP SVE set FPSIMD get SVE for VL 3264
2548 10:53:38.534883 # ok 821 Set SVE VL 3280
2549 10:53:38.535057 # ok 822 # SKIP SVE set SVE get SVE for VL 3280
2550 10:53:38.535206 # ok 823 # SKIP SVE set SVE get FPSIMD for VL 3280
2551 10:53:38.535351 # ok 824 # SKIP SVE set FPSIMD get SVE for VL 3280
2552 10:53:38.535544 # ok 825 Set SVE VL 3296
2553 10:53:38.535679 # ok 826 # SKIP SVE set SVE get SVE for VL 3296
2554 10:53:38.535823 # ok 827 # SKIP SVE set SVE get FPSIMD for VL 3296
2555 10:53:38.535966 # ok 828 # SKIP SVE set FPSIMD get SVE for VL 3296
2556 10:53:38.536109 # ok 829 Set SVE VL 3312
2557 10:53:38.536252 # ok 830 # SKIP SVE set SVE get SVE for VL 3312
2558 10:53:38.536394 # ok 831 # SKIP SVE set SVE get FPSIMD for VL 3312
2559 10:53:38.536536 # ok 832 # SKIP SVE set FPSIMD get SVE for VL 3312
2560 10:53:38.536678 # ok 833 Set SVE VL 3328
2561 10:53:38.536819 # ok 834 # SKIP SVE set SVE get SVE for VL 3328
2562 10:53:38.536962 # ok 835 # SKIP SVE set SVE get FPSIMD for VL 3328
2563 10:53:38.537104 # ok 836 # SKIP SVE set FPSIMD get SVE for VL 3328
2564 10:53:38.537247 # ok 837 Set SVE VL 3344
2565 10:53:38.537394 # ok 838 # SKIP SVE set SVE get SVE for VL 3344
2566 10:53:38.537536 # ok 839 # SKIP SVE set SVE get FPSIMD for VL 3344
2567 10:53:38.537688 # ok 840 # SKIP SVE set FPSIMD get SVE for VL 3344
2568 10:53:38.537833 # ok 841 Set SVE VL 3360
2569 10:53:38.537974 # ok 842 # SKIP SVE set SVE get SVE for VL 3360
2570 10:53:38.538116 # ok 843 # SKIP SVE set SVE get FPSIMD for VL 3360
2571 10:53:38.538258 # ok 844 # SKIP SVE set FPSIMD get SVE for VL 3360
2572 10:53:38.538400 # ok 845 Set SVE VL 3376
2573 10:53:38.538541 # ok 846 # SKIP SVE set SVE get SVE for VL 3376
2574 10:53:38.538683 # ok 847 # SKIP SVE set SVE get FPSIMD for VL 3376
2575 10:53:38.539043 # ok 848 # SKIP SVE set FPSIMD get SVE for VL 3376
2576 10:53:38.539181 # ok 849 Set SVE VL 3392
2577 10:53:38.539326 # ok 850 # SKIP SVE set SVE get SVE for VL 3392
2578 10:53:38.539470 # ok 851 # SKIP SVE set SVE get FPSIMD for VL 3392
2579 10:53:38.539612 # ok 852 # SKIP SVE set FPSIMD get SVE for VL 3392
2580 10:53:38.539753 # ok 853 Set SVE VL 3408
2581 10:53:38.539895 # ok 854 # SKIP SVE set SVE get SVE for VL 3408
2582 10:53:38.548200 # ok 855 # SKIP SVE set SVE get FPSIMD for VL 3408
2583 10:53:38.548598 # ok 856 # SKIP SVE set FPSIMD get SVE for VL 3408
2584 10:53:38.548702 # ok 857 Set SVE VL 3424
2585 10:53:38.553887 # ok 858 # SKIP SVE set SVE get SVE for VL 3424
2586 10:53:38.554012 # ok 859 # SKIP SVE set SVE get FPSIMD for VL 3424
2587 10:53:38.554128 # ok 860 # SKIP SVE set FPSIMD get SVE for VL 3424
2588 10:53:38.554249 # ok 861 Set SVE VL 3440
2589 10:53:38.554367 # ok 862 # SKIP SVE set SVE get SVE for VL 3440
2590 10:53:38.554483 # ok 863 # SKIP SVE set SVE get FPSIMD for VL 3440
2591 10:53:38.554606 # ok 864 # SKIP SVE set FPSIMD get SVE for VL 3440
2592 10:53:38.554727 # ok 865 Set SVE VL 3456
2593 10:53:38.554852 # ok 866 # SKIP SVE set SVE get SVE for VL 3456
2594 10:53:38.554950 # ok 867 # SKIP SVE set SVE get FPSIMD for VL 3456
2595 10:53:38.555050 # ok 868 # SKIP SVE set FPSIMD get SVE for VL 3456
2596 10:53:38.555206 # ok 869 Set SVE VL 3472
2597 10:53:38.555335 # ok 870 # SKIP SVE set SVE get SVE for VL 3472
2598 10:53:38.555459 # ok 871 # SKIP SVE set SVE get FPSIMD for VL 3472
2599 10:53:38.555580 # ok 872 # SKIP SVE set FPSIMD get SVE for VL 3472
2600 10:53:38.555692 # ok 873 Set SVE VL 3488
2601 10:53:38.555812 # ok 874 # SKIP SVE set SVE get SVE for VL 3488
2602 10:53:38.555933 # ok 875 # SKIP SVE set SVE get FPSIMD for VL 3488
2603 10:53:38.556057 # ok 876 # SKIP SVE set FPSIMD get SVE for VL 3488
2604 10:53:38.556180 # ok 877 Set SVE VL 3504
2605 10:53:38.556303 # ok 878 # SKIP SVE set SVE get SVE for VL 3504
2606 10:53:38.556417 # ok 879 # SKIP SVE set SVE get FPSIMD for VL 3504
2607 10:53:38.556536 # ok 880 # SKIP SVE set FPSIMD get SVE for VL 3504
2608 10:53:38.556657 # ok 881 Set SVE VL 3520
2609 10:53:38.556778 # ok 882 # SKIP SVE set SVE get SVE for VL 3520
2610 10:53:38.556901 # ok 883 # SKIP SVE set SVE get FPSIMD for VL 3520
2611 10:53:38.557022 # ok 884 # SKIP SVE set FPSIMD get SVE for VL 3520
2612 10:53:38.557143 # ok 885 Set SVE VL 3536
2613 10:53:38.557261 # ok 886 # SKIP SVE set SVE get SVE for VL 3536
2614 10:53:38.557376 # ok 887 # SKIP SVE set SVE get FPSIMD for VL 3536
2615 10:53:38.557490 # ok 888 # SKIP SVE set FPSIMD get SVE for VL 3536
2616 10:53:38.557609 # ok 889 Set SVE VL 3552
2617 10:53:38.557748 # ok 890 # SKIP SVE set SVE get SVE for VL 3552
2618 10:53:38.557871 # ok 891 # SKIP SVE set SVE get FPSIMD for VL 3552
2619 10:53:38.557999 # ok 892 # SKIP SVE set FPSIMD get SVE for VL 3552
2620 10:53:38.558130 # ok 893 Set SVE VL 3568
2621 10:53:38.558245 # ok 894 # SKIP SVE set SVE get SVE for VL 3568
2622 10:53:38.558363 # ok 895 # SKIP SVE set SVE get FPSIMD for VL 3568
2623 10:53:38.558517 # ok 896 # SKIP SVE set FPSIMD get SVE for VL 3568
2624 10:53:38.558654 # ok 897 Set SVE VL 3584
2625 10:53:38.558776 # ok 898 # SKIP SVE set SVE get SVE for VL 3584
2626 10:53:38.558898 # ok 899 # SKIP SVE set SVE get FPSIMD for VL 3584
2627 10:53:38.559320 # ok 900 # SKIP SVE set FPSIMD get SVE for VL 3584
2628 10:53:38.559552 # ok 901 Set SVE VL 3600
2629 10:53:38.559672 # ok 902 # SKIP SVE set SVE get SVE for VL 3600
2630 10:53:38.559793 # ok 903 # SKIP SVE set SVE get FPSIMD for VL 3600
2631 10:53:38.559912 # ok 904 # SKIP SVE set FPSIMD get SVE for VL 3600
2632 10:53:38.560028 # ok 905 Set SVE VL 3616
2633 10:53:38.560144 # ok 906 # SKIP SVE set SVE get SVE for VL 3616
2634 10:53:38.560255 # ok 907 # SKIP SVE set SVE get FPSIMD for VL 3616
2635 10:53:38.560369 # ok 908 # SKIP SVE set FPSIMD get SVE for VL 3616
2636 10:53:38.560484 # ok 909 Set SVE VL 3632
2637 10:53:38.560599 # ok 910 # SKIP SVE set SVE get SVE for VL 3632
2638 10:53:38.560714 # ok 911 # SKIP SVE set SVE get FPSIMD for VL 3632
2639 10:53:38.560827 # ok 912 # SKIP SVE set FPSIMD get SVE for VL 3632
2640 10:53:38.560939 # ok 913 Set SVE VL 3648
2641 10:53:38.561051 # ok 914 # SKIP SVE set SVE get SVE for VL 3648
2642 10:53:38.561162 # ok 915 # SKIP SVE set SVE get FPSIMD for VL 3648
2643 10:53:38.561274 # ok 916 # SKIP SVE set FPSIMD get SVE for VL 3648
2644 10:53:38.561388 # ok 917 Set SVE VL 3664
2645 10:53:38.561508 # ok 918 # SKIP SVE set SVE get SVE for VL 3664
2646 10:53:38.561620 # ok 919 # SKIP SVE set SVE get FPSIMD for VL 3664
2647 10:53:38.561745 # ok 920 # SKIP SVE set FPSIMD get SVE for VL 3664
2648 10:53:38.561859 # ok 921 Set SVE VL 3680
2649 10:53:38.561973 # ok 922 # SKIP SVE set SVE get SVE for VL 3680
2650 10:53:38.562091 # ok 923 # SKIP SVE set SVE get FPSIMD for VL 3680
2651 10:53:38.562206 # ok 924 # SKIP SVE set FPSIMD get SVE for VL 3680
2652 10:53:38.562320 # ok 925 Set SVE VL 3696
2653 10:53:38.562433 # ok 926 # SKIP SVE set SVE get SVE for VL 3696
2654 10:53:38.562546 # ok 927 # SKIP SVE set SVE get FPSIMD for VL 3696
2655 10:53:38.562660 # ok 928 # SKIP SVE set FPSIMD get SVE for VL 3696
2656 10:53:38.562779 # ok 929 Set SVE VL 3712
2657 10:53:38.562894 # ok 930 # SKIP SVE set SVE get SVE for VL 3712
2658 10:53:38.563009 # ok 931 # SKIP SVE set SVE get FPSIMD for VL 3712
2659 10:53:38.563123 # ok 932 # SKIP SVE set FPSIMD get SVE for VL 3712
2660 10:53:38.563238 # ok 933 Set SVE VL 3728
2661 10:53:38.563353 # ok 934 # SKIP SVE set SVE get SVE for VL 3728
2662 10:53:38.563471 # ok 935 # SKIP SVE set SVE get FPSIMD for VL 3728
2663 10:53:38.563609 # ok 936 # SKIP SVE set FPSIMD get SVE for VL 3728
2664 10:53:38.563742 # ok 937 Set SVE VL 3744
2665 10:53:38.563852 # ok 938 # SKIP SVE set SVE get SVE for VL 3744
2666 10:53:38.563962 # ok 939 # SKIP SVE set SVE get FPSIMD for VL 3744
2667 10:53:38.564073 # ok 940 # SKIP SVE set FPSIMD get SVE for VL 3744
2668 10:53:38.564186 # ok 941 Set SVE VL 3760
2669 10:53:38.564299 # ok 942 # SKIP SVE set SVE get SVE for VL 3760
2670 10:53:38.564433 # ok 943 # SKIP SVE set SVE get FPSIMD for VL 3760
2671 10:53:38.564823 # ok 944 # SKIP SVE set FPSIMD get SVE for VL 3760
2672 10:53:38.565031 # ok 945 Set SVE VL 3776
2673 10:53:38.565215 # ok 946 # SKIP SVE set SVE get SVE for VL 3776
2674 10:53:38.565413 # ok 947 # SKIP SVE set SVE get FPSIMD for VL 3776
2675 10:53:38.565601 # ok 948 # SKIP SVE set FPSIMD get SVE for VL 3776
2676 10:53:38.565800 # ok 949 Set SVE VL 3792
2677 10:53:38.566003 # ok 950 # SKIP SVE set SVE get SVE for VL 3792
2678 10:53:38.566195 # ok 951 # SKIP SVE set SVE get FPSIMD for VL 3792
2679 10:53:38.566440 # ok 952 # SKIP SVE set FPSIMD get SVE for VL 3792
2680 10:53:38.566640 # ok 953 Set SVE VL 3808
2681 10:53:38.566848 # ok 954 # SKIP SVE set SVE get SVE for VL 3808
2682 10:53:38.567022 # ok 955 # SKIP SVE set SVE get FPSIMD for VL 3808
2683 10:53:38.567178 # ok 956 # SKIP SVE set FPSIMD get SVE for VL 3808
2684 10:53:38.567331 # ok 957 Set SVE VL 3824
2685 10:53:38.567487 # ok 958 # SKIP SVE set SVE get SVE for VL 3824
2686 10:53:38.567649 # ok 959 # SKIP SVE set SVE get FPSIMD for VL 3824
2687 10:53:38.567817 # ok 960 # SKIP SVE set FPSIMD get SVE for VL 3824
2688 10:53:38.567964 # ok 961 Set SVE VL 3840
2689 10:53:38.568092 # ok 962 # SKIP SVE set SVE get SVE for VL 3840
2690 10:53:38.568210 # ok 963 # SKIP SVE set SVE get FPSIMD for VL 3840
2691 10:53:38.568346 # ok 964 # SKIP SVE set FPSIMD get SVE for VL 3840
2692 10:53:38.568495 # ok 965 Set SVE VL 3856
2693 10:53:38.568642 # ok 966 # SKIP SVE set SVE get SVE for VL 3856
2694 10:53:38.568766 # ok 967 # SKIP SVE set SVE get FPSIMD for VL 3856
2695 10:53:38.568910 # ok 968 # SKIP SVE set FPSIMD get SVE for VL 3856
2696 10:53:38.569037 # ok 969 Set SVE VL 3872
2697 10:53:38.569156 # ok 970 # SKIP SVE set SVE get SVE for VL 3872
2698 10:53:38.569280 # ok 971 # SKIP SVE set SVE get FPSIMD for VL 3872
2699 10:53:38.569400 # ok 972 # SKIP SVE set FPSIMD get SVE for VL 3872
2700 10:53:38.569521 # ok 973 Set SVE VL 3888
2701 10:53:38.569684 # ok 974 # SKIP SVE set SVE get SVE for VL 3888
2702 10:53:38.569840 # ok 975 # SKIP SVE set SVE get FPSIMD for VL 3888
2703 10:53:38.569966 # ok 976 # SKIP SVE set FPSIMD get SVE for VL 3888
2704 10:53:38.570096 # ok 977 Set SVE VL 3904
2705 10:53:38.570224 # ok 978 # SKIP SVE set SVE get SVE for VL 3904
2706 10:53:38.570370 # ok 979 # SKIP SVE set SVE get FPSIMD for VL 3904
2707 10:53:38.570534 # ok 980 # SKIP SVE set FPSIMD get SVE for VL 3904
2708 10:53:38.570677 # ok 981 Set SVE VL 3920
2709 10:53:38.570800 # ok 982 # SKIP SVE set SVE get SVE for VL 3920
2710 10:53:38.570936 # ok 983 # SKIP SVE set SVE get FPSIMD for VL 3920
2711 10:53:38.571083 # ok 984 # SKIP SVE set FPSIMD get SVE for VL 3920
2712 10:53:38.571222 # ok 985 Set SVE VL 3936
2713 10:53:38.571343 # ok 986 # SKIP SVE set SVE get SVE for VL 3936
2714 10:53:38.571705 # ok 987 # SKIP SVE set SVE get FPSIMD for VL 3936
2715 10:53:38.571831 # ok 988 # SKIP SVE set FPSIMD get SVE for VL 3936
2716 10:53:38.571947 # ok 989 Set SVE VL 3952
2717 10:53:38.572061 # ok 990 # SKIP SVE set SVE get SVE for VL 3952
2718 10:53:38.572174 # ok 991 # SKIP SVE set SVE get FPSIMD for VL 3952
2719 10:53:38.572286 # ok 992 # SKIP SVE set FPSIMD get SVE for VL 3952
2720 10:53:38.572401 # ok 993 Set SVE VL 3968
2721 10:53:38.572513 # ok 994 # SKIP SVE set SVE get SVE for VL 3968
2722 10:53:38.572626 # ok 995 # SKIP SVE set SVE get FPSIMD for VL 3968
2723 10:53:38.572766 # ok 996 # SKIP SVE set FPSIMD get SVE for VL 3968
2724 10:53:38.572959 # ok 997 Set SVE VL 3984
2725 10:53:38.573092 # ok 998 # SKIP SVE set SVE get SVE for VL 3984
2726 10:53:38.573269 # ok 999 # SKIP SVE set SVE get FPSIMD for VL 3984
2727 10:53:38.573454 # ok 1000 # SKIP SVE set FPSIMD get SVE for VL 3984
2728 10:53:38.573583 # ok 1001 Set SVE VL 4000
2729 10:53:38.573713 # ok 1002 # SKIP SVE set SVE get SVE for VL 4000
2730 10:53:38.573829 # ok 1003 # SKIP SVE set SVE get FPSIMD for VL 4000
2731 10:53:38.573941 # ok 1004 # SKIP SVE set FPSIMD get SVE for VL 4000
2732 10:53:38.574054 # ok 1005 Set SVE VL 4016
2733 10:53:38.574166 # ok 1006 # SKIP SVE set SVE get SVE for VL 4016
2734 10:53:38.574278 # ok 1007 # SKIP SVE set SVE get FPSIMD for VL 4016
2735 10:53:38.574391 # ok 1008 # SKIP SVE set FPSIMD get SVE for VL 4016
2736 10:53:38.574502 # ok 1009 Set SVE VL 4032
2737 10:53:38.574614 # ok 1010 # SKIP SVE set SVE get SVE for VL 4032
2738 10:53:38.574786 # ok 1011 # SKIP SVE set SVE get FPSIMD for VL 4032
2739 10:53:38.574963 # ok 1012 # SKIP SVE set FPSIMD get SVE for VL 4032
2740 10:53:38.575135 # ok 1013 Set SVE VL 4048
2741 10:53:38.575315 # ok 1014 # SKIP SVE set SVE get SVE for VL 4048
2742 10:53:38.575502 # ok 1015 # SKIP SVE set SVE get FPSIMD for VL 4048
2743 10:53:38.575683 # ok 1016 # SKIP SVE set FPSIMD get SVE for VL 4048
2744 10:53:38.575872 # ok 1017 Set SVE VL 4064
2745 10:53:38.576056 # ok 1018 # SKIP SVE set SVE get SVE for VL 4064
2746 10:53:38.576237 # ok 1019 # SKIP SVE set SVE get FPSIMD for VL 4064
2747 10:53:38.576423 # ok 1020 # SKIP SVE set FPSIMD get SVE for VL 4064
2748 10:53:38.576608 # ok 1021 Set SVE VL 4080
2749 10:53:38.576782 # ok 1022 # SKIP SVE set SVE get SVE for VL 4080
2750 10:53:38.576924 # ok 1023 # SKIP SVE set SVE get FPSIMD for VL 4080
2751 10:53:38.577072 # ok 1024 # SKIP SVE set FPSIMD get SVE for VL 4080
2752 10:53:38.577206 # ok 1025 Set SVE VL 4096
2753 10:53:38.577338 # ok 1026 # SKIP SVE set SVE get SVE for VL 4096
2754 10:53:38.577475 # ok 1027 # SKIP SVE set SVE get FPSIMD for VL 4096
2755 10:53:38.577610 # ok 1028 # SKIP SVE set FPSIMD get SVE for VL 4096
2756 10:53:38.577778 # ok 1029 Set SVE VL 4112
2757 10:53:38.577914 # ok 1030 # SKIP SVE set SVE get SVE for VL 4112
2758 10:53:38.578286 # ok 1031 # SKIP SVE set SVE get FPSIMD for VL 4112
2759 10:53:38.578439 # ok 1032 # SKIP SVE set FPSIMD get SVE for VL 4112
2760 10:53:38.578587 # ok 1033 Set SVE VL 4128
2761 10:53:38.578731 # ok 1034 # SKIP SVE set SVE get SVE for VL 4128
2762 10:53:38.578879 # ok 1035 # SKIP SVE set SVE get FPSIMD for VL 4128
2763 10:53:38.579024 # ok 1036 # SKIP SVE set FPSIMD get SVE for VL 4128
2764 10:53:38.579173 # ok 1037 Set SVE VL 4144
2765 10:53:38.579319 # ok 1038 # SKIP SVE set SVE get SVE for VL 4144
2766 10:53:38.579466 # ok 1039 # SKIP SVE set SVE get FPSIMD for VL 4144
2767 10:53:38.579612 # ok 1040 # SKIP SVE set FPSIMD get SVE for VL 4144
2768 10:53:38.581244 # ok 1041 Set SVE VL 4160
2769 10:53:38.581498 # ok 1042 # SKIP SVE set SVE get SVE for VL 4160
2770 10:53:38.581919 # ok 1043 # SKIP SVE set SVE get FPSIMD for VL 4160
2771 10:53:38.582098 # ok 1044 # SKIP SVE set FPSIMD get SVE for VL 4160
2772 10:53:38.582262 # ok 1045 Set SVE VL 4176
2773 10:53:38.582425 # ok 1046 # SKIP SVE set SVE get SVE for VL 4176
2774 10:53:38.582586 # ok 1047 # SKIP SVE set SVE get FPSIMD for VL 4176
2775 10:53:38.582779 # ok 1048 # SKIP SVE set FPSIMD get SVE for VL 4176
2776 10:53:38.582945 # ok 1049 Set SVE VL 4192
2777 10:53:38.583104 # ok 1050 # SKIP SVE set SVE get SVE for VL 4192
2778 10:53:38.583266 # ok 1051 # SKIP SVE set SVE get FPSIMD for VL 4192
2779 10:53:38.583427 # ok 1052 # SKIP SVE set FPSIMD get SVE for VL 4192
2780 10:53:38.583591 # ok 1053 Set SVE VL 4208
2781 10:53:38.583751 # ok 1054 # SKIP SVE set SVE get SVE for VL 4208
2782 10:53:38.583910 # ok 1055 # SKIP SVE set SVE get FPSIMD for VL 4208
2783 10:53:38.584103 # ok 1056 # SKIP SVE set FPSIMD get SVE for VL 4208
2784 10:53:38.584270 # ok 1057 Set SVE VL 4224
2785 10:53:38.584431 # ok 1058 # SKIP SVE set SVE get SVE for VL 4224
2786 10:53:38.584592 # ok 1059 # SKIP SVE set SVE get FPSIMD for VL 4224
2787 10:53:38.584751 # ok 1060 # SKIP SVE set FPSIMD get SVE for VL 4224
2788 10:53:38.584910 # ok 1061 Set SVE VL 4240
2789 10:53:38.585069 # ok 1062 # SKIP SVE set SVE get SVE for VL 4240
2790 10:53:38.585229 # ok 1063 # SKIP SVE set SVE get FPSIMD for VL 4240
2791 10:53:38.585424 # ok 1064 # SKIP SVE set FPSIMD get SVE for VL 4240
2792 10:53:38.585590 # ok 1065 Set SVE VL 4256
2793 10:53:38.585763 # ok 1066 # SKIP SVE set SVE get SVE for VL 4256
2794 10:53:38.585924 # ok 1067 # SKIP SVE set SVE get FPSIMD for VL 4256
2795 10:53:38.586083 # ok 1068 # SKIP SVE set FPSIMD get SVE for VL 4256
2796 10:53:38.586242 # ok 1069 Set SVE VL 4272
2797 10:53:38.586400 # ok 1070 # SKIP SVE set SVE get SVE for VL 4272
2798 10:53:38.586561 # ok 1071 # SKIP SVE set SVE get FPSIMD for VL 4272
2799 10:53:38.586720 # ok 1072 # SKIP SVE set FPSIMD get SVE for VL 4272
2800 10:53:38.586883 # ok 1073 Set SVE VL 4288
2801 10:53:38.587079 # ok 1074 # SKIP SVE set SVE get SVE for VL 4288
2802 10:53:38.587245 # ok 1075 # SKIP SVE set SVE get FPSIMD for VL 4288
2803 10:53:38.587407 # ok 1076 # SKIP SVE set FPSIMD get SVE for VL 4288
2804 10:53:38.587567 # ok 1077 Set SVE VL 4304
2805 10:53:38.587727 # ok 1078 # SKIP SVE set SVE get SVE for VL 4304
2806 10:53:38.587887 # ok 1079 # SKIP SVE set SVE get FPSIMD for VL 4304
2807 10:53:38.588046 # ok 1080 # SKIP SVE set FPSIMD get SVE for VL 4304
2808 10:53:38.588205 # ok 1081 Set SVE VL 4320
2809 10:53:38.588364 # ok 1082 # SKIP SVE set SVE get SVE for VL 4320
2810 10:53:38.588524 # ok 1083 # SKIP SVE set SVE get FPSIMD for VL 4320
2811 10:53:38.588684 # ok 1084 # SKIP SVE set FPSIMD get SVE for VL 4320
2812 10:53:38.588843 # ok 1085 Set SVE VL 4336
2813 10:53:38.589235 # ok 1086 # SKIP SVE set SVE get SVE for VL 4336
2814 10:53:38.589406 # ok 1087 # SKIP SVE set SVE get FPSIMD for VL 4336
2815 10:53:38.589569 # ok 1088 # SKIP SVE set FPSIMD get SVE for VL 4336
2816 10:53:38.589743 # ok 1089 Set SVE VL 4352
2817 10:53:38.589905 # ok 1090 # SKIP SVE set SVE get SVE for VL 4352
2818 10:53:38.590066 # ok 1091 # SKIP SVE set SVE get FPSIMD for VL 4352
2819 10:53:38.590227 # ok 1092 # SKIP SVE set FPSIMD get SVE for VL 4352
2820 10:53:38.590386 # ok 1093 Set SVE VL 4368
2821 10:53:38.590546 # ok 1094 # SKIP SVE set SVE get SVE for VL 4368
2822 10:53:38.590706 # ok 1095 # SKIP SVE set SVE get FPSIMD for VL 4368
2823 10:53:38.590865 # ok 1096 # SKIP SVE set FPSIMD get SVE for VL 4368
2824 10:53:38.591024 # ok 1097 Set SVE VL 4384
2825 10:53:38.591184 # ok 1098 # SKIP SVE set SVE get SVE for VL 4384
2826 10:53:38.591344 # ok 1099 # SKIP SVE set SVE get FPSIMD for VL 4384
2827 10:53:38.591550 # ok 1100 # SKIP SVE set FPSIMD get SVE for VL 4384
2828 10:53:38.591716 # ok 1101 Set SVE VL 4400
2829 10:53:38.591877 # ok 1102 # SKIP SVE set SVE get SVE for VL 4400
2830 10:53:38.592038 # ok 1103 # SKIP SVE set SVE get FPSIMD for VL 4400
2831 10:53:38.592198 # ok 1104 # SKIP SVE set FPSIMD get SVE for VL 4400
2832 10:53:38.592359 # ok 1105 Set SVE VL 4416
2833 10:53:38.592536 # ok 1106 # SKIP SVE set SVE get SVE for VL 4416
2834 10:53:38.592699 # ok 1107 # SKIP SVE set SVE get FPSIMD for VL 4416
2835 10:53:38.592861 # ok 1108 # SKIP SVE set FPSIMD get SVE for VL 4416
2836 10:53:38.593021 # ok 1109 Set SVE VL 4432
2837 10:53:38.593167 # ok 1110 # SKIP SVE set SVE get SVE for VL 4432
2838 10:53:38.593314 # ok 1111 # SKIP SVE set SVE get FPSIMD for VL 4432
2839 10:53:38.593474 # ok 1112 # SKIP SVE set FPSIMD get SVE for VL 4432
2840 10:53:38.593642 # ok 1113 Set SVE VL 4448
2841 10:53:38.593803 # ok 1114 # SKIP SVE set SVE get SVE for VL 4448
2842 10:53:38.593955 # ok 1115 # SKIP SVE set SVE get FPSIMD for VL 4448
2843 10:53:38.594110 # ok 1116 # SKIP SVE set FPSIMD get SVE for VL 4448
2844 10:53:38.594263 # ok 1117 Set SVE VL 4464
2845 10:53:38.594418 # ok 1118 # SKIP SVE set SVE get SVE for VL 4464
2846 10:53:38.594630 # ok 1119 # SKIP SVE set SVE get FPSIMD for VL 4464
2847 10:53:38.594816 # ok 1120 # SKIP SVE set FPSIMD get SVE for VL 4464
2848 10:53:38.594972 # ok 1121 Set SVE VL 4480
2849 10:53:38.595147 # ok 1122 # SKIP SVE set SVE get SVE for VL 4480
2850 10:53:38.595323 # ok 1123 # SKIP SVE set SVE get FPSIMD for VL 4480
2851 10:53:38.595500 # ok 1124 # SKIP SVE set FPSIMD get SVE for VL 4480
2852 10:53:38.595658 # ok 1125 Set SVE VL 4496
2853 10:53:38.595823 # ok 1126 # SKIP SVE set SVE get SVE for VL 4496
2854 10:53:38.596000 # ok 1127 # SKIP SVE set SVE get FPSIMD for VL 4496
2855 10:53:38.596175 # ok 1128 # SKIP SVE set FPSIMD get SVE for VL 4496
2856 10:53:38.596603 # ok 1129 Set SVE VL 4512
2857 10:53:38.596790 # ok 1130 # SKIP SVE set SVE get SVE for VL 4512
2858 10:53:38.596969 # ok 1131 # SKIP SVE set SVE get FPSIMD for VL 4512
2859 10:53:38.597145 # ok 1132 # SKIP SVE set FPSIMD get SVE for VL 4512
2860 10:53:38.597319 # ok 1133 Set SVE VL 4528
2861 10:53:38.597487 # ok 1134 # SKIP SVE set SVE get SVE for VL 4528
2862 10:53:38.597673 # ok 1135 # SKIP SVE set SVE get FPSIMD for VL 4528
2863 10:53:38.597850 # ok 1136 # SKIP SVE set FPSIMD get SVE for VL 4528
2864 10:53:38.598024 # ok 1137 Set SVE VL 4544
2865 10:53:38.598197 # ok 1138 # SKIP SVE set SVE get SVE for VL 4544
2866 10:53:38.598368 # ok 1139 # SKIP SVE set SVE get FPSIMD for VL 4544
2867 10:53:38.598546 # ok 1140 # SKIP SVE set FPSIMD get SVE for VL 4544
2868 10:53:38.598722 # ok 1141 Set SVE VL 4560
2869 10:53:38.598896 # ok 1142 # SKIP SVE set SVE get SVE for VL 4560
2870 10:53:38.599072 # ok 1143 # SKIP SVE set SVE get FPSIMD for VL 4560
2871 10:53:38.599241 # ok 1144 # SKIP SVE set FPSIMD get SVE for VL 4560
2872 10:53:38.599417 # ok 1145 Set SVE VL 4576
2873 10:53:38.599590 # ok 1146 # SKIP SVE set SVE get SVE for VL 4576
2874 10:53:38.599762 # ok 1147 # SKIP SVE set SVE get FPSIMD for VL 4576
2875 10:53:38.600040 # ok 1148 # SKIP SVE set FPSIMD get SVE for VL 4576
2876 10:53:38.600205 # ok 1149 Set SVE VL 4592
2877 10:53:38.600361 # ok 1150 # SKIP SVE set SVE get SVE for VL 4592
2878 10:53:38.600513 # ok 1151 # SKIP SVE set SVE get FPSIMD for VL 4592
2879 10:53:38.600672 # ok 1152 # SKIP SVE set FPSIMD get SVE for VL 4592
2880 10:53:38.600847 # ok 1153 Set SVE VL 4608
2881 10:53:38.601019 # ok 1154 # SKIP SVE set SVE get SVE for VL 4608
2882 10:53:38.601174 # ok 1155 # SKIP SVE set SVE get FPSIMD for VL 4608
2883 10:53:38.601343 # ok 1156 # SKIP SVE set FPSIMD get SVE for VL 4608
2884 10:53:38.601558 # ok 1157 Set SVE VL 4624
2885 10:53:38.601749 # ok 1158 # SKIP SVE set SVE get SVE for VL 4624
2886 10:53:38.601927 # ok 1159 # SKIP SVE set SVE get FPSIMD for VL 4624
2887 10:53:38.602102 # ok 1160 # SKIP SVE set FPSIMD get SVE for VL 4624
2888 10:53:38.602278 # ok 1161 Set SVE VL 4640
2889 10:53:38.602452 # ok 1162 # SKIP SVE set SVE get SVE for VL 4640
2890 10:53:38.602606 # ok 1163 # SKIP SVE set SVE get FPSIMD for VL 4640
2891 10:53:38.602738 # ok 1164 # SKIP SVE set FPSIMD get SVE for VL 4640
2892 10:53:38.602871 # ok 1165 Set SVE VL 4656
2893 10:53:38.603003 # ok 1166 # SKIP SVE set SVE get SVE for VL 4656
2894 10:53:38.603132 # ok 1167 # SKIP SVE set SVE get FPSIMD for VL 4656
2895 10:53:38.603261 # ok 1168 # SKIP SVE set FPSIMD get SVE for VL 4656
2896 10:53:38.603393 # ok 1169 Set SVE VL 4672
2897 10:53:38.603525 # ok 1170 # SKIP SVE set SVE get SVE for VL 4672
2898 10:53:38.603658 # ok 1171 # SKIP SVE set SVE get FPSIMD for VL 4672
2899 10:53:38.604018 # ok 1172 # SKIP SVE set FPSIMD get SVE for VL 4672
2900 10:53:38.604159 # ok 1173 Set SVE VL 4688
2901 10:53:38.604290 # ok 1174 # SKIP SVE set SVE get SVE for VL 4688
2902 10:53:38.604422 # ok 1175 # SKIP SVE set SVE get FPSIMD for VL 4688
2903 10:53:38.604540 # ok 1176 # SKIP SVE set FPSIMD get SVE for VL 4688
2904 10:53:38.604630 # ok 1177 Set SVE VL 4704
2905 10:53:38.604720 # ok 1178 # SKIP SVE set SVE get SVE for VL 4704
2906 10:53:38.604809 # ok 1179 # SKIP SVE set SVE get FPSIMD for VL 4704
2907 10:53:38.604899 # ok 1180 # SKIP SVE set FPSIMD get SVE for VL 4704
2908 10:53:38.604991 # ok 1181 Set SVE VL 4720
2909 10:53:38.605080 # ok 1182 # SKIP SVE set SVE get SVE for VL 4720
2910 10:53:38.605164 # ok 1183 # SKIP SVE set SVE get FPSIMD for VL 4720
2911 10:53:38.605248 # ok 1184 # SKIP SVE set FPSIMD get SVE for VL 4720
2912 10:53:38.605336 # ok 1185 Set SVE VL 4736
2913 10:53:38.605425 # ok 1186 # SKIP SVE set SVE get SVE for VL 4736
2914 10:53:38.605516 # ok 1187 # SKIP SVE set SVE get FPSIMD for VL 4736
2915 10:53:38.605609 # ok 1188 # SKIP SVE set FPSIMD get SVE for VL 4736
2916 10:53:38.605709 # ok 1189 Set SVE VL 4752
2917 10:53:38.605797 # ok 1190 # SKIP SVE set SVE get SVE for VL 4752
2918 10:53:38.605888 # ok 1191 # SKIP SVE set SVE get FPSIMD for VL 4752
2919 10:53:38.605978 # ok 1192 # SKIP SVE set FPSIMD get SVE for VL 4752
2920 10:53:38.606068 # ok 1193 Set SVE VL 4768
2921 10:53:38.606156 # ok 1194 # SKIP SVE set SVE get SVE for VL 4768
2922 10:53:38.606246 # ok 1195 # SKIP SVE set SVE get FPSIMD for VL 4768
2923 10:53:38.606336 # ok 1196 # SKIP SVE set FPSIMD get SVE for VL 4768
2924 10:53:38.606425 # ok 1197 Set SVE VL 4784
2925 10:53:38.606515 # ok 1198 # SKIP SVE set SVE get SVE for VL 4784
2926 10:53:38.606603 # ok 1199 # SKIP SVE set SVE get FPSIMD for VL 4784
2927 10:53:38.606693 # ok 1200 # SKIP SVE set FPSIMD get SVE for VL 4784
2928 10:53:38.606782 # ok 1201 Set SVE VL 4800
2929 10:53:38.606872 # ok 1202 # SKIP SVE set SVE get SVE for VL 4800
2930 10:53:38.606959 # ok 1203 # SKIP SVE set SVE get FPSIMD for VL 4800
2931 10:53:38.607049 # ok 1204 # SKIP SVE set FPSIMD get SVE for VL 4800
2932 10:53:38.607138 # ok 1205 Set SVE VL 4816
2933 10:53:38.607247 # ok 1206 # SKIP SVE set SVE get SVE for VL 4816
2934 10:53:38.607338 # ok 1207 # SKIP SVE set SVE get FPSIMD for VL 4816
2935 10:53:38.607419 # ok 1208 # SKIP SVE set FPSIMD get SVE for VL 4816
2936 10:53:38.607500 # ok 1209 Set SVE VL 4832
2937 10:53:38.607580 # ok 1210 # SKIP SVE set SVE get SVE for VL 4832
2938 10:53:38.607660 # ok 1211 # SKIP SVE set SVE get FPSIMD for VL 4832
2939 10:53:38.607730 # ok 1212 # SKIP SVE set FPSIMD get SVE for VL 4832
2940 10:53:38.607819 # ok 1213 Set SVE VL 4848
2941 10:53:38.607908 # ok 1214 # SKIP SVE set SVE get SVE for VL 4848
2942 10:53:38.608195 # ok 1215 # SKIP SVE set SVE get FPSIMD for VL 4848
2943 10:53:38.608281 # ok 1216 # SKIP SVE set FPSIMD get SVE for VL 4848
2944 10:53:38.608373 # ok 1217 Set SVE VL 4864
2945 10:53:38.608463 # ok 1218 # SKIP SVE set SVE get SVE for VL 4864
2946 10:53:38.608557 # ok 1219 # SKIP SVE set SVE get FPSIMD for VL 4864
2947 10:53:38.608646 # ok 1220 # SKIP SVE set FPSIMD get SVE for VL 4864
2948 10:53:38.608736 # ok 1221 Set SVE VL 4880
2949 10:53:38.608827 # ok 1222 # SKIP SVE set SVE get SVE for VL 4880
2950 10:53:38.608915 # ok 1223 # SKIP SVE set SVE get FPSIMD for VL 4880
2951 10:53:38.616890 # ok 1224 # SKIP SVE set FPSIMD get SVE for VL 4880
2952 10:53:38.617016 # ok 1225 Set SVE VL 4896
2953 10:53:38.617130 # ok 1226 # SKIP SVE set SVE get SVE for VL 4896
2954 10:53:38.617227 # ok 1227 # SKIP SVE set SVE get FPSIMD for VL 4896
2955 10:53:38.617338 # ok 1228 # SKIP SVE set FPSIMD get SVE for VL 4896
2956 10:53:38.617434 # ok 1229 Set SVE VL 4912
2957 10:53:38.617544 # ok 1230 # SKIP SVE set SVE get SVE for VL 4912
2958 10:53:38.617640 # ok 1231 # SKIP SVE set SVE get FPSIMD for VL 4912
2959 10:53:38.617759 # ok 1232 # SKIP SVE set FPSIMD get SVE for VL 4912
2960 10:53:38.617855 # ok 1233 Set SVE VL 4928
2961 10:53:38.617949 # ok 1234 # SKIP SVE set SVE get SVE for VL 4928
2962 10:53:38.618060 # ok 1235 # SKIP SVE set SVE get FPSIMD for VL 4928
2963 10:53:38.618155 # ok 1236 # SKIP SVE set FPSIMD get SVE for VL 4928
2964 10:53:38.618266 # ok 1237 Set SVE VL 4944
2965 10:53:38.618362 # ok 1238 # SKIP SVE set SVE get SVE for VL 4944
2966 10:53:38.618471 # ok 1239 # SKIP SVE set SVE get FPSIMD for VL 4944
2967 10:53:38.618596 # ok 1240 # SKIP SVE set FPSIMD get SVE for VL 4944
2968 10:53:38.618694 # ok 1241 Set SVE VL 4960
2969 10:53:38.618804 # ok 1242 # SKIP SVE set SVE get SVE for VL 4960
2970 10:53:38.618915 # ok 1243 # SKIP SVE set SVE get FPSIMD for VL 4960
2971 10:53:38.619025 # ok 1244 # SKIP SVE set FPSIMD get SVE for VL 4960
2972 10:53:38.619363 # ok 1245 Set SVE VL 4976
2973 10:53:38.619482 # ok 1246 # SKIP SVE set SVE get SVE for VL 4976
2974 10:53:38.619577 # ok 1247 # SKIP SVE set SVE get FPSIMD for VL 4976
2975 10:53:38.619672 # ok 1248 # SKIP SVE set FPSIMD get SVE for VL 4976
2976 10:53:38.619778 # ok 1249 Set SVE VL 4992
2977 10:53:38.619874 # ok 1250 # SKIP SVE set SVE get SVE for VL 4992
2978 10:53:38.620788 # ok 1251 # SKIP SVE set SVE get FPSIMD for VL 4992
2979 10:53:38.621096 # ok 1252 # SKIP SVE set FPSIMD get SVE for VL 4992
2980 10:53:38.621198 # ok 1253 Set SVE VL 5008
2981 10:53:38.621309 # ok 1254 # SKIP SVE set SVE get SVE for VL 5008
2982 10:53:38.621404 # ok 1255 # SKIP SVE set SVE get FPSIMD for VL 5008
2983 10:53:38.621514 # ok 1256 # SKIP SVE set FPSIMD get SVE for VL 5008
2984 10:53:38.621625 # ok 1257 Set SVE VL 5024
2985 10:53:38.622084 # ok 1258 # SKIP SVE set SVE get SVE for VL 5024
2986 10:53:38.622229 # ok 1259 # SKIP SVE set SVE get FPSIMD for VL 5024
2987 10:53:38.622334 # ok 1260 # SKIP SVE set FPSIMD get SVE for VL 5024
2988 10:53:38.622429 # ok 1261 Set SVE VL 5040
2989 10:53:38.622522 # ok 1262 # SKIP SVE set SVE get SVE for VL 5040
2990 10:53:38.622615 # ok 1263 # SKIP SVE set SVE get FPSIMD for VL 5040
2991 10:53:38.622728 # ok 1264 # SKIP SVE set FPSIMD get SVE for VL 5040
2992 10:53:38.622825 # ok 1265 Set SVE VL 5056
2993 10:53:38.622920 # ok 1266 # SKIP SVE set SVE get SVE for VL 5056
2994 10:53:38.623013 # ok 1267 # SKIP SVE set SVE get FPSIMD for VL 5056
2995 10:53:38.623107 # ok 1268 # SKIP SVE set FPSIMD get SVE for VL 5056
2996 10:53:38.623201 # ok 1269 Set SVE VL 5072
2997 10:53:38.623313 # ok 1270 # SKIP SVE set SVE get SVE for VL 5072
2998 10:53:38.623409 # ok 1271 # SKIP SVE set SVE get FPSIMD for VL 5072
2999 10:53:38.623504 # ok 1272 # SKIP SVE set FPSIMD get SVE for VL 5072
3000 10:53:38.623599 # ok 1273 Set SVE VL 5088
3001 10:53:38.623709 # ok 1274 # SKIP SVE set SVE get SVE for VL 5088
3002 10:53:38.623806 # ok 1275 # SKIP SVE set SVE get FPSIMD for VL 5088
3003 10:53:38.624545 # ok 1276 # SKIP SVE set FPSIMD get SVE for VL 5088
3004 10:53:38.624842 # ok 1277 Set SVE VL 5104
3005 10:53:38.625055 # ok 1278 # SKIP SVE set SVE get SVE for VL 5104
3006 10:53:38.625395 # ok 1279 # SKIP SVE set SVE get FPSIMD for VL 5104
3007 10:53:38.625545 # ok 1280 # SKIP SVE set FPSIMD get SVE for VL 5104
3008 10:53:38.625742 # ok 1281 Set SVE VL 5120
3009 10:53:38.625893 # ok 1282 # SKIP SVE set SVE get SVE for VL 5120
3010 10:53:38.626003 # ok 1283 # SKIP SVE set SVE get FPSIMD for VL 5120
3011 10:53:38.626112 # ok 1284 # SKIP SVE set FPSIMD get SVE for VL 5120
3012 10:53:38.626210 # ok 1285 Set SVE VL 5136
3013 10:53:38.626304 # ok 1286 # SKIP SVE set SVE get SVE for VL 5136
3014 10:53:38.626398 # ok 1287 # SKIP SVE set SVE get FPSIMD for VL 5136
3015 10:53:38.626492 # ok 1288 # SKIP SVE set FPSIMD get SVE for VL 5136
3016 10:53:38.626588 # ok 1289 Set SVE VL 5152
3017 10:53:38.626686 # ok 1290 # SKIP SVE set SVE get SVE for VL 5152
3018 10:53:38.626798 # ok 1291 # SKIP SVE set SVE get FPSIMD for VL 5152
3019 10:53:38.626894 # ok 1292 # SKIP SVE set FPSIMD get SVE for VL 5152
3020 10:53:38.626988 # ok 1293 Set SVE VL 5168
3021 10:53:38.627082 # ok 1294 # SKIP SVE set SVE get SVE for VL 5168
3022 10:53:38.627175 # ok 1295 # SKIP SVE set SVE get FPSIMD for VL 5168
3023 10:53:38.627287 # ok 1296 # SKIP SVE set FPSIMD get SVE for VL 5168
3024 10:53:38.627383 # ok 1297 Set SVE VL 5184
3025 10:53:38.627478 # ok 1298 # SKIP SVE set SVE get SVE for VL 5184
3026 10:53:38.627572 # ok 1299 # SKIP SVE set SVE get FPSIMD for VL 5184
3027 10:53:38.627671 # ok 1300 # SKIP SVE set FPSIMD get SVE for VL 5184
3028 10:53:38.627782 # ok 1301 Set SVE VL 5200
3029 10:53:38.627880 # ok 1302 # SKIP SVE set SVE get SVE for VL 5200
3030 10:53:38.627991 # ok 1303 # SKIP SVE set SVE get FPSIMD for VL 5200
3031 10:53:38.628088 # ok 1304 # SKIP SVE set FPSIMD get SVE for VL 5200
3032 10:53:38.628198 # ok 1305 Set SVE VL 5216
3033 10:53:38.628309 # ok 1306 # SKIP SVE set SVE get SVE for VL 5216
3034 10:53:38.628419 # ok 1307 # SKIP SVE set SVE get FPSIMD for VL 5216
3035 10:53:38.628530 # ok 1308 # SKIP SVE set FPSIMD get SVE for VL 5216
3036 10:53:38.628640 # ok 1309 Set SVE VL 5232
3037 10:53:38.628751 # ok 1310 # SKIP SVE set SVE get SVE for VL 5232
3038 10:53:38.629061 # ok 1311 # SKIP SVE set SVE get FPSIMD for VL 5232
3039 10:53:38.629194 # ok 1312 # SKIP SVE set FPSIMD get SVE for VL 5232
3040 10:53:38.629307 # ok 1313 Set SVE VL 5248
3041 10:53:38.629401 # ok 1314 # SKIP SVE set SVE get SVE for VL 5248
3042 10:53:38.629701 # ok 1315 # SKIP SVE set SVE get FPSIMD for VL 5248
3043 10:53:38.629814 # ok 1316 # SKIP SVE set FPSIMD get SVE for VL 5248
3044 10:53:38.629910 # ok 1317 Set SVE VL 5264
3045 10:53:38.630021 # ok 1318 # SKIP SVE set SVE get SVE for VL 5264
3046 10:53:38.630114 # ok 1319 # SKIP SVE set SVE get FPSIMD for VL 5264
3047 10:53:38.630385 # ok 1320 # SKIP SVE set FPSIMD get SVE for VL 5264
3048 10:53:38.630469 # ok 1321 Set SVE VL 5280
3049 10:53:38.630549 # ok 1322 # SKIP SVE set SVE get SVE for VL 5280
3050 10:53:38.630647 # ok 1323 # SKIP SVE set SVE get FPSIMD for VL 5280
3051 10:53:38.630728 # ok 1324 # SKIP SVE set FPSIMD get SVE for VL 5280
3052 10:53:38.630823 # ok 1325 Set SVE VL 5296
3053 10:53:38.630904 # ok 1326 # SKIP SVE set SVE get SVE for VL 5296
3054 10:53:38.630996 # ok 1327 # SKIP SVE set SVE get FPSIMD for VL 5296
3055 10:53:38.631272 # ok 1328 # SKIP SVE set FPSIMD get SVE for VL 5296
3056 10:53:38.631370 # ok 1329 Set SVE VL 5312
3057 10:53:38.631477 # ok 1330 # SKIP SVE set SVE get SVE for VL 5312
3058 10:53:38.631585 # ok 1331 # SKIP SVE set SVE get FPSIMD for VL 5312
3059 10:53:38.632083 # ok 1332 # SKIP SVE set FPSIMD get SVE for VL 5312
3060 10:53:38.632375 # ok 1333 Set SVE VL 5328
3061 10:53:38.632472 # ok 1334 # SKIP SVE set SVE get SVE for VL 5328
3062 10:53:38.632582 # ok 1335 # SKIP SVE set SVE get FPSIMD for VL 5328
3063 10:53:38.632691 # ok 1336 # SKIP SVE set FPSIMD get SVE for VL 5328
3064 10:53:38.632799 # ok 1337 Set SVE VL 5344
3065 10:53:38.632907 # ok 1338 # SKIP SVE set SVE get SVE for VL 5344
3066 10:53:38.633193 # ok 1339 # SKIP SVE set SVE get FPSIMD for VL 5344
3067 10:53:38.633290 # ok 1340 # SKIP SVE set FPSIMD get SVE for VL 5344
3068 10:53:38.633382 # ok 1341 Set SVE VL 5360
3069 10:53:38.633489 # ok 1342 # SKIP SVE set SVE get SVE for VL 5360
3070 10:53:38.633602 # ok 1343 # SKIP SVE set SVE get FPSIMD for VL 5360
3071 10:53:38.633718 # ok 1344 # SKIP SVE set FPSIMD get SVE for VL 5360
3072 10:53:38.633828 # ok 1345 Set SVE VL 5376
3073 10:53:38.634182 # ok 1346 # SKIP SVE set SVE get SVE for VL 5376
3074 10:53:38.634290 # ok 1347 # SKIP SVE set SVE get FPSIMD for VL 5376
3075 10:53:38.634399 # ok 1348 # SKIP SVE set FPSIMD get SVE for VL 5376
3076 10:53:38.634493 # ok 1349 Set SVE VL 5392
3077 10:53:38.634599 # ok 1350 # SKIP SVE set SVE get SVE for VL 5392
3078 10:53:38.634894 # ok 1351 # SKIP SVE set SVE get FPSIMD for VL 5392
3079 10:53:38.635001 # ok 1352 # SKIP SVE set FPSIMD get SVE for VL 5392
3080 10:53:38.635095 # ok 1353 Set SVE VL 5408
3081 10:53:38.635202 # ok 1354 # SKIP SVE set SVE get SVE for VL 5408
3082 10:53:38.635296 # ok 1355 # SKIP SVE set SVE get FPSIMD for VL 5408
3083 10:53:38.635403 # ok 1356 # SKIP SVE set FPSIMD get SVE for VL 5408
3084 10:53:38.635510 # ok 1357 Set SVE VL 5424
3085 10:53:38.635618 # ok 1358 # SKIP SVE set SVE get SVE for VL 5424
3086 10:53:38.636063 # ok 1359 # SKIP SVE set SVE get FPSIMD for VL 5424
3087 10:53:38.636388 # ok 1360 # SKIP SVE set FPSIMD get SVE for VL 5424
3088 10:53:38.636497 # ok 1361 Set SVE VL 5440
3089 10:53:38.636606 # ok 1362 # SKIP SVE set SVE get SVE for VL 5440
3090 10:53:38.636699 # ok 1363 # SKIP SVE set SVE get FPSIMD for VL 5440
3091 10:53:38.636806 # ok 1364 # SKIP SVE set FPSIMD get SVE for VL 5440
3092 10:53:38.636900 # ok 1365 Set SVE VL 5456
3093 10:53:38.637006 # ok 1366 # SKIP SVE set SVE get SVE for VL 5456
3094 10:53:38.637299 # ok 1367 # SKIP SVE set SVE get FPSIMD for VL 5456
3095 10:53:38.637401 # ok 1368 # SKIP SVE set FPSIMD get SVE for VL 5456
3096 10:53:38.637503 # ok 1369 Set SVE VL 5472
3097 10:53:38.637589 # ok 1370 # SKIP SVE set SVE get SVE for VL 5472
3098 10:53:38.637681 # ok 1371 # SKIP SVE set SVE get FPSIMD for VL 5472
3099 10:53:38.637776 # ok 1372 # SKIP SVE set FPSIMD get SVE for VL 5472
3100 10:53:38.637866 # ok 1373 Set SVE VL 5488
3101 10:53:38.640684 # ok 1374 # SKIP SVE set SVE get SVE for VL 5488
3102 10:53:38.640846 # ok 1375 # SKIP SVE set SVE get FPSIMD for VL 5488
3103 10:53:38.640992 # ok 1376 # SKIP SVE set FPSIMD get SVE for VL 5488
3104 10:53:38.641140 # ok 1377 Set SVE VL 5504
3105 10:53:38.641258 # ok 1378 # SKIP SVE set SVE get SVE for VL 5504
3106 10:53:38.641357 # ok 1379 # SKIP SVE set SVE get FPSIMD for VL 5504
3107 10:53:38.641454 # ok 1380 # SKIP SVE set FPSIMD get SVE for VL 5504
3108 10:53:38.641549 # ok 1381 Set SVE VL 5520
3109 10:53:38.641643 # ok 1382 # SKIP SVE set SVE get SVE for VL 5520
3110 10:53:38.641748 # ok 1383 # SKIP SVE set SVE get FPSIMD for VL 5520
3111 10:53:38.641844 # ok 1384 # SKIP SVE set FPSIMD get SVE for VL 5520
3112 10:53:38.641939 # ok 1385 Set SVE VL 5536
3113 10:53:38.642034 # ok 1386 # SKIP SVE set SVE get SVE for VL 5536
3114 10:53:38.642130 # ok 1387 # SKIP SVE set SVE get FPSIMD for VL 5536
3115 10:53:38.642225 # ok 1388 # SKIP SVE set FPSIMD get SVE for VL 5536
3116 10:53:38.642320 # ok 1389 Set SVE VL 5552
3117 10:53:38.642415 # ok 1390 # SKIP SVE set SVE get SVE for VL 5552
3118 10:53:38.642510 # ok 1391 # SKIP SVE set SVE get FPSIMD for VL 5552
3119 10:53:38.642605 # ok 1392 # SKIP SVE set FPSIMD get SVE for VL 5552
3120 10:53:38.642700 # ok 1393 Set SVE VL 5568
3121 10:53:38.642794 # ok 1394 # SKIP SVE set SVE get SVE for VL 5568
3122 10:53:38.642889 # ok 1395 # SKIP SVE set SVE get FPSIMD for VL 5568
3123 10:53:38.642984 # ok 1396 # SKIP SVE set FPSIMD get SVE for VL 5568
3124 10:53:38.643079 # ok 1397 Set SVE VL 5584
3125 10:53:38.643375 # ok 1398 # SKIP SVE set SVE get SVE for VL 5584
3126 10:53:38.643477 # ok 1399 # SKIP SVE set SVE get FPSIMD for VL 5584
3127 10:53:38.643574 # ok 1400 # SKIP SVE set FPSIMD get SVE for VL 5584
3128 10:53:38.643675 # ok 1401 Set SVE VL 5600
3129 10:53:38.643771 # ok 1402 # SKIP SVE set SVE get SVE for VL 5600
3130 10:53:38.643866 # ok 1403 # SKIP SVE set SVE get FPSIMD for VL 5600
3131 10:53:38.643961 # ok 1404 # SKIP SVE set FPSIMD get SVE for VL 5600
3132 10:53:38.644056 # ok 1405 Set SVE VL 5616
3133 10:53:38.644151 # ok 1406 # SKIP SVE set SVE get SVE for VL 5616
3134 10:53:38.675122 # ok 1407 # SKIP SVE set SVE get FPSIMD for VL 5616
3135 10:53:38.675238 # ok 1408 # SKIP SVE set FPSIMD get SVE for VL 5616
3136 10:53:38.675550 # ok 1409 Set SVE VL 5632
3137 10:53:38.675651 # ok 1410 # SKIP SVE set SVE get SVE for VL 5632
3138 10:53:38.675742 # ok 1411 # SKIP SVE set SVE get FPSIMD for VL 5632
3139 10:53:38.675821 # ok 1412 # SKIP SVE set FPSIMD get SVE for VL 5632
3140 10:53:38.675900 # ok 1413 Set SVE VL 5648
3141 10:53:38.678215 # ok 1414 # SKIP SVE set SVE get SVE for VL 5648
3142 10:53:38.678519 # ok 1415 # SKIP SVE set SVE get FPSIMD for VL 5648
3143 10:53:38.678625 # ok 1416 # SKIP SVE set FPSIMD get SVE for VL 5648
3144 10:53:38.678711 # ok 1417 Set SVE VL 5664
3145 10:53:38.678807 # ok 1418 # SKIP SVE set SVE get SVE for VL 5664
3146 10:53:38.678891 # ok 1419 # SKIP SVE set SVE get FPSIMD for VL 5664
3147 10:53:38.678982 # ok 1420 # SKIP SVE set FPSIMD get SVE for VL 5664
3148 10:53:38.679064 # ok 1421 Set SVE VL 5680
3149 10:53:38.679158 # ok 1422 # SKIP SVE set SVE get SVE for VL 5680
3150 10:53:38.679251 # ok 1423 # SKIP SVE set SVE get FPSIMD for VL 5680
3151 10:53:38.679343 # ok 1424 # SKIP SVE set FPSIMD get SVE for VL 5680
3152 10:53:38.679436 # ok 1425 Set SVE VL 5696
3153 10:53:38.679528 # ok 1426 # SKIP SVE set SVE get SVE for VL 5696
3154 10:53:38.679817 # ok 1427 # SKIP SVE set SVE get FPSIMD for VL 5696
3155 10:53:38.681292 # ok 1428 # SKIP SVE set FPSIMD get SVE for VL 5696
3156 10:53:38.681394 # ok 1429 Set SVE VL 5712
3157 10:53:38.681489 # ok 1430 # SKIP SVE set SVE get SVE for VL 5712
3158 10:53:38.681583 # ok 1431 # SKIP SVE set SVE get FPSIMD for VL 5712
3159 10:53:38.681685 # ok 1432 # SKIP SVE set FPSIMD get SVE for VL 5712
3160 10:53:38.681784 # ok 1433 Set SVE VL 5728
3161 10:53:38.681876 # ok 1434 # SKIP SVE set SVE get SVE for VL 5728
3162 10:53:38.682164 # ok 1435 # SKIP SVE set SVE get FPSIMD for VL 5728
3163 10:53:38.682266 # ok 1436 # SKIP SVE set FPSIMD get SVE for VL 5728
3164 10:53:38.682363 # ok 1437 Set SVE VL 5744
3165 10:53:38.682456 # ok 1438 # SKIP SVE set SVE get SVE for VL 5744
3166 10:53:38.682548 # ok 1439 # SKIP SVE set SVE get FPSIMD for VL 5744
3167 10:53:38.682640 # ok 1440 # SKIP SVE set FPSIMD get SVE for VL 5744
3168 10:53:38.682735 # ok 1441 Set SVE VL 5760
3169 10:53:38.682826 # ok 1442 # SKIP SVE set SVE get SVE for VL 5760
3170 10:53:38.683152 # ok 1443 # SKIP SVE set SVE get FPSIMD for VL 5760
3171 10:53:38.683252 # ok 1444 # SKIP SVE set FPSIMD get SVE for VL 5760
3172 10:53:38.683346 # ok 1445 Set SVE VL 5776
3173 10:53:38.683426 # ok 1446 # SKIP SVE set SVE get SVE for VL 5776
3174 10:53:38.683517 # ok 1447 # SKIP SVE set SVE get FPSIMD for VL 5776
3175 10:53:38.683802 # ok 1448 # SKIP SVE set FPSIMD get SVE for VL 5776
3176 10:53:38.685845 # ok 1449 Set SVE VL 5792
3177 10:53:38.686139 # ok 1450 # SKIP SVE set SVE get SVE for VL 5792
3178 10:53:38.686239 # ok 1451 # SKIP SVE set SVE get FPSIMD for VL 5792
3179 10:53:38.686764 # ok 1452 # SKIP SVE set FPSIMD get SVE for VL 5792
3180 10:53:38.686943 # ok 1453 Set SVE VL 5808
3181 10:53:38.687138 # ok 1454 # SKIP SVE set SVE get SVE for VL 5808
3182 10:53:38.687315 # ok 1455 # SKIP SVE set SVE get FPSIMD for VL 5808
3183 10:53:38.687501 # ok 1456 # SKIP SVE set FPSIMD get SVE for VL 5808
3184 10:53:38.687656 # ok 1457 Set SVE VL 5824
3185 10:53:38.687827 # ok 1458 # SKIP SVE set SVE get SVE for VL 5824
3186 10:53:38.689121 # ok 1459 # SKIP SVE set SVE get FPSIMD for VL 5824
3187 10:53:38.689535 # ok 1460 # SKIP SVE set FPSIMD get SVE for VL 5824
3188 10:53:38.689710 # ok 1461 Set SVE VL 5840
3189 10:53:38.689855 # ok 1462 # SKIP SVE set SVE get SVE for VL 5840
3190 10:53:38.690037 # ok 1463 # SKIP SVE set SVE get FPSIMD for VL 5840
3191 10:53:38.690196 # ok 1464 # SKIP SVE set FPSIMD get SVE for VL 5840
3192 10:53:38.690347 # ok 1465 Set SVE VL 5856
3193 10:53:38.690480 # ok 1466 # SKIP SVE set SVE get SVE for VL 5856
3194 10:53:38.690680 # ok 1467 # SKIP SVE set SVE get FPSIMD for VL 5856
3195 10:53:38.690888 # ok 1468 # SKIP SVE set FPSIMD get SVE for VL 5856
3196 10:53:38.691095 # ok 1469 Set SVE VL 5872
3197 10:53:38.691278 # ok 1470 # SKIP SVE set SVE get SVE for VL 5872
3198 10:53:38.691471 # ok 1471 # SKIP SVE set SVE get FPSIMD for VL 5872
3199 10:53:38.691656 # ok 1472 # SKIP SVE set FPSIMD get SVE for VL 5872
3200 10:53:38.691787 # ok 1473 Set SVE VL 5888
3201 10:53:38.691912 # ok 1474 # SKIP SVE set SVE get SVE for VL 5888
3202 10:53:38.692029 # ok 1475 # SKIP SVE set SVE get FPSIMD for VL 5888
3203 10:53:38.692147 # ok 1476 # SKIP SVE set FPSIMD get SVE for VL 5888
3204 10:53:38.692264 # ok 1477 Set SVE VL 5904
3205 10:53:38.692392 # ok 1478 # SKIP SVE set SVE get SVE for VL 5904
3206 10:53:38.692518 # ok 1479 # SKIP SVE set SVE get FPSIMD for VL 5904
3207 10:53:38.692666 # ok 1480 # SKIP SVE set FPSIMD get SVE for VL 5904
3208 10:53:38.692801 # ok 1481 Set SVE VL 5920
3209 10:53:38.692927 # ok 1482 # SKIP SVE set SVE get SVE for VL 5920
3210 10:53:38.693076 # ok 1483 # SKIP SVE set SVE get FPSIMD for VL 5920
3211 10:53:38.693223 # ok 1484 # SKIP SVE set FPSIMD get SVE for VL 5920
3212 10:53:38.693366 # ok 1485 Set SVE VL 5936
3213 10:53:38.693530 # ok 1486 # SKIP SVE set SVE get SVE for VL 5936
3214 10:53:38.693743 # ok 1487 # SKIP SVE set SVE get FPSIMD for VL 5936
3215 10:53:38.693883 # ok 1488 # SKIP SVE set FPSIMD get SVE for VL 5936
3216 10:53:38.694013 # ok 1489 Set SVE VL 5952
3217 10:53:38.694139 # ok 1490 # SKIP SVE set SVE get SVE for VL 5952
3218 10:53:38.694266 # ok 1491 # SKIP SVE set SVE get FPSIMD for VL 5952
3219 10:53:38.694421 # ok 1492 # SKIP SVE set FPSIMD get SVE for VL 5952
3220 10:53:38.694555 # ok 1493 Set SVE VL 5968
3221 10:53:38.694682 # ok 1494 # SKIP SVE set SVE get SVE for VL 5968
3222 10:53:38.694806 # ok 1495 # SKIP SVE set SVE get FPSIMD for VL 5968
3223 10:53:38.694932 # ok 1496 # SKIP SVE set FPSIMD get SVE for VL 5968
3224 10:53:38.695057 # ok 1497 Set SVE VL 5984
3225 10:53:38.695205 # ok 1498 # SKIP SVE set SVE get SVE for VL 5984
3226 10:53:38.695335 # ok 1499 # SKIP SVE set SVE get FPSIMD for VL 5984
3227 10:53:38.695461 # ok 1500 # SKIP SVE set FPSIMD get SVE for VL 5984
3228 10:53:38.695585 # ok 1501 Set SVE VL 6000
3229 10:53:38.695709 # ok 1502 # SKIP SVE set SVE get SVE for VL 6000
3230 10:53:38.696036 # ok 1503 # SKIP SVE set SVE get FPSIMD for VL 6000
3231 10:53:38.696161 # ok 1504 # SKIP SVE set FPSIMD get SVE for VL 6000
3232 10:53:38.696283 # ok 1505 Set SVE VL 6016
3233 10:53:38.696426 # ok 1506 # SKIP SVE set SVE get SVE for VL 6016
3234 10:53:38.696551 # ok 1507 # SKIP SVE set SVE get FPSIMD for VL 6016
3235 10:53:38.696712 # ok 1508 # SKIP SVE set FPSIMD get SVE for VL 6016
3236 10:53:38.696849 # ok 1509 Set SVE VL 6032
3237 10:53:38.696974 # ok 1510 # SKIP SVE set SVE get SVE for VL 6032
3238 10:53:38.697107 # ok 1511 # SKIP SVE set SVE get FPSIMD for VL 6032
3239 10:53:38.697256 # ok 1512 # SKIP SVE set FPSIMD get SVE for VL 6032
3240 10:53:38.697389 # ok 1513 Set SVE VL 6048
3241 10:53:38.697540 # ok 1514 # SKIP SVE set SVE get SVE for VL 6048
3242 10:53:38.697684 # ok 1515 # SKIP SVE set SVE get FPSIMD for VL 6048
3243 10:53:38.697813 # ok 1516 # SKIP SVE set FPSIMD get SVE for VL 6048
3244 10:53:38.697939 # ok 1517 Set SVE VL 6064
3245 10:53:38.698093 # ok 1518 # SKIP SVE set SVE get SVE for VL 6064
3246 10:53:38.698223 # ok 1519 # SKIP SVE set SVE get FPSIMD for VL 6064
3247 10:53:38.698350 # ok 1520 # SKIP SVE set FPSIMD get SVE for VL 6064
3248 10:53:38.698479 # ok 1521 Set SVE VL 6080
3249 10:53:38.698605 # ok 1522 # SKIP SVE set SVE get SVE for VL 6080
3250 10:53:38.698758 # ok 1523 # SKIP SVE set SVE get FPSIMD for VL 6080
3251 10:53:38.698893 # ok 1524 # SKIP SVE set FPSIMD get SVE for VL 6080
3252 10:53:38.699021 # ok 1525 Set SVE VL 6096
3253 10:53:38.699148 # ok 1526 # SKIP SVE set SVE get SVE for VL 6096
3254 10:53:38.699298 # ok 1527 # SKIP SVE set SVE get FPSIMD for VL 6096
3255 10:53:38.699429 # ok 1528 # SKIP SVE set FPSIMD get SVE for VL 6096
3256 10:53:38.699559 # ok 1529 Set SVE VL 6112
3257 10:53:38.699683 # ok 1530 # SKIP SVE set SVE get SVE for VL 6112
3258 10:53:38.699826 # ok 1531 # SKIP SVE set SVE get FPSIMD for VL 6112
3259 10:53:38.699949 # ok 1532 # SKIP SVE set FPSIMD get SVE for VL 6112
3260 10:53:38.700075 # ok 1533 Set SVE VL 6128
3261 10:53:38.700219 # ok 1534 # SKIP SVE set SVE get SVE for VL 6128
3262 10:53:38.700372 # ok 1535 # SKIP SVE set SVE get FPSIMD for VL 6128
3263 10:53:38.700502 # ok 1536 # SKIP SVE set FPSIMD get SVE for VL 6128
3264 10:53:38.700649 # ok 1537 Set SVE VL 6144
3265 10:53:38.700782 # ok 1538 # SKIP SVE set SVE get SVE for VL 6144
3266 10:53:38.700932 # ok 1539 # SKIP SVE set SVE get FPSIMD for VL 6144
3267 10:53:38.701063 # ok 1540 # SKIP SVE set FPSIMD get SVE for VL 6144
3268 10:53:38.701190 # ok 1541 Set SVE VL 6160
3269 10:53:38.701337 # ok 1542 # SKIP SVE set SVE get SVE for VL 6160
3270 10:53:38.701467 # ok 1543 # SKIP SVE set SVE get FPSIMD for VL 6160
3271 10:53:38.701617 # ok 1544 # SKIP SVE set FPSIMD get SVE for VL 6160
3272 10:53:38.701762 # ok 1545 Set SVE VL 6176
3273 10:53:38.702102 # ok 1546 # SKIP SVE set SVE get SVE for VL 6176
3274 10:53:38.702239 # ok 1547 # SKIP SVE set SVE get FPSIMD for VL 6176
3275 10:53:38.702369 # ok 1548 # SKIP SVE set FPSIMD get SVE for VL 6176
3276 10:53:38.702502 # ok 1549 Set SVE VL 6192
3277 10:53:38.702753 # ok 1550 # SKIP SVE set SVE get SVE for VL 6192
3278 10:53:38.702939 # ok 1551 # SKIP SVE set SVE get FPSIMD for VL 6192
3279 10:53:38.703088 # ok 1552 # SKIP SVE set FPSIMD get SVE for VL 6192
3280 10:53:38.703256 # ok 1553 Set SVE VL 6208
3281 10:53:38.703405 # ok 1554 # SKIP SVE set SVE get SVE for VL 6208
3282 10:53:38.703599 # ok 1555 # SKIP SVE set SVE get FPSIMD for VL 6208
3283 10:53:38.703761 # ok 1556 # SKIP SVE set FPSIMD get SVE for VL 6208
3284 10:53:38.703914 # ok 1557 Set SVE VL 6224
3285 10:53:38.704077 # ok 1558 # SKIP SVE set SVE get SVE for VL 6224
3286 10:53:38.704216 # ok 1559 # SKIP SVE set SVE get FPSIMD for VL 6224
3287 10:53:38.704363 # ok 1560 # SKIP SVE set FPSIMD get SVE for VL 6224
3288 10:53:38.704531 # ok 1561 Set SVE VL 6240
3289 10:53:38.704732 # ok 1562 # SKIP SVE set SVE get SVE for VL 6240
3290 10:53:38.704909 # ok 1563 # SKIP SVE set SVE get FPSIMD for VL 6240
3291 10:53:38.705064 # ok 1564 # SKIP SVE set FPSIMD get SVE for VL 6240
3292 10:53:38.705230 # ok 1565 Set SVE VL 6256
3293 10:53:38.705389 # ok 1566 # SKIP SVE set SVE get SVE for VL 6256
3294 10:53:38.705547 # ok 1567 # SKIP SVE set SVE get FPSIMD for VL 6256
3295 10:53:38.705771 # ok 1568 # SKIP SVE set FPSIMD get SVE for VL 6256
3296 10:53:38.705972 # ok 1569 Set SVE VL 6272
3297 10:53:38.706156 # ok 1570 # SKIP SVE set SVE get SVE for VL 6272
3298 10:53:38.706340 # ok 1571 # SKIP SVE set SVE get FPSIMD for VL 6272
3299 10:53:38.706556 # ok 1572 # SKIP SVE set FPSIMD get SVE for VL 6272
3300 10:53:38.706753 # ok 1573 Set SVE VL 6288
3301 10:53:38.706932 # ok 1574 # SKIP SVE set SVE get SVE for VL 6288
3302 10:53:38.707078 # ok 1575 # SKIP SVE set SVE get FPSIMD for VL 6288
3303 10:53:38.707221 # ok 1576 # SKIP SVE set FPSIMD get SVE for VL 6288
3304 10:53:38.707363 # ok 1577 Set SVE VL 6304
3305 10:53:38.707505 # ok 1578 # SKIP SVE set SVE get SVE for VL 6304
3306 10:53:38.707647 # ok 1579 # SKIP SVE set SVE get FPSIMD for VL 6304
3307 10:53:38.707788 # ok 1580 # SKIP SVE set FPSIMD get SVE for VL 6304
3308 10:53:38.707934 # ok 1581 Set SVE VL 6320
3309 10:53:38.708076 # ok 1582 # SKIP SVE set SVE get SVE for VL 6320
3310 10:53:38.708219 # ok 1583 # SKIP SVE set SVE get FPSIMD for VL 6320
3311 10:53:38.708362 # ok 1584 # SKIP SVE set FPSIMD get SVE for VL 6320
3312 10:53:38.708507 # ok 1585 Set SVE VL 6336
3313 10:53:38.708649 # ok 1586 # SKIP SVE set SVE get SVE for VL 6336
3314 10:53:38.708826 # ok 1587 # SKIP SVE set SVE get FPSIMD for VL 6336
3315 10:53:38.708964 # ok 1588 # SKIP SVE set FPSIMD get SVE for VL 6336
3316 10:53:38.709319 # ok 1589 Set SVE VL 6352
3317 10:53:38.709896 # ok 1590 # SKIP SVE set SVE get SVE for VL 6352
3318 10:53:38.710071 # ok 1591 # SKIP SVE set SVE get FPSIMD for VL 6352
3319 10:53:38.710506 # ok 1592 # SKIP SVE set FPSIMD get SVE for VL 6352
3320 10:53:38.710691 # ok 1593 Set SVE VL 6368
3321 10:53:38.710818 # ok 1594 # SKIP SVE set SVE get SVE for VL 6368
3322 10:53:38.710917 # ok 1595 # SKIP SVE set SVE get FPSIMD for VL 6368
3323 10:53:38.711025 # ok 1596 # SKIP SVE set FPSIMD get SVE for VL 6368
3324 10:53:38.711160 # ok 1597 Set SVE VL 6384
3325 10:53:38.711263 # ok 1598 # SKIP SVE set SVE get SVE for VL 6384
3326 10:53:38.711374 # ok 1599 # SKIP SVE set SVE get FPSIMD for VL 6384
3327 10:53:38.711481 # ok 1600 # SKIP SVE set FPSIMD get SVE for VL 6384
3328 10:53:38.711588 # ok 1601 Set SVE VL 6400
3329 10:53:38.711707 # ok 1602 # SKIP SVE set SVE get SVE for VL 6400
3330 10:53:38.711800 # ok 1603 # SKIP SVE set SVE get FPSIMD for VL 6400
3331 10:53:38.711889 # ok 1604 # SKIP SVE set FPSIMD get SVE for VL 6400
3332 10:53:38.711977 # ok 1605 Set SVE VL 6416
3333 10:53:38.712333 # ok 1606 # SKIP SVE set SVE get SVE for VL 6416
3334 10:53:38.712672 # ok 1607 # SKIP SVE set SVE get FPSIMD for VL 6416
3335 10:53:38.712789 # ok 1608 # SKIP SVE set FPSIMD get SVE for VL 6416
3336 10:53:38.712871 # ok 1609 Set SVE VL 6432
3337 10:53:38.712964 # ok 1610 # SKIP SVE set SVE get SVE for VL 6432
3338 10:53:38.713030 # ok 1611 # SKIP SVE set SVE get FPSIMD for VL 6432
3339 10:53:38.713091 # ok 1612 # SKIP SVE set FPSIMD get SVE for VL 6432
3340 10:53:38.713165 # ok 1613 Set SVE VL 6448
3341 10:53:38.713231 # ok 1614 # SKIP SVE set SVE get SVE for VL 6448
3342 10:53:38.713487 # ok 1615 # SKIP SVE set SVE get FPSIMD for VL 6448
3343 10:53:38.713579 # ok 1616 # SKIP SVE set FPSIMD get SVE for VL 6448
3344 10:53:38.713662 # ok 1617 Set SVE VL 6464
3345 10:53:38.713746 # ok 1618 # SKIP SVE set SVE get SVE for VL 6464
3346 10:53:38.714013 # ok 1619 # SKIP SVE set SVE get FPSIMD for VL 6464
3347 10:53:38.714098 # ok 1620 # SKIP SVE set FPSIMD get SVE for VL 6464
3348 10:53:38.714182 # ok 1621 Set SVE VL 6480
3349 10:53:38.714265 # ok 1622 # SKIP SVE set SVE get SVE for VL 6480
3350 10:53:38.714506 # ok 1623 # SKIP SVE set SVE get FPSIMD for VL 6480
3351 10:53:38.714608 # ok 1624 # SKIP SVE set FPSIMD get SVE for VL 6480
3352 10:53:38.714704 # ok 1625 Set SVE VL 6496
3353 10:53:38.714782 # ok 1626 # SKIP SVE set SVE get SVE for VL 6496
3354 10:53:38.714870 # ok 1627 # SKIP SVE set SVE get FPSIMD for VL 6496
3355 10:53:38.715143 # ok 1628 # SKIP SVE set FPSIMD get SVE for VL 6496
3356 10:53:38.715224 # ok 1629 Set SVE VL 6512
3357 10:53:38.715311 # ok 1630 # SKIP SVE set SVE get SVE for VL 6512
3358 10:53:38.715398 # ok 1631 # SKIP SVE set SVE get FPSIMD for VL 6512
3359 10:53:38.715668 # ok 1632 # SKIP SVE set FPSIMD get SVE for VL 6512
3360 10:53:38.715749 # ok 1633 Set SVE VL 6528
3361 10:53:38.716019 # ok 1634 # SKIP SVE set SVE get SVE for VL 6528
3362 10:53:38.716100 # ok 1635 # SKIP SVE set SVE get FPSIMD for VL 6528
3363 10:53:38.716376 # ok 1636 # SKIP SVE set FPSIMD get SVE for VL 6528
3364 10:53:38.716473 # ok 1637 Set SVE VL 6544
3365 10:53:38.716549 # ok 1638 # SKIP SVE set SVE get SVE for VL 6544
3366 10:53:38.716637 # ok 1639 # SKIP SVE set SVE get FPSIMD for VL 6544
3367 10:53:38.716725 # ok 1640 # SKIP SVE set FPSIMD get SVE for VL 6544
3368 10:53:38.717001 # ok 1641 Set SVE VL 6560
3369 10:53:38.717085 # ok 1642 # SKIP SVE set SVE get SVE for VL 6560
3370 10:53:38.717165 # ok 1643 # SKIP SVE set SVE get FPSIMD for VL 6560
3371 10:53:38.717253 # ok 1644 # SKIP SVE set FPSIMD get SVE for VL 6560
3372 10:53:38.717508 # ok 1645 Set SVE VL 6576
3373 10:53:38.717578 # ok 1646 # SKIP SVE set SVE get SVE for VL 6576
3374 10:53:38.717658 # ok 1647 # SKIP SVE set SVE get FPSIMD for VL 6576
3375 10:53:38.717903 # ok 1648 # SKIP SVE set FPSIMD get SVE for VL 6576
3376 10:53:38.717970 # ok 1649 Set SVE VL 6592
3377 10:53:38.718043 # ok 1650 # SKIP SVE set SVE get SVE for VL 6592
3378 10:53:38.718123 # ok 1651 # SKIP SVE set SVE get FPSIMD for VL 6592
3379 10:53:38.718371 # ok 1652 # SKIP SVE set FPSIMD get SVE for VL 6592
3380 10:53:38.718438 # ok 1653 Set SVE VL 6608
3381 10:53:38.718511 # ok 1654 # SKIP SVE set SVE get SVE for VL 6608
3382 10:53:38.718762 # ok 1655 # SKIP SVE set SVE get FPSIMD for VL 6608
3383 10:53:38.719011 # ok 1656 # SKIP SVE set FPSIMD get SVE for VL 6608
3384 10:53:38.719078 # ok 1657 Set SVE VL 6624
3385 10:53:38.719326 # ok 1658 # SKIP SVE set SVE get SVE for VL 6624
3386 10:53:38.719394 # ok 1659 # SKIP SVE set SVE get FPSIMD for VL 6624
3387 10:53:38.719641 # ok 1660 # SKIP SVE set FPSIMD get SVE for VL 6624
3388 10:53:38.719709 # ok 1661 Set SVE VL 6640
3389 10:53:38.719771 # ok 1662 # SKIP SVE set SVE get SVE for VL 6640
3390 10:53:38.719850 # ok 1663 # SKIP SVE set SVE get FPSIMD for VL 6640
3391 10:53:38.720262 # ok 1664 # SKIP SVE set FPSIMD get SVE for VL 6640
3392 10:53:38.720330 # ok 1665 Set SVE VL 6656
3393 10:53:38.720392 # ok 1666 # SKIP SVE set SVE get SVE for VL 6656
3394 10:53:38.720465 # ok 1667 # SKIP SVE set SVE get FPSIMD for VL 6656
3395 10:53:38.720538 # ok 1668 # SKIP SVE set FPSIMD get SVE for VL 6656
3396 10:53:38.720786 # ok 1669 Set SVE VL 6672
3397 10:53:38.720853 # ok 1670 # SKIP SVE set SVE get SVE for VL 6672
3398 10:53:38.721102 # ok 1671 # SKIP SVE set SVE get FPSIMD for VL 6672
3399 10:53:38.721179 # ok 1672 # SKIP SVE set FPSIMD get SVE for VL 6672
3400 10:53:38.721253 # ok 1673 Set SVE VL 6688
3401 10:53:38.721345 # ok 1674 # SKIP SVE set SVE get SVE for VL 6688
3402 10:53:38.721762 # ok 1675 # SKIP SVE set SVE get FPSIMD for VL 6688
3403 10:53:38.721830 # ok 1676 # SKIP SVE set FPSIMD get SVE for VL 6688
3404 10:53:38.721901 # ok 1677 Set SVE VL 6704
3405 10:53:38.721963 # ok 1678 # SKIP SVE set SVE get SVE for VL 6704
3406 10:53:38.722205 # ok 1679 # SKIP SVE set SVE get FPSIMD for VL 6704
3407 10:53:38.722279 # ok 1680 # SKIP SVE set FPSIMD get SVE for VL 6704
3408 10:53:38.722353 # ok 1681 Set SVE VL 6720
3409 10:53:38.722651 # ok 1682 # SKIP SVE set SVE get SVE for VL 6720
3410 10:53:38.722757 # ok 1683 # SKIP SVE set SVE get FPSIMD for VL 6720
3411 10:53:38.722863 # ok 1684 # SKIP SVE set FPSIMD get SVE for VL 6720
3412 10:53:38.722969 # ok 1685 Set SVE VL 6736
3413 10:53:38.723062 # ok 1686 # SKIP SVE set SVE get SVE for VL 6736
3414 10:53:38.723178 # ok 1687 # SKIP SVE set SVE get FPSIMD for VL 6736
3415 10:53:38.723275 # ok 1688 # SKIP SVE set FPSIMD get SVE for VL 6736
3416 10:53:38.723370 # ok 1689 Set SVE VL 6752
3417 10:53:38.723450 # ok 1690 # SKIP SVE set SVE get SVE for VL 6752
3418 10:53:38.723548 # ok 1691 # SKIP SVE set SVE get FPSIMD for VL 6752
3419 10:53:38.723639 # ok 1692 # SKIP SVE set FPSIMD get SVE for VL 6752
3420 10:53:38.723721 # ok 1693 Set SVE VL 6768
3421 10:53:38.723814 # ok 1694 # SKIP SVE set SVE get SVE for VL 6768
3422 10:53:38.723908 # ok 1695 # SKIP SVE set SVE get FPSIMD for VL 6768
3423 10:53:38.724209 # ok 1696 # SKIP SVE set FPSIMD get SVE for VL 6768
3424 10:53:38.724308 # ok 1697 Set SVE VL 6784
3425 10:53:38.724411 # ok 1698 # SKIP SVE set SVE get SVE for VL 6784
3426 10:53:38.724521 # ok 1699 # SKIP SVE set SVE get FPSIMD for VL 6784
3427 10:53:38.724642 # ok 1700 # SKIP SVE set FPSIMD get SVE for VL 6784
3428 10:53:38.724743 # ok 1701 Set SVE VL 6800
3429 10:53:38.724888 # ok 1702 # SKIP SVE set SVE get SVE for VL 6800
3430 10:53:38.725001 # ok 1703 # SKIP SVE set SVE get FPSIMD for VL 6800
3431 10:53:38.725139 # ok 1704 # SKIP SVE set FPSIMD get SVE for VL 6800
3432 10:53:38.725234 # ok 1705 Set SVE VL 6816
3433 10:53:38.725343 # ok 1706 # SKIP SVE set SVE get SVE for VL 6816
3434 10:53:38.725450 # ok 1707 # SKIP SVE set SVE get FPSIMD for VL 6816
3435 10:53:38.725552 # ok 1708 # SKIP SVE set FPSIMD get SVE for VL 6816
3436 10:53:38.725644 # ok 1709 Set SVE VL 6832
3437 10:53:38.725748 # ok 1710 # SKIP SVE set SVE get SVE for VL 6832
3438 10:53:38.725844 # ok 1711 # SKIP SVE set SVE get FPSIMD for VL 6832
3439 10:53:38.726167 # ok 1712 # SKIP SVE set FPSIMD get SVE for VL 6832
3440 10:53:38.726266 # ok 1713 Set SVE VL 6848
3441 10:53:38.726340 # ok 1714 # SKIP SVE set SVE get SVE for VL 6848
3442 10:53:38.726434 # ok 1715 # SKIP SVE set SVE get FPSIMD for VL 6848
3443 10:53:38.726529 # ok 1716 # SKIP SVE set FPSIMD get SVE for VL 6848
3444 10:53:38.726609 # ok 1717 Set SVE VL 6864
3445 10:53:38.726688 # ok 1718 # SKIP SVE set SVE get SVE for VL 6864
3446 10:53:38.726781 # ok 1719 # SKIP SVE set SVE get FPSIMD for VL 6864
3447 10:53:38.726875 # ok 1720 # SKIP SVE set FPSIMD get SVE for VL 6864
3448 10:53:38.726965 # ok 1721 Set SVE VL 6880
3449 10:53:38.727064 # ok 1722 # SKIP SVE set SVE get SVE for VL 6880
3450 10:53:38.727161 # ok 1723 # SKIP SVE set SVE get FPSIMD for VL 6880
3451 10:53:38.727256 # ok 1724 # SKIP SVE set FPSIMD get SVE for VL 6880
3452 10:53:38.727375 # ok 1725 Set SVE VL 6896
3453 10:53:38.727720 # ok 1726 # SKIP SVE set SVE get SVE for VL 6896
3454 10:53:38.727834 # ok 1727 # SKIP SVE set SVE get FPSIMD for VL 6896
3455 10:53:38.727955 # ok 1728 # SKIP SVE set FPSIMD get SVE for VL 6896
3456 10:53:38.728044 # ok 1729 Set SVE VL 6912
3457 10:53:38.728146 # ok 1730 # SKIP SVE set SVE get SVE for VL 6912
3458 10:53:38.728227 # ok 1731 # SKIP SVE set SVE get FPSIMD for VL 6912
3459 10:53:38.728332 # ok 1732 # SKIP SVE set FPSIMD get SVE for VL 6912
3460 10:53:38.728433 # ok 1733 Set SVE VL 6928
3461 10:53:38.728552 # ok 1734 # SKIP SVE set SVE get SVE for VL 6928
3462 10:53:38.728663 # ok 1735 # SKIP SVE set SVE get FPSIMD for VL 6928
3463 10:53:38.728758 # ok 1736 # SKIP SVE set FPSIMD get SVE for VL 6928
3464 10:53:38.728903 # ok 1737 Set SVE VL 6944
3465 10:53:38.729027 # ok 1738 # SKIP SVE set SVE get SVE for VL 6944
3466 10:53:38.729125 # ok 1739 # SKIP SVE set SVE get FPSIMD for VL 6944
3467 10:53:38.729218 # ok 1740 # SKIP SVE set FPSIMD get SVE for VL 6944
3468 10:53:38.729309 # ok 1741 Set SVE VL 6960
3469 10:53:38.729607 # ok 1742 # SKIP SVE set SVE get SVE for VL 6960
3470 10:53:38.729724 # ok 1743 # SKIP SVE set SVE get FPSIMD for VL 6960
3471 10:53:38.729879 # ok 1744 # SKIP SVE set FPSIMD get SVE for VL 6960
3472 10:53:38.730087 # ok 1745 Set SVE VL 6976
3473 10:53:38.730299 # ok 1746 # SKIP SVE set SVE get SVE for VL 6976
3474 10:53:38.730501 # ok 1747 # SKIP SVE set SVE get FPSIMD for VL 6976
3475 10:53:38.730660 # ok 1748 # SKIP SVE set FPSIMD get SVE for VL 6976
3476 10:53:38.730804 # ok 1749 Set SVE VL 6992
3477 10:53:38.730929 # ok 1750 # SKIP SVE set SVE get SVE for VL 6992
3478 10:53:38.731075 # ok 1751 # SKIP SVE set SVE get FPSIMD for VL 6992
3479 10:53:38.731234 # ok 1752 # SKIP SVE set FPSIMD get SVE for VL 6992
3480 10:53:38.731392 # ok 1753 Set SVE VL 7008
3481 10:53:38.731544 # ok 1754 # SKIP SVE set SVE get SVE for VL 7008
3482 10:53:38.731703 # ok 1755 # SKIP SVE set SVE get FPSIMD for VL 7008
3483 10:53:38.731871 # ok 1756 # SKIP SVE set FPSIMD get SVE for VL 7008
3484 10:53:38.732038 # ok 1757 Set SVE VL 7024
3485 10:53:38.732214 # ok 1758 # SKIP SVE set SVE get SVE for VL 7024
3486 10:53:38.732368 # ok 1759 # SKIP SVE set SVE get FPSIMD for VL 7024
3487 10:53:38.732510 # ok 1760 # SKIP SVE set FPSIMD get SVE for VL 7024
3488 10:53:38.732697 # ok 1761 Set SVE VL 7040
3489 10:53:38.732813 # ok 1762 # SKIP SVE set SVE get SVE for VL 7040
3490 10:53:38.732904 # ok 1763 # SKIP SVE set SVE get FPSIMD for VL 7040
3491 10:53:38.732992 # ok 1764 # SKIP SVE set FPSIMD get SVE for VL 7040
3492 10:53:38.733080 # ok 1765 Set SVE VL 7056
3493 10:53:38.733166 # ok 1766 # SKIP SVE set SVE get SVE for VL 7056
3494 10:53:38.733253 # ok 1767 # SKIP SVE set SVE get FPSIMD for VL 7056
3495 10:53:38.733340 # ok 1768 # SKIP SVE set FPSIMD get SVE for VL 7056
3496 10:53:38.733427 # ok 1769 Set SVE VL 7072
3497 10:53:38.733512 # ok 1770 # SKIP SVE set SVE get SVE for VL 7072
3498 10:53:38.733598 # ok 1771 # SKIP SVE set SVE get FPSIMD for VL 7072
3499 10:53:38.733750 # ok 1772 # SKIP SVE set FPSIMD get SVE for VL 7072
3500 10:53:38.735249 # ok 1773 Set SVE VL 7088
3501 10:53:38.735357 # ok 1774 # SKIP SVE set SVE get SVE for VL 7088
3502 10:53:38.735486 # ok 1775 # SKIP SVE set SVE get FPSIMD for VL 7088
3503 10:53:38.735612 # ok 1776 # SKIP SVE set FPSIMD get SVE for VL 7088
3504 10:53:38.735721 # ok 1777 Set SVE VL 7104
3505 10:53:38.736346 # ok 1778 # SKIP SVE set SVE get SVE for VL 7104
3506 10:53:38.736661 # ok 1779 # SKIP SVE set SVE get FPSIMD for VL 7104
3507 10:53:38.736775 # ok 1780 # SKIP SVE set FPSIMD get SVE for VL 7104
3508 10:53:38.736878 # ok 1781 Set SVE VL 7120
3509 10:53:38.736973 # ok 1782 # SKIP SVE set SVE get SVE for VL 7120
3510 10:53:38.737260 # ok 1783 # SKIP SVE set SVE get FPSIMD for VL 7120
3511 10:53:38.737363 # ok 1784 # SKIP SVE set FPSIMD get SVE for VL 7120
3512 10:53:38.737448 # ok 1785 Set SVE VL 7136
3513 10:53:38.737540 # ok 1786 # SKIP SVE set SVE get SVE for VL 7136
3514 10:53:38.737620 # ok 1787 # SKIP SVE set SVE get FPSIMD for VL 7136
3515 10:53:38.737720 # ok 1788 # SKIP SVE set FPSIMD get SVE for VL 7136
3516 10:53:38.737806 # ok 1789 Set SVE VL 7152
3517 10:53:38.737895 # ok 1790 # SKIP SVE set SVE get SVE for VL 7152
3518 10:53:38.737987 # ok 1791 # SKIP SVE set SVE get FPSIMD for VL 7152
3519 10:53:38.738079 # ok 1792 # SKIP SVE set FPSIMD get SVE for VL 7152
3520 10:53:38.738171 # ok 1793 Set SVE VL 7168
3521 10:53:38.738270 # ok 1794 # SKIP SVE set SVE get SVE for VL 7168
3522 10:53:38.738573 # ok 1795 # SKIP SVE set SVE get FPSIMD for VL 7168
3523 10:53:38.738700 # ok 1796 # SKIP SVE set FPSIMD get SVE for VL 7168
3524 10:53:38.738816 # ok 1797 Set SVE VL 7184
3525 10:53:38.738963 # ok 1798 # SKIP SVE set SVE get SVE for VL 7184
3526 10:53:38.739075 # ok 1799 # SKIP SVE set SVE get FPSIMD for VL 7184
3527 10:53:38.739182 # ok 1800 # SKIP SVE set FPSIMD get SVE for VL 7184
3528 10:53:38.739286 # ok 1801 Set SVE VL 7200
3529 10:53:38.739391 # ok 1802 # SKIP SVE set SVE get SVE for VL 7200
3530 10:53:38.739496 # ok 1803 # SKIP SVE set SVE get FPSIMD for VL 7200
3531 10:53:38.739628 # ok 1804 # SKIP SVE set FPSIMD get SVE for VL 7200
3532 10:53:38.739929 # ok 1805 Set SVE VL 7216
3533 10:53:38.740026 # ok 1806 # SKIP SVE set SVE get SVE for VL 7216
3534 10:53:38.740118 # ok 1807 # SKIP SVE set SVE get FPSIMD for VL 7216
3535 10:53:38.740206 # ok 1808 # SKIP SVE set FPSIMD get SVE for VL 7216
3536 10:53:38.740282 # ok 1809 Set SVE VL 7232
3537 10:53:38.740366 # ok 1810 # SKIP SVE set SVE get SVE for VL 7232
3538 10:53:38.740649 # ok 1811 # SKIP SVE set SVE get FPSIMD for VL 7232
3539 10:53:38.740747 # ok 1812 # SKIP SVE set FPSIMD get SVE for VL 7232
3540 10:53:38.740823 # ok 1813 Set SVE VL 7248
3541 10:53:38.740909 # ok 1814 # SKIP SVE set SVE get SVE for VL 7248
3542 10:53:38.740984 # ok 1815 # SKIP SVE set SVE get FPSIMD for VL 7248
3543 10:53:38.741070 # ok 1816 # SKIP SVE set FPSIMD get SVE for VL 7248
3544 10:53:38.741144 # ok 1817 Set SVE VL 7264
3545 10:53:38.741228 # ok 1818 # SKIP SVE set SVE get SVE for VL 7264
3546 10:53:38.741510 # ok 1819 # SKIP SVE set SVE get FPSIMD for VL 7264
3547 10:53:38.741608 # ok 1820 # SKIP SVE set FPSIMD get SVE for VL 7264
3548 10:53:38.741706 # ok 1821 Set SVE VL 7280
3549 10:53:38.741796 # ok 1822 # SKIP SVE set SVE get SVE for VL 7280
3550 10:53:38.741886 # ok 1823 # SKIP SVE set SVE get FPSIMD for VL 7280
3551 10:53:38.742169 # ok 1824 # SKIP SVE set FPSIMD get SVE for VL 7280
3552 10:53:38.742264 # ok 1825 Set SVE VL 7296
3553 10:53:38.742360 # ok 1826 # SKIP SVE set SVE get SVE for VL 7296
3554 10:53:38.742486 # ok 1827 # SKIP SVE set SVE get FPSIMD for VL 7296
3555 10:53:38.742600 # ok 1828 # SKIP SVE set FPSIMD get SVE for VL 7296
3556 10:53:38.742722 # ok 1829 Set SVE VL 7312
3557 10:53:38.742857 # ok 1830 # SKIP SVE set SVE get SVE for VL 7312
3558 10:53:38.742976 # ok 1831 # SKIP SVE set SVE get FPSIMD for VL 7312
3559 10:53:38.743075 # ok 1832 # SKIP SVE set FPSIMD get SVE for VL 7312
3560 10:53:38.743208 # ok 1833 Set SVE VL 7328
3561 10:53:38.743312 # ok 1834 # SKIP SVE set SVE get SVE for VL 7328
3562 10:53:38.743418 # ok 1835 # SKIP SVE set SVE get FPSIMD for VL 7328
3563 10:53:38.743534 # ok 1836 # SKIP SVE set FPSIMD get SVE for VL 7328
3564 10:53:38.743631 # ok 1837 Set SVE VL 7344
3565 10:53:38.743722 # ok 1838 # SKIP SVE set SVE get SVE for VL 7344
3566 10:53:38.743847 # ok 1839 # SKIP SVE set SVE get FPSIMD for VL 7344
3567 10:53:38.743949 # ok 1840 # SKIP SVE set FPSIMD get SVE for VL 7344
3568 10:53:38.744071 # ok 1841 Set SVE VL 7360
3569 10:53:38.744176 # ok 1842 # SKIP SVE set SVE get SVE for VL 7360
3570 10:53:38.744279 # ok 1843 # SKIP SVE set SVE get FPSIMD for VL 7360
3571 10:53:38.744387 # ok 1844 # SKIP SVE set FPSIMD get SVE for VL 7360
3572 10:53:38.744465 # ok 1845 Set SVE VL 7376
3573 10:53:38.744552 # ok 1846 # SKIP SVE set SVE get SVE for VL 7376
3574 10:53:38.744650 # ok 1847 # SKIP SVE set SVE get FPSIMD for VL 7376
3575 10:53:38.745020 # ok 1848 # SKIP SVE set FPSIMD get SVE for VL 7376
3576 10:53:38.745125 # ok 1849 Set SVE VL 7392
3577 10:53:38.745201 # ok 1850 # SKIP SVE set SVE get SVE for VL 7392
3578 10:53:38.745291 # ok 1851 # SKIP SVE set SVE get FPSIMD for VL 7392
3579 10:53:38.745368 # ok 1852 # SKIP SVE set FPSIMD get SVE for VL 7392
3580 10:53:38.745455 # ok 1853 Set SVE VL 7408
3581 10:53:38.745536 # ok 1854 # SKIP SVE set SVE get SVE for VL 7408
3582 10:53:38.745619 # ok 1855 # SKIP SVE set SVE get FPSIMD for VL 7408
3583 10:53:38.745723 # ok 1856 # SKIP SVE set FPSIMD get SVE for VL 7408
3584 10:53:38.746013 # ok 1857 Set SVE VL 7424
3585 10:53:38.746114 # ok 1858 # SKIP SVE set SVE get SVE for VL 7424
3586 10:53:38.746210 # ok 1859 # SKIP SVE set SVE get FPSIMD for VL 7424
3587 10:53:38.746291 # ok 1860 # SKIP SVE set FPSIMD get SVE for VL 7424
3588 10:53:38.746382 # ok 1861 Set SVE VL 7440
3589 10:53:38.746475 # ok 1862 # SKIP SVE set SVE get SVE for VL 7440
3590 10:53:38.746568 # ok 1863 # SKIP SVE set SVE get FPSIMD for VL 7440
3591 10:53:38.746856 # ok 1864 # SKIP SVE set FPSIMD get SVE for VL 7440
3592 10:53:38.746957 # ok 1865 Set SVE VL 7456
3593 10:53:38.747050 # ok 1866 # SKIP SVE set SVE get SVE for VL 7456
3594 10:53:38.747130 # ok 1867 # SKIP SVE set SVE get FPSIMD for VL 7456
3595 10:53:38.747221 # ok 1868 # SKIP SVE set FPSIMD get SVE for VL 7456
3596 10:53:38.747500 # ok 1869 Set SVE VL 7472
3597 10:53:38.747600 # ok 1870 # SKIP SVE set SVE get SVE for VL 7472
3598 10:53:38.747693 # ok 1871 # SKIP SVE set SVE get FPSIMD for VL 7472
3599 10:53:38.747975 # ok 1872 # SKIP SVE set FPSIMD get SVE for VL 7472
3600 10:53:38.748075 # ok 1873 Set SVE VL 7488
3601 10:53:38.748155 # ok 1874 # SKIP SVE set SVE get SVE for VL 7488
3602 10:53:38.748246 # ok 1875 # SKIP SVE set SVE get FPSIMD for VL 7488
3603 10:53:38.748327 # ok 1876 # SKIP SVE set FPSIMD get SVE for VL 7488
3604 10:53:38.748418 # ok 1877 Set SVE VL 7504
3605 10:53:38.748498 # ok 1878 # SKIP SVE set SVE get SVE for VL 7504
3606 10:53:38.748589 # ok 1879 # SKIP SVE set SVE get FPSIMD for VL 7504
3607 10:53:38.748681 # ok 1880 # SKIP SVE set FPSIMD get SVE for VL 7504
3608 10:53:38.748761 # ok 1881 Set SVE VL 7520
3609 10:53:38.749055 # ok 1882 # SKIP SVE set SVE get SVE for VL 7520
3610 10:53:38.749161 # ok 1883 # SKIP SVE set SVE get FPSIMD for VL 7520
3611 10:53:38.749255 # ok 1884 # SKIP SVE set FPSIMD get SVE for VL 7520
3612 10:53:38.749339 # ok 1885 Set SVE VL 7536
3613 10:53:38.749430 # ok 1886 # SKIP SVE set SVE get SVE for VL 7536
3614 10:53:38.749681 # ok 1887 # SKIP SVE set SVE get FPSIMD for VL 7536
3615 10:53:38.749779 # ok 1888 # SKIP SVE set FPSIMD get SVE for VL 7536
3616 10:53:38.749882 # ok 1889 Set SVE VL 7552
3617 10:53:38.750168 # ok 1890 # SKIP SVE set SVE get SVE for VL 7552
3618 10:53:38.750254 # ok 1891 # SKIP SVE set SVE get FPSIMD for VL 7552
3619 10:53:38.750345 # ok 1892 # SKIP SVE set FPSIMD get SVE for VL 7552
3620 10:53:38.750425 # ok 1893 Set SVE VL 7568
3621 10:53:38.750701 # ok 1894 # SKIP SVE set SVE get SVE for VL 7568
3622 10:53:38.750800 # ok 1895 # SKIP SVE set SVE get FPSIMD for VL 7568
3623 10:53:38.750899 # ok 1896 # SKIP SVE set FPSIMD get SVE for VL 7568
3624 10:53:38.750979 # ok 1897 Set SVE VL 7584
3625 10:53:38.751070 # ok 1898 # SKIP SVE set SVE get SVE for VL 7584
3626 10:53:38.751348 # ok 1899 # SKIP SVE set SVE get FPSIMD for VL 7584
3627 10:53:38.751431 # ok 1900 # SKIP SVE set FPSIMD get SVE for VL 7584
3628 10:53:38.751509 # ok 1901 Set SVE VL 7600
3629 10:53:38.751599 # ok 1902 # SKIP SVE set SVE get SVE for VL 7600
3630 10:53:38.751690 # ok 1903 # SKIP SVE set SVE get FPSIMD for VL 7600
3631 10:53:38.751958 # ok 1904 # SKIP SVE set FPSIMD get SVE for VL 7600
3632 10:53:38.752053 # ok 1905 Set SVE VL 7616
3633 10:53:38.752341 # ok 1906 # SKIP SVE set SVE get SVE for VL 7616
3634 10:53:38.752454 # ok 1907 # SKIP SVE set SVE get FPSIMD for VL 7616
3635 10:53:38.752537 # ok 1908 # SKIP SVE set FPSIMD get SVE for VL 7616
3636 10:53:38.752628 # ok 1909 Set SVE VL 7632
3637 10:53:38.752720 # ok 1910 # SKIP SVE set SVE get SVE for VL 7632
3638 10:53:38.752999 # ok 1911 # SKIP SVE set SVE get FPSIMD for VL 7632
3639 10:53:38.753084 # ok 1912 # SKIP SVE set FPSIMD get SVE for VL 7632
3640 10:53:38.753364 # ok 1913 Set SVE VL 7648
3641 10:53:38.753464 # ok 1914 # SKIP SVE set SVE get SVE for VL 7648
3642 10:53:38.753545 # ok 1915 # SKIP SVE set SVE get FPSIMD for VL 7648
3643 10:53:38.753637 # ok 1916 # SKIP SVE set FPSIMD get SVE for VL 7648
3644 10:53:38.753726 # ok 1917 Set SVE VL 7664
3645 10:53:38.753823 # ok 1918 # SKIP SVE set SVE get SVE for VL 7664
3646 10:53:38.753903 # ok 1919 # SKIP SVE set SVE get FPSIMD for VL 7664
3647 10:53:38.753999 # ok 1920 # SKIP SVE set FPSIMD get SVE for VL 7664
3648 10:53:38.756062 # ok 1921 Set SVE VL 7680
3649 10:53:38.756157 # ok 1922 # SKIP SVE set SVE get SVE for VL 7680
3650 10:53:38.756237 # ok 1923 # SKIP SVE set SVE get FPSIMD for VL 7680
3651 10:53:38.756314 # ok 1924 # SKIP SVE set FPSIMD get SVE for VL 7680
3652 10:53:38.756391 # ok 1925 Set SVE VL 7696
3653 10:53:38.756468 # ok 1926 # SKIP SVE set SVE get SVE for VL 7696
3654 10:53:38.756545 # ok 1927 # SKIP SVE set SVE get FPSIMD for VL 7696
3655 10:53:38.756623 # ok 1928 # SKIP SVE set FPSIMD get SVE for VL 7696
3656 10:53:38.756700 # ok 1929 Set SVE VL 7712
3657 10:53:38.756776 # ok 1930 # SKIP SVE set SVE get SVE for VL 7712
3658 10:53:38.756859 # ok 1931 # SKIP SVE set SVE get FPSIMD for VL 7712
3659 10:53:38.756936 # ok 1932 # SKIP SVE set FPSIMD get SVE for VL 7712
3660 10:53:38.757012 # ok 1933 Set SVE VL 7728
3661 10:53:38.757089 # ok 1934 # SKIP SVE set SVE get SVE for VL 7728
3662 10:53:38.757166 # ok 1935 # SKIP SVE set SVE get FPSIMD for VL 7728
3663 10:53:38.757242 # ok 1936 # SKIP SVE set FPSIMD get SVE for VL 7728
3664 10:53:38.757319 # ok 1937 Set SVE VL 7744
3665 10:53:38.757395 # ok 1938 # SKIP SVE set SVE get SVE for VL 7744
3666 10:53:38.757492 # ok 1939 # SKIP SVE set SVE get FPSIMD for VL 7744
3667 10:53:38.757573 # ok 1940 # SKIP SVE set FPSIMD get SVE for VL 7744
3668 10:53:38.757657 # ok 1941 Set SVE VL 7760
3669 10:53:38.757736 # ok 1942 # SKIP SVE set SVE get SVE for VL 7760
3670 10:53:38.757812 # ok 1943 # SKIP SVE set SVE get FPSIMD for VL 7760
3671 10:53:38.757894 # ok 1944 # SKIP SVE set FPSIMD get SVE for VL 7760
3672 10:53:38.757971 # ok 1945 Set SVE VL 7776
3673 10:53:38.758047 # ok 1946 # SKIP SVE set SVE get SVE for VL 7776
3674 10:53:38.758123 # ok 1947 # SKIP SVE set SVE get FPSIMD for VL 7776
3675 10:53:38.758200 # ok 1948 # SKIP SVE set FPSIMD get SVE for VL 7776
3676 10:53:38.758277 # ok 1949 Set SVE VL 7792
3677 10:53:38.758353 # ok 1950 # SKIP SVE set SVE get SVE for VL 7792
3678 10:53:38.758447 # ok 1951 # SKIP SVE set SVE get FPSIMD for VL 7792
3679 10:53:38.758526 # ok 1952 # SKIP SVE set FPSIMD get SVE for VL 7792
3680 10:53:38.758604 # ok 1953 Set SVE VL 7808
3681 10:53:38.758680 # ok 1954 # SKIP SVE set SVE get SVE for VL 7808
3682 10:53:38.758955 # ok 1955 # SKIP SVE set SVE get FPSIMD for VL 7808
3683 10:53:38.761300 # ok 1956 # SKIP SVE set FPSIMD get SVE for VL 7808
3684 10:53:38.761408 # ok 1957 Set SVE VL 7824
3685 10:53:38.761501 # ok 1958 # SKIP SVE set SVE get SVE for VL 7824
3686 10:53:38.761594 # ok 1959 # SKIP SVE set SVE get FPSIMD for VL 7824
3687 10:53:38.761879 # ok 1960 # SKIP SVE set FPSIMD get SVE for VL 7824
3688 10:53:38.761963 # ok 1961 Set SVE VL 7840
3689 10:53:38.762054 # ok 1962 # SKIP SVE set SVE get SVE for VL 7840
3690 10:53:38.762146 # ok 1963 # SKIP SVE set SVE get FPSIMD for VL 7840
3691 10:53:38.762420 # ok 1964 # SKIP SVE set FPSIMD get SVE for VL 7840
3692 10:53:38.762505 # ok 1965 Set SVE VL 7856
3693 10:53:38.762595 # ok 1966 # SKIP SVE set SVE get SVE for VL 7856
3694 10:53:38.762687 # ok 1967 # SKIP SVE set SVE get FPSIMD for VL 7856
3695 10:53:38.762787 # ok 1968 # SKIP SVE set FPSIMD get SVE for VL 7856
3696 10:53:38.763062 # ok 1969 Set SVE VL 7872
3697 10:53:38.763145 # ok 1970 # SKIP SVE set SVE get SVE for VL 7872
3698 10:53:38.763236 # ok 1971 # SKIP SVE set SVE get FPSIMD for VL 7872
3699 10:53:38.763509 # ok 1972 # SKIP SVE set FPSIMD get SVE for VL 7872
3700 10:53:38.763592 # ok 1973 Set SVE VL 7888
3701 10:53:38.763684 # ok 1974 # SKIP SVE set SVE get SVE for VL 7888
3702 10:53:38.764069 # ok 1975 # SKIP SVE set SVE get FPSIMD for VL 7888
3703 10:53:38.764339 # ok 1976 # SKIP SVE set FPSIMD get SVE for VL 7888
3704 10:53:38.764422 # ok 1977 Set SVE VL 7904
3705 10:53:38.764514 # ok 1978 # SKIP SVE set SVE get SVE for VL 7904
3706 10:53:38.764606 # ok 1979 # SKIP SVE set SVE get FPSIMD for VL 7904
3707 10:53:38.764884 # ok 1980 # SKIP SVE set FPSIMD get SVE for VL 7904
3708 10:53:38.764970 # ok 1981 Set SVE VL 7920
3709 10:53:38.765062 # ok 1982 # SKIP SVE set SVE get SVE for VL 7920
3710 10:53:38.765153 # ok 1983 # SKIP SVE set SVE get FPSIMD for VL 7920
3711 10:53:38.765437 # ok 1984 # SKIP SVE set FPSIMD get SVE for VL 7920
3712 10:53:38.765521 # ok 1985 Set SVE VL 7936
3713 10:53:38.765613 # ok 1986 # SKIP SVE set SVE get SVE for VL 7936
3714 10:53:38.765713 # ok 1987 # SKIP SVE set SVE get FPSIMD for VL 7936
3715 10:53:38.765987 # ok 1988 # SKIP SVE set FPSIMD get SVE for VL 7936
3716 10:53:38.766071 # ok 1989 Set SVE VL 7952
3717 10:53:38.766162 # ok 1990 # SKIP SVE set SVE get SVE for VL 7952
3718 10:53:38.766253 # ok 1991 # SKIP SVE set SVE get FPSIMD for VL 7952
3719 10:53:38.766527 # ok 1992 # SKIP SVE set FPSIMD get SVE for VL 7952
3720 10:53:38.766611 # ok 1993 Set SVE VL 7968
3721 10:53:38.766702 # ok 1994 # SKIP SVE set SVE get SVE for VL 7968
3722 10:53:38.766794 # ok 1995 # SKIP SVE set SVE get FPSIMD for VL 7968
3723 10:53:38.766890 # ok 1996 # SKIP SVE set FPSIMD get SVE for VL 7968
3724 10:53:38.767165 # ok 1997 Set SVE VL 7984
3725 10:53:38.767248 # ok 1998 # SKIP SVE set SVE get SVE for VL 7984
3726 10:53:38.767339 # ok 1999 # SKIP SVE set SVE get FPSIMD for VL 7984
3727 10:53:38.767432 # ok 2000 # SKIP SVE set FPSIMD get SVE for VL 7984
3728 10:53:38.767524 # ok 2001 Set SVE VL 8000
3729 10:53:38.767797 # ok 2002 # SKIP SVE set SVE get SVE for VL 8000
3730 10:53:38.767897 # ok 2003 # SKIP SVE set SVE get FPSIMD for VL 8000
3731 10:53:38.768170 # ok 2004 # SKIP SVE set FPSIMD get SVE for VL 8000
3732 10:53:38.768253 # ok 2005 Set SVE VL 8016
3733 10:53:38.768345 # ok 2006 # SKIP SVE set SVE get SVE for VL 8016
3734 10:53:38.768452 # ok 2007 # SKIP SVE set SVE get FPSIMD for VL 8016
3735 10:53:38.768727 # ok 2008 # SKIP SVE set FPSIMD get SVE for VL 8016
3736 10:53:38.768810 # ok 2009 Set SVE VL 8032
3737 10:53:38.768906 # ok 2010 # SKIP SVE set SVE get SVE for VL 8032
3738 10:53:38.768999 # ok 2011 # SKIP SVE set SVE get FPSIMD for VL 8032
3739 10:53:38.769273 # ok 2012 # SKIP SVE set FPSIMD get SVE for VL 8032
3740 10:53:38.769356 # ok 2013 Set SVE VL 8048
3741 10:53:38.769447 # ok 2014 # SKIP SVE set SVE get SVE for VL 8048
3742 10:53:38.769541 # ok 2015 # SKIP SVE set SVE get FPSIMD for VL 8048
3743 10:53:38.769847 # ok 2016 # SKIP SVE set FPSIMD get SVE for VL 8048
3744 10:53:38.769965 # ok 2017 Set SVE VL 8064
3745 10:53:38.770075 # ok 2018 # SKIP SVE set SVE get SVE for VL 8064
3746 10:53:38.770169 # ok 2019 # SKIP SVE set SVE get FPSIMD for VL 8064
3747 10:53:38.770275 # ok 2020 # SKIP SVE set FPSIMD get SVE for VL 8064
3748 10:53:38.770382 # ok 2021 Set SVE VL 8080
3749 10:53:38.770472 # ok 2022 # SKIP SVE set SVE get SVE for VL 8080
3750 10:53:38.770577 # ok 2023 # SKIP SVE set SVE get FPSIMD for VL 8080
3751 10:53:38.770873 # ok 2024 # SKIP SVE set FPSIMD get SVE for VL 8080
3752 10:53:38.770971 # ok 2025 Set SVE VL 8096
3753 10:53:38.771076 # ok 2026 # SKIP SVE set SVE get SVE for VL 8096
3754 10:53:38.771169 # ok 2027 # SKIP SVE set SVE get FPSIMD for VL 8096
3755 10:53:38.771272 # ok 2028 # SKIP SVE set FPSIMD get SVE for VL 8096
3756 10:53:38.771381 # ok 2029 Set SVE VL 8112
3757 10:53:38.771487 # ok 2030 # SKIP SVE set SVE get SVE for VL 8112
3758 10:53:38.771781 # ok 2031 # SKIP SVE set SVE get FPSIMD for VL 8112
3759 10:53:38.772078 # ok 2032 # SKIP SVE set FPSIMD get SVE for VL 8112
3760 10:53:38.772164 # ok 2033 Set SVE VL 8128
3761 10:53:38.772258 # ok 2034 # SKIP SVE set SVE get SVE for VL 8128
3762 10:53:38.772541 # ok 2035 # SKIP SVE set SVE get FPSIMD for VL 8128
3763 10:53:38.772636 # ok 2036 # SKIP SVE set FPSIMD get SVE for VL 8128
3764 10:53:38.772726 # ok 2037 Set SVE VL 8144
3765 10:53:38.772832 # ok 2038 # SKIP SVE set SVE get SVE for VL 8144
3766 10:53:38.772928 # ok 2039 # SKIP SVE set SVE get FPSIMD for VL 8144
3767 10:53:38.773031 # ok 2040 # SKIP SVE set FPSIMD get SVE for VL 8144
3768 10:53:38.773136 # ok 2041 Set SVE VL 8160
3769 10:53:38.773242 # ok 2042 # SKIP SVE set SVE get SVE for VL 8160
3770 10:53:38.773537 # ok 2043 # SKIP SVE set SVE get FPSIMD for VL 8160
3771 10:53:38.773633 # ok 2044 # SKIP SVE set FPSIMD get SVE for VL 8160
3772 10:53:38.773756 # ok 2045 Set SVE VL 8176
3773 10:53:38.773882 # ok 2046 # SKIP SVE set SVE get SVE for VL 8176
3774 10:53:38.774178 # ok 2047 # SKIP SVE set SVE get FPSIMD for VL 8176
3775 10:53:38.774275 # ok 2048 # SKIP SVE set FPSIMD get SVE for VL 8176
3776 10:53:38.774382 # ok 2049 Set SVE VL 8192
3777 10:53:38.774474 # ok 2050 # SKIP SVE set SVE get SVE for VL 8192
3778 10:53:38.774577 # ok 2051 # SKIP SVE set SVE get FPSIMD for VL 8192
3779 10:53:38.774677 # ok 2052 # SKIP SVE set FPSIMD get SVE for VL 8192
3780 10:53:38.774791 # ok 2053 Streaming SVE FPSIMD set via SVE: 0
3781 10:53:38.775086 # ok 2054 Streaming SVE get_fpsimd() gave same state
3782 10:53:38.775197 # ok 2055 Streaming SVE SVE_PT_VL_INHERIT set
3783 10:53:38.775311 # ok 2056 Streaming SVE SVE_PT_VL_INHERIT cleared
3784 10:53:38.775418 # ok 2057 Set Streaming SVE VL 16
3785 10:53:38.775524 # ok 2058 Set and get Streaming SVE data for VL 16
3786 10:53:38.775999 # ok 2059 Set and get FPSIMD data for Streaming SVE VL 16
3787 10:53:38.776111 # ok 2060 Set FPSIMD, read via SVE for Streaming SVE VL 16
3788 10:53:38.776205 # ok 2061 Set Streaming SVE VL 32
3789 10:53:38.776497 # ok 2062 Set and get Streaming SVE data for VL 32
3790 10:53:38.776593 # ok 2063 Set and get FPSIMD data for Streaming SVE VL 32
3791 10:53:38.776698 # ok 2064 Set FPSIMD, read via SVE for Streaming SVE VL 32
3792 10:53:38.776785 # ok 2065 Set Streaming SVE VL 48
3793 10:53:38.777058 # ok 2066 # SKIP Streaming SVE set SVE get SVE for VL 48
3794 10:53:38.777148 # ok 2067 # SKIP Streaming SVE set SVE get FPSIMD for VL 48
3795 10:53:38.777248 # ok 2068 # SKIP Streaming SVE set FPSIMD get SVE for VL 48
3796 10:53:38.777350 # ok 2069 Set Streaming SVE VL 64
3797 10:53:38.777455 # ok 2070 Set and get Streaming SVE data for VL 64
3798 10:53:38.777567 # ok 2071 Set and get FPSIMD data for Streaming SVE VL 64
3799 10:53:38.777864 # ok 2072 Set FPSIMD, read via SVE for Streaming SVE VL 64
3800 10:53:38.777949 # ok 2073 Set Streaming SVE VL 80
3801 10:53:38.778038 # ok 2074 # SKIP Streaming SVE set SVE get SVE for VL 80
3802 10:53:38.778140 # ok 2075 # SKIP Streaming SVE set SVE get FPSIMD for VL 80
3803 10:53:38.778430 # ok 2076 # SKIP Streaming SVE set FPSIMD get SVE for VL 80
3804 10:53:38.778528 # ok 2077 Set Streaming SVE VL 96
3805 10:53:38.778620 # ok 2078 # SKIP Streaming SVE set SVE get SVE for VL 96
3806 10:53:38.778899 # ok 2079 # SKIP Streaming SVE set SVE get FPSIMD for VL 96
3807 10:53:38.778994 # ok 2080 # SKIP Streaming SVE set FPSIMD get SVE for VL 96
3808 10:53:38.779275 # ok 2081 Set Streaming SVE VL 112
3809 10:53:38.779358 # ok 2082 # SKIP Streaming SVE set SVE get SVE for VL 112
3810 10:53:38.779448 # ok 2083 # SKIP Streaming SVE set SVE get FPSIMD for VL 112
3811 10:53:38.779540 # ok 2084 # SKIP Streaming SVE set FPSIMD get SVE for VL 112
3812 10:53:38.779815 # ok 2085 Set Streaming SVE VL 128
3813 10:53:38.780100 # ok 2086 Set and get Streaming SVE data for VL 128
3814 10:53:38.780182 # ok 2087 Set and get FPSIMD data for Streaming SVE VL 128
3815 10:53:38.780271 # ok 2088 Set FPSIMD, read via SVE for Streaming SVE VL 128
3816 10:53:38.780376 # ok 2089 Set Streaming SVE VL 144
3817 10:53:38.780490 # ok 2090 # SKIP Streaming SVE set SVE get SVE for VL 144
3818 10:53:38.780786 # ok 2091 # SKIP Streaming SVE set SVE get FPSIMD for VL 144
3819 10:53:38.780886 # ok 2092 # SKIP Streaming SVE set FPSIMD get SVE for VL 144
3820 10:53:38.780968 # ok 2093 Set Streaming SVE VL 160
3821 10:53:38.781066 # ok 2094 # SKIP Streaming SVE set SVE get SVE for VL 160
3822 10:53:38.781342 # ok 2095 # SKIP Streaming SVE set SVE get FPSIMD for VL 160
3823 10:53:38.781442 # ok 2096 # SKIP Streaming SVE set FPSIMD get SVE for VL 160
3824 10:53:38.781539 # ok 2097 Set Streaming SVE VL 176
3825 10:53:38.781630 # ok 2098 # SKIP Streaming SVE set SVE get SVE for VL 176
3826 10:53:38.782099 # ok 2099 # SKIP Streaming SVE set SVE get FPSIMD for VL 176
3827 10:53:38.782183 # ok 2100 # SKIP Streaming SVE set FPSIMD get SVE for VL 176
3828 10:53:38.782274 # ok 2101 Set Streaming SVE VL 192
3829 10:53:38.782355 # ok 2102 # SKIP Streaming SVE set SVE get SVE for VL 192
3830 10:53:38.782627 # ok 2103 # SKIP Streaming SVE set SVE get FPSIMD for VL 192
3831 10:53:38.782708 # ok 2104 # SKIP Streaming SVE set FPSIMD get SVE for VL 192
3832 10:53:38.782796 # ok 2105 Set Streaming SVE VL 208
3833 10:53:38.782886 # ok 2106 # SKIP Streaming SVE set SVE get SVE for VL 208
3834 10:53:38.783158 # ok 2107 # SKIP Streaming SVE set SVE get FPSIMD for VL 208
3835 10:53:38.783252 # ok 2108 # SKIP Streaming SVE set FPSIMD get SVE for VL 208
3836 10:53:38.783340 # ok 2109 Set Streaming SVE VL 224
3837 10:53:38.783611 # ok 2110 # SKIP Streaming SVE set SVE get SVE for VL 224
3838 10:53:38.783705 # ok 2111 # SKIP Streaming SVE set SVE get FPSIMD for VL 224
3839 10:53:38.783971 # ok 2112 # SKIP Streaming SVE set FPSIMD get SVE for VL 224
3840 10:53:38.784062 # ok 2113 Set Streaming SVE VL 240
3841 10:53:38.784331 # ok 2114 # SKIP Streaming SVE set SVE get SVE for VL 240
3842 10:53:38.784422 # ok 2115 # SKIP Streaming SVE set SVE get FPSIMD for VL 240
3843 10:53:38.784697 # ok 2116 # SKIP Streaming SVE set FPSIMD get SVE for VL 240
3844 10:53:38.784783 # ok 2117 Set Streaming SVE VL 256
3845 10:53:38.784880 # ok 2118 Set and get Streaming SVE data for VL 256
3846 10:53:38.784972 # ok 2119 Set and get FPSIMD data for Streaming SVE VL 256
3847 10:53:38.785242 # ok 2120 Set FPSIMD, read via SVE for Streaming SVE VL 256
3848 10:53:38.785324 # ok 2121 Set Streaming SVE VL 272
3849 10:53:38.785413 # ok 2122 # SKIP Streaming SVE set SVE get SVE for VL 272
3850 10:53:38.785692 # ok 2123 # SKIP Streaming SVE set SVE get FPSIMD for VL 272
3851 10:53:38.785789 # ok 2124 # SKIP Streaming SVE set FPSIMD get SVE for VL 272
3852 10:53:38.785881 # ok 2125 Set Streaming SVE VL 288
3853 10:53:38.789096 # ok 2126 # SKIP Streaming SVE set SVE get SVE for VL 288
3854 10:53:38.789312 # ok 2127 # SKIP Streaming SVE set SVE get FPSIMD for VL 288
3855 10:53:38.789407 # ok 2128 # SKIP Streaming SVE set FPSIMD get SVE for VL 288
3856 10:53:38.789488 # ok 2129 Set Streaming SVE VL 304
3857 10:53:38.789590 # ok 2130 # SKIP Streaming SVE set SVE get SVE for VL 304
3858 10:53:38.789696 # ok 2131 # SKIP Streaming SVE set SVE get FPSIMD for VL 304
3859 10:53:38.789973 # ok 2132 # SKIP Streaming SVE set FPSIMD get SVE for VL 304
3860 10:53:38.790056 # ok 2133 Set Streaming SVE VL 320
3861 10:53:38.790328 # ok 2134 # SKIP Streaming SVE set SVE get SVE for VL 320
3862 10:53:38.790423 # ok 2135 # SKIP Streaming SVE set SVE get FPSIMD for VL 320
3863 10:53:38.790696 # ok 2136 # SKIP Streaming SVE set FPSIMD get SVE for VL 320
3864 10:53:38.790780 # ok 2137 Set Streaming SVE VL 336
3865 10:53:38.790870 # ok 2138 # SKIP Streaming SVE set SVE get SVE for VL 336
3866 10:53:38.791149 # ok 2139 # SKIP Streaming SVE set SVE get FPSIMD for VL 336
3867 10:53:38.791246 # ok 2140 # SKIP Streaming SVE set FPSIMD get SVE for VL 336
3868 10:53:38.791340 # ok 2141 Set Streaming SVE VL 352
3869 10:53:38.791439 # ok 2142 # SKIP Streaming SVE set SVE get SVE for VL 352
3870 10:53:38.791714 # ok 2143 # SKIP Streaming SVE set SVE get FPSIMD for VL 352
3871 10:53:38.792342 # ok 2144 # SKIP Streaming SVE set FPSIMD get SVE for VL 352
3872 10:53:38.792439 # ok 2145 Set Streaming SVE VL 368
3873 10:53:38.792710 # ok 2146 # SKIP Streaming SVE set SVE get SVE for VL 368
3874 10:53:38.792804 # ok 2147 # SKIP Streaming SVE set SVE get FPSIMD for VL 368
3875 10:53:38.792894 # ok 2148 # SKIP Streaming SVE set FPSIMD get SVE for VL 368
3876 10:53:38.793172 # ok 2149 Set Streaming SVE VL 384
3877 10:53:38.793268 # ok 2150 # SKIP Streaming SVE set SVE get SVE for VL 384
3878 10:53:38.793360 # ok 2151 # SKIP Streaming SVE set SVE get FPSIMD for VL 384
3879 10:53:38.793461 # ok 2152 # SKIP Streaming SVE set FPSIMD get SVE for VL 384
3880 10:53:38.793754 # ok 2153 Set Streaming SVE VL 400
3881 10:53:38.793870 # ok 2154 # SKIP Streaming SVE set SVE get SVE for VL 400
3882 10:53:38.794220 # ok 2155 # SKIP Streaming SVE set SVE get FPSIMD for VL 400
3883 10:53:38.794342 # ok 2156 # SKIP Streaming SVE set FPSIMD get SVE for VL 400
3884 10:53:38.794791 # ok 2157 Set Streaming SVE VL 416
3885 10:53:38.794893 # ok 2158 # SKIP Streaming SVE set SVE get SVE for VL 416
3886 10:53:38.795068 # ok 2159 # SKIP Streaming SVE set SVE get FPSIMD for VL 416
3887 10:53:38.795153 # ok 2160 # SKIP Streaming SVE set FPSIMD get SVE for VL 416
3888 10:53:38.795250 # ok 2161 Set Streaming SVE VL 432
3889 10:53:38.795331 # ok 2162 # SKIP Streaming SVE set SVE get SVE for VL 432
3890 10:53:38.795422 # ok 2163 # SKIP Streaming SVE set SVE get FPSIMD for VL 432
3891 10:53:38.795604 # ok 2164 # SKIP Streaming SVE set FPSIMD get SVE for VL 432
3892 10:53:38.795736 # ok 2165 Set Streaming SVE VL 448
3893 10:53:38.795859 # ok 2166 # SKIP Streaming SVE set SVE get SVE for VL 448
3894 10:53:38.796118 # ok 2167 # SKIP Streaming SVE set SVE get FPSIMD for VL 448
3895 10:53:38.796395 # ok 2168 # SKIP Streaming SVE set FPSIMD get SVE for VL 448
3896 10:53:38.796629 # ok 2169 Set Streaming SVE VL 464
3897 10:53:38.796896 # ok 2170 # SKIP Streaming SVE set SVE get SVE for VL 464
3898 10:53:38.797264 # ok 2171 # SKIP Streaming SVE set SVE get FPSIMD for VL 464
3899 10:53:38.797419 # ok 2172 # SKIP Streaming SVE set FPSIMD get SVE for VL 464
3900 10:53:38.797509 # ok 2173 Set Streaming SVE VL 480
3901 10:53:38.797591 # ok 2174 # SKIP Streaming SVE set SVE get SVE for VL 480
3902 10:53:38.797688 # ok 2175 # SKIP Streaming SVE set SVE get FPSIMD for VL 480
3903 10:53:38.797787 # ok 2176 # SKIP Streaming SVE set FPSIMD get SVE for VL 480
3904 10:53:38.797868 # ok 2177 Set Streaming SVE VL 496
3905 10:53:38.797944 # ok 2178 # SKIP Streaming SVE set SVE get SVE for VL 496
3906 10:53:38.798021 # ok 2179 # SKIP Streaming SVE set SVE get FPSIMD for VL 496
3907 10:53:38.798112 # ok 2180 # SKIP Streaming SVE set FPSIMD get SVE for VL 496
3908 10:53:38.798191 # ok 2181 Set Streaming SVE VL 512
3909 10:53:38.798281 # ok 2182 # SKIP Streaming SVE set SVE get SVE for VL 512
3910 10:53:38.798372 # ok 2183 # SKIP Streaming SVE set SVE get FPSIMD for VL 512
3911 10:53:38.798927 # ok 2184 # SKIP Streaming SVE set FPSIMD get SVE for VL 512
3912 10:53:38.799190 # ok 2185 Set Streaming SVE VL 528
3913 10:53:38.799647 # ok 2186 # SKIP Streaming SVE set SVE get SVE for VL 528
3914 10:53:38.800027 # ok 2187 # SKIP Streaming SVE set SVE get FPSIMD for VL 528
3915 10:53:38.800172 # ok 2188 # SKIP Streaming SVE set FPSIMD get SVE for VL 528
3916 10:53:38.800333 # ok 2189 Set Streaming SVE VL 544
3917 10:53:38.800579 # ok 2190 # SKIP Streaming SVE set SVE get SVE for VL 544
3918 10:53:38.801231 # ok 2191 # SKIP Streaming SVE set SVE get FPSIMD for VL 544
3919 10:53:38.801527 # ok 2192 # SKIP Streaming SVE set FPSIMD get SVE for VL 544
3920 10:53:38.801813 # ok 2193 Set Streaming SVE VL 560
3921 10:53:38.802207 # ok 2194 # SKIP Streaming SVE set SVE get SVE for VL 560
3922 10:53:38.802392 # ok 2195 # SKIP Streaming SVE set SVE get FPSIMD for VL 560
3923 10:53:38.802479 # ok 2196 # SKIP Streaming SVE set FPSIMD get SVE for VL 560
3924 10:53:38.802581 # ok 2197 Set Streaming SVE VL 576
3925 10:53:38.802735 # ok 2198 # SKIP Streaming SVE set SVE get SVE for VL 576
3926 10:53:38.802824 # ok 2199 # SKIP Streaming SVE set SVE get FPSIMD for VL 576
3927 10:53:38.802902 # ok 2200 # SKIP Streaming SVE set FPSIMD get SVE for VL 576
3928 10:53:38.802979 # ok 2201 Set Streaming SVE VL 592
3929 10:53:38.803086 # ok 2202 # SKIP Streaming SVE set SVE get SVE for VL 592
3930 10:53:38.803168 # ok 2203 # SKIP Streaming SVE set SVE get FPSIMD for VL 592
3931 10:53:38.803245 # ok 2204 # SKIP Streaming SVE set FPSIMD get SVE for VL 592
3932 10:53:38.803323 # ok 2205 Set Streaming SVE VL 608
3933 10:53:38.803398 # ok 2206 # SKIP Streaming SVE set SVE get SVE for VL 608
3934 10:53:38.803581 # ok 2207 # SKIP Streaming SVE set SVE get FPSIMD for VL 608
3935 10:53:38.803776 # ok 2208 # SKIP Streaming SVE set FPSIMD get SVE for VL 608
3936 10:53:38.803876 # ok 2209 Set Streaming SVE VL 624
3937 10:53:38.803960 # ok 2210 # SKIP Streaming SVE set SVE get SVE for VL 624
3938 10:53:38.804037 # ok 2211 # SKIP Streaming SVE set SVE get FPSIMD for VL 624
3939 10:53:38.804113 # ok 2212 # SKIP Streaming SVE set FPSIMD get SVE for VL 624
3940 10:53:38.804190 # ok 2213 Set Streaming SVE VL 640
3941 10:53:38.804266 # ok 2214 # SKIP Streaming SVE set SVE get SVE for VL 640
3942 10:53:38.804366 # ok 2215 # SKIP Streaming SVE set SVE get FPSIMD for VL 640
3943 10:53:38.804446 # ok 2216 # SKIP Streaming SVE set FPSIMD get SVE for VL 640
3944 10:53:38.804524 # ok 2217 Set Streaming SVE VL 656
3945 10:53:38.804602 # ok 2218 # SKIP Streaming SVE set SVE get SVE for VL 656
3946 10:53:38.804678 # ok 2219 # SKIP Streaming SVE set SVE get FPSIMD for VL 656
3947 10:53:38.804888 # ok 2220 # SKIP Streaming SVE set FPSIMD get SVE for VL 656
3948 10:53:38.805041 # ok 2221 Set Streaming SVE VL 672
3949 10:53:38.805129 # ok 2222 # SKIP Streaming SVE set SVE get SVE for VL 672
3950 10:53:38.805225 # ok 2223 # SKIP Streaming SVE set SVE get FPSIMD for VL 672
3951 10:53:38.805305 # ok 2224 # SKIP Streaming SVE set FPSIMD get SVE for VL 672
3952 10:53:38.805517 # ok 2225 Set Streaming SVE VL 688
3953 10:53:38.805614 # ok 2226 # SKIP Streaming SVE set SVE get SVE for VL 688
3954 10:53:38.806309 # ok 2227 # SKIP Streaming SVE set SVE get FPSIMD for VL 688
3955 10:53:38.806497 # ok 2228 # SKIP Streaming SVE set FPSIMD get SVE for VL 688
3956 10:53:38.806650 # ok 2229 Set Streaming SVE VL 704
3957 10:53:38.806776 # ok 2230 # SKIP Streaming SVE set SVE get SVE for VL 704
3958 10:53:38.806914 # ok 2231 # SKIP Streaming SVE set SVE get FPSIMD for VL 704
3959 10:53:38.807003 # ok 2232 # SKIP Streaming SVE set FPSIMD get SVE for VL 704
3960 10:53:38.807081 # ok 2233 Set Streaming SVE VL 720
3961 10:53:38.807157 # ok 2234 # SKIP Streaming SVE set SVE get SVE for VL 720
3962 10:53:38.807253 # ok 2235 # SKIP Streaming SVE set SVE get FPSIMD for VL 720
3963 10:53:38.807334 # ok 2236 # SKIP Streaming SVE set FPSIMD get SVE for VL 720
3964 10:53:38.807412 # ok 2237 Set Streaming SVE VL 736
3965 10:53:38.807592 # ok 2238 # SKIP Streaming SVE set SVE get SVE for VL 736
3966 10:53:38.807877 # ok 2239 # SKIP Streaming SVE set SVE get FPSIMD for VL 736
3967 10:53:38.808016 # ok 2240 # SKIP Streaming SVE set FPSIMD get SVE for VL 736
3968 10:53:38.808198 # ok 2241 Set Streaming SVE VL 752
3969 10:53:38.808404 # ok 2242 # SKIP Streaming SVE set SVE get SVE for VL 752
3970 10:53:38.808601 # ok 2243 # SKIP Streaming SVE set SVE get FPSIMD for VL 752
3971 10:53:38.808775 # ok 2244 # SKIP Streaming SVE set FPSIMD get SVE for VL 752
3972 10:53:38.809112 # ok 2245 Set Streaming SVE VL 768
3973 10:53:38.809208 # ok 2246 # SKIP Streaming SVE set SVE get SVE for VL 768
3974 10:53:38.809287 # ok 2247 # SKIP Streaming SVE set SVE get FPSIMD for VL 768
3975 10:53:38.809365 # ok 2248 # SKIP Streaming SVE set FPSIMD get SVE for VL 768
3976 10:53:38.809442 # ok 2249 Set Streaming SVE VL 784
3977 10:53:38.809519 # ok 2250 # SKIP Streaming SVE set SVE get SVE for VL 784
3978 10:53:38.809595 # ok 2251 # SKIP Streaming SVE set SVE get FPSIMD for VL 784
3979 10:53:38.809690 # ok 2252 # SKIP Streaming SVE set FPSIMD get SVE for VL 784
3980 10:53:38.809785 # ok 2253 Set Streaming SVE VL 800
3981 10:53:38.809864 # ok 2254 # SKIP Streaming SVE set SVE get SVE for VL 800
3982 10:53:38.809942 # ok 2255 # SKIP Streaming SVE set SVE get FPSIMD for VL 800
3983 10:53:38.810020 # ok 2256 # SKIP Streaming SVE set FPSIMD get SVE for VL 800
3984 10:53:38.810113 # ok 2257 Set Streaming SVE VL 816
3985 10:53:38.810192 # ok 2258 # SKIP Streaming SVE set SVE get SVE for VL 816
3986 10:53:38.810283 # ok 2259 # SKIP Streaming SVE set SVE get FPSIMD for VL 816
3987 10:53:38.810601 # ok 2260 # SKIP Streaming SVE set FPSIMD get SVE for VL 816
3988 10:53:38.810700 # ok 2261 Set Streaming SVE VL 832
3989 10:53:38.810780 # ok 2262 # SKIP Streaming SVE set SVE get SVE for VL 832
3990 10:53:38.810871 # ok 2263 # SKIP Streaming SVE set SVE get FPSIMD for VL 832
3991 10:53:38.811175 # ok 2264 # SKIP Streaming SVE set FPSIMD get SVE for VL 832
3992 10:53:38.811315 # ok 2265 Set Streaming SVE VL 848
3993 10:53:38.811452 # ok 2266 # SKIP Streaming SVE set SVE get SVE for VL 848
3994 10:53:38.811608 # ok 2267 # SKIP Streaming SVE set SVE get FPSIMD for VL 848
3995 10:53:38.811759 # ok 2268 # SKIP Streaming SVE set FPSIMD get SVE for VL 848
3996 10:53:38.811892 # ok 2269 Set Streaming SVE VL 864
3997 10:53:38.812013 # ok 2270 # SKIP Streaming SVE set SVE get SVE for VL 864
3998 10:53:38.812625 # ok 2271 # SKIP Streaming SVE set SVE get FPSIMD for VL 864
3999 10:53:38.812734 # ok 2272 # SKIP Streaming SVE set FPSIMD get SVE for VL 864
4000 10:53:38.812815 # ok 2273 Set Streaming SVE VL 880
4001 10:53:38.812892 # ok 2274 # SKIP Streaming SVE set SVE get SVE for VL 880
4002 10:53:38.812969 # ok 2275 # SKIP Streaming SVE set SVE get FPSIMD for VL 880
4003 10:53:38.813045 # ok 2276 # SKIP Streaming SVE set FPSIMD get SVE for VL 880
4004 10:53:38.813122 # ok 2277 Set Streaming SVE VL 896
4005 10:53:38.813198 # ok 2278 # SKIP Streaming SVE set SVE get SVE for VL 896
4006 10:53:38.817234 # ok 2279 # SKIP Streaming SVE set SVE get FPSIMD for VL 896
4007 10:53:38.818075 # ok 2280 # SKIP Streaming SVE set FPSIMD get SVE for VL 896
4008 10:53:38.818176 # ok 2281 Set Streaming SVE VL 912
4009 10:53:38.818257 # ok 2282 # SKIP Streaming SVE set SVE get SVE for VL 912
4010 10:53:38.818336 # ok 2283 # SKIP Streaming SVE set SVE get FPSIMD for VL 912
4011 10:53:38.818413 # ok 2284 # SKIP Streaming SVE set FPSIMD get SVE for VL 912
4012 10:53:38.818490 # ok 2285 Set Streaming SVE VL 928
4013 10:53:38.818567 # ok 2286 # SKIP Streaming SVE set SVE get SVE for VL 928
4014 10:53:38.818644 # ok 2287 # SKIP Streaming SVE set SVE get FPSIMD for VL 928
4015 10:53:38.818739 # ok 2288 # SKIP Streaming SVE set FPSIMD get SVE for VL 928
4016 10:53:38.818819 # ok 2289 Set Streaming SVE VL 944
4017 10:53:38.818896 # ok 2290 # SKIP Streaming SVE set SVE get SVE for VL 944
4018 10:53:38.818973 # ok 2291 # SKIP Streaming SVE set SVE get FPSIMD for VL 944
4019 10:53:38.819050 # ok 2292 # SKIP Streaming SVE set FPSIMD get SVE for VL 944
4020 10:53:38.819127 # ok 2293 Set Streaming SVE VL 960
4021 10:53:38.819219 # ok 2294 # SKIP Streaming SVE set SVE get SVE for VL 960
4022 10:53:38.819298 # ok 2295 # SKIP Streaming SVE set SVE get FPSIMD for VL 960
4023 10:53:38.819389 # ok 2296 # SKIP Streaming SVE set FPSIMD get SVE for VL 960
4024 10:53:38.819469 # ok 2297 Set Streaming SVE VL 976
4025 10:53:38.819761 # ok 2298 # SKIP Streaming SVE set SVE get SVE for VL 976
4026 10:53:38.819863 # ok 2299 # SKIP Streaming SVE set SVE get FPSIMD for VL 976
4027 10:53:38.819944 # ok 2300 # SKIP Streaming SVE set FPSIMD get SVE for VL 976
4028 10:53:38.821080 # ok 2301 Set Streaming SVE VL 992
4029 10:53:38.821252 # ok 2302 # SKIP Streaming SVE set SVE get SVE for VL 992
4030 10:53:38.821400 # ok 2303 # SKIP Streaming SVE set SVE get FPSIMD for VL 992
4031 10:53:38.821508 # ok 2304 # SKIP Streaming SVE set FPSIMD get SVE for VL 992
4032 10:53:38.821588 # ok 2305 Set Streaming SVE VL 1008
4033 10:53:38.821674 # ok 2306 # SKIP Streaming SVE set SVE get SVE for VL 1008
4034 10:53:38.821752 # ok 2307 # SKIP Streaming SVE set SVE get FPSIMD for VL 1008
4035 10:53:38.821829 # ok 2308 # SKIP Streaming SVE set FPSIMD get SVE for VL 1008
4036 10:53:38.821906 # ok 2309 Set Streaming SVE VL 1024
4037 10:53:38.822197 # ok 2310 # SKIP Streaming SVE set SVE get SVE for VL 1024
4038 10:53:38.822298 # ok 2311 # SKIP Streaming SVE set SVE get FPSIMD for VL 1024
4039 10:53:38.822379 # ok 2312 # SKIP Streaming SVE set FPSIMD get SVE for VL 1024
4040 10:53:38.822458 # ok 2313 Set Streaming SVE VL 1040
4041 10:53:38.822535 # ok 2314 # SKIP Streaming SVE set SVE get SVE for VL 1040
4042 10:53:38.822612 # ok 2315 # SKIP Streaming SVE set SVE get FPSIMD for VL 1040
4043 10:53:38.822689 # ok 2316 # SKIP Streaming SVE set FPSIMD get SVE for VL 1040
4044 10:53:38.822766 # ok 2317 Set Streaming SVE VL 1056
4045 10:53:38.822843 # ok 2318 # SKIP Streaming SVE set SVE get SVE for VL 1056
4046 10:53:38.823553 # ok 2319 # SKIP Streaming SVE set SVE get FPSIMD for VL 1056
4047 10:53:38.823658 # ok 2320 # SKIP Streaming SVE set FPSIMD get SVE for VL 1056
4048 10:53:38.823740 # ok 2321 Set Streaming SVE VL 1072
4049 10:53:38.823817 # ok 2322 # SKIP Streaming SVE set SVE get SVE for VL 1072
4050 10:53:38.823894 # ok 2323 # SKIP Streaming SVE set SVE get FPSIMD for VL 1072
4051 10:53:38.823970 # ok 2324 # SKIP Streaming SVE set FPSIMD get SVE for VL 1072
4052 10:53:38.824047 # ok 2325 Set Streaming SVE VL 1088
4053 10:53:38.824123 # ok 2326 # SKIP Streaming SVE set SVE get SVE for VL 1088
4054 10:53:38.824200 # ok 2327 # SKIP Streaming SVE set SVE get FPSIMD for VL 1088
4055 10:53:38.824277 # ok 2328 # SKIP Streaming SVE set FPSIMD get SVE for VL 1088
4056 10:53:38.824379 # ok 2329 Set Streaming SVE VL 1104
4057 10:53:38.824460 # ok 2330 # SKIP Streaming SVE set SVE get SVE for VL 1104
4058 10:53:38.824620 # ok 2331 # SKIP Streaming SVE set SVE get FPSIMD for VL 1104
4059 10:53:38.824777 # ok 2332 # SKIP Streaming SVE set FPSIMD get SVE for VL 1104
4060 10:53:38.824863 # ok 2333 Set Streaming SVE VL 1120
4061 10:53:38.824977 # ok 2334 # SKIP Streaming SVE set SVE get SVE for VL 1120
4062 10:53:38.825227 # ok 2335 # SKIP Streaming SVE set SVE get FPSIMD for VL 1120
4063 10:53:38.825392 # ok 2336 # SKIP Streaming SVE set FPSIMD get SVE for VL 1120
4064 10:53:38.825485 # ok 2337 Set Streaming SVE VL 1136
4065 10:53:38.825581 # ok 2338 # SKIP Streaming SVE set SVE get SVE for VL 1136
4066 10:53:38.825672 # ok 2339 # SKIP Streaming SVE set SVE get FPSIMD for VL 1136
4067 10:53:38.825751 # ok 2340 # SKIP Streaming SVE set FPSIMD get SVE for VL 1136
4068 10:53:38.825829 # ok 2341 Set Streaming SVE VL 1152
4069 10:53:38.825948 # ok 2342 # SKIP Streaming SVE set SVE get SVE for VL 1152
4070 10:53:38.826043 # ok 2343 # SKIP Streaming SVE set SVE get FPSIMD for VL 1152
4071 10:53:38.826669 # ok 2344 # SKIP Streaming SVE set FPSIMD get SVE for VL 1152
4072 10:53:38.826769 # ok 2345 Set Streaming SVE VL 1168
4073 10:53:38.826860 # ok 2346 # SKIP Streaming SVE set SVE get SVE for VL 1168
4074 10:53:38.826938 # ok 2347 # SKIP Streaming SVE set SVE get FPSIMD for VL 1168
4075 10:53:38.827015 # ok 2348 # SKIP Streaming SVE set FPSIMD get SVE for VL 1168
4076 10:53:38.827092 # ok 2349 Set Streaming SVE VL 1184
4077 10:53:38.827169 # ok 2350 # SKIP Streaming SVE set SVE get SVE for VL 1184
4078 10:53:38.827262 # ok 2351 # SKIP Streaming SVE set SVE get FPSIMD for VL 1184
4079 10:53:38.827342 # ok 2352 # SKIP Streaming SVE set FPSIMD get SVE for VL 1184
4080 10:53:38.827419 # ok 2353 Set Streaming SVE VL 1200
4081 10:53:38.827496 # ok 2354 # SKIP Streaming SVE set SVE get SVE for VL 1200
4082 10:53:38.827587 # ok 2355 # SKIP Streaming SVE set SVE get FPSIMD for VL 1200
4083 10:53:38.827679 # ok 2356 # SKIP Streaming SVE set FPSIMD get SVE for VL 1200
4084 10:53:38.827759 # ok 2357 Set Streaming SVE VL 1216
4085 10:53:38.828081 # ok 2358 # SKIP Streaming SVE set SVE get SVE for VL 1216
4086 10:53:38.828284 # ok 2359 # SKIP Streaming SVE set SVE get FPSIMD for VL 1216
4087 10:53:38.828379 # ok 2360 # SKIP Streaming SVE set FPSIMD get SVE for VL 1216
4088 10:53:38.828535 # ok 2361 Set Streaming SVE VL 1232
4089 10:53:38.828953 # ok 2362 # SKIP Streaming SVE set SVE get SVE for VL 1232
4090 10:53:38.829103 # ok 2363 # SKIP Streaming SVE set SVE get FPSIMD for VL 1232
4091 10:53:38.829222 # ok 2364 # SKIP Streaming SVE set FPSIMD get SVE for VL 1232
4092 10:53:38.829716 # ok 2365 Set Streaming SVE VL 1248
4093 10:53:38.829922 # ok 2366 # SKIP Streaming SVE set SVE get SVE for VL 1248
4094 10:53:38.830015 # ok 2367 # SKIP Streaming SVE set SVE get FPSIMD for VL 1248
4095 10:53:38.830096 # ok 2368 # SKIP Streaming SVE set FPSIMD get SVE for VL 1248
4096 10:53:38.830173 # ok 2369 Set Streaming SVE VL 1264
4097 10:53:38.830268 # ok 2370 # SKIP Streaming SVE set SVE get SVE for VL 1264
4098 10:53:38.830348 # ok 2371 # SKIP Streaming SVE set SVE get FPSIMD for VL 1264
4099 10:53:38.830425 # ok 2372 # SKIP Streaming SVE set FPSIMD get SVE for VL 1264
4100 10:53:38.830502 # ok 2373 Set Streaming SVE VL 1280
4101 10:53:38.830593 # ok 2374 # SKIP Streaming SVE set SVE get SVE for VL 1280
4102 10:53:38.830673 # ok 2375 # SKIP Streaming SVE set SVE get FPSIMD for VL 1280
4103 10:53:38.830764 # ok 2376 # SKIP Streaming SVE set FPSIMD get SVE for VL 1280
4104 10:53:38.830845 # ok 2377 Set Streaming SVE VL 1296
4105 10:53:38.830935 # ok 2378 # SKIP Streaming SVE set SVE get SVE for VL 1296
4106 10:53:38.831027 # ok 2379 # SKIP Streaming SVE set SVE get FPSIMD for VL 1296
4107 10:53:38.831343 # ok 2380 # SKIP Streaming SVE set FPSIMD get SVE for VL 1296
4108 10:53:38.831484 # ok 2381 Set Streaming SVE VL 1312
4109 10:53:38.831578 # ok 2382 # SKIP Streaming SVE set SVE get SVE for VL 1312
4110 10:53:38.831657 # ok 2383 # SKIP Streaming SVE set SVE get FPSIMD for VL 1312
4111 10:53:38.831747 # ok 2384 # SKIP Streaming SVE set FPSIMD get SVE for VL 1312
4112 10:53:38.831839 # ok 2385 Set Streaming SVE VL 1328
4113 10:53:38.832095 # ok 2386 # SKIP Streaming SVE set SVE get SVE for VL 1328
4114 10:53:38.832254 # ok 2387 # SKIP Streaming SVE set SVE get FPSIMD for VL 1328
4115 10:53:38.832370 # ok 2388 # SKIP Streaming SVE set FPSIMD get SVE for VL 1328
4116 10:53:38.832463 # ok 2389 Set Streaming SVE VL 1344
4117 10:53:38.832554 # ok 2390 # SKIP Streaming SVE set SVE get SVE for VL 1344
4118 10:53:38.832819 # ok 2391 # SKIP Streaming SVE set SVE get FPSIMD for VL 1344
4119 10:53:38.832962 # ok 2392 # SKIP Streaming SVE set FPSIMD get SVE for VL 1344
4120 10:53:38.833122 # ok 2393 Set Streaming SVE VL 1360
4121 10:53:38.833276 # ok 2394 # SKIP Streaming SVE set SVE get SVE for VL 1360
4122 10:53:38.833438 # ok 2395 # SKIP Streaming SVE set SVE get FPSIMD for VL 1360
4123 10:53:38.833577 # ok 2396 # SKIP Streaming SVE set FPSIMD get SVE for VL 1360
4124 10:53:38.833757 # ok 2397 Set Streaming SVE VL 1376
4125 10:53:38.861880 # ok 2398 # SKIP Streaming SVE set SVE get SVE for VL 1376
4126 10:53:38.862097 # ok 2399 # SKIP Streaming SVE set SVE get FPSIMD for VL 1376
4127 10:53:38.862225 # ok 2400 # SKIP Streaming SVE set FPSIMD get SVE for VL 1376
4128 10:53:38.862305 # ok 2401 Set Streaming SVE VL 1392
4129 10:53:38.862379 # ok 2402 # SKIP Streaming SVE set SVE get SVE for VL 1392
4130 10:53:38.862451 # ok 2403 # SKIP Streaming SVE set SVE get FPSIMD for VL 1392
4131 10:53:38.862524 # ok 2404 # SKIP Streaming SVE set FPSIMD get SVE for VL 1392
4132 10:53:38.862599 # ok 2405 Set Streaming SVE VL 1408
4133 10:53:38.862674 # ok 2406 # SKIP Streaming SVE set SVE get SVE for VL 1408
4134 10:53:38.862742 # ok 2407 # SKIP Streaming SVE set SVE get FPSIMD for VL 1408
4135 10:53:38.862802 # ok 2408 # SKIP Streaming SVE set FPSIMD get SVE for VL 1408
4136 10:53:38.862861 # ok 2409 Set Streaming SVE VL 1424
4137 10:53:38.862920 # ok 2410 # SKIP Streaming SVE set SVE get SVE for VL 1424
4138 10:53:38.862979 # ok 2411 # SKIP Streaming SVE set SVE get FPSIMD for VL 1424
4139 10:53:38.863037 # ok 2412 # SKIP Streaming SVE set FPSIMD get SVE for VL 1424
4140 10:53:38.863096 # ok 2413 Set Streaming SVE VL 1440
4141 10:53:38.863155 # ok 2414 # SKIP Streaming SVE set SVE get SVE for VL 1440
4142 10:53:38.863213 # ok 2415 # SKIP Streaming SVE set SVE get FPSIMD for VL 1440
4143 10:53:38.863272 # ok 2416 # SKIP Streaming SVE set FPSIMD get SVE for VL 1440
4144 10:53:38.863329 # ok 2417 Set Streaming SVE VL 1456
4145 10:53:38.863388 # ok 2418 # SKIP Streaming SVE set SVE get SVE for VL 1456
4146 10:53:38.863447 # ok 2419 # SKIP Streaming SVE set SVE get FPSIMD for VL 1456
4147 10:53:38.863505 # ok 2420 # SKIP Streaming SVE set FPSIMD get SVE for VL 1456
4148 10:53:38.863565 # ok 2421 Set Streaming SVE VL 1472
4149 10:53:38.863623 # ok 2422 # SKIP Streaming SVE set SVE get SVE for VL 1472
4150 10:53:38.863682 # ok 2423 # SKIP Streaming SVE set SVE get FPSIMD for VL 1472
4151 10:53:38.863741 # ok 2424 # SKIP Streaming SVE set FPSIMD get SVE for VL 1472
4152 10:53:38.863799 # ok 2425 Set Streaming SVE VL 1488
4153 10:53:38.863858 # ok 2426 # SKIP Streaming SVE set SVE get SVE for VL 1488
4154 10:53:38.864118 # ok 2427 # SKIP Streaming SVE set SVE get FPSIMD for VL 1488
4155 10:53:38.864184 # ok 2428 # SKIP Streaming SVE set FPSIMD get SVE for VL 1488
4156 10:53:38.864244 # ok 2429 Set Streaming SVE VL 1504
4157 10:53:38.864303 # ok 2430 # SKIP Streaming SVE set SVE get SVE for VL 1504
4158 10:53:38.864362 # ok 2431 # SKIP Streaming SVE set SVE get FPSIMD for VL 1504
4159 10:53:38.864421 # ok 2432 # SKIP Streaming SVE set FPSIMD get SVE for VL 1504
4160 10:53:38.864479 # ok 2433 Set Streaming SVE VL 1520
4161 10:53:38.864538 # ok 2434 # SKIP Streaming SVE set SVE get SVE for VL 1520
4162 10:53:38.864597 # ok 2435 # SKIP Streaming SVE set SVE get FPSIMD for VL 1520
4163 10:53:38.864655 # ok 2436 # SKIP Streaming SVE set FPSIMD get SVE for VL 1520
4164 10:53:38.864714 # ok 2437 Set Streaming SVE VL 1536
4165 10:53:38.864773 # ok 2438 # SKIP Streaming SVE set SVE get SVE for VL 1536
4166 10:53:38.864832 # ok 2439 # SKIP Streaming SVE set SVE get FPSIMD for VL 1536
4167 10:53:38.864891 # ok 2440 # SKIP Streaming SVE set FPSIMD get SVE for VL 1536
4168 10:53:38.864950 # ok 2441 Set Streaming SVE VL 1552
4169 10:53:38.865028 # ok 2442 # SKIP Streaming SVE set SVE get SVE for VL 1552
4170 10:53:38.865104 # ok 2443 # SKIP Streaming SVE set SVE get FPSIMD for VL 1552
4171 10:53:38.865168 # ok 2444 # SKIP Streaming SVE set FPSIMD get SVE for VL 1552
4172 10:53:38.865229 # ok 2445 Set Streaming SVE VL 1568
4173 10:53:38.865290 # ok 2446 # SKIP Streaming SVE set SVE get SVE for VL 1568
4174 10:53:38.865353 # ok 2447 # SKIP Streaming SVE set SVE get FPSIMD for VL 1568
4175 10:53:38.865418 # ok 2448 # SKIP Streaming SVE set FPSIMD get SVE for VL 1568
4176 10:53:38.865483 # ok 2449 Set Streaming SVE VL 1584
4177 10:53:38.865543 # ok 2450 # SKIP Streaming SVE set SVE get SVE for VL 1584
4178 10:53:38.865607 # ok 2451 # SKIP Streaming SVE set SVE get FPSIMD for VL 1584
4179 10:53:38.865682 # ok 2452 # SKIP Streaming SVE set FPSIMD get SVE for VL 1584
4180 10:53:38.865758 # ok 2453 Set Streaming SVE VL 1600
4181 10:53:38.865829 # ok 2454 # SKIP Streaming SVE set SVE get SVE for VL 1600
4182 10:53:38.865902 # ok 2455 # SKIP Streaming SVE set SVE get FPSIMD for VL 1600
4183 10:53:38.865976 # ok 2456 # SKIP Streaming SVE set FPSIMD get SVE for VL 1600
4184 10:53:38.866043 # ok 2457 Set Streaming SVE VL 1616
4185 10:53:38.866106 # ok 2458 # SKIP Streaming SVE set SVE get SVE for VL 1616
4186 10:53:38.866170 # ok 2459 # SKIP Streaming SVE set SVE get FPSIMD for VL 1616
4187 10:53:38.866234 # ok 2460 # SKIP Streaming SVE set FPSIMD get SVE for VL 1616
4188 10:53:38.866309 # ok 2461 Set Streaming SVE VL 1632
4189 10:53:38.866568 # ok 2462 # SKIP Streaming SVE set SVE get SVE for VL 1632
4190 10:53:38.866639 # ok 2463 # SKIP Streaming SVE set SVE get FPSIMD for VL 1632
4191 10:53:38.866702 # ok 2464 # SKIP Streaming SVE set FPSIMD get SVE for VL 1632
4192 10:53:38.866764 # ok 2465 Set Streaming SVE VL 1648
4193 10:53:38.866828 # ok 2466 # SKIP Streaming SVE set SVE get SVE for VL 1648
4194 10:53:38.866897 # ok 2467 # SKIP Streaming SVE set SVE get FPSIMD for VL 1648
4195 10:53:38.866968 # ok 2468 # SKIP Streaming SVE set FPSIMD get SVE for VL 1648
4196 10:53:38.867039 # ok 2469 Set Streaming SVE VL 1664
4197 10:53:38.867112 # ok 2470 # SKIP Streaming SVE set SVE get SVE for VL 1664
4198 10:53:38.867180 # ok 2471 # SKIP Streaming SVE set SVE get FPSIMD for VL 1664
4199 10:53:38.867250 # ok 2472 # SKIP Streaming SVE set FPSIMD get SVE for VL 1664
4200 10:53:38.867316 # ok 2473 Set Streaming SVE VL 1680
4201 10:53:38.867388 # ok 2474 # SKIP Streaming SVE set SVE get SVE for VL 1680
4202 10:53:38.867457 # ok 2475 # SKIP Streaming SVE set SVE get FPSIMD for VL 1680
4203 10:53:38.867522 # ok 2476 # SKIP Streaming SVE set FPSIMD get SVE for VL 1680
4204 10:53:38.867594 # ok 2477 Set Streaming SVE VL 1696
4205 10:53:38.867672 # ok 2478 # SKIP Streaming SVE set SVE get SVE for VL 1696
4206 10:53:38.867755 # ok 2479 # SKIP Streaming SVE set SVE get FPSIMD for VL 1696
4207 10:53:38.867836 # ok 2480 # SKIP Streaming SVE set FPSIMD get SVE for VL 1696
4208 10:53:38.867909 # ok 2481 Set Streaming SVE VL 1712
4209 10:53:38.867971 # ok 2482 # SKIP Streaming SVE set SVE get SVE for VL 1712
4210 10:53:38.868029 # ok 2483 # SKIP Streaming SVE set SVE get FPSIMD for VL 1712
4211 10:53:38.868088 # ok 2484 # SKIP Streaming SVE set FPSIMD get SVE for VL 1712
4212 10:53:38.868147 # ok 2485 Set Streaming SVE VL 1728
4213 10:53:38.868205 # ok 2486 # SKIP Streaming SVE set SVE get SVE for VL 1728
4214 10:53:38.868263 # ok 2487 # SKIP Streaming SVE set SVE get FPSIMD for VL 1728
4215 10:53:38.868322 # ok 2488 # SKIP Streaming SVE set FPSIMD get SVE for VL 1728
4216 10:53:38.868380 # ok 2489 Set Streaming SVE VL 1744
4217 10:53:38.868439 # ok 2490 # SKIP Streaming SVE set SVE get SVE for VL 1744
4218 10:53:38.868507 # ok 2491 # SKIP Streaming SVE set SVE get FPSIMD for VL 1744
4219 10:53:38.868583 # ok 2492 # SKIP Streaming SVE set FPSIMD get SVE for VL 1744
4220 10:53:38.868657 # ok 2493 Set Streaming SVE VL 1760
4221 10:53:38.868732 # ok 2494 # SKIP Streaming SVE set SVE get SVE for VL 1760
4222 10:53:38.868809 # ok 2495 # SKIP Streaming SVE set SVE get FPSIMD for VL 1760
4223 10:53:38.868887 # ok 2496 # SKIP Streaming SVE set FPSIMD get SVE for VL 1760
4224 10:53:38.869151 # ok 2497 Set Streaming SVE VL 1776
4225 10:53:38.869230 # ok 2498 # SKIP Streaming SVE set SVE get SVE for VL 1776
4226 10:53:38.869303 # ok 2499 # SKIP Streaming SVE set SVE get FPSIMD for VL 1776
4227 10:53:38.869375 # ok 2500 # SKIP Streaming SVE set FPSIMD get SVE for VL 1776
4228 10:53:38.869443 # ok 2501 Set Streaming SVE VL 1792
4229 10:53:38.869517 # ok 2502 # SKIP Streaming SVE set SVE get SVE for VL 1792
4230 10:53:38.869583 # ok 2503 # SKIP Streaming SVE set SVE get FPSIMD for VL 1792
4231 10:53:38.869664 # ok 2504 # SKIP Streaming SVE set FPSIMD get SVE for VL 1792
4232 10:53:38.869795 # ok 2505 Set Streaming SVE VL 1808
4233 10:53:38.869898 # ok 2506 # SKIP Streaming SVE set SVE get SVE for VL 1808
4234 10:53:38.870005 # ok 2507 # SKIP Streaming SVE set SVE get FPSIMD for VL 1808
4235 10:53:38.870134 # ok 2508 # SKIP Streaming SVE set FPSIMD get SVE for VL 1808
4236 10:53:38.870263 # ok 2509 Set Streaming SVE VL 1824
4237 10:53:38.870358 # ok 2510 # SKIP Streaming SVE set SVE get SVE for VL 1824
4238 10:53:38.870450 # ok 2511 # SKIP Streaming SVE set SVE get FPSIMD for VL 1824
4239 10:53:38.870541 # ok 2512 # SKIP Streaming SVE set FPSIMD get SVE for VL 1824
4240 10:53:38.870629 # ok 2513 Set Streaming SVE VL 1840
4241 10:53:38.870713 # ok 2514 # SKIP Streaming SVE set SVE get SVE for VL 1840
4242 10:53:38.870793 # ok 2515 # SKIP Streaming SVE set SVE get FPSIMD for VL 1840
4243 10:53:38.870872 # ok 2516 # SKIP Streaming SVE set FPSIMD get SVE for VL 1840
4244 10:53:38.870936 # ok 2517 Set Streaming SVE VL 1856
4245 10:53:38.870999 # ok 2518 # SKIP Streaming SVE set SVE get SVE for VL 1856
4246 10:53:38.871080 # ok 2519 # SKIP Streaming SVE set SVE get FPSIMD for VL 1856
4247 10:53:38.871145 # ok 2520 # SKIP Streaming SVE set FPSIMD get SVE for VL 1856
4248 10:53:38.871217 # ok 2521 Set Streaming SVE VL 1872
4249 10:53:38.871281 # ok 2522 # SKIP Streaming SVE set SVE get SVE for VL 1872
4250 10:53:38.871342 # ok 2523 # SKIP Streaming SVE set SVE get FPSIMD for VL 1872
4251 10:53:38.871402 # ok 2524 # SKIP Streaming SVE set FPSIMD get SVE for VL 1872
4252 10:53:38.871463 # ok 2525 Set Streaming SVE VL 1888
4253 10:53:38.871524 # ok 2526 # SKIP Streaming SVE set SVE get SVE for VL 1888
4254 10:53:38.871585 # ok 2527 # SKIP Streaming SVE set SVE get FPSIMD for VL 1888
4255 10:53:38.871655 # ok 2528 # SKIP Streaming SVE set FPSIMD get SVE for VL 1888
4256 10:53:38.871720 # ok 2529 Set Streaming SVE VL 1904
4257 10:53:38.871781 # ok 2530 # SKIP Streaming SVE set SVE get SVE for VL 1904
4258 10:53:38.871854 # ok 2531 # SKIP Streaming SVE set SVE get FPSIMD for VL 1904
4259 10:53:38.872136 # ok 2532 # SKIP Streaming SVE set FPSIMD get SVE for VL 1904
4260 10:53:38.872229 # ok 2533 Set Streaming SVE VL 1920
4261 10:53:38.872307 # ok 2534 # SKIP Streaming SVE set SVE get SVE for VL 1920
4262 10:53:38.872370 # ok 2535 # SKIP Streaming SVE set SVE get FPSIMD for VL 1920
4263 10:53:38.872431 # ok 2536 # SKIP Streaming SVE set FPSIMD get SVE for VL 1920
4264 10:53:38.872493 # ok 2537 Set Streaming SVE VL 1936
4265 10:53:38.872557 # ok 2538 # SKIP Streaming SVE set SVE get SVE for VL 1936
4266 10:53:38.872632 # ok 2539 # SKIP Streaming SVE set SVE get FPSIMD for VL 1936
4267 10:53:38.872712 # ok 2540 # SKIP Streaming SVE set FPSIMD get SVE for VL 1936
4268 10:53:38.872784 # ok 2541 Set Streaming SVE VL 1952
4269 10:53:38.872868 # ok 2542 # SKIP Streaming SVE set SVE get SVE for VL 1952
4270 10:53:38.872949 # ok 2543 # SKIP Streaming SVE set SVE get FPSIMD for VL 1952
4271 10:53:38.873019 # ok 2544 # SKIP Streaming SVE set FPSIMD get SVE for VL 1952
4272 10:53:38.873100 # ok 2545 Set Streaming SVE VL 1968
4273 10:53:38.873184 # ok 2546 # SKIP Streaming SVE set SVE get SVE for VL 1968
4274 10:53:38.873266 # ok 2547 # SKIP Streaming SVE set SVE get FPSIMD for VL 1968
4275 10:53:38.873349 # ok 2548 # SKIP Streaming SVE set FPSIMD get SVE for VL 1968
4276 10:53:38.873430 # ok 2549 Set Streaming SVE VL 1984
4277 10:53:38.873499 # ok 2550 # SKIP Streaming SVE set SVE get SVE for VL 1984
4278 10:53:38.873560 # ok 2551 # SKIP Streaming SVE set SVE get FPSIMD for VL 1984
4279 10:53:38.873625 # ok 2552 # SKIP Streaming SVE set FPSIMD get SVE for VL 1984
4280 10:53:38.873705 # ok 2553 Set Streaming SVE VL 2000
4281 10:53:38.873780 # ok 2554 # SKIP Streaming SVE set SVE get SVE for VL 2000
4282 10:53:38.873860 # ok 2555 # SKIP Streaming SVE set SVE get FPSIMD for VL 2000
4283 10:53:38.873958 # ok 2556 # SKIP Streaming SVE set FPSIMD get SVE for VL 2000
4284 10:53:38.874068 # ok 2557 Set Streaming SVE VL 2016
4285 10:53:38.874188 # ok 2558 # SKIP Streaming SVE set SVE get SVE for VL 2016
4286 10:53:38.874288 # ok 2559 # SKIP Streaming SVE set SVE get FPSIMD for VL 2016
4287 10:53:38.874399 # ok 2560 # SKIP Streaming SVE set FPSIMD get SVE for VL 2016
4288 10:53:38.874474 # ok 2561 Set Streaming SVE VL 2032
4289 10:53:38.874537 # ok 2562 # SKIP Streaming SVE set SVE get SVE for VL 2032
4290 10:53:38.874616 # ok 2563 # SKIP Streaming SVE set SVE get FPSIMD for VL 2032
4291 10:53:38.874683 # ok 2564 # SKIP Streaming SVE set FPSIMD get SVE for VL 2032
4292 10:53:38.874761 # ok 2565 Set Streaming SVE VL 2048
4293 10:53:38.874849 # ok 2566 # SKIP Streaming SVE set SVE get SVE for VL 2048
4294 10:53:38.874945 # ok 2567 # SKIP Streaming SVE set SVE get FPSIMD for VL 2048
4295 10:53:38.875236 # ok 2568 # SKIP Streaming SVE set FPSIMD get SVE for VL 2048
4296 10:53:38.875337 # ok 2569 Set Streaming SVE VL 2064
4297 10:53:38.875418 # ok 2570 # SKIP Streaming SVE set SVE get SVE for VL 2064
4298 10:53:38.875496 # ok 2571 # SKIP Streaming SVE set SVE get FPSIMD for VL 2064
4299 10:53:38.875570 # ok 2572 # SKIP Streaming SVE set FPSIMD get SVE for VL 2064
4300 10:53:38.875643 # ok 2573 Set Streaming SVE VL 2080
4301 10:53:38.875715 # ok 2574 # SKIP Streaming SVE set SVE get SVE for VL 2080
4302 10:53:38.875788 # ok 2575 # SKIP Streaming SVE set SVE get FPSIMD for VL 2080
4303 10:53:38.875860 # ok 2576 # SKIP Streaming SVE set FPSIMD get SVE for VL 2080
4304 10:53:38.875933 # ok 2577 Set Streaming SVE VL 2096
4305 10:53:38.876004 # ok 2578 # SKIP Streaming SVE set SVE get SVE for VL 2096
4306 10:53:38.876077 # ok 2579 # SKIP Streaming SVE set SVE get FPSIMD for VL 2096
4307 10:53:38.876149 # ok 2580 # SKIP Streaming SVE set FPSIMD get SVE for VL 2096
4308 10:53:38.876222 # ok 2581 Set Streaming SVE VL 2112
4309 10:53:38.876294 # ok 2582 # SKIP Streaming SVE set SVE get SVE for VL 2112
4310 10:53:38.876366 # ok 2583 # SKIP Streaming SVE set SVE get FPSIMD for VL 2112
4311 10:53:38.876438 # ok 2584 # SKIP Streaming SVE set FPSIMD get SVE for VL 2112
4312 10:53:38.876510 # ok 2585 Set Streaming SVE VL 2128
4313 10:53:38.876582 # ok 2586 # SKIP Streaming SVE set SVE get SVE for VL 2128
4314 10:53:38.876654 # ok 2587 # SKIP Streaming SVE set SVE get FPSIMD for VL 2128
4315 10:53:38.876727 # ok 2588 # SKIP Streaming SVE set FPSIMD get SVE for VL 2128
4316 10:53:38.876799 # ok 2589 Set Streaming SVE VL 2144
4317 10:53:38.876871 # ok 2590 # SKIP Streaming SVE set SVE get SVE for VL 2144
4318 10:53:38.876943 # ok 2591 # SKIP Streaming SVE set SVE get FPSIMD for VL 2144
4319 10:53:38.877016 # ok 2592 # SKIP Streaming SVE set FPSIMD get SVE for VL 2144
4320 10:53:38.877093 # ok 2593 Set Streaming SVE VL 2160
4321 10:53:38.877164 # ok 2594 # SKIP Streaming SVE set SVE get SVE for VL 2160
4322 10:53:38.877237 # ok 2595 # SKIP Streaming SVE set SVE get FPSIMD for VL 2160
4323 10:53:38.877309 # ok 2596 # SKIP Streaming SVE set FPSIMD get SVE for VL 2160
4324 10:53:38.877381 # ok 2597 Set Streaming SVE VL 2176
4325 10:53:38.877453 # ok 2598 # SKIP Streaming SVE set SVE get SVE for VL 2176
4326 10:53:38.877524 # ok 2599 # SKIP Streaming SVE set SVE get FPSIMD for VL 2176
4327 10:53:38.877596 # ok 2600 # SKIP Streaming SVE set FPSIMD get SVE for VL 2176
4328 10:53:38.878074 # ok 2601 Set Streaming SVE VL 2192
4329 10:53:38.878164 # ok 2602 # SKIP Streaming SVE set SVE get SVE for VL 2192
4330 10:53:38.878443 # ok 2603 # SKIP Streaming SVE set SVE get FPSIMD for VL 2192
4331 10:53:38.878534 # ok 2604 # SKIP Streaming SVE set FPSIMD get SVE for VL 2192
4332 10:53:38.878609 # ok 2605 Set Streaming SVE VL 2208
4333 10:53:38.878700 # ok 2606 # SKIP Streaming SVE set SVE get SVE for VL 2208
4334 10:53:38.878793 # ok 2607 # SKIP Streaming SVE set SVE get FPSIMD for VL 2208
4335 10:53:38.878888 # ok 2608 # SKIP Streaming SVE set FPSIMD get SVE for VL 2208
4336 10:53:38.878967 # ok 2609 Set Streaming SVE VL 2224
4337 10:53:38.879033 # ok 2610 # SKIP Streaming SVE set SVE get SVE for VL 2224
4338 10:53:38.879096 # ok 2611 # SKIP Streaming SVE set SVE get FPSIMD for VL 2224
4339 10:53:38.879159 # ok 2612 # SKIP Streaming SVE set FPSIMD get SVE for VL 2224
4340 10:53:38.879224 # ok 2613 Set Streaming SVE VL 2240
4341 10:53:38.879287 # ok 2614 # SKIP Streaming SVE set SVE get SVE for VL 2240
4342 10:53:38.879350 # ok 2615 # SKIP Streaming SVE set SVE get FPSIMD for VL 2240
4343 10:53:38.879413 # ok 2616 # SKIP Streaming SVE set FPSIMD get SVE for VL 2240
4344 10:53:38.879474 # ok 2617 Set Streaming SVE VL 2256
4345 10:53:38.879538 # ok 2618 # SKIP Streaming SVE set SVE get SVE for VL 2256
4346 10:53:38.879602 # ok 2619 # SKIP Streaming SVE set SVE get FPSIMD for VL 2256
4347 10:53:38.879666 # ok 2620 # SKIP Streaming SVE set FPSIMD get SVE for VL 2256
4348 10:53:38.879731 # ok 2621 Set Streaming SVE VL 2272
4349 10:53:38.879794 # ok 2622 # SKIP Streaming SVE set SVE get SVE for VL 2272
4350 10:53:38.879859 # ok 2623 # SKIP Streaming SVE set SVE get FPSIMD for VL 2272
4351 10:53:38.879924 # ok 2624 # SKIP Streaming SVE set FPSIMD get SVE for VL 2272
4352 10:53:38.879988 # ok 2625 Set Streaming SVE VL 2288
4353 10:53:38.880053 # ok 2626 # SKIP Streaming SVE set SVE get SVE for VL 2288
4354 10:53:38.880119 # ok 2627 # SKIP Streaming SVE set SVE get FPSIMD for VL 2288
4355 10:53:38.880183 # ok 2628 # SKIP Streaming SVE set FPSIMD get SVE for VL 2288
4356 10:53:38.880247 # ok 2629 Set Streaming SVE VL 2304
4357 10:53:38.880309 # ok 2630 # SKIP Streaming SVE set SVE get SVE for VL 2304
4358 10:53:38.880371 # ok 2631 # SKIP Streaming SVE set SVE get FPSIMD for VL 2304
4359 10:53:38.880434 # ok 2632 # SKIP Streaming SVE set FPSIMD get SVE for VL 2304
4360 10:53:38.880504 # ok 2633 Set Streaming SVE VL 2320
4361 10:53:38.880566 # ok 2634 # SKIP Streaming SVE set SVE get SVE for VL 2320
4362 10:53:38.880630 # ok 2635 # SKIP Streaming SVE set SVE get FPSIMD for VL 2320
4363 10:53:38.880706 # ok 2636 # SKIP Streaming SVE set FPSIMD get SVE for VL 2320
4364 10:53:38.880787 # ok 2637 Set Streaming SVE VL 2336
4365 10:53:38.881105 # ok 2638 # SKIP Streaming SVE set SVE get SVE for VL 2336
4366 10:53:38.881217 # ok 2639 # SKIP Streaming SVE set SVE get FPSIMD for VL 2336
4367 10:53:38.881301 # ok 2640 # SKIP Streaming SVE set FPSIMD get SVE for VL 2336
4368 10:53:38.881379 # ok 2641 Set Streaming SVE VL 2352
4369 10:53:38.881455 # ok 2642 # SKIP Streaming SVE set SVE get SVE for VL 2352
4370 10:53:38.881533 # ok 2643 # SKIP Streaming SVE set SVE get FPSIMD for VL 2352
4371 10:53:38.881610 # ok 2644 # SKIP Streaming SVE set FPSIMD get SVE for VL 2352
4372 10:53:38.881697 # ok 2645 Set Streaming SVE VL 2368
4373 10:53:38.881775 # ok 2646 # SKIP Streaming SVE set SVE get SVE for VL 2368
4374 10:53:38.881854 # ok 2647 # SKIP Streaming SVE set SVE get FPSIMD for VL 2368
4375 10:53:38.881933 # ok 2648 # SKIP Streaming SVE set FPSIMD get SVE for VL 2368
4376 10:53:38.882012 # ok 2649 Set Streaming SVE VL 2384
4377 10:53:38.882090 # ok 2650 # SKIP Streaming SVE set SVE get SVE for VL 2384
4378 10:53:38.882169 # ok 2651 # SKIP Streaming SVE set SVE get FPSIMD for VL 2384
4379 10:53:38.882248 # ok 2652 # SKIP Streaming SVE set FPSIMD get SVE for VL 2384
4380 10:53:38.882328 # ok 2653 Set Streaming SVE VL 2400
4381 10:53:38.882407 # ok 2654 # SKIP Streaming SVE set SVE get SVE for VL 2400
4382 10:53:38.882486 # ok 2655 # SKIP Streaming SVE set SVE get FPSIMD for VL 2400
4383 10:53:38.882564 # ok 2656 # SKIP Streaming SVE set FPSIMD get SVE for VL 2400
4384 10:53:38.882643 # ok 2657 Set Streaming SVE VL 2416
4385 10:53:38.882721 # ok 2658 # SKIP Streaming SVE set SVE get SVE for VL 2416
4386 10:53:38.882800 # ok 2659 # SKIP Streaming SVE set SVE get FPSIMD for VL 2416
4387 10:53:38.882878 # ok 2660 # SKIP Streaming SVE set FPSIMD get SVE for VL 2416
4388 10:53:38.882956 # ok 2661 Set Streaming SVE VL 2432
4389 10:53:38.883035 # ok 2662 # SKIP Streaming SVE set SVE get SVE for VL 2432
4390 10:53:38.883118 # ok 2663 # SKIP Streaming SVE set SVE get FPSIMD for VL 2432
4391 10:53:38.883197 # ok 2664 # SKIP Streaming SVE set FPSIMD get SVE for VL 2432
4392 10:53:38.883276 # ok 2665 Set Streaming SVE VL 2448
4393 10:53:38.883354 # ok 2666 # SKIP Streaming SVE set SVE get SVE for VL 2448
4394 10:53:38.883433 # ok 2667 # SKIP Streaming SVE set SVE get FPSIMD for VL 2448
4395 10:53:38.883511 # ok 2668 # SKIP Streaming SVE set FPSIMD get SVE for VL 2448
4396 10:53:38.883589 # ok 2669 Set Streaming SVE VL 2464
4397 10:53:38.883667 # ok 2670 # SKIP Streaming SVE set SVE get SVE for VL 2464
4398 10:53:38.883746 # ok 2671 # SKIP Streaming SVE set SVE get FPSIMD for VL 2464
4399 10:53:38.883824 # ok 2672 # SKIP Streaming SVE set FPSIMD get SVE for VL 2464
4400 10:53:38.884108 # ok 2673 Set Streaming SVE VL 2480
4401 10:53:38.884194 # ok 2674 # SKIP Streaming SVE set SVE get SVE for VL 2480
4402 10:53:38.884275 # ok 2675 # SKIP Streaming SVE set SVE get FPSIMD for VL 2480
4403 10:53:38.884354 # ok 2676 # SKIP Streaming SVE set FPSIMD get SVE for VL 2480
4404 10:53:38.884432 # ok 2677 Set Streaming SVE VL 2496
4405 10:53:38.884511 # ok 2678 # SKIP Streaming SVE set SVE get SVE for VL 2496
4406 10:53:38.884589 # ok 2679 # SKIP Streaming SVE set SVE get FPSIMD for VL 2496
4407 10:53:38.884668 # ok 2680 # SKIP Streaming SVE set FPSIMD get SVE for VL 2496
4408 10:53:38.884747 # ok 2681 Set Streaming SVE VL 2512
4409 10:53:38.884825 # ok 2682 # SKIP Streaming SVE set SVE get SVE for VL 2512
4410 10:53:38.884904 # ok 2683 # SKIP Streaming SVE set SVE get FPSIMD for VL 2512
4411 10:53:38.884984 # ok 2684 # SKIP Streaming SVE set FPSIMD get SVE for VL 2512
4412 10:53:38.885063 # ok 2685 Set Streaming SVE VL 2528
4413 10:53:38.885147 # ok 2686 # SKIP Streaming SVE set SVE get SVE for VL 2528
4414 10:53:38.885226 # ok 2687 # SKIP Streaming SVE set SVE get FPSIMD for VL 2528
4415 10:53:38.885305 # ok 2688 # SKIP Streaming SVE set FPSIMD get SVE for VL 2528
4416 10:53:38.885383 # ok 2689 Set Streaming SVE VL 2544
4417 10:53:38.885461 # ok 2690 # SKIP Streaming SVE set SVE get SVE for VL 2544
4418 10:53:38.885539 # ok 2691 # SKIP Streaming SVE set SVE get FPSIMD for VL 2544
4419 10:53:38.885619 # ok 2692 # SKIP Streaming SVE set FPSIMD get SVE for VL 2544
4420 10:53:38.885709 # ok 2693 Set Streaming SVE VL 2560
4421 10:53:38.885788 # ok 2694 # SKIP Streaming SVE set SVE get SVE for VL 2560
4422 10:53:38.885868 # ok 2695 # SKIP Streaming SVE set SVE get FPSIMD for VL 2560
4423 10:53:38.885946 # ok 2696 # SKIP Streaming SVE set FPSIMD get SVE for VL 2560
4424 10:53:38.886022 # ok 2697 Set Streaming SVE VL 2576
4425 10:53:38.886104 # ok 2698 # SKIP Streaming SVE set SVE get SVE for VL 2576
4426 10:53:38.886181 # ok 2699 # SKIP Streaming SVE set SVE get FPSIMD for VL 2576
4427 10:53:38.886258 # ok 2700 # SKIP Streaming SVE set FPSIMD get SVE for VL 2576
4428 10:53:38.886335 # ok 2701 Set Streaming SVE VL 2592
4429 10:53:38.886430 # ok 2702 # SKIP Streaming SVE set SVE get SVE for VL 2592
4430 10:53:38.886511 # ok 2703 # SKIP Streaming SVE set SVE get FPSIMD for VL 2592
4431 10:53:38.886588 # ok 2704 # SKIP Streaming SVE set FPSIMD get SVE for VL 2592
4432 10:53:38.886665 # ok 2705 Set Streaming SVE VL 2608
4433 10:53:38.886742 # ok 2706 # SKIP Streaming SVE set SVE get SVE for VL 2608
4434 10:53:38.886819 # ok 2707 # SKIP Streaming SVE set SVE get FPSIMD for VL 2608
4435 10:53:38.887126 # ok 2708 # SKIP Streaming SVE set FPSIMD get SVE for VL 2608
4436 10:53:38.887222 # ok 2709 Set Streaming SVE VL 2624
4437 10:53:38.887302 # ok 2710 # SKIP Streaming SVE set SVE get SVE for VL 2624
4438 10:53:38.887365 # ok 2711 # SKIP Streaming SVE set SVE get FPSIMD for VL 2624
4439 10:53:38.887428 # ok 2712 # SKIP Streaming SVE set FPSIMD get SVE for VL 2624
4440 10:53:38.887507 # ok 2713 Set Streaming SVE VL 2640
4441 10:53:38.887581 # ok 2714 # SKIP Streaming SVE set SVE get SVE for VL 2640
4442 10:53:38.887648 # ok 2715 # SKIP Streaming SVE set SVE get FPSIMD for VL 2640
4443 10:53:38.887711 # ok 2716 # SKIP Streaming SVE set FPSIMD get SVE for VL 2640
4444 10:53:38.887777 # ok 2717 Set Streaming SVE VL 2656
4445 10:53:38.887841 # ok 2718 # SKIP Streaming SVE set SVE get SVE for VL 2656
4446 10:53:38.887908 # ok 2719 # SKIP Streaming SVE set SVE get FPSIMD for VL 2656
4447 10:53:38.887972 # ok 2720 # SKIP Streaming SVE set FPSIMD get SVE for VL 2656
4448 10:53:38.888033 # ok 2721 Set Streaming SVE VL 2672
4449 10:53:38.888094 # ok 2722 # SKIP Streaming SVE set SVE get SVE for VL 2672
4450 10:53:38.888169 # ok 2723 # SKIP Streaming SVE set SVE get FPSIMD for VL 2672
4451 10:53:38.888233 # ok 2724 # SKIP Streaming SVE set FPSIMD get SVE for VL 2672
4452 10:53:38.888295 # ok 2725 Set Streaming SVE VL 2688
4453 10:53:38.888356 # ok 2726 # SKIP Streaming SVE set SVE get SVE for VL 2688
4454 10:53:38.888415 # ok 2727 # SKIP Streaming SVE set SVE get FPSIMD for VL 2688
4455 10:53:38.891252 # ok 2728 # SKIP Streaming SVE set FPSIMD get SVE for VL 2688
4456 10:53:38.891364 # ok 2729 Set Streaming SVE VL 2704
4457 10:53:38.891457 # ok 2730 # SKIP Streaming SVE set SVE get SVE for VL 2704
4458 10:53:38.891545 # ok 2731 # SKIP Streaming SVE set SVE get FPSIMD for VL 2704
4459 10:53:38.892510 # ok 2732 # SKIP Streaming SVE set FPSIMD get SVE for VL 2704
4460 10:53:38.892789 # ok 2733 Set Streaming SVE VL 2720
4461 10:53:38.892871 # ok 2734 # SKIP Streaming SVE set SVE get SVE for VL 2720
4462 10:53:38.892960 # ok 2735 # SKIP Streaming SVE set SVE get FPSIMD for VL 2720
4463 10:53:38.893230 # ok 2736 # SKIP Streaming SVE set FPSIMD get SVE for VL 2720
4464 10:53:38.893310 # ok 2737 Set Streaming SVE VL 2736
4465 10:53:38.893398 # ok 2738 # SKIP Streaming SVE set SVE get SVE for VL 2736
4466 10:53:38.893486 # ok 2739 # SKIP Streaming SVE set SVE get FPSIMD for VL 2736
4467 10:53:38.893769 # ok 2740 # SKIP Streaming SVE set FPSIMD get SVE for VL 2736
4468 10:53:38.893868 # ok 2741 Set Streaming SVE VL 2752
4469 10:53:38.893969 # ok 2742 # SKIP Streaming SVE set SVE get SVE for VL 2752
4470 10:53:38.894254 # ok 2743 # SKIP Streaming SVE set SVE get FPSIMD for VL 2752
4471 10:53:38.894348 # ok 2744 # SKIP Streaming SVE set FPSIMD get SVE for VL 2752
4472 10:53:38.894476 # ok 2745 Set Streaming SVE VL 2768
4473 10:53:38.894581 # ok 2746 # SKIP Streaming SVE set SVE get SVE for VL 2768
4474 10:53:38.894697 # ok 2747 # SKIP Streaming SVE set SVE get FPSIMD for VL 2768
4475 10:53:38.894798 # ok 2748 # SKIP Streaming SVE set FPSIMD get SVE for VL 2768
4476 10:53:38.895008 # ok 2749 Set Streaming SVE VL 2784
4477 10:53:38.895126 # ok 2750 # SKIP Streaming SVE set SVE get SVE for VL 2784
4478 10:53:38.895233 # ok 2751 # SKIP Streaming SVE set SVE get FPSIMD for VL 2784
4479 10:53:38.895572 # ok 2752 # SKIP Streaming SVE set FPSIMD get SVE for VL 2784
4480 10:53:38.895701 # ok 2753 Set Streaming SVE VL 2800
4481 10:53:38.895804 # ok 2754 # SKIP Streaming SVE set SVE get SVE for VL 2800
4482 10:53:38.895899 # ok 2755 # SKIP Streaming SVE set SVE get FPSIMD for VL 2800
4483 10:53:38.896187 # ok 2756 # SKIP Streaming SVE set FPSIMD get SVE for VL 2800
4484 10:53:38.896289 # ok 2757 Set Streaming SVE VL 2816
4485 10:53:38.896384 # ok 2758 # SKIP Streaming SVE set SVE get SVE for VL 2816
4486 10:53:38.896690 # ok 2759 # SKIP Streaming SVE set SVE get FPSIMD for VL 2816
4487 10:53:38.896791 # ok 2760 # SKIP Streaming SVE set FPSIMD get SVE for VL 2816
4488 10:53:38.896901 # ok 2761 Set Streaming SVE VL 2832
4489 10:53:38.896997 # ok 2762 # SKIP Streaming SVE set SVE get SVE for VL 2832
4490 10:53:38.897123 # ok 2763 # SKIP Streaming SVE set SVE get FPSIMD for VL 2832
4491 10:53:38.897247 # ok 2764 # SKIP Streaming SVE set FPSIMD get SVE for VL 2832
4492 10:53:38.897363 # ok 2765 Set Streaming SVE VL 2848
4493 10:53:38.897487 # ok 2766 # SKIP Streaming SVE set SVE get SVE for VL 2848
4494 10:53:38.897628 # ok 2767 # SKIP Streaming SVE set SVE get FPSIMD for VL 2848
4495 10:53:38.898006 # ok 2768 # SKIP Streaming SVE set FPSIMD get SVE for VL 2848
4496 10:53:38.898103 # ok 2769 Set Streaming SVE VL 2864
4497 10:53:38.898207 # ok 2770 # SKIP Streaming SVE set SVE get SVE for VL 2864
4498 10:53:38.898297 # ok 2771 # SKIP Streaming SVE set SVE get FPSIMD for VL 2864
4499 10:53:38.898423 # ok 2772 # SKIP Streaming SVE set FPSIMD get SVE for VL 2864
4500 10:53:38.898538 # ok 2773 Set Streaming SVE VL 2880
4501 10:53:38.898672 # ok 2774 # SKIP Streaming SVE set SVE get SVE for VL 2880
4502 10:53:38.898799 # ok 2775 # SKIP Streaming SVE set SVE get FPSIMD for VL 2880
4503 10:53:38.898957 # ok 2776 # SKIP Streaming SVE set FPSIMD get SVE for VL 2880
4504 10:53:38.899079 # ok 2777 Set Streaming SVE VL 2896
4505 10:53:38.899178 # ok 2778 # SKIP Streaming SVE set SVE get SVE for VL 2896
4506 10:53:38.899502 # ok 2779 # SKIP Streaming SVE set SVE get FPSIMD for VL 2896
4507 10:53:38.899610 # ok 2780 # SKIP Streaming SVE set FPSIMD get SVE for VL 2896
4508 10:53:38.899735 # ok 2781 Set Streaming SVE VL 2912
4509 10:53:38.899846 # ok 2782 # SKIP Streaming SVE set SVE get SVE for VL 2912
4510 10:53:38.900150 # ok 2783 # SKIP Streaming SVE set SVE get FPSIMD for VL 2912
4511 10:53:38.900259 # ok 2784 # SKIP Streaming SVE set FPSIMD get SVE for VL 2912
4512 10:53:38.900383 # ok 2785 Set Streaming SVE VL 2928
4513 10:53:38.900501 # ok 2786 # SKIP Streaming SVE set SVE get SVE for VL 2928
4514 10:53:38.900621 # ok 2787 # SKIP Streaming SVE set SVE get FPSIMD for VL 2928
4515 10:53:38.900753 # ok 2788 # SKIP Streaming SVE set FPSIMD get SVE for VL 2928
4516 10:53:38.901072 # ok 2789 Set Streaming SVE VL 2944
4517 10:53:38.901173 # ok 2790 # SKIP Streaming SVE set SVE get SVE for VL 2944
4518 10:53:38.901263 # ok 2791 # SKIP Streaming SVE set SVE get FPSIMD for VL 2944
4519 10:53:38.901339 # ok 2792 # SKIP Streaming SVE set FPSIMD get SVE for VL 2944
4520 10:53:38.901424 # ok 2793 Set Streaming SVE VL 2960
4521 10:53:38.901697 # ok 2794 # SKIP Streaming SVE set SVE get SVE for VL 2960
4522 10:53:38.901807 # ok 2795 # SKIP Streaming SVE set SVE get FPSIMD for VL 2960
4523 10:53:38.901906 # ok 2796 # SKIP Streaming SVE set FPSIMD get SVE for VL 2960
4524 10:53:38.901996 # ok 2797 Set Streaming SVE VL 2976
4525 10:53:38.902279 # ok 2798 # SKIP Streaming SVE set SVE get SVE for VL 2976
4526 10:53:38.902399 # ok 2799 # SKIP Streaming SVE set SVE get FPSIMD for VL 2976
4527 10:53:38.902510 # ok 2800 # SKIP Streaming SVE set FPSIMD get SVE for VL 2976
4528 10:53:38.902596 # ok 2801 Set Streaming SVE VL 2992
4529 10:53:38.902912 # ok 2802 # SKIP Streaming SVE set SVE get SVE for VL 2992
4530 10:53:38.903031 # ok 2803 # SKIP Streaming SVE set SVE get FPSIMD for VL 2992
4531 10:53:38.903128 # ok 2804 # SKIP Streaming SVE set FPSIMD get SVE for VL 2992
4532 10:53:38.903416 # ok 2805 Set Streaming SVE VL 3008
4533 10:53:38.903509 # ok 2806 # SKIP Streaming SVE set SVE get SVE for VL 3008
4534 10:53:38.903606 # ok 2807 # SKIP Streaming SVE set SVE get FPSIMD for VL 3008
4535 10:53:38.903694 # ok 2808 # SKIP Streaming SVE set FPSIMD get SVE for VL 3008
4536 10:53:38.903990 # ok 2809 Set Streaming SVE VL 3024
4537 10:53:38.904108 # ok 2810 # SKIP Streaming SVE set SVE get SVE for VL 3024
4538 10:53:38.904237 # ok 2811 # SKIP Streaming SVE set SVE get FPSIMD for VL 3024
4539 10:53:38.904535 # ok 2812 # SKIP Streaming SVE set FPSIMD get SVE for VL 3024
4540 10:53:38.904633 # ok 2813 Set Streaming SVE VL 3040
4541 10:53:38.904909 # ok 2814 # SKIP Streaming SVE set SVE get SVE for VL 3040
4542 10:53:38.905006 # ok 2815 # SKIP Streaming SVE set SVE get FPSIMD for VL 3040
4543 10:53:38.905098 # ok 2816 # SKIP Streaming SVE set FPSIMD get SVE for VL 3040
4544 10:53:38.905177 # ok 2817 Set Streaming SVE VL 3056
4545 10:53:38.905265 # ok 2818 # SKIP Streaming SVE set SVE get SVE for VL 3056
4546 10:53:38.905353 # ok 2819 # SKIP Streaming SVE set SVE get FPSIMD for VL 3056
4547 10:53:38.905642 # ok 2820 # SKIP Streaming SVE set FPSIMD get SVE for VL 3056
4548 10:53:38.905732 # ok 2821 Set Streaming SVE VL 3072
4549 10:53:38.905818 # ok 2822 # SKIP Streaming SVE set SVE get SVE for VL 3072
4550 10:53:38.906087 # ok 2823 # SKIP Streaming SVE set SVE get FPSIMD for VL 3072
4551 10:53:38.906179 # ok 2824 # SKIP Streaming SVE set FPSIMD get SVE for VL 3072
4552 10:53:38.906267 # ok 2825 Set Streaming SVE VL 3088
4553 10:53:38.906535 # ok 2826 # SKIP Streaming SVE set SVE get SVE for VL 3088
4554 10:53:38.906627 # ok 2827 # SKIP Streaming SVE set SVE get FPSIMD for VL 3088
4555 10:53:38.906715 # ok 2828 # SKIP Streaming SVE set FPSIMD get SVE for VL 3088
4556 10:53:38.906984 # ok 2829 Set Streaming SVE VL 3104
4557 10:53:38.907063 # ok 2830 # SKIP Streaming SVE set SVE get SVE for VL 3104
4558 10:53:38.907150 # ok 2831 # SKIP Streaming SVE set SVE get FPSIMD for VL 3104
4559 10:53:38.907420 # ok 2832 # SKIP Streaming SVE set FPSIMD get SVE for VL 3104
4560 10:53:38.907500 # ok 2833 Set Streaming SVE VL 3120
4561 10:53:38.907768 # ok 2834 # SKIP Streaming SVE set SVE get SVE for VL 3120
4562 10:53:38.907858 # ok 2835 # SKIP Streaming SVE set SVE get FPSIMD for VL 3120
4563 10:53:38.908127 # ok 2836 # SKIP Streaming SVE set FPSIMD get SVE for VL 3120
4564 10:53:38.908207 # ok 2837 Set Streaming SVE VL 3136
4565 10:53:38.908293 # ok 2838 # SKIP Streaming SVE set SVE get SVE for VL 3136
4566 10:53:38.908561 # ok 2839 # SKIP Streaming SVE set SVE get FPSIMD for VL 3136
4567 10:53:38.908641 # ok 2840 # SKIP Streaming SVE set FPSIMD get SVE for VL 3136
4568 10:53:38.908728 # ok 2841 Set Streaming SVE VL 3152
4569 10:53:38.908995 # ok 2842 # SKIP Streaming SVE set SVE get SVE for VL 3152
4570 10:53:38.909085 # ok 2843 # SKIP Streaming SVE set SVE get FPSIMD for VL 3152
4571 10:53:38.909172 # ok 2844 # SKIP Streaming SVE set FPSIMD get SVE for VL 3152
4572 10:53:38.909260 # ok 2845 Set Streaming SVE VL 3168
4573 10:53:38.909528 # ok 2846 # SKIP Streaming SVE set SVE get SVE for VL 3168
4574 10:53:38.909619 # ok 2847 # SKIP Streaming SVE set SVE get FPSIMD for VL 3168
4575 10:53:38.909723 # ok 2848 # SKIP Streaming SVE set FPSIMD get SVE for VL 3168
4576 10:53:38.909991 # ok 2849 Set Streaming SVE VL 3184
4577 10:53:38.910082 # ok 2850 # SKIP Streaming SVE set SVE get SVE for VL 3184
4578 10:53:38.910349 # ok 2851 # SKIP Streaming SVE set SVE get FPSIMD for VL 3184
4579 10:53:38.910440 # ok 2852 # SKIP Streaming SVE set FPSIMD get SVE for VL 3184
4580 10:53:38.910529 # ok 2853 Set Streaming SVE VL 3200
4581 10:53:38.910616 # ok 2854 # SKIP Streaming SVE set SVE get SVE for VL 3200
4582 10:53:38.910884 # ok 2855 # SKIP Streaming SVE set SVE get FPSIMD for VL 3200
4583 10:53:38.910975 # ok 2856 # SKIP Streaming SVE set FPSIMD get SVE for VL 3200
4584 10:53:38.911061 # ok 2857 Set Streaming SVE VL 3216
4585 10:53:38.911334 # ok 2858 # SKIP Streaming SVE set SVE get SVE for VL 3216
4586 10:53:38.911424 # ok 2859 # SKIP Streaming SVE set SVE get FPSIMD for VL 3216
4587 10:53:38.911690 # ok 2860 # SKIP Streaming SVE set FPSIMD get SVE for VL 3216
4588 10:53:38.911769 # ok 2861 Set Streaming SVE VL 3232
4589 10:53:38.912102 # ok 2862 # SKIP Streaming SVE set SVE get SVE for VL 3232
4590 10:53:38.912181 # ok 2863 # SKIP Streaming SVE set SVE get FPSIMD for VL 3232
4591 10:53:38.912255 # ok 2864 # SKIP Streaming SVE set FPSIMD get SVE for VL 3232
4592 10:53:38.912510 # ok 2865 Set Streaming SVE VL 3248
4593 10:53:38.912588 # ok 2866 # SKIP Streaming SVE set SVE get SVE for VL 3248
4594 10:53:38.912673 # ok 2867 # SKIP Streaming SVE set SVE get FPSIMD for VL 3248
4595 10:53:38.912759 # ok 2868 # SKIP Streaming SVE set FPSIMD get SVE for VL 3248
4596 10:53:38.912845 # ok 2869 Set Streaming SVE VL 3264
4597 10:53:38.913112 # ok 2870 # SKIP Streaming SVE set SVE get SVE for VL 3264
4598 10:53:38.913381 # ok 2871 # SKIP Streaming SVE set SVE get FPSIMD for VL 3264
4599 10:53:38.913470 # ok 2872 # SKIP Streaming SVE set FPSIMD get SVE for VL 3264
4600 10:53:38.913556 # ok 2873 Set Streaming SVE VL 3280
4601 10:53:38.913823 # ok 2874 # SKIP Streaming SVE set SVE get SVE for VL 3280
4602 10:53:38.913902 # ok 2875 # SKIP Streaming SVE set SVE get FPSIMD for VL 3280
4603 10:53:38.914002 # ok 2876 # SKIP Streaming SVE set FPSIMD get SVE for VL 3280
4604 10:53:38.914269 # ok 2877 Set Streaming SVE VL 3296
4605 10:53:38.923164 # ok 2878 # SKIP Streaming SVE set SVE get SVE for VL 3296
4606 10:53:38.923379 # ok 2879 # SKIP Streaming SVE set SVE get FPSIMD for VL 3296
4607 10:53:38.923549 # ok 2880 # SKIP Streaming SVE set FPSIMD get SVE for VL 3296
4608 10:53:38.923684 # ok 2881 Set Streaming SVE VL 3312
4609 10:53:38.923799 # ok 2882 # SKIP Streaming SVE set SVE get SVE for VL 3312
4610 10:53:38.923911 # ok 2883 # SKIP Streaming SVE set SVE get FPSIMD for VL 3312
4611 10:53:38.929801 # ok 2884 # SKIP Streaming SVE set FPSIMD get SVE for VL 3312
4612 10:53:38.930271 # ok 2885 Set Streaming SVE VL 3328
4613 10:53:38.930377 # ok 2886 # SKIP Streaming SVE set SVE get SVE for VL 3328
4614 10:53:38.930472 # ok 2887 # SKIP Streaming SVE set SVE get FPSIMD for VL 3328
4615 10:53:38.930595 # ok 2888 # SKIP Streaming SVE set FPSIMD get SVE for VL 3328
4616 10:53:38.930702 # ok 2889 Set Streaming SVE VL 3344
4617 10:53:38.930815 # ok 2890 # SKIP Streaming SVE set SVE get SVE for VL 3344
4618 10:53:38.930932 # ok 2891 # SKIP Streaming SVE set SVE get FPSIMD for VL 3344
4619 10:53:38.931031 # ok 2892 # SKIP Streaming SVE set FPSIMD get SVE for VL 3344
4620 10:53:38.931131 # ok 2893 Set Streaming SVE VL 3360
4621 10:53:38.931257 # ok 2894 # SKIP Streaming SVE set SVE get SVE for VL 3360
4622 10:53:38.931355 # ok 2895 # SKIP Streaming SVE set SVE get FPSIMD for VL 3360
4623 10:53:38.931470 # ok 2896 # SKIP Streaming SVE set FPSIMD get SVE for VL 3360
4624 10:53:38.931567 # ok 2897 Set Streaming SVE VL 3376
4625 10:53:38.931690 # ok 2898 # SKIP Streaming SVE set SVE get SVE for VL 3376
4626 10:53:38.931785 # ok 2899 # SKIP Streaming SVE set SVE get FPSIMD for VL 3376
4627 10:53:38.939491 # ok 2900 # SKIP Streaming SVE set FPSIMD get SVE for VL 3376
4628 10:53:38.939878 # ok 2901 Set Streaming SVE VL 3392
4629 10:53:38.939979 # ok 2902 # SKIP Streaming SVE set SVE get SVE for VL 3392
4630 10:53:38.945785 # ok 2903 # SKIP Streaming SVE set SVE get FPSIMD for VL 3392
4631 10:53:38.946204 # ok 2904 # SKIP Streaming SVE set FPSIMD get SVE for VL 3392
4632 10:53:38.946340 # ok 2905 Set Streaming SVE VL 3408
4633 10:53:38.946459 # ok 2906 # SKIP Streaming SVE set SVE get SVE for VL 3408
4634 10:53:38.946615 # ok 2907 # SKIP Streaming SVE set SVE get FPSIMD for VL 3408
4635 10:53:38.946710 # ok 2908 # SKIP Streaming SVE set FPSIMD get SVE for VL 3408
4636 10:53:38.946789 # ok 2909 Set Streaming SVE VL 3424
4637 10:53:38.946865 # ok 2910 # SKIP Streaming SVE set SVE get SVE for VL 3424
4638 10:53:38.946954 # ok 2911 # SKIP Streaming SVE set SVE get FPSIMD for VL 3424
4639 10:53:38.947032 # ok 2912 # SKIP Streaming SVE set FPSIMD get SVE for VL 3424
4640 10:53:38.947111 # ok 2913 Set Streaming SVE VL 3440
4641 10:53:38.947200 # ok 2914 # SKIP Streaming SVE set SVE get SVE for VL 3440
4642 10:53:38.947489 # ok 2915 # SKIP Streaming SVE set SVE get FPSIMD for VL 3440
4643 10:53:38.947586 # ok 2916 # SKIP Streaming SVE set FPSIMD get SVE for VL 3440
4644 10:53:38.947672 # ok 2917 Set Streaming SVE VL 3456
4645 10:53:38.947958 # ok 2918 # SKIP Streaming SVE set SVE get SVE for VL 3456
4646 10:53:38.948038 # ok 2919 # SKIP Streaming SVE set SVE get FPSIMD for VL 3456
4647 10:53:38.952917 # ok 2920 # SKIP Streaming SVE set FPSIMD get SVE for VL 3456
4648 10:53:38.953223 # ok 2921 Set Streaming SVE VL 3472
4649 10:53:38.953428 # ok 2922 # SKIP Streaming SVE set SVE get SVE for VL 3472
4650 10:53:38.953523 # ok 2923 # SKIP Streaming SVE set SVE get FPSIMD for VL 3472
4651 10:53:38.953620 # ok 2924 # SKIP Streaming SVE set FPSIMD get SVE for VL 3472
4652 10:53:38.953709 # ok 2925 Set Streaming SVE VL 3488
4653 10:53:38.953789 # ok 2926 # SKIP Streaming SVE set SVE get SVE for VL 3488
4654 10:53:38.953882 # ok 2927 # SKIP Streaming SVE set SVE get FPSIMD for VL 3488
4655 10:53:38.953962 # ok 2928 # SKIP Streaming SVE set FPSIMD get SVE for VL 3488
4656 10:53:38.954040 # ok 2929 Set Streaming SVE VL 3504
4657 10:53:38.954132 # ok 2930 # SKIP Streaming SVE set SVE get SVE for VL 3504
4658 10:53:38.954212 # ok 2931 # SKIP Streaming SVE set SVE get FPSIMD for VL 3504
4659 10:53:38.954306 # ok 2932 # SKIP Streaming SVE set FPSIMD get SVE for VL 3504
4660 10:53:38.954398 # ok 2933 Set Streaming SVE VL 3520
4661 10:53:38.954498 # ok 2934 # SKIP Streaming SVE set SVE get SVE for VL 3520
4662 10:53:38.954834 # ok 2935 # SKIP Streaming SVE set SVE get FPSIMD for VL 3520
4663 10:53:38.954935 # ok 2936 # SKIP Streaming SVE set FPSIMD get SVE for VL 3520
4664 10:53:38.955037 # ok 2937 Set Streaming SVE VL 3536
4665 10:53:38.955106 # ok 2938 # SKIP Streaming SVE set SVE get SVE for VL 3536
4666 10:53:38.955223 # ok 2939 # SKIP Streaming SVE set SVE get FPSIMD for VL 3536
4667 10:53:38.955323 # ok 2940 # SKIP Streaming SVE set FPSIMD get SVE for VL 3536
4668 10:53:38.955412 # ok 2941 Set Streaming SVE VL 3552
4669 10:53:38.955495 # ok 2942 # SKIP Streaming SVE set SVE get SVE for VL 3552
4670 10:53:38.955576 # ok 2943 # SKIP Streaming SVE set SVE get FPSIMD for VL 3552
4671 10:53:38.955812 # ok 2944 # SKIP Streaming SVE set FPSIMD get SVE for VL 3552
4672 10:53:38.960953 # ok 2945 Set Streaming SVE VL 3568
4673 10:53:38.961316 # ok 2946 # SKIP Streaming SVE set SVE get SVE for VL 3568
4674 10:53:38.961416 # ok 2947 # SKIP Streaming SVE set SVE get FPSIMD for VL 3568
4675 10:53:38.961512 # ok 2948 # SKIP Streaming SVE set FPSIMD get SVE for VL 3568
4676 10:53:38.961594 # ok 2949 Set Streaming SVE VL 3584
4677 10:53:38.961694 # ok 2950 # SKIP Streaming SVE set SVE get SVE for VL 3584
4678 10:53:38.961775 # ok 2951 # SKIP Streaming SVE set SVE get FPSIMD for VL 3584
4679 10:53:38.962050 # ok 2952 # SKIP Streaming SVE set FPSIMD get SVE for VL 3584
4680 10:53:38.962134 # ok 2953 Set Streaming SVE VL 3600
4681 10:53:38.962225 # ok 2954 # SKIP Streaming SVE set SVE get SVE for VL 3600
4682 10:53:38.962588 # ok 2955 # SKIP Streaming SVE set SVE get FPSIMD for VL 3600
4683 10:53:38.962692 # ok 2956 # SKIP Streaming SVE set FPSIMD get SVE for VL 3600
4684 10:53:38.962808 # ok 2957 Set Streaming SVE VL 3616
4685 10:53:38.962913 # ok 2958 # SKIP Streaming SVE set SVE get SVE for VL 3616
4686 10:53:38.963007 # ok 2959 # SKIP Streaming SVE set SVE get FPSIMD for VL 3616
4687 10:53:38.963100 # ok 2960 # SKIP Streaming SVE set FPSIMD get SVE for VL 3616
4688 10:53:38.963192 # ok 2961 Set Streaming SVE VL 3632
4689 10:53:38.963475 # ok 2962 # SKIP Streaming SVE set SVE get SVE for VL 3632
4690 10:53:38.963572 # ok 2963 # SKIP Streaming SVE set SVE get FPSIMD for VL 3632
4691 10:53:38.963664 # ok 2964 # SKIP Streaming SVE set FPSIMD get SVE for VL 3632
4692 10:53:38.969259 # ok 2965 Set Streaming SVE VL 3648
4693 10:53:38.969538 # ok 2966 # SKIP Streaming SVE set SVE get SVE for VL 3648
4694 10:53:38.969634 # ok 2967 # SKIP Streaming SVE set SVE get FPSIMD for VL 3648
4695 10:53:38.969742 # ok 2968 # SKIP Streaming SVE set FPSIMD get SVE for VL 3648
4696 10:53:38.970107 # ok 2969 Set Streaming SVE VL 3664
4697 10:53:38.970264 # ok 2970 # SKIP Streaming SVE set SVE get SVE for VL 3664
4698 10:53:38.970368 # ok 2971 # SKIP Streaming SVE set SVE get FPSIMD for VL 3664
4699 10:53:38.970449 # ok 2972 # SKIP Streaming SVE set FPSIMD get SVE for VL 3664
4700 10:53:38.970540 # ok 2973 Set Streaming SVE VL 3680
4701 10:53:38.970632 # ok 2974 # SKIP Streaming SVE set SVE get SVE for VL 3680
4702 10:53:38.970932 # ok 2975 # SKIP Streaming SVE set SVE get FPSIMD for VL 3680
4703 10:53:38.971050 # ok 2976 # SKIP Streaming SVE set FPSIMD get SVE for VL 3680
4704 10:53:38.971133 # ok 2977 Set Streaming SVE VL 3696
4705 10:53:38.971428 # ok 2978 # SKIP Streaming SVE set SVE get SVE for VL 3696
4706 10:53:38.971568 # ok 2979 # SKIP Streaming SVE set SVE get FPSIMD for VL 3696
4707 10:53:38.971724 # ok 2980 # SKIP Streaming SVE set FPSIMD get SVE for VL 3696
4708 10:53:38.971850 # ok 2981 Set Streaming SVE VL 3712
4709 10:53:38.971955 # ok 2982 # SKIP Streaming SVE set SVE get SVE for VL 3712
4710 10:53:38.977394 # ok 2983 # SKIP Streaming SVE set SVE get FPSIMD for VL 3712
4711 10:53:38.977609 # ok 2984 # SKIP Streaming SVE set FPSIMD get SVE for VL 3712
4712 10:53:38.977795 # ok 2985 Set Streaming SVE VL 3728
4713 10:53:38.978171 # ok 2986 # SKIP Streaming SVE set SVE get SVE for VL 3728
4714 10:53:38.978281 # ok 2987 # SKIP Streaming SVE set SVE get FPSIMD for VL 3728
4715 10:53:38.978365 # ok 2988 # SKIP Streaming SVE set FPSIMD get SVE for VL 3728
4716 10:53:38.978444 # ok 2989 Set Streaming SVE VL 3744
4717 10:53:38.978525 # ok 2990 # SKIP Streaming SVE set SVE get SVE for VL 3744
4718 10:53:38.978618 # ok 2991 # SKIP Streaming SVE set SVE get FPSIMD for VL 3744
4719 10:53:38.978698 # ok 2992 # SKIP Streaming SVE set FPSIMD get SVE for VL 3744
4720 10:53:38.978790 # ok 2993 Set Streaming SVE VL 3760
4721 10:53:38.978882 # ok 2994 # SKIP Streaming SVE set SVE get SVE for VL 3760
4722 10:53:38.978975 # ok 2995 # SKIP Streaming SVE set SVE get FPSIMD for VL 3760
4723 10:53:38.979277 # ok 2996 # SKIP Streaming SVE set FPSIMD get SVE for VL 3760
4724 10:53:38.979383 # ok 2997 Set Streaming SVE VL 3776
4725 10:53:38.979478 # ok 2998 # SKIP Streaming SVE set SVE get SVE for VL 3776
4726 10:53:38.979571 # ok 2999 # SKIP Streaming SVE set SVE get FPSIMD for VL 3776
4727 10:53:38.979860 # ok 3000 # SKIP Streaming SVE set FPSIMD get SVE for VL 3776
4728 10:53:38.982852 # ok 3001 Set Streaming SVE VL 3792
4729 10:53:38.983154 # ok 3002 # SKIP Streaming SVE set SVE get SVE for VL 3792
4730 10:53:38.983252 # ok 3003 # SKIP Streaming SVE set SVE get FPSIMD for VL 3792
4731 10:53:38.983349 # ok 3004 # SKIP Streaming SVE set FPSIMD get SVE for VL 3792
4732 10:53:38.983429 # ok 3005 Set Streaming SVE VL 3808
4733 10:53:38.983515 # ok 3006 # SKIP Streaming SVE set SVE get SVE for VL 3808
4734 10:53:38.983798 # ok 3007 # SKIP Streaming SVE set SVE get FPSIMD for VL 3808
4735 10:53:38.987397 # ok 3008 # SKIP Streaming SVE set FPSIMD get SVE for VL 3808
4736 10:53:38.987692 # ok 3009 Set Streaming SVE VL 3824
4737 10:53:38.987788 # ok 3010 # SKIP Streaming SVE set SVE get SVE for VL 3824
4738 10:53:38.988702 # ok 3011 # SKIP Streaming SVE set SVE get FPSIMD for VL 3824
4739 10:53:38.988998 # ok 3012 # SKIP Streaming SVE set FPSIMD get SVE for VL 3824
4740 10:53:38.989095 # ok 3013 Set Streaming SVE VL 3840
4741 10:53:38.989192 # ok 3014 # SKIP Streaming SVE set SVE get SVE for VL 3840
4742 10:53:38.989283 # ok 3015 # SKIP Streaming SVE set SVE get FPSIMD for VL 3840
4743 10:53:38.989603 # ok 3016 # SKIP Streaming SVE set FPSIMD get SVE for VL 3840
4744 10:53:38.989706 # ok 3017 Set Streaming SVE VL 3856
4745 10:53:38.989795 # ok 3018 # SKIP Streaming SVE set SVE get SVE for VL 3856
4746 10:53:38.989882 # ok 3019 # SKIP Streaming SVE set SVE get FPSIMD for VL 3856
4747 10:53:38.990164 # ok 3020 # SKIP Streaming SVE set FPSIMD get SVE for VL 3856
4748 10:53:38.990510 # ok 3021 Set Streaming SVE VL 3872
4749 10:53:38.990734 # ok 3022 # SKIP Streaming SVE set SVE get SVE for VL 3872
4750 10:53:38.990934 # ok 3023 # SKIP Streaming SVE set SVE get FPSIMD for VL 3872
4751 10:53:38.991130 # ok 3024 # SKIP Streaming SVE set FPSIMD get SVE for VL 3872
4752 10:53:38.991268 # ok 3025 Set Streaming SVE VL 3888
4753 10:53:38.991412 # ok 3026 # SKIP Streaming SVE set SVE get SVE for VL 3888
4754 10:53:38.997492 # ok 3027 # SKIP Streaming SVE set SVE get FPSIMD for VL 3888
4755 10:53:38.997596 # ok 3028 # SKIP Streaming SVE set FPSIMD get SVE for VL 3888
4756 10:53:38.997700 # ok 3029 Set Streaming SVE VL 3904
4757 10:53:38.997993 # ok 3030 # SKIP Streaming SVE set SVE get SVE for VL 3904
4758 10:53:38.998095 # ok 3031 # SKIP Streaming SVE set SVE get FPSIMD for VL 3904
4759 10:53:38.998175 # ok 3032 # SKIP Streaming SVE set FPSIMD get SVE for VL 3904
4760 10:53:38.998518 # ok 3033 Set Streaming SVE VL 3920
4761 10:53:38.998622 # ok 3034 # SKIP Streaming SVE set SVE get SVE for VL 3920
4762 10:53:38.998703 # ok 3035 # SKIP Streaming SVE set SVE get FPSIMD for VL 3920
4763 10:53:38.998795 # ok 3036 # SKIP Streaming SVE set FPSIMD get SVE for VL 3920
4764 10:53:38.998875 # ok 3037 Set Streaming SVE VL 3936
4765 10:53:38.998953 # ok 3038 # SKIP Streaming SVE set SVE get SVE for VL 3936
4766 10:53:38.999044 # ok 3039 # SKIP Streaming SVE set SVE get FPSIMD for VL 3936
4767 10:53:38.999124 # ok 3040 # SKIP Streaming SVE set FPSIMD get SVE for VL 3936
4768 10:53:38.999214 # ok 3041 Set Streaming SVE VL 3952
4769 10:53:38.999305 # ok 3042 # SKIP Streaming SVE set SVE get SVE for VL 3952
4770 10:53:38.999397 # ok 3043 # SKIP Streaming SVE set SVE get FPSIMD for VL 3952
4771 10:53:38.999730 # ok 3044 # SKIP Streaming SVE set FPSIMD get SVE for VL 3952
4772 10:53:38.999909 # ok 3045 Set Streaming SVE VL 3968
4773 10:53:39.005115 # ok 3046 # SKIP Streaming SVE set SVE get SVE for VL 3968
4774 10:53:39.005470 # ok 3047 # SKIP Streaming SVE set SVE get FPSIMD for VL 3968
4775 10:53:39.005568 # ok 3048 # SKIP Streaming SVE set FPSIMD get SVE for VL 3968
4776 10:53:39.005651 # ok 3049 Set Streaming SVE VL 3984
4777 10:53:39.005740 # ok 3050 # SKIP Streaming SVE set SVE get SVE for VL 3984
4778 10:53:39.005826 # ok 3051 # SKIP Streaming SVE set SVE get FPSIMD for VL 3984
4779 10:53:39.005913 # ok 3052 # SKIP Streaming SVE set FPSIMD get SVE for VL 3984
4780 10:53:39.006189 # ok 3053 Set Streaming SVE VL 4000
4781 10:53:39.006286 # ok 3054 # SKIP Streaming SVE set SVE get SVE for VL 4000
4782 10:53:39.006373 # ok 3055 # SKIP Streaming SVE set SVE get FPSIMD for VL 4000
4783 10:53:39.006688 # ok 3056 # SKIP Streaming SVE set FPSIMD get SVE for VL 4000
4784 10:53:39.006785 # ok 3057 Set Streaming SVE VL 4016
4785 10:53:39.006861 # ok 3058 # SKIP Streaming SVE set SVE get SVE for VL 4016
4786 10:53:39.006948 # ok 3059 # SKIP Streaming SVE set SVE get FPSIMD for VL 4016
4787 10:53:39.007023 # ok 3060 # SKIP Streaming SVE set FPSIMD get SVE for VL 4016
4788 10:53:39.007096 # ok 3061 Set Streaming SVE VL 4032
4789 10:53:39.007181 # ok 3062 # SKIP Streaming SVE set SVE get SVE for VL 4032
4790 10:53:39.007256 # ok 3063 # SKIP Streaming SVE set SVE get FPSIMD for VL 4032
4791 10:53:39.007785 # ok 3064 # SKIP Streaming SVE set FPSIMD get SVE for VL 4032
4792 10:53:39.008015 # ok 3065 Set Streaming SVE VL 4048
4793 10:53:39.008151 # ok 3066 # SKIP Streaming SVE set SVE get SVE for VL 4048
4794 10:53:39.008269 # ok 3067 # SKIP Streaming SVE set SVE get FPSIMD for VL 4048
4795 10:53:39.013485 # ok 3068 # SKIP Streaming SVE set FPSIMD get SVE for VL 4048
4796 10:53:39.013806 # ok 3069 Set Streaming SVE VL 4064
4797 10:53:39.014236 # ok 3070 # SKIP Streaming SVE set SVE get SVE for VL 4064
4798 10:53:39.014430 # ok 3071 # SKIP Streaming SVE set SVE get FPSIMD for VL 4064
4799 10:53:39.014647 # ok 3072 # SKIP Streaming SVE set FPSIMD get SVE for VL 4064
4800 10:53:39.014809 # ok 3073 Set Streaming SVE VL 4080
4801 10:53:39.015000 # ok 3074 # SKIP Streaming SVE set SVE get SVE for VL 4080
4802 10:53:39.015154 # ok 3075 # SKIP Streaming SVE set SVE get FPSIMD for VL 4080
4803 10:53:39.015319 # ok 3076 # SKIP Streaming SVE set FPSIMD get SVE for VL 4080
4804 10:53:39.015477 # ok 3077 Set Streaming SVE VL 4096
4805 10:53:39.015617 # ok 3078 # SKIP Streaming SVE set SVE get SVE for VL 4096
4806 10:53:39.015755 # ok 3079 # SKIP Streaming SVE set SVE get FPSIMD for VL 4096
4807 10:53:39.015926 # ok 3080 # SKIP Streaming SVE set FPSIMD get SVE for VL 4096
4808 10:53:39.016050 # ok 3081 Set Streaming SVE VL 4112
4809 10:53:39.016166 # ok 3082 # SKIP Streaming SVE set SVE get SVE for VL 4112
4810 10:53:39.016295 # ok 3083 # SKIP Streaming SVE set SVE get FPSIMD for VL 4112
4811 10:53:39.016437 # ok 3084 # SKIP Streaming SVE set FPSIMD get SVE for VL 4112
4812 10:53:39.016593 # ok 3085 Set Streaming SVE VL 4128
4813 10:53:39.016780 # ok 3086 # SKIP Streaming SVE set SVE get SVE for VL 4128
4814 10:53:39.016937 # ok 3087 # SKIP Streaming SVE set SVE get FPSIMD for VL 4128
4815 10:53:39.017100 # ok 3088 # SKIP Streaming SVE set FPSIMD get SVE for VL 4128
4816 10:53:39.017294 # ok 3089 Set Streaming SVE VL 4144
4817 10:53:39.017456 # ok 3090 # SKIP Streaming SVE set SVE get SVE for VL 4144
4818 10:53:39.017623 # ok 3091 # SKIP Streaming SVE set SVE get FPSIMD for VL 4144
4819 10:53:39.017801 # ok 3092 # SKIP Streaming SVE set FPSIMD get SVE for VL 4144
4820 10:53:39.017965 # ok 3093 Set Streaming SVE VL 4160
4821 10:53:39.018162 # ok 3094 # SKIP Streaming SVE set SVE get SVE for VL 4160
4822 10:53:39.018334 # ok 3095 # SKIP Streaming SVE set SVE get FPSIMD for VL 4160
4823 10:53:39.018488 # ok 3096 # SKIP Streaming SVE set FPSIMD get SVE for VL 4160
4824 10:53:39.018658 # ok 3097 Set Streaming SVE VL 4176
4825 10:53:39.018877 # ok 3098 # SKIP Streaming SVE set SVE get SVE for VL 4176
4826 10:53:39.019069 # ok 3099 # SKIP Streaming SVE set SVE get FPSIMD for VL 4176
4827 10:53:39.019270 # ok 3100 # SKIP Streaming SVE set FPSIMD get SVE for VL 4176
4828 10:53:39.019463 # ok 3101 Set Streaming SVE VL 4192
4829 10:53:39.019627 # ok 3102 # SKIP Streaming SVE set SVE get SVE for VL 4192
4830 10:53:39.019790 # ok 3103 # SKIP Streaming SVE set SVE get FPSIMD for VL 4192
4831 10:53:39.020130 # ok 3104 # SKIP Streaming SVE set FPSIMD get SVE for VL 4192
4832 10:53:39.020256 # ok 3105 Set Streaming SVE VL 4208
4833 10:53:39.020371 # ok 3106 # SKIP Streaming SVE set SVE get SVE for VL 4208
4834 10:53:39.020484 # ok 3107 # SKIP Streaming SVE set SVE get FPSIMD for VL 4208
4835 10:53:39.020598 # ok 3108 # SKIP Streaming SVE set FPSIMD get SVE for VL 4208
4836 10:53:39.020713 # ok 3109 Set Streaming SVE VL 4224
4837 10:53:39.020825 # ok 3110 # SKIP Streaming SVE set SVE get SVE for VL 4224
4838 10:53:39.020937 # ok 3111 # SKIP Streaming SVE set SVE get FPSIMD for VL 4224
4839 10:53:39.029042 # ok 3112 # SKIP Streaming SVE set FPSIMD get SVE for VL 4224
4840 10:53:39.029455 # ok 3113 Set Streaming SVE VL 4240
4841 10:53:39.029582 # ok 3114 # SKIP Streaming SVE set SVE get SVE for VL 4240
4842 10:53:39.029693 # ok 3115 # SKIP Streaming SVE set SVE get FPSIMD for VL 4240
4843 10:53:39.029799 # ok 3116 # SKIP Streaming SVE set FPSIMD get SVE for VL 4240
4844 10:53:39.029902 # ok 3117 Set Streaming SVE VL 4256
4845 10:53:39.030020 # ok 3118 # SKIP Streaming SVE set SVE get SVE for VL 4256
4846 10:53:39.030107 # ok 3119 # SKIP Streaming SVE set SVE get FPSIMD for VL 4256
4847 10:53:39.030208 # ok 3120 # SKIP Streaming SVE set FPSIMD get SVE for VL 4256
4848 10:53:39.030341 # ok 3121 Set Streaming SVE VL 4272
4849 10:53:39.030463 # ok 3122 # SKIP Streaming SVE set SVE get SVE for VL 4272
4850 10:53:39.030810 # ok 3123 # SKIP Streaming SVE set SVE get FPSIMD for VL 4272
4851 10:53:39.030944 # ok 3124 # SKIP Streaming SVE set FPSIMD get SVE for VL 4272
4852 10:53:39.031047 # ok 3125 Set Streaming SVE VL 4288
4853 10:53:39.031343 # ok 3126 # SKIP Streaming SVE set SVE get SVE for VL 4288
4854 10:53:39.031461 # ok 3127 # SKIP Streaming SVE set SVE get FPSIMD for VL 4288
4855 10:53:39.031584 # ok 3128 # SKIP Streaming SVE set FPSIMD get SVE for VL 4288
4856 10:53:39.031684 # ok 3129 Set Streaming SVE VL 4304
4857 10:53:39.031806 # ok 3130 # SKIP Streaming SVE set SVE get SVE for VL 4304
4858 10:53:39.036973 # ok 3131 # SKIP Streaming SVE set SVE get FPSIMD for VL 4304
4859 10:53:39.037407 # ok 3132 # SKIP Streaming SVE set FPSIMD get SVE for VL 4304
4860 10:53:39.037513 # ok 3133 Set Streaming SVE VL 4320
4861 10:53:39.037615 # ok 3134 # SKIP Streaming SVE set SVE get SVE for VL 4320
4862 10:53:39.037735 # ok 3135 # SKIP Streaming SVE set SVE get FPSIMD for VL 4320
4863 10:53:39.037837 # ok 3136 # SKIP Streaming SVE set FPSIMD get SVE for VL 4320
4864 10:53:39.037960 # ok 3137 Set Streaming SVE VL 4336
4865 10:53:39.038073 # ok 3138 # SKIP Streaming SVE set SVE get SVE for VL 4336
4866 10:53:39.038200 # ok 3139 # SKIP Streaming SVE set SVE get FPSIMD for VL 4336
4867 10:53:39.038327 # ok 3140 # SKIP Streaming SVE set FPSIMD get SVE for VL 4336
4868 10:53:39.038438 # ok 3141 Set Streaming SVE VL 4352
4869 10:53:39.038554 # ok 3142 # SKIP Streaming SVE set SVE get SVE for VL 4352
4870 10:53:39.038876 # ok 3143 # SKIP Streaming SVE set SVE get FPSIMD for VL 4352
4871 10:53:39.038982 # ok 3144 # SKIP Streaming SVE set FPSIMD get SVE for VL 4352
4872 10:53:39.039075 # ok 3145 Set Streaming SVE VL 4368
4873 10:53:39.039178 # ok 3146 # SKIP Streaming SVE set SVE get SVE for VL 4368
4874 10:53:39.039300 # ok 3147 # SKIP Streaming SVE set SVE get FPSIMD for VL 4368
4875 10:53:39.039407 # ok 3148 # SKIP Streaming SVE set FPSIMD get SVE for VL 4368
4876 10:53:39.039514 # ok 3149 Set Streaming SVE VL 4384
4877 10:53:39.039629 # ok 3150 # SKIP Streaming SVE set SVE get SVE for VL 4384
4878 10:53:39.039873 # ok 3151 # SKIP Streaming SVE set SVE get FPSIMD for VL 4384
4879 10:53:39.045762 # ok 3152 # SKIP Streaming SVE set FPSIMD get SVE for VL 4384
4880 10:53:39.046208 # ok 3153 Set Streaming SVE VL 4400
4881 10:53:39.046331 # ok 3154 # SKIP Streaming SVE set SVE get SVE for VL 4400
4882 10:53:39.046431 # ok 3155 # SKIP Streaming SVE set SVE get FPSIMD for VL 4400
4883 10:53:39.046544 # ok 3156 # SKIP Streaming SVE set FPSIMD get SVE for VL 4400
4884 10:53:39.046646 # ok 3157 Set Streaming SVE VL 4416
4885 10:53:39.046734 # ok 3158 # SKIP Streaming SVE set SVE get SVE for VL 4416
4886 10:53:39.046834 # ok 3159 # SKIP Streaming SVE set SVE get FPSIMD for VL 4416
4887 10:53:39.046937 # ok 3160 # SKIP Streaming SVE set FPSIMD get SVE for VL 4416
4888 10:53:39.047043 # ok 3161 Set Streaming SVE VL 4432
4889 10:53:39.047351 # ok 3162 # SKIP Streaming SVE set SVE get SVE for VL 4432
4890 10:53:39.047458 # ok 3163 # SKIP Streaming SVE set SVE get FPSIMD for VL 4432
4891 10:53:39.047771 # ok 3164 # SKIP Streaming SVE set FPSIMD get SVE for VL 4432
4892 10:53:39.047875 # ok 3165 Set Streaming SVE VL 4448
4893 10:53:39.047957 # ok 3166 # SKIP Streaming SVE set SVE get SVE for VL 4448
4894 10:53:39.053172 # ok 3167 # SKIP Streaming SVE set SVE get FPSIMD for VL 4448
4895 10:53:39.053629 # ok 3168 # SKIP Streaming SVE set FPSIMD get SVE for VL 4448
4896 10:53:39.053741 # ok 3169 Set Streaming SVE VL 4464
4897 10:53:39.053833 # ok 3170 # SKIP Streaming SVE set SVE get SVE for VL 4464
4898 10:53:39.054123 # ok 3171 # SKIP Streaming SVE set SVE get FPSIMD for VL 4464
4899 10:53:39.054226 # ok 3172 # SKIP Streaming SVE set FPSIMD get SVE for VL 4464
4900 10:53:39.054315 # ok 3173 Set Streaming SVE VL 4480
4901 10:53:39.054595 # ok 3174 # SKIP Streaming SVE set SVE get SVE for VL 4480
4902 10:53:39.054691 # ok 3175 # SKIP Streaming SVE set SVE get FPSIMD for VL 4480
4903 10:53:39.054770 # ok 3176 # SKIP Streaming SVE set FPSIMD get SVE for VL 4480
4904 10:53:39.055649 # ok 3177 Set Streaming SVE VL 4496
4905 10:53:39.055939 # ok 3178 # SKIP Streaming SVE set SVE get SVE for VL 4496
4906 10:53:39.065363 # ok 3179 # SKIP Streaming SVE set SVE get FPSIMD for VL 4496
4907 10:53:39.065587 # ok 3180 # SKIP Streaming SVE set FPSIMD get SVE for VL 4496
4908 10:53:39.065717 # ok 3181 Set Streaming SVE VL 4512
4909 10:53:39.065827 # ok 3182 # SKIP Streaming SVE set SVE get SVE for VL 4512
4910 10:53:39.065942 # ok 3183 # SKIP Streaming SVE set SVE get FPSIMD for VL 4512
4911 10:53:39.066061 # ok 3184 # SKIP Streaming SVE set FPSIMD get SVE for VL 4512
4912 10:53:39.066151 # ok 3185 Set Streaming SVE VL 4528
4913 10:53:39.066241 # ok 3186 # SKIP Streaming SVE set SVE get SVE for VL 4528
4914 10:53:39.066523 # ok 3187 # SKIP Streaming SVE set SVE get FPSIMD for VL 4528
4915 10:53:39.066627 # ok 3188 # SKIP Streaming SVE set FPSIMD get SVE for VL 4528
4916 10:53:39.066738 # ok 3189 Set Streaming SVE VL 4544
4917 10:53:39.066840 # ok 3190 # SKIP Streaming SVE set SVE get SVE for VL 4544
4918 10:53:39.066947 # ok 3191 # SKIP Streaming SVE set SVE get FPSIMD for VL 4544
4919 10:53:39.067054 # ok 3192 # SKIP Streaming SVE set FPSIMD get SVE for VL 4544
4920 10:53:39.067173 # ok 3193 Set Streaming SVE VL 4560
4921 10:53:39.067285 # ok 3194 # SKIP Streaming SVE set SVE get SVE for VL 4560
4922 10:53:39.067393 # ok 3195 # SKIP Streaming SVE set SVE get FPSIMD for VL 4560
4923 10:53:39.067667 # ok 3196 # SKIP Streaming SVE set FPSIMD get SVE for VL 4560
4924 10:53:39.067762 # ok 3197 Set Streaming SVE VL 4576
4925 10:53:39.067859 # ok 3198 # SKIP Streaming SVE set SVE get SVE for VL 4576
4926 10:53:39.076985 # ok 3199 # SKIP Streaming SVE set SVE get FPSIMD for VL 4576
4927 10:53:39.077450 # ok 3200 # SKIP Streaming SVE set FPSIMD get SVE for VL 4576
4928 10:53:39.077556 # ok 3201 Set Streaming SVE VL 4592
4929 10:53:39.077641 # ok 3202 # SKIP Streaming SVE set SVE get SVE for VL 4592
4930 10:53:39.077934 # ok 3203 # SKIP Streaming SVE set SVE get FPSIMD for VL 4592
4931 10:53:39.078042 # ok 3204 # SKIP Streaming SVE set FPSIMD get SVE for VL 4592
4932 10:53:39.078136 # ok 3205 Set Streaming SVE VL 4608
4933 10:53:39.078219 # ok 3206 # SKIP Streaming SVE set SVE get SVE for VL 4608
4934 10:53:39.078314 # ok 3207 # SKIP Streaming SVE set SVE get FPSIMD for VL 4608
4935 10:53:39.078395 # ok 3208 # SKIP Streaming SVE set FPSIMD get SVE for VL 4608
4936 10:53:39.078473 # ok 3209 Set Streaming SVE VL 4624
4937 10:53:39.078565 # ok 3210 # SKIP Streaming SVE set SVE get SVE for VL 4624
4938 10:53:39.078648 # ok 3211 # SKIP Streaming SVE set SVE get FPSIMD for VL 4624
4939 10:53:39.078749 # ok 3212 # SKIP Streaming SVE set FPSIMD get SVE for VL 4624
4940 10:53:39.078835 # ok 3213 Set Streaming SVE VL 4640
4941 10:53:39.078937 # ok 3214 # SKIP Streaming SVE set SVE get SVE for VL 4640
4942 10:53:39.079229 # ok 3215 # SKIP Streaming SVE set SVE get FPSIMD for VL 4640
4943 10:53:39.079333 # ok 3216 # SKIP Streaming SVE set FPSIMD get SVE for VL 4640
4944 10:53:39.079620 # ok 3217 Set Streaming SVE VL 4656
4945 10:53:39.079723 # ok 3218 # SKIP Streaming SVE set SVE get SVE for VL 4656
4946 10:53:39.079825 # ok 3219 # SKIP Streaming SVE set SVE get FPSIMD for VL 4656
4947 10:53:39.079927 # ok 3220 # SKIP Streaming SVE set FPSIMD get SVE for VL 4656
4948 10:53:39.093565 # ok 3221 Set Streaming SVE VL 4672
4949 10:53:39.094035 # ok 3222 # SKIP Streaming SVE set SVE get SVE for VL 4672
4950 10:53:39.094140 # ok 3223 # SKIP Streaming SVE set SVE get FPSIMD for VL 4672
4951 10:53:39.094223 # ok 3224 # SKIP Streaming SVE set FPSIMD get SVE for VL 4672
4952 10:53:39.094318 # ok 3225 Set Streaming SVE VL 4688
4953 10:53:39.094402 # ok 3226 # SKIP Streaming SVE set SVE get SVE for VL 4688
4954 10:53:39.094509 # ok 3227 # SKIP Streaming SVE set SVE get FPSIMD for VL 4688
4955 10:53:39.094803 # ok 3228 # SKIP Streaming SVE set FPSIMD get SVE for VL 4688
4956 10:53:39.094912 # ok 3229 Set Streaming SVE VL 4704
4957 10:53:39.095034 # ok 3230 # SKIP Streaming SVE set SVE get SVE for VL 4704
4958 10:53:39.095134 # ok 3231 # SKIP Streaming SVE set SVE get FPSIMD for VL 4704
4959 10:53:39.095234 # ok 3232 # SKIP Streaming SVE set FPSIMD get SVE for VL 4704
4960 10:53:39.095330 # ok 3233 Set Streaming SVE VL 4720
4961 10:53:39.095411 # ok 3234 # SKIP Streaming SVE set SVE get SVE for VL 4720
4962 10:53:39.095682 # ok 3235 # SKIP Streaming SVE set SVE get FPSIMD for VL 4720
4963 10:53:39.095788 # ok 3236 # SKIP Streaming SVE set FPSIMD get SVE for VL 4720
4964 10:53:39.095875 # ok 3237 Set Streaming SVE VL 4736
4965 10:53:39.095970 # ok 3238 # SKIP Streaming SVE set SVE get SVE for VL 4736
4966 10:53:39.104962 # ok 3239 # SKIP Streaming SVE set SVE get FPSIMD for VL 4736
4967 10:53:39.105415 # ok 3240 # SKIP Streaming SVE set FPSIMD get SVE for VL 4736
4968 10:53:39.105526 # ok 3241 Set Streaming SVE VL 4752
4969 10:53:39.105642 # ok 3242 # SKIP Streaming SVE set SVE get SVE for VL 4752
4970 10:53:39.105776 # ok 3243 # SKIP Streaming SVE set SVE get FPSIMD for VL 4752
4971 10:53:39.105874 # ok 3244 # SKIP Streaming SVE set FPSIMD get SVE for VL 4752
4972 10:53:39.105968 # ok 3245 Set Streaming SVE VL 4768
4973 10:53:39.106067 # ok 3246 # SKIP Streaming SVE set SVE get SVE for VL 4768
4974 10:53:39.106180 # ok 3247 # SKIP Streaming SVE set SVE get FPSIMD for VL 4768
4975 10:53:39.106274 # ok 3248 # SKIP Streaming SVE set FPSIMD get SVE for VL 4768
4976 10:53:39.106363 # ok 3249 Set Streaming SVE VL 4784
4977 10:53:39.106456 # ok 3250 # SKIP Streaming SVE set SVE get SVE for VL 4784
4978 10:53:39.106665 # ok 3251 # SKIP Streaming SVE set SVE get FPSIMD for VL 4784
4979 10:53:39.106966 # ok 3252 # SKIP Streaming SVE set FPSIMD get SVE for VL 4784
4980 10:53:39.107067 # ok 3253 Set Streaming SVE VL 4800
4981 10:53:39.107180 # ok 3254 # SKIP Streaming SVE set SVE get SVE for VL 4800
4982 10:53:39.107467 # ok 3255 # SKIP Streaming SVE set SVE get FPSIMD for VL 4800
4983 10:53:39.107574 # ok 3256 # SKIP Streaming SVE set FPSIMD get SVE for VL 4800
4984 10:53:39.107693 # ok 3257 Set Streaming SVE VL 4816
4985 10:53:39.107781 # ok 3258 # SKIP Streaming SVE set SVE get SVE for VL 4816
4986 10:53:39.107873 # ok 3259 # SKIP Streaming SVE set SVE get FPSIMD for VL 4816
4987 10:53:39.125269 # ok 3260 # SKIP Streaming SVE set FPSIMD get SVE for VL 4816
4988 10:53:39.125712 # ok 3261 Set Streaming SVE VL 4832
4989 10:53:39.125821 # ok 3262 # SKIP Streaming SVE set SVE get SVE for VL 4832
4990 10:53:39.125907 # ok 3263 # SKIP Streaming SVE set SVE get FPSIMD for VL 4832
4991 10:53:39.126003 # ok 3264 # SKIP Streaming SVE set FPSIMD get SVE for VL 4832
4992 10:53:39.126087 # ok 3265 Set Streaming SVE VL 4848
4993 10:53:39.126167 # ok 3266 # SKIP Streaming SVE set SVE get SVE for VL 4848
4994 10:53:39.126261 # ok 3267 # SKIP Streaming SVE set SVE get FPSIMD for VL 4848
4995 10:53:39.126364 # ok 3268 # SKIP Streaming SVE set FPSIMD get SVE for VL 4848
4996 10:53:39.126462 # ok 3269 Set Streaming SVE VL 4864
4997 10:53:39.126554 # ok 3270 # SKIP Streaming SVE set SVE get SVE for VL 4864
4998 10:53:39.126854 # ok 3271 # SKIP Streaming SVE set SVE get FPSIMD for VL 4864
4999 10:53:39.126971 # ok 3272 # SKIP Streaming SVE set FPSIMD get SVE for VL 4864
5000 10:53:39.127262 # ok 3273 Set Streaming SVE VL 4880
5001 10:53:39.127365 # ok 3274 # SKIP Streaming SVE set SVE get SVE for VL 4880
5002 10:53:39.127462 # ok 3275 # SKIP Streaming SVE set SVE get FPSIMD for VL 4880
5003 10:53:39.127548 # ok 3276 # SKIP Streaming SVE set FPSIMD get SVE for VL 4880
5004 10:53:39.127638 # ok 3277 Set Streaming SVE VL 4896
5005 10:53:39.127730 # ok 3278 # SKIP Streaming SVE set SVE get SVE for VL 4896
5006 10:53:39.139700 # ok 3279 # SKIP Streaming SVE set SVE get FPSIMD for VL 4896
5007 10:53:39.140240 # ok 3280 # SKIP Streaming SVE set FPSIMD get SVE for VL 4896
5008 10:53:39.140378 # ok 3281 Set Streaming SVE VL 4912
5009 10:53:39.141919 # ok 3282 # SKIP Streaming SVE set SVE get SVE for VL 4912
5010 10:53:39.142442 # ok 3283 # SKIP Streaming SVE set SVE get FPSIMD for VL 4912
5011 10:53:39.142660 # ok 3284 # SKIP Streaming SVE set FPSIMD get SVE for VL 4912
5012 10:53:39.143202 # ok 3285 Set Streaming SVE VL 4928
5013 10:53:39.143406 # ok 3286 # SKIP Streaming SVE set SVE get SVE for VL 4928
5014 10:53:39.143575 # ok 3287 # SKIP Streaming SVE set SVE get FPSIMD for VL 4928
5015 10:53:39.143737 # ok 3288 # SKIP Streaming SVE set FPSIMD get SVE for VL 4928
5016 10:53:39.143878 # ok 3289 Set Streaming SVE VL 4944
5017 10:53:39.143996 # ok 3290 # SKIP Streaming SVE set SVE get SVE for VL 4944
5018 10:53:39.144109 # ok 3291 # SKIP Streaming SVE set SVE get FPSIMD for VL 4944
5019 10:53:39.144249 # ok 3292 # SKIP Streaming SVE set FPSIMD get SVE for VL 4944
5020 10:53:39.144367 # ok 3293 Set Streaming SVE VL 4960
5021 10:53:39.144479 # ok 3294 # SKIP Streaming SVE set SVE get SVE for VL 4960
5022 10:53:39.144592 # ok 3295 # SKIP Streaming SVE set SVE get FPSIMD for VL 4960
5023 10:53:39.144705 # ok 3296 # SKIP Streaming SVE set FPSIMD get SVE for VL 4960
5024 10:53:39.149641 # ok 3297 Set Streaming SVE VL 4976
5025 10:53:39.149858 # ok 3298 # SKIP Streaming SVE set SVE get SVE for VL 4976
5026 10:53:39.149970 # ok 3299 # SKIP Streaming SVE set SVE get FPSIMD for VL 4976
5027 10:53:39.150268 # ok 3300 # SKIP Streaming SVE set FPSIMD get SVE for VL 4976
5028 10:53:39.150373 # ok 3301 Set Streaming SVE VL 4992
5029 10:53:39.150466 # ok 3302 # SKIP Streaming SVE set SVE get SVE for VL 4992
5030 10:53:39.150770 # ok 3303 # SKIP Streaming SVE set SVE get FPSIMD for VL 4992
5031 10:53:39.150877 # ok 3304 # SKIP Streaming SVE set FPSIMD get SVE for VL 4992
5032 10:53:39.150970 # ok 3305 Set Streaming SVE VL 5008
5033 10:53:39.151060 # ok 3306 # SKIP Streaming SVE set SVE get SVE for VL 5008
5034 10:53:39.151418 # ok 3307 # SKIP Streaming SVE set SVE get FPSIMD for VL 5008
5035 10:53:39.151524 # ok 3308 # SKIP Streaming SVE set FPSIMD get SVE for VL 5008
5036 10:53:39.151607 # ok 3309 Set Streaming SVE VL 5024
5037 10:53:39.151686 # ok 3310 # SKIP Streaming SVE set SVE get SVE for VL 5024
5038 10:53:39.151903 # ok 3311 # SKIP Streaming SVE set SVE get FPSIMD for VL 5024
5039 10:53:39.152000 # ok 3312 # SKIP Streaming SVE set FPSIMD get SVE for VL 5024
5040 10:53:39.152080 # ok 3313 Set Streaming SVE VL 5040
5041 10:53:39.154616 # ok 3314 # SKIP Streaming SVE set SVE get SVE for VL 5040
5042 10:53:39.155008 # ok 3315 # SKIP Streaming SVE set SVE get FPSIMD for VL 5040
5043 10:53:39.155110 # ok 3316 # SKIP Streaming SVE set FPSIMD get SVE for VL 5040
5044 10:53:39.155193 # ok 3317 Set Streaming SVE VL 5056
5045 10:53:39.155285 # ok 3318 # SKIP Streaming SVE set SVE get SVE for VL 5056
5046 10:53:39.155365 # ok 3319 # SKIP Streaming SVE set SVE get FPSIMD for VL 5056
5047 10:53:39.155457 # ok 3320 # SKIP Streaming SVE set FPSIMD get SVE for VL 5056
5048 10:53:39.155549 # ok 3321 Set Streaming SVE VL 5072
5049 10:53:39.155640 # ok 3322 # SKIP Streaming SVE set SVE get SVE for VL 5072
5050 10:53:39.155732 # ok 3323 # SKIP Streaming SVE set SVE get FPSIMD for VL 5072
5051 10:53:39.155824 # ok 3324 # SKIP Streaming SVE set FPSIMD get SVE for VL 5072
5052 10:53:39.158967 # ok 3325 Set Streaming SVE VL 5088
5053 10:53:39.159398 # ok 3326 # SKIP Streaming SVE set SVE get SVE for VL 5088
5054 10:53:39.165695 # ok 3327 # SKIP Streaming SVE set SVE get FPSIMD for VL 5088
5055 10:53:39.166312 # ok 3328 # SKIP Streaming SVE set FPSIMD get SVE for VL 5088
5056 10:53:39.166518 # ok 3329 Set Streaming SVE VL 5104
5057 10:53:39.166692 # ok 3330 # SKIP Streaming SVE set SVE get SVE for VL 5104
5058 10:53:39.166828 # ok 3331 # SKIP Streaming SVE set SVE get FPSIMD for VL 5104
5059 10:53:39.166946 # ok 3332 # SKIP Streaming SVE set FPSIMD get SVE for VL 5104
5060 10:53:39.167060 # ok 3333 Set Streaming SVE VL 5120
5061 10:53:39.167205 # ok 3334 # SKIP Streaming SVE set SVE get SVE for VL 5120
5062 10:53:39.167394 # ok 3335 # SKIP Streaming SVE set SVE get FPSIMD for VL 5120
5063 10:53:39.167562 # ok 3336 # SKIP Streaming SVE set FPSIMD get SVE for VL 5120
5064 10:53:39.167694 # ok 3337 Set Streaming SVE VL 5136
5065 10:53:39.167837 # ok 3338 # SKIP Streaming SVE set SVE get SVE for VL 5136
5066 10:53:39.167958 # ok 3339 # SKIP Streaming SVE set SVE get FPSIMD for VL 5136
5067 10:53:39.168103 # ok 3340 # SKIP Streaming SVE set FPSIMD get SVE for VL 5136
5068 10:53:39.168225 # ok 3341 Set Streaming SVE VL 5152
5069 10:53:39.168341 # ok 3342 # SKIP Streaming SVE set SVE get SVE for VL 5152
5070 10:53:39.168456 # ok 3343 # SKIP Streaming SVE set SVE get FPSIMD for VL 5152
5071 10:53:39.168570 # ok 3344 # SKIP Streaming SVE set FPSIMD get SVE for VL 5152
5072 10:53:39.168688 # ok 3345 Set Streaming SVE VL 5168
5073 10:53:39.174748 # ok 3346 # SKIP Streaming SVE set SVE get SVE for VL 5168
5074 10:53:39.175200 # ok 3347 # SKIP Streaming SVE set SVE get FPSIMD for VL 5168
5075 10:53:39.175307 # ok 3348 # SKIP Streaming SVE set FPSIMD get SVE for VL 5168
5076 10:53:39.175399 # ok 3349 Set Streaming SVE VL 5184
5077 10:53:39.175690 # ok 3350 # SKIP Streaming SVE set SVE get SVE for VL 5184
5078 10:53:39.175799 # ok 3351 # SKIP Streaming SVE set SVE get FPSIMD for VL 5184
5079 10:53:39.175889 # ok 3352 # SKIP Streaming SVE set FPSIMD get SVE for VL 5184
5080 10:53:39.175989 # ok 3353 Set Streaming SVE VL 5200
5081 10:53:39.176264 # ok 3354 # SKIP Streaming SVE set SVE get SVE for VL 5200
5082 10:53:39.177659 # ok 3355 # SKIP Streaming SVE set SVE get FPSIMD for VL 5200
5083 10:53:39.177973 # ok 3356 # SKIP Streaming SVE set FPSIMD get SVE for VL 5200
5084 10:53:39.178078 # ok 3357 Set Streaming SVE VL 5216
5085 10:53:39.178178 # ok 3358 # SKIP Streaming SVE set SVE get SVE for VL 5216
5086 10:53:39.178476 # ok 3359 # SKIP Streaming SVE set SVE get FPSIMD for VL 5216
5087 10:53:39.178595 # ok 3360 # SKIP Streaming SVE set FPSIMD get SVE for VL 5216
5088 10:53:39.178685 # ok 3361 Set Streaming SVE VL 5232
5089 10:53:39.178786 # ok 3362 # SKIP Streaming SVE set SVE get SVE for VL 5232
5090 10:53:39.179106 # ok 3363 # SKIP Streaming SVE set SVE get FPSIMD for VL 5232
5091 10:53:39.179223 # ok 3364 # SKIP Streaming SVE set FPSIMD get SVE for VL 5232
5092 10:53:39.179512 # ok 3365 Set Streaming SVE VL 5248
5093 10:53:39.179615 # ok 3366 # SKIP Streaming SVE set SVE get SVE for VL 5248
5094 10:53:39.179717 # ok 3367 # SKIP Streaming SVE set SVE get FPSIMD for VL 5248
5095 10:53:39.180012 # ok 3368 # SKIP Streaming SVE set FPSIMD get SVE for VL 5248
5096 10:53:39.185052 # ok 3369 Set Streaming SVE VL 5264
5097 10:53:39.185488 # ok 3370 # SKIP Streaming SVE set SVE get SVE for VL 5264
5098 10:53:39.185593 # ok 3371 # SKIP Streaming SVE set SVE get FPSIMD for VL 5264
5099 10:53:39.185690 # ok 3372 # SKIP Streaming SVE set FPSIMD get SVE for VL 5264
5100 10:53:39.185792 # ok 3373 Set Streaming SVE VL 5280
5101 10:53:39.185881 # ok 3374 # SKIP Streaming SVE set SVE get SVE for VL 5280
5102 10:53:39.185984 # ok 3375 # SKIP Streaming SVE set SVE get FPSIMD for VL 5280
5103 10:53:39.186086 # ok 3376 # SKIP Streaming SVE set FPSIMD get SVE for VL 5280
5104 10:53:39.186190 # ok 3377 Set Streaming SVE VL 5296
5105 10:53:39.186486 # ok 3378 # SKIP Streaming SVE set SVE get SVE for VL 5296
5106 10:53:39.186591 # ok 3379 # SKIP Streaming SVE set SVE get FPSIMD for VL 5296
5107 10:53:39.186893 # ok 3380 # SKIP Streaming SVE set FPSIMD get SVE for VL 5296
5108 10:53:39.186996 # ok 3381 Set Streaming SVE VL 5312
5109 10:53:39.187100 # ok 3382 # SKIP Streaming SVE set SVE get SVE for VL 5312
5110 10:53:39.187453 # ok 3383 # SKIP Streaming SVE set SVE get FPSIMD for VL 5312
5111 10:53:39.187712 # ok 3384 # SKIP Streaming SVE set FPSIMD get SVE for VL 5312
5112 10:53:39.187929 # ok 3385 Set Streaming SVE VL 5328
5113 10:53:39.188094 # ok 3386 # SKIP Streaming SVE set SVE get SVE for VL 5328
5114 10:53:39.188224 # ok 3387 # SKIP Streaming SVE set SVE get FPSIMD for VL 5328
5115 10:53:39.193330 # ok 3388 # SKIP Streaming SVE set FPSIMD get SVE for VL 5328
5116 10:53:39.193559 # ok 3389 Set Streaming SVE VL 5344
5117 10:53:39.193883 # ok 3390 # SKIP Streaming SVE set SVE get SVE for VL 5344
5118 10:53:39.193994 # ok 3391 # SKIP Streaming SVE set SVE get FPSIMD for VL 5344
5119 10:53:39.194088 # ok 3392 # SKIP Streaming SVE set FPSIMD get SVE for VL 5344
5120 10:53:39.194179 # ok 3393 Set Streaming SVE VL 5360
5121 10:53:39.194287 # ok 3394 # SKIP Streaming SVE set SVE get SVE for VL 5360
5122 10:53:39.194381 # ok 3395 # SKIP Streaming SVE set SVE get FPSIMD for VL 5360
5123 10:53:39.194473 # ok 3396 # SKIP Streaming SVE set FPSIMD get SVE for VL 5360
5124 10:53:39.194579 # ok 3397 Set Streaming SVE VL 5376
5125 10:53:39.194884 # ok 3398 # SKIP Streaming SVE set SVE get SVE for VL 5376
5126 10:53:39.194994 # ok 3399 # SKIP Streaming SVE set SVE get FPSIMD for VL 5376
5127 10:53:39.195095 # ok 3400 # SKIP Streaming SVE set FPSIMD get SVE for VL 5376
5128 10:53:39.195185 # ok 3401 Set Streaming SVE VL 5392
5129 10:53:39.195291 # ok 3402 # SKIP Streaming SVE set SVE get SVE for VL 5392
5130 10:53:39.195396 # ok 3403 # SKIP Streaming SVE set SVE get FPSIMD for VL 5392
5131 10:53:39.195501 # ok 3404 # SKIP Streaming SVE set FPSIMD get SVE for VL 5392
5132 10:53:39.195608 # ok 3405 Set Streaming SVE VL 5408
5133 10:53:39.195920 # ok 3406 # SKIP Streaming SVE set SVE get SVE for VL 5408
5134 10:53:39.196034 # ok 3407 # SKIP Streaming SVE set SVE get FPSIMD for VL 5408
5135 10:53:39.201782 # ok 3408 # SKIP Streaming SVE set FPSIMD get SVE for VL 5408
5136 10:53:39.202016 # ok 3409 Set Streaming SVE VL 5424
5137 10:53:39.202106 # ok 3410 # SKIP Streaming SVE set SVE get SVE for VL 5424
5138 10:53:39.202449 # ok 3411 # SKIP Streaming SVE set SVE get FPSIMD for VL 5424
5139 10:53:39.202646 # ok 3412 # SKIP Streaming SVE set FPSIMD get SVE for VL 5424
5140 10:53:39.202819 # ok 3413 Set Streaming SVE VL 5440
5141 10:53:39.202972 # ok 3414 # SKIP Streaming SVE set SVE get SVE for VL 5440
5142 10:53:39.203139 # ok 3415 # SKIP Streaming SVE set SVE get FPSIMD for VL 5440
5143 10:53:39.203269 # ok 3416 # SKIP Streaming SVE set FPSIMD get SVE for VL 5440
5144 10:53:39.203400 # ok 3417 Set Streaming SVE VL 5456
5145 10:53:39.203517 # ok 3418 # SKIP Streaming SVE set SVE get SVE for VL 5456
5146 10:53:39.203639 # ok 3419 # SKIP Streaming SVE set SVE get FPSIMD for VL 5456
5147 10:53:39.204063 # ok 3420 # SKIP Streaming SVE set FPSIMD get SVE for VL 5456
5148 10:53:39.204215 # ok 3421 Set Streaming SVE VL 5472
5149 10:53:39.204340 # ok 3422 # SKIP Streaming SVE set SVE get SVE for VL 5472
5150 10:53:39.204461 # ok 3423 # SKIP Streaming SVE set SVE get FPSIMD for VL 5472
5151 10:53:39.204580 # ok 3424 # SKIP Streaming SVE set FPSIMD get SVE for VL 5472
5152 10:53:39.204726 # ok 3425 Set Streaming SVE VL 5488
5153 10:53:39.204887 # ok 3426 # SKIP Streaming SVE set SVE get SVE for VL 5488
5154 10:53:39.205045 # ok 3427 # SKIP Streaming SVE set SVE get FPSIMD for VL 5488
5155 10:53:39.205241 # ok 3428 # SKIP Streaming SVE set FPSIMD get SVE for VL 5488
5156 10:53:39.205403 # ok 3429 Set Streaming SVE VL 5504
5157 10:53:39.205556 # ok 3430 # SKIP Streaming SVE set SVE get SVE for VL 5504
5158 10:53:39.205717 # ok 3431 # SKIP Streaming SVE set SVE get FPSIMD for VL 5504
5159 10:53:39.205882 # ok 3432 # SKIP Streaming SVE set FPSIMD get SVE for VL 5504
5160 10:53:39.206054 # ok 3433 Set Streaming SVE VL 5520
5161 10:53:39.206199 # ok 3434 # SKIP Streaming SVE set SVE get SVE for VL 5520
5162 10:53:39.206325 # ok 3435 # SKIP Streaming SVE set SVE get FPSIMD for VL 5520
5163 10:53:39.206489 # ok 3436 # SKIP Streaming SVE set FPSIMD get SVE for VL 5520
5164 10:53:39.206647 # ok 3437 Set Streaming SVE VL 5536
5165 10:53:39.206812 # ok 3438 # SKIP Streaming SVE set SVE get SVE for VL 5536
5166 10:53:39.206979 # ok 3439 # SKIP Streaming SVE set SVE get FPSIMD for VL 5536
5167 10:53:39.207144 # ok 3440 # SKIP Streaming SVE set FPSIMD get SVE for VL 5536
5168 10:53:39.207313 # ok 3441 Set Streaming SVE VL 5552
5169 10:53:39.207476 # ok 3442 # SKIP Streaming SVE set SVE get SVE for VL 5552
5170 10:53:39.207637 # ok 3443 # SKIP Streaming SVE set SVE get FPSIMD for VL 5552
5171 10:53:39.207803 # ok 3444 # SKIP Streaming SVE set FPSIMD get SVE for VL 5552
5172 10:53:39.207945 # ok 3445 Set Streaming SVE VL 5568
5173 10:53:39.208286 # ok 3446 # SKIP Streaming SVE set SVE get SVE for VL 5568
5174 10:53:39.208414 # ok 3447 # SKIP Streaming SVE set SVE get FPSIMD for VL 5568
5175 10:53:39.208532 # ok 3448 # SKIP Streaming SVE set FPSIMD get SVE for VL 5568
5176 10:53:39.208649 # ok 3449 Set Streaming SVE VL 5584
5177 10:53:39.208766 # ok 3450 # SKIP Streaming SVE set SVE get SVE for VL 5584
5178 10:53:39.208882 # ok 3451 # SKIP Streaming SVE set SVE get FPSIMD for VL 5584
5179 10:53:39.208999 # ok 3452 # SKIP Streaming SVE set FPSIMD get SVE for VL 5584
5180 10:53:39.209114 # ok 3453 Set Streaming SVE VL 5600
5181 10:53:39.209230 # ok 3454 # SKIP Streaming SVE set SVE get SVE for VL 5600
5182 10:53:39.209346 # ok 3455 # SKIP Streaming SVE set SVE get FPSIMD for VL 5600
5183 10:53:39.209462 # ok 3456 # SKIP Streaming SVE set FPSIMD get SVE for VL 5600
5184 10:53:39.209579 # ok 3457 Set Streaming SVE VL 5616
5185 10:53:39.209717 # ok 3458 # SKIP Streaming SVE set SVE get SVE for VL 5616
5186 10:53:39.217801 # ok 3459 # SKIP Streaming SVE set SVE get FPSIMD for VL 5616
5187 10:53:39.218256 # ok 3460 # SKIP Streaming SVE set FPSIMD get SVE for VL 5616
5188 10:53:39.218362 # ok 3461 Set Streaming SVE VL 5632
5189 10:53:39.218451 # ok 3462 # SKIP Streaming SVE set SVE get SVE for VL 5632
5190 10:53:39.218551 # ok 3463 # SKIP Streaming SVE set SVE get FPSIMD for VL 5632
5191 10:53:39.218641 # ok 3464 # SKIP Streaming SVE set FPSIMD get SVE for VL 5632
5192 10:53:39.218743 # ok 3465 Set Streaming SVE VL 5648
5193 10:53:39.218846 # ok 3466 # SKIP Streaming SVE set SVE get SVE for VL 5648
5194 10:53:39.218945 # ok 3467 # SKIP Streaming SVE set SVE get FPSIMD for VL 5648
5195 10:53:39.219291 # ok 3468 # SKIP Streaming SVE set FPSIMD get SVE for VL 5648
5196 10:53:39.219395 # ok 3469 Set Streaming SVE VL 5664
5197 10:53:39.219497 # ok 3470 # SKIP Streaming SVE set SVE get SVE for VL 5664
5198 10:53:39.219584 # ok 3471 # SKIP Streaming SVE set SVE get FPSIMD for VL 5664
5199 10:53:39.219689 # ok 3472 # SKIP Streaming SVE set FPSIMD get SVE for VL 5664
5200 10:53:39.219791 # ok 3473 Set Streaming SVE VL 5680
5201 10:53:39.225993 # ok 3474 # SKIP Streaming SVE set SVE get SVE for VL 5680
5202 10:53:39.226422 # ok 3475 # SKIP Streaming SVE set SVE get FPSIMD for VL 5680
5203 10:53:39.227114 # ok 3476 # SKIP Streaming SVE set FPSIMD get SVE for VL 5680
5204 10:53:39.227418 # ok 3477 Set Streaming SVE VL 5696
5205 10:53:39.227521 # ok 3478 # SKIP Streaming SVE set SVE get SVE for VL 5696
5206 10:53:39.227620 # ok 3479 # SKIP Streaming SVE set SVE get FPSIMD for VL 5696
5207 10:53:39.227703 # ok 3480 # SKIP Streaming SVE set FPSIMD get SVE for VL 5696
5208 10:53:39.227796 # ok 3481 Set Streaming SVE VL 5712
5209 10:53:39.228067 # ok 3482 # SKIP Streaming SVE set SVE get SVE for VL 5712
5210 10:53:39.233344 # ok 3483 # SKIP Streaming SVE set SVE get FPSIMD for VL 5712
5211 10:53:39.233556 # ok 3484 # SKIP Streaming SVE set FPSIMD get SVE for VL 5712
5212 10:53:39.233899 # ok 3485 Set Streaming SVE VL 5728
5213 10:53:39.234083 # ok 3486 # SKIP Streaming SVE set SVE get SVE for VL 5728
5214 10:53:39.234252 # ok 3487 # SKIP Streaming SVE set SVE get FPSIMD for VL 5728
5215 10:53:39.234419 # ok 3488 # SKIP Streaming SVE set FPSIMD get SVE for VL 5728
5216 10:53:39.234620 # ok 3489 Set Streaming SVE VL 5744
5217 10:53:39.234792 # ok 3490 # SKIP Streaming SVE set SVE get SVE for VL 5744
5218 10:53:39.234972 # ok 3491 # SKIP Streaming SVE set SVE get FPSIMD for VL 5744
5219 10:53:39.235164 # ok 3492 # SKIP Streaming SVE set FPSIMD get SVE for VL 5744
5220 10:53:39.235306 # ok 3493 Set Streaming SVE VL 5760
5221 10:53:39.235463 # ok 3494 # SKIP Streaming SVE set SVE get SVE for VL 5760
5222 10:53:39.235663 # ok 3495 # SKIP Streaming SVE set SVE get FPSIMD for VL 5760
5223 10:53:39.235846 # ok 3496 # SKIP Streaming SVE set FPSIMD get SVE for VL 5760
5224 10:53:39.236000 # ok 3497 Set Streaming SVE VL 5776
5225 10:53:39.236121 # ok 3498 # SKIP Streaming SVE set SVE get SVE for VL 5776
5226 10:53:39.236238 # ok 3499 # SKIP Streaming SVE set SVE get FPSIMD for VL 5776
5227 10:53:39.236400 # ok 3500 # SKIP Streaming SVE set FPSIMD get SVE for VL 5776
5228 10:53:39.236528 # ok 3501 Set Streaming SVE VL 5792
5229 10:53:39.236644 # ok 3502 # SKIP Streaming SVE set SVE get SVE for VL 5792
5230 10:53:39.236758 # ok 3503 # SKIP Streaming SVE set SVE get FPSIMD for VL 5792
5231 10:53:39.236871 # ok 3504 # SKIP Streaming SVE set FPSIMD get SVE for VL 5792
5232 10:53:39.237016 # ok 3505 Set Streaming SVE VL 5808
5233 10:53:39.237137 # ok 3506 # SKIP Streaming SVE set SVE get SVE for VL 5808
5234 10:53:39.241298 # ok 3507 # SKIP Streaming SVE set SVE get FPSIMD for VL 5808
5235 10:53:39.241839 # ok 3508 # SKIP Streaming SVE set FPSIMD get SVE for VL 5808
5236 10:53:39.242029 # ok 3509 Set Streaming SVE VL 5824
5237 10:53:39.242193 # ok 3510 # SKIP Streaming SVE set SVE get SVE for VL 5824
5238 10:53:39.242355 # ok 3511 # SKIP Streaming SVE set SVE get FPSIMD for VL 5824
5239 10:53:39.242502 # ok 3512 # SKIP Streaming SVE set FPSIMD get SVE for VL 5824
5240 10:53:39.242644 # ok 3513 Set Streaming SVE VL 5840
5241 10:53:39.242846 # ok 3514 # SKIP Streaming SVE set SVE get SVE for VL 5840
5242 10:53:39.243009 # ok 3515 # SKIP Streaming SVE set SVE get FPSIMD for VL 5840
5243 10:53:39.243169 # ok 3516 # SKIP Streaming SVE set FPSIMD get SVE for VL 5840
5244 10:53:39.243335 # ok 3517 Set Streaming SVE VL 5856
5245 10:53:39.243499 # ok 3518 # SKIP Streaming SVE set SVE get SVE for VL 5856
5246 10:53:39.243626 # ok 3519 # SKIP Streaming SVE set SVE get FPSIMD for VL 5856
5247 10:53:39.243749 # ok 3520 # SKIP Streaming SVE set FPSIMD get SVE for VL 5856
5248 10:53:39.243911 # ok 3521 Set Streaming SVE VL 5872
5249 10:53:39.244044 # ok 3522 # SKIP Streaming SVE set SVE get SVE for VL 5872
5250 10:53:39.244195 # ok 3523 # SKIP Streaming SVE set SVE get FPSIMD for VL 5872
5251 10:53:39.244332 # ok 3524 # SKIP Streaming SVE set FPSIMD get SVE for VL 5872
5252 10:53:39.244454 # ok 3525 Set Streaming SVE VL 5888
5253 10:53:39.244571 # ok 3526 # SKIP Streaming SVE set SVE get SVE for VL 5888
5254 10:53:39.244689 # ok 3527 # SKIP Streaming SVE set SVE get FPSIMD for VL 5888
5255 10:53:39.244809 # ok 3528 # SKIP Streaming SVE set FPSIMD get SVE for VL 5888
5256 10:53:39.244975 # ok 3529 Set Streaming SVE VL 5904
5257 10:53:39.245106 # ok 3530 # SKIP Streaming SVE set SVE get SVE for VL 5904
5258 10:53:39.245224 # ok 3531 # SKIP Streaming SVE set SVE get FPSIMD for VL 5904
5259 10:53:39.248552 # ok 3532 # SKIP Streaming SVE set FPSIMD get SVE for VL 5904
5260 10:53:39.248752 # ok 3533 Set Streaming SVE VL 5920
5261 10:53:39.249145 # ok 3534 # SKIP Streaming SVE set SVE get SVE for VL 5920
5262 10:53:39.249256 # ok 3535 # SKIP Streaming SVE set SVE get FPSIMD for VL 5920
5263 10:53:39.249349 # ok 3536 # SKIP Streaming SVE set FPSIMD get SVE for VL 5920
5264 10:53:39.249438 # ok 3537 Set Streaming SVE VL 5936
5265 10:53:39.249541 # ok 3538 # SKIP Streaming SVE set SVE get SVE for VL 5936
5266 10:53:39.249630 # ok 3539 # SKIP Streaming SVE set SVE get FPSIMD for VL 5936
5267 10:53:39.249727 # ok 3540 # SKIP Streaming SVE set FPSIMD get SVE for VL 5936
5268 10:53:39.249821 # ok 3541 Set Streaming SVE VL 5952
5269 10:53:39.249922 # ok 3542 # SKIP Streaming SVE set SVE get SVE for VL 5952
5270 10:53:39.250009 # ok 3543 # SKIP Streaming SVE set SVE get FPSIMD for VL 5952
5271 10:53:39.250110 # ok 3544 # SKIP Streaming SVE set FPSIMD get SVE for VL 5952
5272 10:53:39.250210 # ok 3545 Set Streaming SVE VL 5968
5273 10:53:39.250510 # ok 3546 # SKIP Streaming SVE set SVE get SVE for VL 5968
5274 10:53:39.250629 # ok 3547 # SKIP Streaming SVE set SVE get FPSIMD for VL 5968
5275 10:53:39.250733 # ok 3548 # SKIP Streaming SVE set FPSIMD get SVE for VL 5968
5276 10:53:39.251037 # ok 3549 Set Streaming SVE VL 5984
5277 10:53:39.251140 # ok 3550 # SKIP Streaming SVE set SVE get SVE for VL 5984
5278 10:53:39.251242 # ok 3551 # SKIP Streaming SVE set SVE get FPSIMD for VL 5984
5279 10:53:39.251577 # ok 3552 # SKIP Streaming SVE set FPSIMD get SVE for VL 5984
5280 10:53:39.251769 # ok 3553 Set Streaming SVE VL 6000
5281 10:53:39.252022 # ok 3554 # SKIP Streaming SVE set SVE get SVE for VL 6000
5282 10:53:39.252159 # ok 3555 # SKIP Streaming SVE set SVE get FPSIMD for VL 6000
5283 10:53:39.259701 # ok 3556 # SKIP Streaming SVE set FPSIMD get SVE for VL 6000
5284 10:53:39.260292 # ok 3557 Set Streaming SVE VL 6016
5285 10:53:39.260463 # ok 3558 # SKIP Streaming SVE set SVE get SVE for VL 6016
5286 10:53:39.260921 # ok 3559 # SKIP Streaming SVE set SVE get FPSIMD for VL 6016
5287 10:53:39.261324 # ok 3560 # SKIP Streaming SVE set FPSIMD get SVE for VL 6016
5288 10:53:39.261529 # ok 3561 Set Streaming SVE VL 6032
5289 10:53:39.261739 # ok 3562 # SKIP Streaming SVE set SVE get SVE for VL 6032
5290 10:53:39.262155 # ok 3563 # SKIP Streaming SVE set SVE get FPSIMD for VL 6032
5291 10:53:39.262359 # ok 3564 # SKIP Streaming SVE set FPSIMD get SVE for VL 6032
5292 10:53:39.262554 # ok 3565 Set Streaming SVE VL 6048
5293 10:53:39.262954 # ok 3566 # SKIP Streaming SVE set SVE get SVE for VL 6048
5294 10:53:39.263107 # ok 3567 # SKIP Streaming SVE set SVE get FPSIMD for VL 6048
5295 10:53:39.263443 # ok 3568 # SKIP Streaming SVE set FPSIMD get SVE for VL 6048
5296 10:53:39.263919 # ok 3569 Set Streaming SVE VL 6064
5297 10:53:39.264055 # ok 3570 # SKIP Streaming SVE set SVE get SVE for VL 6064
5298 10:53:39.264176 # ok 3571 # SKIP Streaming SVE set SVE get FPSIMD for VL 6064
5299 10:53:39.264292 # ok 3572 # SKIP Streaming SVE set FPSIMD get SVE for VL 6064
5300 10:53:39.273008 # ok 3573 Set Streaming SVE VL 6080
5301 10:53:39.273482 # ok 3574 # SKIP Streaming SVE set SVE get SVE for VL 6080
5302 10:53:39.273589 # ok 3575 # SKIP Streaming SVE set SVE get FPSIMD for VL 6080
5303 10:53:39.273687 # ok 3576 # SKIP Streaming SVE set FPSIMD get SVE for VL 6080
5304 10:53:39.273776 # ok 3577 Set Streaming SVE VL 6096
5305 10:53:39.273879 # ok 3578 # SKIP Streaming SVE set SVE get SVE for VL 6096
5306 10:53:39.273965 # ok 3579 # SKIP Streaming SVE set SVE get FPSIMD for VL 6096
5307 10:53:39.274067 # ok 3580 # SKIP Streaming SVE set FPSIMD get SVE for VL 6096
5308 10:53:39.274152 # ok 3581 Set Streaming SVE VL 6112
5309 10:53:39.274259 # ok 3582 # SKIP Streaming SVE set SVE get SVE for VL 6112
5310 10:53:39.274558 # ok 3583 # SKIP Streaming SVE set SVE get FPSIMD for VL 6112
5311 10:53:39.274678 # ok 3584 # SKIP Streaming SVE set FPSIMD get SVE for VL 6112
5312 10:53:39.274781 # ok 3585 Set Streaming SVE VL 6128
5313 10:53:39.275102 # ok 3586 # SKIP Streaming SVE set SVE get SVE for VL 6128
5314 10:53:39.275315 # ok 3587 # SKIP Streaming SVE set SVE get FPSIMD for VL 6128
5315 10:53:39.275478 # ok 3588 # SKIP Streaming SVE set FPSIMD get SVE for VL 6128
5316 10:53:39.275627 # ok 3589 Set Streaming SVE VL 6144
5317 10:53:39.275812 # ok 3590 # SKIP Streaming SVE set SVE get SVE for VL 6144
5318 10:53:39.275974 # ok 3591 # SKIP Streaming SVE set SVE get FPSIMD for VL 6144
5319 10:53:39.276149 # ok 3592 # SKIP Streaming SVE set FPSIMD get SVE for VL 6144
5320 10:53:39.276295 # ok 3593 Set Streaming SVE VL 6160
5321 10:53:39.285097 # ok 3594 # SKIP Streaming SVE set SVE get SVE for VL 6160
5322 10:53:39.285642 # ok 3595 # SKIP Streaming SVE set SVE get FPSIMD for VL 6160
5323 10:53:39.285852 # ok 3596 # SKIP Streaming SVE set FPSIMD get SVE for VL 6160
5324 10:53:39.286037 # ok 3597 Set Streaming SVE VL 6176
5325 10:53:39.286211 # ok 3598 # SKIP Streaming SVE set SVE get SVE for VL 6176
5326 10:53:39.286392 # ok 3599 # SKIP Streaming SVE set SVE get FPSIMD for VL 6176
5327 10:53:39.286546 # ok 3600 # SKIP Streaming SVE set FPSIMD get SVE for VL 6176
5328 10:53:39.286714 # ok 3601 Set Streaming SVE VL 6192
5329 10:53:39.286877 # ok 3602 # SKIP Streaming SVE set SVE get SVE for VL 6192
5330 10:53:39.287022 # ok 3603 # SKIP Streaming SVE set SVE get FPSIMD for VL 6192
5331 10:53:39.287170 # ok 3604 # SKIP Streaming SVE set FPSIMD get SVE for VL 6192
5332 10:53:39.287292 # ok 3605 Set Streaming SVE VL 6208
5333 10:53:39.287407 # ok 3606 # SKIP Streaming SVE set SVE get SVE for VL 6208
5334 10:53:39.287524 # ok 3607 # SKIP Streaming SVE set SVE get FPSIMD for VL 6208
5335 10:53:39.287639 # ok 3608 # SKIP Streaming SVE set FPSIMD get SVE for VL 6208
5336 10:53:39.287753 # ok 3609 Set Streaming SVE VL 6224
5337 10:53:39.287892 # ok 3610 # SKIP Streaming SVE set SVE get SVE for VL 6224
5338 10:53:39.288012 # ok 3611 # SKIP Streaming SVE set SVE get FPSIMD for VL 6224
5339 10:53:39.288127 # ok 3612 # SKIP Streaming SVE set FPSIMD get SVE for VL 6224
5340 10:53:39.288241 # ok 3613 Set Streaming SVE VL 6240
5341 10:53:39.288356 # ok 3614 # SKIP Streaming SVE set SVE get SVE for VL 6240
5342 10:53:39.288491 # ok 3615 # SKIP Streaming SVE set SVE get FPSIMD for VL 6240
5343 10:53:39.301908 # ok 3616 # SKIP Streaming SVE set FPSIMD get SVE for VL 6240
5344 10:53:39.302490 # ok 3617 Set Streaming SVE VL 6256
5345 10:53:39.302738 # ok 3618 # SKIP Streaming SVE set SVE get SVE for VL 6256
5346 10:53:39.302930 # ok 3619 # SKIP Streaming SVE set SVE get FPSIMD for VL 6256
5347 10:53:39.303137 # ok 3620 # SKIP Streaming SVE set FPSIMD get SVE for VL 6256
5348 10:53:39.303314 # ok 3621 Set Streaming SVE VL 6272
5349 10:53:39.303442 # ok 3622 # SKIP Streaming SVE set SVE get SVE for VL 6272
5350 10:53:39.303562 # ok 3623 # SKIP Streaming SVE set SVE get FPSIMD for VL 6272
5351 10:53:39.303679 # ok 3624 # SKIP Streaming SVE set FPSIMD get SVE for VL 6272
5352 10:53:39.303795 # ok 3625 Set Streaming SVE VL 6288
5353 10:53:39.315087 # ok 3626 # SKIP Streaming SVE set SVE get SVE for VL 6288
5354 10:53:39.315434 # ok 3627 # SKIP Streaming SVE set SVE get FPSIMD for VL 6288
5355 10:53:39.315675 # ok 3628 # SKIP Streaming SVE set FPSIMD get SVE for VL 6288
5356 10:53:39.315854 # ok 3629 Set Streaming SVE VL 6304
5357 10:53:39.316063 # ok 3630 # SKIP Streaming SVE set SVE get SVE for VL 6304
5358 10:53:39.316218 # ok 3631 # SKIP Streaming SVE set SVE get FPSIMD for VL 6304
5359 10:53:39.316397 # ok 3632 # SKIP Streaming SVE set FPSIMD get SVE for VL 6304
5360 10:53:39.316538 # ok 3633 Set Streaming SVE VL 6320
5361 10:53:39.316689 # ok 3634 # SKIP Streaming SVE set SVE get SVE for VL 6320
5362 10:53:39.325777 # ok 3635 # SKIP Streaming SVE set SVE get FPSIMD for VL 6320
5363 10:53:39.326131 # ok 3636 # SKIP Streaming SVE set FPSIMD get SVE for VL 6320
5364 10:53:39.326368 # ok 3637 Set Streaming SVE VL 6336
5365 10:53:39.326542 # ok 3638 # SKIP Streaming SVE set SVE get SVE for VL 6336
5366 10:53:39.326726 # ok 3639 # SKIP Streaming SVE set SVE get FPSIMD for VL 6336
5367 10:53:39.326915 # ok 3640 # SKIP Streaming SVE set FPSIMD get SVE for VL 6336
5368 10:53:39.327076 # ok 3641 Set Streaming SVE VL 6352
5369 10:53:39.327258 # ok 3642 # SKIP Streaming SVE set SVE get SVE for VL 6352
5370 10:53:39.327439 # ok 3643 # SKIP Streaming SVE set SVE get FPSIMD for VL 6352
5371 10:53:39.327619 # ok 3644 # SKIP Streaming SVE set FPSIMD get SVE for VL 6352
5372 10:53:39.327811 # ok 3645 Set Streaming SVE VL 6368
5373 10:53:39.327988 # ok 3646 # SKIP Streaming SVE set SVE get SVE for VL 6368
5374 10:53:39.341227 # ok 3647 # SKIP Streaming SVE set SVE get FPSIMD for VL 6368
5375 10:53:39.341707 # ok 3648 # SKIP Streaming SVE set FPSIMD get SVE for VL 6368
5376 10:53:39.341904 # ok 3649 Set Streaming SVE VL 6384
5377 10:53:39.342125 # ok 3650 # SKIP Streaming SVE set SVE get SVE for VL 6384
5378 10:53:39.342389 # ok 3651 # SKIP Streaming SVE set SVE get FPSIMD for VL 6384
5379 10:53:39.342587 # ok 3652 # SKIP Streaming SVE set FPSIMD get SVE for VL 6384
5380 10:53:39.342755 # ok 3653 Set Streaming SVE VL 6400
5381 10:53:39.342952 # ok 3654 # SKIP Streaming SVE set SVE get SVE for VL 6400
5382 10:53:39.343146 # ok 3655 # SKIP Streaming SVE set SVE get FPSIMD for VL 6400
5383 10:53:39.343354 # ok 3656 # SKIP Streaming SVE set FPSIMD get SVE for VL 6400
5384 10:53:39.343555 # ok 3657 Set Streaming SVE VL 6416
5385 10:53:39.343767 # ok 3658 # SKIP Streaming SVE set SVE get SVE for VL 6416
5386 10:53:39.343967 # ok 3659 # SKIP Streaming SVE set SVE get FPSIMD for VL 6416
5387 10:53:39.344104 # ok 3660 # SKIP Streaming SVE set FPSIMD get SVE for VL 6416
5388 10:53:39.344222 # ok 3661 Set Streaming SVE VL 6432
5389 10:53:39.344364 # ok 3662 # SKIP Streaming SVE set SVE get SVE for VL 6432
5390 10:53:39.344485 # ok 3663 # SKIP Streaming SVE set SVE get FPSIMD for VL 6432
5391 10:53:39.353354 # ok 3664 # SKIP Streaming SVE set FPSIMD get SVE for VL 6432
5392 10:53:39.353572 # ok 3665 Set Streaming SVE VL 6448
5393 10:53:39.353973 # ok 3666 # SKIP Streaming SVE set SVE get SVE for VL 6448
5394 10:53:39.354179 # ok 3667 # SKIP Streaming SVE set SVE get FPSIMD for VL 6448
5395 10:53:39.354362 # ok 3668 # SKIP Streaming SVE set FPSIMD get SVE for VL 6448
5396 10:53:39.354556 # ok 3669 Set Streaming SVE VL 6464
5397 10:53:39.354784 # ok 3670 # SKIP Streaming SVE set SVE get SVE for VL 6464
5398 10:53:39.354946 # ok 3671 # SKIP Streaming SVE set SVE get FPSIMD for VL 6464
5399 10:53:39.355124 # ok 3672 # SKIP Streaming SVE set FPSIMD get SVE for VL 6464
5400 10:53:39.355279 # ok 3673 Set Streaming SVE VL 6480
5401 10:53:39.355517 # ok 3674 # SKIP Streaming SVE set SVE get SVE for VL 6480
5402 10:53:39.355705 # ok 3675 # SKIP Streaming SVE set SVE get FPSIMD for VL 6480
5403 10:53:39.355872 # ok 3676 # SKIP Streaming SVE set FPSIMD get SVE for VL 6480
5404 10:53:39.356042 # ok 3677 Set Streaming SVE VL 6496
5405 10:53:39.356206 # ok 3678 # SKIP Streaming SVE set SVE get SVE for VL 6496
5406 10:53:39.356367 # ok 3679 # SKIP Streaming SVE set SVE get FPSIMD for VL 6496
5407 10:53:39.356493 # ok 3680 # SKIP Streaming SVE set FPSIMD get SVE for VL 6496
5408 10:53:39.356612 # ok 3681 Set Streaming SVE VL 6512
5409 10:53:39.356727 # ok 3682 # SKIP Streaming SVE set SVE get SVE for VL 6512
5410 10:53:39.365505 # ok 3683 # SKIP Streaming SVE set SVE get FPSIMD for VL 6512
5411 10:53:39.365742 # ok 3684 # SKIP Streaming SVE set FPSIMD get SVE for VL 6512
5412 10:53:39.365894 # ok 3685 Set Streaming SVE VL 6528
5413 10:53:39.366078 # ok 3686 # SKIP Streaming SVE set SVE get SVE for VL 6528
5414 10:53:39.366231 # ok 3687 # SKIP Streaming SVE set SVE get FPSIMD for VL 6528
5415 10:53:39.366378 # ok 3688 # SKIP Streaming SVE set FPSIMD get SVE for VL 6528
5416 10:53:39.366569 # ok 3689 Set Streaming SVE VL 6544
5417 10:53:39.366755 # ok 3690 # SKIP Streaming SVE set SVE get SVE for VL 6544
5418 10:53:39.366933 # ok 3691 # SKIP Streaming SVE set SVE get FPSIMD for VL 6544
5419 10:53:39.367148 # ok 3692 # SKIP Streaming SVE set FPSIMD get SVE for VL 6544
5420 10:53:39.367315 # ok 3693 Set Streaming SVE VL 6560
5421 10:53:39.367468 # ok 3694 # SKIP Streaming SVE set SVE get SVE for VL 6560
5422 10:53:39.367646 # ok 3695 # SKIP Streaming SVE set SVE get FPSIMD for VL 6560
5423 10:53:39.367844 # ok 3696 # SKIP Streaming SVE set FPSIMD get SVE for VL 6560
5424 10:53:39.367986 # ok 3697 Set Streaming SVE VL 6576
5425 10:53:39.368110 # ok 3698 # SKIP Streaming SVE set SVE get SVE for VL 6576
5426 10:53:39.368228 # ok 3699 # SKIP Streaming SVE set SVE get FPSIMD for VL 6576
5427 10:53:39.368368 # ok 3700 # SKIP Streaming SVE set FPSIMD get SVE for VL 6576
5428 10:53:39.368487 # ok 3701 Set Streaming SVE VL 6592
5429 10:53:39.368603 # ok 3702 # SKIP Streaming SVE set SVE get SVE for VL 6592
5430 10:53:39.368718 # ok 3703 # SKIP Streaming SVE set SVE get FPSIMD for VL 6592
5431 10:53:39.371405 # ok 3704 # SKIP Streaming SVE set FPSIMD get SVE for VL 6592
5432 10:53:39.371750 # ok 3705 Set Streaming SVE VL 6608
5433 10:53:39.372122 # ok 3706 # SKIP Streaming SVE set SVE get SVE for VL 6608
5434 10:53:39.372287 # ok 3707 # SKIP Streaming SVE set SVE get FPSIMD for VL 6608
5435 10:53:39.372436 # ok 3708 # SKIP Streaming SVE set FPSIMD get SVE for VL 6608
5436 10:53:39.372580 # ok 3709 Set Streaming SVE VL 6624
5437 10:53:39.372722 # ok 3710 # SKIP Streaming SVE set SVE get SVE for VL 6624
5438 10:53:39.377489 # ok 3711 # SKIP Streaming SVE set SVE get FPSIMD for VL 6624
5439 10:53:39.377768 # ok 3712 # SKIP Streaming SVE set FPSIMD get SVE for VL 6624
5440 10:53:39.377989 # ok 3713 Set Streaming SVE VL 6640
5441 10:53:39.378168 # ok 3714 # SKIP Streaming SVE set SVE get SVE for VL 6640
5442 10:53:39.378426 # ok 3715 # SKIP Streaming SVE set SVE get FPSIMD for VL 6640
5443 10:53:39.378630 # ok 3716 # SKIP Streaming SVE set FPSIMD get SVE for VL 6640
5444 10:53:39.378805 # ok 3717 Set Streaming SVE VL 6656
5445 10:53:39.378956 # ok 3718 # SKIP Streaming SVE set SVE get SVE for VL 6656
5446 10:53:39.379137 # ok 3719 # SKIP Streaming SVE set SVE get FPSIMD for VL 6656
5447 10:53:39.379276 # ok 3720 # SKIP Streaming SVE set FPSIMD get SVE for VL 6656
5448 10:53:39.379420 # ok 3721 Set Streaming SVE VL 6672
5449 10:53:39.379563 # ok 3722 # SKIP Streaming SVE set SVE get SVE for VL 6672
5450 10:53:39.379705 # ok 3723 # SKIP Streaming SVE set SVE get FPSIMD for VL 6672
5451 10:53:39.379881 # ok 3724 # SKIP Streaming SVE set FPSIMD get SVE for VL 6672
5452 10:53:39.380017 # ok 3725 Set Streaming SVE VL 6688
5453 10:53:39.380163 # ok 3726 # SKIP Streaming SVE set SVE get SVE for VL 6688
5454 10:53:39.380306 # ok 3727 # SKIP Streaming SVE set SVE get FPSIMD for VL 6688
5455 10:53:39.385349 # ok 3728 # SKIP Streaming SVE set FPSIMD get SVE for VL 6688
5456 10:53:39.385735 # ok 3729 Set Streaming SVE VL 6704
5457 10:53:39.385938 # ok 3730 # SKIP Streaming SVE set SVE get SVE for VL 6704
5458 10:53:39.386112 # ok 3731 # SKIP Streaming SVE set SVE get FPSIMD for VL 6704
5459 10:53:39.386243 # ok 3732 # SKIP Streaming SVE set FPSIMD get SVE for VL 6704
5460 10:53:39.386362 # ok 3733 Set Streaming SVE VL 6720
5461 10:53:39.386806 # ok 3734 # SKIP Streaming SVE set SVE get SVE for VL 6720
5462 10:53:39.386972 # ok 3735 # SKIP Streaming SVE set SVE get FPSIMD for VL 6720
5463 10:53:39.387102 # ok 3736 # SKIP Streaming SVE set FPSIMD get SVE for VL 6720
5464 10:53:39.387224 # ok 3737 Set Streaming SVE VL 6736
5465 10:53:39.387358 # ok 3738 # SKIP Streaming SVE set SVE get SVE for VL 6736
5466 10:53:39.387772 # ok 3739 # SKIP Streaming SVE set SVE get FPSIMD for VL 6736
5467 10:53:39.387947 # ok 3740 # SKIP Streaming SVE set FPSIMD get SVE for VL 6736
5468 10:53:39.388120 # ok 3741 Set Streaming SVE VL 6752
5469 10:53:39.388267 # ok 3742 # SKIP Streaming SVE set SVE get SVE for VL 6752
5470 10:53:39.388413 # ok 3743 # SKIP Streaming SVE set SVE get FPSIMD for VL 6752
5471 10:53:39.388555 # ok 3744 # SKIP Streaming SVE set FPSIMD get SVE for VL 6752
5472 10:53:39.388731 # ok 3745 Set Streaming SVE VL 6768
5473 10:53:39.388869 # ok 3746 # SKIP Streaming SVE set SVE get SVE for VL 6768
5474 10:53:39.393570 # ok 3747 # SKIP Streaming SVE set SVE get FPSIMD for VL 6768
5475 10:53:39.393807 # ok 3748 # SKIP Streaming SVE set FPSIMD get SVE for VL 6768
5476 10:53:39.394000 # ok 3749 Set Streaming SVE VL 6784
5477 10:53:39.394175 # ok 3750 # SKIP Streaming SVE set SVE get SVE for VL 6784
5478 10:53:39.394344 # ok 3751 # SKIP Streaming SVE set SVE get FPSIMD for VL 6784
5479 10:53:39.394510 # ok 3752 # SKIP Streaming SVE set FPSIMD get SVE for VL 6784
5480 10:53:39.394679 # ok 3753 Set Streaming SVE VL 6800
5481 10:53:39.394848 # ok 3754 # SKIP Streaming SVE set SVE get SVE for VL 6800
5482 10:53:39.394987 # ok 3755 # SKIP Streaming SVE set SVE get FPSIMD for VL 6800
5483 10:53:39.395163 # ok 3756 # SKIP Streaming SVE set FPSIMD get SVE for VL 6800
5484 10:53:39.395301 # ok 3757 Set Streaming SVE VL 6816
5485 10:53:39.395476 # ok 3758 # SKIP Streaming SVE set SVE get SVE for VL 6816
5486 10:53:39.395614 # ok 3759 # SKIP Streaming SVE set SVE get FPSIMD for VL 6816
5487 10:53:39.395787 # ok 3760 # SKIP Streaming SVE set FPSIMD get SVE for VL 6816
5488 10:53:39.395925 # ok 3761 Set Streaming SVE VL 6832
5489 10:53:39.396098 # ok 3762 # SKIP Streaming SVE set SVE get SVE for VL 6832
5490 10:53:39.402269 # ok 3763 # SKIP Streaming SVE set SVE get FPSIMD for VL 6832
5491 10:53:39.403209 # ok 3764 # SKIP Streaming SVE set FPSIMD get SVE for VL 6832
5492 10:53:39.403413 # ok 3765 Set Streaming SVE VL 6848
5493 10:53:39.403600 # ok 3766 # SKIP Streaming SVE set SVE get SVE for VL 6848
5494 10:53:39.403822 # ok 3767 # SKIP Streaming SVE set SVE get FPSIMD for VL 6848
5495 10:53:39.404043 # ok 3768 # SKIP Streaming SVE set FPSIMD get SVE for VL 6848
5496 10:53:39.404193 # ok 3769 Set Streaming SVE VL 6864
5497 10:53:39.404339 # ok 3770 # SKIP Streaming SVE set SVE get SVE for VL 6864
5498 10:53:39.404521 # ok 3771 # SKIP Streaming SVE set SVE get FPSIMD for VL 6864
5499 10:53:39.404718 # ok 3772 # SKIP Streaming SVE set FPSIMD get SVE for VL 6864
5500 10:53:39.404910 # ok 3773 Set Streaming SVE VL 6880
5501 10:53:39.405082 # ok 3774 # SKIP Streaming SVE set SVE get SVE for VL 6880
5502 10:53:39.653732 # ok 3775 # SKIP Streaming SVE set SVE get FPSIMD for VL 6880
5503 10:53:39.653996 # ok 3776 # SKIP Streaming SVE set FPSIMD get SVE for VL 6880
5504 10:53:39.654094 # ok 3777 Set Streaming SVE VL 6896
5505 10:53:39.654201 # ok 3778 # SKIP Streaming SVE set SVE get SVE for VL 6896
5506 10:53:39.654291 # ok 3779 # SKIP Streaming SVE set SVE get FPSIMD for VL 6896
5507 10:53:39.655253 # ok 3780 # SKIP Streaming SVE set FPSIMD get SVE for VL 6896
5508 10:53:39.655362 # ok 3781 Set Streaming SVE VL 6912
5509 10:53:39.655449 # ok 3782 # SKIP Streaming SVE set SVE get SVE for VL 6912
5510 10:53:39.655532 # ok 3783 # SKIP Streaming SVE set SVE get FPSIMD for VL 6912
5511 10:53:39.655615 # ok 3784 # SKIP Streaming SVE set FPSIMD get SVE for VL 6912
5512 10:53:39.655697 # ok 3785 Set Streaming SVE VL 6928
5513 10:53:39.655779 # ok 3786 # SKIP Streaming SVE set SVE get SVE for VL 6928
5514 10:53:39.655859 # ok 3787 # SKIP Streaming SVE set SVE get FPSIMD for VL 6928
5515 10:53:39.655941 # ok 3788 # SKIP Streaming SVE set FPSIMD get SVE for VL 6928
5516 10:53:39.656224 # ok 3789 Set Streaming SVE VL 6944
5517 10:53:39.656330 # ok 3790 # SKIP Streaming SVE set SVE get SVE for VL 6944
5518 10:53:39.656418 # ok 3791 # SKIP Streaming SVE set SVE get FPSIMD for VL 6944
5519 10:53:39.656502 # ok 3792 # SKIP Streaming SVE set FPSIMD get SVE for VL 6944
5520 10:53:39.656586 # ok 3793 Set Streaming SVE VL 6960
5521 10:53:39.656668 # ok 3794 # SKIP Streaming SVE set SVE get SVE for VL 6960
5522 10:53:39.656752 # ok 3795 # SKIP Streaming SVE set SVE get FPSIMD for VL 6960
5523 10:53:39.658620 # ok 3796 # SKIP Streaming SVE set FPSIMD get SVE for VL 6960
5524 10:53:39.659067 # ok 3797 Set Streaming SVE VL 6976
5525 10:53:39.659175 # ok 3798 # SKIP Streaming SVE set SVE get SVE for VL 6976
5526 10:53:39.659261 # ok 3799 # SKIP Streaming SVE set SVE get FPSIMD for VL 6976
5527 10:53:39.659359 # ok 3800 # SKIP Streaming SVE set FPSIMD get SVE for VL 6976
5528 10:53:39.659443 # ok 3801 Set Streaming SVE VL 6992
5529 10:53:39.659527 # ok 3802 # SKIP Streaming SVE set SVE get SVE for VL 6992
5530 10:53:39.659625 # ok 3803 # SKIP Streaming SVE set SVE get FPSIMD for VL 6992
5531 10:53:39.659709 # ok 3804 # SKIP Streaming SVE set FPSIMD get SVE for VL 6992
5532 10:53:39.659804 # ok 3805 Set Streaming SVE VL 7008
5533 10:53:39.659901 # ok 3806 # SKIP Streaming SVE set SVE get SVE for VL 7008
5534 10:53:39.659985 # ok 3807 # SKIP Streaming SVE set SVE get FPSIMD for VL 7008
5535 10:53:39.660081 # ok 3808 # SKIP Streaming SVE set FPSIMD get SVE for VL 7008
5536 10:53:39.669268 # ok 3809 Set Streaming SVE VL 7024
5537 10:53:39.669727 # ok 3810 # SKIP Streaming SVE set SVE get SVE for VL 7024
5538 10:53:39.669892 # ok 3811 # SKIP Streaming SVE set SVE get FPSIMD for VL 7024
5539 10:53:39.670089 # ok 3812 # SKIP Streaming SVE set FPSIMD get SVE for VL 7024
5540 10:53:39.670297 # ok 3813 Set Streaming SVE VL 7040
5541 10:53:39.670466 # ok 3814 # SKIP Streaming SVE set SVE get SVE for VL 7040
5542 10:53:39.670659 # ok 3815 # SKIP Streaming SVE set SVE get FPSIMD for VL 7040
5543 10:53:39.670825 # ok 3816 # SKIP Streaming SVE set FPSIMD get SVE for VL 7040
5544 10:53:39.670989 # ok 3817 Set Streaming SVE VL 7056
5545 10:53:39.671176 # ok 3818 # SKIP Streaming SVE set SVE get SVE for VL 7056
5546 10:53:39.671366 # ok 3819 # SKIP Streaming SVE set SVE get FPSIMD for VL 7056
5547 10:53:39.671514 # ok 3820 # SKIP Streaming SVE set FPSIMD get SVE for VL 7056
5548 10:53:39.671667 # ok 3821 Set Streaming SVE VL 7072
5549 10:53:39.671826 # ok 3822 # SKIP Streaming SVE set SVE get SVE for VL 7072
5550 10:53:39.672013 # ok 3823 # SKIP Streaming SVE set SVE get FPSIMD for VL 7072
5551 10:53:39.672150 # ok 3824 # SKIP Streaming SVE set FPSIMD get SVE for VL 7072
5552 10:53:39.672269 # ok 3825 Set Streaming SVE VL 7088
5553 10:53:39.672384 # ok 3826 # SKIP Streaming SVE set SVE get SVE for VL 7088
5554 10:53:39.672500 # ok 3827 # SKIP Streaming SVE set SVE get FPSIMD for VL 7088
5555 10:53:39.672640 # ok 3828 # SKIP Streaming SVE set FPSIMD get SVE for VL 7088
5556 10:53:39.717958 # ok 3829 Set Streaming SVE VL 7104
5557 10:53:39.718433 # ok 3830 # SKIP Streaming SVE set SVE get SVE for VL 7104
5558 10:53:39.718545 # ok 3831 # SKIP Streaming SVE set SVE get FPSIMD for VL 7104
5559 10:53:39.718634 # ok 3832 # SKIP Streaming SVE set FPSIMD get SVE for VL 7104
5560 10:53:39.718737 # ok 3833 Set Streaming SVE VL 7120
5561 10:53:39.718821 # ok 3834 # SKIP Streaming SVE set SVE get SVE for VL 7120
5562 10:53:39.718919 # ok 3835 # SKIP Streaming SVE set SVE get FPSIMD for VL 7120
5563 10:53:39.719003 # ok 3836 # SKIP Streaming SVE set FPSIMD get SVE for VL 7120
5564 10:53:39.719099 # ok 3837 Set Streaming SVE VL 7136
5565 10:53:39.719198 # ok 3838 # SKIP Streaming SVE set SVE get SVE for VL 7136
5566 10:53:39.719298 # ok 3839 # SKIP Streaming SVE set SVE get FPSIMD for VL 7136
5567 10:53:39.719604 # ok 3840 # SKIP Streaming SVE set FPSIMD get SVE for VL 7136
5568 10:53:39.719713 # ok 3841 Set Streaming SVE VL 7152
5569 10:53:39.719811 # ok 3842 # SKIP Streaming SVE set SVE get SVE for VL 7152
5570 10:53:39.719910 # ok 3843 # SKIP Streaming SVE set SVE get FPSIMD for VL 7152
5571 10:53:39.720010 # ok 3844 # SKIP Streaming SVE set FPSIMD get SVE for VL 7152
5572 10:53:39.720109 # ok 3845 Set Streaming SVE VL 7168
5573 10:53:39.720207 # ok 3846 # SKIP Streaming SVE set SVE get SVE for VL 7168
5574 10:53:39.731085 # ok 3847 # SKIP Streaming SVE set SVE get FPSIMD for VL 7168
5575 10:53:39.731392 # ok 3848 # SKIP Streaming SVE set FPSIMD get SVE for VL 7168
5576 10:53:39.731496 # ok 3849 Set Streaming SVE VL 7184
5577 10:53:39.731598 # ok 3850 # SKIP Streaming SVE set SVE get SVE for VL 7184
5578 10:53:39.731693 # ok 3851 # SKIP Streaming SVE set SVE get FPSIMD for VL 7184
5579 10:53:39.731786 # ok 3852 # SKIP Streaming SVE set FPSIMD get SVE for VL 7184
5580 10:53:39.731867 # ok 3853 Set Streaming SVE VL 7200
5581 10:53:39.731959 # ok 3854 # SKIP Streaming SVE set SVE get SVE for VL 7200
5582 10:53:39.732052 # ok 3855 # SKIP Streaming SVE set SVE get FPSIMD for VL 7200
5583 10:53:39.737491 # ok 3856 # SKIP Streaming SVE set FPSIMD get SVE for VL 7200
5584 10:53:39.737894 # ok 3857 Set Streaming SVE VL 7216
5585 10:53:39.738004 # ok 3858 # SKIP Streaming SVE set SVE get SVE for VL 7216
5586 10:53:39.738092 # ok 3859 # SKIP Streaming SVE set SVE get FPSIMD for VL 7216
5587 10:53:39.738378 # ok 3860 # SKIP Streaming SVE set FPSIMD get SVE for VL 7216
5588 10:53:39.738480 # ok 3861 Set Streaming SVE VL 7232
5589 10:53:39.738566 # ok 3862 # SKIP Streaming SVE set SVE get SVE for VL 7232
5590 10:53:39.738647 # ok 3863 # SKIP Streaming SVE set SVE get FPSIMD for VL 7232
5591 10:53:39.738743 # ok 3864 # SKIP Streaming SVE set FPSIMD get SVE for VL 7232
5592 10:53:39.738826 # ok 3865 Set Streaming SVE VL 7248
5593 10:53:39.738923 # ok 3866 # SKIP Streaming SVE set SVE get SVE for VL 7248
5594 10:53:39.739247 # ok 3867 # SKIP Streaming SVE set SVE get FPSIMD for VL 7248
5595 10:53:39.739743 # ok 3868 # SKIP Streaming SVE set FPSIMD get SVE for VL 7248
5596 10:53:39.739872 # ok 3869 Set Streaming SVE VL 7264
5597 10:53:39.739988 # ok 3870 # SKIP Streaming SVE set SVE get SVE for VL 7264
5598 10:53:39.740076 # ok 3871 # SKIP Streaming SVE set SVE get FPSIMD for VL 7264
5599 10:53:39.740160 # ok 3872 # SKIP Streaming SVE set FPSIMD get SVE for VL 7264
5600 10:53:39.740244 # ok 3873 Set Streaming SVE VL 7280
5601 10:53:39.740327 # ok 3874 # SKIP Streaming SVE set SVE get SVE for VL 7280
5602 10:53:39.740410 # ok 3875 # SKIP Streaming SVE set SVE get FPSIMD for VL 7280
5603 10:53:39.740494 # ok 3876 # SKIP Streaming SVE set FPSIMD get SVE for VL 7280
5604 10:53:39.740578 # ok 3877 Set Streaming SVE VL 7296
5605 10:53:39.744781 # ok 3878 # SKIP Streaming SVE set SVE get SVE for VL 7296
5606 10:53:39.745278 # ok 3879 # SKIP Streaming SVE set SVE get FPSIMD for VL 7296
5607 10:53:39.745477 # ok 3880 # SKIP Streaming SVE set FPSIMD get SVE for VL 7296
5608 10:53:39.745655 # ok 3881 Set Streaming SVE VL 7312
5609 10:53:39.746038 # ok 3882 # SKIP Streaming SVE set SVE get SVE for VL 7312
5610 10:53:39.746193 # ok 3883 # SKIP Streaming SVE set SVE get FPSIMD for VL 7312
5611 10:53:39.746368 # ok 3884 # SKIP Streaming SVE set FPSIMD get SVE for VL 7312
5612 10:53:39.746502 # ok 3885 Set Streaming SVE VL 7328
5613 10:53:39.746617 # ok 3886 # SKIP Streaming SVE set SVE get SVE for VL 7328
5614 10:53:39.748285 # ok 3887 # SKIP Streaming SVE set SVE get FPSIMD for VL 7328
5615 10:53:39.748397 # ok 3888 # SKIP Streaming SVE set FPSIMD get SVE for VL 7328
5616 10:53:39.748485 # ok 3889 Set Streaming SVE VL 7344
5617 10:53:39.748571 # ok 3890 # SKIP Streaming SVE set SVE get SVE for VL 7344
5618 10:53:39.748655 # ok 3891 # SKIP Streaming SVE set SVE get FPSIMD for VL 7344
5619 10:53:39.748740 # ok 3892 # SKIP Streaming SVE set FPSIMD get SVE for VL 7344
5620 10:53:39.748825 # ok 3893 Set Streaming SVE VL 7360
5621 10:53:39.748905 # ok 3894 # SKIP Streaming SVE set SVE get SVE for VL 7360
5622 10:53:39.748988 # ok 3895 # SKIP Streaming SVE set SVE get FPSIMD for VL 7360
5623 10:53:39.749070 # ok 3896 # SKIP Streaming SVE set FPSIMD get SVE for VL 7360
5624 10:53:39.749152 # ok 3897 Set Streaming SVE VL 7376
5625 10:53:39.749236 # ok 3898 # SKIP Streaming SVE set SVE get SVE for VL 7376
5626 10:53:39.749319 # ok 3899 # SKIP Streaming SVE set SVE get FPSIMD for VL 7376
5627 10:53:39.749401 # ok 3900 # SKIP Streaming SVE set FPSIMD get SVE for VL 7376
5628 10:53:39.749484 # ok 3901 Set Streaming SVE VL 7392
5629 10:53:39.749566 # ok 3902 # SKIP Streaming SVE set SVE get SVE for VL 7392
5630 10:53:39.749655 # ok 3903 # SKIP Streaming SVE set SVE get FPSIMD for VL 7392
5631 10:53:39.749738 # ok 3904 # SKIP Streaming SVE set FPSIMD get SVE for VL 7392
5632 10:53:39.749826 # ok 3905 Set Streaming SVE VL 7408
5633 10:53:39.749911 # ok 3906 # SKIP Streaming SVE set SVE get SVE for VL 7408
5634 10:53:39.752851 # ok 3907 # SKIP Streaming SVE set SVE get FPSIMD for VL 7408
5635 10:53:39.753166 # ok 3908 # SKIP Streaming SVE set FPSIMD get SVE for VL 7408
5636 10:53:39.753311 # ok 3909 Set Streaming SVE VL 7424
5637 10:53:39.753450 # ok 3910 # SKIP Streaming SVE set SVE get SVE for VL 7424
5638 10:53:39.753614 # ok 3911 # SKIP Streaming SVE set SVE get FPSIMD for VL 7424
5639 10:53:39.753782 # ok 3912 # SKIP Streaming SVE set FPSIMD get SVE for VL 7424
5640 10:53:39.753923 # ok 3913 Set Streaming SVE VL 7440
5641 10:53:39.754049 # ok 3914 # SKIP Streaming SVE set SVE get SVE for VL 7440
5642 10:53:39.754184 # ok 3915 # SKIP Streaming SVE set SVE get FPSIMD for VL 7440
5643 10:53:39.754327 # ok 3916 # SKIP Streaming SVE set FPSIMD get SVE for VL 7440
5644 10:53:39.754480 # ok 3917 Set Streaming SVE VL 7456
5645 10:53:39.754606 # ok 3918 # SKIP Streaming SVE set SVE get SVE for VL 7456
5646 10:53:39.754730 # ok 3919 # SKIP Streaming SVE set SVE get FPSIMD for VL 7456
5647 10:53:39.754838 # ok 3920 # SKIP Streaming SVE set FPSIMD get SVE for VL 7456
5648 10:53:39.754928 # ok 3921 Set Streaming SVE VL 7472
5649 10:53:39.755012 # ok 3922 # SKIP Streaming SVE set SVE get SVE for VL 7472
5650 10:53:39.755099 # ok 3923 # SKIP Streaming SVE set SVE get FPSIMD for VL 7472
5651 10:53:39.755182 # ok 3924 # SKIP Streaming SVE set FPSIMD get SVE for VL 7472
5652 10:53:39.762052 # ok 3925 Set Streaming SVE VL 7488
5653 10:53:39.762193 # ok 3926 # SKIP Streaming SVE set SVE get SVE for VL 7488
5654 10:53:39.762564 # ok 3927 # SKIP Streaming SVE set SVE get FPSIMD for VL 7488
5655 10:53:39.762733 # ok 3928 # SKIP Streaming SVE set FPSIMD get SVE for VL 7488
5656 10:53:39.762828 # ok 3929 Set Streaming SVE VL 7504
5657 10:53:39.762913 # ok 3930 # SKIP Streaming SVE set SVE get SVE for VL 7504
5658 10:53:39.762996 # ok 3931 # SKIP Streaming SVE set SVE get FPSIMD for VL 7504
5659 10:53:39.763079 # ok 3932 # SKIP Streaming SVE set FPSIMD get SVE for VL 7504
5660 10:53:39.763180 # ok 3933 Set Streaming SVE VL 7520
5661 10:53:39.763486 # ok 3934 # SKIP Streaming SVE set SVE get SVE for VL 7520
5662 10:53:39.763590 # ok 3935 # SKIP Streaming SVE set SVE get FPSIMD for VL 7520
5663 10:53:39.763678 # ok 3936 # SKIP Streaming SVE set FPSIMD get SVE for VL 7520
5664 10:53:39.763762 # ok 3937 Set Streaming SVE VL 7536
5665 10:53:39.763846 # ok 3938 # SKIP Streaming SVE set SVE get SVE for VL 7536
5666 10:53:39.763930 # ok 3939 # SKIP Streaming SVE set SVE get FPSIMD for VL 7536
5667 10:53:39.764230 # ok 3940 # SKIP Streaming SVE set FPSIMD get SVE for VL 7536
5668 10:53:39.764335 # ok 3941 Set Streaming SVE VL 7552
5669 10:53:39.764421 # ok 3942 # SKIP Streaming SVE set SVE get SVE for VL 7552
5670 10:53:39.764505 # ok 3943 # SKIP Streaming SVE set SVE get FPSIMD for VL 7552
5671 10:53:39.764588 # ok 3944 # SKIP Streaming SVE set FPSIMD get SVE for VL 7552
5672 10:53:39.769185 # ok 3945 Set Streaming SVE VL 7568
5673 10:53:39.769318 # ok 3946 # SKIP Streaming SVE set SVE get SVE for VL 7568
5674 10:53:39.769405 # ok 3947 # SKIP Streaming SVE set SVE get FPSIMD for VL 7568
5675 10:53:39.769490 # ok 3948 # SKIP Streaming SVE set FPSIMD get SVE for VL 7568
5676 10:53:39.769572 # ok 3949 Set Streaming SVE VL 7584
5677 10:53:39.769874 # ok 3950 # SKIP Streaming SVE set SVE get SVE for VL 7584
5678 10:53:39.769978 # ok 3951 # SKIP Streaming SVE set SVE get FPSIMD for VL 7584
5679 10:53:39.770062 # ok 3952 # SKIP Streaming SVE set FPSIMD get SVE for VL 7584
5680 10:53:39.770146 # ok 3953 Set Streaming SVE VL 7600
5681 10:53:39.770232 # ok 3954 # SKIP Streaming SVE set SVE get SVE for VL 7600
5682 10:53:39.770315 # ok 3955 # SKIP Streaming SVE set SVE get FPSIMD for VL 7600
5683 10:53:39.770400 # ok 3956 # SKIP Streaming SVE set FPSIMD get SVE for VL 7600
5684 10:53:39.770500 # ok 3957 Set Streaming SVE VL 7616
5685 10:53:39.770588 # ok 3958 # SKIP Streaming SVE set SVE get SVE for VL 7616
5686 10:53:39.770873 # ok 3959 # SKIP Streaming SVE set SVE get FPSIMD for VL 7616
5687 10:53:39.770976 # ok 3960 # SKIP Streaming SVE set FPSIMD get SVE for VL 7616
5688 10:53:39.771065 # ok 3961 Set Streaming SVE VL 7632
5689 10:53:39.771169 # ok 3962 # SKIP Streaming SVE set SVE get SVE for VL 7632
5690 10:53:39.771257 # ok 3963 # SKIP Streaming SVE set SVE get FPSIMD for VL 7632
5691 10:53:39.771345 # ok 3964 # SKIP Streaming SVE set FPSIMD get SVE for VL 7632
5692 10:53:39.771432 # ok 3965 Set Streaming SVE VL 7648
5693 10:53:39.771516 # ok 3966 # SKIP Streaming SVE set SVE get SVE for VL 7648
5694 10:53:39.771811 # ok 3967 # SKIP Streaming SVE set SVE get FPSIMD for VL 7648
5695 10:53:39.771918 # ok 3968 # SKIP Streaming SVE set FPSIMD get SVE for VL 7648
5696 10:53:39.772006 # ok 3969 Set Streaming SVE VL 7664
5697 10:53:39.772090 # ok 3970 # SKIP Streaming SVE set SVE get SVE for VL 7664
5698 10:53:39.772174 # ok 3971 # SKIP Streaming SVE set SVE get FPSIMD for VL 7664
5699 10:53:39.772260 # ok 3972 # SKIP Streaming SVE set FPSIMD get SVE for VL 7664
5700 10:53:39.772345 # ok 3973 Set Streaming SVE VL 7680
5701 10:53:39.772428 # ok 3974 # SKIP Streaming SVE set SVE get SVE for VL 7680
5702 10:53:39.772529 # ok 3975 # SKIP Streaming SVE set SVE get FPSIMD for VL 7680
5703 10:53:39.772616 # ok 3976 # SKIP Streaming SVE set FPSIMD get SVE for VL 7680
5704 10:53:39.772705 # ok 3977 Set Streaming SVE VL 7696
5705 10:53:39.772789 # ok 3978 # SKIP Streaming SVE set SVE get SVE for VL 7696
5706 10:53:39.776342 # ok 3979 # SKIP Streaming SVE set SVE get FPSIMD for VL 7696
5707 10:53:39.776759 # ok 3980 # SKIP Streaming SVE set FPSIMD get SVE for VL 7696
5708 10:53:39.776892 # ok 3981 Set Streaming SVE VL 7712
5709 10:53:39.776980 # ok 3982 # SKIP Streaming SVE set SVE get SVE for VL 7712
5710 10:53:39.777067 # ok 3983 # SKIP Streaming SVE set SVE get FPSIMD for VL 7712
5711 10:53:39.777170 # ok 3984 # SKIP Streaming SVE set FPSIMD get SVE for VL 7712
5712 10:53:39.777258 # ok 3985 Set Streaming SVE VL 7728
5713 10:53:39.777343 # ok 3986 # SKIP Streaming SVE set SVE get SVE for VL 7728
5714 10:53:39.777429 # ok 3987 # SKIP Streaming SVE set SVE get FPSIMD for VL 7728
5715 10:53:39.777530 # ok 3988 # SKIP Streaming SVE set FPSIMD get SVE for VL 7728
5716 10:53:39.777620 # ok 3989 Set Streaming SVE VL 7744
5717 10:53:39.777727 # ok 3990 # SKIP Streaming SVE set SVE get SVE for VL 7744
5718 10:53:39.777822 # ok 3991 # SKIP Streaming SVE set SVE get FPSIMD for VL 7744
5719 10:53:39.777924 # ok 3992 # SKIP Streaming SVE set FPSIMD get SVE for VL 7744
5720 10:53:39.778013 # ok 3993 Set Streaming SVE VL 7760
5721 10:53:39.778113 # ok 3994 # SKIP Streaming SVE set SVE get SVE for VL 7760
5722 10:53:39.778215 # ok 3995 # SKIP Streaming SVE set SVE get FPSIMD for VL 7760
5723 10:53:39.778316 # ok 3996 # SKIP Streaming SVE set FPSIMD get SVE for VL 7760
5724 10:53:39.778416 # ok 3997 Set Streaming SVE VL 7776
5725 10:53:39.778722 # ok 3998 # SKIP Streaming SVE set SVE get SVE for VL 7776
5726 10:53:39.778843 # ok 3999 # SKIP Streaming SVE set SVE get FPSIMD for VL 7776
5727 10:53:39.779437 # ok 4000 # SKIP Streaming SVE set FPSIMD get SVE for VL 7776
5728 10:53:39.779581 # ok 4001 Set Streaming SVE VL 7792
5729 10:53:39.779726 # ok 4002 # SKIP Streaming SVE set SVE get SVE for VL 7792
5730 10:53:39.780065 # ok 4003 # SKIP Streaming SVE set SVE get FPSIMD for VL 7792
5731 10:53:39.780171 # ok 4004 # SKIP Streaming SVE set FPSIMD get SVE for VL 7792
5732 10:53:39.780260 # ok 4005 Set Streaming SVE VL 7808
5733 10:53:39.780345 # ok 4006 # SKIP Streaming SVE set SVE get SVE for VL 7808
5734 10:53:39.780430 # ok 4007 # SKIP Streaming SVE set SVE get FPSIMD for VL 7808
5735 10:53:39.780516 # ok 4008 # SKIP Streaming SVE set FPSIMD get SVE for VL 7808
5736 10:53:39.780615 # ok 4009 Set Streaming SVE VL 7824
5737 10:53:39.780704 # ok 4010 # SKIP Streaming SVE set SVE get SVE for VL 7824
5738 10:53:39.788855 # ok 4011 # SKIP Streaming SVE set SVE get FPSIMD for VL 7824
5739 10:53:39.789429 # ok 4012 # SKIP Streaming SVE set FPSIMD get SVE for VL 7824
5740 10:53:39.789637 # ok 4013 Set Streaming SVE VL 7840
5741 10:53:39.789867 # ok 4014 # SKIP Streaming SVE set SVE get SVE for VL 7840
5742 10:53:39.790086 # ok 4015 # SKIP Streaming SVE set SVE get FPSIMD for VL 7840
5743 10:53:39.790291 # ok 4016 # SKIP Streaming SVE set FPSIMD get SVE for VL 7840
5744 10:53:39.790437 # ok 4017 Set Streaming SVE VL 7856
5745 10:53:39.790565 # ok 4018 # SKIP Streaming SVE set SVE get SVE for VL 7856
5746 10:53:39.790691 # ok 4019 # SKIP Streaming SVE set SVE get FPSIMD for VL 7856
5747 10:53:39.790817 # ok 4020 # SKIP Streaming SVE set FPSIMD get SVE for VL 7856
5748 10:53:39.790940 # ok 4021 Set Streaming SVE VL 7872
5749 10:53:39.791064 # ok 4022 # SKIP Streaming SVE set SVE get SVE for VL 7872
5750 10:53:39.791216 # ok 4023 # SKIP Streaming SVE set SVE get FPSIMD for VL 7872
5751 10:53:39.791345 # ok 4024 # SKIP Streaming SVE set FPSIMD get SVE for VL 7872
5752 10:53:39.791469 # ok 4025 Set Streaming SVE VL 7888
5753 10:53:39.791592 # ok 4026 # SKIP Streaming SVE set SVE get SVE for VL 7888
5754 10:53:39.791715 # ok 4027 # SKIP Streaming SVE set SVE get FPSIMD for VL 7888
5755 10:53:39.791837 # ok 4028 # SKIP Streaming SVE set FPSIMD get SVE for VL 7888
5756 10:53:39.791990 # ok 4029 Set Streaming SVE VL 7904
5757 10:53:39.792121 # ok 4030 # SKIP Streaming SVE set SVE get SVE for VL 7904
5758 10:53:39.792248 # ok 4031 # SKIP Streaming SVE set SVE get FPSIMD for VL 7904
5759 10:53:39.792367 # ok 4032 # SKIP Streaming SVE set FPSIMD get SVE for VL 7904
5760 10:53:39.792483 # ok 4033 Set Streaming SVE VL 7920
5761 10:53:39.792599 # ok 4034 # SKIP Streaming SVE set SVE get SVE for VL 7920
5762 10:53:39.792745 # ok 4035 # SKIP Streaming SVE set SVE get FPSIMD for VL 7920
5763 10:53:39.792902 # ok 4036 # SKIP Streaming SVE set FPSIMD get SVE for VL 7920
5764 10:53:39.793031 # ok 4037 Set Streaming SVE VL 7936
5765 10:53:39.793156 # ok 4038 # SKIP Streaming SVE set SVE get SVE for VL 7936
5766 10:53:39.793544 # ok 4039 # SKIP Streaming SVE set SVE get FPSIMD for VL 7936
5767 10:53:39.793750 # ok 4040 # SKIP Streaming SVE set FPSIMD get SVE for VL 7936
5768 10:53:39.793929 # ok 4041 Set Streaming SVE VL 7952
5769 10:53:39.794153 # ok 4042 # SKIP Streaming SVE set SVE get SVE for VL 7952
5770 10:53:39.794361 # ok 4043 # SKIP Streaming SVE set SVE get FPSIMD for VL 7952
5771 10:53:39.794624 # ok 4044 # SKIP Streaming SVE set FPSIMD get SVE for VL 7952
5772 10:53:39.794842 # ok 4045 Set Streaming SVE VL 7968
5773 10:53:39.795027 # ok 4046 # SKIP Streaming SVE set SVE get SVE for VL 7968
5774 10:53:39.795233 # ok 4047 # SKIP Streaming SVE set SVE get FPSIMD for VL 7968
5775 10:53:39.795415 # ok 4048 # SKIP Streaming SVE set FPSIMD get SVE for VL 7968
5776 10:53:39.795586 # ok 4049 Set Streaming SVE VL 7984
5777 10:53:39.795786 # ok 4050 # SKIP Streaming SVE set SVE get SVE for VL 7984
5778 10:53:39.796017 # ok 4051 # SKIP Streaming SVE set SVE get FPSIMD for VL 7984
5779 10:53:39.796237 # ok 4052 # SKIP Streaming SVE set FPSIMD get SVE for VL 7984
5780 10:53:39.796410 # ok 4053 Set Streaming SVE VL 8000
5781 10:53:39.796539 # ok 4054 # SKIP Streaming SVE set SVE get SVE for VL 8000
5782 10:53:39.796666 # ok 4055 # SKIP Streaming SVE set SVE get FPSIMD for VL 8000
5783 10:53:39.796813 # ok 4056 # SKIP Streaming SVE set FPSIMD get SVE for VL 8000
5784 10:53:39.796935 # ok 4057 Set Streaming SVE VL 8016
5785 10:53:39.797051 # ok 4058 # SKIP Streaming SVE set SVE get SVE for VL 8016
5786 10:53:39.797167 # ok 4059 # SKIP Streaming SVE set SVE get FPSIMD for VL 8016
5787 10:53:39.797282 # ok 4060 # SKIP Streaming SVE set FPSIMD get SVE for VL 8016
5788 10:53:39.797397 # ok 4061 Set Streaming SVE VL 8032
5789 10:53:39.797511 # ok 4062 # SKIP Streaming SVE set SVE get SVE for VL 8032
5790 10:53:39.797635 # ok 4063 # SKIP Streaming SVE set SVE get FPSIMD for VL 8032
5791 10:53:39.800419 # ok 4064 # SKIP Streaming SVE set FPSIMD get SVE for VL 8032
5792 10:53:39.800928 # ok 4065 Set Streaming SVE VL 8048
5793 10:53:39.801118 # ok 4066 # SKIP Streaming SVE set SVE get SVE for VL 8048
5794 10:53:39.801326 # ok 4067 # SKIP Streaming SVE set SVE get FPSIMD for VL 8048
5795 10:53:39.801591 # ok 4068 # SKIP Streaming SVE set FPSIMD get SVE for VL 8048
5796 10:53:39.801775 # ok 4069 Set Streaming SVE VL 8064
5797 10:53:39.801900 # ok 4070 # SKIP Streaming SVE set SVE get SVE for VL 8064
5798 10:53:39.802016 # ok 4071 # SKIP Streaming SVE set SVE get FPSIMD for VL 8064
5799 10:53:39.802131 # ok 4072 # SKIP Streaming SVE set FPSIMD get SVE for VL 8064
5800 10:53:39.802246 # ok 4073 Set Streaming SVE VL 8080
5801 10:53:39.802390 # ok 4074 # SKIP Streaming SVE set SVE get SVE for VL 8080
5802 10:53:39.802758 # ok 4075 # SKIP Streaming SVE set SVE get FPSIMD for VL 8080
5803 10:53:39.802965 # ok 4076 # SKIP Streaming SVE set FPSIMD get SVE for VL 8080
5804 10:53:39.803167 # ok 4077 Set Streaming SVE VL 8096
5805 10:53:39.803589 # ok 4078 # SKIP Streaming SVE set SVE get SVE for VL 8096
5806 10:53:39.803794 # ok 4079 # SKIP Streaming SVE set SVE get FPSIMD for VL 8096
5807 10:53:39.803966 # ok 4080 # SKIP Streaming SVE set FPSIMD get SVE for VL 8096
5808 10:53:39.804137 # ok 4081 Set Streaming SVE VL 8112
5809 10:53:39.804340 # ok 4082 # SKIP Streaming SVE set SVE get SVE for VL 8112
5810 10:53:39.804473 # ok 4083 # SKIP Streaming SVE set SVE get FPSIMD for VL 8112
5811 10:53:39.804589 # ok 4084 # SKIP Streaming SVE set FPSIMD get SVE for VL 8112
5812 10:53:39.804732 # ok 4085 Set Streaming SVE VL 8128
5813 10:53:39.804855 # ok 4086 # SKIP Streaming SVE set SVE get SVE for VL 8128
5814 10:53:39.804971 # ok 4087 # SKIP Streaming SVE set SVE get FPSIMD for VL 8128
5815 10:53:39.805087 # ok 4088 # SKIP Streaming SVE set FPSIMD get SVE for VL 8128
5816 10:53:39.805202 # ok 4089 Set Streaming SVE VL 8144
5817 10:53:39.808845 # ok 4090 # SKIP Streaming SVE set SVE get SVE for VL 8144
5818 10:53:39.809170 # ok 4091 # SKIP Streaming SVE set SVE get FPSIMD for VL 8144
5819 10:53:39.809279 # ok 4092 # SKIP Streaming SVE set FPSIMD get SVE for VL 8144
5820 10:53:39.809370 # ok 4093 Set Streaming SVE VL 8160
5821 10:53:39.809472 # ok 4094 # SKIP Streaming SVE set SVE get SVE for VL 8160
5822 10:53:39.809585 # ok 4095 # SKIP Streaming SVE set SVE get FPSIMD for VL 8160
5823 10:53:39.809684 # ok 4096 # SKIP Streaming SVE set FPSIMD get SVE for VL 8160
5824 10:53:39.809790 # ok 4097 Set Streaming SVE VL 8176
5825 10:53:39.809887 # ok 4098 # SKIP Streaming SVE set SVE get SVE for VL 8176
5826 10:53:39.810010 # ok 4099 # SKIP Streaming SVE set SVE get FPSIMD for VL 8176
5827 10:53:39.810306 # ok 4100 # SKIP Streaming SVE set FPSIMD get SVE for VL 8176
5828 10:53:39.810404 # ok 4101 Set Streaming SVE VL 8192
5829 10:53:39.810505 # ok 4102 # SKIP Streaming SVE set SVE get SVE for VL 8192
5830 10:53:39.810616 # ok 4103 # SKIP Streaming SVE set SVE get FPSIMD for VL 8192
5831 10:53:39.810719 # ok 4104 # SKIP Streaming SVE set FPSIMD get SVE for VL 8192
5832 10:53:39.810980 # # Totals: pass:1095 fail:0 xfail:0 xpass:0 skip:3009 error:0
5833 10:53:39.811129 ok 30 selftests: arm64: sve-ptrace
5834 10:53:39.811266 # selftests: arm64: sve-probe-vls
5835 10:53:39.811379 # TAP version 13
5836 10:53:39.811469 # 1..2
5837 10:53:39.811554 # ok 1 Enumerated 16 vector lengths
5838 10:53:39.811655 # ok 2 All vector lengths valid
5839 10:53:39.811741 # # 16
5840 10:53:39.811825 # # 32
5841 10:53:39.811911 # # 48
5842 10:53:39.811996 # # 64
5843 10:53:39.812079 # # 80
5844 10:53:39.812163 # # 96
5845 10:53:39.812247 # # 112
5846 10:53:39.812330 # # 128
5847 10:53:39.812412 # # 144
5848 10:53:39.812495 # # 160
5849 10:53:39.812578 # # 176
5850 10:53:39.812662 # # 192
5851 10:53:39.812745 # # 208
5852 10:53:39.812850 # # 224
5853 10:53:39.812935 # # 240
5854 10:53:39.813019 # # 256
5855 10:53:39.813101 # # Totals: pass:2 fail:0 xfail:0 xpass:0 skip:0 error:0
5856 10:53:39.813184 ok 31 selftests: arm64: sve-probe-vls
5857 10:53:39.915141 # selftests: arm64: vec-syscfg
5858 10:53:40.610570 # TAP version 13
5859 10:53:40.610994 # 1..20
5860 10:53:40.611099 # ok 1 SVE default vector length 64
5861 10:53:40.611183 # ok 2 SVE minimum vector length 16
5862 10:53:40.611261 # ok 3 SVE maximum vector length 256
5863 10:53:40.611336 # ok 4 SVE current VL is 64
5864 10:53:40.611415 # ok 5 SVE set VL 64 and have VL 64
5865 10:53:40.611509 # ok 6 SVE prctl() set min/max
5866 10:53:40.611588 # ok 7 SVE vector length used default
5867 10:53:40.611664 # ok 8 SVE vector length was inherited
5868 10:53:40.611739 # ok 9 SVE vector length set on exec
5869 10:53:40.611815 # ok 10 SVE prctl() set all VLs, 0 errors
5870 10:53:40.611891 # ok 11 SME default vector length 32
5871 10:53:40.611982 # ok 12 SME minimum vector length 16
5872 10:53:40.612060 # ok 13 SME maximum vector length 256
5873 10:53:40.612136 # ok 14 SME current VL is 32
5874 10:53:40.612211 # ok 15 SME set VL 32 and have VL 32
5875 10:53:40.612287 # ok 16 SME prctl() set min/max
5876 10:53:40.612363 # ok 17 SME vector length used default
5877 10:53:40.612438 # ok 18 SME vector length was inherited
5878 10:53:40.612530 # ok 19 SME vector length set on exec
5879 10:53:40.612608 # ok 20 SME prctl() set all VLs, 0 errors
5880 10:53:40.612683 # # Totals: pass:20 fail:0 xfail:0 xpass:0 skip:0 error:0
5881 10:53:40.630551 ok 32 selftests: arm64: vec-syscfg
5882 10:53:40.722928 # selftests: arm64: za-fork
5883 10:53:40.880245 # TAP version 13
5884 10:53:40.880670 # 1..1
5885 10:53:40.880773 # # PID: 1015
5886 10:53:40.880857 # ok 1 fork_test
5887 10:53:40.880939 # # Totals: pass:1 fail:0 xfail:0 xpass:0 skip:0 error:0
5888 10:53:40.904240 ok 33 selftests: arm64: za-fork
5889 10:53:41.015519 # selftests: arm64: za-ptrace
5890 10:53:41.151042 # TAP version 13
5891 10:53:41.151279 # 1..1536
5892 10:53:41.151564 # # Parent is 1033, child is 1034
5893 10:53:41.151677 # ok 1 Set VL 16
5894 10:53:41.151770 # ok 2 Disabled ZA for VL 16
5895 10:53:41.151855 # ok 3 Data match for VL 16
5896 10:53:41.151941 # ok 4 Set VL 32
5897 10:53:41.152025 # ok 5 Disabled ZA for VL 32
5898 10:53:41.152107 # ok 6 Data match for VL 32
5899 10:53:41.152191 # ok 7 Set VL 48
5900 10:53:41.152274 # ok 8 # SKIP Disabled ZA for VL 48
5901 10:53:41.152375 # ok 9 # SKIP Get and set data for VL 48
5902 10:53:41.152461 # ok 10 Set VL 64
5903 10:53:41.152546 # ok 11 Disabled ZA for VL 64
5904 10:53:41.152628 # ok 12 Data match for VL 64
5905 10:53:41.152700 # ok 13 Set VL 80
5906 10:53:41.152778 # ok 14 # SKIP Disabled ZA for VL 80
5907 10:53:41.152854 # ok 15 # SKIP Get and set data for VL 80
5908 10:53:41.152928 # ok 16 Set VL 96
5909 10:53:41.153018 # ok 17 # SKIP Disabled ZA for VL 96
5910 10:53:41.153096 # ok 18 # SKIP Get and set data for VL 96
5911 10:53:41.153171 # ok 19 Set VL 112
5912 10:53:41.154147 # ok 20 # SKIP Disabled ZA for VL 112
5913 10:53:41.154583 # ok 21 # SKIP Get and set data for VL 112
5914 10:53:41.154784 # ok 22 Set VL 128
5915 10:53:41.154950 # ok 23 Disabled ZA for VL 128
5916 10:53:41.155108 # ok 24 Data match for VL 128
5917 10:53:41.155262 # ok 25 Set VL 144
5918 10:53:41.155416 # ok 26 # SKIP Disabled ZA for VL 144
5919 10:53:41.155568 # ok 27 # SKIP Get and set data for VL 144
5920 10:53:41.155757 # ok 28 Set VL 160
5921 10:53:41.155915 # ok 29 # SKIP Disabled ZA for VL 160
5922 10:53:41.156068 # ok 30 # SKIP Get and set data for VL 160
5923 10:53:41.156218 # ok 31 Set VL 176
5924 10:53:41.156378 # ok 32 # SKIP Disabled ZA for VL 176
5925 10:53:41.156536 # ok 33 # SKIP Get and set data for VL 176
5926 10:53:41.156698 # ok 34 Set VL 192
5927 10:53:41.156853 # ok 35 # SKIP Disabled ZA for VL 192
5928 10:53:41.157009 # ok 36 # SKIP Get and set data for VL 192
5929 10:53:41.157167 # ok 37 Set VL 208
5930 10:53:41.157331 # ok 38 # SKIP Disabled ZA for VL 208
5931 10:53:41.157484 # ok 39 # SKIP Get and set data for VL 208
5932 10:53:41.157721 # ok 40 Set VL 224
5933 10:53:41.157963 # ok 41 # SKIP Disabled ZA for VL 224
5934 10:53:41.158160 # ok 42 # SKIP Get and set data for VL 224
5935 10:53:41.158342 # ok 43 Set VL 240
5936 10:53:41.158515 # ok 44 # SKIP Disabled ZA for VL 240
5937 10:53:41.158681 # ok 45 # SKIP Get and set data for VL 240
5938 10:53:41.158867 # ok 46 Set VL 256
5939 10:53:41.159032 # ok 47 Disabled ZA for VL 256
5940 10:53:41.159172 # ok 48 Data match for VL 256
5941 10:53:41.159298 # ok 49 Set VL 272
5942 10:53:41.159420 # ok 50 # SKIP Disabled ZA for VL 272
5943 10:53:41.159556 # ok 51 # SKIP Get and set data for VL 272
5944 10:53:41.159728 # ok 52 Set VL 288
5945 10:53:41.159866 # ok 53 # SKIP Disabled ZA for VL 288
5946 10:53:41.159994 # ok 54 # SKIP Get and set data for VL 288
5947 10:53:41.160119 # ok 55 Set VL 304
5948 10:53:41.160244 # ok 56 # SKIP Disabled ZA for VL 304
5949 10:53:41.160368 # ok 57 # SKIP Get and set data for VL 304
5950 10:53:41.160491 # ok 58 Set VL 320
5951 10:53:41.160615 # ok 59 # SKIP Disabled ZA for VL 320
5952 10:53:41.160737 # ok 60 # SKIP Get and set data for VL 320
5953 10:53:41.160874 # ok 61 Set VL 336
5954 10:53:41.161022 # ok 62 # SKIP Disabled ZA for VL 336
5955 10:53:41.161142 # ok 63 # SKIP Get and set data for VL 336
5956 10:53:41.161302 # ok 64 Set VL 352
5957 10:53:41.161434 # ok 65 # SKIP Disabled ZA for VL 352
5958 10:53:41.161554 # ok 66 # SKIP Get and set data for VL 352
5959 10:53:41.161706 # ok 67 Set VL 368
5960 10:53:41.161911 # ok 68 # SKIP Disabled ZA for VL 368
5961 10:53:41.162100 # ok 69 # SKIP Get and set data for VL 368
5962 10:53:41.162286 # ok 70 Set VL 384
5963 10:53:41.162468 # ok 71 # SKIP Disabled ZA for VL 384
5964 10:53:41.162654 # ok 72 # SKIP Get and set data for VL 384
5965 10:53:41.162818 # ok 73 Set VL 400
5966 10:53:41.162963 # ok 74 # SKIP Disabled ZA for VL 400
5967 10:53:41.163107 # ok 75 # SKIP Get and set data for VL 400
5968 10:53:41.163251 # ok 76 Set VL 416
5969 10:53:41.163393 # ok 77 # SKIP Disabled ZA for VL 416
5970 10:53:41.163567 # ok 78 # SKIP Get and set data for VL 416
5971 10:53:41.163743 # ok 79 Set VL 432
5972 10:53:41.164135 # ok 80 # SKIP Disabled ZA for VL 432
5973 10:53:41.164277 # ok 81 # SKIP Get and set data for VL 432
5974 10:53:41.164427 # ok 82 Set VL 448
5975 10:53:41.164570 # ok 83 # SKIP Disabled ZA for VL 448
5976 10:53:41.164714 # ok 84 # SKIP Get and set data for VL 448
5977 10:53:41.164869 # ok 85 Set VL 464
5978 10:53:41.165025 # ok 86 # SKIP Disabled ZA for VL 464
5979 10:53:41.165149 # ok 87 # SKIP Get and set data for VL 464
5980 10:53:41.165318 # ok 88 Set VL 480
5981 10:53:41.165452 # ok 89 # SKIP Disabled ZA for VL 480
5982 10:53:41.165572 # ok 90 # SKIP Get and set data for VL 480
5983 10:53:41.165710 # ok 91 Set VL 496
5984 10:53:41.165830 # ok 92 # SKIP Disabled ZA for VL 496
5985 10:53:41.165947 # ok 93 # SKIP Get and set data for VL 496
5986 10:53:41.166067 # ok 94 Set VL 512
5987 10:53:41.166185 # ok 95 # SKIP Disabled ZA for VL 512
5988 10:53:41.166302 # ok 96 # SKIP Get and set data for VL 512
5989 10:53:41.166421 # ok 97 Set VL 528
5990 10:53:41.166537 # ok 98 # SKIP Disabled ZA for VL 528
5991 10:53:41.166655 # ok 99 # SKIP Get and set data for VL 528
5992 10:53:41.166773 # ok 100 Set VL 544
5993 10:53:41.166890 # ok 101 # SKIP Disabled ZA for VL 544
5994 10:53:41.167007 # ok 102 # SKIP Get and set data for VL 544
5995 10:53:41.167127 # ok 103 Set VL 560
5996 10:53:41.167243 # ok 104 # SKIP Disabled ZA for VL 560
5997 10:53:41.167360 # ok 105 # SKIP Get and set data for VL 560
5998 10:53:41.167481 # ok 106 Set VL 576
5999 10:53:41.167600 # ok 107 # SKIP Disabled ZA for VL 576
6000 10:53:41.167718 # ok 108 # SKIP Get and set data for VL 576
6001 10:53:41.167836 # ok 109 Set VL 592
6002 10:53:41.167955 # ok 110 # SKIP Disabled ZA for VL 592
6003 10:53:41.168072 # ok 111 # SKIP Get and set data for VL 592
6004 10:53:41.168189 # ok 112 Set VL 608
6005 10:53:41.168307 # ok 113 # SKIP Disabled ZA for VL 608
6006 10:53:41.171589 # ok 114 # SKIP Get and set data for VL 608
6007 10:53:41.171765 # ok 115 Set VL 624
6008 10:53:41.172161 # ok 116 # SKIP Disabled ZA for VL 624
6009 10:53:41.172312 # ok 117 # SKIP Get and set data for VL 624
6010 10:53:41.172438 # ok 118 Set VL 640
6011 10:53:41.172559 # ok 119 # SKIP Disabled ZA for VL 640
6012 10:53:41.172678 # ok 120 # SKIP Get and set data for VL 640
6013 10:53:41.172796 # ok 121 Set VL 656
6014 10:53:41.172915 # ok 122 # SKIP Disabled ZA for VL 656
6015 10:53:41.173146 # ok 123 # SKIP Get and set data for VL 656
6016 10:53:41.173331 # ok 124 Set VL 672
6017 10:53:41.186657 # ok 125 # SKIP Disabled ZA for VL 672
6018 10:53:41.187191 # ok 126 # SKIP Get and set data for VL 672
6019 10:53:41.187402 # ok 127 Set VL 688
6020 10:53:41.187580 # ok 128 # SKIP Disabled ZA for VL 688
6021 10:53:41.187746 # ok 129 # SKIP Get and set data for VL 688
6022 10:53:41.187916 # ok 130 Set VL 704
6023 10:53:41.188082 # ok 131 # SKIP Disabled ZA for VL 704
6024 10:53:41.188289 # ok 132 # SKIP Get and set data for VL 704
6025 10:53:41.188505 # ok 133 Set VL 720
6026 10:53:41.188769 # ok 134 # SKIP Disabled ZA for VL 720
6027 10:53:41.188933 # ok 135 # SKIP Get and set data for VL 720
6028 10:53:41.189065 # ok 136 Set VL 736
6029 10:53:41.189214 # ok 137 # SKIP Disabled ZA for VL 736
6030 10:53:41.189431 # ok 138 # SKIP Get and set data for VL 736
6031 10:53:41.189682 # ok 139 Set VL 752
6032 10:53:41.189899 # ok 140 # SKIP Disabled ZA for VL 752
6033 10:53:41.190118 # ok 141 # SKIP Get and set data for VL 752
6034 10:53:41.190334 # ok 142 Set VL 768
6035 10:53:41.190550 # ok 143 # SKIP Disabled ZA for VL 768
6036 10:53:41.190770 # ok 144 # SKIP Get and set data for VL 768
6037 10:53:41.190981 # ok 145 Set VL 784
6038 10:53:41.191196 # ok 146 # SKIP Disabled ZA for VL 784
6039 10:53:41.191395 # ok 147 # SKIP Get and set data for VL 784
6040 10:53:41.191604 # ok 148 Set VL 800
6041 10:53:41.191818 # ok 149 # SKIP Disabled ZA for VL 800
6042 10:53:41.192079 # ok 150 # SKIP Get and set data for VL 800
6043 10:53:41.192295 # ok 151 Set VL 816
6044 10:53:41.192499 # ok 152 # SKIP Disabled ZA for VL 816
6045 10:53:41.192727 # ok 153 # SKIP Get and set data for VL 816
6046 10:53:41.192916 # ok 154 Set VL 832
6047 10:53:41.193053 # ok 155 # SKIP Disabled ZA for VL 832
6048 10:53:41.193173 # ok 156 # SKIP Get and set data for VL 832
6049 10:53:41.193341 # ok 157 Set VL 848
6050 10:53:41.193475 # ok 158 # SKIP Disabled ZA for VL 848
6051 10:53:41.193594 # ok 159 # SKIP Get and set data for VL 848
6052 10:53:41.193808 # ok 160 Set VL 864
6053 10:53:41.194006 # ok 161 # SKIP Disabled ZA for VL 864
6054 10:53:41.194191 # ok 162 # SKIP Get and set data for VL 864
6055 10:53:41.194375 # ok 163 Set VL 880
6056 10:53:41.194560 # ok 164 # SKIP Disabled ZA for VL 880
6057 10:53:41.194743 # ok 165 # SKIP Get and set data for VL 880
6058 10:53:41.194932 # ok 166 Set VL 896
6059 10:53:41.195076 # ok 167 # SKIP Disabled ZA for VL 896
6060 10:53:41.195220 # ok 168 # SKIP Get and set data for VL 896
6061 10:53:41.195364 # ok 169 Set VL 912
6062 10:53:41.195508 # ok 170 # SKIP Disabled ZA for VL 912
6063 10:53:41.195651 # ok 171 # SKIP Get and set data for VL 912
6064 10:53:41.195794 # ok 172 Set VL 928
6065 10:53:41.195938 # ok 173 # SKIP Disabled ZA for VL 928
6066 10:53:41.196081 # ok 174 # SKIP Get and set data for VL 928
6067 10:53:41.196223 # ok 175 Set VL 944
6068 10:53:41.196364 # ok 176 # SKIP Disabled ZA for VL 944
6069 10:53:41.196510 # ok 177 # SKIP Get and set data for VL 944
6070 10:53:41.196654 # ok 178 Set VL 960
6071 10:53:41.196846 # ok 179 # SKIP Disabled ZA for VL 960
6072 10:53:41.196984 # ok 180 # SKIP Get and set data for VL 960
6073 10:53:41.197373 # ok 181 Set VL 976
6074 10:53:41.197534 # ok 182 # SKIP Disabled ZA for VL 976
6075 10:53:41.197673 # ok 183 # SKIP Get and set data for VL 976
6076 10:53:41.197796 # ok 184 Set VL 992
6077 10:53:41.200125 # ok 185 # SKIP Disabled ZA for VL 992
6078 10:53:41.200364 # ok 186 # SKIP Get and set data for VL 992
6079 10:53:41.200819 # ok 187 Set VL 1008
6080 10:53:41.200979 # ok 188 # SKIP Disabled ZA for VL 1008
6081 10:53:41.201123 # ok 189 # SKIP Get and set data for VL 1008
6082 10:53:41.201328 # ok 190 Set VL 1024
6083 10:53:41.201550 # ok 191 # SKIP Disabled ZA for VL 1024
6084 10:53:41.201789 # ok 192 # SKIP Get and set data for VL 1024
6085 10:53:41.202071 # ok 193 Set VL 1040
6086 10:53:41.202270 # ok 194 # SKIP Disabled ZA for VL 1040
6087 10:53:41.202479 # ok 195 # SKIP Get and set data for VL 1040
6088 10:53:41.202713 # ok 196 Set VL 1056
6089 10:53:41.202927 # ok 197 # SKIP Disabled ZA for VL 1056
6090 10:53:41.203138 # ok 198 # SKIP Get and set data for VL 1056
6091 10:53:41.203349 # ok 199 Set VL 1072
6092 10:53:41.203565 # ok 200 # SKIP Disabled ZA for VL 1072
6093 10:53:41.203779 # ok 201 # SKIP Get and set data for VL 1072
6094 10:53:41.204043 # ok 202 Set VL 1088
6095 10:53:41.204247 # ok 203 # SKIP Disabled ZA for VL 1088
6096 10:53:41.204439 # ok 204 # SKIP Get and set data for VL 1088
6097 10:53:41.204615 # ok 205 Set VL 1104
6098 10:53:41.204822 # ok 206 # SKIP Disabled ZA for VL 1104
6099 10:53:41.204980 # ok 207 # SKIP Get and set data for VL 1104
6100 10:53:41.205103 # ok 208 Set VL 1120
6101 10:53:41.205243 # ok 209 # SKIP Disabled ZA for VL 1120
6102 10:53:41.205392 # ok 210 # SKIP Get and set data for VL 1120
6103 10:53:41.205512 # ok 211 Set VL 1136
6104 10:53:41.205629 # ok 212 # SKIP Disabled ZA for VL 1136
6105 10:53:41.205863 # ok 213 # SKIP Get and set data for VL 1136
6106 10:53:41.206059 # ok 214 Set VL 1152
6107 10:53:41.206229 # ok 215 # SKIP Disabled ZA for VL 1152
6108 10:53:41.206373 # ok 216 # SKIP Get and set data for VL 1152
6109 10:53:41.206517 # ok 217 Set VL 1168
6110 10:53:41.206660 # ok 218 # SKIP Disabled ZA for VL 1168
6111 10:53:41.206802 # ok 219 # SKIP Get and set data for VL 1168
6112 10:53:41.206990 # ok 220 Set VL 1184
6113 10:53:41.207128 # ok 221 # SKIP Disabled ZA for VL 1184
6114 10:53:41.207270 # ok 222 # SKIP Get and set data for VL 1184
6115 10:53:41.207413 # ok 223 Set VL 1200
6116 10:53:41.207555 # ok 224 # SKIP Disabled ZA for VL 1200
6117 10:53:41.207697 # ok 225 # SKIP Get and set data for VL 1200
6118 10:53:41.207838 # ok 226 Set VL 1216
6119 10:53:41.207982 # ok 227 # SKIP Disabled ZA for VL 1216
6120 10:53:41.208123 # ok 228 # SKIP Get and set data for VL 1216
6121 10:53:41.208264 # ok 229 Set VL 1232
6122 10:53:41.208406 # ok 230 # SKIP Disabled ZA for VL 1232
6123 10:53:41.208551 # ok 231 # SKIP Get and set data for VL 1232
6124 10:53:41.208694 # ok 232 Set VL 1248
6125 10:53:41.211244 # ok 233 # SKIP Disabled ZA for VL 1248
6126 10:53:41.211716 # ok 234 # SKIP Get and set data for VL 1248
6127 10:53:41.211886 # ok 235 Set VL 1264
6128 10:53:41.212089 # ok 236 # SKIP Disabled ZA for VL 1264
6129 10:53:41.212261 # ok 237 # SKIP Get and set data for VL 1264
6130 10:53:41.212421 # ok 238 Set VL 1280
6131 10:53:41.212617 # ok 239 # SKIP Disabled ZA for VL 1280
6132 10:53:41.212749 # ok 240 # SKIP Get and set data for VL 1280
6133 10:53:41.212871 # ok 241 Set VL 1296
6134 10:53:41.212990 # ok 242 # SKIP Disabled ZA for VL 1296
6135 10:53:41.213124 # ok 243 # SKIP Get and set data for VL 1296
6136 10:53:41.213316 # ok 244 Set VL 1312
6137 10:53:41.213463 # ok 245 # SKIP Disabled ZA for VL 1312
6138 10:53:41.213645 # ok 246 # SKIP Get and set data for VL 1312
6139 10:53:41.213796 # ok 247 Set VL 1328
6140 10:53:41.213943 # ok 248 # SKIP Disabled ZA for VL 1328
6141 10:53:41.214087 # ok 249 # SKIP Get and set data for VL 1328
6142 10:53:41.214231 # ok 250 Set VL 1344
6143 10:53:41.214411 # ok 251 # SKIP Disabled ZA for VL 1344
6144 10:53:41.214548 # ok 252 # SKIP Get and set data for VL 1344
6145 10:53:41.214692 # ok 253 Set VL 1360
6146 10:53:41.214835 # ok 254 # SKIP Disabled ZA for VL 1360
6147 10:53:41.214977 # ok 255 # SKIP Get and set data for VL 1360
6148 10:53:41.215118 # ok 256 Set VL 1376
6149 10:53:41.215260 # ok 257 # SKIP Disabled ZA for VL 1376
6150 10:53:41.215403 # ok 258 # SKIP Get and set data for VL 1376
6151 10:53:41.215549 # ok 259 Set VL 1392
6152 10:53:41.215734 # ok 260 # SKIP Disabled ZA for VL 1392
6153 10:53:41.215869 # ok 261 # SKIP Get and set data for VL 1392
6154 10:53:41.216013 # ok 262 Set VL 1408
6155 10:53:41.216154 # ok 263 # SKIP Disabled ZA for VL 1408
6156 10:53:41.216298 # ok 264 # SKIP Get and set data for VL 1408
6157 10:53:41.216440 # ok 265 Set VL 1424
6158 10:53:41.216583 # ok 266 # SKIP Disabled ZA for VL 1424
6159 10:53:41.216726 # ok 267 # SKIP Get and set data for VL 1424
6160 10:53:41.216869 # ok 268 Set VL 1440
6161 10:53:41.217011 # ok 269 # SKIP Disabled ZA for VL 1440
6162 10:53:41.217155 # ok 270 # SKIP Get and set data for VL 1440
6163 10:53:41.217298 # ok 271 Set VL 1456
6164 10:53:41.217440 # ok 272 # SKIP Disabled ZA for VL 1456
6165 10:53:41.217582 # ok 273 # SKIP Get and set data for VL 1456
6166 10:53:41.217790 # ok 274 Set VL 1472
6167 10:53:41.217964 # ok 275 # SKIP Disabled ZA for VL 1472
6168 10:53:41.218089 # ok 276 # SKIP Get and set data for VL 1472
6169 10:53:41.218207 # ok 277 Set VL 1488
6170 10:53:41.218326 # ok 278 # SKIP Disabled ZA for VL 1488
6171 10:53:41.218446 # ok 279 # SKIP Get and set data for VL 1488
6172 10:53:41.218567 # ok 280 Set VL 1504
6173 10:53:41.218686 # ok 281 # SKIP Disabled ZA for VL 1504
6174 10:53:41.218803 # ok 282 # SKIP Get and set data for VL 1504
6175 10:53:41.218922 # ok 283 Set VL 1520
6176 10:53:41.219077 # ok 284 # SKIP Disabled ZA for VL 1520
6177 10:53:41.219212 # ok 285 # SKIP Get and set data for VL 1520
6178 10:53:41.219334 # ok 286 Set VL 1536
6179 10:53:41.226315 # ok 287 # SKIP Disabled ZA for VL 1536
6180 10:53:41.226845 # ok 288 # SKIP Get and set data for VL 1536
6181 10:53:41.226962 # ok 289 Set VL 1552
6182 10:53:41.227064 # ok 290 # SKIP Disabled ZA for VL 1552
6183 10:53:41.227165 # ok 291 # SKIP Get and set data for VL 1552
6184 10:53:41.227262 # ok 292 Set VL 1568
6185 10:53:41.227358 # ok 293 # SKIP Disabled ZA for VL 1568
6186 10:53:41.227464 # ok 294 # SKIP Get and set data for VL 1568
6187 10:53:41.227553 # ok 295 Set VL 1584
6188 10:53:41.227635 # ok 296 # SKIP Disabled ZA for VL 1584
6189 10:53:41.227718 # ok 297 # SKIP Get and set data for VL 1584
6190 10:53:41.227837 # ok 298 Set VL 1600
6191 10:53:41.227933 # ok 299 # SKIP Disabled ZA for VL 1600
6192 10:53:41.228039 # ok 300 # SKIP Get and set data for VL 1600
6193 10:53:41.228148 # ok 301 Set VL 1616
6194 10:53:41.228240 # ok 302 # SKIP Disabled ZA for VL 1616
6195 10:53:41.228339 # ok 303 # SKIP Get and set data for VL 1616
6196 10:53:41.228736 # ok 304 Set VL 1632
6197 10:53:41.228838 # ok 305 # SKIP Disabled ZA for VL 1632
6198 10:53:41.228917 # ok 306 # SKIP Get and set data for VL 1632
6199 10:53:41.228992 # ok 307 Set VL 1648
6200 10:53:41.229067 # ok 308 # SKIP Disabled ZA for VL 1648
6201 10:53:41.231649 # ok 309 # SKIP Get and set data for VL 1648
6202 10:53:41.231951 # ok 310 Set VL 1664
6203 10:53:41.232056 # ok 311 # SKIP Disabled ZA for VL 1664
6204 10:53:41.232148 # ok 312 # SKIP Get and set data for VL 1664
6205 10:53:41.232250 # ok 313 Set VL 1680
6206 10:53:41.232334 # ok 314 # SKIP Disabled ZA for VL 1680
6207 10:53:41.232418 # ok 315 # SKIP Get and set data for VL 1680
6208 10:53:41.232517 # ok 316 Set VL 1696
6209 10:53:41.232604 # ok 317 # SKIP Disabled ZA for VL 1696
6210 10:53:41.232699 # ok 318 # SKIP Get and set data for VL 1696
6211 10:53:41.232781 # ok 319 Set VL 1712
6212 10:53:41.232857 # ok 320 # SKIP Disabled ZA for VL 1712
6213 10:53:41.287548 # ok 321 # SKIP Get and set data for VL 1712
6214 10:53:41.287811 # ok 322 Set VL 1728
6215 10:53:41.288131 # ok 323 # SKIP Disabled ZA for VL 1728
6216 10:53:41.288240 # ok 324 # SKIP Get and set data for VL 1728
6217 10:53:41.288334 # ok 325 Set VL 1744
6218 10:53:41.288420 # ok 326 # SKIP Disabled ZA for VL 1744
6219 10:53:41.288506 # ok 327 # SKIP Get and set data for VL 1744
6220 10:53:41.288590 # ok 328 Set VL 1760
6221 10:53:41.288695 # ok 329 # SKIP Disabled ZA for VL 1760
6222 10:53:41.288808 # ok 330 # SKIP Get and set data for VL 1760
6223 10:53:41.288913 # ok 331 Set VL 1776
6224 10:53:41.289014 # ok 332 # SKIP Disabled ZA for VL 1776
6225 10:53:41.289117 # ok 333 # SKIP Get and set data for VL 1776
6226 10:53:41.289241 # ok 334 Set VL 1792
6227 10:53:41.307318 # ok 335 # SKIP Disabled ZA for VL 1792
6228 10:53:41.307951 # ok 336 # SKIP Get and set data for VL 1792
6229 10:53:41.308141 # ok 337 Set VL 1808
6230 10:53:41.308318 # ok 338 # SKIP Disabled ZA for VL 1808
6231 10:53:41.308498 # ok 339 # SKIP Get and set data for VL 1808
6232 10:53:41.308676 # ok 340 Set VL 1824
6233 10:53:41.308827 # ok 341 # SKIP Disabled ZA for VL 1824
6234 10:53:41.309013 # ok 342 # SKIP Get and set data for VL 1824
6235 10:53:41.309153 # ok 343 Set VL 1840
6236 10:53:41.309298 # ok 344 # SKIP Disabled ZA for VL 1840
6237 10:53:41.309441 # ok 345 # SKIP Get and set data for VL 1840
6238 10:53:41.309585 # ok 346 Set VL 1856
6239 10:53:41.309744 # ok 347 # SKIP Disabled ZA for VL 1856
6240 10:53:41.309888 # ok 348 # SKIP Get and set data for VL 1856
6241 10:53:41.310030 # ok 349 Set VL 1872
6242 10:53:41.310172 # ok 350 # SKIP Disabled ZA for VL 1872
6243 10:53:41.310314 # ok 351 # SKIP Get and set data for VL 1872
6244 10:53:41.310456 # ok 352 Set VL 1888
6245 10:53:41.310599 # ok 353 # SKIP Disabled ZA for VL 1888
6246 10:53:41.313717 # ok 354 # SKIP Get and set data for VL 1888
6247 10:53:41.313902 # ok 355 Set VL 1904
6248 10:53:41.314277 # ok 356 # SKIP Disabled ZA for VL 1904
6249 10:53:41.314439 # ok 357 # SKIP Get and set data for VL 1904
6250 10:53:41.314590 # ok 358 Set VL 1920
6251 10:53:41.315216 # ok 359 # SKIP Disabled ZA for VL 1920
6252 10:53:41.315418 # ok 360 # SKIP Get and set data for VL 1920
6253 10:53:41.315594 # ok 361 Set VL 1936
6254 10:53:41.315798 # ok 362 # SKIP Disabled ZA for VL 1936
6255 10:53:41.315973 # ok 363 # SKIP Get and set data for VL 1936
6256 10:53:41.316143 # ok 364 Set VL 1952
6257 10:53:41.316307 # ok 365 # SKIP Disabled ZA for VL 1952
6258 10:53:41.316466 # ok 366 # SKIP Get and set data for VL 1952
6259 10:53:41.316625 # ok 367 Set VL 1968
6260 10:53:41.316809 # ok 368 # SKIP Disabled ZA for VL 1968
6261 10:53:41.316936 # ok 369 # SKIP Get and set data for VL 1968
6262 10:53:41.317106 # ok 370 Set VL 1984
6263 10:53:41.317268 # ok 371 # SKIP Disabled ZA for VL 1984
6264 10:53:41.317416 # ok 372 # SKIP Get and set data for VL 1984
6265 10:53:41.317563 # ok 373 Set VL 2000
6266 10:53:41.317726 # ok 374 # SKIP Disabled ZA for VL 2000
6267 10:53:41.317878 # ok 375 # SKIP Get and set data for VL 2000
6268 10:53:41.318030 # ok 376 Set VL 2016
6269 10:53:41.321771 # ok 377 # SKIP Disabled ZA for VL 2016
6270 10:53:41.322163 # ok 378 # SKIP Get and set data for VL 2016
6271 10:53:41.322259 # ok 379 Set VL 2032
6272 10:53:41.322347 # ok 380 # SKIP Disabled ZA for VL 2032
6273 10:53:41.322435 # ok 381 # SKIP Get and set data for VL 2032
6274 10:53:41.322539 # ok 382 Set VL 2048
6275 10:53:41.322629 # ok 383 # SKIP Disabled ZA for VL 2048
6276 10:53:41.322715 # ok 384 # SKIP Get and set data for VL 2048
6277 10:53:41.322802 # ok 385 Set VL 2064
6278 10:53:41.322907 # ok 386 # SKIP Disabled ZA for VL 2064
6279 10:53:41.322997 # ok 387 # SKIP Get and set data for VL 2064
6280 10:53:41.323084 # ok 388 Set VL 2080
6281 10:53:41.323185 # ok 389 # SKIP Disabled ZA for VL 2080
6282 10:53:41.323272 # ok 390 # SKIP Get and set data for VL 2080
6283 10:53:41.323371 # ok 391 Set VL 2096
6284 10:53:41.323459 # ok 392 # SKIP Disabled ZA for VL 2096
6285 10:53:41.323559 # ok 393 # SKIP Get and set data for VL 2096
6286 10:53:41.323647 # ok 394 Set VL 2112
6287 10:53:41.323752 # ok 395 # SKIP Disabled ZA for VL 2112
6288 10:53:41.324037 # ok 396 # SKIP Get and set data for VL 2112
6289 10:53:41.324128 # ok 397 Set VL 2128
6290 10:53:41.324214 # ok 398 # SKIP Disabled ZA for VL 2128
6291 10:53:41.324299 # ok 399 # SKIP Get and set data for VL 2128
6292 10:53:41.324399 # ok 400 Set VL 2144
6293 10:53:41.324486 # ok 401 # SKIP Disabled ZA for VL 2144
6294 10:53:41.324585 # ok 402 # SKIP Get and set data for VL 2144
6295 10:53:41.324677 # ok 403 Set VL 2160
6296 10:53:41.324774 # ok 404 # SKIP Disabled ZA for VL 2160
6297 10:53:41.324852 # ok 405 # SKIP Get and set data for VL 2160
6298 10:53:41.329793 # ok 406 Set VL 2176
6299 10:53:41.330026 # ok 407 # SKIP Disabled ZA for VL 2176
6300 10:53:41.330330 # ok 408 # SKIP Get and set data for VL 2176
6301 10:53:41.330436 # ok 409 Set VL 2192
6302 10:53:41.330524 # ok 410 # SKIP Disabled ZA for VL 2192
6303 10:53:41.330608 # ok 411 # SKIP Get and set data for VL 2192
6304 10:53:41.330717 # ok 412 Set VL 2208
6305 10:53:41.330803 # ok 413 # SKIP Disabled ZA for VL 2208
6306 10:53:41.330887 # ok 414 # SKIP Get and set data for VL 2208
6307 10:53:41.330971 # ok 415 Set VL 2224
6308 10:53:41.331069 # ok 416 # SKIP Disabled ZA for VL 2224
6309 10:53:41.331156 # ok 417 # SKIP Get and set data for VL 2224
6310 10:53:41.331255 # ok 418 Set VL 2240
6311 10:53:41.331340 # ok 419 # SKIP Disabled ZA for VL 2240
6312 10:53:41.331422 # ok 420 # SKIP Get and set data for VL 2240
6313 10:53:41.331521 # ok 421 Set VL 2256
6314 10:53:41.331605 # ok 422 # SKIP Disabled ZA for VL 2256
6315 10:53:41.331688 # ok 423 # SKIP Get and set data for VL 2256
6316 10:53:41.331788 # ok 424 Set VL 2272
6317 10:53:41.331876 # ok 425 # SKIP Disabled ZA for VL 2272
6318 10:53:41.331975 # ok 426 # SKIP Get and set data for VL 2272
6319 10:53:41.332063 # ok 427 Set VL 2288
6320 10:53:41.332150 # ok 428 # SKIP Disabled ZA for VL 2288
6321 10:53:41.332252 # ok 429 # SKIP Get and set data for VL 2288
6322 10:53:41.332341 # ok 430 Set VL 2304
6323 10:53:41.332443 # ok 431 # SKIP Disabled ZA for VL 2304
6324 10:53:41.332546 # ok 432 # SKIP Get and set data for VL 2304
6325 10:53:41.332647 # ok 433 Set VL 2320
6326 10:53:41.332747 # ok 434 # SKIP Disabled ZA for VL 2320
6327 10:53:41.338078 # ok 435 # SKIP Get and set data for VL 2320
6328 10:53:41.338519 # ok 436 Set VL 2336
6329 10:53:41.338613 # ok 437 # SKIP Disabled ZA for VL 2336
6330 10:53:41.338703 # ok 438 # SKIP Get and set data for VL 2336
6331 10:53:41.338790 # ok 439 Set VL 2352
6332 10:53:41.338877 # ok 440 # SKIP Disabled ZA for VL 2352
6333 10:53:41.338980 # ok 441 # SKIP Get and set data for VL 2352
6334 10:53:41.339068 # ok 442 Set VL 2368
6335 10:53:41.339155 # ok 443 # SKIP Disabled ZA for VL 2368
6336 10:53:41.339239 # ok 444 # SKIP Get and set data for VL 2368
6337 10:53:41.339325 # ok 445 Set VL 2384
6338 10:53:41.339426 # ok 446 # SKIP Disabled ZA for VL 2384
6339 10:53:41.339514 # ok 447 # SKIP Get and set data for VL 2384
6340 10:53:41.339598 # ok 448 Set VL 2400
6341 10:53:41.339683 # ok 449 # SKIP Disabled ZA for VL 2400
6342 10:53:41.339790 # ok 450 # SKIP Get and set data for VL 2400
6343 10:53:41.339876 # ok 451 Set VL 2416
6344 10:53:41.339959 # ok 452 # SKIP Disabled ZA for VL 2416
6345 10:53:41.340056 # ok 453 # SKIP Get and set data for VL 2416
6346 10:53:41.340143 # ok 454 Set VL 2432
6347 10:53:41.340243 # ok 455 # SKIP Disabled ZA for VL 2432
6348 10:53:41.340328 # ok 456 # SKIP Get and set data for VL 2432
6349 10:53:41.340427 # ok 457 Set VL 2448
6350 10:53:41.340514 # ok 458 # SKIP Disabled ZA for VL 2448
6351 10:53:41.340613 # ok 459 # SKIP Get and set data for VL 2448
6352 10:53:41.340699 # ok 460 Set VL 2464
6353 10:53:41.340798 # ok 461 # SKIP Disabled ZA for VL 2464
6354 10:53:41.344818 # ok 462 # SKIP Get and set data for VL 2464
6355 10:53:41.345077 # ok 463 Set VL 2480
6356 10:53:41.348631 # ok 464 # SKIP Disabled ZA for VL 2480
6357 10:53:41.349116 # ok 465 # SKIP Get and set data for VL 2480
6358 10:53:41.349261 # ok 466 Set VL 2496
6359 10:53:41.349743 # ok 467 # SKIP Disabled ZA for VL 2496
6360 10:53:41.350187 # ok 468 # SKIP Get and set data for VL 2496
6361 10:53:41.350375 # ok 469 Set VL 2512
6362 10:53:41.350541 # ok 470 # SKIP Disabled ZA for VL 2512
6363 10:53:41.350704 # ok 471 # SKIP Get and set data for VL 2512
6364 10:53:41.350872 # ok 472 Set VL 2528
6365 10:53:41.351073 # ok 473 # SKIP Disabled ZA for VL 2528
6366 10:53:41.351235 # ok 474 # SKIP Get and set data for VL 2528
6367 10:53:41.351400 # ok 475 Set VL 2544
6368 10:53:41.351564 # ok 476 # SKIP Disabled ZA for VL 2544
6369 10:53:41.351728 # ok 477 # SKIP Get and set data for VL 2544
6370 10:53:41.351890 # ok 478 Set VL 2560
6371 10:53:41.352047 # ok 479 # SKIP Disabled ZA for VL 2560
6372 10:53:41.352191 # ok 480 # SKIP Get and set data for VL 2560
6373 10:53:41.352333 # ok 481 Set VL 2576
6374 10:53:41.352516 # ok 482 # SKIP Disabled ZA for VL 2576
6375 10:53:41.352652 # ok 483 # SKIP Get and set data for VL 2576
6376 10:53:41.352779 # ok 484 Set VL 2592
6377 10:53:41.352896 # ok 485 # SKIP Disabled ZA for VL 2592
6378 10:53:41.353012 # ok 486 # SKIP Get and set data for VL 2592
6379 10:53:41.353127 # ok 487 Set VL 2608
6380 10:53:41.353242 # ok 488 # SKIP Disabled ZA for VL 2608
6381 10:53:41.353357 # ok 489 # SKIP Get and set data for VL 2608
6382 10:53:41.353472 # ok 490 Set VL 2624
6383 10:53:41.353587 # ok 491 # SKIP Disabled ZA for VL 2624
6384 10:53:41.353772 # ok 492 # SKIP Get and set data for VL 2624
6385 10:53:41.353972 # ok 493 Set VL 2640
6386 10:53:41.354158 # ok 494 # SKIP Disabled ZA for VL 2640
6387 10:53:41.354342 # ok 495 # SKIP Get and set data for VL 2640
6388 10:53:41.354527 # ok 496 Set VL 2656
6389 10:53:41.354701 # ok 497 # SKIP Disabled ZA for VL 2656
6390 10:53:41.354844 # ok 498 # SKIP Get and set data for VL 2656
6391 10:53:41.354986 # ok 499 Set VL 2672
6392 10:53:41.355174 # ok 500 # SKIP Disabled ZA for VL 2672
6393 10:53:41.355313 # ok 501 # SKIP Get and set data for VL 2672
6394 10:53:41.355458 # ok 502 Set VL 2688
6395 10:53:41.355602 # ok 503 # SKIP Disabled ZA for VL 2688
6396 10:53:41.357923 # ok 504 # SKIP Get and set data for VL 2688
6397 10:53:41.358418 # ok 505 Set VL 2704
6398 10:53:41.358617 # ok 506 # SKIP Disabled ZA for VL 2704
6399 10:53:41.358784 # ok 507 # SKIP Get and set data for VL 2704
6400 10:53:41.359946 # ok 508 Set VL 2720
6401 10:53:41.360146 # ok 509 # SKIP Disabled ZA for VL 2720
6402 10:53:41.360333 # ok 510 # SKIP Get and set data for VL 2720
6403 10:53:41.360501 # ok 511 Set VL 2736
6404 10:53:41.360657 # ok 512 # SKIP Disabled ZA for VL 2736
6405 10:53:41.360802 # ok 513 # SKIP Get and set data for VL 2736
6406 10:53:41.360923 # ok 514 Set VL 2752
6407 10:53:41.361039 # ok 515 # SKIP Disabled ZA for VL 2752
6408 10:53:41.361154 # ok 516 # SKIP Get and set data for VL 2752
6409 10:53:41.361269 # ok 517 Set VL 2768
6410 10:53:41.361383 # ok 518 # SKIP Disabled ZA for VL 2768
6411 10:53:41.361498 # ok 519 # SKIP Get and set data for VL 2768
6412 10:53:41.361613 # ok 520 Set VL 2784
6413 10:53:41.361755 # ok 521 # SKIP Disabled ZA for VL 2784
6414 10:53:41.361873 # ok 522 # SKIP Get and set data for VL 2784
6415 10:53:41.361988 # ok 523 Set VL 2800
6416 10:53:41.362104 # ok 524 # SKIP Disabled ZA for VL 2800
6417 10:53:41.362478 # ok 525 # SKIP Get and set data for VL 2800
6418 10:53:41.362697 # ok 526 Set VL 2816
6419 10:53:41.362885 # ok 527 # SKIP Disabled ZA for VL 2816
6420 10:53:41.363031 # ok 528 # SKIP Get and set data for VL 2816
6421 10:53:41.363175 # ok 529 Set VL 2832
6422 10:53:41.363320 # ok 530 # SKIP Disabled ZA for VL 2832
6423 10:53:41.363461 # ok 531 # SKIP Get and set data for VL 2832
6424 10:53:41.363601 # ok 532 Set VL 2848
6425 10:53:41.365986 # ok 533 # SKIP Disabled ZA for VL 2848
6426 10:53:41.366465 # ok 534 # SKIP Get and set data for VL 2848
6427 10:53:41.366644 # ok 535 Set VL 2864
6428 10:53:41.366813 # ok 536 # SKIP Disabled ZA for VL 2864
6429 10:53:41.366980 # ok 537 # SKIP Get and set data for VL 2864
6430 10:53:41.367142 # ok 538 Set VL 2880
6431 10:53:41.367304 # ok 539 # SKIP Disabled ZA for VL 2880
6432 10:53:41.367503 # ok 540 # SKIP Get and set data for VL 2880
6433 10:53:41.367672 # ok 541 Set VL 2896
6434 10:53:41.367834 # ok 542 # SKIP Disabled ZA for VL 2896
6435 10:53:41.367992 # ok 543 # SKIP Get and set data for VL 2896
6436 10:53:41.368155 # ok 544 Set VL 2912
6437 10:53:41.368318 # ok 545 # SKIP Disabled ZA for VL 2912
6438 10:53:41.368479 # ok 546 # SKIP Get and set data for VL 2912
6439 10:53:41.368642 # ok 547 Set VL 2928
6440 10:53:41.368803 # ok 548 # SKIP Disabled ZA for VL 2928
6441 10:53:41.368926 # ok 549 # SKIP Get and set data for VL 2928
6442 10:53:41.369042 # ok 550 Set VL 2944
6443 10:53:41.369157 # ok 551 # SKIP Disabled ZA for VL 2944
6444 10:53:41.369303 # ok 552 # SKIP Get and set data for VL 2944
6445 10:53:41.369425 # ok 553 Set VL 2960
6446 10:53:41.369542 # ok 554 # SKIP Disabled ZA for VL 2960
6447 10:53:41.369674 # ok 555 # SKIP Get and set data for VL 2960
6448 10:53:41.369794 # ok 556 Set VL 2976
6449 10:53:41.369908 # ok 557 # SKIP Disabled ZA for VL 2976
6450 10:53:41.370022 # ok 558 # SKIP Get and set data for VL 2976
6451 10:53:41.370136 # ok 559 Set VL 2992
6452 10:53:41.370250 # ok 560 # SKIP Disabled ZA for VL 2992
6453 10:53:41.370364 # ok 561 # SKIP Get and set data for VL 2992
6454 10:53:41.370478 # ok 562 Set VL 3008
6455 10:53:41.370591 # ok 563 # SKIP Disabled ZA for VL 3008
6456 10:53:41.370704 # ok 564 # SKIP Get and set data for VL 3008
6457 10:53:41.370818 # ok 565 Set VL 3024
6458 10:53:41.370931 # ok 566 # SKIP Disabled ZA for VL 3024
6459 10:53:41.374025 # ok 567 # SKIP Get and set data for VL 3024
6460 10:53:41.374386 # ok 568 Set VL 3040
6461 10:53:41.374481 # ok 569 # SKIP Disabled ZA for VL 3040
6462 10:53:41.374570 # ok 570 # SKIP Get and set data for VL 3040
6463 10:53:41.374673 # ok 571 Set VL 3056
6464 10:53:41.374763 # ok 572 # SKIP Disabled ZA for VL 3056
6465 10:53:41.374848 # ok 573 # SKIP Get and set data for VL 3056
6466 10:53:41.374929 # ok 574 Set VL 3072
6467 10:53:41.375028 # ok 575 # SKIP Disabled ZA for VL 3072
6468 10:53:41.375113 # ok 576 # SKIP Get and set data for VL 3072
6469 10:53:41.375197 # ok 577 Set VL 3088
6470 10:53:41.375279 # ok 578 # SKIP Disabled ZA for VL 3088
6471 10:53:41.375377 # ok 579 # SKIP Get and set data for VL 3088
6472 10:53:41.375463 # ok 580 Set VL 3104
6473 10:53:41.375547 # ok 581 # SKIP Disabled ZA for VL 3104
6474 10:53:41.375645 # ok 582 # SKIP Get and set data for VL 3104
6475 10:53:41.375730 # ok 583 Set VL 3120
6476 10:53:41.375828 # ok 584 # SKIP Disabled ZA for VL 3120
6477 10:53:41.375915 # ok 585 # SKIP Get and set data for VL 3120
6478 10:53:41.376013 # ok 586 Set VL 3136
6479 10:53:41.376112 # ok 587 # SKIP Disabled ZA for VL 3136
6480 10:53:41.376211 # ok 588 # SKIP Get and set data for VL 3136
6481 10:53:41.376310 # ok 589 Set VL 3152
6482 10:53:41.382728 # ok 590 # SKIP Disabled ZA for VL 3152
6483 10:53:41.383285 # ok 591 # SKIP Get and set data for VL 3152
6484 10:53:41.383497 # ok 592 Set VL 3168
6485 10:53:41.383725 # ok 593 # SKIP Disabled ZA for VL 3168
6486 10:53:41.383944 # ok 594 # SKIP Get and set data for VL 3168
6487 10:53:41.384147 # ok 595 Set VL 3184
6488 10:53:41.384399 # ok 596 # SKIP Disabled ZA for VL 3184
6489 10:53:41.384717 # ok 597 # SKIP Get and set data for VL 3184
6490 10:53:41.384910 # ok 598 Set VL 3200
6491 10:53:41.385043 # ok 599 # SKIP Disabled ZA for VL 3200
6492 10:53:41.385160 # ok 600 # SKIP Get and set data for VL 3200
6493 10:53:41.385276 # ok 601 Set VL 3216
6494 10:53:41.385390 # ok 602 # SKIP Disabled ZA for VL 3216
6495 10:53:41.385505 # ok 603 # SKIP Get and set data for VL 3216
6496 10:53:41.385618 # ok 604 Set VL 3232
6497 10:53:41.385754 # ok 605 # SKIP Disabled ZA for VL 3232
6498 10:53:41.385869 # ok 606 # SKIP Get and set data for VL 3232
6499 10:53:41.385982 # ok 607 Set VL 3248
6500 10:53:41.386094 # ok 608 # SKIP Disabled ZA for VL 3248
6501 10:53:41.386208 # ok 609 # SKIP Get and set data for VL 3248
6502 10:53:41.386322 # ok 610 Set VL 3264
6503 10:53:41.386435 # ok 611 # SKIP Disabled ZA for VL 3264
6504 10:53:41.386579 # ok 612 # SKIP Get and set data for VL 3264
6505 10:53:41.388841 # ok 613 Set VL 3280
6506 10:53:41.390123 # ok 614 # SKIP Disabled ZA for VL 3280
6507 10:53:41.390262 # ok 615 # SKIP Get and set data for VL 3280
6508 10:53:41.390356 # ok 616 Set VL 3296
6509 10:53:41.390462 # ok 617 # SKIP Disabled ZA for VL 3296
6510 10:53:41.390566 # ok 618 # SKIP Get and set data for VL 3296
6511 10:53:41.390655 # ok 619 Set VL 3312
6512 10:53:41.390754 # ok 620 # SKIP Disabled ZA for VL 3312
6513 10:53:41.390841 # ok 621 # SKIP Get and set data for VL 3312
6514 10:53:41.390940 # ok 622 Set VL 3328
6515 10:53:41.391243 # ok 623 # SKIP Disabled ZA for VL 3328
6516 10:53:41.391352 # ok 624 # SKIP Get and set data for VL 3328
6517 10:53:41.391440 # ok 625 Set VL 3344
6518 10:53:41.391540 # ok 626 # SKIP Disabled ZA for VL 3344
6519 10:53:41.391625 # ok 627 # SKIP Get and set data for VL 3344
6520 10:53:41.391708 # ok 628 Set VL 3360
6521 10:53:41.391811 # ok 629 # SKIP Disabled ZA for VL 3360
6522 10:53:41.391902 # ok 630 # SKIP Get and set data for VL 3360
6523 10:53:41.392003 # ok 631 Set VL 3376
6524 10:53:41.392093 # ok 632 # SKIP Disabled ZA for VL 3376
6525 10:53:41.392193 # ok 633 # SKIP Get and set data for VL 3376
6526 10:53:41.392291 # ok 634 Set VL 3392
6527 10:53:41.392392 # ok 635 # SKIP Disabled ZA for VL 3392
6528 10:53:41.392494 # ok 636 # SKIP Get and set data for VL 3392
6529 10:53:41.392598 # ok 637 Set VL 3408
6530 10:53:41.392903 # ok 638 # SKIP Disabled ZA for VL 3408
6531 10:53:41.397859 # ok 639 # SKIP Get and set data for VL 3408
6532 10:53:41.398087 # ok 640 Set VL 3424
6533 10:53:41.398401 # ok 641 # SKIP Disabled ZA for VL 3424
6534 10:53:41.398506 # ok 642 # SKIP Get and set data for VL 3424
6535 10:53:41.398593 # ok 643 Set VL 3440
6536 10:53:41.398679 # ok 644 # SKIP Disabled ZA for VL 3440
6537 10:53:41.398779 # ok 645 # SKIP Get and set data for VL 3440
6538 10:53:41.398871 # ok 646 Set VL 3456
6539 10:53:41.398954 # ok 647 # SKIP Disabled ZA for VL 3456
6540 10:53:41.399059 # ok 648 # SKIP Get and set data for VL 3456
6541 10:53:41.399147 # ok 649 Set VL 3472
6542 10:53:41.399451 # ok 650 # SKIP Disabled ZA for VL 3472
6543 10:53:41.399553 # ok 651 # SKIP Get and set data for VL 3472
6544 10:53:41.399641 # ok 652 Set VL 3488
6545 10:53:41.399723 # ok 653 # SKIP Disabled ZA for VL 3488
6546 10:53:41.399821 # ok 654 # SKIP Get and set data for VL 3488
6547 10:53:41.399908 # ok 655 Set VL 3504
6548 10:53:41.399992 # ok 656 # SKIP Disabled ZA for VL 3504
6549 10:53:41.400092 # ok 657 # SKIP Get and set data for VL 3504
6550 10:53:41.400175 # ok 658 Set VL 3520
6551 10:53:41.400260 # ok 659 # SKIP Disabled ZA for VL 3520
6552 10:53:41.400345 # ok 660 # SKIP Get and set data for VL 3520
6553 10:53:41.400430 # ok 661 Set VL 3536
6554 10:53:41.400532 # ok 662 # SKIP Disabled ZA for VL 3536
6555 10:53:41.400620 # ok 663 # SKIP Get and set data for VL 3536
6556 10:53:41.400703 # ok 664 Set VL 3552
6557 10:53:41.400785 # ok 665 # SKIP Disabled ZA for VL 3552
6558 10:53:41.400884 # ok 666 # SKIP Get and set data for VL 3552
6559 10:53:41.400969 # ok 667 Set VL 3568
6560 10:53:41.401052 # ok 668 # SKIP Disabled ZA for VL 3568
6561 10:53:41.401135 # ok 669 # SKIP Get and set data for VL 3568
6562 10:53:41.407901 # ok 670 Set VL 3584
6563 10:53:41.408125 # ok 671 # SKIP Disabled ZA for VL 3584
6564 10:53:41.408218 # ok 672 # SKIP Get and set data for VL 3584
6565 10:53:41.408305 # ok 673 Set VL 3600
6566 10:53:41.408410 # ok 674 # SKIP Disabled ZA for VL 3600
6567 10:53:41.408500 # ok 675 # SKIP Get and set data for VL 3600
6568 10:53:41.408586 # ok 676 Set VL 3616
6569 10:53:41.408669 # ok 677 # SKIP Disabled ZA for VL 3616
6570 10:53:41.408754 # ok 678 # SKIP Get and set data for VL 3616
6571 10:53:41.408844 # ok 679 Set VL 3632
6572 10:53:41.408930 # ok 680 # SKIP Disabled ZA for VL 3632
6573 10:53:41.409029 # ok 681 # SKIP Get and set data for VL 3632
6574 10:53:41.409116 # ok 682 Set VL 3648
6575 10:53:41.409203 # ok 683 # SKIP Disabled ZA for VL 3648
6576 10:53:41.409287 # ok 684 # SKIP Get and set data for VL 3648
6577 10:53:41.409368 # ok 685 Set VL 3664
6578 10:53:41.422635 # ok 686 # SKIP Disabled ZA for VL 3664
6579 10:53:41.423207 # ok 687 # SKIP Get and set data for VL 3664
6580 10:53:41.423398 # ok 688 Set VL 3680
6581 10:53:41.423571 # ok 689 # SKIP Disabled ZA for VL 3680
6582 10:53:41.423738 # ok 690 # SKIP Get and set data for VL 3680
6583 10:53:41.423947 # ok 691 Set VL 3696
6584 10:53:41.424159 # ok 692 # SKIP Disabled ZA for VL 3696
6585 10:53:41.424339 # ok 693 # SKIP Get and set data for VL 3696
6586 10:53:41.424517 # ok 694 Set VL 3712
6587 10:53:41.424733 # ok 695 # SKIP Disabled ZA for VL 3712
6588 10:53:41.424914 # ok 696 # SKIP Get and set data for VL 3712
6589 10:53:41.425074 # ok 697 Set VL 3728
6590 10:53:41.425230 # ok 698 # SKIP Disabled ZA for VL 3728
6591 10:53:41.425388 # ok 699 # SKIP Get and set data for VL 3728
6592 10:53:41.425546 # ok 700 Set VL 3744
6593 10:53:41.425718 # ok 701 # SKIP Disabled ZA for VL 3744
6594 10:53:41.425875 # ok 702 # SKIP Get and set data for VL 3744
6595 10:53:41.426031 # ok 703 Set VL 3760
6596 10:53:41.426185 # ok 704 # SKIP Disabled ZA for VL 3760
6597 10:53:41.426340 # ok 705 # SKIP Get and set data for VL 3760
6598 10:53:41.426495 # ok 706 Set VL 3776
6599 10:53:41.426650 # ok 707 # SKIP Disabled ZA for VL 3776
6600 10:53:41.426844 # ok 708 # SKIP Get and set data for VL 3776
6601 10:53:41.433974 # ok 709 Set VL 3792
6602 10:53:41.434577 # ok 710 # SKIP Disabled ZA for VL 3792
6603 10:53:41.434778 # ok 711 # SKIP Get and set data for VL 3792
6604 10:53:41.434943 # ok 712 Set VL 3808
6605 10:53:41.435100 # ok 713 # SKIP Disabled ZA for VL 3808
6606 10:53:41.435256 # ok 714 # SKIP Get and set data for VL 3808
6607 10:53:41.435412 # ok 715 Set VL 3824
6608 10:53:41.435567 # ok 716 # SKIP Disabled ZA for VL 3824
6609 10:53:41.435722 # ok 717 # SKIP Get and set data for VL 3824
6610 10:53:41.435915 # ok 718 Set VL 3840
6611 10:53:41.436077 # ok 719 # SKIP Disabled ZA for VL 3840
6612 10:53:41.436231 # ok 720 # SKIP Get and set data for VL 3840
6613 10:53:41.436379 # ok 721 Set VL 3856
6614 10:53:41.436525 # ok 722 # SKIP Disabled ZA for VL 3856
6615 10:53:41.436671 # ok 723 # SKIP Get and set data for VL 3856
6616 10:53:41.436815 # ok 724 Set VL 3872
6617 10:53:41.436955 # ok 725 # SKIP Disabled ZA for VL 3872
6618 10:53:41.437096 # ok 726 # SKIP Get and set data for VL 3872
6619 10:53:41.437236 # ok 727 Set VL 3888
6620 10:53:41.437377 # ok 728 # SKIP Disabled ZA for VL 3888
6621 10:53:41.437518 # ok 729 # SKIP Get and set data for VL 3888
6622 10:53:41.437672 # ok 730 Set VL 3904
6623 10:53:41.437835 # ok 731 # SKIP Disabled ZA for VL 3904
6624 10:53:41.438017 # ok 732 # SKIP Get and set data for VL 3904
6625 10:53:41.438182 # ok 733 Set VL 3920
6626 10:53:41.438315 # ok 734 # SKIP Disabled ZA for VL 3920
6627 10:53:41.438502 # ok 735 # SKIP Get and set data for VL 3920
6628 10:53:41.438670 # ok 736 Set VL 3936
6629 10:53:41.438848 # ok 737 # SKIP Disabled ZA for VL 3936
6630 10:53:41.439022 # ok 738 # SKIP Get and set data for VL 3936
6631 10:53:41.439199 # ok 739 Set VL 3952
6632 10:53:41.439371 # ok 740 # SKIP Disabled ZA for VL 3952
6633 10:53:41.439549 # ok 741 # SKIP Get and set data for VL 3952
6634 10:53:41.439722 # ok 742 Set VL 3968
6635 10:53:41.439879 # ok 743 # SKIP Disabled ZA for VL 3968
6636 10:53:41.440004 # ok 744 # SKIP Get and set data for VL 3968
6637 10:53:41.450442 # ok 745 Set VL 3984
6638 10:53:41.450849 # ok 746 # SKIP Disabled ZA for VL 3984
6639 10:53:41.450931 # ok 747 # SKIP Get and set data for VL 3984
6640 10:53:41.451261 # ok 748 Set VL 4000
6641 10:53:41.451343 # ok 749 # SKIP Disabled ZA for VL 4000
6642 10:53:41.451407 # ok 750 # SKIP Get and set data for VL 4000
6643 10:53:41.451467 # ok 751 Set VL 4016
6644 10:53:41.451526 # ok 752 # SKIP Disabled ZA for VL 4016
6645 10:53:41.451585 # ok 753 # SKIP Get and set data for VL 4016
6646 10:53:41.451645 # ok 754 Set VL 4032
6647 10:53:41.451704 # ok 755 # SKIP Disabled ZA for VL 4032
6648 10:53:41.451946 # ok 756 # SKIP Get and set data for VL 4032
6649 10:53:41.452010 # ok 757 Set VL 4048
6650 10:53:41.452070 # ok 758 # SKIP Disabled ZA for VL 4048
6651 10:53:41.452128 # ok 759 # SKIP Get and set data for VL 4048
6652 10:53:41.452187 # ok 760 Set VL 4064
6653 10:53:41.452246 # ok 761 # SKIP Disabled ZA for VL 4064
6654 10:53:41.452304 # ok 762 # SKIP Get and set data for VL 4064
6655 10:53:41.452363 # ok 763 Set VL 4080
6656 10:53:41.452422 # ok 764 # SKIP Disabled ZA for VL 4080
6657 10:53:41.452479 # ok 765 # SKIP Get and set data for VL 4080
6658 10:53:41.452538 # ok 766 Set VL 4096
6659 10:53:41.452610 # ok 767 # SKIP Disabled ZA for VL 4096
6660 10:53:41.452671 # ok 768 # SKIP Get and set data for VL 4096
6661 10:53:41.452748 # ok 769 Set VL 4112
6662 10:53:41.452818 # ok 770 # SKIP Disabled ZA for VL 4112
6663 10:53:41.452884 # ok 771 # SKIP Get and set data for VL 4112
6664 10:53:41.452944 # ok 772 Set VL 4128
6665 10:53:41.453002 # ok 773 # SKIP Disabled ZA for VL 4128
6666 10:53:41.453060 # ok 774 # SKIP Get and set data for VL 4128
6667 10:53:41.453119 # ok 775 Set VL 4144
6668 10:53:41.453192 # ok 776 # SKIP Disabled ZA for VL 4144
6669 10:53:41.453255 # ok 777 # SKIP Get and set data for VL 4144
6670 10:53:41.453314 # ok 778 Set VL 4160
6671 10:53:41.453373 # ok 779 # SKIP Disabled ZA for VL 4160
6672 10:53:41.453431 # ok 780 # SKIP Get and set data for VL 4160
6673 10:53:41.453489 # ok 781 Set VL 4176
6674 10:53:41.453547 # ok 782 # SKIP Disabled ZA for VL 4176
6675 10:53:41.461730 # ok 783 # SKIP Get and set data for VL 4176
6676 10:53:41.461923 # ok 784 Set VL 4192
6677 10:53:41.461992 # ok 785 # SKIP Disabled ZA for VL 4192
6678 10:53:41.462249 # ok 786 # SKIP Get and set data for VL 4192
6679 10:53:41.462317 # ok 787 Set VL 4208
6680 10:53:41.462378 # ok 788 # SKIP Disabled ZA for VL 4208
6681 10:53:41.462439 # ok 789 # SKIP Get and set data for VL 4208
6682 10:53:41.462499 # ok 790 Set VL 4224
6683 10:53:41.462558 # ok 791 # SKIP Disabled ZA for VL 4224
6684 10:53:41.462618 # ok 792 # SKIP Get and set data for VL 4224
6685 10:53:41.462862 # ok 793 Set VL 4240
6686 10:53:41.462931 # ok 794 # SKIP Disabled ZA for VL 4240
6687 10:53:41.462994 # ok 795 # SKIP Get and set data for VL 4240
6688 10:53:41.463056 # ok 796 Set VL 4256
6689 10:53:41.463116 # ok 797 # SKIP Disabled ZA for VL 4256
6690 10:53:41.463177 # ok 798 # SKIP Get and set data for VL 4256
6691 10:53:41.463239 # ok 799 Set VL 4272
6692 10:53:41.463300 # ok 800 # SKIP Disabled ZA for VL 4272
6693 10:53:41.463361 # ok 801 # SKIP Get and set data for VL 4272
6694 10:53:41.463421 # ok 802 Set VL 4288
6695 10:53:41.463496 # ok 803 # SKIP Disabled ZA for VL 4288
6696 10:53:41.463560 # ok 804 # SKIP Get and set data for VL 4288
6697 10:53:41.463621 # ok 805 Set VL 4304
6698 10:53:41.463683 # ok 806 # SKIP Disabled ZA for VL 4304
6699 10:53:41.463745 # ok 807 # SKIP Get and set data for VL 4304
6700 10:53:41.463805 # ok 808 Set VL 4320
6701 10:53:41.463865 # ok 809 # SKIP Disabled ZA for VL 4320
6702 10:53:41.463940 # ok 810 # SKIP Get and set data for VL 4320
6703 10:53:41.464019 # ok 811 Set VL 4336
6704 10:53:41.464083 # ok 812 # SKIP Disabled ZA for VL 4336
6705 10:53:41.464145 # ok 813 # SKIP Get and set data for VL 4336
6706 10:53:41.464203 # ok 814 Set VL 4352
6707 10:53:41.464261 # ok 815 # SKIP Disabled ZA for VL 4352
6708 10:53:41.464320 # ok 816 # SKIP Get and set data for VL 4352
6709 10:53:41.464377 # ok 817 Set VL 4368
6710 10:53:41.464435 # ok 818 # SKIP Disabled ZA for VL 4368
6711 10:53:41.464493 # ok 819 # SKIP Get and set data for VL 4368
6712 10:53:41.464551 # ok 820 Set VL 4384
6713 10:53:41.464609 # ok 821 # SKIP Disabled ZA for VL 4384
6714 10:53:41.464862 # ok 822 # SKIP Get and set data for VL 4384
6715 10:53:41.472561 # ok 823 Set VL 4400
6716 10:53:41.472989 # ok 824 # SKIP Disabled ZA for VL 4400
6717 10:53:41.473068 # ok 825 # SKIP Get and set data for VL 4400
6718 10:53:41.473132 # ok 826 Set VL 4416
6719 10:53:41.473196 # ok 827 # SKIP Disabled ZA for VL 4416
6720 10:53:41.473256 # ok 828 # SKIP Get and set data for VL 4416
6721 10:53:41.473315 # ok 829 Set VL 4432
6722 10:53:41.480551 # ok 830 # SKIP Disabled ZA for VL 4432
6723 10:53:41.480775 # ok 831 # SKIP Get and set data for VL 4432
6724 10:53:41.481067 # ok 832 Set VL 4448
6725 10:53:41.481148 # ok 833 # SKIP Disabled ZA for VL 4448
6726 10:53:41.481222 # ok 834 # SKIP Get and set data for VL 4448
6727 10:53:41.481283 # ok 835 Set VL 4464
6728 10:53:41.482113 # ok 836 # SKIP Disabled ZA for VL 4464
6729 10:53:41.482401 # ok 837 # SKIP Get and set data for VL 4464
6730 10:53:41.482498 # ok 838 Set VL 4480
6731 10:53:41.482567 # ok 839 # SKIP Disabled ZA for VL 4480
6732 10:53:41.482628 # ok 840 # SKIP Get and set data for VL 4480
6733 10:53:41.482886 # ok 841 Set VL 4496
6734 10:53:41.482991 # ok 842 # SKIP Disabled ZA for VL 4496
6735 10:53:41.483084 # ok 843 # SKIP Get and set data for VL 4496
6736 10:53:41.483193 # ok 844 Set VL 4512
6737 10:53:41.483269 # ok 845 # SKIP Disabled ZA for VL 4512
6738 10:53:41.483346 # ok 846 # SKIP Get and set data for VL 4512
6739 10:53:41.483433 # ok 847 Set VL 4528
6740 10:53:41.483513 # ok 848 # SKIP Disabled ZA for VL 4528
6741 10:53:41.483581 # ok 849 # SKIP Get and set data for VL 4528
6742 10:53:41.483644 # ok 850 Set VL 4544
6743 10:53:41.483747 # ok 851 # SKIP Disabled ZA for VL 4544
6744 10:53:41.483839 # ok 852 # SKIP Get and set data for VL 4544
6745 10:53:41.483932 # ok 853 Set VL 4560
6746 10:53:41.484017 # ok 854 # SKIP Disabled ZA for VL 4560
6747 10:53:41.484115 # ok 855 # SKIP Get and set data for VL 4560
6748 10:53:41.484218 # ok 856 Set VL 4576
6749 10:53:41.484330 # ok 857 # SKIP Disabled ZA for VL 4576
6750 10:53:41.484401 # ok 858 # SKIP Get and set data for VL 4576
6751 10:53:41.484480 # ok 859 Set VL 4592
6752 10:53:41.484574 # ok 860 # SKIP Disabled ZA for VL 4592
6753 10:53:41.484643 # ok 861 # SKIP Get and set data for VL 4592
6754 10:53:41.484729 # ok 862 Set VL 4608
6755 10:53:41.484820 # ok 863 # SKIP Disabled ZA for VL 4608
6756 10:53:41.484884 # ok 864 # SKIP Get and set data for VL 4608
6757 10:53:41.484958 # ok 865 Set VL 4624
6758 10:53:41.485020 # ok 866 # SKIP Disabled ZA for VL 4624
6759 10:53:41.485080 # ok 867 # SKIP Get and set data for VL 4624
6760 10:53:41.485139 # ok 868 Set VL 4640
6761 10:53:41.485197 # ok 869 # SKIP Disabled ZA for VL 4640
6762 10:53:41.489963 # ok 870 # SKIP Get and set data for VL 4640
6763 10:53:41.490319 # ok 871 Set VL 4656
6764 10:53:41.490453 # ok 872 # SKIP Disabled ZA for VL 4656
6765 10:53:41.490876 # ok 873 # SKIP Get and set data for VL 4656
6766 10:53:41.491067 # ok 874 Set VL 4672
6767 10:53:41.491236 # ok 875 # SKIP Disabled ZA for VL 4672
6768 10:53:41.491370 # ok 876 # SKIP Get and set data for VL 4672
6769 10:53:41.491514 # ok 877 Set VL 4688
6770 10:53:41.491672 # ok 878 # SKIP Disabled ZA for VL 4688
6771 10:53:41.491811 # ok 879 # SKIP Get and set data for VL 4688
6772 10:53:41.491949 # ok 880 Set VL 4704
6773 10:53:41.492105 # ok 881 # SKIP Disabled ZA for VL 4704
6774 10:53:41.492244 # ok 882 # SKIP Get and set data for VL 4704
6775 10:53:41.492443 # ok 883 Set VL 4720
6776 10:53:41.492601 # ok 884 # SKIP Disabled ZA for VL 4720
6777 10:53:41.492725 # ok 885 # SKIP Get and set data for VL 4720
6778 10:53:41.492849 # ok 886 Set VL 4736
6779 10:53:41.492968 # ok 887 # SKIP Disabled ZA for VL 4736
6780 10:53:41.493085 # ok 888 # SKIP Get and set data for VL 4736
6781 10:53:41.493199 # ok 889 Set VL 4752
6782 10:53:41.493311 # ok 890 # SKIP Disabled ZA for VL 4752
6783 10:53:41.493424 # ok 891 # SKIP Get and set data for VL 4752
6784 10:53:41.493536 # ok 892 Set VL 4768
6785 10:53:41.493659 # ok 893 # SKIP Disabled ZA for VL 4768
6786 10:53:41.493777 # ok 894 # SKIP Get and set data for VL 4768
6787 10:53:41.493889 # ok 895 Set VL 4784
6788 10:53:41.494000 # ok 896 # SKIP Disabled ZA for VL 4784
6789 10:53:41.494110 # ok 897 # SKIP Get and set data for VL 4784
6790 10:53:41.494221 # ok 898 Set VL 4800
6791 10:53:41.494331 # ok 899 # SKIP Disabled ZA for VL 4800
6792 10:53:41.494443 # ok 900 # SKIP Get and set data for VL 4800
6793 10:53:41.494554 # ok 901 Set VL 4816
6794 10:53:41.494665 # ok 902 # SKIP Disabled ZA for VL 4816
6795 10:53:41.494775 # ok 903 # SKIP Get and set data for VL 4816
6796 10:53:41.494922 # ok 904 Set VL 4832
6797 10:53:41.495037 # ok 905 # SKIP Disabled ZA for VL 4832
6798 10:53:41.495149 # ok 906 # SKIP Get and set data for VL 4832
6799 10:53:41.495260 # ok 907 Set VL 4848
6800 10:53:41.495371 # ok 908 # SKIP Disabled ZA for VL 4848
6801 10:53:41.497941 # ok 909 # SKIP Get and set data for VL 4848
6802 10:53:41.498120 # ok 910 Set VL 4864
6803 10:53:41.498416 # ok 911 # SKIP Disabled ZA for VL 4864
6804 10:53:41.498517 # ok 912 # SKIP Get and set data for VL 4864
6805 10:53:41.498604 # ok 913 Set VL 4880
6806 10:53:41.498689 # ok 914 # SKIP Disabled ZA for VL 4880
6807 10:53:41.498792 # ok 915 # SKIP Get and set data for VL 4880
6808 10:53:41.498879 # ok 916 Set VL 4896
6809 10:53:41.498962 # ok 917 # SKIP Disabled ZA for VL 4896
6810 10:53:41.499047 # ok 918 # SKIP Get and set data for VL 4896
6811 10:53:41.499146 # ok 919 Set VL 4912
6812 10:53:41.499232 # ok 920 # SKIP Disabled ZA for VL 4912
6813 10:53:41.499318 # ok 921 # SKIP Get and set data for VL 4912
6814 10:53:41.499403 # ok 922 Set VL 4928
6815 10:53:41.499506 # ok 923 # SKIP Disabled ZA for VL 4928
6816 10:53:41.499595 # ok 924 # SKIP Get and set data for VL 4928
6817 10:53:41.499681 # ok 925 Set VL 4944
6818 10:53:41.499781 # ok 926 # SKIP Disabled ZA for VL 4944
6819 10:53:41.499872 # ok 927 # SKIP Get and set data for VL 4944
6820 10:53:41.499972 # ok 928 Set VL 4960
6821 10:53:41.500073 # ok 929 # SKIP Disabled ZA for VL 4960
6822 10:53:41.500158 # ok 930 # SKIP Get and set data for VL 4960
6823 10:53:41.500256 # ok 931 Set VL 4976
6824 10:53:41.500354 # ok 932 # SKIP Disabled ZA for VL 4976
6825 10:53:41.500649 # ok 933 # SKIP Get and set data for VL 4976
6826 10:53:41.500760 # ok 934 Set VL 4992
6827 10:53:41.500851 # ok 935 # SKIP Disabled ZA for VL 4992
6828 10:53:41.500955 # ok 936 # SKIP Get and set data for VL 4992
6829 10:53:41.501039 # ok 937 Set VL 5008
6830 10:53:41.506184 # ok 938 # SKIP Disabled ZA for VL 5008
6831 10:53:41.506418 # ok 939 # SKIP Get and set data for VL 5008
6832 10:53:41.506769 # ok 940 Set VL 5024
6833 10:53:41.506936 # ok 941 # SKIP Disabled ZA for VL 5024
6834 10:53:41.507070 # ok 942 # SKIP Get and set data for VL 5024
6835 10:53:41.507200 # ok 943 Set VL 5040
6836 10:53:41.507325 # ok 944 # SKIP Disabled ZA for VL 5040
6837 10:53:41.507445 # ok 945 # SKIP Get and set data for VL 5040
6838 10:53:41.507570 # ok 946 Set VL 5056
6839 10:53:41.507734 # ok 947 # SKIP Disabled ZA for VL 5056
6840 10:53:41.507865 # ok 948 # SKIP Get and set data for VL 5056
6841 10:53:41.507989 # ok 949 Set VL 5072
6842 10:53:41.508114 # ok 950 # SKIP Disabled ZA for VL 5072
6843 10:53:41.508239 # ok 951 # SKIP Get and set data for VL 5072
6844 10:53:41.508362 # ok 952 Set VL 5088
6845 10:53:41.508484 # ok 953 # SKIP Disabled ZA for VL 5088
6846 10:53:41.508609 # ok 954 # SKIP Get and set data for VL 5088
6847 10:53:41.508756 # ok 955 Set VL 5104
6848 10:53:41.508955 # ok 956 # SKIP Disabled ZA for VL 5104
6849 10:53:41.509086 # ok 957 # SKIP Get and set data for VL 5104
6850 10:53:41.509245 # ok 958 Set VL 5120
6851 10:53:41.509374 # ok 959 # SKIP Disabled ZA for VL 5120
6852 10:53:41.509491 # ok 960 # SKIP Get and set data for VL 5120
6853 10:53:41.509605 # ok 961 Set VL 5136
6854 10:53:41.509736 # ok 962 # SKIP Disabled ZA for VL 5136
6855 10:53:41.509852 # ok 963 # SKIP Get and set data for VL 5136
6856 10:53:41.509967 # ok 964 Set VL 5152
6857 10:53:41.510084 # ok 965 # SKIP Disabled ZA for VL 5152
6858 10:53:41.510201 # ok 966 # SKIP Get and set data for VL 5152
6859 10:53:41.512905 # ok 967 Set VL 5168
6860 10:53:41.516810 # ok 968 # SKIP Disabled ZA for VL 5168
6861 10:53:41.517267 # ok 969 # SKIP Get and set data for VL 5168
6862 10:53:41.517980 # ok 970 Set VL 5184
6863 10:53:41.518093 # ok 971 # SKIP Disabled ZA for VL 5184
6864 10:53:41.518184 # ok 972 # SKIP Get and set data for VL 5184
6865 10:53:41.518287 # ok 973 Set VL 5200
6866 10:53:41.518376 # ok 974 # SKIP Disabled ZA for VL 5200
6867 10:53:41.518463 # ok 975 # SKIP Get and set data for VL 5200
6868 10:53:41.518566 # ok 976 Set VL 5216
6869 10:53:41.518654 # ok 977 # SKIP Disabled ZA for VL 5216
6870 10:53:41.518755 # ok 978 # SKIP Get and set data for VL 5216
6871 10:53:41.518843 # ok 979 Set VL 5232
6872 10:53:41.519139 # ok 980 # SKIP Disabled ZA for VL 5232
6873 10:53:41.519242 # ok 981 # SKIP Get and set data for VL 5232
6874 10:53:41.519331 # ok 982 Set VL 5248
6875 10:53:41.519416 # ok 983 # SKIP Disabled ZA for VL 5248
6876 10:53:41.519519 # ok 984 # SKIP Get and set data for VL 5248
6877 10:53:41.519607 # ok 985 Set VL 5264
6878 10:53:41.519693 # ok 986 # SKIP Disabled ZA for VL 5264
6879 10:53:41.519794 # ok 987 # SKIP Get and set data for VL 5264
6880 10:53:41.519882 # ok 988 Set VL 5280
6881 10:53:41.519967 # ok 989 # SKIP Disabled ZA for VL 5280
6882 10:53:41.520068 # ok 990 # SKIP Get and set data for VL 5280
6883 10:53:41.520156 # ok 991 Set VL 5296
6884 10:53:41.520256 # ok 992 # SKIP Disabled ZA for VL 5296
6885 10:53:41.520343 # ok 993 # SKIP Get and set data for VL 5296
6886 10:53:41.520423 # ok 994 Set VL 5312
6887 10:53:41.520524 # ok 995 # SKIP Disabled ZA for VL 5312
6888 10:53:41.520627 # ok 996 # SKIP Get and set data for VL 5312
6889 10:53:41.520715 # ok 997 Set VL 5328
6890 10:53:41.520812 # ok 998 # SKIP Disabled ZA for VL 5328
6891 10:53:41.524306 # ok 999 # SKIP Get and set data for VL 5328
6892 10:53:41.524755 # ok 1000 Set VL 5344
6893 10:53:41.524851 # ok 1001 # SKIP Disabled ZA for VL 5344
6894 10:53:41.524930 # ok 1002 # SKIP Get and set data for VL 5344
6895 10:53:41.525004 # ok 1003 Set VL 5360
6896 10:53:41.525094 # ok 1004 # SKIP Disabled ZA for VL 5360
6897 10:53:41.525174 # ok 1005 # SKIP Get and set data for VL 5360
6898 10:53:41.526159 # ok 1006 Set VL 5376
6899 10:53:41.526269 # ok 1007 # SKIP Disabled ZA for VL 5376
6900 10:53:41.526552 # ok 1008 # SKIP Get and set data for VL 5376
6901 10:53:41.526651 # ok 1009 Set VL 5392
6902 10:53:41.526734 # ok 1010 # SKIP Disabled ZA for VL 5392
6903 10:53:41.526833 # ok 1011 # SKIP Get and set data for VL 5392
6904 10:53:41.526919 # ok 1012 Set VL 5408
6905 10:53:41.527002 # ok 1013 # SKIP Disabled ZA for VL 5408
6906 10:53:41.527084 # ok 1014 # SKIP Get and set data for VL 5408
6907 10:53:41.527165 # ok 1015 Set VL 5424
6908 10:53:41.527266 # ok 1016 # SKIP Disabled ZA for VL 5424
6909 10:53:41.527351 # ok 1017 # SKIP Get and set data for VL 5424
6910 10:53:41.527430 # ok 1018 Set VL 5440
6911 10:53:41.527510 # ok 1019 # SKIP Disabled ZA for VL 5440
6912 10:53:41.527592 # ok 1020 # SKIP Get and set data for VL 5440
6913 10:53:41.527677 # ok 1021 Set VL 5456
6914 10:53:41.527774 # ok 1022 # SKIP Disabled ZA for VL 5456
6915 10:53:41.527860 # ok 1023 # SKIP Get and set data for VL 5456
6916 10:53:41.527945 # ok 1024 Set VL 5472
6917 10:53:41.528029 # ok 1025 # SKIP Disabled ZA for VL 5472
6918 10:53:41.528114 # ok 1026 # SKIP Get and set data for VL 5472
6919 10:53:41.528199 # ok 1027 Set VL 5488
6920 10:53:41.528283 # ok 1028 # SKIP Disabled ZA for VL 5488
6921 10:53:41.528382 # ok 1029 # SKIP Get and set data for VL 5488
6922 10:53:41.528467 # ok 1030 Set VL 5504
6923 10:53:41.528550 # ok 1031 # SKIP Disabled ZA for VL 5504
6924 10:53:41.528634 # ok 1032 # SKIP Get and set data for VL 5504
6925 10:53:41.528716 # ok 1033 Set VL 5520
6926 10:53:41.528797 # ok 1034 # SKIP Disabled ZA for VL 5520
6927 10:53:41.528896 # ok 1035 # SKIP Get and set data for VL 5520
6928 10:53:41.528980 # ok 1036 Set VL 5536
6929 10:53:41.529068 # ok 1037 # SKIP Disabled ZA for VL 5536
6930 10:53:41.529155 # ok 1038 # SKIP Get and set data for VL 5536
6931 10:53:41.529239 # ok 1039 Set VL 5552
6932 10:53:41.529321 # ok 1040 # SKIP Disabled ZA for VL 5552
6933 10:53:41.529400 # ok 1041 # SKIP Get and set data for VL 5552
6934 10:53:41.529484 # ok 1042 Set VL 5568
6935 10:53:41.529567 # ok 1043 # SKIP Disabled ZA for VL 5568
6936 10:53:41.529661 # ok 1044 # SKIP Get and set data for VL 5568
6937 10:53:41.533548 # ok 1045 Set VL 5584
6938 10:53:41.533970 # ok 1046 # SKIP Disabled ZA for VL 5584
6939 10:53:41.534077 # ok 1047 # SKIP Get and set data for VL 5584
6940 10:53:41.534171 # ok 1048 Set VL 5600
6941 10:53:41.534254 # ok 1049 # SKIP Disabled ZA for VL 5600
6942 10:53:41.534350 # ok 1050 # SKIP Get and set data for VL 5600
6943 10:53:41.534438 # ok 1051 Set VL 5616
6944 10:53:41.534522 # ok 1052 # SKIP Disabled ZA for VL 5616
6945 10:53:41.535461 # ok 1053 # SKIP Get and set data for VL 5616
6946 10:53:41.535570 # ok 1054 Set VL 5632
6947 10:53:41.535673 # ok 1055 # SKIP Disabled ZA for VL 5632
6948 10:53:41.535777 # ok 1056 # SKIP Get and set data for VL 5632
6949 10:53:41.535864 # ok 1057 Set VL 5648
6950 10:53:41.535948 # ok 1058 # SKIP Disabled ZA for VL 5648
6951 10:53:41.536044 # ok 1059 # SKIP Get and set data for VL 5648
6952 10:53:41.536130 # ok 1060 Set VL 5664
6953 10:53:41.536268 # ok 1061 # SKIP Disabled ZA for VL 5664
6954 10:53:41.536358 # ok 1062 # SKIP Get and set data for VL 5664
6955 10:53:41.536442 # ok 1063 Set VL 5680
6956 10:53:41.536521 # ok 1064 # SKIP Disabled ZA for VL 5680
6957 10:53:41.536620 # ok 1065 # SKIP Get and set data for VL 5680
6958 10:53:41.536705 # ok 1066 Set VL 5696
6959 10:53:41.536784 # ok 1067 # SKIP Disabled ZA for VL 5696
6960 10:53:41.536879 # ok 1068 # SKIP Get and set data for VL 5696
6961 10:53:41.536967 # ok 1069 Set VL 5712
6962 10:53:41.537049 # ok 1070 # SKIP Disabled ZA for VL 5712
6963 10:53:41.544249 # ok 1071 # SKIP Get and set data for VL 5712
6964 10:53:41.544464 # ok 1072 Set VL 5728
6965 10:53:41.544571 # ok 1073 # SKIP Disabled ZA for VL 5728
6966 10:53:41.544663 # ok 1074 # SKIP Get and set data for VL 5728
6967 10:53:41.544748 # ok 1075 Set VL 5744
6968 10:53:41.544833 # ok 1076 # SKIP Disabled ZA for VL 5744
6969 10:53:41.544949 # ok 1077 # SKIP Get and set data for VL 5744
6970 10:53:41.545035 # ok 1078 Set VL 5760
6971 10:53:41.545115 # ok 1079 # SKIP Disabled ZA for VL 5760
6972 10:53:41.548946 # ok 1080 # SKIP Get and set data for VL 5760
6973 10:53:41.549554 # ok 1081 Set VL 5776
6974 10:53:41.549667 # ok 1082 # SKIP Disabled ZA for VL 5776
6975 10:53:41.549774 # ok 1083 # SKIP Get and set data for VL 5776
6976 10:53:41.549861 # ok 1084 Set VL 5792
6977 10:53:41.549962 # ok 1085 # SKIP Disabled ZA for VL 5792
6978 10:53:41.550066 # ok 1086 # SKIP Get and set data for VL 5792
6979 10:53:41.550154 # ok 1087 Set VL 5808
6980 10:53:41.550253 # ok 1088 # SKIP Disabled ZA for VL 5808
6981 10:53:41.550356 # ok 1089 # SKIP Get and set data for VL 5808
6982 10:53:41.550458 # ok 1090 Set VL 5824
6983 10:53:41.550559 # ok 1091 # SKIP Disabled ZA for VL 5824
6984 10:53:41.551335 # ok 1092 # SKIP Get and set data for VL 5824
6985 10:53:41.551528 # ok 1093 Set VL 5840
6986 10:53:41.551691 # ok 1094 # SKIP Disabled ZA for VL 5840
6987 10:53:41.551839 # ok 1095 # SKIP Get and set data for VL 5840
6988 10:53:41.551996 # ok 1096 Set VL 5856
6989 10:53:41.552152 # ok 1097 # SKIP Disabled ZA for VL 5856
6990 10:53:41.552320 # ok 1098 # SKIP Get and set data for VL 5856
6991 10:53:41.552479 # ok 1099 Set VL 5872
6992 10:53:41.552788 # ok 1100 # SKIP Disabled ZA for VL 5872
6993 10:53:41.552889 # ok 1101 # SKIP Get and set data for VL 5872
6994 10:53:41.552976 # ok 1102 Set VL 5888
6995 10:53:41.553057 # ok 1103 # SKIP Disabled ZA for VL 5888
6996 10:53:41.553142 # ok 1104 # SKIP Get and set data for VL 5888
6997 10:53:41.553222 # ok 1105 Set VL 5904
6998 10:53:41.553306 # ok 1106 # SKIP Disabled ZA for VL 5904
6999 10:53:41.553389 # ok 1107 # SKIP Get and set data for VL 5904
7000 10:53:41.553473 # ok 1108 Set VL 5920
7001 10:53:41.553557 # ok 1109 # SKIP Disabled ZA for VL 5920
7002 10:53:41.553639 # ok 1110 # SKIP Get and set data for VL 5920
7003 10:53:41.553732 # ok 1111 Set VL 5936
7004 10:53:41.553812 # ok 1112 # SKIP Disabled ZA for VL 5936
7005 10:53:41.553894 # ok 1113 # SKIP Get and set data for VL 5936
7006 10:53:41.553978 # ok 1114 Set VL 5952
7007 10:53:41.554059 # ok 1115 # SKIP Disabled ZA for VL 5952
7008 10:53:41.554136 # ok 1116 # SKIP Get and set data for VL 5952
7009 10:53:41.554216 # ok 1117 Set VL 5968
7010 10:53:41.554299 # ok 1118 # SKIP Disabled ZA for VL 5968
7011 10:53:41.554382 # ok 1119 # SKIP Get and set data for VL 5968
7012 10:53:41.554462 # ok 1120 Set VL 5984
7013 10:53:41.554541 # ok 1121 # SKIP Disabled ZA for VL 5984
7014 10:53:41.563225 # ok 1122 # SKIP Get and set data for VL 5984
7015 10:53:41.563707 # ok 1123 Set VL 6000
7016 10:53:41.563813 # ok 1124 # SKIP Disabled ZA for VL 6000
7017 10:53:41.563899 # ok 1125 # SKIP Get and set data for VL 6000
7018 10:53:41.563983 # ok 1126 Set VL 6016
7019 10:53:41.564064 # ok 1127 # SKIP Disabled ZA for VL 6016
7020 10:53:41.564161 # ok 1128 # SKIP Get and set data for VL 6016
7021 10:53:41.564929 # ok 1129 Set VL 6032
7022 10:53:41.565031 # ok 1130 # SKIP Disabled ZA for VL 6032
7023 10:53:41.565120 # ok 1131 # SKIP Get and set data for VL 6032
7024 10:53:41.565203 # ok 1132 Set VL 6048
7025 10:53:41.565287 # ok 1133 # SKIP Disabled ZA for VL 6048
7026 10:53:41.565372 # ok 1134 # SKIP Get and set data for VL 6048
7027 10:53:41.565457 # ok 1135 Set VL 6064
7028 10:53:41.565539 # ok 1136 # SKIP Disabled ZA for VL 6064
7029 10:53:41.565621 # ok 1137 # SKIP Get and set data for VL 6064
7030 10:53:41.565715 # ok 1138 Set VL 6080
7031 10:53:41.565799 # ok 1139 # SKIP Disabled ZA for VL 6080
7032 10:53:41.570216 # ok 1140 # SKIP Get and set data for VL 6080
7033 10:53:41.570437 # ok 1141 Set VL 6096
7034 10:53:41.570760 # ok 1142 # SKIP Disabled ZA for VL 6096
7035 10:53:41.570914 # ok 1143 # SKIP Get and set data for VL 6096
7036 10:53:41.571047 # ok 1144 Set VL 6112
7037 10:53:41.571274 # ok 1145 # SKIP Disabled ZA for VL 6112
7038 10:53:41.571465 # ok 1146 # SKIP Get and set data for VL 6112
7039 10:53:41.571674 # ok 1147 Set VL 6128
7040 10:53:41.571819 # ok 1148 # SKIP Disabled ZA for VL 6128
7041 10:53:41.572049 # ok 1149 # SKIP Get and set data for VL 6128
7042 10:53:41.572193 # ok 1150 Set VL 6144
7043 10:53:41.572372 # ok 1151 # SKIP Disabled ZA for VL 6144
7044 10:53:41.572507 # ok 1152 # SKIP Get and set data for VL 6144
7045 10:53:41.572650 # ok 1153 Set VL 6160
7046 10:53:41.572752 # ok 1154 # SKIP Disabled ZA for VL 6160
7047 10:53:41.572839 # ok 1155 # SKIP Get and set data for VL 6160
7048 10:53:41.572919 # ok 1156 Set VL 6176
7049 10:53:41.573018 # ok 1157 # SKIP Disabled ZA for VL 6176
7050 10:53:41.573104 # ok 1158 # SKIP Get and set data for VL 6176
7051 10:53:41.573188 # ok 1159 Set VL 6192
7052 10:53:41.573268 # ok 1160 # SKIP Disabled ZA for VL 6192
7053 10:53:41.573348 # ok 1161 # SKIP Get and set data for VL 6192
7054 10:53:41.573433 # ok 1162 Set VL 6208
7055 10:53:41.573516 # ok 1163 # SKIP Disabled ZA for VL 6208
7056 10:53:41.573600 # ok 1164 # SKIP Get and set data for VL 6208
7057 10:53:41.573697 # ok 1165 Set VL 6224
7058 10:53:41.573783 # ok 1166 # SKIP Disabled ZA for VL 6224
7059 10:53:41.573864 # ok 1167 # SKIP Get and set data for VL 6224
7060 10:53:41.573945 # ok 1168 Set VL 6240
7061 10:53:41.581727 # ok 1169 # SKIP Disabled ZA for VL 6240
7062 10:53:41.582237 # ok 1170 # SKIP Get and set data for VL 6240
7063 10:53:41.582407 # ok 1171 Set VL 6256
7064 10:53:41.582535 # ok 1172 # SKIP Disabled ZA for VL 6256
7065 10:53:41.582657 # ok 1173 # SKIP Get and set data for VL 6256
7066 10:53:41.582776 # ok 1174 Set VL 6272
7067 10:53:41.582934 # ok 1175 # SKIP Disabled ZA for VL 6272
7068 10:53:41.583109 # ok 1176 # SKIP Get and set data for VL 6272
7069 10:53:41.583282 # ok 1177 Set VL 6288
7070 10:53:41.583455 # ok 1178 # SKIP Disabled ZA for VL 6288
7071 10:53:41.583638 # ok 1179 # SKIP Get and set data for VL 6288
7072 10:53:41.583787 # ok 1180 Set VL 6304
7073 10:53:41.583929 # ok 1181 # SKIP Disabled ZA for VL 6304
7074 10:53:41.584113 # ok 1182 # SKIP Get and set data for VL 6304
7075 10:53:41.584253 # ok 1183 Set VL 6320
7076 10:53:41.584396 # ok 1184 # SKIP Disabled ZA for VL 6320
7077 10:53:41.584540 # ok 1185 # SKIP Get and set data for VL 6320
7078 10:53:41.584682 # ok 1186 Set VL 6336
7079 10:53:41.584865 # ok 1187 # SKIP Disabled ZA for VL 6336
7080 10:53:41.585039 # ok 1188 # SKIP Get and set data for VL 6336
7081 10:53:41.585221 # ok 1189 Set VL 6352
7082 10:53:41.585395 # ok 1190 # SKIP Disabled ZA for VL 6352
7083 10:53:41.585542 # ok 1191 # SKIP Get and set data for VL 6352
7084 10:53:41.585699 # ok 1192 Set VL 6368
7085 10:53:41.585844 # ok 1193 # SKIP Disabled ZA for VL 6368
7086 10:53:41.585986 # ok 1194 # SKIP Get and set data for VL 6368
7087 10:53:41.586129 # ok 1195 Set VL 6384
7088 10:53:41.586273 # ok 1196 # SKIP Disabled ZA for VL 6384
7089 10:53:41.586458 # ok 1197 # SKIP Get and set data for VL 6384
7090 10:53:41.586595 # ok 1198 Set VL 6400
7091 10:53:41.586738 # ok 1199 # SKIP Disabled ZA for VL 6400
7092 10:53:41.586883 # ok 1200 # SKIP Get and set data for VL 6400
7093 10:53:41.587027 # ok 1201 Set VL 6416
7094 10:53:41.587168 # ok 1202 # SKIP Disabled ZA for VL 6416
7095 10:53:41.587311 # ok 1203 # SKIP Get and set data for VL 6416
7096 10:53:41.587452 # ok 1204 Set VL 6432
7097 10:53:41.594062 # ok 1205 # SKIP Disabled ZA for VL 6432
7098 10:53:41.594395 # ok 1206 # SKIP Get and set data for VL 6432
7099 10:53:41.594910 # ok 1207 Set VL 6448
7100 10:53:41.595107 # ok 1208 # SKIP Disabled ZA for VL 6448
7101 10:53:41.595252 # ok 1209 # SKIP Get and set data for VL 6448
7102 10:53:41.595402 # ok 1210 Set VL 6464
7103 10:53:41.595561 # ok 1211 # SKIP Disabled ZA for VL 6464
7104 10:53:41.595737 # ok 1212 # SKIP Get and set data for VL 6464
7105 10:53:41.595885 # ok 1213 Set VL 6480
7106 10:53:41.596114 # ok 1214 # SKIP Disabled ZA for VL 6480
7107 10:53:41.596335 # ok 1215 # SKIP Get and set data for VL 6480
7108 10:53:41.596496 # ok 1216 Set VL 6496
7109 10:53:41.596664 # ok 1217 # SKIP Disabled ZA for VL 6496
7110 10:53:41.596838 # ok 1218 # SKIP Get and set data for VL 6496
7111 10:53:41.596974 # ok 1219 Set VL 6512
7112 10:53:41.597091 # ok 1220 # SKIP Disabled ZA for VL 6512
7113 10:53:41.597219 # ok 1221 # SKIP Get and set data for VL 6512
7114 10:53:41.597338 # ok 1222 Set VL 6528
7115 10:53:41.597453 # ok 1223 # SKIP Disabled ZA for VL 6528
7116 10:53:41.597569 # ok 1224 # SKIP Get and set data for VL 6528
7117 10:53:41.597702 # ok 1225 Set VL 6544
7118 10:53:41.597817 # ok 1226 # SKIP Disabled ZA for VL 6544
7119 10:53:41.597943 # ok 1227 # SKIP Get and set data for VL 6544
7120 10:53:41.598121 # ok 1228 Set VL 6560
7121 10:53:41.598309 # ok 1229 # SKIP Disabled ZA for VL 6560
7122 10:53:41.598446 # ok 1230 # SKIP Get and set data for VL 6560
7123 10:53:41.598590 # ok 1231 Set VL 6576
7124 10:53:41.598732 # ok 1232 # SKIP Disabled ZA for VL 6576
7125 10:53:41.598875 # ok 1233 # SKIP Get and set data for VL 6576
7126 10:53:41.605916 # ok 1234 Set VL 6592
7127 10:53:41.606516 # ok 1235 # SKIP Disabled ZA for VL 6592
7128 10:53:41.606633 # ok 1236 # SKIP Get and set data for VL 6592
7129 10:53:41.606722 # ok 1237 Set VL 6608
7130 10:53:41.606808 # ok 1238 # SKIP Disabled ZA for VL 6608
7131 10:53:41.606912 # ok 1239 # SKIP Get and set data for VL 6608
7132 10:53:41.607003 # ok 1240 Set VL 6624
7133 10:53:41.607089 # ok 1241 # SKIP Disabled ZA for VL 6624
7134 10:53:41.607171 # ok 1242 # SKIP Get and set data for VL 6624
7135 10:53:41.607267 # ok 1243 Set VL 6640
7136 10:53:41.607356 # ok 1244 # SKIP Disabled ZA for VL 6640
7137 10:53:41.607456 # ok 1245 # SKIP Get and set data for VL 6640
7138 10:53:41.607544 # ok 1246 Set VL 6656
7139 10:53:41.607646 # ok 1247 # SKIP Disabled ZA for VL 6656
7140 10:53:41.607734 # ok 1248 # SKIP Get and set data for VL 6656
7141 10:53:41.607832 # ok 1249 Set VL 6672
7142 10:53:41.607918 # ok 1250 # SKIP Disabled ZA for VL 6672
7143 10:53:41.608015 # ok 1251 # SKIP Get and set data for VL 6672
7144 10:53:41.608112 # ok 1252 Set VL 6688
7145 10:53:41.608211 # ok 1253 # SKIP Disabled ZA for VL 6688
7146 10:53:41.608317 # ok 1254 # SKIP Get and set data for VL 6688
7147 10:53:41.608405 # ok 1255 Set VL 6704
7148 10:53:41.608505 # ok 1256 # SKIP Disabled ZA for VL 6704
7149 10:53:41.608602 # ok 1257 # SKIP Get and set data for VL 6704
7150 10:53:41.608932 # ok 1258 Set VL 6720
7151 10:53:41.609091 # ok 1259 # SKIP Disabled ZA for VL 6720
7152 10:53:41.613973 # ok 1260 # SKIP Get and set data for VL 6720
7153 10:53:41.614758 # ok 1261 Set VL 6736
7154 10:53:41.614968 # ok 1262 # SKIP Disabled ZA for VL 6736
7155 10:53:41.615221 # ok 1263 # SKIP Get and set data for VL 6736
7156 10:53:41.615412 # ok 1264 Set VL 6752
7157 10:53:41.615561 # ok 1265 # SKIP Disabled ZA for VL 6752
7158 10:53:41.615705 # ok 1266 # SKIP Get and set data for VL 6752
7159 10:53:41.615849 # ok 1267 Set VL 6768
7160 10:53:41.615991 # ok 1268 # SKIP Disabled ZA for VL 6768
7161 10:53:41.616170 # ok 1269 # SKIP Get and set data for VL 6768
7162 10:53:41.616308 # ok 1270 Set VL 6784
7163 10:53:41.616449 # ok 1271 # SKIP Disabled ZA for VL 6784
7164 10:53:41.616591 # ok 1272 # SKIP Get and set data for VL 6784
7165 10:53:41.616760 # ok 1273 Set VL 6800
7166 10:53:41.616967 # ok 1274 # SKIP Disabled ZA for VL 6800
7167 10:53:41.617119 # ok 1275 # SKIP Get and set data for VL 6800
7168 10:53:41.617300 # ok 1276 Set VL 6816
7169 10:53:41.617473 # ok 1277 # SKIP Disabled ZA for VL 6816
7170 10:53:41.617774 # ok 1278 # SKIP Get and set data for VL 6816
7171 10:53:41.617944 # ok 1279 Set VL 6832
7172 10:53:41.618096 # ok 1280 # SKIP Disabled ZA for VL 6832
7173 10:53:41.621928 # ok 1281 # SKIP Get and set data for VL 6832
7174 10:53:41.622517 # ok 1282 Set VL 6848
7175 10:53:41.622746 # ok 1283 # SKIP Disabled ZA for VL 6848
7176 10:53:41.622959 # ok 1284 # SKIP Get and set data for VL 6848
7177 10:53:41.623163 # ok 1285 Set VL 6864
7178 10:53:41.623362 # ok 1286 # SKIP Disabled ZA for VL 6864
7179 10:53:41.623600 # ok 1287 # SKIP Get and set data for VL 6864
7180 10:53:41.623797 # ok 1288 Set VL 6880
7181 10:53:41.623998 # ok 1289 # SKIP Disabled ZA for VL 6880
7182 10:53:41.624226 # ok 1290 # SKIP Get and set data for VL 6880
7183 10:53:41.624422 # ok 1291 Set VL 6896
7184 10:53:41.624591 # ok 1292 # SKIP Disabled ZA for VL 6896
7185 10:53:41.624750 # ok 1293 # SKIP Get and set data for VL 6896
7186 10:53:41.624934 # ok 1294 Set VL 6912
7187 10:53:41.625077 # ok 1295 # SKIP Disabled ZA for VL 6912
7188 10:53:41.625235 # ok 1296 # SKIP Get and set data for VL 6912
7189 10:53:41.625368 # ok 1297 Set VL 6928
7190 10:53:41.625484 # ok 1298 # SKIP Disabled ZA for VL 6928
7191 10:53:41.625631 # ok 1299 # SKIP Get and set data for VL 6928
7192 10:53:41.625846 # ok 1300 Set VL 6944
7193 10:53:41.626038 # ok 1301 # SKIP Disabled ZA for VL 6944
7194 10:53:41.626223 # ok 1302 # SKIP Get and set data for VL 6944
7195 10:53:41.626409 # ok 1303 Set VL 6960
7196 10:53:41.626554 # ok 1304 # SKIP Disabled ZA for VL 6960
7197 10:53:41.626695 # ok 1305 # SKIP Get and set data for VL 6960
7198 10:53:41.626870 # ok 1306 Set VL 6976
7199 10:53:41.627043 # ok 1307 # SKIP Disabled ZA for VL 6976
7200 10:53:41.627189 # ok 1308 # SKIP Get and set data for VL 6976
7201 10:53:41.627331 # ok 1309 Set VL 6992
7202 10:53:41.627473 # ok 1310 # SKIP Disabled ZA for VL 6992
7203 10:53:41.627614 # ok 1311 # SKIP Get and set data for VL 6992
7204 10:53:41.644463 # ok 1312 Set VL 7008
7205 10:53:41.645046 # ok 1313 # SKIP Disabled ZA for VL 7008
7206 10:53:41.645212 # ok 1314 # SKIP Get and set data for VL 7008
7207 10:53:41.645343 # ok 1315 Set VL 7024
7208 10:53:41.645522 # ok 1316 # SKIP Disabled ZA for VL 7024
7209 10:53:41.645759 # ok 1317 # SKIP Get and set data for VL 7024
7210 10:53:41.645994 # ok 1318 Set VL 7040
7211 10:53:41.646252 # ok 1319 # SKIP Disabled ZA for VL 7040
7212 10:53:41.646479 # ok 1320 # SKIP Get and set data for VL 7040
7213 10:53:41.646692 # ok 1321 Set VL 7056
7214 10:53:41.646911 # ok 1322 # SKIP Disabled ZA for VL 7056
7215 10:53:41.647154 # ok 1323 # SKIP Get and set data for VL 7056
7216 10:53:41.647372 # ok 1324 Set VL 7072
7217 10:53:41.647593 # ok 1325 # SKIP Disabled ZA for VL 7072
7218 10:53:41.647816 # ok 1326 # SKIP Get and set data for VL 7072
7219 10:53:41.648031 # ok 1327 Set VL 7088
7220 10:53:41.648236 # ok 1328 # SKIP Disabled ZA for VL 7088
7221 10:53:41.648447 # ok 1329 # SKIP Get and set data for VL 7088
7222 10:53:41.648658 # ok 1330 Set VL 7104
7223 10:53:41.648933 # ok 1331 # SKIP Disabled ZA for VL 7104
7224 10:53:41.649136 # ok 1332 # SKIP Get and set data for VL 7104
7225 10:53:41.649322 # ok 1333 Set VL 7120
7226 10:53:41.649493 # ok 1334 # SKIP Disabled ZA for VL 7120
7227 10:53:41.649670 # ok 1335 # SKIP Get and set data for VL 7120
7228 10:53:41.649839 # ok 1336 Set VL 7136
7229 10:53:41.650004 # ok 1337 # SKIP Disabled ZA for VL 7136
7230 10:53:41.650185 # ok 1338 # SKIP Get and set data for VL 7136
7231 10:53:41.650373 # ok 1339 Set VL 7152
7232 10:53:41.650540 # ok 1340 # SKIP Disabled ZA for VL 7152
7233 10:53:41.650712 # ok 1341 # SKIP Get and set data for VL 7152
7234 10:53:41.650913 # ok 1342 Set VL 7168
7235 10:53:41.651085 # ok 1343 # SKIP Disabled ZA for VL 7168
7236 10:53:41.651245 # ok 1344 # SKIP Get and set data for VL 7168
7237 10:53:41.651403 # ok 1345 Set VL 7184
7238 10:53:41.651580 # ok 1346 # SKIP Disabled ZA for VL 7184
7239 10:53:41.651763 # ok 1347 # SKIP Get and set data for VL 7184
7240 10:53:41.651951 # ok 1348 Set VL 7200
7241 10:53:41.652147 # ok 1349 # SKIP Disabled ZA for VL 7200
7242 10:53:41.652356 # ok 1350 # SKIP Get and set data for VL 7200
7243 10:53:41.652535 # ok 1351 Set VL 7216
7244 10:53:41.652742 # ok 1352 # SKIP Disabled ZA for VL 7216
7245 10:53:41.652955 # ok 1353 # SKIP Get and set data for VL 7216
7246 10:53:41.653161 # ok 1354 Set VL 7232
7247 10:53:41.653356 # ok 1355 # SKIP Disabled ZA for VL 7232
7248 10:53:41.653553 # ok 1356 # SKIP Get and set data for VL 7232
7249 10:53:41.653830 # ok 1357 Set VL 7248
7250 10:53:41.654048 # ok 1358 # SKIP Disabled ZA for VL 7248
7251 10:53:41.654264 # ok 1359 # SKIP Get and set data for VL 7248
7252 10:53:41.654442 # ok 1360 Set VL 7264
7253 10:53:41.654603 # ok 1361 # SKIP Disabled ZA for VL 7264
7254 10:53:41.654805 # ok 1362 # SKIP Get and set data for VL 7264
7255 10:53:41.655000 # ok 1363 Set VL 7280
7256 10:53:41.655168 # ok 1364 # SKIP Disabled ZA for VL 7280
7257 10:53:41.655549 # ok 1365 # SKIP Get and set data for VL 7280
7258 10:53:41.655656 # ok 1366 Set VL 7296
7259 10:53:41.655746 # ok 1367 # SKIP Disabled ZA for VL 7296
7260 10:53:41.655829 # ok 1368 # SKIP Get and set data for VL 7296
7261 10:53:41.655915 # ok 1369 Set VL 7312
7262 10:53:41.655997 # ok 1370 # SKIP Disabled ZA for VL 7312
7263 10:53:41.656079 # ok 1371 # SKIP Get and set data for VL 7312
7264 10:53:41.656162 # ok 1372 Set VL 7328
7265 10:53:41.656423 # ok 1373 # SKIP Disabled ZA for VL 7328
7266 10:53:41.656515 # ok 1374 # SKIP Get and set data for VL 7328
7267 10:53:41.656630 # ok 1375 Set VL 7344
7268 10:53:41.656732 # ok 1376 # SKIP Disabled ZA for VL 7344
7269 10:53:41.656820 # ok 1377 # SKIP Get and set data for VL 7344
7270 10:53:41.656904 # ok 1378 Set VL 7360
7271 10:53:41.656989 # ok 1379 # SKIP Disabled ZA for VL 7360
7272 10:53:41.657073 # ok 1380 # SKIP Get and set data for VL 7360
7273 10:53:41.657156 # ok 1381 Set VL 7376
7274 10:53:41.657240 # ok 1382 # SKIP Disabled ZA for VL 7376
7275 10:53:41.657323 # ok 1383 # SKIP Get and set data for VL 7376
7276 10:53:41.657407 # ok 1384 Set VL 7392
7277 10:53:41.657490 # ok 1385 # SKIP Disabled ZA for VL 7392
7278 10:53:41.657573 # ok 1386 # SKIP Get and set data for VL 7392
7279 10:53:41.657664 # ok 1387 Set VL 7408
7280 10:53:41.657750 # ok 1388 # SKIP Disabled ZA for VL 7408
7281 10:53:41.657832 # ok 1389 # SKIP Get and set data for VL 7408
7282 10:53:41.657914 # ok 1390 Set VL 7424
7283 10:53:41.657996 # ok 1391 # SKIP Disabled ZA for VL 7424
7284 10:53:41.658078 # ok 1392 # SKIP Get and set data for VL 7424
7285 10:53:41.658161 # ok 1393 Set VL 7440
7286 10:53:41.658243 # ok 1394 # SKIP Disabled ZA for VL 7440
7287 10:53:41.658324 # ok 1395 # SKIP Get and set data for VL 7440
7288 10:53:41.658407 # ok 1396 Set VL 7456
7289 10:53:41.658488 # ok 1397 # SKIP Disabled ZA for VL 7456
7290 10:53:41.658571 # ok 1398 # SKIP Get and set data for VL 7456
7291 10:53:41.658650 # ok 1399 Set VL 7472
7292 10:53:41.658732 # ok 1400 # SKIP Disabled ZA for VL 7472
7293 10:53:41.658813 # ok 1401 # SKIP Get and set data for VL 7472
7294 10:53:41.658896 # ok 1402 Set VL 7488
7295 10:53:41.658979 # ok 1403 # SKIP Disabled ZA for VL 7488
7296 10:53:41.659061 # ok 1404 # SKIP Get and set data for VL 7488
7297 10:53:41.659144 # ok 1405 Set VL 7504
7298 10:53:41.659229 # ok 1406 # SKIP Disabled ZA for VL 7504
7299 10:53:41.659317 # ok 1407 # SKIP Get and set data for VL 7504
7300 10:53:41.659402 # ok 1408 Set VL 7520
7301 10:53:41.659484 # ok 1409 # SKIP Disabled ZA for VL 7520
7302 10:53:41.659567 # ok 1410 # SKIP Get and set data for VL 7520
7303 10:53:41.659651 # ok 1411 Set VL 7536
7304 10:53:41.659733 # ok 1412 # SKIP Disabled ZA for VL 7536
7305 10:53:41.659816 # ok 1413 # SKIP Get and set data for VL 7536
7306 10:53:41.659897 # ok 1414 Set VL 7552
7307 10:53:41.659982 # ok 1415 # SKIP Disabled ZA for VL 7552
7308 10:53:41.660069 # ok 1416 # SKIP Get and set data for VL 7552
7309 10:53:41.660152 # ok 1417 Set VL 7568
7310 10:53:41.660456 # ok 1418 # SKIP Disabled ZA for VL 7568
7311 10:53:41.660563 # ok 1419 # SKIP Get and set data for VL 7568
7312 10:53:41.660653 # ok 1420 Set VL 7584
7313 10:53:41.660738 # ok 1421 # SKIP Disabled ZA for VL 7584
7314 10:53:41.660830 # ok 1422 # SKIP Get and set data for VL 7584
7315 10:53:41.660918 # ok 1423 Set VL 7600
7316 10:53:41.661001 # ok 1424 # SKIP Disabled ZA for VL 7600
7317 10:53:41.661086 # ok 1425 # SKIP Get and set data for VL 7600
7318 10:53:41.661169 # ok 1426 Set VL 7616
7319 10:53:41.661248 # ok 1427 # SKIP Disabled ZA for VL 7616
7320 10:53:41.661333 # ok 1428 # SKIP Get and set data for VL 7616
7321 10:53:41.661418 # ok 1429 Set VL 7632
7322 10:53:41.661504 # ok 1430 # SKIP Disabled ZA for VL 7632
7323 10:53:41.661588 # ok 1431 # SKIP Get and set data for VL 7632
7324 10:53:41.661683 # ok 1432 Set VL 7648
7325 10:53:41.661765 # ok 1433 # SKIP Disabled ZA for VL 7648
7326 10:53:41.661849 # ok 1434 # SKIP Get and set data for VL 7648
7327 10:53:41.661937 # ok 1435 Set VL 7664
7328 10:53:41.662024 # ok 1436 # SKIP Disabled ZA for VL 7664
7329 10:53:41.662113 # ok 1437 # SKIP Get and set data for VL 7664
7330 10:53:41.662200 # ok 1438 Set VL 7680
7331 10:53:41.662281 # ok 1439 # SKIP Disabled ZA for VL 7680
7332 10:53:41.662369 # ok 1440 # SKIP Get and set data for VL 7680
7333 10:53:41.662456 # ok 1441 Set VL 7696
7334 10:53:41.662541 # ok 1442 # SKIP Disabled ZA for VL 7696
7335 10:53:41.662626 # ok 1443 # SKIP Get and set data for VL 7696
7336 10:53:41.662713 # ok 1444 Set VL 7712
7337 10:53:41.662799 # ok 1445 # SKIP Disabled ZA for VL 7712
7338 10:53:41.662882 # ok 1446 # SKIP Get and set data for VL 7712
7339 10:53:41.662966 # ok 1447 Set VL 7728
7340 10:53:41.663051 # ok 1448 # SKIP Disabled ZA for VL 7728
7341 10:53:41.663134 # ok 1449 # SKIP Get and set data for VL 7728
7342 10:53:41.663215 # ok 1450 Set VL 7744
7343 10:53:41.663298 # ok 1451 # SKIP Disabled ZA for VL 7744
7344 10:53:41.663386 # ok 1452 # SKIP Get and set data for VL 7744
7345 10:53:41.663472 # ok 1453 Set VL 7760
7346 10:53:41.663559 # ok 1454 # SKIP Disabled ZA for VL 7760
7347 10:53:41.663641 # ok 1455 # SKIP Get and set data for VL 7760
7348 10:53:41.663723 # ok 1456 Set VL 7776
7349 10:53:41.663810 # ok 1457 # SKIP Disabled ZA for VL 7776
7350 10:53:41.663895 # ok 1458 # SKIP Get and set data for VL 7776
7351 10:53:41.663980 # ok 1459 Set VL 7792
7352 10:53:41.664067 # ok 1460 # SKIP Disabled ZA for VL 7792
7353 10:53:41.664153 # ok 1461 # SKIP Get and set data for VL 7792
7354 10:53:41.664239 # ok 1462 Set VL 7808
7355 10:53:41.664322 # ok 1463 # SKIP Disabled ZA for VL 7808
7356 10:53:41.664407 # ok 1464 # SKIP Get and set data for VL 7808
7357 10:53:41.664492 # ok 1465 Set VL 7824
7358 10:53:41.664575 # ok 1466 # SKIP Disabled ZA for VL 7824
7359 10:53:41.664658 # ok 1467 # SKIP Get and set data for VL 7824
7360 10:53:41.664741 # ok 1468 Set VL 7840
7361 10:53:41.664822 # ok 1469 # SKIP Disabled ZA for VL 7840
7362 10:53:41.665114 # ok 1470 # SKIP Get and set data for VL 7840
7363 10:53:41.665208 # ok 1471 Set VL 7856
7364 10:53:41.665294 # ok 1472 # SKIP Disabled ZA for VL 7856
7365 10:53:41.665385 # ok 1473 # SKIP Get and set data for VL 7856
7366 10:53:41.665469 # ok 1474 Set VL 7872
7367 10:53:41.665552 # ok 1475 # SKIP Disabled ZA for VL 7872
7368 10:53:41.665635 # ok 1476 # SKIP Get and set data for VL 7872
7369 10:53:41.665732 # ok 1477 Set VL 7888
7370 10:53:41.665816 # ok 1478 # SKIP Disabled ZA for VL 7888
7371 10:53:41.665896 # ok 1479 # SKIP Get and set data for VL 7888
7372 10:53:41.665977 # ok 1480 Set VL 7904
7373 10:53:41.666061 # ok 1481 # SKIP Disabled ZA for VL 7904
7374 10:53:41.666147 # ok 1482 # SKIP Get and set data for VL 7904
7375 10:53:41.666228 # ok 1483 Set VL 7920
7376 10:53:41.667065 # ok 1484 # SKIP Disabled ZA for VL 7920
7377 10:53:41.667382 # ok 1485 # SKIP Get and set data for VL 7920
7378 10:53:41.667484 # ok 1486 Set VL 7936
7379 10:53:41.667569 # ok 1487 # SKIP Disabled ZA for VL 7936
7380 10:53:41.667671 # ok 1488 # SKIP Get and set data for VL 7936
7381 10:53:41.667758 # ok 1489 Set VL 7952
7382 10:53:41.667843 # ok 1490 # SKIP Disabled ZA for VL 7952
7383 10:53:41.667945 # ok 1491 # SKIP Get and set data for VL 7952
7384 10:53:41.668034 # ok 1492 Set VL 7968
7385 10:53:41.668130 # ok 1493 # SKIP Disabled ZA for VL 7968
7386 10:53:41.668564 # ok 1494 # SKIP Get and set data for VL 7968
7387 10:53:41.668701 # ok 1495 Set VL 7984
7388 10:53:41.668988 # ok 1496 # SKIP Disabled ZA for VL 7984
7389 10:53:41.669092 # ok 1497 # SKIP Get and set data for VL 7984
7390 10:53:41.669181 # ok 1498 Set VL 8000
7391 10:53:41.669268 # ok 1499 # SKIP Disabled ZA for VL 8000
7392 10:53:41.669352 # ok 1500 # SKIP Get and set data for VL 8000
7393 10:53:41.669436 # ok 1501 Set VL 8016
7394 10:53:41.669516 # ok 1502 # SKIP Disabled ZA for VL 8016
7395 10:53:41.670159 # ok 1503 # SKIP Get and set data for VL 8016
7396 10:53:41.670477 # ok 1504 Set VL 8032
7397 10:53:41.670580 # ok 1505 # SKIP Disabled ZA for VL 8032
7398 10:53:41.670668 # ok 1506 # SKIP Get and set data for VL 8032
7399 10:53:41.670753 # ok 1507 Set VL 8048
7400 10:53:41.670854 # ok 1508 # SKIP Disabled ZA for VL 8048
7401 10:53:41.670942 # ok 1509 # SKIP Get and set data for VL 8048
7402 10:53:41.671027 # ok 1510 Set VL 8064
7403 10:53:41.671108 # ok 1511 # SKIP Disabled ZA for VL 8064
7404 10:53:41.671201 # ok 1512 # SKIP Get and set data for VL 8064
7405 10:53:41.671283 # ok 1513 Set VL 8080
7406 10:53:41.671380 # ok 1514 # SKIP Disabled ZA for VL 8080
7407 10:53:41.671481 # ok 1515 # SKIP Get and set data for VL 8080
7408 10:53:41.671565 # ok 1516 Set VL 8096
7409 10:53:41.671661 # ok 1517 # SKIP Disabled ZA for VL 8096
7410 10:53:41.671744 # ok 1518 # SKIP Get and set data for VL 8096
7411 10:53:41.671839 # ok 1519 Set VL 8112
7412 10:53:41.671937 # ok 1520 # SKIP Disabled ZA for VL 8112
7413 10:53:41.672021 # ok 1521 # SKIP Get and set data for VL 8112
7414 10:53:41.672105 # ok 1522 Set VL 8128
7415 10:53:41.672202 # ok 1523 # SKIP Disabled ZA for VL 8128
7416 10:53:41.672284 # ok 1524 # SKIP Get and set data for VL 8128
7417 10:53:41.672362 # ok 1525 Set VL 8144
7418 10:53:41.672459 # ok 1526 # SKIP Disabled ZA for VL 8144
7419 10:53:41.672562 # ok 1527 # SKIP Get and set data for VL 8144
7420 10:53:41.672649 # ok 1528 Set VL 8160
7421 10:53:41.672749 # ok 1529 # SKIP Disabled ZA for VL 8160
7422 10:53:41.672848 # ok 1530 # SKIP Get and set data for VL 8160
7423 10:53:41.672948 # ok 1531 Set VL 8176
7424 10:53:41.683360 # ok 1532 # SKIP Disabled ZA for VL 8176
7425 10:53:41.683855 # ok 1533 # SKIP Get and set data for VL 8176
7426 10:53:41.684025 # ok 1534 Set VL 8192
7427 10:53:41.684152 # ok 1535 # SKIP Disabled ZA for VL 8192
7428 10:53:41.684271 # ok 1536 # SKIP Get and set data for VL 8192
7429 10:53:41.684389 # # Totals: pass:522 fail:0 xfail:0 xpass:0 skip:1014 error:0
7430 10:53:41.684529 ok 34 selftests: arm64: za-ptrace
7431 10:53:41.684650 # selftests: arm64: check_buffer_fill
7432 10:53:42.087185 # 1..20
7433 10:53:42.087516 # ok 1 Check buffer correctness by byte with sync err mode and mmap memory
7434 10:53:42.087989 # ok 2 Check buffer correctness by byte with async err mode and mmap memory
7435 10:53:42.088104 # ok 3 Check buffer correctness by byte with sync err mode and mmap/mprotect memory
7436 10:53:42.088201 # ok 4 Check buffer correctness by byte with async err mode and mmap/mprotect memory
7437 10:53:42.088290 # not ok 5 Check buffer write underflow by byte with sync mode and mmap memory
7438 10:53:42.088398 # not ok 6 Check buffer write underflow by byte with async mode and mmap memory
7439 10:53:42.088486 # ok 7 Check buffer write underflow by byte with tag check fault ignore and mmap memory
7440 10:53:42.088573 # ok 8 Check buffer write underflow by byte with sync mode and mmap memory
7441 10:53:42.088670 # ok 9 Check buffer write underflow by byte with async mode and mmap memory
7442 10:53:42.088770 # ok 10 Check buffer write underflow by byte with tag check fault ignore and mmap memory
7443 10:53:42.088870 # not ok 11 Check buffer write overflow by byte with sync mode and mmap memory
7444 10:53:42.089149 # not ok 12 Check buffer write overflow by byte with async mode and mmap memory
7445 10:53:42.094745 # ok 13 Check buffer write overflow by byte with tag fault ignore mode and mmap memory
7446 10:53:42.095207 # not ok 14 Check buffer write correctness by block with sync mode and mmap memory
7447 10:53:42.095313 # not ok 15 Check buffer write correctness by block with async mode and mmap memory
7448 10:53:42.095417 # ok 16 Check buffer write correctness by block with tag fault ignore and mmap memory
7449 10:53:42.095520 # ok 17 Check initial tags with private mapping, sync error mode and mmap memory
7450 10:53:42.095807 # ok 18 Check initial tags with private mapping, sync error mode and mmap/mprotect memory
7451 10:53:42.096123 # ok 19 Check initial tags with shared mapping, sync error mode and mmap memory
7452 10:53:42.096234 # ok 20 Check initial tags with shared mapping, sync error mode and mmap/mprotect memory
7453 10:53:42.096339 # # Totals: pass:14 fail:6 xfail:0 xpass:0 skip:0 error:0
7454 10:53:42.108889 not ok 35 selftests: arm64: check_buffer_fill # exit=1
7455 10:53:42.213117 # selftests: arm64: check_child_memory
7456 10:53:42.664746 # 1..12
7457 10:53:42.665362 # not ok 1 Check child anonymous memory with private mapping, precise mode and mmap memory
7458 10:53:42.665575 # not ok 2 Check child anonymous memory with shared mapping, precise mode and mmap memory
7459 10:53:42.670462 # not ok 3 Check child anonymous memory with private mapping, imprecise mode and mmap memory
7460 10:53:42.671005 # not ok 4 Check child anonymous memory with shared mapping, imprecise mode and mmap memory
7461 10:53:42.671211 # not ok 5 Check child anonymous memory with private mapping, precise mode and mmap/mprotect memory
7462 10:53:42.671398 # not ok 6 Check child anonymous memory with shared mapping, precise mode and mmap/mprotect memory
7463 10:53:42.671528 # not ok 7 Check child file memory with private mapping, precise mode and mmap memory
7464 10:53:42.671885 # not ok 8 Check child file memory with shared mapping, precise mode and mmap memory
7465 10:53:42.672069 # not ok 9 Check child file memory with private mapping, imprecise mode and mmap memory
7466 10:53:42.672242 # not ok 10 Check child file memory with shared mapping, imprecise mode and mmap memory
7467 10:53:42.672426 # not ok 11 Check child file memory with private mapping, precise mode and mmap/mprotect memory
7468 10:53:42.672564 # not ok 12 Check child file memory with shared mapping, precise mode and mmap/mprotect memory
7469 10:53:42.672707 # # Totals: pass:0 fail:12 xfail:0 xpass:0 skip:0 error:0
7470 10:53:42.684217 not ok 36 selftests: arm64: check_child_memory # exit=1
7471 10:53:42.774444 # selftests: arm64: check_gcr_el1_cswitch
7472 10:54:26.716569 # 1..1
7473 10:54:26.716821 # 1..1
7474 10:54:26.716913 # 1..1
7475 10:54:26.717236 # 1..1
7476 10:54:26.717337 # 1..1
7477 10:54:26.717420 # 1..1
7478 10:54:26.717496 # 1..1
7479 10:54:26.717570 # 1..1
7480 10:54:26.717644 # 1..1
7481 10:54:26.717731 # 1..1
7482 10:54:26.717817 # 1..1
7483 10:54:26.717896 # 1..1
7484 10:54:26.717978 # 1..1
7485 10:54:26.718057 # 1..1
7486 10:54:26.718134 # 1..1
7487 10:54:26.718212 # 1..1
7488 10:54:26.718288 # 1..1
7489 10:54:26.718366 # 1..1
7490 10:54:26.718449 # 1..1
7491 10:54:26.718531 # 1..1
7492 10:54:26.718614 # 1..1
7493 10:54:26.718697 # 1..1
7494 10:54:26.718781 # 1..1
7495 10:54:26.718864 # 1..1
7496 10:54:26.718948 # 1..1
7497 10:54:26.719032 # 1..1
7498 10:54:26.719117 # 1..1
7499 10:54:26.719201 # 1..1
7500 10:54:26.719280 # 1..1
7501 10:54:26.719357 # 1..1
7502 10:54:26.719468 # 1..1
7503 10:54:26.719554 # 1..1
7504 10:54:26.719637 # 1..1
7505 10:54:26.719719 # 1..1
7506 10:54:26.719802 # 1..1
7507 10:54:26.719882 # 1..1
7508 10:54:26.719958 # 1..1
7509 10:54:26.720034 # 1..1
7510 10:54:26.720110 # 1..1
7511 10:54:26.720188 # 1..1
7512 10:54:26.720269 # 1..1
7513 10:54:26.720351 # 1..1
7514 10:54:26.720430 # 1..1
7515 10:54:26.720512 # 1..1
7516 10:54:26.720596 # 1..1
7517 10:54:26.720679 # 1..1
7518 10:54:26.720756 # 1..1
7519 10:54:26.720839 # 1..1
7520 10:54:26.720924 # 1..1
7521 10:54:26.721006 # 1..1
7522 10:54:26.721086 # 1..1
7523 10:54:26.721166 # 1..1
7524 10:54:26.721246 # 1..1
7525 10:54:26.721324 # 1..1
7526 10:54:26.721406 # 1..1
7527 10:54:26.721489 # 1..1
7528 10:54:26.721574 # 1..1
7529 10:54:26.721666 # 1..1
7530 10:54:26.721744 # 1..1
7531 10:54:26.721823 # 1..1
7532 10:54:26.721904 # 1..1
7533 10:54:26.721982 # 1..1
7534 10:54:26.722058 # 1..1
7535 10:54:26.722132 # 1..1
7536 10:54:26.722207 # 1..1
7537 10:54:26.722287 # 1..1
7538 10:54:26.722368 # 1..1
7539 10:54:26.722450 # 1..1
7540 10:54:26.722529 # 1..1
7541 10:54:26.722606 # 1..1
7542 10:54:26.722683 # 1..1
7543 10:54:26.722760 # 1..1
7544 10:54:26.722843 # 1..1
7545 10:54:26.722925 # 1..1
7546 10:54:26.723004 # 1..1
7547 10:54:26.723086 # 1..1
7548 10:54:26.723170 # 1..1
7549 10:54:26.723253 # 1..1
7550 10:54:26.723337 # 1..1
7551 10:54:26.723421 # 1..1
7552 10:54:26.723500 # 1..1
7553 10:54:26.723581 # 1..1
7554 10:54:26.723665 # 1..1
7555 10:54:26.723748 # 1..1
7556 10:54:26.723831 # 1..1
7557 10:54:26.723908 # 1..1
7558 10:54:26.723986 # 1..1
7559 10:54:26.724070 # 1..1
7560 10:54:26.724152 # 1..1
7561 10:54:26.724235 # 1..1
7562 10:54:26.724317 # 1..1
7563 10:54:26.724401 # 1..1
7564 10:54:26.724484 # 1..1
7565 10:54:26.724568 # 1..1
7566 10:54:26.724651 # 1..1
7567 10:54:26.724735 # 1..1
7568 10:54:26.724818 # 1..1
7569 10:54:26.724901 # 1..1
7570 10:54:26.724985 # 1..1
7571 10:54:26.725069 # 1..1
7572 10:54:26.725152 # 1..1
7573 10:54:26.725270 # 1..1
7574 10:54:26.725355 # 1..1
7575 10:54:26.725433 # 1..1
7576 10:54:26.776595 # 1..1
7577 10:54:26.776938 # 1..1
7578 10:54:26.777170 # 1..1
7579 10:54:26.777364 # 1..1
7580 10:54:26.777575 # 1..1
7581 10:54:26.777827 # 1..1
7582 10:54:26.778284 # 1..1
7583 10:54:26.778395 # 1..1
7584 10:54:26.778487 # 1..1
7585 10:54:26.778576 # 1..1
7586 10:54:26.778661 # 1..1
7587 10:54:26.778748 # 1..1
7588 10:54:26.778835 # 1..1
7589 10:54:26.778923 # 1..1
7590 10:54:26.779009 # 1..1
7591 10:54:26.779096 # 1..1
7592 10:54:26.779182 # 1..1
7593 10:54:26.779268 # 1..1
7594 10:54:26.779359 # 1..1
7595 10:54:26.779441 # 1..1
7596 10:54:26.779522 # 1..1
7597 10:54:26.779600 # 1..1
7598 10:54:26.779678 # 1..1
7599 10:54:26.779756 # 1..1
7600 10:54:26.779834 # 1..1
7601 10:54:26.779914 # 1..1
7602 10:54:26.779992 # 1..1
7603 10:54:26.780070 # 1..1
7604 10:54:26.780146 # 1..1
7605 10:54:26.780220 # 1..1
7606 10:54:26.780295 # 1..1
7607 10:54:26.780371 # 1..1
7608 10:54:26.780447 # 1..1
7609 10:54:26.780521 # 1..1
7610 10:54:26.780600 # 1..1
7611 10:54:26.780683 # 1..1
7612 10:54:26.780767 # 1..1
7613 10:54:26.780854 # 1..1
7614 10:54:26.780943 # 1..1
7615 10:54:26.781036 # 1..1
7616 10:54:26.781121 # 1..1
7617 10:54:26.781206 # 1..1
7618 10:54:26.781293 # 1..1
7619 10:54:26.781380 # 1..1
7620 10:54:26.781463 # 1..1
7621 10:54:26.781538 # 1..1
7622 10:54:26.781612 # 1..1
7623 10:54:26.781698 # 1..1
7624 10:54:26.781772 # 1..1
7625 10:54:26.781847 # 1..1
7626 10:54:26.781924 # 1..1
7627 10:54:26.782001 # 1..1
7628 10:54:26.782077 # 1..1
7629 10:54:26.782152 # 1..1
7630 10:54:26.782233 # 1..1
7631 10:54:26.782318 # 1..1
7632 10:54:26.782406 # 1..1
7633 10:54:26.782493 # 1..1
7634 10:54:26.782582 # 1..1
7635 10:54:26.782665 # 1..1
7636 10:54:26.782741 # 1..1
7637 10:54:26.782821 # 1..1
7638 10:54:26.782899 # 1..1
7639 10:54:26.782976 # 1..1
7640 10:54:26.783054 # 1..1
7641 10:54:26.783137 # 1..1
7642 10:54:26.783215 # 1..1
7643 10:54:26.783291 # 1..1
7644 10:54:26.783397 # 1..1
7645 10:54:26.783481 # 1..1
7646 10:54:26.783557 # 1..1
7647 10:54:26.783633 # 1..1
7648 10:54:26.783709 # 1..1
7649 10:54:26.783782 # 1..1
7650 10:54:26.783856 # 1..1
7651 10:54:26.783935 # 1..1
7652 10:54:26.784012 # 1..1
7653 10:54:26.784087 # 1..1
7654 10:54:26.784163 # 1..1
7655 10:54:26.784243 # 1..1
7656 10:54:26.784323 # 1..1
7657 10:54:26.784400 # 1..1
7658 10:54:26.784482 # 1..1
7659 10:54:26.784568 # 1..1
7660 10:54:26.784653 # 1..1
7661 10:54:26.784737 # 1..1
7662 10:54:26.784823 # 1..1
7663 10:54:26.784908 # 1..1
7664 10:54:26.784993 # 1..1
7665 10:54:26.785077 # 1..1
7666 10:54:26.785162 # 1..1
7667 10:54:26.785247 # 1..1
7668 10:54:26.785332 # 1..1
7669 10:54:26.785416 # 1..1
7670 10:54:26.785501 # 1..1
7671 10:54:26.785585 # 1..1
7672 10:54:26.785676 # 1..1
7673 10:54:26.785762 # 1..1
7674 10:54:26.785847 # 1..1
7675 10:54:26.785931 # 1..1
7676 10:54:26.786016 # 1..1
7677 10:54:26.786101 # 1..1
7678 10:54:26.786185 # 1..1
7679 10:54:26.988718 # 1..1
7680 10:54:26.989002 # 1..1
7681 10:54:26.989103 # 1..1
7682 10:54:26.989419 # 1..1
7683 10:54:26.989524 # 1..1
7684 10:54:26.989614 # 1..1
7685 10:54:26.989791 # 1..1
7686 10:54:26.989885 # 1..1
7687 10:54:26.989968 # 1..1
7688 10:54:26.990050 # 1..1
7689 10:54:26.990264 # 1..1
7690 10:54:26.990358 # 1..1
7691 10:54:26.990437 # 1..1
7692 10:54:26.990514 # 1..1
7693 10:54:26.990590 # 1..1
7694 10:54:26.990667 # 1..1
7695 10:54:26.990745 # 1..1
7696 10:54:26.990821 # 1..1
7697 10:54:26.990898 # 1..1
7698 10:54:26.990975 # 1..1
7699 10:54:26.991052 # 1..1
7700 10:54:26.991129 # 1..1
7701 10:54:26.991205 # 1..1
7702 10:54:26.991282 # 1..1
7703 10:54:26.991363 # 1..1
7704 10:54:26.991439 # 1..1
7705 10:54:26.991515 # 1..1
7706 10:54:26.991592 # 1..1
7707 10:54:26.991668 # 1..1
7708 10:54:26.991745 # 1..1
7709 10:54:26.991845 # 1..1
7710 10:54:26.991924 # 1..1
7711 10:54:26.991999 # 1..1
7712 10:54:26.992074 # 1..1
7713 10:54:26.992148 # 1..1
7714 10:54:26.992222 # 1..1
7715 10:54:26.992296 # 1..1
7716 10:54:26.992378 # 1..1
7717 10:54:26.992452 # 1..1
7718 10:54:26.992527 # 1..1
7719 10:54:26.992601 # 1..1
7720 10:54:26.992675 # 1..1
7721 10:54:26.992749 # 1..1
7722 10:54:26.992824 # 1..1
7723 10:54:26.992898 # 1..1
7724 10:54:26.992973 # 1..1
7725 10:54:26.993047 # 1..1
7726 10:54:26.993128 # 1..1
7727 10:54:26.993204 # 1..1
7728 10:54:26.993266 # 1..1
7729 10:54:26.993324 # 1..1
7730 10:54:26.993381 # 1..1
7731 10:54:26.993439 # 1..1
7732 10:54:26.993505 # 1..1
7733 10:54:26.993581 # 1..1
7734 10:54:26.994252 # 1..1
7735 10:54:26.994351 # 1..1
7736 10:54:26.994430 # 1..1
7737 10:54:26.994507 # 1..1
7738 10:54:26.994583 # 1..1
7739 10:54:26.994659 # 1..1
7740 10:54:26.994735 # 1..1
7741 10:54:26.994812 # 1..1
7742 10:54:26.994888 # 1..1
7743 10:54:26.994963 # 1..1
7744 10:54:26.995039 # 1..1
7745 10:54:26.995116 # 1..1
7746 10:54:26.995192 # 1..1
7747 10:54:26.995268 # 1..1
7748 10:54:26.995349 # 1..1
7749 10:54:26.995425 # 1..1
7750 10:54:26.995500 # 1..1
7751 10:54:26.995576 # 1..1
7752 10:54:26.995655 # 1..1
7753 10:54:26.995736 # 1..1
7754 10:54:26.995817 # 1..1
7755 10:54:26.995897 # 1..1
7756 10:54:26.995980 # 1..1
7757 10:54:26.996061 # 1..1
7758 10:54:26.996142 # 1..1
7759 10:54:26.996223 # 1..1
7760 10:54:26.996307 # 1..1
7761 10:54:26.996392 # 1..1
7762 10:54:26.996478 # 1..1
7763 10:54:26.996563 # 1..1
7764 10:54:26.996649 # 1..1
7765 10:54:26.996735 # 1..1
7766 10:54:26.996821 # 1..1
7767 10:54:26.996906 # 1..1
7768 10:54:26.996992 # 1..1
7769 10:54:26.997078 # 1..1
7770 10:54:26.997164 # 1..1
7771 10:54:26.997250 # 1..1
7772 10:54:26.997336 # 1..1
7773 10:54:26.997421 # 1..1
7774 10:54:27.204257 # 1..1
7775 10:54:27.204506 # 1..1
7776 10:54:27.204601 # 1..1
7777 10:54:27.204690 # 1..1
7778 10:54:27.204779 # 1..1
7779 10:54:27.204866 # 1..1
7780 10:54:27.205176 # 1..1
7781 10:54:27.205281 # 1..1
7782 10:54:27.205371 # 1..1
7783 10:54:27.205460 # 1..1
7784 10:54:27.205545 # 1..1
7785 10:54:27.205624 # 1..1
7786 10:54:27.205710 # 1..1
7787 10:54:27.205789 # 1..1
7788 10:54:27.205868 # 1..1
7789 10:54:27.205955 # 1..1
7790 10:54:27.206044 # 1..1
7791 10:54:27.206130 # 1..1
7792 10:54:27.206215 # 1..1
7793 10:54:27.206300 # 1..1
7794 10:54:27.206384 # 1..1
7795 10:54:27.206469 # 1..1
7796 10:54:27.206552 # 1..1
7797 10:54:27.206632 # 1..1
7798 10:54:27.206715 # 1..1
7799 10:54:27.206797 # 1..1
7800 10:54:27.206881 # 1..1
7801 10:54:27.206965 # 1..1
7802 10:54:27.207047 # 1..1
7803 10:54:27.207126 # 1..1
7804 10:54:27.207204 # 1..1
7805 10:54:27.207281 # 1..1
7806 10:54:27.207358 # 1..1
7807 10:54:27.207434 # 1..1
7808 10:54:27.207512 # 1..1
7809 10:54:27.207590 # 1..1
7810 10:54:27.207696 # 1..1
7811 10:54:27.207781 # 1..1
7812 10:54:27.207864 # 1..1
7813 10:54:27.207947 # 1..1
7814 10:54:27.208028 # 1..1
7815 10:54:27.208110 # 1..1
7816 10:54:27.208192 # 1..1
7817 10:54:27.208275 # 1..1
7818 10:54:27.208354 # 1..1
7819 10:54:27.208431 # 1..1
7820 10:54:27.208507 # 1..1
7821 10:54:27.208584 # 1..1
7822 10:54:27.208660 # 1..1
7823 10:54:27.208739 # 1..1
7824 10:54:27.208820 # 1..1
7825 10:54:27.208902 # 1..1
7826 10:54:27.208985 # 1..1
7827 10:54:27.209068 # 1..1
7828 10:54:27.209150 # 1..1
7829 10:54:27.209233 # 1..1
7830 10:54:27.209313 # 1..1
7831 10:54:27.209389 # 1..1
7832 10:54:27.209465 # 1..1
7833 10:54:27.209542 # 1..1
7834 10:54:27.209618 # 1..1
7835 10:54:27.209708 # 1..1
7836 10:54:27.209789 # 1..1
7837 10:54:27.209872 # 1..1
7838 10:54:27.209954 # 1..1
7839 10:54:27.210036 # 1..1
7840 10:54:27.210118 # 1..1
7841 10:54:27.210200 # 1..1
7842 10:54:27.210280 # 1..1
7843 10:54:27.210357 # 1..1
7844 10:54:27.210436 # 1..1
7845 10:54:27.210515 # 1..1
7846 10:54:27.210593 # 1..1
7847 10:54:27.210674 # 1..1
7848 10:54:27.210762 # 1..1
7849 10:54:27.210851 # 1..1
7850 10:54:27.210936 # 1..1
7851 10:54:27.211016 # 1..1
7852 10:54:27.211094 # 1..1
7853 10:54:27.211171 # 1..1
7854 10:54:27.211249 # 1..1
7855 10:54:27.211329 # 1..1
7856 10:54:27.211412 # 1..1
7857 10:54:27.211496 # 1..1
7858 10:54:27.211575 # 1..1
7859 10:54:27.211653 # 1..1
7860 10:54:27.211732 # 1..1
7861 10:54:27.211810 # 1..1
7862 10:54:27.211889 # 1..1
7863 10:54:27.211971 # 1..1
7864 10:54:27.212056 # 1..1
7865 10:54:27.212135 # 1..1
7866 10:54:27.212214 # 1..1
7867 10:54:27.212292 # 1..1
7868 10:54:27.212371 # 1..1
7869 10:54:27.212450 # 1..1
7870 10:54:27.212533 # 1..1
7871 10:54:27.212617 # 1..1
7872 10:54:27.212697 # 1..1
7873 10:54:27.212776 # 1..1
7874 10:54:27.212857 # 1..1
7875 10:54:27.212936 # 1..1
7876 10:54:27.213014 # 1..1
7877 10:54:27.213099 # 1..1
7878 10:54:27.213183 # 1..1
7879 10:54:27.213262 # 1..1
7880 10:54:27.213342 # 1..1
7881 10:54:27.213422 # 1..1
7882 10:54:27.213502 # 1..1
7883 10:54:27.213582 # 1..1
7884 10:54:27.213673 # 1..1
7885 10:54:27.213762 # 1..1
7886 10:54:27.213843 # 1..1
7887 10:54:27.213927 # 1..1
7888 10:54:27.214012 # 1..1
7889 10:54:27.445096 # 1..1
7890 10:54:27.445676 # 1..1
7891 10:54:27.445791 # 1..1
7892 10:54:27.445884 # 1..1
7893 10:54:27.445973 # 1..1
7894 10:54:27.446060 # 1..1
7895 10:54:27.446147 # 1..1
7896 10:54:27.446238 # 1..1
7897 10:54:27.446325 # 1..1
7898 10:54:27.446411 # 1..1
7899 10:54:27.446496 # 1..1
7900 10:54:27.446582 # 1..1
7901 10:54:27.446669 # 1..1
7902 10:54:27.446755 # 1..1
7903 10:54:27.446840 # 1..1
7904 10:54:27.446925 # 1..1
7905 10:54:27.447010 # 1..1
7906 10:54:27.447095 # 1..1
7907 10:54:27.447180 # 1..1
7908 10:54:27.447265 # 1..1
7909 10:54:27.447354 # 1..1
7910 10:54:27.447435 # 1..1
7911 10:54:27.447512 # 1..1
7912 10:54:27.447587 # 1..1
7913 10:54:27.447661 # 1..1
7914 10:54:27.447737 # 1..1
7915 10:54:27.447834 # 1..1
7916 10:54:27.447917 # 1..1
7917 10:54:27.447996 # 1..1
7918 10:54:27.448071 # 1..1
7919 10:54:27.448147 # 1..1
7920 10:54:27.448221 # 1..1
7921 10:54:27.448294 # 1..1
7922 10:54:27.448367 # 1..1
7923 10:54:27.448440 # 1..1
7924 10:54:27.448514 # 1..1
7925 10:54:27.448586 # 1..1
7926 10:54:27.448664 # 1..1
7927 10:54:27.448748 # 1..1
7928 10:54:27.448829 # 1..1
7929 10:54:27.448914 # 1..1
7930 10:54:27.448998 # 1..1
7931 10:54:27.449084 # 1..1
7932 10:54:27.449167 # 1..1
7933 10:54:27.449250 # 1..1
7934 10:54:27.449335 # 1..1
7935 10:54:27.449420 # 1..1
7936 10:54:27.449498 # 1..1
7937 10:54:27.449570 # 1..1
7938 10:54:27.449642 # 1..1
7939 10:54:27.450373 # 1..1
7940 10:54:27.450466 # 1..1
7941 10:54:27.450555 # 1..1
7942 10:54:27.450642 # 1..1
7943 10:54:27.450724 # 1..1
7944 10:54:27.450801 # 1..1
7945 10:54:27.450881 # 1..1
7946 10:54:27.450958 # 1..1
7947 10:54:27.451036 # 1..1
7948 10:54:27.451113 # 1..1
7949 10:54:27.451191 # 1..1
7950 10:54:27.451267 # 1..1
7951 10:54:27.451343 # 1..1
7952 10:54:27.451424 # 1..1
7953 10:54:27.451501 # 1..1
7954 10:54:27.451576 # 1..1
7955 10:54:27.451652 # 1..1
7956 10:54:27.451730 # 1..1
7957 10:54:27.451805 # 1..1
7958 10:54:27.451878 # 1..1
7959 10:54:27.451955 # 1..1
7960 10:54:27.452031 # 1..1
7961 10:54:27.452109 # 1..1
7962 10:54:27.452190 # 1..1
7963 10:54:27.642071 # 1..1
7964 10:54:27.642364 # 1..1
7965 10:54:27.642552 # 1..1
7966 10:54:27.642704 # 1..1
7967 10:54:27.642835 # 1..1
7968 10:54:27.642964 # 1..1
7969 10:54:27.643340 # 1..1
7970 10:54:27.643505 # 1..1
7971 10:54:27.643688 # 1..1
7972 10:54:27.643829 # 1..1
7973 10:54:27.643957 # 1..1
7974 10:54:27.644081 # 1..1
7975 10:54:27.644206 # 1..1
7976 10:54:27.644331 # 1..1
7977 10:54:27.644455 # 1..1
7978 10:54:27.644583 # 1..1
7979 10:54:27.644706 # 1..1
7980 10:54:27.644830 # 1..1
7981 10:54:27.644953 # 1..1
7982 10:54:27.645077 # 1..1
7983 10:54:27.645201 # 1..1
7984 10:54:27.645322 # 1..1
7985 10:54:27.645445 # 1..1
7986 10:54:27.645625 # 1..1
7987 10:54:27.645819 # 1..1
7988 10:54:27.645989 # 1..1
7989 10:54:27.646140 # 1..1
7990 10:54:27.646261 # 1..1
7991 10:54:27.646380 # 1..1
7992 10:54:27.646497 # 1..1
7993 10:54:27.646616 # 1..1
7994 10:54:27.646733 # 1..1
7995 10:54:27.646849 # 1..1
7996 10:54:27.646964 # 1..1
7997 10:54:27.647080 # 1..1
7998 10:54:27.647196 # 1..1
7999 10:54:27.647311 # 1..1
8000 10:54:27.647426 # 1..1
8001 10:54:27.647572 # 1..1
8002 10:54:27.647698 # 1..1
8003 10:54:27.647816 # 1..1
8004 10:54:27.647933 # 1..1
8005 10:54:27.648050 # 1..1
8006 10:54:27.648168 # 1..1
8007 10:54:27.753138 # 1..1
8008 10:54:27.753502 # 1..1
8009 10:54:27.753715 # 1..1
8010 10:54:27.753927 # 1..1
8011 10:54:27.754126 # 1..1
8012 10:54:27.754291 # 1..1
8013 10:54:27.754697 # 1..1
8014 10:54:27.754845 # 1..1
8015 10:54:27.754992 # 1..1
8016 10:54:27.755135 # 1..1
8017 10:54:27.755276 # 1..1
8018 10:54:27.755417 # 1..1
8019 10:54:27.755558 # 1..1
8020 10:54:27.755700 # 1..1
8021 10:54:27.755843 # 1..1
8022 10:54:27.755983 # 1..1
8023 10:54:27.756123 # 1..1
8024 10:54:27.756263 # 1..1
8025 10:54:27.756402 # 1..1
8026 10:54:27.756543 # 1..1
8027 10:54:27.756682 # 1..1
8028 10:54:27.756824 # 1..1
8029 10:54:27.756964 # 1..1
8030 10:54:27.757103 # 1..1
8031 10:54:27.757242 # 1..1
8032 10:54:27.757383 # 1..1
8033 10:54:27.757523 # 1..1
8034 10:54:27.757674 # 1..1
8035 10:54:27.757825 # 1..1
8036 10:54:27.757966 # 1..1
8037 10:54:27.758106 # 1..1
8038 10:54:27.758246 # 1..1
8039 10:54:27.758386 # 1..1
8040 10:54:27.758527 # 1..1
8041 10:54:27.758666 # 1..1
8042 10:54:27.758809 # 1..1
8043 10:54:27.758952 # 1..1
8044 10:54:27.759092 # 1..1
8045 10:54:27.759232 # 1..1
8046 10:54:27.759373 # 1..1
8047 10:54:27.759514 # 1..1
8048 10:54:27.759655 # 1..1
8049 10:54:27.759796 # 1..1
8050 10:54:27.759937 # 1..1
8051 10:54:27.760078 # 1..1
8052 10:54:27.760219 # 1..1
8053 10:54:27.760361 # 1..1
8054 10:54:27.760502 # 1..1
8055 10:54:27.760643 # 1..1
8056 10:54:27.760785 # 1..1
8057 10:54:28.028220 #<47>[ 99.554116] systemd-journald[105]: Sent WATCHDOG=1 notification.
8058 10:54:28.586958 <47>[ 100.114252] systemd-journald[105]: Data hash table of /run/log/journal/938dcdc227b64155a30c60b8906c70ae/system.journal has a fill level at 75.0 (3328 of 4437 items, 2555904 file size, 768 bytes per hash table item), suggesting rotation.
8059 10:54:28.587318 <47>[ 100.114833] systemd-journald[105]: /run/log/journal/938dcdc227b64155a30c60b8906c70ae/system.journal: Journal header limits reached or header out-of-date, rotating.
8060 10:54:28.587523 <47>[ 100.115228] systemd-journald[105]: Rotating...
8061 10:54:28.610657 <47>[ 100.138396] systemd-journald[105]: Reserving 333 entries in field hash table.
8062 10:54:28.656983 <47>[ 100.184648] systemd-journald[105]: Reserving 4437 entries in data hash table.
8063 10:54:28.669061 <47>[ 100.196801] systemd-journald[105]: Vacuuming...
8064 10:54:28.671578 <47>[ 100.199202] systemd-journald[105]: Vacuuming done, freed 0B of archived journals from /run/log/journal/938dcdc227b64155a30c60b8906c70ae.
8065 10:54:29.337145 1..1
8066 10:54:29.337409 # 1..1
8067 10:54:29.337529 # 1..1
8068 10:54:29.337639 # 1..1
8069 10:54:29.337750 # 1..1
8070 10:54:29.337894 # 1..1
8071 10:54:29.338291 # 1..1
8072 10:54:29.338453 # 1..1
8073 10:54:29.338581 # 1..1
8074 10:54:29.338699 # 1..1
8075 10:54:29.338817 # 1..1
8076 10:54:29.338934 # 1..1
8077 10:54:29.339052 # 1..1
8078 10:54:29.339169 # 1..1
8079 10:54:29.339286 # 1..1
8080 10:54:29.339410 # 1..1
8081 10:54:29.339528 # 1..1
8082 10:54:29.339644 # 1..1
8083 10:54:29.339810 # 1..1
8084 10:54:29.339937 # 1..1
8085 10:54:29.340056 # 1..1
8086 10:54:29.340173 # 1..1
8087 10:54:29.340289 # 1..1
8088 10:54:29.340405 # 1..1
8089 10:54:29.340521 # 1..1
8090 10:54:29.340637 # 1..1
8091 10:54:29.340755 # 1..1
8092 10:54:29.340876 # 1..1
8093 10:54:29.382713 #
8094 10:54:29.383472 not ok 37 selftests: arm64: check_gcr_el1_cswitch # TIMEOUT 45 seconds
8095 10:54:29.637557 # selftests: arm64: check_ksm_options
8096 10:54:29.929086 # 1..4
8097 10:54:29.929325 # # Invalid MTE synchronous exception caught!
8098 10:54:29.958018 not ok 38 selftests: arm64: check_ksm_options # exit=1
8099 10:54:30.146449 # selftests: arm64: check_mmap_options
8100 10:54:30.780959 # 1..22
8101 10:54:30.781506 # ok 1 Check anonymous memory with private mapping, sync error mode, mmap memory and tag check off
8102 10:54:30.781618 # ok 2 Check file memory with private mapping, sync error mode, mmap/mprotect memory and tag check off
8103 10:54:30.781717 # ok 3 Check anonymous memory with private mapping, no error mode, mmap memory and tag check off
8104 10:54:30.781821 # ok 4 Check file memory with private mapping, no error mode, mmap/mprotect memory and tag check off
8105 10:54:30.782160 # not ok 5 Check anonymous memory with private mapping, sync error mode, mmap memory and tag check on
8106 10:54:30.782384 # not ok 6 Check anonymous memory with private mapping, sync error mode, mmap/mprotect memory and tag check on
8107 10:54:30.782630 # not ok 7 Check anonymous memory with shared mapping, sync error mode, mmap memory and tag check on
8108 10:54:30.782870 # not ok 8 Check anonymous memory with shared mapping, sync error mode, mmap/mprotect memory and tag check on
8109 10:54:30.783103 # not ok 9 Check anonymous memory with private mapping, async error mode, mmap memory and tag check on
8110 10:54:30.783342 # not ok 10 Check anonymous memory with private mapping, async error mode, mmap/mprotect memory and tag check on
8111 10:54:30.783553 # not ok 11 Check anonymous memory with shared mapping, async error mode, mmap memory and tag check on
8112 10:54:30.801585 # not ok 12 Check anonymous memory with shared mapping, async error mode, mmap/mprotect memory and tag check on
8113 10:54:30.802149 # not ok 13 Check file memory with private mapping, sync error mode, mmap memory and tag check on
8114 10:54:30.802313 # not ok 14 Check file memory with private mapping, sync error mode, mmap/mprotect memory and tag check on
8115 10:54:30.802516 # not ok 15 Check file memory with shared mapping, sync error mode, mmap memory and tag check on
8116 10:54:30.802776 # not ok 16 Check file memory with shared mapping, sync error mode, mmap/mprotect memory and tag check on
8117 10:54:30.802941 # not ok 17 Check file memory with private mapping, async error mode, mmap memory and tag check on
8118 10:54:30.803091 # not ok 18 Check file memory with private mapping, async error mode, mmap/mprotect memory and tag check on
8119 10:54:30.803272 # not ok 19 Check file memory with shared mapping, async error mode, mmap memory and tag check on
8120 10:54:30.803429 # not ok 20 Check file memory with shared mapping, async error mode, mmap/mprotect memory and tag check on
8121 10:54:30.803583 # not ok 21 Check clear PROT_MTE flags with private mapping, sync error mode and mmap memory
8122 10:54:30.836567 # not ok 22 Check clear PROT_MTE flags with private mapping and sync error mode and mmap/mprotect memory
8123 10:54:30.836900 # # Totals: pass:4 fail:18 xfail:0 xpass:0 skip:0 error:0
8124 10:54:30.844284 not ok 39 selftests: arm64: check_mmap_options # exit=1
8125 10:54:31.121501 # selftests: arm64: check_prctl
8126 10:54:31.396592 # TAP version 13
8127 10:54:31.396878 # 1..5
8128 10:54:31.397010 # ok 1 check_basic_read
8129 10:54:31.397131 # ok 2 NONE
8130 10:54:31.397472 # ok 3 SYNC
8131 10:54:31.397601 # ok 4 ASYNC
8132 10:54:31.397740 # ok 5 SYNC+ASYNC
8133 10:54:31.397858 # # Totals: pass:5 fail:0 xfail:0 xpass:0 skip:0 error:0
8134 10:54:31.424707 ok 40 selftests: arm64: check_prctl
8135 10:54:31.685303 # selftests: arm64: check_tags_inclusion
8136 10:54:31.975605 # 1..4
8137 10:54:31.976354 # # Unexpected fault recorded for 0xe00ffff92a5b000-0xe00ffff92a5b050 in mode 1
8138 10:54:31.976569 # not ok 1 Check an included tag value with sync mode
8139 10:54:31.976787 # # Unexpected fault recorded for 0xa00ffff92a5b000-0xa00ffff92a5b050 in mode 1
8140 10:54:31.976970 # not ok 2 Check different included tags value with sync mode
8141 10:54:31.977142 # ok 3 Check none included tags value with sync mode
8142 10:54:31.977312 # # Unexpected fault recorded for 0xe00ffff92a5b000-0xe00ffff92a5b050 in mode 1
8143 10:54:31.977435 # not ok 4 Check all included tags value with sync mode
8144 10:54:31.977552 # # Totals: pass:1 fail:3 xfail:0 xpass:0 skip:0 error:0
8145 10:54:32.022613 not ok 41 selftests: arm64: check_tags_inclusion # exit=1
8146 10:54:32.260957 # selftests: arm64: check_user_mem
8147 10:54:39.859109 # 1..64
8148 10:54:39.859471 # ok 1 test type: read, MTE_SYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 0
8149 10:54:39.859881 # ok 2 test type: read, MTE_SYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 16
8150 10:54:39.860040 # ok 3 test type: read, MTE_SYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 0
8151 10:54:39.860570 # ok 4 test type: read, MTE_SYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 16
8152 10:54:39.860939 # ok 5 test type: read, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 0
8153 10:54:39.861086 # ok 6 test type: read, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 16
8154 10:54:39.861245 # ok 7 test type: read, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 0
8155 10:54:39.861395 # ok 8 test type: read, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 16
8156 10:54:39.861606 # ok 9 test type: read, MTE_ASYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 0
8157 10:54:39.861831 # ok 10 test type: read, MTE_ASYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 16
8158 10:54:39.862035 # ok 11 test type: read, MTE_ASYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 0
8159 10:54:39.862247 # ok 12 test type: read, MTE_ASYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 16
8160 10:54:39.862432 # ok 13 test type: read, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 0
8161 10:54:39.862629 # ok 14 test type: read, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 16
8162 10:54:39.862820 # ok 15 test type: read, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 0
8163 10:54:39.862979 # ok 16 test type: read, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 16
8164 10:54:39.863143 # ok 17 test type: write, MTE_SYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 0
8165 10:54:39.863321 # ok 18 test type: write, MTE_SYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 16
8166 10:54:39.863524 # ok 19 test type: write, MTE_SYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 0
8167 10:54:39.863709 # ok 20 test type: write, MTE_SYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 16
8168 10:54:39.863876 # ok 21 test type: write, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 0
8169 10:54:39.869125 # ok 22 test type: write, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 16
8170 10:54:39.869666 # ok 23 test type: write, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 0
8171 10:54:39.869780 # ok 24 test type: write, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 16
8172 10:54:39.869876 # ok 25 test type: write, MTE_ASYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 0
8173 10:54:39.869979 # ok 26 test type: write, MTE_ASYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 16
8174 10:54:39.870283 # ok 27 test type: write, MTE_ASYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 0
8175 10:54:39.870407 # ok 28 test type: write, MTE_ASYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 16
8176 10:54:39.870750 # ok 29 test type: write, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 0
8177 10:54:39.870977 # ok 30 test type: write, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 16
8178 10:54:39.871185 # ok 31 test type: write, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 0
8179 10:54:39.871419 # ok 32 test type: write, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 16
8180 10:54:39.871639 # ok 33 test type: readv, MTE_SYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 0
8181 10:54:39.871876 # ok 34 test type: readv, MTE_SYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 16
8182 10:54:39.872070 # ok 35 test type: readv, MTE_SYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 0
8183 10:54:39.872310 # ok 36 test type: readv, MTE_SYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 16
8184 10:54:39.872484 # ok 37 test type: readv, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 0
8185 10:54:39.872689 # ok 38 test type: readv, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 16
8186 10:54:39.872902 # ok 39 test type: readv, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 0
8187 10:54:39.873154 # ok 40 test type: readv, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 16
8188 10:54:39.873318 # ok 41 test type: readv, MTE_ASYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 0
8189 10:54:39.873536 # ok 42 test type: readv, MTE_ASYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 16
8190 10:54:39.873812 # ok 43 test type: readv, MTE_ASYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 0
8191 10:54:39.874022 # ok 44 test type: readv, MTE_ASYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 16
8192 10:54:39.874237 # ok 45 test type: readv, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 0
8193 10:54:39.874415 # ok 46 test type: readv, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 16
8194 10:54:39.874557 # ok 47 test type: readv, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 0
8195 10:54:39.874747 # ok 48 test type: readv, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 16
8196 10:54:39.874885 # ok 49 test type: writev, MTE_SYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 0
8197 10:54:39.875022 # ok 50 test type: writev, MTE_SYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 16
8198 10:54:39.875167 # ok 51 test type: writev, MTE_SYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 0
8199 10:54:41.352913 # ok 52 test type: writev, MTE_SYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 16
8200 10:54:41.353491 # ok 53 test type: writev, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 0
8201 10:54:41.354974 # ok 54 test type: writev, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 16
8202 10:54:41.355083 # ok 55 test type: writev, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 0
8203 10:54:41.355169 # ok 56 test type: writev, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 16
8204 10:54:41.355253 # ok 57 test type: writev, MTE_ASYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 0
8205 10:54:41.355336 # ok 58 test type: writev, MTE_ASYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 16
8206 10:54:41.355420 # ok 59 test type: writev, MTE_ASYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 0
8207 10:54:41.355502 # ok 60 test type: writev, MTE_ASYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 16
8208 10:54:41.355587 # ok 61 test type: writev, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 0
8209 10:54:41.355663 # ok 62 test type: writev, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 16
8210 10:54:41.355740 # ok 63 test type: writev, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 0
8211 10:54:41.355817 # ok 64 test type: writev, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 16
8212 10:54:41.355896 # # Totals: pass:64 fail:0 xfail:0 xpass:0 skip:0 error:0
8213 10:54:41.370390 ok 42 selftests: arm64: check_user_mem
8214 10:54:41.453034 # selftests: arm64: btitest
8215 10:54:41.570298 # TAP version 13
8216 10:54:41.570587 # 1..18
8217 10:54:41.570779 # # HWCAP_PACA present
8218 10:54:41.570944 # # HWCAP2_BTI present
8219 10:54:41.571359 # # Test binary built for BTI
8220 10:54:41.571527 # # [SIGILL in nohint_func/call_using_br_x0, BTYPE=11 (expected)]
8221 10:54:41.571685 # ok 1 nohint_func/call_using_br_x0
8222 10:54:41.571856 # # [SIGILL in nohint_func/call_using_br_x16, BTYPE=01 (expected)]
8223 10:54:41.571986 # ok 2 nohint_func/call_using_br_x16
8224 10:54:41.572105 # # [SIGILL in nohint_func/call_using_blr, BTYPE=10 (expected)]
8225 10:54:41.572224 # ok 3 nohint_func/call_using_blr
8226 10:54:41.572340 # # [SIGILL in bti_none_func/call_using_br_x0, BTYPE=11 (expected)]
8227 10:54:41.572486 # ok 4 bti_none_func/call_using_br_x0
8228 10:54:41.573392 # # [SIGILL in bti_none_func/call_using_br_x16, BTYPE=01 (expected)]
8229 10:54:41.573783 # ok 5 bti_none_func/call_using_br_x16
8230 10:54:41.573936 # # [SIGILL in bti_none_func/call_using_blr, BTYPE=10 (expected)]
8231 10:54:41.574072 # ok 6 bti_none_func/call_using_blr
8232 10:54:41.574232 # # [SIGILL in bti_c_func/call_using_br_x0, BTYPE=11 (expected)]
8233 10:54:41.574424 # ok 7 bti_c_func/call_using_br_x0
8234 10:54:41.574613 # ok 8 bti_c_func/call_using_br_x16
8235 10:54:41.574801 # ok 9 bti_c_func/call_using_blr
8236 10:54:41.574974 # ok 10 bti_j_func/call_using_br_x0
8237 10:54:41.575171 # ok 11 bti_j_func/call_using_br_x16
8238 10:54:41.575306 # # [SIGILL in bti_j_func/call_using_blr, BTYPE=10 (expected)]
8239 10:54:41.575425 # ok 12 bti_j_func/call_using_blr
8240 10:54:41.575541 # ok 13 bti_jc_func/call_using_br_x0
8241 10:54:41.575709 # ok 14 bti_jc_func/call_using_br_x16
8242 10:54:41.575868 # ok 15 bti_jc_func/call_using_blr
8243 10:54:41.575993 # # [SIGILL in paciasp_func/call_using_br_x0, BTYPE=11 (expected)]
8244 10:54:41.576112 # ok 16 paciasp_func/call_using_br_x0
8245 10:54:41.576231 # ok 17 paciasp_func/call_using_br_x16
8246 10:54:41.576347 # ok 18 paciasp_func/call_using_blr
8247 10:54:41.576463 # # Totals: pass:18 fail:0 xfail:0 xpass:0 skip:0 error:0
8248 10:54:41.591211 ok 43 selftests: arm64: btitest
8249 10:54:41.673145 # selftests: arm64: nobtitest
8250 10:54:41.783415 # TAP version 13
8251 10:54:41.783716 # 1..18
8252 10:54:41.784106 # # HWCAP_PACA present
8253 10:54:41.784250 # # HWCAP2_BTI present
8254 10:54:41.784384 # # Test binary not built for BTI
8255 10:54:41.784838 # ok 1 nohint_func/call_using_br_x0
8256 10:54:41.785000 # ok 2 nohint_func/call_using_br_x16
8257 10:54:41.785161 # ok 3 nohint_func/call_using_blr
8258 10:54:41.785299 # ok 4 bti_none_func/call_using_br_x0
8259 10:54:41.785429 # ok 5 bti_none_func/call_using_br_x16
8260 10:54:41.785574 # ok 6 bti_none_func/call_using_blr
8261 10:54:41.785714 # ok 7 bti_c_func/call_using_br_x0
8262 10:54:41.785836 # ok 8 bti_c_func/call_using_br_x16
8263 10:54:41.785955 # ok 9 bti_c_func/call_using_blr
8264 10:54:41.786134 # ok 10 bti_j_func/call_using_br_x0
8265 10:54:41.786349 # ok 11 bti_j_func/call_using_br_x16
8266 10:54:41.786564 # ok 12 bti_j_func/call_using_blr
8267 10:54:41.786714 # ok 13 bti_jc_func/call_using_br_x0
8268 10:54:41.786836 # ok 14 bti_jc_func/call_using_br_x16
8269 10:54:41.786954 # ok 15 bti_jc_func/call_using_blr
8270 10:54:41.787071 # ok 16 paciasp_func/call_using_br_x0
8271 10:54:41.787190 # ok 17 paciasp_func/call_using_br_x16
8272 10:54:41.787337 # ok 18 paciasp_func/call_using_blr
8273 10:54:41.787505 # # Totals: pass:18 fail:0 xfail:0 xpass:0 skip:0 error:0
8274 10:54:41.802742 ok 44 selftests: arm64: nobtitest
8275 10:54:41.881025 # selftests: arm64: hwcap
8276 10:54:42.029311 # TAP version 13
8277 10:54:42.029554 # 1..28
8278 10:54:42.029655 # # RNG present
8279 10:54:42.029939 # ok 1 cpuinfo_match_RNG
8280 10:54:42.030037 # ok 2 sigill_RNG
8281 10:54:42.030130 # # SME present
8282 10:54:42.030220 # ok 3 cpuinfo_match_SME
8283 10:54:42.030308 # ok 4 sigill_SME
8284 10:54:42.030399 # # SVE present
8285 10:54:42.030488 # ok 5 cpuinfo_match_SVE
8286 10:54:42.030575 # ok 6 sigill_SVE
8287 10:54:42.030661 # # SVE 2 present
8288 10:54:42.030750 # ok 7 cpuinfo_match_SVE 2
8289 10:54:42.030862 # ok 8 sigill_SVE 2
8290 10:54:42.030955 # # SVE AES present
8291 10:54:42.031043 # ok 9 cpuinfo_match_SVE AES
8292 10:54:42.031131 # ok 10 sigill_SVE AES
8293 10:54:42.031218 # # SVE2 PMULL present
8294 10:54:42.031303 # ok 11 cpuinfo_match_SVE2 PMULL
8295 10:54:42.031390 # ok 12 sigill_SVE2 PMULL
8296 10:54:42.031475 # # SVE2 BITPERM present
8297 10:54:42.031555 # ok 13 cpuinfo_match_SVE2 BITPERM
8298 10:54:42.031631 # ok 14 sigill_SVE2 BITPERM
8299 10:54:42.031723 # # SVE2 SHA3 present
8300 10:54:42.031803 # ok 15 cpuinfo_match_SVE2 SHA3
8301 10:54:42.031880 # ok 16 sigill_SVE2 SHA3
8302 10:54:42.031954 # # SVE2 SM4 present
8303 10:54:42.032029 # ok 17 cpuinfo_match_SVE2 SM4
8304 10:54:42.032106 # ok 18 sigill_SVE2 SM4
8305 10:54:42.032180 # # SVE2 I8MM present
8306 10:54:42.034595 # ok 19 cpuinfo_match_SVE2 I8MM
8307 10:54:42.035029 # ok 20 sigill_SVE2 I8MM
8308 10:54:42.035139 # # SVE2 F32MM present
8309 10:54:42.035216 # ok 21 cpuinfo_match_SVE2 F32MM
8310 10:54:42.035282 # ok 22 sigill_SVE2 F32MM
8311 10:54:42.035361 # # SVE2 F64MM present
8312 10:54:42.035428 # ok 23 cpuinfo_match_SVE2 F64MM
8313 10:54:42.035506 # ok 24 sigill_SVE2 F64MM
8314 10:54:42.035585 # # SVE2 BF16 present
8315 10:54:42.035647 # ok 25 cpuinfo_match_SVE2 BF16
8316 10:54:42.035705 # ok 26 sigill_SVE2 BF16
8317 10:54:42.035763 # ok 27 cpuinfo_match_SVE2 EBF16
8318 10:54:42.035821 # ok 28 # SKIP sigill_SVE2 EBF16
8319 10:54:42.049025 # # Totals: pass:27 fail:0 xfail:0 xpass:0 skip:1 error:0
8320 10:54:42.060469 ok 45 selftests: arm64: hwcap
8321 10:54:42.223161 # selftests: arm64: ptrace
8322 10:54:42.425255 # TAP version 13
8323 10:54:42.425495 # 1..7
8324 10:54:42.425833 # # Parent is 4947, child is 4948
8325 10:54:42.425937 # ok 1 read_tpidr_one
8326 10:54:42.426027 # ok 2 write_tpidr_one
8327 10:54:42.426113 # ok 3 verify_tpidr_one
8328 10:54:42.426199 # ok 4 count_tpidrs
8329 10:54:42.426284 # ok 5 tpidr2_write
8330 10:54:42.426368 # ok 6 tpidr2_read
8331 10:54:42.426451 # ok 7 write_tpidr_only
8332 10:54:42.426551 # # Totals: pass:7 fail:0 xfail:0 xpass:0 skip:0 error:0
8333 10:54:42.453900 ok 46 selftests: arm64: ptrace
8334 10:54:42.594968 # selftests: arm64: syscall-abi
8335 10:54:45.594901 # TAP version 13
8336 10:54:45.595253 # 1..514
8337 10:54:45.595667 # # SME with FA64
8338 10:54:45.595826 # ok 1 getpid() FPSIMD
8339 10:54:45.595983 # ok 2 getpid() SVE VL 256
8340 10:54:45.596139 # ok 3 getpid() SVE VL 256/SME VL 256 SM+ZA
8341 10:54:45.596294 # ok 4 getpid() SVE VL 256/SME VL 256 SM
8342 10:54:45.596452 # ok 5 getpid() SVE VL 256/SME VL 256 ZA
8343 10:54:45.596646 # ok 6 getpid() SVE VL 256/SME VL 128 SM+ZA
8344 10:54:45.596793 # ok 7 getpid() SVE VL 256/SME VL 128 SM
8345 10:54:45.596922 # ok 8 getpid() SVE VL 256/SME VL 128 ZA
8346 10:54:45.597097 # ok 9 getpid() SVE VL 256/SME VL 64 SM+ZA
8347 10:54:45.597243 # ok 10 getpid() SVE VL 256/SME VL 64 SM
8348 10:54:45.597385 # ok 11 getpid() SVE VL 256/SME VL 64 ZA
8349 10:54:45.597569 # ok 12 getpid() SVE VL 256/SME VL 32 SM+ZA
8350 10:54:45.597759 # ok 13 getpid() SVE VL 256/SME VL 32 SM
8351 10:54:45.597960 # ok 14 getpid() SVE VL 256/SME VL 32 ZA
8352 10:54:45.598133 # ok 15 getpid() SVE VL 256/SME VL 16 SM+ZA
8353 10:54:45.598292 # ok 16 getpid() SVE VL 256/SME VL 16 SM
8354 10:54:45.598445 # ok 17 getpid() SVE VL 256/SME VL 16 ZA
8355 10:54:45.598582 # ok 18 getpid() SVE VL 240
8356 10:54:45.598739 # ok 19 getpid() SVE VL 240/SME VL 256 SM+ZA
8357 10:54:45.598889 # ok 20 getpid() SVE VL 240/SME VL 256 SM
8358 10:54:45.599039 # ok 21 getpid() SVE VL 240/SME VL 256 ZA
8359 10:54:45.599190 # ok 22 getpid() SVE VL 240/SME VL 128 SM+ZA
8360 10:54:45.599341 # ok 23 getpid() SVE VL 240/SME VL 128 SM
8361 10:54:45.599497 # ok 24 getpid() SVE VL 240/SME VL 128 ZA
8362 10:54:45.599619 # ok 25 getpid() SVE VL 240/SME VL 64 SM+ZA
8363 10:54:45.599734 # ok 26 getpid() SVE VL 240/SME VL 64 SM
8364 10:54:45.599878 # ok 27 getpid() SVE VL 240/SME VL 64 ZA
8365 10:54:45.599997 # ok 28 getpid() SVE VL 240/SME VL 32 SM+ZA
8366 10:54:45.600112 # ok 29 getpid() SVE VL 240/SME VL 32 SM
8367 10:54:45.600225 # ok 30 getpid() SVE VL 240/SME VL 32 ZA
8368 10:54:45.600338 # ok 31 getpid() SVE VL 240/SME VL 16 SM+ZA
8369 10:54:45.600451 # ok 32 getpid() SVE VL 240/SME VL 16 SM
8370 10:54:45.600564 # ok 33 getpid() SVE VL 240/SME VL 16 ZA
8371 10:54:45.600677 # ok 34 getpid() SVE VL 224
8372 10:54:45.600790 # ok 35 getpid() SVE VL 224/SME VL 256 SM+ZA
8373 10:54:45.600902 # ok 36 getpid() SVE VL 224/SME VL 256 SM
8374 10:54:45.601016 # ok 37 getpid() SVE VL 224/SME VL 256 ZA
8375 10:54:45.601129 # ok 38 getpid() SVE VL 224/SME VL 128 SM+ZA
8376 10:54:45.601242 # ok 39 getpid() SVE VL 224/SME VL 128 SM
8377 10:54:45.601355 # ok 40 getpid() SVE VL 224/SME VL 128 ZA
8378 10:54:45.604514 # ok 41 getpid() SVE VL 224/SME VL 64 SM+ZA
8379 10:54:45.604990 # ok 42 getpid() SVE VL 224/SME VL 64 SM
8380 10:54:45.605220 # ok 43 getpid() SVE VL 224/SME VL 64 ZA
8381 10:54:45.605386 # ok 44 getpid() SVE VL 224/SME VL 32 SM+ZA
8382 10:54:45.605543 # ok 45 getpid() SVE VL 224/SME VL 32 SM
8383 10:54:45.605787 # ok 46 getpid() SVE VL 224/SME VL 32 ZA
8384 10:54:45.605985 # ok 47 getpid() SVE VL 224/SME VL 16 SM+ZA
8385 10:54:45.606163 # ok 48 getpid() SVE VL 224/SME VL 16 SM
8386 10:54:45.606331 # ok 49 getpid() SVE VL 224/SME VL 16 ZA
8387 10:54:45.606510 # ok 50 getpid() SVE VL 208
8388 10:54:45.606693 # ok 51 getpid() SVE VL 208/SME VL 256 SM+ZA
8389 10:54:45.606852 # ok 52 getpid() SVE VL 208/SME VL 256 SM
8390 10:54:45.607001 # ok 53 getpid() SVE VL 208/SME VL 256 ZA
8391 10:54:45.607163 # ok 54 getpid() SVE VL 208/SME VL 128 SM+ZA
8392 10:54:45.607330 # ok 55 getpid() SVE VL 208/SME VL 128 SM
8393 10:54:45.607510 # ok 56 getpid() SVE VL 208/SME VL 128 ZA
8394 10:54:45.607659 # ok 57 getpid() SVE VL 208/SME VL 64 SM+ZA
8395 10:54:45.607782 # ok 58 getpid() SVE VL 208/SME VL 64 SM
8396 10:54:45.607900 # ok 59 getpid() SVE VL 208/SME VL 64 ZA
8397 10:54:45.608048 # ok 60 getpid() SVE VL 208/SME VL 32 SM+ZA
8398 10:54:45.608172 # ok 61 getpid() SVE VL 208/SME VL 32 SM
8399 10:54:45.608291 # ok 62 getpid() SVE VL 208/SME VL 32 ZA
8400 10:54:45.608408 # ok 63 getpid() SVE VL 208/SME VL 16 SM+ZA
8401 10:54:45.608525 # ok 64 getpid() SVE VL 208/SME VL 16 SM
8402 10:54:45.608645 # ok 65 getpid() SVE VL 208/SME VL 16 ZA
8403 10:54:45.608761 # ok 66 getpid() SVE VL 192
8404 10:54:45.611755 # ok 67 getpid() SVE VL 192/SME VL 256 SM+ZA
8405 10:54:45.611944 # ok 68 getpid() SVE VL 192/SME VL 256 SM
8406 10:54:45.612370 # ok 69 getpid() SVE VL 192/SME VL 256 ZA
8407 10:54:45.612585 # ok 70 getpid() SVE VL 192/SME VL 128 SM+ZA
8408 10:54:45.612816 # ok 71 getpid() SVE VL 192/SME VL 128 SM
8409 10:54:45.612997 # ok 72 getpid() SVE VL 192/SME VL 128 ZA
8410 10:54:45.613186 # ok 73 getpid() SVE VL 192/SME VL 64 SM+ZA
8411 10:54:45.613409 # ok 74 getpid() SVE VL 192/SME VL 64 SM
8412 10:54:45.613625 # ok 75 getpid() SVE VL 192/SME VL 64 ZA
8413 10:54:45.613876 # ok 76 getpid() SVE VL 192/SME VL 32 SM+ZA
8414 10:54:45.614071 # ok 77 getpid() SVE VL 192/SME VL 32 SM
8415 10:54:45.614278 # ok 78 getpid() SVE VL 192/SME VL 32 ZA
8416 10:54:45.614488 # ok 79 getpid() SVE VL 192/SME VL 16 SM+ZA
8417 10:54:45.614670 # ok 80 getpid() SVE VL 192/SME VL 16 SM
8418 10:54:45.614832 # ok 81 getpid() SVE VL 192/SME VL 16 ZA
8419 10:54:45.614983 # ok 82 getpid() SVE VL 176
8420 10:54:45.615103 # ok 83 getpid() SVE VL 176/SME VL 256 SM+ZA
8421 10:54:45.615219 # ok 84 getpid() SVE VL 176/SME VL 256 SM
8422 10:54:45.615369 # ok 85 getpid() SVE VL 176/SME VL 256 ZA
8423 10:54:45.615493 # ok 86 getpid() SVE VL 176/SME VL 128 SM+ZA
8424 10:54:45.615614 # ok 87 getpid() SVE VL 176/SME VL 128 SM
8425 10:54:45.615730 # ok 88 getpid() SVE VL 176/SME VL 128 ZA
8426 10:54:45.615848 # ok 89 getpid() SVE VL 176/SME VL 64 SM+ZA
8427 10:54:45.615964 # ok 90 getpid() SVE VL 176/SME VL 64 SM
8428 10:54:45.616081 # ok 91 getpid() SVE VL 176/SME VL 64 ZA
8429 10:54:45.616197 # ok 92 getpid() SVE VL 176/SME VL 32 SM+ZA
8430 10:54:45.616314 # ok 93 getpid() SVE VL 176/SME VL 32 SM
8431 10:54:45.616430 # ok 94 getpid() SVE VL 176/SME VL 32 ZA
8432 10:54:45.616546 # ok 95 getpid() SVE VL 176/SME VL 16 SM+ZA
8433 10:54:45.616662 # ok 96 getpid() SVE VL 176/SME VL 16 SM
8434 10:54:45.616775 # ok 97 getpid() SVE VL 176/SME VL 16 ZA
8435 10:54:45.616890 # ok 98 getpid() SVE VL 160
8436 10:54:48.407605 # ok 99 getpid() SVE VL 160/SME VL 256 SM+ZA
8437 10:54:48.408553 # ok 100 getpid() SVE VL 160/SME VL 256 SM
8438 10:54:48.409040 # ok 101 getpid() SVE VL 160/SME VL 256 ZA
8439 10:54:48.409245 # ok 102 getpid() SVE VL 160/SME VL 128 SM+ZA
8440 10:54:48.409996 # ok 103 getpid() SVE VL 160/SME VL 128 SM
8441 10:54:48.410155 # ok 104 getpid() SVE VL 160/SME VL 128 ZA
8442 10:54:48.410281 # ok 105 getpid() SVE VL 160/SME VL 64 SM+ZA
8443 10:54:48.410390 # ok 106 getpid() SVE VL 160/SME VL 64 SM
8444 10:54:48.410505 # ok 107 getpid() SVE VL 160/SME VL 64 ZA
8445 10:54:48.410633 # ok 108 getpid() SVE VL 160/SME VL 32 SM+ZA
8446 10:54:48.410766 # ok 109 getpid() SVE VL 160/SME VL 32 SM
8447 10:54:48.410897 # ok 110 getpid() SVE VL 160/SME VL 32 ZA
8448 10:54:48.411029 # ok 111 getpid() SVE VL 160/SME VL 16 SM+ZA
8449 10:54:48.411145 # ok 112 getpid() SVE VL 160/SME VL 16 SM
8450 10:54:48.411309 # ok 113 getpid() SVE VL 160/SME VL 16 ZA
8451 10:54:48.411436 # ok 114 getpid() SVE VL 144
8452 10:54:48.411579 # ok 115 getpid() SVE VL 144/SME VL 256 SM+ZA
8453 10:54:48.411706 # ok 116 getpid() SVE VL 144/SME VL 256 SM
8454 10:54:48.411817 # ok 117 getpid() SVE VL 144/SME VL 256 ZA
8455 10:54:48.411925 # ok 118 getpid() SVE VL 144/SME VL 128 SM+ZA
8456 10:54:48.412036 # ok 119 getpid() SVE VL 144/SME VL 128 SM
8457 10:54:48.412142 # ok 120 getpid() SVE VL 144/SME VL 128 ZA
8458 10:54:48.412248 # ok 121 getpid() SVE VL 144/SME VL 64 SM+ZA
8459 10:54:48.412351 # ok 122 getpid() SVE VL 144/SME VL 64 SM
8460 10:54:48.412457 # ok 123 getpid() SVE VL 144/SME VL 64 ZA
8461 10:54:48.412562 # ok 124 getpid() SVE VL 144/SME VL 32 SM+ZA
8462 10:54:48.412692 # ok 125 getpid() SVE VL 144/SME VL 32 SM
8463 10:54:48.412808 # ok 126 getpid() SVE VL 144/SME VL 32 ZA
8464 10:54:48.416408 # ok 127 getpid() SVE VL 144/SME VL 16 SM+ZA
8465 10:54:48.416792 # ok 128 getpid() SVE VL 144/SME VL 16 SM
8466 10:54:48.416883 # ok 129 getpid() SVE VL 144/SME VL 16 ZA
8467 10:54:48.416967 # ok 130 getpid() SVE VL 128
8468 10:54:48.417048 # ok 131 getpid() SVE VL 128/SME VL 256 SM+ZA
8469 10:54:48.417147 # ok 132 getpid() SVE VL 128/SME VL 256 SM
8470 10:54:48.417232 # ok 133 getpid() SVE VL 128/SME VL 256 ZA
8471 10:54:48.417329 # ok 134 getpid() SVE VL 128/SME VL 128 SM+ZA
8472 10:54:48.417415 # ok 135 getpid() SVE VL 128/SME VL 128 SM
8473 10:54:48.417510 # ok 136 getpid() SVE VL 128/SME VL 128 ZA
8474 10:54:48.417608 # ok 137 getpid() SVE VL 128/SME VL 64 SM+ZA
8475 10:54:48.417907 # ok 138 getpid() SVE VL 128/SME VL 64 SM
8476 10:54:48.417997 # ok 139 getpid() SVE VL 128/SME VL 64 ZA
8477 10:54:48.418095 # ok 140 getpid() SVE VL 128/SME VL 32 SM+ZA
8478 10:54:48.418180 # ok 141 getpid() SVE VL 128/SME VL 32 SM
8479 10:54:48.418281 # ok 142 getpid() SVE VL 128/SME VL 32 ZA
8480 10:54:48.418366 # ok 143 getpid() SVE VL 128/SME VL 16 SM+ZA
8481 10:54:48.418648 # ok 144 getpid() SVE VL 128/SME VL 16 SM
8482 10:54:48.418737 # ok 145 getpid() SVE VL 128/SME VL 16 ZA
8483 10:54:48.418819 # ok 146 getpid() SVE VL 112
8484 10:54:48.419106 # ok 147 getpid() SVE VL 112/SME VL 256 SM+ZA
8485 10:54:48.419198 # ok 148 getpid() SVE VL 112/SME VL 256 SM
8486 10:54:48.419297 # ok 149 getpid() SVE VL 112/SME VL 256 ZA
8487 10:54:48.419453 # ok 150 getpid() SVE VL 112/SME VL 128 SM+ZA
8488 10:54:48.420373 # ok 151 getpid() SVE VL 112/SME VL 128 SM
8489 10:54:48.424900 # ok 152 getpid() SVE VL 112/SME VL 128 ZA
8490 10:54:48.425323 # ok 153 getpid() SVE VL 112/SME VL 64 SM+ZA
8491 10:54:48.425410 # ok 154 getpid() SVE VL 112/SME VL 64 SM
8492 10:54:48.425488 # ok 155 getpid() SVE VL 112/SME VL 64 ZA
8493 10:54:48.425576 # ok 156 getpid() SVE VL 112/SME VL 32 SM+ZA
8494 10:54:48.425676 # ok 157 getpid() SVE VL 112/SME VL 32 SM
8495 10:54:48.425752 # ok 158 getpid() SVE VL 112/SME VL 32 ZA
8496 10:54:48.425839 # ok 159 getpid() SVE VL 112/SME VL 16 SM+ZA
8497 10:54:48.426111 # ok 160 getpid() SVE VL 112/SME VL 16 SM
8498 10:54:48.426196 # ok 161 getpid() SVE VL 112/SME VL 16 ZA
8499 10:54:48.426284 # ok 162 getpid() SVE VL 96
8500 10:54:48.426370 # ok 163 getpid() SVE VL 96/SME VL 256 SM+ZA
8501 10:54:48.426632 # ok 164 getpid() SVE VL 96/SME VL 256 SM
8502 10:54:48.426713 # ok 165 getpid() SVE VL 96/SME VL 256 ZA
8503 10:54:48.426798 # ok 166 getpid() SVE VL 96/SME VL 128 SM+ZA
8504 10:54:48.426886 # ok 167 getpid() SVE VL 96/SME VL 128 SM
8505 10:54:48.426978 # ok 168 getpid() SVE VL 96/SME VL 128 ZA
8506 10:54:48.427253 # ok 169 getpid() SVE VL 96/SME VL 64 SM+ZA
8507 10:54:48.427357 # ok 170 getpid() SVE VL 96/SME VL 64 SM
8508 10:54:48.427439 # ok 171 getpid() SVE VL 96/SME VL 64 ZA
8509 10:54:48.427532 # ok 172 getpid() SVE VL 96/SME VL 32 SM+ZA
8510 10:54:48.436085 # ok 173 getpid() SVE VL 96/SME VL 32 SM
8511 10:54:48.436302 # ok 174 getpid() SVE VL 96/SME VL 32 ZA
8512 10:54:48.436386 # ok 175 getpid() SVE VL 96/SME VL 16 SM+ZA
8513 10:54:48.436484 # ok 176 getpid() SVE VL 96/SME VL 16 SM
8514 10:54:48.436568 # ok 177 getpid() SVE VL 96/SME VL 16 ZA
8515 10:54:48.436649 # ok 178 getpid() SVE VL 80
8516 10:54:48.436729 # ok 179 getpid() SVE VL 80/SME VL 256 SM+ZA
8517 10:54:48.436809 # ok 180 getpid() SVE VL 80/SME VL 256 SM
8518 10:54:48.436905 # ok 181 getpid() SVE VL 80/SME VL 256 ZA
8519 10:54:48.436988 # ok 182 getpid() SVE VL 80/SME VL 128 SM+ZA
8520 10:54:48.437069 # ok 183 getpid() SVE VL 80/SME VL 128 SM
8521 10:54:48.437149 # ok 184 getpid() SVE VL 80/SME VL 128 ZA
8522 10:54:48.437229 # ok 185 getpid() SVE VL 80/SME VL 64 SM+ZA
8523 10:54:48.437323 # ok 186 getpid() SVE VL 80/SME VL 64 SM
8524 10:54:48.437401 # ok 187 getpid() SVE VL 80/SME VL 64 ZA
8525 10:54:48.437477 # ok 188 getpid() SVE VL 80/SME VL 32 SM+ZA
8526 10:54:48.437552 # ok 189 getpid() SVE VL 80/SME VL 32 SM
8527 10:54:48.437625 # ok 190 getpid() SVE VL 80/SME VL 32 ZA
8528 10:54:48.437723 # ok 191 getpid() SVE VL 80/SME VL 16 SM+ZA
8529 10:54:48.437800 # ok 192 getpid() SVE VL 80/SME VL 16 SM
8530 10:54:48.437873 # ok 193 getpid() SVE VL 80/SME VL 16 ZA
8531 10:54:48.437947 # ok 194 getpid() SVE VL 64
8532 10:54:48.438020 # ok 195 getpid() SVE VL 64/SME VL 256 SM+ZA
8533 10:54:51.024620 # ok 196 getpid() SVE VL 64/SME VL 256 SM
8534 10:54:51.025191 # ok 197 getpid() SVE VL 64/SME VL 256 ZA
8535 10:54:51.025401 # ok 198 getpid() SVE VL 64/SME VL 128 SM+ZA
8536 10:54:51.025580 # ok 199 getpid() SVE VL 64/SME VL 128 SM
8537 10:54:51.025780 # ok 200 getpid() SVE VL 64/SME VL 128 ZA
8538 10:54:51.025973 # ok 201 getpid() SVE VL 64/SME VL 64 SM+ZA
8539 10:54:51.026201 # ok 202 getpid() SVE VL 64/SME VL 64 SM
8540 10:54:51.026410 # ok 203 getpid() SVE VL 64/SME VL 64 ZA
8541 10:54:51.026570 # ok 204 getpid() SVE VL 64/SME VL 32 SM+ZA
8542 10:54:51.026716 # ok 205 getpid() SVE VL 64/SME VL 32 SM
8543 10:54:51.026870 # ok 206 getpid() SVE VL 64/SME VL 32 ZA
8544 10:54:51.027029 # ok 207 getpid() SVE VL 64/SME VL 16 SM+ZA
8545 10:54:51.027188 # ok 208 getpid() SVE VL 64/SME VL 16 SM
8546 10:54:51.027334 # ok 209 getpid() SVE VL 64/SME VL 16 ZA
8547 10:54:51.027534 # ok 210 getpid() SVE VL 48
8548 10:54:51.027712 # ok 211 getpid() SVE VL 48/SME VL 256 SM+ZA
8549 10:54:51.027836 # ok 212 getpid() SVE VL 48/SME VL 256 SM
8550 10:54:51.027951 # ok 213 getpid() SVE VL 48/SME VL 256 ZA
8551 10:54:51.028066 # ok 214 getpid() SVE VL 48/SME VL 128 SM+ZA
8552 10:54:51.028180 # ok 215 getpid() SVE VL 48/SME VL 128 SM
8553 10:54:51.028292 # ok 216 getpid() SVE VL 48/SME VL 128 ZA
8554 10:54:51.028404 # ok 217 getpid() SVE VL 48/SME VL 64 SM+ZA
8555 10:54:51.028516 # ok 218 getpid() SVE VL 48/SME VL 64 SM
8556 10:54:51.028629 # ok 219 getpid() SVE VL 48/SME VL 64 ZA
8557 10:54:51.028741 # ok 220 getpid() SVE VL 48/SME VL 32 SM+ZA
8558 10:54:51.028851 # ok 221 getpid() SVE VL 48/SME VL 32 SM
8559 10:54:51.028963 # ok 222 getpid() SVE VL 48/SME VL 32 ZA
8560 10:54:51.029074 # ok 223 getpid() SVE VL 48/SME VL 16 SM+ZA
8561 10:54:51.032027 # ok 224 getpid() SVE VL 48/SME VL 16 SM
8562 10:54:51.032339 # ok 225 getpid() SVE VL 48/SME VL 16 ZA
8563 10:54:51.032446 # ok 226 getpid() SVE VL 32
8564 10:54:51.032533 # ok 227 getpid() SVE VL 32/SME VL 256 SM+ZA
8565 10:54:51.032615 # ok 228 getpid() SVE VL 32/SME VL 256 SM
8566 10:54:51.032713 # ok 229 getpid() SVE VL 32/SME VL 256 ZA
8567 10:54:51.032795 # ok 230 getpid() SVE VL 32/SME VL 128 SM+ZA
8568 10:54:51.032878 # ok 231 getpid() SVE VL 32/SME VL 128 SM
8569 10:54:51.032972 # ok 232 getpid() SVE VL 32/SME VL 128 ZA
8570 10:54:51.033051 # ok 233 getpid() SVE VL 32/SME VL 64 SM+ZA
8571 10:54:51.033128 # ok 234 getpid() SVE VL 32/SME VL 64 SM
8572 10:54:51.033221 # ok 235 getpid() SVE VL 32/SME VL 64 ZA
8573 10:54:51.033304 # ok 236 getpid() SVE VL 32/SME VL 32 SM+ZA
8574 10:54:51.033386 # ok 237 getpid() SVE VL 32/SME VL 32 SM
8575 10:54:51.033482 # ok 238 getpid() SVE VL 32/SME VL 32 ZA
8576 10:54:51.033568 # ok 239 getpid() SVE VL 32/SME VL 16 SM+ZA
8577 10:54:51.033676 # ok 240 getpid() SVE VL 32/SME VL 16 SM
8578 10:54:51.033770 # ok 241 getpid() SVE VL 32/SME VL 16 ZA
8579 10:54:51.033864 # ok 242 getpid() SVE VL 16
8580 10:54:51.034174 # ok 243 getpid() SVE VL 16/SME VL 256 SM+ZA
8581 10:54:51.034337 # ok 244 getpid() SVE VL 16/SME VL 256 SM
8582 10:54:51.034497 # ok 245 getpid() SVE VL 16/SME VL 256 ZA
8583 10:54:51.034693 # ok 246 getpid() SVE VL 16/SME VL 128 SM+ZA
8584 10:54:51.034883 # ok 247 getpid() SVE VL 16/SME VL 128 SM
8585 10:54:51.035039 # ok 248 getpid() SVE VL 16/SME VL 128 ZA
8586 10:54:51.035215 # ok 249 getpid() SVE VL 16/SME VL 64 SM+ZA
8587 10:54:51.035420 # ok 250 getpid() SVE VL 16/SME VL 64 SM
8588 10:54:51.035566 # ok 251 getpid() SVE VL 16/SME VL 64 ZA
8589 10:54:51.035710 # ok 252 getpid() SVE VL 16/SME VL 32 SM+ZA
8590 10:54:51.035853 # ok 253 getpid() SVE VL 16/SME VL 32 SM
8591 10:54:51.035995 # ok 254 getpid() SVE VL 16/SME VL 32 ZA
8592 10:54:51.039921 # ok 255 getpid() SVE VL 16/SME VL 16 SM+ZA
8593 10:54:51.040336 # ok 256 getpid() SVE VL 16/SME VL 16 SM
8594 10:54:51.040521 # ok 257 getpid() SVE VL 16/SME VL 16 ZA
8595 10:54:51.040694 # ok 258 sched_yield() FPSIMD
8596 10:54:51.040849 # ok 259 sched_yield() SVE VL 256
8597 10:54:51.041045 # ok 260 sched_yield() SVE VL 256/SME VL 256 SM+ZA
8598 10:54:51.041209 # ok 261 sched_yield() SVE VL 256/SME VL 256 SM
8599 10:54:51.041366 # ok 262 sched_yield() SVE VL 256/SME VL 256 ZA
8600 10:54:51.041514 # ok 263 sched_yield() SVE VL 256/SME VL 128 SM+ZA
8601 10:54:51.041665 # ok 264 sched_yield() SVE VL 256/SME VL 128 SM
8602 10:54:51.041827 # ok 265 sched_yield() SVE VL 256/SME VL 128 ZA
8603 10:54:51.042018 # ok 266 sched_yield() SVE VL 256/SME VL 64 SM+ZA
8604 10:54:51.042186 # ok 267 sched_yield() SVE VL 256/SME VL 64 SM
8605 10:54:51.042352 # ok 268 sched_yield() SVE VL 256/SME VL 64 ZA
8606 10:54:51.042519 # ok 269 sched_yield() SVE VL 256/SME VL 32 SM+ZA
8607 10:54:51.042684 # ok 270 sched_yield() SVE VL 256/SME VL 32 SM
8608 10:54:51.042843 # ok 271 sched_yield() SVE VL 256/SME VL 32 ZA
8609 10:54:51.042998 # ok 272 sched_yield() SVE VL 256/SME VL 16 SM+ZA
8610 10:54:51.043145 # ok 273 sched_yield() SVE VL 256/SME VL 16 SM
8611 10:54:51.043345 # ok 274 sched_yield() SVE VL 256/SME VL 16 ZA
8612 10:54:51.043522 # ok 275 sched_yield() SVE VL 240
8613 10:54:51.043687 # ok 276 sched_yield() SVE VL 240/SME VL 256 SM+ZA
8614 10:54:51.043851 # ok 277 sched_yield() SVE VL 240/SME VL 256 SM
8615 10:54:51.043984 # ok 278 sched_yield() SVE VL 240/SME VL 256 ZA
8616 10:54:51.044100 # ok 279 sched_yield() SVE VL 240/SME VL 128 SM+ZA
8617 10:54:51.044215 # ok 280 sched_yield() SVE VL 240/SME VL 128 SM
8618 10:54:51.044328 # ok 281 sched_yield() SVE VL 240/SME VL 128 ZA
8619 10:54:51.044441 # ok 282 sched_yield() SVE VL 240/SME VL 64 SM+ZA
8620 10:54:51.044555 # ok 283 sched_yield() SVE VL 240/SME VL 64 SM
8621 10:54:51.044668 # ok 284 sched_yield() SVE VL 240/SME VL 64 ZA
8622 10:54:51.044811 # ok 285 sched_yield() SVE VL 240/SME VL 32 SM+ZA
8623 10:54:51.044933 # ok 286 sched_yield() SVE VL 240/SME VL 32 SM
8624 10:54:51.045047 # ok 287 sched_yield() SVE VL 240/SME VL 32 ZA
8625 10:54:51.045160 # ok 288 sched_yield() SVE VL 240/SME VL 16 SM+ZA
8626 10:54:51.045275 # ok 289 sched_yield() SVE VL 240/SME VL 16 SM
8627 10:54:53.421973 # ok 290 sched_yield() SVE VL 240/SME VL 16 ZA
8628 10:54:53.422566 # ok 291 sched_yield() SVE VL 224
8629 10:54:53.422784 # ok 292 sched_yield() SVE VL 224/SME VL 256 SM+ZA
8630 10:54:53.422973 # ok 293 sched_yield() SVE VL 224/SME VL 256 SM
8631 10:54:53.423155 # ok 294 sched_yield() SVE VL 224/SME VL 256 ZA
8632 10:54:53.423360 # ok 295 sched_yield() SVE VL 224/SME VL 128 SM+ZA
8633 10:54:53.423523 # ok 296 sched_yield() SVE VL 224/SME VL 128 SM
8634 10:54:53.423680 # ok 297 sched_yield() SVE VL 224/SME VL 128 ZA
8635 10:54:53.423836 # ok 298 sched_yield() SVE VL 224/SME VL 64 SM+ZA
8636 10:54:53.423993 # ok 299 sched_yield() SVE VL 224/SME VL 64 SM
8637 10:54:53.424148 # ok 300 sched_yield() SVE VL 224/SME VL 64 ZA
8638 10:54:53.424304 # ok 301 sched_yield() SVE VL 224/SME VL 32 SM+ZA
8639 10:54:53.424459 # ok 302 sched_yield() SVE VL 224/SME VL 32 SM
8640 10:54:53.424614 # ok 303 sched_yield() SVE VL 224/SME VL 32 ZA
8641 10:54:53.424806 # ok 304 sched_yield() SVE VL 224/SME VL 16 SM+ZA
8642 10:54:53.424966 # ok 305 sched_yield() SVE VL 224/SME VL 16 SM
8643 10:54:53.425121 # ok 306 sched_yield() SVE VL 224/SME VL 16 ZA
8644 10:54:53.425276 # ok 307 sched_yield() SVE VL 208
8645 10:54:53.425430 # ok 308 sched_yield() SVE VL 208/SME VL 256 SM+ZA
8646 10:54:53.425588 # ok 309 sched_yield() SVE VL 208/SME VL 256 SM
8647 10:54:53.425760 # ok 310 sched_yield() SVE VL 208/SME VL 256 ZA
8648 10:54:53.425910 # ok 311 sched_yield() SVE VL 208/SME VL 128 SM+ZA
8649 10:54:53.426051 # ok 312 sched_yield() SVE VL 208/SME VL 128 SM
8650 10:54:53.426206 # ok 313 sched_yield() SVE VL 208/SME VL 128 ZA
8651 10:54:53.426406 # ok 314 sched_yield() SVE VL 208/SME VL 64 SM+ZA
8652 10:54:53.426595 # ok 315 sched_yield() SVE VL 208/SME VL 64 SM
8653 10:54:53.426773 # ok 316 sched_yield() SVE VL 208/SME VL 64 ZA
8654 10:54:53.426949 # ok 317 sched_yield() SVE VL 208/SME VL 32 SM+ZA
8655 10:54:53.427129 # ok 318 sched_yield() SVE VL 208/SME VL 32 SM
8656 10:54:53.427300 # ok 319 sched_yield() SVE VL 208/SME VL 32 ZA
8657 10:54:53.427487 # ok 320 sched_yield() SVE VL 208/SME VL 16 SM+ZA
8658 10:54:53.427614 # ok 321 sched_yield() SVE VL 208/SME VL 16 SM
8659 10:54:53.427729 # ok 322 sched_yield() SVE VL 208/SME VL 16 ZA
8660 10:54:53.427842 # ok 323 sched_yield() SVE VL 192
8661 10:54:53.427954 # ok 324 sched_yield() SVE VL 192/SME VL 256 SM+ZA
8662 10:54:53.428066 # ok 325 sched_yield() SVE VL 192/SME VL 256 SM
8663 10:54:53.428178 # ok 326 sched_yield() SVE VL 192/SME VL 256 ZA
8664 10:54:53.428295 # ok 327 sched_yield() SVE VL 192/SME VL 128 SM+ZA
8665 10:54:53.428409 # ok 328 sched_yield() SVE VL 192/SME VL 128 SM
8666 10:54:53.428554 # ok 329 sched_yield() SVE VL 192/SME VL 128 ZA
8667 10:54:53.428674 # ok 330 sched_yield() SVE VL 192/SME VL 64 SM+ZA
8668 10:54:53.428998 # ok 331 sched_yield() SVE VL 192/SME VL 64 SM
8669 10:54:53.429122 # ok 332 sched_yield() SVE VL 192/SME VL 64 ZA
8670 10:54:53.429236 # ok 333 sched_yield() SVE VL 192/SME VL 32 SM+ZA
8671 10:54:53.429350 # ok 334 sched_yield() SVE VL 192/SME VL 32 SM
8672 10:54:53.429464 # ok 335 sched_yield() SVE VL 192/SME VL 32 ZA
8673 10:54:53.435903 # ok 336 sched_yield() SVE VL 192/SME VL 16 SM+ZA
8674 10:54:53.436469 # ok 337 sched_yield() SVE VL 192/SME VL 16 SM
8675 10:54:53.436685 # ok 338 sched_yield() SVE VL 192/SME VL 16 ZA
8676 10:54:53.436840 # ok 339 sched_yield() SVE VL 176
8677 10:54:53.436997 # ok 340 sched_yield() SVE VL 176/SME VL 256 SM+ZA
8678 10:54:53.437156 # ok 341 sched_yield() SVE VL 176/SME VL 256 SM
8679 10:54:53.437345 # ok 342 sched_yield() SVE VL 176/SME VL 256 ZA
8680 10:54:53.437596 # ok 343 sched_yield() SVE VL 176/SME VL 128 SM+ZA
8681 10:54:53.437783 # ok 344 sched_yield() SVE VL 176/SME VL 128 SM
8682 10:54:53.437950 # ok 345 sched_yield() SVE VL 176/SME VL 128 ZA
8683 10:54:53.438111 # ok 346 sched_yield() SVE VL 176/SME VL 64 SM+ZA
8684 10:54:53.438313 # ok 347 sched_yield() SVE VL 176/SME VL 64 SM
8685 10:54:53.438496 # ok 348 sched_yield() SVE VL 176/SME VL 64 ZA
8686 10:54:53.438659 # ok 349 sched_yield() SVE VL 176/SME VL 32 SM+ZA
8687 10:54:53.438850 # ok 350 sched_yield() SVE VL 176/SME VL 32 SM
8688 10:54:53.439066 # ok 351 sched_yield() SVE VL 176/SME VL 32 ZA
8689 10:54:53.439244 # ok 352 sched_yield() SVE VL 176/SME VL 16 SM+ZA
8690 10:54:53.439449 # ok 353 sched_yield() SVE VL 176/SME VL 16 SM
8691 10:54:53.439590 # ok 354 sched_yield() SVE VL 176/SME VL 16 ZA
8692 10:54:53.439713 # ok 355 sched_yield() SVE VL 160
8693 10:54:53.439836 # ok 356 sched_yield() SVE VL 160/SME VL 256 SM+ZA
8694 10:54:53.440007 # ok 357 sched_yield() SVE VL 160/SME VL 256 SM
8695 10:54:53.440170 # ok 358 sched_yield() SVE VL 160/SME VL 256 ZA
8696 10:54:53.440317 # ok 359 sched_yield() SVE VL 160/SME VL 128 SM+ZA
8697 10:54:53.440457 # ok 360 sched_yield() SVE VL 160/SME VL 128 SM
8698 10:54:53.440577 # ok 361 sched_yield() SVE VL 160/SME VL 128 ZA
8699 10:54:53.440694 # ok 362 sched_yield() SVE VL 160/SME VL 64 SM+ZA
8700 10:54:53.440807 # ok 363 sched_yield() SVE VL 160/SME VL 64 SM
8701 10:54:53.440918 # ok 364 sched_yield() SVE VL 160/SME VL 64 ZA
8702 10:54:53.441029 # ok 365 sched_yield() SVE VL 160/SME VL 32 SM+ZA
8703 10:54:53.441142 # ok 366 sched_yield() SVE VL 160/SME VL 32 SM
8704 10:54:53.441286 # ok 367 sched_yield() SVE VL 160/SME VL 32 ZA
8705 10:54:53.441405 # ok 368 sched_yield() SVE VL 160/SME VL 16 SM+ZA
8706 10:54:53.441518 # ok 369 sched_yield() SVE VL 160/SME VL 16 SM
8707 10:54:53.441631 # ok 370 sched_yield() SVE VL 160/SME VL 16 ZA
8708 10:54:53.444520 # ok 371 sched_yield() SVE VL 144
8709 10:54:53.444706 # ok 372 sched_yield() SVE VL 144/SME VL 256 SM+ZA
8710 10:54:53.444812 # ok 373 sched_yield() SVE VL 144/SME VL 256 SM
8711 10:54:53.444898 # ok 374 sched_yield() SVE VL 144/SME VL 256 ZA
8712 10:54:53.444996 # ok 375 sched_yield() SVE VL 144/SME VL 128 SM+ZA
8713 10:54:53.445081 # ok 376 sched_yield() SVE VL 144/SME VL 128 SM
8714 10:54:55.854999 # ok 377 sched_yield() SVE VL 144/SME VL 128 ZA
8715 10:54:55.855408 # ok 378 sched_yield() SVE VL 144/SME VL 64 SM+ZA
8716 10:54:55.855495 # ok 379 sched_yield() SVE VL 144/SME VL 64 SM
8717 10:54:55.855575 # ok 380 sched_yield() SVE VL 144/SME VL 64 ZA
8718 10:54:55.856431 # ok 381 sched_yield() SVE VL 144/SME VL 32 SM+ZA
8719 10:54:55.856537 # ok 382 sched_yield() SVE VL 144/SME VL 32 SM
8720 10:54:55.856835 # ok 383 sched_yield() SVE VL 144/SME VL 32 ZA
8721 10:54:55.856940 # ok 384 sched_yield() SVE VL 144/SME VL 16 SM+ZA
8722 10:54:55.857030 # ok 385 sched_yield() SVE VL 144/SME VL 16 SM
8723 10:54:55.857131 # ok 386 sched_yield() SVE VL 144/SME VL 16 ZA
8724 10:54:55.857216 # ok 387 sched_yield() SVE VL 128
8725 10:54:55.857314 # ok 388 sched_yield() SVE VL 128/SME VL 256 SM+ZA
8726 10:54:55.857413 # ok 389 sched_yield() SVE VL 128/SME VL 256 SM
8727 10:54:55.857512 # ok 390 sched_yield() SVE VL 128/SME VL 256 ZA
8728 10:54:55.857817 # ok 391 sched_yield() SVE VL 128/SME VL 128 SM+ZA
8729 10:54:55.857923 # ok 392 sched_yield() SVE VL 128/SME VL 128 SM
8730 10:54:55.858023 # ok 393 sched_yield() SVE VL 128/SME VL 128 ZA
8731 10:54:55.858129 # ok 394 sched_yield() SVE VL 128/SME VL 64 SM+ZA
8732 10:54:55.858432 # ok 395 sched_yield() SVE VL 128/SME VL 64 SM
8733 10:54:55.858536 # ok 396 sched_yield() SVE VL 128/SME VL 64 ZA
8734 10:54:55.858639 # ok 397 sched_yield() SVE VL 128/SME VL 32 SM+ZA
8735 10:54:55.858739 # ok 398 sched_yield() SVE VL 128/SME VL 32 SM
8736 10:54:55.858839 # ok 399 sched_yield() SVE VL 128/SME VL 32 ZA
8737 10:54:55.859136 # ok 400 sched_yield() SVE VL 128/SME VL 16 SM+ZA
8738 10:54:55.859239 # ok 401 sched_yield() SVE VL 128/SME VL 16 SM
8739 10:54:55.859340 # ok 402 sched_yield() SVE VL 128/SME VL 16 ZA
8740 10:54:55.859443 # ok 403 sched_yield() SVE VL 112
8741 10:54:55.859526 # ok 404 sched_yield() SVE VL 112/SME VL 256 SM+ZA
8742 10:54:55.863981 # ok 405 sched_yield() SVE VL 112/SME VL 256 SM
8743 10:54:55.864285 # ok 406 sched_yield() SVE VL 112/SME VL 256 ZA
8744 10:54:55.864396 # ok 407 sched_yield() SVE VL 112/SME VL 128 SM+ZA
8745 10:54:55.864503 # ok 408 sched_yield() SVE VL 112/SME VL 128 SM
8746 10:54:55.864587 # ok 409 sched_yield() SVE VL 112/SME VL 128 ZA
8747 10:54:55.864680 # ok 410 sched_yield() SVE VL 112/SME VL 64 SM+ZA
8748 10:54:55.864774 # ok 411 sched_yield() SVE VL 112/SME VL 64 SM
8749 10:54:55.864922 # ok 412 sched_yield() SVE VL 112/SME VL 64 ZA
8750 10:54:55.865186 # ok 413 sched_yield() SVE VL 112/SME VL 32 SM+ZA
8751 10:54:55.865415 # ok 414 sched_yield() SVE VL 112/SME VL 32 SM
8752 10:54:55.865590 # ok 415 sched_yield() SVE VL 112/SME VL 32 ZA
8753 10:54:55.865858 # ok 416 sched_yield() SVE VL 112/SME VL 16 SM+ZA
8754 10:54:55.866009 # ok 417 sched_yield() SVE VL 112/SME VL 16 SM
8755 10:54:55.866156 # ok 418 sched_yield() SVE VL 112/SME VL 16 ZA
8756 10:54:55.866309 # ok 419 sched_yield() SVE VL 96
8757 10:54:55.866488 # ok 420 sched_yield() SVE VL 96/SME VL 256 SM+ZA
8758 10:54:55.866651 # ok 421 sched_yield() SVE VL 96/SME VL 256 SM
8759 10:54:55.866814 # ok 422 sched_yield() SVE VL 96/SME VL 256 ZA
8760 10:54:55.867009 # ok 423 sched_yield() SVE VL 96/SME VL 128 SM+ZA
8761 10:54:55.867157 # ok 424 sched_yield() SVE VL 96/SME VL 128 SM
8762 10:54:55.867316 # ok 425 sched_yield() SVE VL 96/SME VL 128 ZA
8763 10:54:55.867465 # ok 426 sched_yield() SVE VL 96/SME VL 64 SM+ZA
8764 10:54:55.867585 # ok 427 sched_yield() SVE VL 96/SME VL 64 SM
8765 10:54:55.867699 # ok 428 sched_yield() SVE VL 96/SME VL 64 ZA
8766 10:54:55.867840 # ok 429 sched_yield() SVE VL 96/SME VL 32 SM+ZA
8767 10:54:55.867958 # ok 430 sched_yield() SVE VL 96/SME VL 32 SM
8768 10:54:55.868072 # ok 431 sched_yield() SVE VL 96/SME VL 32 ZA
8769 10:54:55.868186 # ok 432 sched_yield() SVE VL 96/SME VL 16 SM+ZA
8770 10:54:55.871994 # ok 433 sched_yield() SVE VL 96/SME VL 16 SM
8771 10:54:55.872356 # ok 434 sched_yield() SVE VL 96/SME VL 16 ZA
8772 10:54:55.872458 # ok 435 sched_yield() SVE VL 80
8773 10:54:55.872563 # ok 436 sched_yield() SVE VL 80/SME VL 256 SM+ZA
8774 10:54:55.872650 # ok 437 sched_yield() SVE VL 80/SME VL 256 SM
8775 10:54:55.872749 # ok 438 sched_yield() SVE VL 80/SME VL 256 ZA
8776 10:54:55.872834 # ok 439 sched_yield() SVE VL 80/SME VL 128 SM+ZA
8777 10:54:55.872930 # ok 440 sched_yield() SVE VL 80/SME VL 128 SM
8778 10:54:55.873225 # ok 441 sched_yield() SVE VL 80/SME VL 128 ZA
8779 10:54:55.873328 # ok 442 sched_yield() SVE VL 80/SME VL 64 SM+ZA
8780 10:54:55.873430 # ok 443 sched_yield() SVE VL 80/SME VL 64 SM
8781 10:54:55.873518 # ok 444 sched_yield() SVE VL 80/SME VL 64 ZA
8782 10:54:55.873621 # ok 445 sched_yield() SVE VL 80/SME VL 32 SM+ZA
8783 10:54:55.873732 # ok 446 sched_yield() SVE VL 80/SME VL 32 SM
8784 10:54:55.873834 # ok 447 sched_yield() SVE VL 80/SME VL 32 ZA
8785 10:54:55.874128 # ok 448 sched_yield() SVE VL 80/SME VL 16 SM+ZA
8786 10:54:55.874247 # ok 449 sched_yield() SVE VL 80/SME VL 16 SM
8787 10:54:55.874335 # ok 450 sched_yield() SVE VL 80/SME VL 16 ZA
8788 10:54:55.874433 # ok 451 sched_yield() SVE VL 64
8789 10:54:55.874532 # ok 452 sched_yield() SVE VL 64/SME VL 256 SM+ZA
8790 10:54:55.874633 # ok 453 sched_yield() SVE VL 64/SME VL 256 SM
8791 10:54:55.874938 # ok 454 sched_yield() SVE VL 64/SME VL 256 ZA
8792 10:54:55.875059 # ok 455 sched_yield() SVE VL 64/SME VL 128 SM+ZA
8793 10:54:55.875151 # ok 456 sched_yield() SVE VL 64/SME VL 128 SM
8794 10:54:55.875253 # ok 457 sched_yield() SVE VL 64/SME VL 128 ZA
8795 10:54:55.875353 # ok 458 sched_yield() SVE VL 64/SME VL 64 SM+ZA
8796 10:54:55.879926 # ok 459 sched_yield() SVE VL 64/SME VL 64 SM
8797 10:54:55.880300 # ok 460 sched_yield() SVE VL 64/SME VL 64 ZA
8798 10:54:55.880406 # ok 461 sched_yield() SVE VL 64/SME VL 32 SM+ZA
8799 10:54:55.880495 # ok 462 sched_yield() SVE VL 64/SME VL 32 SM
8800 10:54:55.880594 # ok 463 sched_yield() SVE VL 64/SME VL 32 ZA
8801 10:54:56.647068 # ok 464 sched_yield() SVE VL 64/SME VL 16 SM+ZA
8802 10:54:56.647327 # ok 465 sched_yield() SVE VL 64/SME VL 16 SM
8803 10:54:56.647641 # ok 466 sched_yield() SVE VL 64/SME VL 16 ZA
8804 10:54:56.647744 # ok 467 sched_yield() SVE VL 48
8805 10:54:56.647832 # ok 468 sched_yield() SVE VL 48/SME VL 256 SM+ZA
8806 10:54:56.647918 # ok 469 sched_yield() SVE VL 48/SME VL 256 SM
8807 10:54:56.649420 # ok 470 sched_yield() SVE VL 48/SME VL 256 ZA
8808 10:54:56.649858 # ok 471 sched_yield() SVE VL 48/SME VL 128 SM+ZA
8809 10:54:56.649968 # ok 472 sched_yield() SVE VL 48/SME VL 128 SM
8810 10:54:56.650058 # ok 473 sched_yield() SVE VL 48/SME VL 128 ZA
8811 10:54:56.650161 # ok 474 sched_yield() SVE VL 48/SME VL 64 SM+ZA
8812 10:54:56.650249 # ok 475 sched_yield() SVE VL 48/SME VL 64 SM
8813 10:54:56.650331 # ok 476 sched_yield() SVE VL 48/SME VL 64 ZA
8814 10:54:56.650566 # ok 477 sched_yield() SVE VL 48/SME VL 32 SM+ZA
8815 10:54:56.650672 # ok 478 sched_yield() SVE VL 48/SME VL 32 SM
8816 10:54:56.650776 # ok 479 sched_yield() SVE VL 48/SME VL 32 ZA
8817 10:54:56.650879 # ok 480 sched_yield() SVE VL 48/SME VL 16 SM+ZA
8818 10:54:56.650967 # ok 481 sched_yield() SVE VL 48/SME VL 16 SM
8819 10:54:56.651267 # ok 482 sched_yield() SVE VL 48/SME VL 16 ZA
8820 10:54:56.651421 # ok 483 sched_yield() SVE VL 32
8821 10:54:56.651535 # ok 484 sched_yield() SVE VL 32/SME VL 256 SM+ZA
8822 10:54:56.651629 # ok 485 sched_yield() SVE VL 32/SME VL 256 SM
8823 10:54:56.659082 # ok 486 sched_yield() SVE VL 32/SME VL 256 ZA
8824 10:54:56.659322 # ok 487 sched_yield() SVE VL 32/SME VL 128 SM+ZA
8825 10:54:56.659412 # ok 488 sched_yield() SVE VL 32/SME VL 128 SM
8826 10:54:56.659711 # ok 489 sched_yield() SVE VL 32/SME VL 128 ZA
8827 10:54:56.659813 # ok 490 sched_yield() SVE VL 32/SME VL 64 SM+ZA
8828 10:54:56.659899 # ok 491 sched_yield() SVE VL 32/SME VL 64 SM
8829 10:54:56.659985 # ok 492 sched_yield() SVE VL 32/SME VL 64 ZA
8830 10:54:56.660284 # ok 493 sched_yield() SVE VL 32/SME VL 32 SM+ZA
8831 10:54:56.660626 # ok 494 sched_yield() SVE VL 32/SME VL 32 SM
8832 10:54:56.660837 # ok 495 sched_yield() SVE VL 32/SME VL 32 ZA
8833 10:54:56.661058 # ok 496 sched_yield() SVE VL 32/SME VL 16 SM+ZA
8834 10:54:56.661239 # ok 497 sched_yield() SVE VL 32/SME VL 16 SM
8835 10:54:56.661451 # ok 498 sched_yield() SVE VL 32/SME VL 16 ZA
8836 10:54:56.661714 # ok 499 sched_yield() SVE VL 16
8837 10:54:56.662301 # ok 500 sched_yield() SVE VL 16/SME VL 256 SM+ZA
8838 10:54:56.662503 # ok 501 sched_yield() SVE VL 16/SME VL 256 SM
8839 10:54:56.662723 # ok 502 sched_yield() SVE VL 16/SME VL 256 ZA
8840 10:54:56.662957 # ok 503 sched_yield() SVE VL 16/SME VL 128 SM+ZA
8841 10:54:56.663162 # ok 504 sched_yield() SVE VL 16/SME VL 128 SM
8842 10:54:56.663335 # ok 505 sched_yield() SVE VL 16/SME VL 128 ZA
8843 10:54:56.663484 # ok 506 sched_yield() SVE VL 16/SME VL 64 SM+ZA
8844 10:54:56.663626 # ok 507 sched_yield() SVE VL 16/SME VL 64 SM
8845 10:54:56.663809 # ok 508 sched_yield() SVE VL 16/SME VL 64 ZA
8846 10:54:56.663942 # ok 509 sched_yield() SVE VL 16/SME VL 32 SM+ZA
8847 10:54:56.664083 # ok 510 sched_yield() SVE VL 16/SME VL 32 SM
8848 10:54:56.664223 # ok 511 sched_yield() SVE VL 16/SME VL 32 ZA
8849 10:54:56.664364 # ok 512 sched_yield() SVE VL 16/SME VL 16 SM+ZA
8850 10:54:56.664504 # ok 513 sched_yield() SVE VL 16/SME VL 16 SM
8851 10:54:56.664644 # ok 514 sched_yield() SVE VL 16/SME VL 16 ZA
8852 10:54:56.664783 # # Totals: pass:514 fail:0 xfail:0 xpass:0 skip:0 error:0
8853 10:54:56.668349 ok 47 selftests: arm64: syscall-abi
8854 10:54:56.716328 # selftests: arm64: tpidr2
8855 10:54:56.865865 # TAP version 13
8856 10:54:56.866111 # 1..5
8857 10:54:56.866414 # # PID: 4982
8858 10:54:56.866509 # ok 1 default_value
8859 10:54:56.866610 # ok 2 write_read
8860 10:54:56.866694 # ok 3 write_sleep_read
8861 10:54:56.866769 # ok 4 write_fork_read
8862 10:54:56.866843 # ok 5 write_clone_read
8863 10:54:56.866916 # # Totals: pass:5 fail:0 xfail:0 xpass:0 skip:0 error:0
8864 10:54:56.876904 ok 48 selftests: arm64: tpidr2
8865 10:54:57.442621 arm64_tags_test pass
8866 10:54:57.442871 arm64_run_tags_test_sh pass
8867 10:54:57.443353 arm64_fake_sigreturn_bad_magic pass
8868 10:54:57.443573 arm64_fake_sigreturn_bad_size pass
8869 10:54:57.443789 arm64_fake_sigreturn_bad_size_for_magic0 pass
8870 10:54:57.444103 arm64_fake_sigreturn_duplicated_fpsimd pass
8871 10:54:57.444324 arm64_fake_sigreturn_misaligned_sp pass
8872 10:54:57.444530 arm64_fake_sigreturn_missing_fpsimd pass
8873 10:54:57.444769 arm64_fake_sigreturn_sme_change_vl pass
8874 10:54:57.444954 arm64_fake_sigreturn_sve_change_vl pass
8875 10:54:57.445166 arm64_mangle_pstate_invalid_compat_toggle pass
8876 10:54:57.445371 arm64_mangle_pstate_invalid_daif_bits pass
8877 10:54:57.445575 arm64_mangle_pstate_invalid_mode_el1h pass
8878 10:54:57.445797 arm64_mangle_pstate_invalid_mode_el1t pass
8879 10:54:57.445997 arm64_mangle_pstate_invalid_mode_el2h pass
8880 10:54:57.446218 arm64_mangle_pstate_invalid_mode_el2t pass
8881 10:54:57.446431 arm64_mangle_pstate_invalid_mode_el3h pass
8882 10:54:57.446651 arm64_mangle_pstate_invalid_mode_el3t pass
8883 10:54:57.446922 arm64_sme_trap_no_sm pass
8884 10:54:57.447138 arm64_sme_trap_non_streaming skip
8885 10:54:57.447328 arm64_sme_trap_za pass
8886 10:54:57.447532 arm64_sme_vl pass
8887 10:54:57.447733 arm64_ssve_regs pass
8888 10:54:57.447938 arm64_sve_regs pass
8889 10:54:57.448166 arm64_sve_vl pass
8890 10:54:57.448333 arm64_za_no_regs pass
8891 10:54:57.448466 arm64_za_regs pass
8892 10:54:57.448583 arm64_pac_global_corrupt_pac pass
8893 10:54:57.448698 arm64_pac_global_pac_instructions_not_nop pass
8894 10:54:57.448814 arm64_pac_global_pac_instructions_not_nop_generic pass
8895 10:54:57.448929 arm64_pac_global_single_thread_different_keys pass
8896 10:54:57.449043 arm64_pac_global_exec_changed_keys pass
8897 10:54:57.449160 arm64_pac_global_context_switch_keep_keys pass
8898 10:54:57.449276 arm64_pac_global_context_switch_keep_keys_generic pass
8899 10:54:57.449390 arm64_pac pass
8900 10:54:57.449504 arm64_fp-stress_FPSIMD-0-0 pass
8901 10:54:57.449620 arm64_fp-stress_SVE-VL-256-0 pass
8902 10:54:57.449849 arm64_fp-stress_SVE-VL-240-0 pass
8903 10:54:57.450047 arm64_fp-stress_SVE-VL-224-0 pass
8904 10:54:57.450232 arm64_fp-stress_SVE-VL-208-0 pass
8905 10:54:57.450415 arm64_fp-stress_SVE-VL-192-0 pass
8906 10:54:57.450637 arm64_fp-stress_SVE-VL-176-0 pass
8907 10:54:57.450777 arm64_fp-stress_SVE-VL-160-0 pass
8908 10:54:57.450921 arm64_fp-stress_SVE-VL-144-0 pass
8909 10:54:57.451064 arm64_fp-stress_SVE-VL-128-0 pass
8910 10:54:57.451207 arm64_fp-stress_SVE-VL-112-0 pass
8911 10:54:57.451354 arm64_fp-stress_SVE-VL-96-0 pass
8912 10:54:57.451497 arm64_fp-stress_SVE-VL-80-0 pass
8913 10:54:57.451660 arm64_fp-stress_SVE-VL-64-0 pass
8914 10:54:57.451890 arm64_fp-stress_SVE-VL-48-0 pass
8915 10:54:57.452146 arm64_fp-stress_SVE-VL-32-0 pass
8916 10:54:57.452368 arm64_fp-stress_SVE-VL-16-0 pass
8917 10:54:57.452535 arm64_fp-stress_SSVE-VL-256-0 pass
8918 10:54:57.452712 arm64_fp-stress_ZA-VL-256-0 pass
8919 10:54:57.452969 arm64_fp-stress_SSVE-VL-128-0 pass
8920 10:54:57.453399 arm64_fp-stress_ZA-VL-128-0 pass
8921 10:54:57.453497 arm64_fp-stress_SSVE-VL-64-0 pass
8922 10:54:57.453579 arm64_fp-stress_ZA-VL-64-0 pass
8923 10:54:57.453665 arm64_fp-stress_SSVE-VL-32-0 pass
8924 10:54:57.453745 arm64_fp-stress_ZA-VL-32-0 pass
8925 10:54:57.453827 arm64_fp-stress_SSVE-VL-16-0 pass
8926 10:54:57.453908 arm64_fp-stress_ZA-VL-16-0 pass
8927 10:54:57.453986 arm64_fp-stress pass
8928 10:54:57.454067 arm64_sve-ptrace_SVE_FPSIMD_set_via_SVE_0 pass
8929 10:54:57.454143 arm64_sve-ptrace_SVE_get_fpsimd_gave_same_state pass
8930 10:54:57.454232 arm64_sve-ptrace_SVE_SVE_PT_VL_INHERIT_set pass
8931 10:54:57.454308 arm64_sve-ptrace_SVE_SVE_PT_VL_INHERIT_cleared pass
8932 10:54:57.454380 arm64_sve-ptrace_Set_SVE_VL_16 pass
8933 10:54:57.454455 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_16 pass
8934 10:54:57.454530 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_16 pass
8935 10:54:57.454607 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_16 pass
8936 10:54:57.454703 arm64_sve-ptrace_Set_SVE_VL_32 pass
8937 10:54:57.454800 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_32 pass
8938 10:54:57.454880 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_32 pass
8939 10:54:57.454965 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_32 pass
8940 10:54:57.455050 arm64_sve-ptrace_Set_SVE_VL_48 pass
8941 10:54:57.455505 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_48 pass
8942 10:54:57.455603 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_48 pass
8943 10:54:57.455690 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_48 pass
8944 10:54:57.455770 arm64_sve-ptrace_Set_SVE_VL_64 pass
8945 10:54:57.459751 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_64 pass
8946 10:54:57.460283 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_64 pass
8947 10:54:57.460460 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_64 pass
8948 10:54:57.460623 arm64_sve-ptrace_Set_SVE_VL_80 pass
8949 10:54:57.460788 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_80 pass
8950 10:54:57.460944 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_80 pass
8951 10:54:57.461133 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_80 pass
8952 10:54:57.461298 arm64_sve-ptrace_Set_SVE_VL_96 pass
8953 10:54:57.461454 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_96 pass
8954 10:54:57.461613 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_96 pass
8955 10:54:57.461823 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_96 pass
8956 10:54:57.461999 arm64_sve-ptrace_Set_SVE_VL_112 pass
8957 10:54:57.462166 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_112 pass
8958 10:54:57.462323 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_112 pass
8959 10:54:57.462485 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_112 pass
8960 10:54:57.462632 arm64_sve-ptrace_Set_SVE_VL_128 pass
8961 10:54:57.462788 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_128 pass
8962 10:54:57.462954 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_128 pass
8963 10:54:57.463157 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_128 pass
8964 10:54:57.463318 arm64_sve-ptrace_Set_SVE_VL_144 pass
8965 10:54:57.463477 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_144 pass
8966 10:54:57.463639 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_144 pass
8967 10:54:57.463805 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_144 pass
8968 10:54:57.463965 arm64_sve-ptrace_Set_SVE_VL_160 pass
8969 10:54:57.464155 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_160 pass
8970 10:54:57.464321 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_160 pass
8971 10:54:57.464487 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_160 pass
8972 10:54:57.464662 arm64_sve-ptrace_Set_SVE_VL_176 pass
8973 10:54:57.467829 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_176 pass
8974 10:54:57.468418 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_176 pass
8975 10:54:57.468514 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_176 pass
8976 10:54:57.468592 arm64_sve-ptrace_Set_SVE_VL_192 pass
8977 10:54:57.468667 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_192 pass
8978 10:54:57.468741 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_192 pass
8979 10:54:57.468814 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_192 pass
8980 10:54:57.468887 arm64_sve-ptrace_Set_SVE_VL_208 pass
8981 10:54:57.469161 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_208 pass
8982 10:54:57.469255 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_208 pass
8983 10:54:57.469332 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_208 pass
8984 10:54:57.469405 arm64_sve-ptrace_Set_SVE_VL_224 pass
8985 10:54:57.469479 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_224 pass
8986 10:54:57.469559 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_224 pass
8987 10:54:57.469640 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_224 pass
8988 10:54:57.469748 arm64_sve-ptrace_Set_SVE_VL_240 pass
8989 10:54:57.469829 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_240 pass
8990 10:54:57.469908 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_240 pass
8991 10:54:57.469986 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_240 pass
8992 10:54:57.470065 arm64_sve-ptrace_Set_SVE_VL_256 pass
8993 10:54:57.470150 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_256 pass
8994 10:54:57.470239 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_256 pass
8995 10:54:57.470318 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_256 pass
8996 10:54:57.470396 arm64_sve-ptrace_Set_SVE_VL_272 pass
8997 10:54:57.470474 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_272 skip
8998 10:54:57.470566 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_272 skip
8999 10:54:57.470648 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_272 skip
9000 10:54:57.470729 arm64_sve-ptrace_Set_SVE_VL_288 pass
9001 10:54:57.470820 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_288 skip
9002 10:54:57.470906 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_288 skip
9003 10:54:57.471013 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_288 skip
9004 10:54:57.471105 arm64_sve-ptrace_Set_SVE_VL_304 pass
9005 10:54:57.471199 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_304 skip
9006 10:54:57.471307 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_304 skip
9007 10:54:57.471404 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_304 skip
9008 10:54:57.471495 arm64_sve-ptrace_Set_SVE_VL_320 pass
9009 10:54:57.471601 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_320 skip
9010 10:54:57.471693 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_320 skip
9011 10:54:57.475686 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_320 skip
9012 10:54:57.476023 arm64_sve-ptrace_Set_SVE_VL_336 pass
9013 10:54:57.476160 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_336 skip
9014 10:54:57.476265 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_336 skip
9015 10:54:57.476354 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_336 skip
9016 10:54:57.476439 arm64_sve-ptrace_Set_SVE_VL_352 pass
9017 10:54:57.476503 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_352 skip
9018 10:54:57.476591 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_352 skip
9019 10:54:57.476671 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_352 skip
9020 10:54:57.476756 arm64_sve-ptrace_Set_SVE_VL_368 pass
9021 10:54:57.476820 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_368 skip
9022 10:54:57.477087 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_368 skip
9023 10:54:57.477184 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_368 skip
9024 10:54:57.477283 arm64_sve-ptrace_Set_SVE_VL_384 pass
9025 10:54:57.477379 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_384 skip
9026 10:54:57.477453 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_384 skip
9027 10:54:57.477529 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_384 skip
9028 10:54:57.477621 arm64_sve-ptrace_Set_SVE_VL_400 pass
9029 10:54:57.477707 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_400 skip
9030 10:54:57.477796 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_400 skip
9031 10:54:57.477863 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_400 skip
9032 10:54:57.477954 arm64_sve-ptrace_Set_SVE_VL_416 pass
9033 10:54:57.478037 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_416 skip
9034 10:54:57.478131 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_416 skip
9035 10:54:57.478410 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_416 skip
9036 10:54:57.478501 arm64_sve-ptrace_Set_SVE_VL_432 pass
9037 10:54:57.478590 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_432 skip
9038 10:54:57.478656 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_432 skip
9039 10:54:57.478730 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_432 skip
9040 10:54:57.478988 arm64_sve-ptrace_Set_SVE_VL_448 pass
9041 10:54:57.479059 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_448 skip
9042 10:54:57.481291 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_448 skip
9043 10:54:57.500027 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_448 skip
9044 10:54:57.500528 arm64_sve-ptrace_Set_SVE_VL_464 pass
9045 10:54:57.500633 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_464 skip
9046 10:54:57.500722 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_464 skip
9047 10:54:57.500808 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_464 skip
9048 10:54:57.500891 arm64_sve-ptrace_Set_SVE_VL_480 pass
9049 10:54:57.500991 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_480 skip
9050 10:54:57.501074 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_480 skip
9051 10:54:57.501183 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_480 skip
9052 10:54:57.501290 arm64_sve-ptrace_Set_SVE_VL_496 pass
9053 10:54:57.501424 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_496 skip
9054 10:54:57.501540 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_496 skip
9055 10:54:57.501677 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_496 skip
9056 10:54:57.501795 arm64_sve-ptrace_Set_SVE_VL_512 pass
9057 10:54:57.501911 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_512 skip
9058 10:54:57.502033 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_512 skip
9059 10:54:57.502496 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_512 skip
9060 10:54:57.502604 arm64_sve-ptrace_Set_SVE_VL_528 pass
9061 10:54:57.502697 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_528 skip
9062 10:54:57.502802 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_528 skip
9063 10:54:57.502892 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_528 skip
9064 10:54:57.502996 arm64_sve-ptrace_Set_SVE_VL_544 pass
9065 10:54:57.503103 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_544 skip
9066 10:54:57.503230 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_544 skip
9067 10:54:57.503362 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_544 skip
9068 10:54:57.507739 arm64_sve-ptrace_Set_SVE_VL_560 pass
9069 10:54:57.508122 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_560 skip
9070 10:54:57.508235 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_560 skip
9071 10:54:57.508337 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_560 skip
9072 10:54:57.508442 arm64_sve-ptrace_Set_SVE_VL_576 pass
9073 10:54:57.508532 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_576 skip
9074 10:54:57.508634 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_576 skip
9075 10:54:57.508737 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_576 skip
9076 10:54:57.508839 arm64_sve-ptrace_Set_SVE_VL_592 pass
9077 10:54:57.509132 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_592 skip
9078 10:54:57.509253 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_592 skip
9079 10:54:57.509348 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_592 skip
9080 10:54:57.509450 arm64_sve-ptrace_Set_SVE_VL_608 pass
9081 10:54:57.509567 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_608 skip
9082 10:54:57.509895 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_608 skip
9083 10:54:57.510197 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_608 skip
9084 10:54:57.510295 arm64_sve-ptrace_Set_SVE_VL_624 pass
9085 10:54:57.510373 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_624 skip
9086 10:54:57.510473 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_624 skip
9087 10:54:57.510578 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_624 skip
9088 10:54:57.510877 arm64_sve-ptrace_Set_SVE_VL_640 pass
9089 10:54:57.510984 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_640 skip
9090 10:54:57.511091 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_640 skip
9091 10:54:57.511202 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_640 skip
9092 10:54:57.511294 arm64_sve-ptrace_Set_SVE_VL_656 pass
9093 10:54:57.511397 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_656 skip
9094 10:54:57.515745 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_656 skip
9095 10:54:57.516184 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_656 skip
9096 10:54:57.516281 arm64_sve-ptrace_Set_SVE_VL_672 pass
9097 10:54:57.516380 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_672 skip
9098 10:54:57.516470 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_672 skip
9099 10:54:57.516566 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_672 skip
9100 10:54:57.516639 arm64_sve-ptrace_Set_SVE_VL_688 pass
9101 10:54:57.516732 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_688 skip
9102 10:54:57.516819 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_688 skip
9103 10:54:57.517126 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_688 skip
9104 10:54:57.517242 arm64_sve-ptrace_Set_SVE_VL_704 pass
9105 10:54:57.517361 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_704 skip
9106 10:54:57.517482 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_704 skip
9107 10:54:57.517589 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_704 skip
9108 10:54:57.517908 arm64_sve-ptrace_Set_SVE_VL_720 pass
9109 10:54:57.518015 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_720 skip
9110 10:54:57.518105 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_720 skip
9111 10:54:57.518203 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_720 skip
9112 10:54:57.518288 arm64_sve-ptrace_Set_SVE_VL_736 pass
9113 10:54:57.518385 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_736 skip
9114 10:54:57.518485 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_736 skip
9115 10:54:57.518848 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_736 skip
9116 10:54:57.518959 arm64_sve-ptrace_Set_SVE_VL_752 pass
9117 10:54:57.519066 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_752 skip
9118 10:54:57.519171 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_752 skip
9119 10:54:57.519478 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_752 skip
9120 10:54:57.519585 arm64_sve-ptrace_Set_SVE_VL_768 pass
9121 10:54:57.523698 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_768 skip
9122 10:54:57.524036 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_768 skip
9123 10:54:57.524140 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_768 skip
9124 10:54:57.524254 arm64_sve-ptrace_Set_SVE_VL_784 pass
9125 10:54:57.524350 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_784 skip
9126 10:54:57.524455 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_784 skip
9127 10:54:57.524570 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_784 skip
9128 10:54:57.525800 arm64_sve-ptrace_Set_SVE_VL_800 pass
9129 10:54:57.525901 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_800 skip
9130 10:54:57.525986 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_800 skip
9131 10:54:57.526070 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_800 skip
9132 10:54:57.526155 arm64_sve-ptrace_Set_SVE_VL_816 pass
9133 10:54:57.526273 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_816 skip
9134 10:54:57.526368 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_816 skip
9135 10:54:57.526447 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_816 skip
9136 10:54:57.526525 arm64_sve-ptrace_Set_SVE_VL_832 pass
9137 10:54:57.526816 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_832 skip
9138 10:54:57.526942 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_832 skip
9139 10:54:57.527029 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_832 skip
9140 10:54:57.527108 arm64_sve-ptrace_Set_SVE_VL_848 pass
9141 10:54:57.527188 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_848 skip
9142 10:54:57.527272 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_848 skip
9143 10:54:57.527349 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_848 skip
9144 10:54:57.527428 arm64_sve-ptrace_Set_SVE_VL_864 pass
9145 10:54:57.527529 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_864 skip
9146 10:54:57.527611 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_864 skip
9147 10:54:57.527689 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_864 skip
9148 10:54:57.527774 arm64_sve-ptrace_Set_SVE_VL_880 pass
9149 10:54:57.527882 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_880 skip
9150 10:54:57.527986 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_880 skip
9151 10:54:57.528095 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_880 skip
9152 10:54:57.528224 arm64_sve-ptrace_Set_SVE_VL_896 pass
9153 10:54:57.528337 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_896 skip
9154 10:54:57.528451 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_896 skip
9155 10:54:57.528561 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_896 skip
9156 10:54:57.528672 arm64_sve-ptrace_Set_SVE_VL_912 pass
9157 10:54:57.528792 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_912 skip
9158 10:54:57.528894 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_912 skip
9159 10:54:57.528995 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_912 skip
9160 10:54:57.529085 arm64_sve-ptrace_Set_SVE_VL_928 pass
9161 10:54:57.529182 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_928 skip
9162 10:54:57.529266 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_928 skip
9163 10:54:57.529345 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_928 skip
9164 10:54:57.529424 arm64_sve-ptrace_Set_SVE_VL_944 pass
9165 10:54:57.529520 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_944 skip
9166 10:54:57.529600 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_944 skip
9167 10:54:57.529698 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_944 skip
9168 10:54:57.530209 arm64_sve-ptrace_Set_SVE_VL_960 pass
9169 10:54:57.530337 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_960 skip
9170 10:54:57.530468 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_960 skip
9171 10:54:57.530563 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_960 skip
9172 10:54:57.530652 arm64_sve-ptrace_Set_SVE_VL_976 pass
9173 10:54:57.530742 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_976 skip
9174 10:54:57.530830 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_976 skip
9175 10:54:57.535605 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_976 skip
9176 10:54:57.535950 arm64_sve-ptrace_Set_SVE_VL_992 pass
9177 10:54:57.536051 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_992 skip
9178 10:54:57.536140 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_992 skip
9179 10:54:57.536238 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_992 skip
9180 10:54:57.536327 arm64_sve-ptrace_Set_SVE_VL_1008 pass
9181 10:54:57.536427 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1008 skip
9182 10:54:57.536525 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1008 skip
9183 10:54:57.536995 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1008 skip
9184 10:54:57.537099 arm64_sve-ptrace_Set_SVE_VL_1024 pass
9185 10:54:57.537186 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1024 skip
9186 10:54:57.537461 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1024 skip
9187 10:54:57.537552 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1024 skip
9188 10:54:57.537636 arm64_sve-ptrace_Set_SVE_VL_1040 pass
9189 10:54:57.538409 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1040 skip
9190 10:54:57.538501 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1040 skip
9191 10:54:57.538586 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1040 skip
9192 10:54:57.538670 arm64_sve-ptrace_Set_SVE_VL_1056 pass
9193 10:54:57.538753 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1056 skip
9194 10:54:57.538839 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1056 skip
9195 10:54:57.538924 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1056 skip
9196 10:54:57.539009 arm64_sve-ptrace_Set_SVE_VL_1072 pass
9197 10:54:57.539095 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1072 skip
9198 10:54:57.539177 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1072 skip
9199 10:54:57.539260 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1072 skip
9200 10:54:57.539539 arm64_sve-ptrace_Set_SVE_VL_1088 pass
9201 10:54:57.539633 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1088 skip
9202 10:54:57.539718 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1088 skip
9203 10:54:57.539795 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1088 skip
9204 10:54:57.539865 arm64_sve-ptrace_Set_SVE_VL_1104 pass
9205 10:54:57.561086 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1104 skip
9206 10:54:57.561335 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1104 skip
9207 10:54:57.561775 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1104 skip
9208 10:54:57.561887 arm64_sve-ptrace_Set_SVE_VL_1120 pass
9209 10:54:57.561975 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1120 skip
9210 10:54:57.564469 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1120 skip
9211 10:54:57.564579 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1120 skip
9212 10:54:57.564665 arm64_sve-ptrace_Set_SVE_VL_1136 pass
9213 10:54:57.564738 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1136 skip
9214 10:54:57.564799 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1136 skip
9215 10:54:57.564860 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1136 skip
9216 10:54:57.564922 arm64_sve-ptrace_Set_SVE_VL_1152 pass
9217 10:54:57.564984 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1152 skip
9218 10:54:57.565050 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1152 skip
9219 10:54:57.565111 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1152 skip
9220 10:54:57.565211 arm64_sve-ptrace_Set_SVE_VL_1168 pass
9221 10:54:57.565315 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1168 skip
9222 10:54:57.565398 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1168 skip
9223 10:54:57.565500 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1168 skip
9224 10:54:57.565597 arm64_sve-ptrace_Set_SVE_VL_1184 pass
9225 10:54:57.567815 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1184 skip
9226 10:54:57.568110 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1184 skip
9227 10:54:57.568204 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1184 skip
9228 10:54:57.568295 arm64_sve-ptrace_Set_SVE_VL_1200 pass
9229 10:54:57.568548 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1200 skip
9230 10:54:57.568622 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1200 skip
9231 10:54:57.568701 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1200 skip
9232 10:54:57.568782 arm64_sve-ptrace_Set_SVE_VL_1216 pass
9233 10:54:57.568880 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1216 skip
9234 10:54:57.568979 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1216 skip
9235 10:54:57.569255 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1216 skip
9236 10:54:57.569354 arm64_sve-ptrace_Set_SVE_VL_1232 pass
9237 10:54:57.569446 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1232 skip
9238 10:54:57.569698 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1232 skip
9239 10:54:57.569798 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1232 skip
9240 10:54:57.569888 arm64_sve-ptrace_Set_SVE_VL_1248 pass
9241 10:54:57.569984 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1248 skip
9242 10:54:57.570296 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1248 skip
9243 10:54:57.570405 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1248 skip
9244 10:54:57.570511 arm64_sve-ptrace_Set_SVE_VL_1264 pass
9245 10:54:57.570612 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1264 skip
9246 10:54:57.570900 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1264 skip
9247 10:54:57.570997 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1264 skip
9248 10:54:57.571103 arm64_sve-ptrace_Set_SVE_VL_1280 pass
9249 10:54:57.571209 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1280 skip
9250 10:54:57.571300 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1280 skip
9251 10:54:57.575785 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1280 skip
9252 10:54:57.576177 arm64_sve-ptrace_Set_SVE_VL_1296 pass
9253 10:54:57.576281 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1296 skip
9254 10:54:57.576380 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1296 skip
9255 10:54:57.576459 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1296 skip
9256 10:54:57.576535 arm64_sve-ptrace_Set_SVE_VL_1312 pass
9257 10:54:57.576625 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1312 skip
9258 10:54:57.576712 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1312 skip
9259 10:54:57.577020 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1312 skip
9260 10:54:57.577114 arm64_sve-ptrace_Set_SVE_VL_1328 pass
9261 10:54:57.577203 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1328 skip
9262 10:54:57.577290 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1328 skip
9263 10:54:57.577587 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1328 skip
9264 10:54:57.577702 arm64_sve-ptrace_Set_SVE_VL_1344 pass
9265 10:54:57.578023 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1344 skip
9266 10:54:57.578121 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1344 skip
9267 10:54:57.578208 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1344 skip
9268 10:54:57.578309 arm64_sve-ptrace_Set_SVE_VL_1360 pass
9269 10:54:57.578393 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1360 skip
9270 10:54:57.578700 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1360 skip
9271 10:54:57.578803 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1360 skip
9272 10:54:57.578906 arm64_sve-ptrace_Set_SVE_VL_1376 pass
9273 10:54:57.579005 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1376 skip
9274 10:54:57.579089 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1376 skip
9275 10:54:57.580239 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1376 skip
9276 10:54:57.580341 arm64_sve-ptrace_Set_SVE_VL_1392 pass
9277 10:54:57.580422 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1392 skip
9278 10:54:57.584082 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1392 skip
9279 10:54:57.584192 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1392 skip
9280 10:54:57.584281 arm64_sve-ptrace_Set_SVE_VL_1408 pass
9281 10:54:57.584566 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1408 skip
9282 10:54:57.584670 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1408 skip
9283 10:54:57.584772 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1408 skip
9284 10:54:57.584862 arm64_sve-ptrace_Set_SVE_VL_1424 pass
9285 10:54:57.584947 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1424 skip
9286 10:54:57.585049 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1424 skip
9287 10:54:57.585148 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1424 skip
9288 10:54:57.585446 arm64_sve-ptrace_Set_SVE_VL_1440 pass
9289 10:54:57.585550 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1440 skip
9290 10:54:57.585721 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1440 skip
9291 10:54:57.585846 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1440 skip
9292 10:54:57.585937 arm64_sve-ptrace_Set_SVE_VL_1456 pass
9293 10:54:57.586034 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1456 skip
9294 10:54:57.586322 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1456 skip
9295 10:54:57.586425 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1456 skip
9296 10:54:57.586510 arm64_sve-ptrace_Set_SVE_VL_1472 pass
9297 10:54:57.586606 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1472 skip
9298 10:54:57.586706 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1472 skip
9299 10:54:57.587001 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1472 skip
9300 10:54:57.587307 arm64_sve-ptrace_Set_SVE_VL_1488 pass
9301 10:54:57.587444 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1488 skip
9302 10:54:57.587537 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1488 skip
9303 10:54:57.587638 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1488 skip
9304 10:54:57.587726 arm64_sve-ptrace_Set_SVE_VL_1504 pass
9305 10:54:57.591853 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1504 skip
9306 10:54:57.591966 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1504 skip
9307 10:54:57.592240 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1504 skip
9308 10:54:57.592348 arm64_sve-ptrace_Set_SVE_VL_1520 pass
9309 10:54:57.592425 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1520 skip
9310 10:54:57.592510 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1520 skip
9311 10:54:57.592604 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1520 skip
9312 10:54:57.592900 arm64_sve-ptrace_Set_SVE_VL_1536 pass
9313 10:54:57.593001 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1536 skip
9314 10:54:57.593295 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1536 skip
9315 10:54:57.593379 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1536 skip
9316 10:54:57.593444 arm64_sve-ptrace_Set_SVE_VL_1552 pass
9317 10:54:57.593689 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1552 skip
9318 10:54:57.593785 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1552 skip
9319 10:54:57.594061 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1552 skip
9320 10:54:57.594144 arm64_sve-ptrace_Set_SVE_VL_1568 pass
9321 10:54:57.594222 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1568 skip
9322 10:54:57.594481 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1568 skip
9323 10:54:57.594553 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1568 skip
9324 10:54:57.594629 arm64_sve-ptrace_Set_SVE_VL_1584 pass
9325 10:54:57.594720 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1584 skip
9326 10:54:57.595470 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1584 skip
9327 10:54:57.595554 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1584 skip
9328 10:54:57.595632 arm64_sve-ptrace_Set_SVE_VL_1600 pass
9329 10:54:57.595706 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1600 skip
9330 10:54:57.595781 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1600 skip
9331 10:54:57.595855 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1600 skip
9332 10:54:57.595946 arm64_sve-ptrace_Set_SVE_VL_1616 pass
9333 10:54:57.599783 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1616 skip
9334 10:54:57.600168 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1616 skip
9335 10:54:57.600292 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1616 skip
9336 10:54:57.600400 arm64_sve-ptrace_Set_SVE_VL_1632 pass
9337 10:54:57.600496 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1632 skip
9338 10:54:57.600612 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1632 skip
9339 10:54:57.600947 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1632 skip
9340 10:54:57.601146 arm64_sve-ptrace_Set_SVE_VL_1648 pass
9341 10:54:57.601244 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1648 skip
9342 10:54:57.601350 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1648 skip
9343 10:54:57.601751 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1648 skip
9344 10:54:57.601856 arm64_sve-ptrace_Set_SVE_VL_1664 pass
9345 10:54:57.601957 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1664 skip
9346 10:54:57.602045 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1664 skip
9347 10:54:57.602459 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1664 skip
9348 10:54:57.602591 arm64_sve-ptrace_Set_SVE_VL_1680 pass
9349 10:54:57.602672 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1680 skip
9350 10:54:57.602949 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1680 skip
9351 10:54:57.603048 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1680 skip
9352 10:54:57.603144 arm64_sve-ptrace_Set_SVE_VL_1696 pass
9353 10:54:57.603222 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1696 skip
9354 10:54:57.603311 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1696 skip
9355 10:54:57.603550 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1696 skip
9356 10:54:57.610853 arm64_sve-ptrace_Set_SVE_VL_1712 pass
9357 10:54:57.611077 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1712 skip
9358 10:54:57.611211 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1712 skip
9359 10:54:57.611318 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1712 skip
9360 10:54:57.611445 arm64_sve-ptrace_Set_SVE_VL_1728 pass
9361 10:54:57.611557 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1728 skip
9362 10:54:57.611677 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1728 skip
9363 10:54:57.611984 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1728 skip
9364 10:54:57.612274 arm64_sve-ptrace_Set_SVE_VL_1744 pass
9365 10:54:57.632573 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1744 skip
9366 10:54:57.632985 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1744 skip
9367 10:54:57.633075 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1744 skip
9368 10:54:57.633168 arm64_sve-ptrace_Set_SVE_VL_1760 pass
9369 10:54:57.633267 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1760 skip
9370 10:54:57.633340 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1760 skip
9371 10:54:57.633421 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1760 skip
9372 10:54:57.633499 arm64_sve-ptrace_Set_SVE_VL_1776 pass
9373 10:54:57.633621 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1776 skip
9374 10:54:57.633724 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1776 skip
9375 10:54:57.633825 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1776 skip
9376 10:54:57.633918 arm64_sve-ptrace_Set_SVE_VL_1792 pass
9377 10:54:57.634014 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1792 skip
9378 10:54:57.634086 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1792 skip
9379 10:54:57.634162 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1792 skip
9380 10:54:57.634237 arm64_sve-ptrace_Set_SVE_VL_1808 pass
9381 10:54:57.634330 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1808 skip
9382 10:54:57.634406 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1808 skip
9383 10:54:57.634480 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1808 skip
9384 10:54:57.634571 arm64_sve-ptrace_Set_SVE_VL_1824 pass
9385 10:54:57.634657 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1824 skip
9386 10:54:57.634923 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1824 skip
9387 10:54:57.635005 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1824 skip
9388 10:54:57.635102 arm64_sve-ptrace_Set_SVE_VL_1840 pass
9389 10:54:57.635221 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1840 skip
9390 10:54:57.635305 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1840 skip
9391 10:54:57.635401 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1840 skip
9392 10:54:57.635502 arm64_sve-ptrace_Set_SVE_VL_1856 pass
9393 10:54:57.635594 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1856 skip
9394 10:54:57.639673 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1856 skip
9395 10:54:57.640003 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1856 skip
9396 10:54:57.640088 arm64_sve-ptrace_Set_SVE_VL_1872 pass
9397 10:54:57.640169 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1872 skip
9398 10:54:57.640269 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1872 skip
9399 10:54:57.640338 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1872 skip
9400 10:54:57.640401 arm64_sve-ptrace_Set_SVE_VL_1888 pass
9401 10:54:57.640479 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1888 skip
9402 10:54:57.640552 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1888 skip
9403 10:54:57.640625 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1888 skip
9404 10:54:57.640699 arm64_sve-ptrace_Set_SVE_VL_1904 pass
9405 10:54:57.640968 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1904 skip
9406 10:54:57.641053 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1904 skip
9407 10:54:57.641132 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1904 skip
9408 10:54:57.641231 arm64_sve-ptrace_Set_SVE_VL_1920 pass
9409 10:54:57.641314 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1920 skip
9410 10:54:57.641391 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1920 skip
9411 10:54:57.641654 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1920 skip
9412 10:54:57.641727 arm64_sve-ptrace_Set_SVE_VL_1936 pass
9413 10:54:57.641803 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1936 skip
9414 10:54:57.641882 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1936 skip
9415 10:54:57.641966 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1936 skip
9416 10:54:57.642221 arm64_sve-ptrace_Set_SVE_VL_1952 pass
9417 10:54:57.642294 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1952 skip
9418 10:54:57.642372 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1952 skip
9419 10:54:57.642449 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1952 skip
9420 10:54:57.642528 arm64_sve-ptrace_Set_SVE_VL_1968 pass
9421 10:54:57.642608 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1968 skip
9422 10:54:57.642866 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1968 skip
9423 10:54:57.642938 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1968 skip
9424 10:54:57.643015 arm64_sve-ptrace_Set_SVE_VL_1984 pass
9425 10:54:57.643264 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1984 skip
9426 10:54:57.643333 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1984 skip
9427 10:54:57.643432 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1984 skip
9428 10:54:57.643688 arm64_sve-ptrace_Set_SVE_VL_2000 pass
9429 10:54:57.643771 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2000 skip
9430 10:54:57.647793 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2000 skip
9431 10:54:57.648191 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2000 skip
9432 10:54:57.648301 arm64_sve-ptrace_Set_SVE_VL_2016 pass
9433 10:54:57.648393 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2016 skip
9434 10:54:57.648498 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2016 skip
9435 10:54:57.648586 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2016 skip
9436 10:54:57.648688 arm64_sve-ptrace_Set_SVE_VL_2032 pass
9437 10:54:57.648791 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2032 skip
9438 10:54:57.649043 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2032 skip
9439 10:54:57.649165 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2032 skip
9440 10:54:57.649270 arm64_sve-ptrace_Set_SVE_VL_2048 pass
9441 10:54:57.649370 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2048 skip
9442 10:54:57.649714 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2048 skip
9443 10:54:57.649820 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2048 skip
9444 10:54:57.649924 arm64_sve-ptrace_Set_SVE_VL_2064 pass
9445 10:54:57.650028 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2064 skip
9446 10:54:57.650354 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2064 skip
9447 10:54:57.650461 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2064 skip
9448 10:54:57.650560 arm64_sve-ptrace_Set_SVE_VL_2080 pass
9449 10:54:57.650660 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2080 skip
9450 10:54:57.650972 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2080 skip
9451 10:54:57.651089 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2080 skip
9452 10:54:57.651176 arm64_sve-ptrace_Set_SVE_VL_2096 pass
9453 10:54:57.651466 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2096 skip
9454 10:54:57.655777 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2096 skip
9455 10:54:57.656177 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2096 skip
9456 10:54:57.656263 arm64_sve-ptrace_Set_SVE_VL_2112 pass
9457 10:54:57.656332 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2112 skip
9458 10:54:57.656399 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2112 skip
9459 10:54:57.656483 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2112 skip
9460 10:54:57.656549 arm64_sve-ptrace_Set_SVE_VL_2128 pass
9461 10:54:57.656626 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2128 skip
9462 10:54:57.656876 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2128 skip
9463 10:54:57.656964 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2128 skip
9464 10:54:57.657034 arm64_sve-ptrace_Set_SVE_VL_2144 pass
9465 10:54:57.657099 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2144 skip
9466 10:54:57.657178 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2144 skip
9467 10:54:57.657248 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2144 skip
9468 10:54:57.657326 arm64_sve-ptrace_Set_SVE_VL_2160 pass
9469 10:54:57.657394 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2160 skip
9470 10:54:57.657478 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2160 skip
9471 10:54:57.657576 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2160 skip
9472 10:54:57.657672 arm64_sve-ptrace_Set_SVE_VL_2176 pass
9473 10:54:57.657762 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2176 skip
9474 10:54:57.658018 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2176 skip
9475 10:54:57.658100 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2176 skip
9476 10:54:57.658168 arm64_sve-ptrace_Set_SVE_VL_2192 pass
9477 10:54:57.658244 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2192 skip
9478 10:54:57.658323 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2192 skip
9479 10:54:57.658401 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2192 skip
9480 10:54:57.658484 arm64_sve-ptrace_Set_SVE_VL_2208 pass
9481 10:54:57.658739 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2208 skip
9482 10:54:57.658811 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2208 skip
9483 10:54:57.658888 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2208 skip
9484 10:54:57.658966 arm64_sve-ptrace_Set_SVE_VL_2224 pass
9485 10:54:57.659219 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2224 skip
9486 10:54:57.659291 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2224 skip
9487 10:54:57.659381 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2224 skip
9488 10:54:57.659481 arm64_sve-ptrace_Set_SVE_VL_2240 pass
9489 10:54:57.663754 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2240 skip
9490 10:54:57.664172 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2240 skip
9491 10:54:57.664292 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2240 skip
9492 10:54:57.664387 arm64_sve-ptrace_Set_SVE_VL_2256 pass
9493 10:54:57.664469 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2256 skip
9494 10:54:57.664551 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2256 skip
9495 10:54:57.664619 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2256 skip
9496 10:54:57.664686 arm64_sve-ptrace_Set_SVE_VL_2272 pass
9497 10:54:57.664763 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2272 skip
9498 10:54:57.664832 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2272 skip
9499 10:54:57.664909 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2272 skip
9500 10:54:57.665016 arm64_sve-ptrace_Set_SVE_VL_2288 pass
9501 10:54:57.665302 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2288 skip
9502 10:54:57.665385 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2288 skip
9503 10:54:57.665451 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2288 skip
9504 10:54:57.665534 arm64_sve-ptrace_Set_SVE_VL_2304 pass
9505 10:54:57.665603 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2304 skip
9506 10:54:57.665700 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2304 skip
9507 10:54:57.665794 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2304 skip
9508 10:54:57.665885 arm64_sve-ptrace_Set_SVE_VL_2320 pass
9509 10:54:57.665971 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2320 skip
9510 10:54:57.666264 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2320 skip
9511 10:54:57.666383 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2320 skip
9512 10:54:57.666484 arm64_sve-ptrace_Set_SVE_VL_2336 pass
9513 10:54:57.666601 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2336 skip
9514 10:54:57.666751 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2336 skip
9515 10:54:57.666859 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2336 skip
9516 10:54:57.666998 arm64_sve-ptrace_Set_SVE_VL_2352 pass
9517 10:54:57.667110 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2352 skip
9518 10:54:57.667228 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2352 skip
9519 10:54:57.667346 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2352 skip
9520 10:54:57.667657 arm64_sve-ptrace_Set_SVE_VL_2368 pass
9521 10:54:57.671994 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2368 skip
9522 10:54:57.672213 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2368 skip
9523 10:54:57.672316 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2368 skip
9524 10:54:57.672388 arm64_sve-ptrace_Set_SVE_VL_2384 pass
9525 10:54:57.688652 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2384 skip
9526 10:54:57.689129 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2384 skip
9527 10:54:57.689233 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2384 skip
9528 10:54:57.689327 arm64_sve-ptrace_Set_SVE_VL_2400 pass
9529 10:54:57.689433 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2400 skip
9530 10:54:57.689547 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2400 skip
9531 10:54:57.689642 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2400 skip
9532 10:54:57.689742 arm64_sve-ptrace_Set_SVE_VL_2416 pass
9533 10:54:57.689863 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2416 skip
9534 10:54:57.689968 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2416 skip
9535 10:54:57.690082 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2416 skip
9536 10:54:57.690208 arm64_sve-ptrace_Set_SVE_VL_2432 pass
9537 10:54:57.690328 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2432 skip
9538 10:54:57.690445 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2432 skip
9539 10:54:57.690564 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2432 skip
9540 10:54:57.690684 arm64_sve-ptrace_Set_SVE_VL_2448 pass
9541 10:54:57.690790 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2448 skip
9542 10:54:57.690911 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2448 skip
9543 10:54:57.691249 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2448 skip
9544 10:54:57.691430 arm64_sve-ptrace_Set_SVE_VL_2464 pass
9545 10:54:57.691636 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2464 skip
9546 10:54:57.691731 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2464 skip
9547 10:54:57.695910 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2464 skip
9548 10:54:57.696167 arm64_sve-ptrace_Set_SVE_VL_2480 pass
9549 10:54:57.696556 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2480 skip
9550 10:54:57.696742 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2480 skip
9551 10:54:57.696902 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2480 skip
9552 10:54:57.697058 arm64_sve-ptrace_Set_SVE_VL_2496 pass
9553 10:54:57.697246 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2496 skip
9554 10:54:57.697443 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2496 skip
9555 10:54:57.697643 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2496 skip
9556 10:54:57.697856 arm64_sve-ptrace_Set_SVE_VL_2512 pass
9557 10:54:57.698021 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2512 skip
9558 10:54:57.698172 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2512 skip
9559 10:54:57.698359 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2512 skip
9560 10:54:57.698514 arm64_sve-ptrace_Set_SVE_VL_2528 pass
9561 10:54:57.698663 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2528 skip
9562 10:54:57.698814 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2528 skip
9563 10:54:57.698969 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2528 skip
9564 10:54:57.699121 arm64_sve-ptrace_Set_SVE_VL_2544 pass
9565 10:54:57.699269 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2544 skip
9566 10:54:57.699416 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2544 skip
9567 10:54:57.699561 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2544 skip
9568 10:54:57.699676 arm64_sve-ptrace_Set_SVE_VL_2560 pass
9569 10:54:57.699815 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2560 skip
9570 10:54:57.699930 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2560 skip
9571 10:54:57.700039 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2560 skip
9572 10:54:57.700149 arm64_sve-ptrace_Set_SVE_VL_2576 pass
9573 10:54:57.700257 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2576 skip
9574 10:54:57.700365 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2576 skip
9575 10:54:57.700475 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2576 skip
9576 10:54:57.700584 arm64_sve-ptrace_Set_SVE_VL_2592 pass
9577 10:54:57.703834 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2592 skip
9578 10:54:57.704514 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2592 skip
9579 10:54:57.704701 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2592 skip
9580 10:54:57.704898 arm64_sve-ptrace_Set_SVE_VL_2608 pass
9581 10:54:57.705128 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2608 skip
9582 10:54:57.705345 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2608 skip
9583 10:54:57.705558 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2608 skip
9584 10:54:57.705773 arm64_sve-ptrace_Set_SVE_VL_2624 pass
9585 10:54:57.705986 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2624 skip
9586 10:54:57.706237 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2624 skip
9587 10:54:57.706426 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2624 skip
9588 10:54:57.706582 arm64_sve-ptrace_Set_SVE_VL_2640 pass
9589 10:54:57.706740 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2640 skip
9590 10:54:57.706897 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2640 skip
9591 10:54:57.707060 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2640 skip
9592 10:54:57.707215 arm64_sve-ptrace_Set_SVE_VL_2656 pass
9593 10:54:57.707373 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2656 skip
9594 10:54:57.707531 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2656 skip
9595 10:54:57.707651 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2656 skip
9596 10:54:57.707765 arm64_sve-ptrace_Set_SVE_VL_2672 pass
9597 10:54:57.707877 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2672 skip
9598 10:54:57.707991 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2672 skip
9599 10:54:57.708104 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2672 skip
9600 10:54:57.708219 arm64_sve-ptrace_Set_SVE_VL_2688 pass
9601 10:54:57.708332 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2688 skip
9602 10:54:57.708445 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2688 skip
9603 10:54:57.708557 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2688 skip
9604 10:54:57.708671 arm64_sve-ptrace_Set_SVE_VL_2704 pass
9605 10:54:57.711994 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2704 skip
9606 10:54:57.712165 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2704 skip
9607 10:54:57.712362 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2704 skip
9608 10:54:57.712563 arm64_sve-ptrace_Set_SVE_VL_2720 pass
9609 10:54:57.712675 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2720 skip
9610 10:54:57.712782 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2720 skip
9611 10:54:57.712900 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2720 skip
9612 10:54:57.713004 arm64_sve-ptrace_Set_SVE_VL_2736 pass
9613 10:54:57.713104 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2736 skip
9614 10:54:57.713185 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2736 skip
9615 10:54:57.713273 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2736 skip
9616 10:54:57.713373 arm64_sve-ptrace_Set_SVE_VL_2752 pass
9617 10:54:57.713461 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2752 skip
9618 10:54:57.713544 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2752 skip
9619 10:54:57.713833 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2752 skip
9620 10:54:57.713932 arm64_sve-ptrace_Set_SVE_VL_2768 pass
9621 10:54:57.714021 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2768 skip
9622 10:54:57.714120 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2768 skip
9623 10:54:57.714228 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2768 skip
9624 10:54:57.714329 arm64_sve-ptrace_Set_SVE_VL_2784 pass
9625 10:54:57.714439 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2784 skip
9626 10:54:57.714537 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2784 skip
9627 10:54:57.714618 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2784 skip
9628 10:54:57.714710 arm64_sve-ptrace_Set_SVE_VL_2800 pass
9629 10:54:57.714785 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2800 skip
9630 10:54:57.714857 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2800 skip
9631 10:54:57.714957 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2800 skip
9632 10:54:57.715036 arm64_sve-ptrace_Set_SVE_VL_2816 pass
9633 10:54:57.715123 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2816 skip
9634 10:54:57.715223 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2816 skip
9635 10:54:57.715615 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2816 skip
9636 10:54:57.715824 arm64_sve-ptrace_Set_SVE_VL_2832 pass
9637 10:54:57.719856 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2832 skip
9638 10:54:57.720308 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2832 skip
9639 10:54:57.720532 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2832 skip
9640 10:54:57.720662 arm64_sve-ptrace_Set_SVE_VL_2848 pass
9641 10:54:57.720768 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2848 skip
9642 10:54:57.720909 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2848 skip
9643 10:54:57.721029 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2848 skip
9644 10:54:57.721147 arm64_sve-ptrace_Set_SVE_VL_2864 pass
9645 10:54:57.721266 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2864 skip
9646 10:54:57.721405 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2864 skip
9647 10:54:57.721520 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2864 skip
9648 10:54:57.721632 arm64_sve-ptrace_Set_SVE_VL_2880 pass
9649 10:54:57.721757 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2880 skip
9650 10:54:57.721897 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2880 skip
9651 10:54:57.721998 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2880 skip
9652 10:54:57.722108 arm64_sve-ptrace_Set_SVE_VL_2896 pass
9653 10:54:57.722222 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2896 skip
9654 10:54:57.722351 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2896 skip
9655 10:54:57.722726 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2896 skip
9656 10:54:57.722974 arm64_sve-ptrace_Set_SVE_VL_2912 pass
9657 10:54:57.723143 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2912 skip
9658 10:54:57.723295 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2912 skip
9659 10:54:57.723480 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2912 skip
9660 10:54:57.723650 arm64_sve-ptrace_Set_SVE_VL_2928 pass
9661 10:54:57.723822 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2928 skip
9662 10:54:57.723996 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2928 skip
9663 10:54:57.724167 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2928 skip
9664 10:54:57.724303 arm64_sve-ptrace_Set_SVE_VL_2944 pass
9665 10:54:57.724451 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2944 skip
9666 10:54:57.724574 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2944 skip
9667 10:54:57.724692 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2944 skip
9668 10:54:57.728072 arm64_sve-ptrace_Set_SVE_VL_2960 pass
9669 10:54:57.728443 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2960 skip
9670 10:54:57.728587 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2960 skip
9671 10:54:57.728701 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2960 skip
9672 10:54:57.728811 arm64_sve-ptrace_Set_SVE_VL_2976 pass
9673 10:54:57.728940 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2976 skip
9674 10:54:57.729054 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2976 skip
9675 10:54:57.729168 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2976 skip
9676 10:54:57.729283 arm64_sve-ptrace_Set_SVE_VL_2992 pass
9677 10:54:57.729419 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2992 skip
9678 10:54:57.729535 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2992 skip
9679 10:54:57.729662 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2992 skip
9680 10:54:57.729778 arm64_sve-ptrace_Set_SVE_VL_3008 pass
9681 10:54:57.729911 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3008 skip
9682 10:54:57.730028 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3008 skip
9683 10:54:57.730140 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3008 skip
9684 10:54:57.730272 arm64_sve-ptrace_Set_SVE_VL_3024 pass
9685 10:54:57.756227 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3024 skip
9686 10:54:57.756437 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3024 skip
9687 10:54:57.756522 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3024 skip
9688 10:54:57.756812 arm64_sve-ptrace_Set_SVE_VL_3040 pass
9689 10:54:57.756909 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3040 skip
9690 10:54:57.757024 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3040 skip
9691 10:54:57.757104 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3040 skip
9692 10:54:57.757197 arm64_sve-ptrace_Set_SVE_VL_3056 pass
9693 10:54:57.757291 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3056 skip
9694 10:54:57.757374 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3056 skip
9695 10:54:57.757452 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3056 skip
9696 10:54:57.757542 arm64_sve-ptrace_Set_SVE_VL_3072 pass
9697 10:54:57.757624 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3072 skip
9698 10:54:57.757730 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3072 skip
9699 10:54:57.758024 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3072 skip
9700 10:54:57.758440 arm64_sve-ptrace_Set_SVE_VL_3088 pass
9701 10:54:57.758538 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3088 skip
9702 10:54:57.758622 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3088 skip
9703 10:54:57.758700 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3088 skip
9704 10:54:57.759007 arm64_sve-ptrace_Set_SVE_VL_3104 pass
9705 10:54:57.759109 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3104 skip
9706 10:54:57.759189 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3104 skip
9707 10:54:57.759267 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3104 skip
9708 10:54:57.759344 arm64_sve-ptrace_Set_SVE_VL_3120 pass
9709 10:54:57.759436 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3120 skip
9710 10:54:57.759516 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3120 skip
9711 10:54:57.759593 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3120 skip
9712 10:54:57.759684 arm64_sve-ptrace_Set_SVE_VL_3136 pass
9713 10:54:57.759776 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3136 skip
9714 10:54:57.764164 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3136 skip
9715 10:54:57.764568 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3136 skip
9716 10:54:57.764669 arm64_sve-ptrace_Set_SVE_VL_3152 pass
9717 10:54:57.764761 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3152 skip
9718 10:54:57.764828 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3152 skip
9719 10:54:57.764915 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3152 skip
9720 10:54:57.764993 arm64_sve-ptrace_Set_SVE_VL_3168 pass
9721 10:54:57.765324 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3168 skip
9722 10:54:57.765440 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3168 skip
9723 10:54:57.765513 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3168 skip
9724 10:54:57.765613 arm64_sve-ptrace_Set_SVE_VL_3184 pass
9725 10:54:57.766020 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3184 skip
9726 10:54:57.766127 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3184 skip
9727 10:54:57.766225 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3184 skip
9728 10:54:57.766327 arm64_sve-ptrace_Set_SVE_VL_3200 pass
9729 10:54:57.766435 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3200 skip
9730 10:54:57.766531 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3200 skip
9731 10:54:57.766611 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3200 skip
9732 10:54:57.766689 arm64_sve-ptrace_Set_SVE_VL_3216 pass
9733 10:54:57.766776 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3216 skip
9734 10:54:57.766872 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3216 skip
9735 10:54:57.766957 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3216 skip
9736 10:54:57.767043 arm64_sve-ptrace_Set_SVE_VL_3232 pass
9737 10:54:57.767143 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3232 skip
9738 10:54:57.767456 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3232 skip
9739 10:54:57.767555 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3232 skip
9740 10:54:57.767641 arm64_sve-ptrace_Set_SVE_VL_3248 pass
9741 10:54:57.771762 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3248 skip
9742 10:54:57.772179 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3248 skip
9743 10:54:57.772279 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3248 skip
9744 10:54:57.772361 arm64_sve-ptrace_Set_SVE_VL_3264 pass
9745 10:54:57.772452 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3264 skip
9746 10:54:57.772532 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3264 skip
9747 10:54:57.772621 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3264 skip
9748 10:54:57.772713 arm64_sve-ptrace_Set_SVE_VL_3280 pass
9749 10:54:57.773008 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3280 skip
9750 10:54:57.773101 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3280 skip
9751 10:54:57.773177 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3280 skip
9752 10:54:57.773266 arm64_sve-ptrace_Set_SVE_VL_3296 pass
9753 10:54:57.773341 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3296 skip
9754 10:54:57.773430 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3296 skip
9755 10:54:57.773706 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3296 skip
9756 10:54:57.773787 arm64_sve-ptrace_Set_SVE_VL_3312 pass
9757 10:54:57.773861 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3312 skip
9758 10:54:57.773955 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3312 skip
9759 10:54:57.774211 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3312 skip
9760 10:54:57.774277 arm64_sve-ptrace_Set_SVE_VL_3328 pass
9761 10:54:57.774362 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3328 skip
9762 10:54:57.774451 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3328 skip
9763 10:54:57.774717 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3328 skip
9764 10:54:57.774788 arm64_sve-ptrace_Set_SVE_VL_3344 pass
9765 10:54:57.775035 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3344 skip
9766 10:54:57.775100 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3344 skip
9767 10:54:57.775171 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3344 skip
9768 10:54:57.775416 arm64_sve-ptrace_Set_SVE_VL_3360 pass
9769 10:54:57.775480 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3360 skip
9770 10:54:57.775575 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3360 skip
9771 10:54:57.779979 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3360 skip
9772 10:54:57.780192 arm64_sve-ptrace_Set_SVE_VL_3376 pass
9773 10:54:57.780278 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3376 skip
9774 10:54:57.780569 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3376 skip
9775 10:54:57.780685 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3376 skip
9776 10:54:57.780775 arm64_sve-ptrace_Set_SVE_VL_3392 pass
9777 10:54:57.780869 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3392 skip
9778 10:54:57.781303 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3392 skip
9779 10:54:57.781400 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3392 skip
9780 10:54:57.781478 arm64_sve-ptrace_Set_SVE_VL_3408 pass
9781 10:54:57.781551 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3408 skip
9782 10:54:57.781621 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3408 skip
9783 10:54:57.781890 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3408 skip
9784 10:54:57.781968 arm64_sve-ptrace_Set_SVE_VL_3424 pass
9785 10:54:57.782029 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3424 skip
9786 10:54:57.782906 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3424 skip
9787 10:54:57.783032 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3424 skip
9788 10:54:57.783119 arm64_sve-ptrace_Set_SVE_VL_3440 pass
9789 10:54:57.783203 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3440 skip
9790 10:54:57.783279 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3440 skip
9791 10:54:57.783370 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3440 skip
9792 10:54:57.783457 arm64_sve-ptrace_Set_SVE_VL_3456 pass
9793 10:54:57.783538 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3456 skip
9794 10:54:57.783605 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3456 skip
9795 10:54:57.783695 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3456 skip
9796 10:54:57.783776 arm64_sve-ptrace_Set_SVE_VL_3472 pass
9797 10:54:57.783860 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3472 skip
9798 10:54:57.783936 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3472 skip
9799 10:54:57.787701 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3472 skip
9800 10:54:57.788096 arm64_sve-ptrace_Set_SVE_VL_3488 pass
9801 10:54:57.788189 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3488 skip
9802 10:54:57.788282 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3488 skip
9803 10:54:57.788354 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3488 skip
9804 10:54:57.788435 arm64_sve-ptrace_Set_SVE_VL_3504 pass
9805 10:54:57.788720 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3504 skip
9806 10:54:57.788801 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3504 skip
9807 10:54:57.789101 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3504 skip
9808 10:54:57.789238 arm64_sve-ptrace_Set_SVE_VL_3520 pass
9809 10:54:57.789335 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3520 skip
9810 10:54:57.789463 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3520 skip
9811 10:54:57.789563 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3520 skip
9812 10:54:57.789672 arm64_sve-ptrace_Set_SVE_VL_3536 pass
9813 10:54:57.789790 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3536 skip
9814 10:54:57.789869 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3536 skip
9815 10:54:57.790150 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3536 skip
9816 10:54:57.790258 arm64_sve-ptrace_Set_SVE_VL_3552 pass
9817 10:54:57.790356 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3552 skip
9818 10:54:57.790470 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3552 skip
9819 10:54:57.790568 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3552 skip
9820 10:54:57.790665 arm64_sve-ptrace_Set_SVE_VL_3568 pass
9821 10:54:57.790780 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3568 skip
9822 10:54:57.790870 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3568 skip
9823 10:54:57.790953 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3568 skip
9824 10:54:57.791073 arm64_sve-ptrace_Set_SVE_VL_3584 pass
9825 10:54:57.791189 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3584 skip
9826 10:54:57.791509 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3584 skip
9827 10:54:57.791616 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3584 skip
9828 10:54:57.795745 arm64_sve-ptrace_Set_SVE_VL_3600 pass
9829 10:54:57.796090 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3600 skip
9830 10:54:57.796234 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3600 skip
9831 10:54:57.796328 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3600 skip
9832 10:54:57.796424 arm64_sve-ptrace_Set_SVE_VL_3616 pass
9833 10:54:57.796504 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3616 skip
9834 10:54:57.796593 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3616 skip
9835 10:54:57.796683 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3616 skip
9836 10:54:57.796785 arm64_sve-ptrace_Set_SVE_VL_3632 pass
9837 10:54:57.796891 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3632 skip
9838 10:54:57.797298 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3632 skip
9839 10:54:57.797401 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3632 skip
9840 10:54:57.797490 arm64_sve-ptrace_Set_SVE_VL_3648 pass
9841 10:54:57.797595 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3648 skip
9842 10:54:57.797700 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3648 skip
9843 10:54:57.797815 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3648 skip
9844 10:54:57.797913 arm64_sve-ptrace_Set_SVE_VL_3664 pass
9845 10:54:57.827447 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3664 skip
9846 10:54:57.831705 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3664 skip
9847 10:54:57.831910 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3664 skip
9848 10:54:57.832012 arm64_sve-ptrace_Set_SVE_VL_3680 pass
9849 10:54:57.832123 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3680 skip
9850 10:54:57.832226 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3680 skip
9851 10:54:57.832326 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3680 skip
9852 10:54:57.832426 arm64_sve-ptrace_Set_SVE_VL_3696 pass
9853 10:54:57.832526 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3696 skip
9854 10:54:57.832627 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3696 skip
9855 10:54:57.832726 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3696 skip
9856 10:54:57.832830 arm64_sve-ptrace_Set_SVE_VL_3712 pass
9857 10:54:57.832928 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3712 skip
9858 10:54:57.833026 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3712 skip
9859 10:54:57.833124 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3712 skip
9860 10:54:57.833222 arm64_sve-ptrace_Set_SVE_VL_3728 pass
9861 10:54:57.833319 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3728 skip
9862 10:54:57.833415 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3728 skip
9863 10:54:57.833516 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3728 skip
9864 10:54:57.833613 arm64_sve-ptrace_Set_SVE_VL_3744 pass
9865 10:54:57.833728 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3744 skip
9866 10:54:57.833831 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3744 skip
9867 10:54:57.833929 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3744 skip
9868 10:54:57.834027 arm64_sve-ptrace_Set_SVE_VL_3760 pass
9869 10:54:57.834125 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3760 skip
9870 10:54:57.834224 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3760 skip
9871 10:54:57.834322 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3760 skip
9872 10:54:57.834421 arm64_sve-ptrace_Set_SVE_VL_3776 pass
9873 10:54:57.834519 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3776 skip
9874 10:54:57.834617 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3776 skip
9875 10:54:57.834716 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3776 skip
9876 10:54:57.834819 arm64_sve-ptrace_Set_SVE_VL_3792 pass
9877 10:54:57.834917 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3792 skip
9878 10:54:57.835016 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3792 skip
9879 10:54:57.835111 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3792 skip
9880 10:54:57.835797 arm64_sve-ptrace_Set_SVE_VL_3808 pass
9881 10:54:57.836105 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3808 skip
9882 10:54:57.836233 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3808 skip
9883 10:54:57.836360 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3808 skip
9884 10:54:57.836464 arm64_sve-ptrace_Set_SVE_VL_3824 pass
9885 10:54:57.836582 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3824 skip
9886 10:54:57.836901 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3824 skip
9887 10:54:57.837001 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3824 skip
9888 10:54:57.837117 arm64_sve-ptrace_Set_SVE_VL_3840 pass
9889 10:54:57.837245 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3840 skip
9890 10:54:57.837350 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3840 skip
9891 10:54:57.837800 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3840 skip
9892 10:54:57.837912 arm64_sve-ptrace_Set_SVE_VL_3856 pass
9893 10:54:57.838011 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3856 skip
9894 10:54:57.838107 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3856 skip
9895 10:54:57.838222 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3856 skip
9896 10:54:57.838312 arm64_sve-ptrace_Set_SVE_VL_3872 pass
9897 10:54:57.838394 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3872 skip
9898 10:54:57.838471 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3872 skip
9899 10:54:57.838563 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3872 skip
9900 10:54:57.838655 arm64_sve-ptrace_Set_SVE_VL_3888 pass
9901 10:54:57.838737 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3888 skip
9902 10:54:57.838829 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3888 skip
9903 10:54:57.838910 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3888 skip
9904 10:54:57.839004 arm64_sve-ptrace_Set_SVE_VL_3904 pass
9905 10:54:57.839481 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3904 skip
9906 10:54:57.839617 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3904 skip
9907 10:54:57.839916 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3904 skip
9908 10:54:57.843668 arm64_sve-ptrace_Set_SVE_VL_3920 pass
9909 10:54:57.844051 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3920 skip
9910 10:54:57.844164 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3920 skip
9911 10:54:57.844271 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3920 skip
9912 10:54:57.844357 arm64_sve-ptrace_Set_SVE_VL_3936 pass
9913 10:54:57.844457 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3936 skip
9914 10:54:57.844757 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3936 skip
9915 10:54:57.844862 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3936 skip
9916 10:54:57.844972 arm64_sve-ptrace_Set_SVE_VL_3952 pass
9917 10:54:57.845328 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3952 skip
9918 10:54:57.845434 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3952 skip
9919 10:54:57.845544 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3952 skip
9920 10:54:57.845640 arm64_sve-ptrace_Set_SVE_VL_3968 pass
9921 10:54:57.845762 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3968 skip
9922 10:54:57.845871 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3968 skip
9923 10:54:57.845973 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3968 skip
9924 10:54:57.846101 arm64_sve-ptrace_Set_SVE_VL_3984 pass
9925 10:54:57.846218 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3984 skip
9926 10:54:57.846296 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3984 skip
9927 10:54:57.846405 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3984 skip
9928 10:54:57.846482 arm64_sve-ptrace_Set_SVE_VL_4000 pass
9929 10:54:57.846556 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4000 skip
9930 10:54:57.846644 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4000 skip
9931 10:54:57.846765 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4000 skip
9932 10:54:57.846857 arm64_sve-ptrace_Set_SVE_VL_4016 pass
9933 10:54:57.847232 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4016 skip
9934 10:54:57.847343 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4016 skip
9935 10:54:57.847445 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4016 skip
9936 10:54:57.847560 arm64_sve-ptrace_Set_SVE_VL_4032 pass
9937 10:54:57.851630 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4032 skip
9938 10:54:57.851950 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4032 skip
9939 10:54:57.852063 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4032 skip
9940 10:54:57.852183 arm64_sve-ptrace_Set_SVE_VL_4048 pass
9941 10:54:57.852299 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4048 skip
9942 10:54:57.852405 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4048 skip
9943 10:54:57.852509 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4048 skip
9944 10:54:57.852813 arm64_sve-ptrace_Set_SVE_VL_4064 pass
9945 10:54:57.852921 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4064 skip
9946 10:54:57.853037 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4064 skip
9947 10:54:57.853135 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4064 skip
9948 10:54:57.853226 arm64_sve-ptrace_Set_SVE_VL_4080 pass
9949 10:54:57.853319 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4080 skip
9950 10:54:57.853424 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4080 skip
9951 10:54:57.853716 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4080 skip
9952 10:54:57.853839 arm64_sve-ptrace_Set_SVE_VL_4096 pass
9953 10:54:57.854173 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4096 skip
9954 10:54:57.854281 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4096 skip
9955 10:54:57.854383 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4096 skip
9956 10:54:57.854495 arm64_sve-ptrace_Set_SVE_VL_4112 pass
9957 10:54:57.854613 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4112 skip
9958 10:54:57.854718 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4112 skip
9959 10:54:57.854839 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4112 skip
9960 10:54:57.854926 arm64_sve-ptrace_Set_SVE_VL_4128 pass
9961 10:54:57.855028 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4128 skip
9962 10:54:57.855137 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4128 skip
9963 10:54:57.855480 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4128 skip
9964 10:54:57.855596 arm64_sve-ptrace_Set_SVE_VL_4144 pass
9965 10:54:57.859713 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4144 skip
9966 10:54:57.860004 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4144 skip
9967 10:54:57.860106 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4144 skip
9968 10:54:57.860363 arm64_sve-ptrace_Set_SVE_VL_4160 pass
9969 10:54:57.860442 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4160 skip
9970 10:54:57.860519 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4160 skip
9971 10:54:57.860767 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4160 skip
9972 10:54:57.860849 arm64_sve-ptrace_Set_SVE_VL_4176 pass
9973 10:54:57.863209 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4176 skip
9974 10:54:57.863279 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4176 skip
9975 10:54:57.863342 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4176 skip
9976 10:54:57.863402 arm64_sve-ptrace_Set_SVE_VL_4192 pass
9977 10:54:57.863462 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4192 skip
9978 10:54:57.863523 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4192 skip
9979 10:54:57.863584 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4192 skip
9980 10:54:57.863644 arm64_sve-ptrace_Set_SVE_VL_4208 pass
9981 10:54:57.863705 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4208 skip
9982 10:54:57.863766 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4208 skip
9983 10:54:57.863831 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4208 skip
9984 10:54:57.863892 arm64_sve-ptrace_Set_SVE_VL_4224 pass
9985 10:54:57.863952 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4224 skip
9986 10:54:57.864013 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4224 skip
9987 10:54:57.864074 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4224 skip
9988 10:54:57.864135 arm64_sve-ptrace_Set_SVE_VL_4240 pass
9989 10:54:57.864194 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4240 skip
9990 10:54:57.864435 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4240 skip
9991 10:54:57.864501 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4240 skip
9992 10:54:57.864562 arm64_sve-ptrace_Set_SVE_VL_4256 pass
9993 10:54:57.864622 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4256 skip
9994 10:54:57.867670 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4256 skip
9995 10:54:57.867919 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4256 skip
9996 10:54:57.867989 arm64_sve-ptrace_Set_SVE_VL_4272 pass
9997 10:54:57.868068 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4272 skip
9998 10:54:57.868145 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4272 skip
9999 10:54:57.868416 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4272 skip
10000 10:54:57.868514 arm64_sve-ptrace_Set_SVE_VL_4288 pass
10001 10:54:57.868637 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4288 skip
10002 10:54:57.868735 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4288 skip
10003 10:54:57.868850 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4288 skip
10004 10:54:57.868954 arm64_sve-ptrace_Set_SVE_VL_4304 pass
10005 10:54:57.896804 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4304 skip
10006 10:54:57.897208 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4304 skip
10007 10:54:57.897315 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4304 skip
10008 10:54:57.897408 arm64_sve-ptrace_Set_SVE_VL_4320 pass
10009 10:54:57.897506 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4320 skip
10010 10:54:57.897776 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4320 skip
10011 10:54:57.897866 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4320 skip
10012 10:54:57.897943 arm64_sve-ptrace_Set_SVE_VL_4336 pass
10013 10:54:57.898050 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4336 skip
10014 10:54:57.898158 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4336 skip
10015 10:54:57.898279 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4336 skip
10016 10:54:57.898377 arm64_sve-ptrace_Set_SVE_VL_4352 pass
10017 10:54:57.898472 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4352 skip
10018 10:54:57.898587 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4352 skip
10019 10:54:57.898684 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4352 skip
10020 10:54:57.898779 arm64_sve-ptrace_Set_SVE_VL_4368 pass
10021 10:54:57.898892 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4368 skip
10022 10:54:57.898990 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4368 skip
10023 10:54:57.899085 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4368 skip
10024 10:54:57.899198 arm64_sve-ptrace_Set_SVE_VL_4384 pass
10025 10:54:57.899294 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4384 skip
10026 10:54:57.899406 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4384 skip
10027 10:54:57.899518 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4384 skip
10028 10:54:57.903811 arm64_sve-ptrace_Set_SVE_VL_4400 pass
10029 10:54:57.904068 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4400 skip
10030 10:54:57.904460 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4400 skip
10031 10:54:57.904630 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4400 skip
10032 10:54:57.904756 arm64_sve-ptrace_Set_SVE_VL_4416 pass
10033 10:54:57.904878 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4416 skip
10034 10:54:57.905074 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4416 skip
10035 10:54:57.905290 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4416 skip
10036 10:54:57.905477 arm64_sve-ptrace_Set_SVE_VL_4432 pass
10037 10:54:57.905735 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4432 skip
10038 10:54:57.905940 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4432 skip
10039 10:54:57.906117 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4432 skip
10040 10:54:57.906277 arm64_sve-ptrace_Set_SVE_VL_4448 pass
10041 10:54:57.906435 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4448 skip
10042 10:54:57.906620 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4448 skip
10043 10:54:57.907367 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4448 skip
10044 10:54:57.907544 arm64_sve-ptrace_Set_SVE_VL_4464 pass
10045 10:54:57.907765 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4464 skip
10046 10:54:57.907952 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4464 skip
10047 10:54:57.908171 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4464 skip
10048 10:54:57.908321 arm64_sve-ptrace_Set_SVE_VL_4480 pass
10049 10:54:57.908471 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4480 skip
10050 10:54:57.908632 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4480 skip
10051 10:54:57.908792 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4480 skip
10052 10:54:57.908955 arm64_sve-ptrace_Set_SVE_VL_4496 pass
10053 10:54:57.909471 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4496 skip
10054 10:54:57.911653 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4496 skip
10055 10:54:57.912158 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4496 skip
10056 10:54:57.912258 arm64_sve-ptrace_Set_SVE_VL_4512 pass
10057 10:54:57.912353 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4512 skip
10058 10:54:57.912443 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4512 skip
10059 10:54:57.912721 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4512 skip
10060 10:54:57.912822 arm64_sve-ptrace_Set_SVE_VL_4528 pass
10061 10:54:57.912937 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4528 skip
10062 10:54:57.913058 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4528 skip
10063 10:54:57.913157 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4528 skip
10064 10:54:57.913263 arm64_sve-ptrace_Set_SVE_VL_4544 pass
10065 10:54:57.913386 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4544 skip
10066 10:54:57.913494 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4544 skip
10067 10:54:57.913796 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4544 skip
10068 10:54:57.913914 arm64_sve-ptrace_Set_SVE_VL_4560 pass
10069 10:54:57.914032 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4560 skip
10070 10:54:57.914153 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4560 skip
10071 10:54:57.914274 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4560 skip
10072 10:54:57.914402 arm64_sve-ptrace_Set_SVE_VL_4576 pass
10073 10:54:57.914505 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4576 skip
10074 10:54:57.914609 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4576 skip
10075 10:54:57.914716 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4576 skip
10076 10:54:57.914816 arm64_sve-ptrace_Set_SVE_VL_4592 pass
10077 10:54:57.914922 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4592 skip
10078 10:54:57.915027 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4592 skip
10079 10:54:57.915147 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4592 skip
10080 10:54:57.915276 arm64_sve-ptrace_Set_SVE_VL_4608 pass
10081 10:54:57.915387 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4608 skip
10082 10:54:57.915495 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4608 skip
10083 10:54:57.915620 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4608 skip
10084 10:54:57.915721 arm64_sve-ptrace_Set_SVE_VL_4624 pass
10085 10:54:57.919986 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4624 skip
10086 10:54:57.920086 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4624 skip
10087 10:54:57.920620 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4624 skip
10088 10:54:57.920716 arm64_sve-ptrace_Set_SVE_VL_4640 pass
10089 10:54:57.920822 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4640 skip
10090 10:54:57.920921 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4640 skip
10091 10:54:57.921038 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4640 skip
10092 10:54:57.921137 arm64_sve-ptrace_Set_SVE_VL_4656 pass
10093 10:54:57.921248 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4656 skip
10094 10:54:57.921332 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4656 skip
10095 10:54:57.921428 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4656 skip
10096 10:54:57.921512 arm64_sve-ptrace_Set_SVE_VL_4672 pass
10097 10:54:57.921590 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4672 skip
10098 10:54:57.921698 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4672 skip
10099 10:54:57.921801 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4672 skip
10100 10:54:57.921902 arm64_sve-ptrace_Set_SVE_VL_4688 pass
10101 10:54:57.922196 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4688 skip
10102 10:54:57.922298 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4688 skip
10103 10:54:57.922401 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4688 skip
10104 10:54:57.922500 arm64_sve-ptrace_Set_SVE_VL_4704 pass
10105 10:54:57.922633 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4704 skip
10106 10:54:57.922770 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4704 skip
10107 10:54:57.922903 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4704 skip
10108 10:54:57.922995 arm64_sve-ptrace_Set_SVE_VL_4720 pass
10109 10:54:57.923094 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4720 skip
10110 10:54:57.923193 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4720 skip
10111 10:54:57.923291 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4720 skip
10112 10:54:57.923572 arm64_sve-ptrace_Set_SVE_VL_4736 pass
10113 10:54:57.927690 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4736 skip
10114 10:54:57.927970 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4736 skip
10115 10:54:57.928072 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4736 skip
10116 10:54:57.928227 arm64_sve-ptrace_Set_SVE_VL_4752 pass
10117 10:54:57.928325 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4752 skip
10118 10:54:57.928427 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4752 skip
10119 10:54:57.928507 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4752 skip
10120 10:54:57.928601 arm64_sve-ptrace_Set_SVE_VL_4768 pass
10121 10:54:57.928777 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4768 skip
10122 10:54:57.928909 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4768 skip
10123 10:54:57.929005 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4768 skip
10124 10:54:57.929114 arm64_sve-ptrace_Set_SVE_VL_4784 pass
10125 10:54:57.929226 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4784 skip
10126 10:54:57.929361 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4784 skip
10127 10:54:57.929484 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4784 skip
10128 10:54:57.929576 arm64_sve-ptrace_Set_SVE_VL_4800 pass
10129 10:54:57.929680 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4800 skip
10130 10:54:57.929782 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4800 skip
10131 10:54:57.929914 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4800 skip
10132 10:54:57.930224 arm64_sve-ptrace_Set_SVE_VL_4816 pass
10133 10:54:57.930327 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4816 skip
10134 10:54:57.930442 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4816 skip
10135 10:54:57.930557 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4816 skip
10136 10:54:57.930672 arm64_sve-ptrace_Set_SVE_VL_4832 pass
10137 10:54:57.930785 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4832 skip
10138 10:54:57.931098 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4832 skip
10139 10:54:57.931410 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4832 skip
10140 10:54:57.931499 arm64_sve-ptrace_Set_SVE_VL_4848 pass
10141 10:54:57.931567 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4848 skip
10142 10:54:57.931659 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4848 skip
10143 10:54:57.935712 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4848 skip
10144 10:54:57.936037 arm64_sve-ptrace_Set_SVE_VL_4864 pass
10145 10:54:57.936136 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4864 skip
10146 10:54:57.936233 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4864 skip
10147 10:54:57.936545 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4864 skip
10148 10:54:57.936649 arm64_sve-ptrace_Set_SVE_VL_4880 pass
10149 10:54:57.936765 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4880 skip
10150 10:54:57.936855 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4880 skip
10151 10:54:57.936950 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4880 skip
10152 10:54:57.937069 arm64_sve-ptrace_Set_SVE_VL_4896 pass
10153 10:54:57.937158 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4896 skip
10154 10:54:57.937244 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4896 skip
10155 10:54:57.937331 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4896 skip
10156 10:54:57.937436 arm64_sve-ptrace_Set_SVE_VL_4912 pass
10157 10:54:57.937565 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4912 skip
10158 10:54:57.937686 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4912 skip
10159 10:54:57.937800 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4912 skip
10160 10:54:57.937908 arm64_sve-ptrace_Set_SVE_VL_4928 pass
10161 10:54:57.938010 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4928 skip
10162 10:54:57.938111 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4928 skip
10163 10:54:57.938183 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4928 skip
10164 10:54:57.938259 arm64_sve-ptrace_Set_SVE_VL_4944 pass
10165 10:54:57.962786 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4944 skip
10166 10:54:57.963243 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4944 skip
10167 10:54:57.963341 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4944 skip
10168 10:54:57.963431 arm64_sve-ptrace_Set_SVE_VL_4960 pass
10169 10:54:57.963503 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4960 skip
10170 10:54:57.963585 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4960 skip
10171 10:54:57.963837 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4960 skip
10172 10:54:57.963918 arm64_sve-ptrace_Set_SVE_VL_4976 pass
10173 10:54:57.964002 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4976 skip
10174 10:54:57.964272 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4976 skip
10175 10:54:57.964547 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4976 skip
10176 10:54:57.964620 arm64_sve-ptrace_Set_SVE_VL_4992 pass
10177 10:54:57.964698 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4992 skip
10178 10:54:57.964776 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4992 skip
10179 10:54:57.965046 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4992 skip
10180 10:54:57.965129 arm64_sve-ptrace_Set_SVE_VL_5008 pass
10181 10:54:57.965386 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5008 skip
10182 10:54:57.965457 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5008 skip
10183 10:54:57.965678 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5008 skip
10184 10:54:57.965748 arm64_sve-ptrace_Set_SVE_VL_5024 pass
10185 10:54:57.965823 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5024 skip
10186 10:54:57.965899 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5024 skip
10187 10:54:57.966151 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5024 skip
10188 10:54:57.966232 arm64_sve-ptrace_Set_SVE_VL_5040 pass
10189 10:54:57.966310 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5040 skip
10190 10:54:57.966576 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5040 skip
10191 10:54:57.966672 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5040 skip
10192 10:54:57.966750 arm64_sve-ptrace_Set_SVE_VL_5056 pass
10193 10:54:57.967008 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5056 skip
10194 10:54:57.967090 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5056 skip
10195 10:54:57.967344 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5056 skip
10196 10:54:57.967599 arm64_sve-ptrace_Set_SVE_VL_5072 pass
10197 10:54:57.971768 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5072 skip
10198 10:54:57.972058 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5072 skip
10199 10:54:57.972160 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5072 skip
10200 10:54:57.972277 arm64_sve-ptrace_Set_SVE_VL_5088 pass
10201 10:54:57.972381 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5088 skip
10202 10:54:57.972494 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5088 skip
10203 10:54:57.972583 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5088 skip
10204 10:54:57.972674 arm64_sve-ptrace_Set_SVE_VL_5104 pass
10205 10:54:57.972994 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5104 skip
10206 10:54:57.973133 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5104 skip
10207 10:54:57.973222 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5104 skip
10208 10:54:57.973304 arm64_sve-ptrace_Set_SVE_VL_5120 pass
10209 10:54:57.973584 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5120 skip
10210 10:54:57.973703 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5120 skip
10211 10:54:57.973797 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5120 skip
10212 10:54:57.973891 arm64_sve-ptrace_Set_SVE_VL_5136 pass
10213 10:54:57.973983 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5136 skip
10214 10:54:57.974253 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5136 skip
10215 10:54:57.974337 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5136 skip
10216 10:54:57.974448 arm64_sve-ptrace_Set_SVE_VL_5152 pass
10217 10:54:57.974789 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5152 skip
10218 10:54:57.974923 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5152 skip
10219 10:54:57.975271 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5152 skip
10220 10:54:57.975377 arm64_sve-ptrace_Set_SVE_VL_5168 pass
10221 10:54:57.975484 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5168 skip
10222 10:54:57.975609 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5168 skip
10223 10:54:57.975693 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5168 skip
10224 10:54:57.979797 arm64_sve-ptrace_Set_SVE_VL_5184 pass
10225 10:54:57.980104 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5184 skip
10226 10:54:57.980390 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5184 skip
10227 10:54:57.980485 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5184 skip
10228 10:54:57.980580 arm64_sve-ptrace_Set_SVE_VL_5200 pass
10229 10:54:57.980675 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5200 skip
10230 10:54:57.980784 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5200 skip
10231 10:54:57.981089 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5200 skip
10232 10:54:57.981189 arm64_sve-ptrace_Set_SVE_VL_5216 pass
10233 10:54:57.981303 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5216 skip
10234 10:54:57.981618 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5216 skip
10235 10:54:57.981726 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5216 skip
10236 10:54:57.981806 arm64_sve-ptrace_Set_SVE_VL_5232 pass
10237 10:54:57.982099 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5232 skip
10238 10:54:57.982217 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5232 skip
10239 10:54:57.982334 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5232 skip
10240 10:54:57.982446 arm64_sve-ptrace_Set_SVE_VL_5248 pass
10241 10:54:57.982557 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5248 skip
10242 10:54:57.982668 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5248 skip
10243 10:54:57.982979 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5248 skip
10244 10:54:57.983116 arm64_sve-ptrace_Set_SVE_VL_5264 pass
10245 10:54:57.983425 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5264 skip
10246 10:54:57.983564 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5264 skip
10247 10:54:57.987754 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5264 skip
10248 10:54:57.988136 arm64_sve-ptrace_Set_SVE_VL_5280 pass
10249 10:54:57.988233 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5280 skip
10250 10:54:57.988316 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5280 skip
10251 10:54:57.988409 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5280 skip
10252 10:54:57.988491 arm64_sve-ptrace_Set_SVE_VL_5296 pass
10253 10:54:57.988579 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5296 skip
10254 10:54:57.988873 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5296 skip
10255 10:54:57.988990 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5296 skip
10256 10:54:57.989095 arm64_sve-ptrace_Set_SVE_VL_5312 pass
10257 10:54:57.989208 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5312 skip
10258 10:54:57.989306 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5312 skip
10259 10:54:57.989422 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5312 skip
10260 10:54:57.989520 arm64_sve-ptrace_Set_SVE_VL_5328 pass
10261 10:54:57.989632 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5328 skip
10262 10:54:57.989758 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5328 skip
10263 10:54:57.989869 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5328 skip
10264 10:54:57.989981 arm64_sve-ptrace_Set_SVE_VL_5344 pass
10265 10:54:57.990097 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5344 skip
10266 10:54:57.990397 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5344 skip
10267 10:54:57.990513 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5344 skip
10268 10:54:57.990612 arm64_sve-ptrace_Set_SVE_VL_5360 pass
10269 10:54:57.990725 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5360 skip
10270 10:54:57.990823 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5360 skip
10271 10:54:57.990935 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5360 skip
10272 10:54:57.991033 arm64_sve-ptrace_Set_SVE_VL_5376 pass
10273 10:54:57.991150 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5376 skip
10274 10:54:57.991453 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5376 skip
10275 10:54:57.991568 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5376 skip
10276 10:54:57.991666 arm64_sve-ptrace_Set_SVE_VL_5392 pass
10277 10:54:57.996034 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5392 skip
10278 10:54:57.996349 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5392 skip
10279 10:54:57.996438 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5392 skip
10280 10:54:57.996541 arm64_sve-ptrace_Set_SVE_VL_5408 pass
10281 10:54:57.996652 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5408 skip
10282 10:54:57.996740 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5408 skip
10283 10:54:57.996837 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5408 skip
10284 10:54:57.996955 arm64_sve-ptrace_Set_SVE_VL_5424 pass
10285 10:54:57.997040 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5424 skip
10286 10:54:57.997137 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5424 skip
10287 10:54:57.997223 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5424 skip
10288 10:54:57.997479 arm64_sve-ptrace_Set_SVE_VL_5440 pass
10289 10:54:57.997550 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5440 skip
10290 10:54:57.997639 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5440 skip
10291 10:54:57.997919 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5440 skip
10292 10:54:57.997990 arm64_sve-ptrace_Set_SVE_VL_5456 pass
10293 10:54:57.998085 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5456 skip
10294 10:54:57.998412 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5456 skip
10295 10:54:57.998572 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5456 skip
10296 10:54:57.998720 arm64_sve-ptrace_Set_SVE_VL_5472 pass
10297 10:54:57.999085 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5472 skip
10298 10:54:57.999185 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5472 skip
10299 10:54:57.999281 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5472 skip
10300 10:54:57.999378 arm64_sve-ptrace_Set_SVE_VL_5488 pass
10301 10:54:57.999481 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5488 skip
10302 10:54:57.999588 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5488 skip
10303 10:54:57.999677 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5488 skip
10304 10:54:57.999763 arm64_sve-ptrace_Set_SVE_VL_5504 pass
10305 10:54:58.003795 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5504 skip
10306 10:54:58.004138 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5504 skip
10307 10:54:58.004251 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5504 skip
10308 10:54:58.004377 arm64_sve-ptrace_Set_SVE_VL_5520 pass
10309 10:54:58.004478 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5520 skip
10310 10:54:58.004573 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5520 skip
10311 10:54:58.004679 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5520 skip
10312 10:54:58.004763 arm64_sve-ptrace_Set_SVE_VL_5536 pass
10313 10:54:58.004854 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5536 skip
10314 10:54:58.004933 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5536 skip
10315 10:54:58.005017 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5536 skip
10316 10:54:58.005112 arm64_sve-ptrace_Set_SVE_VL_5552 pass
10317 10:54:58.005232 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5552 skip
10318 10:54:58.005352 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5552 skip
10319 10:54:58.005466 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5552 skip
10320 10:54:58.005561 arm64_sve-ptrace_Set_SVE_VL_5568 pass
10321 10:54:58.005673 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5568 skip
10322 10:54:58.005991 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5568 skip
10323 10:54:58.006093 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5568 skip
10324 10:54:58.006171 arm64_sve-ptrace_Set_SVE_VL_5584 pass
10325 10:54:58.024868 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5584 skip
10326 10:54:58.025171 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5584 skip
10327 10:54:58.025276 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5584 skip
10328 10:54:58.025384 arm64_sve-ptrace_Set_SVE_VL_5600 pass
10329 10:54:58.025486 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5600 skip
10330 10:54:58.025816 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5600 skip
10331 10:54:58.025917 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5600 skip
10332 10:54:58.026013 arm64_sve-ptrace_Set_SVE_VL_5616 pass
10333 10:54:58.026131 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5616 skip
10334 10:54:58.026411 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5616 skip
10335 10:54:58.026516 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5616 skip
10336 10:54:58.026606 arm64_sve-ptrace_Set_SVE_VL_5632 pass
10337 10:54:58.026684 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5632 skip
10338 10:54:58.026761 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5632 skip
10339 10:54:58.026861 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5632 skip
10340 10:54:58.026968 arm64_sve-ptrace_Set_SVE_VL_5648 pass
10341 10:54:58.027050 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5648 skip
10342 10:54:58.027139 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5648 skip
10343 10:54:58.027242 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5648 skip
10344 10:54:58.027339 arm64_sve-ptrace_Set_SVE_VL_5664 pass
10345 10:54:58.027454 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5664 skip
10346 10:54:58.027552 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5664 skip
10347 10:54:58.027666 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5664 skip
10348 10:54:58.027763 arm64_sve-ptrace_Set_SVE_VL_5680 pass
10349 10:54:58.031735 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5680 skip
10350 10:54:58.032012 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5680 skip
10351 10:54:58.032097 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5680 skip
10352 10:54:58.032196 arm64_sve-ptrace_Set_SVE_VL_5696 pass
10353 10:54:58.032281 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5696 skip
10354 10:54:58.032539 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5696 skip
10355 10:54:58.032625 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5696 skip
10356 10:54:58.032747 arm64_sve-ptrace_Set_SVE_VL_5712 pass
10357 10:54:58.032830 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5712 skip
10358 10:54:58.032923 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5712 skip
10359 10:54:58.033009 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5712 skip
10360 10:54:58.033280 arm64_sve-ptrace_Set_SVE_VL_5728 pass
10361 10:54:58.033375 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5728 skip
10362 10:54:58.033492 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5728 skip
10363 10:54:58.033610 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5728 skip
10364 10:54:58.033717 arm64_sve-ptrace_Set_SVE_VL_5744 pass
10365 10:54:58.033999 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5744 skip
10366 10:54:58.034094 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5744 skip
10367 10:54:58.034205 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5744 skip
10368 10:54:58.034329 arm64_sve-ptrace_Set_SVE_VL_5760 pass
10369 10:54:58.034439 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5760 skip
10370 10:54:58.034554 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5760 skip
10371 10:54:58.034672 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5760 skip
10372 10:54:58.034764 arm64_sve-ptrace_Set_SVE_VL_5776 pass
10373 10:54:58.034857 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5776 skip
10374 10:54:58.035137 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5776 skip
10375 10:54:58.035242 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5776 skip
10376 10:54:58.035340 arm64_sve-ptrace_Set_SVE_VL_5792 pass
10377 10:54:58.035447 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5792 skip
10378 10:54:58.039767 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5792 skip
10379 10:54:58.040056 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5792 skip
10380 10:54:58.040158 arm64_sve-ptrace_Set_SVE_VL_5808 pass
10381 10:54:58.040283 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5808 skip
10382 10:54:58.040410 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5808 skip
10383 10:54:58.040503 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5808 skip
10384 10:54:58.040604 arm64_sve-ptrace_Set_SVE_VL_5824 pass
10385 10:54:58.040718 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5824 skip
10386 10:54:58.040829 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5824 skip
10387 10:54:58.041157 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5824 skip
10388 10:54:58.041307 arm64_sve-ptrace_Set_SVE_VL_5840 pass
10389 10:54:58.041455 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5840 skip
10390 10:54:58.041587 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5840 skip
10391 10:54:58.041714 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5840 skip
10392 10:54:58.041849 arm64_sve-ptrace_Set_SVE_VL_5856 pass
10393 10:54:58.041965 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5856 skip
10394 10:54:58.042102 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5856 skip
10395 10:54:58.042225 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5856 skip
10396 10:54:58.042344 arm64_sve-ptrace_Set_SVE_VL_5872 pass
10397 10:54:58.042468 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5872 skip
10398 10:54:58.042563 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5872 skip
10399 10:54:58.042671 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5872 skip
10400 10:54:58.042777 arm64_sve-ptrace_Set_SVE_VL_5888 pass
10401 10:54:58.042903 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5888 skip
10402 10:54:58.043212 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5888 skip
10403 10:54:58.043302 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5888 skip
10404 10:54:58.043383 arm64_sve-ptrace_Set_SVE_VL_5904 pass
10405 10:54:58.043458 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5904 skip
10406 10:54:58.047890 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5904 skip
10407 10:54:58.047982 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5904 skip
10408 10:54:58.048234 arm64_sve-ptrace_Set_SVE_VL_5920 pass
10409 10:54:58.048310 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5920 skip
10410 10:54:58.048385 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5920 skip
10411 10:54:58.048459 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5920 skip
10412 10:54:58.048708 arm64_sve-ptrace_Set_SVE_VL_5936 pass
10413 10:54:58.048957 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5936 skip
10414 10:54:58.049051 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5936 skip
10415 10:54:58.049150 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5936 skip
10416 10:54:58.049226 arm64_sve-ptrace_Set_SVE_VL_5952 pass
10417 10:54:58.049306 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5952 skip
10418 10:54:58.049383 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5952 skip
10419 10:54:58.049657 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5952 skip
10420 10:54:58.049744 arm64_sve-ptrace_Set_SVE_VL_5968 pass
10421 10:54:58.049858 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5968 skip
10422 10:54:58.050134 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5968 skip
10423 10:54:58.050220 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5968 skip
10424 10:54:58.050338 arm64_sve-ptrace_Set_SVE_VL_5984 pass
10425 10:54:58.050431 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5984 skip
10426 10:54:58.050555 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5984 skip
10427 10:54:58.050658 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5984 skip
10428 10:54:58.050772 arm64_sve-ptrace_Set_SVE_VL_6000 pass
10429 10:54:58.050879 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6000 skip
10430 10:54:58.051148 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6000 skip
10431 10:54:58.051244 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6000 skip
10432 10:54:58.051336 arm64_sve-ptrace_Set_SVE_VL_6016 pass
10433 10:54:58.055795 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6016 skip
10434 10:54:58.056141 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6016 skip
10435 10:54:58.056257 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6016 skip
10436 10:54:58.056358 arm64_sve-ptrace_Set_SVE_VL_6032 pass
10437 10:54:58.056480 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6032 skip
10438 10:54:58.056581 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6032 skip
10439 10:54:58.056708 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6032 skip
10440 10:54:58.056813 arm64_sve-ptrace_Set_SVE_VL_6048 pass
10441 10:54:58.056937 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6048 skip
10442 10:54:58.057021 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6048 skip
10443 10:54:58.057113 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6048 skip
10444 10:54:58.057229 arm64_sve-ptrace_Set_SVE_VL_6064 pass
10445 10:54:58.057538 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6064 skip
10446 10:54:58.057654 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6064 skip
10447 10:54:58.057772 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6064 skip
10448 10:54:58.057887 arm64_sve-ptrace_Set_SVE_VL_6080 pass
10449 10:54:58.057998 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6080 skip
10450 10:54:58.058355 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6080 skip
10451 10:54:58.058565 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6080 skip
10452 10:54:58.058730 arm64_sve-ptrace_Set_SVE_VL_6096 pass
10453 10:54:58.058921 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6096 skip
10454 10:54:58.059112 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6096 skip
10455 10:54:58.059278 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6096 skip
10456 10:54:58.059443 arm64_sve-ptrace_Set_SVE_VL_6112 pass
10457 10:54:58.059630 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6112 skip
10458 10:54:58.059761 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6112 skip
10459 10:54:58.059876 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6112 skip
10460 10:54:58.059991 arm64_sve-ptrace_Set_SVE_VL_6128 pass
10461 10:54:58.063759 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6128 skip
10462 10:54:58.064215 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6128 skip
10463 10:54:58.064406 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6128 skip
10464 10:54:58.064583 arm64_sve-ptrace_Set_SVE_VL_6144 pass
10465 10:54:58.064780 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6144 skip
10466 10:54:58.065000 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6144 skip
10467 10:54:58.065165 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6144 skip
10468 10:54:58.065318 arm64_sve-ptrace_Set_SVE_VL_6160 pass
10469 10:54:58.065463 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6160 skip
10470 10:54:58.065607 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6160 skip
10471 10:54:58.065844 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6160 skip
10472 10:54:58.066028 arm64_sve-ptrace_Set_SVE_VL_6176 pass
10473 10:54:58.066184 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6176 skip
10474 10:54:58.066403 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6176 skip
10475 10:54:58.066608 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6176 skip
10476 10:54:58.066806 arm64_sve-ptrace_Set_SVE_VL_6192 pass
10477 10:54:58.066988 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6192 skip
10478 10:54:58.067211 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6192 skip
10479 10:54:58.067381 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6192 skip
10480 10:54:58.067526 arm64_sve-ptrace_Set_SVE_VL_6208 pass
10481 10:54:58.067660 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6208 skip
10482 10:54:58.067802 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6208 skip
10483 10:54:58.067948 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6208 skip
10484 10:54:58.068086 arm64_sve-ptrace_Set_SVE_VL_6224 pass
10485 10:54:58.090767 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6224 skip
10486 10:54:58.091003 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6224 skip
10487 10:54:58.091197 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6224 skip
10488 10:54:58.091629 arm64_sve-ptrace_Set_SVE_VL_6240 pass
10489 10:54:58.091843 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6240 skip
10490 10:54:58.092037 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6240 skip
10491 10:54:58.092224 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6240 skip
10492 10:54:58.092413 arm64_sve-ptrace_Set_SVE_VL_6256 pass
10493 10:54:58.092638 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6256 skip
10494 10:54:58.092828 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6256 skip
10495 10:54:58.093015 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6256 skip
10496 10:54:58.093202 arm64_sve-ptrace_Set_SVE_VL_6272 pass
10497 10:54:58.093389 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6272 skip
10498 10:54:58.093574 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6272 skip
10499 10:54:58.093800 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6272 skip
10500 10:54:58.093993 arm64_sve-ptrace_Set_SVE_VL_6288 pass
10501 10:54:58.094225 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6288 skip
10502 10:54:58.094438 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6288 skip
10503 10:54:58.094626 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6288 skip
10504 10:54:58.094808 arm64_sve-ptrace_Set_SVE_VL_6304 pass
10505 10:54:58.094976 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6304 skip
10506 10:54:58.095152 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6304 skip
10507 10:54:58.095311 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6304 skip
10508 10:54:58.095497 arm64_sve-ptrace_Set_SVE_VL_6320 pass
10509 10:54:58.095629 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6320 skip
10510 10:54:58.095744 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6320 skip
10511 10:54:58.095890 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6320 skip
10512 10:54:58.096011 arm64_sve-ptrace_Set_SVE_VL_6336 pass
10513 10:54:58.096127 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6336 skip
10514 10:54:58.096241 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6336 skip
10515 10:54:58.096354 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6336 skip
10516 10:54:58.096467 arm64_sve-ptrace_Set_SVE_VL_6352 pass
10517 10:54:58.096580 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6352 skip
10518 10:54:58.096693 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6352 skip
10519 10:54:58.096805 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6352 skip
10520 10:54:58.096919 arm64_sve-ptrace_Set_SVE_VL_6368 pass
10521 10:54:58.097032 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6368 skip
10522 10:54:58.097145 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6368 skip
10523 10:54:58.097257 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6368 skip
10524 10:54:58.097369 arm64_sve-ptrace_Set_SVE_VL_6384 pass
10525 10:54:58.099872 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6384 skip
10526 10:54:58.100329 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6384 skip
10527 10:54:58.100528 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6384 skip
10528 10:54:58.100701 arm64_sve-ptrace_Set_SVE_VL_6400 pass
10529 10:54:58.100876 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6400 skip
10530 10:54:58.101068 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6400 skip
10531 10:54:58.101210 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6400 skip
10532 10:54:58.101367 arm64_sve-ptrace_Set_SVE_VL_6416 pass
10533 10:54:58.101506 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6416 skip
10534 10:54:58.101670 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6416 skip
10535 10:54:58.101862 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6416 skip
10536 10:54:58.102016 arm64_sve-ptrace_Set_SVE_VL_6432 pass
10537 10:54:58.102189 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6432 skip
10538 10:54:58.102378 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6432 skip
10539 10:54:58.102549 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6432 skip
10540 10:54:58.102758 arm64_sve-ptrace_Set_SVE_VL_6448 pass
10541 10:54:58.102933 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6448 skip
10542 10:54:58.103135 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6448 skip
10543 10:54:58.103302 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6448 skip
10544 10:54:58.103452 arm64_sve-ptrace_Set_SVE_VL_6464 pass
10545 10:54:58.103644 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6464 skip
10546 10:54:58.103789 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6464 skip
10547 10:54:58.103962 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6464 skip
10548 10:54:58.104138 arm64_sve-ptrace_Set_SVE_VL_6480 pass
10549 10:54:58.104297 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6480 skip
10550 10:54:58.104457 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6480 skip
10551 10:54:58.104638 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6480 skip
10552 10:54:58.107859 arm64_sve-ptrace_Set_SVE_VL_6496 pass
10553 10:54:58.108432 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6496 skip
10554 10:54:58.108636 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6496 skip
10555 10:54:58.108847 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6496 skip
10556 10:54:58.109041 arm64_sve-ptrace_Set_SVE_VL_6512 pass
10557 10:54:58.109249 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6512 skip
10558 10:54:58.109419 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6512 skip
10559 10:54:58.109580 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6512 skip
10560 10:54:58.109756 arm64_sve-ptrace_Set_SVE_VL_6528 pass
10561 10:54:58.109916 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6528 skip
10562 10:54:58.110064 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6528 skip
10563 10:54:58.110225 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6528 skip
10564 10:54:58.110365 arm64_sve-ptrace_Set_SVE_VL_6544 pass
10565 10:54:58.110494 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6544 skip
10566 10:54:58.110627 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6544 skip
10567 10:54:58.110802 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6544 skip
10568 10:54:58.110990 arm64_sve-ptrace_Set_SVE_VL_6560 pass
10569 10:54:58.111157 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6560 skip
10570 10:54:58.111346 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6560 skip
10571 10:54:58.111485 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6560 skip
10572 10:54:58.111675 arm64_sve-ptrace_Set_SVE_VL_6576 pass
10573 10:54:58.111809 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6576 skip
10574 10:54:58.111959 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6576 skip
10575 10:54:58.112107 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6576 skip
10576 10:54:58.112223 arm64_sve-ptrace_Set_SVE_VL_6592 pass
10577 10:54:58.112336 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6592 skip
10578 10:54:58.112472 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6592 skip
10579 10:54:58.116022 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6592 skip
10580 10:54:58.116225 arm64_sve-ptrace_Set_SVE_VL_6608 pass
10581 10:54:58.116603 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6608 skip
10582 10:54:58.116735 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6608 skip
10583 10:54:58.116875 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6608 skip
10584 10:54:58.116999 arm64_sve-ptrace_Set_SVE_VL_6624 pass
10585 10:54:58.117101 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6624 skip
10586 10:54:58.117216 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6624 skip
10587 10:54:58.117315 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6624 skip
10588 10:54:58.117427 arm64_sve-ptrace_Set_SVE_VL_6640 pass
10589 10:54:58.117526 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6640 skip
10590 10:54:58.117669 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6640 skip
10591 10:54:58.117832 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6640 skip
10592 10:54:58.117985 arm64_sve-ptrace_Set_SVE_VL_6656 pass
10593 10:54:58.118119 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6656 skip
10594 10:54:58.118285 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6656 skip
10595 10:54:58.118411 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6656 skip
10596 10:54:58.118522 arm64_sve-ptrace_Set_SVE_VL_6672 pass
10597 10:54:58.118612 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6672 skip
10598 10:54:58.118949 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6672 skip
10599 10:54:58.119072 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6672 skip
10600 10:54:58.119187 arm64_sve-ptrace_Set_SVE_VL_6688 pass
10601 10:54:58.119493 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6688 skip
10602 10:54:58.119592 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6688 skip
10603 10:54:58.119690 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6688 skip
10604 10:54:58.119803 arm64_sve-ptrace_Set_SVE_VL_6704 pass
10605 10:54:58.123940 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6704 skip
10606 10:54:58.124051 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6704 skip
10607 10:54:58.124132 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6704 skip
10608 10:54:58.124392 arm64_sve-ptrace_Set_SVE_VL_6720 pass
10609 10:54:58.124472 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6720 skip
10610 10:54:58.124750 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6720 skip
10611 10:54:58.124856 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6720 skip
10612 10:54:58.124956 arm64_sve-ptrace_Set_SVE_VL_6736 pass
10613 10:54:58.125051 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6736 skip
10614 10:54:58.125346 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6736 skip
10615 10:54:58.125441 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6736 skip
10616 10:54:58.125535 arm64_sve-ptrace_Set_SVE_VL_6752 pass
10617 10:54:58.125805 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6752 skip
10618 10:54:58.125892 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6752 skip
10619 10:54:58.126185 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6752 skip
10620 10:54:58.126288 arm64_sve-ptrace_Set_SVE_VL_6768 pass
10621 10:54:58.126390 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6768 skip
10622 10:54:58.126473 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6768 skip
10623 10:54:58.126566 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6768 skip
10624 10:54:58.126648 arm64_sve-ptrace_Set_SVE_VL_6784 pass
10625 10:54:58.126741 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6784 skip
10626 10:54:58.126843 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6784 skip
10627 10:54:58.126940 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6784 skip
10628 10:54:58.127220 arm64_sve-ptrace_Set_SVE_VL_6800 pass
10629 10:54:58.127304 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6800 skip
10630 10:54:58.127401 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6800 skip
10631 10:54:58.131739 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6800 skip
10632 10:54:58.132019 arm64_sve-ptrace_Set_SVE_VL_6816 pass
10633 10:54:58.132111 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6816 skip
10634 10:54:58.132207 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6816 skip
10635 10:54:58.132487 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6816 skip
10636 10:54:58.132586 arm64_sve-ptrace_Set_SVE_VL_6832 pass
10637 10:54:58.132667 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6832 skip
10638 10:54:58.132759 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6832 skip
10639 10:54:58.132839 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6832 skip
10640 10:54:58.132929 arm64_sve-ptrace_Set_SVE_VL_6848 pass
10641 10:54:58.133020 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6848 skip
10642 10:54:58.133334 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6848 skip
10643 10:54:58.133426 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6848 skip
10644 10:54:58.133517 arm64_sve-ptrace_Set_SVE_VL_6864 pass
10645 10:54:58.152379 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6864 skip
10646 10:54:58.152840 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6864 skip
10647 10:54:58.153067 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6864 skip
10648 10:54:58.153171 arm64_sve-ptrace_Set_SVE_VL_6880 pass
10649 10:54:58.153474 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6880 skip
10650 10:54:58.153584 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6880 skip
10651 10:54:58.153903 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6880 skip
10652 10:54:58.154009 arm64_sve-ptrace_Set_SVE_VL_6896 pass
10653 10:54:58.154295 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6896 skip
10654 10:54:58.154584 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6896 skip
10655 10:54:58.154677 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6896 skip
10656 10:54:58.154942 arm64_sve-ptrace_Set_SVE_VL_6912 pass
10657 10:54:58.155232 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6912 skip
10658 10:54:58.155352 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6912 skip
10659 10:54:58.159856 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6912 skip
10660 10:54:58.160344 arm64_sve-ptrace_Set_SVE_VL_6928 pass
10661 10:54:58.160442 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6928 skip
10662 10:54:58.160528 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6928 skip
10663 10:54:58.160612 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6928 skip
10664 10:54:58.160710 arm64_sve-ptrace_Set_SVE_VL_6944 pass
10665 10:54:58.160794 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6944 skip
10666 10:54:58.160874 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6944 skip
10667 10:54:58.160969 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6944 skip
10668 10:54:58.161064 arm64_sve-ptrace_Set_SVE_VL_6960 pass
10669 10:54:58.161159 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6960 skip
10670 10:54:58.161254 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6960 skip
10671 10:54:58.161536 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6960 skip
10672 10:54:58.161634 arm64_sve-ptrace_Set_SVE_VL_6976 pass
10673 10:54:58.161743 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6976 skip
10674 10:54:58.162020 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6976 skip
10675 10:54:58.162130 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6976 skip
10676 10:54:58.162226 arm64_sve-ptrace_Set_SVE_VL_6992 pass
10677 10:54:58.162503 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6992 skip
10678 10:54:58.162589 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6992 skip
10679 10:54:58.162683 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6992 skip
10680 10:54:58.162777 arm64_sve-ptrace_Set_SVE_VL_7008 pass
10681 10:54:58.162878 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7008 skip
10682 10:54:58.163154 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7008 skip
10683 10:54:58.163250 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7008 skip
10684 10:54:58.163525 arm64_sve-ptrace_Set_SVE_VL_7024 pass
10685 10:54:58.167872 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7024 skip
10686 10:54:58.168307 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7024 skip
10687 10:54:58.168396 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7024 skip
10688 10:54:58.168479 arm64_sve-ptrace_Set_SVE_VL_7040 pass
10689 10:54:58.168574 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7040 skip
10690 10:54:58.168657 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7040 skip
10691 10:54:58.168753 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7040 skip
10692 10:54:58.168836 arm64_sve-ptrace_Set_SVE_VL_7056 pass
10693 10:54:58.168930 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7056 skip
10694 10:54:58.169025 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7056 skip
10695 10:54:58.169121 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7056 skip
10696 10:54:58.169456 arm64_sve-ptrace_Set_SVE_VL_7072 pass
10697 10:54:58.169584 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7072 skip
10698 10:54:58.169694 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7072 skip
10699 10:54:58.169792 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7072 skip
10700 10:54:58.169874 arm64_sve-ptrace_Set_SVE_VL_7088 pass
10701 10:54:58.169966 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7088 skip
10702 10:54:58.170222 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7088 skip
10703 10:54:58.170340 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7088 skip
10704 10:54:58.170438 arm64_sve-ptrace_Set_SVE_VL_7104 pass
10705 10:54:58.170524 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7104 skip
10706 10:54:58.170617 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7104 skip
10707 10:54:58.170938 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7104 skip
10708 10:54:58.171042 arm64_sve-ptrace_Set_SVE_VL_7120 pass
10709 10:54:58.171125 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7120 skip
10710 10:54:58.171217 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7120 skip
10711 10:54:58.171312 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7120 skip
10712 10:54:58.171393 arm64_sve-ptrace_Set_SVE_VL_7136 pass
10713 10:54:58.171486 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7136 skip
10714 10:54:58.171568 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7136 skip
10715 10:54:58.171660 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7136 skip
10716 10:54:58.175796 arm64_sve-ptrace_Set_SVE_VL_7152 pass
10717 10:54:58.176237 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7152 skip
10718 10:54:58.176338 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7152 skip
10719 10:54:58.176419 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7152 skip
10720 10:54:58.176499 arm64_sve-ptrace_Set_SVE_VL_7168 pass
10721 10:54:58.176591 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7168 skip
10722 10:54:58.176671 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7168 skip
10723 10:54:58.176764 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7168 skip
10724 10:54:58.176845 arm64_sve-ptrace_Set_SVE_VL_7184 pass
10725 10:54:58.176936 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7184 skip
10726 10:54:58.177028 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7184 skip
10727 10:54:58.177121 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7184 skip
10728 10:54:58.177453 arm64_sve-ptrace_Set_SVE_VL_7200 pass
10729 10:54:58.177664 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7200 skip
10730 10:54:58.177869 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7200 skip
10731 10:54:58.178046 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7200 skip
10732 10:54:58.178214 arm64_sve-ptrace_Set_SVE_VL_7216 pass
10733 10:54:58.178408 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7216 skip
10734 10:54:58.178581 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7216 skip
10735 10:54:58.178755 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7216 skip
10736 10:54:58.178919 arm64_sve-ptrace_Set_SVE_VL_7232 pass
10737 10:54:58.179151 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7232 skip
10738 10:54:58.179339 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7232 skip
10739 10:54:58.179507 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7232 skip
10740 10:54:58.179643 arm64_sve-ptrace_Set_SVE_VL_7248 pass
10741 10:54:58.179761 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7248 skip
10742 10:54:58.179876 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7248 skip
10743 10:54:58.180016 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7248 skip
10744 10:54:58.180135 arm64_sve-ptrace_Set_SVE_VL_7264 pass
10745 10:54:58.180248 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7264 skip
10746 10:54:58.183774 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7264 skip
10747 10:54:58.184404 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7264 skip
10748 10:54:58.184514 arm64_sve-ptrace_Set_SVE_VL_7280 pass
10749 10:54:58.184598 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7280 skip
10750 10:54:58.184680 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7280 skip
10751 10:54:58.184760 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7280 skip
10752 10:54:58.184856 arm64_sve-ptrace_Set_SVE_VL_7296 pass
10753 10:54:58.184938 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7296 skip
10754 10:54:58.185018 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7296 skip
10755 10:54:58.185098 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7296 skip
10756 10:54:58.185192 arm64_sve-ptrace_Set_SVE_VL_7312 pass
10757 10:54:58.185274 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7312 skip
10758 10:54:58.185368 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7312 skip
10759 10:54:58.185450 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7312 skip
10760 10:54:58.185549 arm64_sve-ptrace_Set_SVE_VL_7328 pass
10761 10:54:58.185643 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7328 skip
10762 10:54:58.185985 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7328 skip
10763 10:54:58.186180 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7328 skip
10764 10:54:58.186350 arm64_sve-ptrace_Set_SVE_VL_7344 pass
10765 10:54:58.186554 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7344 skip
10766 10:54:58.186717 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7344 skip
10767 10:54:58.186869 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7344 skip
10768 10:54:58.187012 arm64_sve-ptrace_Set_SVE_VL_7360 pass
10769 10:54:58.187173 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7360 skip
10770 10:54:58.187377 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7360 skip
10771 10:54:58.187512 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7360 skip
10772 10:54:58.187687 arm64_sve-ptrace_Set_SVE_VL_7376 pass
10773 10:54:58.187817 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7376 skip
10774 10:54:58.187932 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7376 skip
10775 10:54:58.188095 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7376 skip
10776 10:54:58.188251 arm64_sve-ptrace_Set_SVE_VL_7392 pass
10777 10:54:58.191780 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7392 skip
10778 10:54:58.192166 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7392 skip
10779 10:54:58.192260 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7392 skip
10780 10:54:58.192338 arm64_sve-ptrace_Set_SVE_VL_7408 pass
10781 10:54:58.192427 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7408 skip
10782 10:54:58.192514 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7408 skip
10783 10:54:58.192599 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7408 skip
10784 10:54:58.192673 arm64_sve-ptrace_Set_SVE_VL_7424 pass
10785 10:54:58.192925 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7424 skip
10786 10:54:58.193032 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7424 skip
10787 10:54:58.193117 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7424 skip
10788 10:54:58.193197 arm64_sve-ptrace_Set_SVE_VL_7440 pass
10789 10:54:58.193277 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7440 skip
10790 10:54:58.193357 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7440 skip
10791 10:54:58.193618 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7440 skip
10792 10:54:58.193700 arm64_sve-ptrace_Set_SVE_VL_7456 pass
10793 10:54:58.193779 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7456 skip
10794 10:54:58.194051 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7456 skip
10795 10:54:58.194137 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7456 skip
10796 10:54:58.194217 arm64_sve-ptrace_Set_SVE_VL_7472 pass
10797 10:54:58.194296 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7472 skip
10798 10:54:58.194413 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7472 skip
10799 10:54:58.194681 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7472 skip
10800 10:54:58.194752 arm64_sve-ptrace_Set_SVE_VL_7488 pass
10801 10:54:58.194831 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7488 skip
10802 10:54:58.195105 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7488 skip
10803 10:54:58.195191 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7488 skip
10804 10:54:58.195260 arm64_sve-ptrace_Set_SVE_VL_7504 pass
10805 10:54:58.213841 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7504 skip
10806 10:54:58.214035 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7504 skip
10807 10:54:58.214381 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7504 skip
10808 10:54:58.214483 arm64_sve-ptrace_Set_SVE_VL_7520 pass
10809 10:54:58.214567 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7520 skip
10810 10:54:58.214648 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7520 skip
10811 10:54:58.214728 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7520 skip
10812 10:54:58.214823 arm64_sve-ptrace_Set_SVE_VL_7536 pass
10813 10:54:58.214905 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7536 skip
10814 10:54:58.214985 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7536 skip
10815 10:54:58.215079 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7536 skip
10816 10:54:58.215161 arm64_sve-ptrace_Set_SVE_VL_7552 pass
10817 10:54:58.215254 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7552 skip
10818 10:54:58.215349 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7552 skip
10819 10:54:58.215444 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7552 skip
10820 10:54:58.216464 arm64_sve-ptrace_Set_SVE_VL_7568 pass
10821 10:54:58.216570 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7568 skip
10822 10:54:58.216951 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7568 skip
10823 10:54:58.217091 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7568 skip
10824 10:54:58.217243 arm64_sve-ptrace_Set_SVE_VL_7584 pass
10825 10:54:58.217331 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7584 skip
10826 10:54:58.217411 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7584 skip
10827 10:54:58.217490 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7584 skip
10828 10:54:58.217569 arm64_sve-ptrace_Set_SVE_VL_7600 pass
10829 10:54:58.217655 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7600 skip
10830 10:54:58.217905 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7600 skip
10831 10:54:58.218066 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7600 skip
10832 10:54:58.218201 arm64_sve-ptrace_Set_SVE_VL_7616 pass
10833 10:54:58.218359 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7616 skip
10834 10:54:58.218511 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7616 skip
10835 10:54:58.218669 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7616 skip
10836 10:54:58.218834 arm64_sve-ptrace_Set_SVE_VL_7632 pass
10837 10:54:58.218995 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7632 skip
10838 10:54:58.219131 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7632 skip
10839 10:54:58.219267 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7632 skip
10840 10:54:58.219378 arm64_sve-ptrace_Set_SVE_VL_7648 pass
10841 10:54:58.219475 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7648 skip
10842 10:54:58.219568 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7648 skip
10843 10:54:58.219658 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7648 skip
10844 10:54:58.219749 arm64_sve-ptrace_Set_SVE_VL_7664 pass
10845 10:54:58.219837 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7664 skip
10846 10:54:58.219927 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7664 skip
10847 10:54:58.220017 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7664 skip
10848 10:54:58.220106 arm64_sve-ptrace_Set_SVE_VL_7680 pass
10849 10:54:58.220197 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7680 skip
10850 10:54:58.220305 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7680 skip
10851 10:54:58.220399 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7680 skip
10852 10:54:58.223800 arm64_sve-ptrace_Set_SVE_VL_7696 pass
10853 10:54:58.223931 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7696 skip
10854 10:54:58.224234 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7696 skip
10855 10:54:58.224340 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7696 skip
10856 10:54:58.224424 arm64_sve-ptrace_Set_SVE_VL_7712 pass
10857 10:54:58.224519 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7712 skip
10858 10:54:58.224609 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7712 skip
10859 10:54:58.224703 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7712 skip
10860 10:54:58.224795 arm64_sve-ptrace_Set_SVE_VL_7728 pass
10861 10:54:58.224882 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7728 skip
10862 10:54:58.224970 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7728 skip
10863 10:54:58.225077 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7728 skip
10864 10:54:58.225381 arm64_sve-ptrace_Set_SVE_VL_7744 pass
10865 10:54:58.225524 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7744 skip
10866 10:54:58.225664 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7744 skip
10867 10:54:58.225770 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7744 skip
10868 10:54:58.225944 arm64_sve-ptrace_Set_SVE_VL_7760 pass
10869 10:54:58.226099 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7760 skip
10870 10:54:58.226277 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7760 skip
10871 10:54:58.226416 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7760 skip
10872 10:54:58.226598 arm64_sve-ptrace_Set_SVE_VL_7776 pass
10873 10:54:58.226756 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7776 skip
10874 10:54:58.226896 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7776 skip
10875 10:54:58.226992 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7776 skip
10876 10:54:58.227079 arm64_sve-ptrace_Set_SVE_VL_7792 pass
10877 10:54:58.227165 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7792 skip
10878 10:54:58.227316 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7792 skip
10879 10:54:58.227415 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7792 skip
10880 10:54:58.227503 arm64_sve-ptrace_Set_SVE_VL_7808 pass
10881 10:54:58.227589 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7808 skip
10882 10:54:58.227676 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7808 skip
10883 10:54:58.227821 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7808 skip
10884 10:54:58.227968 arm64_sve-ptrace_Set_SVE_VL_7824 pass
10885 10:54:58.228134 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7824 skip
10886 10:54:58.228278 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7824 skip
10887 10:54:58.232006 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7824 skip
10888 10:54:58.232213 arm64_sve-ptrace_Set_SVE_VL_7840 pass
10889 10:54:58.232384 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7840 skip
10890 10:54:58.232531 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7840 skip
10891 10:54:58.232700 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7840 skip
10892 10:54:58.232846 arm64_sve-ptrace_Set_SVE_VL_7856 pass
10893 10:54:58.232987 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7856 skip
10894 10:54:58.233153 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7856 skip
10895 10:54:58.233297 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7856 skip
10896 10:54:58.233439 arm64_sve-ptrace_Set_SVE_VL_7872 pass
10897 10:54:58.233605 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7872 skip
10898 10:54:58.233762 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7872 skip
10899 10:54:58.233903 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7872 skip
10900 10:54:58.234069 arm64_sve-ptrace_Set_SVE_VL_7888 pass
10901 10:54:58.234212 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7888 skip
10902 10:54:58.234352 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7888 skip
10903 10:54:58.234516 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7888 skip
10904 10:54:58.234660 arm64_sve-ptrace_Set_SVE_VL_7904 pass
10905 10:54:58.234799 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7904 skip
10906 10:54:58.234963 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7904 skip
10907 10:54:58.235106 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7904 skip
10908 10:54:58.235270 arm64_sve-ptrace_Set_SVE_VL_7920 pass
10909 10:54:58.235411 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7920 skip
10910 10:54:58.235577 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7920 skip
10911 10:54:58.235722 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7920 skip
10912 10:54:58.235886 arm64_sve-ptrace_Set_SVE_VL_7936 pass
10913 10:54:58.243831 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7936 skip
10914 10:54:58.244154 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7936 skip
10915 10:54:58.244250 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7936 skip
10916 10:54:58.244330 arm64_sve-ptrace_Set_SVE_VL_7952 pass
10917 10:54:58.244416 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7952 skip
10918 10:54:58.244497 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7952 skip
10919 10:54:58.244761 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7952 skip
10920 10:54:58.244843 arm64_sve-ptrace_Set_SVE_VL_7968 pass
10921 10:54:58.244920 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7968 skip
10922 10:54:58.245180 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7968 skip
10923 10:54:58.245260 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7968 skip
10924 10:54:58.245522 arm64_sve-ptrace_Set_SVE_VL_7984 pass
10925 10:54:58.245603 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7984 skip
10926 10:54:58.245861 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7984 skip
10927 10:54:58.245938 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7984 skip
10928 10:54:58.246179 arm64_sve-ptrace_Set_SVE_VL_8000 pass
10929 10:54:58.246255 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8000 skip
10930 10:54:58.246519 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8000 skip
10931 10:54:58.246614 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8000 skip
10932 10:54:58.246689 arm64_sve-ptrace_Set_SVE_VL_8016 pass
10933 10:54:58.247101 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8016 skip
10934 10:54:58.247177 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8016 skip
10935 10:54:58.247288 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8016 skip
10936 10:54:58.247386 arm64_sve-ptrace_Set_SVE_VL_8032 pass
10937 10:54:58.247494 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8032 skip
10938 10:54:58.251768 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8032 skip
10939 10:54:58.252072 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8032 skip
10940 10:54:58.252175 arm64_sve-ptrace_Set_SVE_VL_8048 pass
10941 10:54:58.252273 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8048 skip
10942 10:54:58.252356 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8048 skip
10943 10:54:58.252641 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8048 skip
10944 10:54:58.252725 arm64_sve-ptrace_Set_SVE_VL_8064 pass
10945 10:54:58.252802 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8064 skip
10946 10:54:58.253057 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8064 skip
10947 10:54:58.253128 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8064 skip
10948 10:54:58.253203 arm64_sve-ptrace_Set_SVE_VL_8080 pass
10949 10:54:58.253279 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8080 skip
10950 10:54:58.253530 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8080 skip
10951 10:54:58.253792 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8080 skip
10952 10:54:58.253863 arm64_sve-ptrace_Set_SVE_VL_8096 pass
10953 10:54:58.253939 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8096 skip
10954 10:54:58.254015 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8096 skip
10955 10:54:58.254281 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8096 skip
10956 10:54:58.254361 arm64_sve-ptrace_Set_SVE_VL_8112 pass
10957 10:54:58.254613 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8112 skip
10958 10:54:58.254692 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8112 skip
10959 10:54:58.254943 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8112 skip
10960 10:54:58.255014 arm64_sve-ptrace_Set_SVE_VL_8128 pass
10961 10:54:58.255090 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8128 skip
10962 10:54:58.255342 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8128 skip
10963 10:54:58.255612 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8128 skip
10964 10:54:58.255763 arm64_sve-ptrace_Set_SVE_VL_8144 pass
10965 10:54:58.270922 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8144 skip
10966 10:54:58.271345 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8144 skip
10967 10:54:58.271488 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8144 skip
10968 10:54:58.271616 arm64_sve-ptrace_Set_SVE_VL_8160 pass
10969 10:54:58.271749 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8160 skip
10970 10:54:58.271881 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8160 skip
10971 10:54:58.272015 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8160 skip
10972 10:54:58.272149 arm64_sve-ptrace_Set_SVE_VL_8176 pass
10973 10:54:58.272286 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8176 skip
10974 10:54:58.272628 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8176 skip
10975 10:54:58.272753 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8176 skip
10976 10:54:58.272890 arm64_sve-ptrace_Set_SVE_VL_8192 pass
10977 10:54:58.273010 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8192 skip
10978 10:54:58.273144 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8192 skip
10979 10:54:58.273263 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8192 skip
10980 10:54:58.273397 arm64_sve-ptrace_Streaming_SVE_FPSIMD_set_via_SVE_0 pass
10981 10:54:58.273553 arm64_sve-ptrace_Streaming_SVE_get_fpsimd_gave_same_state pass
10982 10:54:58.273695 arm64_sve-ptrace_Streaming_SVE_SVE_PT_VL_INHERIT_set pass
10983 10:54:58.274060 arm64_sve-ptrace_Streaming_SVE_SVE_PT_VL_INHERIT_cleared pass
10984 10:54:58.274145 arm64_sve-ptrace_Set_Streaming_SVE_VL_16 pass
10985 10:54:58.274463 arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_16 pass
10986 10:54:58.274574 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_16 pass
10987 10:54:58.274698 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_16 pass
10988 10:54:58.274796 arm64_sve-ptrace_Set_Streaming_SVE_VL_32 pass
10989 10:54:58.274876 arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_32 pass
10990 10:54:58.275156 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_32 pass
10991 10:54:58.275283 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_32 pass
10992 10:54:58.275398 arm64_sve-ptrace_Set_Streaming_SVE_VL_48 pass
10993 10:54:58.279737 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_48 skip
10994 10:54:58.280063 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_48 skip
10995 10:54:58.280153 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_48 skip
10996 10:54:58.280231 arm64_sve-ptrace_Set_Streaming_SVE_VL_64 pass
10997 10:54:58.280510 arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_64 pass
10998 10:54:58.280592 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_64 pass
10999 10:54:58.280681 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_64 pass
11000 10:54:58.280959 arm64_sve-ptrace_Set_Streaming_SVE_VL_80 pass
11001 10:54:58.281080 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_80 skip
11002 10:54:58.281230 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_80 skip
11003 10:54:58.281376 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_80 skip
11004 10:54:58.281540 arm64_sve-ptrace_Set_Streaming_SVE_VL_96 pass
11005 10:54:58.281638 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_96 skip
11006 10:54:58.281748 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_96 skip
11007 10:54:58.281868 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_96 skip
11008 10:54:58.281993 arm64_sve-ptrace_Set_Streaming_SVE_VL_112 pass
11009 10:54:58.282345 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_112 skip
11010 10:54:58.282457 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_112 skip
11011 10:54:58.282563 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_112 skip
11012 10:54:58.282672 arm64_sve-ptrace_Set_Streaming_SVE_VL_128 pass
11013 10:54:58.282795 arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_128 pass
11014 10:54:58.283107 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_128 pass
11015 10:54:58.283212 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_128 pass
11016 10:54:58.283474 arm64_sve-ptrace_Set_Streaming_SVE_VL_144 pass
11017 10:54:58.283546 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_144 skip
11018 10:54:58.287784 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_144 skip
11019 10:54:58.288087 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_144 skip
11020 10:54:58.288180 arm64_sve-ptrace_Set_Streaming_SVE_VL_160 pass
11021 10:54:58.288268 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_160 skip
11022 10:54:58.288529 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_160 skip
11023 10:54:58.288642 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_160 skip
11024 10:54:58.288736 arm64_sve-ptrace_Set_Streaming_SVE_VL_176 pass
11025 10:54:58.288977 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_176 skip
11026 10:54:58.289084 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_176 skip
11027 10:54:58.289184 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_176 skip
11028 10:54:58.289465 arm64_sve-ptrace_Set_Streaming_SVE_VL_192 pass
11029 10:54:58.289553 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_192 skip
11030 10:54:58.289654 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_192 skip
11031 10:54:58.289956 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_192 skip
11032 10:54:58.290079 arm64_sve-ptrace_Set_Streaming_SVE_VL_208 pass
11033 10:54:58.290165 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_208 skip
11034 10:54:58.290459 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_208 skip
11035 10:54:58.290567 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_208 skip
11036 10:54:58.290657 arm64_sve-ptrace_Set_Streaming_SVE_VL_224 pass
11037 10:54:58.290905 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_224 skip
11038 10:54:58.291155 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_224 skip
11039 10:54:58.291225 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_224 skip
11040 10:54:58.291327 arm64_sve-ptrace_Set_Streaming_SVE_VL_240 pass
11041 10:54:58.291430 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_240 skip
11042 10:54:58.295879 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_240 skip
11043 10:54:58.296182 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_240 skip
11044 10:54:58.296260 arm64_sve-ptrace_Set_Streaming_SVE_VL_256 pass
11045 10:54:58.296351 arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_256 pass
11046 10:54:58.296614 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_256 pass
11047 10:54:58.296692 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_256 pass
11048 10:54:58.296938 arm64_sve-ptrace_Set_Streaming_SVE_VL_272 pass
11049 10:54:58.297020 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_272 skip
11050 10:54:58.297282 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_272 skip
11051 10:54:58.297538 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_272 skip
11052 10:54:58.297605 arm64_sve-ptrace_Set_Streaming_SVE_VL_288 pass
11053 10:54:58.297692 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_288 skip
11054 10:54:58.297941 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_288 skip
11055 10:54:58.298191 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_288 skip
11056 10:54:58.298267 arm64_sve-ptrace_Set_Streaming_SVE_VL_304 pass
11057 10:54:58.298520 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_304 skip
11058 10:54:58.298596 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_304 skip
11059 10:54:58.298842 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_304 skip
11060 10:54:58.298918 arm64_sve-ptrace_Set_Streaming_SVE_VL_320 pass
11061 10:54:58.299166 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_320 skip
11062 10:54:58.299409 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_320 skip
11063 10:54:58.299474 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_320 skip
11064 10:54:58.303827 arm64_sve-ptrace_Set_Streaming_SVE_VL_336 pass
11065 10:54:58.304174 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_336 skip
11066 10:54:58.304320 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_336 skip
11067 10:54:58.304438 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_336 skip
11068 10:54:58.304550 arm64_sve-ptrace_Set_Streaming_SVE_VL_352 pass
11069 10:54:58.304660 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_352 skip
11070 10:54:58.304759 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_352 skip
11071 10:54:58.304843 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_352 skip
11072 10:54:58.304935 arm64_sve-ptrace_Set_Streaming_SVE_VL_368 pass
11073 10:54:58.305129 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_368 skip
11074 10:54:58.305431 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_368 skip
11075 10:54:58.305515 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_368 skip
11076 10:54:58.305598 arm64_sve-ptrace_Set_Streaming_SVE_VL_384 pass
11077 10:54:58.305886 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_384 skip
11078 10:54:58.305984 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_384 skip
11079 10:54:58.306249 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_384 skip
11080 10:54:58.306334 arm64_sve-ptrace_Set_Streaming_SVE_VL_400 pass
11081 10:54:58.306621 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_400 skip
11082 10:54:58.306706 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_400 skip
11083 10:54:58.307010 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_400 skip
11084 10:54:58.307099 arm64_sve-ptrace_Set_Streaming_SVE_VL_416 pass
11085 10:54:58.307176 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_416 skip
11086 10:54:58.307426 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_416 skip
11087 10:54:58.311774 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_416 skip
11088 10:54:58.312149 arm64_sve-ptrace_Set_Streaming_SVE_VL_432 pass
11089 10:54:58.312251 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_432 skip
11090 10:54:58.312350 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_432 skip
11091 10:54:58.312467 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_432 skip
11092 10:54:58.312560 arm64_sve-ptrace_Set_Streaming_SVE_VL_448 pass
11093 10:54:58.312644 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_448 skip
11094 10:54:58.312921 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_448 skip
11095 10:54:58.313028 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_448 skip
11096 10:54:58.313308 arm64_sve-ptrace_Set_Streaming_SVE_VL_464 pass
11097 10:54:58.313388 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_464 skip
11098 10:54:58.313482 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_464 skip
11099 10:54:58.313579 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_464 skip
11100 10:54:58.313859 arm64_sve-ptrace_Set_Streaming_SVE_VL_480 pass
11101 10:54:58.313932 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_480 skip
11102 10:54:58.329671 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_480 skip
11103 10:54:58.330058 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_480 skip
11104 10:54:58.330139 arm64_sve-ptrace_Set_Streaming_SVE_VL_496 pass
11105 10:54:58.330235 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_496 skip
11106 10:54:58.330323 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_496 skip
11107 10:54:58.330595 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_496 skip
11108 10:54:58.330682 arm64_sve-ptrace_Set_Streaming_SVE_VL_512 pass
11109 10:54:58.330960 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_512 skip
11110 10:54:58.331063 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_512 skip
11111 10:54:58.331357 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_512 skip
11112 10:54:58.331437 arm64_sve-ptrace_Set_Streaming_SVE_VL_528 pass
11113 10:54:58.331708 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_528 skip
11114 10:54:58.331990 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_528 skip
11115 10:54:58.332078 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_528 skip
11116 10:54:58.332186 arm64_sve-ptrace_Set_Streaming_SVE_VL_544 pass
11117 10:54:58.332297 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_544 skip
11118 10:54:58.332604 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_544 skip
11119 10:54:58.332713 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_544 skip
11120 10:54:58.332825 arm64_sve-ptrace_Set_Streaming_SVE_VL_560 pass
11121 10:54:58.332914 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_560 skip
11122 10:54:58.333202 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_560 skip
11123 10:54:58.333325 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_560 skip
11124 10:54:58.333613 arm64_sve-ptrace_Set_Streaming_SVE_VL_576 pass
11125 10:54:58.333713 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_576 skip
11126 10:54:58.333817 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_576 skip
11127 10:54:58.333915 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_576 skip
11128 10:54:58.334000 arm64_sve-ptrace_Set_Streaming_SVE_VL_592 pass
11129 10:54:58.334095 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_592 skip
11130 10:54:58.334388 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_592 skip
11131 10:54:58.334492 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_592 skip
11132 10:54:58.334590 arm64_sve-ptrace_Set_Streaming_SVE_VL_608 pass
11133 10:54:58.334685 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_608 skip
11134 10:54:58.334983 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_608 skip
11135 10:54:58.335101 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_608 skip
11136 10:54:58.335416 arm64_sve-ptrace_Set_Streaming_SVE_VL_624 pass
11137 10:54:58.335571 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_624 skip
11138 10:54:58.335707 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_624 skip
11139 10:54:58.335816 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_624 skip
11140 10:54:58.335901 arm64_sve-ptrace_Set_Streaming_SVE_VL_640 pass
11141 10:54:58.339988 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_640 skip
11142 10:54:58.341279 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_640 skip
11143 10:54:58.341385 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_640 skip
11144 10:54:58.341470 arm64_sve-ptrace_Set_Streaming_SVE_VL_656 pass
11145 10:54:58.341551 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_656 skip
11146 10:54:58.341631 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_656 skip
11147 10:54:58.341719 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_656 skip
11148 10:54:58.341800 arm64_sve-ptrace_Set_Streaming_SVE_VL_672 pass
11149 10:54:58.341881 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_672 skip
11150 10:54:58.341963 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_672 skip
11151 10:54:58.342236 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_672 skip
11152 10:54:58.342324 arm64_sve-ptrace_Set_Streaming_SVE_VL_688 pass
11153 10:54:58.342406 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_688 skip
11154 10:54:58.342487 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_688 skip
11155 10:54:58.342568 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_688 skip
11156 10:54:58.342666 arm64_sve-ptrace_Set_Streaming_SVE_VL_704 pass
11157 10:54:58.342754 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_704 skip
11158 10:54:58.342836 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_704 skip
11159 10:54:58.342931 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_704 skip
11160 10:54:58.343015 arm64_sve-ptrace_Set_Streaming_SVE_VL_720 pass
11161 10:54:58.343111 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_720 skip
11162 10:54:58.343391 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_720 skip
11163 10:54:58.343490 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_720 skip
11164 10:54:58.347672 arm64_sve-ptrace_Set_Streaming_SVE_VL_736 pass
11165 10:54:58.348012 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_736 skip
11166 10:54:58.348102 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_736 skip
11167 10:54:58.348383 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_736 skip
11168 10:54:58.348472 arm64_sve-ptrace_Set_Streaming_SVE_VL_752 pass
11169 10:54:58.348568 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_752 skip
11170 10:54:58.348849 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_752 skip
11171 10:54:58.348937 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_752 skip
11172 10:54:58.349246 arm64_sve-ptrace_Set_Streaming_SVE_VL_768 pass
11173 10:54:58.349356 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_768 skip
11174 10:54:58.349629 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_768 skip
11175 10:54:58.349730 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_768 skip
11176 10:54:58.349813 arm64_sve-ptrace_Set_Streaming_SVE_VL_784 pass
11177 10:54:58.349907 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_784 skip
11178 10:54:58.350191 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_784 skip
11179 10:54:58.350295 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_784 skip
11180 10:54:58.350392 arm64_sve-ptrace_Set_Streaming_SVE_VL_800 pass
11181 10:54:58.350476 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_800 skip
11182 10:54:58.350558 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_800 skip
11183 10:54:58.350652 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_800 skip
11184 10:54:58.350750 arm64_sve-ptrace_Set_Streaming_SVE_VL_816 pass
11185 10:54:58.350903 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_816 skip
11186 10:54:58.351220 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_816 skip
11187 10:54:58.351323 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_816 skip
11188 10:54:58.351623 arm64_sve-ptrace_Set_Streaming_SVE_VL_832 pass
11189 10:54:58.355673 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_832 skip
11190 10:54:58.356035 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_832 skip
11191 10:54:58.356141 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_832 skip
11192 10:54:58.356241 arm64_sve-ptrace_Set_Streaming_SVE_VL_848 pass
11193 10:54:58.356355 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_848 skip
11194 10:54:58.356480 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_848 skip
11195 10:54:58.356764 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_848 skip
11196 10:54:58.356835 arm64_sve-ptrace_Set_Streaming_SVE_VL_864 pass
11197 10:54:58.356936 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_864 skip
11198 10:54:58.357195 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_864 skip
11199 10:54:58.357265 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_864 skip
11200 10:54:58.357341 arm64_sve-ptrace_Set_Streaming_SVE_VL_880 pass
11201 10:54:58.357605 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_880 skip
11202 10:54:58.357700 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_880 skip
11203 10:54:58.357992 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_880 skip
11204 10:54:58.358100 arm64_sve-ptrace_Set_Streaming_SVE_VL_896 pass
11205 10:54:58.358220 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_896 skip
11206 10:54:58.358341 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_896 skip
11207 10:54:58.358462 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_896 skip
11208 10:54:58.358590 arm64_sve-ptrace_Set_Streaming_SVE_VL_912 pass
11209 10:54:58.358704 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_912 skip
11210 10:54:58.358818 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_912 skip
11211 10:54:58.359112 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_912 skip
11212 10:54:58.359223 arm64_sve-ptrace_Set_Streaming_SVE_VL_928 pass
11213 10:54:58.359355 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_928 skip
11214 10:54:58.359479 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_928 skip
11215 10:54:58.363681 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_928 skip
11216 10:54:58.364038 arm64_sve-ptrace_Set_Streaming_SVE_VL_944 pass
11217 10:54:58.364142 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_944 skip
11218 10:54:58.364240 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_944 skip
11219 10:54:58.364562 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_944 skip
11220 10:54:58.364666 arm64_sve-ptrace_Set_Streaming_SVE_VL_960 pass
11221 10:54:58.364766 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_960 skip
11222 10:54:58.364854 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_960 skip
11223 10:54:58.364949 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_960 skip
11224 10:54:58.365030 arm64_sve-ptrace_Set_Streaming_SVE_VL_976 pass
11225 10:54:58.365124 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_976 skip
11226 10:54:58.365417 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_976 skip
11227 10:54:58.365535 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_976 skip
11228 10:54:58.365634 arm64_sve-ptrace_Set_Streaming_SVE_VL_992 pass
11229 10:54:58.365776 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_992 skip
11230 10:54:58.366080 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_992 skip
11231 10:54:58.366171 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_992 skip
11232 10:54:58.366466 arm64_sve-ptrace_Set_Streaming_SVE_VL_1008 pass
11233 10:54:58.366584 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1008 skip
11234 10:54:58.366694 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1008 skip
11235 10:54:58.366767 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1008 skip
11236 10:54:58.366855 arm64_sve-ptrace_Set_Streaming_SVE_VL_1024 pass
11237 10:54:58.366939 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1024 skip
11238 10:54:58.385442 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1024 skip
11239 10:54:58.385840 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1024 skip
11240 10:54:58.385940 arm64_sve-ptrace_Set_Streaming_SVE_VL_1040 pass
11241 10:54:58.386044 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1040 skip
11242 10:54:58.386153 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1040 skip
11243 10:54:58.386235 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1040 skip
11244 10:54:58.386338 arm64_sve-ptrace_Set_Streaming_SVE_VL_1056 pass
11245 10:54:58.386445 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1056 skip
11246 10:54:58.386741 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1056 skip
11247 10:54:58.386862 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1056 skip
11248 10:54:58.386952 arm64_sve-ptrace_Set_Streaming_SVE_VL_1072 pass
11249 10:54:58.387045 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1072 skip
11250 10:54:58.387343 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1072 skip
11251 10:54:58.387468 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1072 skip
11252 10:54:58.387752 arm64_sve-ptrace_Set_Streaming_SVE_VL_1088 pass
11253 10:54:58.387854 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1088 skip
11254 10:54:58.388140 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1088 skip
11255 10:54:58.388233 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1088 skip
11256 10:54:58.388498 arm64_sve-ptrace_Set_Streaming_SVE_VL_1104 pass
11257 10:54:58.388602 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1104 skip
11258 10:54:58.388701 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1104 skip
11259 10:54:58.388988 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1104 skip
11260 10:54:58.389083 arm64_sve-ptrace_Set_Streaming_SVE_VL_1120 pass
11261 10:54:58.389318 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1120 skip
11262 10:54:58.389417 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1120 skip
11263 10:54:58.389682 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1120 skip
11264 10:54:58.389762 arm64_sve-ptrace_Set_Streaming_SVE_VL_1136 pass
11265 10:54:58.389864 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1136 skip
11266 10:54:58.389969 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1136 skip
11267 10:54:58.390238 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1136 skip
11268 10:54:58.390312 arm64_sve-ptrace_Set_Streaming_SVE_VL_1152 pass
11269 10:54:58.390598 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1152 skip
11270 10:54:58.390689 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1152 skip
11271 10:54:58.390946 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1152 skip
11272 10:54:58.391016 arm64_sve-ptrace_Set_Streaming_SVE_VL_1168 pass
11273 10:54:58.391268 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1168 skip
11274 10:54:58.391338 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1168 skip
11275 10:54:58.395610 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1168 skip
11276 10:54:58.395922 arm64_sve-ptrace_Set_Streaming_SVE_VL_1184 pass
11277 10:54:58.396021 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1184 skip
11278 10:54:58.396116 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1184 skip
11279 10:54:58.396205 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1184 skip
11280 10:54:58.396295 arm64_sve-ptrace_Set_Streaming_SVE_VL_1200 pass
11281 10:54:58.396580 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1200 skip
11282 10:54:58.396688 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1200 skip
11283 10:54:58.396794 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1200 skip
11284 10:54:58.397067 arm64_sve-ptrace_Set_Streaming_SVE_VL_1216 pass
11285 10:54:58.397161 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1216 skip
11286 10:54:58.397251 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1216 skip
11287 10:54:58.397522 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1216 skip
11288 10:54:58.397620 arm64_sve-ptrace_Set_Streaming_SVE_VL_1232 pass
11289 10:54:58.397905 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1232 skip
11290 10:54:58.398000 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1232 skip
11291 10:54:58.398286 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1232 skip
11292 10:54:58.398375 arm64_sve-ptrace_Set_Streaming_SVE_VL_1248 pass
11293 10:54:58.398648 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1248 skip
11294 10:54:58.398750 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1248 skip
11295 10:54:58.398843 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1248 skip
11296 10:54:58.398938 arm64_sve-ptrace_Set_Streaming_SVE_VL_1264 pass
11297 10:54:58.399223 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1264 skip
11298 10:54:58.399327 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1264 skip
11299 10:54:58.403593 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1264 skip
11300 10:54:58.403976 arm64_sve-ptrace_Set_Streaming_SVE_VL_1280 pass
11301 10:54:58.404072 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1280 skip
11302 10:54:58.404166 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1280 skip
11303 10:54:58.404449 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1280 skip
11304 10:54:58.404556 arm64_sve-ptrace_Set_Streaming_SVE_VL_1296 pass
11305 10:54:58.404645 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1296 skip
11306 10:54:58.404928 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1296 skip
11307 10:54:58.405034 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1296 skip
11308 10:54:58.405124 arm64_sve-ptrace_Set_Streaming_SVE_VL_1312 pass
11309 10:54:58.405211 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1312 skip
11310 10:54:58.405493 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1312 skip
11311 10:54:58.405593 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1312 skip
11312 10:54:58.405700 arm64_sve-ptrace_Set_Streaming_SVE_VL_1328 pass
11313 10:54:58.405794 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1328 skip
11314 10:54:58.406068 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1328 skip
11315 10:54:58.406166 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1328 skip
11316 10:54:58.406257 arm64_sve-ptrace_Set_Streaming_SVE_VL_1344 pass
11317 10:54:58.406530 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1344 skip
11318 10:54:58.406626 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1344 skip
11319 10:54:58.406717 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1344 skip
11320 10:54:58.406993 arm64_sve-ptrace_Set_Streaming_SVE_VL_1360 pass
11321 10:54:58.407100 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1360 skip
11322 10:54:58.407400 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1360 skip
11323 10:54:58.407505 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1360 skip
11324 10:54:58.411807 arm64_sve-ptrace_Set_Streaming_SVE_VL_1376 pass
11325 10:54:58.411952 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1376 skip
11326 10:54:58.412259 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1376 skip
11327 10:54:58.412357 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1376 skip
11328 10:54:58.412448 arm64_sve-ptrace_Set_Streaming_SVE_VL_1392 pass
11329 10:54:58.412538 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1392 skip
11330 10:54:58.412616 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1392 skip
11331 10:54:58.412706 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1392 skip
11332 10:54:58.413010 arm64_sve-ptrace_Set_Streaming_SVE_VL_1408 pass
11333 10:54:58.413116 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1408 skip
11334 10:54:58.413215 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1408 skip
11335 10:54:58.413312 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1408 skip
11336 10:54:58.413408 arm64_sve-ptrace_Set_Streaming_SVE_VL_1424 pass
11337 10:54:58.413502 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1424 skip
11338 10:54:58.413797 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1424 skip
11339 10:54:58.413901 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1424 skip
11340 10:54:58.414000 arm64_sve-ptrace_Set_Streaming_SVE_VL_1440 pass
11341 10:54:58.414272 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1440 skip
11342 10:54:58.414364 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1440 skip
11343 10:54:58.414507 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1440 skip
11344 10:54:58.414626 arm64_sve-ptrace_Set_Streaming_SVE_VL_1456 pass
11345 10:54:58.414885 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1456 skip
11346 10:54:58.414983 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1456 skip
11347 10:54:58.415092 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1456 skip
11348 10:54:58.415182 arm64_sve-ptrace_Set_Streaming_SVE_VL_1472 pass
11349 10:54:58.415448 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1472 skip
11350 10:54:58.419655 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1472 skip
11351 10:54:58.420044 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1472 skip
11352 10:54:58.420164 arm64_sve-ptrace_Set_Streaming_SVE_VL_1488 pass
11353 10:54:58.420281 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1488 skip
11354 10:54:58.420416 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1488 skip
11355 10:54:58.420523 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1488 skip
11356 10:54:58.420657 arm64_sve-ptrace_Set_Streaming_SVE_VL_1504 pass
11357 10:54:58.420764 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1504 skip
11358 10:54:58.420898 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1504 skip
11359 10:54:58.421004 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1504 skip
11360 10:54:58.421136 arm64_sve-ptrace_Set_Streaming_SVE_VL_1520 pass
11361 10:54:58.421262 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1520 skip
11362 10:54:58.421414 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1520 skip
11363 10:54:58.421545 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1520 skip
11364 10:54:58.421736 arm64_sve-ptrace_Set_Streaming_SVE_VL_1536 pass
11365 10:54:58.421902 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1536 skip
11366 10:54:58.422075 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1536 skip
11367 10:54:58.422239 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1536 skip
11368 10:54:58.422421 arm64_sve-ptrace_Set_Streaming_SVE_VL_1552 pass
11369 10:54:58.422563 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1552 skip
11370 10:54:58.423245 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1552 skip
11371 10:54:58.423391 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1552 skip
11372 10:54:58.439031 arm64_sve-ptrace_Set_Streaming_SVE_VL_1568 pass
11373 10:54:58.439454 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1568 skip
11374 10:54:58.439556 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1568 skip
11375 10:54:58.439637 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1568 skip
11376 10:54:58.439730 arm64_sve-ptrace_Set_Streaming_SVE_VL_1584 pass
11377 10:54:58.439808 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1584 skip
11378 10:54:58.439902 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1584 skip
11379 10:54:58.440307 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1584 skip
11380 10:54:58.440418 arm64_sve-ptrace_Set_Streaming_SVE_VL_1600 pass
11381 10:54:58.440517 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1600 skip
11382 10:54:58.440659 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1600 skip
11383 10:54:58.440813 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1600 skip
11384 10:54:58.440962 arm64_sve-ptrace_Set_Streaming_SVE_VL_1616 pass
11385 10:54:58.441080 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1616 skip
11386 10:54:58.441218 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1616 skip
11387 10:54:58.441339 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1616 skip
11388 10:54:58.441481 arm64_sve-ptrace_Set_Streaming_SVE_VL_1632 pass
11389 10:54:58.441620 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1632 skip
11390 10:54:58.441770 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1632 skip
11391 10:54:58.441910 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1632 skip
11392 10:54:58.442055 arm64_sve-ptrace_Set_Streaming_SVE_VL_1648 pass
11393 10:54:58.442188 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1648 skip
11394 10:54:58.442323 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1648 skip
11395 10:54:58.442459 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1648 skip
11396 10:54:58.442604 arm64_sve-ptrace_Set_Streaming_SVE_VL_1664 pass
11397 10:54:58.442748 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1664 skip
11398 10:54:58.442892 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1664 skip
11399 10:54:58.443040 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1664 skip
11400 10:54:58.443220 arm64_sve-ptrace_Set_Streaming_SVE_VL_1680 pass
11401 10:54:58.443376 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1680 skip
11402 10:54:58.447722 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1680 skip
11403 10:54:58.448214 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1680 skip
11404 10:54:58.448471 arm64_sve-ptrace_Set_Streaming_SVE_VL_1696 pass
11405 10:54:58.448647 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1696 skip
11406 10:54:58.448805 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1696 skip
11407 10:54:58.448960 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1696 skip
11408 10:54:58.449098 arm64_sve-ptrace_Set_Streaming_SVE_VL_1712 pass
11409 10:54:58.449262 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1712 skip
11410 10:54:58.449434 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1712 skip
11411 10:54:58.449573 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1712 skip
11412 10:54:58.449774 arm64_sve-ptrace_Set_Streaming_SVE_VL_1728 pass
11413 10:54:58.449903 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1728 skip
11414 10:54:58.450011 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1728 skip
11415 10:54:58.450113 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1728 skip
11416 10:54:58.450203 arm64_sve-ptrace_Set_Streaming_SVE_VL_1744 pass
11417 10:54:58.450312 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1744 skip
11418 10:54:58.450406 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1744 skip
11419 10:54:58.450508 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1744 skip
11420 10:54:58.450609 arm64_sve-ptrace_Set_Streaming_SVE_VL_1760 pass
11421 10:54:58.450729 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1760 skip
11422 10:54:58.450876 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1760 skip
11423 10:54:58.451243 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1760 skip
11424 10:54:58.451405 arm64_sve-ptrace_Set_Streaming_SVE_VL_1776 pass
11425 10:54:58.451558 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1776 skip
11426 10:54:58.451897 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1776 skip
11427 10:54:58.452018 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1776 skip
11428 10:54:58.452112 arm64_sve-ptrace_Set_Streaming_SVE_VL_1792 pass
11429 10:54:58.455775 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1792 skip
11430 10:54:58.456288 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1792 skip
11431 10:54:58.456467 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1792 skip
11432 10:54:58.456625 arm64_sve-ptrace_Set_Streaming_SVE_VL_1808 pass
11433 10:54:58.456803 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1808 skip
11434 10:54:58.456956 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1808 skip
11435 10:54:58.457088 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1808 skip
11436 10:54:58.457209 arm64_sve-ptrace_Set_Streaming_SVE_VL_1824 pass
11437 10:54:58.457350 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1824 skip
11438 10:54:58.457475 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1824 skip
11439 10:54:58.457677 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1824 skip
11440 10:54:58.457857 arm64_sve-ptrace_Set_Streaming_SVE_VL_1840 pass
11441 10:54:58.458040 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1840 skip
11442 10:54:58.458205 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1840 skip
11443 10:54:58.458406 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1840 skip
11444 10:54:58.458553 arm64_sve-ptrace_Set_Streaming_SVE_VL_1856 pass
11445 10:54:58.458676 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1856 skip
11446 10:54:58.458796 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1856 skip
11447 10:54:58.458937 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1856 skip
11448 10:54:58.459061 arm64_sve-ptrace_Set_Streaming_SVE_VL_1872 pass
11449 10:54:58.459177 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1872 skip
11450 10:54:58.459313 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1872 skip
11451 10:54:58.459436 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1872 skip
11452 10:54:58.459590 arm64_sve-ptrace_Set_Streaming_SVE_VL_1888 pass
11453 10:54:58.459694 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1888 skip
11454 10:54:58.459786 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1888 skip
11455 10:54:58.459876 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1888 skip
11456 10:54:58.459966 arm64_sve-ptrace_Set_Streaming_SVE_VL_1904 pass
11457 10:54:58.460055 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1904 skip
11458 10:54:58.463699 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1904 skip
11459 10:54:58.464193 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1904 skip
11460 10:54:58.464441 arm64_sve-ptrace_Set_Streaming_SVE_VL_1920 pass
11461 10:54:58.464665 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1920 skip
11462 10:54:58.464835 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1920 skip
11463 10:54:58.464999 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1920 skip
11464 10:54:58.465160 arm64_sve-ptrace_Set_Streaming_SVE_VL_1936 pass
11465 10:54:58.465350 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1936 skip
11466 10:54:58.465517 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1936 skip
11467 10:54:58.465704 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1936 skip
11468 10:54:58.465885 arm64_sve-ptrace_Set_Streaming_SVE_VL_1952 pass
11469 10:54:58.466084 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1952 skip
11470 10:54:58.466305 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1952 skip
11471 10:54:58.466570 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1952 skip
11472 10:54:58.466767 arm64_sve-ptrace_Set_Streaming_SVE_VL_1968 pass
11473 10:54:58.466915 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1968 skip
11474 10:54:58.467079 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1968 skip
11475 10:54:58.467275 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1968 skip
11476 10:54:58.467458 arm64_sve-ptrace_Set_Streaming_SVE_VL_1984 pass
11477 10:54:58.467623 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1984 skip
11478 10:54:58.467745 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1984 skip
11479 10:54:58.467859 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1984 skip
11480 10:54:58.467971 arm64_sve-ptrace_Set_Streaming_SVE_VL_2000 pass
11481 10:54:58.468082 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2000 skip
11482 10:54:58.468196 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2000 skip
11483 10:54:58.468307 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2000 skip
11484 10:54:58.468444 arm64_sve-ptrace_Set_Streaming_SVE_VL_2016 pass
11485 10:54:58.471739 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2016 skip
11486 10:54:58.472064 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2016 skip
11487 10:54:58.472828 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2016 skip
11488 10:54:58.472920 arm64_sve-ptrace_Set_Streaming_SVE_VL_2032 pass
11489 10:54:58.472997 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2032 skip
11490 10:54:58.473071 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2032 skip
11491 10:54:58.473145 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2032 skip
11492 10:54:58.473222 arm64_sve-ptrace_Set_Streaming_SVE_VL_2048 pass
11493 10:54:58.473496 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2048 skip
11494 10:54:58.473591 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2048 skip
11495 10:54:58.473676 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2048 skip
11496 10:54:58.473752 arm64_sve-ptrace_Set_Streaming_SVE_VL_2064 pass
11497 10:54:58.473827 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2064 skip
11498 10:54:58.473918 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2064 skip
11499 10:54:58.473996 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2064 skip
11500 10:54:58.474074 arm64_sve-ptrace_Set_Streaming_SVE_VL_2080 pass
11501 10:54:58.474168 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2080 skip
11502 10:54:58.474683 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2080 skip
11503 10:54:58.474884 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2080 skip
11504 10:54:58.475012 arm64_sve-ptrace_Set_Streaming_SVE_VL_2096 pass
11505 10:54:58.475104 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2096 skip
11506 10:54:58.495953 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2096 skip
11507 10:54:58.496418 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2096 skip
11508 10:54:58.496517 arm64_sve-ptrace_Set_Streaming_SVE_VL_2112 pass
11509 10:54:58.496602 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2112 skip
11510 10:54:58.496702 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2112 skip
11511 10:54:58.496776 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2112 skip
11512 10:54:58.496855 arm64_sve-ptrace_Set_Streaming_SVE_VL_2128 pass
11513 10:54:58.497112 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2128 skip
11514 10:54:58.497195 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2128 skip
11515 10:54:58.497450 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2128 skip
11516 10:54:58.497678 arm64_sve-ptrace_Set_Streaming_SVE_VL_2144 pass
11517 10:54:58.497952 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2144 skip
11518 10:54:58.498040 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2144 skip
11519 10:54:58.498119 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2144 skip
11520 10:54:58.498377 arm64_sve-ptrace_Set_Streaming_SVE_VL_2160 pass
11521 10:54:58.498466 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2160 skip
11522 10:54:58.498568 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2160 skip
11523 10:54:58.498832 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2160 skip
11524 10:54:58.498914 arm64_sve-ptrace_Set_Streaming_SVE_VL_2176 pass
11525 10:54:58.499168 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2176 skip
11526 10:54:58.499249 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2176 skip
11527 10:54:58.499502 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2176 skip
11528 10:54:58.503691 arm64_sve-ptrace_Set_Streaming_SVE_VL_2192 pass
11529 10:54:58.504020 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2192 skip
11530 10:54:58.504152 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2192 skip
11531 10:54:58.504268 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2192 skip
11532 10:54:58.504382 arm64_sve-ptrace_Set_Streaming_SVE_VL_2208 pass
11533 10:54:58.504665 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2208 skip
11534 10:54:58.504753 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2208 skip
11535 10:54:58.505039 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2208 skip
11536 10:54:58.505141 arm64_sve-ptrace_Set_Streaming_SVE_VL_2224 pass
11537 10:54:58.505454 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2224 skip
11538 10:54:58.505566 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2224 skip
11539 10:54:58.505750 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2224 skip
11540 10:54:58.506058 arm64_sve-ptrace_Set_Streaming_SVE_VL_2240 pass
11541 10:54:58.506178 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2240 skip
11542 10:54:58.506489 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2240 skip
11543 10:54:58.506604 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2240 skip
11544 10:54:58.506718 arm64_sve-ptrace_Set_Streaming_SVE_VL_2256 pass
11545 10:54:58.506997 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2256 skip
11546 10:54:58.507290 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2256 skip
11547 10:54:58.507382 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2256 skip
11548 10:54:58.507495 arm64_sve-ptrace_Set_Streaming_SVE_VL_2272 pass
11549 10:54:58.511630 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2272 skip
11550 10:54:58.512042 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2272 skip
11551 10:54:58.512204 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2272 skip
11552 10:54:58.512371 arm64_sve-ptrace_Set_Streaming_SVE_VL_2288 pass
11553 10:54:58.512511 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2288 skip
11554 10:54:58.512666 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2288 skip
11555 10:54:58.512802 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2288 skip
11556 10:54:58.513044 arm64_sve-ptrace_Set_Streaming_SVE_VL_2304 pass
11557 10:54:58.513202 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2304 skip
11558 10:54:58.513358 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2304 skip
11559 10:54:58.513495 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2304 skip
11560 10:54:58.513663 arm64_sve-ptrace_Set_Streaming_SVE_VL_2320 pass
11561 10:54:58.513802 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2320 skip
11562 10:54:58.513961 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2320 skip
11563 10:54:58.514099 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2320 skip
11564 10:54:58.514253 arm64_sve-ptrace_Set_Streaming_SVE_VL_2336 pass
11565 10:54:58.514414 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2336 skip
11566 10:54:58.514652 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2336 skip
11567 10:54:58.514833 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2336 skip
11568 10:54:58.515040 arm64_sve-ptrace_Set_Streaming_SVE_VL_2352 pass
11569 10:54:58.515225 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2352 skip
11570 10:54:58.515398 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2352 skip
11571 10:54:58.515566 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2352 skip
11572 10:54:58.515706 arm64_sve-ptrace_Set_Streaming_SVE_VL_2368 pass
11573 10:54:58.520021 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2368 skip
11574 10:54:58.520229 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2368 skip
11575 10:54:58.520446 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2368 skip
11576 10:54:58.520594 arm64_sve-ptrace_Set_Streaming_SVE_VL_2384 pass
11577 10:54:58.520740 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2384 skip
11578 10:54:58.520890 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2384 skip
11579 10:54:58.521053 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2384 skip
11580 10:54:58.521139 arm64_sve-ptrace_Set_Streaming_SVE_VL_2400 pass
11581 10:54:58.521231 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2400 skip
11582 10:54:58.521318 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2400 skip
11583 10:54:58.521598 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2400 skip
11584 10:54:58.521714 arm64_sve-ptrace_Set_Streaming_SVE_VL_2416 pass
11585 10:54:58.521825 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2416 skip
11586 10:54:58.522124 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2416 skip
11587 10:54:58.522243 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2416 skip
11588 10:54:58.522345 arm64_sve-ptrace_Set_Streaming_SVE_VL_2432 pass
11589 10:54:58.522434 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2432 skip
11590 10:54:58.522701 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2432 skip
11591 10:54:58.522822 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2432 skip
11592 10:54:58.522926 arm64_sve-ptrace_Set_Streaming_SVE_VL_2448 pass
11593 10:54:58.523208 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2448 skip
11594 10:54:58.523330 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2448 skip
11595 10:54:58.528011 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2448 skip
11596 10:54:58.528130 arm64_sve-ptrace_Set_Streaming_SVE_VL_2464 pass
11597 10:54:58.528404 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2464 skip
11598 10:54:58.528488 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2464 skip
11599 10:54:58.528580 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2464 skip
11600 10:54:58.528671 arm64_sve-ptrace_Set_Streaming_SVE_VL_2480 pass
11601 10:54:58.528767 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2480 skip
11602 10:54:58.529071 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2480 skip
11603 10:54:58.529190 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2480 skip
11604 10:54:58.529485 arm64_sve-ptrace_Set_Streaming_SVE_VL_2496 pass
11605 10:54:58.529607 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2496 skip
11606 10:54:58.530003 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2496 skip
11607 10:54:58.530123 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2496 skip
11608 10:54:58.530219 arm64_sve-ptrace_Set_Streaming_SVE_VL_2512 pass
11609 10:54:58.530299 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2512 skip
11610 10:54:58.530517 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2512 skip
11611 10:54:58.530637 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2512 skip
11612 10:54:58.530740 arm64_sve-ptrace_Set_Streaming_SVE_VL_2528 pass
11613 10:54:58.531421 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2528 skip
11614 10:54:58.531524 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2528 skip
11615 10:54:58.531609 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2528 skip
11616 10:54:58.531693 arm64_sve-ptrace_Set_Streaming_SVE_VL_2544 pass
11617 10:54:58.535607 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2544 skip
11618 10:54:58.535939 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2544 skip
11619 10:54:58.536038 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2544 skip
11620 10:54:58.536136 arm64_sve-ptrace_Set_Streaming_SVE_VL_2560 pass
11621 10:54:58.536405 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2560 skip
11622 10:54:58.536491 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2560 skip
11623 10:54:58.536756 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2560 skip
11624 10:54:58.536841 arm64_sve-ptrace_Set_Streaming_SVE_VL_2576 pass
11625 10:54:58.537121 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2576 skip
11626 10:54:58.537218 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2576 skip
11627 10:54:58.537487 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2576 skip
11628 10:54:58.537572 arm64_sve-ptrace_Set_Streaming_SVE_VL_2592 pass
11629 10:54:58.537679 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2592 skip
11630 10:54:58.537979 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2592 skip
11631 10:54:58.538095 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2592 skip
11632 10:54:58.538195 arm64_sve-ptrace_Set_Streaming_SVE_VL_2608 pass
11633 10:54:58.538476 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2608 skip
11634 10:54:58.538564 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2608 skip
11635 10:54:58.538659 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2608 skip
11636 10:54:58.538754 arm64_sve-ptrace_Set_Streaming_SVE_VL_2624 pass
11637 10:54:58.539047 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2624 skip
11638 10:54:58.539151 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2624 skip
11639 10:54:58.539444 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2624 skip
11640 10:54:58.554476 arm64_sve-ptrace_Set_Streaming_SVE_VL_2640 pass
11641 10:54:58.554931 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2640 skip
11642 10:54:58.556058 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2640 skip
11643 10:54:58.556171 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2640 skip
11644 10:54:58.556275 arm64_sve-ptrace_Set_Streaming_SVE_VL_2656 pass
11645 10:54:58.556367 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2656 skip
11646 10:54:58.556451 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2656 skip
11647 10:54:58.556539 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2656 skip
11648 10:54:58.556624 arm64_sve-ptrace_Set_Streaming_SVE_VL_2672 pass
11649 10:54:58.556705 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2672 skip
11650 10:54:58.556983 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2672 skip
11651 10:54:58.557087 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2672 skip
11652 10:54:58.557191 arm64_sve-ptrace_Set_Streaming_SVE_VL_2688 pass
11653 10:54:58.557299 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2688 skip
11654 10:54:58.557414 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2688 skip
11655 10:54:58.557531 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2688 skip
11656 10:54:58.557656 arm64_sve-ptrace_Set_Streaming_SVE_VL_2704 pass
11657 10:54:58.557750 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2704 skip
11658 10:54:58.557853 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2704 skip
11659 10:54:58.557975 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2704 skip
11660 10:54:58.558128 arm64_sve-ptrace_Set_Streaming_SVE_VL_2720 pass
11661 10:54:58.558252 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2720 skip
11662 10:54:58.558590 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2720 skip
11663 10:54:58.558732 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2720 skip
11664 10:54:58.558864 arm64_sve-ptrace_Set_Streaming_SVE_VL_2736 pass
11665 10:54:58.559000 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2736 skip
11666 10:54:58.559344 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2736 skip
11667 10:54:58.559469 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2736 skip
11668 10:54:58.559632 arm64_sve-ptrace_Set_Streaming_SVE_VL_2752 pass
11669 10:54:58.559933 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2752 skip
11670 10:54:58.563668 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2752 skip
11671 10:54:58.563971 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2752 skip
11672 10:54:58.564075 arm64_sve-ptrace_Set_Streaming_SVE_VL_2768 pass
11673 10:54:58.564194 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2768 skip
11674 10:54:58.564325 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2768 skip
11675 10:54:58.564641 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2768 skip
11676 10:54:58.564742 arm64_sve-ptrace_Set_Streaming_SVE_VL_2784 pass
11677 10:54:58.564841 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2784 skip
11678 10:54:58.565117 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2784 skip
11679 10:54:58.565206 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2784 skip
11680 10:54:58.565488 arm64_sve-ptrace_Set_Streaming_SVE_VL_2800 pass
11681 10:54:58.565586 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2800 skip
11682 10:54:58.565695 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2800 skip
11683 10:54:58.565793 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2800 skip
11684 10:54:58.566092 arm64_sve-ptrace_Set_Streaming_SVE_VL_2816 pass
11685 10:54:58.566172 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2816 skip
11686 10:54:58.566445 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2816 skip
11687 10:54:58.566559 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2816 skip
11688 10:54:58.566644 arm64_sve-ptrace_Set_Streaming_SVE_VL_2832 pass
11689 10:54:58.567010 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2832 skip
11690 10:54:58.567094 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2832 skip
11691 10:54:58.567357 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2832 skip
11692 10:54:58.567466 arm64_sve-ptrace_Set_Streaming_SVE_VL_2848 pass
11693 10:54:58.567728 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2848 skip
11694 10:54:58.567805 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2848 skip
11695 10:54:58.567869 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2848 skip
11696 10:54:58.571923 arm64_sve-ptrace_Set_Streaming_SVE_VL_2864 pass
11697 10:54:58.572239 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2864 skip
11698 10:54:58.572329 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2864 skip
11699 10:54:58.572426 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2864 skip
11700 10:54:58.572730 arm64_sve-ptrace_Set_Streaming_SVE_VL_2880 pass
11701 10:54:58.572831 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2880 skip
11702 10:54:58.572939 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2880 skip
11703 10:54:58.573245 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2880 skip
11704 10:54:58.573324 arm64_sve-ptrace_Set_Streaming_SVE_VL_2896 pass
11705 10:54:58.573644 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2896 skip
11706 10:54:58.573751 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2896 skip
11707 10:54:58.574040 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2896 skip
11708 10:54:58.574137 arm64_sve-ptrace_Set_Streaming_SVE_VL_2912 pass
11709 10:54:58.574218 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2912 skip
11710 10:54:58.574500 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2912 skip
11711 10:54:58.574598 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2912 skip
11712 10:54:58.574662 arm64_sve-ptrace_Set_Streaming_SVE_VL_2928 pass
11713 10:54:58.574733 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2928 skip
11714 10:54:58.574993 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2928 skip
11715 10:54:58.575073 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2928 skip
11716 10:54:58.575335 arm64_sve-ptrace_Set_Streaming_SVE_VL_2944 pass
11717 10:54:58.575430 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2944 skip
11718 10:54:58.575499 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2944 skip
11719 10:54:58.579598 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2944 skip
11720 10:54:58.579935 arm64_sve-ptrace_Set_Streaming_SVE_VL_2960 pass
11721 10:54:58.580046 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2960 skip
11722 10:54:58.580160 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2960 skip
11723 10:54:58.580270 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2960 skip
11724 10:54:58.580375 arm64_sve-ptrace_Set_Streaming_SVE_VL_2976 pass
11725 10:54:58.580687 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2976 skip
11726 10:54:58.580992 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2976 skip
11727 10:54:58.581092 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2976 skip
11728 10:54:58.581193 arm64_sve-ptrace_Set_Streaming_SVE_VL_2992 pass
11729 10:54:58.581281 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2992 skip
11730 10:54:58.581571 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2992 skip
11731 10:54:58.581703 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2992 skip
11732 10:54:58.582013 arm64_sve-ptrace_Set_Streaming_SVE_VL_3008 pass
11733 10:54:58.582305 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3008 skip
11734 10:54:58.582404 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3008 skip
11735 10:54:58.582517 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3008 skip
11736 10:54:58.582641 arm64_sve-ptrace_Set_Streaming_SVE_VL_3024 pass
11737 10:54:58.582769 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3024 skip
11738 10:54:58.583085 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3024 skip
11739 10:54:58.583199 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3024 skip
11740 10:54:58.583514 arm64_sve-ptrace_Set_Streaming_SVE_VL_3040 pass
11741 10:54:58.587592 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3040 skip
11742 10:54:58.587892 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3040 skip
11743 10:54:58.588173 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3040 skip
11744 10:54:58.588281 arm64_sve-ptrace_Set_Streaming_SVE_VL_3056 pass
11745 10:54:58.588371 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3056 skip
11746 10:54:58.588499 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3056 skip
11747 10:54:58.588629 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3056 skip
11748 10:54:58.588766 arm64_sve-ptrace_Set_Streaming_SVE_VL_3072 pass
11749 10:54:58.588899 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3072 skip
11750 10:54:58.589025 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3072 skip
11751 10:54:58.589358 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3072 skip
11752 10:54:58.589470 arm64_sve-ptrace_Set_Streaming_SVE_VL_3088 pass
11753 10:54:58.589580 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3088 skip
11754 10:54:58.589691 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3088 skip
11755 10:54:58.589992 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3088 skip
11756 10:54:58.590117 arm64_sve-ptrace_Set_Streaming_SVE_VL_3104 pass
11757 10:54:58.590416 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3104 skip
11758 10:54:58.590722 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3104 skip
11759 10:54:58.590826 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3104 skip
11760 10:54:58.590917 arm64_sve-ptrace_Set_Streaming_SVE_VL_3120 pass
11761 10:54:58.591231 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3120 skip
11762 10:54:58.591336 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3120 skip
11763 10:54:58.591646 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3120 skip
11764 10:54:58.591751 arm64_sve-ptrace_Set_Streaming_SVE_VL_3136 pass
11765 10:54:58.599570 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3136 skip
11766 10:54:58.599882 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3136 skip
11767 10:54:58.599975 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3136 skip
11768 10:54:58.600270 arm64_sve-ptrace_Set_Streaming_SVE_VL_3152 pass
11769 10:54:58.600373 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3152 skip
11770 10:54:58.600481 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3152 skip
11771 10:54:58.600607 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3152 skip
11772 10:54:58.600717 arm64_sve-ptrace_Set_Streaming_SVE_VL_3168 pass
11773 10:54:58.601014 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3168 skip
11774 10:54:58.610646 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3168 skip
11775 10:54:58.611052 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3168 skip
11776 10:54:58.611169 arm64_sve-ptrace_Set_Streaming_SVE_VL_3184 pass
11777 10:54:58.611285 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3184 skip
11778 10:54:58.611414 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3184 skip
11779 10:54:58.611513 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3184 skip
11780 10:54:58.611808 arm64_sve-ptrace_Set_Streaming_SVE_VL_3200 pass
11781 10:54:58.612138 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3200 skip
11782 10:54:58.612248 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3200 skip
11783 10:54:58.612554 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3200 skip
11784 10:54:58.612666 arm64_sve-ptrace_Set_Streaming_SVE_VL_3216 pass
11785 10:54:58.612973 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3216 skip
11786 10:54:58.613082 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3216 skip
11787 10:54:58.613175 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3216 skip
11788 10:54:58.613471 arm64_sve-ptrace_Set_Streaming_SVE_VL_3232 pass
11789 10:54:58.613576 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3232 skip
11790 10:54:58.613689 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3232 skip
11791 10:54:58.613788 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3232 skip
11792 10:54:58.613886 arm64_sve-ptrace_Set_Streaming_SVE_VL_3248 pass
11793 10:54:58.614193 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3248 skip
11794 10:54:58.614775 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3248 skip
11795 10:54:58.614892 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3248 skip
11796 10:54:58.615011 arm64_sve-ptrace_Set_Streaming_SVE_VL_3264 pass
11797 10:54:58.615321 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3264 skip
11798 10:54:58.615410 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3264 skip
11799 10:54:58.615526 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3264 skip
11800 10:54:58.615629 arm64_sve-ptrace_Set_Streaming_SVE_VL_3280 pass
11801 10:54:58.615740 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3280 skip
11802 10:54:58.619853 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3280 skip
11803 10:54:58.620291 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3280 skip
11804 10:54:58.620385 arm64_sve-ptrace_Set_Streaming_SVE_VL_3296 pass
11805 10:54:58.620486 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3296 skip
11806 10:54:58.620569 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3296 skip
11807 10:54:58.620662 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3296 skip
11808 10:54:58.620748 arm64_sve-ptrace_Set_Streaming_SVE_VL_3312 pass
11809 10:54:58.620841 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3312 skip
11810 10:54:58.620951 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3312 skip
11811 10:54:58.621067 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3312 skip
11812 10:54:58.621158 arm64_sve-ptrace_Set_Streaming_SVE_VL_3328 pass
11813 10:54:58.621441 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3328 skip
11814 10:54:58.621693 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3328 skip
11815 10:54:58.621814 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3328 skip
11816 10:54:58.621926 arm64_sve-ptrace_Set_Streaming_SVE_VL_3344 pass
11817 10:54:58.622020 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3344 skip
11818 10:54:58.622151 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3344 skip
11819 10:54:58.622257 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3344 skip
11820 10:54:58.622354 arm64_sve-ptrace_Set_Streaming_SVE_VL_3360 pass
11821 10:54:58.622448 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3360 skip
11822 10:54:58.622834 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3360 skip
11823 10:54:58.622935 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3360 skip
11824 10:54:58.623004 arm64_sve-ptrace_Set_Streaming_SVE_VL_3376 pass
11825 10:54:58.623330 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3376 skip
11826 10:54:58.623430 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3376 skip
11827 10:54:58.623505 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3376 skip
11828 10:54:58.624156 arm64_sve-ptrace_Set_Streaming_SVE_VL_3392 pass
11829 10:54:58.624247 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3392 skip
11830 10:54:58.627921 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3392 skip
11831 10:54:58.628348 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3392 skip
11832 10:54:58.628455 arm64_sve-ptrace_Set_Streaming_SVE_VL_3408 pass
11833 10:54:58.628547 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3408 skip
11834 10:54:58.628667 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3408 skip
11835 10:54:58.628772 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3408 skip
11836 10:54:58.628894 arm64_sve-ptrace_Set_Streaming_SVE_VL_3424 pass
11837 10:54:58.628985 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3424 skip
11838 10:54:58.629589 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3424 skip
11839 10:54:58.629709 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3424 skip
11840 10:54:58.629804 arm64_sve-ptrace_Set_Streaming_SVE_VL_3440 pass
11841 10:54:58.629896 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3440 skip
11842 10:54:58.630207 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3440 skip
11843 10:54:58.630312 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3440 skip
11844 10:54:58.630403 arm64_sve-ptrace_Set_Streaming_SVE_VL_3456 pass
11845 10:54:58.630486 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3456 skip
11846 10:54:58.630593 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3456 skip
11847 10:54:58.630895 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3456 skip
11848 10:54:58.631000 arm64_sve-ptrace_Set_Streaming_SVE_VL_3472 pass
11849 10:54:58.631104 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3472 skip
11850 10:54:58.631206 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3472 skip
11851 10:54:58.631309 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3472 skip
11852 10:54:58.631611 arm64_sve-ptrace_Set_Streaming_SVE_VL_3488 pass
11853 10:54:58.636165 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3488 skip
11854 10:54:58.636350 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3488 skip
11855 10:54:58.636437 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3488 skip
11856 10:54:58.636732 arm64_sve-ptrace_Set_Streaming_SVE_VL_3504 pass
11857 10:54:58.636827 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3504 skip
11858 10:54:58.636902 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3504 skip
11859 10:54:58.636970 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3504 skip
11860 10:54:58.637031 arm64_sve-ptrace_Set_Streaming_SVE_VL_3520 pass
11861 10:54:58.637304 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3520 skip
11862 10:54:58.637417 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3520 skip
11863 10:54:58.637523 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3520 skip
11864 10:54:58.637633 arm64_sve-ptrace_Set_Streaming_SVE_VL_3536 pass
11865 10:54:58.637741 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3536 skip
11866 10:54:58.637844 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3536 skip
11867 10:54:58.637927 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3536 skip
11868 10:54:58.638021 arm64_sve-ptrace_Set_Streaming_SVE_VL_3552 pass
11869 10:54:58.638311 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3552 skip
11870 10:54:58.638424 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3552 skip
11871 10:54:58.638516 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3552 skip
11872 10:54:58.638804 arm64_sve-ptrace_Set_Streaming_SVE_VL_3568 pass
11873 10:54:58.638906 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3568 skip
11874 10:54:58.638999 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3568 skip
11875 10:54:58.639370 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3568 skip
11876 10:54:58.639482 arm64_sve-ptrace_Set_Streaming_SVE_VL_3584 pass
11877 10:54:58.639574 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3584 skip
11878 10:54:58.639664 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3584 skip
11879 10:54:58.639940 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3584 skip
11880 10:54:58.640043 arm64_sve-ptrace_Set_Streaming_SVE_VL_3600 pass
11881 10:54:58.648691 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3600 skip
11882 10:54:58.648847 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3600 skip
11883 10:54:58.648929 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3600 skip
11884 10:54:58.649027 arm64_sve-ptrace_Set_Streaming_SVE_VL_3616 pass
11885 10:54:58.649110 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3616 skip
11886 10:54:58.649185 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3616 skip
11887 10:54:58.649259 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3616 skip
11888 10:54:58.649336 arm64_sve-ptrace_Set_Streaming_SVE_VL_3632 pass
11889 10:54:58.649403 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3632 skip
11890 10:54:58.649490 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3632 skip
11891 10:54:58.649779 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3632 skip
11892 10:54:58.649882 arm64_sve-ptrace_Set_Streaming_SVE_VL_3648 pass
11893 10:54:58.649966 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3648 skip
11894 10:54:58.650046 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3648 skip
11895 10:54:58.650127 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3648 skip
11896 10:54:58.650205 arm64_sve-ptrace_Set_Streaming_SVE_VL_3664 pass
11897 10:54:58.650286 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3664 skip
11898 10:54:58.650367 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3664 skip
11899 10:54:58.650470 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3664 skip
11900 10:54:58.650556 arm64_sve-ptrace_Set_Streaming_SVE_VL_3680 pass
11901 10:54:58.650639 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3680 skip
11902 10:54:58.650721 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3680 skip
11903 10:54:58.650803 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3680 skip
11904 10:54:58.650898 arm64_sve-ptrace_Set_Streaming_SVE_VL_3696 pass
11905 10:54:58.650987 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3696 skip
11906 10:54:58.651087 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3696 skip
11907 10:54:58.651154 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3696 skip
11908 10:54:58.668096 arm64_sve-ptrace_Set_Streaming_SVE_VL_3712 pass
11909 10:54:58.668441 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3712 skip
11910 10:54:58.668556 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3712 skip
11911 10:54:58.668684 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3712 skip
11912 10:54:58.668778 arm64_sve-ptrace_Set_Streaming_SVE_VL_3728 pass
11913 10:54:58.668876 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3728 skip
11914 10:54:58.669003 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3728 skip
11915 10:54:58.669121 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3728 skip
11916 10:54:58.669423 arm64_sve-ptrace_Set_Streaming_SVE_VL_3744 pass
11917 10:54:58.669539 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3744 skip
11918 10:54:58.669653 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3744 skip
11919 10:54:58.669760 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3744 skip
11920 10:54:58.670062 arm64_sve-ptrace_Set_Streaming_SVE_VL_3760 pass
11921 10:54:58.670175 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3760 skip
11922 10:54:58.670283 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3760 skip
11923 10:54:58.670391 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3760 skip
11924 10:54:58.670538 arm64_sve-ptrace_Set_Streaming_SVE_VL_3776 pass
11925 10:54:58.670822 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3776 skip
11926 10:54:58.670946 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3776 skip
11927 10:54:58.671054 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3776 skip
11928 10:54:58.671342 arm64_sve-ptrace_Set_Streaming_SVE_VL_3792 pass
11929 10:54:58.671451 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3792 skip
11930 10:54:58.675595 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3792 skip
11931 10:54:58.675904 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3792 skip
11932 10:54:58.676011 arm64_sve-ptrace_Set_Streaming_SVE_VL_3808 pass
11933 10:54:58.676309 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3808 skip
11934 10:54:58.676426 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3808 skip
11935 10:54:58.676560 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3808 skip
11936 10:54:58.676666 arm64_sve-ptrace_Set_Streaming_SVE_VL_3824 pass
11937 10:54:58.676792 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3824 skip
11938 10:54:58.676909 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3824 skip
11939 10:54:58.677215 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3824 skip
11940 10:54:58.677316 arm64_sve-ptrace_Set_Streaming_SVE_VL_3840 pass
11941 10:54:58.677617 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3840 skip
11942 10:54:58.677729 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3840 skip
11943 10:54:58.677828 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3840 skip
11944 10:54:58.678190 arm64_sve-ptrace_Set_Streaming_SVE_VL_3856 pass
11945 10:54:58.678291 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3856 skip
11946 10:54:58.678383 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3856 skip
11947 10:54:58.678652 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3856 skip
11948 10:54:58.678774 arm64_sve-ptrace_Set_Streaming_SVE_VL_3872 pass
11949 10:54:58.678890 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3872 skip
11950 10:54:58.679017 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3872 skip
11951 10:54:58.679124 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3872 skip
11952 10:54:58.679232 arm64_sve-ptrace_Set_Streaming_SVE_VL_3888 pass
11953 10:54:58.679352 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3888 skip
11954 10:54:58.679461 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3888 skip
11955 10:54:58.679591 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3888 skip
11956 10:54:58.683589 arm64_sve-ptrace_Set_Streaming_SVE_VL_3904 pass
11957 10:54:58.683859 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3904 skip
11958 10:54:58.684170 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3904 skip
11959 10:54:58.684276 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3904 skip
11960 10:54:58.684582 arm64_sve-ptrace_Set_Streaming_SVE_VL_3920 pass
11961 10:54:58.684688 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3920 skip
11962 10:54:58.684796 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3920 skip
11963 10:54:58.684902 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3920 skip
11964 10:54:58.685005 arm64_sve-ptrace_Set_Streaming_SVE_VL_3936 pass
11965 10:54:58.685137 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3936 skip
11966 10:54:58.685487 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3936 skip
11967 10:54:58.685616 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3936 skip
11968 10:54:58.685750 arm64_sve-ptrace_Set_Streaming_SVE_VL_3952 pass
11969 10:54:58.685877 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3952 skip
11970 10:54:58.686004 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3952 skip
11971 10:54:58.686326 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3952 skip
11972 10:54:58.686472 arm64_sve-ptrace_Set_Streaming_SVE_VL_3968 pass
11973 10:54:58.686613 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3968 skip
11974 10:54:58.686742 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3968 skip
11975 10:54:58.687070 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3968 skip
11976 10:54:58.687172 arm64_sve-ptrace_Set_Streaming_SVE_VL_3984 pass
11977 10:54:58.687275 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3984 skip
11978 10:54:58.687391 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3984 skip
11979 10:54:58.691596 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3984 skip
11980 10:54:58.691939 arm64_sve-ptrace_Set_Streaming_SVE_VL_4000 pass
11981 10:54:58.692092 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4000 skip
11982 10:54:58.692249 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4000 skip
11983 10:54:58.692368 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4000 skip
11984 10:54:58.692507 arm64_sve-ptrace_Set_Streaming_SVE_VL_4016 pass
11985 10:54:58.692604 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4016 skip
11986 10:54:58.692724 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4016 skip
11987 10:54:58.692823 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4016 skip
11988 10:54:58.692954 arm64_sve-ptrace_Set_Streaming_SVE_VL_4032 pass
11989 10:54:58.693429 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4032 skip
11990 10:54:58.693533 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4032 skip
11991 10:54:58.693639 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4032 skip
11992 10:54:58.693987 arm64_sve-ptrace_Set_Streaming_SVE_VL_4048 pass
11993 10:54:58.694089 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4048 skip
11994 10:54:58.694177 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4048 skip
11995 10:54:58.694303 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4048 skip
11996 10:54:58.694397 arm64_sve-ptrace_Set_Streaming_SVE_VL_4064 pass
11997 10:54:58.694482 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4064 skip
11998 10:54:58.694581 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4064 skip
11999 10:54:58.694681 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4064 skip
12000 10:54:58.694966 arm64_sve-ptrace_Set_Streaming_SVE_VL_4080 pass
12001 10:54:58.695085 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4080 skip
12002 10:54:58.695206 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4080 skip
12003 10:54:58.695311 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4080 skip
12004 10:54:58.695597 arm64_sve-ptrace_Set_Streaming_SVE_VL_4096 pass
12005 10:54:58.695702 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4096 skip
12006 10:54:58.699630 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4096 skip
12007 10:54:58.699968 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4096 skip
12008 10:54:58.700097 arm64_sve-ptrace_Set_Streaming_SVE_VL_4112 pass
12009 10:54:58.700252 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4112 skip
12010 10:54:58.700360 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4112 skip
12011 10:54:58.700475 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4112 skip
12012 10:54:58.700583 arm64_sve-ptrace_Set_Streaming_SVE_VL_4128 pass
12013 10:54:58.700857 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4128 skip
12014 10:54:58.700942 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4128 skip
12015 10:54:58.701033 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4128 skip
12016 10:54:58.701584 arm64_sve-ptrace_Set_Streaming_SVE_VL_4144 pass
12017 10:54:58.701693 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4144 skip
12018 10:54:58.701776 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4144 skip
12019 10:54:58.701857 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4144 skip
12020 10:54:58.701936 arm64_sve-ptrace_Set_Streaming_SVE_VL_4160 pass
12021 10:54:58.702222 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4160 skip
12022 10:54:58.702332 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4160 skip
12023 10:54:58.702424 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4160 skip
12024 10:54:58.702519 arm64_sve-ptrace_Set_Streaming_SVE_VL_4176 pass
12025 10:54:58.702624 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4176 skip
12026 10:54:58.702716 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4176 skip
12027 10:54:58.702794 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4176 skip
12028 10:54:58.702879 arm64_sve-ptrace_Set_Streaming_SVE_VL_4192 pass
12029 10:54:58.703016 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4192 skip
12030 10:54:58.703137 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4192 skip
12031 10:54:58.703267 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4192 skip
12032 10:54:58.703381 arm64_sve-ptrace_Set_Streaming_SVE_VL_4208 pass
12033 10:54:58.703504 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4208 skip
12034 10:54:58.707606 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4208 skip
12035 10:54:58.707915 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4208 skip
12036 10:54:58.708007 arm64_sve-ptrace_Set_Streaming_SVE_VL_4224 pass
12037 10:54:58.708121 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4224 skip
12038 10:54:58.708245 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4224 skip
12039 10:54:58.708557 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4224 skip
12040 10:54:58.708655 arm64_sve-ptrace_Set_Streaming_SVE_VL_4240 pass
12041 10:54:58.708757 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4240 skip
12042 10:54:58.722388 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4240 skip
12043 10:54:58.722510 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4240 skip
12044 10:54:58.722783 arm64_sve-ptrace_Set_Streaming_SVE_VL_4256 pass
12045 10:54:58.722861 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4256 skip
12046 10:54:58.722952 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4256 skip
12047 10:54:58.723046 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4256 skip
12048 10:54:58.723141 arm64_sve-ptrace_Set_Streaming_SVE_VL_4272 pass
12049 10:54:58.723254 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4272 skip
12050 10:54:58.723576 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4272 skip
12051 10:54:58.723798 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4272 skip
12052 10:54:58.723946 arm64_sve-ptrace_Set_Streaming_SVE_VL_4288 pass
12053 10:54:58.724197 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4288 skip
12054 10:54:58.724375 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4288 skip
12055 10:54:58.724569 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4288 skip
12056 10:54:58.724804 arm64_sve-ptrace_Set_Streaming_SVE_VL_4304 pass
12057 10:54:58.724985 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4304 skip
12058 10:54:58.725159 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4304 skip
12059 10:54:58.725356 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4304 skip
12060 10:54:58.725594 arm64_sve-ptrace_Set_Streaming_SVE_VL_4320 pass
12061 10:54:58.725788 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4320 skip
12062 10:54:58.725986 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4320 skip
12063 10:54:58.726179 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4320 skip
12064 10:54:58.726355 arm64_sve-ptrace_Set_Streaming_SVE_VL_4336 pass
12065 10:54:58.726566 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4336 skip
12066 10:54:58.726746 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4336 skip
12067 10:54:58.726919 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4336 skip
12068 10:54:58.727083 arm64_sve-ptrace_Set_Streaming_SVE_VL_4352 pass
12069 10:54:58.727251 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4352 skip
12070 10:54:58.727421 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4352 skip
12071 10:54:58.727546 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4352 skip
12072 10:54:58.727693 arm64_sve-ptrace_Set_Streaming_SVE_VL_4368 pass
12073 10:54:58.727816 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4368 skip
12074 10:54:58.727934 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4368 skip
12075 10:54:58.728051 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4368 skip
12076 10:54:58.728167 arm64_sve-ptrace_Set_Streaming_SVE_VL_4384 pass
12077 10:54:58.728282 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4384 skip
12078 10:54:58.731813 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4384 skip
12079 10:54:58.731947 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4384 skip
12080 10:54:58.732091 arm64_sve-ptrace_Set_Streaming_SVE_VL_4400 pass
12081 10:54:58.732209 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4400 skip
12082 10:54:58.732330 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4400 skip
12083 10:54:58.732460 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4400 skip
12084 10:54:58.732603 arm64_sve-ptrace_Set_Streaming_SVE_VL_4416 pass
12085 10:54:58.732959 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4416 skip
12086 10:54:58.733126 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4416 skip
12087 10:54:58.733512 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4416 skip
12088 10:54:58.733728 arm64_sve-ptrace_Set_Streaming_SVE_VL_4432 pass
12089 10:54:58.733904 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4432 skip
12090 10:54:58.734063 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4432 skip
12091 10:54:58.734249 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4432 skip
12092 10:54:58.734403 arm64_sve-ptrace_Set_Streaming_SVE_VL_4448 pass
12093 10:54:58.734561 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4448 skip
12094 10:54:58.734727 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4448 skip
12095 10:54:58.734892 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4448 skip
12096 10:54:58.735092 arm64_sve-ptrace_Set_Streaming_SVE_VL_4464 pass
12097 10:54:58.735255 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4464 skip
12098 10:54:58.735418 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4464 skip
12099 10:54:58.735577 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4464 skip
12100 10:54:58.735698 arm64_sve-ptrace_Set_Streaming_SVE_VL_4480 pass
12101 10:54:58.735815 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4480 skip
12102 10:54:58.735958 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4480 skip
12103 10:54:58.736081 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4480 skip
12104 10:54:58.736197 arm64_sve-ptrace_Set_Streaming_SVE_VL_4496 pass
12105 10:54:58.739676 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4496 skip
12106 10:54:58.739976 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4496 skip
12107 10:54:58.740076 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4496 skip
12108 10:54:58.740155 arm64_sve-ptrace_Set_Streaming_SVE_VL_4512 pass
12109 10:54:58.740452 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4512 skip
12110 10:54:58.740554 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4512 skip
12111 10:54:58.740638 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4512 skip
12112 10:54:58.740734 arm64_sve-ptrace_Set_Streaming_SVE_VL_4528 pass
12113 10:54:58.740817 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4528 skip
12114 10:54:58.740912 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4528 skip
12115 10:54:58.740996 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4528 skip
12116 10:54:58.741093 arm64_sve-ptrace_Set_Streaming_SVE_VL_4544 pass
12117 10:54:58.741397 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4544 skip
12118 10:54:58.741693 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4544 skip
12119 10:54:58.741792 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4544 skip
12120 10:54:58.741895 arm64_sve-ptrace_Set_Streaming_SVE_VL_4560 pass
12121 10:54:58.741986 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4560 skip
12122 10:54:58.742275 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4560 skip
12123 10:54:58.742394 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4560 skip
12124 10:54:58.742494 arm64_sve-ptrace_Set_Streaming_SVE_VL_4576 pass
12125 10:54:58.742773 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4576 skip
12126 10:54:58.742873 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4576 skip
12127 10:54:58.743173 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4576 skip
12128 10:54:58.743280 arm64_sve-ptrace_Set_Streaming_SVE_VL_4592 pass
12129 10:54:58.743385 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4592 skip
12130 10:54:58.743500 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4592 skip
12131 10:54:58.743571 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4592 skip
12132 10:54:58.747829 arm64_sve-ptrace_Set_Streaming_SVE_VL_4608 pass
12133 10:54:58.747939 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4608 skip
12134 10:54:58.748060 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4608 skip
12135 10:54:58.748191 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4608 skip
12136 10:54:58.748297 arm64_sve-ptrace_Set_Streaming_SVE_VL_4624 pass
12137 10:54:58.748582 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4624 skip
12138 10:54:58.748676 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4624 skip
12139 10:54:58.748770 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4624 skip
12140 10:54:58.749033 arm64_sve-ptrace_Set_Streaming_SVE_VL_4640 pass
12141 10:54:58.749116 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4640 skip
12142 10:54:58.749389 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4640 skip
12143 10:54:58.749503 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4640 skip
12144 10:54:58.749606 arm64_sve-ptrace_Set_Streaming_SVE_VL_4656 pass
12145 10:54:58.749738 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4656 skip
12146 10:54:58.749821 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4656 skip
12147 10:54:58.749929 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4656 skip
12148 10:54:58.750017 arm64_sve-ptrace_Set_Streaming_SVE_VL_4672 pass
12149 10:54:58.750114 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4672 skip
12150 10:54:58.750438 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4672 skip
12151 10:54:58.750639 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4672 skip
12152 10:54:58.750885 arm64_sve-ptrace_Set_Streaming_SVE_VL_4688 pass
12153 10:54:58.751085 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4688 skip
12154 10:54:58.751264 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4688 skip
12155 10:54:58.751469 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4688 skip
12156 10:54:58.751582 arm64_sve-ptrace_Set_Streaming_SVE_VL_4704 pass
12157 10:54:58.751674 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4704 skip
12158 10:54:58.751763 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4704 skip
12159 10:54:58.755614 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4704 skip
12160 10:54:58.755943 arm64_sve-ptrace_Set_Streaming_SVE_VL_4720 pass
12161 10:54:58.756051 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4720 skip
12162 10:54:58.756159 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4720 skip
12163 10:54:58.756261 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4720 skip
12164 10:54:58.756362 arm64_sve-ptrace_Set_Streaming_SVE_VL_4736 pass
12165 10:54:58.756647 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4736 skip
12166 10:54:58.756758 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4736 skip
12167 10:54:58.756864 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4736 skip
12168 10:54:58.756968 arm64_sve-ptrace_Set_Streaming_SVE_VL_4752 pass
12169 10:54:58.757254 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4752 skip
12170 10:54:58.757361 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4752 skip
12171 10:54:58.757461 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4752 skip
12172 10:54:58.757748 arm64_sve-ptrace_Set_Streaming_SVE_VL_4768 pass
12173 10:54:58.757854 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4768 skip
12174 10:54:58.757954 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4768 skip
12175 10:54:58.758243 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4768 skip
12176 10:54:58.772919 arm64_sve-ptrace_Set_Streaming_SVE_VL_4784 pass
12177 10:54:58.773222 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4784 skip
12178 10:54:58.773325 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4784 skip
12179 10:54:58.773431 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4784 skip
12180 10:54:58.773519 arm64_sve-ptrace_Set_Streaming_SVE_VL_4800 pass
12181 10:54:58.773624 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4800 skip
12182 10:54:58.773933 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4800 skip
12183 10:54:58.774049 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4800 skip
12184 10:54:58.774152 arm64_sve-ptrace_Set_Streaming_SVE_VL_4816 pass
12185 10:54:58.774479 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4816 skip
12186 10:54:58.774627 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4816 skip
12187 10:54:58.774797 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4816 skip
12188 10:54:58.774940 arm64_sve-ptrace_Set_Streaming_SVE_VL_4832 pass
12189 10:54:58.775133 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4832 skip
12190 10:54:58.775272 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4832 skip
12191 10:54:58.775422 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4832 skip
12192 10:54:58.775528 arm64_sve-ptrace_Set_Streaming_SVE_VL_4848 pass
12193 10:54:58.775869 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4848 skip
12194 10:54:58.776036 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4848 skip
12195 10:54:58.776161 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4848 skip
12196 10:54:58.776316 arm64_sve-ptrace_Set_Streaming_SVE_VL_4864 pass
12197 10:54:58.776500 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4864 skip
12198 10:54:58.776640 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4864 skip
12199 10:54:58.776772 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4864 skip
12200 10:54:58.776918 arm64_sve-ptrace_Set_Streaming_SVE_VL_4880 pass
12201 10:54:58.777057 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4880 skip
12202 10:54:58.777169 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4880 skip
12203 10:54:58.777315 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4880 skip
12204 10:54:58.777732 arm64_sve-ptrace_Set_Streaming_SVE_VL_4896 pass
12205 10:54:58.777982 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4896 skip
12206 10:54:58.778170 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4896 skip
12207 10:54:58.778339 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4896 skip
12208 10:54:58.778537 arm64_sve-ptrace_Set_Streaming_SVE_VL_4912 pass
12209 10:54:58.778757 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4912 skip
12210 10:54:58.778956 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4912 skip
12211 10:54:58.779165 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4912 skip
12212 10:54:58.779331 arm64_sve-ptrace_Set_Streaming_SVE_VL_4928 pass
12213 10:54:58.779523 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4928 skip
12214 10:54:58.779677 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4928 skip
12215 10:54:58.779827 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4928 skip
12216 10:54:58.779950 arm64_sve-ptrace_Set_Streaming_SVE_VL_4944 pass
12217 10:54:58.783815 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4944 skip
12218 10:54:58.783948 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4944 skip
12219 10:54:58.784234 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4944 skip
12220 10:54:58.784435 arm64_sve-ptrace_Set_Streaming_SVE_VL_4960 pass
12221 10:54:58.784613 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4960 skip
12222 10:54:58.784801 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4960 skip
12223 10:54:58.784974 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4960 skip
12224 10:54:58.785122 arm64_sve-ptrace_Set_Streaming_SVE_VL_4976 pass
12225 10:54:58.785292 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4976 skip
12226 10:54:58.785446 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4976 skip
12227 10:54:58.785604 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4976 skip
12228 10:54:58.785774 arm64_sve-ptrace_Set_Streaming_SVE_VL_4992 pass
12229 10:54:58.785962 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4992 skip
12230 10:54:58.786116 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4992 skip
12231 10:54:58.786250 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4992 skip
12232 10:54:58.786374 arm64_sve-ptrace_Set_Streaming_SVE_VL_5008 pass
12233 10:54:58.786520 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5008 skip
12234 10:54:58.786646 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5008 skip
12235 10:54:58.786767 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5008 skip
12236 10:54:58.786893 arm64_sve-ptrace_Set_Streaming_SVE_VL_5024 pass
12237 10:54:58.787012 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5024 skip
12238 10:54:58.787160 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5024 skip
12239 10:54:58.787312 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5024 skip
12240 10:54:58.787476 arm64_sve-ptrace_Set_Streaming_SVE_VL_5040 pass
12241 10:54:58.787609 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5040 skip
12242 10:54:58.787726 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5040 skip
12243 10:54:58.787867 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5040 skip
12244 10:54:58.787989 arm64_sve-ptrace_Set_Streaming_SVE_VL_5056 pass
12245 10:54:58.791646 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5056 skip
12246 10:54:58.791959 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5056 skip
12247 10:54:58.792063 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5056 skip
12248 10:54:58.792166 arm64_sve-ptrace_Set_Streaming_SVE_VL_5072 pass
12249 10:54:58.792463 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5072 skip
12250 10:54:58.792568 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5072 skip
12251 10:54:58.792678 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5072 skip
12252 10:54:58.792782 arm64_sve-ptrace_Set_Streaming_SVE_VL_5088 pass
12253 10:54:58.793089 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5088 skip
12254 10:54:58.793208 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5088 skip
12255 10:54:58.793319 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5088 skip
12256 10:54:58.793430 arm64_sve-ptrace_Set_Streaming_SVE_VL_5104 pass
12257 10:54:58.793634 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5104 skip
12258 10:54:58.793963 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5104 skip
12259 10:54:58.794132 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5104 skip
12260 10:54:58.794433 arm64_sve-ptrace_Set_Streaming_SVE_VL_5120 pass
12261 10:54:58.794584 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5120 skip
12262 10:54:58.794721 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5120 skip
12263 10:54:58.794874 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5120 skip
12264 10:54:58.795006 arm64_sve-ptrace_Set_Streaming_SVE_VL_5136 pass
12265 10:54:58.795192 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5136 skip
12266 10:54:58.795394 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5136 skip
12267 10:54:58.795560 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5136 skip
12268 10:54:58.795714 arm64_sve-ptrace_Set_Streaming_SVE_VL_5152 pass
12269 10:54:58.803826 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5152 skip
12270 10:54:58.804074 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5152 skip
12271 10:54:58.804380 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5152 skip
12272 10:54:58.804488 arm64_sve-ptrace_Set_Streaming_SVE_VL_5168 pass
12273 10:54:58.804575 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5168 skip
12274 10:54:58.804670 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5168 skip
12275 10:54:58.804756 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5168 skip
12276 10:54:58.804847 arm64_sve-ptrace_Set_Streaming_SVE_VL_5184 pass
12277 10:54:58.804920 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5184 skip
12278 10:54:58.805015 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5184 skip
12279 10:54:58.805312 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5184 skip
12280 10:54:58.805420 arm64_sve-ptrace_Set_Streaming_SVE_VL_5200 pass
12281 10:54:58.805531 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5200 skip
12282 10:54:58.805663 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5200 skip
12283 10:54:58.805794 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5200 skip
12284 10:54:58.805901 arm64_sve-ptrace_Set_Streaming_SVE_VL_5216 pass
12285 10:54:58.805993 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5216 skip
12286 10:54:58.806290 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5216 skip
12287 10:54:58.806403 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5216 skip
12288 10:54:58.806669 arm64_sve-ptrace_Set_Streaming_SVE_VL_5232 pass
12289 10:54:58.806775 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5232 skip
12290 10:54:58.806875 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5232 skip
12291 10:54:58.806964 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5232 skip
12292 10:54:58.807238 arm64_sve-ptrace_Set_Streaming_SVE_VL_5248 pass
12293 10:54:58.807326 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5248 skip
12294 10:54:58.807421 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5248 skip
12295 10:54:58.807488 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5248 skip
12296 10:54:58.811724 arm64_sve-ptrace_Set_Streaming_SVE_VL_5264 pass
12297 10:54:58.812012 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5264 skip
12298 10:54:58.812094 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5264 skip
12299 10:54:58.812385 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5264 skip
12300 10:54:58.812539 arm64_sve-ptrace_Set_Streaming_SVE_VL_5280 pass
12301 10:54:58.812672 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5280 skip
12302 10:54:58.812823 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5280 skip
12303 10:54:58.812956 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5280 skip
12304 10:54:58.813085 arm64_sve-ptrace_Set_Streaming_SVE_VL_5296 pass
12305 10:54:58.813233 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5296 skip
12306 10:54:58.813339 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5296 skip
12307 10:54:58.813431 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5296 skip
12308 10:54:58.813539 arm64_sve-ptrace_Set_Streaming_SVE_VL_5312 pass
12309 10:54:58.813633 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5312 skip
12310 10:54:58.825964 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5312 skip
12311 10:54:58.826088 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5312 skip
12312 10:54:58.826375 arm64_sve-ptrace_Set_Streaming_SVE_VL_5328 pass
12313 10:54:58.826484 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5328 skip
12314 10:54:58.826577 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5328 skip
12315 10:54:58.826678 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5328 skip
12316 10:54:58.826782 arm64_sve-ptrace_Set_Streaming_SVE_VL_5344 pass
12317 10:54:58.827064 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5344 skip
12318 10:54:58.827190 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5344 skip
12319 10:54:58.827287 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5344 skip
12320 10:54:58.827578 arm64_sve-ptrace_Set_Streaming_SVE_VL_5360 pass
12321 10:54:58.827866 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5360 skip
12322 10:54:58.828160 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5360 skip
12323 10:54:58.828267 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5360 skip
12324 10:54:58.828358 arm64_sve-ptrace_Set_Streaming_SVE_VL_5376 pass
12325 10:54:58.828457 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5376 skip
12326 10:54:58.828556 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5376 skip
12327 10:54:58.828853 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5376 skip
12328 10:54:58.828958 arm64_sve-ptrace_Set_Streaming_SVE_VL_5392 pass
12329 10:54:58.829061 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5392 skip
12330 10:54:58.829371 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5392 skip
12331 10:54:58.829491 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5392 skip
12332 10:54:58.829600 arm64_sve-ptrace_Set_Streaming_SVE_VL_5408 pass
12333 10:54:58.829919 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5408 skip
12334 10:54:58.830024 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5408 skip
12335 10:54:58.830127 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5408 skip
12336 10:54:58.830229 arm64_sve-ptrace_Set_Streaming_SVE_VL_5424 pass
12337 10:54:58.830526 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5424 skip
12338 10:54:58.830634 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5424 skip
12339 10:54:58.830743 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5424 skip
12340 10:54:58.830849 arm64_sve-ptrace_Set_Streaming_SVE_VL_5440 pass
12341 10:54:58.831192 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5440 skip
12342 10:54:58.831306 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5440 skip
12343 10:54:58.835594 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5440 skip
12344 10:54:58.835912 arm64_sve-ptrace_Set_Streaming_SVE_VL_5456 pass
12345 10:54:58.836075 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5456 skip
12346 10:54:58.836199 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5456 skip
12347 10:54:58.836323 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5456 skip
12348 10:54:58.836453 arm64_sve-ptrace_Set_Streaming_SVE_VL_5472 pass
12349 10:54:58.836608 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5472 skip
12350 10:54:58.836763 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5472 skip
12351 10:54:58.836893 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5472 skip
12352 10:54:58.837189 arm64_sve-ptrace_Set_Streaming_SVE_VL_5488 pass
12353 10:54:58.837291 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5488 skip
12354 10:54:58.837391 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5488 skip
12355 10:54:58.837494 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5488 skip
12356 10:54:58.837600 arm64_sve-ptrace_Set_Streaming_SVE_VL_5504 pass
12357 10:54:58.837927 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5504 skip
12358 10:54:58.838045 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5504 skip
12359 10:54:58.838131 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5504 skip
12360 10:54:58.838222 arm64_sve-ptrace_Set_Streaming_SVE_VL_5520 pass
12361 10:54:58.838502 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5520 skip
12362 10:54:58.838617 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5520 skip
12363 10:54:58.838718 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5520 skip
12364 10:54:58.838821 arm64_sve-ptrace_Set_Streaming_SVE_VL_5536 pass
12365 10:54:58.838943 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5536 skip
12366 10:54:58.839268 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5536 skip
12367 10:54:58.839369 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5536 skip
12368 10:54:58.839470 arm64_sve-ptrace_Set_Streaming_SVE_VL_5552 pass
12369 10:54:58.843623 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5552 skip
12370 10:54:58.843915 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5552 skip
12371 10:54:58.844009 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5552 skip
12372 10:54:58.844111 arm64_sve-ptrace_Set_Streaming_SVE_VL_5568 pass
12373 10:54:58.844212 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5568 skip
12374 10:54:58.844304 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5568 skip
12375 10:54:58.844569 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5568 skip
12376 10:54:58.844642 arm64_sve-ptrace_Set_Streaming_SVE_VL_5584 pass
12377 10:54:58.844724 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5584 skip
12378 10:54:58.844993 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5584 skip
12379 10:54:58.845078 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5584 skip
12380 10:54:58.845154 arm64_sve-ptrace_Set_Streaming_SVE_VL_5600 pass
12381 10:54:58.845401 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5600 skip
12382 10:54:58.845474 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5600 skip
12383 10:54:58.845549 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5600 skip
12384 10:54:58.845623 arm64_sve-ptrace_Set_Streaming_SVE_VL_5616 pass
12385 10:54:58.845778 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5616 skip
12386 10:54:58.846024 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5616 skip
12387 10:54:58.846092 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5616 skip
12388 10:54:58.846166 arm64_sve-ptrace_Set_Streaming_SVE_VL_5632 pass
12389 10:54:58.846230 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5632 skip
12390 10:54:58.846308 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5632 skip
12391 10:54:58.846557 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5632 skip
12392 10:54:58.846625 arm64_sve-ptrace_Set_Streaming_SVE_VL_5648 pass
12393 10:54:58.846698 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5648 skip
12394 10:54:58.846951 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5648 skip
12395 10:54:58.847018 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5648 skip
12396 10:54:58.847092 arm64_sve-ptrace_Set_Streaming_SVE_VL_5664 pass
12397 10:54:58.847166 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5664 skip
12398 10:54:58.847428 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5664 skip
12399 10:54:58.847512 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5664 skip
12400 10:54:58.851874 arm64_sve-ptrace_Set_Streaming_SVE_VL_5680 pass
12401 10:54:58.852009 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5680 skip
12402 10:54:58.852084 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5680 skip
12403 10:54:58.852148 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5680 skip
12404 10:54:58.852249 arm64_sve-ptrace_Set_Streaming_SVE_VL_5696 pass
12405 10:54:58.852352 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5696 skip
12406 10:54:58.852645 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5696 skip
12407 10:54:58.852943 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5696 skip
12408 10:54:58.853046 arm64_sve-ptrace_Set_Streaming_SVE_VL_5712 pass
12409 10:54:58.853141 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5712 skip
12410 10:54:58.853232 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5712 skip
12411 10:54:58.853324 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5712 skip
12412 10:54:58.853605 arm64_sve-ptrace_Set_Streaming_SVE_VL_5728 pass
12413 10:54:58.853703 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5728 skip
12414 10:54:58.853803 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5728 skip
12415 10:54:58.853886 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5728 skip
12416 10:54:58.853979 arm64_sve-ptrace_Set_Streaming_SVE_VL_5744 pass
12417 10:54:58.854080 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5744 skip
12418 10:54:58.854174 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5744 skip
12419 10:54:58.854465 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5744 skip
12420 10:54:58.854564 arm64_sve-ptrace_Set_Streaming_SVE_VL_5760 pass
12421 10:54:58.854673 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5760 skip
12422 10:54:58.854970 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5760 skip
12423 10:54:58.855063 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5760 skip
12424 10:54:58.855165 arm64_sve-ptrace_Set_Streaming_SVE_VL_5776 pass
12425 10:54:58.855255 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5776 skip
12426 10:54:58.855365 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5776 skip
12427 10:54:58.855470 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5776 skip
12428 10:54:58.855573 arm64_sve-ptrace_Set_Streaming_SVE_VL_5792 pass
12429 10:54:58.855676 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5792 skip
12430 10:54:58.855781 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5792 skip
12431 10:54:58.856081 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5792 skip
12432 10:54:58.863834 arm64_sve-ptrace_Set_Streaming_SVE_VL_5808 pass
12433 10:54:58.864242 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5808 skip
12434 10:54:58.864320 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5808 skip
12435 10:54:58.864400 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5808 skip
12436 10:54:58.864469 arm64_sve-ptrace_Set_Streaming_SVE_VL_5824 pass
12437 10:54:58.864726 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5824 skip
12438 10:54:58.864814 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5824 skip
12439 10:54:58.865074 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5824 skip
12440 10:54:58.865145 arm64_sve-ptrace_Set_Streaming_SVE_VL_5840 pass
12441 10:54:58.865233 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5840 skip
12442 10:54:58.865363 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5840 skip
12443 10:54:58.865677 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5840 skip
12444 10:54:58.880092 arm64_sve-ptrace_Set_Streaming_SVE_VL_5856 pass
12445 10:54:58.880298 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5856 skip
12446 10:54:58.880572 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5856 skip
12447 10:54:58.880675 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5856 skip
12448 10:54:58.880777 arm64_sve-ptrace_Set_Streaming_SVE_VL_5872 pass
12449 10:54:58.880907 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5872 skip
12450 10:54:58.881007 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5872 skip
12451 10:54:58.881126 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5872 skip
12452 10:54:58.881236 arm64_sve-ptrace_Set_Streaming_SVE_VL_5888 pass
12453 10:54:58.881355 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5888 skip
12454 10:54:58.881482 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5888 skip
12455 10:54:58.881602 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5888 skip
12456 10:54:58.881729 arm64_sve-ptrace_Set_Streaming_SVE_VL_5904 pass
12457 10:54:58.881852 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5904 skip
12458 10:54:58.881955 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5904 skip
12459 10:54:58.882244 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5904 skip
12460 10:54:58.882354 arm64_sve-ptrace_Set_Streaming_SVE_VL_5920 pass
12461 10:54:58.882464 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5920 skip
12462 10:54:58.882572 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5920 skip
12463 10:54:58.882687 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5920 skip
12464 10:54:58.882800 arm64_sve-ptrace_Set_Streaming_SVE_VL_5936 pass
12465 10:54:58.883114 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5936 skip
12466 10:54:58.883237 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5936 skip
12467 10:54:58.883344 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5936 skip
12468 10:54:58.887597 arm64_sve-ptrace_Set_Streaming_SVE_VL_5952 pass
12469 10:54:58.887892 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5952 skip
12470 10:54:58.887991 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5952 skip
12471 10:54:58.888085 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5952 skip
12472 10:54:58.888194 arm64_sve-ptrace_Set_Streaming_SVE_VL_5968 pass
12473 10:54:58.888285 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5968 skip
12474 10:54:58.888585 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5968 skip
12475 10:54:58.888686 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5968 skip
12476 10:54:58.888788 arm64_sve-ptrace_Set_Streaming_SVE_VL_5984 pass
12477 10:54:58.888886 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5984 skip
12478 10:54:58.888981 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5984 skip
12479 10:54:58.889273 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5984 skip
12480 10:54:58.889373 arm64_sve-ptrace_Set_Streaming_SVE_VL_6000 pass
12481 10:54:58.889459 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6000 skip
12482 10:54:58.889552 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6000 skip
12483 10:54:58.889820 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6000 skip
12484 10:54:58.889906 arm64_sve-ptrace_Set_Streaming_SVE_VL_6016 pass
12485 10:54:58.890014 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6016 skip
12486 10:54:58.890122 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6016 skip
12487 10:54:58.890205 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6016 skip
12488 10:54:58.890307 arm64_sve-ptrace_Set_Streaming_SVE_VL_6032 pass
12489 10:54:58.890406 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6032 skip
12490 10:54:58.890493 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6032 skip
12491 10:54:58.890576 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6032 skip
12492 10:54:58.890840 arm64_sve-ptrace_Set_Streaming_SVE_VL_6048 pass
12493 10:54:58.890934 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6048 skip
12494 10:54:58.891018 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6048 skip
12495 10:54:58.891103 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6048 skip
12496 10:54:58.891394 arm64_sve-ptrace_Set_Streaming_SVE_VL_6064 pass
12497 10:54:58.891498 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6064 skip
12498 10:54:58.895638 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6064 skip
12499 10:54:58.895938 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6064 skip
12500 10:54:58.896037 arm64_sve-ptrace_Set_Streaming_SVE_VL_6080 pass
12501 10:54:58.896126 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6080 skip
12502 10:54:58.896224 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6080 skip
12503 10:54:58.896500 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6080 skip
12504 10:54:58.896600 arm64_sve-ptrace_Set_Streaming_SVE_VL_6096 pass
12505 10:54:58.896707 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6096 skip
12506 10:54:58.896804 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6096 skip
12507 10:54:58.897096 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6096 skip
12508 10:54:58.897206 arm64_sve-ptrace_Set_Streaming_SVE_VL_6112 pass
12509 10:54:58.897312 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6112 skip
12510 10:54:58.897417 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6112 skip
12511 10:54:58.897777 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6112 skip
12512 10:54:58.898009 arm64_sve-ptrace_Set_Streaming_SVE_VL_6128 pass
12513 10:54:58.898097 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6128 skip
12514 10:54:58.898203 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6128 skip
12515 10:54:58.898323 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6128 skip
12516 10:54:58.898440 arm64_sve-ptrace_Set_Streaming_SVE_VL_6144 pass
12517 10:54:58.898547 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6144 skip
12518 10:54:58.898859 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6144 skip
12519 10:54:58.898968 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6144 skip
12520 10:54:58.899071 arm64_sve-ptrace_Set_Streaming_SVE_VL_6160 pass
12521 10:54:58.899151 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6160 skip
12522 10:54:58.899225 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6160 skip
12523 10:54:58.899528 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6160 skip
12524 10:54:58.903619 arm64_sve-ptrace_Set_Streaming_SVE_VL_6176 pass
12525 10:54:58.904007 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6176 skip
12526 10:54:58.904097 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6176 skip
12527 10:54:58.904204 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6176 skip
12528 10:54:58.904284 arm64_sve-ptrace_Set_Streaming_SVE_VL_6192 pass
12529 10:54:58.904380 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6192 skip
12530 10:54:58.904490 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6192 skip
12531 10:54:58.904809 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6192 skip
12532 10:54:58.904916 arm64_sve-ptrace_Set_Streaming_SVE_VL_6208 pass
12533 10:54:58.905028 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6208 skip
12534 10:54:58.905131 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6208 skip
12535 10:54:58.905231 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6208 skip
12536 10:54:58.905332 arm64_sve-ptrace_Set_Streaming_SVE_VL_6224 pass
12537 10:54:58.905645 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6224 skip
12538 10:54:58.905758 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6224 skip
12539 10:54:58.906073 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6224 skip
12540 10:54:58.906174 arm64_sve-ptrace_Set_Streaming_SVE_VL_6240 pass
12541 10:54:58.906266 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6240 skip
12542 10:54:58.906374 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6240 skip
12543 10:54:58.906466 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6240 skip
12544 10:54:58.906568 arm64_sve-ptrace_Set_Streaming_SVE_VL_6256 pass
12545 10:54:58.906677 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6256 skip
12546 10:54:58.906789 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6256 skip
12547 10:54:58.906901 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6256 skip
12548 10:54:58.907010 arm64_sve-ptrace_Set_Streaming_SVE_VL_6272 pass
12549 10:54:58.907117 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6272 skip
12550 10:54:58.907478 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6272 skip
12551 10:54:58.911641 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6272 skip
12552 10:54:58.912026 arm64_sve-ptrace_Set_Streaming_SVE_VL_6288 pass
12553 10:54:58.912131 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6288 skip
12554 10:54:58.912221 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6288 skip
12555 10:54:58.912308 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6288 skip
12556 10:54:58.912384 arm64_sve-ptrace_Set_Streaming_SVE_VL_6304 pass
12557 10:54:58.912469 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6304 skip
12558 10:54:58.912556 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6304 skip
12559 10:54:58.912661 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6304 skip
12560 10:54:58.912768 arm64_sve-ptrace_Set_Streaming_SVE_VL_6320 pass
12561 10:54:58.912889 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6320 skip
12562 10:54:58.912989 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6320 skip
12563 10:54:58.913288 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6320 skip
12564 10:54:58.913410 arm64_sve-ptrace_Set_Streaming_SVE_VL_6336 pass
12565 10:54:58.913513 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6336 skip
12566 10:54:58.913803 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6336 skip
12567 10:54:58.913907 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6336 skip
12568 10:54:58.914003 arm64_sve-ptrace_Set_Streaming_SVE_VL_6352 pass
12569 10:54:58.914281 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6352 skip
12570 10:54:58.914380 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6352 skip
12571 10:54:58.914659 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6352 skip
12572 10:54:58.914746 arm64_sve-ptrace_Set_Streaming_SVE_VL_6368 pass
12573 10:54:58.914846 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6368 skip
12574 10:54:58.914942 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6368 skip
12575 10:54:58.915220 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6368 skip
12576 10:54:58.915306 arm64_sve-ptrace_Set_Streaming_SVE_VL_6384 pass
12577 10:54:58.915400 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6384 skip
12578 10:54:58.930335 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6384 skip
12579 10:54:58.930769 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6384 skip
12580 10:54:58.930880 arm64_sve-ptrace_Set_Streaming_SVE_VL_6400 pass
12581 10:54:58.930965 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6400 skip
12582 10:54:58.931064 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6400 skip
12583 10:54:58.931149 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6400 skip
12584 10:54:58.931247 arm64_sve-ptrace_Set_Streaming_SVE_VL_6416 pass
12585 10:54:58.931341 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6416 skip
12586 10:54:58.931637 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6416 skip
12587 10:54:58.931753 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6416 skip
12588 10:54:58.932053 arm64_sve-ptrace_Set_Streaming_SVE_VL_6432 pass
12589 10:54:58.932156 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6432 skip
12590 10:54:58.932252 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6432 skip
12591 10:54:58.932346 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6432 skip
12592 10:54:58.932633 arm64_sve-ptrace_Set_Streaming_SVE_VL_6448 pass
12593 10:54:58.932722 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6448 skip
12594 10:54:58.932823 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6448 skip
12595 10:54:58.933181 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6448 skip
12596 10:54:58.933278 arm64_sve-ptrace_Set_Streaming_SVE_VL_6464 pass
12597 10:54:58.933371 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6464 skip
12598 10:54:58.933526 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6464 skip
12599 10:54:58.933678 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6464 skip
12600 10:54:58.933812 arm64_sve-ptrace_Set_Streaming_SVE_VL_6480 pass
12601 10:54:58.934087 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6480 skip
12602 10:54:58.934188 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6480 skip
12603 10:54:58.934279 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6480 skip
12604 10:54:58.934385 arm64_sve-ptrace_Set_Streaming_SVE_VL_6496 pass
12605 10:54:58.934679 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6496 skip
12606 10:54:58.934777 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6496 skip
12607 10:54:58.934906 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6496 skip
12608 10:54:58.935029 arm64_sve-ptrace_Set_Streaming_SVE_VL_6512 pass
12609 10:54:58.935188 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6512 skip
12610 10:54:58.935311 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6512 skip
12611 10:54:58.935430 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6512 skip
12612 10:54:58.939630 arm64_sve-ptrace_Set_Streaming_SVE_VL_6528 pass
12613 10:54:58.940005 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6528 skip
12614 10:54:58.940108 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6528 skip
12615 10:54:58.940204 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6528 skip
12616 10:54:58.940312 arm64_sve-ptrace_Set_Streaming_SVE_VL_6544 pass
12617 10:54:58.940420 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6544 skip
12618 10:54:58.940541 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6544 skip
12619 10:54:58.940626 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6544 skip
12620 10:54:58.940741 arm64_sve-ptrace_Set_Streaming_SVE_VL_6560 pass
12621 10:54:58.940835 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6560 skip
12622 10:54:58.940937 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6560 skip
12623 10:54:58.941224 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6560 skip
12624 10:54:58.941326 arm64_sve-ptrace_Set_Streaming_SVE_VL_6576 pass
12625 10:54:58.941423 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6576 skip
12626 10:54:58.941518 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6576 skip
12627 10:54:58.941806 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6576 skip
12628 10:54:58.941909 arm64_sve-ptrace_Set_Streaming_SVE_VL_6592 pass
12629 10:54:58.942004 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6592 skip
12630 10:54:58.942096 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6592 skip
12631 10:54:58.942402 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6592 skip
12632 10:54:58.942501 arm64_sve-ptrace_Set_Streaming_SVE_VL_6608 pass
12633 10:54:58.942595 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6608 skip
12634 10:54:58.942689 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6608 skip
12635 10:54:58.942785 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6608 skip
12636 10:54:58.943105 arm64_sve-ptrace_Set_Streaming_SVE_VL_6624 pass
12637 10:54:58.943203 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6624 skip
12638 10:54:58.943486 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6624 skip
12639 10:54:58.943584 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6624 skip
12640 10:54:58.947602 arm64_sve-ptrace_Set_Streaming_SVE_VL_6640 pass
12641 10:54:58.947899 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6640 skip
12642 10:54:58.948016 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6640 skip
12643 10:54:58.948113 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6640 skip
12644 10:54:58.948210 arm64_sve-ptrace_Set_Streaming_SVE_VL_6656 pass
12645 10:54:58.948498 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6656 skip
12646 10:54:58.948608 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6656 skip
12647 10:54:58.948708 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6656 skip
12648 10:54:58.948803 arm64_sve-ptrace_Set_Streaming_SVE_VL_6672 pass
12649 10:54:58.949082 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6672 skip
12650 10:54:58.949193 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6672 skip
12651 10:54:58.949476 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6672 skip
12652 10:54:58.949571 arm64_sve-ptrace_Set_Streaming_SVE_VL_6688 pass
12653 10:54:58.949688 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6688 skip
12654 10:54:58.949780 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6688 skip
12655 10:54:58.949891 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6688 skip
12656 10:54:58.950181 arm64_sve-ptrace_Set_Streaming_SVE_VL_6704 pass
12657 10:54:58.950473 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6704 skip
12658 10:54:58.950895 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6704 skip
12659 10:54:58.950982 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6704 skip
12660 10:54:58.951079 arm64_sve-ptrace_Set_Streaming_SVE_VL_6720 pass
12661 10:54:58.951161 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6720 skip
12662 10:54:58.951240 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6720 skip
12663 10:54:58.951338 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6720 skip
12664 10:54:58.951417 arm64_sve-ptrace_Set_Streaming_SVE_VL_6736 pass
12665 10:54:58.951511 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6736 skip
12666 10:54:58.951585 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6736 skip
12667 10:54:58.955648 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6736 skip
12668 10:54:58.956006 arm64_sve-ptrace_Set_Streaming_SVE_VL_6752 pass
12669 10:54:58.956106 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6752 skip
12670 10:54:58.956190 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6752 skip
12671 10:54:58.956283 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6752 skip
12672 10:54:58.956378 arm64_sve-ptrace_Set_Streaming_SVE_VL_6768 pass
12673 10:54:58.956472 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6768 skip
12674 10:54:58.956583 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6768 skip
12675 10:54:58.956907 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6768 skip
12676 10:54:58.957007 arm64_sve-ptrace_Set_Streaming_SVE_VL_6784 pass
12677 10:54:58.957102 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6784 skip
12678 10:54:58.957195 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6784 skip
12679 10:54:58.957451 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6784 skip
12680 10:54:58.957548 arm64_sve-ptrace_Set_Streaming_SVE_VL_6800 pass
12681 10:54:58.957640 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6800 skip
12682 10:54:58.957947 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6800 skip
12683 10:54:58.958027 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6800 skip
12684 10:54:58.958102 arm64_sve-ptrace_Set_Streaming_SVE_VL_6816 pass
12685 10:54:58.958368 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6816 skip
12686 10:54:58.958465 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6816 skip
12687 10:54:58.959069 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6816 skip
12688 10:54:58.959154 arm64_sve-ptrace_Set_Streaming_SVE_VL_6832 pass
12689 10:54:58.959219 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6832 skip
12690 10:54:58.959279 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6832 skip
12691 10:54:58.959533 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6832 skip
12692 10:54:58.959612 arm64_sve-ptrace_Set_Streaming_SVE_VL_6848 pass
12693 10:54:58.959673 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6848 skip
12694 10:54:58.959741 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6848 skip
12695 10:54:58.963690 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6848 skip
12696 10:54:58.964005 arm64_sve-ptrace_Set_Streaming_SVE_VL_6864 pass
12697 10:54:58.964104 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6864 skip
12698 10:54:58.964194 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6864 skip
12699 10:54:58.968241 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6864 skip
12700 10:54:58.968401 arm64_sve-ptrace_Set_Streaming_SVE_VL_6880 pass
12701 10:54:58.968518 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6880 skip
12702 10:54:58.968629 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6880 skip
12703 10:54:58.968751 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6880 skip
12704 10:54:58.968876 arm64_sve-ptrace_Set_Streaming_SVE_VL_6896 pass
12705 10:54:58.968972 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6896 skip
12706 10:54:58.969057 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6896 skip
12707 10:54:58.969142 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6896 skip
12708 10:54:58.969226 arm64_sve-ptrace_Set_Streaming_SVE_VL_6912 pass
12709 10:54:58.969310 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6912 skip
12710 10:54:58.969393 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6912 skip
12711 10:54:58.969475 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6912 skip
12712 10:54:58.990962 arm64_sve-ptrace_Set_Streaming_SVE_VL_6928 pass
12713 10:54:58.991205 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6928 skip
12714 10:54:58.991551 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6928 skip
12715 10:54:58.991634 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6928 skip
12716 10:54:58.991719 arm64_sve-ptrace_Set_Streaming_SVE_VL_6944 pass
12717 10:54:58.991787 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6944 skip
12718 10:54:58.992056 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6944 skip
12719 10:54:58.992377 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6944 skip
12720 10:54:58.992479 arm64_sve-ptrace_Set_Streaming_SVE_VL_6960 pass
12721 10:54:58.992565 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6960 skip
12722 10:54:58.992665 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6960 skip
12723 10:54:58.992750 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6960 skip
12724 10:54:58.992860 arm64_sve-ptrace_Set_Streaming_SVE_VL_6976 pass
12725 10:54:58.992970 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6976 skip
12726 10:54:58.993077 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6976 skip
12727 10:54:58.993170 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6976 skip
12728 10:54:58.993288 arm64_sve-ptrace_Set_Streaming_SVE_VL_6992 pass
12729 10:54:58.993383 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6992 skip
12730 10:54:58.993494 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6992 skip
12731 10:54:58.993598 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6992 skip
12732 10:54:58.993699 arm64_sve-ptrace_Set_Streaming_SVE_VL_7008 pass
12733 10:54:58.993769 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7008 skip
12734 10:54:58.993903 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7008 skip
12735 10:54:58.994010 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7008 skip
12736 10:54:58.994110 arm64_sve-ptrace_Set_Streaming_SVE_VL_7024 pass
12737 10:54:58.994214 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7024 skip
12738 10:54:58.994325 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7024 skip
12739 10:54:58.994435 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7024 skip
12740 10:54:58.994519 arm64_sve-ptrace_Set_Streaming_SVE_VL_7040 pass
12741 10:54:58.994623 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7040 skip
12742 10:54:58.994740 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7040 skip
12743 10:54:58.994827 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7040 skip
12744 10:54:58.994951 arm64_sve-ptrace_Set_Streaming_SVE_VL_7056 pass
12745 10:54:58.995049 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7056 skip
12746 10:54:58.995161 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7056 skip
12747 10:54:58.995261 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7056 skip
12748 10:54:58.995371 arm64_sve-ptrace_Set_Streaming_SVE_VL_7072 pass
12749 10:54:58.999812 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7072 skip
12750 10:54:59.000006 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7072 skip
12751 10:54:59.000289 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7072 skip
12752 10:54:59.000382 arm64_sve-ptrace_Set_Streaming_SVE_VL_7088 pass
12753 10:54:59.000475 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7088 skip
12754 10:54:59.000549 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7088 skip
12755 10:54:59.003486 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7088 skip
12756 10:54:59.003578 arm64_sve-ptrace_Set_Streaming_SVE_VL_7104 pass
12757 10:54:59.003647 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7104 skip
12758 10:54:59.003707 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7104 skip
12759 10:54:59.003767 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7104 skip
12760 10:54:59.003826 arm64_sve-ptrace_Set_Streaming_SVE_VL_7120 pass
12761 10:54:59.003885 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7120 skip
12762 10:54:59.003944 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7120 skip
12763 10:54:59.004009 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7120 skip
12764 10:54:59.004069 arm64_sve-ptrace_Set_Streaming_SVE_VL_7136 pass
12765 10:54:59.004128 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7136 skip
12766 10:54:59.004187 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7136 skip
12767 10:54:59.004246 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7136 skip
12768 10:54:59.004304 arm64_sve-ptrace_Set_Streaming_SVE_VL_7152 pass
12769 10:54:59.004363 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7152 skip
12770 10:54:59.004422 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7152 skip
12771 10:54:59.004480 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7152 skip
12772 10:54:59.004540 arm64_sve-ptrace_Set_Streaming_SVE_VL_7168 pass
12773 10:54:59.004599 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7168 skip
12774 10:54:59.004658 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7168 skip
12775 10:54:59.004717 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7168 skip
12776 10:54:59.004775 arm64_sve-ptrace_Set_Streaming_SVE_VL_7184 pass
12777 10:54:59.004833 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7184 skip
12778 10:54:59.004891 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7184 skip
12779 10:54:59.004951 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7184 skip
12780 10:54:59.007715 arm64_sve-ptrace_Set_Streaming_SVE_VL_7200 pass
12781 10:54:59.008043 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7200 skip
12782 10:54:59.008137 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7200 skip
12783 10:54:59.008228 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7200 skip
12784 10:54:59.008340 arm64_sve-ptrace_Set_Streaming_SVE_VL_7216 pass
12785 10:54:59.008443 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7216 skip
12786 10:54:59.008546 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7216 skip
12787 10:54:59.008846 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7216 skip
12788 10:54:59.008948 arm64_sve-ptrace_Set_Streaming_SVE_VL_7232 pass
12789 10:54:59.009053 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7232 skip
12790 10:54:59.009145 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7232 skip
12791 10:54:59.009237 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7232 skip
12792 10:54:59.009326 arm64_sve-ptrace_Set_Streaming_SVE_VL_7248 pass
12793 10:54:59.009434 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7248 skip
12794 10:54:59.009756 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7248 skip
12795 10:54:59.009866 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7248 skip
12796 10:54:59.009993 arm64_sve-ptrace_Set_Streaming_SVE_VL_7264 pass
12797 10:54:59.010111 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7264 skip
12798 10:54:59.010215 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7264 skip
12799 10:54:59.010344 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7264 skip
12800 10:54:59.010467 arm64_sve-ptrace_Set_Streaming_SVE_VL_7280 pass
12801 10:54:59.010585 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7280 skip
12802 10:54:59.010698 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7280 skip
12803 10:54:59.011007 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7280 skip
12804 10:54:59.011113 arm64_sve-ptrace_Set_Streaming_SVE_VL_7296 pass
12805 10:54:59.011217 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7296 skip
12806 10:54:59.011306 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7296 skip
12807 10:54:59.011407 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7296 skip
12808 10:54:59.015646 arm64_sve-ptrace_Set_Streaming_SVE_VL_7312 pass
12809 10:54:59.016032 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7312 skip
12810 10:54:59.016138 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7312 skip
12811 10:54:59.016251 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7312 skip
12812 10:54:59.016335 arm64_sve-ptrace_Set_Streaming_SVE_VL_7328 pass
12813 10:54:59.016434 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7328 skip
12814 10:54:59.016530 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7328 skip
12815 10:54:59.016644 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7328 skip
12816 10:54:59.016776 arm64_sve-ptrace_Set_Streaming_SVE_VL_7344 pass
12817 10:54:59.017075 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7344 skip
12818 10:54:59.017175 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7344 skip
12819 10:54:59.017271 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7344 skip
12820 10:54:59.017365 arm64_sve-ptrace_Set_Streaming_SVE_VL_7360 pass
12821 10:54:59.017459 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7360 skip
12822 10:54:59.017777 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7360 skip
12823 10:54:59.017877 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7360 skip
12824 10:54:59.017971 arm64_sve-ptrace_Set_Streaming_SVE_VL_7376 pass
12825 10:54:59.018065 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7376 skip
12826 10:54:59.018156 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7376 skip
12827 10:54:59.018445 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7376 skip
12828 10:54:59.018544 arm64_sve-ptrace_Set_Streaming_SVE_VL_7392 pass
12829 10:54:59.018636 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7392 skip
12830 10:54:59.018729 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7392 skip
12831 10:54:59.019062 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7392 skip
12832 10:54:59.019162 arm64_sve-ptrace_Set_Streaming_SVE_VL_7408 pass
12833 10:54:59.019255 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7408 skip
12834 10:54:59.019348 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7408 skip
12835 10:54:59.023633 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7408 skip
12836 10:54:59.023993 arm64_sve-ptrace_Set_Streaming_SVE_VL_7424 pass
12837 10:54:59.024096 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7424 skip
12838 10:54:59.024177 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7424 skip
12839 10:54:59.024269 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7424 skip
12840 10:54:59.024350 arm64_sve-ptrace_Set_Streaming_SVE_VL_7440 pass
12841 10:54:59.024442 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7440 skip
12842 10:54:59.024535 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7440 skip
12843 10:54:59.024628 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7440 skip
12844 10:54:59.024721 arm64_sve-ptrace_Set_Streaming_SVE_VL_7456 pass
12845 10:54:59.025026 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7456 skip
12846 10:54:59.041589 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7456 skip
12847 10:54:59.042059 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7456 skip
12848 10:54:59.042165 arm64_sve-ptrace_Set_Streaming_SVE_VL_7472 pass
12849 10:54:59.042255 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7472 skip
12850 10:54:59.042336 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7472 skip
12851 10:54:59.042435 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7472 skip
12852 10:54:59.042521 arm64_sve-ptrace_Set_Streaming_SVE_VL_7488 pass
12853 10:54:59.042617 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7488 skip
12854 10:54:59.042715 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7488 skip
12855 10:54:59.042810 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7488 skip
12856 10:54:59.042917 arm64_sve-ptrace_Set_Streaming_SVE_VL_7504 pass
12857 10:54:59.043208 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7504 skip
12858 10:54:59.043298 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7504 skip
12859 10:54:59.043393 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7504 skip
12860 10:54:59.043661 arm64_sve-ptrace_Set_Streaming_SVE_VL_7520 pass
12861 10:54:59.043941 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7520 skip
12862 10:54:59.044046 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7520 skip
12863 10:54:59.044147 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7520 skip
12864 10:54:59.044251 arm64_sve-ptrace_Set_Streaming_SVE_VL_7536 pass
12865 10:54:59.044545 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7536 skip
12866 10:54:59.044644 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7536 skip
12867 10:54:59.044737 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7536 skip
12868 10:54:59.044831 arm64_sve-ptrace_Set_Streaming_SVE_VL_7552 pass
12869 10:54:59.045131 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7552 skip
12870 10:54:59.045241 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7552 skip
12871 10:54:59.045541 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7552 skip
12872 10:54:59.045658 arm64_sve-ptrace_Set_Streaming_SVE_VL_7568 pass
12873 10:54:59.045767 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7568 skip
12874 10:54:59.046070 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7568 skip
12875 10:54:59.046187 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7568 skip
12876 10:54:59.046273 arm64_sve-ptrace_Set_Streaming_SVE_VL_7584 pass
12877 10:54:59.046367 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7584 skip
12878 10:54:59.046462 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7584 skip
12879 10:54:59.046758 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7584 skip
12880 10:54:59.046861 arm64_sve-ptrace_Set_Streaming_SVE_VL_7600 pass
12881 10:54:59.046956 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7600 skip
12882 10:54:59.047245 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7600 skip
12883 10:54:59.047347 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7600 skip
12884 10:54:59.047444 arm64_sve-ptrace_Set_Streaming_SVE_VL_7616 pass
12885 10:54:59.047527 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7616 skip
12886 10:54:59.051807 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7616 skip
12887 10:54:59.051955 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7616 skip
12888 10:54:59.052102 arm64_sve-ptrace_Set_Streaming_SVE_VL_7632 pass
12889 10:54:59.052380 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7632 skip
12890 10:54:59.052511 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7632 skip
12891 10:54:59.052603 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7632 skip
12892 10:54:59.052706 arm64_sve-ptrace_Set_Streaming_SVE_VL_7648 pass
12893 10:54:59.052794 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7648 skip
12894 10:54:59.052896 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7648 skip
12895 10:54:59.052996 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7648 skip
12896 10:54:59.053102 arm64_sve-ptrace_Set_Streaming_SVE_VL_7664 pass
12897 10:54:59.053213 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7664 skip
12898 10:54:59.053521 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7664 skip
12899 10:54:59.053643 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7664 skip
12900 10:54:59.053759 arm64_sve-ptrace_Set_Streaming_SVE_VL_7680 pass
12901 10:54:59.054061 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7680 skip
12902 10:54:59.054172 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7680 skip
12903 10:54:59.054289 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7680 skip
12904 10:54:59.054381 arm64_sve-ptrace_Set_Streaming_SVE_VL_7696 pass
12905 10:54:59.054481 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7696 skip
12906 10:54:59.054583 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7696 skip
12907 10:54:59.054692 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7696 skip
12908 10:54:59.054793 arm64_sve-ptrace_Set_Streaming_SVE_VL_7712 pass
12909 10:54:59.055081 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7712 skip
12910 10:54:59.055364 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7712 skip
12911 10:54:59.055451 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7712 skip
12912 10:54:59.055528 arm64_sve-ptrace_Set_Streaming_SVE_VL_7728 pass
12913 10:54:59.059847 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7728 skip
12914 10:54:59.060181 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7728 skip
12915 10:54:59.060278 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7728 skip
12916 10:54:59.060358 arm64_sve-ptrace_Set_Streaming_SVE_VL_7744 pass
12917 10:54:59.060432 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7744 skip
12918 10:54:59.060681 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7744 skip
12919 10:54:59.060760 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7744 skip
12920 10:54:59.060849 arm64_sve-ptrace_Set_Streaming_SVE_VL_7760 pass
12921 10:54:59.060930 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7760 skip
12922 10:54:59.061179 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7760 skip
12923 10:54:59.061439 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7760 skip
12924 10:54:59.061510 arm64_sve-ptrace_Set_Streaming_SVE_VL_7776 pass
12925 10:54:59.061582 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7776 skip
12926 10:54:59.061679 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7776 skip
12927 10:54:59.061941 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7776 skip
12928 10:54:59.062037 arm64_sve-ptrace_Set_Streaming_SVE_VL_7792 pass
12929 10:54:59.062213 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7792 skip
12930 10:54:59.062418 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7792 skip
12931 10:54:59.062618 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7792 skip
12932 10:54:59.062821 arm64_sve-ptrace_Set_Streaming_SVE_VL_7808 pass
12933 10:54:59.063170 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7808 skip
12934 10:54:59.063275 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7808 skip
12935 10:54:59.063383 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7808 skip
12936 10:54:59.063471 arm64_sve-ptrace_Set_Streaming_SVE_VL_7824 pass
12937 10:54:59.063566 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7824 skip
12938 10:54:59.067684 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7824 skip
12939 10:54:59.068007 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7824 skip
12940 10:54:59.068110 arm64_sve-ptrace_Set_Streaming_SVE_VL_7840 pass
12941 10:54:59.068194 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7840 skip
12942 10:54:59.068516 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7840 skip
12943 10:54:59.068710 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7840 skip
12944 10:54:59.068888 arm64_sve-ptrace_Set_Streaming_SVE_VL_7856 pass
12945 10:54:59.069102 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7856 skip
12946 10:54:59.069274 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7856 skip
12947 10:54:59.069431 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7856 skip
12948 10:54:59.069586 arm64_sve-ptrace_Set_Streaming_SVE_VL_7872 pass
12949 10:54:59.069794 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7872 skip
12950 10:54:59.069962 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7872 skip
12951 10:54:59.070122 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7872 skip
12952 10:54:59.070288 arm64_sve-ptrace_Set_Streaming_SVE_VL_7888 pass
12953 10:54:59.070480 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7888 skip
12954 10:54:59.070643 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7888 skip
12955 10:54:59.070815 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7888 skip
12956 10:54:59.070986 arm64_sve-ptrace_Set_Streaming_SVE_VL_7904 pass
12957 10:54:59.071158 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7904 skip
12958 10:54:59.071321 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7904 skip
12959 10:54:59.071450 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7904 skip
12960 10:54:59.071596 arm64_sve-ptrace_Set_Streaming_SVE_VL_7920 pass
12961 10:54:59.071715 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7920 skip
12962 10:54:59.071829 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7920 skip
12963 10:54:59.071942 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7920 skip
12964 10:54:59.072053 arm64_sve-ptrace_Set_Streaming_SVE_VL_7936 pass
12965 10:54:59.072165 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7936 skip
12966 10:54:59.072277 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7936 skip
12967 10:54:59.072388 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7936 skip
12968 10:54:59.075730 arm64_sve-ptrace_Set_Streaming_SVE_VL_7952 pass
12969 10:54:59.076027 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7952 skip
12970 10:54:59.076121 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7952 skip
12971 10:54:59.076197 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7952 skip
12972 10:54:59.076282 arm64_sve-ptrace_Set_Streaming_SVE_VL_7968 pass
12973 10:54:59.076356 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7968 skip
12974 10:54:59.076428 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7968 skip
12975 10:54:59.076512 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7968 skip
12976 10:54:59.076585 arm64_sve-ptrace_Set_Streaming_SVE_VL_7984 pass
12977 10:54:59.076669 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7984 skip
12978 10:54:59.076898 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7984 skip
12979 10:54:59.077023 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7984 skip
12980 10:54:59.096773 arm64_sve-ptrace_Set_Streaming_SVE_VL_8000 pass
12981 10:54:59.097023 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8000 skip
12982 10:54:59.097330 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8000 skip
12983 10:54:59.097440 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8000 skip
12984 10:54:59.097520 arm64_sve-ptrace_Set_Streaming_SVE_VL_8016 pass
12985 10:54:59.097592 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8016 skip
12986 10:54:59.097680 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8016 skip
12987 10:54:59.097754 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8016 skip
12988 10:54:59.097836 arm64_sve-ptrace_Set_Streaming_SVE_VL_8032 pass
12989 10:54:59.097905 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8032 skip
12990 10:54:59.097985 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8032 skip
12991 10:54:59.098064 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8032 skip
12992 10:54:59.098346 arm64_sve-ptrace_Set_Streaming_SVE_VL_8048 pass
12993 10:54:59.098444 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8048 skip
12994 10:54:59.098771 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8048 skip
12995 10:54:59.098982 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8048 skip
12996 10:54:59.099196 arm64_sve-ptrace_Set_Streaming_SVE_VL_8064 pass
12997 10:54:59.099381 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8064 skip
12998 10:54:59.099561 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8064 skip
12999 10:54:59.099689 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8064 skip
13000 10:54:59.099806 arm64_sve-ptrace_Set_Streaming_SVE_VL_8080 pass
13001 10:54:59.099919 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8080 skip
13002 10:54:59.100034 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8080 skip
13003 10:54:59.103646 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8080 skip
13004 10:54:59.103968 arm64_sve-ptrace_Set_Streaming_SVE_VL_8096 pass
13005 10:54:59.104092 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8096 skip
13006 10:54:59.104195 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8096 skip
13007 10:54:59.104296 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8096 skip
13008 10:54:59.104400 arm64_sve-ptrace_Set_Streaming_SVE_VL_8112 pass
13009 10:54:59.104511 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8112 skip
13010 10:54:59.104610 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8112 skip
13011 10:54:59.104874 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8112 skip
13012 10:54:59.104990 arm64_sve-ptrace_Set_Streaming_SVE_VL_8128 pass
13013 10:54:59.105084 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8128 skip
13014 10:54:59.105401 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8128 skip
13015 10:54:59.105517 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8128 skip
13016 10:54:59.105622 arm64_sve-ptrace_Set_Streaming_SVE_VL_8144 pass
13017 10:54:59.105732 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8144 skip
13018 10:54:59.106019 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8144 skip
13019 10:54:59.106127 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8144 skip
13020 10:54:59.106255 arm64_sve-ptrace_Set_Streaming_SVE_VL_8160 pass
13021 10:54:59.106553 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8160 skip
13022 10:54:59.106649 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8160 skip
13023 10:54:59.106774 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8160 skip
13024 10:54:59.106875 arm64_sve-ptrace_Set_Streaming_SVE_VL_8176 pass
13025 10:54:59.106981 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8176 skip
13026 10:54:59.107102 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8176 skip
13027 10:54:59.107224 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8176 skip
13028 10:54:59.107372 arm64_sve-ptrace_Set_Streaming_SVE_VL_8192 pass
13029 10:54:59.107665 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8192 skip
13030 10:54:59.111784 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8192 skip
13031 10:54:59.111882 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8192 skip
13032 10:54:59.112158 arm64_sve-ptrace pass
13033 10:54:59.112263 arm64_sve-probe-vls_Enumerated_16_vector_lengths pass
13034 10:54:59.112342 arm64_sve-probe-vls_All_vector_lengths_valid pass
13035 10:54:59.112419 arm64_sve-probe-vls pass
13036 10:54:59.112538 arm64_vec-syscfg_SVE_default_vector_length_64 pass
13037 10:54:59.112628 arm64_vec-syscfg_SVE_minimum_vector_length_16 pass
13038 10:54:59.112702 arm64_vec-syscfg_SVE_maximum_vector_length_256 pass
13039 10:54:59.112781 arm64_vec-syscfg_SVE_current_VL_is_64 pass
13040 10:54:59.112894 arm64_vec-syscfg_SVE_set_VL_64_and_have_VL_64 pass
13041 10:54:59.113008 arm64_vec-syscfg_SVE_prctl_set_min_max pass
13042 10:54:59.113102 arm64_vec-syscfg_SVE_vector_length_used_default pass
13043 10:54:59.113200 arm64_vec-syscfg_SVE_vector_length_was_inherited pass
13044 10:54:59.113313 arm64_vec-syscfg_SVE_vector_length_set_on_exec pass
13045 10:54:59.113427 arm64_vec-syscfg_SVE_prctl_set_all_VLs_0_errors pass
13046 10:54:59.113537 arm64_vec-syscfg_SME_default_vector_length_32 pass
13047 10:54:59.113644 arm64_vec-syscfg_SME_minimum_vector_length_16 pass
13048 10:54:59.113778 arm64_vec-syscfg_SME_maximum_vector_length_256 pass
13049 10:54:59.113902 arm64_vec-syscfg_SME_current_VL_is_32 pass
13050 10:54:59.114183 arm64_vec-syscfg_SME_set_VL_32_and_have_VL_32 pass
13051 10:54:59.114272 arm64_vec-syscfg_SME_prctl_set_min_max pass
13052 10:54:59.114378 arm64_vec-syscfg_SME_vector_length_used_default pass
13053 10:54:59.114477 arm64_vec-syscfg_SME_vector_length_was_inherited pass
13054 10:54:59.114595 arm64_vec-syscfg_SME_vector_length_set_on_exec pass
13055 10:54:59.114685 arm64_vec-syscfg_SME_prctl_set_all_VLs_0_errors pass
13056 10:54:59.114778 arm64_vec-syscfg pass
13057 10:54:59.114886 arm64_za-fork_fork_test pass
13058 10:54:59.114990 arm64_za-fork pass
13059 10:54:59.115091 arm64_za-ptrace_Set_VL_16 pass
13060 10:54:59.115178 arm64_za-ptrace_Disabled_ZA_for_VL_16 pass
13061 10:54:59.115263 arm64_za-ptrace_Data_match_for_VL_16 pass
13062 10:54:59.115340 arm64_za-ptrace_Set_VL_32 pass
13063 10:54:59.115436 arm64_za-ptrace_Disabled_ZA_for_VL_32 pass
13064 10:54:59.115504 arm64_za-ptrace_Data_match_for_VL_32 pass
13065 10:54:59.115567 arm64_za-ptrace_Set_VL_48 pass
13066 10:54:59.115631 arm64_za-ptrace_Disabled_ZA_for_VL_48 skip
13067 10:54:59.115709 arm64_za-ptrace_Get_and_set_data_for_VL_48 skip
13068 10:54:59.115783 arm64_za-ptrace_Set_VL_64 pass
13069 10:54:59.115867 arm64_za-ptrace_Disabled_ZA_for_VL_64 pass
13070 10:54:59.115938 arm64_za-ptrace_Data_match_for_VL_64 pass
13071 10:54:59.116055 arm64_za-ptrace_Set_VL_80 pass
13072 10:54:59.116155 arm64_za-ptrace_Disabled_ZA_for_VL_80 skip
13073 10:54:59.116281 arm64_za-ptrace_Get_and_set_data_for_VL_80 skip
13074 10:54:59.116379 arm64_za-ptrace_Set_VL_96 pass
13075 10:54:59.116483 arm64_za-ptrace_Disabled_ZA_for_VL_96 skip
13076 10:54:59.116598 arm64_za-ptrace_Get_and_set_data_for_VL_96 skip
13077 10:54:59.116687 arm64_za-ptrace_Set_VL_112 pass
13078 10:54:59.116786 arm64_za-ptrace_Disabled_ZA_for_VL_112 skip
13079 10:54:59.116891 arm64_za-ptrace_Get_and_set_data_for_VL_112 skip
13080 10:54:59.116968 arm64_za-ptrace_Set_VL_128 pass
13081 10:54:59.117071 arm64_za-ptrace_Disabled_ZA_for_VL_128 pass
13082 10:54:59.117165 arm64_za-ptrace_Data_match_for_VL_128 pass
13083 10:54:59.117288 arm64_za-ptrace_Set_VL_144 pass
13084 10:54:59.117382 arm64_za-ptrace_Disabled_ZA_for_VL_144 skip
13085 10:54:59.117477 arm64_za-ptrace_Get_and_set_data_for_VL_144 skip
13086 10:54:59.117558 arm64_za-ptrace_Set_VL_160 pass
13087 10:54:59.117674 arm64_za-ptrace_Disabled_ZA_for_VL_160 skip
13088 10:54:59.117754 arm64_za-ptrace_Get_and_set_data_for_VL_160 skip
13089 10:54:59.117849 arm64_za-ptrace_Set_VL_176 pass
13090 10:54:59.117922 arm64_za-ptrace_Disabled_ZA_for_VL_176 skip
13091 10:54:59.117988 arm64_za-ptrace_Get_and_set_data_for_VL_176 skip
13092 10:54:59.118062 arm64_za-ptrace_Set_VL_192 pass
13093 10:54:59.118139 arm64_za-ptrace_Disabled_ZA_for_VL_192 skip
13094 10:54:59.118204 arm64_za-ptrace_Get_and_set_data_for_VL_192 skip
13095 10:54:59.118279 arm64_za-ptrace_Set_VL_208 pass
13096 10:54:59.118352 arm64_za-ptrace_Disabled_ZA_for_VL_208 skip
13097 10:54:59.118626 arm64_za-ptrace_Get_and_set_data_for_VL_208 skip
13098 10:54:59.118712 arm64_za-ptrace_Set_VL_224 pass
13099 10:54:59.123610 arm64_za-ptrace_Disabled_ZA_for_VL_224 skip
13100 10:54:59.123923 arm64_za-ptrace_Get_and_set_data_for_VL_224 skip
13101 10:54:59.124056 arm64_za-ptrace_Set_VL_240 pass
13102 10:54:59.124191 arm64_za-ptrace_Disabled_ZA_for_VL_240 skip
13103 10:54:59.124316 arm64_za-ptrace_Get_and_set_data_for_VL_240 skip
13104 10:54:59.124403 arm64_za-ptrace_Set_VL_256 pass
13105 10:54:59.124477 arm64_za-ptrace_Disabled_ZA_for_VL_256 pass
13106 10:54:59.124550 arm64_za-ptrace_Data_match_for_VL_256 pass
13107 10:54:59.124635 arm64_za-ptrace_Set_VL_272 pass
13108 10:54:59.124710 arm64_za-ptrace_Disabled_ZA_for_VL_272 skip
13109 10:54:59.124789 arm64_za-ptrace_Get_and_set_data_for_VL_272 skip
13110 10:54:59.124856 arm64_za-ptrace_Set_VL_288 pass
13111 10:54:59.124930 arm64_za-ptrace_Disabled_ZA_for_VL_288 skip
13112 10:54:59.125006 arm64_za-ptrace_Get_and_set_data_for_VL_288 skip
13113 10:54:59.125121 arm64_za-ptrace_Set_VL_304 pass
13114 10:54:59.125224 arm64_za-ptrace_Disabled_ZA_for_VL_304 skip
13115 10:54:59.125342 arm64_za-ptrace_Get_and_set_data_for_VL_304 skip
13116 10:54:59.125446 arm64_za-ptrace_Set_VL_320 pass
13117 10:54:59.125551 arm64_za-ptrace_Disabled_ZA_for_VL_320 skip
13118 10:54:59.125677 arm64_za-ptrace_Get_and_set_data_for_VL_320 skip
13119 10:54:59.125781 arm64_za-ptrace_Set_VL_336 pass
13120 10:54:59.125888 arm64_za-ptrace_Disabled_ZA_for_VL_336 skip
13121 10:54:59.125978 arm64_za-ptrace_Get_and_set_data_for_VL_336 skip
13122 10:54:59.126069 arm64_za-ptrace_Set_VL_352 pass
13123 10:54:59.126153 arm64_za-ptrace_Disabled_ZA_for_VL_352 skip
13124 10:54:59.126264 arm64_za-ptrace_Get_and_set_data_for_VL_352 skip
13125 10:54:59.126352 arm64_za-ptrace_Set_VL_368 pass
13126 10:54:59.126477 arm64_za-ptrace_Disabled_ZA_for_VL_368 skip
13127 10:54:59.126582 arm64_za-ptrace_Get_and_set_data_for_VL_368 skip
13128 10:54:59.126689 arm64_za-ptrace_Set_VL_384 pass
13129 10:54:59.126799 arm64_za-ptrace_Disabled_ZA_for_VL_384 skip
13130 10:54:59.126915 arm64_za-ptrace_Get_and_set_data_for_VL_384 skip
13131 10:54:59.127011 arm64_za-ptrace_Set_VL_400 pass
13132 10:54:59.127107 arm64_za-ptrace_Disabled_ZA_for_VL_400 skip
13133 10:54:59.127203 arm64_za-ptrace_Get_and_set_data_for_VL_400 skip
13134 10:54:59.127328 arm64_za-ptrace_Set_VL_416 pass
13135 10:54:59.127437 arm64_za-ptrace_Disabled_ZA_for_VL_416 skip
13136 10:54:59.127522 arm64_za-ptrace_Get_and_set_data_for_VL_416 skip
13137 10:54:59.127594 arm64_za-ptrace_Set_VL_432 pass
13138 10:54:59.127668 arm64_za-ptrace_Disabled_ZA_for_VL_432 skip
13139 10:54:59.127734 arm64_za-ptrace_Get_and_set_data_for_VL_432 skip
13140 10:54:59.131898 arm64_za-ptrace_Set_VL_448 pass
13141 10:54:59.132104 arm64_za-ptrace_Disabled_ZA_for_VL_448 skip
13142 10:54:59.132316 arm64_za-ptrace_Get_and_set_data_for_VL_448 skip
13143 10:54:59.132506 arm64_za-ptrace_Set_VL_464 pass
13144 10:54:59.132666 arm64_za-ptrace_Disabled_ZA_for_VL_464 skip
13145 10:54:59.132802 arm64_za-ptrace_Get_and_set_data_for_VL_464 skip
13146 10:54:59.132923 arm64_za-ptrace_Set_VL_480 pass
13147 10:54:59.133068 arm64_za-ptrace_Disabled_ZA_for_VL_480 skip
13148 10:54:59.133199 arm64_za-ptrace_Get_and_set_data_for_VL_480 skip
13149 10:54:59.133320 arm64_za-ptrace_Set_VL_496 pass
13150 10:54:59.133438 arm64_za-ptrace_Disabled_ZA_for_VL_496 skip
13151 10:54:59.153747 arm64_za-ptrace_Get_and_set_data_for_VL_496 skip
13152 10:54:59.153942 arm64_za-ptrace_Set_VL_512 pass
13153 10:54:59.154084 arm64_za-ptrace_Disabled_ZA_for_VL_512 skip
13154 10:54:59.154447 arm64_za-ptrace_Get_and_set_data_for_VL_512 skip
13155 10:54:59.154616 arm64_za-ptrace_Set_VL_528 pass
13156 10:54:59.154781 arm64_za-ptrace_Disabled_ZA_for_VL_528 skip
13157 10:54:59.154920 arm64_za-ptrace_Get_and_set_data_for_VL_528 skip
13158 10:54:59.155049 arm64_za-ptrace_Set_VL_544 pass
13159 10:54:59.155171 arm64_za-ptrace_Disabled_ZA_for_VL_544 skip
13160 10:54:59.155301 arm64_za-ptrace_Get_and_set_data_for_VL_544 skip
13161 10:54:59.155542 arm64_za-ptrace_Set_VL_560 pass
13162 10:54:59.155699 arm64_za-ptrace_Disabled_ZA_for_VL_560 skip
13163 10:54:59.155866 arm64_za-ptrace_Get_and_set_data_for_VL_560 skip
13164 10:54:59.156015 arm64_za-ptrace_Set_VL_576 pass
13165 10:54:59.156170 arm64_za-ptrace_Disabled_ZA_for_VL_576 skip
13166 10:54:59.156342 arm64_za-ptrace_Get_and_set_data_for_VL_576 skip
13167 10:54:59.156511 arm64_za-ptrace_Set_VL_592 pass
13168 10:54:59.156726 arm64_za-ptrace_Disabled_ZA_for_VL_592 skip
13169 10:54:59.156905 arm64_za-ptrace_Get_and_set_data_for_VL_592 skip
13170 10:54:59.157074 arm64_za-ptrace_Set_VL_608 pass
13171 10:54:59.157238 arm64_za-ptrace_Disabled_ZA_for_VL_608 skip
13172 10:54:59.157410 arm64_za-ptrace_Get_and_set_data_for_VL_608 skip
13173 10:54:59.157616 arm64_za-ptrace_Set_VL_624 pass
13174 10:54:59.157807 arm64_za-ptrace_Disabled_ZA_for_VL_624 skip
13175 10:54:59.157978 arm64_za-ptrace_Get_and_set_data_for_VL_624 skip
13176 10:54:59.158143 arm64_za-ptrace_Set_VL_640 pass
13177 10:54:59.158322 arm64_za-ptrace_Disabled_ZA_for_VL_640 skip
13178 10:54:59.158529 arm64_za-ptrace_Get_and_set_data_for_VL_640 skip
13179 10:54:59.158733 arm64_za-ptrace_Set_VL_656 pass
13180 10:54:59.158904 arm64_za-ptrace_Disabled_ZA_for_VL_656 skip
13181 10:54:59.159056 arm64_za-ptrace_Get_and_set_data_for_VL_656 skip
13182 10:54:59.159224 arm64_za-ptrace_Set_VL_672 pass
13183 10:54:59.159397 arm64_za-ptrace_Disabled_ZA_for_VL_672 skip
13184 10:54:59.159556 arm64_za-ptrace_Get_and_set_data_for_VL_672 skip
13185 10:54:59.159679 arm64_za-ptrace_Set_VL_688 pass
13186 10:54:59.159796 arm64_za-ptrace_Disabled_ZA_for_VL_688 skip
13187 10:54:59.159913 arm64_za-ptrace_Get_and_set_data_for_VL_688 skip
13188 10:54:59.160028 arm64_za-ptrace_Set_VL_704 pass
13189 10:54:59.160144 arm64_za-ptrace_Disabled_ZA_for_VL_704 skip
13190 10:54:59.160259 arm64_za-ptrace_Get_and_set_data_for_VL_704 skip
13191 10:54:59.160376 arm64_za-ptrace_Set_VL_720 pass
13192 10:54:59.160492 arm64_za-ptrace_Disabled_ZA_for_VL_720 skip
13193 10:54:59.160638 arm64_za-ptrace_Get_and_set_data_for_VL_720 skip
13194 10:54:59.160760 arm64_za-ptrace_Set_VL_736 pass
13195 10:54:59.160878 arm64_za-ptrace_Disabled_ZA_for_VL_736 skip
13196 10:54:59.160994 arm64_za-ptrace_Get_and_set_data_for_VL_736 skip
13197 10:54:59.161110 arm64_za-ptrace_Set_VL_752 pass
13198 10:54:59.161225 arm64_za-ptrace_Disabled_ZA_for_VL_752 skip
13199 10:54:59.161339 arm64_za-ptrace_Get_and_set_data_for_VL_752 skip
13200 10:54:59.161699 arm64_za-ptrace_Set_VL_768 pass
13201 10:54:59.161860 arm64_za-ptrace_Disabled_ZA_for_VL_768 skip
13202 10:54:59.161989 arm64_za-ptrace_Get_and_set_data_for_VL_768 skip
13203 10:54:59.162107 arm64_za-ptrace_Set_VL_784 pass
13204 10:54:59.162222 arm64_za-ptrace_Disabled_ZA_for_VL_784 skip
13205 10:54:59.162338 arm64_za-ptrace_Get_and_set_data_for_VL_784 skip
13206 10:54:59.162453 arm64_za-ptrace_Set_VL_800 pass
13207 10:54:59.162567 arm64_za-ptrace_Disabled_ZA_for_VL_800 skip
13208 10:54:59.162681 arm64_za-ptrace_Get_and_set_data_for_VL_800 skip
13209 10:54:59.162795 arm64_za-ptrace_Set_VL_816 pass
13210 10:54:59.162908 arm64_za-ptrace_Disabled_ZA_for_VL_816 skip
13211 10:54:59.163022 arm64_za-ptrace_Get_and_set_data_for_VL_816 skip
13212 10:54:59.163679 arm64_za-ptrace_Set_VL_832 pass
13213 10:54:59.164115 arm64_za-ptrace_Disabled_ZA_for_VL_832 skip
13214 10:54:59.164320 arm64_za-ptrace_Get_and_set_data_for_VL_832 skip
13215 10:54:59.164522 arm64_za-ptrace_Set_VL_848 pass
13216 10:54:59.164729 arm64_za-ptrace_Disabled_ZA_for_VL_848 skip
13217 10:54:59.165003 arm64_za-ptrace_Get_and_set_data_for_VL_848 skip
13218 10:54:59.165219 arm64_za-ptrace_Set_VL_864 pass
13219 10:54:59.165425 arm64_za-ptrace_Disabled_ZA_for_VL_864 skip
13220 10:54:59.165642 arm64_za-ptrace_Get_and_set_data_for_VL_864 skip
13221 10:54:59.165883 arm64_za-ptrace_Set_VL_880 pass
13222 10:54:59.166070 arm64_za-ptrace_Disabled_ZA_for_VL_880 skip
13223 10:54:59.166272 arm64_za-ptrace_Get_and_set_data_for_VL_880 skip
13224 10:54:59.166490 arm64_za-ptrace_Set_VL_896 pass
13225 10:54:59.166660 arm64_za-ptrace_Disabled_ZA_for_VL_896 skip
13226 10:54:59.166861 arm64_za-ptrace_Get_and_set_data_for_VL_896 skip
13227 10:54:59.167079 arm64_za-ptrace_Set_VL_912 pass
13228 10:54:59.167258 arm64_za-ptrace_Disabled_ZA_for_VL_912 skip
13229 10:54:59.167442 arm64_za-ptrace_Get_and_set_data_for_VL_912 skip
13230 10:54:59.167597 arm64_za-ptrace_Set_VL_928 pass
13231 10:54:59.167757 arm64_za-ptrace_Disabled_ZA_for_VL_928 skip
13232 10:54:59.167891 arm64_za-ptrace_Get_and_set_data_for_VL_928 skip
13233 10:54:59.168009 arm64_za-ptrace_Set_VL_944 pass
13234 10:54:59.168124 arm64_za-ptrace_Disabled_ZA_for_VL_944 skip
13235 10:54:59.168239 arm64_za-ptrace_Get_and_set_data_for_VL_944 skip
13236 10:54:59.168355 arm64_za-ptrace_Set_VL_960 pass
13237 10:54:59.168470 arm64_za-ptrace_Disabled_ZA_for_VL_960 skip
13238 10:54:59.168584 arm64_za-ptrace_Get_and_set_data_for_VL_960 skip
13239 10:54:59.168698 arm64_za-ptrace_Set_VL_976 pass
13240 10:54:59.168812 arm64_za-ptrace_Disabled_ZA_for_VL_976 skip
13241 10:54:59.168925 arm64_za-ptrace_Get_and_set_data_for_VL_976 skip
13242 10:54:59.169038 arm64_za-ptrace_Set_VL_992 pass
13243 10:54:59.169152 arm64_za-ptrace_Disabled_ZA_for_VL_992 skip
13244 10:54:59.169266 arm64_za-ptrace_Get_and_set_data_for_VL_992 skip
13245 10:54:59.169408 arm64_za-ptrace_Set_VL_1008 pass
13246 10:54:59.169532 arm64_za-ptrace_Disabled_ZA_for_VL_1008 skip
13247 10:54:59.169677 arm64_za-ptrace_Get_and_set_data_for_VL_1008 skip
13248 10:54:59.169898 arm64_za-ptrace_Set_VL_1024 pass
13249 10:54:59.170088 arm64_za-ptrace_Disabled_ZA_for_VL_1024 skip
13250 10:54:59.170272 arm64_za-ptrace_Get_and_set_data_for_VL_1024 skip
13251 10:54:59.171722 arm64_za-ptrace_Set_VL_1040 pass
13252 10:54:59.172153 arm64_za-ptrace_Disabled_ZA_for_VL_1040 skip
13253 10:54:59.172340 arm64_za-ptrace_Get_and_set_data_for_VL_1040 skip
13254 10:54:59.172513 arm64_za-ptrace_Set_VL_1056 pass
13255 10:54:59.172704 arm64_za-ptrace_Disabled_ZA_for_VL_1056 skip
13256 10:54:59.172861 arm64_za-ptrace_Get_and_set_data_for_VL_1056 skip
13257 10:54:59.173029 arm64_za-ptrace_Set_VL_1072 pass
13258 10:54:59.173190 arm64_za-ptrace_Disabled_ZA_for_VL_1072 skip
13259 10:54:59.173372 arm64_za-ptrace_Get_and_set_data_for_VL_1072 skip
13260 10:54:59.173563 arm64_za-ptrace_Set_VL_1088 pass
13261 10:54:59.173749 arm64_za-ptrace_Disabled_ZA_for_VL_1088 skip
13262 10:54:59.173908 arm64_za-ptrace_Get_and_set_data_for_VL_1088 skip
13263 10:54:59.174063 arm64_za-ptrace_Set_VL_1104 pass
13264 10:54:59.174222 arm64_za-ptrace_Disabled_ZA_for_VL_1104 skip
13265 10:54:59.174410 arm64_za-ptrace_Get_and_set_data_for_VL_1104 skip
13266 10:54:59.174623 arm64_za-ptrace_Set_VL_1120 pass
13267 10:54:59.174802 arm64_za-ptrace_Disabled_ZA_for_VL_1120 skip
13268 10:54:59.175000 arm64_za-ptrace_Get_and_set_data_for_VL_1120 skip
13269 10:54:59.175215 arm64_za-ptrace_Set_VL_1136 pass
13270 10:54:59.175435 arm64_za-ptrace_Disabled_ZA_for_VL_1136 skip
13271 10:54:59.175624 arm64_za-ptrace_Get_and_set_data_for_VL_1136 skip
13272 10:54:59.175846 arm64_za-ptrace_Set_VL_1152 pass
13273 10:54:59.176056 arm64_za-ptrace_Disabled_ZA_for_VL_1152 skip
13274 10:54:59.176229 arm64_za-ptrace_Get_and_set_data_for_VL_1152 skip
13275 10:54:59.176390 arm64_za-ptrace_Set_VL_1168 pass
13276 10:54:59.176590 arm64_za-ptrace_Disabled_ZA_for_VL_1168 skip
13277 10:54:59.176777 arm64_za-ptrace_Get_and_set_data_for_VL_1168 skip
13278 10:54:59.176956 arm64_za-ptrace_Set_VL_1184 pass
13279 10:54:59.177125 arm64_za-ptrace_Disabled_ZA_for_VL_1184 skip
13280 10:54:59.177300 arm64_za-ptrace_Get_and_set_data_for_VL_1184 skip
13281 10:54:59.177476 arm64_za-ptrace_Set_VL_1200 pass
13282 10:54:59.177684 arm64_za-ptrace_Disabled_ZA_for_VL_1200 skip
13283 10:54:59.177904 arm64_za-ptrace_Get_and_set_data_for_VL_1200 skip
13284 10:54:59.178094 arm64_za-ptrace_Set_VL_1216 pass
13285 10:54:59.178279 arm64_za-ptrace_Disabled_ZA_for_VL_1216 skip
13286 10:54:59.178465 arm64_za-ptrace_Get_and_set_data_for_VL_1216 skip
13287 10:54:59.178650 arm64_za-ptrace_Set_VL_1232 pass
13288 10:54:59.178845 arm64_za-ptrace_Disabled_ZA_for_VL_1232 skip
13289 10:54:59.179019 arm64_za-ptrace_Get_and_set_data_for_VL_1232 skip
13290 10:54:59.179165 arm64_za-ptrace_Set_VL_1248 pass
13291 10:54:59.179308 arm64_za-ptrace_Disabled_ZA_for_VL_1248 skip
13292 10:54:59.179451 arm64_za-ptrace_Get_and_set_data_for_VL_1248 skip
13293 10:54:59.179594 arm64_za-ptrace_Set_VL_1264 pass
13294 10:54:59.179772 arm64_za-ptrace_Disabled_ZA_for_VL_1264 skip
13295 10:54:59.179910 arm64_za-ptrace_Get_and_set_data_for_VL_1264 skip
13296 10:54:59.180054 arm64_za-ptrace_Set_VL_1280 pass
13297 10:54:59.180414 arm64_za-ptrace_Disabled_ZA_for_VL_1280 skip
13298 10:54:59.180552 arm64_za-ptrace_Get_and_set_data_for_VL_1280 skip
13299 10:54:59.180696 arm64_za-ptrace_Set_VL_1296 pass
13300 10:54:59.180839 arm64_za-ptrace_Disabled_ZA_for_VL_1296 skip
13301 10:54:59.180982 arm64_za-ptrace_Get_and_set_data_for_VL_1296 skip
13302 10:54:59.181125 arm64_za-ptrace_Set_VL_1312 pass
13303 10:54:59.181267 arm64_za-ptrace_Disabled_ZA_for_VL_1312 skip
13304 10:54:59.181409 arm64_za-ptrace_Get_and_set_data_for_VL_1312 skip
13305 10:54:59.181551 arm64_za-ptrace_Set_VL_1328 pass
13306 10:54:59.181707 arm64_za-ptrace_Disabled_ZA_for_VL_1328 skip
13307 10:54:59.181852 arm64_za-ptrace_Get_and_set_data_for_VL_1328 skip
13308 10:54:59.181996 arm64_za-ptrace_Set_VL_1344 pass
13309 10:54:59.182140 arm64_za-ptrace_Disabled_ZA_for_VL_1344 skip
13310 10:54:59.182283 arm64_za-ptrace_Get_and_set_data_for_VL_1344 skip
13311 10:54:59.182426 arm64_za-ptrace_Set_VL_1360 pass
13312 10:54:59.182568 arm64_za-ptrace_Disabled_ZA_for_VL_1360 skip
13313 10:54:59.182710 arm64_za-ptrace_Get_and_set_data_for_VL_1360 skip
13314 10:54:59.187638 arm64_za-ptrace_Set_VL_1376 pass
13315 10:54:59.188077 arm64_za-ptrace_Disabled_ZA_for_VL_1376 skip
13316 10:54:59.188271 arm64_za-ptrace_Get_and_set_data_for_VL_1376 skip
13317 10:54:59.188449 arm64_za-ptrace_Set_VL_1392 pass
13318 10:54:59.188662 arm64_za-ptrace_Disabled_ZA_for_VL_1392 skip
13319 10:54:59.188913 arm64_za-ptrace_Get_and_set_data_for_VL_1392 skip
13320 10:54:59.189120 arm64_za-ptrace_Set_VL_1408 pass
13321 10:54:59.189284 arm64_za-ptrace_Disabled_ZA_for_VL_1408 skip
13322 10:54:59.189417 arm64_za-ptrace_Get_and_set_data_for_VL_1408 skip
13323 10:54:59.189574 arm64_za-ptrace_Set_VL_1424 pass
13324 10:54:59.189757 arm64_za-ptrace_Disabled_ZA_for_VL_1424 skip
13325 10:54:59.189961 arm64_za-ptrace_Get_and_set_data_for_VL_1424 skip
13326 10:54:59.190143 arm64_za-ptrace_Set_VL_1440 pass
13327 10:54:59.190359 arm64_za-ptrace_Disabled_ZA_for_VL_1440 skip
13328 10:54:59.190560 arm64_za-ptrace_Get_and_set_data_for_VL_1440 skip
13329 10:54:59.190733 arm64_za-ptrace_Set_VL_1456 pass
13330 10:54:59.190896 arm64_za-ptrace_Disabled_ZA_for_VL_1456 skip
13331 10:54:59.191018 arm64_za-ptrace_Get_and_set_data_for_VL_1456 skip
13332 10:54:59.191132 arm64_za-ptrace_Set_VL_1472 pass
13333 10:54:59.191259 arm64_za-ptrace_Disabled_ZA_for_VL_1472 skip
13334 10:54:59.191378 arm64_za-ptrace_Get_and_set_data_for_VL_1472 skip
13335 10:54:59.191494 arm64_za-ptrace_Set_VL_1488 pass
13336 10:54:59.191608 arm64_za-ptrace_Disabled_ZA_for_VL_1488 skip
13337 10:54:59.191722 arm64_za-ptrace_Get_and_set_data_for_VL_1488 skip
13338 10:54:59.191835 arm64_za-ptrace_Set_VL_1504 pass
13339 10:54:59.191949 arm64_za-ptrace_Disabled_ZA_for_VL_1504 skip
13340 10:54:59.192094 arm64_za-ptrace_Get_and_set_data_for_VL_1504 skip
13341 10:54:59.192215 arm64_za-ptrace_Set_VL_1520 pass
13342 10:54:59.192331 arm64_za-ptrace_Disabled_ZA_for_VL_1520 skip
13343 10:54:59.192448 arm64_za-ptrace_Get_and_set_data_for_VL_1520 skip
13344 10:54:59.192561 arm64_za-ptrace_Set_VL_1536 pass
13345 10:54:59.192675 arm64_za-ptrace_Disabled_ZA_for_VL_1536 skip
13346 10:54:59.212680 arm64_za-ptrace_Get_and_set_data_for_VL_1536 skip
13347 10:54:59.212890 arm64_za-ptrace_Set_VL_1552 pass
13348 10:54:59.213248 arm64_za-ptrace_Disabled_ZA_for_VL_1552 skip
13349 10:54:59.213349 arm64_za-ptrace_Get_and_set_data_for_VL_1552 skip
13350 10:54:59.213444 arm64_za-ptrace_Set_VL_1568 pass
13351 10:54:59.213545 arm64_za-ptrace_Disabled_ZA_for_VL_1568 skip
13352 10:54:59.213652 arm64_za-ptrace_Get_and_set_data_for_VL_1568 skip
13353 10:54:59.213765 arm64_za-ptrace_Set_VL_1584 pass
13354 10:54:59.213889 arm64_za-ptrace_Disabled_ZA_for_VL_1584 skip
13355 10:54:59.213980 arm64_za-ptrace_Get_and_set_data_for_VL_1584 skip
13356 10:54:59.214062 arm64_za-ptrace_Set_VL_1600 pass
13357 10:54:59.214143 arm64_za-ptrace_Disabled_ZA_for_VL_1600 skip
13358 10:54:59.214223 arm64_za-ptrace_Get_and_set_data_for_VL_1600 skip
13359 10:54:59.214318 arm64_za-ptrace_Set_VL_1616 pass
13360 10:54:59.214392 arm64_za-ptrace_Disabled_ZA_for_VL_1616 skip
13361 10:54:59.214457 arm64_za-ptrace_Get_and_set_data_for_VL_1616 skip
13362 10:54:59.214527 arm64_za-ptrace_Set_VL_1632 pass
13363 10:54:59.214620 arm64_za-ptrace_Disabled_ZA_for_VL_1632 skip
13364 10:54:59.214704 arm64_za-ptrace_Get_and_set_data_for_VL_1632 skip
13365 10:54:59.214785 arm64_za-ptrace_Set_VL_1648 pass
13366 10:54:59.214879 arm64_za-ptrace_Disabled_ZA_for_VL_1648 skip
13367 10:54:59.214958 arm64_za-ptrace_Get_and_set_data_for_VL_1648 skip
13368 10:54:59.215050 arm64_za-ptrace_Set_VL_1664 pass
13369 10:54:59.215130 arm64_za-ptrace_Disabled_ZA_for_VL_1664 skip
13370 10:54:59.215219 arm64_za-ptrace_Get_and_set_data_for_VL_1664 skip
13371 10:54:59.215561 arm64_za-ptrace_Set_VL_1680 pass
13372 10:54:59.215648 arm64_za-ptrace_Disabled_ZA_for_VL_1680 skip
13373 10:54:59.215717 arm64_za-ptrace_Get_and_set_data_for_VL_1680 skip
13374 10:54:59.219639 arm64_za-ptrace_Set_VL_1696 pass
13375 10:54:59.219741 arm64_za-ptrace_Disabled_ZA_for_VL_1696 skip
13376 10:54:59.220016 arm64_za-ptrace_Get_and_set_data_for_VL_1696 skip
13377 10:54:59.220108 arm64_za-ptrace_Set_VL_1712 pass
13378 10:54:59.220203 arm64_za-ptrace_Disabled_ZA_for_VL_1712 skip
13379 10:54:59.220285 arm64_za-ptrace_Get_and_set_data_for_VL_1712 skip
13380 10:54:59.220409 arm64_za-ptrace_Set_VL_1728 pass
13381 10:54:59.220510 arm64_za-ptrace_Disabled_ZA_for_VL_1728 skip
13382 10:54:59.220630 arm64_za-ptrace_Get_and_set_data_for_VL_1728 skip
13383 10:54:59.220738 arm64_za-ptrace_Set_VL_1744 pass
13384 10:54:59.220825 arm64_za-ptrace_Disabled_ZA_for_VL_1744 skip
13385 10:54:59.220921 arm64_za-ptrace_Get_and_set_data_for_VL_1744 skip
13386 10:54:59.221006 arm64_za-ptrace_Set_VL_1760 pass
13387 10:54:59.221100 arm64_za-ptrace_Disabled_ZA_for_VL_1760 skip
13388 10:54:59.221178 arm64_za-ptrace_Get_and_set_data_for_VL_1760 skip
13389 10:54:59.221302 arm64_za-ptrace_Set_VL_1776 pass
13390 10:54:59.221428 arm64_za-ptrace_Disabled_ZA_for_VL_1776 skip
13391 10:54:59.221532 arm64_za-ptrace_Get_and_set_data_for_VL_1776 skip
13392 10:54:59.221633 arm64_za-ptrace_Set_VL_1792 pass
13393 10:54:59.221930 arm64_za-ptrace_Disabled_ZA_for_VL_1792 skip
13394 10:54:59.222022 arm64_za-ptrace_Get_and_set_data_for_VL_1792 skip
13395 10:54:59.222108 arm64_za-ptrace_Set_VL_1808 pass
13396 10:54:59.222207 arm64_za-ptrace_Disabled_ZA_for_VL_1808 skip
13397 10:54:59.222484 arm64_za-ptrace_Get_and_set_data_for_VL_1808 skip
13398 10:54:59.222576 arm64_za-ptrace_Set_VL_1824 pass
13399 10:54:59.222661 arm64_za-ptrace_Disabled_ZA_for_VL_1824 skip
13400 10:54:59.222743 arm64_za-ptrace_Get_and_set_data_for_VL_1824 skip
13401 10:54:59.222844 arm64_za-ptrace_Set_VL_1840 pass
13402 10:54:59.222932 arm64_za-ptrace_Disabled_ZA_for_VL_1840 skip
13403 10:54:59.223016 arm64_za-ptrace_Get_and_set_data_for_VL_1840 skip
13404 10:54:59.223117 arm64_za-ptrace_Set_VL_1856 pass
13405 10:54:59.223204 arm64_za-ptrace_Disabled_ZA_for_VL_1856 skip
13406 10:54:59.223304 arm64_za-ptrace_Get_and_set_data_for_VL_1856 skip
13407 10:54:59.223415 arm64_za-ptrace_Set_VL_1872 pass
13408 10:54:59.227665 arm64_za-ptrace_Disabled_ZA_for_VL_1872 skip
13409 10:54:59.228119 arm64_za-ptrace_Get_and_set_data_for_VL_1872 skip
13410 10:54:59.228318 arm64_za-ptrace_Set_VL_1888 pass
13411 10:54:59.228489 arm64_za-ptrace_Disabled_ZA_for_VL_1888 skip
13412 10:54:59.228700 arm64_za-ptrace_Get_and_set_data_for_VL_1888 skip
13413 10:54:59.228855 arm64_za-ptrace_Set_VL_1904 pass
13414 10:54:59.229060 arm64_za-ptrace_Disabled_ZA_for_VL_1904 skip
13415 10:54:59.229257 arm64_za-ptrace_Get_and_set_data_for_VL_1904 skip
13416 10:54:59.229472 arm64_za-ptrace_Set_VL_1920 pass
13417 10:54:59.229666 arm64_za-ptrace_Disabled_ZA_for_VL_1920 skip
13418 10:54:59.229876 arm64_za-ptrace_Get_and_set_data_for_VL_1920 skip
13419 10:54:59.230065 arm64_za-ptrace_Set_VL_1936 pass
13420 10:54:59.230273 arm64_za-ptrace_Disabled_ZA_for_VL_1936 skip
13421 10:54:59.230414 arm64_za-ptrace_Get_and_set_data_for_VL_1936 skip
13422 10:54:59.230547 arm64_za-ptrace_Set_VL_1952 pass
13423 10:54:59.230683 arm64_za-ptrace_Disabled_ZA_for_VL_1952 skip
13424 10:54:59.230894 arm64_za-ptrace_Get_and_set_data_for_VL_1952 skip
13425 10:54:59.231072 arm64_za-ptrace_Set_VL_1968 pass
13426 10:54:59.231238 arm64_za-ptrace_Disabled_ZA_for_VL_1968 skip
13427 10:54:59.231402 arm64_za-ptrace_Get_and_set_data_for_VL_1968 skip
13428 10:54:59.231546 arm64_za-ptrace_Set_VL_1984 pass
13429 10:54:59.231713 arm64_za-ptrace_Disabled_ZA_for_VL_1984 skip
13430 10:54:59.231843 arm64_za-ptrace_Get_and_set_data_for_VL_1984 skip
13431 10:54:59.231959 arm64_za-ptrace_Set_VL_2000 pass
13432 10:54:59.232074 arm64_za-ptrace_Disabled_ZA_for_VL_2000 skip
13433 10:54:59.232190 arm64_za-ptrace_Get_and_set_data_for_VL_2000 skip
13434 10:54:59.232337 arm64_za-ptrace_Set_VL_2016 pass
13435 10:54:59.232464 arm64_za-ptrace_Disabled_ZA_for_VL_2016 skip
13436 10:54:59.232582 arm64_za-ptrace_Get_and_set_data_for_VL_2016 skip
13437 10:54:59.232697 arm64_za-ptrace_Set_VL_2032 pass
13438 10:54:59.232813 arm64_za-ptrace_Disabled_ZA_for_VL_2032 skip
13439 10:54:59.232929 arm64_za-ptrace_Get_and_set_data_for_VL_2032 skip
13440 10:54:59.233044 arm64_za-ptrace_Set_VL_2048 pass
13441 10:54:59.233158 arm64_za-ptrace_Disabled_ZA_for_VL_2048 skip
13442 10:54:59.233273 arm64_za-ptrace_Get_and_set_data_for_VL_2048 skip
13443 10:54:59.233389 arm64_za-ptrace_Set_VL_2064 pass
13444 10:54:59.235730 arm64_za-ptrace_Disabled_ZA_for_VL_2064 skip
13445 10:54:59.235915 arm64_za-ptrace_Get_and_set_data_for_VL_2064 skip
13446 10:54:59.236390 arm64_za-ptrace_Set_VL_2080 pass
13447 10:54:59.236586 arm64_za-ptrace_Disabled_ZA_for_VL_2080 skip
13448 10:54:59.236755 arm64_za-ptrace_Get_and_set_data_for_VL_2080 skip
13449 10:54:59.236915 arm64_za-ptrace_Set_VL_2096 pass
13450 10:54:59.237074 arm64_za-ptrace_Disabled_ZA_for_VL_2096 skip
13451 10:54:59.237233 arm64_za-ptrace_Get_and_set_data_for_VL_2096 skip
13452 10:54:59.237421 arm64_za-ptrace_Set_VL_2112 pass
13453 10:54:59.237600 arm64_za-ptrace_Disabled_ZA_for_VL_2112 skip
13454 10:54:59.237808 arm64_za-ptrace_Get_and_set_data_for_VL_2112 skip
13455 10:54:59.238006 arm64_za-ptrace_Set_VL_2128 pass
13456 10:54:59.238166 arm64_za-ptrace_Disabled_ZA_for_VL_2128 skip
13457 10:54:59.238410 arm64_za-ptrace_Get_and_set_data_for_VL_2128 skip
13458 10:54:59.238654 arm64_za-ptrace_Set_VL_2144 pass
13459 10:54:59.238854 arm64_za-ptrace_Disabled_ZA_for_VL_2144 skip
13460 10:54:59.239024 arm64_za-ptrace_Get_and_set_data_for_VL_2144 skip
13461 10:54:59.239232 arm64_za-ptrace_Set_VL_2160 pass
13462 10:54:59.239406 arm64_za-ptrace_Disabled_ZA_for_VL_2160 skip
13463 10:54:59.239598 arm64_za-ptrace_Get_and_set_data_for_VL_2160 skip
13464 10:54:59.239738 arm64_za-ptrace_Set_VL_2176 pass
13465 10:54:59.239853 arm64_za-ptrace_Disabled_ZA_for_VL_2176 skip
13466 10:54:59.239968 arm64_za-ptrace_Get_and_set_data_for_VL_2176 skip
13467 10:54:59.240082 arm64_za-ptrace_Set_VL_2192 pass
13468 10:54:59.240196 arm64_za-ptrace_Disabled_ZA_for_VL_2192 skip
13469 10:54:59.240308 arm64_za-ptrace_Get_and_set_data_for_VL_2192 skip
13470 10:54:59.240422 arm64_za-ptrace_Set_VL_2208 pass
13471 10:54:59.240534 arm64_za-ptrace_Disabled_ZA_for_VL_2208 skip
13472 10:54:59.240646 arm64_za-ptrace_Get_and_set_data_for_VL_2208 skip
13473 10:54:59.240760 arm64_za-ptrace_Set_VL_2224 pass
13474 10:54:59.240873 arm64_za-ptrace_Disabled_ZA_for_VL_2224 skip
13475 10:54:59.240986 arm64_za-ptrace_Get_and_set_data_for_VL_2224 skip
13476 10:54:59.241099 arm64_za-ptrace_Set_VL_2240 pass
13477 10:54:59.241211 arm64_za-ptrace_Disabled_ZA_for_VL_2240 skip
13478 10:54:59.241351 arm64_za-ptrace_Get_and_set_data_for_VL_2240 skip
13479 10:54:59.241476 arm64_za-ptrace_Set_VL_2256 pass
13480 10:54:59.243647 arm64_za-ptrace_Disabled_ZA_for_VL_2256 skip
13481 10:54:59.244129 arm64_za-ptrace_Get_and_set_data_for_VL_2256 skip
13482 10:54:59.244310 arm64_za-ptrace_Set_VL_2272 pass
13483 10:54:59.244473 arm64_za-ptrace_Disabled_ZA_for_VL_2272 skip
13484 10:54:59.244629 arm64_za-ptrace_Get_and_set_data_for_VL_2272 skip
13485 10:54:59.244784 arm64_za-ptrace_Set_VL_2288 pass
13486 10:54:59.245038 arm64_za-ptrace_Disabled_ZA_for_VL_2288 skip
13487 10:54:59.245218 arm64_za-ptrace_Get_and_set_data_for_VL_2288 skip
13488 10:54:59.245373 arm64_za-ptrace_Set_VL_2304 pass
13489 10:54:59.245536 arm64_za-ptrace_Disabled_ZA_for_VL_2304 skip
13490 10:54:59.245728 arm64_za-ptrace_Get_and_set_data_for_VL_2304 skip
13491 10:54:59.245935 arm64_za-ptrace_Set_VL_2320 pass
13492 10:54:59.246095 arm64_za-ptrace_Disabled_ZA_for_VL_2320 skip
13493 10:54:59.246276 arm64_za-ptrace_Get_and_set_data_for_VL_2320 skip
13494 10:54:59.246505 arm64_za-ptrace_Set_VL_2336 pass
13495 10:54:59.246646 arm64_za-ptrace_Disabled_ZA_for_VL_2336 skip
13496 10:54:59.246769 arm64_za-ptrace_Get_and_set_data_for_VL_2336 skip
13497 10:54:59.246925 arm64_za-ptrace_Set_VL_2352 pass
13498 10:54:59.247059 arm64_za-ptrace_Disabled_ZA_for_VL_2352 skip
13499 10:54:59.247191 arm64_za-ptrace_Get_and_set_data_for_VL_2352 skip
13500 10:54:59.247340 arm64_za-ptrace_Set_VL_2368 pass
13501 10:54:59.247480 arm64_za-ptrace_Disabled_ZA_for_VL_2368 skip
13502 10:54:59.247603 arm64_za-ptrace_Get_and_set_data_for_VL_2368 skip
13503 10:54:59.247719 arm64_za-ptrace_Set_VL_2384 pass
13504 10:54:59.247835 arm64_za-ptrace_Disabled_ZA_for_VL_2384 skip
13505 10:54:59.247950 arm64_za-ptrace_Get_and_set_data_for_VL_2384 skip
13506 10:54:59.248065 arm64_za-ptrace_Set_VL_2400 pass
13507 10:54:59.248210 arm64_za-ptrace_Disabled_ZA_for_VL_2400 skip
13508 10:54:59.248330 arm64_za-ptrace_Get_and_set_data_for_VL_2400 skip
13509 10:54:59.248447 arm64_za-ptrace_Set_VL_2416 pass
13510 10:54:59.248562 arm64_za-ptrace_Disabled_ZA_for_VL_2416 skip
13511 10:54:59.248678 arm64_za-ptrace_Get_and_set_data_for_VL_2416 skip
13512 10:54:59.248794 arm64_za-ptrace_Set_VL_2432 pass
13513 10:54:59.248910 arm64_za-ptrace_Disabled_ZA_for_VL_2432 skip
13514 10:54:59.249025 arm64_za-ptrace_Get_and_set_data_for_VL_2432 skip
13515 10:54:59.249141 arm64_za-ptrace_Set_VL_2448 pass
13516 10:54:59.251756 arm64_za-ptrace_Disabled_ZA_for_VL_2448 skip
13517 10:54:59.252168 arm64_za-ptrace_Get_and_set_data_for_VL_2448 skip
13518 10:54:59.252275 arm64_za-ptrace_Set_VL_2464 pass
13519 10:54:59.252365 arm64_za-ptrace_Disabled_ZA_for_VL_2464 skip
13520 10:54:59.252449 arm64_za-ptrace_Get_and_set_data_for_VL_2464 skip
13521 10:54:59.252532 arm64_za-ptrace_Set_VL_2480 pass
13522 10:54:59.252633 arm64_za-ptrace_Disabled_ZA_for_VL_2480 skip
13523 10:54:59.252718 arm64_za-ptrace_Get_and_set_data_for_VL_2480 skip
13524 10:54:59.252801 arm64_za-ptrace_Set_VL_2496 pass
13525 10:54:59.252881 arm64_za-ptrace_Disabled_ZA_for_VL_2496 skip
13526 10:54:59.252963 arm64_za-ptrace_Get_and_set_data_for_VL_2496 skip
13527 10:54:59.253061 arm64_za-ptrace_Set_VL_2512 pass
13528 10:54:59.253146 arm64_za-ptrace_Disabled_ZA_for_VL_2512 skip
13529 10:54:59.253229 arm64_za-ptrace_Get_and_set_data_for_VL_2512 skip
13530 10:54:59.253327 arm64_za-ptrace_Set_VL_2528 pass
13531 10:54:59.253412 arm64_za-ptrace_Disabled_ZA_for_VL_2528 skip
13532 10:54:59.253510 arm64_za-ptrace_Get_and_set_data_for_VL_2528 skip
13533 10:54:59.253596 arm64_za-ptrace_Set_VL_2544 pass
13534 10:54:59.253707 arm64_za-ptrace_Disabled_ZA_for_VL_2544 skip
13535 10:54:59.253808 arm64_za-ptrace_Get_and_set_data_for_VL_2544 skip
13536 10:54:59.253915 arm64_za-ptrace_Set_VL_2560 pass
13537 10:54:59.254014 arm64_za-ptrace_Disabled_ZA_for_VL_2560 skip
13538 10:54:59.254717 arm64_za-ptrace_Get_and_set_data_for_VL_2560 skip
13539 10:54:59.272002 arm64_za-ptrace_Set_VL_2576 pass
13540 10:54:59.272457 arm64_za-ptrace_Disabled_ZA_for_VL_2576 skip
13541 10:54:59.272663 arm64_za-ptrace_Get_and_set_data_for_VL_2576 skip
13542 10:54:59.272815 arm64_za-ptrace_Set_VL_2592 pass
13543 10:54:59.273011 arm64_za-ptrace_Disabled_ZA_for_VL_2592 skip
13544 10:54:59.273207 arm64_za-ptrace_Get_and_set_data_for_VL_2592 skip
13545 10:54:59.273443 arm64_za-ptrace_Set_VL_2608 pass
13546 10:54:59.273601 arm64_za-ptrace_Disabled_ZA_for_VL_2608 skip
13547 10:54:59.273769 arm64_za-ptrace_Get_and_set_data_for_VL_2608 skip
13548 10:54:59.273994 arm64_za-ptrace_Set_VL_2624 pass
13549 10:54:59.274169 arm64_za-ptrace_Disabled_ZA_for_VL_2624 skip
13550 10:54:59.274328 arm64_za-ptrace_Get_and_set_data_for_VL_2624 skip
13551 10:54:59.274493 arm64_za-ptrace_Set_VL_2640 pass
13552 10:54:59.274650 arm64_za-ptrace_Disabled_ZA_for_VL_2640 skip
13553 10:54:59.274811 arm64_za-ptrace_Get_and_set_data_for_VL_2640 skip
13554 10:54:59.274971 arm64_za-ptrace_Set_VL_2656 pass
13555 10:54:59.275165 arm64_za-ptrace_Disabled_ZA_for_VL_2656 skip
13556 10:54:59.275330 arm64_za-ptrace_Get_and_set_data_for_VL_2656 skip
13557 10:54:59.275511 arm64_za-ptrace_Set_VL_2672 pass
13558 10:54:59.275649 arm64_za-ptrace_Disabled_ZA_for_VL_2672 skip
13559 10:54:59.275766 arm64_za-ptrace_Get_and_set_data_for_VL_2672 skip
13560 10:54:59.275881 arm64_za-ptrace_Set_VL_2688 pass
13561 10:54:59.275997 arm64_za-ptrace_Disabled_ZA_for_VL_2688 skip
13562 10:54:59.276111 arm64_za-ptrace_Get_and_set_data_for_VL_2688 skip
13563 10:54:59.276225 arm64_za-ptrace_Set_VL_2704 pass
13564 10:54:59.276337 arm64_za-ptrace_Disabled_ZA_for_VL_2704 skip
13565 10:54:59.276450 arm64_za-ptrace_Get_and_set_data_for_VL_2704 skip
13566 10:54:59.276566 arm64_za-ptrace_Set_VL_2720 pass
13567 10:54:59.276679 arm64_za-ptrace_Disabled_ZA_for_VL_2720 skip
13568 10:54:59.276794 arm64_za-ptrace_Get_and_set_data_for_VL_2720 skip
13569 10:54:59.276908 arm64_za-ptrace_Set_VL_2736 pass
13570 10:54:59.277020 arm64_za-ptrace_Disabled_ZA_for_VL_2736 skip
13571 10:54:59.277161 arm64_za-ptrace_Get_and_set_data_for_VL_2736 skip
13572 10:54:59.277283 arm64_za-ptrace_Set_VL_2752 pass
13573 10:54:59.277398 arm64_za-ptrace_Disabled_ZA_for_VL_2752 skip
13574 10:54:59.279731 arm64_za-ptrace_Get_and_set_data_for_VL_2752 skip
13575 10:54:59.279909 arm64_za-ptrace_Set_VL_2768 pass
13576 10:54:59.280326 arm64_za-ptrace_Disabled_ZA_for_VL_2768 skip
13577 10:54:59.280433 arm64_za-ptrace_Get_and_set_data_for_VL_2768 skip
13578 10:54:59.280522 arm64_za-ptrace_Set_VL_2784 pass
13579 10:54:59.280612 arm64_za-ptrace_Disabled_ZA_for_VL_2784 skip
13580 10:54:59.280698 arm64_za-ptrace_Get_and_set_data_for_VL_2784 skip
13581 10:54:59.280783 arm64_za-ptrace_Set_VL_2800 pass
13582 10:54:59.280885 arm64_za-ptrace_Disabled_ZA_for_VL_2800 skip
13583 10:54:59.280974 arm64_za-ptrace_Get_and_set_data_for_VL_2800 skip
13584 10:54:59.281056 arm64_za-ptrace_Set_VL_2816 pass
13585 10:54:59.281139 arm64_za-ptrace_Disabled_ZA_for_VL_2816 skip
13586 10:54:59.281235 arm64_za-ptrace_Get_and_set_data_for_VL_2816 skip
13587 10:54:59.281320 arm64_za-ptrace_Set_VL_2832 pass
13588 10:54:59.281418 arm64_za-ptrace_Disabled_ZA_for_VL_2832 skip
13589 10:54:59.281504 arm64_za-ptrace_Get_and_set_data_for_VL_2832 skip
13590 10:54:59.281594 arm64_za-ptrace_Set_VL_2848 pass
13591 10:54:59.281704 arm64_za-ptrace_Disabled_ZA_for_VL_2848 skip
13592 10:54:59.281807 arm64_za-ptrace_Get_and_set_data_for_VL_2848 skip
13593 10:54:59.281894 arm64_za-ptrace_Set_VL_2864 pass
13594 10:54:59.281994 arm64_za-ptrace_Disabled_ZA_for_VL_2864 skip
13595 10:54:59.282104 arm64_za-ptrace_Get_and_set_data_for_VL_2864 skip
13596 10:54:59.282450 arm64_za-ptrace_Set_VL_2880 pass
13597 10:54:59.282676 arm64_za-ptrace_Disabled_ZA_for_VL_2880 skip
13598 10:54:59.282845 arm64_za-ptrace_Get_and_set_data_for_VL_2880 skip
13599 10:54:59.283002 arm64_za-ptrace_Set_VL_2896 pass
13600 10:54:59.283186 arm64_za-ptrace_Disabled_ZA_for_VL_2896 skip
13601 10:54:59.283339 arm64_za-ptrace_Get_and_set_data_for_VL_2896 skip
13602 10:54:59.283507 arm64_za-ptrace_Set_VL_2912 pass
13603 10:54:59.283647 arm64_za-ptrace_Disabled_ZA_for_VL_2912 skip
13604 10:54:59.283763 arm64_za-ptrace_Get_and_set_data_for_VL_2912 skip
13605 10:54:59.283876 arm64_za-ptrace_Set_VL_2928 pass
13606 10:54:59.284016 arm64_za-ptrace_Disabled_ZA_for_VL_2928 skip
13607 10:54:59.284136 arm64_za-ptrace_Get_and_set_data_for_VL_2928 skip
13608 10:54:59.284250 arm64_za-ptrace_Set_VL_2944 pass
13609 10:54:59.284364 arm64_za-ptrace_Disabled_ZA_for_VL_2944 skip
13610 10:54:59.287817 arm64_za-ptrace_Get_and_set_data_for_VL_2944 skip
13611 10:54:59.288004 arm64_za-ptrace_Set_VL_2960 pass
13612 10:54:59.288152 arm64_za-ptrace_Disabled_ZA_for_VL_2960 skip
13613 10:54:59.288526 arm64_za-ptrace_Get_and_set_data_for_VL_2960 skip
13614 10:54:59.288696 arm64_za-ptrace_Set_VL_2976 pass
13615 10:54:59.288823 arm64_za-ptrace_Disabled_ZA_for_VL_2976 skip
13616 10:54:59.288950 arm64_za-ptrace_Get_and_set_data_for_VL_2976 skip
13617 10:54:59.289078 arm64_za-ptrace_Set_VL_2992 pass
13618 10:54:59.289208 arm64_za-ptrace_Disabled_ZA_for_VL_2992 skip
13619 10:54:59.289399 arm64_za-ptrace_Get_and_set_data_for_VL_2992 skip
13620 10:54:59.289585 arm64_za-ptrace_Set_VL_3008 pass
13621 10:54:59.289798 arm64_za-ptrace_Disabled_ZA_for_VL_3008 skip
13622 10:54:59.289984 arm64_za-ptrace_Get_and_set_data_for_VL_3008 skip
13623 10:54:59.290214 arm64_za-ptrace_Set_VL_3024 pass
13624 10:54:59.290393 arm64_za-ptrace_Disabled_ZA_for_VL_3024 skip
13625 10:54:59.290579 arm64_za-ptrace_Get_and_set_data_for_VL_3024 skip
13626 10:54:59.290775 arm64_za-ptrace_Set_VL_3040 pass
13627 10:54:59.290989 arm64_za-ptrace_Disabled_ZA_for_VL_3040 skip
13628 10:54:59.291197 arm64_za-ptrace_Get_and_set_data_for_VL_3040 skip
13629 10:54:59.291413 arm64_za-ptrace_Set_VL_3056 pass
13630 10:54:59.291634 arm64_za-ptrace_Disabled_ZA_for_VL_3056 skip
13631 10:54:59.291785 arm64_za-ptrace_Get_and_set_data_for_VL_3056 skip
13632 10:54:59.291906 arm64_za-ptrace_Set_VL_3072 pass
13633 10:54:59.292021 arm64_za-ptrace_Disabled_ZA_for_VL_3072 skip
13634 10:54:59.292167 arm64_za-ptrace_Get_and_set_data_for_VL_3072 skip
13635 10:54:59.292287 arm64_za-ptrace_Set_VL_3088 pass
13636 10:54:59.292401 arm64_za-ptrace_Disabled_ZA_for_VL_3088 skip
13637 10:54:59.292514 arm64_za-ptrace_Get_and_set_data_for_VL_3088 skip
13638 10:54:59.292627 arm64_za-ptrace_Set_VL_3104 pass
13639 10:54:59.292738 arm64_za-ptrace_Disabled_ZA_for_VL_3104 skip
13640 10:54:59.292852 arm64_za-ptrace_Get_and_set_data_for_VL_3104 skip
13641 10:54:59.292966 arm64_za-ptrace_Set_VL_3120 pass
13642 10:54:59.293078 arm64_za-ptrace_Disabled_ZA_for_VL_3120 skip
13643 10:54:59.293190 arm64_za-ptrace_Get_and_set_data_for_VL_3120 skip
13644 10:54:59.293303 arm64_za-ptrace_Set_VL_3136 pass
13645 10:54:59.293414 arm64_za-ptrace_Disabled_ZA_for_VL_3136 skip
13646 10:54:59.293527 arm64_za-ptrace_Get_and_set_data_for_VL_3136 skip
13647 10:54:59.293641 arm64_za-ptrace_Set_VL_3152 pass
13648 10:54:59.293766 arm64_za-ptrace_Disabled_ZA_for_VL_3152 skip
13649 10:54:59.293879 arm64_za-ptrace_Get_and_set_data_for_VL_3152 skip
13650 10:54:59.293991 arm64_za-ptrace_Set_VL_3168 pass
13651 10:54:59.294104 arm64_za-ptrace_Disabled_ZA_for_VL_3168 skip
13652 10:54:59.294217 arm64_za-ptrace_Get_and_set_data_for_VL_3168 skip
13653 10:54:59.295741 arm64_za-ptrace_Set_VL_3184 pass
13654 10:54:59.295916 arm64_za-ptrace_Disabled_ZA_for_VL_3184 skip
13655 10:54:59.296309 arm64_za-ptrace_Get_and_set_data_for_VL_3184 skip
13656 10:54:59.296496 arm64_za-ptrace_Set_VL_3200 pass
13657 10:54:59.296707 arm64_za-ptrace_Disabled_ZA_for_VL_3200 skip
13658 10:54:59.296905 arm64_za-ptrace_Get_and_set_data_for_VL_3200 skip
13659 10:54:59.297075 arm64_za-ptrace_Set_VL_3216 pass
13660 10:54:59.297278 arm64_za-ptrace_Disabled_ZA_for_VL_3216 skip
13661 10:54:59.297478 arm64_za-ptrace_Get_and_set_data_for_VL_3216 skip
13662 10:54:59.297626 arm64_za-ptrace_Set_VL_3232 pass
13663 10:54:59.297766 arm64_za-ptrace_Disabled_ZA_for_VL_3232 skip
13664 10:54:59.297891 arm64_za-ptrace_Get_and_set_data_for_VL_3232 skip
13665 10:54:59.298015 arm64_za-ptrace_Set_VL_3248 pass
13666 10:54:59.298143 arm64_za-ptrace_Disabled_ZA_for_VL_3248 skip
13667 10:54:59.298265 arm64_za-ptrace_Get_and_set_data_for_VL_3248 skip
13668 10:54:59.298391 arm64_za-ptrace_Set_VL_3264 pass
13669 10:54:59.298515 arm64_za-ptrace_Disabled_ZA_for_VL_3264 skip
13670 10:54:59.298642 arm64_za-ptrace_Get_and_set_data_for_VL_3264 skip
13671 10:54:59.298863 arm64_za-ptrace_Set_VL_3280 pass
13672 10:54:59.299053 arm64_za-ptrace_Disabled_ZA_for_VL_3280 skip
13673 10:54:59.299195 arm64_za-ptrace_Get_and_set_data_for_VL_3280 skip
13674 10:54:59.299338 arm64_za-ptrace_Set_VL_3296 pass
13675 10:54:59.299534 arm64_za-ptrace_Disabled_ZA_for_VL_3296 skip
13676 10:54:59.299664 arm64_za-ptrace_Get_and_set_data_for_VL_3296 skip
13677 10:54:59.299778 arm64_za-ptrace_Set_VL_3312 pass
13678 10:54:59.299888 arm64_za-ptrace_Disabled_ZA_for_VL_3312 skip
13679 10:54:59.299998 arm64_za-ptrace_Get_and_set_data_for_VL_3312 skip
13680 10:54:59.300110 arm64_za-ptrace_Set_VL_3328 pass
13681 10:54:59.300221 arm64_za-ptrace_Disabled_ZA_for_VL_3328 skip
13682 10:54:59.300334 arm64_za-ptrace_Get_and_set_data_for_VL_3328 skip
13683 10:54:59.300447 arm64_za-ptrace_Set_VL_3344 pass
13684 10:54:59.300559 arm64_za-ptrace_Disabled_ZA_for_VL_3344 skip
13685 10:54:59.300674 arm64_za-ptrace_Get_and_set_data_for_VL_3344 skip
13686 10:54:59.300787 arm64_za-ptrace_Set_VL_3360 pass
13687 10:54:59.300899 arm64_za-ptrace_Disabled_ZA_for_VL_3360 skip
13688 10:54:59.301011 arm64_za-ptrace_Get_and_set_data_for_VL_3360 skip
13689 10:54:59.301123 arm64_za-ptrace_Set_VL_3376 pass
13690 10:54:59.301237 arm64_za-ptrace_Disabled_ZA_for_VL_3376 skip
13691 10:54:59.301379 arm64_za-ptrace_Get_and_set_data_for_VL_3376 skip
13692 10:54:59.301499 arm64_za-ptrace_Set_VL_3392 pass
13693 10:54:59.301616 arm64_za-ptrace_Disabled_ZA_for_VL_3392 skip
13694 10:54:59.301746 arm64_za-ptrace_Get_and_set_data_for_VL_3392 skip
13695 10:54:59.301865 arm64_za-ptrace_Set_VL_3408 pass
13696 10:54:59.301977 arm64_za-ptrace_Disabled_ZA_for_VL_3408 skip
13697 10:54:59.302089 arm64_za-ptrace_Get_and_set_data_for_VL_3408 skip
13698 10:54:59.303754 arm64_za-ptrace_Set_VL_3424 pass
13699 10:54:59.303923 arm64_za-ptrace_Disabled_ZA_for_VL_3424 skip
13700 10:54:59.304269 arm64_za-ptrace_Get_and_set_data_for_VL_3424 skip
13701 10:54:59.304408 arm64_za-ptrace_Set_VL_3440 pass
13702 10:54:59.304598 arm64_za-ptrace_Disabled_ZA_for_VL_3440 skip
13703 10:54:59.304759 arm64_za-ptrace_Get_and_set_data_for_VL_3440 skip
13704 10:54:59.304898 arm64_za-ptrace_Set_VL_3456 pass
13705 10:54:59.305078 arm64_za-ptrace_Disabled_ZA_for_VL_3456 skip
13706 10:54:59.305229 arm64_za-ptrace_Get_and_set_data_for_VL_3456 skip
13707 10:54:59.305393 arm64_za-ptrace_Set_VL_3472 pass
13708 10:54:59.305565 arm64_za-ptrace_Disabled_ZA_for_VL_3472 skip
13709 10:54:59.305743 arm64_za-ptrace_Get_and_set_data_for_VL_3472 skip
13710 10:54:59.305896 arm64_za-ptrace_Set_VL_3488 pass
13711 10:54:59.306058 arm64_za-ptrace_Disabled_ZA_for_VL_3488 skip
13712 10:54:59.306230 arm64_za-ptrace_Get_and_set_data_for_VL_3488 skip
13713 10:54:59.306465 arm64_za-ptrace_Set_VL_3504 pass
13714 10:54:59.306629 arm64_za-ptrace_Disabled_ZA_for_VL_3504 skip
13715 10:54:59.306835 arm64_za-ptrace_Get_and_set_data_for_VL_3504 skip
13716 10:54:59.306971 arm64_za-ptrace_Set_VL_3520 pass
13717 10:54:59.307088 arm64_za-ptrace_Disabled_ZA_for_VL_3520 skip
13718 10:54:59.307264 arm64_za-ptrace_Get_and_set_data_for_VL_3520 skip
13719 10:54:59.307397 arm64_za-ptrace_Set_VL_3536 pass
13720 10:54:59.307513 arm64_za-ptrace_Disabled_ZA_for_VL_3536 skip
13721 10:54:59.307631 arm64_za-ptrace_Get_and_set_data_for_VL_3536 skip
13722 10:54:59.307746 arm64_za-ptrace_Set_VL_3552 pass
13723 10:54:59.307861 arm64_za-ptrace_Disabled_ZA_for_VL_3552 skip
13724 10:54:59.307976 arm64_za-ptrace_Get_and_set_data_for_VL_3552 skip
13725 10:54:59.308090 arm64_za-ptrace_Set_VL_3568 pass
13726 10:54:59.308202 arm64_za-ptrace_Disabled_ZA_for_VL_3568 skip
13727 10:54:59.308315 arm64_za-ptrace_Get_and_set_data_for_VL_3568 skip
13728 10:54:59.308429 arm64_za-ptrace_Set_VL_3584 pass
13729 10:54:59.308543 arm64_za-ptrace_Disabled_ZA_for_VL_3584 skip
13730 10:54:59.308659 arm64_za-ptrace_Get_and_set_data_for_VL_3584 skip
13731 10:54:59.334883 arm64_za-ptrace_Set_VL_3600 pass
13732 10:54:59.335112 arm64_za-ptrace_Disabled_ZA_for_VL_3600 skip
13733 10:54:59.335393 arm64_za-ptrace_Get_and_set_data_for_VL_3600 skip
13734 10:54:59.335477 arm64_za-ptrace_Set_VL_3616 pass
13735 10:54:59.335542 arm64_za-ptrace_Disabled_ZA_for_VL_3616 skip
13736 10:54:59.335605 arm64_za-ptrace_Get_and_set_data_for_VL_3616 skip
13737 10:54:59.335680 arm64_za-ptrace_Set_VL_3632 pass
13738 10:54:59.335756 arm64_za-ptrace_Disabled_ZA_for_VL_3632 skip
13739 10:54:59.336006 arm64_za-ptrace_Get_and_set_data_for_VL_3632 skip
13740 10:54:59.336077 arm64_za-ptrace_Set_VL_3648 pass
13741 10:54:59.336152 arm64_za-ptrace_Disabled_ZA_for_VL_3648 skip
13742 10:54:59.336227 arm64_za-ptrace_Get_and_set_data_for_VL_3648 skip
13743 10:54:59.336304 arm64_za-ptrace_Set_VL_3664 pass
13744 10:54:59.336560 arm64_za-ptrace_Disabled_ZA_for_VL_3664 skip
13745 10:54:59.336644 arm64_za-ptrace_Get_and_set_data_for_VL_3664 skip
13746 10:54:59.336890 arm64_za-ptrace_Set_VL_3680 pass
13747 10:54:59.336957 arm64_za-ptrace_Disabled_ZA_for_VL_3680 skip
13748 10:54:59.337031 arm64_za-ptrace_Get_and_set_data_for_VL_3680 skip
13749 10:54:59.337105 arm64_za-ptrace_Set_VL_3696 pass
13750 10:54:59.337355 arm64_za-ptrace_Disabled_ZA_for_VL_3696 skip
13751 10:54:59.337608 arm64_za-ptrace_Get_and_set_data_for_VL_3696 skip
13752 10:54:59.337686 arm64_za-ptrace_Set_VL_3712 pass
13753 10:54:59.337750 arm64_za-ptrace_Disabled_ZA_for_VL_3712 skip
13754 10:54:59.337824 arm64_za-ptrace_Get_and_set_data_for_VL_3712 skip
13755 10:54:59.337889 arm64_za-ptrace_Set_VL_3728 pass
13756 10:54:59.338137 arm64_za-ptrace_Disabled_ZA_for_VL_3728 skip
13757 10:54:59.338207 arm64_za-ptrace_Get_and_set_data_for_VL_3728 skip
13758 10:54:59.338281 arm64_za-ptrace_Set_VL_3744 pass
13759 10:54:59.338524 arm64_za-ptrace_Disabled_ZA_for_VL_3744 skip
13760 10:54:59.338590 arm64_za-ptrace_Get_and_set_data_for_VL_3744 skip
13761 10:54:59.338669 arm64_za-ptrace_Set_VL_3760 pass
13762 10:54:59.338746 arm64_za-ptrace_Disabled_ZA_for_VL_3760 skip
13763 10:54:59.338993 arm64_za-ptrace_Get_and_set_data_for_VL_3760 skip
13764 10:54:59.339069 arm64_za-ptrace_Set_VL_3776 pass
13765 10:54:59.339141 arm64_za-ptrace_Disabled_ZA_for_VL_3776 skip
13766 10:54:59.339388 arm64_za-ptrace_Get_and_set_data_for_VL_3776 skip
13767 10:54:59.339465 arm64_za-ptrace_Set_VL_3792 pass
13768 10:54:59.343768 arm64_za-ptrace_Disabled_ZA_for_VL_3792 skip
13769 10:54:59.344047 arm64_za-ptrace_Get_and_set_data_for_VL_3792 skip
13770 10:54:59.344124 arm64_za-ptrace_Set_VL_3808 pass
13771 10:54:59.344189 arm64_za-ptrace_Disabled_ZA_for_VL_3808 skip
13772 10:54:59.344263 arm64_za-ptrace_Get_and_set_data_for_VL_3808 skip
13773 10:54:59.344328 arm64_za-ptrace_Set_VL_3824 pass
13774 10:54:59.344582 arm64_za-ptrace_Disabled_ZA_for_VL_3824 skip
13775 10:54:59.344650 arm64_za-ptrace_Get_and_set_data_for_VL_3824 skip
13776 10:54:59.344725 arm64_za-ptrace_Set_VL_3840 pass
13777 10:54:59.344992 arm64_za-ptrace_Disabled_ZA_for_VL_3840 skip
13778 10:54:59.345072 arm64_za-ptrace_Get_and_set_data_for_VL_3840 skip
13779 10:54:59.345156 arm64_za-ptrace_Set_VL_3856 pass
13780 10:54:59.345222 arm64_za-ptrace_Disabled_ZA_for_VL_3856 skip
13781 10:54:59.345474 arm64_za-ptrace_Get_and_set_data_for_VL_3856 skip
13782 10:54:59.345544 arm64_za-ptrace_Set_VL_3872 pass
13783 10:54:59.345625 arm64_za-ptrace_Disabled_ZA_for_VL_3872 skip
13784 10:54:59.345885 arm64_za-ptrace_Get_and_set_data_for_VL_3872 skip
13785 10:54:59.345954 arm64_za-ptrace_Set_VL_3888 pass
13786 10:54:59.346029 arm64_za-ptrace_Disabled_ZA_for_VL_3888 skip
13787 10:54:59.346111 arm64_za-ptrace_Get_and_set_data_for_VL_3888 skip
13788 10:54:59.346387 arm64_za-ptrace_Set_VL_3904 pass
13789 10:54:59.346471 arm64_za-ptrace_Disabled_ZA_for_VL_3904 skip
13790 10:54:59.346548 arm64_za-ptrace_Get_and_set_data_for_VL_3904 skip
13791 10:54:59.346794 arm64_za-ptrace_Set_VL_3920 pass
13792 10:54:59.346876 arm64_za-ptrace_Disabled_ZA_for_VL_3920 skip
13793 10:54:59.347121 arm64_za-ptrace_Get_and_set_data_for_VL_3920 skip
13794 10:54:59.347189 arm64_za-ptrace_Set_VL_3936 pass
13795 10:54:59.347262 arm64_za-ptrace_Disabled_ZA_for_VL_3936 skip
13796 10:54:59.347504 arm64_za-ptrace_Get_and_set_data_for_VL_3936 skip
13797 10:54:59.347570 arm64_za-ptrace_Set_VL_3952 pass
13798 10:54:59.351802 arm64_za-ptrace_Disabled_ZA_for_VL_3952 skip
13799 10:54:59.352063 arm64_za-ptrace_Get_and_set_data_for_VL_3952 skip
13800 10:54:59.352157 arm64_za-ptrace_Set_VL_3968 pass
13801 10:54:59.352261 arm64_za-ptrace_Disabled_ZA_for_VL_3968 skip
13802 10:54:59.352367 arm64_za-ptrace_Get_and_set_data_for_VL_3968 skip
13803 10:54:59.352477 arm64_za-ptrace_Set_VL_3984 pass
13804 10:54:59.352555 arm64_za-ptrace_Disabled_ZA_for_VL_3984 skip
13805 10:54:59.352635 arm64_za-ptrace_Get_and_set_data_for_VL_3984 skip
13806 10:54:59.352885 arm64_za-ptrace_Set_VL_4000 pass
13807 10:54:59.352966 arm64_za-ptrace_Disabled_ZA_for_VL_4000 skip
13808 10:54:59.353042 arm64_za-ptrace_Get_and_set_data_for_VL_4000 skip
13809 10:54:59.353296 arm64_za-ptrace_Set_VL_4016 pass
13810 10:54:59.353389 arm64_za-ptrace_Disabled_ZA_for_VL_4016 skip
13811 10:54:59.353466 arm64_za-ptrace_Get_and_set_data_for_VL_4016 skip
13812 10:54:59.353567 arm64_za-ptrace_Set_VL_4032 pass
13813 10:54:59.353643 arm64_za-ptrace_Disabled_ZA_for_VL_4032 skip
13814 10:54:59.353921 arm64_za-ptrace_Get_and_set_data_for_VL_4032 skip
13815 10:54:59.354009 arm64_za-ptrace_Set_VL_4048 pass
13816 10:54:59.354255 arm64_za-ptrace_Disabled_ZA_for_VL_4048 skip
13817 10:54:59.354323 arm64_za-ptrace_Get_and_set_data_for_VL_4048 skip
13818 10:54:59.354397 arm64_za-ptrace_Set_VL_4064 pass
13819 10:54:59.354643 arm64_za-ptrace_Disabled_ZA_for_VL_4064 skip
13820 10:54:59.354722 arm64_za-ptrace_Get_and_set_data_for_VL_4064 skip
13821 10:54:59.354786 arm64_za-ptrace_Set_VL_4080 pass
13822 10:54:59.355027 arm64_za-ptrace_Disabled_ZA_for_VL_4080 skip
13823 10:54:59.355096 arm64_za-ptrace_Get_and_set_data_for_VL_4080 skip
13824 10:54:59.355169 arm64_za-ptrace_Set_VL_4096 pass
13825 10:54:59.355417 arm64_za-ptrace_Disabled_ZA_for_VL_4096 skip
13826 10:54:59.355485 arm64_za-ptrace_Get_and_set_data_for_VL_4096 skip
13827 10:54:59.355560 arm64_za-ptrace_Set_VL_4112 pass
13828 10:54:59.360144 arm64_za-ptrace_Disabled_ZA_for_VL_4112 skip
13829 10:54:59.360369 arm64_za-ptrace_Get_and_set_data_for_VL_4112 skip
13830 10:54:59.360463 arm64_za-ptrace_Set_VL_4128 pass
13831 10:54:59.360539 arm64_za-ptrace_Disabled_ZA_for_VL_4128 skip
13832 10:54:59.360628 arm64_za-ptrace_Get_and_set_data_for_VL_4128 skip
13833 10:54:59.360709 arm64_za-ptrace_Set_VL_4144 pass
13834 10:54:59.360782 arm64_za-ptrace_Disabled_ZA_for_VL_4144 skip
13835 10:54:59.360867 arm64_za-ptrace_Get_and_set_data_for_VL_4144 skip
13836 10:54:59.360941 arm64_za-ptrace_Set_VL_4160 pass
13837 10:54:59.361012 arm64_za-ptrace_Disabled_ZA_for_VL_4160 skip
13838 10:54:59.361300 arm64_za-ptrace_Get_and_set_data_for_VL_4160 skip
13839 10:54:59.361395 arm64_za-ptrace_Set_VL_4176 pass
13840 10:54:59.361475 arm64_za-ptrace_Disabled_ZA_for_VL_4176 skip
13841 10:54:59.361551 arm64_za-ptrace_Get_and_set_data_for_VL_4176 skip
13842 10:54:59.361836 arm64_za-ptrace_Set_VL_4192 pass
13843 10:54:59.361932 arm64_za-ptrace_Disabled_ZA_for_VL_4192 skip
13844 10:54:59.362009 arm64_za-ptrace_Get_and_set_data_for_VL_4192 skip
13845 10:54:59.362083 arm64_za-ptrace_Set_VL_4208 pass
13846 10:54:59.362171 arm64_za-ptrace_Disabled_ZA_for_VL_4208 skip
13847 10:54:59.362259 arm64_za-ptrace_Get_and_set_data_for_VL_4208 skip
13848 10:54:59.362333 arm64_za-ptrace_Set_VL_4224 pass
13849 10:54:59.362421 arm64_za-ptrace_Disabled_ZA_for_VL_4224 skip
13850 10:54:59.362511 arm64_za-ptrace_Get_and_set_data_for_VL_4224 skip
13851 10:54:59.362592 arm64_za-ptrace_Set_VL_4240 pass
13852 10:54:59.362687 arm64_za-ptrace_Disabled_ZA_for_VL_4240 skip
13853 10:54:59.362782 arm64_za-ptrace_Get_and_set_data_for_VL_4240 skip
13854 10:54:59.362871 arm64_za-ptrace_Set_VL_4256 pass
13855 10:54:59.363416 arm64_za-ptrace_Disabled_ZA_for_VL_4256 skip
13856 10:54:59.363518 arm64_za-ptrace_Get_and_set_data_for_VL_4256 skip
13857 10:54:59.363599 arm64_za-ptrace_Set_VL_4272 pass
13858 10:54:59.363677 arm64_za-ptrace_Disabled_ZA_for_VL_4272 skip
13859 10:54:59.367885 arm64_za-ptrace_Get_and_set_data_for_VL_4272 skip
13860 10:54:59.368084 arm64_za-ptrace_Set_VL_4288 pass
13861 10:54:59.368462 arm64_za-ptrace_Disabled_ZA_for_VL_4288 skip
13862 10:54:59.368564 arm64_za-ptrace_Get_and_set_data_for_VL_4288 skip
13863 10:54:59.368650 arm64_za-ptrace_Set_VL_4304 pass
13864 10:54:59.368726 arm64_za-ptrace_Disabled_ZA_for_VL_4304 skip
13865 10:54:59.368797 arm64_za-ptrace_Get_and_set_data_for_VL_4304 skip
13866 10:54:59.368868 arm64_za-ptrace_Set_VL_4320 pass
13867 10:54:59.368937 arm64_za-ptrace_Disabled_ZA_for_VL_4320 skip
13868 10:54:59.369016 arm64_za-ptrace_Get_and_set_data_for_VL_4320 skip
13869 10:54:59.369109 arm64_za-ptrace_Set_VL_4336 pass
13870 10:54:59.369182 arm64_za-ptrace_Disabled_ZA_for_VL_4336 skip
13871 10:54:59.369251 arm64_za-ptrace_Get_and_set_data_for_VL_4336 skip
13872 10:54:59.369321 arm64_za-ptrace_Set_VL_4352 pass
13873 10:54:59.369390 arm64_za-ptrace_Disabled_ZA_for_VL_4352 skip
13874 10:54:59.369462 arm64_za-ptrace_Get_and_set_data_for_VL_4352 skip
13875 10:54:59.369534 arm64_za-ptrace_Set_VL_4368 pass
13876 10:54:59.369607 arm64_za-ptrace_Disabled_ZA_for_VL_4368 skip
13877 10:54:59.369712 arm64_za-ptrace_Get_and_set_data_for_VL_4368 skip
13878 10:54:59.369796 arm64_za-ptrace_Set_VL_4384 pass
13879 10:54:59.369872 arm64_za-ptrace_Disabled_ZA_for_VL_4384 skip
13880 10:54:59.369951 arm64_za-ptrace_Get_and_set_data_for_VL_4384 skip
13881 10:54:59.370039 arm64_za-ptrace_Set_VL_4400 pass
13882 10:54:59.370111 arm64_za-ptrace_Disabled_ZA_for_VL_4400 skip
13883 10:54:59.370198 arm64_za-ptrace_Get_and_set_data_for_VL_4400 skip
13884 10:54:59.370274 arm64_za-ptrace_Set_VL_4416 pass
13885 10:54:59.370348 arm64_za-ptrace_Disabled_ZA_for_VL_4416 skip
13886 10:54:59.370423 arm64_za-ptrace_Get_and_set_data_for_VL_4416 skip
13887 10:54:59.370664 arm64_za-ptrace_Set_VL_4432 pass
13888 10:54:59.370756 arm64_za-ptrace_Disabled_ZA_for_VL_4432 skip
13889 10:54:59.370843 arm64_za-ptrace_Get_and_set_data_for_VL_4432 skip
13890 10:54:59.371014 arm64_za-ptrace_Set_VL_4448 pass
13891 10:54:59.371103 arm64_za-ptrace_Disabled_ZA_for_VL_4448 skip
13892 10:54:59.371174 arm64_za-ptrace_Get_and_set_data_for_VL_4448 skip
13893 10:54:59.371258 arm64_za-ptrace_Set_VL_4464 pass
13894 10:54:59.371356 arm64_za-ptrace_Disabled_ZA_for_VL_4464 skip
13895 10:54:59.371443 arm64_za-ptrace_Get_and_set_data_for_VL_4464 skip
13896 10:54:59.371530 arm64_za-ptrace_Set_VL_4480 pass
13897 10:54:59.371607 arm64_za-ptrace_Disabled_ZA_for_VL_4480 skip
13898 10:54:59.371679 arm64_za-ptrace_Get_and_set_data_for_VL_4480 skip
13899 10:54:59.371750 arm64_za-ptrace_Set_VL_4496 pass
13900 10:54:59.371820 arm64_za-ptrace_Disabled_ZA_for_VL_4496 skip
13901 10:54:59.371889 arm64_za-ptrace_Get_and_set_data_for_VL_4496 skip
13902 10:54:59.371959 arm64_za-ptrace_Set_VL_4512 pass
13903 10:54:59.372028 arm64_za-ptrace_Disabled_ZA_for_VL_4512 skip
13904 10:54:59.372113 arm64_za-ptrace_Get_and_set_data_for_VL_4512 skip
13905 10:54:59.372188 arm64_za-ptrace_Set_VL_4528 pass
13906 10:54:59.372453 arm64_za-ptrace_Disabled_ZA_for_VL_4528 skip
13907 10:54:59.375763 arm64_za-ptrace_Get_and_set_data_for_VL_4528 skip
13908 10:54:59.375927 arm64_za-ptrace_Set_VL_4544 pass
13909 10:54:59.376218 arm64_za-ptrace_Disabled_ZA_for_VL_4544 skip
13910 10:54:59.376314 arm64_za-ptrace_Get_and_set_data_for_VL_4544 skip
13911 10:54:59.376388 arm64_za-ptrace_Set_VL_4560 pass
13912 10:54:59.376463 arm64_za-ptrace_Disabled_ZA_for_VL_4560 skip
13913 10:54:59.376536 arm64_za-ptrace_Get_and_set_data_for_VL_4560 skip
13914 10:54:59.376628 arm64_za-ptrace_Set_VL_4576 pass
13915 10:54:59.376705 arm64_za-ptrace_Disabled_ZA_for_VL_4576 skip
13916 10:54:59.376777 arm64_za-ptrace_Get_and_set_data_for_VL_4576 skip
13917 10:54:59.376848 arm64_za-ptrace_Set_VL_4592 pass
13918 10:54:59.376918 arm64_za-ptrace_Disabled_ZA_for_VL_4592 skip
13919 10:54:59.377002 arm64_za-ptrace_Get_and_set_data_for_VL_4592 skip
13920 10:54:59.377079 arm64_za-ptrace_Set_VL_4608 pass
13921 10:54:59.377155 arm64_za-ptrace_Disabled_ZA_for_VL_4608 skip
13922 10:54:59.377237 arm64_za-ptrace_Get_and_set_data_for_VL_4608 skip
13923 10:54:59.377327 arm64_za-ptrace_Set_VL_4624 pass
13924 10:54:59.400477 arm64_za-ptrace_Disabled_ZA_for_VL_4624 skip
13925 10:54:59.400945 arm64_za-ptrace_Get_and_set_data_for_VL_4624 skip
13926 10:54:59.401051 arm64_za-ptrace_Set_VL_4640 pass
13927 10:54:59.401140 arm64_za-ptrace_Disabled_ZA_for_VL_4640 skip
13928 10:54:59.401224 arm64_za-ptrace_Get_and_set_data_for_VL_4640 skip
13929 10:54:59.401306 arm64_za-ptrace_Set_VL_4656 pass
13930 10:54:59.401407 arm64_za-ptrace_Disabled_ZA_for_VL_4656 skip
13931 10:54:59.401492 arm64_za-ptrace_Get_and_set_data_for_VL_4656 skip
13932 10:54:59.401577 arm64_za-ptrace_Set_VL_4672 pass
13933 10:54:59.401668 arm64_za-ptrace_Disabled_ZA_for_VL_4672 skip
13934 10:54:59.401776 arm64_za-ptrace_Get_and_set_data_for_VL_4672 skip
13935 10:54:59.401861 arm64_za-ptrace_Set_VL_4688 pass
13936 10:54:59.401947 arm64_za-ptrace_Disabled_ZA_for_VL_4688 skip
13937 10:54:59.402047 arm64_za-ptrace_Get_and_set_data_for_VL_4688 skip
13938 10:54:59.402150 arm64_za-ptrace_Set_VL_4704 pass
13939 10:54:59.402238 arm64_za-ptrace_Disabled_ZA_for_VL_4704 skip
13940 10:54:59.402339 arm64_za-ptrace_Get_and_set_data_for_VL_4704 skip
13941 10:54:59.402427 arm64_za-ptrace_Set_VL_4720 pass
13942 10:54:59.402529 arm64_za-ptrace_Disabled_ZA_for_VL_4720 skip
13943 10:54:59.402616 arm64_za-ptrace_Get_and_set_data_for_VL_4720 skip
13944 10:54:59.402715 arm64_za-ptrace_Set_VL_4736 pass
13945 10:54:59.402818 arm64_za-ptrace_Disabled_ZA_for_VL_4736 skip
13946 10:54:59.402916 arm64_za-ptrace_Get_and_set_data_for_VL_4736 skip
13947 10:54:59.403018 arm64_za-ptrace_Set_VL_4752 pass
13948 10:54:59.403299 arm64_za-ptrace_Disabled_ZA_for_VL_4752 skip
13949 10:54:59.403395 arm64_za-ptrace_Get_and_set_data_for_VL_4752 skip
13950 10:54:59.403497 arm64_za-ptrace_Set_VL_4768 pass
13951 10:54:59.403596 arm64_za-ptrace_Disabled_ZA_for_VL_4768 skip
13952 10:54:59.407643 arm64_za-ptrace_Get_and_set_data_for_VL_4768 skip
13953 10:54:59.407999 arm64_za-ptrace_Set_VL_4784 pass
13954 10:54:59.408095 arm64_za-ptrace_Disabled_ZA_for_VL_4784 skip
13955 10:54:59.408189 arm64_za-ptrace_Get_and_set_data_for_VL_4784 skip
13956 10:54:59.408268 arm64_za-ptrace_Set_VL_4800 pass
13957 10:54:59.408360 arm64_za-ptrace_Disabled_ZA_for_VL_4800 skip
13958 10:54:59.408453 arm64_za-ptrace_Get_and_set_data_for_VL_4800 skip
13959 10:54:59.408545 arm64_za-ptrace_Set_VL_4816 pass
13960 10:54:59.408636 arm64_za-ptrace_Disabled_ZA_for_VL_4816 skip
13961 10:54:59.408804 arm64_za-ptrace_Get_and_set_data_for_VL_4816 skip
13962 10:54:59.408922 arm64_za-ptrace_Set_VL_4832 pass
13963 10:54:59.409011 arm64_za-ptrace_Disabled_ZA_for_VL_4832 skip
13964 10:54:59.409111 arm64_za-ptrace_Get_and_set_data_for_VL_4832 skip
13965 10:54:59.409313 arm64_za-ptrace_Set_VL_4848 pass
13966 10:54:59.409418 arm64_za-ptrace_Disabled_ZA_for_VL_4848 skip
13967 10:54:59.409523 arm64_za-ptrace_Get_and_set_data_for_VL_4848 skip
13968 10:54:59.409624 arm64_za-ptrace_Set_VL_4864 pass
13969 10:54:59.409719 arm64_za-ptrace_Disabled_ZA_for_VL_4864 skip
13970 10:54:59.409825 arm64_za-ptrace_Get_and_set_data_for_VL_4864 skip
13971 10:54:59.409913 arm64_za-ptrace_Set_VL_4880 pass
13972 10:54:59.410012 arm64_za-ptrace_Disabled_ZA_for_VL_4880 skip
13973 10:54:59.410097 arm64_za-ptrace_Get_and_set_data_for_VL_4880 skip
13974 10:54:59.410195 arm64_za-ptrace_Set_VL_4896 pass
13975 10:54:59.410279 arm64_za-ptrace_Disabled_ZA_for_VL_4896 skip
13976 10:54:59.410375 arm64_za-ptrace_Get_and_set_data_for_VL_4896 skip
13977 10:54:59.410475 arm64_za-ptrace_Set_VL_4912 pass
13978 10:54:59.410570 arm64_za-ptrace_Disabled_ZA_for_VL_4912 skip
13979 10:54:59.410670 arm64_za-ptrace_Get_and_set_data_for_VL_4912 skip
13980 10:54:59.410752 arm64_za-ptrace_Set_VL_4928 pass
13981 10:54:59.410845 arm64_za-ptrace_Disabled_ZA_for_VL_4928 skip
13982 10:54:59.410943 arm64_za-ptrace_Get_and_set_data_for_VL_4928 skip
13983 10:54:59.411035 arm64_za-ptrace_Set_VL_4944 pass
13984 10:54:59.411432 arm64_za-ptrace_Disabled_ZA_for_VL_4944 skip
13985 10:54:59.411538 arm64_za-ptrace_Get_and_set_data_for_VL_4944 skip
13986 10:54:59.411621 arm64_za-ptrace_Set_VL_4960 pass
13987 10:54:59.415643 arm64_za-ptrace_Disabled_ZA_for_VL_4960 skip
13988 10:54:59.415988 arm64_za-ptrace_Get_and_set_data_for_VL_4960 skip
13989 10:54:59.416098 arm64_za-ptrace_Set_VL_4976 pass
13990 10:54:59.416193 arm64_za-ptrace_Disabled_ZA_for_VL_4976 skip
13991 10:54:59.416298 arm64_za-ptrace_Get_and_set_data_for_VL_4976 skip
13992 10:54:59.416392 arm64_za-ptrace_Set_VL_4992 pass
13993 10:54:59.416740 arm64_za-ptrace_Disabled_ZA_for_VL_4992 skip
13994 10:54:59.416839 arm64_za-ptrace_Get_and_set_data_for_VL_4992 skip
13995 10:54:59.416929 arm64_za-ptrace_Set_VL_5008 pass
13996 10:54:59.417018 arm64_za-ptrace_Disabled_ZA_for_VL_5008 skip
13997 10:54:59.417104 arm64_za-ptrace_Get_and_set_data_for_VL_5008 skip
13998 10:54:59.417189 arm64_za-ptrace_Set_VL_5024 pass
13999 10:54:59.417279 arm64_za-ptrace_Disabled_ZA_for_VL_5024 skip
14000 10:54:59.417383 arm64_za-ptrace_Get_and_set_data_for_VL_5024 skip
14001 10:54:59.417473 arm64_za-ptrace_Set_VL_5040 pass
14002 10:54:59.417557 arm64_za-ptrace_Disabled_ZA_for_VL_5040 skip
14003 10:54:59.417640 arm64_za-ptrace_Get_and_set_data_for_VL_5040 skip
14004 10:54:59.417733 arm64_za-ptrace_Set_VL_5056 pass
14005 10:54:59.417815 arm64_za-ptrace_Disabled_ZA_for_VL_5056 skip
14006 10:54:59.417921 arm64_za-ptrace_Get_and_set_data_for_VL_5056 skip
14007 10:54:59.418009 arm64_za-ptrace_Set_VL_5072 pass
14008 10:54:59.418094 arm64_za-ptrace_Disabled_ZA_for_VL_5072 skip
14009 10:54:59.418179 arm64_za-ptrace_Get_and_set_data_for_VL_5072 skip
14010 10:54:59.418264 arm64_za-ptrace_Set_VL_5088 pass
14011 10:54:59.418348 arm64_za-ptrace_Disabled_ZA_for_VL_5088 skip
14012 10:54:59.418452 arm64_za-ptrace_Get_and_set_data_for_VL_5088 skip
14013 10:54:59.418540 arm64_za-ptrace_Set_VL_5104 pass
14014 10:54:59.418625 arm64_za-ptrace_Disabled_ZA_for_VL_5104 skip
14015 10:54:59.418709 arm64_za-ptrace_Get_and_set_data_for_VL_5104 skip
14016 10:54:59.418793 arm64_za-ptrace_Set_VL_5120 pass
14017 10:54:59.418879 arm64_za-ptrace_Disabled_ZA_for_VL_5120 skip
14018 10:54:59.418963 arm64_za-ptrace_Get_and_set_data_for_VL_5120 skip
14019 10:54:59.419043 arm64_za-ptrace_Set_VL_5136 pass
14020 10:54:59.419141 arm64_za-ptrace_Disabled_ZA_for_VL_5136 skip
14021 10:54:59.419229 arm64_za-ptrace_Get_and_set_data_for_VL_5136 skip
14022 10:54:59.419315 arm64_za-ptrace_Set_VL_5152 pass
14023 10:54:59.419399 arm64_za-ptrace_Disabled_ZA_for_VL_5152 skip
14024 10:54:59.419485 arm64_za-ptrace_Get_and_set_data_for_VL_5152 skip
14025 10:54:59.419570 arm64_za-ptrace_Set_VL_5168 pass
14026 10:54:59.419657 arm64_za-ptrace_Disabled_ZA_for_VL_5168 skip
14027 10:54:59.419759 arm64_za-ptrace_Get_and_set_data_for_VL_5168 skip
14028 10:54:59.419851 arm64_za-ptrace_Set_VL_5184 pass
14029 10:54:59.419935 arm64_za-ptrace_Disabled_ZA_for_VL_5184 skip
14030 10:54:59.423695 arm64_za-ptrace_Get_and_set_data_for_VL_5184 skip
14031 10:54:59.424262 arm64_za-ptrace_Set_VL_5200 pass
14032 10:54:59.424482 arm64_za-ptrace_Disabled_ZA_for_VL_5200 skip
14033 10:54:59.424671 arm64_za-ptrace_Get_and_set_data_for_VL_5200 skip
14034 10:54:59.424833 arm64_za-ptrace_Set_VL_5216 pass
14035 10:54:59.425071 arm64_za-ptrace_Disabled_ZA_for_VL_5216 skip
14036 10:54:59.425304 arm64_za-ptrace_Get_and_set_data_for_VL_5216 skip
14037 10:54:59.425568 arm64_za-ptrace_Set_VL_5232 pass
14038 10:54:59.425816 arm64_za-ptrace_Disabled_ZA_for_VL_5232 skip
14039 10:54:59.426009 arm64_za-ptrace_Get_and_set_data_for_VL_5232 skip
14040 10:54:59.426172 arm64_za-ptrace_Set_VL_5248 pass
14041 10:54:59.426362 arm64_za-ptrace_Disabled_ZA_for_VL_5248 skip
14042 10:54:59.426528 arm64_za-ptrace_Get_and_set_data_for_VL_5248 skip
14043 10:54:59.426664 arm64_za-ptrace_Set_VL_5264 pass
14044 10:54:59.426791 arm64_za-ptrace_Disabled_ZA_for_VL_5264 skip
14045 10:54:59.426912 arm64_za-ptrace_Get_and_set_data_for_VL_5264 skip
14046 10:54:59.427035 arm64_za-ptrace_Set_VL_5280 pass
14047 10:54:59.427195 arm64_za-ptrace_Disabled_ZA_for_VL_5280 skip
14048 10:54:59.427323 arm64_za-ptrace_Get_and_set_data_for_VL_5280 skip
14049 10:54:59.427450 arm64_za-ptrace_Set_VL_5296 pass
14050 10:54:59.427567 arm64_za-ptrace_Disabled_ZA_for_VL_5296 skip
14051 10:54:59.427681 arm64_za-ptrace_Get_and_set_data_for_VL_5296 skip
14052 10:54:59.427794 arm64_za-ptrace_Set_VL_5312 pass
14053 10:54:59.427907 arm64_za-ptrace_Disabled_ZA_for_VL_5312 skip
14054 10:54:59.428021 arm64_za-ptrace_Get_and_set_data_for_VL_5312 skip
14055 10:54:59.428134 arm64_za-ptrace_Set_VL_5328 pass
14056 10:54:59.428249 arm64_za-ptrace_Disabled_ZA_for_VL_5328 skip
14057 10:54:59.428365 arm64_za-ptrace_Get_and_set_data_for_VL_5328 skip
14058 10:54:59.428478 arm64_za-ptrace_Set_VL_5344 pass
14059 10:54:59.428591 arm64_za-ptrace_Disabled_ZA_for_VL_5344 skip
14060 10:54:59.428704 arm64_za-ptrace_Get_and_set_data_for_VL_5344 skip
14061 10:54:59.428818 arm64_za-ptrace_Set_VL_5360 pass
14062 10:54:59.428930 arm64_za-ptrace_Disabled_ZA_for_VL_5360 skip
14063 10:54:59.429043 arm64_za-ptrace_Get_and_set_data_for_VL_5360 skip
14064 10:54:59.429156 arm64_za-ptrace_Set_VL_5376 pass
14065 10:54:59.429295 arm64_za-ptrace_Disabled_ZA_for_VL_5376 skip
14066 10:54:59.429414 arm64_za-ptrace_Get_and_set_data_for_VL_5376 skip
14067 10:54:59.429530 arm64_za-ptrace_Set_VL_5392 pass
14068 10:54:59.431703 arm64_za-ptrace_Disabled_ZA_for_VL_5392 skip
14069 10:54:59.431917 arm64_za-ptrace_Get_and_set_data_for_VL_5392 skip
14070 10:54:59.432352 arm64_za-ptrace_Set_VL_5408 pass
14071 10:54:59.432540 arm64_za-ptrace_Disabled_ZA_for_VL_5408 skip
14072 10:54:59.432727 arm64_za-ptrace_Get_and_set_data_for_VL_5408 skip
14073 10:54:59.432905 arm64_za-ptrace_Set_VL_5424 pass
14074 10:54:59.433048 arm64_za-ptrace_Disabled_ZA_for_VL_5424 skip
14075 10:54:59.433200 arm64_za-ptrace_Get_and_set_data_for_VL_5424 skip
14076 10:54:59.433353 arm64_za-ptrace_Set_VL_5440 pass
14077 10:54:59.433545 arm64_za-ptrace_Disabled_ZA_for_VL_5440 skip
14078 10:54:59.433754 arm64_za-ptrace_Get_and_set_data_for_VL_5440 skip
14079 10:54:59.433951 arm64_za-ptrace_Set_VL_5456 pass
14080 10:54:59.434131 arm64_za-ptrace_Disabled_ZA_for_VL_5456 skip
14081 10:54:59.434289 arm64_za-ptrace_Get_and_set_data_for_VL_5456 skip
14082 10:54:59.434446 arm64_za-ptrace_Set_VL_5472 pass
14083 10:54:59.434574 arm64_za-ptrace_Disabled_ZA_for_VL_5472 skip
14084 10:54:59.434688 arm64_za-ptrace_Get_and_set_data_for_VL_5472 skip
14085 10:54:59.434822 arm64_za-ptrace_Set_VL_5488 pass
14086 10:54:59.434979 arm64_za-ptrace_Disabled_ZA_for_VL_5488 skip
14087 10:54:59.435113 arm64_za-ptrace_Get_and_set_data_for_VL_5488 skip
14088 10:54:59.435268 arm64_za-ptrace_Set_VL_5504 pass
14089 10:54:59.435427 arm64_za-ptrace_Disabled_ZA_for_VL_5504 skip
14090 10:54:59.435593 arm64_za-ptrace_Get_and_set_data_for_VL_5504 skip
14091 10:54:59.435715 arm64_za-ptrace_Set_VL_5520 pass
14092 10:54:59.435832 arm64_za-ptrace_Disabled_ZA_for_VL_5520 skip
14093 10:54:59.435951 arm64_za-ptrace_Get_and_set_data_for_VL_5520 skip
14094 10:54:59.436066 arm64_za-ptrace_Set_VL_5536 pass
14095 10:54:59.436181 arm64_za-ptrace_Disabled_ZA_for_VL_5536 skip
14096 10:54:59.436295 arm64_za-ptrace_Get_and_set_data_for_VL_5536 skip
14097 10:54:59.436410 arm64_za-ptrace_Set_VL_5552 pass
14098 10:54:59.436525 arm64_za-ptrace_Disabled_ZA_for_VL_5552 skip
14099 10:54:59.436640 arm64_za-ptrace_Get_and_set_data_for_VL_5552 skip
14100 10:54:59.436754 arm64_za-ptrace_Set_VL_5568 pass
14101 10:54:59.436870 arm64_za-ptrace_Disabled_ZA_for_VL_5568 skip
14102 10:54:59.436986 arm64_za-ptrace_Get_and_set_data_for_VL_5568 skip
14103 10:54:59.437100 arm64_za-ptrace_Set_VL_5584 pass
14104 10:54:59.437214 arm64_za-ptrace_Disabled_ZA_for_VL_5584 skip
14105 10:54:59.437329 arm64_za-ptrace_Get_and_set_data_for_VL_5584 skip
14106 10:54:59.437444 arm64_za-ptrace_Set_VL_5600 pass
14107 10:54:59.437558 arm64_za-ptrace_Disabled_ZA_for_VL_5600 skip
14108 10:54:59.437728 arm64_za-ptrace_Get_and_set_data_for_VL_5600 skip
14109 10:54:59.437947 arm64_za-ptrace_Set_VL_5616 pass
14110 10:54:59.439711 arm64_za-ptrace_Disabled_ZA_for_VL_5616 skip
14111 10:54:59.439885 arm64_za-ptrace_Get_and_set_data_for_VL_5616 skip
14112 10:54:59.440220 arm64_za-ptrace_Set_VL_5632 pass
14113 10:54:59.440348 arm64_za-ptrace_Disabled_ZA_for_VL_5632 skip
14114 10:54:59.440467 arm64_za-ptrace_Get_and_set_data_for_VL_5632 skip
14115 10:54:59.440633 arm64_za-ptrace_Set_VL_5648 pass
14116 10:54:59.457441 arm64_za-ptrace_Disabled_ZA_for_VL_5648 skip
14117 10:54:59.457688 arm64_za-ptrace_Get_and_set_data_for_VL_5648 skip
14118 10:54:59.458136 arm64_za-ptrace_Set_VL_5664 pass
14119 10:54:59.458319 arm64_za-ptrace_Disabled_ZA_for_VL_5664 skip
14120 10:54:59.458495 arm64_za-ptrace_Get_and_set_data_for_VL_5664 skip
14121 10:54:59.458721 arm64_za-ptrace_Set_VL_5680 pass
14122 10:54:59.458929 arm64_za-ptrace_Disabled_ZA_for_VL_5680 skip
14123 10:54:59.459138 arm64_za-ptrace_Get_and_set_data_for_VL_5680 skip
14124 10:54:59.459326 arm64_za-ptrace_Set_VL_5696 pass
14125 10:54:59.459580 arm64_za-ptrace_Disabled_ZA_for_VL_5696 skip
14126 10:54:59.459765 arm64_za-ptrace_Get_and_set_data_for_VL_5696 skip
14127 10:54:59.459907 arm64_za-ptrace_Set_VL_5712 pass
14128 10:54:59.460057 arm64_za-ptrace_Disabled_ZA_for_VL_5712 skip
14129 10:54:59.460262 arm64_za-ptrace_Get_and_set_data_for_VL_5712 skip
14130 10:54:59.460432 arm64_za-ptrace_Set_VL_5728 pass
14131 10:54:59.460619 arm64_za-ptrace_Disabled_ZA_for_VL_5728 skip
14132 10:54:59.460793 arm64_za-ptrace_Get_and_set_data_for_VL_5728 skip
14133 10:54:59.460955 arm64_za-ptrace_Set_VL_5744 pass
14134 10:54:59.461116 arm64_za-ptrace_Disabled_ZA_for_VL_5744 skip
14135 10:54:59.461280 arm64_za-ptrace_Get_and_set_data_for_VL_5744 skip
14136 10:54:59.461487 arm64_za-ptrace_Set_VL_5760 pass
14137 10:54:59.462137 arm64_za-ptrace_Disabled_ZA_for_VL_5760 skip
14138 10:54:59.462335 arm64_za-ptrace_Get_and_set_data_for_VL_5760 skip
14139 10:54:59.462555 arm64_za-ptrace_Set_VL_5776 pass
14140 10:54:59.462741 arm64_za-ptrace_Disabled_ZA_for_VL_5776 skip
14141 10:54:59.462898 arm64_za-ptrace_Get_and_set_data_for_VL_5776 skip
14142 10:54:59.463057 arm64_za-ptrace_Set_VL_5792 pass
14143 10:54:59.463217 arm64_za-ptrace_Disabled_ZA_for_VL_5792 skip
14144 10:54:59.463416 arm64_za-ptrace_Get_and_set_data_for_VL_5792 skip
14145 10:54:59.463552 arm64_za-ptrace_Set_VL_5808 pass
14146 10:54:59.463670 arm64_za-ptrace_Disabled_ZA_for_VL_5808 skip
14147 10:54:59.463830 arm64_za-ptrace_Get_and_set_data_for_VL_5808 skip
14148 10:54:59.463961 arm64_za-ptrace_Set_VL_5824 pass
14149 10:54:59.464076 arm64_za-ptrace_Disabled_ZA_for_VL_5824 skip
14150 10:54:59.464190 arm64_za-ptrace_Get_and_set_data_for_VL_5824 skip
14151 10:54:59.464304 arm64_za-ptrace_Set_VL_5840 pass
14152 10:54:59.464418 arm64_za-ptrace_Disabled_ZA_for_VL_5840 skip
14153 10:54:59.464533 arm64_za-ptrace_Get_and_set_data_for_VL_5840 skip
14154 10:54:59.464647 arm64_za-ptrace_Set_VL_5856 pass
14155 10:54:59.464792 arm64_za-ptrace_Disabled_ZA_for_VL_5856 skip
14156 10:54:59.464915 arm64_za-ptrace_Get_and_set_data_for_VL_5856 skip
14157 10:54:59.465031 arm64_za-ptrace_Set_VL_5872 pass
14158 10:54:59.465148 arm64_za-ptrace_Disabled_ZA_for_VL_5872 skip
14159 10:54:59.465262 arm64_za-ptrace_Get_and_set_data_for_VL_5872 skip
14160 10:54:59.465376 arm64_za-ptrace_Set_VL_5888 pass
14161 10:54:59.465491 arm64_za-ptrace_Disabled_ZA_for_VL_5888 skip
14162 10:54:59.465606 arm64_za-ptrace_Get_and_set_data_for_VL_5888 skip
14163 10:54:59.466062 arm64_za-ptrace_Set_VL_5904 pass
14164 10:54:59.466263 arm64_za-ptrace_Disabled_ZA_for_VL_5904 skip
14165 10:54:59.466449 arm64_za-ptrace_Get_and_set_data_for_VL_5904 skip
14166 10:54:59.466595 arm64_za-ptrace_Set_VL_5920 pass
14167 10:54:59.466740 arm64_za-ptrace_Disabled_ZA_for_VL_5920 skip
14168 10:54:59.466885 arm64_za-ptrace_Get_and_set_data_for_VL_5920 skip
14169 10:54:59.467028 arm64_za-ptrace_Set_VL_5936 pass
14170 10:54:59.467170 arm64_za-ptrace_Disabled_ZA_for_VL_5936 skip
14171 10:54:59.467311 arm64_za-ptrace_Get_and_set_data_for_VL_5936 skip
14172 10:54:59.467693 arm64_za-ptrace_Set_VL_5952 pass
14173 10:54:59.467913 arm64_za-ptrace_Disabled_ZA_for_VL_5952 skip
14174 10:54:59.468073 arm64_za-ptrace_Get_and_set_data_for_VL_5952 skip
14175 10:54:59.468219 arm64_za-ptrace_Set_VL_5968 pass
14176 10:54:59.468388 arm64_za-ptrace_Disabled_ZA_for_VL_5968 skip
14177 10:54:59.468559 arm64_za-ptrace_Get_and_set_data_for_VL_5968 skip
14178 10:54:59.468727 arm64_za-ptrace_Set_VL_5984 pass
14179 10:54:59.468880 arm64_za-ptrace_Disabled_ZA_for_VL_5984 skip
14180 10:54:59.469055 arm64_za-ptrace_Get_and_set_data_for_VL_5984 skip
14181 10:54:59.469214 arm64_za-ptrace_Set_VL_6000 pass
14182 10:54:59.469366 arm64_za-ptrace_Disabled_ZA_for_VL_6000 skip
14183 10:54:59.469532 arm64_za-ptrace_Get_and_set_data_for_VL_6000 skip
14184 10:54:59.469714 arm64_za-ptrace_Set_VL_6016 pass
14185 10:54:59.469918 arm64_za-ptrace_Disabled_ZA_for_VL_6016 skip
14186 10:54:59.470143 arm64_za-ptrace_Get_and_set_data_for_VL_6016 skip
14187 10:54:59.470315 arm64_za-ptrace_Set_VL_6032 pass
14188 10:54:59.470466 arm64_za-ptrace_Disabled_ZA_for_VL_6032 skip
14189 10:54:59.470599 arm64_za-ptrace_Get_and_set_data_for_VL_6032 skip
14190 10:54:59.470751 arm64_za-ptrace_Set_VL_6048 pass
14191 10:54:59.470905 arm64_za-ptrace_Disabled_ZA_for_VL_6048 skip
14192 10:54:59.471054 arm64_za-ptrace_Get_and_set_data_for_VL_6048 skip
14193 10:54:59.471207 arm64_za-ptrace_Set_VL_6064 pass
14194 10:54:59.471401 arm64_za-ptrace_Disabled_ZA_for_VL_6064 skip
14195 10:54:59.471545 arm64_za-ptrace_Get_and_set_data_for_VL_6064 skip
14196 10:54:59.471663 arm64_za-ptrace_Set_VL_6080 pass
14197 10:54:59.471777 arm64_za-ptrace_Disabled_ZA_for_VL_6080 skip
14198 10:54:59.471889 arm64_za-ptrace_Get_and_set_data_for_VL_6080 skip
14199 10:54:59.472006 arm64_za-ptrace_Set_VL_6096 pass
14200 10:54:59.472121 arm64_za-ptrace_Disabled_ZA_for_VL_6096 skip
14201 10:54:59.472233 arm64_za-ptrace_Get_and_set_data_for_VL_6096 skip
14202 10:54:59.472347 arm64_za-ptrace_Set_VL_6112 pass
14203 10:54:59.472461 arm64_za-ptrace_Disabled_ZA_for_VL_6112 skip
14204 10:54:59.472577 arm64_za-ptrace_Get_and_set_data_for_VL_6112 skip
14205 10:54:59.472692 arm64_za-ptrace_Set_VL_6128 pass
14206 10:54:59.472807 arm64_za-ptrace_Disabled_ZA_for_VL_6128 skip
14207 10:54:59.476084 arm64_za-ptrace_Get_and_set_data_for_VL_6128 skip
14208 10:54:59.476274 arm64_za-ptrace_Set_VL_6144 pass
14209 10:54:59.476496 arm64_za-ptrace_Disabled_ZA_for_VL_6144 skip
14210 10:54:59.476950 arm64_za-ptrace_Get_and_set_data_for_VL_6144 skip
14211 10:54:59.477177 arm64_za-ptrace_Set_VL_6160 pass
14212 10:54:59.477395 arm64_za-ptrace_Disabled_ZA_for_VL_6160 skip
14213 10:54:59.477610 arm64_za-ptrace_Get_and_set_data_for_VL_6160 skip
14214 10:54:59.477873 arm64_za-ptrace_Set_VL_6176 pass
14215 10:54:59.478103 arm64_za-ptrace_Disabled_ZA_for_VL_6176 skip
14216 10:54:59.478321 arm64_za-ptrace_Get_and_set_data_for_VL_6176 skip
14217 10:54:59.478551 arm64_za-ptrace_Set_VL_6192 pass
14218 10:54:59.478832 arm64_za-ptrace_Disabled_ZA_for_VL_6192 skip
14219 10:54:59.479034 arm64_za-ptrace_Get_and_set_data_for_VL_6192 skip
14220 10:54:59.479214 arm64_za-ptrace_Set_VL_6208 pass
14221 10:54:59.479384 arm64_za-ptrace_Disabled_ZA_for_VL_6208 skip
14222 10:54:59.479581 arm64_za-ptrace_Get_and_set_data_for_VL_6208 skip
14223 10:54:59.479726 arm64_za-ptrace_Set_VL_6224 pass
14224 10:54:59.479846 arm64_za-ptrace_Disabled_ZA_for_VL_6224 skip
14225 10:54:59.479965 arm64_za-ptrace_Get_and_set_data_for_VL_6224 skip
14226 10:54:59.480082 arm64_za-ptrace_Set_VL_6240 pass
14227 10:54:59.480196 arm64_za-ptrace_Disabled_ZA_for_VL_6240 skip
14228 10:54:59.480312 arm64_za-ptrace_Get_and_set_data_for_VL_6240 skip
14229 10:54:59.480427 arm64_za-ptrace_Set_VL_6256 pass
14230 10:54:59.480542 arm64_za-ptrace_Disabled_ZA_for_VL_6256 skip
14231 10:54:59.480657 arm64_za-ptrace_Get_and_set_data_for_VL_6256 skip
14232 10:54:59.480803 arm64_za-ptrace_Set_VL_6272 pass
14233 10:54:59.480927 arm64_za-ptrace_Disabled_ZA_for_VL_6272 skip
14234 10:54:59.481045 arm64_za-ptrace_Get_and_set_data_for_VL_6272 skip
14235 10:54:59.481161 arm64_za-ptrace_Set_VL_6288 pass
14236 10:54:59.481277 arm64_za-ptrace_Disabled_ZA_for_VL_6288 skip
14237 10:54:59.481394 arm64_za-ptrace_Get_and_set_data_for_VL_6288 skip
14238 10:54:59.481509 arm64_za-ptrace_Set_VL_6304 pass
14239 10:54:59.481624 arm64_za-ptrace_Disabled_ZA_for_VL_6304 skip
14240 10:54:59.483674 arm64_za-ptrace_Get_and_set_data_for_VL_6304 skip
14241 10:54:59.484138 arm64_za-ptrace_Set_VL_6320 pass
14242 10:54:59.484345 arm64_za-ptrace_Disabled_ZA_for_VL_6320 skip
14243 10:54:59.484531 arm64_za-ptrace_Get_and_set_data_for_VL_6320 skip
14244 10:54:59.484705 arm64_za-ptrace_Set_VL_6336 pass
14245 10:54:59.484897 arm64_za-ptrace_Disabled_ZA_for_VL_6336 skip
14246 10:54:59.485056 arm64_za-ptrace_Get_and_set_data_for_VL_6336 skip
14247 10:54:59.485198 arm64_za-ptrace_Set_VL_6352 pass
14248 10:54:59.485356 arm64_za-ptrace_Disabled_ZA_for_VL_6352 skip
14249 10:54:59.485485 arm64_za-ptrace_Get_and_set_data_for_VL_6352 skip
14250 10:54:59.485625 arm64_za-ptrace_Set_VL_6368 pass
14251 10:54:59.485882 arm64_za-ptrace_Disabled_ZA_for_VL_6368 skip
14252 10:54:59.485983 arm64_za-ptrace_Get_and_set_data_for_VL_6368 skip
14253 10:54:59.486073 arm64_za-ptrace_Set_VL_6384 pass
14254 10:54:59.486183 arm64_za-ptrace_Disabled_ZA_for_VL_6384 skip
14255 10:54:59.486281 arm64_za-ptrace_Get_and_set_data_for_VL_6384 skip
14256 10:54:59.486372 arm64_za-ptrace_Set_VL_6400 pass
14257 10:54:59.486451 arm64_za-ptrace_Disabled_ZA_for_VL_6400 skip
14258 10:54:59.486528 arm64_za-ptrace_Get_and_set_data_for_VL_6400 skip
14259 10:54:59.486608 arm64_za-ptrace_Set_VL_6416 pass
14260 10:54:59.486686 arm64_za-ptrace_Disabled_ZA_for_VL_6416 skip
14261 10:54:59.486772 arm64_za-ptrace_Get_and_set_data_for_VL_6416 skip
14262 10:54:59.486889 arm64_za-ptrace_Set_VL_6432 pass
14263 10:54:59.487015 arm64_za-ptrace_Disabled_ZA_for_VL_6432 skip
14264 10:54:59.487150 arm64_za-ptrace_Get_and_set_data_for_VL_6432 skip
14265 10:54:59.487253 arm64_za-ptrace_Set_VL_6448 pass
14266 10:54:59.487343 arm64_za-ptrace_Disabled_ZA_for_VL_6448 skip
14267 10:54:59.487453 arm64_za-ptrace_Get_and_set_data_for_VL_6448 skip
14268 10:54:59.487536 arm64_za-ptrace_Set_VL_6464 pass
14269 10:54:59.487610 arm64_za-ptrace_Disabled_ZA_for_VL_6464 skip
14270 10:54:59.487685 arm64_za-ptrace_Get_and_set_data_for_VL_6464 skip
14271 10:54:59.487746 arm64_za-ptrace_Set_VL_6480 pass
14272 10:54:59.487822 arm64_za-ptrace_Disabled_ZA_for_VL_6480 skip
14273 10:54:59.487889 arm64_za-ptrace_Get_and_set_data_for_VL_6480 skip
14274 10:54:59.487952 arm64_za-ptrace_Set_VL_6496 pass
14275 10:54:59.488011 arm64_za-ptrace_Disabled_ZA_for_VL_6496 skip
14276 10:54:59.491613 arm64_za-ptrace_Get_and_set_data_for_VL_6496 skip
14277 10:54:59.491972 arm64_za-ptrace_Set_VL_6512 pass
14278 10:54:59.492087 arm64_za-ptrace_Disabled_ZA_for_VL_6512 skip
14279 10:54:59.492183 arm64_za-ptrace_Get_and_set_data_for_VL_6512 skip
14280 10:54:59.492301 arm64_za-ptrace_Set_VL_6528 pass
14281 10:54:59.492597 arm64_za-ptrace_Disabled_ZA_for_VL_6528 skip
14282 10:54:59.492706 arm64_za-ptrace_Get_and_set_data_for_VL_6528 skip
14283 10:54:59.492801 arm64_za-ptrace_Set_VL_6544 pass
14284 10:54:59.492907 arm64_za-ptrace_Disabled_ZA_for_VL_6544 skip
14285 10:54:59.492994 arm64_za-ptrace_Get_and_set_data_for_VL_6544 skip
14286 10:54:59.493079 arm64_za-ptrace_Set_VL_6560 pass
14287 10:54:59.493180 arm64_za-ptrace_Disabled_ZA_for_VL_6560 skip
14288 10:54:59.493267 arm64_za-ptrace_Get_and_set_data_for_VL_6560 skip
14289 10:54:59.493368 arm64_za-ptrace_Set_VL_6576 pass
14290 10:54:59.493455 arm64_za-ptrace_Disabled_ZA_for_VL_6576 skip
14291 10:54:59.493555 arm64_za-ptrace_Get_and_set_data_for_VL_6576 skip
14292 10:54:59.493852 arm64_za-ptrace_Set_VL_6592 pass
14293 10:54:59.493957 arm64_za-ptrace_Disabled_ZA_for_VL_6592 skip
14294 10:54:59.494059 arm64_za-ptrace_Get_and_set_data_for_VL_6592 skip
14295 10:54:59.494159 arm64_za-ptrace_Set_VL_6608 pass
14296 10:54:59.494259 arm64_za-ptrace_Disabled_ZA_for_VL_6608 skip
14297 10:54:59.494543 arm64_za-ptrace_Get_and_set_data_for_VL_6608 skip
14298 10:54:59.494648 arm64_za-ptrace_Set_VL_6624 pass
14299 10:54:59.494750 arm64_za-ptrace_Disabled_ZA_for_VL_6624 skip
14300 10:54:59.494836 arm64_za-ptrace_Get_and_set_data_for_VL_6624 skip
14301 10:54:59.494940 arm64_za-ptrace_Set_VL_6640 pass
14302 10:54:59.495040 arm64_za-ptrace_Disabled_ZA_for_VL_6640 skip
14303 10:54:59.495141 arm64_za-ptrace_Get_and_set_data_for_VL_6640 skip
14304 10:54:59.495428 arm64_za-ptrace_Set_VL_6656 pass
14305 10:54:59.495536 arm64_za-ptrace_Disabled_ZA_for_VL_6656 skip
14306 10:54:59.499644 arm64_za-ptrace_Get_and_set_data_for_VL_6656 skip
14307 10:54:59.499948 arm64_za-ptrace_Set_VL_6672 pass
14308 10:54:59.500294 arm64_za-ptrace_Disabled_ZA_for_VL_6672 skip
14309 10:54:59.517240 arm64_za-ptrace_Get_and_set_data_for_VL_6672 skip
14310 10:54:59.517718 arm64_za-ptrace_Set_VL_6688 pass
14311 10:54:59.517921 arm64_za-ptrace_Disabled_ZA_for_VL_6688 skip
14312 10:54:59.518106 arm64_za-ptrace_Get_and_set_data_for_VL_6688 skip
14313 10:54:59.518277 arm64_za-ptrace_Set_VL_6704 pass
14314 10:54:59.518448 arm64_za-ptrace_Disabled_ZA_for_VL_6704 skip
14315 10:54:59.518645 arm64_za-ptrace_Get_and_set_data_for_VL_6704 skip
14316 10:54:59.518808 arm64_za-ptrace_Set_VL_6720 pass
14317 10:54:59.518930 arm64_za-ptrace_Disabled_ZA_for_VL_6720 skip
14318 10:54:59.519048 arm64_za-ptrace_Get_and_set_data_for_VL_6720 skip
14319 10:54:59.519169 arm64_za-ptrace_Set_VL_6736 pass
14320 10:54:59.519314 arm64_za-ptrace_Disabled_ZA_for_VL_6736 skip
14321 10:54:59.519511 arm64_za-ptrace_Get_and_set_data_for_VL_6736 skip
14322 10:54:59.519707 arm64_za-ptrace_Set_VL_6752 pass
14323 10:54:59.519919 arm64_za-ptrace_Disabled_ZA_for_VL_6752 skip
14324 10:54:59.520099 arm64_za-ptrace_Get_and_set_data_for_VL_6752 skip
14325 10:54:59.520273 arm64_za-ptrace_Set_VL_6768 pass
14326 10:54:59.520405 arm64_za-ptrace_Disabled_ZA_for_VL_6768 skip
14327 10:54:59.520574 arm64_za-ptrace_Get_and_set_data_for_VL_6768 skip
14328 10:54:59.520749 arm64_za-ptrace_Set_VL_6784 pass
14329 10:54:59.520882 arm64_za-ptrace_Disabled_ZA_for_VL_6784 skip
14330 10:54:59.521073 arm64_za-ptrace_Get_and_set_data_for_VL_6784 skip
14331 10:54:59.521258 arm64_za-ptrace_Set_VL_6800 pass
14332 10:54:59.521429 arm64_za-ptrace_Disabled_ZA_for_VL_6800 skip
14333 10:54:59.521600 arm64_za-ptrace_Get_and_set_data_for_VL_6800 skip
14334 10:54:59.522490 arm64_za-ptrace_Set_VL_6816 pass
14335 10:54:59.522719 arm64_za-ptrace_Disabled_ZA_for_VL_6816 skip
14336 10:54:59.522921 arm64_za-ptrace_Get_and_set_data_for_VL_6816 skip
14337 10:54:59.523144 arm64_za-ptrace_Set_VL_6832 pass
14338 10:54:59.523347 arm64_za-ptrace_Disabled_ZA_for_VL_6832 skip
14339 10:54:59.523542 arm64_za-ptrace_Get_and_set_data_for_VL_6832 skip
14340 10:54:59.523675 arm64_za-ptrace_Set_VL_6848 pass
14341 10:54:59.523792 arm64_za-ptrace_Disabled_ZA_for_VL_6848 skip
14342 10:54:59.523907 arm64_za-ptrace_Get_and_set_data_for_VL_6848 skip
14343 10:54:59.524023 arm64_za-ptrace_Set_VL_6864 pass
14344 10:54:59.524137 arm64_za-ptrace_Disabled_ZA_for_VL_6864 skip
14345 10:54:59.524251 arm64_za-ptrace_Get_and_set_data_for_VL_6864 skip
14346 10:54:59.524365 arm64_za-ptrace_Set_VL_6880 pass
14347 10:54:59.524478 arm64_za-ptrace_Disabled_ZA_for_VL_6880 skip
14348 10:54:59.524592 arm64_za-ptrace_Get_and_set_data_for_VL_6880 skip
14349 10:54:59.524705 arm64_za-ptrace_Set_VL_6896 pass
14350 10:54:59.524818 arm64_za-ptrace_Disabled_ZA_for_VL_6896 skip
14351 10:54:59.524932 arm64_za-ptrace_Get_and_set_data_for_VL_6896 skip
14352 10:54:59.525049 arm64_za-ptrace_Set_VL_6912 pass
14353 10:54:59.525164 arm64_za-ptrace_Disabled_ZA_for_VL_6912 skip
14354 10:54:59.525513 arm64_za-ptrace_Get_and_set_data_for_VL_6912 skip
14355 10:54:59.525682 arm64_za-ptrace_Set_VL_6928 pass
14356 10:54:59.525811 arm64_za-ptrace_Disabled_ZA_for_VL_6928 skip
14357 10:54:59.525931 arm64_za-ptrace_Get_and_set_data_for_VL_6928 skip
14358 10:54:59.526050 arm64_za-ptrace_Set_VL_6944 pass
14359 10:54:59.526167 arm64_za-ptrace_Disabled_ZA_for_VL_6944 skip
14360 10:54:59.526284 arm64_za-ptrace_Get_and_set_data_for_VL_6944 skip
14361 10:54:59.526401 arm64_za-ptrace_Set_VL_6960 pass
14362 10:54:59.526518 arm64_za-ptrace_Disabled_ZA_for_VL_6960 skip
14363 10:54:59.526634 arm64_za-ptrace_Get_and_set_data_for_VL_6960 skip
14364 10:54:59.526750 arm64_za-ptrace_Set_VL_6976 pass
14365 10:54:59.526866 arm64_za-ptrace_Disabled_ZA_for_VL_6976 skip
14366 10:54:59.526985 arm64_za-ptrace_Get_and_set_data_for_VL_6976 skip
14367 10:54:59.527101 arm64_za-ptrace_Set_VL_6992 pass
14368 10:54:59.527217 arm64_za-ptrace_Disabled_ZA_for_VL_6992 skip
14369 10:54:59.527660 arm64_za-ptrace_Get_and_set_data_for_VL_6992 skip
14370 10:54:59.528101 arm64_za-ptrace_Set_VL_7008 pass
14371 10:54:59.528265 arm64_za-ptrace_Disabled_ZA_for_VL_7008 skip
14372 10:54:59.528464 arm64_za-ptrace_Get_and_set_data_for_VL_7008 skip
14373 10:54:59.528677 arm64_za-ptrace_Set_VL_7024 pass
14374 10:54:59.528924 arm64_za-ptrace_Disabled_ZA_for_VL_7024 skip
14375 10:54:59.529107 arm64_za-ptrace_Get_and_set_data_for_VL_7024 skip
14376 10:54:59.529271 arm64_za-ptrace_Set_VL_7040 pass
14377 10:54:59.529427 arm64_za-ptrace_Disabled_ZA_for_VL_7040 skip
14378 10:54:59.529584 arm64_za-ptrace_Get_and_set_data_for_VL_7040 skip
14379 10:54:59.529750 arm64_za-ptrace_Set_VL_7056 pass
14380 10:54:59.529909 arm64_za-ptrace_Disabled_ZA_for_VL_7056 skip
14381 10:54:59.530053 arm64_za-ptrace_Get_and_set_data_for_VL_7056 skip
14382 10:54:59.530210 arm64_za-ptrace_Set_VL_7072 pass
14383 10:54:59.530408 arm64_za-ptrace_Disabled_ZA_for_VL_7072 skip
14384 10:54:59.530582 arm64_za-ptrace_Get_and_set_data_for_VL_7072 skip
14385 10:54:59.530743 arm64_za-ptrace_Set_VL_7088 pass
14386 10:54:59.530903 arm64_za-ptrace_Disabled_ZA_for_VL_7088 skip
14387 10:54:59.531050 arm64_za-ptrace_Get_and_set_data_for_VL_7088 skip
14388 10:54:59.531216 arm64_za-ptrace_Set_VL_7104 pass
14389 10:54:59.531386 arm64_za-ptrace_Disabled_ZA_for_VL_7104 skip
14390 10:54:59.531548 arm64_za-ptrace_Get_and_set_data_for_VL_7104 skip
14391 10:54:59.531672 arm64_za-ptrace_Set_VL_7120 pass
14392 10:54:59.531787 arm64_za-ptrace_Disabled_ZA_for_VL_7120 skip
14393 10:54:59.531903 arm64_za-ptrace_Get_and_set_data_for_VL_7120 skip
14394 10:54:59.532018 arm64_za-ptrace_Set_VL_7136 pass
14395 10:54:59.532134 arm64_za-ptrace_Disabled_ZA_for_VL_7136 skip
14396 10:54:59.532249 arm64_za-ptrace_Get_and_set_data_for_VL_7136 skip
14397 10:54:59.532395 arm64_za-ptrace_Set_VL_7152 pass
14398 10:54:59.532517 arm64_za-ptrace_Disabled_ZA_for_VL_7152 skip
14399 10:54:59.532632 arm64_za-ptrace_Get_and_set_data_for_VL_7152 skip
14400 10:54:59.532748 arm64_za-ptrace_Set_VL_7168 pass
14401 10:54:59.532862 arm64_za-ptrace_Disabled_ZA_for_VL_7168 skip
14402 10:54:59.532976 arm64_za-ptrace_Get_and_set_data_for_VL_7168 skip
14403 10:54:59.533090 arm64_za-ptrace_Set_VL_7184 pass
14404 10:54:59.533202 arm64_za-ptrace_Disabled_ZA_for_VL_7184 skip
14405 10:54:59.533316 arm64_za-ptrace_Get_and_set_data_for_VL_7184 skip
14406 10:54:59.535681 arm64_za-ptrace_Set_VL_7200 pass
14407 10:54:59.536117 arm64_za-ptrace_Disabled_ZA_for_VL_7200 skip
14408 10:54:59.536310 arm64_za-ptrace_Get_and_set_data_for_VL_7200 skip
14409 10:54:59.536522 arm64_za-ptrace_Set_VL_7216 pass
14410 10:54:59.536707 arm64_za-ptrace_Disabled_ZA_for_VL_7216 skip
14411 10:54:59.536872 arm64_za-ptrace_Get_and_set_data_for_VL_7216 skip
14412 10:54:59.537068 arm64_za-ptrace_Set_VL_7232 pass
14413 10:54:59.537241 arm64_za-ptrace_Disabled_ZA_for_VL_7232 skip
14414 10:54:59.537410 arm64_za-ptrace_Get_and_set_data_for_VL_7232 skip
14415 10:54:59.537577 arm64_za-ptrace_Set_VL_7248 pass
14416 10:54:59.537755 arm64_za-ptrace_Disabled_ZA_for_VL_7248 skip
14417 10:54:59.537924 arm64_za-ptrace_Get_and_set_data_for_VL_7248 skip
14418 10:54:59.538094 arm64_za-ptrace_Set_VL_7264 pass
14419 10:54:59.538269 arm64_za-ptrace_Disabled_ZA_for_VL_7264 skip
14420 10:54:59.538420 arm64_za-ptrace_Get_and_set_data_for_VL_7264 skip
14421 10:54:59.538611 arm64_za-ptrace_Set_VL_7280 pass
14422 10:54:59.538799 arm64_za-ptrace_Disabled_ZA_for_VL_7280 skip
14423 10:54:59.538963 arm64_za-ptrace_Get_and_set_data_for_VL_7280 skip
14424 10:54:59.539167 arm64_za-ptrace_Set_VL_7296 pass
14425 10:54:59.539402 arm64_za-ptrace_Disabled_ZA_for_VL_7296 skip
14426 10:54:59.539562 arm64_za-ptrace_Get_and_set_data_for_VL_7296 skip
14427 10:54:59.539685 arm64_za-ptrace_Set_VL_7312 pass
14428 10:54:59.539801 arm64_za-ptrace_Disabled_ZA_for_VL_7312 skip
14429 10:54:59.539916 arm64_za-ptrace_Get_and_set_data_for_VL_7312 skip
14430 10:54:59.540032 arm64_za-ptrace_Set_VL_7328 pass
14431 10:54:59.540148 arm64_za-ptrace_Disabled_ZA_for_VL_7328 skip
14432 10:54:59.540263 arm64_za-ptrace_Get_and_set_data_for_VL_7328 skip
14433 10:54:59.540377 arm64_za-ptrace_Set_VL_7344 pass
14434 10:54:59.540491 arm64_za-ptrace_Disabled_ZA_for_VL_7344 skip
14435 10:54:59.540605 arm64_za-ptrace_Get_and_set_data_for_VL_7344 skip
14436 10:54:59.540719 arm64_za-ptrace_Set_VL_7360 pass
14437 10:54:59.540863 arm64_za-ptrace_Disabled_ZA_for_VL_7360 skip
14438 10:54:59.540986 arm64_za-ptrace_Get_and_set_data_for_VL_7360 skip
14439 10:54:59.541106 arm64_za-ptrace_Set_VL_7376 pass
14440 10:54:59.541222 arm64_za-ptrace_Disabled_ZA_for_VL_7376 skip
14441 10:54:59.541336 arm64_za-ptrace_Get_and_set_data_for_VL_7376 skip
14442 10:54:59.541450 arm64_za-ptrace_Set_VL_7392 pass
14443 10:54:59.541565 arm64_za-ptrace_Disabled_ZA_for_VL_7392 skip
14444 10:54:59.541742 arm64_za-ptrace_Get_and_set_data_for_VL_7392 skip
14445 10:54:59.543624 arm64_za-ptrace_Set_VL_7408 pass
14446 10:54:59.543973 arm64_za-ptrace_Disabled_ZA_for_VL_7408 skip
14447 10:54:59.544077 arm64_za-ptrace_Get_and_set_data_for_VL_7408 skip
14448 10:54:59.544166 arm64_za-ptrace_Set_VL_7424 pass
14449 10:54:59.544268 arm64_za-ptrace_Disabled_ZA_for_VL_7424 skip
14450 10:54:59.544361 arm64_za-ptrace_Get_and_set_data_for_VL_7424 skip
14451 10:54:59.544446 arm64_za-ptrace_Set_VL_7440 pass
14452 10:54:59.544545 arm64_za-ptrace_Disabled_ZA_for_VL_7440 skip
14453 10:54:59.544647 arm64_za-ptrace_Get_and_set_data_for_VL_7440 skip
14454 10:54:59.544748 arm64_za-ptrace_Set_VL_7456 pass
14455 10:54:59.544846 arm64_za-ptrace_Disabled_ZA_for_VL_7456 skip
14456 10:54:59.544945 arm64_za-ptrace_Get_and_set_data_for_VL_7456 skip
14457 10:54:59.545044 arm64_za-ptrace_Set_VL_7472 pass
14458 10:54:59.545339 arm64_za-ptrace_Disabled_ZA_for_VL_7472 skip
14459 10:54:59.545444 arm64_za-ptrace_Get_and_set_data_for_VL_7472 skip
14460 10:54:59.545548 arm64_za-ptrace_Set_VL_7488 pass
14461 10:54:59.545635 arm64_za-ptrace_Disabled_ZA_for_VL_7488 skip
14462 10:54:59.545748 arm64_za-ptrace_Get_and_set_data_for_VL_7488 skip
14463 10:54:59.545849 arm64_za-ptrace_Set_VL_7504 pass
14464 10:54:59.546146 arm64_za-ptrace_Disabled_ZA_for_VL_7504 skip
14465 10:54:59.546248 arm64_za-ptrace_Get_and_set_data_for_VL_7504 skip
14466 10:54:59.546350 arm64_za-ptrace_Set_VL_7520 pass
14467 10:54:59.546635 arm64_za-ptrace_Disabled_ZA_for_VL_7520 skip
14468 10:54:59.546739 arm64_za-ptrace_Get_and_set_data_for_VL_7520 skip
14469 10:54:59.546825 arm64_za-ptrace_Set_VL_7536 pass
14470 10:54:59.546924 arm64_za-ptrace_Disabled_ZA_for_VL_7536 skip
14471 10:54:59.547022 arm64_za-ptrace_Get_and_set_data_for_VL_7536 skip
14472 10:54:59.547109 arm64_za-ptrace_Set_VL_7552 pass
14473 10:54:59.547208 arm64_za-ptrace_Disabled_ZA_for_VL_7552 skip
14474 10:54:59.547307 arm64_za-ptrace_Get_and_set_data_for_VL_7552 skip
14475 10:54:59.547611 arm64_za-ptrace_Set_VL_7568 pass
14476 10:54:59.555623 arm64_za-ptrace_Disabled_ZA_for_VL_7568 skip
14477 10:54:59.556039 arm64_za-ptrace_Get_and_set_data_for_VL_7568 skip
14478 10:54:59.556212 arm64_za-ptrace_Set_VL_7584 pass
14479 10:54:59.556377 arm64_za-ptrace_Disabled_ZA_for_VL_7584 skip
14480 10:54:59.556559 arm64_za-ptrace_Get_and_set_data_for_VL_7584 skip
14481 10:54:59.556706 arm64_za-ptrace_Set_VL_7600 pass
14482 10:54:59.556851 arm64_za-ptrace_Disabled_ZA_for_VL_7600 skip
14483 10:54:59.556981 arm64_za-ptrace_Get_and_set_data_for_VL_7600 skip
14484 10:54:59.557131 arm64_za-ptrace_Set_VL_7616 pass
14485 10:54:59.557234 arm64_za-ptrace_Disabled_ZA_for_VL_7616 skip
14486 10:54:59.557325 arm64_za-ptrace_Get_and_set_data_for_VL_7616 skip
14487 10:54:59.557445 arm64_za-ptrace_Set_VL_7632 pass
14488 10:54:59.557587 arm64_za-ptrace_Disabled_ZA_for_VL_7632 skip
14489 10:54:59.557765 arm64_za-ptrace_Get_and_set_data_for_VL_7632 skip
14490 10:54:59.557915 arm64_za-ptrace_Set_VL_7648 pass
14491 10:54:59.558050 arm64_za-ptrace_Disabled_ZA_for_VL_7648 skip
14492 10:54:59.558162 arm64_za-ptrace_Get_and_set_data_for_VL_7648 skip
14493 10:54:59.558289 arm64_za-ptrace_Set_VL_7664 pass
14494 10:54:59.558420 arm64_za-ptrace_Disabled_ZA_for_VL_7664 skip
14495 10:54:59.558559 arm64_za-ptrace_Get_and_set_data_for_VL_7664 skip
14496 10:54:59.558663 arm64_za-ptrace_Set_VL_7680 pass
14497 10:54:59.558807 arm64_za-ptrace_Disabled_ZA_for_VL_7680 skip
14498 10:54:59.558937 arm64_za-ptrace_Get_and_set_data_for_VL_7680 skip
14499 10:54:59.559051 arm64_za-ptrace_Set_VL_7696 pass
14500 10:54:59.559158 arm64_za-ptrace_Disabled_ZA_for_VL_7696 skip
14501 10:54:59.587640 arm64_za-ptrace_Get_and_set_data_for_VL_7696 skip
14502 10:54:59.587863 arm64_za-ptrace_Set_VL_7712 pass
14503 10:54:59.588251 arm64_za-ptrace_Disabled_ZA_for_VL_7712 skip
14504 10:54:59.588386 arm64_za-ptrace_Get_and_set_data_for_VL_7712 skip
14505 10:54:59.588550 arm64_za-ptrace_Set_VL_7728 pass
14506 10:54:59.588707 arm64_za-ptrace_Disabled_ZA_for_VL_7728 skip
14507 10:54:59.588848 arm64_za-ptrace_Get_and_set_data_for_VL_7728 skip
14508 10:54:59.589005 arm64_za-ptrace_Set_VL_7744 pass
14509 10:54:59.589166 arm64_za-ptrace_Disabled_ZA_for_VL_7744 skip
14510 10:54:59.589298 arm64_za-ptrace_Get_and_set_data_for_VL_7744 skip
14511 10:54:59.589425 arm64_za-ptrace_Set_VL_7760 pass
14512 10:54:59.589545 arm64_za-ptrace_Disabled_ZA_for_VL_7760 skip
14513 10:54:59.589675 arm64_za-ptrace_Get_and_set_data_for_VL_7760 skip
14514 10:54:59.589795 arm64_za-ptrace_Set_VL_7776 pass
14515 10:54:59.589917 arm64_za-ptrace_Disabled_ZA_for_VL_7776 skip
14516 10:54:59.590026 arm64_za-ptrace_Get_and_set_data_for_VL_7776 skip
14517 10:54:59.590146 arm64_za-ptrace_Set_VL_7792 pass
14518 10:54:59.590264 arm64_za-ptrace_Disabled_ZA_for_VL_7792 skip
14519 10:54:59.590405 arm64_za-ptrace_Get_and_set_data_for_VL_7792 skip
14520 10:54:59.590524 arm64_za-ptrace_Set_VL_7808 pass
14521 10:54:59.590634 arm64_za-ptrace_Disabled_ZA_for_VL_7808 skip
14522 10:54:59.590795 arm64_za-ptrace_Get_and_set_data_for_VL_7808 skip
14523 10:54:59.590916 arm64_za-ptrace_Set_VL_7824 pass
14524 10:54:59.591068 arm64_za-ptrace_Disabled_ZA_for_VL_7824 skip
14525 10:54:59.591228 arm64_za-ptrace_Get_and_set_data_for_VL_7824 skip
14526 10:54:59.591376 arm64_za-ptrace_Set_VL_7840 pass
14527 10:54:59.591523 arm64_za-ptrace_Disabled_ZA_for_VL_7840 skip
14528 10:54:59.591637 arm64_za-ptrace_Get_and_set_data_for_VL_7840 skip
14529 10:54:59.591727 arm64_za-ptrace_Set_VL_7856 pass
14530 10:54:59.591839 arm64_za-ptrace_Disabled_ZA_for_VL_7856 skip
14531 10:54:59.591930 arm64_za-ptrace_Get_and_set_data_for_VL_7856 skip
14532 10:54:59.592017 arm64_za-ptrace_Set_VL_7872 pass
14533 10:54:59.592106 arm64_za-ptrace_Disabled_ZA_for_VL_7872 skip
14534 10:54:59.592193 arm64_za-ptrace_Get_and_set_data_for_VL_7872 skip
14535 10:54:59.592277 arm64_za-ptrace_Set_VL_7888 pass
14536 10:54:59.592364 arm64_za-ptrace_Disabled_ZA_for_VL_7888 skip
14537 10:54:59.592448 arm64_za-ptrace_Get_and_set_data_for_VL_7888 skip
14538 10:54:59.592534 arm64_za-ptrace_Set_VL_7904 pass
14539 10:54:59.592620 arm64_za-ptrace_Disabled_ZA_for_VL_7904 skip
14540 10:54:59.595875 arm64_za-ptrace_Get_and_set_data_for_VL_7904 skip
14541 10:54:59.596211 arm64_za-ptrace_Set_VL_7920 pass
14542 10:54:59.596362 arm64_za-ptrace_Disabled_ZA_for_VL_7920 skip
14543 10:54:59.596483 arm64_za-ptrace_Get_and_set_data_for_VL_7920 skip
14544 10:54:59.596622 arm64_za-ptrace_Set_VL_7936 pass
14545 10:54:59.596740 arm64_za-ptrace_Disabled_ZA_for_VL_7936 skip
14546 10:54:59.596855 arm64_za-ptrace_Get_and_set_data_for_VL_7936 skip
14547 10:54:59.596968 arm64_za-ptrace_Set_VL_7952 pass
14548 10:54:59.597083 arm64_za-ptrace_Disabled_ZA_for_VL_7952 skip
14549 10:54:59.597227 arm64_za-ptrace_Get_and_set_data_for_VL_7952 skip
14550 10:54:59.597326 arm64_za-ptrace_Set_VL_7968 pass
14551 10:54:59.597415 arm64_za-ptrace_Disabled_ZA_for_VL_7968 skip
14552 10:54:59.597502 arm64_za-ptrace_Get_and_set_data_for_VL_7968 skip
14553 10:54:59.597591 arm64_za-ptrace_Set_VL_7984 pass
14554 10:54:59.597708 arm64_za-ptrace_Disabled_ZA_for_VL_7984 skip
14555 10:54:59.597862 arm64_za-ptrace_Get_and_set_data_for_VL_7984 skip
14556 10:54:59.598020 arm64_za-ptrace_Set_VL_8000 pass
14557 10:54:59.598146 arm64_za-ptrace_Disabled_ZA_for_VL_8000 skip
14558 10:54:59.598279 arm64_za-ptrace_Get_and_set_data_for_VL_8000 skip
14559 10:54:59.598402 arm64_za-ptrace_Set_VL_8016 pass
14560 10:54:59.598533 arm64_za-ptrace_Disabled_ZA_for_VL_8016 skip
14561 10:54:59.598687 arm64_za-ptrace_Get_and_set_data_for_VL_8016 skip
14562 10:54:59.598825 arm64_za-ptrace_Set_VL_8032 pass
14563 10:54:59.598955 arm64_za-ptrace_Disabled_ZA_for_VL_8032 skip
14564 10:54:59.599111 arm64_za-ptrace_Get_and_set_data_for_VL_8032 skip
14565 10:54:59.599246 arm64_za-ptrace_Set_VL_8048 pass
14566 10:54:59.599377 arm64_za-ptrace_Disabled_ZA_for_VL_8048 skip
14567 10:54:59.599507 arm64_za-ptrace_Get_and_set_data_for_VL_8048 skip
14568 10:54:59.599645 arm64_za-ptrace_Set_VL_8064 pass
14569 10:54:59.599794 arm64_za-ptrace_Disabled_ZA_for_VL_8064 skip
14570 10:54:59.599927 arm64_za-ptrace_Get_and_set_data_for_VL_8064 skip
14571 10:54:59.600028 arm64_za-ptrace_Set_VL_8080 pass
14572 10:54:59.600143 arm64_za-ptrace_Disabled_ZA_for_VL_8080 skip
14573 10:54:59.600275 arm64_za-ptrace_Get_and_set_data_for_VL_8080 skip
14574 10:54:59.600407 arm64_za-ptrace_Set_VL_8096 pass
14575 10:54:59.600564 arm64_za-ptrace_Disabled_ZA_for_VL_8096 skip
14576 10:54:59.600703 arm64_za-ptrace_Get_and_set_data_for_VL_8096 skip
14577 10:54:59.600841 arm64_za-ptrace_Set_VL_8112 pass
14578 10:54:59.600977 arm64_za-ptrace_Disabled_ZA_for_VL_8112 skip
14579 10:54:59.603774 arm64_za-ptrace_Get_and_set_data_for_VL_8112 skip
14580 10:54:59.603904 arm64_za-ptrace_Set_VL_8128 pass
14581 10:54:59.604221 arm64_za-ptrace_Disabled_ZA_for_VL_8128 skip
14582 10:54:59.604324 arm64_za-ptrace_Get_and_set_data_for_VL_8128 skip
14583 10:54:59.604414 arm64_za-ptrace_Set_VL_8144 pass
14584 10:54:59.604501 arm64_za-ptrace_Disabled_ZA_for_VL_8144 skip
14585 10:54:59.604588 arm64_za-ptrace_Get_and_set_data_for_VL_8144 skip
14586 10:54:59.604675 arm64_za-ptrace_Set_VL_8160 pass
14587 10:54:59.604782 arm64_za-ptrace_Disabled_ZA_for_VL_8160 skip
14588 10:54:59.604872 arm64_za-ptrace_Get_and_set_data_for_VL_8160 skip
14589 10:54:59.604960 arm64_za-ptrace_Set_VL_8176 pass
14590 10:54:59.605047 arm64_za-ptrace_Disabled_ZA_for_VL_8176 skip
14591 10:54:59.605134 arm64_za-ptrace_Get_and_set_data_for_VL_8176 skip
14592 10:54:59.605221 arm64_za-ptrace_Set_VL_8192 pass
14593 10:54:59.605307 arm64_za-ptrace_Disabled_ZA_for_VL_8192 skip
14594 10:54:59.605414 arm64_za-ptrace_Get_and_set_data_for_VL_8192 skip
14595 10:54:59.605504 arm64_za-ptrace pass
14596 10:54:59.605592 arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_sync_err_mode_and_mmap_memory pass
14597 10:54:59.605726 arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_async_err_mode_and_mmap_memory pass
14598 10:54:59.605855 arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_sync_err_mode_and_mmap_mprotect_memory pass
14599 10:54:59.605953 arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_async_err_mode_and_mmap_mprotect_memory pass
14600 10:54:59.606069 arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_sync_mode_and_mmap_memory fail
14601 10:54:59.606166 arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_async_mode_and_mmap_memory fail
14602 10:54:59.606475 arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_tag_check_fault_ignore_and_mmap_memory pass
14603 10:54:59.606582 arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_sync_mode_and_mmap_memory pass
14604 10:54:59.606960 arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_async_mode_and_mmap_memory pass
14605 10:54:59.607146 arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_tag_check_fault_ignore_and_mmap_memory pass
14606 10:54:59.607339 arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_sync_mode_and_mmap_memory fail
14607 10:54:59.607515 arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_async_mode_and_mmap_memory fail
14608 10:54:59.611738 arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_tag_fault_ignore_mode_and_mmap_memory pass
14609 10:54:59.612189 arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_sync_mode_and_mmap_memory fail
14610 10:54:59.612398 arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_async_mode_and_mmap_memory fail
14611 10:54:59.612643 arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_tag_fault_ignore_and_mmap_memory pass
14612 10:54:59.612818 arm64_check_buffer_fill_Check_initial_tags_with_private_mapping_sync_error_mode_and_mmap_memory pass
14613 10:54:59.613054 arm64_check_buffer_fill_Check_initial_tags_with_private_mapping_sync_error_mode_and_mmap_mprotect_memory pass
14614 10:54:59.613225 arm64_check_buffer_fill_Check_initial_tags_with_shared_mapping_sync_error_mode_and_mmap_memory pass
14615 10:54:59.613447 arm64_check_buffer_fill_Check_initial_tags_with_shared_mapping_sync_error_mode_and_mmap_mprotect_memory pass
14616 10:54:59.613637 arm64_check_buffer_fill fail
14617 10:54:59.613944 arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_precise_mode_and_mmap_memory fail
14618 10:54:59.614098 arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_precise_mode_and_mmap_memory fail
14619 10:54:59.614291 arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_imprecise_mode_and_mmap_memory fail
14620 10:54:59.614479 arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_imprecise_mode_and_mmap_memory fail
14621 10:54:59.614667 arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_precise_mode_and_mmap_mprotect_memory fail
14622 10:54:59.615071 arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_precise_mode_and_mmap_mprotect_memory fail
14623 10:54:59.615180 arm64_check_child_memory_Check_child_file_memory_with_private_mapping_precise_mode_and_mmap_memory fail
14624 10:54:59.615489 arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_precise_mode_and_mmap_memory fail
14625 10:54:59.619672 arm64_check_child_memory_Check_child_file_memory_with_private_mapping_imprecise_mode_and_mmap_memory fail
14626 10:54:59.620178 arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_imprecise_mode_and_mmap_memory fail
14627 10:54:59.620356 arm64_check_child_memory_Check_child_file_memory_with_private_mapping_precise_mode_and_mmap_mprotect_memory fail
14628 10:54:59.620562 arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_precise_mode_and_mmap_mprotect_memory fail
14629 10:54:59.620760 arm64_check_child_memory fail
14630 10:54:59.621187 arm64_check_gcr_el1_cswitch fail
14631 10:54:59.621386 arm64_check_ksm_options fail
14632 10:54:59.621559 arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_off pass
14633 10:54:59.621741 arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_off pass
14634 10:54:59.621879 arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_no_error_mode_mmap_memory_and_tag_check_off pass
14635 10:54:59.622023 arm64_check_mmap_options_Check_file_memory_with_private_mapping_no_error_mode_mmap_mprotect_memory_and_tag_check_off pass
14636 10:54:59.622168 arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_on fail
14637 10:54:59.630723 arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on fail
14638 10:54:59.631237 arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_sync_error_mode_mmap_memory_and_tag_check_on fail
14639 10:54:59.631346 arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on fail
14640 10:54:59.631455 arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_async_error_mode_mmap_memory_and_tag_check_on fail
14641 10:54:59.631997 arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on fail
14642 10:54:59.632245 arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_async_error_mode_mmap_memory_and_tag_check_on fail
14643 10:54:59.632575 arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on fail
14644 10:54:59.632789 arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_on fail
14645 10:54:59.633174 arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on fail
14646 10:54:59.633286 arm64_check_mmap_options_Check_file_memory_with_shared_mapping_sync_error_mode_mmap_memory_and_tag_check_on fail
14647 10:54:59.633368 arm64_check_mmap_options_Check_file_memory_with_shared_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on fail
14648 10:54:59.633641 arm64_check_mmap_options_Check_file_memory_with_private_mapping_async_error_mode_mmap_memory_and_tag_check_on fail
14649 10:54:59.634218 arm64_check_mmap_options_Check_file_memory_with_private_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on fail
14650 10:54:59.634319 arm64_check_mmap_options_Check_file_memory_with_shared_mapping_async_error_mode_mmap_memory_and_tag_check_on fail
14651 10:54:59.634423 arm64_check_mmap_options_Check_file_memory_with_shared_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on fail
14652 10:54:59.634726 arm64_check_mmap_options_Check_clear_PROT_MTE_flags_with_private_mapping_sync_error_mode_and_mmap_memory fail
14653 10:54:59.635080 arm64_check_mmap_options_Check_clear_PROT_MTE_flags_with_private_mapping_and_sync_error_mode_and_mmap_mprotect_memory fail
14654 10:54:59.635177 arm64_check_mmap_options fail
14655 10:54:59.635470 arm64_check_prctl_check_basic_read pass
14656 10:54:59.635574 arm64_check_prctl_NONE pass
14657 10:54:59.635657 arm64_check_prctl_SYNC pass
14658 10:54:59.635736 arm64_check_prctl_ASYNC pass
14659 10:54:59.635815 arm64_check_prctl_SYNC_ASYNC pass
14660 10:54:59.635895 arm64_check_prctl pass
14661 10:54:59.639694 arm64_check_tags_inclusion_Check_an_included_tag_value_with_sync_mode fail
14662 10:54:59.640076 arm64_check_tags_inclusion_Check_different_included_tags_value_with_sync_mode fail
14663 10:54:59.640182 arm64_check_tags_inclusion_Check_none_included_tags_value_with_sync_mode pass
14664 10:54:59.640276 arm64_check_tags_inclusion_Check_all_included_tags_value_with_sync_mode fail
14665 10:54:59.640559 arm64_check_tags_inclusion fail
14666 10:54:59.640649 arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 pass
14667 10:54:59.640739 arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 pass
14668 10:54:59.640815 arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 pass
14669 10:54:59.640912 arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 pass
14670 10:54:59.641206 arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 pass
14671 10:54:59.641295 arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 pass
14672 10:54:59.641380 arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 pass
14673 10:54:59.641466 arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 pass
14674 10:54:59.641755 arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 pass
14675 10:54:59.641861 arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 pass
14676 10:54:59.641958 arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 pass
14677 10:54:59.642308 arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 pass
14678 10:54:59.642531 arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 pass
14679 10:54:59.642718 arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 pass
14680 10:54:59.642916 arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 pass
14681 10:54:59.643124 arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 pass
14682 10:54:59.643297 arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 pass
14683 10:54:59.643481 arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 pass
14684 10:54:59.643608 arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 pass
14685 10:54:59.647623 arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 pass
14686 10:54:59.647951 arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 pass
14687 10:54:59.648152 arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 pass
14688 10:54:59.648436 arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 pass
14689 10:54:59.648538 arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 pass
14690 10:54:59.648856 arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 pass
14691 10:54:59.648971 arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 pass
14692 10:54:59.649268 arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 pass
14693 10:54:59.649418 arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 pass
14694 10:54:59.649580 arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 pass
14695 10:54:59.649901 arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 pass
14696 10:54:59.650020 arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 pass
14697 10:54:59.650151 arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 pass
14698 10:54:59.650465 arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 pass
14699 10:54:59.650624 arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 pass
14700 10:54:59.651002 arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 pass
14701 10:54:59.651104 arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 pass
14702 10:54:59.651401 arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 pass
14703 10:54:59.651535 arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 pass
14704 10:54:59.655735 arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 pass
14705 10:54:59.656185 arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 pass
14706 10:54:59.656371 arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 pass
14707 10:54:59.656530 arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 pass
14708 10:54:59.656675 arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 pass
14709 10:54:59.656836 arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 pass
14710 10:54:59.657017 arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 pass
14711 10:54:59.657198 arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 pass
14712 10:54:59.657364 arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 pass
14713 10:54:59.657849 arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 pass
14714 10:54:59.658035 arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 pass
14715 10:54:59.658418 arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 pass
14716 10:54:59.658521 arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 pass
14717 10:54:59.658610 arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 pass
14718 10:54:59.658710 arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 pass
14719 10:54:59.658825 arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 pass
14720 10:54:59.658938 arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 pass
14721 10:54:59.659233 arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 pass
14722 10:54:59.659352 arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 pass
14723 10:54:59.659647 arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 pass
14724 10:54:59.663877 arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 pass
14725 10:54:59.664278 arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 pass
14726 10:54:59.664388 arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 pass
14727 10:54:59.664687 arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 pass
14728 10:54:59.683396 arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 pass
14729 10:54:59.683625 arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 pass
14730 10:54:59.683715 arm64_check_user_mem pass
14731 10:54:59.684012 arm64_btitest_nohint_func_call_using_br_x0 pass
14732 10:54:59.684112 arm64_btitest_nohint_func_call_using_br_x16 pass
14733 10:54:59.684194 arm64_btitest_nohint_func_call_using_blr pass
14734 10:54:59.684278 arm64_btitest_bti_none_func_call_using_br_x0 pass
14735 10:54:59.684356 arm64_btitest_bti_none_func_call_using_br_x16 pass
14736 10:54:59.684434 arm64_btitest_bti_none_func_call_using_blr pass
14737 10:54:59.684529 arm64_btitest_bti_c_func_call_using_br_x0 pass
14738 10:54:59.684610 arm64_btitest_bti_c_func_call_using_br_x16 pass
14739 10:54:59.684687 arm64_btitest_bti_c_func_call_using_blr pass
14740 10:54:59.684764 arm64_btitest_bti_j_func_call_using_br_x0 pass
14741 10:54:59.684842 arm64_btitest_bti_j_func_call_using_br_x16 pass
14742 10:54:59.684935 arm64_btitest_bti_j_func_call_using_blr pass
14743 10:54:59.685015 arm64_btitest_bti_jc_func_call_using_br_x0 pass
14744 10:54:59.685093 arm64_btitest_bti_jc_func_call_using_br_x16 pass
14745 10:54:59.685170 arm64_btitest_bti_jc_func_call_using_blr pass
14746 10:54:59.685263 arm64_btitest_paciasp_func_call_using_br_x0 pass
14747 10:54:59.685343 arm64_btitest_paciasp_func_call_using_br_x16 pass
14748 10:54:59.685421 arm64_btitest_paciasp_func_call_using_blr pass
14749 10:54:59.685513 arm64_btitest pass
14750 10:54:59.685593 arm64_nobtitest_nohint_func_call_using_br_x0 pass
14751 10:54:59.685698 arm64_nobtitest_nohint_func_call_using_br_x16 pass
14752 10:54:59.685780 arm64_nobtitest_nohint_func_call_using_blr pass
14753 10:54:59.685870 arm64_nobtitest_bti_none_func_call_using_br_x0 pass
14754 10:54:59.685963 arm64_nobtitest_bti_none_func_call_using_br_x16 pass
14755 10:54:59.686043 arm64_nobtitest_bti_none_func_call_using_blr pass
14756 10:54:59.686134 arm64_nobtitest_bti_c_func_call_using_br_x0 pass
14757 10:54:59.686423 arm64_nobtitest_bti_c_func_call_using_br_x16 pass
14758 10:54:59.686524 arm64_nobtitest_bti_c_func_call_using_blr pass
14759 10:54:59.686608 arm64_nobtitest_bti_j_func_call_using_br_x0 pass
14760 10:54:59.686682 arm64_nobtitest_bti_j_func_call_using_br_x16 pass
14761 10:54:59.686760 arm64_nobtitest_bti_j_func_call_using_blr pass
14762 10:54:59.686826 arm64_nobtitest_bti_jc_func_call_using_br_x0 pass
14763 10:54:59.686904 arm64_nobtitest_bti_jc_func_call_using_br_x16 pass
14764 10:54:59.687130 arm64_nobtitest_bti_jc_func_call_using_blr pass
14765 10:54:59.687230 arm64_nobtitest_paciasp_func_call_using_br_x0 pass
14766 10:54:59.687325 arm64_nobtitest_paciasp_func_call_using_br_x16 pass
14767 10:54:59.687405 arm64_nobtitest_paciasp_func_call_using_blr pass
14768 10:54:59.687496 arm64_nobtitest pass
14769 10:54:59.691807 arm64_hwcap_cpuinfo_match_RNG pass
14770 10:54:59.692217 arm64_hwcap_sigill_RNG pass
14771 10:54:59.692316 arm64_hwcap_cpuinfo_match_SME pass
14772 10:54:59.692399 arm64_hwcap_sigill_SME pass
14773 10:54:59.692478 arm64_hwcap_cpuinfo_match_SVE pass
14774 10:54:59.692556 arm64_hwcap_sigill_SVE pass
14775 10:54:59.692635 arm64_hwcap_cpuinfo_match_SVE_2 pass
14776 10:54:59.692728 arm64_hwcap_sigill_SVE_2 pass
14777 10:54:59.692809 arm64_hwcap_cpuinfo_match_SVE_AES pass
14778 10:54:59.692888 arm64_hwcap_sigill_SVE_AES pass
14779 10:54:59.692964 arm64_hwcap_cpuinfo_match_SVE2_PMULL pass
14780 10:54:59.693042 arm64_hwcap_sigill_SVE2_PMULL pass
14781 10:54:59.693134 arm64_hwcap_cpuinfo_match_SVE2_BITPERM pass
14782 10:54:59.693213 arm64_hwcap_sigill_SVE2_BITPERM pass
14783 10:54:59.693291 arm64_hwcap_cpuinfo_match_SVE2_SHA3 pass
14784 10:54:59.693368 arm64_hwcap_sigill_SVE2_SHA3 pass
14785 10:54:59.693444 arm64_hwcap_cpuinfo_match_SVE2_SM4 pass
14786 10:54:59.693537 arm64_hwcap_sigill_SVE2_SM4 pass
14787 10:54:59.693617 arm64_hwcap_cpuinfo_match_SVE2_I8MM pass
14788 10:54:59.693707 arm64_hwcap_sigill_SVE2_I8MM pass
14789 10:54:59.693786 arm64_hwcap_cpuinfo_match_SVE2_F32MM pass
14790 10:54:59.693864 arm64_hwcap_sigill_SVE2_F32MM pass
14791 10:54:59.693957 arm64_hwcap_cpuinfo_match_SVE2_F64MM pass
14792 10:54:59.694239 arm64_hwcap_sigill_SVE2_F64MM pass
14793 10:54:59.694335 arm64_hwcap_cpuinfo_match_SVE2_BF16 pass
14794 10:54:59.694409 arm64_hwcap_sigill_SVE2_BF16 pass
14795 10:54:59.694484 arm64_hwcap_cpuinfo_match_SVE2_EBF16 pass
14796 10:54:59.694560 arm64_hwcap_sigill_SVE2_EBF16 skip
14797 10:54:59.694632 arm64_hwcap pass
14798 10:54:59.694718 arm64_ptrace_read_tpidr_one pass
14799 10:54:59.694795 arm64_ptrace_write_tpidr_one pass
14800 10:54:59.694871 arm64_ptrace_verify_tpidr_one pass
14801 10:54:59.694942 arm64_ptrace_count_tpidrs pass
14802 10:54:59.695020 arm64_ptrace_tpidr2_write pass
14803 10:54:59.695112 arm64_ptrace_tpidr2_read pass
14804 10:54:59.695190 arm64_ptrace_write_tpidr_only pass
14805 10:54:59.695263 arm64_ptrace pass
14806 10:54:59.695334 arm64_syscall-abi_getpid_FPSIMD pass
14807 10:54:59.695415 arm64_syscall-abi_getpid_SVE_VL_256 pass
14808 10:54:59.695503 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_SM_ZA pass
14809 10:54:59.695584 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_SM pass
14810 10:54:59.699805 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_ZA pass
14811 10:54:59.700139 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_SM_ZA pass
14812 10:54:59.700234 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_SM pass
14813 10:54:59.700324 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_ZA pass
14814 10:54:59.700406 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_SM_ZA pass
14815 10:54:59.700494 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_SM pass
14816 10:54:59.700587 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_ZA pass
14817 10:54:59.700681 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_SM_ZA pass
14818 10:54:59.700782 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_SM pass
14819 10:54:59.701110 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_ZA pass
14820 10:54:59.701311 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_SM_ZA pass
14821 10:54:59.701489 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_SM pass
14822 10:54:59.701728 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_ZA pass
14823 10:54:59.701903 arm64_syscall-abi_getpid_SVE_VL_240 pass
14824 10:54:59.702067 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_SM_ZA pass
14825 10:54:59.702234 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_SM pass
14826 10:54:59.702430 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_ZA pass
14827 10:54:59.702597 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_SM_ZA pass
14828 10:54:59.702757 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_SM pass
14829 10:54:59.702919 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_ZA pass
14830 10:54:59.703087 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_SM_ZA pass
14831 10:54:59.703251 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_SM pass
14832 10:54:59.703450 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_ZA pass
14833 10:54:59.703584 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_SM_ZA pass
14834 10:54:59.703700 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_SM pass
14835 10:54:59.703813 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_ZA pass
14836 10:54:59.703927 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_SM_ZA pass
14837 10:54:59.704040 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_SM pass
14838 10:54:59.704181 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_ZA pass
14839 10:54:59.704300 arm64_syscall-abi_getpid_SVE_VL_224 pass
14840 10:54:59.704414 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_SM_ZA pass
14841 10:54:59.704527 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_SM pass
14842 10:54:59.707867 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_ZA pass
14843 10:54:59.708159 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_SM_ZA pass
14844 10:54:59.708338 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_SM pass
14845 10:54:59.708771 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_ZA pass
14846 10:54:59.709007 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_SM_ZA pass
14847 10:54:59.709230 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_SM pass
14848 10:54:59.709418 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_ZA pass
14849 10:54:59.709586 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_SM_ZA pass
14850 10:54:59.709759 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_SM pass
14851 10:54:59.709914 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_ZA pass
14852 10:54:59.710074 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_SM_ZA pass
14853 10:54:59.710279 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_SM pass
14854 10:54:59.710453 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_ZA pass
14855 10:54:59.710622 arm64_syscall-abi_getpid_SVE_VL_208 pass
14856 10:54:59.710788 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_SM_ZA pass
14857 10:54:59.710950 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_SM pass
14858 10:54:59.711115 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_ZA pass
14859 10:54:59.711279 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_SM_ZA pass
14860 10:54:59.711451 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_SM pass
14861 10:54:59.711577 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_ZA pass
14862 10:54:59.711693 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_SM_ZA pass
14863 10:54:59.711806 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_SM pass
14864 10:54:59.711920 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_ZA pass
14865 10:54:59.712034 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_SM_ZA pass
14866 10:54:59.712180 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_SM pass
14867 10:54:59.712302 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_ZA pass
14868 10:54:59.712417 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_SM_ZA pass
14869 10:54:59.712532 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_SM pass
14870 10:54:59.712645 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_ZA pass
14871 10:54:59.712763 arm64_syscall-abi_getpid_SVE_VL_192 pass
14872 10:54:59.712877 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_SM_ZA pass
14873 10:54:59.712991 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_SM pass
14874 10:54:59.713103 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_ZA pass
14875 10:54:59.713217 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_SM_ZA pass
14876 10:54:59.713331 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_SM pass
14877 10:54:59.715809 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_ZA pass
14878 10:54:59.715999 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_SM_ZA pass
14879 10:54:59.716247 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_SM pass
14880 10:54:59.716349 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_ZA pass
14881 10:54:59.716438 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_SM_ZA pass
14882 10:54:59.716512 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_SM pass
14883 10:54:59.716604 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_ZA pass
14884 10:54:59.716684 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_SM_ZA pass
14885 10:54:59.716753 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_SM pass
14886 10:54:59.716842 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_ZA pass
14887 10:54:59.716924 arm64_syscall-abi_getpid_SVE_VL_176 pass
14888 10:54:59.717012 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_SM_ZA pass
14889 10:54:59.717285 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_SM pass
14890 10:54:59.717367 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_ZA pass
14891 10:54:59.717448 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_SM_ZA pass
14892 10:54:59.717522 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_SM pass
14893 10:54:59.717776 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_ZA pass
14894 10:54:59.718054 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_SM_ZA pass
14895 10:54:59.718147 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_SM pass
14896 10:54:59.718221 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_ZA pass
14897 10:54:59.718587 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_SM_ZA pass
14898 10:54:59.734354 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_SM pass
14899 10:54:59.734764 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_ZA pass
14900 10:54:59.734846 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_SM_ZA pass
14901 10:54:59.734923 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_SM pass
14902 10:54:59.734998 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_ZA pass
14903 10:54:59.735090 arm64_syscall-abi_getpid_SVE_VL_160 pass
14904 10:54:59.735160 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_SM_ZA pass
14905 10:54:59.735233 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_SM pass
14906 10:54:59.735307 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_ZA pass
14907 10:54:59.735402 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_SM_ZA pass
14908 10:54:59.735474 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_SM pass
14909 10:54:59.735553 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_ZA pass
14910 10:54:59.735643 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_SM_ZA pass
14911 10:54:59.735730 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_SM pass
14912 10:54:59.735997 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_ZA pass
14913 10:54:59.736069 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_SM_ZA pass
14914 10:54:59.736146 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_SM pass
14915 10:54:59.736237 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_ZA pass
14916 10:54:59.736308 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_SM_ZA pass
14917 10:54:59.736397 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_SM pass
14918 10:54:59.736474 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_ZA pass
14919 10:54:59.736750 arm64_syscall-abi_getpid_SVE_VL_144 pass
14920 10:54:59.736849 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_SM_ZA pass
14921 10:54:59.736927 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_SM pass
14922 10:54:59.736999 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_ZA pass
14923 10:54:59.737089 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_SM_ZA pass
14924 10:54:59.737173 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_SM pass
14925 10:54:59.737252 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_ZA pass
14926 10:54:59.737348 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_SM_ZA pass
14927 10:54:59.737429 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_SM pass
14928 10:54:59.737520 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_ZA pass
14929 10:54:59.737892 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_SM_ZA pass
14930 10:54:59.738161 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_SM pass
14931 10:54:59.738240 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_ZA pass
14932 10:54:59.738323 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_SM_ZA pass
14933 10:54:59.738389 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_SM pass
14934 10:54:59.738476 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_ZA pass
14935 10:54:59.738557 arm64_syscall-abi_getpid_SVE_VL_128 pass
14936 10:54:59.738633 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_SM_ZA pass
14937 10:54:59.738724 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_SM pass
14938 10:54:59.738801 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_ZA pass
14939 10:54:59.738895 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_SM_ZA pass
14940 10:54:59.738973 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_SM pass
14941 10:54:59.739036 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_ZA pass
14942 10:54:59.739118 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_SM_ZA pass
14943 10:54:59.739199 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_SM pass
14944 10:54:59.739275 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_ZA pass
14945 10:54:59.739350 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_SM_ZA pass
14946 10:54:59.743619 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_SM pass
14947 10:54:59.743937 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_ZA pass
14948 10:54:59.744062 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_SM_ZA pass
14949 10:54:59.744195 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_SM pass
14950 10:54:59.744357 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_ZA pass
14951 10:54:59.744463 arm64_syscall-abi_getpid_SVE_VL_112 pass
14952 10:54:59.744577 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_SM_ZA pass
14953 10:54:59.744685 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_SM pass
14954 10:54:59.744788 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_ZA pass
14955 10:54:59.744898 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_SM_ZA pass
14956 10:54:59.745024 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_SM pass
14957 10:54:59.745311 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_ZA pass
14958 10:54:59.745401 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_SM_ZA pass
14959 10:54:59.745704 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_SM pass
14960 10:54:59.745807 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_ZA pass
14961 10:54:59.745897 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_SM_ZA pass
14962 10:54:59.746000 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_SM pass
14963 10:54:59.746119 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_ZA pass
14964 10:54:59.746216 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_SM_ZA pass
14965 10:54:59.746313 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_SM pass
14966 10:54:59.746418 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_ZA pass
14967 10:54:59.746534 arm64_syscall-abi_getpid_SVE_VL_96 pass
14968 10:54:59.746615 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_SM_ZA pass
14969 10:54:59.746708 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_SM pass
14970 10:54:59.746803 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_ZA pass
14971 10:54:59.747079 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_SM_ZA pass
14972 10:54:59.747161 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_SM pass
14973 10:54:59.747238 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_ZA pass
14974 10:54:59.747312 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_SM_ZA pass
14975 10:54:59.747408 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_SM pass
14976 10:54:59.751614 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_ZA pass
14977 10:54:59.751945 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_SM_ZA pass
14978 10:54:59.752062 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_SM pass
14979 10:54:59.752199 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_ZA pass
14980 10:54:59.752328 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_SM_ZA pass
14981 10:54:59.752431 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_SM pass
14982 10:54:59.752549 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_ZA pass
14983 10:54:59.752646 arm64_syscall-abi_getpid_SVE_VL_80 pass
14984 10:54:59.752746 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_SM_ZA pass
14985 10:54:59.752868 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_SM pass
14986 10:54:59.752960 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_ZA pass
14987 10:54:59.753078 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_SM_ZA pass
14988 10:54:59.753163 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_SM pass
14989 10:54:59.753280 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_ZA pass
14990 10:54:59.753388 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_SM_ZA pass
14991 10:54:59.753474 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_SM pass
14992 10:54:59.753890 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_ZA pass
14993 10:54:59.753974 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_SM_ZA pass
14994 10:54:59.754219 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_SM pass
14995 10:54:59.754289 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_ZA pass
14996 10:54:59.754353 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_SM_ZA pass
14997 10:54:59.754416 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_SM pass
14998 10:54:59.754496 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_ZA pass
14999 10:54:59.754560 arm64_syscall-abi_getpid_SVE_VL_64 pass
15000 10:54:59.754635 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_SM_ZA pass
15001 10:54:59.754700 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_SM pass
15002 10:54:59.754763 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_ZA pass
15003 10:54:59.754826 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_SM_ZA pass
15004 10:54:59.754900 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_SM pass
15005 10:54:59.754964 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_ZA pass
15006 10:54:59.755407 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_SM_ZA pass
15007 10:54:59.755680 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_SM pass
15008 10:54:59.755760 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_ZA pass
15009 10:54:59.755824 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_SM_ZA pass
15010 10:54:59.755884 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_SM pass
15011 10:54:59.755945 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_ZA pass
15012 10:54:59.759655 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_SM_ZA pass
15013 10:54:59.759936 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_SM pass
15014 10:54:59.760027 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_ZA pass
15015 10:54:59.760122 arm64_syscall-abi_getpid_SVE_VL_48 pass
15016 10:54:59.760216 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_SM_ZA pass
15017 10:54:59.760300 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_SM pass
15018 10:54:59.760377 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_ZA pass
15019 10:54:59.760655 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_SM_ZA pass
15020 10:54:59.760738 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_SM pass
15021 10:54:59.760820 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_ZA pass
15022 10:54:59.760893 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_SM_ZA pass
15023 10:54:59.760973 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_SM pass
15024 10:54:59.761044 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_ZA pass
15025 10:54:59.761135 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_SM_ZA pass
15026 10:54:59.761245 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_SM pass
15027 10:54:59.761342 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_ZA pass
15028 10:54:59.761622 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_SM_ZA pass
15029 10:54:59.761739 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_SM pass
15030 10:54:59.761830 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_ZA pass
15031 10:54:59.761936 arm64_syscall-abi_getpid_SVE_VL_32 pass
15032 10:54:59.762032 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_SM_ZA pass
15033 10:54:59.762122 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_SM pass
15034 10:54:59.762220 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_ZA pass
15035 10:54:59.762511 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_SM_ZA pass
15036 10:54:59.762610 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_SM pass
15037 10:54:59.762702 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_ZA pass
15038 10:54:59.762812 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_SM_ZA pass
15039 10:54:59.762894 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_SM pass
15040 10:54:59.762983 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_ZA pass
15041 10:54:59.763266 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_SM_ZA pass
15042 10:54:59.763365 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_SM pass
15043 10:54:59.763494 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_ZA pass
15044 10:54:59.763588 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_SM_ZA pass
15045 10:54:59.767675 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_SM pass
15046 10:54:59.768109 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_ZA pass
15047 10:54:59.768265 arm64_syscall-abi_getpid_SVE_VL_16 pass
15048 10:54:59.768390 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_SM_ZA pass
15049 10:54:59.768568 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_SM pass
15050 10:54:59.780673 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_ZA pass
15051 10:54:59.781067 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_SM_ZA pass
15052 10:54:59.781216 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_SM pass
15053 10:54:59.781373 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_ZA pass
15054 10:54:59.781551 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_SM_ZA pass
15055 10:54:59.781719 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_SM pass
15056 10:54:59.781866 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_ZA pass
15057 10:54:59.782027 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_SM_ZA pass
15058 10:54:59.782156 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_SM pass
15059 10:54:59.782278 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_ZA pass
15060 10:54:59.782414 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_SM_ZA pass
15061 10:54:59.782585 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_SM pass
15062 10:54:59.782725 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_ZA pass
15063 10:54:59.782855 arm64_syscall-abi_sched_yield_FPSIMD pass
15064 10:54:59.783019 arm64_syscall-abi_sched_yield_SVE_VL_256 pass
15065 10:54:59.783155 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_SM_ZA pass
15066 10:54:59.783306 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_SM pass
15067 10:54:59.783439 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_ZA pass
15068 10:54:59.783578 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_SM_ZA pass
15069 10:54:59.783673 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_SM pass
15070 10:54:59.783761 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_ZA pass
15071 10:54:59.787624 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_SM_ZA pass
15072 10:54:59.787929 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_SM pass
15073 10:54:59.788056 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_ZA pass
15074 10:54:59.788169 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_SM_ZA pass
15075 10:54:59.788272 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_SM pass
15076 10:54:59.788372 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_ZA pass
15077 10:54:59.788481 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_SM_ZA pass
15078 10:54:59.788565 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_SM pass
15079 10:54:59.788666 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_ZA pass
15080 10:54:59.788774 arm64_syscall-abi_sched_yield_SVE_VL_240 pass
15081 10:54:59.789049 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_SM_ZA pass
15082 10:54:59.789135 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_SM pass
15083 10:54:59.789224 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_ZA pass
15084 10:54:59.789327 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_SM_ZA pass
15085 10:54:59.789635 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_SM pass
15086 10:54:59.789742 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_ZA pass
15087 10:54:59.789865 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_SM_ZA pass
15088 10:54:59.789964 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_SM pass
15089 10:54:59.790057 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_ZA pass
15090 10:54:59.790148 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_SM_ZA pass
15091 10:54:59.790432 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_SM pass
15092 10:54:59.790534 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_ZA pass
15093 10:54:59.790632 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_SM_ZA pass
15094 10:54:59.790727 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_SM pass
15095 10:54:59.790975 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_ZA pass
15096 10:54:59.791088 arm64_syscall-abi_sched_yield_SVE_VL_224 pass
15097 10:54:59.791187 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_SM_ZA pass
15098 10:54:59.791303 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_SM pass
15099 10:54:59.795611 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_ZA pass
15100 10:54:59.795918 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_SM_ZA pass
15101 10:54:59.796057 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_SM pass
15102 10:54:59.796231 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_ZA pass
15103 10:54:59.796376 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_SM_ZA pass
15104 10:54:59.796584 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_SM pass
15105 10:54:59.796735 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_ZA pass
15106 10:54:59.796924 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_SM_ZA pass
15107 10:54:59.797086 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_SM pass
15108 10:54:59.797265 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_ZA pass
15109 10:54:59.797440 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_SM_ZA pass
15110 10:54:59.797559 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_SM pass
15111 10:54:59.797731 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_ZA pass
15112 10:54:59.797894 arm64_syscall-abi_sched_yield_SVE_VL_208 pass
15113 10:54:59.798015 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_SM_ZA pass
15114 10:54:59.798127 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_SM pass
15115 10:54:59.798225 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_ZA pass
15116 10:54:59.798352 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_SM_ZA pass
15117 10:54:59.798468 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_SM pass
15118 10:54:59.798586 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_ZA pass
15119 10:54:59.798705 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_SM_ZA pass
15120 10:54:59.798847 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_SM pass
15121 10:54:59.798974 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_ZA pass
15122 10:54:59.799096 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_SM_ZA pass
15123 10:54:59.799239 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_SM pass
15124 10:54:59.799383 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_ZA pass
15125 10:54:59.799547 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_SM_ZA pass
15126 10:54:59.799672 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_SM pass
15127 10:54:59.803697 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_ZA pass
15128 10:54:59.804118 arm64_syscall-abi_sched_yield_SVE_VL_192 pass
15129 10:54:59.804313 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_SM_ZA pass
15130 10:54:59.804539 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_SM pass
15131 10:54:59.804768 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_ZA pass
15132 10:54:59.804947 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_SM_ZA pass
15133 10:54:59.805092 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_SM pass
15134 10:54:59.805256 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_ZA pass
15135 10:54:59.805470 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_SM_ZA pass
15136 10:54:59.805618 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_SM pass
15137 10:54:59.805782 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_ZA pass
15138 10:54:59.805939 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_SM_ZA pass
15139 10:54:59.806117 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_SM pass
15140 10:54:59.806252 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_ZA pass
15141 10:54:59.806369 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_SM_ZA pass
15142 10:54:59.806564 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_SM pass
15143 10:54:59.806718 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_ZA pass
15144 10:54:59.806840 arm64_syscall-abi_sched_yield_SVE_VL_176 pass
15145 10:54:59.806997 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_SM_ZA pass
15146 10:54:59.807154 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_SM pass
15147 10:54:59.807355 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_ZA pass
15148 10:54:59.807555 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_SM_ZA pass
15149 10:54:59.807704 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_SM pass
15150 10:54:59.807826 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_ZA pass
15151 10:54:59.807942 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_SM_ZA pass
15152 10:54:59.811676 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_SM pass
15153 10:54:59.812156 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_ZA pass
15154 10:54:59.812435 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_SM_ZA pass
15155 10:54:59.812626 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_SM pass
15156 10:54:59.812859 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_ZA pass
15157 10:54:59.813052 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_SM_ZA pass
15158 10:54:59.813242 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_SM pass
15159 10:54:59.813394 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_ZA pass
15160 10:54:59.813564 arm64_syscall-abi_sched_yield_SVE_VL_160 pass
15161 10:54:59.813832 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_SM_ZA pass
15162 10:54:59.814061 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_SM pass
15163 10:54:59.814266 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_ZA pass
15164 10:54:59.814494 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_SM_ZA pass
15165 10:54:59.814688 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_SM pass
15166 10:54:59.814961 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_ZA pass
15167 10:54:59.815201 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_SM_ZA pass
15168 10:54:59.815390 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_SM pass
15169 10:54:59.815578 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_ZA pass
15170 10:54:59.815736 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_SM_ZA pass
15171 10:54:59.815860 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_SM pass
15172 10:54:59.816006 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_ZA pass
15173 10:54:59.816131 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_SM_ZA pass
15174 10:54:59.816248 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_SM pass
15175 10:54:59.816365 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_ZA pass
15176 10:54:59.819847 arm64_syscall-abi_sched_yield_SVE_VL_144 pass
15177 10:54:59.820259 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_SM_ZA pass
15178 10:54:59.820366 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_SM pass
15179 10:54:59.820459 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_ZA pass
15180 10:54:59.820560 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_SM_ZA pass
15181 10:54:59.820655 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_SM pass
15182 10:54:59.820945 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_ZA pass
15183 10:54:59.821039 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_SM_ZA pass
15184 10:54:59.821141 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_SM pass
15185 10:54:59.821240 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_ZA pass
15186 10:54:59.821339 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_SM_ZA pass
15187 10:54:59.821635 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_SM pass
15188 10:54:59.821758 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_ZA pass
15189 10:54:59.821865 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_SM_ZA pass
15190 10:54:59.830406 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_SM pass
15191 10:54:59.830605 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_ZA pass
15192 10:54:59.831051 arm64_syscall-abi_sched_yield_SVE_VL_128 pass
15193 10:54:59.831244 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_SM_ZA pass
15194 10:54:59.831436 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_SM pass
15195 10:54:59.831614 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_ZA pass
15196 10:54:59.831798 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_SM_ZA pass
15197 10:54:59.831993 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_SM pass
15198 10:54:59.832162 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_ZA pass
15199 10:54:59.832349 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_SM_ZA pass
15200 10:54:59.832540 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_SM pass
15201 10:54:59.832723 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_ZA pass
15202 10:54:59.832901 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_SM_ZA pass
15203 10:54:59.833140 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_SM pass
15204 10:54:59.833334 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_ZA pass
15205 10:54:59.833529 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_SM_ZA pass
15206 10:54:59.833738 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_SM pass
15207 10:54:59.833945 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_ZA pass
15208 10:54:59.834161 arm64_syscall-abi_sched_yield_SVE_VL_112 pass
15209 10:54:59.834300 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_SM_ZA pass
15210 10:54:59.834446 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_SM pass
15211 10:54:59.834590 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_ZA pass
15212 10:54:59.834753 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_SM_ZA pass
15213 10:54:59.834930 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_SM pass
15214 10:54:59.835125 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_ZA pass
15215 10:54:59.835288 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_SM_ZA pass
15216 10:54:59.835445 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_SM pass
15217 10:54:59.835610 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_ZA pass
15218 10:54:59.835745 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_SM_ZA pass
15219 10:54:59.835862 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_SM pass
15220 10:54:59.836005 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_ZA pass
15221 10:54:59.836126 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_SM_ZA pass
15222 10:54:59.839720 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_SM pass
15223 10:54:59.840077 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_ZA pass
15224 10:54:59.840274 arm64_syscall-abi_sched_yield_SVE_VL_96 pass
15225 10:54:59.840435 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_SM_ZA pass
15226 10:54:59.840633 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_SM pass
15227 10:54:59.840787 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_ZA pass
15228 10:54:59.840951 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_SM_ZA pass
15229 10:54:59.841138 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_SM pass
15230 10:54:59.841300 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_ZA pass
15231 10:54:59.841453 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_SM_ZA pass
15232 10:54:59.841643 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_SM pass
15233 10:54:59.841884 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_ZA pass
15234 10:54:59.842071 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_SM_ZA pass
15235 10:54:59.842240 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_SM pass
15236 10:54:59.842446 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_ZA pass
15237 10:54:59.842620 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_SM_ZA pass
15238 10:54:59.842782 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_SM pass
15239 10:54:59.842945 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_ZA pass
15240 10:54:59.843097 arm64_syscall-abi_sched_yield_SVE_VL_80 pass
15241 10:54:59.843282 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_SM_ZA pass
15242 10:54:59.843473 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_SM pass
15243 10:54:59.843614 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_ZA pass
15244 10:54:59.843732 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_SM_ZA pass
15245 10:54:59.843846 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_SM pass
15246 10:54:59.843960 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_ZA pass
15247 10:54:59.844099 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_SM_ZA pass
15248 10:54:59.847695 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_SM pass
15249 10:54:59.848117 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_ZA pass
15250 10:54:59.848223 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_SM_ZA pass
15251 10:54:59.848310 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_SM pass
15252 10:54:59.848411 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_ZA pass
15253 10:54:59.848496 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_SM_ZA pass
15254 10:54:59.848596 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_SM pass
15255 10:54:59.848694 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_ZA pass
15256 10:54:59.848793 arm64_syscall-abi_sched_yield_SVE_VL_64 pass
15257 10:54:59.849089 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_SM_ZA pass
15258 10:54:59.849206 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_SM pass
15259 10:54:59.849310 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_ZA pass
15260 10:54:59.849662 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_SM_ZA pass
15261 10:54:59.849860 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_SM pass
15262 10:54:59.850061 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_ZA pass
15263 10:54:59.850225 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_SM_ZA pass
15264 10:54:59.850382 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_SM pass
15265 10:54:59.850568 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_ZA pass
15266 10:54:59.850736 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_SM_ZA pass
15267 10:54:59.851107 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_SM pass
15268 10:54:59.851358 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_ZA pass
15269 10:54:59.851552 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_SM_ZA pass
15270 10:54:59.851725 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_SM pass
15271 10:54:59.851859 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_ZA pass
15272 10:54:59.851978 arm64_syscall-abi_sched_yield_SVE_VL_48 pass
15273 10:54:59.852093 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_SM_ZA pass
15274 10:54:59.852236 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_SM pass
15275 10:54:59.855644 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_ZA pass
15276 10:54:59.855997 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_SM_ZA pass
15277 10:54:59.856210 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_SM pass
15278 10:54:59.856395 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_ZA pass
15279 10:54:59.856556 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_SM_ZA pass
15280 10:54:59.856717 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_SM pass
15281 10:54:59.856909 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_ZA pass
15282 10:54:59.857077 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_SM_ZA pass
15283 10:54:59.857242 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_SM pass
15284 10:54:59.857437 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_ZA pass
15285 10:54:59.857599 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_SM_ZA pass
15286 10:54:59.857771 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_SM pass
15287 10:54:59.857978 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_ZA pass
15288 10:54:59.858147 arm64_syscall-abi_sched_yield_SVE_VL_32 pass
15289 10:54:59.858290 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_SM_ZA pass
15290 10:54:59.858475 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_SM pass
15291 10:54:59.858707 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_ZA pass
15292 10:54:59.858861 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_SM_ZA pass
15293 10:54:59.859063 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_SM pass
15294 10:54:59.859232 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_ZA pass
15295 10:54:59.859422 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_SM_ZA pass
15296 10:54:59.859559 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_SM pass
15297 10:54:59.859677 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_ZA pass
15298 10:54:59.859794 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_SM_ZA pass
15299 10:54:59.859909 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_SM pass
15300 10:54:59.863661 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_ZA pass
15301 10:54:59.864111 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_SM_ZA pass
15302 10:54:59.864312 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_SM pass
15303 10:54:59.864454 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_ZA pass
15304 10:54:59.864606 arm64_syscall-abi_sched_yield_SVE_VL_16 pass
15305 10:54:59.864864 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_SM_ZA pass
15306 10:54:59.865051 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_SM pass
15307 10:54:59.865282 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_ZA pass
15308 10:54:59.865507 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_SM_ZA pass
15309 10:54:59.865740 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_SM pass
15310 10:54:59.865981 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_ZA pass
15311 10:54:59.866131 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_SM_ZA pass
15312 10:54:59.866342 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_SM pass
15313 10:54:59.866563 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_ZA pass
15314 10:54:59.866741 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_SM_ZA pass
15315 10:54:59.866868 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_SM pass
15316 10:54:59.866984 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_ZA pass
15317 10:54:59.867098 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_SM_ZA pass
15318 10:54:59.867240 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_SM pass
15319 10:54:59.867362 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_ZA pass
15320 10:54:59.867477 arm64_syscall-abi pass
15321 10:54:59.867590 arm64_tpidr2_default_value pass
15322 10:54:59.867706 arm64_tpidr2_write_read pass
15323 10:54:59.867819 arm64_tpidr2_write_sleep_read pass
15324 10:54:59.867932 arm64_tpidr2_write_fork_read pass
15325 10:54:59.868044 arm64_tpidr2_write_clone_read pass
15326 10:54:59.868156 arm64_tpidr2 pass
15327 10:54:59.882590 + ../../utils/send-to-lava.sh ./output/result.txt
15328 10:54:59.927011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tags_test RESULT=pass>
15329 10:54:59.928113 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tags_test RESULT=pass
15331 10:54:59.957878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_run_tags_test_sh RESULT=pass>
15332 10:54:59.958441 Received signal: <TESTCASE> TEST_CASE_ID=arm64_run_tags_test_sh RESULT=pass
15334 10:54:59.988722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_magic RESULT=pass>
15335 10:54:59.989206 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_magic RESULT=pass
15337 10:55:00.018624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_size RESULT=pass>
15338 10:55:00.019066 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_size RESULT=pass
15340 10:55:00.049503 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_size_for_magic0 RESULT=pass>
15341 10:55:00.049920 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_size_for_magic0 RESULT=pass
15343 10:55:00.079795 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_duplicated_fpsimd RESULT=pass
15345 10:55:00.080371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_duplicated_fpsimd RESULT=pass>
15346 10:55:00.110021 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_misaligned_sp RESULT=pass
15348 10:55:00.110582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_misaligned_sp RESULT=pass>
15349 10:55:00.141462 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_missing_fpsimd RESULT=pass
15351 10:55:00.142036 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_missing_fpsimd RESULT=pass>
15352 10:55:00.173635 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_sme_change_vl RESULT=pass
15354 10:55:00.174117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_sme_change_vl RESULT=pass>
15355 10:55:00.206532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_sve_change_vl RESULT=pass>
15356 10:55:00.206963 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_sve_change_vl RESULT=pass
15358 10:55:00.240680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_compat_toggle RESULT=pass>
15359 10:55:00.241148 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_compat_toggle RESULT=pass
15361 10:55:00.270975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_daif_bits RESULT=pass>
15362 10:55:00.271498 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_daif_bits RESULT=pass
15364 10:55:00.309116 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1h RESULT=pass
15366 10:55:00.309567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1h RESULT=pass>
15367 10:55:00.340724 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1t RESULT=pass>
15368 10:55:00.341154 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1t RESULT=pass
15370 10:55:00.374714 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2h RESULT=pass
15372 10:55:00.375175 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2h RESULT=pass>
15373 10:55:00.407172 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2t RESULT=pass
15375 10:55:00.407786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2t RESULT=pass>
15376 10:55:00.441068 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3h RESULT=pass>
15377 10:55:00.441487 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3h RESULT=pass
15379 10:55:00.474792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3t RESULT=pass>
15380 10:55:00.475296 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3t RESULT=pass
15382 10:55:00.509301 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_no_sm RESULT=pass
15384 10:55:00.509722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_no_sm RESULT=pass>
15385 10:55:00.540693 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_non_streaming RESULT=skip
15387 10:55:00.541251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_non_streaming RESULT=skip>
15388 10:55:00.576906 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_za RESULT=pass
15390 10:55:00.577322 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_za RESULT=pass>
15391 10:55:00.617020 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_vl RESULT=pass>
15392 10:55:00.617484 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_vl RESULT=pass
15394 10:55:00.652851 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ssve_regs RESULT=pass
15396 10:55:00.653296 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ssve_regs RESULT=pass>
15397 10:55:00.702149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve_regs RESULT=pass>
15398 10:55:00.702585 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve_regs RESULT=pass
15400 10:55:00.752050 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve_vl RESULT=pass
15402 10:55:00.752489 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve_vl RESULT=pass>
15403 10:55:00.792612 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za_no_regs RESULT=pass
15405 10:55:00.793257 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za_no_regs RESULT=pass>
15406 10:55:00.825684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za_regs RESULT=pass>
15407 10:55:00.826223 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za_regs RESULT=pass
15409 10:55:00.858506 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_global_corrupt_pac RESULT=pass
15411 10:55:00.858942 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_global_corrupt_pac RESULT=pass>
15412 10:55:00.897517 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_global_pac_instructions_not_nop RESULT=pass
15414 10:55:00.898058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_global_pac_instructions_not_nop RESULT=pass>
15415 10:55:00.934706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_global_pac_instructions_not_nop_generic RESULT=pass>
15416 10:55:00.935208 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_global_pac_instructions_not_nop_generic RESULT=pass
15418 10:55:00.966184 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_global_single_thread_different_keys RESULT=pass
15420 10:55:00.966830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_global_single_thread_different_keys RESULT=pass>
15421 10:55:00.996842 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_global_exec_changed_keys RESULT=pass
15423 10:55:00.997478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_global_exec_changed_keys RESULT=pass>
15424 10:55:01.026788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_global_context_switch_keep_keys RESULT=pass>
15425 10:55:01.027274 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_global_context_switch_keep_keys RESULT=pass
15427 10:55:01.058885 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_global_context_switch_keep_keys_generic RESULT=pass
15429 10:55:01.059334 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_global_context_switch_keep_keys_generic RESULT=pass>
15430 10:55:01.090420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac RESULT=pass>
15431 10:55:01.090850 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac RESULT=pass
15433 10:55:01.121186 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-0 RESULT=pass>
15434 10:55:01.121685 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-0 RESULT=pass
15436 10:55:01.151885 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-256-0 RESULT=pass
15438 10:55:01.152543 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-256-0 RESULT=pass>
15439 10:55:01.182860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-240-0 RESULT=pass>
15440 10:55:01.183337 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-240-0 RESULT=pass
15442 10:55:01.213951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-224-0 RESULT=pass>
15443 10:55:01.214444 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-224-0 RESULT=pass
15445 10:55:01.244909 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-208-0 RESULT=pass
15447 10:55:01.245362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-208-0 RESULT=pass>
15448 10:55:01.275122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-192-0 RESULT=pass>
15449 10:55:01.275558 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-192-0 RESULT=pass
15451 10:55:01.306136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-176-0 RESULT=pass>
15452 10:55:01.306560 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-176-0 RESULT=pass
15454 10:55:01.337675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-160-0 RESULT=pass>
15455 10:55:01.338107 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-160-0 RESULT=pass
15457 10:55:01.368911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-144-0 RESULT=pass>
15458 10:55:01.369350 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-144-0 RESULT=pass
15460 10:55:01.399660 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-128-0 RESULT=pass
15462 10:55:01.400125 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-128-0 RESULT=pass>
15463 10:55:01.429533 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-112-0 RESULT=pass>
15464 10:55:01.429977 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-112-0 RESULT=pass
15466 10:55:01.462033 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-96-0 RESULT=pass>
15467 10:55:01.462437 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-96-0 RESULT=pass
15469 10:55:01.493815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-80-0 RESULT=pass>
15470 10:55:01.494246 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-80-0 RESULT=pass
15472 10:55:01.525724 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-64-0 RESULT=pass>
15473 10:55:01.526177 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-64-0 RESULT=pass
15475 10:55:01.556929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-48-0 RESULT=pass>
15476 10:55:01.557359 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-48-0 RESULT=pass
15478 10:55:01.588770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-32-0 RESULT=pass>
15479 10:55:01.589178 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-32-0 RESULT=pass
15481 10:55:01.619608 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-16-0 RESULT=pass
15483 10:55:01.620079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-16-0 RESULT=pass>
15484 10:55:01.650279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SSVE-VL-256-0 RESULT=pass>
15485 10:55:01.650714 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SSVE-VL-256-0 RESULT=pass
15487 10:55:01.681042 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_ZA-VL-256-0 RESULT=pass
15489 10:55:01.681498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_ZA-VL-256-0 RESULT=pass>
15490 10:55:01.711451 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SSVE-VL-128-0 RESULT=pass>
15491 10:55:01.711873 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SSVE-VL-128-0 RESULT=pass
15493 10:55:01.745699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_ZA-VL-128-0 RESULT=pass>
15494 10:55:01.746130 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_ZA-VL-128-0 RESULT=pass
15496 10:55:01.776664 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SSVE-VL-64-0 RESULT=pass>
15497 10:55:01.777095 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SSVE-VL-64-0 RESULT=pass
15499 10:55:01.806271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_ZA-VL-64-0 RESULT=pass>
15500 10:55:01.806702 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_ZA-VL-64-0 RESULT=pass
15502 10:55:01.837818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SSVE-VL-32-0 RESULT=pass>
15503 10:55:01.838246 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SSVE-VL-32-0 RESULT=pass
15505 10:55:01.868132 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_ZA-VL-32-0 RESULT=pass>
15506 10:55:01.868556 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_ZA-VL-32-0 RESULT=pass
15508 10:55:01.898515 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SSVE-VL-16-0 RESULT=pass>
15509 10:55:01.899016 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SSVE-VL-16-0 RESULT=pass
15511 10:55:01.929187 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_ZA-VL-16-0 RESULT=pass>
15512 10:55:01.929681 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_ZA-VL-16-0 RESULT=pass
15514 10:55:01.960081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress RESULT=pass>
15515 10:55:01.960551 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress RESULT=pass
15517 10:55:01.990623 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_FPSIMD_set_via_SVE_0 RESULT=pass>
15518 10:55:01.991049 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_FPSIMD_set_via_SVE_0 RESULT=pass
15520 10:55:02.021400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_get_fpsimd_gave_same_state RESULT=pass>
15521 10:55:02.021869 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_get_fpsimd_gave_same_state RESULT=pass
15523 10:55:02.053023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_SVE_PT_VL_INHERIT_set RESULT=pass>
15524 10:55:02.053439 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_SVE_PT_VL_INHERIT_set RESULT=pass
15526 10:55:02.088129 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_SVE_PT_VL_INHERIT_cleared RESULT=pass>
15527 10:55:02.088555 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_SVE_PT_VL_INHERIT_cleared RESULT=pass
15529 10:55:02.118355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_16 RESULT=pass>
15530 10:55:02.118926 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_16 RESULT=pass
15532 10:55:02.148747 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_16 RESULT=pass>
15533 10:55:02.149173 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_16 RESULT=pass
15535 10:55:02.179263 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_16 RESULT=pass>
15536 10:55:02.179690 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_16 RESULT=pass
15538 10:55:02.210053 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_16 RESULT=pass>
15539 10:55:02.210463 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_16 RESULT=pass
15541 10:55:02.240531 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_32 RESULT=pass>
15542 10:55:02.240957 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_32 RESULT=pass
15544 10:55:02.270739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_32 RESULT=pass>
15545 10:55:02.271265 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_32 RESULT=pass
15547 10:55:02.301461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_32 RESULT=pass>
15548 10:55:02.301891 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_32 RESULT=pass
15550 10:55:02.333102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_32 RESULT=pass>
15551 10:55:02.333643 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_32 RESULT=pass
15553 10:55:02.367296 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_48 RESULT=pass>
15554 10:55:02.367858 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_48 RESULT=pass
15556 10:55:02.398851 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_48 RESULT=pass
15558 10:55:02.399578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_48 RESULT=pass>
15559 10:55:02.429803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_48 RESULT=pass>
15560 10:55:02.430302 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_48 RESULT=pass
15562 10:55:02.460967 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_48 RESULT=pass
15564 10:55:02.461413 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_48 RESULT=pass>
15565 10:55:02.491405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_64 RESULT=pass>
15566 10:55:02.491834 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_64 RESULT=pass
15568 10:55:02.522155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_64 RESULT=pass>
15569 10:55:02.522722 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_64 RESULT=pass
15571 10:55:02.552984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_64 RESULT=pass>
15572 10:55:02.553512 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_64 RESULT=pass
15574 10:55:02.584604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_64 RESULT=pass>
15575 10:55:02.585066 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_64 RESULT=pass
15577 10:55:02.614513 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_80 RESULT=pass>
15578 10:55:02.614974 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_80 RESULT=pass
15580 10:55:02.644785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_80 RESULT=pass>
15581 10:55:02.645222 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_80 RESULT=pass
15583 10:55:02.675789 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_80 RESULT=pass
15585 10:55:02.676254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_80 RESULT=pass>
15586 10:55:02.706830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_80 RESULT=pass>
15587 10:55:02.707263 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_80 RESULT=pass
15589 10:55:02.738376 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_96 RESULT=pass>
15590 10:55:02.738871 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_96 RESULT=pass
15592 10:55:02.769904 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_96 RESULT=pass
15594 10:55:02.770499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_96 RESULT=pass>
15595 10:55:02.801137 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_96 RESULT=pass
15597 10:55:02.801719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_96 RESULT=pass>
15598 10:55:02.832736 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_96 RESULT=pass>
15599 10:55:02.833226 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_96 RESULT=pass
15601 10:55:02.863241 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_112 RESULT=pass>
15602 10:55:02.863669 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_112 RESULT=pass
15604 10:55:02.894428 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_112 RESULT=pass
15606 10:55:02.894890 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_112 RESULT=pass>
15607 10:55:02.925807 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_112 RESULT=pass>
15608 10:55:02.926218 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_112 RESULT=pass
15610 10:55:02.957150 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_112 RESULT=pass>
15611 10:55:02.957643 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_112 RESULT=pass
15613 10:55:02.988655 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_128 RESULT=pass
15615 10:55:02.989294 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_128 RESULT=pass>
15616 10:55:03.019439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_128 RESULT=pass>
15617 10:55:03.019916 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_128 RESULT=pass
15619 10:55:03.050622 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_128 RESULT=pass>
15620 10:55:03.051034 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_128 RESULT=pass
15622 10:55:03.082275 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_128 RESULT=pass
15624 10:55:03.082929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_128 RESULT=pass>
15625 10:55:03.113286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_144 RESULT=pass>
15626 10:55:03.113770 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_144 RESULT=pass
15628 10:55:03.145193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_144 RESULT=pass>
15629 10:55:03.145710 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_144 RESULT=pass
15631 10:55:03.176919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_144 RESULT=pass>
15632 10:55:03.177468 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_144 RESULT=pass
15634 10:55:03.207589 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_144 RESULT=pass
15636 10:55:03.208377 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_144 RESULT=pass>
15637 10:55:03.238408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_160 RESULT=pass>
15638 10:55:03.238866 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_160 RESULT=pass
15640 10:55:03.270390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_160 RESULT=pass>
15641 10:55:03.270831 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_160 RESULT=pass
15643 10:55:03.305591 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_160 RESULT=pass
15645 10:55:03.306055 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_160 RESULT=pass>
15646 10:55:03.341272 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_160 RESULT=pass>
15647 10:55:03.342107 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_160 RESULT=pass
15649 10:55:03.375190 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_176 RESULT=pass>
15650 10:55:03.375636 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_176 RESULT=pass
15652 10:55:03.406379 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_176 RESULT=pass>
15653 10:55:03.406814 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_176 RESULT=pass
15655 10:55:03.437299 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_176 RESULT=pass>
15656 10:55:03.437687 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_176 RESULT=pass
15658 10:55:03.469007 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_176 RESULT=pass>
15659 10:55:03.469441 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_176 RESULT=pass
15661 10:55:03.500644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_192 RESULT=pass>
15662 10:55:03.501075 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_192 RESULT=pass
15664 10:55:03.532376 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_192 RESULT=pass>
15665 10:55:03.532814 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_192 RESULT=pass
15667 10:55:03.564255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_192 RESULT=pass>
15668 10:55:03.564696 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_192 RESULT=pass
15670 10:55:03.597216 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_192 RESULT=pass>
15671 10:55:03.597669 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_192 RESULT=pass
15673 10:55:03.629183 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_208 RESULT=pass>
15674 10:55:03.629580 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_208 RESULT=pass
15676 10:55:03.661534 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_208 RESULT=pass
15678 10:55:03.662193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_208 RESULT=pass>
15679 10:55:03.693154 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_208 RESULT=pass>
15680 10:55:03.693634 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_208 RESULT=pass
15682 10:55:03.724710 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_208 RESULT=pass>
15683 10:55:03.725183 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_208 RESULT=pass
15685 10:55:03.755672 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_224 RESULT=pass
15687 10:55:03.756231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_224 RESULT=pass>
15688 10:55:03.787725 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_224 RESULT=pass
15690 10:55:03.788284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_224 RESULT=pass>
15691 10:55:03.820010 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_224 RESULT=pass
15693 10:55:03.820466 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_224 RESULT=pass>
15694 10:55:03.854167 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_224 RESULT=pass
15696 10:55:03.854804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_224 RESULT=pass>
15697 10:55:03.885456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_240 RESULT=pass>
15698 10:55:03.885959 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_240 RESULT=pass
15700 10:55:03.916440 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_240 RESULT=pass
15702 10:55:03.916886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_240 RESULT=pass>
15703 10:55:03.947897 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_240 RESULT=pass
15705 10:55:03.948331 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_240 RESULT=pass>
15706 10:55:03.978768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_240 RESULT=pass>
15707 10:55:03.979263 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_240 RESULT=pass
15709 10:55:04.010665 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_256 RESULT=pass
15711 10:55:04.011302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_256 RESULT=pass>
15712 10:55:04.042202 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_256 RESULT=pass
15714 10:55:04.042841 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_256 RESULT=pass>
15715 10:55:04.073156 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_256 RESULT=pass
15717 10:55:04.073816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_256 RESULT=pass>
15718 10:55:04.104963 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_256 RESULT=pass
15720 10:55:04.105589 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_256 RESULT=pass>
15721 10:55:04.135741 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_272 RESULT=pass
15723 10:55:04.136201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_272 RESULT=pass>
15724 10:55:04.167130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_272 RESULT=skip>
15725 10:55:04.167592 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_272 RESULT=skip
15727 10:55:04.197640 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_272 RESULT=skip>
15728 10:55:04.198122 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_272 RESULT=skip
15730 10:55:04.228534 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_272 RESULT=skip
15732 10:55:04.229124 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_272 RESULT=skip>
15733 10:55:04.258712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_288 RESULT=pass>
15734 10:55:04.259177 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_288 RESULT=pass
15736 10:55:04.289532 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_288 RESULT=skip
15738 10:55:04.290173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_288 RESULT=skip>
15739 10:55:04.320905 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_288 RESULT=skip
15741 10:55:04.321468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_288 RESULT=skip>
15742 10:55:04.351898 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_288 RESULT=skip
15744 10:55:04.352467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_288 RESULT=skip>
15745 10:55:04.382914 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_304 RESULT=pass
15747 10:55:04.383514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_304 RESULT=pass>
15748 10:55:04.413129 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_304 RESULT=skip
15750 10:55:04.413704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_304 RESULT=skip>
15751 10:55:04.445955 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_304 RESULT=skip
15753 10:55:04.446560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_304 RESULT=skip>
15754 10:55:04.478991 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_304 RESULT=skip
15756 10:55:04.479468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_304 RESULT=skip>
15757 10:55:04.511354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_320 RESULT=pass>
15758 10:55:04.511804 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_320 RESULT=pass
15760 10:55:04.544354 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_320 RESULT=skip
15762 10:55:04.544945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_320 RESULT=skip>
15763 10:55:04.577140 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_320 RESULT=skip
15765 10:55:04.577721 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_320 RESULT=skip>
15766 10:55:04.611798 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_320 RESULT=skip
15768 10:55:04.612367 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_320 RESULT=skip>
15769 10:55:04.645560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_336 RESULT=pass>
15770 10:55:04.646046 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_336 RESULT=pass
15772 10:55:04.678316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_336 RESULT=skip>
15773 10:55:04.678723 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_336 RESULT=skip
15775 10:55:04.710946 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_336 RESULT=skip>
15776 10:55:04.711356 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_336 RESULT=skip
15778 10:55:04.744667 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_336 RESULT=skip
15780 10:55:04.745124 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_336 RESULT=skip>
15781 10:55:04.777732 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_352 RESULT=pass>
15782 10:55:04.778180 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_352 RESULT=pass
15784 10:55:04.812518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_352 RESULT=skip>
15785 10:55:04.812964 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_352 RESULT=skip
15787 10:55:04.845641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_352 RESULT=skip>
15788 10:55:04.846136 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_352 RESULT=skip
15790 10:55:04.881209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_352 RESULT=skip>
15791 10:55:04.881701 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_352 RESULT=skip
15793 10:55:04.914498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_368 RESULT=pass>
15794 10:55:04.914986 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_368 RESULT=pass
15796 10:55:04.946436 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_368 RESULT=skip
15798 10:55:04.946891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_368 RESULT=skip>
15799 10:55:04.978633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_368 RESULT=skip>
15800 10:55:04.979045 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_368 RESULT=skip
15802 10:55:05.009339 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_368 RESULT=skip
15804 10:55:05.009909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_368 RESULT=skip>
15805 10:55:05.042996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_384 RESULT=pass>
15806 10:55:05.043430 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_384 RESULT=pass
15808 10:55:05.078228 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_384 RESULT=skip
15810 10:55:05.078698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_384 RESULT=skip>
15811 10:55:05.110520 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_384 RESULT=skip
15813 10:55:05.111156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_384 RESULT=skip>
15814 10:55:05.141783 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_384 RESULT=skip>
15815 10:55:05.142258 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_384 RESULT=skip
15817 10:55:05.174366 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_400 RESULT=pass>
15818 10:55:05.174848 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_400 RESULT=pass
15820 10:55:05.207746 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_400 RESULT=skip
15822 10:55:05.208396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_400 RESULT=skip>
15823 10:55:05.240308 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_400 RESULT=skip
15825 10:55:05.240947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_400 RESULT=skip>
15826 10:55:05.271658 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_400 RESULT=skip
15828 10:55:05.272301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_400 RESULT=skip>
15829 10:55:05.303407 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_416 RESULT=pass
15831 10:55:05.304049 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_416 RESULT=pass>
15832 10:55:05.336675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_416 RESULT=skip>
15833 10:55:05.337143 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_416 RESULT=skip
15835 10:55:05.367495 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_416 RESULT=skip
15837 10:55:05.368147 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_416 RESULT=skip>
15838 10:55:05.398536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_416 RESULT=skip>
15839 10:55:05.399012 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_416 RESULT=skip
15841 10:55:05.428672 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_432 RESULT=pass
15843 10:55:05.429120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_432 RESULT=pass>
15844 10:55:05.458692 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_432 RESULT=skip
15846 10:55:05.459244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_432 RESULT=skip>
15847 10:55:05.488881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_432 RESULT=skip>
15848 10:55:05.489339 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_432 RESULT=skip
15850 10:55:05.521199 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_432 RESULT=skip
15852 10:55:05.521779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_432 RESULT=skip>
15853 10:55:05.553406 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_448 RESULT=pass>
15854 10:55:05.553928 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_448 RESULT=pass
15856 10:55:05.586027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_448 RESULT=skip>
15857 10:55:05.586544 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_448 RESULT=skip
15859 10:55:05.619864 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_448 RESULT=skip
15861 10:55:05.620353 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_448 RESULT=skip>
15862 10:55:05.654292 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_448 RESULT=skip
15864 10:55:05.654755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_448 RESULT=skip>
15865 10:55:05.688378 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_464 RESULT=pass
15867 10:55:05.688829 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_464 RESULT=pass>
15868 10:55:05.720726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_464 RESULT=skip>
15869 10:55:05.721154 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_464 RESULT=skip
15871 10:55:05.752819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_464 RESULT=skip>
15872 10:55:05.753246 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_464 RESULT=skip
15874 10:55:05.784638 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_464 RESULT=skip>
15875 10:55:05.785048 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_464 RESULT=skip
15877 10:55:05.815835 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_480 RESULT=pass
15879 10:55:05.816308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_480 RESULT=pass>
15880 10:55:05.847829 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_480 RESULT=skip
15882 10:55:05.848299 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_480 RESULT=skip>
15883 10:55:05.879221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_480 RESULT=skip>
15884 10:55:05.879651 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_480 RESULT=skip
15886 10:55:05.911688 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_480 RESULT=skip
15888 10:55:05.912164 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_480 RESULT=skip>
15889 10:55:05.943055 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_496 RESULT=pass>
15890 10:55:05.943492 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_496 RESULT=pass
15892 10:55:05.974535 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_496 RESULT=skip>
15893 10:55:05.974946 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_496 RESULT=skip
15895 10:55:06.007505 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_496 RESULT=skip
15897 10:55:06.008067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_496 RESULT=skip>
15898 10:55:06.040689 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_496 RESULT=skip
15900 10:55:06.041246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_496 RESULT=skip>
15901 10:55:06.072681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_512 RESULT=pass>
15902 10:55:06.073178 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_512 RESULT=pass
15904 10:55:06.104871 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_512 RESULT=skip>
15905 10:55:06.105309 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_512 RESULT=skip
15907 10:55:06.137440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_512 RESULT=skip>
15908 10:55:06.137884 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_512 RESULT=skip
15910 10:55:06.171416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_512 RESULT=skip>
15911 10:55:06.171857 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_512 RESULT=skip
15913 10:55:06.203191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_528 RESULT=pass>
15914 10:55:06.203634 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_528 RESULT=pass
15916 10:55:06.234180 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_528 RESULT=skip
15918 10:55:06.234614 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_528 RESULT=skip>
15919 10:55:06.264817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_528 RESULT=skip>
15920 10:55:06.265262 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_528 RESULT=skip
15922 10:55:06.296669 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_528 RESULT=skip
15924 10:55:06.297063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_528 RESULT=skip>
15925 10:55:06.328681 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_544 RESULT=pass
15927 10:55:06.329139 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_544 RESULT=pass>
15928 10:55:06.361031 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_544 RESULT=skip
15930 10:55:06.361472 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_544 RESULT=skip>
15931 10:55:06.392243 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_544 RESULT=skip>
15932 10:55:06.392670 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_544 RESULT=skip
15934 10:55:06.424595 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_544 RESULT=skip
15936 10:55:06.425043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_544 RESULT=skip>
15937 10:55:06.455310 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_560 RESULT=pass>
15938 10:55:06.455733 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_560 RESULT=pass
15940 10:55:06.486593 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_560 RESULT=skip
15942 10:55:06.487064 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_560 RESULT=skip>
15943 10:55:06.518936 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_560 RESULT=skip
15945 10:55:06.519387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_560 RESULT=skip>
15946 10:55:06.552738 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_560 RESULT=skip>
15947 10:55:06.553185 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_560 RESULT=skip
15949 10:55:06.586269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_576 RESULT=pass>
15950 10:55:06.586713 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_576 RESULT=pass
15952 10:55:06.620235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_576 RESULT=skip>
15953 10:55:06.620730 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_576 RESULT=skip
15955 10:55:06.653870 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_576 RESULT=skip>
15956 10:55:06.654341 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_576 RESULT=skip
15958 10:55:06.688476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_576 RESULT=skip>
15959 10:55:06.688894 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_576 RESULT=skip
15961 10:55:06.722851 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_592 RESULT=pass>
15962 10:55:06.723282 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_592 RESULT=pass
15964 10:55:06.759167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_592 RESULT=skip>
15965 10:55:06.759577 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_592 RESULT=skip
15967 10:55:06.794215 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_592 RESULT=skip
15969 10:55:06.794664 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_592 RESULT=skip>
15970 10:55:06.829297 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_592 RESULT=skip>
15971 10:55:06.829790 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_592 RESULT=skip
15973 10:55:06.864665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_608 RESULT=pass>
15974 10:55:06.865113 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_608 RESULT=pass
15976 10:55:06.899786 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_608 RESULT=skip
15978 10:55:06.900446 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_608 RESULT=skip>
15979 10:55:06.934040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_608 RESULT=skip>
15980 10:55:06.934523 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_608 RESULT=skip
15982 10:55:06.969671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_608 RESULT=skip>
15983 10:55:06.970158 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_608 RESULT=skip
15985 10:55:07.003831 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_624 RESULT=pass
15987 10:55:07.004474 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_624 RESULT=pass>
15988 10:55:07.038250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_624 RESULT=skip>
15989 10:55:07.038734 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_624 RESULT=skip
15991 10:55:07.072840 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_624 RESULT=skip>
15992 10:55:07.073343 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_624 RESULT=skip
15994 10:55:07.106568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_624 RESULT=skip>
15995 10:55:07.107075 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_624 RESULT=skip
15997 10:55:07.141080 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_640 RESULT=pass
15999 10:55:07.141751 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_640 RESULT=pass>
16000 10:55:07.175749 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_640 RESULT=skip
16002 10:55:07.176207 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_640 RESULT=skip>
16003 10:55:07.212351 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_640 RESULT=skip
16005 10:55:07.212832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_640 RESULT=skip>
16006 10:55:07.252909 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_640 RESULT=skip
16008 10:55:07.253341 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_640 RESULT=skip>
16009 10:55:07.287217 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_656 RESULT=pass
16011 10:55:07.287768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_656 RESULT=pass>
16012 10:55:07.320447 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_656 RESULT=skip>
16013 10:55:07.320918 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_656 RESULT=skip
16015 10:55:07.353965 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_656 RESULT=skip>
16016 10:55:07.354430 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_656 RESULT=skip
16018 10:55:07.387545 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_656 RESULT=skip
16020 10:55:07.388130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_656 RESULT=skip>
16021 10:55:07.421243 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_672 RESULT=pass>
16022 10:55:07.421703 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_672 RESULT=pass
16024 10:55:07.456315 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_672 RESULT=skip
16026 10:55:07.456867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_672 RESULT=skip>
16027 10:55:07.491508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_672 RESULT=skip>
16028 10:55:07.491973 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_672 RESULT=skip
16030 10:55:07.527600 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_672 RESULT=skip
16032 10:55:07.528170 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_672 RESULT=skip>
16033 10:55:07.562518 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_688 RESULT=pass
16035 10:55:07.563087 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_688 RESULT=pass>
16036 10:55:07.596961 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_688 RESULT=skip
16038 10:55:07.597435 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_688 RESULT=skip>
16039 10:55:07.631072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_688 RESULT=skip>
16040 10:55:07.631502 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_688 RESULT=skip
16042 10:55:07.665877 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_688 RESULT=skip
16044 10:55:07.666359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_688 RESULT=skip>
16045 10:55:07.700910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_704 RESULT=pass>
16046 10:55:07.701355 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_704 RESULT=pass
16048 10:55:07.735947 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_704 RESULT=skip
16050 10:55:07.736410 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_704 RESULT=skip>
16051 10:55:07.776338 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_704 RESULT=skip
16053 10:55:07.776828 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_704 RESULT=skip>
16054 10:55:07.812462 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_704 RESULT=skip
16056 10:55:07.812932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_704 RESULT=skip>
16057 10:55:07.848395 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_720 RESULT=pass
16059 10:55:07.848840 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_720 RESULT=pass>
16060 10:55:07.883453 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_720 RESULT=skip>
16061 10:55:07.883928 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_720 RESULT=skip
16063 10:55:07.919358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_720 RESULT=skip>
16064 10:55:07.919857 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_720 RESULT=skip
16066 10:55:07.956360 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_720 RESULT=skip>
16067 10:55:07.956841 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_720 RESULT=skip
16069 10:55:07.992209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_736 RESULT=pass>
16070 10:55:07.992693 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_736 RESULT=pass
16072 10:55:08.027517 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_736 RESULT=skip
16074 10:55:08.028077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_736 RESULT=skip>
16075 10:55:08.063169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_736 RESULT=skip>
16076 10:55:08.063653 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_736 RESULT=skip
16078 10:55:08.099062 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_736 RESULT=skip
16080 10:55:08.099541 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_736 RESULT=skip>
16081 10:55:08.132952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_752 RESULT=pass>
16082 10:55:08.133392 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_752 RESULT=pass
16084 10:55:08.171651 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_752 RESULT=skip
16086 10:55:08.172210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_752 RESULT=skip>
16087 10:55:08.209371 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_752 RESULT=skip
16089 10:55:08.209810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_752 RESULT=skip>
16090 10:55:08.245441 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_752 RESULT=skip
16092 10:55:08.245944 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_752 RESULT=skip>
16093 10:55:08.277908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_768 RESULT=pass>
16094 10:55:08.278283 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_768 RESULT=pass
16096 10:55:08.312325 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_768 RESULT=skip
16098 10:55:08.312782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_768 RESULT=skip>
16099 10:55:08.347021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_768 RESULT=skip>
16100 10:55:08.347436 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_768 RESULT=skip
16102 10:55:08.382828 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_768 RESULT=skip>
16103 10:55:08.383246 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_768 RESULT=skip
16105 10:55:08.427857 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_784 RESULT=pass
16107 10:55:08.428343 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_784 RESULT=pass>
16108 10:55:08.463394 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_784 RESULT=skip>
16109 10:55:08.463868 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_784 RESULT=skip
16111 10:55:08.494873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_784 RESULT=skip>
16112 10:55:08.495353 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_784 RESULT=skip
16114 10:55:08.525849 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_784 RESULT=skip>
16115 10:55:08.526297 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_784 RESULT=skip
16117 10:55:08.556771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_800 RESULT=pass>
16118 10:55:08.557266 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_800 RESULT=pass
16120 10:55:08.587832 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_800 RESULT=skip
16122 10:55:08.588299 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_800 RESULT=skip>
16123 10:55:08.619483 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_800 RESULT=skip
16125 10:55:08.619853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_800 RESULT=skip>
16126 10:55:08.651624 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_800 RESULT=skip
16128 10:55:08.652089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_800 RESULT=skip>
16129 10:55:08.682906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_816 RESULT=pass>
16130 10:55:08.683350 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_816 RESULT=pass
16132 10:55:08.714418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_816 RESULT=skip>
16133 10:55:08.714835 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_816 RESULT=skip
16135 10:55:08.745469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_816 RESULT=skip>
16136 10:55:08.745970 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_816 RESULT=skip
16138 10:55:08.777220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_816 RESULT=skip>
16139 10:55:08.777699 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_816 RESULT=skip
16141 10:55:08.808243 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_832 RESULT=pass>
16142 10:55:08.808735 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_832 RESULT=pass
16144 10:55:08.839791 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_832 RESULT=skip
16146 10:55:08.840371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_832 RESULT=skip>
16147 10:55:08.872462 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_832 RESULT=skip
16149 10:55:08.872928 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_832 RESULT=skip>
16150 10:55:08.904894 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_832 RESULT=skip
16152 10:55:08.905460 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_832 RESULT=skip>
16153 10:55:08.935728 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_848 RESULT=pass
16155 10:55:08.936291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_848 RESULT=pass>
16156 10:55:08.966874 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_848 RESULT=skip
16158 10:55:08.967361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_848 RESULT=skip>
16159 10:55:08.998234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_848 RESULT=skip>
16160 10:55:08.998677 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_848 RESULT=skip
16162 10:55:09.030851 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_848 RESULT=skip
16164 10:55:09.031338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_848 RESULT=skip>
16165 10:55:09.062725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_864 RESULT=pass>
16166 10:55:09.063168 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_864 RESULT=pass
16168 10:55:09.095115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_864 RESULT=skip>
16169 10:55:09.095537 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_864 RESULT=skip
16171 10:55:09.126197 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_864 RESULT=skip
16173 10:55:09.126663 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_864 RESULT=skip>
16174 10:55:09.157932 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_864 RESULT=skip
16176 10:55:09.158400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_864 RESULT=skip>
16177 10:55:09.188967 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_880 RESULT=pass>
16178 10:55:09.189394 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_880 RESULT=pass
16180 10:55:09.220646 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_880 RESULT=skip
16182 10:55:09.221119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_880 RESULT=skip>
16183 10:55:09.252504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_880 RESULT=skip>
16184 10:55:09.252966 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_880 RESULT=skip
16186 10:55:09.283606 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_880 RESULT=skip>
16187 10:55:09.284074 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_880 RESULT=skip
16189 10:55:09.314936 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_896 RESULT=pass
16191 10:55:09.315574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_896 RESULT=pass>
16192 10:55:09.346923 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_896 RESULT=skip
16194 10:55:09.347539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_896 RESULT=skip>
16195 10:55:09.382396 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_896 RESULT=skip
16197 10:55:09.382982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_896 RESULT=skip>
16198 10:55:09.417398 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_896 RESULT=skip
16200 10:55:09.417874 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_896 RESULT=skip>
16201 10:55:09.448966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_912 RESULT=pass>
16202 10:55:09.449472 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_912 RESULT=pass
16204 10:55:09.480500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_912 RESULT=skip>
16205 10:55:09.480950 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_912 RESULT=skip
16207 10:55:09.512310 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_912 RESULT=skip
16209 10:55:09.512668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_912 RESULT=skip>
16210 10:55:09.543429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_912 RESULT=skip>
16211 10:55:09.543855 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_912 RESULT=skip
16213 10:55:09.574662 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_928 RESULT=pass>
16214 10:55:09.575168 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_928 RESULT=pass
16216 10:55:09.607133 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_928 RESULT=skip
16218 10:55:09.607722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_928 RESULT=skip>
16219 10:55:09.639466 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_928 RESULT=skip
16221 10:55:09.639927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_928 RESULT=skip>
16222 10:55:09.674117 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_928 RESULT=skip
16224 10:55:09.674567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_928 RESULT=skip>
16225 10:55:09.707021 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_944 RESULT=pass
16227 10:55:09.707475 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_944 RESULT=pass>
16228 10:55:09.740489 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_944 RESULT=skip>
16229 10:55:09.740981 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_944 RESULT=skip
16231 10:55:09.772384 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_944 RESULT=skip
16233 10:55:09.773005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_944 RESULT=skip>
16234 10:55:09.803235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_944 RESULT=skip>
16235 10:55:09.803754 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_944 RESULT=skip
16237 10:55:09.836684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_960 RESULT=pass>
16238 10:55:09.837117 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_960 RESULT=pass
16240 10:55:09.868813 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_960 RESULT=skip
16242 10:55:09.869262 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_960 RESULT=skip>
16243 10:55:09.900932 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_960 RESULT=skip
16245 10:55:09.901332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_960 RESULT=skip>
16246 10:55:09.932842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_960 RESULT=skip>
16247 10:55:09.933300 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_960 RESULT=skip
16249 10:55:09.964746 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_976 RESULT=pass>
16250 10:55:09.965109 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_976 RESULT=pass
16252 10:55:09.996664 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_976 RESULT=skip>
16253 10:55:09.997092 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_976 RESULT=skip
16255 10:55:10.030004 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_976 RESULT=skip
16257 10:55:10.030555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_976 RESULT=skip>
16258 10:55:10.062552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_976 RESULT=skip>
16259 10:55:10.063019 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_976 RESULT=skip
16261 10:55:10.094507 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_992 RESULT=pass
16263 10:55:10.095105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_992 RESULT=pass>
16264 10:55:10.126462 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_992 RESULT=skip
16266 10:55:10.126913 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_992 RESULT=skip>
16267 10:55:10.158046 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_992 RESULT=skip
16269 10:55:10.158625 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_992 RESULT=skip>
16270 10:55:10.189784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_992 RESULT=skip>
16271 10:55:10.190238 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_992 RESULT=skip
16273 10:55:10.224290 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1008 RESULT=pass
16275 10:55:10.224854 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1008 RESULT=pass>
16276 10:55:10.256334 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1008 RESULT=skip
16278 10:55:10.256949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1008 RESULT=skip>
16279 10:55:10.288365 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1008 RESULT=skip>
16280 10:55:10.288781 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1008 RESULT=skip
16282 10:55:10.320450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1008 RESULT=skip>
16283 10:55:10.320863 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1008 RESULT=skip
16285 10:55:10.352464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1024 RESULT=pass>
16286 10:55:10.352906 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1024 RESULT=pass
16288 10:55:10.384893 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1024 RESULT=skip
16290 10:55:10.385348 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1024 RESULT=skip>
16291 10:55:10.417566 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1024 RESULT=skip
16293 10:55:10.418032 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1024 RESULT=skip>
16294 10:55:10.449605 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1024 RESULT=skip
16296 10:55:10.450045 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1024 RESULT=skip>
16297 10:55:10.481505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1040 RESULT=pass>
16298 10:55:10.481946 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1040 RESULT=pass
16300 10:55:10.513040 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1040 RESULT=skip
16302 10:55:10.513475 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1040 RESULT=skip>
16303 10:55:10.543546 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1040 RESULT=skip>
16304 10:55:10.543960 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1040 RESULT=skip
16306 10:55:10.574572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1040 RESULT=skip>
16307 10:55:10.574983 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1040 RESULT=skip
16309 10:55:10.605061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1056 RESULT=pass>
16310 10:55:10.605485 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1056 RESULT=pass
16312 10:55:10.636724 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1056 RESULT=skip
16314 10:55:10.637163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1056 RESULT=skip>
16315 10:55:10.667525 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1056 RESULT=skip>
16316 10:55:10.667937 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1056 RESULT=skip
16318 10:55:10.698692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1056 RESULT=skip>
16319 10:55:10.699157 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1056 RESULT=skip
16321 10:55:10.729424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1072 RESULT=pass>
16322 10:55:10.729864 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1072 RESULT=pass
16324 10:55:10.761033 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1072 RESULT=skip
16326 10:55:10.761491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1072 RESULT=skip>
16327 10:55:10.792779 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1072 RESULT=skip
16329 10:55:10.793373 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1072 RESULT=skip>
16330 10:55:10.824754 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1072 RESULT=skip
16332 10:55:10.825186 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1072 RESULT=skip>
16333 10:55:10.856570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1088 RESULT=pass>
16334 10:55:10.856990 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1088 RESULT=pass
16336 10:55:10.888263 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1088 RESULT=skip
16338 10:55:10.888878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1088 RESULT=skip>
16339 10:55:10.919667 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1088 RESULT=skip>
16340 10:55:10.920124 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1088 RESULT=skip
16342 10:55:10.950998 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1088 RESULT=skip
16344 10:55:10.951541 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1088 RESULT=skip>
16345 10:55:10.983136 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1104 RESULT=pass
16347 10:55:10.983693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1104 RESULT=pass>
16348 10:55:11.014751 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1104 RESULT=skip
16350 10:55:11.015341 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1104 RESULT=skip>
16351 10:55:11.046357 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1104 RESULT=skip
16353 10:55:11.046925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1104 RESULT=skip>
16354 10:55:11.078574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1104 RESULT=skip>
16355 10:55:11.079046 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1104 RESULT=skip
16357 10:55:11.110155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1120 RESULT=pass>
16358 10:55:11.110610 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1120 RESULT=pass
16360 10:55:11.141440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1120 RESULT=skip>
16361 10:55:11.141847 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1120 RESULT=skip
16363 10:55:11.173299 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1120 RESULT=skip
16365 10:55:11.173860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1120 RESULT=skip>
16366 10:55:11.204941 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1120 RESULT=skip
16368 10:55:11.205362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1120 RESULT=skip>
16369 10:55:11.236328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1136 RESULT=pass>
16370 10:55:11.236760 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1136 RESULT=pass
16372 10:55:11.267456 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1136 RESULT=skip
16374 10:55:11.267907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1136 RESULT=skip>
16375 10:55:11.298539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1136 RESULT=skip>
16376 10:55:11.299016 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1136 RESULT=skip
16378 10:55:11.330364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1136 RESULT=skip>
16379 10:55:11.330837 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1136 RESULT=skip
16381 10:55:11.363797 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1152 RESULT=pass
16383 10:55:11.364365 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1152 RESULT=pass>
16384 10:55:11.396827 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1152 RESULT=skip
16386 10:55:11.397377 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1152 RESULT=skip>
16387 10:55:11.430561 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1152 RESULT=skip
16389 10:55:11.431103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1152 RESULT=skip>
16390 10:55:11.462471 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1152 RESULT=skip
16392 10:55:11.462930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1152 RESULT=skip>
16393 10:55:11.494508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1168 RESULT=pass>
16394 10:55:11.494985 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1168 RESULT=pass
16396 10:55:11.526085 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1168 RESULT=skip
16398 10:55:11.526637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1168 RESULT=skip>
16399 10:55:11.558048 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1168 RESULT=skip>
16400 10:55:11.558515 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1168 RESULT=skip
16402 10:55:11.589698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1168 RESULT=skip>
16403 10:55:11.590186 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1168 RESULT=skip
16405 10:55:11.621273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1184 RESULT=pass>
16406 10:55:11.621701 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1184 RESULT=pass
16408 10:55:11.654846 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1184 RESULT=skip
16410 10:55:11.655441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1184 RESULT=skip>
16411 10:55:11.687616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1184 RESULT=skip>
16412 10:55:11.688039 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1184 RESULT=skip
16414 10:55:11.722524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1184 RESULT=skip>
16415 10:55:11.722935 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1184 RESULT=skip
16417 10:55:11.755836 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1200 RESULT=pass
16419 10:55:11.756307 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1200 RESULT=pass>
16420 10:55:11.787583 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1200 RESULT=skip>
16421 10:55:11.787997 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1200 RESULT=skip
16423 10:55:11.819066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1200 RESULT=skip>
16424 10:55:11.819519 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1200 RESULT=skip
16426 10:55:11.851487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1200 RESULT=skip>
16427 10:55:11.851981 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1200 RESULT=skip
16429 10:55:11.883280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1216 RESULT=pass>
16430 10:55:11.883765 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1216 RESULT=pass
16432 10:55:11.916727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1216 RESULT=skip>
16433 10:55:11.917191 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1216 RESULT=skip
16435 10:55:11.948476 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1216 RESULT=skip
16437 10:55:11.949078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1216 RESULT=skip>
16438 10:55:11.979159 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1216 RESULT=skip>
16439 10:55:11.979583 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1216 RESULT=skip
16441 10:55:12.012829 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1232 RESULT=pass
16443 10:55:12.013290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1232 RESULT=pass>
16444 10:55:12.045440 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1232 RESULT=skip
16446 10:55:12.046098 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1232 RESULT=skip>
16447 10:55:12.077800 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1232 RESULT=skip
16449 10:55:12.078395 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1232 RESULT=skip>
16450 10:55:12.110854 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1232 RESULT=skip>
16451 10:55:12.111286 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1232 RESULT=skip
16453 10:55:12.142388 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1248 RESULT=pass
16455 10:55:12.142846 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1248 RESULT=pass>
16456 10:55:12.173936 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1248 RESULT=skip
16458 10:55:12.174395 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1248 RESULT=skip>
16459 10:55:12.205719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1248 RESULT=skip>
16460 10:55:12.206134 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1248 RESULT=skip
16462 10:55:12.239301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1248 RESULT=skip>
16463 10:55:12.239743 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1248 RESULT=skip
16465 10:55:12.273092 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1264 RESULT=pass>
16466 10:55:12.273573 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1264 RESULT=pass
16468 10:55:12.305022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1264 RESULT=skip>
16469 10:55:12.305524 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1264 RESULT=skip
16471 10:55:12.337137 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1264 RESULT=skip>
16472 10:55:12.337610 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1264 RESULT=skip
16474 10:55:12.369176 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1264 RESULT=skip
16476 10:55:12.369772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1264 RESULT=skip>
16477 10:55:12.400749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1280 RESULT=pass>
16478 10:55:12.401231 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1280 RESULT=pass
16480 10:55:12.432327 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1280 RESULT=skip>
16481 10:55:12.432769 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1280 RESULT=skip
16483 10:55:12.465949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1280 RESULT=skip>
16484 10:55:12.466362 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1280 RESULT=skip
16486 10:55:12.497975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1280 RESULT=skip>
16487 10:55:12.498402 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1280 RESULT=skip
16489 10:55:12.528675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1296 RESULT=pass>
16490 10:55:12.529095 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1296 RESULT=pass
16492 10:55:12.559248 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1296 RESULT=skip
16494 10:55:12.559883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1296 RESULT=skip>
16495 10:55:12.589545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1296 RESULT=skip>
16496 10:55:12.589941 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1296 RESULT=skip
16498 10:55:12.622253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1296 RESULT=skip>
16499 10:55:12.622660 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1296 RESULT=skip
16501 10:55:12.653968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1312 RESULT=pass>
16502 10:55:12.654388 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1312 RESULT=pass
16504 10:55:12.685335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1312 RESULT=skip>
16505 10:55:12.685745 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1312 RESULT=skip
16507 10:55:12.716772 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1312 RESULT=skip
16509 10:55:12.717136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1312 RESULT=skip>
16510 10:55:12.748371 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1312 RESULT=skip
16512 10:55:12.749142 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1312 RESULT=skip>
16513 10:55:12.780456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1328 RESULT=pass>
16514 10:55:12.780933 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1328 RESULT=pass
16516 10:55:12.811307 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1328 RESULT=skip
16518 10:55:12.811856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1328 RESULT=skip>
16519 10:55:12.842540 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1328 RESULT=skip
16521 10:55:12.843084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1328 RESULT=skip>
16522 10:55:12.875267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1328 RESULT=skip>
16523 10:55:12.875692 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1328 RESULT=skip
16525 10:55:12.910670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1344 RESULT=pass>
16526 10:55:12.911164 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1344 RESULT=pass
16528 10:55:12.947985 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1344 RESULT=skip
16530 10:55:12.948427 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1344 RESULT=skip>
16531 10:55:12.983308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1344 RESULT=skip>
16532 10:55:12.983671 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1344 RESULT=skip
16534 10:55:13.017451 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1344 RESULT=skip>
16535 10:55:13.017812 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1344 RESULT=skip
16537 10:55:13.052461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1360 RESULT=pass>
16538 10:55:13.052817 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1360 RESULT=pass
16540 10:55:13.086512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1360 RESULT=skip>
16541 10:55:13.086882 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1360 RESULT=skip
16543 10:55:13.120202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1360 RESULT=skip>
16544 10:55:13.120597 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1360 RESULT=skip
16546 10:55:13.155228 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1360 RESULT=skip>
16547 10:55:13.155648 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1360 RESULT=skip
16549 10:55:13.190347 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1376 RESULT=pass
16551 10:55:13.190790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1376 RESULT=pass>
16552 10:55:13.225941 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1376 RESULT=skip
16554 10:55:13.226543 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1376 RESULT=skip>
16555 10:55:13.260618 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1376 RESULT=skip>
16556 10:55:13.261075 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1376 RESULT=skip
16558 10:55:13.295816 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1376 RESULT=skip
16560 10:55:13.296399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1376 RESULT=skip>
16561 10:55:13.330547 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1392 RESULT=pass>
16562 10:55:13.331006 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1392 RESULT=pass
16564 10:55:13.365428 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1392 RESULT=skip
16566 10:55:13.366093 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1392 RESULT=skip>
16567 10:55:13.400297 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1392 RESULT=skip
16569 10:55:13.400831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1392 RESULT=skip>
16570 10:55:13.435522 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1392 RESULT=skip
16572 10:55:13.436075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1392 RESULT=skip>
16573 10:55:13.470194 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1408 RESULT=pass
16575 10:55:13.470641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1408 RESULT=pass>
16576 10:55:13.505554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1408 RESULT=skip>
16577 10:55:13.505947 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1408 RESULT=skip
16579 10:55:13.541252 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1408 RESULT=skip
16581 10:55:13.541934 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1408 RESULT=skip>
16582 10:55:13.576500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1408 RESULT=skip>
16583 10:55:13.576979 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1408 RESULT=skip
16585 10:55:13.609998 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1424 RESULT=pass>
16586 10:55:13.610415 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1424 RESULT=pass
16588 10:55:13.644865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1424 RESULT=skip>
16589 10:55:13.645335 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1424 RESULT=skip
16591 10:55:13.678998 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1424 RESULT=skip>
16592 10:55:13.679477 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1424 RESULT=skip
16594 10:55:13.714228 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1424 RESULT=skip>
16595 10:55:13.714696 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1424 RESULT=skip
16597 10:55:13.749640 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1440 RESULT=pass
16599 10:55:13.750247 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1440 RESULT=pass>
16600 10:55:13.784834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1440 RESULT=skip>
16601 10:55:13.785250 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1440 RESULT=skip
16603 10:55:13.819099 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1440 RESULT=skip
16605 10:55:13.819648 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1440 RESULT=skip>
16606 10:55:13.853468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1440 RESULT=skip>
16607 10:55:13.853825 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1440 RESULT=skip
16609 10:55:13.888749 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1456 RESULT=pass
16611 10:55:13.889375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1456 RESULT=pass>
16612 10:55:13.922932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1456 RESULT=skip>
16613 10:55:13.923390 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1456 RESULT=skip
16615 10:55:13.957171 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1456 RESULT=skip
16617 10:55:13.957661 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1456 RESULT=skip>
16618 10:55:13.992403 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1456 RESULT=skip
16620 10:55:13.992853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1456 RESULT=skip>
16621 10:55:14.029086 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1472 RESULT=pass>
16622 10:55:14.029576 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1472 RESULT=pass
16624 10:55:14.065816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1472 RESULT=skip>
16625 10:55:14.066206 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1472 RESULT=skip
16627 10:55:14.109873 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1472 RESULT=skip
16629 10:55:14.110309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1472 RESULT=skip>
16630 10:55:14.145052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1472 RESULT=skip>
16631 10:55:14.145400 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1472 RESULT=skip
16633 10:55:14.180583 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1488 RESULT=pass>
16634 10:55:14.180888 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1488 RESULT=pass
16636 10:55:14.214656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1488 RESULT=skip>
16637 10:55:14.214977 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1488 RESULT=skip
16639 10:55:14.249026 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1488 RESULT=skip>
16640 10:55:14.249497 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1488 RESULT=skip
16642 10:55:14.283281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1488 RESULT=skip>
16643 10:55:14.283641 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1488 RESULT=skip
16645 10:55:14.317071 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1504 RESULT=pass
16647 10:55:14.317500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1504 RESULT=pass>
16648 10:55:14.352714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1504 RESULT=skip>
16649 10:55:14.353059 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1504 RESULT=skip
16651 10:55:14.395320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1504 RESULT=skip>
16652 10:55:14.395764 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1504 RESULT=skip
16654 10:55:14.431175 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1504 RESULT=skip
16656 10:55:14.431647 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1504 RESULT=skip>
16657 10:55:14.466789 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1520 RESULT=pass>
16658 10:55:14.467155 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1520 RESULT=pass
16660 10:55:14.501637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1520 RESULT=skip>
16661 10:55:14.502173 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1520 RESULT=skip
16663 10:55:14.535447 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1520 RESULT=skip>
16664 10:55:14.535793 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1520 RESULT=skip
16666 10:55:14.571863 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1520 RESULT=skip
16668 10:55:14.572333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1520 RESULT=skip>
16669 10:55:14.606526 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1536 RESULT=pass
16671 10:55:14.606995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1536 RESULT=pass>
16672 10:55:14.641201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1536 RESULT=skip>
16673 10:55:14.641592 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1536 RESULT=skip
16675 10:55:14.679600 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1536 RESULT=skip
16677 10:55:14.679997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1536 RESULT=skip>
16678 10:55:14.714654 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1536 RESULT=skip>
16679 10:55:14.714925 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1536 RESULT=skip
16681 10:55:14.748595 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1552 RESULT=pass
16683 10:55:14.749119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1552 RESULT=pass>
16684 10:55:14.782401 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1552 RESULT=skip>
16685 10:55:14.782778 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1552 RESULT=skip
16687 10:55:14.816940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1552 RESULT=skip>
16688 10:55:14.817287 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1552 RESULT=skip
16690 10:55:14.852834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1552 RESULT=skip>
16691 10:55:14.853178 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1552 RESULT=skip
16693 10:55:14.887686 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1568 RESULT=pass
16695 10:55:14.888145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1568 RESULT=pass>
16696 10:55:14.922852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1568 RESULT=skip>
16697 10:55:14.923287 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1568 RESULT=skip
16699 10:55:14.958591 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1568 RESULT=skip
16701 10:55:14.959087 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1568 RESULT=skip>
16702 10:55:14.993289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1568 RESULT=skip>
16703 10:55:14.993589 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1568 RESULT=skip
16705 10:55:15.028845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1584 RESULT=pass>
16706 10:55:15.029139 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1584 RESULT=pass
16708 10:55:15.063517 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1584 RESULT=skip>
16709 10:55:15.063873 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1584 RESULT=skip
16711 10:55:15.098636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1584 RESULT=skip>
16712 10:55:15.099003 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1584 RESULT=skip
16714 10:55:15.133177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1584 RESULT=skip>
16715 10:55:15.133549 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1584 RESULT=skip
16717 10:55:15.168914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1600 RESULT=pass>
16718 10:55:15.169201 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1600 RESULT=pass
16720 10:55:15.204197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1600 RESULT=skip>
16721 10:55:15.204567 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1600 RESULT=skip
16723 10:55:15.238121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1600 RESULT=skip>
16724 10:55:15.238476 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1600 RESULT=skip
16726 10:55:15.272242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1600 RESULT=skip>
16727 10:55:15.272629 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1600 RESULT=skip
16729 10:55:15.309036 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1616 RESULT=pass
16731 10:55:15.309706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1616 RESULT=pass>
16732 10:55:15.345221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1616 RESULT=skip>
16733 10:55:15.345627 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1616 RESULT=skip
16735 10:55:15.380391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1616 RESULT=skip>
16736 10:55:15.380797 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1616 RESULT=skip
16738 10:55:15.414437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1616 RESULT=skip>
16739 10:55:15.414855 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1616 RESULT=skip
16741 10:55:15.449748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1632 RESULT=pass>
16742 10:55:15.450156 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1632 RESULT=pass
16744 10:55:15.486075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1632 RESULT=skip>
16745 10:55:15.486489 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1632 RESULT=skip
16747 10:55:15.521779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1632 RESULT=skip>
16748 10:55:15.522181 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1632 RESULT=skip
16750 10:55:15.556917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1632 RESULT=skip>
16751 10:55:15.557299 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1632 RESULT=skip
16753 10:55:15.592667 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1648 RESULT=pass
16755 10:55:15.593131 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1648 RESULT=pass>
16756 10:55:15.627561 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1648 RESULT=skip
16758 10:55:15.628036 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1648 RESULT=skip>
16759 10:55:15.662016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1648 RESULT=skip>
16760 10:55:15.662451 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1648 RESULT=skip
16762 10:55:15.697335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1648 RESULT=skip>
16763 10:55:15.697677 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1648 RESULT=skip
16765 10:55:15.732592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1664 RESULT=pass>
16766 10:55:15.733028 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1664 RESULT=pass
16768 10:55:15.768800 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1664 RESULT=skip>
16769 10:55:15.769221 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1664 RESULT=skip
16771 10:55:15.804579 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1664 RESULT=skip>
16772 10:55:15.804975 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1664 RESULT=skip
16774 10:55:15.843575 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1664 RESULT=skip>
16775 10:55:15.843961 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1664 RESULT=skip
16777 10:55:15.882530 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1680 RESULT=pass>
16778 10:55:15.882963 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1680 RESULT=pass
16780 10:55:15.918996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1680 RESULT=skip>
16781 10:55:15.919377 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1680 RESULT=skip
16783 10:55:15.953776 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1680 RESULT=skip
16785 10:55:15.954155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1680 RESULT=skip>
16786 10:55:15.987394 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1680 RESULT=skip>
16787 10:55:15.987686 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1680 RESULT=skip
16789 10:55:16.022481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1696 RESULT=pass>
16790 10:55:16.022973 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1696 RESULT=pass
16792 10:55:16.058011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1696 RESULT=skip>
16793 10:55:16.058473 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1696 RESULT=skip
16795 10:55:16.094141 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1696 RESULT=skip>
16796 10:55:16.094673 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1696 RESULT=skip
16798 10:55:16.129705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1696 RESULT=skip>
16799 10:55:16.130095 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1696 RESULT=skip
16801 10:55:16.167383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1712 RESULT=pass>
16802 10:55:16.167837 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1712 RESULT=pass
16804 10:55:16.203440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1712 RESULT=skip>
16805 10:55:16.203912 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1712 RESULT=skip
16807 10:55:16.239825 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1712 RESULT=skip
16809 10:55:16.240459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1712 RESULT=skip>
16810 10:55:16.277855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1712 RESULT=skip>
16811 10:55:16.278285 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1712 RESULT=skip
16813 10:55:16.309716 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1728 RESULT=pass>
16814 10:55:16.310147 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1728 RESULT=pass
16816 10:55:16.341492 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1728 RESULT=skip>
16817 10:55:16.341931 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1728 RESULT=skip
16819 10:55:16.373303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1728 RESULT=skip>
16820 10:55:16.373743 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1728 RESULT=skip
16822 10:55:16.406547 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1728 RESULT=skip
16824 10:55:16.407176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1728 RESULT=skip>
16825 10:55:16.445986 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1744 RESULT=pass
16827 10:55:16.446558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1744 RESULT=pass>
16828 10:55:16.479338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1744 RESULT=skip>
16829 10:55:16.479765 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1744 RESULT=skip
16831 10:55:16.512855 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1744 RESULT=skip
16833 10:55:16.513308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1744 RESULT=skip>
16834 10:55:16.544658 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1744 RESULT=skip>
16835 10:55:16.545084 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1744 RESULT=skip
16837 10:55:16.575723 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1760 RESULT=pass
16839 10:55:16.576155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1760 RESULT=pass>
16840 10:55:16.606924 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1760 RESULT=skip>
16841 10:55:16.607363 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1760 RESULT=skip
16843 10:55:16.640530 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1760 RESULT=skip>
16844 10:55:16.640951 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1760 RESULT=skip
16846 10:55:16.672244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1760 RESULT=skip>
16847 10:55:16.672642 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1760 RESULT=skip
16849 10:55:16.705322 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1776 RESULT=pass>
16850 10:55:16.705752 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1776 RESULT=pass
16852 10:55:16.738324 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1776 RESULT=skip
16854 10:55:16.738906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1776 RESULT=skip>
16855 10:55:16.770600 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1776 RESULT=skip
16857 10:55:16.771168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1776 RESULT=skip>
16858 10:55:16.804976 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1776 RESULT=skip
16860 10:55:16.805456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1776 RESULT=skip>
16861 10:55:16.844515 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1792 RESULT=pass
16863 10:55:16.844908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1792 RESULT=pass>
16864 10:55:16.877066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1792 RESULT=skip>
16865 10:55:16.877451 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1792 RESULT=skip
16867 10:55:16.917696 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1792 RESULT=skip>
16868 10:55:16.918143 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1792 RESULT=skip
16870 10:55:16.951824 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1792 RESULT=skip
16872 10:55:16.952432 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1792 RESULT=skip>
16873 10:55:16.985352 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1808 RESULT=pass
16875 10:55:16.985766 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1808 RESULT=pass>
16876 10:55:17.019902 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1808 RESULT=skip
16878 10:55:17.020310 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1808 RESULT=skip>
16879 10:55:17.053486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1808 RESULT=skip>
16880 10:55:17.053915 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1808 RESULT=skip
16882 10:55:17.086209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1808 RESULT=skip>
16883 10:55:17.086620 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1808 RESULT=skip
16885 10:55:17.119207 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1824 RESULT=pass
16887 10:55:17.119675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1824 RESULT=pass>
16888 10:55:17.152516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1824 RESULT=skip>
16889 10:55:17.152936 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1824 RESULT=skip
16891 10:55:17.185707 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1824 RESULT=skip
16893 10:55:17.186165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1824 RESULT=skip>
16894 10:55:17.217865 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1824 RESULT=skip
16896 10:55:17.218432 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1824 RESULT=skip>
16897 10:55:17.251718 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1840 RESULT=pass
16899 10:55:17.252145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1840 RESULT=pass>
16900 10:55:17.284157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1840 RESULT=skip>
16901 10:55:17.284640 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1840 RESULT=skip
16903 10:55:17.316180 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1840 RESULT=skip>
16904 10:55:17.316629 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1840 RESULT=skip
16906 10:55:17.346649 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1840 RESULT=skip>
16907 10:55:17.347131 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1840 RESULT=skip
16909 10:55:17.377827 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1856 RESULT=pass
16911 10:55:17.378270 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1856 RESULT=pass>
16912 10:55:17.408973 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1856 RESULT=skip>
16913 10:55:17.409408 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1856 RESULT=skip
16915 10:55:17.441159 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1856 RESULT=skip>
16916 10:55:17.441600 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1856 RESULT=skip
16918 10:55:17.475415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1856 RESULT=skip>
16919 10:55:17.475859 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1856 RESULT=skip
16921 10:55:17.508144 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1872 RESULT=pass>
16922 10:55:17.508625 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1872 RESULT=pass
16924 10:55:17.540248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1872 RESULT=skip>
16925 10:55:17.540724 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1872 RESULT=skip
16927 10:55:17.572191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1872 RESULT=skip>
16928 10:55:17.572672 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1872 RESULT=skip
16930 10:55:17.603220 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1872 RESULT=skip
16932 10:55:17.603790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1872 RESULT=skip>
16933 10:55:17.633860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1888 RESULT=pass>
16934 10:55:17.634339 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1888 RESULT=pass
16936 10:55:17.668361 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1888 RESULT=skip
16938 10:55:17.668748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1888 RESULT=skip>
16939 10:55:17.701479 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1888 RESULT=skip
16941 10:55:17.701961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1888 RESULT=skip>
16942 10:55:17.734627 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1888 RESULT=skip
16944 10:55:17.735387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1888 RESULT=skip>
16945 10:55:17.767943 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1904 RESULT=pass
16947 10:55:17.768511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1904 RESULT=pass>
16948 10:55:17.806249 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1904 RESULT=skip
16950 10:55:17.806977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1904 RESULT=skip>
16951 10:55:17.840578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1904 RESULT=skip>
16952 10:55:17.841015 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1904 RESULT=skip
16954 10:55:17.882924 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1904 RESULT=skip>
16955 10:55:17.883340 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1904 RESULT=skip
16957 10:55:17.920439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1920 RESULT=pass>
16958 10:55:17.920838 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1920 RESULT=pass
16960 10:55:17.953072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1920 RESULT=skip>
16961 10:55:17.953476 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1920 RESULT=skip
16963 10:55:17.986611 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1920 RESULT=skip>
16964 10:55:17.987055 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1920 RESULT=skip
16966 10:55:18.018484 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1920 RESULT=skip>
16967 10:55:18.018924 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1920 RESULT=skip
16969 10:55:18.050433 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1936 RESULT=pass
16971 10:55:18.050897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1936 RESULT=pass>
16972 10:55:18.084758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1936 RESULT=skip>
16973 10:55:18.085187 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1936 RESULT=skip
16975 10:55:18.117312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1936 RESULT=skip>
16976 10:55:18.117747 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1936 RESULT=skip
16978 10:55:18.150593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1936 RESULT=skip>
16979 10:55:18.151046 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1936 RESULT=skip
16981 10:55:18.183446 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1952 RESULT=pass>
16982 10:55:18.183861 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1952 RESULT=pass
16984 10:55:18.217467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1952 RESULT=skip>
16985 10:55:18.217911 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1952 RESULT=skip
16987 10:55:18.253398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1952 RESULT=skip>
16988 10:55:18.253857 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1952 RESULT=skip
16990 10:55:18.293179 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1952 RESULT=skip>
16991 10:55:18.293642 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1952 RESULT=skip
16993 10:55:18.328699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1968 RESULT=pass>
16994 10:55:18.329143 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1968 RESULT=pass
16996 10:55:18.361111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1968 RESULT=skip>
16997 10:55:18.361491 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1968 RESULT=skip
16999 10:55:18.393558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1968 RESULT=skip>
17000 10:55:18.393989 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1968 RESULT=skip
17002 10:55:18.428638 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1968 RESULT=skip>
17003 10:55:18.429069 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1968 RESULT=skip
17005 10:55:18.465452 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1984 RESULT=pass
17007 10:55:18.465917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1984 RESULT=pass>
17008 10:55:18.499551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1984 RESULT=skip>
17009 10:55:18.499955 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1984 RESULT=skip
17011 10:55:18.531505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1984 RESULT=skip>
17012 10:55:18.531911 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1984 RESULT=skip
17014 10:55:18.564434 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1984 RESULT=skip>
17015 10:55:18.564858 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1984 RESULT=skip
17017 10:55:18.596364 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2000 RESULT=pass
17019 10:55:18.596981 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2000 RESULT=pass>
17020 10:55:18.629140 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2000 RESULT=skip>
17021 10:55:18.629708 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2000 RESULT=skip
17023 10:55:18.660666 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2000 RESULT=skip>
17024 10:55:18.661148 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2000 RESULT=skip
17026 10:55:18.691392 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2000 RESULT=skip
17028 10:55:18.691795 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2000 RESULT=skip>
17029 10:55:18.722845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2016 RESULT=pass>
17030 10:55:18.723252 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2016 RESULT=pass
17032 10:55:18.754139 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2016 RESULT=skip>
17033 10:55:18.754610 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2016 RESULT=skip
17035 10:55:18.785107 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2016 RESULT=skip
17037 10:55:18.785640 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2016 RESULT=skip>
17038 10:55:18.816114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2016 RESULT=skip>
17039 10:55:18.816564 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2016 RESULT=skip
17041 10:55:18.848235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2032 RESULT=pass>
17042 10:55:18.848683 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2032 RESULT=pass
17044 10:55:18.879683 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2032 RESULT=skip
17046 10:55:18.880152 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2032 RESULT=skip>
17047 10:55:18.912414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2032 RESULT=skip>
17048 10:55:18.912858 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2032 RESULT=skip
17050 10:55:18.945226 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2032 RESULT=skip>
17051 10:55:18.945672 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2032 RESULT=skip
17053 10:55:18.979371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2048 RESULT=pass>
17054 10:55:18.979828 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2048 RESULT=pass
17056 10:55:19.011798 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2048 RESULT=skip
17058 10:55:19.012395 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2048 RESULT=skip>
17059 10:55:19.043041 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2048 RESULT=skip
17061 10:55:19.043596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2048 RESULT=skip>
17062 10:55:19.073951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2048 RESULT=skip>
17063 10:55:19.074362 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2048 RESULT=skip
17065 10:55:19.106147 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2064 RESULT=pass
17067 10:55:19.106617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2064 RESULT=pass>
17068 10:55:19.138726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2064 RESULT=skip>
17069 10:55:19.139130 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2064 RESULT=skip
17071 10:55:19.170718 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2064 RESULT=skip
17073 10:55:19.171167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2064 RESULT=skip>
17074 10:55:19.202418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2064 RESULT=skip>
17075 10:55:19.202825 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2064 RESULT=skip
17077 10:55:19.234594 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2080 RESULT=pass
17079 10:55:19.235238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2080 RESULT=pass>
17080 10:55:19.265717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2080 RESULT=skip>
17081 10:55:19.266114 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2080 RESULT=skip
17083 10:55:19.297102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2080 RESULT=skip>
17084 10:55:19.297508 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2080 RESULT=skip
17086 10:55:19.328507 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2080 RESULT=skip
17088 10:55:19.328933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2080 RESULT=skip>
17089 10:55:19.360216 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2096 RESULT=pass>
17090 10:55:19.360708 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2096 RESULT=pass
17092 10:55:19.390904 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2096 RESULT=skip>
17093 10:55:19.391383 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2096 RESULT=skip
17095 10:55:19.423200 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2096 RESULT=skip
17097 10:55:19.423772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2096 RESULT=skip>
17098 10:55:19.455029 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2096 RESULT=skip
17100 10:55:19.455586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2096 RESULT=skip>
17101 10:55:19.487206 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2112 RESULT=pass
17103 10:55:19.487985 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2112 RESULT=pass>
17104 10:55:19.522655 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2112 RESULT=skip>
17105 10:55:19.523125 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2112 RESULT=skip
17107 10:55:19.554963 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2112 RESULT=skip
17109 10:55:19.555427 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2112 RESULT=skip>
17110 10:55:19.587129 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2112 RESULT=skip>
17111 10:55:19.587565 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2112 RESULT=skip
17113 10:55:19.619277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2128 RESULT=pass>
17114 10:55:19.619723 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2128 RESULT=pass
17116 10:55:19.653637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2128 RESULT=skip>
17117 10:55:19.654083 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2128 RESULT=skip
17119 10:55:19.686238 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2128 RESULT=skip
17121 10:55:19.686684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2128 RESULT=skip>
17122 10:55:19.719350 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2128 RESULT=skip
17124 10:55:19.719826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2128 RESULT=skip>
17125 10:55:19.753333 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2144 RESULT=pass
17127 10:55:19.753806 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2144 RESULT=pass>
17128 10:55:19.785887 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2144 RESULT=skip
17130 10:55:19.786336 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2144 RESULT=skip>
17131 10:55:19.818875 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2144 RESULT=skip>
17132 10:55:19.819290 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2144 RESULT=skip
17134 10:55:19.851095 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2144 RESULT=skip>
17135 10:55:19.851534 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2144 RESULT=skip
17137 10:55:19.882420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2160 RESULT=pass>
17138 10:55:19.882861 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2160 RESULT=pass
17140 10:55:19.913883 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2160 RESULT=skip
17142 10:55:19.914466 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2160 RESULT=skip>
17143 10:55:19.946055 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2160 RESULT=skip>
17144 10:55:19.946516 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2160 RESULT=skip
17146 10:55:19.977712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2160 RESULT=skip>
17147 10:55:19.978120 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2160 RESULT=skip
17149 10:55:20.009253 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2176 RESULT=pass
17151 10:55:20.009834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2176 RESULT=pass>
17152 10:55:20.040867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2176 RESULT=skip>
17153 10:55:20.041281 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2176 RESULT=skip
17155 10:55:20.073027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2176 RESULT=skip>
17156 10:55:20.073433 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2176 RESULT=skip
17158 10:55:20.106699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2176 RESULT=skip>
17159 10:55:20.107137 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2176 RESULT=skip
17161 10:55:20.140058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2192 RESULT=pass>
17162 10:55:20.140562 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2192 RESULT=pass
17164 10:55:20.172641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2192 RESULT=skip>
17165 10:55:20.173123 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2192 RESULT=skip
17167 10:55:20.204065 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2192 RESULT=skip>
17168 10:55:20.204517 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2192 RESULT=skip
17170 10:55:20.235844 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2192 RESULT=skip
17172 10:55:20.236524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2192 RESULT=skip>
17173 10:55:20.267841 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2208 RESULT=pass
17175 10:55:20.268500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2208 RESULT=pass>
17176 10:55:20.301041 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2208 RESULT=skip
17178 10:55:20.301509 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2208 RESULT=skip>
17179 10:55:20.335288 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2208 RESULT=skip
17181 10:55:20.335717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2208 RESULT=skip>
17182 10:55:20.367525 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2208 RESULT=skip
17184 10:55:20.367948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2208 RESULT=skip>
17185 10:55:20.400796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2224 RESULT=pass>
17186 10:55:20.401242 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2224 RESULT=pass
17188 10:55:20.438446 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2224 RESULT=skip
17190 10:55:20.438912 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2224 RESULT=skip>
17191 10:55:20.471284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2224 RESULT=skip>
17192 10:55:20.471696 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2224 RESULT=skip
17194 10:55:20.505822 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2224 RESULT=skip
17196 10:55:20.506278 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2224 RESULT=skip>
17197 10:55:20.538093 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2240 RESULT=pass
17199 10:55:20.538659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2240 RESULT=pass>
17200 10:55:20.570579 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2240 RESULT=skip>
17201 10:55:20.571053 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2240 RESULT=skip
17203 10:55:20.606102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2240 RESULT=skip>
17204 10:55:20.606545 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2240 RESULT=skip
17206 10:55:20.638363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2240 RESULT=skip>
17207 10:55:20.638797 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2240 RESULT=skip
17209 10:55:20.673799 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2256 RESULT=pass>
17210 10:55:20.674238 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2256 RESULT=pass
17212 10:55:20.718272 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2256 RESULT=skip
17214 10:55:20.718733 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2256 RESULT=skip>
17215 10:55:20.750251 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2256 RESULT=skip
17217 10:55:20.750825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2256 RESULT=skip>
17218 10:55:20.791174 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2256 RESULT=skip
17220 10:55:20.791650 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2256 RESULT=skip>
17221 10:55:20.825928 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2272 RESULT=pass>
17222 10:55:20.826409 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2272 RESULT=pass
17224 10:55:20.859930 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2272 RESULT=skip
17226 10:55:20.860391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2272 RESULT=skip>
17227 10:55:20.905503 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2272 RESULT=skip>
17228 10:55:20.906004 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2272 RESULT=skip
17230 10:55:20.937011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2272 RESULT=skip>
17231 10:55:20.937469 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2272 RESULT=skip
17233 10:55:20.981267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2288 RESULT=pass>
17234 10:55:20.981748 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2288 RESULT=pass
17236 10:55:21.017949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2288 RESULT=skip>
17237 10:55:21.018429 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2288 RESULT=skip
17239 10:55:21.054217 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2288 RESULT=skip>
17240 10:55:21.054670 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2288 RESULT=skip
17242 10:55:21.088448 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2288 RESULT=skip
17244 10:55:21.088856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2288 RESULT=skip>
17245 10:55:21.120964 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2304 RESULT=pass>
17246 10:55:21.121394 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2304 RESULT=pass
17248 10:55:21.153526 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2304 RESULT=skip>
17249 10:55:21.154042 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2304 RESULT=skip
17251 10:55:21.189892 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2304 RESULT=skip>
17252 10:55:21.190386 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2304 RESULT=skip
17254 10:55:21.221808 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2304 RESULT=skip
17256 10:55:21.222273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2304 RESULT=skip>
17257 10:55:21.258265 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2320 RESULT=pass
17259 10:55:21.258733 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2320 RESULT=pass>
17260 10:55:21.291378 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2320 RESULT=skip
17262 10:55:21.291818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2320 RESULT=skip>
17263 10:55:21.322650 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2320 RESULT=skip
17265 10:55:21.323130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2320 RESULT=skip>
17266 10:55:21.356682 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2320 RESULT=skip
17268 10:55:21.357136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2320 RESULT=skip>
17269 10:55:21.389433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2336 RESULT=pass>
17270 10:55:21.389888 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2336 RESULT=pass
17272 10:55:21.421118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2336 RESULT=skip>
17273 10:55:21.421629 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2336 RESULT=skip
17275 10:55:21.454213 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2336 RESULT=skip
17277 10:55:21.454669 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2336 RESULT=skip>
17278 10:55:21.487275 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2336 RESULT=skip
17280 10:55:21.487925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2336 RESULT=skip>
17281 10:55:21.520873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2352 RESULT=pass>
17282 10:55:21.521343 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2352 RESULT=pass
17284 10:55:21.556526 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2352 RESULT=skip
17286 10:55:21.557089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2352 RESULT=skip>
17287 10:55:21.588757 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2352 RESULT=skip
17289 10:55:21.589320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2352 RESULT=skip>
17290 10:55:21.623114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2352 RESULT=skip>
17291 10:55:21.623532 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2352 RESULT=skip
17293 10:55:21.657049 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2368 RESULT=pass
17295 10:55:21.657523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2368 RESULT=pass>
17296 10:55:21.688757 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2368 RESULT=skip
17298 10:55:21.689351 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2368 RESULT=skip>
17299 10:55:21.720952 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2368 RESULT=skip
17301 10:55:21.721420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2368 RESULT=skip>
17302 10:55:21.755237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2368 RESULT=skip>
17303 10:55:21.755682 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2368 RESULT=skip
17305 10:55:21.788120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2384 RESULT=pass>
17306 10:55:21.788584 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2384 RESULT=pass
17308 10:55:21.824076 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2384 RESULT=skip
17310 10:55:21.824533 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2384 RESULT=skip>
17311 10:55:21.856853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2384 RESULT=skip>
17312 10:55:21.857287 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2384 RESULT=skip
17314 10:55:21.890083 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2384 RESULT=skip
17316 10:55:21.890542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2384 RESULT=skip>
17317 10:55:21.929190 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2400 RESULT=pass
17319 10:55:21.929639 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2400 RESULT=pass>
17320 10:55:21.965122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2400 RESULT=skip>
17321 10:55:21.965523 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2400 RESULT=skip
17323 10:55:22.004837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2400 RESULT=skip>
17324 10:55:22.005309 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2400 RESULT=skip
17326 10:55:22.056759 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2400 RESULT=skip
17328 10:55:22.057213 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2400 RESULT=skip>
17329 10:55:22.105013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2416 RESULT=pass>
17330 10:55:22.105394 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2416 RESULT=pass
17332 10:55:22.141622 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2416 RESULT=skip>
17333 10:55:22.142008 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2416 RESULT=skip
17335 10:55:22.177984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2416 RESULT=skip>
17336 10:55:22.178401 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2416 RESULT=skip
17338 10:55:22.215531 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2416 RESULT=skip>
17339 10:55:22.215949 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2416 RESULT=skip
17341 10:55:22.253356 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2432 RESULT=pass
17343 10:55:22.253822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2432 RESULT=pass>
17344 10:55:22.289504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2432 RESULT=skip>
17345 10:55:22.289840 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2432 RESULT=skip
17347 10:55:22.333558 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2432 RESULT=skip
17349 10:55:22.334039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2432 RESULT=skip>
17350 10:55:22.386888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2432 RESULT=skip>
17351 10:55:22.387336 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2432 RESULT=skip
17353 10:55:22.437234 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2448 RESULT=pass
17355 10:55:22.437718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2448 RESULT=pass>
17356 10:55:22.476704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2448 RESULT=skip>
17357 10:55:22.477215 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2448 RESULT=skip
17359 10:55:22.517864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2448 RESULT=skip>
17360 10:55:22.518320 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2448 RESULT=skip
17362 10:55:22.557811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2448 RESULT=skip>
17363 10:55:22.558242 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2448 RESULT=skip
17365 10:55:22.595252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2464 RESULT=pass>
17366 10:55:22.595692 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2464 RESULT=pass
17368 10:55:22.635245 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2464 RESULT=skip>
17369 10:55:22.635673 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2464 RESULT=skip
17371 10:55:22.666547 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2464 RESULT=skip>
17372 10:55:22.666983 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2464 RESULT=skip
17374 10:55:22.697492 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2464 RESULT=skip>
17375 10:55:22.697927 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2464 RESULT=skip
17377 10:55:22.728703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2480 RESULT=pass>
17378 10:55:22.729142 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2480 RESULT=pass
17380 10:55:22.761056 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2480 RESULT=skip
17382 10:55:22.761626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2480 RESULT=skip>
17383 10:55:22.793423 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2480 RESULT=skip>
17384 10:55:22.793888 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2480 RESULT=skip
17386 10:55:22.825369 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2480 RESULT=skip
17388 10:55:22.825829 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2480 RESULT=skip>
17389 10:55:22.856709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2496 RESULT=pass>
17390 10:55:22.857137 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2496 RESULT=pass
17392 10:55:22.888427 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2496 RESULT=skip>
17393 10:55:22.888848 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2496 RESULT=skip
17395 10:55:22.919861 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2496 RESULT=skip
17397 10:55:22.920315 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2496 RESULT=skip>
17398 10:55:22.951014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2496 RESULT=skip>
17399 10:55:22.951430 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2496 RESULT=skip
17401 10:55:22.982715 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2512 RESULT=pass
17403 10:55:22.983158 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2512 RESULT=pass>
17404 10:55:23.014073 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2512 RESULT=skip>
17405 10:55:23.014547 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2512 RESULT=skip
17407 10:55:23.045712 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2512 RESULT=skip
17409 10:55:23.046171 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2512 RESULT=skip>
17410 10:55:23.077807 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2512 RESULT=skip
17412 10:55:23.078258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2512 RESULT=skip>
17413 10:55:23.109677 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2528 RESULT=pass
17415 10:55:23.110126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2528 RESULT=pass>
17416 10:55:23.141362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2528 RESULT=skip>
17417 10:55:23.141775 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2528 RESULT=skip
17419 10:55:23.172785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2528 RESULT=skip>
17420 10:55:23.173210 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2528 RESULT=skip
17422 10:55:23.204594 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2528 RESULT=skip
17424 10:55:23.205060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2528 RESULT=skip>
17425 10:55:23.239882 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2544 RESULT=pass
17427 10:55:23.240361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2544 RESULT=pass>
17428 10:55:23.278319 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2544 RESULT=skip
17430 10:55:23.278931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2544 RESULT=skip>
17431 10:55:23.312763 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2544 RESULT=skip>
17432 10:55:23.313209 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2544 RESULT=skip
17434 10:55:23.348390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2544 RESULT=skip>
17435 10:55:23.348818 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2544 RESULT=skip
17437 10:55:23.383445 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2560 RESULT=pass
17439 10:55:23.383898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2560 RESULT=pass>
17440 10:55:23.417937 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2560 RESULT=skip
17442 10:55:23.418399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2560 RESULT=skip>
17443 10:55:23.450668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2560 RESULT=skip>
17444 10:55:23.451040 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2560 RESULT=skip
17446 10:55:23.483334 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2560 RESULT=skip
17448 10:55:23.483808 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2560 RESULT=skip>
17449 10:55:23.514169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2576 RESULT=pass>
17450 10:55:23.514607 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2576 RESULT=pass
17452 10:55:23.545654 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2576 RESULT=skip>
17453 10:55:23.546095 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2576 RESULT=skip
17455 10:55:23.576798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2576 RESULT=skip>
17456 10:55:23.577239 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2576 RESULT=skip
17458 10:55:23.608232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2576 RESULT=skip>
17459 10:55:23.608677 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2576 RESULT=skip
17461 10:55:23.639446 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2592 RESULT=pass>
17462 10:55:23.639880 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2592 RESULT=pass
17464 10:55:23.677966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2592 RESULT=skip>
17465 10:55:23.678374 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2592 RESULT=skip
17467 10:55:23.714722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2592 RESULT=skip>
17468 10:55:23.715164 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2592 RESULT=skip
17470 10:55:23.745677 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2592 RESULT=skip>
17471 10:55:23.746124 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2592 RESULT=skip
17473 10:55:23.777161 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2608 RESULT=pass>
17474 10:55:23.777605 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2608 RESULT=pass
17476 10:55:23.808030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2608 RESULT=skip>
17477 10:55:23.808464 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2608 RESULT=skip
17479 10:55:23.838277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2608 RESULT=skip>
17480 10:55:23.838716 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2608 RESULT=skip
17482 10:55:23.869580 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2608 RESULT=skip
17484 10:55:23.870052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2608 RESULT=skip>
17485 10:55:23.900058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2624 RESULT=pass>
17486 10:55:23.900455 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2624 RESULT=pass
17488 10:55:23.930592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2624 RESULT=skip>
17489 10:55:23.931036 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2624 RESULT=skip
17491 10:55:23.961345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2624 RESULT=skip>
17492 10:55:23.961858 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2624 RESULT=skip
17494 10:55:23.992438 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2624 RESULT=skip>
17495 10:55:23.992912 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2624 RESULT=skip
17497 10:55:24.023774 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2640 RESULT=pass
17499 10:55:24.024334 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2640 RESULT=pass>
17500 10:55:24.054727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2640 RESULT=skip>
17501 10:55:24.055155 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2640 RESULT=skip
17503 10:55:24.086102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2640 RESULT=skip>
17504 10:55:24.086519 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2640 RESULT=skip
17506 10:55:24.118258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2640 RESULT=skip>
17507 10:55:24.118658 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2640 RESULT=skip
17509 10:55:24.149777 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2656 RESULT=pass>
17510 10:55:24.150200 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2656 RESULT=pass
17512 10:55:24.181181 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2656 RESULT=skip>
17513 10:55:24.181612 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2656 RESULT=skip
17515 10:55:24.212885 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2656 RESULT=skip
17517 10:55:24.213334 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2656 RESULT=skip>
17518 10:55:24.244072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2656 RESULT=skip>
17519 10:55:24.244495 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2656 RESULT=skip
17521 10:55:24.276208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2672 RESULT=pass>
17522 10:55:24.276635 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2672 RESULT=pass
17524 10:55:24.307424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2672 RESULT=skip>
17525 10:55:24.307860 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2672 RESULT=skip
17527 10:55:24.339221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2672 RESULT=skip>
17528 10:55:24.339656 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2672 RESULT=skip
17530 10:55:24.371237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2672 RESULT=skip>
17531 10:55:24.371668 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2672 RESULT=skip
17533 10:55:24.403027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2688 RESULT=pass>
17534 10:55:24.403451 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2688 RESULT=pass
17536 10:55:24.434155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2688 RESULT=skip>
17537 10:55:24.434570 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2688 RESULT=skip
17539 10:55:24.466702 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2688 RESULT=skip
17541 10:55:24.467173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2688 RESULT=skip>
17542 10:55:24.498049 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2688 RESULT=skip
17544 10:55:24.498521 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2688 RESULT=skip>
17545 10:55:24.529152 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2704 RESULT=pass>
17546 10:55:24.529599 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2704 RESULT=pass
17548 10:55:24.560713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2704 RESULT=skip>
17549 10:55:24.561154 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2704 RESULT=skip
17551 10:55:24.591651 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2704 RESULT=skip>
17552 10:55:24.592111 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2704 RESULT=skip
17554 10:55:24.623235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2704 RESULT=skip>
17555 10:55:24.623639 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2704 RESULT=skip
17557 10:55:24.658186 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2720 RESULT=pass>
17558 10:55:24.658621 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2720 RESULT=pass
17560 10:55:24.690690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2720 RESULT=skip>
17561 10:55:24.691124 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2720 RESULT=skip
17563 10:55:24.722399 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2720 RESULT=skip
17565 10:55:24.722847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2720 RESULT=skip>
17566 10:55:24.752912 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2720 RESULT=skip>
17567 10:55:24.753337 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2720 RESULT=skip
17569 10:55:24.784024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2736 RESULT=pass>
17570 10:55:24.784514 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2736 RESULT=pass
17572 10:55:24.815903 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2736 RESULT=skip
17574 10:55:24.816562 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2736 RESULT=skip>
17575 10:55:24.847125 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2736 RESULT=skip>
17576 10:55:24.847612 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2736 RESULT=skip
17578 10:55:24.878824 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2736 RESULT=skip
17580 10:55:24.879497 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2736 RESULT=skip>
17581 10:55:24.910166 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2752 RESULT=pass>
17582 10:55:24.910629 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2752 RESULT=pass
17584 10:55:24.941161 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2752 RESULT=skip>
17585 10:55:24.941613 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2752 RESULT=skip
17587 10:55:24.972592 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2752 RESULT=skip
17589 10:55:24.973053 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2752 RESULT=skip>
17590 10:55:25.004316 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2752 RESULT=skip
17592 10:55:25.004750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2752 RESULT=skip>
17593 10:55:25.036062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2768 RESULT=pass>
17594 10:55:25.036494 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2768 RESULT=pass
17596 10:55:25.067343 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2768 RESULT=skip>
17597 10:55:25.067768 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2768 RESULT=skip
17599 10:55:25.098788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2768 RESULT=skip>
17600 10:55:25.099223 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2768 RESULT=skip
17602 10:55:25.130122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2768 RESULT=skip>
17603 10:55:25.130561 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2768 RESULT=skip
17605 10:55:25.161110 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2784 RESULT=pass>
17606 10:55:25.161542 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2784 RESULT=pass
17608 10:55:25.192503 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2784 RESULT=skip>
17609 10:55:25.192940 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2784 RESULT=skip
17611 10:55:25.223504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2784 RESULT=skip>
17612 10:55:25.223939 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2784 RESULT=skip
17614 10:55:25.254817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2784 RESULT=skip>
17615 10:55:25.255254 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2784 RESULT=skip
17617 10:55:25.287076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2800 RESULT=pass>
17618 10:55:25.287503 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2800 RESULT=pass
17620 10:55:25.318719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2800 RESULT=skip>
17621 10:55:25.319134 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2800 RESULT=skip
17623 10:55:25.353822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2800 RESULT=skip>
17624 10:55:25.354226 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2800 RESULT=skip
17626 10:55:25.388423 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2800 RESULT=skip
17628 10:55:25.388902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2800 RESULT=skip>
17629 10:55:25.419928 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2816 RESULT=pass
17631 10:55:25.420369 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2816 RESULT=pass>
17632 10:55:25.451715 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2816 RESULT=skip
17634 10:55:25.452156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2816 RESULT=skip>
17635 10:55:25.486325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2816 RESULT=skip>
17636 10:55:25.486746 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2816 RESULT=skip
17638 10:55:25.518488 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2816 RESULT=skip
17640 10:55:25.519117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2816 RESULT=skip>
17641 10:55:25.549902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2832 RESULT=pass>
17642 10:55:25.550340 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2832 RESULT=pass
17644 10:55:25.581560 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2832 RESULT=skip
17646 10:55:25.582027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2832 RESULT=skip>
17647 10:55:25.613117 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2832 RESULT=skip
17649 10:55:25.613586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2832 RESULT=skip>
17650 10:55:25.644663 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2832 RESULT=skip>
17651 10:55:25.645092 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2832 RESULT=skip
17653 10:55:25.676528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2848 RESULT=pass>
17654 10:55:25.676960 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2848 RESULT=pass
17656 10:55:25.708614 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2848 RESULT=skip>
17657 10:55:25.709046 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2848 RESULT=skip
17659 10:55:25.740783 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2848 RESULT=skip
17661 10:55:25.741256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2848 RESULT=skip>
17662 10:55:25.772591 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2848 RESULT=skip
17664 10:55:25.773059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2848 RESULT=skip>
17665 10:55:25.804522 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2864 RESULT=pass>
17666 10:55:25.804954 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2864 RESULT=pass
17668 10:55:25.836744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2864 RESULT=skip>
17669 10:55:25.837183 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2864 RESULT=skip
17671 10:55:25.868456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2864 RESULT=skip>
17672 10:55:25.868899 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2864 RESULT=skip
17674 10:55:25.900192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2864 RESULT=skip>
17675 10:55:25.900632 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2864 RESULT=skip
17677 10:55:25.932375 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2880 RESULT=pass
17679 10:55:25.932820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2880 RESULT=pass>
17680 10:55:25.964490 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2880 RESULT=skip>
17681 10:55:25.964962 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2880 RESULT=skip
17683 10:55:25.996646 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2880 RESULT=skip>
17684 10:55:25.997058 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2880 RESULT=skip
17686 10:55:26.028608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2880 RESULT=skip>
17687 10:55:26.029011 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2880 RESULT=skip
17689 10:55:26.060815 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2896 RESULT=pass
17691 10:55:26.061260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2896 RESULT=pass>
17692 10:55:26.092653 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2896 RESULT=skip
17694 10:55:26.093120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2896 RESULT=skip>
17695 10:55:26.124568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2896 RESULT=skip>
17696 10:55:26.124983 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2896 RESULT=skip
17698 10:55:26.156842 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2896 RESULT=skip
17700 10:55:26.157293 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2896 RESULT=skip>
17701 10:55:26.191680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2912 RESULT=pass>
17702 10:55:26.192157 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2912 RESULT=pass
17704 10:55:26.223518 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2912 RESULT=skip
17706 10:55:26.224113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2912 RESULT=skip>
17707 10:55:26.255174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2912 RESULT=skip>
17708 10:55:26.255653 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2912 RESULT=skip
17710 10:55:26.287181 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2912 RESULT=skip>
17711 10:55:26.287598 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2912 RESULT=skip
17713 10:55:26.323616 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2928 RESULT=pass
17715 10:55:26.324090 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2928 RESULT=pass>
17716 10:55:26.359177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2928 RESULT=skip>
17717 10:55:26.359572 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2928 RESULT=skip
17719 10:55:26.395582 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2928 RESULT=skip
17721 10:55:26.396023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2928 RESULT=skip>
17722 10:55:26.432340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2928 RESULT=skip>
17723 10:55:26.432741 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2928 RESULT=skip
17725 10:55:26.468868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2944 RESULT=pass>
17726 10:55:26.469291 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2944 RESULT=pass
17728 10:55:26.504537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2944 RESULT=skip>
17729 10:55:26.504953 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2944 RESULT=skip
17731 10:55:26.540985 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2944 RESULT=skip>
17732 10:55:26.541406 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2944 RESULT=skip
17734 10:55:26.577360 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2944 RESULT=skip>
17735 10:55:26.577829 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2944 RESULT=skip
17737 10:55:26.612379 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2960 RESULT=pass
17739 10:55:26.612779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2960 RESULT=pass>
17740 10:55:26.647909 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2960 RESULT=skip
17742 10:55:26.648364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2960 RESULT=skip>
17743 10:55:26.683900 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2960 RESULT=skip
17745 10:55:26.684334 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2960 RESULT=skip>
17746 10:55:26.719222 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2960 RESULT=skip
17748 10:55:26.719691 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2960 RESULT=skip>
17749 10:55:26.754283 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2976 RESULT=pass>
17750 10:55:26.754691 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2976 RESULT=pass
17752 10:55:26.790326 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2976 RESULT=skip
17754 10:55:26.790776 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2976 RESULT=skip>
17755 10:55:26.824906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2976 RESULT=skip>
17756 10:55:26.825321 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2976 RESULT=skip
17758 10:55:26.860437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2976 RESULT=skip>
17759 10:55:26.860817 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2976 RESULT=skip
17761 10:55:26.896170 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2992 RESULT=pass>
17762 10:55:26.896593 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2992 RESULT=pass
17764 10:55:26.931943 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2992 RESULT=skip
17766 10:55:26.932390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2992 RESULT=skip>
17767 10:55:26.969408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2992 RESULT=skip>
17768 10:55:26.969749 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2992 RESULT=skip
17770 10:55:27.005250 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2992 RESULT=skip
17772 10:55:27.005878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2992 RESULT=skip>
17773 10:55:27.040935 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3008 RESULT=pass>
17774 10:55:27.041304 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3008 RESULT=pass
17776 10:55:27.076944 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3008 RESULT=skip>
17777 10:55:27.077316 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3008 RESULT=skip
17779 10:55:27.113356 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3008 RESULT=skip>
17780 10:55:27.113802 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3008 RESULT=skip
17782 10:55:27.149280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3008 RESULT=skip>
17783 10:55:27.149684 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3008 RESULT=skip
17785 10:55:27.185715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3024 RESULT=pass>
17786 10:55:27.186123 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3024 RESULT=pass
17788 10:55:27.221209 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3024 RESULT=skip
17790 10:55:27.221799 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3024 RESULT=skip>
17791 10:55:27.255895 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3024 RESULT=skip
17793 10:55:27.256197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3024 RESULT=skip>
17794 10:55:27.291199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3024 RESULT=skip>
17795 10:55:27.291484 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3024 RESULT=skip
17797 10:55:27.327512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3040 RESULT=pass>
17798 10:55:27.327871 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3040 RESULT=pass
17800 10:55:27.363185 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3040 RESULT=skip>
17801 10:55:27.363557 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3040 RESULT=skip
17803 10:55:27.397826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3040 RESULT=skip>
17804 10:55:27.398177 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3040 RESULT=skip
17806 10:55:27.432823 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3040 RESULT=skip>
17807 10:55:27.433119 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3040 RESULT=skip
17809 10:55:27.468379 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3056 RESULT=pass>
17810 10:55:27.468729 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3056 RESULT=pass
17812 10:55:27.504590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3056 RESULT=skip>
17813 10:55:27.504952 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3056 RESULT=skip
17815 10:55:27.539076 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3056 RESULT=skip
17817 10:55:27.539376 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3056 RESULT=skip>
17818 10:55:27.574774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3056 RESULT=skip>
17819 10:55:27.575069 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3056 RESULT=skip
17821 10:55:27.608928 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3072 RESULT=pass>
17822 10:55:27.609288 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3072 RESULT=pass
17824 10:55:27.645075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3072 RESULT=skip>
17825 10:55:27.645507 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3072 RESULT=skip
17827 10:55:27.681813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3072 RESULT=skip>
17828 10:55:27.682254 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3072 RESULT=skip
17830 10:55:27.718133 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3072 RESULT=skip>
17831 10:55:27.718428 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3072 RESULT=skip
17833 10:55:27.754054 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3088 RESULT=pass
17835 10:55:27.754542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3088 RESULT=pass>
17836 10:55:27.789085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3088 RESULT=skip>
17837 10:55:27.789436 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3088 RESULT=skip
17839 10:55:27.825521 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3088 RESULT=skip>
17840 10:55:27.825869 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3088 RESULT=skip
17842 10:55:27.861218 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3088 RESULT=skip>
17843 10:55:27.861510 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3088 RESULT=skip
17845 10:55:27.896705 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3104 RESULT=pass
17847 10:55:27.897162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3104 RESULT=pass>
17848 10:55:27.931085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3104 RESULT=skip>
17849 10:55:27.931474 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3104 RESULT=skip
17851 10:55:27.966762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3104 RESULT=skip>
17852 10:55:27.967180 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3104 RESULT=skip
17854 10:55:28.003067 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3104 RESULT=skip
17856 10:55:28.003717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3104 RESULT=skip>
17857 10:55:28.038879 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3120 RESULT=pass>
17858 10:55:28.039192 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3120 RESULT=pass
17860 10:55:28.073444 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3120 RESULT=skip>
17861 10:55:28.073736 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3120 RESULT=skip
17863 10:55:28.108997 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3120 RESULT=skip
17865 10:55:28.109314 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3120 RESULT=skip>
17866 10:55:28.144647 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3120 RESULT=skip>
17867 10:55:28.144943 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3120 RESULT=skip
17869 10:55:28.181002 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3136 RESULT=pass>
17870 10:55:28.181406 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3136 RESULT=pass
17872 10:55:28.217186 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3136 RESULT=skip
17874 10:55:28.217642 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3136 RESULT=skip>
17875 10:55:28.255311 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3136 RESULT=skip>
17876 10:55:28.255759 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3136 RESULT=skip
17878 10:55:28.291606 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3136 RESULT=skip
17880 10:55:28.292032 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3136 RESULT=skip>
17881 10:55:28.327839 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3152 RESULT=pass
17883 10:55:28.328302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3152 RESULT=pass>
17884 10:55:28.363515 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3152 RESULT=skip
17886 10:55:28.363907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3152 RESULT=skip>
17887 10:55:28.399294 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3152 RESULT=skip
17889 10:55:28.399726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3152 RESULT=skip>
17890 10:55:28.435973 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3152 RESULT=skip
17892 10:55:28.436333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3152 RESULT=skip>
17893 10:55:28.471850 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3168 RESULT=pass
17895 10:55:28.472269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3168 RESULT=pass>
17896 10:55:28.507200 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3168 RESULT=skip>
17897 10:55:28.507605 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3168 RESULT=skip
17899 10:55:28.542704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3168 RESULT=skip>
17900 10:55:28.543117 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3168 RESULT=skip
17902 10:55:28.578859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3168 RESULT=skip>
17903 10:55:28.579276 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3168 RESULT=skip
17905 10:55:28.614410 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3184 RESULT=pass
17907 10:55:28.614938 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3184 RESULT=pass>
17908 10:55:28.649909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3184 RESULT=skip>
17909 10:55:28.650276 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3184 RESULT=skip
17911 10:55:28.685169 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3184 RESULT=skip
17913 10:55:28.685615 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3184 RESULT=skip>
17914 10:55:28.721405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3184 RESULT=skip>
17915 10:55:28.721824 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3184 RESULT=skip
17917 10:55:28.757350 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3200 RESULT=pass
17919 10:55:28.757823 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3200 RESULT=pass>
17920 10:55:28.793203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3200 RESULT=skip>
17921 10:55:28.793696 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3200 RESULT=skip
17923 10:55:28.829789 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3200 RESULT=skip>
17924 10:55:28.830189 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3200 RESULT=skip
17926 10:55:28.865606 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3200 RESULT=skip>
17927 10:55:28.865952 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3200 RESULT=skip
17929 10:55:28.900255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3216 RESULT=pass>
17930 10:55:28.900544 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3216 RESULT=pass
17932 10:55:28.935753 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3216 RESULT=skip
17934 10:55:28.936073 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3216 RESULT=skip>
17935 10:55:28.972262 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3216 RESULT=skip>
17936 10:55:28.972575 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3216 RESULT=skip
17938 10:55:29.007046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3216 RESULT=skip>
17939 10:55:29.007331 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3216 RESULT=skip
17941 10:55:29.042074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3232 RESULT=pass>
17942 10:55:29.042369 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3232 RESULT=pass
17944 10:55:29.077267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3232 RESULT=skip>
17945 10:55:29.077628 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3232 RESULT=skip
17947 10:55:29.112592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3232 RESULT=skip>
17948 10:55:29.112946 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3232 RESULT=skip
17950 10:55:29.147405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3232 RESULT=skip>
17951 10:55:29.147877 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3232 RESULT=skip
17953 10:55:29.182711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3248 RESULT=pass>
17954 10:55:29.183077 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3248 RESULT=pass
17956 10:55:29.220002 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3248 RESULT=skip
17958 10:55:29.220577 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3248 RESULT=skip>
17959 10:55:29.251440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3248 RESULT=skip>
17960 10:55:29.251864 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3248 RESULT=skip
17962 10:55:29.283151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3248 RESULT=skip>
17963 10:55:29.283556 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3248 RESULT=skip
17965 10:55:29.314815 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3264 RESULT=pass
17967 10:55:29.315261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3264 RESULT=pass>
17968 10:55:29.346648 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3264 RESULT=skip>
17969 10:55:29.347073 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3264 RESULT=skip
17971 10:55:29.378313 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3264 RESULT=skip
17973 10:55:29.378909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3264 RESULT=skip>
17974 10:55:29.409389 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3264 RESULT=skip
17976 10:55:29.409996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3264 RESULT=skip>
17977 10:55:29.440480 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3280 RESULT=pass>
17978 10:55:29.440953 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3280 RESULT=pass
17980 10:55:29.471349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3280 RESULT=skip>
17981 10:55:29.471828 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3280 RESULT=skip
17983 10:55:29.503923 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3280 RESULT=skip
17985 10:55:29.504368 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3280 RESULT=skip>
17986 10:55:29.536718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3280 RESULT=skip>
17987 10:55:29.537157 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3280 RESULT=skip
17989 10:55:29.568239 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3296 RESULT=pass>
17990 10:55:29.568668 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3296 RESULT=pass
17992 10:55:29.599428 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3296 RESULT=skip
17994 10:55:29.599852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3296 RESULT=skip>
17995 10:55:29.631087 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3296 RESULT=skip
17997 10:55:29.631503 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3296 RESULT=skip>
17998 10:55:29.663179 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3296 RESULT=skip>
17999 10:55:29.663658 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3296 RESULT=skip
18001 10:55:29.697008 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3312 RESULT=pass>
18002 10:55:29.697493 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3312 RESULT=pass
18004 10:55:29.738828 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3312 RESULT=skip>
18005 10:55:29.739261 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3312 RESULT=skip
18007 10:55:29.770111 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3312 RESULT=skip
18009 10:55:29.770533 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3312 RESULT=skip>
18010 10:55:29.801397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3312 RESULT=skip>
18011 10:55:29.801791 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3312 RESULT=skip
18013 10:55:29.832821 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3328 RESULT=pass
18015 10:55:29.833284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3328 RESULT=pass>
18016 10:55:29.864556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3328 RESULT=skip>
18017 10:55:29.864983 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3328 RESULT=skip
18019 10:55:29.897637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3328 RESULT=skip>
18020 10:55:29.898056 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3328 RESULT=skip
18022 10:55:29.930165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3328 RESULT=skip>
18023 10:55:29.930602 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3328 RESULT=skip
18025 10:55:29.962627 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3344 RESULT=pass>
18026 10:55:29.963074 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3344 RESULT=pass
18028 10:55:29.995415 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3344 RESULT=skip
18030 10:55:29.995887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3344 RESULT=skip>
18031 10:55:30.029238 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3344 RESULT=skip
18033 10:55:30.029899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3344 RESULT=skip>
18034 10:55:30.061048 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3344 RESULT=skip>
18035 10:55:30.061530 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3344 RESULT=skip
18037 10:55:30.095312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3360 RESULT=pass>
18038 10:55:30.095755 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3360 RESULT=pass
18040 10:55:30.128706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3360 RESULT=skip>
18041 10:55:30.129127 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3360 RESULT=skip
18043 10:55:30.160935 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3360 RESULT=skip>
18044 10:55:30.161361 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3360 RESULT=skip
18046 10:55:30.192763 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3360 RESULT=skip>
18047 10:55:30.193189 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3360 RESULT=skip
18049 10:55:30.225586 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3376 RESULT=pass
18051 10:55:30.226057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3376 RESULT=pass>
18052 10:55:30.257554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3376 RESULT=skip>
18053 10:55:30.258002 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3376 RESULT=skip
18055 10:55:30.292551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3376 RESULT=skip>
18056 10:55:30.292999 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3376 RESULT=skip
18058 10:55:30.328740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3376 RESULT=skip>
18059 10:55:30.329149 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3376 RESULT=skip
18061 10:55:30.362049 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3392 RESULT=pass
18063 10:55:30.362511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3392 RESULT=pass>
18064 10:55:30.395168 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3392 RESULT=skip
18066 10:55:30.395622 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3392 RESULT=skip>
18067 10:55:30.442715 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3392 RESULT=skip
18069 10:55:30.443192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3392 RESULT=skip>
18070 10:55:30.475038 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3392 RESULT=skip
18072 10:55:30.475522 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3392 RESULT=skip>
18073 10:55:30.509032 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3408 RESULT=pass>
18074 10:55:30.509473 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3408 RESULT=pass
18076 10:55:30.541620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3408 RESULT=skip>
18077 10:55:30.542054 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3408 RESULT=skip
18079 10:55:30.574057 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3408 RESULT=skip
18081 10:55:30.574522 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3408 RESULT=skip>
18082 10:55:30.605948 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3408 RESULT=skip
18084 10:55:30.606415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3408 RESULT=skip>
18085 10:55:30.637535 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3424 RESULT=pass
18087 10:55:30.638004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3424 RESULT=pass>
18088 10:55:30.669223 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3424 RESULT=skip>
18089 10:55:30.669668 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3424 RESULT=skip
18091 10:55:30.701519 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3424 RESULT=skip
18093 10:55:30.701990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3424 RESULT=skip>
18094 10:55:30.733221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3424 RESULT=skip>
18095 10:55:30.733655 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3424 RESULT=skip
18097 10:55:30.766262 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3440 RESULT=pass
18099 10:55:30.766712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3440 RESULT=pass>
18100 10:55:30.808904 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3440 RESULT=skip>
18101 10:55:30.809313 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3440 RESULT=skip
18103 10:55:30.843543 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3440 RESULT=skip
18105 10:55:30.844246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3440 RESULT=skip>
18106 10:55:30.878165 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3440 RESULT=skip
18108 10:55:30.878858 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3440 RESULT=skip>
18109 10:55:30.910538 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3456 RESULT=pass
18111 10:55:30.911177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3456 RESULT=pass>
18112 10:55:30.942910 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3456 RESULT=skip
18114 10:55:30.943353 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3456 RESULT=skip>
18115 10:55:30.976664 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3456 RESULT=skip
18117 10:55:30.977119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3456 RESULT=skip>
18118 10:55:31.010159 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3456 RESULT=skip>
18119 10:55:31.010638 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3456 RESULT=skip
18121 10:55:31.043441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3472 RESULT=pass>
18122 10:55:31.043926 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3472 RESULT=pass
18124 10:55:31.077125 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3472 RESULT=skip
18126 10:55:31.077594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3472 RESULT=skip>
18127 10:55:31.111318 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3472 RESULT=skip
18129 10:55:31.111755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3472 RESULT=skip>
18130 10:55:31.145312 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3472 RESULT=skip
18132 10:55:31.145787 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3472 RESULT=skip>
18133 10:55:31.180051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3488 RESULT=pass>
18134 10:55:31.180540 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3488 RESULT=pass
18136 10:55:31.213148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3488 RESULT=skip>
18137 10:55:31.213625 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3488 RESULT=skip
18139 10:55:31.245993 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3488 RESULT=skip>
18140 10:55:31.246476 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3488 RESULT=skip
18142 10:55:31.279257 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3488 RESULT=skip>
18143 10:55:31.279753 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3488 RESULT=skip
18145 10:55:31.313020 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3504 RESULT=pass
18147 10:55:31.313613 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3504 RESULT=pass>
18148 10:55:31.346238 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3504 RESULT=skip
18150 10:55:31.346868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3504 RESULT=skip>
18151 10:55:31.379658 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3504 RESULT=skip>
18152 10:55:31.380128 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3504 RESULT=skip
18154 10:55:31.412802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3504 RESULT=skip>
18155 10:55:31.413230 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3504 RESULT=skip
18157 10:55:31.445306 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3520 RESULT=pass>
18158 10:55:31.445783 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3520 RESULT=pass
18160 10:55:31.478023 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3520 RESULT=skip
18162 10:55:31.478454 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3520 RESULT=skip>
18163 10:55:31.511426 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3520 RESULT=skip
18165 10:55:31.511865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3520 RESULT=skip>
18166 10:55:31.543873 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3520 RESULT=skip
18168 10:55:31.544289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3520 RESULT=skip>
18169 10:55:31.576738 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3536 RESULT=pass
18171 10:55:31.577364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3536 RESULT=pass>
18172 10:55:31.609208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3536 RESULT=skip>
18173 10:55:31.609707 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3536 RESULT=skip
18175 10:55:31.642746 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3536 RESULT=skip>
18176 10:55:31.643175 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3536 RESULT=skip
18178 10:55:31.676802 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3536 RESULT=skip
18180 10:55:31.677267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3536 RESULT=skip>
18181 10:55:31.711839 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3552 RESULT=pass
18183 10:55:31.712315 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3552 RESULT=pass>
18184 10:55:31.745811 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3552 RESULT=skip
18186 10:55:31.746280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3552 RESULT=skip>
18187 10:55:31.779922 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3552 RESULT=skip
18189 10:55:31.780383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3552 RESULT=skip>
18190 10:55:31.814642 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3552 RESULT=skip>
18191 10:55:31.815064 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3552 RESULT=skip
18193 10:55:31.849372 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3568 RESULT=pass>
18194 10:55:31.849789 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3568 RESULT=pass
18196 10:55:31.883345 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3568 RESULT=skip
18198 10:55:31.884022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3568 RESULT=skip>
18199 10:55:31.920248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3568 RESULT=skip>
18200 10:55:31.920797 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3568 RESULT=skip
18202 10:55:31.953229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3568 RESULT=skip>
18203 10:55:31.953754 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3568 RESULT=skip
18205 10:55:31.986104 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3584 RESULT=pass
18207 10:55:31.986564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3584 RESULT=pass>
18208 10:55:32.018969 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3584 RESULT=skip
18210 10:55:32.019433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3584 RESULT=skip>
18211 10:55:32.053211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3584 RESULT=skip>
18212 10:55:32.053639 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3584 RESULT=skip
18214 10:55:32.084746 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3584 RESULT=skip>
18215 10:55:32.085168 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3584 RESULT=skip
18217 10:55:32.115634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3600 RESULT=pass>
18218 10:55:32.116063 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3600 RESULT=pass
18220 10:55:32.147487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3600 RESULT=skip>
18221 10:55:32.147905 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3600 RESULT=skip
18223 10:55:32.179131 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3600 RESULT=skip>
18224 10:55:32.179565 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3600 RESULT=skip
18226 10:55:32.210194 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3600 RESULT=skip
18228 10:55:32.210777 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3600 RESULT=skip>
18229 10:55:32.241639 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3616 RESULT=pass>
18230 10:55:32.242068 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3616 RESULT=pass
18232 10:55:32.272848 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3616 RESULT=skip
18234 10:55:32.273300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3616 RESULT=skip>
18235 10:55:32.304393 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3616 RESULT=skip>
18236 10:55:32.304826 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3616 RESULT=skip
18238 10:55:32.337482 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3616 RESULT=skip>
18239 10:55:32.337916 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3616 RESULT=skip
18241 10:55:32.370296 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3632 RESULT=pass>
18242 10:55:32.370735 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3632 RESULT=pass
18244 10:55:32.402012 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3632 RESULT=skip
18246 10:55:32.402469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3632 RESULT=skip>
18247 10:55:32.433913 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3632 RESULT=skip
18249 10:55:32.434374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3632 RESULT=skip>
18250 10:55:32.465454 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3632 RESULT=skip>
18251 10:55:32.465878 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3632 RESULT=skip
18253 10:55:32.496971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3648 RESULT=pass>
18254 10:55:32.497467 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3648 RESULT=pass
18256 10:55:32.530618 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3648 RESULT=skip
18258 10:55:32.531201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3648 RESULT=skip>
18259 10:55:32.562278 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3648 RESULT=skip
18261 10:55:32.562860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3648 RESULT=skip>
18262 10:55:32.593438 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3648 RESULT=skip>
18263 10:55:32.593909 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3648 RESULT=skip
18265 10:55:32.625301 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3664 RESULT=pass
18267 10:55:32.625778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3664 RESULT=pass>
18268 10:55:32.656939 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3664 RESULT=skip
18270 10:55:32.657402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3664 RESULT=skip>
18271 10:55:32.688178 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3664 RESULT=skip>
18272 10:55:32.688618 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3664 RESULT=skip
18274 10:55:32.719611 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3664 RESULT=skip
18276 10:55:32.720071 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3664 RESULT=skip>
18277 10:55:32.751737 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3680 RESULT=pass
18279 10:55:32.752185 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3680 RESULT=pass>
18280 10:55:32.783335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3680 RESULT=skip>
18281 10:55:32.783858 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3680 RESULT=skip
18283 10:55:32.814891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3680 RESULT=skip>
18284 10:55:32.815386 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3680 RESULT=skip
18286 10:55:32.846429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3680 RESULT=skip>
18287 10:55:32.846906 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3680 RESULT=skip
18289 10:55:32.878358 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3696 RESULT=pass
18291 10:55:32.878984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3696 RESULT=pass>
18292 10:55:32.909248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3696 RESULT=skip>
18293 10:55:32.909704 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3696 RESULT=skip
18295 10:55:32.940516 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3696 RESULT=skip
18297 10:55:32.941089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3696 RESULT=skip>
18298 10:55:32.971547 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3696 RESULT=skip>
18299 10:55:32.971954 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3696 RESULT=skip
18301 10:55:33.002263 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3712 RESULT=pass
18303 10:55:33.002695 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3712 RESULT=pass>
18304 10:55:33.033149 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3712 RESULT=skip
18306 10:55:33.033724 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3712 RESULT=skip>
18307 10:55:33.065232 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3712 RESULT=skip
18309 10:55:33.065809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3712 RESULT=skip>
18310 10:55:33.096669 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3712 RESULT=skip
18312 10:55:33.097109 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3712 RESULT=skip>
18313 10:55:33.127894 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3728 RESULT=pass
18315 10:55:33.128544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3728 RESULT=pass>
18316 10:55:33.159210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3728 RESULT=skip>
18317 10:55:33.159646 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3728 RESULT=skip
18319 10:55:33.192412 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3728 RESULT=skip
18321 10:55:33.192889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3728 RESULT=skip>
18322 10:55:33.224305 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3728 RESULT=skip
18324 10:55:33.224768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3728 RESULT=skip>
18325 10:55:33.256498 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3744 RESULT=pass
18327 10:55:33.257065 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3744 RESULT=pass>
18328 10:55:33.287786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3744 RESULT=skip>
18329 10:55:33.288196 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3744 RESULT=skip
18331 10:55:33.323457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3744 RESULT=skip>
18332 10:55:33.323982 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3744 RESULT=skip
18334 10:55:33.359988 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3744 RESULT=skip
18336 10:55:33.360452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3744 RESULT=skip>
18337 10:55:33.409890 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3760 RESULT=pass
18339 10:55:33.410347 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3760 RESULT=pass>
18340 10:55:33.453816 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3760 RESULT=skip
18342 10:55:33.454264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3760 RESULT=skip>
18343 10:55:33.488459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3760 RESULT=skip>
18344 10:55:33.488762 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3760 RESULT=skip
18346 10:55:33.523300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3760 RESULT=skip>
18347 10:55:33.523629 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3760 RESULT=skip
18349 10:55:33.558376 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3776 RESULT=pass
18351 10:55:33.558706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3776 RESULT=pass>
18352 10:55:33.593671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3776 RESULT=skip>
18353 10:55:33.593973 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3776 RESULT=skip
18355 10:55:33.629062 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3776 RESULT=skip
18357 10:55:33.629490 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3776 RESULT=skip>
18358 10:55:33.665094 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3776 RESULT=skip
18360 10:55:33.665549 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3776 RESULT=skip>
18361 10:55:33.702481 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3792 RESULT=pass
18363 10:55:33.702918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3792 RESULT=pass>
18364 10:55:33.739411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3792 RESULT=skip>
18365 10:55:33.739818 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3792 RESULT=skip
18367 10:55:33.776617 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3792 RESULT=skip
18369 10:55:33.777084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3792 RESULT=skip>
18370 10:55:33.813345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3792 RESULT=skip>
18371 10:55:33.813845 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3792 RESULT=skip
18373 10:55:33.849712 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3808 RESULT=pass
18375 10:55:33.850180 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3808 RESULT=pass>
18376 10:55:33.885600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3808 RESULT=skip>
18377 10:55:33.886050 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3808 RESULT=skip
18379 10:55:33.921553 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3808 RESULT=skip>
18380 10:55:33.921975 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3808 RESULT=skip
18382 10:55:33.958192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3808 RESULT=skip>
18383 10:55:33.958616 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3808 RESULT=skip
18385 10:55:33.995032 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3824 RESULT=pass>
18386 10:55:33.995511 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3824 RESULT=pass
18388 10:55:34.031205 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3824 RESULT=skip>
18389 10:55:34.031697 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3824 RESULT=skip
18391 10:55:34.068741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3824 RESULT=skip>
18392 10:55:34.069142 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3824 RESULT=skip
18394 10:55:34.105674 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3824 RESULT=skip
18396 10:55:34.106145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3824 RESULT=skip>
18397 10:55:34.142602 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3840 RESULT=pass
18399 10:55:34.142968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3840 RESULT=pass>
18400 10:55:34.178707 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3840 RESULT=skip>
18401 10:55:34.179010 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3840 RESULT=skip
18403 10:55:34.215203 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3840 RESULT=skip
18405 10:55:34.215555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3840 RESULT=skip>
18406 10:55:34.251020 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3840 RESULT=skip>
18407 10:55:34.251310 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3840 RESULT=skip
18409 10:55:34.285843 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3856 RESULT=pass>
18410 10:55:34.286260 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3856 RESULT=pass
18412 10:55:34.333173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3856 RESULT=skip>
18413 10:55:34.333534 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3856 RESULT=skip
18415 10:55:34.382663 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3856 RESULT=skip>
18416 10:55:34.383108 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3856 RESULT=skip
18418 10:55:34.418894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3856 RESULT=skip>
18419 10:55:34.419309 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3856 RESULT=skip
18421 10:55:34.453367 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3872 RESULT=pass>
18422 10:55:34.453796 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3872 RESULT=pass
18424 10:55:34.490774 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3872 RESULT=skip
18426 10:55:34.491229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3872 RESULT=skip>
18427 10:55:34.527289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3872 RESULT=skip>
18428 10:55:34.527785 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3872 RESULT=skip
18430 10:55:34.563716 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3872 RESULT=skip
18432 10:55:34.564163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3872 RESULT=skip>
18433 10:55:34.600391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3888 RESULT=pass>
18434 10:55:34.600906 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3888 RESULT=pass
18436 10:55:34.636291 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3888 RESULT=skip
18438 10:55:34.636927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3888 RESULT=skip>
18439 10:55:34.671113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3888 RESULT=skip>
18440 10:55:34.671590 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3888 RESULT=skip
18442 10:55:34.708277 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3888 RESULT=skip
18444 10:55:34.708723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3888 RESULT=skip>
18445 10:55:34.742713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3904 RESULT=pass>
18446 10:55:34.743154 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3904 RESULT=pass
18448 10:55:34.778592 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3904 RESULT=skip
18450 10:55:34.779241 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3904 RESULT=skip>
18451 10:55:34.813015 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3904 RESULT=skip>
18452 10:55:34.813476 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3904 RESULT=skip
18454 10:55:34.849312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3904 RESULT=skip>
18455 10:55:34.849783 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3904 RESULT=skip
18457 10:55:34.884903 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3920 RESULT=pass>
18458 10:55:34.885449 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3920 RESULT=pass
18460 10:55:34.920499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3920 RESULT=skip>
18461 10:55:34.920885 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3920 RESULT=skip
18463 10:55:34.955369 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3920 RESULT=skip>
18464 10:55:34.955694 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3920 RESULT=skip
18466 10:55:34.990966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3920 RESULT=skip>
18467 10:55:34.991274 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3920 RESULT=skip
18469 10:55:35.025598 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3936 RESULT=pass>
18470 10:55:35.026011 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3936 RESULT=pass
18472 10:55:35.061114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3936 RESULT=skip>
18473 10:55:35.061686 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3936 RESULT=skip
18475 10:55:35.095914 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3936 RESULT=skip
18477 10:55:35.096375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3936 RESULT=skip>
18478 10:55:35.131341 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3936 RESULT=skip>
18479 10:55:35.131792 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3936 RESULT=skip
18481 10:55:35.167471 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3952 RESULT=pass>
18482 10:55:35.167921 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3952 RESULT=pass
18484 10:55:35.203059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3952 RESULT=skip>
18485 10:55:35.203437 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3952 RESULT=skip
18487 10:55:35.239834 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3952 RESULT=skip
18489 10:55:35.240497 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3952 RESULT=skip>
18490 10:55:35.274596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3952 RESULT=skip>
18491 10:55:35.275016 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3952 RESULT=skip
18493 10:55:35.309994 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3968 RESULT=pass>
18494 10:55:35.310453 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3968 RESULT=pass
18496 10:55:35.345245 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3968 RESULT=skip
18498 10:55:35.345714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3968 RESULT=skip>
18499 10:55:35.380961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3968 RESULT=skip>
18500 10:55:35.381411 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3968 RESULT=skip
18502 10:55:35.415849 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3968 RESULT=skip
18504 10:55:35.416338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3968 RESULT=skip>
18505 10:55:35.451028 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3984 RESULT=pass>
18506 10:55:35.451427 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3984 RESULT=pass
18508 10:55:35.485616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3984 RESULT=skip>
18509 10:55:35.486064 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3984 RESULT=skip
18511 10:55:35.521132 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3984 RESULT=skip>
18512 10:55:35.521577 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3984 RESULT=skip
18514 10:55:35.557988 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3984 RESULT=skip>
18515 10:55:35.558340 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3984 RESULT=skip
18517 10:55:35.593027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4000 RESULT=pass>
18518 10:55:35.593355 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4000 RESULT=pass
18520 10:55:35.628895 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4000 RESULT=skip>
18521 10:55:35.629306 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4000 RESULT=skip
18523 10:55:35.664692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4000 RESULT=skip>
18524 10:55:35.665111 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4000 RESULT=skip
18526 10:55:35.699365 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4000 RESULT=skip>
18527 10:55:35.699858 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4000 RESULT=skip
18529 10:55:35.735452 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4016 RESULT=pass
18531 10:55:35.735877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4016 RESULT=pass>
18532 10:55:35.771701 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4016 RESULT=skip
18534 10:55:35.772167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4016 RESULT=skip>
18535 10:55:35.807118 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4016 RESULT=skip
18537 10:55:35.807578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4016 RESULT=skip>
18538 10:55:35.842227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4016 RESULT=skip>
18539 10:55:35.842533 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4016 RESULT=skip
18541 10:55:35.885340 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4032 RESULT=pass
18543 10:55:35.885768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4032 RESULT=pass>
18544 10:55:35.933661 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4032 RESULT=skip
18546 10:55:35.934049 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4032 RESULT=skip>
18547 10:55:35.981799 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4032 RESULT=skip>
18548 10:55:35.982280 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4032 RESULT=skip
18550 10:55:36.023885 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4032 RESULT=skip
18552 10:55:36.024292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4032 RESULT=skip>
18553 10:55:36.062568 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4048 RESULT=pass
18555 10:55:36.063035 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4048 RESULT=pass>
18556 10:55:36.099086 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4048 RESULT=skip>
18557 10:55:36.099535 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4048 RESULT=skip
18559 10:55:36.142544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4048 RESULT=skip>
18560 10:55:36.142999 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4048 RESULT=skip
18562 10:55:36.179260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4048 RESULT=skip>
18563 10:55:36.179683 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4048 RESULT=skip
18565 10:55:36.215269 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4064 RESULT=pass
18567 10:55:36.215757 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4064 RESULT=pass>
18568 10:55:36.251866 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4064 RESULT=skip
18570 10:55:36.252262 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4064 RESULT=skip>
18571 10:55:36.287386 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4064 RESULT=skip
18573 10:55:36.287862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4064 RESULT=skip>
18574 10:55:36.323060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4064 RESULT=skip>
18575 10:55:36.323512 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4064 RESULT=skip
18577 10:55:36.358969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4080 RESULT=pass>
18578 10:55:36.359421 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4080 RESULT=pass
18580 10:55:36.394759 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4080 RESULT=skip>
18581 10:55:36.395223 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4080 RESULT=skip
18583 10:55:36.429921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4080 RESULT=skip>
18584 10:55:36.430370 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4080 RESULT=skip
18586 10:55:36.466783 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4080 RESULT=skip
18588 10:55:36.467350 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4080 RESULT=skip>
18589 10:55:36.502250 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4096 RESULT=pass
18591 10:55:36.502736 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4096 RESULT=pass>
18592 10:55:36.538350 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4096 RESULT=skip
18594 10:55:36.538823 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4096 RESULT=skip>
18595 10:55:36.575289 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4096 RESULT=skip
18597 10:55:36.575718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4096 RESULT=skip>
18598 10:55:36.611449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4096 RESULT=skip>
18599 10:55:36.611969 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4096 RESULT=skip
18601 10:55:36.646397 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4112 RESULT=pass
18603 10:55:36.646819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4112 RESULT=pass>
18604 10:55:36.681887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4112 RESULT=skip>
18605 10:55:36.682359 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4112 RESULT=skip
18607 10:55:36.716386 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4112 RESULT=skip
18609 10:55:36.716963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4112 RESULT=skip>
18610 10:55:36.751321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4112 RESULT=skip>
18611 10:55:36.751827 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4112 RESULT=skip
18613 10:55:36.787521 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4128 RESULT=pass
18615 10:55:36.788080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4128 RESULT=pass>
18616 10:55:36.823126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4128 RESULT=skip>
18617 10:55:36.823633 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4128 RESULT=skip
18619 10:55:36.857553 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4128 RESULT=skip>
18620 10:55:36.858056 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4128 RESULT=skip
18622 10:55:36.892711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4128 RESULT=skip>
18623 10:55:36.893190 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4128 RESULT=skip
18625 10:55:36.928827 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4144 RESULT=pass>
18626 10:55:36.929317 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4144 RESULT=pass
18628 10:55:36.964715 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4144 RESULT=skip
18630 10:55:36.965422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4144 RESULT=skip>
18631 10:55:37.000465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4144 RESULT=skip>
18632 10:55:37.000947 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4144 RESULT=skip
18634 10:55:37.035547 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4144 RESULT=skip
18636 10:55:37.036117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4144 RESULT=skip>
18637 10:55:37.070747 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4160 RESULT=pass
18639 10:55:37.071338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4160 RESULT=pass>
18640 10:55:37.104964 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4160 RESULT=skip
18642 10:55:37.105538 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4160 RESULT=skip>
18643 10:55:37.140556 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4160 RESULT=skip
18645 10:55:37.141106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4160 RESULT=skip>
18646 10:55:37.176687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4160 RESULT=skip>
18647 10:55:37.177054 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4160 RESULT=skip
18649 10:55:37.213251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4176 RESULT=pass>
18650 10:55:37.213605 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4176 RESULT=pass
18652 10:55:37.247796 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4176 RESULT=skip
18654 10:55:37.248443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4176 RESULT=skip>
18655 10:55:37.281565 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4176 RESULT=skip
18657 10:55:37.282205 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4176 RESULT=skip>
18658 10:55:37.314912 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4176 RESULT=skip
18660 10:55:37.315547 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4176 RESULT=skip>
18661 10:55:37.345721 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4192 RESULT=pass
18663 10:55:37.346275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4192 RESULT=pass>
18664 10:55:37.377052 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4192 RESULT=skip
18666 10:55:37.377605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4192 RESULT=skip>
18667 10:55:37.408504 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4192 RESULT=skip
18669 10:55:37.409104 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4192 RESULT=skip>
18670 10:55:37.440374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4192 RESULT=skip>
18671 10:55:37.440849 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4192 RESULT=skip
18673 10:55:37.472797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4208 RESULT=pass>
18674 10:55:37.473290 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4208 RESULT=pass
18676 10:55:37.505713 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4208 RESULT=skip
18678 10:55:37.506188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4208 RESULT=skip>
18679 10:55:37.537847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4208 RESULT=skip>
18680 10:55:37.538265 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4208 RESULT=skip
18682 10:55:37.570101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4208 RESULT=skip>
18683 10:55:37.570575 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4208 RESULT=skip
18685 10:55:37.602263 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4224 RESULT=pass>
18686 10:55:37.602736 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4224 RESULT=pass
18688 10:55:37.638374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4224 RESULT=skip>
18689 10:55:37.638794 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4224 RESULT=skip
18691 10:55:37.672547 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4224 RESULT=skip
18693 10:55:37.673169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4224 RESULT=skip>
18694 10:55:37.707558 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4224 RESULT=skip
18696 10:55:37.708038 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4224 RESULT=skip>
18697 10:55:37.740768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4240 RESULT=pass>
18698 10:55:37.741203 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4240 RESULT=pass
18700 10:55:37.777035 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4240 RESULT=skip>
18701 10:55:37.777424 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4240 RESULT=skip
18703 10:55:37.810340 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4240 RESULT=skip
18705 10:55:37.810810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4240 RESULT=skip>
18706 10:55:37.844933 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4240 RESULT=skip
18708 10:55:37.845386 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4240 RESULT=skip>
18709 10:55:37.876849 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4256 RESULT=pass
18711 10:55:37.877309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4256 RESULT=pass>
18712 10:55:37.909255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4256 RESULT=skip>
18713 10:55:37.909681 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4256 RESULT=skip
18715 10:55:37.943096 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4256 RESULT=skip
18717 10:55:37.943536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4256 RESULT=skip>
18718 10:55:37.974849 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4256 RESULT=skip>
18719 10:55:37.975278 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4256 RESULT=skip
18721 10:55:38.008533 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4272 RESULT=pass>
18722 10:55:38.008969 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4272 RESULT=pass
18724 10:55:38.042145 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4272 RESULT=skip
18726 10:55:38.042592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4272 RESULT=skip>
18727 10:55:38.074070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4272 RESULT=skip>
18728 10:55:38.074478 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4272 RESULT=skip
18730 10:55:38.106368 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4272 RESULT=skip
18732 10:55:38.106811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4272 RESULT=skip>
18733 10:55:38.138770 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4288 RESULT=pass
18735 10:55:38.139208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4288 RESULT=pass>
18736 10:55:38.171322 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4288 RESULT=skip
18738 10:55:38.171775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4288 RESULT=skip>
18739 10:55:38.204474 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4288 RESULT=skip>
18740 10:55:38.204961 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4288 RESULT=skip
18742 10:55:38.239831 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4288 RESULT=skip
18744 10:55:38.240554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4288 RESULT=skip>
18745 10:55:38.276584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4304 RESULT=pass>
18746 10:55:38.276987 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4304 RESULT=pass
18748 10:55:38.313926 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4304 RESULT=skip>
18749 10:55:38.314302 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4304 RESULT=skip
18751 10:55:38.360971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4304 RESULT=skip>
18752 10:55:38.361451 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4304 RESULT=skip
18754 10:55:38.401133 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4304 RESULT=skip>
18755 10:55:38.401604 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4304 RESULT=skip
18757 10:55:38.437608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4320 RESULT=pass>
18758 10:55:38.438119 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4320 RESULT=pass
18760 10:55:38.474163 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4320 RESULT=skip
18762 10:55:38.474554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4320 RESULT=skip>
18763 10:55:38.509881 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4320 RESULT=skip
18765 10:55:38.510328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4320 RESULT=skip>
18766 10:55:38.545797 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4320 RESULT=skip
18768 10:55:38.546236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4320 RESULT=skip>
18769 10:55:38.583293 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4336 RESULT=pass
18771 10:55:38.583765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4336 RESULT=pass>
18772 10:55:38.618919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4336 RESULT=skip>
18773 10:55:38.619362 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4336 RESULT=skip
18775 10:55:38.655535 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4336 RESULT=skip
18777 10:55:38.656001 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4336 RESULT=skip>
18778 10:55:38.691329 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4336 RESULT=skip
18780 10:55:38.691965 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4336 RESULT=skip>
18781 10:55:38.727014 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4352 RESULT=pass
18783 10:55:38.727615 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4352 RESULT=pass>
18784 10:55:38.761816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4352 RESULT=skip>
18785 10:55:38.762264 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4352 RESULT=skip
18787 10:55:38.797838 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4352 RESULT=skip>
18788 10:55:38.798343 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4352 RESULT=skip
18790 10:55:38.833770 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4352 RESULT=skip
18792 10:55:38.834419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4352 RESULT=skip>
18793 10:55:38.869095 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4368 RESULT=pass>
18794 10:55:38.869552 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4368 RESULT=pass
18796 10:55:38.906106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4368 RESULT=skip>
18797 10:55:38.906603 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4368 RESULT=skip
18799 10:55:38.942369 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4368 RESULT=skip>
18800 10:55:38.942747 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4368 RESULT=skip
18802 10:55:38.977041 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4368 RESULT=skip
18804 10:55:38.977407 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4368 RESULT=skip>
18805 10:55:39.009987 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4384 RESULT=pass
18807 10:55:39.010597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4384 RESULT=pass>
18808 10:55:39.046308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4384 RESULT=skip>
18809 10:55:39.046746 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4384 RESULT=skip
18811 10:55:39.080667 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4384 RESULT=skip>
18812 10:55:39.081113 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4384 RESULT=skip
18814 10:55:39.114399 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4384 RESULT=skip
18816 10:55:39.114838 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4384 RESULT=skip>
18817 10:55:39.149559 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4400 RESULT=pass>
18818 10:55:39.150056 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4400 RESULT=pass
18820 10:55:39.185617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4400 RESULT=skip>
18821 10:55:39.186039 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4400 RESULT=skip
18823 10:55:39.221049 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4400 RESULT=skip>
18824 10:55:39.221530 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4400 RESULT=skip
18826 10:55:39.256720 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4400 RESULT=skip
18828 10:55:39.257289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4400 RESULT=skip>
18829 10:55:39.292914 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4416 RESULT=pass
18831 10:55:39.293586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4416 RESULT=pass>
18832 10:55:39.330074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4416 RESULT=skip>
18833 10:55:39.330551 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4416 RESULT=skip
18835 10:55:39.365284 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4416 RESULT=skip
18837 10:55:39.365893 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4416 RESULT=skip>
18838 10:55:39.401219 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4416 RESULT=skip
18840 10:55:39.401705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4416 RESULT=skip>
18841 10:55:39.440608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4432 RESULT=pass>
18842 10:55:39.441054 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4432 RESULT=pass
18844 10:55:39.493146 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4432 RESULT=skip
18846 10:55:39.493600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4432 RESULT=skip>
18847 10:55:39.528347 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4432 RESULT=skip
18849 10:55:39.528825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4432 RESULT=skip>
18850 10:55:39.564854 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4432 RESULT=skip
18852 10:55:39.565445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4432 RESULT=skip>
18853 10:55:39.600796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4448 RESULT=pass>
18854 10:55:39.601272 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4448 RESULT=pass
18856 10:55:39.637760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4448 RESULT=skip>
18857 10:55:39.638256 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4448 RESULT=skip
18859 10:55:39.674414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4448 RESULT=skip>
18860 10:55:39.674844 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4448 RESULT=skip
18862 10:55:39.711903 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4448 RESULT=skip
18864 10:55:39.712471 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4448 RESULT=skip>
18865 10:55:39.746922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4464 RESULT=pass>
18866 10:55:39.747393 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4464 RESULT=pass
18868 10:55:39.786595 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4464 RESULT=skip>
18869 10:55:39.787082 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4464 RESULT=skip
18871 10:55:39.821934 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4464 RESULT=skip>
18872 10:55:39.822415 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4464 RESULT=skip
18874 10:55:39.856063 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4464 RESULT=skip
18876 10:55:39.856652 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4464 RESULT=skip>
18877 10:55:39.890471 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4480 RESULT=pass
18879 10:55:39.891056 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4480 RESULT=pass>
18880 10:55:39.924735 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4480 RESULT=skip>
18881 10:55:39.925178 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4480 RESULT=skip
18883 10:55:39.960981 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4480 RESULT=skip
18885 10:55:39.961558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4480 RESULT=skip>
18886 10:55:40.001067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4480 RESULT=skip>
18887 10:55:40.001540 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4480 RESULT=skip
18889 10:55:40.035638 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4496 RESULT=pass
18891 10:55:40.036235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4496 RESULT=pass>
18892 10:55:40.071475 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4496 RESULT=skip
18894 10:55:40.072074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4496 RESULT=skip>
18895 10:55:40.105870 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4496 RESULT=skip>
18896 10:55:40.106344 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4496 RESULT=skip
18898 10:55:40.141982 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4496 RESULT=skip
18900 10:55:40.142589 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4496 RESULT=skip>
18901 10:55:40.175091 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4512 RESULT=pass>
18902 10:55:40.175512 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4512 RESULT=pass
18904 10:55:40.211120 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4512 RESULT=skip
18906 10:55:40.211487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4512 RESULT=skip>
18907 10:55:40.245636 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4512 RESULT=skip
18909 10:55:40.246227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4512 RESULT=skip>
18910 10:55:40.279673 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4512 RESULT=skip
18912 10:55:40.280145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4512 RESULT=skip>
18913 10:55:40.316605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4528 RESULT=pass>
18914 10:55:40.317027 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4528 RESULT=pass
18916 10:55:40.352255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4528 RESULT=skip>
18917 10:55:40.352638 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4528 RESULT=skip
18919 10:55:40.388458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4528 RESULT=skip>
18920 10:55:40.388918 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4528 RESULT=skip
18922 10:55:40.422710 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4528 RESULT=skip
18924 10:55:40.423174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4528 RESULT=skip>
18925 10:55:40.458453 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4544 RESULT=pass
18927 10:55:40.458922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4544 RESULT=pass>
18928 10:55:40.495835 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4544 RESULT=skip
18930 10:55:40.496310 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4544 RESULT=skip>
18931 10:55:40.535909 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4544 RESULT=skip
18933 10:55:40.536381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4544 RESULT=skip>
18934 10:55:40.574318 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4544 RESULT=skip>
18935 10:55:40.574821 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4544 RESULT=skip
18937 10:55:40.612654 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4560 RESULT=pass>
18938 10:55:40.613124 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4560 RESULT=pass
18940 10:55:40.647827 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4560 RESULT=skip
18942 10:55:40.648297 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4560 RESULT=skip>
18943 10:55:40.683375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4560 RESULT=skip>
18944 10:55:40.683854 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4560 RESULT=skip
18946 10:55:40.718757 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4560 RESULT=skip>
18947 10:55:40.719185 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4560 RESULT=skip
18949 10:55:40.753586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4576 RESULT=pass>
18950 10:55:40.754015 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4576 RESULT=pass
18952 10:55:40.788758 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4576 RESULT=skip
18954 10:55:40.789226 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4576 RESULT=skip>
18955 10:55:40.824529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4576 RESULT=skip>
18956 10:55:40.824975 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4576 RESULT=skip
18958 10:55:40.860955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4576 RESULT=skip>
18959 10:55:40.861443 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4576 RESULT=skip
18961 10:55:40.898548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4592 RESULT=pass>
18962 10:55:40.899095 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4592 RESULT=pass
18964 10:55:40.933621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4592 RESULT=skip>
18965 10:55:40.934105 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4592 RESULT=skip
18967 10:55:40.965172 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4592 RESULT=skip
18969 10:55:40.965736 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4592 RESULT=skip>
18970 10:55:40.999350 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4592 RESULT=skip
18972 10:55:40.999806 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4592 RESULT=skip>
18973 10:55:41.029754 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4608 RESULT=pass>
18974 10:55:41.030196 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4608 RESULT=pass
18976 10:55:41.063950 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4608 RESULT=skip
18978 10:55:41.064406 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4608 RESULT=skip>
18979 10:55:41.098846 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4608 RESULT=skip>
18980 10:55:41.099307 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4608 RESULT=skip
18982 10:55:41.134569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4608 RESULT=skip>
18983 10:55:41.135016 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4608 RESULT=skip
18985 10:55:41.170941 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4624 RESULT=pass
18987 10:55:41.171589 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4624 RESULT=pass>
18988 10:55:41.204361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4624 RESULT=skip>
18989 10:55:41.204784 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4624 RESULT=skip
18991 10:55:41.235997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4624 RESULT=skip>
18992 10:55:41.236489 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4624 RESULT=skip
18994 10:55:41.267531 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4624 RESULT=skip
18996 10:55:41.268002 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4624 RESULT=skip>
18997 10:55:41.299306 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4640 RESULT=pass
18999 10:55:41.299760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4640 RESULT=pass>
19000 10:55:41.331130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4640 RESULT=skip>
19001 10:55:41.331565 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4640 RESULT=skip
19003 10:55:41.362811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4640 RESULT=skip>
19004 10:55:41.363299 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4640 RESULT=skip
19006 10:55:41.394691 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4640 RESULT=skip
19008 10:55:41.395109 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4640 RESULT=skip>
19009 10:55:41.427281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4656 RESULT=pass>
19010 10:55:41.427815 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4656 RESULT=pass
19012 10:55:41.461295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4656 RESULT=skip>
19013 10:55:41.461772 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4656 RESULT=skip
19015 10:55:41.493794 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4656 RESULT=skip
19017 10:55:41.494435 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4656 RESULT=skip>
19018 10:55:41.525342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4656 RESULT=skip>
19019 10:55:41.525829 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4656 RESULT=skip
19021 10:55:41.557037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4672 RESULT=pass>
19022 10:55:41.557462 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4672 RESULT=pass
19024 10:55:41.589113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4672 RESULT=skip>
19025 10:55:41.589556 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4672 RESULT=skip
19027 10:55:41.621240 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4672 RESULT=skip>
19028 10:55:41.621685 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4672 RESULT=skip
19030 10:55:41.653422 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4672 RESULT=skip
19032 10:55:41.653804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4672 RESULT=skip>
19033 10:55:41.685789 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4688 RESULT=pass>
19034 10:55:41.686208 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4688 RESULT=pass
19036 10:55:41.718135 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4688 RESULT=skip
19038 10:55:41.718832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4688 RESULT=skip>
19039 10:55:41.750628 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4688 RESULT=skip>
19040 10:55:41.751217 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4688 RESULT=skip
19042 10:55:41.783004 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4688 RESULT=skip
19044 10:55:41.783481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4688 RESULT=skip>
19045 10:55:41.817520 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4704 RESULT=pass
19047 10:55:41.818005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4704 RESULT=pass>
19048 10:55:41.850666 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4704 RESULT=skip
19050 10:55:41.851100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4704 RESULT=skip>
19051 10:55:41.883881 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4704 RESULT=skip
19053 10:55:41.884325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4704 RESULT=skip>
19054 10:55:41.916705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4704 RESULT=skip>
19055 10:55:41.917116 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4704 RESULT=skip
19057 10:55:41.950458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4720 RESULT=pass>
19058 10:55:41.950888 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4720 RESULT=pass
19060 10:55:41.982431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4720 RESULT=skip>
19061 10:55:41.982863 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4720 RESULT=skip
19063 10:55:42.018294 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4720 RESULT=skip>
19064 10:55:42.018804 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4720 RESULT=skip
19066 10:55:42.053009 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4720 RESULT=skip
19068 10:55:42.053453 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4720 RESULT=skip>
19069 10:55:42.088770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4736 RESULT=pass>
19070 10:55:42.089207 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4736 RESULT=pass
19072 10:55:42.125303 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4736 RESULT=skip
19074 10:55:42.125774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4736 RESULT=skip>
19075 10:55:42.162383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4736 RESULT=skip>
19076 10:55:42.162808 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4736 RESULT=skip
19078 10:55:42.195005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4736 RESULT=skip>
19079 10:55:42.195438 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4736 RESULT=skip
19081 10:55:42.227354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4752 RESULT=pass>
19082 10:55:42.227901 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4752 RESULT=pass
19084 10:55:42.263896 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4752 RESULT=skip
19086 10:55:42.264513 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4752 RESULT=skip>
19087 10:55:42.300210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4752 RESULT=skip>
19088 10:55:42.300640 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4752 RESULT=skip
19090 10:55:42.332821 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4752 RESULT=skip
19092 10:55:42.333288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4752 RESULT=skip>
19093 10:55:42.366040 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4768 RESULT=pass
19095 10:55:42.366686 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4768 RESULT=pass>
19096 10:55:42.399387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4768 RESULT=skip>
19097 10:55:42.399872 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4768 RESULT=skip
19099 10:55:42.431897 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4768 RESULT=skip
19101 10:55:42.432572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4768 RESULT=skip>
19102 10:55:42.465018 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4768 RESULT=skip
19104 10:55:42.465591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4768 RESULT=skip>
19105 10:55:42.499398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4784 RESULT=pass>
19106 10:55:42.499853 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4784 RESULT=pass
19108 10:55:42.532371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4784 RESULT=skip>
19109 10:55:42.532815 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4784 RESULT=skip
19111 10:55:42.565379 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4784 RESULT=skip
19113 10:55:42.565843 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4784 RESULT=skip>
19114 10:55:42.600308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4784 RESULT=skip>
19115 10:55:42.600808 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4784 RESULT=skip
19117 10:55:42.633240 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4800 RESULT=pass
19119 10:55:42.633890 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4800 RESULT=pass>
19120 10:55:42.666347 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4800 RESULT=skip
19122 10:55:42.666980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4800 RESULT=skip>
19123 10:55:42.699249 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4800 RESULT=skip
19125 10:55:42.699895 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4800 RESULT=skip>
19126 10:55:42.732651 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4800 RESULT=skip
19128 10:55:42.733128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4800 RESULT=skip>
19129 10:55:42.765641 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4816 RESULT=pass
19131 10:55:42.766112 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4816 RESULT=pass>
19132 10:55:42.801899 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4816 RESULT=skip
19134 10:55:42.802361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4816 RESULT=skip>
19135 10:55:42.837716 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4816 RESULT=skip
19137 10:55:42.838168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4816 RESULT=skip>
19138 10:55:42.871570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4816 RESULT=skip>
19139 10:55:42.872067 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4816 RESULT=skip
19141 10:55:42.905381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4832 RESULT=pass>
19142 10:55:42.905796 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4832 RESULT=pass
19144 10:55:42.938796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4832 RESULT=skip>
19145 10:55:42.939226 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4832 RESULT=skip
19147 10:55:42.972601 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4832 RESULT=skip
19149 10:55:42.973047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4832 RESULT=skip>
19150 10:55:43.005351 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4832 RESULT=skip>
19151 10:55:43.005843 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4832 RESULT=skip
19153 10:55:43.038385 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4848 RESULT=pass>
19154 10:55:43.038919 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4848 RESULT=pass
19156 10:55:43.071068 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4848 RESULT=skip
19158 10:55:43.071717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4848 RESULT=skip>
19159 10:55:43.104641 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4848 RESULT=skip
19161 10:55:43.105247 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4848 RESULT=skip>
19162 10:55:43.138447 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4848 RESULT=skip>
19163 10:55:43.138888 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4848 RESULT=skip
19165 10:55:43.171762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4864 RESULT=pass>
19166 10:55:43.172182 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4864 RESULT=pass
19168 10:55:43.205577 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4864 RESULT=skip
19170 10:55:43.206254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4864 RESULT=skip>
19171 10:55:43.239735 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4864 RESULT=skip
19173 10:55:43.240363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4864 RESULT=skip>
19174 10:55:43.276799 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4864 RESULT=skip>
19175 10:55:43.277236 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4864 RESULT=skip
19177 10:55:43.322655 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4880 RESULT=pass
19179 10:55:43.323116 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4880 RESULT=pass>
19180 10:55:43.357258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4880 RESULT=skip>
19181 10:55:43.357688 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4880 RESULT=skip
19183 10:55:43.393512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4880 RESULT=skip>
19184 10:55:43.393951 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4880 RESULT=skip
19186 10:55:43.431347 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4880 RESULT=skip>
19187 10:55:43.431771 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4880 RESULT=skip
19189 10:55:43.466377 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4896 RESULT=pass>
19190 10:55:43.466816 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4896 RESULT=pass
19192 10:55:43.500376 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4896 RESULT=skip
19194 10:55:43.500960 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4896 RESULT=skip>
19195 10:55:43.533595 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4896 RESULT=skip>
19196 10:55:43.534039 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4896 RESULT=skip
19198 10:55:43.567640 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4896 RESULT=skip>
19199 10:55:43.568059 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4896 RESULT=skip
19201 10:55:43.602692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4912 RESULT=pass>
19202 10:55:43.603134 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4912 RESULT=pass
19204 10:55:43.636604 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4912 RESULT=skip
19206 10:55:43.637059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4912 RESULT=skip>
19207 10:55:43.670166 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4912 RESULT=skip>
19208 10:55:43.670604 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4912 RESULT=skip
19210 10:55:43.704172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4912 RESULT=skip>
19211 10:55:43.704606 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4912 RESULT=skip
19213 10:55:43.737324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4928 RESULT=pass>
19214 10:55:43.737760 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4928 RESULT=pass
19216 10:55:43.771405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4928 RESULT=skip>
19217 10:55:43.771822 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4928 RESULT=skip
19219 10:55:43.805478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4928 RESULT=skip>
19220 10:55:43.805931 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4928 RESULT=skip
19222 10:55:43.839549 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4928 RESULT=skip>
19223 10:55:43.839986 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4928 RESULT=skip
19225 10:55:43.877486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4944 RESULT=pass>
19226 10:55:43.877937 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4944 RESULT=pass
19228 10:55:43.914226 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4944 RESULT=skip>
19229 10:55:43.914668 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4944 RESULT=skip
19231 10:55:43.952358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4944 RESULT=skip>
19232 10:55:43.952845 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4944 RESULT=skip
19234 10:55:43.989045 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4944 RESULT=skip>
19235 10:55:43.989537 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4944 RESULT=skip
19237 10:55:44.025910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4960 RESULT=pass>
19238 10:55:44.026342 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4960 RESULT=pass
19240 10:55:44.059807 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4960 RESULT=skip
19242 10:55:44.060456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4960 RESULT=skip>
19243 10:55:44.096951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4960 RESULT=skip>
19244 10:55:44.097435 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4960 RESULT=skip
19246 10:55:44.129709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4960 RESULT=skip>
19247 10:55:44.130152 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4960 RESULT=skip
19249 10:55:44.163746 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4976 RESULT=pass
19251 10:55:44.164212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4976 RESULT=pass>
19252 10:55:44.199905 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4976 RESULT=skip
19254 10:55:44.200373 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4976 RESULT=skip>
19255 10:55:44.237076 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4976 RESULT=skip
19257 10:55:44.237542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4976 RESULT=skip>
19258 10:55:44.271021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4976 RESULT=skip>
19259 10:55:44.271535 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4976 RESULT=skip
19261 10:55:44.304986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4992 RESULT=pass>
19262 10:55:44.305472 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4992 RESULT=pass
19264 10:55:44.339257 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4992 RESULT=skip>
19265 10:55:44.339734 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4992 RESULT=skip
19267 10:55:44.373561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4992 RESULT=skip>
19268 10:55:44.373980 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4992 RESULT=skip
19270 10:55:44.407472 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4992 RESULT=skip>
19271 10:55:44.407960 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4992 RESULT=skip
19273 10:55:44.440094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5008 RESULT=pass>
19274 10:55:44.440578 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5008 RESULT=pass
19276 10:55:44.472995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5008 RESULT=skip>
19277 10:55:44.473433 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5008 RESULT=skip
19279 10:55:44.508789 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5008 RESULT=skip>
19280 10:55:44.509216 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5008 RESULT=skip
19282 10:55:44.541917 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5008 RESULT=skip
19284 10:55:44.542361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5008 RESULT=skip>
19285 10:55:44.600013 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5024 RESULT=pass
19287 10:55:44.600452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5024 RESULT=pass>
19288 10:55:44.637098 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5024 RESULT=skip
19290 10:55:44.637779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5024 RESULT=skip>
19291 10:55:44.674003 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5024 RESULT=skip
19293 10:55:44.674643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5024 RESULT=skip>
19294 10:55:44.710398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5024 RESULT=skip>
19295 10:55:44.710889 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5024 RESULT=skip
19297 10:55:44.747496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5040 RESULT=pass>
19298 10:55:44.747995 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5040 RESULT=pass
19300 10:55:44.785190 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5040 RESULT=skip
19302 10:55:44.785784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5040 RESULT=skip>
19303 10:55:44.821453 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5040 RESULT=skip
19305 10:55:44.822101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5040 RESULT=skip>
19306 10:55:44.858176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5040 RESULT=skip>
19307 10:55:44.858630 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5040 RESULT=skip
19309 10:55:44.894251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5056 RESULT=pass>
19310 10:55:44.894694 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5056 RESULT=pass
19312 10:55:44.927843 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5056 RESULT=skip
19314 10:55:44.928329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5056 RESULT=skip>
19315 10:55:44.960978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5056 RESULT=skip>
19316 10:55:44.961421 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5056 RESULT=skip
19318 10:55:44.994054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5056 RESULT=skip>
19319 10:55:44.994569 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5056 RESULT=skip
19321 10:55:45.028592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5072 RESULT=pass>
19322 10:55:45.029083 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5072 RESULT=pass
19324 10:55:45.062492 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5072 RESULT=skip>
19325 10:55:45.062923 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5072 RESULT=skip
19327 10:55:45.097045 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5072 RESULT=skip
19329 10:55:45.097689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5072 RESULT=skip>
19330 10:55:45.131081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5072 RESULT=skip>
19331 10:55:45.131573 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5072 RESULT=skip
19333 10:55:45.164407 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5088 RESULT=pass>
19334 10:55:45.164897 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5088 RESULT=pass
19336 10:55:45.198696 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5088 RESULT=skip
19338 10:55:45.199336 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5088 RESULT=skip>
19339 10:55:45.231735 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5088 RESULT=skip
19341 10:55:45.232405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5088 RESULT=skip>
19342 10:55:45.265988 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5088 RESULT=skip
19344 10:55:45.266468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5088 RESULT=skip>
19345 10:55:45.299309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5104 RESULT=pass>
19346 10:55:45.299755 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5104 RESULT=pass
19348 10:55:45.333293 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5104 RESULT=skip>
19349 10:55:45.333740 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5104 RESULT=skip
19351 10:55:45.366661 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5104 RESULT=skip
19353 10:55:45.367140 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5104 RESULT=skip>
19354 10:55:45.400364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5104 RESULT=skip>
19355 10:55:45.400805 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5104 RESULT=skip
19357 10:55:45.434442 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5120 RESULT=pass
19359 10:55:45.434913 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5120 RESULT=pass>
19360 10:55:45.468724 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5120 RESULT=skip>
19361 10:55:45.469167 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5120 RESULT=skip
19363 10:55:45.504215 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5120 RESULT=skip>
19364 10:55:45.504712 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5120 RESULT=skip
19366 10:55:45.538694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5120 RESULT=skip>
19367 10:55:45.539148 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5120 RESULT=skip
19369 10:55:45.572214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5136 RESULT=pass>
19370 10:55:45.572701 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5136 RESULT=pass
19372 10:55:45.606214 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5136 RESULT=skip
19374 10:55:45.606768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5136 RESULT=skip>
19375 10:55:45.639691 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5136 RESULT=skip
19377 10:55:45.640148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5136 RESULT=skip>
19378 10:55:45.673467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5136 RESULT=skip>
19379 10:55:45.673921 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5136 RESULT=skip
19381 10:55:45.706872 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5152 RESULT=pass>
19382 10:55:45.707314 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5152 RESULT=pass
19384 10:55:45.743634 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5152 RESULT=skip
19386 10:55:45.744093 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5152 RESULT=skip>
19387 10:55:45.776902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5152 RESULT=skip>
19388 10:55:45.777347 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5152 RESULT=skip
19390 10:55:45.812766 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5152 RESULT=skip>
19391 10:55:45.813728 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5152 RESULT=skip
19393 10:55:45.848631 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5168 RESULT=pass>
19394 10:55:45.849108 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5168 RESULT=pass
19396 10:55:45.879136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5168 RESULT=skip>
19397 10:55:45.879598 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5168 RESULT=skip
19399 10:55:45.910947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5168 RESULT=skip>
19400 10:55:45.911381 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5168 RESULT=skip
19402 10:55:45.941916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5168 RESULT=skip>
19403 10:55:45.942333 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5168 RESULT=skip
19405 10:55:45.972693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5184 RESULT=pass>
19406 10:55:45.973107 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5184 RESULT=pass
19408 10:55:46.005182 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5184 RESULT=skip
19410 10:55:46.005629 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5184 RESULT=skip>
19411 10:55:46.036556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5184 RESULT=skip>
19412 10:55:46.036987 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5184 RESULT=skip
19414 10:55:46.068362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5184 RESULT=skip>
19415 10:55:46.068796 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5184 RESULT=skip
19417 10:55:46.099509 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5200 RESULT=pass>
19418 10:55:46.099940 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5200 RESULT=pass
19420 10:55:46.130544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5200 RESULT=skip>
19421 10:55:46.131007 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5200 RESULT=skip
19423 10:55:46.162117 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5200 RESULT=skip
19425 10:55:46.162683 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5200 RESULT=skip>
19426 10:55:46.193371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5200 RESULT=skip>
19427 10:55:46.193781 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5200 RESULT=skip
19429 10:55:46.224524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5216 RESULT=pass>
19430 10:55:46.224979 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5216 RESULT=pass
19432 10:55:46.256249 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5216 RESULT=skip>
19433 10:55:46.256778 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5216 RESULT=skip
19435 10:55:46.288444 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5216 RESULT=skip>
19436 10:55:46.288925 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5216 RESULT=skip
19438 10:55:46.320304 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5216 RESULT=skip>
19439 10:55:46.320763 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5216 RESULT=skip
19441 10:55:46.352472 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5232 RESULT=pass>
19442 10:55:46.352928 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5232 RESULT=pass
19444 10:55:46.383780 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5232 RESULT=skip
19446 10:55:46.384286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5232 RESULT=skip>
19447 10:55:46.416045 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5232 RESULT=skip
19449 10:55:46.416589 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5232 RESULT=skip>
19450 10:55:46.447176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5232 RESULT=skip>
19451 10:55:46.447635 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5232 RESULT=skip
19453 10:55:46.478636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5248 RESULT=pass>
19454 10:55:46.479062 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5248 RESULT=pass
19456 10:55:46.511008 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5248 RESULT=skip
19458 10:55:46.511444 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5248 RESULT=skip>
19459 10:55:46.545423 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5248 RESULT=skip
19461 10:55:46.545878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5248 RESULT=skip>
19462 10:55:46.577838 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5248 RESULT=skip
19464 10:55:46.578282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5248 RESULT=skip>
19465 10:55:46.609387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5264 RESULT=pass>
19466 10:55:46.609801 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5264 RESULT=pass
19468 10:55:46.642720 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5264 RESULT=skip>
19469 10:55:46.643150 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5264 RESULT=skip
19471 10:55:46.676192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5264 RESULT=skip>
19472 10:55:46.676620 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5264 RESULT=skip
19474 10:55:46.708191 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5264 RESULT=skip
19476 10:55:46.708775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5264 RESULT=skip>
19477 10:55:46.739043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5280 RESULT=pass>
19478 10:55:46.739523 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5280 RESULT=pass
19480 10:55:46.770522 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5280 RESULT=skip>
19481 10:55:46.771002 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5280 RESULT=skip
19483 10:55:46.802022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5280 RESULT=skip>
19484 10:55:46.802496 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5280 RESULT=skip
19486 10:55:46.833158 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5280 RESULT=skip>
19487 10:55:46.833641 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5280 RESULT=skip
19489 10:55:46.865209 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5296 RESULT=pass
19491 10:55:46.865803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5296 RESULT=pass>
19492 10:55:46.896227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5296 RESULT=skip>
19493 10:55:46.896699 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5296 RESULT=skip
19495 10:55:46.926988 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5296 RESULT=skip>
19496 10:55:46.927504 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5296 RESULT=skip
19498 10:55:46.958794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5296 RESULT=skip>
19499 10:55:46.959378 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5296 RESULT=skip
19501 10:55:46.989913 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5312 RESULT=pass>
19502 10:55:46.990402 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5312 RESULT=pass
19504 10:55:47.020825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5312 RESULT=skip>
19505 10:55:47.021271 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5312 RESULT=skip
19507 10:55:47.052458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5312 RESULT=skip>
19508 10:55:47.052896 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5312 RESULT=skip
19510 10:55:47.083237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5312 RESULT=skip>
19511 10:55:47.083721 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5312 RESULT=skip
19513 10:55:47.114902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5328 RESULT=pass>
19514 10:55:47.115381 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5328 RESULT=pass
19516 10:55:47.146331 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5328 RESULT=skip>
19517 10:55:47.146752 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5328 RESULT=skip
19519 10:55:47.179075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5328 RESULT=skip>
19520 10:55:47.179530 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5328 RESULT=skip
19522 10:55:47.211236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5328 RESULT=skip>
19523 10:55:47.211715 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5328 RESULT=skip
19525 10:55:47.242572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5344 RESULT=pass>
19526 10:55:47.243047 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5344 RESULT=pass
19528 10:55:47.274170 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5344 RESULT=skip
19530 10:55:47.274731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5344 RESULT=skip>
19531 10:55:47.305729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5344 RESULT=skip>
19532 10:55:47.306200 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5344 RESULT=skip
19534 10:55:47.337486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5344 RESULT=skip>
19535 10:55:47.337908 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5344 RESULT=skip
19537 10:55:47.370065 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5360 RESULT=pass
19539 10:55:47.370495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5360 RESULT=pass>
19540 10:55:47.401958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5360 RESULT=skip>
19541 10:55:47.402418 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5360 RESULT=skip
19543 10:55:47.435044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5360 RESULT=skip>
19544 10:55:47.435479 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5360 RESULT=skip
19546 10:55:47.468400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5360 RESULT=skip>
19547 10:55:47.468896 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5360 RESULT=skip
19549 10:55:47.499177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5376 RESULT=pass>
19550 10:55:47.499607 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5376 RESULT=pass
19552 10:55:47.529442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5376 RESULT=skip>
19553 10:55:47.529891 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5376 RESULT=skip
19555 10:55:47.560960 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5376 RESULT=skip>
19556 10:55:47.561388 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5376 RESULT=skip
19558 10:55:47.591919 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5376 RESULT=skip
19560 10:55:47.592368 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5376 RESULT=skip>
19561 10:55:47.621980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5392 RESULT=pass>
19562 10:55:47.622411 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5392 RESULT=pass
19564 10:55:47.652722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5392 RESULT=skip>
19565 10:55:47.653206 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5392 RESULT=skip
19567 10:55:47.685133 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5392 RESULT=skip
19569 10:55:47.685781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5392 RESULT=skip>
19570 10:55:47.716818 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5392 RESULT=skip
19572 10:55:47.717449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5392 RESULT=skip>
19573 10:55:47.749976 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5408 RESULT=pass
19575 10:55:47.750605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5408 RESULT=pass>
19576 10:55:47.781151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5408 RESULT=skip>
19577 10:55:47.781617 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5408 RESULT=skip
19579 10:55:47.812736 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5408 RESULT=skip
19581 10:55:47.813364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5408 RESULT=skip>
19582 10:55:47.844971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5408 RESULT=skip>
19583 10:55:47.845427 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5408 RESULT=skip
19585 10:55:47.876348 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5424 RESULT=pass>
19586 10:55:47.876821 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5424 RESULT=pass
19588 10:55:47.907506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5424 RESULT=skip>
19589 10:55:47.907918 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5424 RESULT=skip
19591 10:55:47.939930 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5424 RESULT=skip
19593 10:55:47.940374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5424 RESULT=skip>
19594 10:55:47.972826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5424 RESULT=skip>
19595 10:55:47.973251 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5424 RESULT=skip
19597 10:55:48.004794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5440 RESULT=pass>
19598 10:55:48.005236 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5440 RESULT=pass
19600 10:55:48.036906 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5440 RESULT=skip
19602 10:55:48.037390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5440 RESULT=skip>
19603 10:55:48.069832 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5440 RESULT=skip
19605 10:55:48.070435 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5440 RESULT=skip>
19606 10:55:48.101451 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5440 RESULT=skip
19608 10:55:48.102048 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5440 RESULT=skip>
19609 10:55:48.133264 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5456 RESULT=pass
19611 10:55:48.133710 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5456 RESULT=pass>
19612 10:55:48.164677 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5456 RESULT=skip>
19613 10:55:48.165154 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5456 RESULT=skip
19615 10:55:48.196560 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5456 RESULT=skip
19617 10:55:48.197012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5456 RESULT=skip>
19618 10:55:48.228859 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5456 RESULT=skip
19620 10:55:48.229309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5456 RESULT=skip>
19621 10:55:48.260674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5472 RESULT=pass>
19622 10:55:48.261097 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5472 RESULT=pass
19624 10:55:48.293660 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5472 RESULT=skip>
19625 10:55:48.294095 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5472 RESULT=skip
19627 10:55:48.325704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5472 RESULT=skip>
19628 10:55:48.326222 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5472 RESULT=skip
19630 10:55:48.359576 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5472 RESULT=skip
19632 10:55:48.360158 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5472 RESULT=skip>
19633 10:55:48.392792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5488 RESULT=pass>
19634 10:55:48.393182 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5488 RESULT=pass
19636 10:55:48.425000 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5488 RESULT=skip
19638 10:55:48.425482 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5488 RESULT=skip>
19639 10:55:48.456837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5488 RESULT=skip>
19640 10:55:48.457308 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5488 RESULT=skip
19642 10:55:48.490244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5488 RESULT=skip>
19643 10:55:48.490660 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5488 RESULT=skip
19645 10:55:48.522610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5504 RESULT=pass>
19646 10:55:48.523051 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5504 RESULT=pass
19648 10:55:48.556744 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5504 RESULT=skip
19650 10:55:48.557384 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5504 RESULT=skip>
19651 10:55:48.589233 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5504 RESULT=skip>
19652 10:55:48.589706 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5504 RESULT=skip
19654 10:55:48.620990 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5504 RESULT=skip
19656 10:55:48.621616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5504 RESULT=skip>
19657 10:55:48.652696 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5520 RESULT=pass
19659 10:55:48.653260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5520 RESULT=pass>
19660 10:55:48.684658 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5520 RESULT=skip>
19661 10:55:48.685145 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5520 RESULT=skip
19663 10:55:48.716583 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5520 RESULT=skip
19665 10:55:48.717220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5520 RESULT=skip>
19666 10:55:48.749417 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5520 RESULT=skip>
19667 10:55:48.749922 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5520 RESULT=skip
19669 10:55:48.780950 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5536 RESULT=pass>
19670 10:55:48.781404 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5536 RESULT=pass
19672 10:55:48.813854 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5536 RESULT=skip>
19673 10:55:48.814358 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5536 RESULT=skip
19675 10:55:48.845786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5536 RESULT=skip>
19676 10:55:48.846330 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5536 RESULT=skip
19678 10:55:48.880043 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5536 RESULT=skip
19680 10:55:48.880605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5536 RESULT=skip>
19681 10:55:48.910530 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5552 RESULT=pass>
19682 10:55:48.911014 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5552 RESULT=pass
19684 10:55:48.940834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5552 RESULT=skip>
19685 10:55:48.941252 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5552 RESULT=skip
19687 10:55:48.971224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5552 RESULT=skip>
19688 10:55:48.971687 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5552 RESULT=skip
19690 10:55:49.001973 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5552 RESULT=skip>
19691 10:55:49.002473 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5552 RESULT=skip
19693 10:55:49.032651 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5568 RESULT=pass>
19694 10:55:49.033146 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5568 RESULT=pass
19696 10:55:49.063162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5568 RESULT=skip>
19697 10:55:49.063603 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5568 RESULT=skip
19699 10:55:49.093363 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5568 RESULT=skip
19701 10:55:49.093822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5568 RESULT=skip>
19702 10:55:49.123960 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5568 RESULT=skip
19704 10:55:49.124386 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5568 RESULT=skip>
19705 10:55:49.156088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5584 RESULT=pass>
19706 10:55:49.156525 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5584 RESULT=pass
19708 10:55:49.187773 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5584 RESULT=skip
19710 10:55:49.188251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5584 RESULT=skip>
19711 10:55:49.219499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5584 RESULT=skip>
19712 10:55:49.219972 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5584 RESULT=skip
19714 10:55:49.250785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5584 RESULT=skip>
19715 10:55:49.251260 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5584 RESULT=skip
19717 10:55:49.281882 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5600 RESULT=pass
19719 10:55:49.282485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5600 RESULT=pass>
19720 10:55:49.312561 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5600 RESULT=skip
19722 10:55:49.313014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5600 RESULT=skip>
19723 10:55:49.343033 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5600 RESULT=skip
19725 10:55:49.343595 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5600 RESULT=skip>
19726 10:55:49.373926 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5600 RESULT=skip
19728 10:55:49.374489 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5600 RESULT=skip>
19729 10:55:49.405251 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5616 RESULT=pass
19731 10:55:49.405802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5616 RESULT=pass>
19732 10:55:49.436377 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5616 RESULT=skip
19734 10:55:49.437017 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5616 RESULT=skip>
19735 10:55:49.467329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5616 RESULT=skip>
19736 10:55:49.467785 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5616 RESULT=skip
19738 10:55:49.498229 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5616 RESULT=skip
19740 10:55:49.498781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5616 RESULT=skip>
19741 10:55:49.529047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5632 RESULT=pass>
19742 10:55:49.529507 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5632 RESULT=pass
19744 10:55:49.559399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5632 RESULT=skip>
19745 10:55:49.559884 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5632 RESULT=skip
19747 10:55:49.590489 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5632 RESULT=skip>
19748 10:55:49.590966 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5632 RESULT=skip
19750 10:55:49.621365 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5632 RESULT=skip
19752 10:55:49.621932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5632 RESULT=skip>
19753 10:55:49.651192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5648 RESULT=pass>
19754 10:55:49.651693 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5648 RESULT=pass
19756 10:55:49.696971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5648 RESULT=skip>
19757 10:55:49.697453 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5648 RESULT=skip
19759 10:55:49.735252 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5648 RESULT=skip
19761 10:55:49.735894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5648 RESULT=skip>
19762 10:55:49.768927 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5648 RESULT=skip
19764 10:55:49.769560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5648 RESULT=skip>
19765 10:55:49.799458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5664 RESULT=pass>
19766 10:55:49.799941 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5664 RESULT=pass
19768 10:55:49.831163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5664 RESULT=skip>
19769 10:55:49.831649 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5664 RESULT=skip
19771 10:55:49.862137 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5664 RESULT=skip>
19772 10:55:49.862634 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5664 RESULT=skip
19774 10:55:49.893024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5664 RESULT=skip>
19775 10:55:49.893507 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5664 RESULT=skip
19777 10:55:49.924235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5680 RESULT=pass>
19778 10:55:49.924705 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5680 RESULT=pass
19780 10:55:49.954885 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5680 RESULT=skip>
19781 10:55:49.955371 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5680 RESULT=skip
19783 10:55:49.986442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5680 RESULT=skip>
19784 10:55:49.986917 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5680 RESULT=skip
19786 10:55:50.018414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5680 RESULT=skip>
19787 10:55:50.018904 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5680 RESULT=skip
19789 10:55:50.050245 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5696 RESULT=pass
19791 10:55:50.050876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5696 RESULT=pass>
19792 10:55:50.082333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5696 RESULT=skip>
19793 10:55:50.082832 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5696 RESULT=skip
19795 10:55:50.113971 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5696 RESULT=skip
19797 10:55:50.114409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5696 RESULT=skip>
19798 10:55:50.144709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5696 RESULT=skip>
19799 10:55:50.145143 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5696 RESULT=skip
19801 10:55:50.177323 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5712 RESULT=pass>
19802 10:55:50.177812 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5712 RESULT=pass
19804 10:55:50.209693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5712 RESULT=skip>
19805 10:55:50.210109 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5712 RESULT=skip
19807 10:55:50.241792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5712 RESULT=skip>
19808 10:55:50.242264 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5712 RESULT=skip
19810 10:55:50.273316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5712 RESULT=skip>
19811 10:55:50.273770 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5712 RESULT=skip
19813 10:55:50.305457 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5728 RESULT=pass
19815 10:55:50.305908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5728 RESULT=pass>
19816 10:55:50.336704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5728 RESULT=skip>
19817 10:55:50.337136 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5728 RESULT=skip
19819 10:55:50.369719 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5728 RESULT=skip
19821 10:55:50.370166 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5728 RESULT=skip>
19822 10:55:50.402533 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5728 RESULT=skip>
19823 10:55:50.402998 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5728 RESULT=skip
19825 10:55:50.434617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5744 RESULT=pass>
19826 10:55:50.435088 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5744 RESULT=pass
19828 10:55:50.467148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5744 RESULT=skip>
19829 10:55:50.467635 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5744 RESULT=skip
19831 10:55:50.498322 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5744 RESULT=skip>
19832 10:55:50.498780 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5744 RESULT=skip
19834 10:55:50.529666 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5744 RESULT=skip>
19835 10:55:50.530118 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5744 RESULT=skip
19837 10:55:50.561915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5760 RESULT=pass>
19838 10:55:50.562392 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5760 RESULT=pass
19840 10:55:50.595503 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5760 RESULT=skip
19842 10:55:50.595979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5760 RESULT=skip>
19843 10:55:50.628161 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5760 RESULT=skip>
19844 10:55:50.628599 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5760 RESULT=skip
19846 10:55:50.660318 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5760 RESULT=skip>
19847 10:55:50.660762 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5760 RESULT=skip
19849 10:55:50.693362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5776 RESULT=pass>
19850 10:55:50.693822 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5776 RESULT=pass
19852 10:55:50.725113 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5776 RESULT=skip
19854 10:55:50.725709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5776 RESULT=skip>
19855 10:55:50.756795 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5776 RESULT=skip
19857 10:55:50.757339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5776 RESULT=skip>
19858 10:55:50.788679 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5776 RESULT=skip
19860 10:55:50.789137 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5776 RESULT=skip>
19861 10:55:50.819336 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5792 RESULT=pass>
19862 10:55:50.819785 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5792 RESULT=pass
19864 10:55:50.850045 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5792 RESULT=skip>
19865 10:55:50.850470 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5792 RESULT=skip
19867 10:55:50.880753 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5792 RESULT=skip>
19868 10:55:50.881166 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5792 RESULT=skip
19870 10:55:50.912813 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5792 RESULT=skip
19872 10:55:50.913263 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5792 RESULT=skip>
19873 10:55:50.944648 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5808 RESULT=pass
19875 10:55:50.945101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5808 RESULT=pass>
19876 10:55:50.975985 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5808 RESULT=skip
19878 10:55:50.976529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5808 RESULT=skip>
19879 10:55:51.006496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5808 RESULT=skip>
19880 10:55:51.006961 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5808 RESULT=skip
19882 10:55:51.037681 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5808 RESULT=skip
19884 10:55:51.038120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5808 RESULT=skip>
19885 10:55:51.068508 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5824 RESULT=pass
19887 10:55:51.068943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5824 RESULT=pass>
19888 10:55:51.099307 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5824 RESULT=skip
19890 10:55:51.099745 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5824 RESULT=skip>
19891 10:55:51.130409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5824 RESULT=skip>
19892 10:55:51.130815 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5824 RESULT=skip
19894 10:55:51.161711 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5824 RESULT=skip
19896 10:55:51.162149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5824 RESULT=skip>
19897 10:55:51.193108 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5840 RESULT=pass>
19898 10:55:51.193537 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5840 RESULT=pass
19900 10:55:51.225551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5840 RESULT=skip>
19901 10:55:51.225997 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5840 RESULT=skip
19903 10:55:51.257349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5840 RESULT=skip>
19904 10:55:51.257813 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5840 RESULT=skip
19906 10:55:51.288385 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5840 RESULT=skip>
19907 10:55:51.288896 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5840 RESULT=skip
19909 10:55:51.319787 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5856 RESULT=pass
19911 10:55:51.320382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5856 RESULT=pass>
19912 10:55:51.350737 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5856 RESULT=skip
19914 10:55:51.351334 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5856 RESULT=skip>
19915 10:55:51.381257 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5856 RESULT=skip>
19916 10:55:51.381698 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5856 RESULT=skip
19918 10:55:51.412749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5856 RESULT=skip>
19919 10:55:51.413233 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5856 RESULT=skip
19921 10:55:51.444595 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5872 RESULT=pass>
19922 10:55:51.445067 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5872 RESULT=pass
19924 10:55:51.475798 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5872 RESULT=skip
19926 10:55:51.476493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5872 RESULT=skip>
19927 10:55:51.506416 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5872 RESULT=skip
19929 10:55:51.507018 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5872 RESULT=skip>
19930 10:55:51.536882 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5872 RESULT=skip>
19931 10:55:51.537335 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5872 RESULT=skip
19933 10:55:51.567070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5888 RESULT=pass>
19934 10:55:51.567559 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5888 RESULT=pass
19936 10:55:51.598511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5888 RESULT=skip>
19937 10:55:51.598995 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5888 RESULT=skip
19939 10:55:51.630984 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5888 RESULT=skip
19941 10:55:51.631617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5888 RESULT=skip>
19942 10:55:51.662518 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5888 RESULT=skip
19944 10:55:51.663080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5888 RESULT=skip>
19945 10:55:51.693102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5904 RESULT=pass>
19946 10:55:51.693573 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5904 RESULT=pass
19948 10:55:51.724896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5904 RESULT=skip>
19949 10:55:51.725308 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5904 RESULT=skip
19951 10:55:51.756714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5904 RESULT=skip>
19952 10:55:51.757145 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5904 RESULT=skip
19954 10:55:51.789997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5904 RESULT=skip>
19955 10:55:51.790427 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5904 RESULT=skip
19957 10:55:51.821335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5920 RESULT=pass>
19958 10:55:51.821766 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5920 RESULT=pass
19960 10:55:51.858594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5920 RESULT=skip>
19961 10:55:51.859025 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5920 RESULT=skip
19963 10:55:51.890849 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5920 RESULT=skip
19965 10:55:51.891295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5920 RESULT=skip>
19966 10:55:51.922521 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5920 RESULT=skip>
19967 10:55:51.922934 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5920 RESULT=skip
19969 10:55:51.957303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5936 RESULT=pass>
19970 10:55:51.957800 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5936 RESULT=pass
19972 10:55:51.989909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5936 RESULT=skip>
19973 10:55:51.990368 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5936 RESULT=skip
19975 10:55:52.022408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5936 RESULT=skip>
19976 10:55:52.022849 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5936 RESULT=skip
19978 10:55:52.054777 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5936 RESULT=skip>
19979 10:55:52.055210 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5936 RESULT=skip
19981 10:55:52.086629 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5952 RESULT=pass
19983 10:55:52.087079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5952 RESULT=pass>
19984 10:55:52.118377 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5952 RESULT=skip>
19985 10:55:52.118819 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5952 RESULT=skip
19987 10:55:52.149586 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5952 RESULT=skip
19989 10:55:52.150045 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5952 RESULT=skip>
19990 10:55:52.180699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5952 RESULT=skip>
19991 10:55:52.181129 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5952 RESULT=skip
19993 10:55:52.213246 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5968 RESULT=pass
19995 10:55:52.213699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5968 RESULT=pass>
19996 10:55:52.245276 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5968 RESULT=skip
19998 10:55:52.245720 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5968 RESULT=skip>
19999 10:55:52.276578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5968 RESULT=skip>
20000 10:55:52.277005 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5968 RESULT=skip
20002 10:55:52.308485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5968 RESULT=skip>
20003 10:55:52.308893 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5968 RESULT=skip
20005 10:55:52.342472 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5984 RESULT=pass
20007 10:55:52.342905 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5984 RESULT=pass>
20008 10:55:52.378226 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5984 RESULT=skip>
20009 10:55:52.378614 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5984 RESULT=skip
20011 10:55:52.412740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5984 RESULT=skip>
20012 10:55:52.413124 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5984 RESULT=skip
20014 10:55:52.445346 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5984 RESULT=skip
20016 10:55:52.445943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5984 RESULT=skip>
20017 10:55:52.476847 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6000 RESULT=pass
20019 10:55:52.477431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6000 RESULT=pass>
20020 10:55:52.507509 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6000 RESULT=skip>
20021 10:55:52.507991 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6000 RESULT=skip
20023 10:55:52.538618 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6000 RESULT=skip>
20024 10:55:52.539052 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6000 RESULT=skip
20026 10:55:52.570589 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6000 RESULT=skip
20028 10:55:52.571041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6000 RESULT=skip>
20029 10:55:52.603238 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6016 RESULT=pass
20031 10:55:52.603720 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6016 RESULT=pass>
20032 10:55:52.634572 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6016 RESULT=skip
20034 10:55:52.635198 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6016 RESULT=skip>
20035 10:55:52.666687 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6016 RESULT=skip
20037 10:55:52.667458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6016 RESULT=skip>
20038 10:55:52.703268 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6016 RESULT=skip>
20039 10:55:52.703739 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6016 RESULT=skip
20041 10:55:52.734289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6032 RESULT=pass>
20042 10:55:52.734655 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6032 RESULT=pass
20044 10:55:52.765051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6032 RESULT=skip>
20045 10:55:52.765434 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6032 RESULT=skip
20047 10:55:52.795979 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6032 RESULT=skip
20049 10:55:52.796468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6032 RESULT=skip>
20050 10:55:52.826476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6032 RESULT=skip>
20051 10:55:52.826843 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6032 RESULT=skip
20053 10:55:52.857060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6048 RESULT=pass>
20054 10:55:52.857540 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6048 RESULT=pass
20056 10:55:52.887628 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6048 RESULT=skip
20058 10:55:52.888099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6048 RESULT=skip>
20059 10:55:52.918595 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6048 RESULT=skip>
20060 10:55:52.919017 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6048 RESULT=skip
20062 10:55:52.949389 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6048 RESULT=skip
20064 10:55:52.949823 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6048 RESULT=skip>
20065 10:55:52.980853 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6064 RESULT=pass
20067 10:55:52.981492 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6064 RESULT=pass>
20068 10:55:53.011334 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6064 RESULT=skip>
20069 10:55:53.011786 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6064 RESULT=skip
20071 10:55:53.042212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6064 RESULT=skip>
20072 10:55:53.042659 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6064 RESULT=skip
20074 10:55:53.073193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6064 RESULT=skip>
20075 10:55:53.073640 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6064 RESULT=skip
20077 10:55:53.104127 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6080 RESULT=pass>
20078 10:55:53.104585 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6080 RESULT=pass
20080 10:55:53.135153 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6080 RESULT=skip
20082 10:55:53.135705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6080 RESULT=skip>
20083 10:55:53.166416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6080 RESULT=skip>
20084 10:55:53.166864 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6080 RESULT=skip
20086 10:55:53.197720 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6080 RESULT=skip
20088 10:55:53.198265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6080 RESULT=skip>
20089 10:55:53.230084 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6096 RESULT=pass
20091 10:55:53.230637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6096 RESULT=pass>
20092 10:55:53.262003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6096 RESULT=skip>
20093 10:55:53.262449 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6096 RESULT=skip
20095 10:55:53.310013 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6096 RESULT=skip
20097 10:55:53.310569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6096 RESULT=skip>
20098 10:55:53.363228 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6096 RESULT=skip>
20099 10:55:53.363704 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6096 RESULT=skip
20101 10:55:53.400991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6112 RESULT=pass>
20102 10:55:53.401348 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6112 RESULT=pass
20104 10:55:53.438436 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6112 RESULT=skip>
20105 10:55:53.438892 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6112 RESULT=skip
20107 10:55:53.469956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6112 RESULT=skip>
20108 10:55:53.470415 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6112 RESULT=skip
20110 10:55:53.501230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6112 RESULT=skip>
20111 10:55:53.501602 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6112 RESULT=skip
20113 10:55:53.532716 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6128 RESULT=pass
20115 10:55:53.533339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6128 RESULT=pass>
20116 10:55:53.563065 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6128 RESULT=skip>
20117 10:55:53.563530 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6128 RESULT=skip
20119 10:55:53.593854 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6128 RESULT=skip>
20120 10:55:53.594336 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6128 RESULT=skip
20122 10:55:53.624858 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6128 RESULT=skip
20124 10:55:53.625302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6128 RESULT=skip>
20125 10:55:53.655399 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6144 RESULT=pass
20127 10:55:53.655841 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6144 RESULT=pass>
20128 10:55:53.687729 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6144 RESULT=skip
20130 10:55:53.688173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6144 RESULT=skip>
20131 10:55:53.719949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6144 RESULT=skip>
20132 10:55:53.720375 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6144 RESULT=skip
20134 10:55:53.751671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6144 RESULT=skip>
20135 10:55:53.752145 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6144 RESULT=skip
20137 10:55:53.783115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6160 RESULT=pass>
20138 10:55:53.783521 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6160 RESULT=pass
20140 10:55:53.816305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6160 RESULT=skip>
20141 10:55:53.816757 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6160 RESULT=skip
20143 10:55:53.848054 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6160 RESULT=skip
20145 10:55:53.848497 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6160 RESULT=skip>
20146 10:55:53.879654 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6160 RESULT=skip
20148 10:55:53.880246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6160 RESULT=skip>
20149 10:55:53.911199 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6176 RESULT=pass
20151 10:55:53.911637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6176 RESULT=pass>
20152 10:55:53.941973 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6176 RESULT=skip
20154 10:55:53.942414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6176 RESULT=skip>
20155 10:55:53.972987 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6176 RESULT=skip
20157 10:55:53.973428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6176 RESULT=skip>
20158 10:55:54.004770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6176 RESULT=skip>
20159 10:55:54.005178 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6176 RESULT=skip
20161 10:55:54.037691 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6192 RESULT=pass>
20162 10:55:54.038128 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6192 RESULT=pass
20164 10:55:54.070114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6192 RESULT=skip>
20165 10:55:54.070591 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6192 RESULT=skip
20167 10:55:54.101850 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6192 RESULT=skip>
20168 10:55:54.102285 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6192 RESULT=skip
20170 10:55:54.134621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6192 RESULT=skip>
20171 10:55:54.135104 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6192 RESULT=skip
20173 10:55:54.166056 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6208 RESULT=pass>
20174 10:55:54.166464 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6208 RESULT=pass
20176 10:55:54.197678 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6208 RESULT=skip
20178 10:55:54.198248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6208 RESULT=skip>
20179 10:55:54.230187 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6208 RESULT=skip
20181 10:55:54.230752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6208 RESULT=skip>
20182 10:55:54.262127 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6208 RESULT=skip>
20183 10:55:54.262507 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6208 RESULT=skip
20185 10:55:54.293863 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6224 RESULT=pass>
20186 10:55:54.294293 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6224 RESULT=pass
20188 10:55:54.325877 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6224 RESULT=skip
20190 10:55:54.326381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6224 RESULT=skip>
20191 10:55:54.356886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6224 RESULT=skip>
20192 10:55:54.357248 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6224 RESULT=skip
20194 10:55:54.388629 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6224 RESULT=skip
20196 10:55:54.389219 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6224 RESULT=skip>
20197 10:55:54.421037 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6240 RESULT=pass
20199 10:55:54.421599 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6240 RESULT=pass>
20200 10:55:54.453202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6240 RESULT=skip>
20201 10:55:54.453583 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6240 RESULT=skip
20203 10:55:54.485522 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6240 RESULT=skip
20205 10:55:54.486134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6240 RESULT=skip>
20206 10:55:54.516994 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6240 RESULT=skip>
20207 10:55:54.517420 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6240 RESULT=skip
20209 10:55:54.548810 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6256 RESULT=pass
20211 10:55:54.549238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6256 RESULT=pass>
20212 10:55:54.579995 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6256 RESULT=skip
20214 10:55:54.580575 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6256 RESULT=skip>
20215 10:55:54.613415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6256 RESULT=skip>
20216 10:55:54.613931 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6256 RESULT=skip
20218 10:55:54.648396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6256 RESULT=skip>
20219 10:55:54.648856 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6256 RESULT=skip
20221 10:55:54.679220 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6272 RESULT=pass
20223 10:55:54.679791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6272 RESULT=pass>
20224 10:55:54.710580 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6272 RESULT=skip>
20225 10:55:54.711045 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6272 RESULT=skip
20227 10:55:54.742011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6272 RESULT=skip>
20228 10:55:54.742435 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6272 RESULT=skip
20230 10:55:54.773546 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6272 RESULT=skip>
20231 10:55:54.773956 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6272 RESULT=skip
20233 10:55:54.820840 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6288 RESULT=pass>
20234 10:55:54.821259 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6288 RESULT=pass
20236 10:55:54.854600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6288 RESULT=skip>
20237 10:55:54.855007 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6288 RESULT=skip
20239 10:55:54.886079 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6288 RESULT=skip
20241 10:55:54.886726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6288 RESULT=skip>
20242 10:55:54.917308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6288 RESULT=skip>
20243 10:55:54.917680 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6288 RESULT=skip
20245 10:55:54.947786 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6304 RESULT=pass
20247 10:55:54.948221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6304 RESULT=pass>
20248 10:55:54.979172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6304 RESULT=skip>
20249 10:55:54.979631 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6304 RESULT=skip
20251 10:55:55.009908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6304 RESULT=skip>
20252 10:55:55.010262 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6304 RESULT=skip
20254 10:55:55.040679 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6304 RESULT=skip
20256 10:55:55.041377 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6304 RESULT=skip>
20257 10:55:55.072599 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6320 RESULT=pass
20259 10:55:55.073106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6320 RESULT=pass>
20260 10:55:55.103390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6320 RESULT=skip>
20261 10:55:55.103782 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6320 RESULT=skip
20263 10:55:55.134865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6320 RESULT=skip>
20264 10:55:55.135340 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6320 RESULT=skip
20266 10:55:55.166187 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6320 RESULT=skip>
20267 10:55:55.166665 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6320 RESULT=skip
20269 10:55:55.196979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6336 RESULT=pass>
20270 10:55:55.197456 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6336 RESULT=pass
20272 10:55:55.228311 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6336 RESULT=skip>
20273 10:55:55.228753 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6336 RESULT=skip
20275 10:55:55.259809 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6336 RESULT=skip
20277 10:55:55.260249 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6336 RESULT=skip>
20278 10:55:55.292394 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6336 RESULT=skip
20280 10:55:55.292831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6336 RESULT=skip>
20281 10:55:55.325989 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6352 RESULT=pass>
20282 10:55:55.326276 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6352 RESULT=pass
20284 10:55:55.357668 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6352 RESULT=skip
20286 10:55:55.358224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6352 RESULT=skip>
20287 10:55:55.389052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6352 RESULT=skip>
20288 10:55:55.389436 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6352 RESULT=skip
20290 10:55:55.421168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6352 RESULT=skip>
20291 10:55:55.421511 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6352 RESULT=skip
20293 10:55:55.452235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6368 RESULT=pass>
20294 10:55:55.452660 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6368 RESULT=pass
20296 10:55:55.484017 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6368 RESULT=skip
20298 10:55:55.484510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6368 RESULT=skip>
20299 10:55:55.519046 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6368 RESULT=skip
20301 10:55:55.519642 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6368 RESULT=skip>
20302 10:55:55.550456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6368 RESULT=skip>
20303 10:55:55.550859 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6368 RESULT=skip
20305 10:55:55.582964 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6384 RESULT=pass
20307 10:55:55.583625 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6384 RESULT=pass>
20308 10:55:55.614819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6384 RESULT=skip>
20309 10:55:55.615287 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6384 RESULT=skip
20311 10:55:55.646463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6384 RESULT=skip>
20312 10:55:55.646938 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6384 RESULT=skip
20314 10:55:55.677705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6384 RESULT=skip>
20315 10:55:55.678058 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6384 RESULT=skip
20317 10:55:55.708588 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6400 RESULT=pass>
20318 10:55:55.708950 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6400 RESULT=pass
20320 10:55:55.739469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6400 RESULT=skip>
20321 10:55:55.739937 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6400 RESULT=skip
20323 10:55:55.771814 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6400 RESULT=skip
20325 10:55:55.772324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6400 RESULT=skip>
20326 10:55:55.804605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6400 RESULT=skip>
20327 10:55:55.805046 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6400 RESULT=skip
20329 10:55:55.836828 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6416 RESULT=pass
20331 10:55:55.837257 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6416 RESULT=pass>
20332 10:55:55.870182 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6416 RESULT=skip
20334 10:55:55.870629 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6416 RESULT=skip>
20335 10:55:55.902431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6416 RESULT=skip>
20336 10:55:55.902910 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6416 RESULT=skip
20338 10:55:55.934936 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6416 RESULT=skip>
20339 10:55:55.935410 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6416 RESULT=skip
20341 10:55:55.965942 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6432 RESULT=pass
20343 10:55:55.966500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6432 RESULT=pass>
20344 10:55:55.996638 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6432 RESULT=skip>
20345 10:55:55.997030 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6432 RESULT=skip
20347 10:55:56.027583 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6432 RESULT=skip>
20348 10:55:56.027921 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6432 RESULT=skip
20350 10:55:56.058993 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6432 RESULT=skip>
20351 10:55:56.059457 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6432 RESULT=skip
20353 10:55:56.091329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6448 RESULT=pass>
20354 10:55:56.091819 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6448 RESULT=pass
20356 10:55:56.124133 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6448 RESULT=skip>
20357 10:55:56.124417 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6448 RESULT=skip
20359 10:55:56.156662 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6448 RESULT=skip>
20360 10:55:56.157087 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6448 RESULT=skip
20362 10:55:56.189399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6448 RESULT=skip>
20363 10:55:56.189814 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6448 RESULT=skip
20365 10:55:56.220832 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6464 RESULT=pass
20367 10:55:56.221278 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6464 RESULT=pass>
20368 10:55:56.252043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6464 RESULT=skip>
20369 10:55:56.252467 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6464 RESULT=skip
20371 10:55:56.284600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6464 RESULT=skip>
20372 10:55:56.285011 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6464 RESULT=skip
20374 10:55:56.315897 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6464 RESULT=skip
20376 10:55:56.316368 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6464 RESULT=skip>
20377 10:55:56.348162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6480 RESULT=pass>
20378 10:55:56.348528 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6480 RESULT=pass
20380 10:55:56.379126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6480 RESULT=skip>
20381 10:55:56.379451 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6480 RESULT=skip
20383 10:55:56.410114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6480 RESULT=skip>
20384 10:55:56.410458 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6480 RESULT=skip
20386 10:55:56.441900 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6480 RESULT=skip>
20387 10:55:56.442251 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6480 RESULT=skip
20389 10:55:56.474659 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6496 RESULT=pass
20391 10:55:56.475097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6496 RESULT=pass>
20392 10:55:56.507081 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6496 RESULT=skip
20394 10:55:56.507521 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6496 RESULT=skip>
20395 10:55:56.538339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6496 RESULT=skip>
20396 10:55:56.538798 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6496 RESULT=skip
20398 10:55:56.570415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6496 RESULT=skip>
20399 10:55:56.570866 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6496 RESULT=skip
20401 10:55:56.602363 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6512 RESULT=pass
20403 10:55:56.602966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6512 RESULT=pass>
20404 10:55:56.634342 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6512 RESULT=skip
20406 10:55:56.634798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6512 RESULT=skip>
20407 10:55:56.667733 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6512 RESULT=skip
20409 10:55:56.668201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6512 RESULT=skip>
20410 10:55:56.699527 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6512 RESULT=skip
20412 10:55:56.699992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6512 RESULT=skip>
20413 10:55:56.731175 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6528 RESULT=pass
20415 10:55:56.731643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6528 RESULT=pass>
20416 10:55:56.763054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6528 RESULT=skip>
20417 10:55:56.763508 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6528 RESULT=skip
20419 10:55:56.795129 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6528 RESULT=skip>
20420 10:55:56.795584 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6528 RESULT=skip
20422 10:55:56.826514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6528 RESULT=skip>
20423 10:55:56.826990 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6528 RESULT=skip
20425 10:55:56.857573 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6544 RESULT=pass>
20426 10:55:56.858049 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6544 RESULT=pass
20428 10:55:56.888890 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6544 RESULT=skip
20430 10:55:56.889442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6544 RESULT=skip>
20431 10:55:56.919867 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6544 RESULT=skip
20433 10:55:56.920416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6544 RESULT=skip>
20434 10:55:56.951033 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6544 RESULT=skip>
20435 10:55:56.951475 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6544 RESULT=skip
20437 10:55:56.982002 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6560 RESULT=pass>
20438 10:55:56.982464 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6560 RESULT=pass
20440 10:55:57.012950 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6560 RESULT=skip
20442 10:55:57.013475 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6560 RESULT=skip>
20443 10:55:57.043951 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6560 RESULT=skip
20445 10:55:57.044383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6560 RESULT=skip>
20446 10:55:57.074946 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6560 RESULT=skip>
20447 10:55:57.075397 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6560 RESULT=skip
20449 10:55:57.105009 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6576 RESULT=pass>
20450 10:55:57.105446 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6576 RESULT=pass
20452 10:55:57.135600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6576 RESULT=skip>
20453 10:55:57.136051 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6576 RESULT=skip
20455 10:55:57.166821 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6576 RESULT=skip>
20456 10:55:57.167221 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6576 RESULT=skip
20458 10:55:57.198128 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6576 RESULT=skip
20460 10:55:57.198561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6576 RESULT=skip>
20461 10:55:57.228944 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6592 RESULT=pass
20463 10:55:57.229591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6592 RESULT=pass>
20464 10:55:57.260680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6592 RESULT=skip>
20465 10:55:57.261079 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6592 RESULT=skip
20467 10:55:57.293830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6592 RESULT=skip>
20468 10:55:57.294263 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6592 RESULT=skip
20470 10:55:57.327511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6592 RESULT=skip>
20471 10:55:57.327961 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6592 RESULT=skip
20473 10:55:57.360937 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6608 RESULT=pass
20475 10:55:57.361395 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6608 RESULT=pass>
20476 10:55:57.394751 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6608 RESULT=skip
20478 10:55:57.395302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6608 RESULT=skip>
20479 10:55:57.425717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6608 RESULT=skip>
20480 10:55:57.426117 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6608 RESULT=skip
20482 10:55:57.457676 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6608 RESULT=skip>
20483 10:55:57.458084 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6608 RESULT=skip
20485 10:55:57.489163 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6624 RESULT=pass
20487 10:55:57.489602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6624 RESULT=pass>
20488 10:55:57.521368 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6624 RESULT=skip
20490 10:55:57.521817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6624 RESULT=skip>
20491 10:55:57.553325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6624 RESULT=skip>
20492 10:55:57.553749 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6624 RESULT=skip
20494 10:55:57.585009 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6624 RESULT=skip
20496 10:55:57.585457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6624 RESULT=skip>
20497 10:55:57.616897 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6640 RESULT=pass
20499 10:55:57.617327 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6640 RESULT=pass>
20500 10:55:57.648336 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6640 RESULT=skip>
20501 10:55:57.648754 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6640 RESULT=skip
20503 10:55:57.679661 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6640 RESULT=skip
20505 10:55:57.680094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6640 RESULT=skip>
20506 10:55:57.711812 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6640 RESULT=skip
20508 10:55:57.712244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6640 RESULT=skip>
20509 10:55:57.743128 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6656 RESULT=pass
20511 10:55:57.743597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6656 RESULT=pass>
20512 10:55:57.774464 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6656 RESULT=skip
20514 10:55:57.774776 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6656 RESULT=skip>
20515 10:55:57.806847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6656 RESULT=skip>
20516 10:55:57.807296 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6656 RESULT=skip
20518 10:55:57.838877 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6656 RESULT=skip
20520 10:55:57.839512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6656 RESULT=skip>
20521 10:55:57.871651 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6672 RESULT=pass
20523 10:55:57.872174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6672 RESULT=pass>
20524 10:55:57.903767 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6672 RESULT=skip
20526 10:55:57.904392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6672 RESULT=skip>
20527 10:55:57.935072 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6672 RESULT=skip
20529 10:55:57.935584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6672 RESULT=skip>
20530 10:55:57.966953 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6672 RESULT=skip
20532 10:55:57.967399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6672 RESULT=skip>
20533 10:55:57.998147 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6688 RESULT=pass
20535 10:55:57.998588 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6688 RESULT=pass>
20536 10:55:58.029385 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6688 RESULT=skip>
20537 10:55:58.029862 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6688 RESULT=skip
20539 10:55:58.061019 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6688 RESULT=skip>
20540 10:55:58.061451 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6688 RESULT=skip
20542 10:55:58.093644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6688 RESULT=skip>
20543 10:55:58.094230 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6688 RESULT=skip
20545 10:55:58.126065 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6704 RESULT=pass
20547 10:55:58.126625 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6704 RESULT=pass>
20548 10:55:58.158198 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6704 RESULT=skip>
20549 10:55:58.158556 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6704 RESULT=skip
20551 10:55:58.191096 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6704 RESULT=skip>
20552 10:55:58.191569 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6704 RESULT=skip
20554 10:55:58.223431 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6704 RESULT=skip
20556 10:55:58.223939 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6704 RESULT=skip>
20557 10:55:58.254497 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6720 RESULT=pass>
20558 10:55:58.254966 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6720 RESULT=pass
20560 10:55:58.286102 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6720 RESULT=skip
20562 10:55:58.286648 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6720 RESULT=skip>
20563 10:55:58.319382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6720 RESULT=skip>
20564 10:55:58.319879 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6720 RESULT=skip
20566 10:55:58.350954 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6720 RESULT=skip
20568 10:55:58.351520 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6720 RESULT=skip>
20569 10:55:58.383113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6736 RESULT=pass>
20570 10:55:58.383584 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6736 RESULT=pass
20572 10:55:58.416185 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6736 RESULT=skip
20574 10:55:58.416632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6736 RESULT=skip>
20575 10:55:58.448394 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6736 RESULT=skip>
20576 10:55:58.448768 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6736 RESULT=skip
20578 10:55:58.482473 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6736 RESULT=skip
20580 10:55:58.482880 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6736 RESULT=skip>
20581 10:55:58.515212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6752 RESULT=pass>
20582 10:55:58.515489 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6752 RESULT=pass
20584 10:55:58.547535 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6752 RESULT=skip>
20585 10:55:58.547921 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6752 RESULT=skip
20587 10:55:58.578723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6752 RESULT=skip>
20588 10:55:58.579048 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6752 RESULT=skip
20590 10:55:58.610539 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6752 RESULT=skip
20592 10:55:58.611090 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6752 RESULT=skip>
20593 10:55:58.642409 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6768 RESULT=pass
20595 10:55:58.642854 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6768 RESULT=pass>
20596 10:55:58.673857 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6768 RESULT=skip
20598 10:55:58.674336 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6768 RESULT=skip>
20599 10:55:58.706961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6768 RESULT=skip>
20600 10:55:58.707339 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6768 RESULT=skip
20602 10:55:58.738670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6768 RESULT=skip>
20603 10:55:58.739086 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6768 RESULT=skip
20605 10:55:58.770640 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6784 RESULT=pass>
20606 10:55:58.771010 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6784 RESULT=pass
20608 10:55:58.802090 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6784 RESULT=skip>
20609 10:55:58.802384 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6784 RESULT=skip
20611 10:55:58.834152 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6784 RESULT=skip>
20612 10:55:58.834486 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6784 RESULT=skip
20614 10:55:58.866029 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6784 RESULT=skip>
20615 10:55:58.866438 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6784 RESULT=skip
20617 10:55:58.897975 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6800 RESULT=pass
20619 10:55:58.898415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6800 RESULT=pass>
20620 10:55:58.929762 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6800 RESULT=skip
20622 10:55:58.930200 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6800 RESULT=skip>
20623 10:55:58.962357 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6800 RESULT=skip>
20624 10:55:58.962757 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6800 RESULT=skip
20626 10:55:58.976303 <47>[ 190.504052] systemd-journald[105]: Sent WATCHDOG=1 notification.
20627 10:55:58.999857 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6800 RESULT=skip
20629 10:55:59.000496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6800 RESULT=skip>
20630 10:55:59.031597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6816 RESULT=pass>
20631 10:55:59.032021 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6816 RESULT=pass
20633 10:55:59.063578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6816 RESULT=skip>
20634 10:55:59.063985 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6816 RESULT=skip
20636 10:55:59.094883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6816 RESULT=skip>
20637 10:55:59.095340 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6816 RESULT=skip
20639 10:55:59.126985 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6816 RESULT=skip>
20640 10:55:59.127400 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6816 RESULT=skip
20642 10:55:59.158357 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6832 RESULT=pass>
20643 10:55:59.158718 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6832 RESULT=pass
20645 10:55:59.189176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6832 RESULT=skip>
20646 10:55:59.189554 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6832 RESULT=skip
20648 10:55:59.220521 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6832 RESULT=skip>
20649 10:55:59.220928 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6832 RESULT=skip
20651 10:55:59.251284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6832 RESULT=skip>
20652 10:55:59.251651 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6832 RESULT=skip
20654 10:55:59.282511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6848 RESULT=pass>
20655 10:55:59.282928 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6848 RESULT=pass
20657 10:55:59.314137 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6848 RESULT=skip
20659 10:55:59.314635 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6848 RESULT=skip>
20660 10:55:59.346148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6848 RESULT=skip>
20661 10:55:59.346536 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6848 RESULT=skip
20663 10:55:59.377659 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6848 RESULT=skip
20665 10:55:59.378093 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6848 RESULT=skip>
20666 10:55:59.409779 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6864 RESULT=pass
20668 10:55:59.410230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6864 RESULT=pass>
20669 10:55:59.441031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6864 RESULT=skip>
20670 10:55:59.441437 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6864 RESULT=skip
20672 10:55:59.472795 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6864 RESULT=skip>
20673 10:55:59.473226 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6864 RESULT=skip
20675 10:55:59.504928 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6864 RESULT=skip>
20676 10:55:59.505390 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6864 RESULT=skip
20678 10:55:59.535759 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6880 RESULT=pass
20680 10:55:59.536203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6880 RESULT=pass>
20681 10:55:59.567229 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6880 RESULT=skip
20683 10:55:59.567739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6880 RESULT=skip>
20684 10:55:59.598449 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6880 RESULT=skip
20686 10:55:59.598892 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6880 RESULT=skip>
20687 10:55:59.629382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6880 RESULT=skip>
20688 10:55:59.629802 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6880 RESULT=skip
20690 10:55:59.661621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6896 RESULT=pass>
20691 10:55:59.662090 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6896 RESULT=pass
20693 10:55:59.693181 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6896 RESULT=skip>
20694 10:55:59.693643 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6896 RESULT=skip
20696 10:55:59.724634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6896 RESULT=skip>
20697 10:55:59.725071 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6896 RESULT=skip
20699 10:55:59.756795 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6896 RESULT=skip
20701 10:55:59.757264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6896 RESULT=skip>
20702 10:55:59.788260 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6912 RESULT=pass
20704 10:55:59.788717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6912 RESULT=pass>
20705 10:55:59.820314 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6912 RESULT=skip>
20706 10:55:59.820732 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6912 RESULT=skip
20708 10:55:59.853224 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6912 RESULT=skip
20710 10:55:59.853683 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6912 RESULT=skip>
20711 10:55:59.886444 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6912 RESULT=skip>
20712 10:55:59.886865 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6912 RESULT=skip
20714 10:55:59.925564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6928 RESULT=pass>
20715 10:55:59.925981 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6928 RESULT=pass
20717 10:55:59.974718 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6928 RESULT=skip
20719 10:55:59.975171 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6928 RESULT=skip>
20720 10:56:00.006778 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6928 RESULT=skip
20722 10:56:00.007238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6928 RESULT=skip>
20723 10:56:00.039813 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6928 RESULT=skip
20725 10:56:00.040254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6928 RESULT=skip>
20726 10:56:00.071967 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6944 RESULT=pass
20728 10:56:00.072572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6944 RESULT=pass>
20729 10:56:00.103977 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6944 RESULT=skip
20731 10:56:00.104432 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6944 RESULT=skip>
20732 10:56:00.137247 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6944 RESULT=skip>
20733 10:56:00.137669 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6944 RESULT=skip
20735 10:56:00.169807 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6944 RESULT=skip
20737 10:56:00.170269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6944 RESULT=skip>
20738 10:56:00.202981 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6960 RESULT=pass
20740 10:56:00.203559 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6960 RESULT=pass>
20741 10:56:00.235222 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6960 RESULT=skip>
20742 10:56:00.235671 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6960 RESULT=skip
20744 10:56:00.266290 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6960 RESULT=skip
20746 10:56:00.266838 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6960 RESULT=skip>
20747 10:56:00.297500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6960 RESULT=skip>
20748 10:56:00.297970 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6960 RESULT=skip
20750 10:56:00.332132 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6976 RESULT=pass>
20751 10:56:00.332601 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6976 RESULT=pass
20753 10:56:00.363585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6976 RESULT=skip>
20754 10:56:00.364050 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6976 RESULT=skip
20756 10:56:00.395566 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6976 RESULT=skip>
20757 10:56:00.395969 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6976 RESULT=skip
20759 10:56:00.427420 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6976 RESULT=skip
20761 10:56:00.427861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6976 RESULT=skip>
20762 10:56:00.458863 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6992 RESULT=pass
20764 10:56:00.459491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6992 RESULT=pass>
20765 10:56:00.491179 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6992 RESULT=skip
20767 10:56:00.491790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6992 RESULT=skip>
20768 10:56:00.523849 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6992 RESULT=skip
20770 10:56:00.524312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6992 RESULT=skip>
20771 10:56:00.556877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6992 RESULT=skip>
20772 10:56:00.557345 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6992 RESULT=skip
20774 10:56:00.588748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7008 RESULT=pass>
20775 10:56:00.589222 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7008 RESULT=pass
20777 10:56:00.620142 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7008 RESULT=skip>
20778 10:56:00.620529 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7008 RESULT=skip
20780 10:56:00.651534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7008 RESULT=skip>
20781 10:56:00.651980 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7008 RESULT=skip
20783 10:56:00.682706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7008 RESULT=skip>
20784 10:56:00.683056 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7008 RESULT=skip
20786 10:56:00.716940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7024 RESULT=pass>
20787 10:56:00.717346 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7024 RESULT=pass
20789 10:56:00.748208 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7024 RESULT=skip
20791 10:56:00.748733 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7024 RESULT=skip>
20792 10:56:00.779253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7024 RESULT=skip>
20793 10:56:00.779625 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7024 RESULT=skip
20795 10:56:00.811350 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7024 RESULT=skip
20797 10:56:00.811904 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7024 RESULT=skip>
20798 10:56:00.842325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7040 RESULT=pass>
20799 10:56:00.842763 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7040 RESULT=pass
20801 10:56:00.874031 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7040 RESULT=skip
20803 10:56:00.874743 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7040 RESULT=skip>
20804 10:56:00.906542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7040 RESULT=skip>
20805 10:56:00.906970 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7040 RESULT=skip
20807 10:56:00.938304 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7040 RESULT=skip>
20808 10:56:00.938783 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7040 RESULT=skip
20810 10:56:00.969634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7056 RESULT=pass>
20811 10:56:00.970097 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7056 RESULT=pass
20813 10:56:01.001249 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7056 RESULT=skip>
20814 10:56:01.001662 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7056 RESULT=skip
20816 10:56:01.033000 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7056 RESULT=skip>
20817 10:56:01.033462 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7056 RESULT=skip
20819 10:56:01.064612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7056 RESULT=skip>
20820 10:56:01.065025 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7056 RESULT=skip
20822 10:56:01.095737 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7072 RESULT=pass
20824 10:56:01.096374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7072 RESULT=pass>
20825 10:56:01.126501 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7072 RESULT=skip>
20826 10:56:01.126878 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7072 RESULT=skip
20828 10:56:01.157703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7072 RESULT=skip>
20829 10:56:01.158104 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7072 RESULT=skip
20831 10:56:01.189307 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7072 RESULT=skip>
20832 10:56:01.189686 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7072 RESULT=skip
20834 10:56:01.220754 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7088 RESULT=pass
20836 10:56:01.221312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7088 RESULT=pass>
20837 10:56:01.252263 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7088 RESULT=skip>
20838 10:56:01.252714 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7088 RESULT=skip
20840 10:56:01.283514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7088 RESULT=skip>
20841 10:56:01.283962 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7088 RESULT=skip
20843 10:56:01.315510 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7088 RESULT=skip
20845 10:56:01.316055 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7088 RESULT=skip>
20846 10:56:01.347019 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7104 RESULT=pass>
20847 10:56:01.347485 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7104 RESULT=pass
20849 10:56:01.378722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7104 RESULT=skip>
20850 10:56:01.379146 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7104 RESULT=skip
20852 10:56:01.409701 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7104 RESULT=skip>
20853 10:56:01.410050 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7104 RESULT=skip
20855 10:56:01.441163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7104 RESULT=skip>
20856 10:56:01.441570 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7104 RESULT=skip
20858 10:56:01.472787 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7120 RESULT=pass>
20859 10:56:01.473209 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7120 RESULT=pass
20861 10:56:01.504320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7120 RESULT=skip>
20862 10:56:01.504759 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7120 RESULT=skip
20864 10:56:01.535174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7120 RESULT=skip>
20865 10:56:01.535543 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7120 RESULT=skip
20867 10:56:01.567123 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7120 RESULT=skip>
20868 10:56:01.567415 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7120 RESULT=skip
20870 10:56:01.598360 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7136 RESULT=pass>
20871 10:56:01.598766 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7136 RESULT=pass
20873 10:56:01.629820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7136 RESULT=skip>
20874 10:56:01.630269 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7136 RESULT=skip
20876 10:56:01.661195 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7136 RESULT=skip
20878 10:56:01.661744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7136 RESULT=skip>
20879 10:56:01.691903 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7136 RESULT=skip
20881 10:56:01.692390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7136 RESULT=skip>
20882 10:56:01.723332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7152 RESULT=pass>
20883 10:56:01.723699 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7152 RESULT=pass
20885 10:56:01.753881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7152 RESULT=skip>
20886 10:56:01.754247 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7152 RESULT=skip
20888 10:56:01.785081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7152 RESULT=skip>
20889 10:56:01.785493 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7152 RESULT=skip
20891 10:56:01.816756 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7152 RESULT=skip>
20892 10:56:01.817158 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7152 RESULT=skip
20894 10:56:01.848647 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7168 RESULT=pass
20896 10:56:01.849085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7168 RESULT=pass>
20897 10:56:01.880611 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7168 RESULT=skip>
20898 10:56:01.881022 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7168 RESULT=skip
20900 10:56:01.914154 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7168 RESULT=skip>
20901 10:56:01.914556 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7168 RESULT=skip
20903 10:56:01.952669 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7168 RESULT=skip>
20904 10:56:01.953080 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7168 RESULT=skip
20906 10:56:01.990011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7184 RESULT=pass>
20907 10:56:01.990363 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7184 RESULT=pass
20909 10:56:02.026731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7184 RESULT=skip>
20910 10:56:02.027065 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7184 RESULT=skip
20912 10:56:02.064573 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7184 RESULT=skip>
20913 10:56:02.064986 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7184 RESULT=skip
20915 10:56:02.097491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7184 RESULT=skip>
20916 10:56:02.097942 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7184 RESULT=skip
20918 10:56:02.130369 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7200 RESULT=pass>
20919 10:56:02.130816 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7200 RESULT=pass
20921 10:56:02.165957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7200 RESULT=skip>
20922 10:56:02.166388 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7200 RESULT=skip
20924 10:56:02.199042 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7200 RESULT=skip
20926 10:56:02.199609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7200 RESULT=skip>
20927 10:56:02.231167 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7200 RESULT=skip
20929 10:56:02.231720 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7200 RESULT=skip>
20930 10:56:02.263338 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7216 RESULT=pass
20932 10:56:02.263892 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7216 RESULT=pass>
20933 10:56:02.294692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7216 RESULT=skip>
20934 10:56:02.295107 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7216 RESULT=skip
20936 10:56:02.327562 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7216 RESULT=skip
20938 10:56:02.328028 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7216 RESULT=skip>
20939 10:56:02.359676 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7216 RESULT=skip
20941 10:56:02.360233 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7216 RESULT=skip>
20942 10:56:02.391094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7232 RESULT=pass>
20943 10:56:02.391581 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7232 RESULT=pass
20945 10:56:02.423503 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7232 RESULT=skip>
20946 10:56:02.423960 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7232 RESULT=skip
20948 10:56:02.455364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7232 RESULT=skip>
20949 10:56:02.455843 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7232 RESULT=skip
20951 10:56:02.487201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7232 RESULT=skip>
20952 10:56:02.487660 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7232 RESULT=skip
20954 10:56:02.519757 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7248 RESULT=pass
20956 10:56:02.520370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7248 RESULT=pass>
20957 10:56:02.553097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7248 RESULT=skip>
20958 10:56:02.553512 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7248 RESULT=skip
20960 10:56:02.586496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7248 RESULT=skip>
20961 10:56:02.586900 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7248 RESULT=skip
20963 10:56:02.617918 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7248 RESULT=skip
20965 10:56:02.618579 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7248 RESULT=skip>
20966 10:56:02.648961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7264 RESULT=pass>
20967 10:56:02.649459 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7264 RESULT=pass
20969 10:56:02.681197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7264 RESULT=skip>
20970 10:56:02.681616 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7264 RESULT=skip
20972 10:56:02.712835 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7264 RESULT=skip>
20973 10:56:02.713247 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7264 RESULT=skip
20975 10:56:02.746992 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7264 RESULT=skip
20977 10:56:02.747445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7264 RESULT=skip>
20978 10:56:02.778843 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7280 RESULT=pass>
20979 10:56:02.779247 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7280 RESULT=pass
20981 10:56:02.810101 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7280 RESULT=skip
20983 10:56:02.810548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7280 RESULT=skip>
20984 10:56:02.842028 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7280 RESULT=skip
20986 10:56:02.842472 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7280 RESULT=skip>
20987 10:56:02.873824 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7280 RESULT=skip
20989 10:56:02.874263 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7280 RESULT=skip>
20990 10:56:02.905461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7296 RESULT=pass>
20991 10:56:02.905886 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7296 RESULT=pass
20993 10:56:02.936912 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7296 RESULT=skip>
20994 10:56:02.937327 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7296 RESULT=skip
20996 10:56:02.969256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7296 RESULT=skip>
20997 10:56:02.969712 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7296 RESULT=skip
20999 10:56:03.002039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7296 RESULT=skip>
21000 10:56:03.002511 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7296 RESULT=skip
21002 10:56:03.033289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7312 RESULT=pass>
21003 10:56:03.033770 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7312 RESULT=pass
21005 10:56:03.064646 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7312 RESULT=skip
21007 10:56:03.065206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7312 RESULT=skip>
21008 10:56:03.097600 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7312 RESULT=skip
21010 10:56:03.098061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7312 RESULT=skip>
21011 10:56:03.129526 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7312 RESULT=skip>
21012 10:56:03.129972 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7312 RESULT=skip
21014 10:56:03.162546 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7328 RESULT=pass>
21015 10:56:03.162970 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7328 RESULT=pass
21017 10:56:03.194497 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7328 RESULT=skip
21019 10:56:03.194911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7328 RESULT=skip>
21020 10:56:03.226525 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7328 RESULT=skip>
21021 10:56:03.226999 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7328 RESULT=skip
21023 10:56:03.257898 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7328 RESULT=skip
21025 10:56:03.258355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7328 RESULT=skip>
21026 10:56:03.289318 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7344 RESULT=pass
21028 10:56:03.290034 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7344 RESULT=pass>
21029 10:56:03.321590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7344 RESULT=skip>
21030 10:56:03.322079 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7344 RESULT=skip
21032 10:56:03.353718 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7344 RESULT=skip
21034 10:56:03.354278 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7344 RESULT=skip>
21035 10:56:03.386385 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7344 RESULT=skip
21037 10:56:03.386981 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7344 RESULT=skip>
21038 10:56:03.422208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7360 RESULT=pass>
21039 10:56:03.422630 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7360 RESULT=pass
21041 10:56:03.454267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7360 RESULT=skip>
21042 10:56:03.454676 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7360 RESULT=skip
21044 10:56:03.486566 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7360 RESULT=skip>
21045 10:56:03.486969 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7360 RESULT=skip
21047 10:56:03.517971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7360 RESULT=skip>
21048 10:56:03.518426 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7360 RESULT=skip
21050 10:56:03.550006 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7376 RESULT=pass>
21051 10:56:03.550465 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7376 RESULT=pass
21053 10:56:03.582071 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7376 RESULT=skip>
21054 10:56:03.582491 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7376 RESULT=skip
21056 10:56:03.614137 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7376 RESULT=skip>
21057 10:56:03.614595 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7376 RESULT=skip
21059 10:56:03.645674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7376 RESULT=skip>
21060 10:56:03.646134 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7376 RESULT=skip
21062 10:56:03.676764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7392 RESULT=pass>
21063 10:56:03.677216 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7392 RESULT=pass
21065 10:56:03.708534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7392 RESULT=skip>
21066 10:56:03.708944 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7392 RESULT=skip
21068 10:56:03.740432 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7392 RESULT=skip>
21069 10:56:03.740867 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7392 RESULT=skip
21071 10:56:03.771560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7392 RESULT=skip>
21072 10:56:03.772006 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7392 RESULT=skip
21074 10:56:03.803648 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7408 RESULT=pass
21076 10:56:03.804192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7408 RESULT=pass>
21077 10:56:03.835088 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7408 RESULT=skip
21079 10:56:03.835636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7408 RESULT=skip>
21080 10:56:03.866527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7408 RESULT=skip>
21081 10:56:03.866940 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7408 RESULT=skip
21083 10:56:03.898532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7408 RESULT=skip>
21084 10:56:03.898991 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7408 RESULT=skip
21086 10:56:03.930717 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7424 RESULT=pass
21088 10:56:03.931268 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7424 RESULT=pass>
21089 10:56:03.964046 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7424 RESULT=skip
21091 10:56:03.964598 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7424 RESULT=skip>
21092 10:56:03.996522 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7424 RESULT=skip>
21093 10:56:03.996971 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7424 RESULT=skip
21095 10:56:04.028130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7424 RESULT=skip>
21096 10:56:04.028543 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7424 RESULT=skip
21098 10:56:04.059161 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7440 RESULT=pass>
21099 10:56:04.059570 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7440 RESULT=pass
21101 10:56:04.090695 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7440 RESULT=skip>
21102 10:56:04.091095 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7440 RESULT=skip
21104 10:56:04.122299 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7440 RESULT=skip>
21105 10:56:04.122766 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7440 RESULT=skip
21107 10:56:04.154457 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7440 RESULT=skip
21109 10:56:04.154907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7440 RESULT=skip>
21110 10:56:04.186269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7456 RESULT=pass>
21111 10:56:04.186696 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7456 RESULT=pass
21113 10:56:04.218230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7456 RESULT=skip>
21114 10:56:04.218604 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7456 RESULT=skip
21116 10:56:04.250199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7456 RESULT=skip>
21117 10:56:04.250556 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7456 RESULT=skip
21119 10:56:04.283434 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7456 RESULT=skip>
21120 10:56:04.283852 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7456 RESULT=skip
21122 10:56:04.314467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7472 RESULT=pass>
21123 10:56:04.314918 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7472 RESULT=pass
21125 10:56:04.356661 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7472 RESULT=skip>
21126 10:56:04.357096 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7472 RESULT=skip
21128 10:56:04.389509 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7472 RESULT=skip>
21129 10:56:04.390000 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7472 RESULT=skip
21131 10:56:04.421632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7472 RESULT=skip>
21132 10:56:04.422075 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7472 RESULT=skip
21134 10:56:04.453457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7488 RESULT=pass>
21135 10:56:04.453887 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7488 RESULT=pass
21137 10:56:04.485417 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7488 RESULT=skip>
21138 10:56:04.485849 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7488 RESULT=skip
21140 10:56:04.517014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7488 RESULT=skip>
21141 10:56:04.517437 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7488 RESULT=skip
21143 10:56:04.549466 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7488 RESULT=skip>
21144 10:56:04.549837 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7488 RESULT=skip
21146 10:56:04.583566 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7504 RESULT=pass>
21147 10:56:04.583862 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7504 RESULT=pass
21149 10:56:04.616714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7504 RESULT=skip>
21150 10:56:04.617087 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7504 RESULT=skip
21152 10:56:04.648609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7504 RESULT=skip>
21153 10:56:04.649011 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7504 RESULT=skip
21155 10:56:04.680386 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7504 RESULT=skip>
21156 10:56:04.680747 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7504 RESULT=skip
21158 10:56:04.711627 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7520 RESULT=pass>
21159 10:56:04.712065 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7520 RESULT=pass
21161 10:56:04.743490 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7520 RESULT=skip>
21162 10:56:04.743912 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7520 RESULT=skip
21164 10:56:04.776622 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7520 RESULT=skip>
21165 10:56:04.776907 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7520 RESULT=skip
21167 10:56:04.807368 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7520 RESULT=skip
21169 10:56:04.807690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7520 RESULT=skip>
21170 10:56:04.840724 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7536 RESULT=pass>
21171 10:56:04.841121 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7536 RESULT=pass
21173 10:56:04.871566 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7536 RESULT=skip>
21174 10:56:04.871851 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7536 RESULT=skip
21176 10:56:04.902595 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7536 RESULT=skip
21178 10:56:04.902921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7536 RESULT=skip>
21179 10:56:04.933906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7536 RESULT=skip>
21180 10:56:04.934263 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7536 RESULT=skip
21182 10:56:04.964802 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7552 RESULT=pass
21184 10:56:04.965286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7552 RESULT=pass>
21185 10:56:04.995901 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7552 RESULT=skip
21187 10:56:04.996348 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7552 RESULT=skip>
21188 10:56:05.029133 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7552 RESULT=skip>
21189 10:56:05.029530 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7552 RESULT=skip
21191 10:56:05.082837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7552 RESULT=skip>
21192 10:56:05.083258 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7552 RESULT=skip
21194 10:56:05.116143 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7568 RESULT=pass
21196 10:56:05.116783 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7568 RESULT=pass>
21197 10:56:05.148426 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7568 RESULT=skip>
21198 10:56:05.148841 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7568 RESULT=skip
21200 10:56:05.181948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7568 RESULT=skip>
21201 10:56:05.182304 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7568 RESULT=skip
21203 10:56:05.215264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7568 RESULT=skip>
21204 10:56:05.215615 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7568 RESULT=skip
21206 10:56:05.249058 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7584 RESULT=pass
21208 10:56:05.249546 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7584 RESULT=pass>
21209 10:56:05.281100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7584 RESULT=skip>
21210 10:56:05.281450 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7584 RESULT=skip
21212 10:56:05.312967 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7584 RESULT=skip>
21213 10:56:05.313252 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7584 RESULT=skip
21215 10:56:05.349002 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7584 RESULT=skip>
21216 10:56:05.349392 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7584 RESULT=skip
21218 10:56:05.384698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7600 RESULT=pass>
21219 10:56:05.384981 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7600 RESULT=pass
21221 10:56:05.416404 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7600 RESULT=skip>
21222 10:56:05.416889 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7600 RESULT=skip
21224 10:56:05.448359 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7600 RESULT=skip
21226 10:56:05.448805 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7600 RESULT=skip>
21227 10:56:05.480405 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7600 RESULT=skip
21229 10:56:05.480910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7600 RESULT=skip>
21230 10:56:05.512513 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7616 RESULT=pass>
21231 10:56:05.512873 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7616 RESULT=pass
21233 10:56:05.545089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7616 RESULT=skip>
21234 10:56:05.545441 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7616 RESULT=skip
21236 10:56:05.580486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7616 RESULT=skip>
21237 10:56:05.580956 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7616 RESULT=skip
21239 10:56:05.612835 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7616 RESULT=skip>
21240 10:56:05.613238 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7616 RESULT=skip
21242 10:56:05.645504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7632 RESULT=pass>
21243 10:56:05.645870 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7632 RESULT=pass
21245 10:56:05.677931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7632 RESULT=skip>
21246 10:56:05.678297 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7632 RESULT=skip
21248 10:56:05.710468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7632 RESULT=skip>
21249 10:56:05.710830 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7632 RESULT=skip
21251 10:56:05.742829 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7632 RESULT=skip>
21252 10:56:05.743191 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7632 RESULT=skip
21254 10:56:05.774622 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7648 RESULT=pass>
21255 10:56:05.774973 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7648 RESULT=pass
21257 10:56:05.806368 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7648 RESULT=skip
21259 10:56:05.806867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7648 RESULT=skip>
21260 10:56:05.838614 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7648 RESULT=skip
21262 10:56:05.839270 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7648 RESULT=skip>
21263 10:56:05.871105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7648 RESULT=skip>
21264 10:56:05.871627 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7648 RESULT=skip
21266 10:56:05.903289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7664 RESULT=pass>
21267 10:56:05.903747 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7664 RESULT=pass
21269 10:56:05.935343 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7664 RESULT=skip>
21270 10:56:05.935787 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7664 RESULT=skip
21272 10:56:05.967486 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7664 RESULT=skip
21274 10:56:05.968060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7664 RESULT=skip>
21275 10:56:06.000540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7664 RESULT=skip>
21276 10:56:06.000955 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7664 RESULT=skip
21278 10:56:06.033115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7680 RESULT=pass>
21279 10:56:06.033539 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7680 RESULT=pass
21281 10:56:06.070730 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7680 RESULT=skip>
21282 10:56:06.071087 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7680 RESULT=skip
21284 10:56:06.104537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7680 RESULT=skip>
21285 10:56:06.104890 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7680 RESULT=skip
21287 10:56:06.136122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7680 RESULT=skip>
21288 10:56:06.136527 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7680 RESULT=skip
21290 10:56:06.167797 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7696 RESULT=pass
21292 10:56:06.168237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7696 RESULT=pass>
21293 10:56:06.199934 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7696 RESULT=skip
21295 10:56:06.200359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7696 RESULT=skip>
21296 10:56:06.233385 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7696 RESULT=skip>
21297 10:56:06.233785 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7696 RESULT=skip
21299 10:56:06.266763 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7696 RESULT=skip>
21300 10:56:06.267167 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7696 RESULT=skip
21302 10:56:06.298977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7712 RESULT=pass>
21303 10:56:06.299380 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7712 RESULT=pass
21305 10:56:06.332175 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7712 RESULT=skip>
21306 10:56:06.332580 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7712 RESULT=skip
21308 10:56:06.364773 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7712 RESULT=skip>
21309 10:56:06.365173 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7712 RESULT=skip
21311 10:56:06.397706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7712 RESULT=skip>
21312 10:56:06.398114 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7712 RESULT=skip
21314 10:56:06.430825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7728 RESULT=pass>
21315 10:56:06.431235 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7728 RESULT=pass
21317 10:56:06.462930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7728 RESULT=skip>
21318 10:56:06.463335 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7728 RESULT=skip
21320 10:56:06.495459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7728 RESULT=skip>
21321 10:56:06.495855 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7728 RESULT=skip
21323 10:56:06.527356 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7728 RESULT=skip>
21324 10:56:06.527770 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7728 RESULT=skip
21326 10:56:06.559375 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7744 RESULT=pass
21328 10:56:06.559812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7744 RESULT=pass>
21329 10:56:06.592092 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7744 RESULT=skip>
21330 10:56:06.592509 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7744 RESULT=skip
21332 10:56:06.624425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7744 RESULT=skip>
21333 10:56:06.624830 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7744 RESULT=skip
21335 10:56:06.656539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7744 RESULT=skip>
21336 10:56:06.656999 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7744 RESULT=skip
21338 10:56:06.689034 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7760 RESULT=pass>
21339 10:56:06.689495 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7760 RESULT=pass
21341 10:56:06.721298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7760 RESULT=skip>
21342 10:56:06.721681 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7760 RESULT=skip
21344 10:56:06.754537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7760 RESULT=skip>
21345 10:56:06.754892 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7760 RESULT=skip
21347 10:56:06.788576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7760 RESULT=skip>
21348 10:56:06.788981 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7760 RESULT=skip
21350 10:56:06.821198 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7776 RESULT=pass>
21351 10:56:06.821669 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7776 RESULT=pass
21353 10:56:06.853723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7776 RESULT=skip>
21354 10:56:06.854192 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7776 RESULT=skip
21356 10:56:06.887176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7776 RESULT=skip>
21357 10:56:06.887603 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7776 RESULT=skip
21359 10:56:06.919792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7776 RESULT=skip>
21360 10:56:06.920210 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7776 RESULT=skip
21362 10:56:06.954063 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7792 RESULT=pass
21364 10:56:06.954509 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7792 RESULT=pass>
21365 10:56:06.986426 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7792 RESULT=skip>
21366 10:56:06.986834 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7792 RESULT=skip
21368 10:56:07.018935 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7792 RESULT=skip>
21369 10:56:07.019354 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7792 RESULT=skip
21371 10:56:07.052312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7792 RESULT=skip>
21372 10:56:07.052723 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7792 RESULT=skip
21374 10:56:07.083793 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7808 RESULT=pass
21376 10:56:07.084261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7808 RESULT=pass>
21377 10:56:07.117181 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7808 RESULT=skip>
21378 10:56:07.117587 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7808 RESULT=skip
21380 10:56:07.150575 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7808 RESULT=skip
21382 10:56:07.151149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7808 RESULT=skip>
21383 10:56:07.182661 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7808 RESULT=skip>
21384 10:56:07.183020 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7808 RESULT=skip
21386 10:56:07.214609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7824 RESULT=pass>
21387 10:56:07.214965 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7824 RESULT=pass
21389 10:56:07.246497 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7824 RESULT=skip>
21390 10:56:07.246858 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7824 RESULT=skip
21392 10:56:07.279010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7824 RESULT=skip>
21393 10:56:07.279355 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7824 RESULT=skip
21395 10:56:07.315375 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7824 RESULT=skip
21397 10:56:07.315877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7824 RESULT=skip>
21398 10:56:07.347145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7840 RESULT=pass>
21399 10:56:07.347504 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7840 RESULT=pass
21401 10:56:07.379156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7840 RESULT=skip>
21402 10:56:07.379441 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7840 RESULT=skip
21404 10:56:07.411241 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7840 RESULT=skip
21406 10:56:07.411746 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7840 RESULT=skip>
21407 10:56:07.442346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7840 RESULT=skip>
21408 10:56:07.442803 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7840 RESULT=skip
21410 10:56:07.474071 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7856 RESULT=pass
21412 10:56:07.474540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7856 RESULT=pass>
21413 10:56:07.506724 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7856 RESULT=skip>
21414 10:56:07.507008 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7856 RESULT=skip
21416 10:56:07.538277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7856 RESULT=skip>
21417 10:56:07.538560 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7856 RESULT=skip
21419 10:56:07.570127 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7856 RESULT=skip>
21420 10:56:07.570482 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7856 RESULT=skip
21422 10:56:07.601761 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7872 RESULT=pass>
21423 10:56:07.602124 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7872 RESULT=pass
21425 10:56:07.633262 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7872 RESULT=skip>
21426 10:56:07.633624 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7872 RESULT=skip
21428 10:56:07.666200 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7872 RESULT=skip>
21429 10:56:07.666572 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7872 RESULT=skip
21431 10:56:07.697394 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7872 RESULT=skip>
21432 10:56:07.697771 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7872 RESULT=skip
21434 10:56:07.729619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7888 RESULT=pass>
21435 10:56:07.729988 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7888 RESULT=pass
21437 10:56:07.761007 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7888 RESULT=skip
21439 10:56:07.761434 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7888 RESULT=skip>
21440 10:56:07.792962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7888 RESULT=skip>
21441 10:56:07.793317 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7888 RESULT=skip
21443 10:56:07.824948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7888 RESULT=skip>
21444 10:56:07.825231 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7888 RESULT=skip
21446 10:56:07.856753 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7904 RESULT=pass>
21447 10:56:07.857118 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7904 RESULT=pass
21449 10:56:07.888531 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7904 RESULT=skip>
21450 10:56:07.888822 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7904 RESULT=skip
21452 10:56:07.920852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7904 RESULT=skip>
21453 10:56:07.921212 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7904 RESULT=skip
21455 10:56:07.953006 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7904 RESULT=skip>
21456 10:56:07.953305 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7904 RESULT=skip
21458 10:56:07.986631 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7920 RESULT=pass>
21459 10:56:07.987065 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7920 RESULT=pass
21461 10:56:08.020199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7920 RESULT=skip>
21462 10:56:08.020570 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7920 RESULT=skip
21464 10:56:08.052827 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7920 RESULT=skip>
21465 10:56:08.053301 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7920 RESULT=skip
21467 10:56:08.085394 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7920 RESULT=skip>
21468 10:56:08.085865 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7920 RESULT=skip
21470 10:56:08.118052 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7936 RESULT=pass
21472 10:56:08.118514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7936 RESULT=pass>
21473 10:56:08.151184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7936 RESULT=skip>
21474 10:56:08.151608 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7936 RESULT=skip
21476 10:56:08.189989 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7936 RESULT=skip>
21477 10:56:08.190470 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7936 RESULT=skip
21479 10:56:08.222244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7936 RESULT=skip>
21480 10:56:08.222670 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7936 RESULT=skip
21482 10:56:08.253352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7952 RESULT=pass>
21483 10:56:08.253785 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7952 RESULT=pass
21485 10:56:08.285602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7952 RESULT=skip>
21486 10:56:08.285999 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7952 RESULT=skip
21488 10:56:08.317812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7952 RESULT=skip>
21489 10:56:08.318151 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7952 RESULT=skip
21491 10:56:08.354141 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7952 RESULT=skip>
21492 10:56:08.354542 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7952 RESULT=skip
21494 10:56:08.386812 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7968 RESULT=pass
21496 10:56:08.387206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7968 RESULT=pass>
21497 10:56:08.418623 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7968 RESULT=skip>
21498 10:56:08.418985 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7968 RESULT=skip
21500 10:56:08.451047 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7968 RESULT=skip
21502 10:56:08.451394 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7968 RESULT=skip>
21503 10:56:08.483949 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7968 RESULT=skip
21505 10:56:08.484460 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7968 RESULT=skip>
21506 10:56:08.518728 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7984 RESULT=pass>
21507 10:56:08.519139 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7984 RESULT=pass
21509 10:56:08.556334 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7984 RESULT=skip>
21510 10:56:08.556815 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7984 RESULT=skip
21512 10:56:08.596017 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7984 RESULT=skip
21514 10:56:08.596656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7984 RESULT=skip>
21515 10:56:08.630455 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7984 RESULT=skip
21517 10:56:08.630903 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7984 RESULT=skip>
21518 10:56:08.662958 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8000 RESULT=pass
21520 10:56:08.663375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8000 RESULT=pass>
21521 10:56:08.696829 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8000 RESULT=skip
21523 10:56:08.697533 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8000 RESULT=skip>
21524 10:56:08.734406 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8000 RESULT=skip
21526 10:56:08.734982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8000 RESULT=skip>
21527 10:56:08.766730 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8000 RESULT=skip>
21528 10:56:08.767131 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8000 RESULT=skip
21530 10:56:08.800941 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8016 RESULT=pass
21532 10:56:08.801365 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8016 RESULT=pass>
21533 10:56:08.833744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8016 RESULT=skip>
21534 10:56:08.834112 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8016 RESULT=skip
21536 10:56:08.865223 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8016 RESULT=skip>
21537 10:56:08.865536 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8016 RESULT=skip
21539 10:56:08.905221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8016 RESULT=skip>
21540 10:56:08.905632 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8016 RESULT=skip
21542 10:56:08.936658 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8032 RESULT=pass>
21543 10:56:08.936945 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8032 RESULT=pass
21545 10:56:08.968707 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8032 RESULT=skip>
21546 10:56:08.968989 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8032 RESULT=skip
21548 10:56:08.999957 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8032 RESULT=skip
21550 10:56:09.000419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8032 RESULT=skip>
21551 10:56:09.032250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8032 RESULT=skip>
21552 10:56:09.032620 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8032 RESULT=skip
21554 10:56:09.069004 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8048 RESULT=pass
21556 10:56:09.069604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8048 RESULT=pass>
21557 10:56:09.102010 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8048 RESULT=skip
21559 10:56:09.102617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8048 RESULT=skip>
21560 10:56:09.134120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8048 RESULT=skip>
21561 10:56:09.134490 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8048 RESULT=skip
21563 10:56:09.165348 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8048 RESULT=skip>
21564 10:56:09.165692 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8048 RESULT=skip
21566 10:56:09.196869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8064 RESULT=pass>
21567 10:56:09.197220 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8064 RESULT=pass
21569 10:56:09.228793 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8064 RESULT=skip>
21570 10:56:09.229162 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8064 RESULT=skip
21572 10:56:09.263503 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8064 RESULT=skip
21574 10:56:09.263802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8064 RESULT=skip>
21575 10:56:09.295246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8064 RESULT=skip>
21576 10:56:09.295611 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8064 RESULT=skip
21578 10:56:09.326750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8080 RESULT=pass>
21579 10:56:09.327099 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8080 RESULT=pass
21581 10:56:09.358461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8080 RESULT=skip>
21582 10:56:09.358832 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8080 RESULT=skip
21584 10:56:09.389801 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8080 RESULT=skip
21586 10:56:09.390305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8080 RESULT=skip>
21587 10:56:09.424828 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8080 RESULT=skip>
21588 10:56:09.425205 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8080 RESULT=skip
21590 10:56:09.456849 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8096 RESULT=pass>
21591 10:56:09.457393 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8096 RESULT=pass
21593 10:56:09.488500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8096 RESULT=skip>
21594 10:56:09.488972 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8096 RESULT=skip
21596 10:56:09.519980 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8096 RESULT=skip
21598 10:56:09.520443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8096 RESULT=skip>
21599 10:56:09.551118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8096 RESULT=skip>
21600 10:56:09.551406 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8096 RESULT=skip
21602 10:56:09.581978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8112 RESULT=pass>
21603 10:56:09.582331 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8112 RESULT=pass
21605 10:56:09.615180 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8112 RESULT=skip>
21606 10:56:09.615739 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8112 RESULT=skip
21608 10:56:09.646733 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8112 RESULT=skip
21610 10:56:09.647260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8112 RESULT=skip>
21611 10:56:09.678227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8112 RESULT=skip>
21612 10:56:09.678516 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8112 RESULT=skip
21614 10:56:09.709381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8128 RESULT=pass>
21615 10:56:09.709671 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8128 RESULT=pass
21617 10:56:09.740864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8128 RESULT=skip>
21618 10:56:09.741235 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8128 RESULT=skip
21620 10:56:09.773842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8128 RESULT=skip>
21621 10:56:09.774130 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8128 RESULT=skip
21623 10:56:09.806671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8128 RESULT=skip>
21624 10:56:09.806952 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8128 RESULT=skip
21626 10:56:09.838251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8144 RESULT=pass>
21627 10:56:09.838603 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8144 RESULT=pass
21629 10:56:09.869438 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8144 RESULT=skip>
21630 10:56:09.869719 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8144 RESULT=skip
21632 10:56:09.900701 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8144 RESULT=skip>
21633 10:56:09.900980 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8144 RESULT=skip
21635 10:56:09.932523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8144 RESULT=skip>
21636 10:56:09.932891 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8144 RESULT=skip
21638 10:56:09.966770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8160 RESULT=pass>
21639 10:56:09.967133 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8160 RESULT=pass
21641 10:56:09.998156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8160 RESULT=skip>
21642 10:56:09.998552 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8160 RESULT=skip
21644 10:56:10.029484 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8160 RESULT=skip
21646 10:56:10.029926 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8160 RESULT=skip>
21647 10:56:10.060890 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8160 RESULT=skip>
21648 10:56:10.061241 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8160 RESULT=skip
21650 10:56:10.093306 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8176 RESULT=pass>
21651 10:56:10.093793 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8176 RESULT=pass
21653 10:56:10.126297 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8176 RESULT=skip
21655 10:56:10.126760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8176 RESULT=skip>
21656 10:56:10.177256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8176 RESULT=skip>
21657 10:56:10.177544 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8176 RESULT=skip
21659 10:56:10.215931 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8176 RESULT=skip
21661 10:56:10.216273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8176 RESULT=skip>
21662 10:56:10.246803 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8192 RESULT=pass
21664 10:56:10.247214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8192 RESULT=pass>
21665 10:56:10.278101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8192 RESULT=skip>
21666 10:56:10.278415 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8192 RESULT=skip
21668 10:56:10.315427 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8192 RESULT=skip>
21669 10:56:10.315814 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8192 RESULT=skip
21671 10:56:10.348829 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8192 RESULT=skip>
21672 10:56:10.349238 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8192 RESULT=skip
21674 10:56:10.380422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_FPSIMD_set_via_SVE_0 RESULT=pass>
21675 10:56:10.380683 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_FPSIMD_set_via_SVE_0 RESULT=pass
21677 10:56:10.412501 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_get_fpsimd_gave_same_state RESULT=pass>
21678 10:56:10.412855 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_get_fpsimd_gave_same_state RESULT=pass
21680 10:56:10.444259 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_SVE_PT_VL_INHERIT_set RESULT=pass
21682 10:56:10.444706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_SVE_PT_VL_INHERIT_set RESULT=pass>
21683 10:56:10.479760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_SVE_PT_VL_INHERIT_cleared RESULT=pass>
21684 10:56:10.480113 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_SVE_PT_VL_INHERIT_cleared RESULT=pass
21686 10:56:10.514505 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_16 RESULT=pass
21688 10:56:10.514950 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_16 RESULT=pass>
21689 10:56:10.545821 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_16 RESULT=pass>
21690 10:56:10.546178 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_16 RESULT=pass
21692 10:56:10.577251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_16 RESULT=pass>
21693 10:56:10.577605 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_16 RESULT=pass
21695 10:56:10.608829 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_16 RESULT=pass>
21696 10:56:10.609307 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_16 RESULT=pass
21698 10:56:10.640179 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_32 RESULT=pass>
21699 10:56:10.640647 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_32 RESULT=pass
21701 10:56:10.677164 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_32 RESULT=pass
21703 10:56:10.677804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_32 RESULT=pass>
21704 10:56:10.709505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_32 RESULT=pass>
21705 10:56:10.709895 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_32 RESULT=pass
21707 10:56:10.741294 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_32 RESULT=pass>
21708 10:56:10.741663 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_32 RESULT=pass
21710 10:56:10.773683 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_48 RESULT=pass
21712 10:56:10.774123 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_48 RESULT=pass>
21713 10:56:10.806009 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_48 RESULT=skip>
21714 10:56:10.806385 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_48 RESULT=skip
21716 10:56:10.842487 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_48 RESULT=skip
21718 10:56:10.843122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_48 RESULT=skip>
21719 10:56:10.875416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_48 RESULT=skip>
21720 10:56:10.875782 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_48 RESULT=skip
21722 10:56:10.915442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_64 RESULT=pass>
21723 10:56:10.915834 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_64 RESULT=pass
21725 10:56:10.951989 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_64 RESULT=pass
21727 10:56:10.952450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_64 RESULT=pass>
21728 10:56:10.983520 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_64 RESULT=pass>
21729 10:56:10.983867 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_64 RESULT=pass
21731 10:56:11.015395 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_64 RESULT=pass>
21732 10:56:11.015818 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_64 RESULT=pass
21734 10:56:11.049675 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_80 RESULT=pass
21736 10:56:11.049974 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_80 RESULT=pass>
21737 10:56:11.081536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_80 RESULT=skip>
21738 10:56:11.081829 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_80 RESULT=skip
21740 10:56:11.113300 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_80 RESULT=skip
21742 10:56:11.113758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_80 RESULT=skip>
21743 10:56:11.144769 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_80 RESULT=skip>
21744 10:56:11.145121 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_80 RESULT=skip
21746 10:56:11.176977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_96 RESULT=pass>
21747 10:56:11.177327 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_96 RESULT=pass
21749 10:56:11.213860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_96 RESULT=skip>
21750 10:56:11.214332 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_96 RESULT=skip
21752 10:56:11.245922 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_96 RESULT=skip
21754 10:56:11.246449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_96 RESULT=skip>
21755 10:56:11.277576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_96 RESULT=skip>
21756 10:56:11.277983 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_96 RESULT=skip
21758 10:56:11.309579 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_112 RESULT=pass
21760 10:56:11.310221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_112 RESULT=pass>
21761 10:56:11.341008 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_112 RESULT=skip>
21762 10:56:11.341464 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_112 RESULT=skip
21764 10:56:11.378222 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_112 RESULT=skip>
21765 10:56:11.378672 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_112 RESULT=skip
21767 10:56:11.411273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_112 RESULT=skip>
21768 10:56:11.411683 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_112 RESULT=skip
21770 10:56:11.442406 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_128 RESULT=pass>
21771 10:56:11.442801 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_128 RESULT=pass
21773 10:56:11.474037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_128 RESULT=pass>
21774 10:56:11.474459 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_128 RESULT=pass
21776 10:56:11.506401 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_128 RESULT=pass>
21777 10:56:11.506799 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_128 RESULT=pass
21779 10:56:11.539333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_128 RESULT=pass>
21780 10:56:11.539737 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_128 RESULT=pass
21782 10:56:11.572989 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_144 RESULT=pass>
21783 10:56:11.573458 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_144 RESULT=pass
21785 10:56:11.605394 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_144 RESULT=skip>
21786 10:56:11.605887 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_144 RESULT=skip
21788 10:56:11.638153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_144 RESULT=skip>
21789 10:56:11.638610 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_144 RESULT=skip
21791 10:56:11.671196 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_144 RESULT=skip>
21792 10:56:11.671600 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_144 RESULT=skip
21794 10:56:11.703688 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_160 RESULT=pass
21796 10:56:11.704244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_160 RESULT=pass>
21797 10:56:11.736867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_160 RESULT=skip>
21798 10:56:11.737266 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_160 RESULT=skip
21800 10:56:11.769266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_160 RESULT=skip>
21801 10:56:11.769677 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_160 RESULT=skip
21803 10:56:11.802081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_160 RESULT=skip>
21804 10:56:11.802540 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_160 RESULT=skip
21806 10:56:11.834349 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_176 RESULT=pass
21808 10:56:11.834923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_176 RESULT=pass>
21809 10:56:11.866796 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_176 RESULT=skip
21811 10:56:11.867314 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_176 RESULT=skip>
21812 10:56:11.899181 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_176 RESULT=skip>
21813 10:56:11.899609 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_176 RESULT=skip
21815 10:56:11.931986 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_176 RESULT=skip
21817 10:56:11.932406 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_176 RESULT=skip>
21818 10:56:11.965215 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_192 RESULT=pass>
21819 10:56:11.965686 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_192 RESULT=pass
21821 10:56:11.998447 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_192 RESULT=skip>
21822 10:56:11.998901 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_192 RESULT=skip
21824 10:56:12.030892 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_192 RESULT=skip>
21825 10:56:12.031348 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_192 RESULT=skip
21827 10:56:12.062908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_192 RESULT=skip>
21828 10:56:12.063312 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_192 RESULT=skip
21830 10:56:12.095941 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_208 RESULT=pass
21832 10:56:12.096512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_208 RESULT=pass>
21833 10:56:12.128808 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_208 RESULT=skip>
21834 10:56:12.129216 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_208 RESULT=skip
21836 10:56:12.161364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_208 RESULT=skip>
21837 10:56:12.161657 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_208 RESULT=skip
21839 10:56:12.193661 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_208 RESULT=skip>
21840 10:56:12.193946 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_208 RESULT=skip
21842 10:56:12.226457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_224 RESULT=pass>
21843 10:56:12.226752 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_224 RESULT=pass
21845 10:56:12.262606 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_224 RESULT=skip>
21846 10:56:12.263074 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_224 RESULT=skip
21848 10:56:12.296272 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_224 RESULT=skip
21850 10:56:12.296776 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_224 RESULT=skip>
21851 10:56:12.327313 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_224 RESULT=skip>
21852 10:56:12.327691 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_224 RESULT=skip
21854 10:56:12.359327 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_240 RESULT=pass>
21855 10:56:12.359712 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_240 RESULT=pass
21857 10:56:12.391862 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_240 RESULT=skip
21859 10:56:12.392383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_240 RESULT=skip>
21860 10:56:12.425190 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_240 RESULT=skip>
21861 10:56:12.425562 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_240 RESULT=skip
21863 10:56:12.459999 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_240 RESULT=skip
21865 10:56:12.460442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_240 RESULT=skip>
21866 10:56:12.492459 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_256 RESULT=pass
21868 10:56:12.492887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_256 RESULT=pass>
21869 10:56:12.524975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_256 RESULT=pass>
21870 10:56:12.525326 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_256 RESULT=pass
21872 10:56:12.557602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_256 RESULT=pass>
21873 10:56:12.557908 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_256 RESULT=pass
21875 10:56:12.590520 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_256 RESULT=pass>
21876 10:56:12.590874 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_256 RESULT=pass
21878 10:56:12.622992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_272 RESULT=pass>
21879 10:56:12.623458 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_272 RESULT=pass
21881 10:56:12.656284 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_272 RESULT=skip
21883 10:56:12.656867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_272 RESULT=skip>
21884 10:56:12.687602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_272 RESULT=skip>
21885 10:56:12.688015 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_272 RESULT=skip
21887 10:56:12.720464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_272 RESULT=skip>
21888 10:56:12.720814 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_272 RESULT=skip
21890 10:56:12.752586 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_288 RESULT=pass
21892 10:56:12.753011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_288 RESULT=pass>
21893 10:56:12.785098 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_288 RESULT=skip>
21894 10:56:12.785394 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_288 RESULT=skip
21896 10:56:12.817841 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_288 RESULT=skip>
21897 10:56:12.818133 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_288 RESULT=skip
21899 10:56:12.849996 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_288 RESULT=skip
21901 10:56:12.850436 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_288 RESULT=skip>
21902 10:56:12.881995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_304 RESULT=pass>
21903 10:56:12.882469 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_304 RESULT=pass
21905 10:56:12.914202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_304 RESULT=skip>
21906 10:56:12.914560 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_304 RESULT=skip
21908 10:56:12.946301 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_304 RESULT=skip
21910 10:56:12.946733 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_304 RESULT=skip>
21911 10:56:12.978933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_304 RESULT=skip>
21912 10:56:12.979294 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_304 RESULT=skip
21914 10:56:13.017094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_320 RESULT=pass>
21915 10:56:13.017486 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_320 RESULT=pass
21917 10:56:13.049712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_320 RESULT=skip>
21918 10:56:13.050093 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_320 RESULT=skip
21920 10:56:13.082041 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_320 RESULT=skip
21922 10:56:13.082495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_320 RESULT=skip>
21923 10:56:13.113784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_320 RESULT=skip>
21924 10:56:13.114134 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_320 RESULT=skip
21926 10:56:13.145255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_336 RESULT=pass>
21927 10:56:13.145603 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_336 RESULT=pass
21929 10:56:13.177424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_336 RESULT=skip>
21930 10:56:13.177776 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_336 RESULT=skip
21932 10:56:13.208690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_336 RESULT=skip>
21933 10:56:13.209067 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_336 RESULT=skip
21935 10:56:13.239411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_336 RESULT=skip>
21936 10:56:13.239791 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_336 RESULT=skip
21938 10:56:13.270619 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_352 RESULT=pass
21940 10:56:13.271142 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_352 RESULT=pass>
21941 10:56:13.305151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_352 RESULT=skip>
21942 10:56:13.305587 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_352 RESULT=skip
21944 10:56:13.338248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_352 RESULT=skip>
21945 10:56:13.338627 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_352 RESULT=skip
21947 10:56:13.372940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_352 RESULT=skip>
21948 10:56:13.373365 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_352 RESULT=skip
21950 10:56:13.404366 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_368 RESULT=pass
21952 10:56:13.404766 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_368 RESULT=pass>
21953 10:56:13.435223 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_368 RESULT=skip
21955 10:56:13.435759 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_368 RESULT=skip>
21956 10:56:13.466778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_368 RESULT=skip>
21957 10:56:13.467181 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_368 RESULT=skip
21959 10:56:13.497815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_368 RESULT=skip>
21960 10:56:13.498273 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_368 RESULT=skip
21962 10:56:13.528736 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_384 RESULT=pass
21964 10:56:13.529279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_384 RESULT=pass>
21965 10:56:13.559901 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_384 RESULT=skip
21967 10:56:13.560474 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_384 RESULT=skip>
21968 10:56:13.592240 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_384 RESULT=skip>
21969 10:56:13.592688 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_384 RESULT=skip
21971 10:56:13.624536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_384 RESULT=skip>
21972 10:56:13.624991 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_384 RESULT=skip
21974 10:56:13.655371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_400 RESULT=pass>
21975 10:56:13.655818 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_400 RESULT=pass
21977 10:56:13.686945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_400 RESULT=skip>
21978 10:56:13.687399 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_400 RESULT=skip
21980 10:56:13.718220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_400 RESULT=skip>
21981 10:56:13.718671 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_400 RESULT=skip
21983 10:56:13.749731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_400 RESULT=skip>
21984 10:56:13.750174 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_400 RESULT=skip
21986 10:56:13.781128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_416 RESULT=pass>
21987 10:56:13.781529 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_416 RESULT=pass
21989 10:56:13.812703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_416 RESULT=skip>
21990 10:56:13.813153 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_416 RESULT=skip
21992 10:56:13.843819 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_416 RESULT=skip
21994 10:56:13.844269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_416 RESULT=skip>
21995 10:56:13.875224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_416 RESULT=skip>
21996 10:56:13.875675 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_416 RESULT=skip
21998 10:56:13.906768 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_432 RESULT=pass
22000 10:56:13.907319 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_432 RESULT=pass>
22001 10:56:13.937364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_432 RESULT=skip>
22002 10:56:13.937798 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_432 RESULT=skip
22004 10:56:13.968575 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_432 RESULT=skip>
22005 10:56:13.969011 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_432 RESULT=skip
22007 10:56:13.999634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_432 RESULT=skip>
22008 10:56:14.000039 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_432 RESULT=skip
22010 10:56:14.031463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_448 RESULT=pass>
22011 10:56:14.031923 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_448 RESULT=pass
22013 10:56:14.062421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_448 RESULT=skip>
22014 10:56:14.062892 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_448 RESULT=skip
22016 10:56:14.093897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_448 RESULT=skip>
22017 10:56:14.094270 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_448 RESULT=skip
22019 10:56:14.125208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_448 RESULT=skip>
22020 10:56:14.125509 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_448 RESULT=skip
22022 10:56:14.158765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_464 RESULT=pass>
22023 10:56:14.159185 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_464 RESULT=pass
22025 10:56:14.194311 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_464 RESULT=skip>
22026 10:56:14.194599 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_464 RESULT=skip
22028 10:56:14.226833 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_464 RESULT=skip>
22029 10:56:14.227238 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_464 RESULT=skip
22031 10:56:14.258660 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_464 RESULT=skip>
22032 10:56:14.259116 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_464 RESULT=skip
22034 10:56:14.294002 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_480 RESULT=pass>
22035 10:56:14.294428 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_480 RESULT=pass
22037 10:56:14.327608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_480 RESULT=skip>
22038 10:56:14.328060 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_480 RESULT=skip
22040 10:56:14.361943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_480 RESULT=skip>
22041 10:56:14.362431 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_480 RESULT=skip
22043 10:56:14.397810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_480 RESULT=skip>
22044 10:56:14.398231 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_480 RESULT=skip
22046 10:56:14.433770 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_496 RESULT=pass
22048 10:56:14.434258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_496 RESULT=pass>
22049 10:56:14.469483 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_496 RESULT=skip
22051 10:56:14.469872 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_496 RESULT=skip>
22052 10:56:14.502531 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_496 RESULT=skip>
22053 10:56:14.502962 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_496 RESULT=skip
22055 10:56:14.534652 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_496 RESULT=skip>
22056 10:56:14.535067 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_496 RESULT=skip
22058 10:56:14.565722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_512 RESULT=pass>
22059 10:56:14.566128 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_512 RESULT=pass
22061 10:56:14.597028 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_512 RESULT=skip>
22062 10:56:14.597477 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_512 RESULT=skip
22064 10:56:14.631974 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_512 RESULT=skip
22066 10:56:14.632561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_512 RESULT=skip>
22067 10:56:14.667172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_512 RESULT=skip>
22068 10:56:14.667633 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_512 RESULT=skip
22070 10:56:14.702044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_528 RESULT=pass>
22071 10:56:14.702563 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_528 RESULT=pass
22073 10:56:14.734124 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_528 RESULT=skip
22075 10:56:14.734702 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_528 RESULT=skip>
22076 10:56:14.764936 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_528 RESULT=skip>
22077 10:56:14.765360 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_528 RESULT=skip
22079 10:56:14.799507 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_528 RESULT=skip
22081 10:56:14.800002 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_528 RESULT=skip>
22082 10:56:14.832830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_544 RESULT=pass>
22083 10:56:14.833302 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_544 RESULT=pass
22085 10:56:14.866061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_544 RESULT=skip>
22086 10:56:14.866556 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_544 RESULT=skip
22088 10:56:14.898500 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_544 RESULT=skip
22090 10:56:14.898950 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_544 RESULT=skip>
22091 10:56:14.930093 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_544 RESULT=skip>
22092 10:56:14.930561 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_544 RESULT=skip
22094 10:56:14.961561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_560 RESULT=pass>
22095 10:56:14.961978 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_560 RESULT=pass
22097 10:56:14.993453 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_560 RESULT=skip>
22098 10:56:14.993951 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_560 RESULT=skip
22100 10:56:15.026088 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_560 RESULT=skip
22102 10:56:15.026687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_560 RESULT=skip>
22103 10:56:15.060853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_560 RESULT=skip>
22104 10:56:15.061299 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_560 RESULT=skip
22106 10:56:15.093610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_576 RESULT=pass>
22107 10:56:15.094057 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_576 RESULT=pass
22109 10:56:15.125388 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_576 RESULT=skip
22111 10:56:15.125807 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_576 RESULT=skip>
22112 10:56:15.158813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_576 RESULT=skip>
22113 10:56:15.159233 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_576 RESULT=skip
22115 10:56:15.194653 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_576 RESULT=skip
22117 10:56:15.195102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_576 RESULT=skip>
22118 10:56:15.230586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_592 RESULT=pass>
22119 10:56:15.230977 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_592 RESULT=pass
22121 10:56:15.264664 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_592 RESULT=skip
22123 10:56:15.265027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_592 RESULT=skip>
22124 10:56:15.314479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_592 RESULT=skip>
22125 10:56:15.314904 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_592 RESULT=skip
22127 10:56:15.346171 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_592 RESULT=skip>
22128 10:56:15.346646 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_592 RESULT=skip
22130 10:56:15.378742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_608 RESULT=pass>
22131 10:56:15.379177 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_608 RESULT=pass
22133 10:56:15.409699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_608 RESULT=skip>
22134 10:56:15.410057 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_608 RESULT=skip
22136 10:56:15.441113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_608 RESULT=skip>
22137 10:56:15.441495 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_608 RESULT=skip
22139 10:56:15.473144 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_608 RESULT=skip>
22140 10:56:15.473527 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_608 RESULT=skip
22142 10:56:15.504232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_624 RESULT=pass>
22143 10:56:15.504688 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_624 RESULT=pass
22145 10:56:15.539478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_624 RESULT=skip>
22146 10:56:15.539963 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_624 RESULT=skip
22148 10:56:15.571830 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_624 RESULT=skip
22150 10:56:15.572422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_624 RESULT=skip>
22151 10:56:15.602584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_624 RESULT=skip>
22152 10:56:15.602991 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_624 RESULT=skip
22154 10:56:15.633641 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_640 RESULT=pass
22156 10:56:15.634284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_640 RESULT=pass>
22157 10:56:15.664835 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_640 RESULT=skip>
22158 10:56:15.665241 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_640 RESULT=skip
22160 10:56:15.696374 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_640 RESULT=skip
22162 10:56:15.696774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_640 RESULT=skip>
22163 10:56:15.728375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_640 RESULT=skip>
22164 10:56:15.728728 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_640 RESULT=skip
22166 10:56:15.758755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_656 RESULT=pass>
22167 10:56:15.759051 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_656 RESULT=pass
22169 10:56:15.789597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_656 RESULT=skip>
22170 10:56:15.790071 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_656 RESULT=skip
22172 10:56:15.820827 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_656 RESULT=skip>
22173 10:56:15.821287 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_656 RESULT=skip
22175 10:56:15.854311 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_656 RESULT=skip>
22176 10:56:15.854789 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_656 RESULT=skip
22178 10:56:15.885136 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_672 RESULT=pass
22180 10:56:15.885781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_672 RESULT=pass>
22181 10:56:15.917154 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_672 RESULT=skip
22183 10:56:15.917737 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_672 RESULT=skip>
22184 10:56:15.948868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_672 RESULT=skip>
22185 10:56:15.949334 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_672 RESULT=skip
22187 10:56:15.980103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_672 RESULT=skip>
22188 10:56:15.980583 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_672 RESULT=skip
22190 10:56:16.011061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_688 RESULT=pass>
22191 10:56:16.011549 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_688 RESULT=pass
22193 10:56:16.042427 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_688 RESULT=skip>
22194 10:56:16.042891 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_688 RESULT=skip
22196 10:56:16.074097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_688 RESULT=skip>
22197 10:56:16.074584 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_688 RESULT=skip
22199 10:56:16.105514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_688 RESULT=skip>
22200 10:56:16.105893 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_688 RESULT=skip
22202 10:56:16.138382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_704 RESULT=pass>
22203 10:56:16.138861 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_704 RESULT=pass
22205 10:56:16.169456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_704 RESULT=skip>
22206 10:56:16.169947 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_704 RESULT=skip
22208 10:56:16.200324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_704 RESULT=skip>
22209 10:56:16.200731 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_704 RESULT=skip
22211 10:56:16.231415 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_704 RESULT=skip
22213 10:56:16.231879 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_704 RESULT=skip>
22214 10:56:16.262581 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_720 RESULT=pass
22216 10:56:16.263023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_720 RESULT=pass>
22217 10:56:16.293820 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_720 RESULT=skip
22219 10:56:16.294389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_720 RESULT=skip>
22220 10:56:16.324915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_720 RESULT=skip>
22221 10:56:16.325365 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_720 RESULT=skip
22223 10:56:16.356105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_720 RESULT=skip>
22224 10:56:16.356519 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_720 RESULT=skip
22226 10:56:16.388606 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_736 RESULT=pass
22228 10:56:16.389052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_736 RESULT=pass>
22229 10:56:16.420341 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_736 RESULT=skip
22231 10:56:16.420804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_736 RESULT=skip>
22232 10:56:16.451042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_736 RESULT=skip>
22233 10:56:16.451434 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_736 RESULT=skip
22235 10:56:16.482058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_736 RESULT=skip>
22236 10:56:16.482462 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_736 RESULT=skip
22238 10:56:16.512699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_752 RESULT=pass>
22239 10:56:16.513159 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_752 RESULT=pass
22241 10:56:16.543541 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_752 RESULT=skip>
22242 10:56:16.543927 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_752 RESULT=skip
22244 10:56:16.581110 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_752 RESULT=skip>
22245 10:56:16.581459 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_752 RESULT=skip
22247 10:56:16.617606 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_752 RESULT=skip
22249 10:56:16.618352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_752 RESULT=skip>
22250 10:56:16.652494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_768 RESULT=pass>
22251 10:56:16.652855 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_768 RESULT=pass
22253 10:56:16.688615 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_768 RESULT=skip>
22254 10:56:16.689289 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_768 RESULT=skip
22256 10:56:16.725842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_768 RESULT=skip>
22257 10:56:16.726291 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_768 RESULT=skip
22259 10:56:16.763333 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_768 RESULT=skip
22261 10:56:16.763955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_768 RESULT=skip>
22262 10:56:16.797092 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_784 RESULT=pass>
22263 10:56:16.797586 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_784 RESULT=pass
22265 10:56:16.834365 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_784 RESULT=skip>
22266 10:56:16.834842 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_784 RESULT=skip
22268 10:56:16.872240 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_784 RESULT=skip
22270 10:56:16.872807 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_784 RESULT=skip>
22271 10:56:16.910281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_784 RESULT=skip>
22272 10:56:16.910821 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_784 RESULT=skip
22274 10:56:16.946401 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_800 RESULT=pass>
22275 10:56:16.946759 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_800 RESULT=pass
22277 10:56:16.985042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_800 RESULT=skip>
22278 10:56:16.985408 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_800 RESULT=skip
22280 10:56:17.022358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_800 RESULT=skip>
22281 10:56:17.022819 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_800 RESULT=skip
22283 10:56:17.060483 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_800 RESULT=skip
22285 10:56:17.060900 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_800 RESULT=skip>
22286 10:56:17.096099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_816 RESULT=pass>
22287 10:56:17.096492 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_816 RESULT=pass
22289 10:56:17.133046 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_816 RESULT=skip
22291 10:56:17.133675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_816 RESULT=skip>
22292 10:56:17.173197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_816 RESULT=skip>
22293 10:56:17.173587 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_816 RESULT=skip
22295 10:56:17.211044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_816 RESULT=skip>
22296 10:56:17.211489 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_816 RESULT=skip
22298 10:56:17.247704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_832 RESULT=pass>
22299 10:56:17.248109 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_832 RESULT=pass
22301 10:56:17.286009 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_832 RESULT=skip
22303 10:56:17.286425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_832 RESULT=skip>
22304 10:56:17.324821 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_832 RESULT=skip>
22305 10:56:17.325175 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_832 RESULT=skip
22307 10:56:17.358325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_832 RESULT=skip>
22308 10:56:17.358625 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_832 RESULT=skip
22310 10:56:17.392156 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_848 RESULT=pass
22312 10:56:17.392709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_848 RESULT=pass>
22313 10:56:17.428888 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_848 RESULT=skip
22315 10:56:17.429346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_848 RESULT=skip>
22316 10:56:17.465102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_848 RESULT=skip>
22317 10:56:17.465562 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_848 RESULT=skip
22319 10:56:17.501038 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_848 RESULT=skip>
22320 10:56:17.501526 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_848 RESULT=skip
22322 10:56:17.538914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_864 RESULT=pass>
22323 10:56:17.539373 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_864 RESULT=pass
22325 10:56:17.575235 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_864 RESULT=skip
22327 10:56:17.575701 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_864 RESULT=skip>
22328 10:56:17.609820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_864 RESULT=skip>
22329 10:56:17.610343 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_864 RESULT=skip
22331 10:56:17.646840 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_864 RESULT=skip>
22332 10:56:17.647298 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_864 RESULT=skip
22334 10:56:17.686273 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_880 RESULT=pass
22336 10:56:17.686970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_880 RESULT=pass>
22337 10:56:17.723145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_880 RESULT=skip>
22338 10:56:17.723584 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_880 RESULT=skip
22340 10:56:17.761713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_880 RESULT=skip>
22341 10:56:17.762150 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_880 RESULT=skip
22343 10:56:17.798648 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_880 RESULT=skip>
22344 10:56:17.799144 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_880 RESULT=skip
22346 10:56:17.836174 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_896 RESULT=pass
22348 10:56:17.836615 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_896 RESULT=pass>
22349 10:56:17.875559 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_896 RESULT=skip>
22350 10:56:17.876003 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_896 RESULT=skip
22352 10:56:17.917296 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_896 RESULT=skip
22354 10:56:17.917880 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_896 RESULT=skip>
22355 10:56:17.956682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_896 RESULT=skip>
22356 10:56:17.957124 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_896 RESULT=skip
22358 10:56:17.992881 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_912 RESULT=pass
22360 10:56:17.993409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_912 RESULT=pass>
22361 10:56:18.027567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_912 RESULT=skip>
22362 10:56:18.028065 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_912 RESULT=skip
22364 10:56:18.065253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_912 RESULT=skip>
22365 10:56:18.065642 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_912 RESULT=skip
22367 10:56:18.101611 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_912 RESULT=skip>
22368 10:56:18.101993 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_912 RESULT=skip
22370 10:56:18.136698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_928 RESULT=pass>
22371 10:56:18.137226 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_928 RESULT=pass
22373 10:56:18.173791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_928 RESULT=skip>
22374 10:56:18.174212 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_928 RESULT=skip
22376 10:56:18.210203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_928 RESULT=skip>
22377 10:56:18.210639 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_928 RESULT=skip
22379 10:56:18.244697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_928 RESULT=skip>
22380 10:56:18.245106 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_928 RESULT=skip
22382 10:56:18.281944 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_944 RESULT=pass>
22383 10:56:18.282426 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_944 RESULT=pass
22385 10:56:18.318092 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_944 RESULT=skip>
22386 10:56:18.318569 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_944 RESULT=skip
22388 10:56:18.356842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_944 RESULT=skip>
22389 10:56:18.357197 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_944 RESULT=skip
22391 10:56:18.398209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_944 RESULT=skip>
22392 10:56:18.398624 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_944 RESULT=skip
22394 10:56:18.433577 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_960 RESULT=pass>
22395 10:56:18.433935 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_960 RESULT=pass
22397 10:56:18.473984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_960 RESULT=skip>
22398 10:56:18.474493 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_960 RESULT=skip
22400 10:56:18.515817 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_960 RESULT=skip
22402 10:56:18.516236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_960 RESULT=skip>
22403 10:56:18.556327 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_960 RESULT=skip>
22404 10:56:18.556732 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_960 RESULT=skip
22406 10:56:18.613942 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_976 RESULT=pass
22408 10:56:18.614394 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_976 RESULT=pass>
22409 10:56:18.681675 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_976 RESULT=skip
22411 10:56:18.682515 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_976 RESULT=skip>
22412 10:56:18.735168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_976 RESULT=skip>
22413 10:56:18.735679 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_976 RESULT=skip
22415 10:56:18.787218 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_976 RESULT=skip>
22416 10:56:18.787708 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_976 RESULT=skip
22418 10:56:18.839720 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_992 RESULT=pass
22420 10:56:18.840392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_992 RESULT=pass>
22421 10:56:18.891582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_992 RESULT=skip>
22422 10:56:18.891998 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_992 RESULT=skip
22424 10:56:18.945071 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_992 RESULT=skip
22426 10:56:18.945555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_992 RESULT=skip>
22427 10:56:18.996633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_992 RESULT=skip>
22428 10:56:18.997012 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_992 RESULT=skip
22430 10:56:19.048932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1008 RESULT=pass>
22431 10:56:19.049326 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1008 RESULT=pass
22433 10:56:19.093137 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1008 RESULT=skip>
22434 10:56:19.093586 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1008 RESULT=skip
22436 10:56:19.133375 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1008 RESULT=skip
22438 10:56:19.133837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1008 RESULT=skip>
22439 10:56:19.170431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1008 RESULT=skip>
22440 10:56:19.170823 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1008 RESULT=skip
22442 10:56:19.225512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1024 RESULT=pass>
22443 10:56:19.225964 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1024 RESULT=pass
22445 10:56:19.280941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1024 RESULT=skip>
22446 10:56:19.281321 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1024 RESULT=skip
22448 10:56:19.334290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1024 RESULT=skip>
22449 10:56:19.334655 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1024 RESULT=skip
22451 10:56:19.389413 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1024 RESULT=skip>
22452 10:56:19.389779 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1024 RESULT=skip
22454 10:56:19.442249 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1040 RESULT=pass
22456 10:56:19.442763 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1040 RESULT=pass>
22457 10:56:19.495295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1040 RESULT=skip>
22458 10:56:19.495764 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1040 RESULT=skip
22460 10:56:19.547751 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1040 RESULT=skip>
22461 10:56:19.548182 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1040 RESULT=skip
22463 10:56:19.601723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1040 RESULT=skip>
22464 10:56:19.602164 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1040 RESULT=skip
22466 10:56:19.655956 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1056 RESULT=pass
22468 10:56:19.656645 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1056 RESULT=pass>
22469 10:56:19.711924 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1056 RESULT=skip
22471 10:56:19.712532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1056 RESULT=skip>
22472 10:56:19.765807 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1056 RESULT=skip>
22473 10:56:19.766226 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1056 RESULT=skip
22475 10:56:19.819383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1056 RESULT=skip>
22476 10:56:19.819767 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1056 RESULT=skip
22478 10:56:19.869722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1072 RESULT=pass>
22479 10:56:19.870156 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1072 RESULT=pass
22481 10:56:19.922008 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1072 RESULT=skip
22483 10:56:19.922450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1072 RESULT=skip>
22484 10:56:19.971604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1072 RESULT=skip>
22485 10:56:19.972042 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1072 RESULT=skip
22487 10:56:20.014138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1072 RESULT=skip>
22488 10:56:20.014572 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1072 RESULT=skip
22490 10:56:20.053160 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1088 RESULT=pass>
22491 10:56:20.053795 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1088 RESULT=pass
22493 10:56:20.101118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1088 RESULT=skip>
22494 10:56:20.101538 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1088 RESULT=skip
22496 10:56:20.139632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1088 RESULT=skip>
22497 10:56:20.140070 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1088 RESULT=skip
22499 10:56:20.185468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1088 RESULT=skip>
22500 10:56:20.185908 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1088 RESULT=skip
22502 10:56:20.234291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1104 RESULT=pass>
22503 10:56:20.234724 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1104 RESULT=pass
22505 10:56:20.282555 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1104 RESULT=skip
22507 10:56:20.283006 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1104 RESULT=skip>
22508 10:56:20.331144 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1104 RESULT=skip>
22509 10:56:20.331573 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1104 RESULT=skip
22511 10:56:20.381158 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1104 RESULT=skip
22513 10:56:20.381618 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1104 RESULT=skip>
22514 10:56:20.455785 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1120 RESULT=pass
22516 10:56:20.456255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1120 RESULT=pass>
22517 10:56:20.505354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1120 RESULT=skip>
22518 10:56:20.505791 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1120 RESULT=skip
22520 10:56:20.547083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1120 RESULT=skip>
22521 10:56:20.547639 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1120 RESULT=skip
22523 10:56:20.595415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1120 RESULT=skip>
22524 10:56:20.595887 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1120 RESULT=skip
22526 10:56:20.636819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1136 RESULT=pass>
22527 10:56:20.637207 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1136 RESULT=pass
22529 10:56:20.673431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1136 RESULT=skip>
22530 10:56:20.673851 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1136 RESULT=skip
22532 10:56:20.709913 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1136 RESULT=skip>
22533 10:56:20.710356 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1136 RESULT=skip
22535 10:56:20.746183 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1136 RESULT=skip>
22536 10:56:20.746612 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1136 RESULT=skip
22538 10:56:20.793522 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1152 RESULT=pass>
22539 10:56:20.793958 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1152 RESULT=pass
22541 10:56:20.841851 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1152 RESULT=skip>
22542 10:56:20.842292 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1152 RESULT=skip
22544 10:56:20.890380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1152 RESULT=skip>
22545 10:56:20.890804 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1152 RESULT=skip
22547 10:56:20.940178 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1152 RESULT=skip
22549 10:56:20.940729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1152 RESULT=skip>
22550 10:56:20.993697 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1168 RESULT=pass
22552 10:56:20.994172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1168 RESULT=pass>
22553 10:56:21.045860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1168 RESULT=skip>
22554 10:56:21.046294 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1168 RESULT=skip
22556 10:56:21.098223 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1168 RESULT=skip>
22557 10:56:21.098640 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1168 RESULT=skip
22559 10:56:21.150821 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1168 RESULT=skip
22561 10:56:21.151264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1168 RESULT=skip>
22562 10:56:21.204921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1184 RESULT=pass>
22563 10:56:21.205330 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1184 RESULT=pass
22565 10:56:21.257245 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1184 RESULT=skip>
22566 10:56:21.257679 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1184 RESULT=skip
22568 10:56:21.309498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1184 RESULT=skip>
22569 10:56:21.309924 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1184 RESULT=skip
22571 10:56:21.361620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1184 RESULT=skip>
22572 10:56:21.362048 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1184 RESULT=skip
22574 10:56:21.413790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1200 RESULT=pass>
22575 10:56:21.414201 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1200 RESULT=pass
22577 10:56:21.466250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1200 RESULT=skip>
22578 10:56:21.466633 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1200 RESULT=skip
22580 10:56:21.518666 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1200 RESULT=skip>
22581 10:56:21.519084 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1200 RESULT=skip
22583 10:56:21.570820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1200 RESULT=skip>
22584 10:56:21.571239 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1200 RESULT=skip
22586 10:56:21.623723 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1216 RESULT=pass
22588 10:56:21.624165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1216 RESULT=pass>
22589 10:56:21.675907 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1216 RESULT=skip
22591 10:56:21.676354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1216 RESULT=skip>
22592 10:56:21.727358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1216 RESULT=skip>
22593 10:56:21.727748 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1216 RESULT=skip
22595 10:56:21.779352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1216 RESULT=skip>
22596 10:56:21.779771 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1216 RESULT=skip
22598 10:56:21.828986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1232 RESULT=pass>
22599 10:56:21.829422 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1232 RESULT=pass
22601 10:56:21.877000 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1232 RESULT=skip>
22602 10:56:21.877425 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1232 RESULT=skip
22604 10:56:21.922157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1232 RESULT=skip>
22605 10:56:21.922598 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1232 RESULT=skip
22607 10:56:21.970858 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1232 RESULT=skip
22609 10:56:21.971323 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1232 RESULT=skip>
22610 10:56:22.021147 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1248 RESULT=pass
22612 10:56:22.021628 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1248 RESULT=pass>
22613 10:56:22.069377 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1248 RESULT=skip>
22614 10:56:22.069818 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1248 RESULT=skip
22616 10:56:22.117668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1248 RESULT=skip>
22617 10:56:22.118116 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1248 RESULT=skip
22619 10:56:22.163443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1248 RESULT=skip>
22620 10:56:22.163843 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1248 RESULT=skip
22622 10:56:22.209607 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1264 RESULT=pass
22624 10:56:22.209986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1264 RESULT=pass>
22625 10:56:22.257962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1264 RESULT=skip>
22626 10:56:22.258286 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1264 RESULT=skip
22628 10:56:22.299236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1264 RESULT=skip>
22629 10:56:22.299559 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1264 RESULT=skip
22631 10:56:22.346051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1264 RESULT=skip>
22632 10:56:22.346407 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1264 RESULT=skip
22634 10:56:22.399406 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1280 RESULT=pass>
22635 10:56:22.399729 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1280 RESULT=pass
22637 10:56:22.445568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1280 RESULT=skip>
22638 10:56:22.445893 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1280 RESULT=skip
22640 10:56:22.489940 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1280 RESULT=skip
22642 10:56:22.490244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1280 RESULT=skip>
22643 10:56:22.544556 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1280 RESULT=skip
22645 10:56:22.544866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1280 RESULT=skip>
22646 10:56:22.597245 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1296 RESULT=pass>
22647 10:56:22.597538 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1296 RESULT=pass
22649 10:56:22.650772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1296 RESULT=skip>
22650 10:56:22.651079 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1296 RESULT=skip
22652 10:56:22.703303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1296 RESULT=skip>
22653 10:56:22.703608 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1296 RESULT=skip
22655 10:56:22.757680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1296 RESULT=skip>
22656 10:56:22.758046 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1296 RESULT=skip
22658 10:56:22.810362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1312 RESULT=pass>
22659 10:56:22.810703 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1312 RESULT=pass
22661 10:56:22.863937 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1312 RESULT=skip
22663 10:56:22.864372 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1312 RESULT=skip>
22664 10:56:22.917567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1312 RESULT=skip>
22665 10:56:22.917911 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1312 RESULT=skip
22667 10:56:22.971875 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1312 RESULT=skip>
22668 10:56:22.972337 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1312 RESULT=skip
22670 10:56:23.026688 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1328 RESULT=pass
22672 10:56:23.027095 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1328 RESULT=pass>
22673 10:56:23.078951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1328 RESULT=skip>
22674 10:56:23.079313 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1328 RESULT=skip
22676 10:56:23.131957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1328 RESULT=skip>
22677 10:56:23.132381 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1328 RESULT=skip
22679 10:56:23.184129 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1328 RESULT=skip
22681 10:56:23.184570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1328 RESULT=skip>
22682 10:56:23.236967 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1344 RESULT=pass>
22683 10:56:23.237356 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1344 RESULT=pass
22685 10:56:23.289407 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1344 RESULT=skip>
22686 10:56:23.289760 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1344 RESULT=skip
22688 10:56:23.341773 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1344 RESULT=skip
22690 10:56:23.342147 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1344 RESULT=skip>
22691 10:56:23.394393 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1344 RESULT=skip>
22692 10:56:23.394713 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1344 RESULT=skip
22694 10:56:23.445277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1360 RESULT=pass>
22695 10:56:23.445684 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1360 RESULT=pass
22697 10:56:23.494576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1360 RESULT=skip>
22698 10:56:23.495035 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1360 RESULT=skip
22700 10:56:23.546325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1360 RESULT=skip>
22701 10:56:23.546722 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1360 RESULT=skip
22703 10:56:23.595383 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1360 RESULT=skip
22705 10:56:23.595811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1360 RESULT=skip>
22706 10:56:23.644997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1376 RESULT=pass>
22707 10:56:23.645353 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1376 RESULT=pass
22709 10:56:23.695495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1376 RESULT=skip>
22710 10:56:23.695905 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1376 RESULT=skip
22712 10:56:23.746510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1376 RESULT=skip>
22713 10:56:23.746954 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1376 RESULT=skip
22715 10:56:23.797971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1376 RESULT=skip>
22716 10:56:23.801684 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1376 RESULT=skip
22718 10:56:23.853727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1392 RESULT=pass>
22719 10:56:23.857688 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1392 RESULT=pass
22721 10:56:23.899058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1392 RESULT=skip>
22722 10:56:23.899516 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1392 RESULT=skip
22724 10:56:23.946807 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1392 RESULT=skip>
22725 10:56:23.947169 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1392 RESULT=skip
22727 10:56:23.997514 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1392 RESULT=skip
22729 10:56:23.997916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1392 RESULT=skip>
22730 10:56:24.045816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1408 RESULT=pass>
22731 10:56:24.046117 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1408 RESULT=pass
22733 10:56:24.094280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1408 RESULT=skip>
22734 10:56:24.094571 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1408 RESULT=skip
22736 10:56:24.142156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1408 RESULT=skip>
22737 10:56:24.142449 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1408 RESULT=skip
22739 10:56:24.195170 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1408 RESULT=skip>
22740 10:56:24.195490 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1408 RESULT=skip
22742 10:56:24.246212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1424 RESULT=pass>
22743 10:56:24.246499 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1424 RESULT=pass
22745 10:56:24.298080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1424 RESULT=skip>
22746 10:56:24.298379 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1424 RESULT=skip
22748 10:56:24.350425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1424 RESULT=skip>
22749 10:56:24.350736 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1424 RESULT=skip
22751 10:56:24.403093 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1424 RESULT=skip>
22752 10:56:24.403488 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1424 RESULT=skip
22754 10:56:24.454783 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1440 RESULT=pass
22756 10:56:24.455213 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1440 RESULT=pass>
22757 10:56:24.505351 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1440 RESULT=skip
22759 10:56:24.505677 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1440 RESULT=skip>
22760 10:56:24.554742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1440 RESULT=skip>
22761 10:56:24.555050 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1440 RESULT=skip
22763 10:56:24.604409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1440 RESULT=skip>
22764 10:56:24.604710 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1440 RESULT=skip
22766 10:56:24.648907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1456 RESULT=pass>
22767 10:56:24.649210 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1456 RESULT=pass
22769 10:56:24.694028 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1456 RESULT=skip>
22770 10:56:24.694339 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1456 RESULT=skip
22772 10:56:24.743752 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1456 RESULT=skip
22774 10:56:24.744075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1456 RESULT=skip>
22775 10:56:24.792509 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1456 RESULT=skip
22777 10:56:24.792812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1456 RESULT=skip>
22778 10:56:24.842380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1472 RESULT=pass>
22779 10:56:24.842665 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1472 RESULT=pass
22781 10:56:24.886544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1472 RESULT=skip>
22782 10:56:24.886812 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1472 RESULT=skip
22784 10:56:24.935850 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1472 RESULT=skip
22786 10:56:24.936154 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1472 RESULT=skip>
22787 10:56:24.984650 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1472 RESULT=skip>
22788 10:56:24.984941 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1472 RESULT=skip
22790 10:56:25.022441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1488 RESULT=pass>
22791 10:56:25.022701 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1488 RESULT=pass
22793 10:56:25.069757 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1488 RESULT=skip
22795 10:56:25.070080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1488 RESULT=skip>
22796 10:56:25.118657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1488 RESULT=skip>
22797 10:56:25.118977 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1488 RESULT=skip
22799 10:56:25.164497 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1488 RESULT=skip>
22800 10:56:25.164919 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1488 RESULT=skip
22802 10:56:25.208879 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1504 RESULT=pass>
22803 10:56:25.209293 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1504 RESULT=pass
22805 10:56:25.250347 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1504 RESULT=skip>
22806 10:56:25.250764 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1504 RESULT=skip
22808 10:56:25.294421 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1504 RESULT=skip
22810 10:56:25.294891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1504 RESULT=skip>
22811 10:56:25.338060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1504 RESULT=skip>
22812 10:56:25.338464 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1504 RESULT=skip
22814 10:56:25.379818 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1520 RESULT=pass
22816 10:56:25.380273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1520 RESULT=pass>
22817 10:56:25.423608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1520 RESULT=skip>
22818 10:56:25.424023 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1520 RESULT=skip
22820 10:56:25.467335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1520 RESULT=skip>
22821 10:56:25.467750 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1520 RESULT=skip
22823 10:56:25.510781 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1520 RESULT=skip
22825 10:56:25.511199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1520 RESULT=skip>
22826 10:56:25.583781 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1536 RESULT=pass
22828 10:56:25.584435 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1536 RESULT=pass>
22829 10:56:25.623385 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1536 RESULT=skip
22831 10:56:25.623828 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1536 RESULT=skip>
22832 10:56:25.666935 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1536 RESULT=skip>
22833 10:56:25.667352 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1536 RESULT=skip
22835 10:56:25.698838 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1536 RESULT=skip
22837 10:56:25.699251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1536 RESULT=skip>
22838 10:56:25.741301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1552 RESULT=pass>
22839 10:56:25.741692 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1552 RESULT=pass
22841 10:56:25.785636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1552 RESULT=skip>
22842 10:56:25.786120 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1552 RESULT=skip
22844 10:56:25.829713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1552 RESULT=skip>
22845 10:56:25.830141 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1552 RESULT=skip
22847 10:56:25.874684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1552 RESULT=skip>
22848 10:56:25.875069 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1552 RESULT=skip
22850 10:56:25.917710 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1568 RESULT=pass>
22851 10:56:25.918143 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1568 RESULT=pass
22853 10:56:25.961859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1568 RESULT=skip>
22854 10:56:25.962283 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1568 RESULT=skip
22856 10:56:26.006058 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1568 RESULT=skip
22858 10:56:26.006505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1568 RESULT=skip>
22859 10:56:26.050254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1568 RESULT=skip>
22860 10:56:26.050642 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1568 RESULT=skip
22862 10:56:26.093218 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1584 RESULT=pass>
22863 10:56:26.093660 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1584 RESULT=pass
22865 10:56:26.130850 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1584 RESULT=skip>
22866 10:56:26.131217 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1584 RESULT=skip
22868 10:56:26.171355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1584 RESULT=skip>
22869 10:56:26.171717 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1584 RESULT=skip
22871 10:56:26.218243 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1584 RESULT=skip
22873 10:56:26.218718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1584 RESULT=skip>
22874 10:56:26.261684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1600 RESULT=pass>
22875 10:56:26.262099 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1600 RESULT=pass
22877 10:56:26.305830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1600 RESULT=skip>
22878 10:56:26.306269 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1600 RESULT=skip
22880 10:56:26.351401 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1600 RESULT=skip>
22881 10:56:26.351843 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1600 RESULT=skip
22883 10:56:26.393951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1600 RESULT=skip>
22884 10:56:26.394364 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1600 RESULT=skip
22886 10:56:26.430978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1616 RESULT=pass>
22887 10:56:26.431378 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1616 RESULT=pass
22889 10:56:26.474558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1616 RESULT=skip>
22890 10:56:26.474992 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1616 RESULT=skip
22892 10:56:26.518084 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1616 RESULT=skip
22894 10:56:26.518526 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1616 RESULT=skip>
22895 10:56:26.561893 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1616 RESULT=skip
22897 10:56:26.562271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1616 RESULT=skip>
22898 10:56:26.606729 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1632 RESULT=pass
22900 10:56:26.607135 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1632 RESULT=pass>
22901 10:56:26.650584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1632 RESULT=skip>
22902 10:56:26.650982 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1632 RESULT=skip
22904 10:56:26.695055 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1632 RESULT=skip>
22905 10:56:26.695434 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1632 RESULT=skip
22907 10:56:26.739103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1632 RESULT=skip>
22908 10:56:26.739513 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1632 RESULT=skip
22910 10:56:26.782675 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1648 RESULT=pass
22912 10:56:26.783114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1648 RESULT=pass>
22913 10:56:26.828629 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1648 RESULT=skip>
22914 10:56:26.829054 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1648 RESULT=skip
22916 10:56:26.861898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1648 RESULT=skip>
22917 10:56:26.862324 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1648 RESULT=skip
22919 10:56:26.902723 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1648 RESULT=skip
22921 10:56:26.903152 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1648 RESULT=skip>
22922 10:56:26.948244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1664 RESULT=pass>
22923 10:56:26.948659 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1664 RESULT=pass
22925 10:56:26.994268 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1664 RESULT=skip>
22926 10:56:26.994679 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1664 RESULT=skip
22928 10:56:27.040998 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1664 RESULT=skip>
22929 10:56:27.041436 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1664 RESULT=skip
22931 10:56:27.086977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1664 RESULT=skip>
22932 10:56:27.087408 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1664 RESULT=skip
22934 10:56:27.129303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1680 RESULT=pass>
22935 10:56:27.129684 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1680 RESULT=pass
22937 10:56:27.172661 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1680 RESULT=skip>
22938 10:56:27.173040 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1680 RESULT=skip
22940 10:56:27.216993 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1680 RESULT=skip>
22941 10:56:27.217383 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1680 RESULT=skip
22943 10:56:27.260832 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1680 RESULT=skip
22945 10:56:27.261309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1680 RESULT=skip>
22946 10:56:27.302447 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1696 RESULT=pass>
22947 10:56:27.302861 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1696 RESULT=pass
22949 10:56:27.346048 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1696 RESULT=skip
22951 10:56:27.346523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1696 RESULT=skip>
22952 10:56:27.389915 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1696 RESULT=skip
22954 10:56:27.390289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1696 RESULT=skip>
22955 10:56:27.432534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1696 RESULT=skip>
22956 10:56:27.432898 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1696 RESULT=skip
22958 10:56:27.473546 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1712 RESULT=pass>
22959 10:56:27.473963 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1712 RESULT=pass
22961 10:56:27.514903 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1712 RESULT=skip>
22962 10:56:27.515330 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1712 RESULT=skip
22964 10:56:27.558258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1712 RESULT=skip>
22965 10:56:27.558673 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1712 RESULT=skip
22967 10:56:27.602459 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1712 RESULT=skip
22969 10:56:27.602934 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1712 RESULT=skip>
22970 10:56:27.649669 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1728 RESULT=pass>
22971 10:56:27.650111 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1728 RESULT=pass
22973 10:56:27.692013 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1728 RESULT=skip
22975 10:56:27.692610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1728 RESULT=skip>
22976 10:56:27.735893 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1728 RESULT=skip
22978 10:56:27.736382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1728 RESULT=skip>
22979 10:56:27.779380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1728 RESULT=skip>
22980 10:56:27.779806 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1728 RESULT=skip
22982 10:56:27.822668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1744 RESULT=pass>
22983 10:56:27.823105 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1744 RESULT=pass
22985 10:56:27.864256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1744 RESULT=skip>
22986 10:56:27.864694 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1744 RESULT=skip
22988 10:56:27.909928 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1744 RESULT=skip>
22989 10:56:27.910357 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1744 RESULT=skip
22991 10:56:27.962992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1744 RESULT=skip>
22992 10:56:27.963422 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1744 RESULT=skip
22994 10:56:28.007876 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1760 RESULT=pass
22996 10:56:28.008357 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1760 RESULT=pass>
22997 10:56:28.045253 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1760 RESULT=skip
22999 10:56:28.045731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1760 RESULT=skip>
23000 10:56:28.077811 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1760 RESULT=skip
23002 10:56:28.078264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1760 RESULT=skip>
23003 10:56:28.121325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1760 RESULT=skip>
23004 10:56:28.121744 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1760 RESULT=skip
23006 10:56:28.164156 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1776 RESULT=pass
23008 10:56:28.164617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1776 RESULT=pass>
23009 10:56:28.209416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1776 RESULT=skip>
23010 10:56:28.209795 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1776 RESULT=skip
23012 10:56:28.254756 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1776 RESULT=skip
23014 10:56:28.255203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1776 RESULT=skip>
23015 10:56:28.296775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1776 RESULT=skip>
23016 10:56:28.297222 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1776 RESULT=skip
23018 10:56:28.340604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1792 RESULT=pass>
23019 10:56:28.341141 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1792 RESULT=pass
23021 10:56:28.384291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1792 RESULT=skip>
23022 10:56:28.384734 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1792 RESULT=skip
23024 10:56:28.427985 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1792 RESULT=skip
23026 10:56:28.428546 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1792 RESULT=skip>
23027 10:56:28.477305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1792 RESULT=skip>
23028 10:56:28.477693 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1792 RESULT=skip
23030 10:56:28.527953 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1808 RESULT=pass
23032 10:56:28.528393 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1808 RESULT=pass>
23033 10:56:28.566539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1808 RESULT=skip>
23034 10:56:28.566986 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1808 RESULT=skip
23036 10:56:28.610499 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1808 RESULT=skip
23038 10:56:28.610871 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1808 RESULT=skip>
23039 10:56:28.646383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1808 RESULT=skip>
23040 10:56:28.646786 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1808 RESULT=skip
23042 10:56:28.689039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1824 RESULT=pass>
23043 10:56:28.689437 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1824 RESULT=pass
23045 10:56:28.727626 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1824 RESULT=skip
23047 10:56:28.728069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1824 RESULT=skip>
23048 10:56:28.760422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1824 RESULT=skip>
23049 10:56:28.760826 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1824 RESULT=skip
23051 10:56:28.797502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1824 RESULT=skip>
23052 10:56:28.797920 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1824 RESULT=skip
23054 10:56:28.838664 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1840 RESULT=pass>
23055 10:56:28.839076 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1840 RESULT=pass
23057 10:56:28.882245 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1840 RESULT=skip>
23058 10:56:28.882652 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1840 RESULT=skip
23060 10:56:28.920690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1840 RESULT=skip>
23061 10:56:28.921084 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1840 RESULT=skip
23063 10:56:28.965417 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1840 RESULT=skip
23065 10:56:28.965853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1840 RESULT=skip>
23066 10:56:29.010121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1856 RESULT=pass>
23067 10:56:29.010520 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1856 RESULT=pass
23069 10:56:29.053858 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1856 RESULT=skip>
23070 10:56:29.054277 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1856 RESULT=skip
23072 10:56:29.099156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1856 RESULT=skip>
23073 10:56:29.099584 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1856 RESULT=skip
23075 10:56:29.131504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1856 RESULT=skip>
23076 10:56:29.131946 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1856 RESULT=skip
23078 10:56:29.166049 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1872 RESULT=pass>
23079 10:56:29.166456 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1872 RESULT=pass
23081 10:56:29.210057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1872 RESULT=skip>
23082 10:56:29.210464 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1872 RESULT=skip
23084 10:56:29.250423 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1872 RESULT=skip>
23085 10:56:29.250822 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1872 RESULT=skip
23087 10:56:29.294743 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1872 RESULT=skip>
23088 10:56:29.295106 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1872 RESULT=skip
23090 10:56:29.336845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1888 RESULT=pass>
23091 10:56:29.337197 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1888 RESULT=pass
23093 10:56:29.380928 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1888 RESULT=skip>
23094 10:56:29.381596 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1888 RESULT=skip
23096 10:56:29.424482 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1888 RESULT=skip>
23097 10:56:29.424864 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1888 RESULT=skip
23099 10:56:29.468341 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1888 RESULT=skip>
23100 10:56:29.468721 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1888 RESULT=skip
23102 10:56:29.510731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1904 RESULT=pass>
23103 10:56:29.511110 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1904 RESULT=pass
23105 10:56:29.553005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1904 RESULT=skip>
23106 10:56:29.553424 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1904 RESULT=skip
23108 10:56:29.599803 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1904 RESULT=skip
23110 10:56:29.600240 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1904 RESULT=skip>
23111 10:56:29.642958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1904 RESULT=skip>
23112 10:56:29.643378 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1904 RESULT=skip
23114 10:56:29.685943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1920 RESULT=pass>
23115 10:56:29.686328 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1920 RESULT=pass
23117 10:56:29.730047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1920 RESULT=skip>
23118 10:56:29.730411 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1920 RESULT=skip
23120 10:56:29.773354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1920 RESULT=skip>
23121 10:56:29.773752 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1920 RESULT=skip
23123 10:56:29.824548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1920 RESULT=skip>
23124 10:56:29.824951 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1920 RESULT=skip
23126 10:56:29.869028 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1936 RESULT=pass
23128 10:56:29.869459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1936 RESULT=pass>
23129 10:56:29.912677 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1936 RESULT=skip>
23130 10:56:29.913097 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1936 RESULT=skip
23132 10:56:29.956082 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1936 RESULT=skip
23134 10:56:29.956632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1936 RESULT=skip>
23135 10:56:29.999355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1936 RESULT=skip>
23136 10:56:29.999772 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1936 RESULT=skip
23138 10:56:30.042082 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1952 RESULT=pass>
23139 10:56:30.042494 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1952 RESULT=pass
23141 10:56:30.084835 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1952 RESULT=skip>
23142 10:56:30.085254 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1952 RESULT=skip
23144 10:56:30.128613 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1952 RESULT=skip>
23145 10:56:30.129031 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1952 RESULT=skip
23147 10:56:30.171777 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1952 RESULT=skip
23149 10:56:30.172248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1952 RESULT=skip>
23150 10:56:30.214456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1968 RESULT=pass>
23151 10:56:30.214856 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1968 RESULT=pass
23153 10:56:30.258246 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1968 RESULT=skip
23155 10:56:30.258695 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1968 RESULT=skip>
23156 10:56:30.301990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1968 RESULT=skip>
23157 10:56:30.302414 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1968 RESULT=skip
23159 10:56:30.346970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1968 RESULT=skip>
23160 10:56:30.347393 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1968 RESULT=skip
23162 10:56:30.390459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1984 RESULT=pass>
23163 10:56:30.390883 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1984 RESULT=pass
23165 10:56:30.434547 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1984 RESULT=skip>
23166 10:56:30.434946 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1984 RESULT=skip
23168 10:56:30.479088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1984 RESULT=skip>
23169 10:56:30.479510 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1984 RESULT=skip
23171 10:56:30.525629 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1984 RESULT=skip>
23172 10:56:30.526052 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1984 RESULT=skip
23174 10:56:30.569430 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2000 RESULT=pass
23176 10:56:30.569852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2000 RESULT=pass>
23177 10:56:30.612541 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2000 RESULT=skip>
23178 10:56:30.612963 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2000 RESULT=skip
23180 10:56:30.685844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2000 RESULT=skip>
23181 10:56:30.686286 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2000 RESULT=skip
23183 10:56:30.734785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2000 RESULT=skip>
23184 10:56:30.735177 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2000 RESULT=skip
23186 10:56:30.779107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2016 RESULT=pass>
23187 10:56:30.779487 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2016 RESULT=pass
23189 10:56:30.822277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2016 RESULT=skip>
23190 10:56:30.822697 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2016 RESULT=skip
23192 10:56:30.865721 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2016 RESULT=skip>
23193 10:56:30.866144 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2016 RESULT=skip
23195 10:56:30.909059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2016 RESULT=skip>
23196 10:56:30.909450 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2016 RESULT=skip
23198 10:56:30.952639 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2032 RESULT=pass
23200 10:56:30.953074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2032 RESULT=pass>
23201 10:56:30.994918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2032 RESULT=skip>
23202 10:56:30.995330 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2032 RESULT=skip
23204 10:56:31.038588 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2032 RESULT=skip>
23205 10:56:31.038982 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2032 RESULT=skip
23207 10:56:31.082236 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2032 RESULT=skip
23209 10:56:31.082649 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2032 RESULT=skip>
23210 10:56:31.123824 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2048 RESULT=pass
23212 10:56:31.124283 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2048 RESULT=pass>
23213 10:56:31.169013 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2048 RESULT=skip
23215 10:56:31.169465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2048 RESULT=skip>
23216 10:56:31.213637 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2048 RESULT=skip
23218 10:56:31.214091 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2048 RESULT=skip>
23219 10:56:31.257376 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2048 RESULT=skip>
23220 10:56:31.257762 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2048 RESULT=skip
23222 10:56:31.300910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2064 RESULT=pass>
23223 10:56:31.301282 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2064 RESULT=pass
23225 10:56:31.342947 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2064 RESULT=skip
23227 10:56:31.343417 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2064 RESULT=skip>
23228 10:56:31.385880 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2064 RESULT=skip>
23229 10:56:31.386311 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2064 RESULT=skip
23231 10:56:31.429400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2064 RESULT=skip>
23232 10:56:31.429833 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2064 RESULT=skip
23234 10:56:31.472562 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2080 RESULT=pass>
23235 10:56:31.472989 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2080 RESULT=pass
23237 10:56:31.515259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2080 RESULT=skip>
23238 10:56:31.515691 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2080 RESULT=skip
23240 10:56:31.559889 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2080 RESULT=skip
23242 10:56:31.560346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2080 RESULT=skip>
23243 10:56:31.603876 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2080 RESULT=skip
23245 10:56:31.604261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2080 RESULT=skip>
23246 10:56:31.646494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2096 RESULT=pass>
23247 10:56:31.646919 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2096 RESULT=pass
23249 10:56:31.689441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2096 RESULT=skip>
23250 10:56:31.689859 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2096 RESULT=skip
23252 10:56:31.731535 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2096 RESULT=skip>
23253 10:56:31.731930 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2096 RESULT=skip
23255 10:56:31.774364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2096 RESULT=skip>
23256 10:56:31.774766 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2096 RESULT=skip
23258 10:56:31.818845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2112 RESULT=pass>
23259 10:56:31.819236 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2112 RESULT=pass
23261 10:56:31.862418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2112 RESULT=skip>
23262 10:56:31.862784 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2112 RESULT=skip
23264 10:56:31.908554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2112 RESULT=skip>
23265 10:56:31.908906 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2112 RESULT=skip
23267 10:56:31.951342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2112 RESULT=skip>
23268 10:56:31.951735 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2112 RESULT=skip
23270 10:56:31.995429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2128 RESULT=pass>
23271 10:56:31.995834 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2128 RESULT=pass
23273 10:56:32.039216 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2128 RESULT=skip>
23274 10:56:32.039644 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2128 RESULT=skip
23276 10:56:32.082945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2128 RESULT=skip>
23277 10:56:32.083339 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2128 RESULT=skip
23279 10:56:32.129011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2128 RESULT=skip>
23280 10:56:32.129414 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2128 RESULT=skip
23282 10:56:32.174547 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2144 RESULT=pass>
23283 10:56:32.174971 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2144 RESULT=pass
23285 10:56:32.218223 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2144 RESULT=skip>
23286 10:56:32.218606 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2144 RESULT=skip
23288 10:56:32.261924 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2144 RESULT=skip>
23289 10:56:32.262342 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2144 RESULT=skip
23291 10:56:32.305298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2144 RESULT=skip>
23292 10:56:32.305689 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2144 RESULT=skip
23294 10:56:32.348814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2160 RESULT=pass>
23295 10:56:32.349256 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2160 RESULT=pass
23297 10:56:32.391434 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2160 RESULT=skip>
23298 10:56:32.391845 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2160 RESULT=skip
23300 10:56:32.435203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2160 RESULT=skip>
23301 10:56:32.435613 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2160 RESULT=skip
23303 10:56:32.479482 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2160 RESULT=skip>
23304 10:56:32.479899 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2160 RESULT=skip
23306 10:56:32.523211 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2176 RESULT=pass
23308 10:56:32.523660 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2176 RESULT=pass>
23309 10:56:32.565982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2176 RESULT=skip>
23310 10:56:32.566422 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2176 RESULT=skip
23312 10:56:32.609051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2176 RESULT=skip>
23313 10:56:32.609471 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2176 RESULT=skip
23315 10:56:32.653020 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2176 RESULT=skip>
23316 10:56:32.653453 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2176 RESULT=skip
23318 10:56:32.695269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2192 RESULT=pass>
23319 10:56:32.695670 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2192 RESULT=pass
23321 10:56:32.743397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2192 RESULT=skip>
23322 10:56:32.743816 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2192 RESULT=skip
23324 10:56:32.791489 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2192 RESULT=skip>
23325 10:56:32.791792 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2192 RESULT=skip
23327 10:56:32.838958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2192 RESULT=skip>
23328 10:56:32.839227 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2192 RESULT=skip
23330 10:56:32.886153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2208 RESULT=pass>
23331 10:56:32.886446 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2208 RESULT=pass
23333 10:56:32.934404 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2208 RESULT=skip
23335 10:56:32.934823 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2208 RESULT=skip>
23336 10:56:32.981838 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2208 RESULT=skip
23338 10:56:32.982305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2208 RESULT=skip>
23339 10:56:33.029892 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2208 RESULT=skip>
23340 10:56:33.030246 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2208 RESULT=skip
23342 10:56:33.077714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2224 RESULT=pass>
23343 10:56:33.078048 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2224 RESULT=pass
23345 10:56:33.125200 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2224 RESULT=skip>
23346 10:56:33.125479 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2224 RESULT=skip
23348 10:56:33.173846 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2224 RESULT=skip
23350 10:56:33.174292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2224 RESULT=skip>
23351 10:56:33.221953 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2224 RESULT=skip>
23352 10:56:33.222263 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2224 RESULT=skip
23354 10:56:33.269782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2240 RESULT=pass>
23355 10:56:33.270085 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2240 RESULT=pass
23357 10:56:33.317276 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2240 RESULT=skip>
23358 10:56:33.317579 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2240 RESULT=skip
23360 10:56:33.361318 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2240 RESULT=skip>
23361 10:56:33.361621 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2240 RESULT=skip
23363 10:56:33.409698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2240 RESULT=skip>
23364 10:56:33.410057 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2240 RESULT=skip
23366 10:56:33.459952 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2256 RESULT=pass
23368 10:56:33.460264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2256 RESULT=pass>
23369 10:56:33.502786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2256 RESULT=skip>
23370 10:56:33.503082 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2256 RESULT=skip
23372 10:56:33.550093 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2256 RESULT=skip
23374 10:56:33.550326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2256 RESULT=skip>
23375 10:56:33.602189 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2256 RESULT=skip
23377 10:56:33.602503 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2256 RESULT=skip>
23378 10:56:33.654790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2272 RESULT=pass>
23379 10:56:33.655106 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2272 RESULT=pass
23381 10:56:33.701256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2272 RESULT=skip>
23382 10:56:33.701548 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2272 RESULT=skip
23384 10:56:33.753961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2272 RESULT=skip>
23385 10:56:33.754265 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2272 RESULT=skip
23387 10:56:33.802005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2272 RESULT=skip>
23388 10:56:33.802297 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2272 RESULT=skip
23390 10:56:33.841341 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2288 RESULT=pass>
23391 10:56:33.841638 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2288 RESULT=pass
23393 10:56:33.886707 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2288 RESULT=skip
23395 10:56:33.887132 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2288 RESULT=skip>
23396 10:56:33.934803 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2288 RESULT=skip
23398 10:56:33.935114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2288 RESULT=skip>
23399 10:56:33.982544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2288 RESULT=skip>
23400 10:56:33.982848 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2288 RESULT=skip
23402 10:56:34.030082 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2304 RESULT=pass>
23403 10:56:34.030376 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2304 RESULT=pass
23405 10:56:34.078992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2304 RESULT=skip>
23406 10:56:34.079382 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2304 RESULT=skip
23408 10:56:34.123303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2304 RESULT=skip>
23409 10:56:34.123616 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2304 RESULT=skip
23411 10:56:34.175095 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2304 RESULT=skip>
23412 10:56:34.175480 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2304 RESULT=skip
23414 10:56:34.223311 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2320 RESULT=pass>
23415 10:56:34.223603 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2320 RESULT=pass
23417 10:56:34.271404 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2320 RESULT=skip
23419 10:56:34.271706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2320 RESULT=skip>
23420 10:56:34.319913 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2320 RESULT=skip
23422 10:56:34.320213 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2320 RESULT=skip>
23423 10:56:34.368987 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2320 RESULT=skip
23425 10:56:34.369280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2320 RESULT=skip>
23426 10:56:34.417390 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2336 RESULT=pass
23428 10:56:34.417690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2336 RESULT=pass>
23429 10:56:34.464717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2336 RESULT=skip>
23430 10:56:34.465010 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2336 RESULT=skip
23432 10:56:34.510952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2336 RESULT=skip>
23433 10:56:34.511272 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2336 RESULT=skip
23435 10:56:34.555862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2336 RESULT=skip>
23436 10:56:34.556162 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2336 RESULT=skip
23438 10:56:34.605674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2352 RESULT=pass>
23439 10:56:34.606109 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2352 RESULT=pass
23441 10:56:34.656426 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2352 RESULT=skip>
23442 10:56:34.656723 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2352 RESULT=skip
23444 10:56:34.705041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2352 RESULT=skip>
23445 10:56:34.705397 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2352 RESULT=skip
23447 10:56:34.740303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2352 RESULT=skip>
23448 10:56:34.740600 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2352 RESULT=skip
23450 10:56:34.782642 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2368 RESULT=pass>
23451 10:56:34.782939 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2368 RESULT=pass
23453 10:56:34.824158 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2368 RESULT=skip
23455 10:56:34.824556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2368 RESULT=skip>
23456 10:56:34.863990 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2368 RESULT=skip
23458 10:56:34.864442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2368 RESULT=skip>
23459 10:56:34.913089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2368 RESULT=skip>
23460 10:56:34.913521 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2368 RESULT=skip
23462 10:56:34.960683 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2384 RESULT=pass>
23463 10:56:34.961106 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2384 RESULT=pass
23465 10:56:35.009029 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2384 RESULT=skip>
23466 10:56:35.009381 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2384 RESULT=skip
23468 10:56:35.055729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2384 RESULT=skip>
23469 10:56:35.059111 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2384 RESULT=skip
23471 10:56:35.105687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2384 RESULT=skip>
23472 10:56:35.109678 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2384 RESULT=skip
23474 10:56:35.149673 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2400 RESULT=pass>
23475 10:56:35.151611 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2400 RESULT=pass
23477 10:56:35.193681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2400 RESULT=skip>
23478 10:56:35.194103 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2400 RESULT=skip
23480 10:56:35.237950 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2400 RESULT=skip
23482 10:56:35.238391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2400 RESULT=skip>
23483 10:56:35.286145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2400 RESULT=skip>
23484 10:56:35.286484 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2400 RESULT=skip
23486 10:56:35.322034 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2416 RESULT=pass
23488 10:56:35.322495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2416 RESULT=pass>
23489 10:56:35.368933 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2416 RESULT=skip
23491 10:56:35.369390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2416 RESULT=skip>
23492 10:56:35.407393 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2416 RESULT=skip>
23493 10:56:35.407815 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2416 RESULT=skip
23495 10:56:35.455259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2416 RESULT=skip>
23496 10:56:35.455692 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2416 RESULT=skip
23498 10:56:35.490097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2432 RESULT=pass>
23499 10:56:35.490463 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2432 RESULT=pass
23501 10:56:35.525574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2432 RESULT=skip>
23502 10:56:35.525976 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2432 RESULT=skip
23504 10:56:35.568943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2432 RESULT=skip>
23505 10:56:35.569375 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2432 RESULT=skip
23507 10:56:35.618259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2432 RESULT=skip>
23508 10:56:35.618681 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2432 RESULT=skip
23510 10:56:35.666069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2448 RESULT=pass>
23511 10:56:35.666487 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2448 RESULT=pass
23513 10:56:35.713494 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2448 RESULT=skip
23515 10:56:35.713994 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2448 RESULT=skip>
23516 10:56:35.770311 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2448 RESULT=skip>
23517 10:56:35.770733 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2448 RESULT=skip
23519 10:56:35.841366 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2448 RESULT=skip>
23520 10:56:35.841795 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2448 RESULT=skip
23522 10:56:35.889458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2464 RESULT=pass>
23523 10:56:35.889857 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2464 RESULT=pass
23525 10:56:35.927486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2464 RESULT=skip>
23526 10:56:35.927917 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2464 RESULT=skip
23528 10:56:35.966917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2464 RESULT=skip>
23529 10:56:35.967344 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2464 RESULT=skip
23531 10:56:36.015090 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2464 RESULT=skip>
23532 10:56:36.015481 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2464 RESULT=skip
23534 10:56:36.063030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2480 RESULT=pass>
23535 10:56:36.063457 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2480 RESULT=pass
23537 10:56:36.111480 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2480 RESULT=skip>
23538 10:56:36.111910 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2480 RESULT=skip
23540 10:56:36.160435 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2480 RESULT=skip
23542 10:56:36.160869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2480 RESULT=skip>
23543 10:56:36.209597 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2480 RESULT=skip
23545 10:56:36.210088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2480 RESULT=skip>
23546 10:56:36.258551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2496 RESULT=pass>
23547 10:56:36.258975 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2496 RESULT=pass
23549 10:56:36.306434 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2496 RESULT=skip>
23550 10:56:36.306866 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2496 RESULT=skip
23552 10:56:36.354519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2496 RESULT=skip>
23553 10:56:36.354951 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2496 RESULT=skip
23555 10:56:36.402324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2496 RESULT=skip>
23556 10:56:36.402748 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2496 RESULT=skip
23558 10:56:36.450192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2512 RESULT=pass>
23559 10:56:36.450540 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2512 RESULT=pass
23561 10:56:36.489793 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2512 RESULT=skip
23563 10:56:36.490274 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2512 RESULT=skip>
23564 10:56:36.539810 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2512 RESULT=skip
23566 10:56:36.540300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2512 RESULT=skip>
23567 10:56:36.584466 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2512 RESULT=skip
23569 10:56:36.584848 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2512 RESULT=skip>
23570 10:56:36.625976 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2528 RESULT=pass
23572 10:56:36.626375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2528 RESULT=pass>
23573 10:56:36.673308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2528 RESULT=skip>
23574 10:56:36.673688 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2528 RESULT=skip
23576 10:56:36.721800 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2528 RESULT=skip>
23577 10:56:36.722202 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2528 RESULT=skip
23579 10:56:36.765772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2528 RESULT=skip>
23580 10:56:36.766159 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2528 RESULT=skip
23582 10:56:36.801157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2544 RESULT=pass>
23583 10:56:36.801551 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2544 RESULT=pass
23585 10:56:36.849776 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2544 RESULT=skip
23587 10:56:36.850253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2544 RESULT=skip>
23588 10:56:36.898702 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2544 RESULT=skip>
23589 10:56:36.899121 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2544 RESULT=skip
23591 10:56:36.947251 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2544 RESULT=skip
23593 10:56:36.947711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2544 RESULT=skip>
23594 10:56:36.988898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2560 RESULT=pass>
23595 10:56:36.989333 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2560 RESULT=pass
23597 10:56:37.040155 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2560 RESULT=skip
23599 10:56:37.040652 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2560 RESULT=skip>
23600 10:56:37.093924 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2560 RESULT=skip
23602 10:56:37.094297 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2560 RESULT=skip>
23603 10:56:37.147440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2560 RESULT=skip>
23604 10:56:37.147756 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2560 RESULT=skip
23606 10:56:37.199525 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2576 RESULT=pass>
23607 10:56:37.199946 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2576 RESULT=pass
23609 10:56:37.251903 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2576 RESULT=skip
23611 10:56:37.252481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2576 RESULT=skip>
23612 10:56:37.305609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2576 RESULT=skip>
23613 10:56:37.306036 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2576 RESULT=skip
23615 10:56:37.358565 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2576 RESULT=skip
23617 10:56:37.359003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2576 RESULT=skip>
23618 10:56:37.411000 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2592 RESULT=pass>
23619 10:56:37.411418 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2592 RESULT=pass
23621 10:56:37.463425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2592 RESULT=skip>
23622 10:56:37.463843 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2592 RESULT=skip
23624 10:56:37.516805 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2592 RESULT=skip
23626 10:56:37.517251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2592 RESULT=skip>
23627 10:56:37.569688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2592 RESULT=skip>
23628 10:56:37.570111 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2592 RESULT=skip
23630 10:56:37.622967 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2608 RESULT=pass
23632 10:56:37.623428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2608 RESULT=pass>
23633 10:56:37.675798 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2608 RESULT=skip
23635 10:56:37.676267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2608 RESULT=skip>
23636 10:56:37.728917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2608 RESULT=skip>
23637 10:56:37.729278 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2608 RESULT=skip
23639 10:56:37.781585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2608 RESULT=skip>
23640 10:56:37.781995 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2608 RESULT=skip
23642 10:56:37.835767 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2624 RESULT=pass
23644 10:56:37.836221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2624 RESULT=pass>
23645 10:56:37.890159 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2624 RESULT=skip>
23646 10:56:37.890593 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2624 RESULT=skip
23648 10:56:37.943423 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2624 RESULT=skip>
23649 10:56:37.943709 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2624 RESULT=skip
23651 10:56:37.996394 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2624 RESULT=skip>
23652 10:56:37.996744 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2624 RESULT=skip
23654 10:56:38.048480 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2640 RESULT=pass>
23655 10:56:38.048839 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2640 RESULT=pass
23657 10:56:38.100499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2640 RESULT=skip>
23658 10:56:38.100897 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2640 RESULT=skip
23660 10:56:38.151904 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2640 RESULT=skip
23662 10:56:38.152316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2640 RESULT=skip>
23663 10:56:38.203818 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2640 RESULT=skip
23665 10:56:38.204253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2640 RESULT=skip>
23666 10:56:38.258230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2656 RESULT=pass>
23667 10:56:38.258550 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2656 RESULT=pass
23669 10:56:38.310830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2656 RESULT=skip>
23670 10:56:38.311238 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2656 RESULT=skip
23672 10:56:38.363763 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2656 RESULT=skip
23674 10:56:38.364332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2656 RESULT=skip>
23675 10:56:38.417444 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2656 RESULT=skip>
23676 10:56:38.417853 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2656 RESULT=skip
23678 10:56:38.469995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2672 RESULT=pass>
23679 10:56:38.470390 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2672 RESULT=pass
23681 10:56:38.523176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2672 RESULT=skip>
23682 10:56:38.523586 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2672 RESULT=skip
23684 10:56:38.578065 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2672 RESULT=skip
23686 10:56:38.578497 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2672 RESULT=skip>
23687 10:56:38.633693 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2672 RESULT=skip
23689 10:56:38.634668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2672 RESULT=skip>
23690 10:56:38.687887 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2688 RESULT=pass
23692 10:56:38.688333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2688 RESULT=pass>
23693 10:56:38.742110 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2688 RESULT=skip>
23694 10:56:38.742495 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2688 RESULT=skip
23696 10:56:38.795411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2688 RESULT=skip>
23697 10:56:38.795798 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2688 RESULT=skip
23699 10:56:38.850674 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2688 RESULT=skip
23701 10:56:38.851114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2688 RESULT=skip>
23702 10:56:38.903172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2704 RESULT=pass>
23703 10:56:38.903879 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2704 RESULT=pass
23705 10:56:38.957937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2704 RESULT=skip>
23706 10:56:38.958325 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2704 RESULT=skip
23708 10:56:39.011126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2704 RESULT=skip>
23709 10:56:39.011551 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2704 RESULT=skip
23711 10:56:39.064728 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2704 RESULT=skip
23713 10:56:39.065156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2704 RESULT=skip>
23714 10:56:39.115324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2720 RESULT=pass>
23715 10:56:39.115750 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2720 RESULT=pass
23717 10:56:39.161107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2720 RESULT=skip>
23718 10:56:39.161528 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2720 RESULT=skip
23720 10:56:39.209679 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2720 RESULT=skip
23722 10:56:39.210155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2720 RESULT=skip>
23723 10:56:39.258232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2720 RESULT=skip>
23724 10:56:39.258652 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2720 RESULT=skip
23726 10:56:39.298229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2736 RESULT=pass>
23727 10:56:39.298612 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2736 RESULT=pass
23729 10:56:39.340604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2736 RESULT=skip>
23730 10:56:39.340988 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2736 RESULT=skip
23732 10:56:39.381909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2736 RESULT=skip>
23733 10:56:39.382314 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2736 RESULT=skip
23735 10:56:39.427919 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2736 RESULT=skip
23737 10:56:39.428799 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2736 RESULT=skip>
23738 10:56:39.477871 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2752 RESULT=pass
23740 10:56:39.478324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2752 RESULT=pass>
23741 10:56:39.526232 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2752 RESULT=skip
23743 10:56:39.526682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2752 RESULT=skip>
23744 10:56:39.575622 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2752 RESULT=skip
23746 10:56:39.576073 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2752 RESULT=skip>
23747 10:56:39.613967 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2752 RESULT=skip>
23748 10:56:39.614388 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2752 RESULT=skip
23750 10:56:39.654040 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2768 RESULT=pass
23752 10:56:39.654507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2768 RESULT=pass>
23753 10:56:39.703345 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2768 RESULT=skip
23755 10:56:39.703796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2768 RESULT=skip>
23756 10:56:39.752934 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2768 RESULT=skip>
23757 10:56:39.753362 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2768 RESULT=skip
23759 10:56:39.791771 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2768 RESULT=skip
23761 10:56:39.792350 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2768 RESULT=skip>
23762 10:56:39.841686 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2784 RESULT=pass>
23763 10:56:39.842083 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2784 RESULT=pass
23765 10:56:39.890419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2784 RESULT=skip>
23766 10:56:39.890874 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2784 RESULT=skip
23768 10:56:39.931557 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2784 RESULT=skip
23770 10:56:39.932037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2784 RESULT=skip>
23771 10:56:39.978535 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2784 RESULT=skip>
23772 10:56:39.978954 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2784 RESULT=skip
23774 10:56:40.026724 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2800 RESULT=pass>
23775 10:56:40.027139 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2800 RESULT=pass
23777 10:56:40.062172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2800 RESULT=skip>
23778 10:56:40.062593 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2800 RESULT=skip
23780 10:56:40.117452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2800 RESULT=skip>
23781 10:56:40.121714 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2800 RESULT=skip
23783 10:56:40.173737 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2800 RESULT=skip>
23784 10:56:40.177724 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2800 RESULT=skip
23786 10:56:40.229726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2816 RESULT=pass>
23787 10:56:40.230157 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2816 RESULT=pass
23789 10:56:40.282067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2816 RESULT=skip>
23790 10:56:40.282467 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2816 RESULT=skip
23792 10:56:40.338770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2816 RESULT=skip>
23793 10:56:40.339153 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2816 RESULT=skip
23795 10:56:40.396814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2816 RESULT=skip>
23796 10:56:40.397196 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2816 RESULT=skip
23798 10:56:40.440678 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2832 RESULT=pass>
23799 10:56:40.441108 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2832 RESULT=pass
23801 10:56:40.487052 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2832 RESULT=skip
23803 10:56:40.487536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2832 RESULT=skip>
23804 10:56:40.530431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2832 RESULT=skip>
23805 10:56:40.530853 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2832 RESULT=skip
23807 10:56:40.573170 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2832 RESULT=skip>
23808 10:56:40.573587 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2832 RESULT=skip
23810 10:56:40.614270 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2848 RESULT=pass>
23811 10:56:40.614687 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2848 RESULT=pass
23813 10:56:40.661735 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2848 RESULT=skip>
23814 10:56:40.662179 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2848 RESULT=skip
23816 10:56:40.701556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2848 RESULT=skip>
23817 10:56:40.701995 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2848 RESULT=skip
23819 10:56:40.745669 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2848 RESULT=skip>
23820 10:56:40.746096 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2848 RESULT=skip
23822 10:56:40.785536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2864 RESULT=pass>
23823 10:56:40.785974 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2864 RESULT=pass
23825 10:56:40.827382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2864 RESULT=skip>
23826 10:56:40.827830 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2864 RESULT=skip
23828 10:56:40.884790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2864 RESULT=skip>
23829 10:56:40.885237 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2864 RESULT=skip
23831 10:56:40.955977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2864 RESULT=skip>
23832 10:56:40.956418 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2864 RESULT=skip
23834 10:56:41.007298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2880 RESULT=pass>
23835 10:56:41.007703 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2880 RESULT=pass
23837 10:56:41.055427 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2880 RESULT=skip
23839 10:56:41.055849 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2880 RESULT=skip>
23840 10:56:41.100267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2880 RESULT=skip>
23841 10:56:41.100675 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2880 RESULT=skip
23843 10:56:41.148526 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2880 RESULT=skip>
23844 10:56:41.148959 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2880 RESULT=skip
23846 10:56:41.198739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2896 RESULT=pass>
23847 10:56:41.199187 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2896 RESULT=pass
23849 10:56:41.250145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2896 RESULT=skip>
23850 10:56:41.250600 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2896 RESULT=skip
23852 10:56:41.301559 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2896 RESULT=skip>
23853 10:56:41.302027 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2896 RESULT=skip
23855 10:56:41.350169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2896 RESULT=skip>
23856 10:56:41.350621 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2896 RESULT=skip
23858 10:56:41.399509 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2912 RESULT=pass
23860 10:56:41.399990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2912 RESULT=pass>
23861 10:56:41.447936 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2912 RESULT=skip
23863 10:56:41.448576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2912 RESULT=skip>
23864 10:56:41.498093 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2912 RESULT=skip>
23865 10:56:41.498854 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2912 RESULT=skip
23867 10:56:41.544609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2912 RESULT=skip>
23868 10:56:41.545061 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2912 RESULT=skip
23870 10:56:41.593106 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2928 RESULT=pass
23872 10:56:41.593587 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2928 RESULT=pass>
23873 10:56:41.642367 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2928 RESULT=skip>
23874 10:56:41.642793 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2928 RESULT=skip
23876 10:56:41.695376 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2928 RESULT=skip>
23877 10:56:41.695800 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2928 RESULT=skip
23879 10:56:41.746185 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2928 RESULT=skip
23881 10:56:41.746668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2928 RESULT=skip>
23882 10:56:41.790711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2944 RESULT=pass>
23883 10:56:41.791161 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2944 RESULT=pass
23885 10:56:41.842221 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2944 RESULT=skip
23887 10:56:41.842702 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2944 RESULT=skip>
23888 10:56:41.882526 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2944 RESULT=skip>
23889 10:56:41.882962 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2944 RESULT=skip
23891 10:56:41.935705 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2944 RESULT=skip
23893 10:56:41.936167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2944 RESULT=skip>
23894 10:56:41.984554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2960 RESULT=pass>
23895 10:56:41.984971 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2960 RESULT=pass
23897 10:56:42.029602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2960 RESULT=skip>
23898 10:56:42.030040 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2960 RESULT=skip
23900 10:56:42.073564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2960 RESULT=skip>
23901 10:56:42.073873 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2960 RESULT=skip
23903 10:56:42.118887 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2960 RESULT=skip
23905 10:56:42.121741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2960 RESULT=skip>
23906 10:56:42.166023 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2976 RESULT=pass
23908 10:56:42.166481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2976 RESULT=pass>
23909 10:56:42.219373 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2976 RESULT=skip>
23910 10:56:42.223339 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2976 RESULT=skip
23912 10:56:42.273742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2976 RESULT=skip>
23913 10:56:42.277745 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2976 RESULT=skip
23915 10:56:42.329750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2976 RESULT=skip>
23916 10:56:42.330175 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2976 RESULT=skip
23918 10:56:42.384940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2992 RESULT=pass>
23919 10:56:42.385388 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2992 RESULT=pass
23921 10:56:42.445053 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2992 RESULT=skip
23923 10:56:42.445520 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2992 RESULT=skip>
23924 10:56:42.505567 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2992 RESULT=skip
23926 10:56:42.506050 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2992 RESULT=skip>
23927 10:56:42.553950 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2992 RESULT=skip>
23928 10:56:42.554353 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2992 RESULT=skip
23930 10:56:42.602910 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3008 RESULT=pass
23932 10:56:42.603358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3008 RESULT=pass>
23933 10:56:42.651663 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3008 RESULT=skip>
23934 10:56:42.652084 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3008 RESULT=skip
23936 10:56:42.700568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3008 RESULT=skip>
23937 10:56:42.701010 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3008 RESULT=skip
23939 10:56:42.749001 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3008 RESULT=skip>
23940 10:56:42.749394 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3008 RESULT=skip
23942 10:56:42.796883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3024 RESULT=pass>
23943 10:56:42.797300 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3024 RESULT=pass
23945 10:56:42.834484 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3024 RESULT=skip>
23946 10:56:42.834914 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3024 RESULT=skip
23948 10:56:42.882329 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3024 RESULT=skip
23950 10:56:42.882806 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3024 RESULT=skip>
23951 10:56:42.930075 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3024 RESULT=skip
23953 10:56:42.930498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3024 RESULT=skip>
23954 10:56:42.983310 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3040 RESULT=pass>
23955 10:56:42.987342 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3040 RESULT=pass
23957 10:56:43.039849 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3040 RESULT=skip
23959 10:56:43.040343 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3040 RESULT=skip>
23960 10:56:43.097521 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3040 RESULT=skip>
23961 10:56:43.097904 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3040 RESULT=skip
23963 10:56:43.154399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3040 RESULT=skip>
23964 10:56:43.154814 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3040 RESULT=skip
23966 10:56:43.211332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3056 RESULT=pass>
23967 10:56:43.211765 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3056 RESULT=pass
23969 10:56:43.270178 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3056 RESULT=skip
23971 10:56:43.270582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3056 RESULT=skip>
23972 10:56:43.330931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3056 RESULT=skip>
23973 10:56:43.331348 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3056 RESULT=skip
23975 10:56:43.390217 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3056 RESULT=skip>
23976 10:56:43.390603 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3056 RESULT=skip
23978 10:56:43.449316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3072 RESULT=pass>
23979 10:56:43.449692 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3072 RESULT=pass
23981 10:56:43.508753 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3072 RESULT=skip>
23982 10:56:43.509149 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3072 RESULT=skip
23984 10:56:43.569937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3072 RESULT=skip>
23985 10:56:43.570366 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3072 RESULT=skip
23987 10:56:43.632080 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3072 RESULT=skip
23989 10:56:43.632477 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3072 RESULT=skip>
23990 10:56:43.690480 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3088 RESULT=pass
23992 10:56:43.690928 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3088 RESULT=pass>
23993 10:56:43.753126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3088 RESULT=skip>
23994 10:56:43.753538 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3088 RESULT=skip
23996 10:56:43.810524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3088 RESULT=skip>
23997 10:56:43.810949 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3088 RESULT=skip
23999 10:56:43.870339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3088 RESULT=skip>
24000 10:56:43.870764 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3088 RESULT=skip
24002 10:56:43.929919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3104 RESULT=pass>
24003 10:56:43.930313 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3104 RESULT=pass
24005 10:56:43.988886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3104 RESULT=skip>
24006 10:56:43.989289 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3104 RESULT=skip
24008 10:56:44.046315 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3104 RESULT=skip>
24009 10:56:44.046678 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3104 RESULT=skip
24011 10:56:44.103570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3104 RESULT=skip>
24012 10:56:44.103988 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3104 RESULT=skip
24014 10:56:44.161864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3120 RESULT=pass>
24015 10:56:44.162286 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3120 RESULT=pass
24017 10:56:44.221620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3120 RESULT=skip>
24018 10:56:44.222052 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3120 RESULT=skip
24020 10:56:44.279355 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3120 RESULT=skip
24022 10:56:44.279824 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3120 RESULT=skip>
24023 10:56:44.337513 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3120 RESULT=skip>
24024 10:56:44.337939 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3120 RESULT=skip
24026 10:56:44.397238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3136 RESULT=pass>
24027 10:56:44.397669 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3136 RESULT=pass
24029 10:56:44.454457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3136 RESULT=skip>
24030 10:56:44.454842 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3136 RESULT=skip
24032 10:56:44.512893 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3136 RESULT=skip
24034 10:56:44.513298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3136 RESULT=skip>
24035 10:56:44.570693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3136 RESULT=skip>
24036 10:56:44.571117 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3136 RESULT=skip
24038 10:56:44.629726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3152 RESULT=pass>
24039 10:56:44.630122 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3152 RESULT=pass
24041 10:56:44.688636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3152 RESULT=skip>
24042 10:56:44.689070 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3152 RESULT=skip
24044 10:56:44.748121 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3152 RESULT=skip
24046 10:56:44.748518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3152 RESULT=skip>
24047 10:56:44.808961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3152 RESULT=skip>
24048 10:56:44.809313 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3152 RESULT=skip
24050 10:56:44.867612 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3168 RESULT=pass
24052 10:56:44.868047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3168 RESULT=pass>
24053 10:56:44.926031 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3168 RESULT=skip
24055 10:56:44.926456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3168 RESULT=skip>
24056 10:56:44.980808 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3168 RESULT=skip>
24057 10:56:44.981096 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3168 RESULT=skip
24059 10:56:45.038229 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3168 RESULT=skip
24061 10:56:45.038534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3168 RESULT=skip>
24062 10:56:45.094261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3184 RESULT=pass>
24063 10:56:45.094643 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3184 RESULT=pass
24065 10:56:45.150790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3184 RESULT=skip>
24066 10:56:45.151087 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3184 RESULT=skip
24068 10:56:45.207823 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3184 RESULT=skip
24070 10:56:45.208278 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3184 RESULT=skip>
24071 10:56:45.265713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3184 RESULT=skip>
24072 10:56:45.266146 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3184 RESULT=skip
24074 10:56:45.313722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3200 RESULT=pass>
24075 10:56:45.314112 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3200 RESULT=pass
24077 10:56:45.364835 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3200 RESULT=skip>
24078 10:56:45.365130 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3200 RESULT=skip
24080 10:56:45.414429 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3200 RESULT=skip
24082 10:56:45.414681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3200 RESULT=skip>
24083 10:56:45.467749 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3200 RESULT=skip
24085 10:56:45.468901 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3200 RESULT=skip>
24086 10:56:45.514399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3216 RESULT=pass>
24087 10:56:45.514724 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3216 RESULT=pass
24089 10:56:45.567183 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3216 RESULT=skip>
24090 10:56:45.567601 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3216 RESULT=skip
24092 10:56:45.625173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3216 RESULT=skip>
24093 10:56:45.625503 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3216 RESULT=skip
24095 10:56:45.674950 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3216 RESULT=skip>
24096 10:56:45.675445 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3216 RESULT=skip
24098 10:56:45.725623 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3232 RESULT=pass>
24099 10:56:45.726058 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3232 RESULT=pass
24101 10:56:45.770328 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3232 RESULT=skip
24103 10:56:45.770777 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3232 RESULT=skip>
24104 10:56:45.827207 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3232 RESULT=skip>
24105 10:56:45.827517 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3232 RESULT=skip
24107 10:56:45.883622 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3232 RESULT=skip
24109 10:56:45.883927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3232 RESULT=skip>
24110 10:56:45.941500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3248 RESULT=pass>
24111 10:56:45.941796 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3248 RESULT=pass
24113 10:56:46.002765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3248 RESULT=skip>
24114 10:56:46.003194 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3248 RESULT=skip
24116 10:56:46.090875 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3248 RESULT=skip>
24117 10:56:46.091278 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3248 RESULT=skip
24119 10:56:46.150057 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3248 RESULT=skip
24121 10:56:46.150430 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3248 RESULT=skip>
24122 10:56:46.209352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3264 RESULT=pass>
24123 10:56:46.209685 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3264 RESULT=pass
24125 10:56:46.256930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3264 RESULT=skip>
24126 10:56:46.257257 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3264 RESULT=skip
24128 10:56:46.301162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3264 RESULT=skip>
24129 10:56:46.301552 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3264 RESULT=skip
24131 10:56:46.337207 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3264 RESULT=skip>
24132 10:56:46.337509 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3264 RESULT=skip
24134 10:56:46.392543 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3280 RESULT=pass>
24135 10:56:46.392854 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3280 RESULT=pass
24137 10:56:46.450072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3280 RESULT=skip>
24138 10:56:46.450376 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3280 RESULT=skip
24140 10:56:46.500209 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3280 RESULT=skip
24142 10:56:46.500635 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3280 RESULT=skip>
24143 10:56:46.550108 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3280 RESULT=skip
24145 10:56:46.550568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3280 RESULT=skip>
24146 10:56:46.599402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3296 RESULT=pass>
24147 10:56:46.599811 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3296 RESULT=pass
24149 10:56:46.641488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3296 RESULT=skip>
24150 10:56:46.641930 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3296 RESULT=skip
24152 10:56:46.686487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3296 RESULT=skip>
24153 10:56:46.686919 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3296 RESULT=skip
24155 10:56:46.734977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3296 RESULT=skip>
24156 10:56:46.735410 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3296 RESULT=skip
24158 10:56:46.783521 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3312 RESULT=pass>
24159 10:56:46.783962 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3312 RESULT=pass
24161 10:56:46.832454 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3312 RESULT=skip>
24162 10:56:46.832842 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3312 RESULT=skip
24164 10:56:46.877003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3312 RESULT=skip>
24165 10:56:46.877418 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3312 RESULT=skip
24167 10:56:46.922811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3312 RESULT=skip>
24168 10:56:46.923237 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3312 RESULT=skip
24170 10:56:46.969941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3328 RESULT=pass>
24171 10:56:46.970378 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3328 RESULT=pass
24173 10:56:47.017268 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3328 RESULT=skip>
24174 10:56:47.017670 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3328 RESULT=skip
24176 10:56:47.063891 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3328 RESULT=skip
24178 10:56:47.064492 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3328 RESULT=skip>
24179 10:56:47.113767 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3328 RESULT=skip>
24180 10:56:47.114178 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3328 RESULT=skip
24182 10:56:47.149905 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3344 RESULT=pass>
24183 10:56:47.150342 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3344 RESULT=pass
24185 10:56:47.185955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3344 RESULT=skip>
24186 10:56:47.186384 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3344 RESULT=skip
24188 10:56:47.221761 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3344 RESULT=skip>
24189 10:56:47.222145 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3344 RESULT=skip
24191 10:56:47.257744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3344 RESULT=skip>
24192 10:56:47.258185 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3344 RESULT=skip
24194 10:56:47.294097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3360 RESULT=pass>
24195 10:56:47.294519 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3360 RESULT=pass
24197 10:56:47.337258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3360 RESULT=skip>
24198 10:56:47.337665 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3360 RESULT=skip
24200 10:56:47.381090 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3360 RESULT=skip>
24201 10:56:47.381525 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3360 RESULT=skip
24203 10:56:47.427105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3360 RESULT=skip>
24204 10:56:47.427572 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3360 RESULT=skip
24206 10:56:47.479172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3376 RESULT=pass>
24207 10:56:47.479603 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3376 RESULT=pass
24209 10:56:47.518751 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3376 RESULT=skip>
24210 10:56:47.519189 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3376 RESULT=skip
24212 10:56:47.557383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3376 RESULT=skip>
24213 10:56:47.557798 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3376 RESULT=skip
24215 10:56:47.598551 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3376 RESULT=skip
24217 10:56:47.598989 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3376 RESULT=skip>
24218 10:56:47.645175 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3392 RESULT=pass>
24219 10:56:47.645601 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3392 RESULT=pass
24221 10:56:47.691712 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3392 RESULT=skip
24223 10:56:47.692376 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3392 RESULT=skip>
24224 10:56:47.730883 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3392 RESULT=skip
24226 10:56:47.731332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3392 RESULT=skip>
24227 10:56:47.774731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3392 RESULT=skip>
24228 10:56:47.775163 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3392 RESULT=skip
24230 10:56:47.812846 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3408 RESULT=pass>
24231 10:56:47.813260 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3408 RESULT=pass
24233 10:56:47.858376 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3408 RESULT=skip
24235 10:56:47.858836 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3408 RESULT=skip>
24236 10:56:47.895574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3408 RESULT=skip>
24237 10:56:47.896034 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3408 RESULT=skip
24239 10:56:47.938469 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3408 RESULT=skip
24241 10:56:47.938936 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3408 RESULT=skip>
24242 10:56:47.986462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3424 RESULT=pass>
24243 10:56:47.986901 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3424 RESULT=pass
24245 10:56:48.029556 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3424 RESULT=skip
24247 10:56:48.031558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3424 RESULT=skip>
24248 10:56:48.079443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3424 RESULT=skip>
24249 10:56:48.079881 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3424 RESULT=skip
24251 10:56:48.128688 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3424 RESULT=skip
24253 10:56:48.129164 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3424 RESULT=skip>
24254 10:56:48.168469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3440 RESULT=pass>
24255 10:56:48.168918 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3440 RESULT=pass
24257 10:56:48.217924 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3440 RESULT=skip
24259 10:56:48.218384 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3440 RESULT=skip>
24260 10:56:48.269095 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3440 RESULT=skip>
24261 10:56:48.269518 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3440 RESULT=skip
24263 10:56:48.318641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3440 RESULT=skip>
24264 10:56:48.319074 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3440 RESULT=skip
24266 10:56:48.370150 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3456 RESULT=pass>
24267 10:56:48.370585 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3456 RESULT=pass
24269 10:56:48.419251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3456 RESULT=skip>
24270 10:56:48.419684 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3456 RESULT=skip
24272 10:56:48.467694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3456 RESULT=skip>
24273 10:56:48.468126 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3456 RESULT=skip
24275 10:56:48.511532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3456 RESULT=skip>
24276 10:56:48.511942 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3456 RESULT=skip
24278 10:56:48.566446 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3472 RESULT=pass>
24279 10:56:48.566884 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3472 RESULT=pass
24281 10:56:48.626580 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3472 RESULT=skip>
24282 10:56:48.626999 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3472 RESULT=skip
24284 10:56:48.673685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3472 RESULT=skip>
24285 10:56:48.674140 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3472 RESULT=skip
24287 10:56:48.738338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3472 RESULT=skip>
24288 10:56:48.738841 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3472 RESULT=skip
24290 10:56:48.793800 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3488 RESULT=pass>
24291 10:56:48.794285 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3488 RESULT=pass
24293 10:56:48.841436 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3488 RESULT=skip>
24294 10:56:48.841851 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3488 RESULT=skip
24296 10:56:48.881204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3488 RESULT=skip>
24297 10:56:48.881630 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3488 RESULT=skip
24299 10:56:48.923950 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3488 RESULT=skip
24301 10:56:48.924414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3488 RESULT=skip>
24302 10:56:48.974799 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3504 RESULT=pass>
24303 10:56:48.975222 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3504 RESULT=pass
24305 10:56:49.025825 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3504 RESULT=skip
24307 10:56:49.026283 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3504 RESULT=skip>
24308 10:56:49.071034 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3504 RESULT=skip
24310 10:56:49.071476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3504 RESULT=skip>
24311 10:56:49.121514 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3504 RESULT=skip
24313 10:56:49.121984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3504 RESULT=skip>
24314 10:56:49.168662 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3520 RESULT=pass>
24315 10:56:49.169090 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3520 RESULT=pass
24317 10:56:49.217742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3520 RESULT=skip>
24318 10:56:49.218203 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3520 RESULT=skip
24320 10:56:49.267941 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3520 RESULT=skip
24322 10:56:49.268406 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3520 RESULT=skip>
24323 10:56:49.318997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3520 RESULT=skip>
24324 10:56:49.319457 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3520 RESULT=skip
24326 10:56:49.368675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3536 RESULT=pass>
24327 10:56:49.369097 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3536 RESULT=pass
24329 10:56:49.417812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3536 RESULT=skip>
24330 10:56:49.418267 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3536 RESULT=skip
24332 10:56:49.465930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3536 RESULT=skip>
24333 10:56:49.466370 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3536 RESULT=skip
24335 10:56:49.517023 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3536 RESULT=skip
24337 10:56:49.517493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3536 RESULT=skip>
24338 10:56:49.567215 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3552 RESULT=pass>
24339 10:56:49.567657 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3552 RESULT=pass
24341 10:56:49.617780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3552 RESULT=skip>
24342 10:56:49.618215 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3552 RESULT=skip
24344 10:56:49.669570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3552 RESULT=skip>
24345 10:56:49.670014 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3552 RESULT=skip
24347 10:56:49.721710 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3552 RESULT=skip>
24348 10:56:49.722101 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3552 RESULT=skip
24350 10:56:49.773199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3568 RESULT=pass>
24351 10:56:49.773584 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3568 RESULT=pass
24353 10:56:49.820891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3568 RESULT=skip>
24354 10:56:49.821290 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3568 RESULT=skip
24356 10:56:49.870745 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3568 RESULT=skip>
24357 10:56:49.871191 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3568 RESULT=skip
24359 10:56:49.920660 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3568 RESULT=skip>
24360 10:56:49.921089 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3568 RESULT=skip
24362 10:56:49.969983 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3584 RESULT=pass
24364 10:56:49.970448 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3584 RESULT=pass>
24365 10:56:50.018343 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3584 RESULT=skip
24367 10:56:50.018804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3584 RESULT=skip>
24368 10:56:50.069402 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3584 RESULT=skip
24370 10:56:50.069870 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3584 RESULT=skip>
24371 10:56:50.121750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3584 RESULT=skip>
24372 10:56:50.122173 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3584 RESULT=skip
24374 10:56:50.172592 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3600 RESULT=pass
24376 10:56:50.173068 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3600 RESULT=pass>
24377 10:56:50.222890 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3600 RESULT=skip>
24378 10:56:50.223330 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3600 RESULT=skip
24380 10:56:50.270124 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3600 RESULT=skip>
24381 10:56:50.270501 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3600 RESULT=skip
24383 10:56:50.313986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3600 RESULT=skip>
24384 10:56:50.314431 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3600 RESULT=skip
24386 10:56:50.361726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3616 RESULT=pass>
24387 10:56:50.362143 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3616 RESULT=pass
24389 10:56:50.403601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3616 RESULT=skip>
24390 10:56:50.404063 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3616 RESULT=skip
24392 10:56:50.443184 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3616 RESULT=skip
24394 10:56:50.443673 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3616 RESULT=skip>
24395 10:56:50.482896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3616 RESULT=skip>
24396 10:56:50.483325 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3616 RESULT=skip
24398 10:56:50.534845 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3632 RESULT=pass
24400 10:56:50.535320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3632 RESULT=pass>
24401 10:56:50.578455 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3632 RESULT=skip
24403 10:56:50.578930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3632 RESULT=skip>
24404 10:56:50.614830 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3632 RESULT=skip
24406 10:56:50.615301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3632 RESULT=skip>
24407 10:56:50.658603 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3632 RESULT=skip>
24408 10:56:50.659033 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3632 RESULT=skip
24410 10:56:50.707209 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3648 RESULT=pass
24412 10:56:50.707667 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3648 RESULT=pass>
24413 10:56:50.758745 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3648 RESULT=skip>
24414 10:56:50.759138 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3648 RESULT=skip
24416 10:56:50.810051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3648 RESULT=skip>
24417 10:56:50.810452 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3648 RESULT=skip
24419 10:56:50.856945 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3648 RESULT=skip
24421 10:56:50.857412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3648 RESULT=skip>
24422 10:56:50.905553 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3664 RESULT=pass>
24423 10:56:50.905998 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3664 RESULT=pass
24425 10:56:50.945643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3664 RESULT=skip>
24426 10:56:50.946064 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3664 RESULT=skip
24428 10:56:50.989826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3664 RESULT=skip>
24429 10:56:50.990261 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3664 RESULT=skip
24431 10:56:51.039143 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3664 RESULT=skip>
24432 10:56:51.039587 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3664 RESULT=skip
24434 10:56:51.090881 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3680 RESULT=pass
24436 10:56:51.091347 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3680 RESULT=pass>
24437 10:56:51.166901 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3680 RESULT=skip>
24438 10:56:51.167292 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3680 RESULT=skip
24440 10:56:51.216474 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3680 RESULT=skip>
24441 10:56:51.216866 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3680 RESULT=skip
24443 10:56:51.267565 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3680 RESULT=skip>
24444 10:56:51.267970 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3680 RESULT=skip
24446 10:56:51.316573 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3696 RESULT=pass
24448 10:56:51.317002 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3696 RESULT=pass>
24449 10:56:51.366038 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3696 RESULT=skip
24451 10:56:51.366471 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3696 RESULT=skip>
24452 10:56:51.413227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3696 RESULT=skip>
24453 10:56:51.413619 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3696 RESULT=skip
24455 10:56:51.453885 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3696 RESULT=skip
24457 10:56:51.454307 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3696 RESULT=skip>
24458 10:56:51.502990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3712 RESULT=pass>
24459 10:56:51.503397 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3712 RESULT=pass
24461 10:56:51.549988 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3712 RESULT=skip>
24462 10:56:51.550399 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3712 RESULT=skip
24464 10:56:51.595211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3712 RESULT=skip>
24465 10:56:51.595609 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3712 RESULT=skip
24467 10:56:51.645442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3712 RESULT=skip>
24468 10:56:51.645842 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3712 RESULT=skip
24470 10:56:51.694361 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3728 RESULT=pass
24472 10:56:51.694824 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3728 RESULT=pass>
24473 10:56:51.743952 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3728 RESULT=skip
24475 10:56:51.744387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3728 RESULT=skip>
24476 10:56:51.791058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3728 RESULT=skip>
24477 10:56:51.791483 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3728 RESULT=skip
24479 10:56:51.834623 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3728 RESULT=skip>
24480 10:56:51.835046 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3728 RESULT=skip
24482 10:56:51.885230 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3744 RESULT=pass
24484 10:56:51.885705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3744 RESULT=pass>
24485 10:56:51.929731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3744 RESULT=skip>
24486 10:56:51.930121 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3744 RESULT=skip
24488 10:56:51.978160 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3744 RESULT=skip>
24489 10:56:51.978584 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3744 RESULT=skip
24491 10:56:52.019904 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3744 RESULT=skip
24493 10:56:52.020378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3744 RESULT=skip>
24494 10:56:52.061680 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3760 RESULT=pass
24496 10:56:52.062145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3760 RESULT=pass>
24497 10:56:52.104955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3760 RESULT=skip>
24498 10:56:52.105377 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3760 RESULT=skip
24500 10:56:52.147177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3760 RESULT=skip>
24501 10:56:52.147608 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3760 RESULT=skip
24503 10:56:52.197071 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3760 RESULT=skip>
24504 10:56:52.197496 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3760 RESULT=skip
24506 10:56:52.246623 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3776 RESULT=pass>
24507 10:56:52.247049 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3776 RESULT=pass
24509 10:56:52.296573 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3776 RESULT=skip>
24510 10:56:52.297004 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3776 RESULT=skip
24512 10:56:52.337720 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3776 RESULT=skip>
24513 10:56:52.338146 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3776 RESULT=skip
24515 10:56:52.386231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3776 RESULT=skip>
24516 10:56:52.386648 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3776 RESULT=skip
24518 10:56:52.437159 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3792 RESULT=pass>
24519 10:56:52.437585 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3792 RESULT=pass
24521 10:56:52.486674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3792 RESULT=skip>
24522 10:56:52.487077 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3792 RESULT=skip
24524 10:56:52.531942 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3792 RESULT=skip
24526 10:56:52.532404 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3792 RESULT=skip>
24527 10:56:52.582297 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3792 RESULT=skip>
24528 10:56:52.582659 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3792 RESULT=skip
24530 10:56:52.633128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3808 RESULT=pass>
24531 10:56:52.633511 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3808 RESULT=pass
24533 10:56:52.681133 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3808 RESULT=skip>
24534 10:56:52.681511 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3808 RESULT=skip
24536 10:56:52.723319 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3808 RESULT=skip>
24537 10:56:52.723648 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3808 RESULT=skip
24539 10:56:52.771983 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3808 RESULT=skip
24541 10:56:52.772426 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3808 RESULT=skip>
24542 10:56:52.818232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3824 RESULT=pass>
24543 10:56:52.818666 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3824 RESULT=pass
24545 10:56:52.869506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3824 RESULT=skip>
24546 10:56:52.869975 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3824 RESULT=skip
24548 10:56:52.918362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3824 RESULT=skip>
24549 10:56:52.918777 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3824 RESULT=skip
24551 10:56:52.965421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3824 RESULT=skip>
24552 10:56:52.965835 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3824 RESULT=skip
24554 10:56:53.013718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3840 RESULT=pass>
24555 10:56:53.014137 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3840 RESULT=pass
24557 10:56:53.057934 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3840 RESULT=skip>
24558 10:56:53.058359 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3840 RESULT=skip
24560 10:56:53.103468 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3840 RESULT=skip
24562 10:56:53.103809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3840 RESULT=skip>
24563 10:56:53.150568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3840 RESULT=skip>
24564 10:56:53.150982 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3840 RESULT=skip
24566 10:56:53.197507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3856 RESULT=pass>
24567 10:56:53.197938 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3856 RESULT=pass
24569 10:56:53.246457 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3856 RESULT=skip
24571 10:56:53.246895 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3856 RESULT=skip>
24572 10:56:53.290310 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3856 RESULT=skip>
24573 10:56:53.290727 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3856 RESULT=skip
24575 10:56:53.341302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3856 RESULT=skip>
24576 10:56:53.341691 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3856 RESULT=skip
24578 10:56:53.391269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3872 RESULT=pass>
24579 10:56:53.391696 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3872 RESULT=pass
24581 10:56:53.427556 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3872 RESULT=skip
24583 10:56:53.428031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3872 RESULT=skip>
24584 10:56:53.474978 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3872 RESULT=skip
24586 10:56:53.475440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3872 RESULT=skip>
24587 10:56:53.511078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3872 RESULT=skip>
24588 10:56:53.511525 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3872 RESULT=skip
24590 10:56:53.555412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3888 RESULT=pass>
24591 10:56:53.555852 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3888 RESULT=pass
24593 10:56:53.603911 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3888 RESULT=skip
24595 10:56:53.604353 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3888 RESULT=skip>
24596 10:56:53.651161 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3888 RESULT=skip>
24597 10:56:53.651581 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3888 RESULT=skip
24599 10:56:53.689879 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3888 RESULT=skip>
24600 10:56:53.690310 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3888 RESULT=skip
24602 10:56:53.735172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3904 RESULT=pass>
24603 10:56:53.735613 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3904 RESULT=pass
24605 10:56:53.785933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3904 RESULT=skip>
24606 10:56:53.786361 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3904 RESULT=skip
24608 10:56:53.833975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3904 RESULT=skip>
24609 10:56:53.834396 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3904 RESULT=skip
24611 10:56:53.883043 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3904 RESULT=skip
24613 10:56:53.883479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3904 RESULT=skip>
24614 10:56:53.930842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3920 RESULT=pass>
24615 10:56:53.931298 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3920 RESULT=pass
24617 10:56:53.979165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3920 RESULT=skip>
24618 10:56:53.979587 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3920 RESULT=skip
24620 10:56:54.015393 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3920 RESULT=skip>
24621 10:56:54.015811 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3920 RESULT=skip
24623 10:56:54.052006 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3920 RESULT=skip
24625 10:56:54.052466 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3920 RESULT=skip>
24626 10:56:54.100927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3936 RESULT=pass>
24627 10:56:54.101342 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3936 RESULT=pass
24629 10:56:54.148757 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3936 RESULT=skip
24631 10:56:54.149202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3936 RESULT=skip>
24632 10:56:54.199363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3936 RESULT=skip>
24633 10:56:54.199790 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3936 RESULT=skip
24635 10:56:54.247935 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3936 RESULT=skip
24637 10:56:54.248413 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3936 RESULT=skip>
24638 10:56:54.296582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3952 RESULT=pass>
24639 10:56:54.296988 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3952 RESULT=pass
24641 10:56:54.344993 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3952 RESULT=skip
24643 10:56:54.345489 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3952 RESULT=skip>
24644 10:56:54.393064 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3952 RESULT=skip>
24645 10:56:54.393496 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3952 RESULT=skip
24647 10:56:54.437784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3952 RESULT=skip>
24648 10:56:54.438232 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3952 RESULT=skip
24650 10:56:54.486651 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3968 RESULT=pass
24652 10:56:54.487077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3968 RESULT=pass>
24653 10:56:54.523922 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3968 RESULT=skip
24655 10:56:54.524330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3968 RESULT=skip>
24656 10:56:54.569468 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3968 RESULT=skip
24658 10:56:54.569928 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3968 RESULT=skip>
24659 10:56:54.618334 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3968 RESULT=skip>
24660 10:56:54.618753 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3968 RESULT=skip
24662 10:56:54.661771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3984 RESULT=pass>
24663 10:56:54.662213 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3984 RESULT=pass
24665 10:56:54.701120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3984 RESULT=skip>
24666 10:56:54.701571 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3984 RESULT=skip
24668 10:56:54.737719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3984 RESULT=skip>
24669 10:56:54.738159 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3984 RESULT=skip
24671 10:56:54.773407 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3984 RESULT=skip
24673 10:56:54.773878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3984 RESULT=skip>
24674 10:56:54.811161 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4000 RESULT=pass>
24675 10:56:54.811554 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4000 RESULT=pass
24677 10:56:54.859830 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4000 RESULT=skip
24679 10:56:54.860281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4000 RESULT=skip>
24680 10:56:54.902775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4000 RESULT=skip>
24681 10:56:54.903204 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4000 RESULT=skip
24683 10:56:54.952634 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4000 RESULT=skip
24685 10:56:54.953069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4000 RESULT=skip>
24686 10:56:55.001270 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4016 RESULT=pass>
24687 10:56:55.001689 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4016 RESULT=pass
24689 10:56:55.039468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4016 RESULT=skip>
24690 10:56:55.039912 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4016 RESULT=skip
24692 10:56:55.079796 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4016 RESULT=skip
24694 10:56:55.080329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4016 RESULT=skip>
24695 10:56:55.125181 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4016 RESULT=skip>
24696 10:56:55.125604 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4016 RESULT=skip
24698 10:56:55.174128 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4032 RESULT=pass
24700 10:56:55.174574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4032 RESULT=pass>
24701 10:56:55.223045 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4032 RESULT=skip
24703 10:56:55.223464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4032 RESULT=skip>
24704 10:56:55.271028 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4032 RESULT=skip>
24705 10:56:55.271456 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4032 RESULT=skip
24707 10:56:55.307174 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4032 RESULT=skip
24709 10:56:55.307647 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4032 RESULT=skip>
24710 10:56:55.351353 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4048 RESULT=pass>
24711 10:56:55.351774 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4048 RESULT=pass
24713 10:56:55.394853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4048 RESULT=skip>
24714 10:56:55.395292 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4048 RESULT=skip
24716 10:56:55.431489 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4048 RESULT=skip>
24717 10:56:55.431913 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4048 RESULT=skip
24719 10:56:55.474196 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4048 RESULT=skip>
24720 10:56:55.474622 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4048 RESULT=skip
24722 10:56:55.514934 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4064 RESULT=pass>
24723 10:56:55.515337 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4064 RESULT=pass
24725 10:56:55.560550 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4064 RESULT=skip
24727 10:56:55.561017 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4064 RESULT=skip>
24728 10:56:55.595417 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4064 RESULT=skip>
24729 10:56:55.595791 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4064 RESULT=skip
24731 10:56:55.633992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4064 RESULT=skip>
24732 10:56:55.634417 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4064 RESULT=skip
24734 10:56:55.683568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4080 RESULT=pass>
24735 10:56:55.683989 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4080 RESULT=pass
24737 10:56:55.739455 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4080 RESULT=skip>
24738 10:56:55.739890 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4080 RESULT=skip
24740 10:56:55.795686 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4080 RESULT=skip
24742 10:56:55.796142 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4080 RESULT=skip>
24743 10:56:55.849291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4080 RESULT=skip>
24744 10:56:55.849677 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4080 RESULT=skip
24746 10:56:55.896820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4096 RESULT=pass>
24747 10:56:55.897159 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4096 RESULT=pass
24749 10:56:55.945262 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4096 RESULT=skip>
24750 10:56:55.945640 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4096 RESULT=skip
24752 10:56:55.989500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4096 RESULT=skip>
24753 10:56:55.989916 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4096 RESULT=skip
24755 10:56:56.033668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4096 RESULT=skip>
24756 10:56:56.034093 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4096 RESULT=skip
24758 10:56:56.081796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4112 RESULT=pass>
24759 10:56:56.082236 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4112 RESULT=pass
24761 10:56:56.129400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4112 RESULT=skip>
24762 10:56:56.129799 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4112 RESULT=skip
24764 10:56:56.175926 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4112 RESULT=skip
24766 10:56:56.176464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4112 RESULT=skip>
24767 10:56:56.223661 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4112 RESULT=skip>
24768 10:56:56.224076 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4112 RESULT=skip
24770 10:56:56.296237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4128 RESULT=pass>
24771 10:56:56.296699 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4128 RESULT=pass
24773 10:56:56.345483 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4128 RESULT=skip>
24774 10:56:56.345989 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4128 RESULT=skip
24776 10:56:56.399823 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4128 RESULT=skip
24778 10:56:56.400261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4128 RESULT=skip>
24779 10:56:56.450741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4128 RESULT=skip>
24780 10:56:56.451146 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4128 RESULT=skip
24782 10:56:56.502096 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4144 RESULT=pass>
24783 10:56:56.502500 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4144 RESULT=pass
24785 10:56:56.553043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4144 RESULT=skip>
24786 10:56:56.553484 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4144 RESULT=skip
24788 10:56:56.605728 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4144 RESULT=skip>
24789 10:56:56.606169 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4144 RESULT=skip
24791 10:56:56.657042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4144 RESULT=skip>
24792 10:56:56.657415 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4144 RESULT=skip
24794 10:56:56.708975 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4160 RESULT=pass
24796 10:56:56.709393 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4160 RESULT=pass>
24797 10:56:56.759860 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4160 RESULT=skip
24799 10:56:56.760320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4160 RESULT=skip>
24800 10:56:56.812749 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4160 RESULT=skip
24802 10:56:56.813109 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4160 RESULT=skip>
24803 10:56:56.862665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4160 RESULT=skip>
24804 10:56:56.863000 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4160 RESULT=skip
24806 10:56:56.913611 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4176 RESULT=pass
24808 10:56:56.914059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4176 RESULT=pass>
24809 10:56:56.965491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4176 RESULT=skip>
24810 10:56:56.965906 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4176 RESULT=skip
24812 10:56:57.017684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4176 RESULT=skip>
24813 10:56:57.018134 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4176 RESULT=skip
24815 10:56:57.069689 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4176 RESULT=skip
24817 10:56:57.070123 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4176 RESULT=skip>
24818 10:56:57.122270 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4192 RESULT=pass>
24819 10:56:57.122694 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4192 RESULT=pass
24821 10:56:57.174045 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4192 RESULT=skip
24823 10:56:57.174465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4192 RESULT=skip>
24824 10:56:57.225708 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4192 RESULT=skip
24826 10:56:57.226115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4192 RESULT=skip>
24827 10:56:57.277168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4192 RESULT=skip>
24828 10:56:57.277560 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4192 RESULT=skip
24830 10:56:57.329700 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4208 RESULT=pass
24832 10:56:57.330139 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4208 RESULT=pass>
24833 10:56:57.381807 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4208 RESULT=skip>
24834 10:56:57.382302 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4208 RESULT=skip
24836 10:56:57.434491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4208 RESULT=skip>
24837 10:56:57.434946 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4208 RESULT=skip
24839 10:56:57.486336 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4208 RESULT=skip>
24840 10:56:57.486827 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4208 RESULT=skip
24842 10:56:57.538306 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4224 RESULT=pass>
24843 10:56:57.538926 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4224 RESULT=pass
24845 10:56:57.589377 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4224 RESULT=skip>
24846 10:56:57.589749 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4224 RESULT=skip
24848 10:56:57.639902 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4224 RESULT=skip
24850 10:56:57.640453 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4224 RESULT=skip>
24851 10:56:57.691155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4224 RESULT=skip>
24852 10:56:57.691581 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4224 RESULT=skip
24854 10:56:57.741718 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4240 RESULT=pass
24856 10:56:57.742166 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4240 RESULT=pass>
24857 10:56:57.793306 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4240 RESULT=skip
24859 10:56:57.793762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4240 RESULT=skip>
24860 10:56:57.845519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4240 RESULT=skip>
24861 10:56:57.845912 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4240 RESULT=skip
24863 10:56:57.899508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4240 RESULT=skip>
24864 10:56:57.899949 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4240 RESULT=skip
24866 10:56:57.953368 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4256 RESULT=pass
24868 10:56:57.953862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4256 RESULT=pass>
24869 10:56:58.005269 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4256 RESULT=skip
24871 10:56:58.005696 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4256 RESULT=skip>
24872 10:56:58.055793 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4256 RESULT=skip
24874 10:56:58.056245 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4256 RESULT=skip>
24875 10:56:58.106446 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4256 RESULT=skip>
24876 10:56:58.106909 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4256 RESULT=skip
24878 10:56:58.158150 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4272 RESULT=pass>
24879 10:56:58.158608 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4272 RESULT=pass
24881 10:56:58.209855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4272 RESULT=skip>
24882 10:56:58.210283 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4272 RESULT=skip
24884 10:56:58.261106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4272 RESULT=skip>
24885 10:56:58.261499 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4272 RESULT=skip
24887 10:56:58.310730 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4272 RESULT=skip>
24888 10:56:58.311159 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4272 RESULT=skip
24890 10:56:58.365090 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4288 RESULT=pass
24892 10:56:58.365555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4288 RESULT=pass>
24893 10:56:58.417692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4288 RESULT=skip>
24894 10:56:58.418065 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4288 RESULT=skip
24896 10:56:58.470824 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4288 RESULT=skip>
24897 10:56:58.471236 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4288 RESULT=skip
24899 10:56:58.529084 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4288 RESULT=skip
24901 10:56:58.529544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4288 RESULT=skip>
24902 10:56:58.589573 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4304 RESULT=pass>
24903 10:56:58.590175 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4304 RESULT=pass
24905 10:56:58.647387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4304 RESULT=skip>
24906 10:56:58.647814 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4304 RESULT=skip
24908 10:56:58.706448 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4304 RESULT=skip>
24909 10:56:58.707026 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4304 RESULT=skip
24911 10:56:58.765567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4304 RESULT=skip>
24912 10:56:58.765989 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4304 RESULT=skip
24914 10:56:58.825477 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4320 RESULT=pass>
24915 10:56:58.825863 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4320 RESULT=pass
24917 10:56:58.879532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4320 RESULT=skip>
24918 10:56:58.879960 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4320 RESULT=skip
24920 10:56:58.933711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4320 RESULT=skip>
24921 10:56:58.934132 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4320 RESULT=skip
24923 10:56:59.001531 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4320 RESULT=skip>
24924 10:56:59.001962 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4320 RESULT=skip
24926 10:56:59.055565 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4336 RESULT=pass
24928 10:56:59.056013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4336 RESULT=pass>
24929 10:56:59.108678 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4336 RESULT=skip
24931 10:56:59.109133 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4336 RESULT=skip>
24932 10:56:59.163365 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4336 RESULT=skip>
24933 10:56:59.163723 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4336 RESULT=skip
24935 10:56:59.216030 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4336 RESULT=skip
24937 10:56:59.216463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4336 RESULT=skip>
24938 10:56:59.266298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4352 RESULT=pass>
24939 10:56:59.266728 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4352 RESULT=pass
24941 10:56:59.311232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4352 RESULT=skip>
24942 10:56:59.311619 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4352 RESULT=skip
24944 10:56:59.359170 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4352 RESULT=skip>
24945 10:56:59.359597 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4352 RESULT=skip
24947 10:56:59.408660 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4352 RESULT=skip>
24948 10:56:59.409087 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4352 RESULT=skip
24950 10:56:59.458162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4368 RESULT=pass>
24951 10:56:59.458558 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4368 RESULT=pass
24953 10:56:59.505678 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4368 RESULT=skip>
24954 10:56:59.506113 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4368 RESULT=skip
24956 10:56:59.553633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4368 RESULT=skip>
24957 10:56:59.554062 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4368 RESULT=skip
24959 10:56:59.601481 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4368 RESULT=skip
24961 10:56:59.601932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4368 RESULT=skip>
24962 10:56:59.640587 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4384 RESULT=pass>
24963 10:56:59.641012 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4384 RESULT=pass
24965 10:56:59.689073 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4384 RESULT=skip>
24966 10:56:59.689501 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4384 RESULT=skip
24968 10:56:59.736938 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4384 RESULT=skip>
24969 10:56:59.737321 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4384 RESULT=skip
24971 10:56:59.785246 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4384 RESULT=skip
24973 10:56:59.785706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4384 RESULT=skip>
24974 10:56:59.832787 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4400 RESULT=pass>
24975 10:56:59.833210 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4400 RESULT=pass
24977 10:56:59.881915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4400 RESULT=skip>
24978 10:56:59.882339 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4400 RESULT=skip
24980 10:56:59.931251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4400 RESULT=skip>
24981 10:56:59.931668 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4400 RESULT=skip
24983 10:56:59.978061 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4400 RESULT=skip
24985 10:56:59.978517 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4400 RESULT=skip>
24986 10:57:00.026661 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4416 RESULT=pass>
24987 10:57:00.027082 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4416 RESULT=pass
24989 10:57:00.075270 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4416 RESULT=skip>
24990 10:57:00.075694 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4416 RESULT=skip
24992 10:57:00.123754 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4416 RESULT=skip
24994 10:57:00.124198 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4416 RESULT=skip>
24995 10:57:00.173396 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4416 RESULT=skip
24997 10:57:00.173763 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4416 RESULT=skip>
24998 10:57:00.221716 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4432 RESULT=pass>
24999 10:57:00.222104 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4432 RESULT=pass
25001 10:57:00.271993 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4432 RESULT=skip
25003 10:57:00.272459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4432 RESULT=skip>
25004 10:57:00.319810 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4432 RESULT=skip
25006 10:57:00.320273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4432 RESULT=skip>
25007 10:57:00.359481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4432 RESULT=skip>
25008 10:57:00.359875 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4432 RESULT=skip
25010 10:57:00.408384 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4448 RESULT=pass>
25011 10:57:00.408694 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4448 RESULT=pass
25013 10:57:00.455796 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4448 RESULT=skip
25015 10:57:00.456246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4448 RESULT=skip>
25016 10:57:00.499182 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4448 RESULT=skip>
25017 10:57:00.499614 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4448 RESULT=skip
25019 10:57:00.546301 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4448 RESULT=skip
25021 10:57:00.546785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4448 RESULT=skip>
25022 10:57:00.594352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4464 RESULT=pass>
25023 10:57:00.594775 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4464 RESULT=pass
25025 10:57:00.641659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4464 RESULT=skip>
25026 10:57:00.642082 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4464 RESULT=skip
25028 10:57:00.690567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4464 RESULT=skip>
25029 10:57:00.690968 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4464 RESULT=skip
25031 10:57:00.734230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4464 RESULT=skip>
25032 10:57:00.734531 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4464 RESULT=skip
25034 10:57:00.778121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4480 RESULT=pass>
25035 10:57:00.778418 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4480 RESULT=pass
25037 10:57:00.826347 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4480 RESULT=skip
25039 10:57:00.826655 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4480 RESULT=skip>
25040 10:57:00.874537 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4480 RESULT=skip
25042 10:57:00.874869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4480 RESULT=skip>
25043 10:57:00.925202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4480 RESULT=skip>
25044 10:57:00.925600 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4480 RESULT=skip
25046 10:57:00.966073 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4496 RESULT=pass>
25047 10:57:00.966491 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4496 RESULT=pass
25049 10:57:01.013926 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4496 RESULT=skip>
25050 10:57:01.014353 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4496 RESULT=skip
25052 10:57:01.062119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4496 RESULT=skip>
25053 10:57:01.062552 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4496 RESULT=skip
25055 10:57:01.111697 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4496 RESULT=skip
25057 10:57:01.112188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4496 RESULT=skip>
25058 10:57:01.160102 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4512 RESULT=pass
25060 10:57:01.160575 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4512 RESULT=pass>
25061 10:57:01.213581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4512 RESULT=skip>
25062 10:57:01.214013 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4512 RESULT=skip
25064 10:57:01.267333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4512 RESULT=skip>
25065 10:57:01.267706 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4512 RESULT=skip
25067 10:57:01.321887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4512 RESULT=skip>
25068 10:57:01.322303 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4512 RESULT=skip
25070 10:57:01.398179 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4528 RESULT=pass
25072 10:57:01.398646 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4528 RESULT=pass>
25073 10:57:01.449702 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4528 RESULT=skip>
25074 10:57:01.450093 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4528 RESULT=skip
25076 10:57:01.497931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4528 RESULT=skip>
25077 10:57:01.498357 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4528 RESULT=skip
25079 10:57:01.543282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4528 RESULT=skip>
25080 10:57:01.543727 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4528 RESULT=skip
25082 10:57:01.580937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4544 RESULT=pass>
25083 10:57:01.581372 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4544 RESULT=pass
25085 10:57:01.626977 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4544 RESULT=skip
25087 10:57:01.627433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4544 RESULT=skip>
25088 10:57:01.678258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4544 RESULT=skip>
25089 10:57:01.679301 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4544 RESULT=skip
25091 10:57:01.718360 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4544 RESULT=skip>
25092 10:57:01.718738 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4544 RESULT=skip
25094 10:57:01.765277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4560 RESULT=pass>
25095 10:57:01.765690 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4560 RESULT=pass
25097 10:57:01.806157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4560 RESULT=skip>
25098 10:57:01.806597 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4560 RESULT=skip
25100 10:57:01.852074 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4560 RESULT=skip
25102 10:57:01.852593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4560 RESULT=skip>
25103 10:57:01.890850 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4560 RESULT=skip>
25104 10:57:01.891262 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4560 RESULT=skip
25106 10:57:01.944997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4576 RESULT=pass>
25107 10:57:01.945419 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4576 RESULT=pass
25109 10:57:01.997959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4576 RESULT=skip>
25110 10:57:01.998390 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4576 RESULT=skip
25112 10:57:02.050854 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4576 RESULT=skip>
25113 10:57:02.051153 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4576 RESULT=skip
25115 10:57:02.103875 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4576 RESULT=skip
25117 10:57:02.104209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4576 RESULT=skip>
25118 10:57:02.155971 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4592 RESULT=pass
25120 10:57:02.156366 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4592 RESULT=pass>
25121 10:57:02.208652 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4592 RESULT=skip>
25122 10:57:02.208949 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4592 RESULT=skip
25124 10:57:02.262482 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4592 RESULT=skip>
25125 10:57:02.262756 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4592 RESULT=skip
25127 10:57:02.316790 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4592 RESULT=skip
25129 10:57:02.317172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4592 RESULT=skip>
25130 10:57:02.369803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4608 RESULT=pass>
25131 10:57:02.370264 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4608 RESULT=pass
25133 10:57:02.426622 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4608 RESULT=skip>
25134 10:57:02.427030 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4608 RESULT=skip
25136 10:57:02.483441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4608 RESULT=skip>
25137 10:57:02.483855 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4608 RESULT=skip
25139 10:57:02.542316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4608 RESULT=skip>
25140 10:57:02.542740 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4608 RESULT=skip
25142 10:57:02.600784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4624 RESULT=pass>
25143 10:57:02.601179 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4624 RESULT=pass
25145 10:57:02.654470 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4624 RESULT=skip>
25146 10:57:02.654873 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4624 RESULT=skip
25148 10:57:02.707894 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4624 RESULT=skip
25150 10:57:02.708292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4624 RESULT=skip>
25151 10:57:02.761798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4624 RESULT=skip>
25152 10:57:02.762251 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4624 RESULT=skip
25154 10:57:02.814845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4640 RESULT=pass>
25155 10:57:02.815273 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4640 RESULT=pass
25157 10:57:02.867774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4640 RESULT=skip>
25158 10:57:02.868215 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4640 RESULT=skip
25160 10:57:02.922874 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4640 RESULT=skip
25162 10:57:02.923323 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4640 RESULT=skip>
25163 10:57:02.977478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4640 RESULT=skip>
25164 10:57:02.977903 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4640 RESULT=skip
25166 10:57:03.030557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4656 RESULT=pass>
25167 10:57:03.030881 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4656 RESULT=pass
25169 10:57:03.083903 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4656 RESULT=skip
25171 10:57:03.084235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4656 RESULT=skip>
25172 10:57:03.138138 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4656 RESULT=skip
25174 10:57:03.138602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4656 RESULT=skip>
25175 10:57:03.191001 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4656 RESULT=skip>
25176 10:57:03.191431 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4656 RESULT=skip
25178 10:57:03.245249 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4672 RESULT=pass>
25179 10:57:03.245677 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4672 RESULT=pass
25181 10:57:03.298732 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4672 RESULT=skip
25183 10:57:03.299173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4672 RESULT=skip>
25184 10:57:03.351501 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4672 RESULT=skip>
25185 10:57:03.351908 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4672 RESULT=skip
25187 10:57:03.405329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4672 RESULT=skip>
25188 10:57:03.405757 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4672 RESULT=skip
25190 10:57:03.457721 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4688 RESULT=pass>
25191 10:57:03.458141 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4688 RESULT=pass
25193 10:57:03.511186 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4688 RESULT=skip>
25194 10:57:03.511624 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4688 RESULT=skip
25196 10:57:03.564031 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4688 RESULT=skip
25198 10:57:03.564615 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4688 RESULT=skip>
25199 10:57:03.619021 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4688 RESULT=skip
25201 10:57:03.619385 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4688 RESULT=skip>
25202 10:57:03.673496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4704 RESULT=pass>
25203 10:57:03.673919 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4704 RESULT=pass
25205 10:57:03.726828 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4704 RESULT=skip>
25206 10:57:03.727249 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4704 RESULT=skip
25208 10:57:03.781639 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4704 RESULT=skip>
25209 10:57:03.782052 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4704 RESULT=skip
25211 10:57:03.835635 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4704 RESULT=skip
25213 10:57:03.836009 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4704 RESULT=skip>
25214 10:57:03.888243 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4720 RESULT=pass
25216 10:57:03.888699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4720 RESULT=pass>
25217 10:57:03.943043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4720 RESULT=skip>
25218 10:57:03.943458 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4720 RESULT=skip
25220 10:57:03.997680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4720 RESULT=skip>
25221 10:57:03.998101 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4720 RESULT=skip
25223 10:57:04.050905 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4720 RESULT=skip>
25224 10:57:04.051351 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4720 RESULT=skip
25226 10:57:04.103917 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4736 RESULT=pass
25228 10:57:04.104381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4736 RESULT=pass>
25229 10:57:04.157430 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4736 RESULT=skip>
25230 10:57:04.157857 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4736 RESULT=skip
25232 10:57:04.210248 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4736 RESULT=skip
25234 10:57:04.210694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4736 RESULT=skip>
25235 10:57:04.264503 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4736 RESULT=skip>
25236 10:57:04.264929 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4736 RESULT=skip
25238 10:57:04.317654 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4752 RESULT=pass>
25239 10:57:04.318072 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4752 RESULT=pass
25241 10:57:04.370219 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4752 RESULT=skip>
25242 10:57:04.370619 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4752 RESULT=skip
25244 10:57:04.423124 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4752 RESULT=skip
25246 10:57:04.423565 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4752 RESULT=skip>
25247 10:57:04.476006 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4752 RESULT=skip
25249 10:57:04.476477 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4752 RESULT=skip>
25250 10:57:04.529202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4768 RESULT=pass>
25251 10:57:04.529620 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4768 RESULT=pass
25253 10:57:04.581953 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4768 RESULT=skip
25255 10:57:04.582366 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4768 RESULT=skip>
25256 10:57:04.635118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4768 RESULT=skip>
25257 10:57:04.635548 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4768 RESULT=skip
25259 10:57:04.688106 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4768 RESULT=skip
25261 10:57:04.688585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4768 RESULT=skip>
25262 10:57:04.741371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4784 RESULT=pass>
25263 10:57:04.741815 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4784 RESULT=pass
25265 10:57:04.794420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4784 RESULT=skip>
25266 10:57:04.794812 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4784 RESULT=skip
25268 10:57:04.848036 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4784 RESULT=skip
25270 10:57:04.848512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4784 RESULT=skip>
25271 10:57:04.901664 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4784 RESULT=skip>
25272 10:57:04.902071 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4784 RESULT=skip
25274 10:57:04.955971 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4800 RESULT=pass
25276 10:57:04.956368 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4800 RESULT=pass>
25277 10:57:05.008945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4800 RESULT=skip>
25278 10:57:05.009284 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4800 RESULT=skip
25280 10:57:05.061789 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4800 RESULT=skip
25282 10:57:05.062215 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4800 RESULT=skip>
25283 10:57:05.115237 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4800 RESULT=skip
25285 10:57:05.115701 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4800 RESULT=skip>
25286 10:57:05.168705 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4816 RESULT=pass
25288 10:57:05.169117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4816 RESULT=pass>
25289 10:57:05.221428 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4816 RESULT=skip
25291 10:57:05.221850 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4816 RESULT=skip>
25292 10:57:05.274826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4816 RESULT=skip>
25293 10:57:05.275199 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4816 RESULT=skip
25295 10:57:05.327861 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4816 RESULT=skip
25297 10:57:05.328312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4816 RESULT=skip>
25298 10:57:05.381674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4832 RESULT=pass>
25299 10:57:05.382106 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4832 RESULT=pass
25301 10:57:05.434983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4832 RESULT=skip>
25302 10:57:05.435354 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4832 RESULT=skip
25304 10:57:05.484799 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4832 RESULT=skip>
25305 10:57:05.485234 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4832 RESULT=skip
25307 10:57:05.533372 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4832 RESULT=skip>
25308 10:57:05.533811 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4832 RESULT=skip
25310 10:57:05.577028 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4848 RESULT=pass>
25311 10:57:05.577468 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4848 RESULT=pass
25313 10:57:05.619859 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4848 RESULT=skip
25315 10:57:05.620346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4848 RESULT=skip>
25316 10:57:05.670355 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4848 RESULT=skip
25318 10:57:05.670796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4848 RESULT=skip>
25319 10:57:05.720180 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4848 RESULT=skip
25321 10:57:05.720645 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4848 RESULT=skip>
25322 10:57:05.765404 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4864 RESULT=pass>
25323 10:57:05.765914 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4864 RESULT=pass
25325 10:57:05.800505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4864 RESULT=skip>
25326 10:57:05.800951 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4864 RESULT=skip
25328 10:57:05.839184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4864 RESULT=skip>
25329 10:57:05.839648 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4864 RESULT=skip
25331 10:57:05.886736 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4864 RESULT=skip
25333 10:57:05.887176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4864 RESULT=skip>
25334 10:57:05.939161 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4880 RESULT=pass>
25335 10:57:05.939595 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4880 RESULT=pass
25337 10:57:05.988837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4880 RESULT=skip>
25338 10:57:05.989246 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4880 RESULT=skip
25340 10:57:06.038165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4880 RESULT=skip>
25341 10:57:06.038591 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4880 RESULT=skip
25343 10:57:06.078123 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4880 RESULT=skip>
25344 10:57:06.078559 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4880 RESULT=skip
25346 10:57:06.125950 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4896 RESULT=pass
25348 10:57:06.126397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4896 RESULT=pass>
25349 10:57:06.170339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4896 RESULT=skip>
25350 10:57:06.170761 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4896 RESULT=skip
25352 10:57:06.218695 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4896 RESULT=skip>
25353 10:57:06.219069 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4896 RESULT=skip
25355 10:57:06.262580 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4896 RESULT=skip
25357 10:57:06.263043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4896 RESULT=skip>
25358 10:57:06.310269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4912 RESULT=pass>
25359 10:57:06.310695 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4912 RESULT=pass
25361 10:57:06.359367 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4912 RESULT=skip
25363 10:57:06.359837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4912 RESULT=skip>
25364 10:57:06.407880 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4912 RESULT=skip
25366 10:57:06.408350 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4912 RESULT=skip>
25367 10:57:06.450606 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4912 RESULT=skip>
25368 10:57:06.451034 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4912 RESULT=skip
25370 10:57:06.518535 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4928 RESULT=pass>
25371 10:57:06.518953 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4928 RESULT=pass
25373 10:57:06.554533 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4928 RESULT=skip>
25374 10:57:06.554941 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4928 RESULT=skip
25376 10:57:06.594072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4928 RESULT=skip>
25377 10:57:06.594465 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4928 RESULT=skip
25379 10:57:06.633937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4928 RESULT=skip>
25380 10:57:06.634371 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4928 RESULT=skip
25382 10:57:06.682756 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4944 RESULT=pass>
25383 10:57:06.683194 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4944 RESULT=pass
25385 10:57:06.735588 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4944 RESULT=skip>
25386 10:57:06.735978 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4944 RESULT=skip
25388 10:57:06.788435 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4944 RESULT=skip>
25389 10:57:06.788836 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4944 RESULT=skip
25391 10:57:06.841292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4944 RESULT=skip>
25392 10:57:06.841694 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4944 RESULT=skip
25394 10:57:06.894638 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4960 RESULT=pass>
25395 10:57:06.895025 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4960 RESULT=pass
25397 10:57:06.949798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4960 RESULT=skip>
25398 10:57:06.950245 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4960 RESULT=skip
25400 10:57:06.997661 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4960 RESULT=skip>
25401 10:57:06.998090 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4960 RESULT=skip
25403 10:57:07.045704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4960 RESULT=skip>
25404 10:57:07.046155 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4960 RESULT=skip
25406 10:57:07.092494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4976 RESULT=pass>
25407 10:57:07.092924 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4976 RESULT=pass
25409 10:57:07.140962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4976 RESULT=skip>
25410 10:57:07.141390 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4976 RESULT=skip
25412 10:57:07.190669 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4976 RESULT=skip
25414 10:57:07.191085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4976 RESULT=skip>
25415 10:57:07.238134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4976 RESULT=skip>
25416 10:57:07.238565 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4976 RESULT=skip
25418 10:57:07.276330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4992 RESULT=pass>
25419 10:57:07.276755 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4992 RESULT=pass
25421 10:57:07.324510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4992 RESULT=skip>
25422 10:57:07.324924 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4992 RESULT=skip
25424 10:57:07.366225 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4992 RESULT=skip>
25425 10:57:07.366609 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4992 RESULT=skip
25427 10:57:07.405995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4992 RESULT=skip>
25428 10:57:07.406412 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4992 RESULT=skip
25430 10:57:07.447412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5008 RESULT=pass>
25431 10:57:07.447835 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5008 RESULT=pass
25433 10:57:07.489069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5008 RESULT=skip>
25434 10:57:07.489500 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5008 RESULT=skip
25436 10:57:07.525273 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5008 RESULT=skip
25438 10:57:07.525745 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5008 RESULT=skip>
25439 10:57:07.573434 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5008 RESULT=skip>
25440 10:57:07.573868 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5008 RESULT=skip
25442 10:57:07.611440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5024 RESULT=pass>
25443 10:57:07.611865 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5024 RESULT=pass
25445 10:57:07.647924 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5024 RESULT=skip
25447 10:57:07.648388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5024 RESULT=skip>
25448 10:57:07.696846 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5024 RESULT=skip>
25449 10:57:07.697279 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5024 RESULT=skip
25451 10:57:07.745616 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5024 RESULT=skip
25453 10:57:07.746049 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5024 RESULT=skip>
25454 10:57:07.790403 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5040 RESULT=pass>
25455 10:57:07.790811 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5040 RESULT=pass
25457 10:57:07.835301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5040 RESULT=skip>
25458 10:57:07.835745 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5040 RESULT=skip
25460 10:57:07.884906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5040 RESULT=skip>
25461 10:57:07.885336 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5040 RESULT=skip
25463 10:57:07.926305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5040 RESULT=skip>
25464 10:57:07.926706 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5040 RESULT=skip
25466 10:57:07.976531 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5056 RESULT=pass
25468 10:57:07.976878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5056 RESULT=pass>
25469 10:57:08.025208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5056 RESULT=skip>
25470 10:57:08.025558 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5056 RESULT=skip
25472 10:57:08.073335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5056 RESULT=skip>
25473 10:57:08.073783 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5056 RESULT=skip
25475 10:57:08.118336 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5056 RESULT=skip>
25476 10:57:08.118642 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5056 RESULT=skip
25478 10:57:08.166962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5072 RESULT=pass>
25479 10:57:08.167291 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5072 RESULT=pass
25481 10:57:08.216581 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5072 RESULT=skip
25483 10:57:08.216941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5072 RESULT=skip>
25484 10:57:08.265096 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5072 RESULT=skip>
25485 10:57:08.265418 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5072 RESULT=skip
25487 10:57:08.313345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5072 RESULT=skip>
25488 10:57:08.313661 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5072 RESULT=skip
25490 10:57:08.360955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5088 RESULT=pass>
25491 10:57:08.361346 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5088 RESULT=pass
25493 10:57:08.409007 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5088 RESULT=skip>
25494 10:57:08.409438 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5088 RESULT=skip
25496 10:57:08.457552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5088 RESULT=skip>
25497 10:57:08.457983 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5088 RESULT=skip
25499 10:57:08.505392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5088 RESULT=skip>
25500 10:57:08.505824 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5088 RESULT=skip
25502 10:57:08.553338 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5104 RESULT=pass
25504 10:57:08.553767 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5104 RESULT=pass>
25505 10:57:08.601691 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5104 RESULT=skip>
25506 10:57:08.601988 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5104 RESULT=skip
25508 10:57:08.653461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5104 RESULT=skip>
25509 10:57:08.653755 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5104 RESULT=skip
25511 10:57:08.702661 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5104 RESULT=skip>
25512 10:57:08.702969 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5104 RESULT=skip
25514 10:57:08.746777 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5120 RESULT=pass>
25515 10:57:08.747196 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5120 RESULT=pass
25517 10:57:08.793619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5120 RESULT=skip>
25518 10:57:08.794051 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5120 RESULT=skip
25520 10:57:08.834290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5120 RESULT=skip>
25521 10:57:08.834713 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5120 RESULT=skip
25523 10:57:08.885950 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5120 RESULT=skip
25525 10:57:08.886404 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5120 RESULT=skip>
25526 10:57:08.939183 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5136 RESULT=pass>
25527 10:57:08.939587 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5136 RESULT=pass
25529 10:57:08.991880 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5136 RESULT=skip
25531 10:57:08.992572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5136 RESULT=skip>
25532 10:57:09.044583 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5136 RESULT=skip>
25533 10:57:09.045023 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5136 RESULT=skip
25535 10:57:09.098531 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5136 RESULT=skip>
25536 10:57:09.098909 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5136 RESULT=skip
25538 10:57:09.150986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5152 RESULT=pass>
25539 10:57:09.151355 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5152 RESULT=pass
25541 10:57:09.203289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5152 RESULT=skip>
25542 10:57:09.203710 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5152 RESULT=skip
25544 10:57:09.255966 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5152 RESULT=skip
25546 10:57:09.256400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5152 RESULT=skip>
25547 10:57:09.308532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5152 RESULT=skip>
25548 10:57:09.308941 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5152 RESULT=skip
25550 10:57:09.361152 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5168 RESULT=pass
25552 10:57:09.361601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5168 RESULT=pass>
25553 10:57:09.411590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5168 RESULT=skip>
25554 10:57:09.411991 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5168 RESULT=skip
25556 10:57:09.461885 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5168 RESULT=skip>
25557 10:57:09.462289 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5168 RESULT=skip
25559 10:57:09.510786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5168 RESULT=skip>
25560 10:57:09.511203 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5168 RESULT=skip
25562 10:57:09.561137 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5184 RESULT=pass
25564 10:57:09.561577 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5184 RESULT=pass>
25565 10:57:09.609692 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5184 RESULT=skip
25567 10:57:09.610057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5184 RESULT=skip>
25568 10:57:09.657127 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5184 RESULT=skip>
25569 10:57:09.657563 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5184 RESULT=skip
25571 10:57:09.703477 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5184 RESULT=skip>
25572 10:57:09.703856 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5184 RESULT=skip
25574 10:57:09.752933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5200 RESULT=pass>
25575 10:57:09.753352 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5200 RESULT=pass
25577 10:57:09.802989 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5200 RESULT=skip
25579 10:57:09.803487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5200 RESULT=skip>
25580 10:57:09.851414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5200 RESULT=skip>
25581 10:57:09.851762 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5200 RESULT=skip
25583 10:57:09.901038 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5200 RESULT=skip>
25584 10:57:09.901461 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5200 RESULT=skip
25586 10:57:09.951031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5216 RESULT=pass>
25587 10:57:09.951433 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5216 RESULT=pass
25589 10:57:10.000858 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5216 RESULT=skip>
25590 10:57:10.001275 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5216 RESULT=skip
25592 10:57:10.050398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5216 RESULT=skip>
25593 10:57:10.050820 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5216 RESULT=skip
25595 10:57:10.099479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5216 RESULT=skip>
25596 10:57:10.099919 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5216 RESULT=skip
25598 10:57:10.147379 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5232 RESULT=pass
25600 10:57:10.147832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5232 RESULT=pass>
25601 10:57:10.194425 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5232 RESULT=skip
25603 10:57:10.194830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5232 RESULT=skip>
25604 10:57:10.245573 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5232 RESULT=skip>
25605 10:57:10.245967 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5232 RESULT=skip
25607 10:57:10.291292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5232 RESULT=skip>
25608 10:57:10.291728 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5232 RESULT=skip
25610 10:57:10.331809 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5248 RESULT=pass
25612 10:57:10.332257 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5248 RESULT=pass>
25613 10:57:10.376298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5248 RESULT=skip>
25614 10:57:10.376716 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5248 RESULT=skip
25616 10:57:10.419781 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5248 RESULT=skip
25618 10:57:10.420275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5248 RESULT=skip>
25619 10:57:10.464486 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5248 RESULT=skip
25621 10:57:10.464914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5248 RESULT=skip>
25622 10:57:10.506754 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5264 RESULT=pass
25624 10:57:10.507178 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5264 RESULT=pass>
25625 10:57:10.551345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5264 RESULT=skip>
25626 10:57:10.552237 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5264 RESULT=skip
25628 10:57:10.595903 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5264 RESULT=skip>
25629 10:57:10.596322 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5264 RESULT=skip
25631 10:57:10.640460 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5264 RESULT=skip>
25632 10:57:10.640851 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5264 RESULT=skip
25634 10:57:10.685547 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5280 RESULT=pass>
25635 10:57:10.685905 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5280 RESULT=pass
25637 10:57:10.727683 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5280 RESULT=skip>
25638 10:57:10.728112 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5280 RESULT=skip
25640 10:57:10.771313 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5280 RESULT=skip
25642 10:57:10.771791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5280 RESULT=skip>
25643 10:57:10.815362 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5280 RESULT=skip
25645 10:57:10.815783 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5280 RESULT=skip>
25646 10:57:10.859482 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5296 RESULT=pass>
25647 10:57:10.859900 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5296 RESULT=pass
25649 10:57:10.897227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5296 RESULT=skip>
25650 10:57:10.897654 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5296 RESULT=skip
25652 10:57:10.941241 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5296 RESULT=skip>
25653 10:57:10.941664 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5296 RESULT=skip
25655 10:57:10.985331 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5296 RESULT=skip>
25656 10:57:10.985738 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5296 RESULT=skip
25658 10:57:11.028665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5312 RESULT=pass>
25659 10:57:11.029055 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5312 RESULT=pass
25661 10:57:11.070096 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5312 RESULT=skip>
25662 10:57:11.070500 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5312 RESULT=skip
25664 10:57:11.114031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5312 RESULT=skip>
25665 10:57:11.114397 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5312 RESULT=skip
25667 10:57:11.161577 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5312 RESULT=skip>
25668 10:57:11.162094 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5312 RESULT=skip
25670 10:57:11.201990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5328 RESULT=pass>
25671 10:57:11.202462 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5328 RESULT=pass
25673 10:57:11.240804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5328 RESULT=skip>
25674 10:57:11.241193 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5328 RESULT=skip
25676 10:57:11.284724 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5328 RESULT=skip>
25677 10:57:11.285125 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5328 RESULT=skip
25679 10:57:11.329111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5328 RESULT=skip>
25680 10:57:11.329533 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5328 RESULT=skip
25682 10:57:11.374127 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5344 RESULT=pass
25684 10:57:11.374616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5344 RESULT=pass>
25685 10:57:11.418293 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5344 RESULT=skip>
25686 10:57:11.418710 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5344 RESULT=skip
25688 10:57:11.462391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5344 RESULT=skip>
25689 10:57:11.462814 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5344 RESULT=skip
25691 10:57:11.506163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5344 RESULT=skip>
25692 10:57:11.506582 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5344 RESULT=skip
25694 10:57:11.548449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5360 RESULT=pass>
25695 10:57:11.548880 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5360 RESULT=pass
25697 10:57:11.588671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5360 RESULT=skip>
25698 10:57:11.589089 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5360 RESULT=skip
25700 10:57:11.646986 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5360 RESULT=skip
25702 10:57:11.647429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5360 RESULT=skip>
25703 10:57:11.686973 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5360 RESULT=skip>
25704 10:57:11.687379 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5360 RESULT=skip
25706 10:57:11.722274 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5376 RESULT=pass>
25707 10:57:11.722688 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5376 RESULT=pass
25709 10:57:11.761020 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5376 RESULT=skip>
25710 10:57:11.761426 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5376 RESULT=skip
25712 10:57:11.803975 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5376 RESULT=skip
25714 10:57:11.804442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5376 RESULT=skip>
25715 10:57:11.850638 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5376 RESULT=skip>
25716 10:57:11.851051 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5376 RESULT=skip
25718 10:57:11.894945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5392 RESULT=pass>
25719 10:57:11.895379 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5392 RESULT=pass
25721 10:57:11.938711 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5392 RESULT=skip
25723 10:57:11.939166 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5392 RESULT=skip>
25724 10:57:11.982529 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5392 RESULT=skip
25726 10:57:11.982977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5392 RESULT=skip>
25727 10:57:12.026616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5392 RESULT=skip>
25728 10:57:12.027020 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5392 RESULT=skip
25730 10:57:12.071341 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5408 RESULT=pass
25732 10:57:12.071769 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5408 RESULT=pass>
25733 10:57:12.117038 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5408 RESULT=skip>
25734 10:57:12.117386 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5408 RESULT=skip
25736 10:57:12.161905 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5408 RESULT=skip>
25737 10:57:12.162314 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5408 RESULT=skip
25739 10:57:12.204572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5408 RESULT=skip>
25740 10:57:12.204965 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5408 RESULT=skip
25742 10:57:12.246915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5424 RESULT=pass>
25743 10:57:12.247308 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5424 RESULT=pass
25745 10:57:12.283121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5424 RESULT=skip>
25746 10:57:12.283570 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5424 RESULT=skip
25748 10:57:12.317853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5424 RESULT=skip>
25749 10:57:12.318368 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5424 RESULT=skip
25751 10:57:12.358346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5424 RESULT=skip>
25752 10:57:12.358765 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5424 RESULT=skip
25754 10:57:12.397670 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5440 RESULT=pass
25756 10:57:12.398121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5440 RESULT=pass>
25757 10:57:12.437270 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5440 RESULT=skip>
25758 10:57:12.437682 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5440 RESULT=skip
25760 10:57:12.476024 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5440 RESULT=skip
25762 10:57:12.476651 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5440 RESULT=skip>
25763 10:57:12.519395 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5440 RESULT=skip>
25764 10:57:12.519791 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5440 RESULT=skip
25766 10:57:12.561945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5456 RESULT=pass>
25767 10:57:12.562367 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5456 RESULT=pass
25769 10:57:12.596232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5456 RESULT=skip>
25770 10:57:12.596631 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5456 RESULT=skip
25772 10:57:12.634128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5456 RESULT=skip>
25773 10:57:12.634536 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5456 RESULT=skip
25775 10:57:12.668619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5456 RESULT=skip>
25776 10:57:12.669021 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5456 RESULT=skip
25778 10:57:12.711133 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5472 RESULT=pass>
25779 10:57:12.711534 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5472 RESULT=pass
25781 10:57:12.755299 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5472 RESULT=skip>
25782 10:57:12.755709 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5472 RESULT=skip
25784 10:57:12.792337 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5472 RESULT=skip>
25785 10:57:12.792747 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5472 RESULT=skip
25787 10:57:12.830047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5472 RESULT=skip>
25788 10:57:12.830518 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5472 RESULT=skip
25790 10:57:12.863260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5488 RESULT=pass>
25791 10:57:12.863687 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5488 RESULT=pass
25793 10:57:12.905318 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5488 RESULT=skip>
25794 10:57:12.905748 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5488 RESULT=skip
25796 10:57:12.945603 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5488 RESULT=skip>
25797 10:57:12.946015 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5488 RESULT=skip
25799 10:57:12.990794 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5488 RESULT=skip
25801 10:57:12.991203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5488 RESULT=skip>
25802 10:57:13.034504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5504 RESULT=pass>
25803 10:57:13.034913 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5504 RESULT=pass
25805 10:57:13.077915 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5504 RESULT=skip
25807 10:57:13.078313 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5504 RESULT=skip>
25808 10:57:13.121403 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5504 RESULT=skip>
25809 10:57:13.121801 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5504 RESULT=skip
25811 10:57:13.158924 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5504 RESULT=skip>
25812 10:57:13.159350 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5504 RESULT=skip
25814 10:57:13.204488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5520 RESULT=pass>
25815 10:57:13.204926 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5520 RESULT=pass
25817 10:57:13.247818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5520 RESULT=skip>
25818 10:57:13.248171 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5520 RESULT=skip
25820 10:57:13.291632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5520 RESULT=skip>
25821 10:57:13.292075 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5520 RESULT=skip
25823 10:57:13.329206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5520 RESULT=skip>
25824 10:57:13.329617 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5520 RESULT=skip
25826 10:57:13.373753 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5536 RESULT=pass>
25827 10:57:13.374214 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5536 RESULT=pass
25829 10:57:13.409367 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5536 RESULT=skip
25831 10:57:13.409821 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5536 RESULT=skip>
25832 10:57:13.445817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5536 RESULT=skip>
25833 10:57:13.446233 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5536 RESULT=skip
25835 10:57:13.480266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5536 RESULT=skip>
25836 10:57:13.480660 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5536 RESULT=skip
25838 10:57:13.519271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5552 RESULT=pass>
25839 10:57:13.519784 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5552 RESULT=pass
25841 10:57:13.564866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5552 RESULT=skip>
25842 10:57:13.565240 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5552 RESULT=skip
25844 10:57:13.606497 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5552 RESULT=skip>
25845 10:57:13.606895 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5552 RESULT=skip
25847 10:57:13.654256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5552 RESULT=skip>
25848 10:57:13.654669 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5552 RESULT=skip
25850 10:57:13.705675 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5568 RESULT=pass
25852 10:57:13.706098 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5568 RESULT=pass>
25853 10:57:13.752653 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5568 RESULT=skip
25855 10:57:13.753103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5568 RESULT=skip>
25856 10:57:13.787256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5568 RESULT=skip>
25857 10:57:13.787684 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5568 RESULT=skip
25859 10:57:13.829402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5568 RESULT=skip>
25860 10:57:13.830166 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5568 RESULT=skip
25862 10:57:13.873439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5584 RESULT=pass>
25863 10:57:13.874066 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5584 RESULT=pass
25865 10:57:13.924820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5584 RESULT=skip>
25866 10:57:13.925213 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5584 RESULT=skip
25868 10:57:13.976798 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5584 RESULT=skip
25870 10:57:13.977182 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5584 RESULT=skip>
25871 10:57:14.013827 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5584 RESULT=skip>
25872 10:57:14.014226 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5584 RESULT=skip
25874 10:57:14.058962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5600 RESULT=pass>
25875 10:57:14.059376 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5600 RESULT=pass
25877 10:57:14.098318 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5600 RESULT=skip>
25878 10:57:14.098737 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5600 RESULT=skip
25880 10:57:14.131814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5600 RESULT=skip>
25881 10:57:14.132257 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5600 RESULT=skip
25883 10:57:14.178017 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5600 RESULT=skip>
25884 10:57:14.178442 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5600 RESULT=skip
25886 10:57:14.227734 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5616 RESULT=pass
25888 10:57:14.228201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5616 RESULT=pass>
25889 10:57:14.274910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5616 RESULT=skip>
25890 10:57:14.275349 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5616 RESULT=skip
25892 10:57:14.312530 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5616 RESULT=skip>
25893 10:57:14.312971 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5616 RESULT=skip
25895 10:57:14.357578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5616 RESULT=skip>
25896 10:57:14.358017 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5616 RESULT=skip
25898 10:57:14.395724 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5632 RESULT=pass
25900 10:57:14.396157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5632 RESULT=pass>
25901 10:57:14.440045 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5632 RESULT=skip
25903 10:57:14.440748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5632 RESULT=skip>
25904 10:57:14.473787 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5632 RESULT=skip
25906 10:57:14.474241 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5632 RESULT=skip>
25907 10:57:14.509148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5632 RESULT=skip>
25908 10:57:14.509540 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5632 RESULT=skip
25910 10:57:14.543884 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5648 RESULT=pass
25912 10:57:14.544343 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5648 RESULT=pass>
25913 10:57:14.582868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5648 RESULT=skip>
25914 10:57:14.583304 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5648 RESULT=skip
25916 10:57:14.619470 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5648 RESULT=skip>
25917 10:57:14.619903 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5648 RESULT=skip
25919 10:57:14.659010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5648 RESULT=skip>
25920 10:57:14.659380 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5648 RESULT=skip
25922 10:57:14.702736 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5664 RESULT=pass>
25923 10:57:14.703141 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5664 RESULT=pass
25925 10:57:14.748156 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5664 RESULT=skip
25927 10:57:14.748616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5664 RESULT=skip>
25928 10:57:14.794738 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5664 RESULT=skip>
25929 10:57:14.795156 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5664 RESULT=skip
25931 10:57:14.841094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5664 RESULT=skip>
25932 10:57:14.841496 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5664 RESULT=skip
25934 10:57:14.885982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5680 RESULT=pass>
25935 10:57:14.886391 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5680 RESULT=pass
25937 10:57:14.929080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5680 RESULT=skip>
25938 10:57:14.929509 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5680 RESULT=skip
25940 10:57:14.968545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5680 RESULT=skip>
25941 10:57:14.968941 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5680 RESULT=skip
25943 10:57:15.002898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5680 RESULT=skip>
25944 10:57:15.003279 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5680 RESULT=skip
25946 10:57:15.044451 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5696 RESULT=pass>
25947 10:57:15.044874 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5696 RESULT=pass
25949 10:57:15.089451 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5696 RESULT=skip
25951 10:57:15.090067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5696 RESULT=skip>
25952 10:57:15.128921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5696 RESULT=skip>
25953 10:57:15.129319 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5696 RESULT=skip
25955 10:57:15.173916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5696 RESULT=skip>
25956 10:57:15.174331 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5696 RESULT=skip
25958 10:57:15.207856 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5712 RESULT=pass
25960 10:57:15.208286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5712 RESULT=pass>
25961 10:57:15.241713 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5712 RESULT=skip
25963 10:57:15.242174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5712 RESULT=skip>
25964 10:57:15.278812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5712 RESULT=skip>
25965 10:57:15.279191 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5712 RESULT=skip
25967 10:57:15.324451 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5712 RESULT=skip>
25968 10:57:15.324861 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5712 RESULT=skip
25970 10:57:15.369294 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5728 RESULT=pass>
25971 10:57:15.369686 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5728 RESULT=pass
25973 10:57:15.413588 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5728 RESULT=skip>
25974 10:57:15.414015 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5728 RESULT=skip
25976 10:57:15.458459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5728 RESULT=skip>
25977 10:57:15.458861 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5728 RESULT=skip
25979 10:57:15.495108 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5728 RESULT=skip
25981 10:57:15.495548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5728 RESULT=skip>
25982 10:57:15.536752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5744 RESULT=pass>
25983 10:57:15.537191 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5744 RESULT=pass
25985 10:57:15.570550 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5744 RESULT=skip>
25986 10:57:15.570964 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5744 RESULT=skip
25988 10:57:15.605066 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5744 RESULT=skip
25990 10:57:15.605510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5744 RESULT=skip>
25991 10:57:15.639782 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5744 RESULT=skip
25993 10:57:15.640325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5744 RESULT=skip>
25994 10:57:15.676246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5760 RESULT=pass>
25995 10:57:15.676641 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5760 RESULT=pass
25997 10:57:15.709346 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5760 RESULT=skip
25999 10:57:15.709893 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5760 RESULT=skip>
26000 10:57:15.743437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5760 RESULT=skip>
26001 10:57:15.743900 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5760 RESULT=skip
26003 10:57:15.789369 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5760 RESULT=skip>
26004 10:57:15.789800 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5760 RESULT=skip
26006 10:57:15.831958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5776 RESULT=pass>
26007 10:57:15.832369 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5776 RESULT=pass
26009 10:57:15.871890 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5776 RESULT=skip
26011 10:57:15.872361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5776 RESULT=skip>
26012 10:57:15.905634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5776 RESULT=skip>
26013 10:57:15.906065 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5776 RESULT=skip
26015 10:57:15.944663 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5776 RESULT=skip>
26016 10:57:15.945052 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5776 RESULT=skip
26018 10:57:15.985568 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5792 RESULT=pass
26020 10:57:15.986061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5792 RESULT=pass>
26021 10:57:16.030832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5792 RESULT=skip>
26022 10:57:16.031269 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5792 RESULT=skip
26024 10:57:16.074907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5792 RESULT=skip>
26025 10:57:16.075389 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5792 RESULT=skip
26027 10:57:16.119660 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5792 RESULT=skip>
26028 10:57:16.120098 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5792 RESULT=skip
26030 10:57:16.164795 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5808 RESULT=pass>
26031 10:57:16.165192 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5808 RESULT=pass
26033 10:57:16.209321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5808 RESULT=skip>
26034 10:57:16.210099 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5808 RESULT=skip
26036 10:57:16.252498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5808 RESULT=skip>
26037 10:57:16.252910 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5808 RESULT=skip
26039 10:57:16.298286 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5808 RESULT=skip
26041 10:57:16.298743 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5808 RESULT=skip>
26042 10:57:16.347288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5824 RESULT=pass>
26043 10:57:16.347718 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5824 RESULT=pass
26045 10:57:16.397279 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5824 RESULT=skip
26047 10:57:16.397736 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5824 RESULT=skip>
26048 10:57:16.445549 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5824 RESULT=skip>
26049 10:57:16.445999 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5824 RESULT=skip
26051 10:57:16.494688 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5824 RESULT=skip
26053 10:57:16.495118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5824 RESULT=skip>
26054 10:57:16.545881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5840 RESULT=pass>
26055 10:57:16.546227 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5840 RESULT=pass
26057 10:57:16.594354 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5840 RESULT=skip
26059 10:57:16.594788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5840 RESULT=skip>
26060 10:57:16.641529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5840 RESULT=skip>
26061 10:57:16.641935 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5840 RESULT=skip
26063 10:57:16.690315 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5840 RESULT=skip
26065 10:57:16.690757 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5840 RESULT=skip>
26066 10:57:16.768256 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5856 RESULT=pass
26068 10:57:16.769096 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5856 RESULT=pass>
26069 10:57:16.823156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5856 RESULT=skip>
26070 10:57:16.823443 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5856 RESULT=skip
26072 10:57:16.877479 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5856 RESULT=skip
26074 10:57:16.877745 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5856 RESULT=skip>
26075 10:57:16.930024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5856 RESULT=skip>
26076 10:57:16.930314 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5856 RESULT=skip
26078 10:57:16.982708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5872 RESULT=pass>
26079 10:57:16.983000 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5872 RESULT=pass
26081 10:57:17.037905 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5872 RESULT=skip>
26082 10:57:17.038314 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5872 RESULT=skip
26084 10:57:17.089065 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5872 RESULT=skip
26086 10:57:17.089383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5872 RESULT=skip>
26087 10:57:17.138591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5872 RESULT=skip>
26088 10:57:17.138883 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5872 RESULT=skip
26090 10:57:17.190875 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5888 RESULT=pass>
26091 10:57:17.191169 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5888 RESULT=pass
26093 10:57:17.242626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5888 RESULT=skip>
26094 10:57:17.242915 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5888 RESULT=skip
26096 10:57:17.289855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5888 RESULT=skip>
26097 10:57:17.290282 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5888 RESULT=skip
26099 10:57:17.336427 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5888 RESULT=skip
26101 10:57:17.336873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5888 RESULT=skip>
26102 10:57:17.381401 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5904 RESULT=pass>
26103 10:57:17.381823 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5904 RESULT=pass
26105 10:57:17.429948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5904 RESULT=skip>
26106 10:57:17.430369 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5904 RESULT=skip
26108 10:57:17.476185 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5904 RESULT=skip>
26109 10:57:17.476544 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5904 RESULT=skip
26111 10:57:17.522773 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5904 RESULT=skip>
26112 10:57:17.523155 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5904 RESULT=skip
26114 10:57:17.568921 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5920 RESULT=pass
26116 10:57:17.569292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5920 RESULT=pass>
26117 10:57:17.614804 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5920 RESULT=skip
26119 10:57:17.615220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5920 RESULT=skip>
26120 10:57:17.660858 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5920 RESULT=skip>
26121 10:57:17.661230 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5920 RESULT=skip
26123 10:57:17.708775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5920 RESULT=skip>
26124 10:57:17.709129 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5920 RESULT=skip
26126 10:57:17.756684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5936 RESULT=pass>
26127 10:57:17.757089 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5936 RESULT=pass
26129 10:57:17.805005 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5936 RESULT=skip
26131 10:57:17.805374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5936 RESULT=skip>
26132 10:57:17.853348 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5936 RESULT=skip>
26133 10:57:17.853771 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5936 RESULT=skip
26135 10:57:17.901444 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5936 RESULT=skip>
26136 10:57:17.901896 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5936 RESULT=skip
26138 10:57:17.951130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5952 RESULT=pass>
26139 10:57:17.951568 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5952 RESULT=pass
26141 10:57:18.000194 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5952 RESULT=skip
26143 10:57:18.000602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5952 RESULT=skip>
26144 10:57:18.049186 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5952 RESULT=skip>
26145 10:57:18.049570 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5952 RESULT=skip
26147 10:57:18.097446 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5952 RESULT=skip
26149 10:57:18.097884 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5952 RESULT=skip>
26150 10:57:18.142748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5968 RESULT=pass>
26151 10:57:18.143150 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5968 RESULT=pass
26153 10:57:18.192088 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5968 RESULT=skip
26155 10:57:18.192538 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5968 RESULT=skip>
26156 10:57:18.241333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5968 RESULT=skip>
26157 10:57:18.241744 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5968 RESULT=skip
26159 10:57:18.288353 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5968 RESULT=skip>
26160 10:57:18.288774 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5968 RESULT=skip
26162 10:57:18.336324 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5984 RESULT=pass
26164 10:57:18.337073 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5984 RESULT=pass>
26165 10:57:18.385279 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5984 RESULT=skip
26167 10:57:18.385734 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5984 RESULT=skip>
26168 10:57:18.432491 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5984 RESULT=skip
26170 10:57:18.432966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5984 RESULT=skip>
26171 10:57:18.481037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5984 RESULT=skip>
26172 10:57:18.481428 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5984 RESULT=skip
26174 10:57:18.531831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6000 RESULT=pass>
26175 10:57:18.532320 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6000 RESULT=pass
26177 10:57:18.577654 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6000 RESULT=skip>
26178 10:57:18.578037 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6000 RESULT=skip
26180 10:57:18.625810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6000 RESULT=skip>
26181 10:57:18.629722 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6000 RESULT=skip
26183 10:57:18.673457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6000 RESULT=skip>
26184 10:57:18.673881 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6000 RESULT=skip
26186 10:57:18.720937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6016 RESULT=pass>
26187 10:57:18.721351 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6016 RESULT=pass
26189 10:57:18.767049 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6016 RESULT=skip>
26190 10:57:18.767465 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6016 RESULT=skip
26192 10:57:18.813843 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6016 RESULT=skip>
26193 10:57:18.814253 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6016 RESULT=skip
26195 10:57:18.866521 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6016 RESULT=skip>
26196 10:57:18.866943 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6016 RESULT=skip
26198 10:57:18.920660 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6032 RESULT=pass
26200 10:57:18.921091 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6032 RESULT=pass>
26201 10:57:18.973546 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6032 RESULT=skip>
26202 10:57:18.973938 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6032 RESULT=skip
26204 10:57:19.014461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6032 RESULT=skip>
26205 10:57:19.014887 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6032 RESULT=skip
26207 10:57:19.047025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6032 RESULT=skip>
26208 10:57:19.047467 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6032 RESULT=skip
26210 10:57:19.090574 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6048 RESULT=pass
26212 10:57:19.091012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6048 RESULT=pass>
26213 10:57:19.132705 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6048 RESULT=skip
26215 10:57:19.133549 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6048 RESULT=skip>
26216 10:57:19.175217 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6048 RESULT=skip>
26217 10:57:19.175634 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6048 RESULT=skip
26219 10:57:19.209419 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6048 RESULT=skip
26221 10:57:19.209857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6048 RESULT=skip>
26222 10:57:19.245121 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6064 RESULT=pass
26224 10:57:19.245560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6064 RESULT=pass>
26225 10:57:19.279585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6064 RESULT=skip>
26226 10:57:19.279991 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6064 RESULT=skip
26228 10:57:19.316969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6064 RESULT=skip>
26229 10:57:19.317350 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6064 RESULT=skip
26231 10:57:19.351165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6064 RESULT=skip>
26232 10:57:19.351570 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6064 RESULT=skip
26234 10:57:19.386778 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6080 RESULT=pass
26236 10:57:19.387231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6080 RESULT=pass>
26237 10:57:19.429481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6080 RESULT=skip>
26238 10:57:19.429928 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6080 RESULT=skip
26240 10:57:19.474604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6080 RESULT=skip>
26241 10:57:19.474999 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6080 RESULT=skip
26243 10:57:19.517046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6080 RESULT=skip>
26244 10:57:19.517412 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6080 RESULT=skip
26246 10:57:19.555186 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6096 RESULT=pass>
26247 10:57:19.555648 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6096 RESULT=pass
26249 10:57:19.591200 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6096 RESULT=skip>
26250 10:57:19.591605 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6096 RESULT=skip
26252 10:57:19.625289 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6096 RESULT=skip
26254 10:57:19.625750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6096 RESULT=skip>
26255 10:57:19.663444 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6096 RESULT=skip>
26256 10:57:19.663850 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6096 RESULT=skip
26258 10:57:19.702004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6112 RESULT=pass>
26259 10:57:19.702421 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6112 RESULT=pass
26261 10:57:19.739316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6112 RESULT=skip>
26262 10:57:19.739738 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6112 RESULT=skip
26264 10:57:19.777879 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6112 RESULT=skip>
26265 10:57:19.778253 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6112 RESULT=skip
26267 10:57:19.825054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6112 RESULT=skip>
26268 10:57:19.825457 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6112 RESULT=skip
26270 10:57:19.866065 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6128 RESULT=pass>
26271 10:57:19.866482 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6128 RESULT=pass
26273 10:57:19.908676 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6128 RESULT=skip>
26274 10:57:19.909097 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6128 RESULT=skip
26276 10:57:19.949697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6128 RESULT=skip>
26277 10:57:19.950108 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6128 RESULT=skip
26279 10:57:19.983107 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6128 RESULT=skip
26281 10:57:19.983549 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6128 RESULT=skip>
26282 10:57:20.026872 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6144 RESULT=pass
26284 10:57:20.027324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6144 RESULT=pass>
26285 10:57:20.067870 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6144 RESULT=skip
26287 10:57:20.068346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6144 RESULT=skip>
26288 10:57:20.113374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6144 RESULT=skip>
26289 10:57:20.113805 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6144 RESULT=skip
26291 10:57:20.157285 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6144 RESULT=skip>
26292 10:57:20.157675 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6144 RESULT=skip
26294 10:57:20.205886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6160 RESULT=pass>
26295 10:57:20.206284 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6160 RESULT=pass
26297 10:57:20.254649 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6160 RESULT=skip>
26298 10:57:20.255019 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6160 RESULT=skip
26300 10:57:20.304574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6160 RESULT=skip>
26301 10:57:20.304951 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6160 RESULT=skip
26303 10:57:20.353316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6160 RESULT=skip>
26304 10:57:20.353736 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6160 RESULT=skip
26306 10:57:20.401315 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6176 RESULT=pass>
26307 10:57:20.401686 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6176 RESULT=pass
26309 10:57:20.449110 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6176 RESULT=skip>
26310 10:57:20.449512 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6176 RESULT=skip
26312 10:57:20.495046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6176 RESULT=skip>
26313 10:57:20.495492 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6176 RESULT=skip
26315 10:57:20.541546 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6176 RESULT=skip>
26316 10:57:20.541972 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6176 RESULT=skip
26318 10:57:20.587407 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6192 RESULT=pass
26320 10:57:20.587898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6192 RESULT=pass>
26321 10:57:20.632728 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6192 RESULT=skip>
26322 10:57:20.633187 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6192 RESULT=skip
26324 10:57:20.665477 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6192 RESULT=skip>
26325 10:57:20.665881 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6192 RESULT=skip
26327 10:57:20.698456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6192 RESULT=skip>
26328 10:57:20.698879 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6192 RESULT=skip
26330 10:57:20.739511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6208 RESULT=pass>
26331 10:57:20.739927 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6208 RESULT=pass
26333 10:57:20.779280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6208 RESULT=skip>
26334 10:57:20.779694 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6208 RESULT=skip
26336 10:57:20.822403 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6208 RESULT=skip>
26337 10:57:20.822814 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6208 RESULT=skip
26339 10:57:20.857972 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6208 RESULT=skip>
26340 10:57:20.858381 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6208 RESULT=skip
26342 10:57:20.893062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6224 RESULT=pass>
26343 10:57:20.893472 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6224 RESULT=pass
26345 10:57:20.925982 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6224 RESULT=skip
26347 10:57:20.926415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6224 RESULT=skip>
26348 10:57:20.974079 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6224 RESULT=skip
26350 10:57:20.974473 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6224 RESULT=skip>
26351 10:57:21.018002 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6224 RESULT=skip>
26352 10:57:21.018707 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6224 RESULT=skip
26354 10:57:21.065620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6240 RESULT=pass>
26355 10:57:21.066063 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6240 RESULT=pass
26357 10:57:21.111079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6240 RESULT=skip>
26358 10:57:21.111508 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6240 RESULT=skip
26360 10:57:21.149012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6240 RESULT=skip>
26361 10:57:21.149513 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6240 RESULT=skip
26363 10:57:21.195344 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6240 RESULT=skip
26365 10:57:21.195876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6240 RESULT=skip>
26366 10:57:21.243493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6256 RESULT=pass>
26367 10:57:21.243951 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6256 RESULT=pass
26369 10:57:21.288995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6256 RESULT=skip>
26370 10:57:21.289427 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6256 RESULT=skip
26372 10:57:21.336657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6256 RESULT=skip>
26373 10:57:21.337078 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6256 RESULT=skip
26375 10:57:21.382073 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6256 RESULT=skip>
26376 10:57:21.382497 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6256 RESULT=skip
26378 10:57:21.428020 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6272 RESULT=pass
26380 10:57:21.428524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6272 RESULT=pass>
26381 10:57:21.470329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6272 RESULT=skip>
26382 10:57:21.470781 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6272 RESULT=skip
26384 10:57:21.516067 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6272 RESULT=skip
26386 10:57:21.516535 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6272 RESULT=skip>
26387 10:57:21.563611 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6272 RESULT=skip>
26388 10:57:21.564012 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6272 RESULT=skip
26390 10:57:21.609450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6288 RESULT=pass>
26391 10:57:21.609839 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6288 RESULT=pass
26393 10:57:21.655993 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6288 RESULT=skip
26395 10:57:21.656471 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6288 RESULT=skip>
26396 10:57:21.701903 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6288 RESULT=skip>
26397 10:57:21.702359 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6288 RESULT=skip
26399 10:57:21.746992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6288 RESULT=skip>
26400 10:57:21.747427 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6288 RESULT=skip
26402 10:57:21.790908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6304 RESULT=pass>
26403 10:57:21.791363 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6304 RESULT=pass
26405 10:57:21.835394 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6304 RESULT=skip>
26406 10:57:21.835804 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6304 RESULT=skip
26408 10:57:21.903852 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6304 RESULT=skip
26410 10:57:21.904263 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6304 RESULT=skip>
26411 10:57:21.950819 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6304 RESULT=skip
26413 10:57:21.951258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6304 RESULT=skip>
26414 10:57:21.996852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6320 RESULT=pass>
26415 10:57:21.997266 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6320 RESULT=pass
26417 10:57:22.042899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6320 RESULT=skip>
26418 10:57:22.043307 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6320 RESULT=skip
26420 10:57:22.089504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6320 RESULT=skip>
26421 10:57:22.089936 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6320 RESULT=skip
26423 10:57:22.135635 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6320 RESULT=skip>
26424 10:57:22.136049 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6320 RESULT=skip
26426 10:57:22.183229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6336 RESULT=pass>
26427 10:57:22.183647 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6336 RESULT=pass
26429 10:57:22.229975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6336 RESULT=skip>
26430 10:57:22.230395 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6336 RESULT=skip
26432 10:57:22.277039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6336 RESULT=skip>
26433 10:57:22.277459 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6336 RESULT=skip
26435 10:57:22.323210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6336 RESULT=skip>
26436 10:57:22.323591 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6336 RESULT=skip
26438 10:57:22.369855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6352 RESULT=pass>
26439 10:57:22.370276 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6352 RESULT=pass
26441 10:57:22.417571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6352 RESULT=skip>
26442 10:57:22.417992 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6352 RESULT=skip
26444 10:57:22.465423 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6352 RESULT=skip>
26445 10:57:22.465845 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6352 RESULT=skip
26447 10:57:22.511388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6352 RESULT=skip>
26448 10:57:22.511793 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6352 RESULT=skip
26450 10:57:22.558865 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6368 RESULT=pass
26452 10:57:22.559303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6368 RESULT=pass>
26453 10:57:22.605525 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6368 RESULT=skip>
26454 10:57:22.605921 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6368 RESULT=skip
26456 10:57:22.651751 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6368 RESULT=skip
26458 10:57:22.652186 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6368 RESULT=skip>
26459 10:57:22.698295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6368 RESULT=skip>
26460 10:57:22.698676 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6368 RESULT=skip
26462 10:57:22.745246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6384 RESULT=pass>
26463 10:57:22.745654 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6384 RESULT=pass
26465 10:57:22.791799 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6384 RESULT=skip
26467 10:57:22.792149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6384 RESULT=skip>
26468 10:57:22.839236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6384 RESULT=skip>
26469 10:57:22.839649 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6384 RESULT=skip
26471 10:57:22.886268 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6384 RESULT=skip>
26472 10:57:22.886633 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6384 RESULT=skip
26474 10:57:22.933388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6400 RESULT=pass>
26475 10:57:22.933798 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6400 RESULT=pass
26477 10:57:22.979898 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6400 RESULT=skip
26479 10:57:22.980331 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6400 RESULT=skip>
26480 10:57:23.026890 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6400 RESULT=skip>
26481 10:57:23.027259 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6400 RESULT=skip
26483 10:57:23.074406 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6400 RESULT=skip>
26484 10:57:23.074821 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6400 RESULT=skip
26486 10:57:23.121013 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6416 RESULT=pass
26488 10:57:23.121367 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6416 RESULT=pass>
26489 10:57:23.167343 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6416 RESULT=skip>
26490 10:57:23.167737 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6416 RESULT=skip
26492 10:57:23.213757 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6416 RESULT=skip>
26493 10:57:23.214136 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6416 RESULT=skip
26495 10:57:23.260922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6416 RESULT=skip>
26496 10:57:23.261305 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6416 RESULT=skip
26498 10:57:23.306878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6432 RESULT=pass>
26499 10:57:23.307233 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6432 RESULT=pass
26501 10:57:23.353534 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6432 RESULT=skip
26503 10:57:23.353955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6432 RESULT=skip>
26504 10:57:23.399857 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6432 RESULT=skip
26506 10:57:23.400308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6432 RESULT=skip>
26507 10:57:23.446286 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6432 RESULT=skip
26509 10:57:23.446654 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6432 RESULT=skip>
26510 10:57:23.498716 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6448 RESULT=pass>
26511 10:57:23.499130 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6448 RESULT=pass
26513 10:57:23.545515 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6448 RESULT=skip>
26514 10:57:23.545946 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6448 RESULT=skip
26516 10:57:23.592317 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6448 RESULT=skip>
26517 10:57:23.592730 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6448 RESULT=skip
26519 10:57:23.638202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6448 RESULT=skip>
26520 10:57:23.638585 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6448 RESULT=skip
26522 10:57:23.686270 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6464 RESULT=pass
26524 10:57:23.686682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6464 RESULT=pass>
26525 10:57:23.732853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6464 RESULT=skip>
26526 10:57:23.733233 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6464 RESULT=skip
26528 10:57:23.779255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6464 RESULT=skip>
26529 10:57:23.779596 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6464 RESULT=skip
26531 10:57:23.826158 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6464 RESULT=skip>
26532 10:57:23.826538 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6464 RESULT=skip
26534 10:57:23.873470 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6480 RESULT=pass>
26535 10:57:23.873896 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6480 RESULT=pass
26537 10:57:23.920815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6480 RESULT=skip>
26538 10:57:23.921242 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6480 RESULT=skip
26540 10:57:23.967343 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6480 RESULT=skip>
26541 10:57:23.967755 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6480 RESULT=skip
26543 10:57:24.012922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6480 RESULT=skip>
26544 10:57:24.013321 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6480 RESULT=skip
26546 10:57:24.058465 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6496 RESULT=pass
26548 10:57:24.058910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6496 RESULT=pass>
26549 10:57:24.106232 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6496 RESULT=skip
26551 10:57:24.106658 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6496 RESULT=skip>
26552 10:57:24.153050 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6496 RESULT=skip>
26553 10:57:24.153456 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6496 RESULT=skip
26555 10:57:24.197640 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6496 RESULT=skip
26557 10:57:24.198074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6496 RESULT=skip>
26558 10:57:24.241445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6512 RESULT=pass>
26559 10:57:24.241861 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6512 RESULT=pass
26561 10:57:24.282649 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6512 RESULT=skip>
26562 10:57:24.283060 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6512 RESULT=skip
26564 10:57:24.326582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6512 RESULT=skip>
26565 10:57:24.326999 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6512 RESULT=skip
26567 10:57:24.371317 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6512 RESULT=skip>
26568 10:57:24.371672 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6512 RESULT=skip
26570 10:57:24.415297 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6528 RESULT=pass
26572 10:57:24.415721 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6528 RESULT=pass>
26573 10:57:24.461169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6528 RESULT=skip>
26574 10:57:24.461561 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6528 RESULT=skip
26576 10:57:24.507378 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6528 RESULT=skip
26578 10:57:24.507814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6528 RESULT=skip>
26579 10:57:24.553252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6528 RESULT=skip>
26580 10:57:24.553615 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6528 RESULT=skip
26582 10:57:24.600697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6544 RESULT=pass>
26583 10:57:24.601109 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6544 RESULT=pass
26585 10:57:24.644799 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6544 RESULT=skip>
26586 10:57:24.645214 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6544 RESULT=skip
26588 10:57:24.692435 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6544 RESULT=skip>
26589 10:57:24.692832 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6544 RESULT=skip
26591 10:57:24.736099 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6544 RESULT=skip
26593 10:57:24.736532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6544 RESULT=skip>
26594 10:57:24.780882 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6560 RESULT=pass>
26595 10:57:24.781260 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6560 RESULT=pass
26597 10:57:24.824573 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6560 RESULT=skip>
26598 10:57:24.824919 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6560 RESULT=skip
26600 10:57:24.869000 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6560 RESULT=skip>
26601 10:57:24.869401 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6560 RESULT=skip
26603 10:57:24.913238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6560 RESULT=skip>
26604 10:57:24.913653 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6560 RESULT=skip
26606 10:57:24.956877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6576 RESULT=pass>
26607 10:57:24.957283 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6576 RESULT=pass
26609 10:57:25.001273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6576 RESULT=skip>
26610 10:57:25.001660 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6576 RESULT=skip
26612 10:57:25.044879 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6576 RESULT=skip>
26613 10:57:25.045305 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6576 RESULT=skip
26615 10:57:25.088940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6576 RESULT=skip>
26616 10:57:25.089353 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6576 RESULT=skip
26618 10:57:25.133512 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6592 RESULT=pass
26620 10:57:25.133923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6592 RESULT=pass>
26621 10:57:25.171977 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6592 RESULT=skip
26623 10:57:25.172440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6592 RESULT=skip>
26624 10:57:25.216908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6592 RESULT=skip>
26625 10:57:25.217320 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6592 RESULT=skip
26627 10:57:25.261371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6592 RESULT=skip>
26628 10:57:25.261783 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6592 RESULT=skip
26630 10:57:25.304886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6608 RESULT=pass>
26631 10:57:25.305299 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6608 RESULT=pass
26633 10:57:25.344222 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6608 RESULT=skip
26635 10:57:25.344686 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6608 RESULT=skip>
26636 10:57:25.390584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6608 RESULT=skip>
26637 10:57:25.390997 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6608 RESULT=skip
26639 10:57:25.435410 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6608 RESULT=skip
26641 10:57:25.435843 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6608 RESULT=skip>
26642 10:57:25.481118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6624 RESULT=pass>
26643 10:57:25.481519 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6624 RESULT=pass
26645 10:57:25.525766 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6624 RESULT=skip
26647 10:57:25.526199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6624 RESULT=skip>
26648 10:57:25.570066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6624 RESULT=skip>
26649 10:57:25.570475 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6624 RESULT=skip
26651 10:57:25.614528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6624 RESULT=skip>
26652 10:57:25.614937 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6624 RESULT=skip
26654 10:57:25.659965 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6640 RESULT=pass
26656 10:57:25.660429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6640 RESULT=pass>
26657 10:57:25.705447 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6640 RESULT=skip
26659 10:57:25.705859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6640 RESULT=skip>
26660 10:57:25.750010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6640 RESULT=skip>
26661 10:57:25.750410 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6640 RESULT=skip
26663 10:57:25.794905 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6640 RESULT=skip
26665 10:57:25.795324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6640 RESULT=skip>
26666 10:57:25.839098 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6656 RESULT=pass>
26667 10:57:25.839484 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6656 RESULT=pass
26669 10:57:25.883391 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6656 RESULT=skip
26671 10:57:25.883759 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6656 RESULT=skip>
26672 10:57:25.928498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6656 RESULT=skip>
26673 10:57:25.928883 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6656 RESULT=skip
26675 10:57:25.974384 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6656 RESULT=skip>
26676 10:57:25.974734 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6656 RESULT=skip
26678 10:57:26.005986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6672 RESULT=pass>
26679 10:57:26.006391 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6672 RESULT=pass
26681 10:57:26.046132 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6672 RESULT=skip>
26682 10:57:26.046544 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6672 RESULT=skip
26684 10:57:26.091430 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6672 RESULT=skip>
26685 10:57:26.091836 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6672 RESULT=skip
26687 10:57:26.135327 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6672 RESULT=skip>
26688 10:57:26.135734 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6672 RESULT=skip
26690 10:57:26.179896 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6688 RESULT=pass
26692 10:57:26.180490 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6688 RESULT=pass>
26693 10:57:26.226162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6688 RESULT=skip>
26694 10:57:26.226568 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6688 RESULT=skip
26696 10:57:26.268997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6688 RESULT=skip>
26697 10:57:26.269365 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6688 RESULT=skip
26699 10:57:26.313189 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6688 RESULT=skip>
26700 10:57:26.314002 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6688 RESULT=skip
26702 10:57:26.357617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6704 RESULT=pass>
26703 10:57:26.358039 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6704 RESULT=pass
26705 10:57:26.403324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6704 RESULT=skip>
26706 10:57:26.403759 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6704 RESULT=skip
26708 10:57:26.449302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6704 RESULT=skip>
26709 10:57:26.449685 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6704 RESULT=skip
26711 10:57:26.494066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6704 RESULT=skip>
26712 10:57:26.494478 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6704 RESULT=skip
26714 10:57:26.539616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6720 RESULT=pass>
26715 10:57:26.540031 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6720 RESULT=pass
26717 10:57:26.585299 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6720 RESULT=skip>
26718 10:57:26.585688 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6720 RESULT=skip
26720 10:57:26.631137 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6720 RESULT=skip>
26721 10:57:26.631562 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6720 RESULT=skip
26723 10:57:26.676921 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6720 RESULT=skip
26725 10:57:26.677389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6720 RESULT=skip>
26726 10:57:26.720990 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6736 RESULT=pass
26728 10:57:26.721431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6736 RESULT=pass>
26729 10:57:26.765579 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6736 RESULT=skip>
26730 10:57:26.766003 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6736 RESULT=skip
26732 10:57:26.810055 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6736 RESULT=skip>
26733 10:57:26.810465 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6736 RESULT=skip
26735 10:57:26.854866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6736 RESULT=skip>
26736 10:57:26.855254 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6736 RESULT=skip
26738 10:57:26.892206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6752 RESULT=pass>
26739 10:57:26.892577 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6752 RESULT=pass
26741 10:57:26.936465 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6752 RESULT=skip
26743 10:57:26.936903 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6752 RESULT=skip>
26744 10:57:27.004102 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6752 RESULT=skip
26746 10:57:27.004565 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6752 RESULT=skip>
26747 10:57:27.050917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6752 RESULT=skip>
26748 10:57:27.051317 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6752 RESULT=skip
26750 10:57:27.097414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6768 RESULT=pass>
26751 10:57:27.097784 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6768 RESULT=pass
26753 10:57:27.144056 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6768 RESULT=skip
26755 10:57:27.144433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6768 RESULT=skip>
26756 10:57:27.192906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6768 RESULT=skip>
26757 10:57:27.193287 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6768 RESULT=skip
26759 10:57:27.239827 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6768 RESULT=skip
26761 10:57:27.240279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6768 RESULT=skip>
26762 10:57:27.286239 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6784 RESULT=pass>
26763 10:57:27.286640 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6784 RESULT=pass
26765 10:57:27.333192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6784 RESULT=skip>
26766 10:57:27.333599 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6784 RESULT=skip
26768 10:57:27.379133 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6784 RESULT=skip>
26769 10:57:27.379541 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6784 RESULT=skip
26771 10:57:27.426783 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6784 RESULT=skip>
26772 10:57:27.427193 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6784 RESULT=skip
26774 10:57:27.473589 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6800 RESULT=pass>
26775 10:57:27.474020 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6800 RESULT=pass
26777 10:57:27.520023 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6800 RESULT=skip
26779 10:57:27.520441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6800 RESULT=skip>
26780 10:57:27.566362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6800 RESULT=skip>
26781 10:57:27.566774 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6800 RESULT=skip
26783 10:57:27.613025 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6800 RESULT=skip
26785 10:57:27.613483 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6800 RESULT=skip>
26786 10:57:27.658470 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6816 RESULT=pass>
26787 10:57:27.658877 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6816 RESULT=pass
26789 10:57:27.705179 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6816 RESULT=skip>
26790 10:57:27.705594 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6816 RESULT=skip
26792 10:57:27.749922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6816 RESULT=skip>
26793 10:57:27.750359 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6816 RESULT=skip
26795 10:57:27.794743 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6816 RESULT=skip>
26796 10:57:27.795154 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6816 RESULT=skip
26798 10:57:27.838541 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6832 RESULT=pass>
26799 10:57:27.838946 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6832 RESULT=pass
26801 10:57:27.882366 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6832 RESULT=skip
26803 10:57:27.882813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6832 RESULT=skip>
26804 10:57:27.927000 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6832 RESULT=skip>
26805 10:57:27.927410 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6832 RESULT=skip
26807 10:57:27.973350 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6832 RESULT=skip
26809 10:57:27.973793 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6832 RESULT=skip>
26810 10:57:28.018506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6848 RESULT=pass>
26811 10:57:28.018903 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6848 RESULT=pass
26813 10:57:28.061432 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6848 RESULT=skip>
26814 10:57:28.061843 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6848 RESULT=skip
26816 10:57:28.107172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6848 RESULT=skip>
26817 10:57:28.107577 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6848 RESULT=skip
26819 10:57:28.152987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6848 RESULT=skip>
26820 10:57:28.153369 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6848 RESULT=skip
26822 10:57:28.197027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6864 RESULT=pass>
26823 10:57:28.197435 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6864 RESULT=pass
26825 10:57:28.240145 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6864 RESULT=skip
26827 10:57:28.240578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6864 RESULT=skip>
26828 10:57:28.283196 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6864 RESULT=skip>
26829 10:57:28.283599 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6864 RESULT=skip
26831 10:57:28.326900 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6864 RESULT=skip>
26832 10:57:28.327311 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6864 RESULT=skip
26834 10:57:28.372472 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6880 RESULT=pass>
26835 10:57:28.372878 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6880 RESULT=pass
26837 10:57:28.416929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6880 RESULT=skip>
26838 10:57:28.417334 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6880 RESULT=skip
26840 10:57:28.460469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6880 RESULT=skip>
26841 10:57:28.460837 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6880 RESULT=skip
26843 10:57:28.504643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6880 RESULT=skip>
26844 10:57:28.505049 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6880 RESULT=skip
26846 10:57:28.549502 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6896 RESULT=pass
26848 10:57:28.549960 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6896 RESULT=pass>
26849 10:57:28.594029 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6896 RESULT=skip>
26850 10:57:28.594443 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6896 RESULT=skip
26852 10:57:28.639328 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6896 RESULT=skip
26854 10:57:28.639792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6896 RESULT=skip>
26855 10:57:28.686848 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6896 RESULT=skip>
26856 10:57:28.687269 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6896 RESULT=skip
26858 10:57:28.733373 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6912 RESULT=pass>
26859 10:57:28.733804 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6912 RESULT=pass
26861 10:57:28.781244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6912 RESULT=skip>
26862 10:57:28.781670 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6912 RESULT=skip
26864 10:57:28.828451 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6912 RESULT=skip>
26865 10:57:28.828884 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6912 RESULT=skip
26867 10:57:28.877806 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6912 RESULT=skip>
26868 10:57:28.878215 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6912 RESULT=skip
26870 10:57:28.921454 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6928 RESULT=pass>
26871 10:57:28.921873 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6928 RESULT=pass
26873 10:57:28.968046 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6928 RESULT=skip
26875 10:57:28.968469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6928 RESULT=skip>
26876 10:57:29.011767 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6928 RESULT=skip
26878 10:57:29.012212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6928 RESULT=skip>
26879 10:57:29.057987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6928 RESULT=skip>
26880 10:57:29.058393 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6928 RESULT=skip
26882 10:57:29.104047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6944 RESULT=pass>
26883 10:57:29.104461 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6944 RESULT=pass
26885 10:57:29.146049 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6944 RESULT=skip>
26886 10:57:29.146485 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6944 RESULT=skip
26888 10:57:29.188915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6944 RESULT=skip>
26889 10:57:29.189333 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6944 RESULT=skip
26891 10:57:29.232671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6944 RESULT=skip>
26892 10:57:29.233085 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6944 RESULT=skip
26894 10:57:29.267481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6960 RESULT=pass>
26895 10:57:29.267883 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6960 RESULT=pass
26897 10:57:29.311396 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6960 RESULT=skip
26899 10:57:29.311880 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6960 RESULT=skip>
26900 10:57:29.355686 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6960 RESULT=skip
26902 10:57:29.356113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6960 RESULT=skip>
26903 10:57:29.394015 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6960 RESULT=skip
26905 10:57:29.394440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6960 RESULT=skip>
26906 10:57:29.427008 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6976 RESULT=pass>
26907 10:57:29.427384 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6976 RESULT=pass
26909 10:57:29.463139 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6976 RESULT=skip>
26910 10:57:29.463524 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6976 RESULT=skip
26912 10:57:29.503942 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6976 RESULT=skip
26914 10:57:29.504336 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6976 RESULT=skip>
26915 10:57:29.545297 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6976 RESULT=skip>
26916 10:57:29.545690 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6976 RESULT=skip
26918 10:57:29.589959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6992 RESULT=pass>
26919 10:57:29.590395 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6992 RESULT=pass
26921 10:57:29.634867 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6992 RESULT=skip
26923 10:57:29.635338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6992 RESULT=skip>
26924 10:57:29.681702 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6992 RESULT=skip>
26925 10:57:29.682145 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6992 RESULT=skip
26927 10:57:29.726374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6992 RESULT=skip>
26928 10:57:29.726792 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6992 RESULT=skip
26930 10:57:29.769373 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7008 RESULT=pass>
26931 10:57:29.769787 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7008 RESULT=pass
26933 10:57:29.813372 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7008 RESULT=skip>
26934 10:57:29.813801 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7008 RESULT=skip
26936 10:57:29.857340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7008 RESULT=skip>
26937 10:57:29.857755 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7008 RESULT=skip
26939 10:57:29.901201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7008 RESULT=skip>
26940 10:57:29.901609 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7008 RESULT=skip
26942 10:57:29.945192 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7024 RESULT=pass
26944 10:57:29.945655 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7024 RESULT=pass>
26945 10:57:29.990587 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7024 RESULT=skip>
26946 10:57:29.991010 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7024 RESULT=skip
26948 10:57:30.036341 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7024 RESULT=skip>
26949 10:57:30.036770 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7024 RESULT=skip
26951 10:57:30.081316 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7024 RESULT=skip
26953 10:57:30.081761 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7024 RESULT=skip>
26954 10:57:30.124986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7040 RESULT=pass>
26955 10:57:30.125400 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7040 RESULT=pass
26957 10:57:30.168922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7040 RESULT=skip>
26958 10:57:30.169352 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7040 RESULT=skip
26960 10:57:30.214808 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7040 RESULT=skip
26962 10:57:30.215256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7040 RESULT=skip>
26963 10:57:30.259808 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7040 RESULT=skip
26965 10:57:30.260260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7040 RESULT=skip>
26966 10:57:30.305082 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7056 RESULT=pass
26968 10:57:30.305519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7056 RESULT=pass>
26969 10:57:30.353236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7056 RESULT=skip>
26970 10:57:30.353677 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7056 RESULT=skip
26972 10:57:30.399922 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7056 RESULT=skip
26974 10:57:30.400396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7056 RESULT=skip>
26975 10:57:30.442973 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7056 RESULT=skip>
26976 10:57:30.443392 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7056 RESULT=skip
26978 10:57:30.487360 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7072 RESULT=pass>
26979 10:57:30.487763 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7072 RESULT=pass
26981 10:57:30.532613 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7072 RESULT=skip>
26982 10:57:30.533017 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7072 RESULT=skip
26984 10:57:30.577099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7072 RESULT=skip>
26985 10:57:30.577444 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7072 RESULT=skip
26987 10:57:30.610286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7072 RESULT=skip>
26988 10:57:30.610852 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7072 RESULT=skip
26990 10:57:30.657211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7088 RESULT=pass>
26991 10:57:30.657665 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7088 RESULT=pass
26993 10:57:30.703786 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7088 RESULT=skip
26995 10:57:30.704207 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7088 RESULT=skip>
26996 10:57:30.738295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7088 RESULT=skip>
26997 10:57:30.738715 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7088 RESULT=skip
26999 10:57:30.775904 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7088 RESULT=skip
27001 10:57:30.776374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7088 RESULT=skip>
27002 10:57:30.825076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7104 RESULT=pass>
27003 10:57:30.825485 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7104 RESULT=pass
27005 10:57:30.870732 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7104 RESULT=skip>
27006 10:57:30.871153 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7104 RESULT=skip
27008 10:57:30.916755 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7104 RESULT=skip
27010 10:57:30.917171 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7104 RESULT=skip>
27011 10:57:30.962982 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7104 RESULT=skip
27013 10:57:30.963406 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7104 RESULT=skip>
27014 10:57:31.009625 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7120 RESULT=pass>
27015 10:57:31.010055 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7120 RESULT=pass
27017 10:57:31.057877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7120 RESULT=skip>
27018 10:57:31.058302 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7120 RESULT=skip
27020 10:57:31.100761 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7120 RESULT=skip>
27021 10:57:31.101173 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7120 RESULT=skip
27023 10:57:31.151800 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7120 RESULT=skip
27025 10:57:31.152279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7120 RESULT=skip>
27026 10:57:31.201389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7136 RESULT=pass>
27027 10:57:31.201817 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7136 RESULT=pass
27029 10:57:31.250027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7136 RESULT=skip>
27030 10:57:31.250412 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7136 RESULT=skip
27032 10:57:31.295326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7136 RESULT=skip>
27033 10:57:31.295727 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7136 RESULT=skip
27035 10:57:31.333076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7136 RESULT=skip>
27036 10:57:31.333473 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7136 RESULT=skip
27038 10:57:31.375966 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7152 RESULT=pass
27040 10:57:31.376527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7152 RESULT=pass>
27041 10:57:31.421152 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7152 RESULT=skip>
27042 10:57:31.421589 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7152 RESULT=skip
27044 10:57:31.467282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7152 RESULT=skip>
27045 10:57:31.467738 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7152 RESULT=skip
27047 10:57:31.513302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7152 RESULT=skip>
27048 10:57:31.513689 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7152 RESULT=skip
27050 10:57:31.557046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7168 RESULT=pass>
27051 10:57:31.557480 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7168 RESULT=pass
27053 10:57:31.603339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7168 RESULT=skip>
27054 10:57:31.603758 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7168 RESULT=skip
27056 10:57:31.648919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7168 RESULT=skip>
27057 10:57:31.649324 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7168 RESULT=skip
27059 10:57:31.694161 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7168 RESULT=skip>
27060 10:57:31.694569 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7168 RESULT=skip
27062 10:57:31.738397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7184 RESULT=pass>
27063 10:57:31.738796 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7184 RESULT=pass
27065 10:57:31.785724 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7184 RESULT=skip>
27066 10:57:31.786142 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7184 RESULT=skip
27068 10:57:31.832945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7184 RESULT=skip>
27069 10:57:31.833358 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7184 RESULT=skip
27071 10:57:31.877554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7184 RESULT=skip>
27072 10:57:31.877976 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7184 RESULT=skip
27074 10:57:31.921874 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7200 RESULT=pass>
27075 10:57:31.922282 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7200 RESULT=pass
27077 10:57:31.965867 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7200 RESULT=skip
27079 10:57:31.966298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7200 RESULT=skip>
27080 10:57:32.011842 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7200 RESULT=skip
27082 10:57:32.012278 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7200 RESULT=skip>
27083 10:57:32.054834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7200 RESULT=skip>
27084 10:57:32.055241 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7200 RESULT=skip
27086 10:57:32.123101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7216 RESULT=pass>
27087 10:57:32.123521 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7216 RESULT=pass
27089 10:57:32.167978 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7216 RESULT=skip
27091 10:57:32.168430 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7216 RESULT=skip>
27092 10:57:32.214545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7216 RESULT=skip>
27093 10:57:32.214954 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7216 RESULT=skip
27095 10:57:32.256623 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7216 RESULT=skip>
27096 10:57:32.257038 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7216 RESULT=skip
27098 10:57:32.301312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7232 RESULT=pass>
27099 10:57:32.301687 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7232 RESULT=pass
27101 10:57:32.346557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7232 RESULT=skip>
27102 10:57:32.346969 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7232 RESULT=skip
27104 10:57:32.391135 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7232 RESULT=skip
27106 10:57:32.391588 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7232 RESULT=skip>
27107 10:57:32.433157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7232 RESULT=skip>
27108 10:57:32.433518 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7232 RESULT=skip
27110 10:57:32.477877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7248 RESULT=pass>
27111 10:57:32.478249 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7248 RESULT=pass
27113 10:57:32.523273 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7248 RESULT=skip
27115 10:57:32.523711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7248 RESULT=skip>
27116 10:57:32.568328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7248 RESULT=skip>
27117 10:57:32.568721 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7248 RESULT=skip
27119 10:57:32.613029 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7248 RESULT=skip
27121 10:57:32.613446 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7248 RESULT=skip>
27122 10:57:32.658101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7264 RESULT=pass>
27123 10:57:32.658512 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7264 RESULT=pass
27125 10:57:32.704376 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7264 RESULT=skip
27127 10:57:32.704842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7264 RESULT=skip>
27128 10:57:32.749660 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7264 RESULT=skip>
27129 10:57:32.750090 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7264 RESULT=skip
27131 10:57:32.794828 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7264 RESULT=skip>
27132 10:57:32.795236 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7264 RESULT=skip
27134 10:57:32.838869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7280 RESULT=pass>
27135 10:57:32.839272 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7280 RESULT=pass
27137 10:57:32.883850 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7280 RESULT=skip
27139 10:57:32.884295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7280 RESULT=skip>
27140 10:57:32.929296 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7280 RESULT=skip>
27141 10:57:32.929681 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7280 RESULT=skip
27143 10:57:32.973516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7280 RESULT=skip>
27144 10:57:32.973909 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7280 RESULT=skip
27146 10:57:33.015909 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7296 RESULT=pass
27148 10:57:33.016339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7296 RESULT=pass>
27149 10:57:33.060641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7296 RESULT=skip>
27150 10:57:33.061028 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7296 RESULT=skip
27152 10:57:33.105937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7296 RESULT=skip>
27153 10:57:33.106306 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7296 RESULT=skip
27155 10:57:33.151241 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7296 RESULT=skip>
27156 10:57:33.151612 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7296 RESULT=skip
27158 10:57:33.194888 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7312 RESULT=pass
27160 10:57:33.195329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7312 RESULT=pass>
27161 10:57:33.238740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7312 RESULT=skip>
27162 10:57:33.239101 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7312 RESULT=skip
27164 10:57:33.282103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7312 RESULT=skip>
27165 10:57:33.282521 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7312 RESULT=skip
27167 10:57:33.326775 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7312 RESULT=skip
27169 10:57:33.327134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7312 RESULT=skip>
27170 10:57:33.370937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7328 RESULT=pass>
27171 10:57:33.371342 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7328 RESULT=pass
27173 10:57:33.418068 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7328 RESULT=skip
27175 10:57:33.418493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7328 RESULT=skip>
27176 10:57:33.461258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7328 RESULT=skip>
27177 10:57:33.461616 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7328 RESULT=skip
27179 10:57:33.508779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7328 RESULT=skip>
27180 10:57:33.509144 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7328 RESULT=skip
27182 10:57:33.553567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7344 RESULT=pass>
27183 10:57:33.553926 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7344 RESULT=pass
27185 10:57:33.585872 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7344 RESULT=skip
27187 10:57:33.586333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7344 RESULT=skip>
27188 10:57:33.629812 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7344 RESULT=skip
27190 10:57:33.630257 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7344 RESULT=skip>
27191 10:57:33.675056 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7344 RESULT=skip>
27192 10:57:33.681262 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7344 RESULT=skip
27194 10:57:33.728688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7360 RESULT=pass>
27195 10:57:33.729081 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7360 RESULT=pass
27197 10:57:33.783326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7360 RESULT=skip>
27198 10:57:33.783749 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7360 RESULT=skip
27200 10:57:33.832619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7360 RESULT=skip>
27201 10:57:33.832964 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7360 RESULT=skip
27203 10:57:33.865211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7360 RESULT=skip>
27204 10:57:33.865604 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7360 RESULT=skip
27206 10:57:33.900273 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7376 RESULT=pass
27208 10:57:33.900738 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7376 RESULT=pass>
27209 10:57:33.945050 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7376 RESULT=skip>
27210 10:57:33.945473 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7376 RESULT=skip
27212 10:57:33.988840 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7376 RESULT=skip
27214 10:57:33.989277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7376 RESULT=skip>
27215 10:57:34.025100 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7376 RESULT=skip
27217 10:57:34.025559 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7376 RESULT=skip>
27218 10:57:34.066249 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7392 RESULT=pass>
27219 10:57:34.066664 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7392 RESULT=pass
27221 10:57:34.108979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7392 RESULT=skip>
27222 10:57:34.109404 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7392 RESULT=skip
27224 10:57:34.151370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7392 RESULT=skip>
27225 10:57:34.151801 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7392 RESULT=skip
27227 10:57:34.198171 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7392 RESULT=skip>
27228 10:57:34.198557 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7392 RESULT=skip
27230 10:57:34.242356 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7408 RESULT=pass>
27231 10:57:34.242769 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7408 RESULT=pass
27233 10:57:34.286754 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7408 RESULT=skip>
27234 10:57:34.287152 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7408 RESULT=skip
27236 10:57:34.332976 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7408 RESULT=skip>
27237 10:57:34.333358 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7408 RESULT=skip
27239 10:57:34.377541 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7408 RESULT=skip>
27240 10:57:34.377954 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7408 RESULT=skip
27242 10:57:34.421951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7424 RESULT=pass>
27243 10:57:34.422326 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7424 RESULT=pass
27245 10:57:34.466365 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7424 RESULT=skip>
27246 10:57:34.466754 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7424 RESULT=skip
27248 10:57:34.510399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7424 RESULT=skip>
27249 10:57:34.510770 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7424 RESULT=skip
27251 10:57:34.555446 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7424 RESULT=skip
27253 10:57:34.555869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7424 RESULT=skip>
27254 10:57:34.601088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7440 RESULT=pass>
27255 10:57:34.601491 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7440 RESULT=pass
27257 10:57:34.646249 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7440 RESULT=skip
27259 10:57:34.646656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7440 RESULT=skip>
27260 10:57:34.691028 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7440 RESULT=skip>
27261 10:57:34.691385 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7440 RESULT=skip
27263 10:57:34.736724 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7440 RESULT=skip>
27264 10:57:34.737102 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7440 RESULT=skip
27266 10:57:34.770014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7456 RESULT=pass>
27267 10:57:34.770410 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7456 RESULT=pass
27269 10:57:34.814238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7456 RESULT=skip>
27270 10:57:34.814642 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7456 RESULT=skip
27272 10:57:34.849827 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7456 RESULT=skip>
27273 10:57:34.850228 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7456 RESULT=skip
27275 10:57:34.891154 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7456 RESULT=skip>
27276 10:57:34.891528 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7456 RESULT=skip
27278 10:57:34.927184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7472 RESULT=pass>
27279 10:57:34.927595 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7472 RESULT=pass
27281 10:57:34.972810 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7472 RESULT=skip
27283 10:57:34.973225 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7472 RESULT=skip>
27284 10:57:35.017478 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7472 RESULT=skip
27286 10:57:35.017902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7472 RESULT=skip>
27287 10:57:35.062429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7472 RESULT=skip>
27288 10:57:35.062817 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7472 RESULT=skip
27290 10:57:35.108221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7488 RESULT=pass>
27291 10:57:35.108610 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7488 RESULT=pass
27293 10:57:35.158017 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7488 RESULT=skip>
27294 10:57:35.158417 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7488 RESULT=skip
27296 10:57:35.202584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7488 RESULT=skip>
27297 10:57:35.202987 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7488 RESULT=skip
27299 10:57:35.249767 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7488 RESULT=skip>
27300 10:57:35.250131 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7488 RESULT=skip
27302 10:57:35.282278 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7504 RESULT=pass>
27303 10:57:35.282693 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7504 RESULT=pass
27305 10:57:35.326946 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7504 RESULT=skip
27307 10:57:35.327374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7504 RESULT=skip>
27308 10:57:35.370911 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7504 RESULT=skip
27310 10:57:35.371347 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7504 RESULT=skip>
27311 10:57:35.415191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7504 RESULT=skip>
27312 10:57:35.415567 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7504 RESULT=skip
27314 10:57:35.460357 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7520 RESULT=pass>
27315 10:57:35.460776 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7520 RESULT=pass
27317 10:57:35.503048 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7520 RESULT=skip
27319 10:57:35.503470 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7520 RESULT=skip>
27320 10:57:35.545209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7520 RESULT=skip>
27321 10:57:35.545585 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7520 RESULT=skip
27323 10:57:35.589518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7520 RESULT=skip>
27324 10:57:35.589882 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7520 RESULT=skip
27326 10:57:35.632961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7536 RESULT=pass>
27327 10:57:35.633388 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7536 RESULT=pass
27329 10:57:35.677224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7536 RESULT=skip>
27330 10:57:35.677635 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7536 RESULT=skip
27332 10:57:35.711486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7536 RESULT=skip>
27333 10:57:35.711918 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7536 RESULT=skip
27335 10:57:35.754511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7536 RESULT=skip>
27336 10:57:35.754924 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7536 RESULT=skip
27338 10:57:35.799323 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7552 RESULT=pass>
27339 10:57:35.799703 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7552 RESULT=pass
27341 10:57:35.843623 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7552 RESULT=skip>
27342 10:57:35.844015 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7552 RESULT=skip
27344 10:57:35.889017 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7552 RESULT=skip>
27345 10:57:35.889418 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7552 RESULT=skip
27347 10:57:35.935255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7552 RESULT=skip>
27348 10:57:35.935628 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7552 RESULT=skip
27350 10:57:35.972515 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7568 RESULT=pass>
27351 10:57:35.972921 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7568 RESULT=pass
27353 10:57:36.015406 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7568 RESULT=skip>
27354 10:57:36.015821 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7568 RESULT=skip
27356 10:57:36.060503 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7568 RESULT=skip>
27357 10:57:36.060913 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7568 RESULT=skip
27359 10:57:36.105417 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7568 RESULT=skip
27361 10:57:36.105878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7568 RESULT=skip>
27362 10:57:36.150343 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7584 RESULT=pass>
27363 10:57:36.150718 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7584 RESULT=pass
27365 10:57:36.196983 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7584 RESULT=skip
27367 10:57:36.197456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7584 RESULT=skip>
27368 10:57:36.241022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7584 RESULT=skip>
27369 10:57:36.241430 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7584 RESULT=skip
27371 10:57:36.284989 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7584 RESULT=skip>
27372 10:57:36.285404 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7584 RESULT=skip
27374 10:57:36.329200 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7600 RESULT=pass
27376 10:57:36.329631 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7600 RESULT=pass>
27377 10:57:36.373368 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7600 RESULT=skip>
27378 10:57:36.373771 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7600 RESULT=skip
27380 10:57:36.418234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7600 RESULT=skip>
27381 10:57:36.418649 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7600 RESULT=skip
27383 10:57:36.463431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7600 RESULT=skip>
27384 10:57:36.463853 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7600 RESULT=skip
27386 10:57:36.509905 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7616 RESULT=pass
27388 10:57:36.510313 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7616 RESULT=pass>
27389 10:57:36.554618 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7616 RESULT=skip>
27390 10:57:36.554990 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7616 RESULT=skip
27392 10:57:36.601157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7616 RESULT=skip>
27393 10:57:36.601587 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7616 RESULT=skip
27395 10:57:36.646317 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7616 RESULT=skip>
27396 10:57:36.646696 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7616 RESULT=skip
27398 10:57:36.690050 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7632 RESULT=pass
27400 10:57:36.690486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7632 RESULT=pass>
27401 10:57:36.734246 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7632 RESULT=skip
27403 10:57:36.734691 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7632 RESULT=skip>
27404 10:57:36.781211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7632 RESULT=skip>
27405 10:57:36.781626 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7632 RESULT=skip
27407 10:57:36.826506 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7632 RESULT=skip
27409 10:57:36.826956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7632 RESULT=skip>
27410 10:57:36.871318 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7648 RESULT=pass>
27411 10:57:36.871724 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7648 RESULT=pass
27413 10:57:36.915233 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7648 RESULT=skip>
27414 10:57:36.915644 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7648 RESULT=skip
27416 10:57:36.959407 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7648 RESULT=skip>
27417 10:57:36.959801 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7648 RESULT=skip
27419 10:57:37.003273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7648 RESULT=skip>
27420 10:57:37.003697 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7648 RESULT=skip
27422 10:57:37.048756 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7664 RESULT=pass>
27423 10:57:37.049175 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7664 RESULT=pass
27425 10:57:37.094442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7664 RESULT=skip>
27426 10:57:37.094835 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7664 RESULT=skip
27428 10:57:37.136809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7664 RESULT=skip>
27429 10:57:37.137232 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7664 RESULT=skip
27431 10:57:37.170029 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7664 RESULT=skip>
27432 10:57:37.170423 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7664 RESULT=skip
27434 10:57:37.234016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7680 RESULT=pass>
27435 10:57:37.234431 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7680 RESULT=pass
27437 10:57:37.271871 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7680 RESULT=skip
27439 10:57:37.272338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7680 RESULT=skip>
27440 10:57:37.308594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7680 RESULT=skip>
27441 10:57:37.309006 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7680 RESULT=skip
27443 10:57:37.349447 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7680 RESULT=skip>
27444 10:57:37.349871 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7680 RESULT=skip
27446 10:57:37.388992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7696 RESULT=pass>
27447 10:57:37.389400 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7696 RESULT=pass
27449 10:57:37.424737 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7696 RESULT=skip>
27450 10:57:37.425169 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7696 RESULT=skip
27452 10:57:37.469281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7696 RESULT=skip>
27453 10:57:37.469691 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7696 RESULT=skip
27455 10:57:37.505415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7696 RESULT=skip>
27456 10:57:37.505831 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7696 RESULT=skip
27458 10:57:37.548955 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7712 RESULT=pass
27460 10:57:37.549370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7712 RESULT=pass>
27461 10:57:37.589310 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7712 RESULT=skip>
27462 10:57:37.589692 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7712 RESULT=skip
27464 10:57:37.635831 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7712 RESULT=skip
27466 10:57:37.636258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7712 RESULT=skip>
27467 10:57:37.679212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7712 RESULT=skip>
27468 10:57:37.679633 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7712 RESULT=skip
27470 10:57:37.724676 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7728 RESULT=pass>
27471 10:57:37.725099 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7728 RESULT=pass
27473 10:57:37.770772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7728 RESULT=skip>
27474 10:57:37.771196 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7728 RESULT=skip
27476 10:57:37.816540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7728 RESULT=skip>
27477 10:57:37.816969 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7728 RESULT=skip
27479 10:57:37.863046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7728 RESULT=skip>
27480 10:57:37.863385 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7728 RESULT=skip
27482 10:57:37.910629 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7744 RESULT=pass>
27483 10:57:37.911034 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7744 RESULT=pass
27485 10:57:37.957951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7744 RESULT=skip>
27486 10:57:37.958370 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7744 RESULT=skip
27488 10:57:38.002601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7744 RESULT=skip>
27489 10:57:38.003001 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7744 RESULT=skip
27491 10:57:38.047419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7744 RESULT=skip>
27492 10:57:38.047866 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7744 RESULT=skip
27494 10:57:38.092310 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7760 RESULT=pass
27496 10:57:38.092801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7760 RESULT=pass>
27497 10:57:38.136991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7760 RESULT=skip>
27498 10:57:38.137424 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7760 RESULT=skip
27500 10:57:38.181248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7760 RESULT=skip>
27501 10:57:38.181669 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7760 RESULT=skip
27503 10:57:38.228032 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7760 RESULT=skip
27505 10:57:38.228491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7760 RESULT=skip>
27506 10:57:38.271994 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7776 RESULT=pass
27508 10:57:38.272452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7776 RESULT=pass>
27509 10:57:38.307380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7776 RESULT=skip>
27510 10:57:38.307789 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7776 RESULT=skip
27512 10:57:38.354695 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7776 RESULT=skip
27514 10:57:38.355145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7776 RESULT=skip>
27515 10:57:38.402242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7776 RESULT=skip>
27516 10:57:38.402602 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7776 RESULT=skip
27518 10:57:38.449546 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7792 RESULT=pass>
27519 10:57:38.449960 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7792 RESULT=pass
27521 10:57:38.494647 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7792 RESULT=skip>
27522 10:57:38.495097 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7792 RESULT=skip
27524 10:57:38.540051 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7792 RESULT=skip
27526 10:57:38.540431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7792 RESULT=skip>
27527 10:57:38.585146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7792 RESULT=skip>
27528 10:57:38.585528 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7792 RESULT=skip
27530 10:57:38.630965 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7808 RESULT=pass>
27531 10:57:38.631377 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7808 RESULT=pass
27533 10:57:38.675114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7808 RESULT=skip>
27534 10:57:38.675519 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7808 RESULT=skip
27536 10:57:38.714393 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7808 RESULT=skip>
27537 10:57:38.714803 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7808 RESULT=skip
27539 10:57:38.766628 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7808 RESULT=skip>
27540 10:57:38.767029 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7808 RESULT=skip
27542 10:57:38.816872 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7824 RESULT=pass>
27543 10:57:38.817395 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7824 RESULT=pass
27545 10:57:38.850902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7824 RESULT=skip>
27546 10:57:38.851278 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7824 RESULT=skip
27548 10:57:38.887496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7824 RESULT=skip>
27549 10:57:38.887907 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7824 RESULT=skip
27551 10:57:38.937100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7824 RESULT=skip>
27552 10:57:38.937464 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7824 RESULT=skip
27554 10:57:38.982310 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7840 RESULT=pass>
27555 10:57:38.982753 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7840 RESULT=pass
27557 10:57:39.027227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7840 RESULT=skip>
27558 10:57:39.027612 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7840 RESULT=skip
27560 10:57:39.071013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7840 RESULT=skip>
27561 10:57:39.071439 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7840 RESULT=skip
27563 10:57:39.117017 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7840 RESULT=skip>
27564 10:57:39.117445 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7840 RESULT=skip
27566 10:57:39.160928 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7856 RESULT=pass>
27567 10:57:39.161346 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7856 RESULT=pass
27569 10:57:39.207283 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7856 RESULT=skip>
27570 10:57:39.207674 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7856 RESULT=skip
27572 10:57:39.252193 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7856 RESULT=skip
27574 10:57:39.252570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7856 RESULT=skip>
27575 10:57:39.296332 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7856 RESULT=skip
27577 10:57:39.296781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7856 RESULT=skip>
27578 10:57:39.341375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7872 RESULT=pass>
27579 10:57:39.341794 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7872 RESULT=pass
27581 10:57:39.385218 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7872 RESULT=skip>
27582 10:57:39.385623 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7872 RESULT=skip
27584 10:57:39.429299 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7872 RESULT=skip>
27585 10:57:39.429687 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7872 RESULT=skip
27587 10:57:39.473408 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7872 RESULT=skip
27589 10:57:39.473845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7872 RESULT=skip>
27590 10:57:39.517838 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7888 RESULT=pass>
27591 10:57:39.518250 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7888 RESULT=pass
27593 10:57:39.559839 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7888 RESULT=skip
27595 10:57:39.560265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7888 RESULT=skip>
27596 10:57:39.596670 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7888 RESULT=skip
27598 10:57:39.597084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7888 RESULT=skip>
27599 10:57:39.640968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7888 RESULT=skip>
27600 10:57:39.641383 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7888 RESULT=skip
27602 10:57:39.685786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7904 RESULT=pass>
27603 10:57:39.686190 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7904 RESULT=pass
27605 10:57:39.732078 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7904 RESULT=skip
27607 10:57:39.732733 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7904 RESULT=skip>
27608 10:57:39.773997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7904 RESULT=skip>
27609 10:57:39.774403 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7904 RESULT=skip
27611 10:57:39.807452 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7904 RESULT=skip
27613 10:57:39.807849 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7904 RESULT=skip>
27614 10:57:39.840905 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7920 RESULT=pass>
27615 10:57:39.841378 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7920 RESULT=pass
27617 10:57:39.885301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7920 RESULT=skip>
27618 10:57:39.885687 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7920 RESULT=skip
27620 10:57:39.931417 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7920 RESULT=skip>
27621 10:57:39.931831 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7920 RESULT=skip
27623 10:57:39.975213 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7920 RESULT=skip>
27624 10:57:39.975635 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7920 RESULT=skip
27626 10:57:40.018855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7936 RESULT=pass>
27627 10:57:40.019269 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7936 RESULT=pass
27629 10:57:40.062731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7936 RESULT=skip>
27630 10:57:40.063151 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7936 RESULT=skip
27632 10:57:40.107276 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7936 RESULT=skip>
27633 10:57:40.107682 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7936 RESULT=skip
27635 10:57:40.152677 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7936 RESULT=skip>
27636 10:57:40.153088 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7936 RESULT=skip
27638 10:57:40.195480 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7952 RESULT=pass>
27639 10:57:40.195916 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7952 RESULT=pass
27641 10:57:40.240918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7952 RESULT=skip>
27642 10:57:40.241356 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7952 RESULT=skip
27644 10:57:40.285836 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7952 RESULT=skip>
27645 10:57:40.286257 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7952 RESULT=skip
27647 10:57:40.330398 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7952 RESULT=skip
27649 10:57:40.330882 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7952 RESULT=skip>
27650 10:57:40.377085 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7968 RESULT=pass
27652 10:57:40.377524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7968 RESULT=pass>
27653 10:57:40.422513 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7968 RESULT=skip>
27654 10:57:40.422928 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7968 RESULT=skip
27656 10:57:40.468854 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7968 RESULT=skip>
27657 10:57:40.469232 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7968 RESULT=skip
27659 10:57:40.513902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7968 RESULT=skip>
27660 10:57:40.514305 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7968 RESULT=skip
27662 10:57:40.557816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7984 RESULT=pass>
27663 10:57:40.558218 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7984 RESULT=pass
27665 10:57:40.602581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7984 RESULT=skip>
27666 10:57:40.602971 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7984 RESULT=skip
27668 10:57:40.641121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7984 RESULT=skip>
27669 10:57:40.641536 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7984 RESULT=skip
27671 10:57:40.685526 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7984 RESULT=skip>
27672 10:57:40.685959 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7984 RESULT=skip
27674 10:57:40.719207 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8000 RESULT=pass>
27675 10:57:40.719663 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8000 RESULT=pass
27677 10:57:40.761073 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8000 RESULT=skip
27679 10:57:40.761441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8000 RESULT=skip>
27680 10:57:40.805217 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8000 RESULT=skip>
27681 10:57:40.805671 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8000 RESULT=skip
27683 10:57:40.849396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8000 RESULT=skip>
27684 10:57:40.849820 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8000 RESULT=skip
27686 10:57:40.897695 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8016 RESULT=pass
27688 10:57:40.898153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8016 RESULT=pass>
27689 10:57:40.941135 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8016 RESULT=skip>
27690 10:57:40.941561 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8016 RESULT=skip
27692 10:57:40.989330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8016 RESULT=skip>
27693 10:57:40.989783 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8016 RESULT=skip
27695 10:57:41.034191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8016 RESULT=skip>
27696 10:57:41.034635 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8016 RESULT=skip
27698 10:57:41.079953 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8032 RESULT=pass
27700 10:57:41.080427 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8032 RESULT=pass>
27701 10:57:41.124030 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8032 RESULT=skip
27703 10:57:41.124516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8032 RESULT=skip>
27704 10:57:41.169083 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8032 RESULT=skip
27706 10:57:41.169567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8032 RESULT=skip>
27707 10:57:41.212811 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8032 RESULT=skip
27709 10:57:41.213255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8032 RESULT=skip>
27710 10:57:41.256872 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8048 RESULT=pass>
27711 10:57:41.257299 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8048 RESULT=pass
27713 10:57:41.301360 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8048 RESULT=skip>
27714 10:57:41.301746 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8048 RESULT=skip
27716 10:57:41.347008 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8048 RESULT=skip
27718 10:57:41.347396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8048 RESULT=skip>
27719 10:57:41.392510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8048 RESULT=skip>
27720 10:57:41.392922 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8048 RESULT=skip
27722 10:57:41.436755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8064 RESULT=pass>
27723 10:57:41.437164 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8064 RESULT=pass
27725 10:57:41.480992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8064 RESULT=skip>
27726 10:57:41.481402 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8064 RESULT=skip
27728 10:57:41.524654 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8064 RESULT=skip>
27729 10:57:41.525035 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8064 RESULT=skip
27731 10:57:41.567919 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8064 RESULT=skip
27733 10:57:41.568375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8064 RESULT=skip>
27734 10:57:41.613148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8080 RESULT=pass>
27735 10:57:41.613654 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8080 RESULT=pass
27737 10:57:41.657943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8080 RESULT=skip>
27738 10:57:41.658377 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8080 RESULT=skip
27740 10:57:41.701479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8080 RESULT=skip>
27741 10:57:41.701900 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8080 RESULT=skip
27743 10:57:41.746468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8080 RESULT=skip>
27744 10:57:41.746913 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8080 RESULT=skip
27746 10:57:41.789334 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8096 RESULT=pass
27748 10:57:41.789820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8096 RESULT=pass>
27749 10:57:41.833126 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8096 RESULT=skip
27751 10:57:41.833588 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8096 RESULT=skip>
27752 10:57:41.876546 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8096 RESULT=skip>
27753 10:57:41.876970 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8096 RESULT=skip
27755 10:57:41.921566 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8096 RESULT=skip>
27756 10:57:41.922006 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8096 RESULT=skip
27758 10:57:41.966882 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8112 RESULT=pass
27760 10:57:41.967348 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8112 RESULT=pass>
27761 10:57:42.005180 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8112 RESULT=skip
27763 10:57:42.005662 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8112 RESULT=skip>
27764 10:57:42.048499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8112 RESULT=skip>
27765 10:57:42.048929 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8112 RESULT=skip
27767 10:57:42.092698 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8112 RESULT=skip
27769 10:57:42.093155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8112 RESULT=skip>
27770 10:57:42.137311 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8128 RESULT=pass
27772 10:57:42.137771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8128 RESULT=pass>
27773 10:57:42.181913 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8128 RESULT=skip>
27774 10:57:42.182341 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8128 RESULT=skip
27776 10:57:42.228986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8128 RESULT=skip>
27777 10:57:42.229434 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8128 RESULT=skip
27779 10:57:42.272815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8128 RESULT=skip>
27780 10:57:42.273250 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8128 RESULT=skip
27782 10:57:42.324678 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8144 RESULT=pass>
27783 10:57:42.325103 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8144 RESULT=pass
27785 10:57:42.383024 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8144 RESULT=skip
27787 10:57:42.383476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8144 RESULT=skip>
27788 10:57:42.428664 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8144 RESULT=skip
27790 10:57:42.429082 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8144 RESULT=skip>
27791 10:57:42.474125 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8144 RESULT=skip>
27792 10:57:42.474563 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8144 RESULT=skip
27794 10:57:42.522395 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8160 RESULT=pass>
27795 10:57:42.522817 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8160 RESULT=pass
27797 10:57:42.568500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8160 RESULT=skip>
27798 10:57:42.568942 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8160 RESULT=skip
27800 10:57:42.613607 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8160 RESULT=skip
27802 10:57:42.614051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8160 RESULT=skip>
27803 10:57:42.659793 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8160 RESULT=skip
27805 10:57:42.660225 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8160 RESULT=skip>
27806 10:57:42.704685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8176 RESULT=pass>
27807 10:57:42.705127 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8176 RESULT=pass
27809 10:57:42.751311 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8176 RESULT=skip>
27810 10:57:42.751745 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8176 RESULT=skip
27812 10:57:42.799399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8176 RESULT=skip>
27813 10:57:42.799810 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8176 RESULT=skip
27815 10:57:42.842651 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8176 RESULT=skip>
27816 10:57:42.843034 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8176 RESULT=skip
27818 10:57:42.888561 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8192 RESULT=pass
27820 10:57:42.889031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8192 RESULT=pass>
27821 10:57:42.933152 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8192 RESULT=skip>
27822 10:57:42.933592 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8192 RESULT=skip
27824 10:57:42.977861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8192 RESULT=skip>
27825 10:57:42.978288 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8192 RESULT=skip
27827 10:57:43.021934 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8192 RESULT=skip>
27828 10:57:43.022357 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8192 RESULT=skip
27830 10:57:43.066881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace RESULT=pass>
27831 10:57:43.067307 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace RESULT=pass
27833 10:57:43.112836 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-probe-vls_Enumerated_16_vector_lengths RESULT=pass
27835 10:57:43.113292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-probe-vls_Enumerated_16_vector_lengths RESULT=pass>
27836 10:57:43.158301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-probe-vls_All_vector_lengths_valid RESULT=pass>
27837 10:57:43.158754 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-probe-vls_All_vector_lengths_valid RESULT=pass
27839 10:57:43.200939 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-probe-vls RESULT=pass>
27840 10:57:43.201351 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-probe-vls RESULT=pass
27842 10:57:43.245141 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_default_vector_length_64 RESULT=pass>
27843 10:57:43.245532 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_default_vector_length_64 RESULT=pass
27845 10:57:43.288636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_minimum_vector_length_16 RESULT=pass>
27846 10:57:43.289044 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_minimum_vector_length_16 RESULT=pass
27848 10:57:43.332801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_maximum_vector_length_256 RESULT=pass>
27849 10:57:43.333201 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_maximum_vector_length_256 RESULT=pass
27851 10:57:43.376857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_current_VL_is_64 RESULT=pass>
27852 10:57:43.377275 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_current_VL_is_64 RESULT=pass
27854 10:57:43.422401 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_set_VL_64_and_have_VL_64 RESULT=pass>
27855 10:57:43.422829 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_set_VL_64_and_have_VL_64 RESULT=pass
27857 10:57:43.466235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_prctl_set_min_max RESULT=pass>
27858 10:57:43.466649 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_prctl_set_min_max RESULT=pass
27860 10:57:43.509719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_vector_length_used_default RESULT=pass>
27861 10:57:43.510137 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_vector_length_used_default RESULT=pass
27863 10:57:43.552993 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_vector_length_was_inherited RESULT=pass>
27864 10:57:43.553361 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_vector_length_was_inherited RESULT=pass
27866 10:57:43.598181 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_vector_length_set_on_exec RESULT=pass>
27867 10:57:43.598575 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_vector_length_set_on_exec RESULT=pass
27869 10:57:43.640637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_prctl_set_all_VLs_0_errors RESULT=pass>
27870 10:57:43.641046 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_prctl_set_all_VLs_0_errors RESULT=pass
27872 10:57:43.685411 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_default_vector_length_32 RESULT=pass
27874 10:57:43.685897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_default_vector_length_32 RESULT=pass>
27875 10:57:43.735871 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_minimum_vector_length_16 RESULT=pass
27877 10:57:43.736304 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_minimum_vector_length_16 RESULT=pass>
27878 10:57:43.784627 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_maximum_vector_length_256 RESULT=pass
27880 10:57:43.785073 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_maximum_vector_length_256 RESULT=pass>
27881 10:57:43.832109 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_current_VL_is_32 RESULT=pass
27883 10:57:43.832582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_current_VL_is_32 RESULT=pass>
27884 10:57:43.878363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_set_VL_32_and_have_VL_32 RESULT=pass>
27885 10:57:43.878740 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_set_VL_32_and_have_VL_32 RESULT=pass
27887 10:57:43.923294 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_prctl_set_min_max RESULT=pass>
27888 10:57:43.923714 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_prctl_set_min_max RESULT=pass
27890 10:57:43.973716 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_vector_length_used_default RESULT=pass>
27891 10:57:43.974132 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_vector_length_used_default RESULT=pass
27893 10:57:44.027342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_vector_length_was_inherited RESULT=pass>
27894 10:57:44.027794 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_vector_length_was_inherited RESULT=pass
27896 10:57:44.073419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_vector_length_set_on_exec RESULT=pass>
27897 10:57:44.073851 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_vector_length_set_on_exec RESULT=pass
27899 10:57:44.118004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_prctl_set_all_VLs_0_errors RESULT=pass>
27900 10:57:44.118423 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_prctl_set_all_VLs_0_errors RESULT=pass
27902 10:57:44.164768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg RESULT=pass>
27903 10:57:44.165183 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg RESULT=pass
27905 10:57:44.208818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-fork_fork_test RESULT=pass>
27906 10:57:44.209234 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-fork_fork_test RESULT=pass
27908 10:57:44.254059 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-fork RESULT=pass
27910 10:57:44.254521 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-fork RESULT=pass>
27911 10:57:44.299015 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_16 RESULT=pass>
27912 10:57:44.299443 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_16 RESULT=pass
27914 10:57:44.343015 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_16 RESULT=pass>
27915 10:57:44.343423 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_16 RESULT=pass
27917 10:57:44.387343 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Data_match_for_VL_16 RESULT=pass
27919 10:57:44.387787 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Data_match_for_VL_16 RESULT=pass>
27920 10:57:44.430857 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_32 RESULT=pass
27922 10:57:44.431289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_32 RESULT=pass>
27923 10:57:44.475540 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_32 RESULT=pass
27925 10:57:44.475983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_32 RESULT=pass>
27926 10:57:44.519659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Data_match_for_VL_32 RESULT=pass>
27927 10:57:44.520062 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Data_match_for_VL_32 RESULT=pass
27929 10:57:44.564721 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_48 RESULT=pass>
27930 10:57:44.565148 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_48 RESULT=pass
27932 10:57:44.608857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_48 RESULT=skip>
27933 10:57:44.609257 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_48 RESULT=skip
27935 10:57:44.649094 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_48 RESULT=skip
27937 10:57:44.649566 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_48 RESULT=skip>
27938 10:57:44.689258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_64 RESULT=pass>
27939 10:57:44.689697 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_64 RESULT=pass
27941 10:57:44.733922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_64 RESULT=pass>
27942 10:57:44.734324 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_64 RESULT=pass
27944 10:57:44.778572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Data_match_for_VL_64 RESULT=pass>
27945 10:57:44.778909 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Data_match_for_VL_64 RESULT=pass
27947 10:57:44.818960 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_80 RESULT=pass>
27948 10:57:44.819369 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_80 RESULT=pass
27950 10:57:44.863634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_80 RESULT=skip>
27951 10:57:44.864046 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_80 RESULT=skip
27953 10:57:44.907983 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_80 RESULT=skip
27955 10:57:44.908390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_80 RESULT=skip>
27956 10:57:44.951900 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_96 RESULT=pass
27958 10:57:44.952325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_96 RESULT=pass>
27959 10:57:44.994274 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_96 RESULT=skip
27961 10:57:44.994702 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_96 RESULT=skip>
27962 10:57:45.040320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_96 RESULT=skip>
27963 10:57:45.040729 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_96 RESULT=skip
27965 10:57:45.085852 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_112 RESULT=pass
27967 10:57:45.086328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_112 RESULT=pass>
27968 10:57:45.129058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_112 RESULT=skip>
27969 10:57:45.129487 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_112 RESULT=skip
27971 10:57:45.173159 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_112 RESULT=skip>
27972 10:57:45.173579 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_112 RESULT=skip
27974 10:57:45.219345 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_128 RESULT=pass
27976 10:57:45.219782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_128 RESULT=pass>
27977 10:57:45.263444 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_128 RESULT=pass>
27978 10:57:45.263847 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_128 RESULT=pass
27980 10:57:45.309510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Data_match_for_VL_128 RESULT=pass>
27981 10:57:45.309956 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Data_match_for_VL_128 RESULT=pass
27983 10:57:45.352371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_144 RESULT=pass>
27984 10:57:45.352810 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_144 RESULT=pass
27986 10:57:45.397107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_144 RESULT=skip>
27987 10:57:45.397542 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_144 RESULT=skip
27989 10:57:45.440877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_144 RESULT=skip>
27990 10:57:45.441265 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_144 RESULT=skip
27992 10:57:45.483472 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_160 RESULT=pass>
27993 10:57:45.483900 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_160 RESULT=pass
27995 10:57:45.528766 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_160 RESULT=skip>
27996 10:57:45.529146 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_160 RESULT=skip
27998 10:57:45.571407 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_160 RESULT=skip>
27999 10:57:45.571752 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_160 RESULT=skip
28001 10:57:45.612493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_176 RESULT=pass>
28002 10:57:45.612906 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_176 RESULT=pass
28004 10:57:45.659048 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_176 RESULT=skip
28006 10:57:45.659481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_176 RESULT=skip>
28007 10:57:45.703725 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_176 RESULT=skip
28009 10:57:45.704163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_176 RESULT=skip>
28010 10:57:45.747040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_192 RESULT=pass>
28011 10:57:45.747436 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_192 RESULT=pass
28013 10:57:45.790973 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_192 RESULT=skip>
28014 10:57:45.791384 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_192 RESULT=skip
28016 10:57:45.835286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_192 RESULT=skip>
28017 10:57:45.835667 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_192 RESULT=skip
28019 10:57:45.877918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_208 RESULT=pass>
28020 10:57:45.878333 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_208 RESULT=pass
28022 10:57:45.922872 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_208 RESULT=skip>
28023 10:57:45.923292 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_208 RESULT=skip
28025 10:57:45.967304 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_208 RESULT=skip>
28026 10:57:45.967716 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_208 RESULT=skip
28028 10:57:46.011832 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_224 RESULT=pass
28030 10:57:46.012276 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_224 RESULT=pass>
28031 10:57:46.057557 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_224 RESULT=skip
28033 10:57:46.058015 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_224 RESULT=skip>
28034 10:57:46.103552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_224 RESULT=skip>
28035 10:57:46.103946 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_224 RESULT=skip
28037 10:57:46.147605 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_240 RESULT=pass
28039 10:57:46.148038 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_240 RESULT=pass>
28040 10:57:46.191483 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_240 RESULT=skip>
28041 10:57:46.191903 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_240 RESULT=skip
28043 10:57:46.234484 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_240 RESULT=skip>
28044 10:57:46.234907 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_240 RESULT=skip
28046 10:57:46.280505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_256 RESULT=pass>
28047 10:57:46.280937 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_256 RESULT=pass
28049 10:57:46.324945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_256 RESULT=pass>
28050 10:57:46.325365 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_256 RESULT=pass
28052 10:57:46.368697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Data_match_for_VL_256 RESULT=pass>
28053 10:57:46.369139 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Data_match_for_VL_256 RESULT=pass
28055 10:57:46.411741 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_272 RESULT=pass
28057 10:57:46.412190 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_272 RESULT=pass>
28058 10:57:46.457160 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_272 RESULT=skip>
28059 10:57:46.457570 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_272 RESULT=skip
28061 10:57:46.501337 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_272 RESULT=skip>
28062 10:57:46.501688 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_272 RESULT=skip
28064 10:57:46.546371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_288 RESULT=pass>
28065 10:57:46.546738 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_288 RESULT=pass
28067 10:57:46.588633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_288 RESULT=skip>
28068 10:57:46.589048 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_288 RESULT=skip
28070 10:57:46.632617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_288 RESULT=skip>
28071 10:57:46.633016 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_288 RESULT=skip
28073 10:57:46.675684 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_304 RESULT=pass
28075 10:57:46.676123 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_304 RESULT=pass>
28076 10:57:46.720784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_304 RESULT=skip>
28077 10:57:46.721195 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_304 RESULT=skip
28079 10:57:46.765159 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_304 RESULT=skip>
28080 10:57:46.765576 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_304 RESULT=skip
28082 10:57:46.810835 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_320 RESULT=pass>
28083 10:57:46.811255 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_320 RESULT=pass
28085 10:57:46.855201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_320 RESULT=skip>
28086 10:57:46.855626 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_320 RESULT=skip
28088 10:57:46.900403 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_320 RESULT=skip>
28089 10:57:46.900813 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_320 RESULT=skip
28091 10:57:46.944793 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_336 RESULT=pass
28093 10:57:46.945240 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_336 RESULT=pass>
28094 10:57:46.989118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_336 RESULT=skip>
28095 10:57:46.989540 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_336 RESULT=skip
28097 10:57:47.036936 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_336 RESULT=skip
28099 10:57:47.037339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_336 RESULT=skip>
28100 10:57:47.079912 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_352 RESULT=pass
28102 10:57:47.080383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_352 RESULT=pass>
28103 10:57:47.124672 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_352 RESULT=skip>
28104 10:57:47.125066 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_352 RESULT=skip
28106 10:57:47.167307 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_352 RESULT=skip>
28107 10:57:47.167726 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_352 RESULT=skip
28109 10:57:47.211540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_368 RESULT=pass>
28110 10:57:47.211921 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_368 RESULT=pass
28112 10:57:47.254693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_368 RESULT=skip>
28113 10:57:47.255083 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_368 RESULT=skip
28115 10:57:47.300883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_368 RESULT=skip>
28116 10:57:47.301268 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_368 RESULT=skip
28118 10:57:47.345014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_384 RESULT=pass>
28119 10:57:47.345424 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_384 RESULT=pass
28121 10:57:47.389633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_384 RESULT=skip>
28122 10:57:47.390037 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_384 RESULT=skip
28124 10:57:47.441652 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_384 RESULT=skip
28126 10:57:47.442093 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_384 RESULT=skip>
28127 10:57:47.505264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_400 RESULT=pass>
28128 10:57:47.505666 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_400 RESULT=pass
28130 10:57:47.549566 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_400 RESULT=skip>
28131 10:57:47.549991 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_400 RESULT=skip
28133 10:57:47.594134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_400 RESULT=skip>
28134 10:57:47.594520 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_400 RESULT=skip
28136 10:57:47.637890 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_416 RESULT=pass>
28137 10:57:47.638279 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_416 RESULT=pass
28139 10:57:47.682111 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_416 RESULT=skip
28141 10:57:47.682520 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_416 RESULT=skip>
28142 10:57:47.726272 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_416 RESULT=skip>
28143 10:57:47.726692 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_416 RESULT=skip
28145 10:57:47.769948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_432 RESULT=pass>
28146 10:57:47.770369 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_432 RESULT=pass
28148 10:57:47.813145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_432 RESULT=skip>
28149 10:57:47.813561 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_432 RESULT=skip
28151 10:57:47.856974 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_432 RESULT=skip>
28152 10:57:47.857392 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_432 RESULT=skip
28154 10:57:47.901121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_448 RESULT=pass>
28155 10:57:47.901530 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_448 RESULT=pass
28157 10:57:47.944896 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_448 RESULT=skip
28159 10:57:47.945336 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_448 RESULT=skip>
28160 10:57:47.989001 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_448 RESULT=skip
28162 10:57:47.989450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_448 RESULT=skip>
28163 10:57:48.031837 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_464 RESULT=pass
28165 10:57:48.032271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_464 RESULT=pass>
28166 10:57:48.075961 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_464 RESULT=skip
28168 10:57:48.076382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_464 RESULT=skip>
28169 10:57:48.119792 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_464 RESULT=skip
28171 10:57:48.120228 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_464 RESULT=skip>
28172 10:57:48.162837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_480 RESULT=pass>
28173 10:57:48.163268 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_480 RESULT=pass
28175 10:57:48.208792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_480 RESULT=skip>
28176 10:57:48.209190 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_480 RESULT=skip
28178 10:57:48.255080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_480 RESULT=skip>
28179 10:57:48.255496 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_480 RESULT=skip
28181 10:57:48.297333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_496 RESULT=pass>
28182 10:57:48.297787 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_496 RESULT=pass
28184 10:57:48.341981 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_496 RESULT=skip>
28185 10:57:48.342377 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_496 RESULT=skip
28187 10:57:48.386242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_496 RESULT=skip>
28188 10:57:48.386651 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_496 RESULT=skip
28190 10:57:48.430235 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_512 RESULT=pass
28192 10:57:48.430675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_512 RESULT=pass>
28193 10:57:48.474757 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_512 RESULT=skip>
28194 10:57:48.475152 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_512 RESULT=skip
28196 10:57:48.520441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_512 RESULT=skip>
28197 10:57:48.520884 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_512 RESULT=skip
28199 10:57:48.563336 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_528 RESULT=pass>
28200 10:57:48.563776 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_528 RESULT=pass
28202 10:57:48.607502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_528 RESULT=skip>
28203 10:57:48.607938 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_528 RESULT=skip
28205 10:57:48.651209 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_528 RESULT=skip
28207 10:57:48.651688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_528 RESULT=skip>
28208 10:57:48.694943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_544 RESULT=pass>
28209 10:57:48.697706 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_544 RESULT=pass
28211 10:57:48.741621 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_544 RESULT=skip
28213 10:57:48.742085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_544 RESULT=skip>
28214 10:57:48.787984 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_544 RESULT=skip
28216 10:57:48.788544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_544 RESULT=skip>
28217 10:57:48.833040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_560 RESULT=pass>
28218 10:57:48.833486 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_560 RESULT=pass
28220 10:57:48.878287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_560 RESULT=skip>
28221 10:57:48.878709 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_560 RESULT=skip
28223 10:57:48.924640 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_560 RESULT=skip
28225 10:57:48.925094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_560 RESULT=skip>
28226 10:57:48.969792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_576 RESULT=pass>
28227 10:57:48.970489 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_576 RESULT=pass
28229 10:57:48.976817 <47>[ 300.504390] systemd-journald[105]: Sent WATCHDOG=1 notification.
28230 10:57:49.023102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_576 RESULT=skip>
28231 10:57:49.023485 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_576 RESULT=skip
28233 10:57:49.069188 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_576 RESULT=skip
28235 10:57:49.069691 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_576 RESULT=skip>
28236 10:57:49.114762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_592 RESULT=pass>
28237 10:57:49.115157 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_592 RESULT=pass
28239 10:57:49.161987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_592 RESULT=skip>
28240 10:57:49.162407 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_592 RESULT=skip
28242 10:57:49.209355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_592 RESULT=skip>
28243 10:57:49.209782 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_592 RESULT=skip
28245 10:57:49.255468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_608 RESULT=pass>
28246 10:57:49.255892 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_608 RESULT=pass
28248 10:57:49.301656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_608 RESULT=skip>
28249 10:57:49.302071 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_608 RESULT=skip
28251 10:57:49.347904 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_608 RESULT=skip
28253 10:57:49.348346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_608 RESULT=skip>
28254 10:57:49.392407 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_624 RESULT=pass>
28255 10:57:49.392832 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_624 RESULT=pass
28257 10:57:49.437316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_624 RESULT=skip>
28258 10:57:49.437685 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_624 RESULT=skip
28260 10:57:49.482455 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_624 RESULT=skip>
28261 10:57:49.482887 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_624 RESULT=skip
28263 10:57:49.526147 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_640 RESULT=pass>
28264 10:57:49.526560 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_640 RESULT=pass
28266 10:57:49.569812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_640 RESULT=skip>
28267 10:57:49.570231 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_640 RESULT=skip
28269 10:57:49.614850 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_640 RESULT=skip>
28270 10:57:49.615267 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_640 RESULT=skip
28272 10:57:49.659497 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_656 RESULT=pass>
28273 10:57:49.659905 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_656 RESULT=pass
28275 10:57:49.705257 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_656 RESULT=skip>
28276 10:57:49.705678 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_656 RESULT=skip
28278 10:57:49.754909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_656 RESULT=skip>
28279 10:57:49.755365 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_656 RESULT=skip
28281 10:57:49.797056 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_672 RESULT=pass>
28282 10:57:49.797476 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_672 RESULT=pass
28284 10:57:49.841456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_672 RESULT=skip>
28285 10:57:49.841912 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_672 RESULT=skip
28287 10:57:49.895080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_672 RESULT=skip>
28288 10:57:49.895508 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_672 RESULT=skip
28290 10:57:49.946637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_688 RESULT=pass>
28291 10:57:49.947062 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_688 RESULT=pass
28293 10:57:50.000664 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_688 RESULT=skip>
28294 10:57:50.001094 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_688 RESULT=skip
28296 10:57:50.043095 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_688 RESULT=skip>
28297 10:57:50.043518 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_688 RESULT=skip
28299 10:57:50.075379 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_704 RESULT=pass
28301 10:57:50.075866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_704 RESULT=pass>
28302 10:57:50.109041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_704 RESULT=skip>
28303 10:57:50.109477 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_704 RESULT=skip
28305 10:57:50.148264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_704 RESULT=skip>
28306 10:57:50.148648 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_704 RESULT=skip
28308 10:57:50.182257 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_720 RESULT=pass>
28309 10:57:50.182667 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_720 RESULT=pass
28311 10:57:50.216297 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_720 RESULT=skip>
28312 10:57:50.216736 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_720 RESULT=skip
28314 10:57:50.253011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_720 RESULT=skip>
28315 10:57:50.253459 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_720 RESULT=skip
28317 10:57:50.296932 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_736 RESULT=pass
28319 10:57:50.297378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_736 RESULT=pass>
28320 10:57:50.343576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_736 RESULT=skip>
28321 10:57:50.343936 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_736 RESULT=skip
28323 10:57:50.389371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_736 RESULT=skip>
28324 10:57:50.389779 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_736 RESULT=skip
28326 10:57:50.436529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_752 RESULT=pass>
28327 10:57:50.436907 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_752 RESULT=pass
28329 10:57:50.482756 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_752 RESULT=skip>
28330 10:57:50.483173 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_752 RESULT=skip
28332 10:57:50.529792 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_752 RESULT=skip
28334 10:57:50.530188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_752 RESULT=skip>
28335 10:57:50.579035 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_768 RESULT=pass>
28336 10:57:50.579475 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_768 RESULT=pass
28338 10:57:50.625786 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_768 RESULT=skip
28340 10:57:50.626245 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_768 RESULT=skip>
28341 10:57:50.672385 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_768 RESULT=skip>
28342 10:57:50.672772 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_768 RESULT=skip
28344 10:57:50.717962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_784 RESULT=pass>
28345 10:57:50.718365 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_784 RESULT=pass
28347 10:57:50.765210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_784 RESULT=skip>
28348 10:57:50.765598 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_784 RESULT=skip
28350 10:57:50.811307 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_784 RESULT=skip>
28351 10:57:50.811689 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_784 RESULT=skip
28353 10:57:50.857476 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_800 RESULT=pass
28355 10:57:50.857934 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_800 RESULT=pass>
28356 10:57:50.903065 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_800 RESULT=skip>
28357 10:57:50.903496 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_800 RESULT=skip
28359 10:57:50.949430 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_800 RESULT=skip
28361 10:57:50.949887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_800 RESULT=skip>
28362 10:57:50.994944 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_816 RESULT=pass>
28363 10:57:50.995394 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_816 RESULT=pass
28365 10:57:51.041288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_816 RESULT=skip>
28366 10:57:51.041683 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_816 RESULT=skip
28368 10:57:51.087290 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_816 RESULT=skip
28370 10:57:51.087761 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_816 RESULT=skip>
28371 10:57:51.134118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_832 RESULT=pass>
28372 10:57:51.134531 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_832 RESULT=pass
28374 10:57:51.179623 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_832 RESULT=skip
28376 10:57:51.180033 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_832 RESULT=skip>
28377 10:57:51.225544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_832 RESULT=skip>
28378 10:57:51.225996 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_832 RESULT=skip
28380 10:57:51.270892 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_848 RESULT=pass>
28381 10:57:51.271331 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_848 RESULT=pass
28383 10:57:51.317374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_848 RESULT=skip>
28384 10:57:51.317789 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_848 RESULT=skip
28386 10:57:51.363102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_848 RESULT=skip>
28387 10:57:51.363489 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_848 RESULT=skip
28389 10:57:51.409525 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_864 RESULT=pass>
28390 10:57:51.409992 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_864 RESULT=pass
28392 10:57:51.456353 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_864 RESULT=skip>
28393 10:57:51.456752 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_864 RESULT=skip
28395 10:57:51.502255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_864 RESULT=skip>
28396 10:57:51.502796 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_864 RESULT=skip
28398 10:57:51.548425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_880 RESULT=pass>
28399 10:57:51.548791 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_880 RESULT=pass
28401 10:57:51.588560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_880 RESULT=skip>
28402 10:57:51.589008 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_880 RESULT=skip
28404 10:57:51.629061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_880 RESULT=skip>
28405 10:57:51.629407 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_880 RESULT=skip
28407 10:57:51.672448 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_896 RESULT=pass>
28408 10:57:51.672877 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_896 RESULT=pass
28410 10:57:51.716905 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_896 RESULT=skip
28412 10:57:51.717345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_896 RESULT=skip>
28413 10:57:51.761112 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_896 RESULT=skip>
28414 10:57:51.761508 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_896 RESULT=skip
28416 10:57:51.804655 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_912 RESULT=pass
28418 10:57:51.805092 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_912 RESULT=pass>
28419 10:57:51.845401 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_912 RESULT=skip>
28420 10:57:51.845823 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_912 RESULT=skip
28422 10:57:51.880877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_912 RESULT=skip>
28423 10:57:51.881295 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_912 RESULT=skip
28425 10:57:51.919185 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_928 RESULT=pass>
28426 10:57:51.919601 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_928 RESULT=pass
28428 10:57:51.963457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_928 RESULT=skip>
28429 10:57:51.963828 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_928 RESULT=skip
28431 10:57:52.008854 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_928 RESULT=skip
28433 10:57:52.009207 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_928 RESULT=skip>
28434 10:57:52.053694 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_944 RESULT=pass
28436 10:57:52.054117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_944 RESULT=pass>
28437 10:57:52.100921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_944 RESULT=skip>
28438 10:57:52.101317 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_944 RESULT=skip
28440 10:57:52.147727 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_944 RESULT=skip
28442 10:57:52.148153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_944 RESULT=skip>
28443 10:57:52.194813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_960 RESULT=pass>
28444 10:57:52.195207 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_960 RESULT=pass
28446 10:57:52.241379 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_960 RESULT=skip>
28447 10:57:52.241757 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_960 RESULT=skip
28449 10:57:52.288121 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_960 RESULT=skip
28451 10:57:52.288591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_960 RESULT=skip>
28452 10:57:52.334698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_976 RESULT=pass>
28453 10:57:52.335122 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_976 RESULT=pass
28455 10:57:52.381113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_976 RESULT=skip>
28456 10:57:52.381466 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_976 RESULT=skip
28458 10:57:52.427163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_976 RESULT=skip>
28459 10:57:52.427576 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_976 RESULT=skip
28461 10:57:52.473392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_992 RESULT=pass>
28462 10:57:52.473837 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_992 RESULT=pass
28464 10:57:52.519081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_992 RESULT=skip>
28465 10:57:52.519507 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_992 RESULT=skip
28467 10:57:52.585719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_992 RESULT=skip>
28468 10:57:52.586143 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_992 RESULT=skip
28470 10:57:52.634920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1008 RESULT=pass>
28471 10:57:52.635300 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1008 RESULT=pass
28473 10:57:52.681564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1008 RESULT=skip>
28474 10:57:52.681940 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1008 RESULT=skip
28476 10:57:52.727287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1008 RESULT=skip>
28477 10:57:52.727700 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1008 RESULT=skip
28479 10:57:52.773800 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1024 RESULT=pass
28481 10:57:52.774222 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1024 RESULT=pass>
28482 10:57:52.820489 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1024 RESULT=skip>
28483 10:57:52.820913 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1024 RESULT=skip
28485 10:57:52.867374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1024 RESULT=skip>
28486 10:57:52.867796 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1024 RESULT=skip
28488 10:57:52.914277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1040 RESULT=pass>
28489 10:57:52.914690 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1040 RESULT=pass
28491 10:57:52.961429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1040 RESULT=skip>
28492 10:57:52.961813 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1040 RESULT=skip
28494 10:57:53.007435 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1040 RESULT=skip>
28495 10:57:53.007885 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1040 RESULT=skip
28497 10:57:53.053499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1056 RESULT=pass>
28498 10:57:53.053941 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1056 RESULT=pass
28500 10:57:53.100477 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1056 RESULT=skip
28502 10:57:53.100915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1056 RESULT=skip>
28503 10:57:53.144828 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1056 RESULT=skip>
28504 10:57:53.145177 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1056 RESULT=skip
28506 10:57:53.189151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1072 RESULT=pass>
28507 10:57:53.189509 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1072 RESULT=pass
28509 10:57:53.237421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1072 RESULT=skip>
28510 10:57:53.237855 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1072 RESULT=skip
28512 10:57:53.282118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1072 RESULT=skip>
28513 10:57:53.282557 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1072 RESULT=skip
28515 10:57:53.324764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1088 RESULT=pass>
28516 10:57:53.325208 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1088 RESULT=pass
28518 10:57:53.369033 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1088 RESULT=skip>
28519 10:57:53.369443 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1088 RESULT=skip
28521 10:57:53.412982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1088 RESULT=skip>
28522 10:57:53.413389 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1088 RESULT=skip
28524 10:57:53.458428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1104 RESULT=pass>
28525 10:57:53.458846 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1104 RESULT=pass
28527 10:57:53.502121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1104 RESULT=skip>
28528 10:57:53.502514 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1104 RESULT=skip
28530 10:57:53.546811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1104 RESULT=skip>
28531 10:57:53.547192 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1104 RESULT=skip
28533 10:57:53.586648 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1120 RESULT=pass>
28534 10:57:53.587032 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1120 RESULT=pass
28536 10:57:53.629638 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1120 RESULT=skip>
28537 10:57:53.630049 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1120 RESULT=skip
28539 10:57:53.674756 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1120 RESULT=skip>
28540 10:57:53.675167 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1120 RESULT=skip
28542 10:57:53.718363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1136 RESULT=pass>
28543 10:57:53.718771 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1136 RESULT=pass
28545 10:57:53.774148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1136 RESULT=skip>
28546 10:57:53.774583 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1136 RESULT=skip
28548 10:57:53.815655 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1136 RESULT=skip
28550 10:57:53.816095 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1136 RESULT=skip>
28551 10:57:53.854680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1152 RESULT=pass>
28552 10:57:53.855002 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1152 RESULT=pass
28554 10:57:53.900543 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1152 RESULT=skip>
28555 10:57:53.900911 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1152 RESULT=skip
28557 10:57:53.943770 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1152 RESULT=skip
28559 10:57:53.944201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1152 RESULT=skip>
28560 10:57:53.990616 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1168 RESULT=pass
28562 10:57:53.991132 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1168 RESULT=pass>
28563 10:57:54.042800 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1168 RESULT=skip
28565 10:57:54.043249 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1168 RESULT=skip>
28566 10:57:54.087222 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1168 RESULT=skip
28568 10:57:54.087667 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1168 RESULT=skip>
28569 10:57:54.132490 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1184 RESULT=pass>
28570 10:57:54.132896 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1184 RESULT=pass
28572 10:57:54.183813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1184 RESULT=skip>
28573 10:57:54.184294 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1184 RESULT=skip
28575 10:57:54.227317 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1184 RESULT=skip>
28576 10:57:54.227769 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1184 RESULT=skip
28578 10:57:54.272058 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1200 RESULT=pass
28580 10:57:54.272529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1200 RESULT=pass>
28581 10:57:54.317318 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1200 RESULT=skip>
28582 10:57:54.317715 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1200 RESULT=skip
28584 10:57:54.361172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1200 RESULT=skip>
28585 10:57:54.361578 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1200 RESULT=skip
28587 10:57:54.404389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1216 RESULT=pass>
28588 10:57:54.404771 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1216 RESULT=pass
28590 10:57:54.448499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1216 RESULT=skip>
28591 10:57:54.448907 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1216 RESULT=skip
28593 10:57:54.492392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1216 RESULT=skip>
28594 10:57:54.492743 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1216 RESULT=skip
28596 10:57:54.538876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1232 RESULT=pass>
28597 10:57:54.539299 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1232 RESULT=pass
28599 10:57:54.587060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1232 RESULT=skip>
28600 10:57:54.587498 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1232 RESULT=skip
28602 10:57:54.633613 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1232 RESULT=skip>
28603 10:57:54.633999 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1232 RESULT=skip
28605 10:57:54.679222 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1248 RESULT=pass>
28606 10:57:54.679637 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1248 RESULT=pass
28608 10:57:54.725609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1248 RESULT=skip>
28609 10:57:54.726040 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1248 RESULT=skip
28611 10:57:54.771523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1248 RESULT=skip>
28612 10:57:54.771882 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1248 RESULT=skip
28614 10:57:54.816445 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1264 RESULT=pass
28616 10:57:54.817142 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1264 RESULT=pass>
28617 10:57:54.853235 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1264 RESULT=skip
28619 10:57:54.853674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1264 RESULT=skip>
28620 10:57:54.897219 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1264 RESULT=skip
28622 10:57:54.897657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1264 RESULT=skip>
28623 10:57:54.940880 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1280 RESULT=pass
28625 10:57:54.941326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1280 RESULT=pass>
28626 10:57:54.984601 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1280 RESULT=skip
28628 10:57:54.985052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1280 RESULT=skip>
28629 10:57:55.027223 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1280 RESULT=skip>
28630 10:57:55.027655 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1280 RESULT=skip
28632 10:57:55.066496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1296 RESULT=pass>
28633 10:57:55.066870 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1296 RESULT=pass
28635 10:57:55.110480 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1296 RESULT=skip>
28636 10:57:55.110888 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1296 RESULT=skip
28638 10:57:55.154804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1296 RESULT=skip>
28639 10:57:55.155200 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1296 RESULT=skip
28641 10:57:55.199073 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1312 RESULT=pass>
28642 10:57:55.199476 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1312 RESULT=pass
28644 10:57:55.246322 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1312 RESULT=skip>
28645 10:57:55.246745 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1312 RESULT=skip
28647 10:57:55.291173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1312 RESULT=skip>
28648 10:57:55.291595 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1312 RESULT=skip
28650 10:57:55.337466 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1328 RESULT=pass
28652 10:57:55.337917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1328 RESULT=pass>
28653 10:57:55.385461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1328 RESULT=skip>
28654 10:57:55.385855 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1328 RESULT=skip
28656 10:57:55.424280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1328 RESULT=skip>
28657 10:57:55.424686 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1328 RESULT=skip
28659 10:57:55.470463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1344 RESULT=pass>
28660 10:57:55.470890 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1344 RESULT=pass
28662 10:57:55.523191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1344 RESULT=skip>
28663 10:57:55.523609 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1344 RESULT=skip
28665 10:57:55.571000 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1344 RESULT=skip
28667 10:57:55.571435 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1344 RESULT=skip>
28668 10:57:55.614909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1360 RESULT=pass>
28669 10:57:55.615328 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1360 RESULT=pass
28671 10:57:55.661393 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1360 RESULT=skip>
28672 10:57:55.661806 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1360 RESULT=skip
28674 10:57:55.702277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1360 RESULT=skip>
28675 10:57:55.702682 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1360 RESULT=skip
28677 10:57:55.746770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1376 RESULT=pass>
28678 10:57:55.747198 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1376 RESULT=pass
28680 10:57:55.779655 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1376 RESULT=skip
28682 10:57:55.780128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1376 RESULT=skip>
28683 10:57:55.824736 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1376 RESULT=skip>
28684 10:57:55.825157 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1376 RESULT=skip
28686 10:57:55.865784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1392 RESULT=pass>
28687 10:57:55.866203 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1392 RESULT=pass
28689 10:57:55.910803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1392 RESULT=skip>
28690 10:57:55.911210 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1392 RESULT=skip
28692 10:57:55.956489 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1392 RESULT=skip>
28693 10:57:55.956914 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1392 RESULT=skip
28695 10:57:56.001540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1408 RESULT=pass>
28696 10:57:56.001972 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1408 RESULT=pass
28698 10:57:56.046295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1408 RESULT=skip>
28699 10:57:56.046720 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1408 RESULT=skip
28701 10:57:56.090789 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1408 RESULT=skip>
28702 10:57:56.091190 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1408 RESULT=skip
28704 10:57:56.136452 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1424 RESULT=pass
28706 10:57:56.136887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1424 RESULT=pass>
28707 10:57:56.181280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1424 RESULT=skip>
28708 10:57:56.181689 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1424 RESULT=skip
28710 10:57:56.227264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1424 RESULT=skip>
28711 10:57:56.227676 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1424 RESULT=skip
28713 10:57:56.272662 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1440 RESULT=pass>
28714 10:57:56.273079 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1440 RESULT=pass
28716 10:57:56.316807 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1440 RESULT=skip>
28717 10:57:56.317155 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1440 RESULT=skip
28719 10:57:56.361624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1440 RESULT=skip>
28720 10:57:56.362023 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1440 RESULT=skip
28722 10:57:56.394366 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1456 RESULT=pass>
28723 10:57:56.394784 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1456 RESULT=pass
28725 10:57:56.439096 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1456 RESULT=skip>
28726 10:57:56.439511 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1456 RESULT=skip
28728 10:57:56.484703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1456 RESULT=skip>
28729 10:57:56.485119 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1456 RESULT=skip
28731 10:57:56.530007 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1472 RESULT=pass>
28732 10:57:56.530444 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1472 RESULT=pass
28734 10:57:56.573800 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1472 RESULT=skip>
28735 10:57:56.574239 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1472 RESULT=skip
28737 10:57:56.618530 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1472 RESULT=skip>
28738 10:57:56.618953 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1472 RESULT=skip
28740 10:57:56.655418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1488 RESULT=pass>
28741 10:57:56.655811 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1488 RESULT=pass
28743 10:57:56.700976 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1488 RESULT=skip>
28744 10:57:56.701339 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1488 RESULT=skip
28746 10:57:56.745310 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1488 RESULT=skip
28748 10:57:56.745736 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1488 RESULT=skip>
28749 10:57:56.788483 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1504 RESULT=pass>
28750 10:57:56.788882 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1504 RESULT=pass
28752 10:57:56.825216 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1504 RESULT=skip
28754 10:57:56.825629 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1504 RESULT=skip>
28755 10:57:56.861951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1504 RESULT=skip>
28756 10:57:56.862375 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1504 RESULT=skip
28758 10:57:56.906588 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1520 RESULT=pass>
28759 10:57:56.907004 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1520 RESULT=pass
28761 10:57:56.950563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1520 RESULT=skip>
28762 10:57:56.950968 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1520 RESULT=skip
28764 10:57:56.994488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1520 RESULT=skip>
28765 10:57:56.994903 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1520 RESULT=skip
28767 10:57:57.038215 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1536 RESULT=pass>
28768 10:57:57.038633 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1536 RESULT=pass
28770 10:57:57.082470 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1536 RESULT=skip
28772 10:57:57.082888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1536 RESULT=skip>
28773 10:57:57.126994 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1536 RESULT=skip>
28774 10:57:57.127388 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1536 RESULT=skip
28776 10:57:57.170621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1552 RESULT=pass>
28777 10:57:57.171017 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1552 RESULT=pass
28779 10:57:57.214537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1552 RESULT=skip>
28780 10:57:57.214913 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1552 RESULT=skip
28782 10:57:57.258566 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1552 RESULT=skip>
28783 10:57:57.258962 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1552 RESULT=skip
28785 10:57:57.303275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1568 RESULT=pass>
28786 10:57:57.303653 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1568 RESULT=pass
28788 10:57:57.350187 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1568 RESULT=skip>
28789 10:57:57.350617 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1568 RESULT=skip
28791 10:57:57.396154 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1568 RESULT=skip>
28792 10:57:57.396582 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1568 RESULT=skip
28794 10:57:57.447427 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1584 RESULT=pass>
28795 10:57:57.447846 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1584 RESULT=pass
28797 10:57:57.487183 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1584 RESULT=skip>
28798 10:57:57.487599 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1584 RESULT=skip
28800 10:57:57.520481 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1584 RESULT=skip
28802 10:57:57.520906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1584 RESULT=skip>
28803 10:57:57.557583 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1600 RESULT=pass
28805 10:57:57.558026 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1600 RESULT=pass>
28806 10:57:57.602722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1600 RESULT=skip>
28807 10:57:57.603101 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1600 RESULT=skip
28809 10:57:57.647561 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1600 RESULT=skip
28811 10:57:57.647977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1600 RESULT=skip>
28812 10:57:57.710874 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1616 RESULT=pass>
28813 10:57:57.711316 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1616 RESULT=pass
28815 10:57:57.756983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1616 RESULT=skip>
28816 10:57:57.757402 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1616 RESULT=skip
28818 10:57:57.801305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1616 RESULT=skip>
28819 10:57:57.801691 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1616 RESULT=skip
28821 10:57:57.845816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1632 RESULT=pass>
28822 10:57:57.846249 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1632 RESULT=pass
28824 10:57:57.889191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1632 RESULT=skip>
28825 10:57:57.889636 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1632 RESULT=skip
28827 10:57:57.933573 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1632 RESULT=skip>
28828 10:57:57.933977 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1632 RESULT=skip
28830 10:57:57.976612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1648 RESULT=pass>
28831 10:57:57.977052 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1648 RESULT=pass
28833 10:57:58.019464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1648 RESULT=skip>
28834 10:57:58.019900 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1648 RESULT=skip
28836 10:57:58.063441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1648 RESULT=skip>
28837 10:57:58.063863 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1648 RESULT=skip
28839 10:57:58.110123 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1664 RESULT=pass>
28840 10:57:58.110567 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1664 RESULT=pass
28842 10:57:58.154231 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1664 RESULT=skip
28844 10:57:58.154679 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1664 RESULT=skip>
28845 10:57:58.198253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1664 RESULT=skip>
28846 10:57:58.198667 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1664 RESULT=skip
28848 10:57:58.241349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1680 RESULT=pass>
28849 10:57:58.241752 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1680 RESULT=pass
28851 10:57:58.286633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1680 RESULT=skip>
28852 10:57:58.287067 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1680 RESULT=skip
28854 10:57:58.330672 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1680 RESULT=skip>
28855 10:57:58.331099 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1680 RESULT=skip
28857 10:57:58.375735 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1696 RESULT=pass
28859 10:57:58.376184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1696 RESULT=pass>
28860 10:57:58.420496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1696 RESULT=skip>
28861 10:57:58.420907 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1696 RESULT=skip
28863 10:57:58.464259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1696 RESULT=skip>
28864 10:57:58.464650 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1696 RESULT=skip
28866 10:57:58.507838 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1712 RESULT=pass
28868 10:57:58.508605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1712 RESULT=pass>
28869 10:57:58.553107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1712 RESULT=skip>
28870 10:57:58.553528 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1712 RESULT=skip
28872 10:57:58.596821 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1712 RESULT=skip>
28873 10:57:58.597216 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1712 RESULT=skip
28875 10:57:58.639236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1728 RESULT=pass>
28876 10:57:58.639631 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1728 RESULT=pass
28878 10:57:58.682760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1728 RESULT=skip>
28879 10:57:58.683162 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1728 RESULT=skip
28881 10:57:58.726761 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1728 RESULT=skip>
28882 10:57:58.727149 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1728 RESULT=skip
28884 10:57:58.773190 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1744 RESULT=pass>
28885 10:57:58.773807 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1744 RESULT=pass
28887 10:57:58.818021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1744 RESULT=skip>
28888 10:57:58.818440 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1744 RESULT=skip
28890 10:57:58.862857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1744 RESULT=skip>
28891 10:57:58.863277 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1744 RESULT=skip
28893 10:57:58.907546 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1760 RESULT=pass>
28894 10:57:58.907952 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1760 RESULT=pass
28896 10:57:58.952166 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1760 RESULT=skip
28898 10:57:58.952599 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1760 RESULT=skip>
28899 10:57:58.997662 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1760 RESULT=skip>
28900 10:57:58.998093 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1760 RESULT=skip
28902 10:57:59.043036 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1776 RESULT=pass
28904 10:57:59.043491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1776 RESULT=pass>
28905 10:57:59.091231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1776 RESULT=skip>
28906 10:57:59.091641 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1776 RESULT=skip
28908 10:57:59.138748 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1776 RESULT=skip
28910 10:57:59.139216 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1776 RESULT=skip>
28911 10:57:59.183683 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1792 RESULT=pass
28913 10:57:59.184145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1792 RESULT=pass>
28914 10:57:59.228560 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1792 RESULT=skip
28916 10:57:59.228983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1792 RESULT=skip>
28917 10:57:59.272431 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1792 RESULT=skip
28919 10:57:59.272867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1792 RESULT=skip>
28920 10:57:59.316601 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1808 RESULT=pass
28922 10:57:59.317068 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1808 RESULT=pass>
28923 10:57:59.363942 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1808 RESULT=skip
28925 10:57:59.364405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1808 RESULT=skip>
28926 10:57:59.397460 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1808 RESULT=skip>
28927 10:57:59.397908 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1808 RESULT=skip
28929 10:57:59.431091 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1824 RESULT=pass
28931 10:57:59.431544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1824 RESULT=pass>
28932 10:57:59.464601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1824 RESULT=skip>
28933 10:57:59.464995 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1824 RESULT=skip
28935 10:57:59.508457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1824 RESULT=skip>
28936 10:57:59.508805 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1824 RESULT=skip
28938 10:57:59.547423 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1840 RESULT=pass
28940 10:57:59.547861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1840 RESULT=pass>
28941 10:57:59.591665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1840 RESULT=skip>
28942 10:57:59.592109 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1840 RESULT=skip
28944 10:57:59.634402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1840 RESULT=skip>
28945 10:57:59.634821 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1840 RESULT=skip
28947 10:57:59.679305 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1856 RESULT=pass
28949 10:57:59.679744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1856 RESULT=pass>
28950 10:57:59.724943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1856 RESULT=skip>
28951 10:57:59.725379 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1856 RESULT=skip
28953 10:57:59.769968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1856 RESULT=skip>
28954 10:57:59.770349 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1856 RESULT=skip
28956 10:57:59.809855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1872 RESULT=pass>
28957 10:57:59.810236 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1872 RESULT=pass
28959 10:57:59.850718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1872 RESULT=skip>
28960 10:57:59.851097 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1872 RESULT=skip
28962 10:57:59.895035 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1872 RESULT=skip
28964 10:57:59.895483 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1872 RESULT=skip>
28965 10:57:59.933885 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1888 RESULT=pass>
28966 10:57:59.934297 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1888 RESULT=pass
28968 10:57:59.977858 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1888 RESULT=skip>
28969 10:57:59.978292 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1888 RESULT=skip
28971 10:58:00.022028 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1888 RESULT=skip>
28972 10:58:00.022449 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1888 RESULT=skip
28974 10:58:00.066454 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1904 RESULT=pass>
28975 10:58:00.066863 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1904 RESULT=pass
28977 10:58:00.110562 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1904 RESULT=skip>
28978 10:58:00.110976 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1904 RESULT=skip
28980 10:58:00.156475 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1904 RESULT=skip>
28981 10:58:00.156854 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1904 RESULT=skip
28983 10:58:00.201193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1920 RESULT=pass>
28984 10:58:00.201604 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1920 RESULT=pass
28986 10:58:00.244348 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1920 RESULT=skip
28988 10:58:00.244789 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1920 RESULT=skip>
28989 10:58:00.288970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1920 RESULT=skip>
28990 10:58:00.289385 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1920 RESULT=skip
28992 10:58:00.333060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1936 RESULT=pass>
28993 10:58:00.333484 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1936 RESULT=pass
28995 10:58:00.376768 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1936 RESULT=skip
28997 10:58:00.377195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1936 RESULT=skip>
28998 10:58:00.420358 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1936 RESULT=skip
29000 10:58:00.420778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1936 RESULT=skip>
29001 10:58:00.464806 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1952 RESULT=pass>
29002 10:58:00.465215 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1952 RESULT=pass
29004 10:58:00.507119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1952 RESULT=skip>
29005 10:58:00.507490 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1952 RESULT=skip
29007 10:58:00.549889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1952 RESULT=skip>
29008 10:58:00.550314 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1952 RESULT=skip
29010 10:58:00.595308 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1968 RESULT=pass
29012 10:58:00.595749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1968 RESULT=pass>
29013 10:58:00.637973 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1968 RESULT=skip
29015 10:58:00.638416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1968 RESULT=skip>
29016 10:58:00.682221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1968 RESULT=skip>
29017 10:58:00.682656 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1968 RESULT=skip
29019 10:58:00.727285 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1984 RESULT=pass>
29020 10:58:00.727730 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1984 RESULT=pass
29022 10:58:00.764532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1984 RESULT=skip>
29023 10:58:00.764969 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1984 RESULT=skip
29025 10:58:00.798350 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1984 RESULT=skip
29027 10:58:00.798712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1984 RESULT=skip>
29028 10:58:00.834684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2000 RESULT=pass>
29029 10:58:00.835078 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2000 RESULT=pass
29031 10:58:00.879248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2000 RESULT=skip>
29032 10:58:00.879676 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2000 RESULT=skip
29034 10:58:00.924713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2000 RESULT=skip>
29035 10:58:00.925104 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2000 RESULT=skip
29037 10:58:00.969083 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2016 RESULT=pass
29039 10:58:00.969574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2016 RESULT=pass>
29040 10:58:01.013570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2016 RESULT=skip>
29041 10:58:01.013998 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2016 RESULT=skip
29043 10:58:01.050641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2016 RESULT=skip>
29044 10:58:01.051054 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2016 RESULT=skip
29046 10:58:01.095976 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2032 RESULT=pass
29048 10:58:01.096414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2032 RESULT=pass>
29049 10:58:01.141170 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2032 RESULT=skip>
29050 10:58:01.141581 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2032 RESULT=skip
29052 10:58:01.184895 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2032 RESULT=skip>
29053 10:58:01.185271 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2032 RESULT=skip
29055 10:58:01.230704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2048 RESULT=pass>
29056 10:58:01.231123 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2048 RESULT=pass
29058 10:58:01.275493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2048 RESULT=skip>
29059 10:58:01.275862 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2048 RESULT=skip
29061 10:58:01.317343 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2048 RESULT=skip
29063 10:58:01.317817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2048 RESULT=skip>
29064 10:58:01.360809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2064 RESULT=pass>
29065 10:58:01.361223 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2064 RESULT=pass
29067 10:58:01.404304 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2064 RESULT=skip>
29068 10:58:01.404743 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2064 RESULT=skip
29070 10:58:01.449014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2064 RESULT=skip>
29071 10:58:01.449431 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2064 RESULT=skip
29073 10:58:01.494667 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2080 RESULT=pass>
29074 10:58:01.495115 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2080 RESULT=pass
29076 10:58:01.541128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2080 RESULT=skip>
29077 10:58:01.541563 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2080 RESULT=skip
29079 10:58:01.585050 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2080 RESULT=skip
29081 10:58:01.585529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2080 RESULT=skip>
29082 10:58:01.628302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2096 RESULT=pass>
29083 10:58:01.628683 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2096 RESULT=pass
29085 10:58:01.672818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2096 RESULT=skip>
29086 10:58:01.673224 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2096 RESULT=skip
29088 10:58:01.713544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2096 RESULT=skip>
29089 10:58:01.713905 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2096 RESULT=skip
29091 10:58:01.752779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2112 RESULT=pass>
29092 10:58:01.753190 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2112 RESULT=pass
29094 10:58:01.794577 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2112 RESULT=skip>
29095 10:58:01.795009 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2112 RESULT=skip
29097 10:58:01.838795 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2112 RESULT=skip>
29098 10:58:01.839226 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2112 RESULT=skip
29100 10:58:01.883075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2128 RESULT=pass>
29101 10:58:01.883489 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2128 RESULT=pass
29103 10:58:01.927259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2128 RESULT=skip>
29104 10:58:01.927671 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2128 RESULT=skip
29106 10:58:01.971658 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2128 RESULT=skip
29108 10:58:01.972019 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2128 RESULT=skip>
29109 10:58:02.015585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2144 RESULT=pass>
29110 10:58:02.015996 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2144 RESULT=pass
29112 10:58:02.060312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2144 RESULT=skip>
29113 10:58:02.060726 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2144 RESULT=skip
29115 10:58:02.103303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2144 RESULT=skip>
29116 10:58:02.103730 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2144 RESULT=skip
29118 10:58:02.146725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2160 RESULT=pass>
29119 10:58:02.147140 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2160 RESULT=pass
29121 10:58:02.179241 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2160 RESULT=skip>
29122 10:58:02.179637 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2160 RESULT=skip
29124 10:58:02.212542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2160 RESULT=skip>
29125 10:58:02.212924 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2160 RESULT=skip
29127 10:58:02.254057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2176 RESULT=pass>
29128 10:58:02.254470 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2176 RESULT=pass
29130 10:58:02.289273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2176 RESULT=skip>
29131 10:58:02.289682 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2176 RESULT=skip
29133 10:58:02.326954 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2176 RESULT=skip>
29134 10:58:02.327374 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2176 RESULT=skip
29136 10:58:02.364555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2192 RESULT=pass>
29137 10:58:02.364963 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2192 RESULT=pass
29139 10:58:02.410479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2192 RESULT=skip>
29140 10:58:02.410876 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2192 RESULT=skip
29142 10:58:02.455819 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2192 RESULT=skip
29144 10:58:02.456322 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2192 RESULT=skip>
29145 10:58:02.503134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2208 RESULT=pass>
29146 10:58:02.503572 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2208 RESULT=pass
29148 10:58:02.549394 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2208 RESULT=skip>
29149 10:58:02.549774 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2208 RESULT=skip
29151 10:58:02.592916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2208 RESULT=skip>
29152 10:58:02.593291 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2208 RESULT=skip
29154 10:58:02.639934 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2224 RESULT=pass
29156 10:58:02.640291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2224 RESULT=pass>
29157 10:58:02.677994 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2224 RESULT=skip>
29158 10:58:02.678350 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2224 RESULT=skip
29160 10:58:02.724506 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2224 RESULT=skip
29162 10:58:02.724968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2224 RESULT=skip>
29163 10:58:02.768677 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2240 RESULT=pass>
29164 10:58:02.769106 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2240 RESULT=pass
29166 10:58:02.837076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2240 RESULT=skip>
29167 10:58:02.837448 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2240 RESULT=skip
29169 10:58:02.870408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2240 RESULT=skip>
29170 10:58:02.870817 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2240 RESULT=skip
29172 10:58:02.906667 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2256 RESULT=pass>
29173 10:58:02.907098 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2256 RESULT=pass
29175 10:58:02.949596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2256 RESULT=skip>
29176 10:58:02.950023 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2256 RESULT=skip
29178 10:58:02.994845 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2256 RESULT=skip
29180 10:58:02.995291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2256 RESULT=skip>
29181 10:58:03.038506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2272 RESULT=pass>
29182 10:58:03.038909 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2272 RESULT=pass
29184 10:58:03.083317 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2272 RESULT=skip>
29185 10:58:03.083727 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2272 RESULT=skip
29187 10:58:03.127566 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2272 RESULT=skip
29189 10:58:03.128039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2272 RESULT=skip>
29190 10:58:03.171687 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2288 RESULT=pass
29192 10:58:03.172155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2288 RESULT=pass>
29193 10:58:03.205933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2288 RESULT=skip>
29194 10:58:03.206326 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2288 RESULT=skip
29196 10:58:03.239272 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2288 RESULT=skip>
29197 10:58:03.239681 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2288 RESULT=skip
29199 10:58:03.273504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2304 RESULT=pass>
29200 10:58:03.273908 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2304 RESULT=pass
29202 10:58:03.316547 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2304 RESULT=skip>
29203 10:58:03.316895 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2304 RESULT=skip
29205 10:58:03.349331 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2304 RESULT=skip>
29206 10:58:03.349750 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2304 RESULT=skip
29208 10:58:03.382857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2320 RESULT=pass>
29209 10:58:03.383282 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2320 RESULT=pass
29211 10:58:03.419220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2320 RESULT=skip>
29212 10:58:03.419647 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2320 RESULT=skip
29214 10:58:03.472758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2320 RESULT=skip>
29215 10:58:03.473182 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2320 RESULT=skip
29217 10:58:03.526930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2336 RESULT=pass>
29218 10:58:03.527358 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2336 RESULT=pass
29220 10:58:03.580622 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2336 RESULT=skip>
29221 10:58:03.580999 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2336 RESULT=skip
29223 10:58:03.633695 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2336 RESULT=skip
29225 10:58:03.634144 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2336 RESULT=skip>
29226 10:58:03.686411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2352 RESULT=pass>
29227 10:58:03.686813 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2352 RESULT=pass
29229 10:58:03.739915 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2352 RESULT=skip
29231 10:58:03.740503 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2352 RESULT=skip>
29232 10:58:03.797424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2352 RESULT=skip>
29233 10:58:03.797873 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2352 RESULT=skip
29235 10:58:03.855939 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2368 RESULT=pass
29237 10:58:03.856435 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2368 RESULT=pass>
29238 10:58:03.912367 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2368 RESULT=skip
29240 10:58:03.912867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2368 RESULT=skip>
29241 10:58:03.965901 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2368 RESULT=skip>
29242 10:58:03.966285 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2368 RESULT=skip
29244 10:58:04.019359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2384 RESULT=pass>
29245 10:58:04.019803 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2384 RESULT=pass
29247 10:58:04.074788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2384 RESULT=skip>
29248 10:58:04.075245 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2384 RESULT=skip
29250 10:58:04.126385 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2384 RESULT=skip
29252 10:58:04.126848 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2384 RESULT=skip>
29253 10:58:04.168054 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2400 RESULT=pass
29255 10:58:04.168490 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2400 RESULT=pass>
29256 10:58:04.205268 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2400 RESULT=skip>
29257 10:58:04.205676 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2400 RESULT=skip
29259 10:58:04.242369 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2400 RESULT=skip
29261 10:58:04.242962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2400 RESULT=skip>
29262 10:58:04.290749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2416 RESULT=pass>
29263 10:58:04.291175 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2416 RESULT=pass
29265 10:58:04.339448 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2416 RESULT=skip
29267 10:58:04.339927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2416 RESULT=skip>
29268 10:58:04.390505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2416 RESULT=skip>
29269 10:58:04.390905 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2416 RESULT=skip
29271 10:58:04.440495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2432 RESULT=pass>
29272 10:58:04.440945 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2432 RESULT=pass
29274 10:58:04.484369 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2432 RESULT=skip>
29275 10:58:04.484786 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2432 RESULT=skip
29277 10:58:04.535283 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2432 RESULT=skip>
29278 10:58:04.535723 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2432 RESULT=skip
29280 10:58:04.584917 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2448 RESULT=pass
29282 10:58:04.585406 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2448 RESULT=pass>
29283 10:58:04.632949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2448 RESULT=skip>
29284 10:58:04.633382 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2448 RESULT=skip
29286 10:58:04.671550 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2448 RESULT=skip>
29287 10:58:04.672006 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2448 RESULT=skip
29289 10:58:04.715194 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2464 RESULT=pass>
29290 10:58:04.715624 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2464 RESULT=pass
29292 10:58:04.752793 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2464 RESULT=skip>
29293 10:58:04.753169 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2464 RESULT=skip
29295 10:58:04.801229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2464 RESULT=skip>
29296 10:58:04.801657 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2464 RESULT=skip
29298 10:58:04.836587 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2480 RESULT=pass>
29299 10:58:04.837010 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2480 RESULT=pass
29301 10:58:04.872777 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2480 RESULT=skip>
29302 10:58:04.873227 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2480 RESULT=skip
29304 10:58:04.909333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2480 RESULT=skip>
29305 10:58:04.909781 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2480 RESULT=skip
29307 10:58:04.958225 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2496 RESULT=pass>
29308 10:58:04.958659 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2496 RESULT=pass
29310 10:58:05.005554 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2496 RESULT=skip
29312 10:58:05.006039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2496 RESULT=skip>
29313 10:58:05.053272 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2496 RESULT=skip>
29314 10:58:05.053695 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2496 RESULT=skip
29316 10:58:05.102315 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2512 RESULT=pass
29318 10:58:05.102763 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2512 RESULT=pass>
29319 10:58:05.151320 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2512 RESULT=skip
29321 10:58:05.151767 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2512 RESULT=skip>
29322 10:58:05.199358 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2512 RESULT=skip
29324 10:58:05.199842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2512 RESULT=skip>
29325 10:58:05.238707 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2528 RESULT=pass>
29326 10:58:05.239159 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2528 RESULT=pass
29328 10:58:05.282472 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2528 RESULT=skip>
29329 10:58:05.282885 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2528 RESULT=skip
29331 10:58:05.331031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2528 RESULT=skip>
29332 10:58:05.331447 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2528 RESULT=skip
29334 10:58:05.376283 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2544 RESULT=pass>
29335 10:58:05.376695 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2544 RESULT=pass
29337 10:58:05.424896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2544 RESULT=skip>
29338 10:58:05.425188 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2544 RESULT=skip
29340 10:58:05.472637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2544 RESULT=skip>
29341 10:58:05.472927 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2544 RESULT=skip
29343 10:58:05.522588 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2560 RESULT=pass>
29344 10:58:05.522878 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2560 RESULT=pass
29346 10:58:05.570011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2560 RESULT=skip>
29347 10:58:05.570429 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2560 RESULT=skip
29349 10:58:05.617707 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2560 RESULT=skip>
29350 10:58:05.618128 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2560 RESULT=skip
29352 10:58:05.665709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2576 RESULT=pass>
29353 10:58:05.666099 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2576 RESULT=pass
29355 10:58:05.714504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2576 RESULT=skip>
29356 10:58:05.715199 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2576 RESULT=skip
29358 10:58:05.765959 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2576 RESULT=skip
29360 10:58:05.766421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2576 RESULT=skip>
29361 10:58:05.813530 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2592 RESULT=pass>
29362 10:58:05.813975 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2592 RESULT=pass
29364 10:58:05.862473 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2592 RESULT=skip>
29365 10:58:05.862895 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2592 RESULT=skip
29367 10:58:05.910507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2592 RESULT=skip>
29368 10:58:05.910879 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2592 RESULT=skip
29370 10:58:05.956687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2608 RESULT=pass>
29371 10:58:05.957073 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2608 RESULT=pass
29373 10:58:06.005216 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2608 RESULT=skip>
29374 10:58:06.005628 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2608 RESULT=skip
29376 10:58:06.045439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2608 RESULT=skip>
29377 10:58:06.045864 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2608 RESULT=skip
29379 10:58:06.081836 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2624 RESULT=pass
29381 10:58:06.082565 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2624 RESULT=pass>
29382 10:58:06.127216 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2624 RESULT=skip>
29383 10:58:06.127646 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2624 RESULT=skip
29385 10:58:06.176499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2624 RESULT=skip>
29386 10:58:06.176898 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2624 RESULT=skip
29388 10:58:06.225435 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2640 RESULT=pass>
29389 10:58:06.225861 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2640 RESULT=pass
29391 10:58:06.273612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2640 RESULT=skip>
29392 10:58:06.274045 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2640 RESULT=skip
29394 10:58:06.318688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2640 RESULT=skip>
29395 10:58:06.319124 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2640 RESULT=skip
29397 10:58:06.366647 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2656 RESULT=pass
29399 10:58:06.367091 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2656 RESULT=pass>
29400 10:58:06.413378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2656 RESULT=skip>
29401 10:58:06.413789 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2656 RESULT=skip
29403 10:58:06.454584 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2656 RESULT=skip
29405 10:58:06.455057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2656 RESULT=skip>
29406 10:58:06.503409 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2672 RESULT=pass
29408 10:58:06.503857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2672 RESULT=pass>
29409 10:58:06.553391 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2672 RESULT=skip
29411 10:58:06.553824 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2672 RESULT=skip>
29412 10:58:06.599441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2672 RESULT=skip>
29413 10:58:06.599824 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2672 RESULT=skip
29415 10:58:06.645944 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2688 RESULT=pass>
29416 10:58:06.646336 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2688 RESULT=pass
29418 10:58:06.697104 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2688 RESULT=skip
29420 10:58:06.697551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2688 RESULT=skip>
29421 10:58:06.744008 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2688 RESULT=skip
29423 10:58:06.744615 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2688 RESULT=skip>
29424 10:58:06.782637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2704 RESULT=pass>
29425 10:58:06.783029 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2704 RESULT=pass
29427 10:58:06.832667 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2704 RESULT=skip
29429 10:58:06.833178 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2704 RESULT=skip>
29430 10:58:06.881820 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2704 RESULT=skip
29432 10:58:06.882246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2704 RESULT=skip>
29433 10:58:06.927571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2720 RESULT=pass>
29434 10:58:06.927974 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2720 RESULT=pass
29436 10:58:06.977304 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2720 RESULT=skip
29438 10:58:06.977720 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2720 RESULT=skip>
29439 10:58:07.027305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2720 RESULT=skip>
29440 10:58:07.027704 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2720 RESULT=skip
29442 10:58:07.075407 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2736 RESULT=pass>
29443 10:58:07.075844 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2736 RESULT=pass
29445 10:58:07.125704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2736 RESULT=skip>
29446 10:58:07.126137 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2736 RESULT=skip
29448 10:58:07.169970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2736 RESULT=skip>
29449 10:58:07.170396 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2736 RESULT=skip
29451 10:58:07.211259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2752 RESULT=pass>
29452 10:58:07.211676 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2752 RESULT=pass
29454 10:58:07.254607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2752 RESULT=skip>
29455 10:58:07.255026 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2752 RESULT=skip
29457 10:58:07.303619 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2752 RESULT=skip
29459 10:58:07.304105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2752 RESULT=skip>
29460 10:58:07.348492 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2768 RESULT=pass
29462 10:58:07.348954 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2768 RESULT=pass>
29463 10:58:07.388797 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2768 RESULT=skip
29465 10:58:07.389214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2768 RESULT=skip>
29466 10:58:07.426629 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2768 RESULT=skip>
29467 10:58:07.427057 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2768 RESULT=skip
29469 10:58:07.476567 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2784 RESULT=pass
29471 10:58:07.477119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2784 RESULT=pass>
29472 10:58:07.526419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2784 RESULT=skip>
29473 10:58:07.526850 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2784 RESULT=skip
29475 10:58:07.574464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2784 RESULT=skip>
29476 10:58:07.574900 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2784 RESULT=skip
29478 10:58:07.623919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2800 RESULT=pass>
29479 10:58:07.624359 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2800 RESULT=pass
29481 10:58:07.671743 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2800 RESULT=skip
29483 10:58:07.672216 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2800 RESULT=skip>
29484 10:58:07.721009 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2800 RESULT=skip>
29485 10:58:07.721441 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2800 RESULT=skip
29487 10:58:07.769272 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2816 RESULT=pass
29489 10:58:07.769735 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2816 RESULT=pass>
29490 10:58:07.819206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2816 RESULT=skip>
29491 10:58:07.819647 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2816 RESULT=skip
29493 10:58:07.869184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2816 RESULT=skip>
29494 10:58:07.869624 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2816 RESULT=skip
29496 10:58:07.925883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2832 RESULT=pass>
29497 10:58:07.926279 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2832 RESULT=pass
29499 10:58:07.995101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2832 RESULT=skip>
29500 10:58:07.995449 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2832 RESULT=skip
29502 10:58:08.044822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2832 RESULT=skip>
29503 10:58:08.045195 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2832 RESULT=skip
29505 10:58:08.086029 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2848 RESULT=pass
29507 10:58:08.086715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2848 RESULT=pass>
29508 10:58:08.126927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2848 RESULT=skip>
29509 10:58:08.127361 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2848 RESULT=skip
29511 10:58:08.173828 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2848 RESULT=skip>
29512 10:58:08.174338 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2848 RESULT=skip
29514 10:58:08.209691 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2864 RESULT=pass>
29515 10:58:08.210129 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2864 RESULT=pass
29517 10:58:08.250514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2864 RESULT=skip>
29518 10:58:08.250870 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2864 RESULT=skip
29520 10:58:08.286103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2864 RESULT=skip>
29521 10:58:08.286554 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2864 RESULT=skip
29523 10:58:08.334817 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2880 RESULT=pass
29525 10:58:08.335253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2880 RESULT=pass>
29526 10:58:08.384372 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2880 RESULT=skip>
29527 10:58:08.384804 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2880 RESULT=skip
29529 10:58:08.433347 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2880 RESULT=skip>
29530 10:58:08.433774 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2880 RESULT=skip
29532 10:58:08.470158 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2896 RESULT=pass>
29533 10:58:08.470584 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2896 RESULT=pass
29535 10:58:08.507180 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2896 RESULT=skip>
29536 10:58:08.507532 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2896 RESULT=skip
29538 10:58:08.543786 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2896 RESULT=skip
29540 10:58:08.544100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2896 RESULT=skip>
29541 10:58:08.590179 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2912 RESULT=pass>
29542 10:58:08.590476 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2912 RESULT=pass
29544 10:58:08.632421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2912 RESULT=skip>
29545 10:58:08.632704 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2912 RESULT=skip
29547 10:58:08.681251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2912 RESULT=skip>
29548 10:58:08.681546 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2912 RESULT=skip
29550 10:58:08.724457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2928 RESULT=pass>
29551 10:58:08.724783 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2928 RESULT=pass
29553 10:58:08.773322 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2928 RESULT=skip>
29554 10:58:08.773682 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2928 RESULT=skip
29556 10:58:08.823417 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2928 RESULT=skip
29558 10:58:08.823856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2928 RESULT=skip>
29559 10:58:08.873611 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2944 RESULT=pass>
29560 10:58:08.873922 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2944 RESULT=pass
29562 10:58:08.923653 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2944 RESULT=skip>
29563 10:58:08.924049 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2944 RESULT=skip
29565 10:58:08.972807 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2944 RESULT=skip>
29566 10:58:08.973228 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2944 RESULT=skip
29568 10:58:09.021463 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2960 RESULT=pass
29570 10:58:09.021923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2960 RESULT=pass>
29571 10:58:09.057638 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2960 RESULT=skip>
29572 10:58:09.057939 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2960 RESULT=skip
29574 10:58:09.107562 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2960 RESULT=skip>
29575 10:58:09.107990 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2960 RESULT=skip
29577 10:58:09.156911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2976 RESULT=pass>
29578 10:58:09.157220 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2976 RESULT=pass
29580 10:58:09.204509 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2976 RESULT=skip
29582 10:58:09.204940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2976 RESULT=skip>
29583 10:58:09.253348 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2976 RESULT=skip>
29584 10:58:09.253755 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2976 RESULT=skip
29586 10:58:09.290517 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2992 RESULT=pass>
29587 10:58:09.290854 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2992 RESULT=pass
29589 10:58:09.338467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2992 RESULT=skip>
29590 10:58:09.338749 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2992 RESULT=skip
29592 10:58:09.387390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2992 RESULT=skip>
29593 10:58:09.387814 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2992 RESULT=skip
29595 10:58:09.438732 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3008 RESULT=pass>
29596 10:58:09.439115 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3008 RESULT=pass
29598 10:58:09.486395 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3008 RESULT=skip>
29599 10:58:09.486689 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3008 RESULT=skip
29601 10:58:09.534016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3008 RESULT=skip>
29602 10:58:09.534317 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3008 RESULT=skip
29604 10:58:09.581710 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3024 RESULT=pass
29606 10:58:09.582140 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3024 RESULT=pass>
29607 10:58:09.629814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3024 RESULT=skip>
29608 10:58:09.630234 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3024 RESULT=skip
29610 10:58:09.677519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3024 RESULT=skip>
29611 10:58:09.677951 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3024 RESULT=skip
29613 10:58:09.725555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3040 RESULT=pass>
29614 10:58:09.725895 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3040 RESULT=pass
29616 10:58:09.771200 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3040 RESULT=skip>
29617 10:58:09.771490 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3040 RESULT=skip
29619 10:58:09.820883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3040 RESULT=skip>
29620 10:58:09.821174 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3040 RESULT=skip
29622 10:58:09.869191 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3056 RESULT=pass
29624 10:58:09.869660 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3056 RESULT=pass>
29625 10:58:09.917060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3056 RESULT=skip>
29626 10:58:09.917521 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3056 RESULT=skip
29628 10:58:09.961881 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3056 RESULT=skip
29630 10:58:09.962219 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3056 RESULT=skip>
29631 10:58:10.009976 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3072 RESULT=pass>
29632 10:58:10.010371 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3072 RESULT=pass
29634 10:58:10.058321 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3072 RESULT=skip
29636 10:58:10.058812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3072 RESULT=skip>
29637 10:58:10.109221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3072 RESULT=skip>
29638 10:58:10.109654 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3072 RESULT=skip
29640 10:58:10.158237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3088 RESULT=pass>
29641 10:58:10.158658 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3088 RESULT=pass
29643 10:58:10.206380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3088 RESULT=skip>
29644 10:58:10.206802 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3088 RESULT=skip
29646 10:58:10.249999 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3088 RESULT=skip
29648 10:58:10.250470 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3088 RESULT=skip>
29649 10:58:10.285903 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3104 RESULT=pass
29651 10:58:10.286325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3104 RESULT=pass>
29652 10:58:10.323997 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3104 RESULT=skip
29654 10:58:10.324572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3104 RESULT=skip>
29655 10:58:10.373157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3104 RESULT=skip>
29656 10:58:10.373575 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3104 RESULT=skip
29658 10:58:10.421526 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3120 RESULT=pass>
29659 10:58:10.421958 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3120 RESULT=pass
29661 10:58:10.470131 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3120 RESULT=skip>
29662 10:58:10.470558 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3120 RESULT=skip
29664 10:58:10.508329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3120 RESULT=skip>
29665 10:58:10.508755 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3120 RESULT=skip
29667 10:58:10.546772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3136 RESULT=pass>
29668 10:58:10.547200 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3136 RESULT=pass
29670 10:58:10.585198 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3136 RESULT=skip>
29671 10:58:10.585587 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3136 RESULT=skip
29673 10:58:10.629570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3136 RESULT=skip>
29674 10:58:10.629988 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3136 RESULT=skip
29676 10:58:10.665589 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3152 RESULT=pass>
29677 10:58:10.666098 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3152 RESULT=pass
29679 10:58:10.707029 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3152 RESULT=skip>
29680 10:58:10.707461 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3152 RESULT=skip
29682 10:58:10.746565 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3152 RESULT=skip>
29683 10:58:10.746965 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3152 RESULT=skip
29685 10:58:10.791668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3168 RESULT=pass>
29686 10:58:10.792103 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3168 RESULT=pass
29688 10:58:10.827130 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3168 RESULT=skip
29690 10:58:10.827598 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3168 RESULT=skip>
29691 10:58:10.876693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3168 RESULT=skip>
29692 10:58:10.877126 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3168 RESULT=skip
29694 10:58:10.913106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3184 RESULT=pass>
29695 10:58:10.913603 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3184 RESULT=pass
29697 10:58:10.959056 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3184 RESULT=skip>
29698 10:58:10.959480 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3184 RESULT=skip
29700 10:58:11.008634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3184 RESULT=skip>
29701 10:58:11.009052 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3184 RESULT=skip
29703 10:58:11.057140 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3200 RESULT=pass>
29704 10:58:11.057576 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3200 RESULT=pass
29706 10:58:11.093282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3200 RESULT=skip>
29707 10:58:11.093696 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3200 RESULT=skip
29709 10:58:11.137062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3200 RESULT=skip>
29710 10:58:11.137485 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3200 RESULT=skip
29712 10:58:11.178497 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3216 RESULT=pass>
29713 10:58:11.178923 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3216 RESULT=pass
29715 10:58:11.228883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3216 RESULT=skip>
29716 10:58:11.229310 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3216 RESULT=skip
29718 10:58:11.276892 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3216 RESULT=skip>
29719 10:58:11.277330 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3216 RESULT=skip
29721 10:58:11.325960 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3232 RESULT=pass
29723 10:58:11.326395 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3232 RESULT=pass>
29724 10:58:11.375277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3232 RESULT=skip>
29725 10:58:11.375700 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3232 RESULT=skip
29727 10:58:11.425407 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3232 RESULT=skip>
29728 10:58:11.425844 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3232 RESULT=skip
29730 10:58:11.461336 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3248 RESULT=pass>
29731 10:58:11.461779 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3248 RESULT=pass
29733 10:58:11.509153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3248 RESULT=skip>
29734 10:58:11.509574 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3248 RESULT=skip
29736 10:58:11.558358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3248 RESULT=skip>
29737 10:58:11.558649 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3248 RESULT=skip
29739 10:58:11.607225 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3264 RESULT=pass>
29740 10:58:11.607607 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3264 RESULT=pass
29742 10:58:11.655464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3264 RESULT=skip>
29743 10:58:11.655907 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3264 RESULT=skip
29745 10:58:11.702320 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3264 RESULT=skip
29747 10:58:11.702768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3264 RESULT=skip>
29748 10:58:11.737945 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3280 RESULT=pass
29750 10:58:11.738417 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3280 RESULT=pass>
29751 10:58:11.782699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3280 RESULT=skip>
29752 10:58:11.783095 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3280 RESULT=skip
29754 10:58:11.831878 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3280 RESULT=skip
29756 10:58:11.832329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3280 RESULT=skip>
29757 10:58:11.881392 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3296 RESULT=pass
29759 10:58:11.881816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3296 RESULT=pass>
29760 10:58:11.922149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3296 RESULT=skip>
29761 10:58:11.922560 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3296 RESULT=skip
29763 10:58:11.966152 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3296 RESULT=skip>
29764 10:58:11.966584 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3296 RESULT=skip
29766 10:58:12.006092 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3312 RESULT=pass>
29767 10:58:12.006539 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3312 RESULT=pass
29769 10:58:12.041957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3312 RESULT=skip>
29770 10:58:12.042406 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3312 RESULT=skip
29772 10:58:12.077482 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3312 RESULT=skip>
29773 10:58:12.078260 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3312 RESULT=skip
29775 10:58:12.124880 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3328 RESULT=pass
29777 10:58:12.125347 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3328 RESULT=pass>
29778 10:58:12.173389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3328 RESULT=skip>
29779 10:58:12.173838 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3328 RESULT=skip
29781 10:58:12.222429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3328 RESULT=skip>
29782 10:58:12.222861 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3328 RESULT=skip
29784 10:58:12.269673 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3344 RESULT=pass
29786 10:58:12.270144 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3344 RESULT=pass>
29787 10:58:12.318328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3344 RESULT=skip>
29788 10:58:12.318760 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3344 RESULT=skip
29790 10:58:12.366720 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3344 RESULT=skip>
29791 10:58:12.367140 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3344 RESULT=skip
29793 10:58:12.415569 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3360 RESULT=pass
29795 10:58:12.416031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3360 RESULT=pass>
29796 10:58:12.464617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3360 RESULT=skip>
29797 10:58:12.465056 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3360 RESULT=skip
29799 10:58:12.512952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3360 RESULT=skip>
29800 10:58:12.513377 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3360 RESULT=skip
29802 10:58:12.553785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3376 RESULT=pass>
29803 10:58:12.554209 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3376 RESULT=pass
29805 10:58:12.595740 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3376 RESULT=skip
29807 10:58:12.596220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3376 RESULT=skip>
29808 10:58:12.642351 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3376 RESULT=skip>
29809 10:58:12.642759 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3376 RESULT=skip
29811 10:58:12.691138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3392 RESULT=pass>
29812 10:58:12.691559 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3392 RESULT=pass
29814 10:58:12.741074 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3392 RESULT=skip
29816 10:58:12.741525 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3392 RESULT=skip>
29817 10:58:12.789599 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3392 RESULT=skip>
29818 10:58:12.789981 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3392 RESULT=skip
29820 10:58:12.830420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3408 RESULT=pass>
29821 10:58:12.830840 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3408 RESULT=pass
29823 10:58:12.866497 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3408 RESULT=skip
29825 10:58:12.866941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3408 RESULT=skip>
29826 10:58:12.914619 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3408 RESULT=skip
29828 10:58:12.915050 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3408 RESULT=skip>
29829 10:58:12.964311 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3424 RESULT=pass>
29830 10:58:12.964691 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3424 RESULT=pass
29832 10:58:13.012527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3424 RESULT=skip>
29833 10:58:13.012947 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3424 RESULT=skip
29835 10:58:13.082060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3424 RESULT=skip>
29836 10:58:13.082489 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3424 RESULT=skip
29838 10:58:13.115934 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3440 RESULT=pass
29840 10:58:13.116379 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3440 RESULT=pass>
29841 10:58:13.152643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3440 RESULT=skip>
29842 10:58:13.153045 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3440 RESULT=skip
29844 10:58:13.193988 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3440 RESULT=skip>
29845 10:58:13.194378 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3440 RESULT=skip
29847 10:58:13.231281 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3456 RESULT=pass
29849 10:58:13.231754 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3456 RESULT=pass>
29850 10:58:13.268659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3456 RESULT=skip>
29851 10:58:13.269101 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3456 RESULT=skip
29853 10:58:13.305965 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3456 RESULT=skip>
29854 10:58:13.306405 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3456 RESULT=skip
29856 10:58:13.342521 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3472 RESULT=pass>
29857 10:58:13.343327 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3472 RESULT=pass
29859 10:58:13.378144 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3472 RESULT=skip>
29860 10:58:13.378593 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3472 RESULT=skip
29862 10:58:13.414774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3472 RESULT=skip>
29863 10:58:13.415217 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3472 RESULT=skip
29865 10:58:13.450991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3488 RESULT=pass>
29866 10:58:13.451401 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3488 RESULT=pass
29868 10:58:13.486639 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3488 RESULT=skip>
29869 10:58:13.487079 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3488 RESULT=skip
29871 10:58:13.523516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3488 RESULT=skip>
29872 10:58:13.523970 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3488 RESULT=skip
29874 10:58:13.567683 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3504 RESULT=pass
29876 10:58:13.568156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3504 RESULT=pass>
29877 10:58:13.603456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3504 RESULT=skip>
29878 10:58:13.603898 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3504 RESULT=skip
29880 10:58:13.645260 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3504 RESULT=skip
29882 10:58:13.645743 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3504 RESULT=skip>
29883 10:58:13.694821 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3520 RESULT=pass
29885 10:58:13.695278 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3520 RESULT=pass>
29886 10:58:13.731186 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3520 RESULT=skip>
29887 10:58:13.731639 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3520 RESULT=skip
29889 10:58:13.768337 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3520 RESULT=skip>
29890 10:58:13.768779 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3520 RESULT=skip
29892 10:58:13.803997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3536 RESULT=pass>
29893 10:58:13.809781 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3536 RESULT=pass
29895 10:58:13.853607 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3536 RESULT=skip
29897 10:58:13.854114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3536 RESULT=skip>
29898 10:58:13.902288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3536 RESULT=skip>
29899 10:58:13.902619 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3536 RESULT=skip
29901 10:58:13.951009 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3552 RESULT=pass
29903 10:58:13.951431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3552 RESULT=pass>
29904 10:58:13.999256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3552 RESULT=skip>
29905 10:58:13.999675 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3552 RESULT=skip
29907 10:58:14.048408 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3552 RESULT=skip
29909 10:58:14.048869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3552 RESULT=skip>
29910 10:58:14.089157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3568 RESULT=pass>
29911 10:58:14.089681 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3568 RESULT=pass
29913 10:58:14.129518 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3568 RESULT=skip
29915 10:58:14.129960 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3568 RESULT=skip>
29916 10:58:14.166176 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3568 RESULT=skip
29918 10:58:14.166618 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3568 RESULT=skip>
29919 10:58:14.214258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3584 RESULT=pass>
29920 10:58:14.214689 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3584 RESULT=pass
29922 10:58:14.260947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3584 RESULT=skip>
29923 10:58:14.261362 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3584 RESULT=skip
29925 10:58:14.303108 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3584 RESULT=skip>
29926 10:58:14.303512 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3584 RESULT=skip
29928 10:58:14.350749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3600 RESULT=pass>
29929 10:58:14.351168 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3600 RESULT=pass
29931 10:58:14.399545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3600 RESULT=skip>
29932 10:58:14.399951 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3600 RESULT=skip
29934 10:58:14.447537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3600 RESULT=skip>
29935 10:58:14.447936 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3600 RESULT=skip
29937 10:58:14.494563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3616 RESULT=pass>
29938 10:58:14.494848 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3616 RESULT=pass
29940 10:58:14.543003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3616 RESULT=skip>
29941 10:58:14.543310 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3616 RESULT=skip
29943 10:58:14.590254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3616 RESULT=skip>
29944 10:58:14.590530 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3616 RESULT=skip
29946 10:58:14.637305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3632 RESULT=pass>
29947 10:58:14.637580 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3632 RESULT=pass
29949 10:58:14.683385 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3632 RESULT=skip>
29950 10:58:14.683687 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3632 RESULT=skip
29952 10:58:14.730655 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3632 RESULT=skip>
29953 10:58:14.730944 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3632 RESULT=skip
29955 10:58:14.769837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3648 RESULT=pass>
29956 10:58:14.770223 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3648 RESULT=pass
29958 10:58:14.817982 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3648 RESULT=skip
29960 10:58:14.818297 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3648 RESULT=skip>
29961 10:58:14.865504 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3648 RESULT=skip
29963 10:58:14.865815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3648 RESULT=skip>
29964 10:58:14.912916 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3664 RESULT=pass
29966 10:58:14.913218 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3664 RESULT=pass>
29967 10:58:14.958683 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3664 RESULT=skip>
29968 10:58:14.958975 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3664 RESULT=skip
29970 10:58:14.993256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3664 RESULT=skip>
29971 10:58:14.993696 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3664 RESULT=skip
29973 10:58:15.041032 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3680 RESULT=pass>
29974 10:58:15.041454 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3680 RESULT=pass
29976 10:58:15.088779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3680 RESULT=skip>
29977 10:58:15.089110 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3680 RESULT=skip
29979 10:58:15.129442 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3680 RESULT=skip
29981 10:58:15.129729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3680 RESULT=skip>
29982 10:58:15.177152 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3696 RESULT=pass>
29983 10:58:15.177446 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3696 RESULT=pass
29985 10:58:15.212578 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3696 RESULT=skip
29987 10:58:15.212887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3696 RESULT=skip>
29988 10:58:15.254623 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3696 RESULT=skip
29990 10:58:15.254863 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3696 RESULT=skip>
29991 10:58:15.301970 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3712 RESULT=pass
29993 10:58:15.302277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3712 RESULT=pass>
29994 10:58:15.349500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3712 RESULT=skip>
29995 10:58:15.349886 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3712 RESULT=skip
29997 10:58:15.397173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3712 RESULT=skip>
29998 10:58:15.397459 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3712 RESULT=skip
30000 10:58:15.444739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3728 RESULT=pass>
30001 10:58:15.445084 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3728 RESULT=pass
30003 10:58:15.488012 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3728 RESULT=skip
30005 10:58:15.488655 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3728 RESULT=skip>
30006 10:58:15.532946 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3728 RESULT=skip>
30007 10:58:15.533386 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3728 RESULT=skip
30009 10:58:15.579830 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3744 RESULT=pass
30011 10:58:15.580443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3744 RESULT=pass>
30012 10:58:15.615297 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3744 RESULT=skip>
30013 10:58:15.615746 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3744 RESULT=skip
30015 10:58:15.651717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3744 RESULT=skip>
30016 10:58:15.652173 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3744 RESULT=skip
30018 10:58:15.688167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3760 RESULT=pass>
30019 10:58:15.688609 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3760 RESULT=pass
30021 10:58:15.729910 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3760 RESULT=skip
30023 10:58:15.730356 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3760 RESULT=skip>
30024 10:58:15.777594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3760 RESULT=skip>
30025 10:58:15.778021 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3760 RESULT=skip
30027 10:58:15.813013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3776 RESULT=pass>
30028 10:58:15.813466 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3776 RESULT=pass
30030 10:58:15.848286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3776 RESULT=skip>
30031 10:58:15.848729 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3776 RESULT=skip
30033 10:58:15.883036 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3776 RESULT=skip>
30034 10:58:15.883476 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3776 RESULT=skip
30036 10:58:15.918770 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3792 RESULT=pass
30038 10:58:15.919190 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3792 RESULT=pass>
30039 10:58:15.966494 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3792 RESULT=skip
30041 10:58:15.966828 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3792 RESULT=skip>
30042 10:58:16.001280 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3792 RESULT=skip
30044 10:58:16.001741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3792 RESULT=skip>
30045 10:58:16.036441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3808 RESULT=pass>
30046 10:58:16.036881 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3808 RESULT=pass
30048 10:58:16.071675 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3808 RESULT=skip
30050 10:58:16.072155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3808 RESULT=skip>
30051 10:58:16.119244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3808 RESULT=skip>
30052 10:58:16.119673 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3808 RESULT=skip
30054 10:58:16.166376 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3824 RESULT=pass>
30055 10:58:16.166681 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3824 RESULT=pass
30057 10:58:16.213806 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3824 RESULT=skip
30059 10:58:16.214091 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3824 RESULT=skip>
30060 10:58:16.261663 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3824 RESULT=skip>
30061 10:58:16.261954 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3824 RESULT=skip
30063 10:58:16.303001 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3840 RESULT=pass
30065 10:58:16.303796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3840 RESULT=pass>
30066 10:58:16.350832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3840 RESULT=skip>
30067 10:58:16.351273 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3840 RESULT=skip
30069 10:58:16.398499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3840 RESULT=skip>
30070 10:58:16.398934 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3840 RESULT=skip
30072 10:58:16.446574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3856 RESULT=pass>
30073 10:58:16.447007 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3856 RESULT=pass
30075 10:58:16.495445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3856 RESULT=skip>
30076 10:58:16.495777 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3856 RESULT=skip
30078 10:58:16.543694 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3856 RESULT=skip
30080 10:58:16.544103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3856 RESULT=skip>
30081 10:58:16.591875 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3872 RESULT=pass
30083 10:58:16.592493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3872 RESULT=pass>
30084 10:58:16.633127 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3872 RESULT=skip>
30085 10:58:16.633419 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3872 RESULT=skip
30087 10:58:16.668261 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3872 RESULT=skip
30089 10:58:16.668566 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3872 RESULT=skip>
30090 10:58:16.715161 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3888 RESULT=pass
30092 10:58:16.715504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3888 RESULT=pass>
30093 10:58:16.762781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3888 RESULT=skip>
30094 10:58:16.763207 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3888 RESULT=skip
30096 10:58:16.803109 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3888 RESULT=skip
30098 10:58:16.803564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3888 RESULT=skip>
30099 10:58:16.844958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3904 RESULT=pass>
30100 10:58:16.845396 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3904 RESULT=pass
30102 10:58:16.880830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3904 RESULT=skip>
30103 10:58:16.881117 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3904 RESULT=skip
30105 10:58:16.915898 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3904 RESULT=skip
30107 10:58:16.916147 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3904 RESULT=skip>
30108 10:58:16.951565 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3920 RESULT=pass
30110 10:58:16.952045 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3920 RESULT=pass>
30111 10:58:16.987950 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3920 RESULT=skip
30113 10:58:16.988392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3920 RESULT=skip>
30114 10:58:17.023399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3920 RESULT=skip>
30115 10:58:17.023857 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3920 RESULT=skip
30117 10:58:17.058956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3936 RESULT=pass>
30118 10:58:17.059288 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3936 RESULT=pass
30120 10:58:17.096850 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3936 RESULT=skip>
30121 10:58:17.097142 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3936 RESULT=skip
30123 10:58:17.145785 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3936 RESULT=skip
30125 10:58:17.146103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3936 RESULT=skip>
30126 10:58:17.193081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3952 RESULT=pass>
30127 10:58:17.193372 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3952 RESULT=pass
30129 10:58:17.240893 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3952 RESULT=skip>
30130 10:58:17.241197 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3952 RESULT=skip
30132 10:58:17.286786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3952 RESULT=skip>
30133 10:58:17.287089 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3952 RESULT=skip
30135 10:58:17.334092 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3968 RESULT=pass
30137 10:58:17.334390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3968 RESULT=pass>
30138 10:58:17.381203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3968 RESULT=skip>
30139 10:58:17.381495 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3968 RESULT=skip
30141 10:58:17.428390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3968 RESULT=skip>
30142 10:58:17.428812 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3968 RESULT=skip
30144 10:58:17.462117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3984 RESULT=pass>
30145 10:58:17.462554 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3984 RESULT=pass
30147 10:58:17.497164 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3984 RESULT=skip>
30148 10:58:17.497598 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3984 RESULT=skip
30150 10:58:17.532534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3984 RESULT=skip>
30151 10:58:17.532969 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3984 RESULT=skip
30153 10:58:17.567383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4000 RESULT=pass>
30154 10:58:17.567801 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4000 RESULT=pass
30156 10:58:17.615053 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4000 RESULT=skip>
30157 10:58:17.615486 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4000 RESULT=skip
30159 10:58:17.662709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4000 RESULT=skip>
30160 10:58:17.663145 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4000 RESULT=skip
30162 10:58:17.709819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4016 RESULT=pass>
30163 10:58:17.710181 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4016 RESULT=pass
30165 10:58:17.757574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4016 RESULT=skip>
30166 10:58:17.757881 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4016 RESULT=skip
30168 10:58:17.805489 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4016 RESULT=skip>
30169 10:58:17.805951 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4016 RESULT=skip
30171 10:58:17.841584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4032 RESULT=pass>
30172 10:58:17.842399 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4032 RESULT=pass
30174 10:58:17.888462 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4032 RESULT=skip
30176 10:58:17.888935 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4032 RESULT=skip>
30177 10:58:17.936633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4032 RESULT=skip>
30178 10:58:17.936961 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4032 RESULT=skip
30180 10:58:17.983619 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4048 RESULT=pass
30182 10:58:17.983980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4048 RESULT=pass>
30183 10:58:18.030766 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4048 RESULT=skip
30185 10:58:18.031230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4048 RESULT=skip>
30186 10:58:18.078494 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4048 RESULT=skip
30188 10:58:18.078772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4048 RESULT=skip>
30189 10:58:18.125688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4064 RESULT=pass>
30190 10:58:18.125978 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4064 RESULT=pass
30192 10:58:18.190097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4064 RESULT=skip>
30193 10:58:18.190524 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4064 RESULT=skip
30195 10:58:18.229113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4064 RESULT=skip>
30196 10:58:18.229559 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4064 RESULT=skip
30198 10:58:18.264712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4080 RESULT=pass>
30199 10:58:18.265146 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4080 RESULT=pass
30201 10:58:18.311997 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4080 RESULT=skip
30203 10:58:18.312584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4080 RESULT=skip>
30204 10:58:18.359404 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4080 RESULT=skip>
30205 10:58:18.359806 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4080 RESULT=skip
30207 10:58:18.397681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4096 RESULT=pass>
30208 10:58:18.398107 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4096 RESULT=pass
30210 10:58:18.445593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4096 RESULT=skip>
30211 10:58:18.446043 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4096 RESULT=skip
30213 10:58:18.493637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4096 RESULT=skip>
30214 10:58:18.494064 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4096 RESULT=skip
30216 10:58:18.541640 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4112 RESULT=pass>
30217 10:58:18.542074 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4112 RESULT=pass
30219 10:58:18.587193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4112 RESULT=skip>
30220 10:58:18.587625 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4112 RESULT=skip
30222 10:58:18.635386 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4112 RESULT=skip>
30223 10:58:18.635824 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4112 RESULT=skip
30225 10:58:18.682839 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4128 RESULT=pass>
30226 10:58:18.683279 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4128 RESULT=pass
30228 10:58:18.731255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4128 RESULT=skip>
30229 10:58:18.731688 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4128 RESULT=skip
30231 10:58:18.778371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4128 RESULT=skip>
30232 10:58:18.778771 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4128 RESULT=skip
30234 10:58:18.825429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4144 RESULT=pass>
30235 10:58:18.825862 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4144 RESULT=pass
30237 10:58:18.876459 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4144 RESULT=skip
30239 10:58:18.876885 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4144 RESULT=skip>
30240 10:58:18.935146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4144 RESULT=skip>
30241 10:58:18.935480 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4144 RESULT=skip
30243 10:58:18.979459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4160 RESULT=pass>
30244 10:58:18.979751 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4160 RESULT=pass
30246 10:58:19.015425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4160 RESULT=skip>
30247 10:58:19.015724 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4160 RESULT=skip
30249 10:58:19.056674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4160 RESULT=skip>
30250 10:58:19.056976 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4160 RESULT=skip
30252 10:58:19.091373 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4176 RESULT=pass>
30253 10:58:19.091826 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4176 RESULT=pass
30255 10:58:19.146947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4176 RESULT=skip>
30256 10:58:19.147376 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4176 RESULT=skip
30258 10:58:19.208448 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4176 RESULT=skip>
30259 10:58:19.208888 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4176 RESULT=skip
30261 10:58:19.249055 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4192 RESULT=pass
30263 10:58:19.249502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4192 RESULT=pass>
30264 10:58:19.291202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4192 RESULT=skip>
30265 10:58:19.291618 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4192 RESULT=skip
30267 10:58:19.338820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4192 RESULT=skip>
30268 10:58:19.339256 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4192 RESULT=skip
30270 10:58:19.389333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4208 RESULT=pass>
30271 10:58:19.389764 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4208 RESULT=pass
30273 10:58:19.431202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4208 RESULT=skip>
30274 10:58:19.431599 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4208 RESULT=skip
30276 10:58:19.482267 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4208 RESULT=skip
30278 10:58:19.482696 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4208 RESULT=skip>
30279 10:58:19.533496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4224 RESULT=pass>
30280 10:58:19.533962 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4224 RESULT=pass
30282 10:58:19.587239 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4224 RESULT=skip>
30283 10:58:19.587694 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4224 RESULT=skip
30285 10:58:19.638440 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4224 RESULT=skip
30287 10:58:19.638859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4224 RESULT=skip>
30288 10:58:19.689471 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4240 RESULT=pass>
30289 10:58:19.689915 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4240 RESULT=pass
30291 10:58:19.740921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4240 RESULT=skip>
30292 10:58:19.741338 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4240 RESULT=skip
30294 10:58:19.795364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4240 RESULT=skip>
30295 10:58:19.795817 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4240 RESULT=skip
30297 10:58:19.846142 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4256 RESULT=pass>
30298 10:58:19.846549 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4256 RESULT=pass
30300 10:58:19.898418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4256 RESULT=skip>
30301 10:58:19.898801 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4256 RESULT=skip
30303 10:58:19.951158 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4256 RESULT=skip>
30304 10:58:19.951581 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4256 RESULT=skip
30306 10:58:20.002646 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4272 RESULT=pass>
30307 10:58:20.002980 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4272 RESULT=pass
30309 10:58:20.054559 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4272 RESULT=skip
30311 10:58:20.054990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4272 RESULT=skip>
30312 10:58:20.105327 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4272 RESULT=skip>
30313 10:58:20.105758 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4272 RESULT=skip
30315 10:58:20.155302 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4288 RESULT=pass
30317 10:58:20.155755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4288 RESULT=pass>
30318 10:58:20.206066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4288 RESULT=skip>
30319 10:58:20.206377 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4288 RESULT=skip
30321 10:58:20.257552 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4288 RESULT=skip
30323 10:58:20.257990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4288 RESULT=skip>
30324 10:58:20.308966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4304 RESULT=pass>
30325 10:58:20.309377 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4304 RESULT=pass
30327 10:58:20.359199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4304 RESULT=skip>
30328 10:58:20.359777 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4304 RESULT=skip
30330 10:58:20.411930 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4304 RESULT=skip
30332 10:58:20.412684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4304 RESULT=skip>
30333 10:58:20.462869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4320 RESULT=pass>
30334 10:58:20.463266 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4320 RESULT=pass
30336 10:58:20.515127 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4320 RESULT=skip
30338 10:58:20.515555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4320 RESULT=skip>
30339 10:58:20.566159 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4320 RESULT=skip>
30340 10:58:20.566575 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4320 RESULT=skip
30342 10:58:20.617617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4336 RESULT=pass>
30343 10:58:20.618684 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4336 RESULT=pass
30345 10:58:20.667716 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4336 RESULT=skip>
30346 10:58:20.668155 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4336 RESULT=skip
30348 10:58:20.718449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4336 RESULT=skip>
30349 10:58:20.718910 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4336 RESULT=skip
30351 10:58:20.769322 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4352 RESULT=pass>
30352 10:58:20.769775 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4352 RESULT=pass
30354 10:58:20.819647 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4352 RESULT=skip
30356 10:58:20.820085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4352 RESULT=skip>
30357 10:58:20.870751 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4352 RESULT=skip>
30358 10:58:20.871210 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4352 RESULT=skip
30360 10:58:20.921831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4368 RESULT=pass>
30361 10:58:20.922271 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4368 RESULT=pass
30363 10:58:20.973957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4368 RESULT=skip>
30364 10:58:20.974409 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4368 RESULT=skip
30366 10:58:21.027577 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4368 RESULT=skip
30368 10:58:21.027928 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4368 RESULT=skip>
30369 10:58:21.078190 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4384 RESULT=pass>
30370 10:58:21.078482 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4384 RESULT=pass
30372 10:58:21.129591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4384 RESULT=skip>
30373 10:58:21.130042 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4384 RESULT=skip
30375 10:58:21.179792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4384 RESULT=skip>
30376 10:58:21.180227 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4384 RESULT=skip
30378 10:58:21.230378 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4400 RESULT=pass
30380 10:58:21.230820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4400 RESULT=pass>
30381 10:58:21.281243 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4400 RESULT=skip
30383 10:58:21.281702 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4400 RESULT=skip>
30384 10:58:21.331011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4400 RESULT=skip>
30385 10:58:21.331393 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4400 RESULT=skip
30387 10:58:21.382924 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4416 RESULT=pass
30389 10:58:21.383368 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4416 RESULT=pass>
30390 10:58:21.433674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4416 RESULT=skip>
30391 10:58:21.434115 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4416 RESULT=skip
30393 10:58:21.485131 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4416 RESULT=skip>
30394 10:58:21.485560 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4416 RESULT=skip
30396 10:58:21.537156 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4432 RESULT=pass
30398 10:58:21.537602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4432 RESULT=pass>
30399 10:58:21.588044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4432 RESULT=skip>
30400 10:58:21.588469 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4432 RESULT=skip
30402 10:58:21.638269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4432 RESULT=skip>
30403 10:58:21.638696 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4432 RESULT=skip
30405 10:58:21.690555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4448 RESULT=pass>
30406 10:58:21.690972 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4448 RESULT=pass
30408 10:58:21.741674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4448 RESULT=skip>
30409 10:58:21.742072 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4448 RESULT=skip
30411 10:58:21.793353 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4448 RESULT=skip>
30412 10:58:21.793771 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4448 RESULT=skip
30414 10:58:21.845338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4464 RESULT=pass>
30415 10:58:21.845792 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4464 RESULT=pass
30417 10:58:21.897608 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4464 RESULT=skip
30419 10:58:21.898097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4464 RESULT=skip>
30420 10:58:21.949003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4464 RESULT=skip>
30421 10:58:21.949385 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4464 RESULT=skip
30423 10:58:21.998902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4480 RESULT=pass>
30424 10:58:21.999343 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4480 RESULT=pass
30426 10:58:22.049924 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4480 RESULT=skip
30428 10:58:22.050420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4480 RESULT=skip>
30429 10:58:22.102187 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4480 RESULT=skip>
30430 10:58:22.102611 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4480 RESULT=skip
30432 10:58:22.154029 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4496 RESULT=pass>
30433 10:58:22.154433 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4496 RESULT=pass
30435 10:58:22.205341 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4496 RESULT=skip>
30436 10:58:22.205809 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4496 RESULT=skip
30438 10:58:22.255462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4496 RESULT=skip>
30439 10:58:22.255919 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4496 RESULT=skip
30441 10:58:22.305786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4512 RESULT=pass>
30442 10:58:22.306270 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4512 RESULT=pass
30444 10:58:22.357197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4512 RESULT=skip>
30445 10:58:22.357619 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4512 RESULT=skip
30447 10:58:22.408018 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4512 RESULT=skip
30449 10:58:22.408427 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4512 RESULT=skip>
30450 10:58:22.458769 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4528 RESULT=pass
30452 10:58:22.459214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4528 RESULT=pass>
30453 10:58:22.510150 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4528 RESULT=skip>
30454 10:58:22.510522 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4528 RESULT=skip
30456 10:58:22.561914 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4528 RESULT=skip
30458 10:58:22.562781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4528 RESULT=skip>
30459 10:58:22.610435 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4544 RESULT=pass>
30460 10:58:22.610861 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4544 RESULT=pass
30462 10:58:22.657845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4544 RESULT=skip>
30463 10:58:22.658253 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4544 RESULT=skip
30465 10:58:22.704425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4544 RESULT=skip>
30466 10:58:22.704838 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4544 RESULT=skip
30468 10:58:22.750807 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4560 RESULT=pass
30470 10:58:22.751211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4560 RESULT=pass>
30471 10:58:22.797602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4560 RESULT=skip>
30472 10:58:22.798031 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4560 RESULT=skip
30474 10:58:22.843415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4560 RESULT=skip>
30475 10:58:22.843846 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4560 RESULT=skip
30477 10:58:22.889551 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4576 RESULT=pass
30479 10:58:22.890095 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4576 RESULT=pass>
30480 10:58:22.935131 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4576 RESULT=skip>
30481 10:58:22.935482 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4576 RESULT=skip
30483 10:58:22.983096 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4576 RESULT=skip>
30484 10:58:22.983508 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4576 RESULT=skip
30486 10:58:23.029557 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4592 RESULT=pass
30488 10:58:23.030014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4592 RESULT=pass>
30489 10:58:23.075053 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4592 RESULT=skip>
30490 10:58:23.075470 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4592 RESULT=skip
30492 10:58:23.121274 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4592 RESULT=skip
30494 10:58:23.121747 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4592 RESULT=skip>
30495 10:58:23.166810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4608 RESULT=pass>
30496 10:58:23.167241 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4608 RESULT=pass
30498 10:58:23.213046 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4608 RESULT=skip
30500 10:58:23.213530 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4608 RESULT=skip>
30501 10:58:23.259916 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4608 RESULT=skip
30503 10:58:23.260358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4608 RESULT=skip>
30504 10:58:23.329627 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4624 RESULT=pass
30506 10:58:23.330090 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4624 RESULT=pass>
30507 10:58:23.375166 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4624 RESULT=skip
30509 10:58:23.375621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4624 RESULT=skip>
30510 10:58:23.421299 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4624 RESULT=skip>
30511 10:58:23.421689 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4624 RESULT=skip
30513 10:58:23.467090 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4640 RESULT=pass>
30514 10:58:23.467439 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4640 RESULT=pass
30516 10:58:23.514471 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4640 RESULT=skip
30518 10:58:23.514896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4640 RESULT=skip>
30519 10:58:23.560917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4640 RESULT=skip>
30520 10:58:23.561336 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4640 RESULT=skip
30522 10:58:23.606967 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4656 RESULT=pass
30524 10:58:23.607420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4656 RESULT=pass>
30525 10:58:23.653380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4656 RESULT=skip>
30526 10:58:23.653805 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4656 RESULT=skip
30528 10:58:23.699521 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4656 RESULT=skip>
30529 10:58:23.699901 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4656 RESULT=skip
30531 10:58:23.745583 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4672 RESULT=pass
30533 10:58:23.745951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4672 RESULT=pass>
30534 10:58:23.791803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4672 RESULT=skip>
30535 10:58:23.792243 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4672 RESULT=skip
30537 10:58:23.837894 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4672 RESULT=skip
30539 10:58:23.838220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4672 RESULT=skip>
30540 10:58:23.884804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4688 RESULT=pass>
30541 10:58:23.885210 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4688 RESULT=pass
30543 10:58:23.930921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4688 RESULT=skip>
30544 10:58:23.931305 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4688 RESULT=skip
30546 10:58:23.977627 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4688 RESULT=skip
30548 10:58:23.978115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4688 RESULT=skip>
30549 10:58:24.023547 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4704 RESULT=pass
30551 10:58:24.023934 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4704 RESULT=pass>
30552 10:58:24.069478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4704 RESULT=skip>
30553 10:58:24.069880 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4704 RESULT=skip
30555 10:58:24.115810 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4704 RESULT=skip
30557 10:58:24.116269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4704 RESULT=skip>
30558 10:58:24.161920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4720 RESULT=pass>
30559 10:58:24.162337 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4720 RESULT=pass
30561 10:58:24.209460 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4720 RESULT=skip
30563 10:58:24.209979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4720 RESULT=skip>
30564 10:58:24.255480 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4720 RESULT=skip
30566 10:58:24.255865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4720 RESULT=skip>
30567 10:58:24.301349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4736 RESULT=pass>
30568 10:58:24.301741 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4736 RESULT=pass
30570 10:58:24.347037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4736 RESULT=skip>
30571 10:58:24.347405 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4736 RESULT=skip
30573 10:58:24.393238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4736 RESULT=skip>
30574 10:58:24.393638 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4736 RESULT=skip
30576 10:58:24.439014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4752 RESULT=pass>
30577 10:58:24.439383 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4752 RESULT=pass
30579 10:58:24.486482 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4752 RESULT=skip>
30580 10:58:24.486879 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4752 RESULT=skip
30582 10:58:24.533391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4752 RESULT=skip>
30583 10:58:24.533798 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4752 RESULT=skip
30585 10:58:24.579771 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4768 RESULT=pass
30587 10:58:24.580192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4768 RESULT=pass>
30588 10:58:24.625844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4768 RESULT=skip>
30589 10:58:24.626248 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4768 RESULT=skip
30591 10:58:24.672457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4768 RESULT=skip>
30592 10:58:24.672852 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4768 RESULT=skip
30594 10:58:24.718185 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4784 RESULT=pass>
30595 10:58:24.718557 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4784 RESULT=pass
30597 10:58:24.764659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4784 RESULT=skip>
30598 10:58:24.765064 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4784 RESULT=skip
30600 10:58:24.810864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4784 RESULT=skip>
30601 10:58:24.811285 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4784 RESULT=skip
30603 10:58:24.856874 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4800 RESULT=pass>
30604 10:58:24.857296 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4800 RESULT=pass
30606 10:58:24.902897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4800 RESULT=skip>
30607 10:58:24.903316 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4800 RESULT=skip
30609 10:58:24.949467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4800 RESULT=skip>
30610 10:58:24.949892 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4800 RESULT=skip
30612 10:58:24.997365 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4816 RESULT=pass
30614 10:58:24.997804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4816 RESULT=pass>
30615 10:58:25.043395 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4816 RESULT=skip>
30616 10:58:25.043805 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4816 RESULT=skip
30618 10:58:25.089342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4816 RESULT=skip>
30619 10:58:25.089754 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4816 RESULT=skip
30621 10:58:25.134675 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4832 RESULT=pass
30623 10:58:25.135096 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4832 RESULT=pass>
30624 10:58:25.180846 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4832 RESULT=skip>
30625 10:58:25.181231 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4832 RESULT=skip
30627 10:58:25.226748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4832 RESULT=skip>
30628 10:58:25.227106 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4832 RESULT=skip
30630 10:58:25.272879 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4848 RESULT=pass>
30631 10:58:25.273319 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4848 RESULT=pass
30633 10:58:25.318158 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4848 RESULT=skip
30635 10:58:25.318611 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4848 RESULT=skip>
30636 10:58:25.365419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4848 RESULT=skip>
30637 10:58:25.365825 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4848 RESULT=skip
30639 10:58:25.412513 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4864 RESULT=pass
30641 10:58:25.412985 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4864 RESULT=pass>
30642 10:58:25.458468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4864 RESULT=skip>
30643 10:58:25.458906 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4864 RESULT=skip
30645 10:58:25.505378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4864 RESULT=skip>
30646 10:58:25.505804 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4864 RESULT=skip
30648 10:58:25.551289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4880 RESULT=pass>
30649 10:58:25.551739 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4880 RESULT=pass
30651 10:58:25.598993 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4880 RESULT=skip>
30652 10:58:25.599372 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4880 RESULT=skip
30654 10:58:25.645804 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4880 RESULT=skip
30656 10:58:25.646219 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4880 RESULT=skip>
30657 10:58:25.691257 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4896 RESULT=pass
30659 10:58:25.691660 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4896 RESULT=pass>
30660 10:58:25.737568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4896 RESULT=skip>
30661 10:58:25.737968 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4896 RESULT=skip
30663 10:58:25.784215 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4896 RESULT=skip>
30664 10:58:25.784612 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4896 RESULT=skip
30666 10:58:25.830085 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4912 RESULT=pass
30668 10:58:25.830497 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4912 RESULT=pass>
30669 10:58:25.878271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4912 RESULT=skip>
30670 10:58:25.878668 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4912 RESULT=skip
30672 10:58:25.925669 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4912 RESULT=skip
30674 10:58:25.926217 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4912 RESULT=skip>
30675 10:58:25.973693 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4928 RESULT=pass
30677 10:58:25.974106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4928 RESULT=pass>
30678 10:58:26.021184 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4928 RESULT=skip
30680 10:58:26.021605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4928 RESULT=skip>
30681 10:58:26.067250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4928 RESULT=skip>
30682 10:58:26.067651 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4928 RESULT=skip
30684 10:58:26.113899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4944 RESULT=pass>
30685 10:58:26.114308 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4944 RESULT=pass
30687 10:58:26.161993 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4944 RESULT=skip>
30688 10:58:26.162413 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4944 RESULT=skip
30690 10:58:26.209258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4944 RESULT=skip>
30691 10:58:26.209675 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4944 RESULT=skip
30693 10:58:26.257186 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4960 RESULT=pass>
30694 10:58:26.257618 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4960 RESULT=pass
30696 10:58:26.303788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4960 RESULT=skip>
30697 10:58:26.304209 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4960 RESULT=skip
30699 10:58:26.350474 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4960 RESULT=skip>
30700 10:58:26.350899 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4960 RESULT=skip
30702 10:58:26.397378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4976 RESULT=pass>
30703 10:58:26.397788 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4976 RESULT=pass
30705 10:58:26.444917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4976 RESULT=skip>
30706 10:58:26.445288 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4976 RESULT=skip
30708 10:58:26.492597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4976 RESULT=skip>
30709 10:58:26.492979 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4976 RESULT=skip
30711 10:58:26.539002 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4992 RESULT=pass>
30712 10:58:26.539442 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4992 RESULT=pass
30714 10:58:26.586192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4992 RESULT=skip>
30715 10:58:26.586624 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4992 RESULT=skip
30717 10:58:26.633322 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4992 RESULT=skip>
30718 10:58:26.633765 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4992 RESULT=skip
30720 10:58:26.679793 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5008 RESULT=pass
30722 10:58:26.680239 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5008 RESULT=pass>
30723 10:58:26.727485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5008 RESULT=skip>
30724 10:58:26.727881 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5008 RESULT=skip
30726 10:58:26.774421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5008 RESULT=skip>
30727 10:58:26.774819 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5008 RESULT=skip
30729 10:58:26.821408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5024 RESULT=pass>
30730 10:58:26.821818 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5024 RESULT=pass
30732 10:58:26.868404 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5024 RESULT=skip>
30733 10:58:26.868822 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5024 RESULT=skip
30735 10:58:26.915169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5024 RESULT=skip>
30736 10:58:26.915582 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5024 RESULT=skip
30738 10:58:26.963327 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5040 RESULT=pass>
30739 10:58:26.963744 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5040 RESULT=pass
30741 10:58:27.010670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5040 RESULT=skip>
30742 10:58:27.011018 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5040 RESULT=skip
30744 10:58:27.057697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5040 RESULT=skip>
30745 10:58:27.058105 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5040 RESULT=skip
30747 10:58:27.105912 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5056 RESULT=pass>
30748 10:58:27.106260 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5056 RESULT=pass
30750 10:58:27.153305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5056 RESULT=skip>
30751 10:58:27.153697 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5056 RESULT=skip
30753 10:58:27.200904 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5056 RESULT=skip
30755 10:58:27.201389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5056 RESULT=skip>
30756 10:58:27.246810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5072 RESULT=pass>
30757 10:58:27.247220 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5072 RESULT=pass
30759 10:58:27.293393 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5072 RESULT=skip>
30760 10:58:27.293799 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5072 RESULT=skip
30762 10:58:27.339885 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5072 RESULT=skip
30764 10:58:27.340332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5072 RESULT=skip>
30765 10:58:27.386162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5088 RESULT=pass>
30766 10:58:27.386544 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5088 RESULT=pass
30768 10:58:27.433162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5088 RESULT=skip>
30769 10:58:27.433547 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5088 RESULT=skip
30771 10:58:27.481413 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5088 RESULT=skip>
30772 10:58:27.481808 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5088 RESULT=skip
30774 10:58:27.528993 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5104 RESULT=pass>
30775 10:58:27.529395 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5104 RESULT=pass
30777 10:58:27.575817 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5104 RESULT=skip
30779 10:58:27.576386 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5104 RESULT=skip>
30780 10:58:27.623071 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5104 RESULT=skip>
30781 10:58:27.623466 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5104 RESULT=skip
30783 10:58:27.670123 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5120 RESULT=pass>
30784 10:58:27.670537 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5120 RESULT=pass
30786 10:58:27.717182 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5120 RESULT=skip
30788 10:58:27.717597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5120 RESULT=skip>
30789 10:58:27.765311 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5120 RESULT=skip>
30790 10:58:27.765687 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5120 RESULT=skip
30792 10:58:27.811540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5136 RESULT=pass>
30793 10:58:27.811892 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5136 RESULT=pass
30795 10:58:27.858094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5136 RESULT=skip>
30796 10:58:27.858492 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5136 RESULT=skip
30798 10:58:27.905540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5136 RESULT=skip>
30799 10:58:27.905948 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5136 RESULT=skip
30801 10:58:27.952560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5152 RESULT=pass>
30802 10:58:27.952978 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5152 RESULT=pass
30804 10:58:28.002294 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5152 RESULT=skip>
30805 10:58:28.002647 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5152 RESULT=skip
30807 10:58:28.049815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5152 RESULT=skip>
30808 10:58:28.050220 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5152 RESULT=skip
30810 10:58:28.097138 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5168 RESULT=pass
30812 10:58:28.097590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5168 RESULT=pass>
30813 10:58:28.142861 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5168 RESULT=skip
30815 10:58:28.143307 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5168 RESULT=skip>
30816 10:58:28.189501 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5168 RESULT=skip>
30817 10:58:28.189924 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5168 RESULT=skip
30819 10:58:28.235299 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5184 RESULT=pass>
30820 10:58:28.235741 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5184 RESULT=pass
30822 10:58:28.282342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5184 RESULT=skip>
30823 10:58:28.282770 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5184 RESULT=skip
30825 10:58:28.329408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5184 RESULT=skip>
30826 10:58:28.329828 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5184 RESULT=skip
30828 10:58:28.376071 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5200 RESULT=pass
30830 10:58:28.376513 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5200 RESULT=pass>
30831 10:58:28.446923 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5200 RESULT=skip
30833 10:58:28.447351 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5200 RESULT=skip>
30834 10:58:28.493688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5200 RESULT=skip>
30835 10:58:28.494093 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5200 RESULT=skip
30837 10:58:28.539764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5216 RESULT=pass>
30838 10:58:28.540168 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5216 RESULT=pass
30840 10:58:28.586923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5216 RESULT=skip>
30841 10:58:28.587327 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5216 RESULT=skip
30843 10:58:28.635386 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5216 RESULT=skip>
30844 10:58:28.635807 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5216 RESULT=skip
30846 10:58:28.681732 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5232 RESULT=pass>
30847 10:58:28.682149 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5232 RESULT=pass
30849 10:58:28.728986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5232 RESULT=skip>
30850 10:58:28.729418 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5232 RESULT=skip
30852 10:58:28.777394 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5232 RESULT=skip>
30853 10:58:28.777811 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5232 RESULT=skip
30855 10:58:28.824882 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5248 RESULT=pass>
30856 10:58:28.825291 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5248 RESULT=pass
30858 10:58:28.871361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5248 RESULT=skip>
30859 10:58:28.873213 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5248 RESULT=skip
30861 10:58:28.922250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5248 RESULT=skip>
30862 10:58:28.922630 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5248 RESULT=skip
30864 10:58:28.973415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5264 RESULT=pass>
30865 10:58:28.973825 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5264 RESULT=pass
30867 10:58:29.023915 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5264 RESULT=skip
30869 10:58:29.024358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5264 RESULT=skip>
30870 10:58:29.072881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5264 RESULT=skip>
30871 10:58:29.073300 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5264 RESULT=skip
30873 10:58:29.119122 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5280 RESULT=pass
30875 10:58:29.119577 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5280 RESULT=pass>
30876 10:58:29.168832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5280 RESULT=skip>
30877 10:58:29.169236 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5280 RESULT=skip
30879 10:58:29.218820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5280 RESULT=skip>
30880 10:58:29.219256 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5280 RESULT=skip
30882 10:58:29.268430 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5296 RESULT=pass>
30883 10:58:29.268830 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5296 RESULT=pass
30885 10:58:29.315903 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5296 RESULT=skip
30887 10:58:29.316361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5296 RESULT=skip>
30888 10:58:29.348742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5296 RESULT=skip>
30889 10:58:29.349150 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5296 RESULT=skip
30891 10:58:29.382013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5312 RESULT=pass>
30892 10:58:29.382451 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5312 RESULT=pass
30894 10:58:29.420128 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5312 RESULT=skip
30896 10:58:29.420613 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5312 RESULT=skip>
30897 10:58:29.464840 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5312 RESULT=skip
30899 10:58:29.465294 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5312 RESULT=skip>
30900 10:58:29.509549 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5328 RESULT=pass
30902 10:58:29.510036 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5328 RESULT=pass>
30903 10:58:29.546013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5328 RESULT=skip>
30904 10:58:29.546442 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5328 RESULT=skip
30906 10:58:29.584944 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5328 RESULT=skip>
30907 10:58:29.585356 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5328 RESULT=skip
30909 10:58:29.623447 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5344 RESULT=pass>
30910 10:58:29.623853 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5344 RESULT=pass
30912 10:58:29.666978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5344 RESULT=skip>
30913 10:58:29.667376 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5344 RESULT=skip
30915 10:58:29.706722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5344 RESULT=skip>
30916 10:58:29.707155 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5344 RESULT=skip
30918 10:58:29.739766 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5360 RESULT=pass>
30919 10:58:29.740212 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5360 RESULT=pass
30921 10:58:29.773058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5360 RESULT=skip>
30922 10:58:29.773446 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5360 RESULT=skip
30924 10:58:29.817206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5360 RESULT=skip>
30925 10:58:29.817606 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5360 RESULT=skip
30927 10:58:29.862474 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5376 RESULT=pass>
30928 10:58:29.862892 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5376 RESULT=pass
30930 10:58:29.907566 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5376 RESULT=skip
30932 10:58:29.908003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5376 RESULT=skip>
30933 10:58:29.953028 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5376 RESULT=skip
30935 10:58:29.953471 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5376 RESULT=skip>
30936 10:58:29.997274 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5392 RESULT=pass
30938 10:58:29.997734 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5392 RESULT=pass>
30939 10:58:30.037092 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5392 RESULT=skip>
30940 10:58:30.037506 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5392 RESULT=skip
30942 10:58:30.077816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5392 RESULT=skip>
30943 10:58:30.078208 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5392 RESULT=skip
30945 10:58:30.119173 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5408 RESULT=pass
30947 10:58:30.119605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5408 RESULT=pass>
30948 10:58:30.161436 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5408 RESULT=skip
30950 10:58:30.161893 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5408 RESULT=skip>
30951 10:58:30.204398 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5408 RESULT=skip
30953 10:58:30.204833 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5408 RESULT=skip>
30954 10:58:30.236604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5424 RESULT=pass>
30955 10:58:30.237043 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5424 RESULT=pass
30957 10:58:30.280875 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5424 RESULT=skip>
30958 10:58:30.281291 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5424 RESULT=skip
30960 10:58:30.325413 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5424 RESULT=skip>
30961 10:58:30.325829 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5424 RESULT=skip
30963 10:58:30.370112 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5440 RESULT=pass>
30964 10:58:30.370549 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5440 RESULT=pass
30966 10:58:30.414010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5440 RESULT=skip>
30967 10:58:30.414441 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5440 RESULT=skip
30969 10:58:30.453243 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5440 RESULT=skip>
30970 10:58:30.453665 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5440 RESULT=skip
30972 10:58:30.496234 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5456 RESULT=pass
30974 10:58:30.496643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5456 RESULT=pass>
30975 10:58:30.542502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5456 RESULT=skip>
30976 10:58:30.542931 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5456 RESULT=skip
30978 10:58:30.589372 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5456 RESULT=skip
30980 10:58:30.589813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5456 RESULT=skip>
30981 10:58:30.636328 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5472 RESULT=pass
30983 10:58:30.636756 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5472 RESULT=pass>
30984 10:58:30.683006 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5472 RESULT=skip>
30985 10:58:30.683411 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5472 RESULT=skip
30987 10:58:30.730862 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5472 RESULT=skip
30989 10:58:30.731329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5472 RESULT=skip>
30990 10:58:30.779383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5488 RESULT=pass>
30991 10:58:30.779808 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5488 RESULT=pass
30993 10:58:30.826705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5488 RESULT=skip>
30994 10:58:30.827125 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5488 RESULT=skip
30996 10:58:30.874780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5488 RESULT=skip>
30997 10:58:30.875197 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5488 RESULT=skip
30999 10:58:30.924706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5504 RESULT=pass>
31000 10:58:30.925135 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5504 RESULT=pass
31002 10:58:30.972291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5504 RESULT=skip>
31003 10:58:30.972668 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5504 RESULT=skip
31005 10:58:31.018813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5504 RESULT=skip>
31006 10:58:31.019209 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5504 RESULT=skip
31008 10:58:31.065891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5520 RESULT=pass>
31009 10:58:31.066308 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5520 RESULT=pass
31011 10:58:31.114204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5520 RESULT=skip>
31012 10:58:31.114617 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5520 RESULT=skip
31014 10:58:31.161467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5520 RESULT=skip>
31015 10:58:31.161888 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5520 RESULT=skip
31017 10:58:31.207852 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5536 RESULT=pass
31019 10:58:31.208411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5536 RESULT=pass>
31020 10:58:31.254835 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5536 RESULT=skip>
31021 10:58:31.255235 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5536 RESULT=skip
31023 10:58:31.302113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5536 RESULT=skip>
31024 10:58:31.302504 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5536 RESULT=skip
31026 10:58:31.349094 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5552 RESULT=pass
31028 10:58:31.349519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5552 RESULT=pass>
31029 10:58:31.396949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5552 RESULT=skip>
31030 10:58:31.397356 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5552 RESULT=skip
31032 10:58:31.443092 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5552 RESULT=skip>
31033 10:58:31.443448 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5552 RESULT=skip
31035 10:58:31.490084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5568 RESULT=pass>
31036 10:58:31.490472 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5568 RESULT=pass
31038 10:58:31.535895 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5568 RESULT=skip
31040 10:58:31.536407 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5568 RESULT=skip>
31041 10:58:31.581925 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5568 RESULT=skip
31043 10:58:31.582366 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5568 RESULT=skip>
31044 10:58:31.627314 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5584 RESULT=pass>
31045 10:58:31.627745 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5584 RESULT=pass
31047 10:58:31.673334 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5584 RESULT=skip>
31048 10:58:31.673690 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5584 RESULT=skip
31050 10:58:31.718976 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5584 RESULT=skip
31052 10:58:31.719422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5584 RESULT=skip>
31053 10:58:31.764877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5600 RESULT=pass>
31054 10:58:31.765238 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5600 RESULT=pass
31056 10:58:31.810612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5600 RESULT=skip>
31057 10:58:31.811027 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5600 RESULT=skip
31059 10:58:31.858273 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5600 RESULT=skip
31061 10:58:31.858709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5600 RESULT=skip>
31062 10:58:31.904407 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5616 RESULT=pass
31064 10:58:31.904862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5616 RESULT=pass>
31065 10:58:31.949837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5616 RESULT=skip>
31066 10:58:31.950236 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5616 RESULT=skip
31068 10:58:31.995138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5616 RESULT=skip>
31069 10:58:31.995572 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5616 RESULT=skip
31071 10:58:32.041316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5632 RESULT=pass>
31072 10:58:32.041677 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5632 RESULT=pass
31074 10:58:32.087172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5632 RESULT=skip>
31075 10:58:32.087597 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5632 RESULT=skip
31077 10:58:32.134457 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5632 RESULT=skip
31079 10:58:32.134938 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5632 RESULT=skip>
31080 10:58:32.180935 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5648 RESULT=pass
31082 10:58:32.181383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5648 RESULT=pass>
31083 10:58:32.227349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5648 RESULT=skip>
31084 10:58:32.227757 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5648 RESULT=skip
31086 10:58:32.274037 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5648 RESULT=skip
31088 10:58:32.274467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5648 RESULT=skip>
31089 10:58:32.320474 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5664 RESULT=pass>
31090 10:58:32.320889 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5664 RESULT=pass
31092 10:58:32.367787 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5664 RESULT=skip
31094 10:58:32.368255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5664 RESULT=skip>
31095 10:58:32.414436 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5664 RESULT=skip
31097 10:58:32.414801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5664 RESULT=skip>
31098 10:58:32.461188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5680 RESULT=pass>
31099 10:58:32.461594 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5680 RESULT=pass
31101 10:58:32.507144 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5680 RESULT=skip>
31102 10:58:32.507567 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5680 RESULT=skip
31104 10:58:32.553578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5680 RESULT=skip>
31105 10:58:32.553958 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5680 RESULT=skip
31107 10:58:32.599334 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5696 RESULT=pass>
31108 10:58:32.599757 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5696 RESULT=pass
31110 10:58:32.645521 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5696 RESULT=skip>
31111 10:58:32.645922 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5696 RESULT=skip
31113 10:58:32.691865 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5696 RESULT=skip
31115 10:58:32.692373 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5696 RESULT=skip>
31116 10:58:32.737707 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5712 RESULT=pass>
31117 10:58:32.738093 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5712 RESULT=pass
31119 10:58:32.784386 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5712 RESULT=skip>
31120 10:58:32.784808 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5712 RESULT=skip
31122 10:58:32.829869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5712 RESULT=skip>
31123 10:58:32.830290 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5712 RESULT=skip
31125 10:58:32.876424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5728 RESULT=pass>
31126 10:58:32.876805 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5728 RESULT=pass
31128 10:58:32.921778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5728 RESULT=skip>
31129 10:58:32.922210 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5728 RESULT=skip
31131 10:58:32.968414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5728 RESULT=skip>
31132 10:58:32.968845 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5728 RESULT=skip
31134 10:58:33.013545 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5744 RESULT=pass
31136 10:58:33.013989 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5744 RESULT=pass>
31137 10:58:33.058987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5744 RESULT=skip>
31138 10:58:33.059426 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5744 RESULT=skip
31140 10:58:33.105473 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5744 RESULT=skip
31142 10:58:33.105926 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5744 RESULT=skip>
31143 10:58:33.150657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5760 RESULT=pass>
31144 10:58:33.151108 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5760 RESULT=pass
31146 10:58:33.196683 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5760 RESULT=skip>
31147 10:58:33.197096 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5760 RESULT=skip
31149 10:58:33.242646 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5760 RESULT=skip>
31150 10:58:33.243066 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5760 RESULT=skip
31152 10:58:33.288379 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5776 RESULT=pass
31154 10:58:33.288851 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5776 RESULT=pass>
31155 10:58:33.334930 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5776 RESULT=skip
31157 10:58:33.335402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5776 RESULT=skip>
31158 10:58:33.381111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5776 RESULT=skip>
31159 10:58:33.381549 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5776 RESULT=skip
31161 10:58:33.426703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5792 RESULT=pass>
31162 10:58:33.427133 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5792 RESULT=pass
31164 10:58:33.473563 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5792 RESULT=skip
31166 10:58:33.474009 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5792 RESULT=skip>
31167 10:58:33.527596 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5792 RESULT=skip
31169 10:58:33.527996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5792 RESULT=skip>
31170 10:58:33.595845 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5808 RESULT=pass
31172 10:58:33.596281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5808 RESULT=pass>
31173 10:58:33.643029 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5808 RESULT=skip>
31174 10:58:33.643434 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5808 RESULT=skip
31176 10:58:33.691409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5808 RESULT=skip>
31177 10:58:33.691832 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5808 RESULT=skip
31179 10:58:33.737517 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5824 RESULT=pass>
31180 10:58:33.737957 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5824 RESULT=pass
31182 10:58:33.783064 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5824 RESULT=skip>
31183 10:58:33.783469 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5824 RESULT=skip
31185 10:58:33.829091 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5824 RESULT=skip>
31186 10:58:33.829520 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5824 RESULT=skip
31188 10:58:33.876584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5840 RESULT=pass>
31189 10:58:33.881720 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5840 RESULT=pass
31191 10:58:33.925596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5840 RESULT=skip>
31192 10:58:33.926021 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5840 RESULT=skip
31194 10:58:33.975187 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5840 RESULT=skip
31196 10:58:33.975649 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5840 RESULT=skip>
31197 10:58:34.025067 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5856 RESULT=pass
31199 10:58:34.025512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5856 RESULT=pass>
31200 10:58:34.064812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5856 RESULT=skip>
31201 10:58:34.065246 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5856 RESULT=skip
31203 10:58:34.098955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5856 RESULT=skip>
31204 10:58:34.099338 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5856 RESULT=skip
31206 10:58:34.130390 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5872 RESULT=pass
31208 10:58:34.130840 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5872 RESULT=pass>
31209 10:58:34.181479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5872 RESULT=skip>
31210 10:58:34.181893 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5872 RESULT=skip
31212 10:58:34.239516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5872 RESULT=skip>
31213 10:58:34.239943 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5872 RESULT=skip
31215 10:58:34.294300 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5888 RESULT=pass
31217 10:58:34.294765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5888 RESULT=pass>
31218 10:58:34.341252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5888 RESULT=skip>
31219 10:58:34.341702 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5888 RESULT=skip
31221 10:58:34.381855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5888 RESULT=skip>
31222 10:58:34.382272 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5888 RESULT=skip
31224 10:58:34.420561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5904 RESULT=pass>
31225 10:58:34.420934 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5904 RESULT=pass
31227 10:58:34.467592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5904 RESULT=skip>
31228 10:58:34.468011 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5904 RESULT=skip
31230 10:58:34.521770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5904 RESULT=skip>
31231 10:58:34.522190 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5904 RESULT=skip
31233 10:58:34.571334 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5920 RESULT=pass>
31234 10:58:34.571715 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5920 RESULT=pass
31236 10:58:34.608505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5920 RESULT=skip>
31237 10:58:34.608894 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5920 RESULT=skip
31239 10:58:34.640753 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5920 RESULT=skip>
31240 10:58:34.641195 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5920 RESULT=skip
31242 10:58:34.675371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5936 RESULT=pass>
31243 10:58:34.675782 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5936 RESULT=pass
31245 10:58:34.711876 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5936 RESULT=skip
31247 10:58:34.712304 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5936 RESULT=skip>
31248 10:58:34.754863 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5936 RESULT=skip>
31249 10:58:34.755265 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5936 RESULT=skip
31251 10:58:34.795604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5952 RESULT=pass>
31252 10:58:34.796003 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5952 RESULT=pass
31254 10:58:34.838651 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5952 RESULT=skip>
31255 10:58:34.839072 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5952 RESULT=skip
31257 10:58:34.881475 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5952 RESULT=skip>
31258 10:58:34.881833 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5952 RESULT=skip
31260 10:58:34.924609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5968 RESULT=pass>
31261 10:58:34.924952 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5968 RESULT=pass
31263 10:58:34.962035 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5968 RESULT=skip>
31264 10:58:34.962453 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5968 RESULT=skip
31266 10:58:35.005220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5968 RESULT=skip>
31267 10:58:35.005629 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5968 RESULT=skip
31269 10:58:35.049546 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5984 RESULT=pass
31271 10:58:35.049994 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5984 RESULT=pass>
31272 10:58:35.093324 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5984 RESULT=skip
31274 10:58:35.093766 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5984 RESULT=skip>
31275 10:58:35.137199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5984 RESULT=skip>
31276 10:58:35.137599 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5984 RESULT=skip
31278 10:58:35.180689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6000 RESULT=pass>
31279 10:58:35.181072 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6000 RESULT=pass
31281 10:58:35.212971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6000 RESULT=skip>
31282 10:58:35.213375 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6000 RESULT=skip
31284 10:58:35.257303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6000 RESULT=skip>
31285 10:58:35.257685 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6000 RESULT=skip
31287 10:58:35.299316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6016 RESULT=pass>
31288 10:58:35.299746 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6016 RESULT=pass
31290 10:58:35.345344 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6016 RESULT=skip>
31291 10:58:35.346070 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6016 RESULT=skip
31293 10:58:35.389316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6016 RESULT=skip>
31294 10:58:35.389691 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6016 RESULT=skip
31296 10:58:35.432828 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6032 RESULT=pass>
31297 10:58:35.433268 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6032 RESULT=pass
31299 10:58:35.476324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6032 RESULT=skip>
31300 10:58:35.476758 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6032 RESULT=skip
31302 10:58:35.519419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6032 RESULT=skip>
31303 10:58:35.519843 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6032 RESULT=skip
31305 10:58:35.556656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6048 RESULT=pass>
31306 10:58:35.557104 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6048 RESULT=pass
31308 10:58:35.589084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6048 RESULT=skip>
31309 10:58:35.589502 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6048 RESULT=skip
31311 10:58:35.621471 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6048 RESULT=skip>
31312 10:58:35.621884 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6048 RESULT=skip
31314 10:58:35.659164 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6064 RESULT=pass
31316 10:58:35.659654 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6064 RESULT=pass>
31317 10:58:35.702547 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6064 RESULT=skip>
31318 10:58:35.702974 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6064 RESULT=skip
31320 10:58:35.745788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6064 RESULT=skip>
31321 10:58:35.746206 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6064 RESULT=skip
31323 10:58:35.789793 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6080 RESULT=pass>
31324 10:58:35.790224 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6080 RESULT=pass
31326 10:58:35.833157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6080 RESULT=skip>
31327 10:58:35.833586 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6080 RESULT=skip
31329 10:58:35.875624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6080 RESULT=skip>
31330 10:58:35.876065 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6080 RESULT=skip
31332 10:58:35.918537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6096 RESULT=pass>
31333 10:58:35.918968 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6096 RESULT=pass
31335 10:58:35.962092 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6096 RESULT=skip>
31336 10:58:35.962491 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6096 RESULT=skip
31338 10:58:35.998241 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6096 RESULT=skip>
31339 10:58:35.998652 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6096 RESULT=skip
31341 10:58:36.033346 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6112 RESULT=pass
31343 10:58:36.033755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6112 RESULT=pass>
31344 10:58:36.071532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6112 RESULT=skip>
31345 10:58:36.071949 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6112 RESULT=skip
31347 10:58:36.115534 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6112 RESULT=skip
31349 10:58:36.116005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6112 RESULT=skip>
31350 10:58:36.148706 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6128 RESULT=pass
31352 10:58:36.149464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6128 RESULT=pass>
31353 10:58:36.194407 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6128 RESULT=skip>
31354 10:58:36.194840 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6128 RESULT=skip
31356 10:58:36.231989 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6128 RESULT=skip
31358 10:58:36.232416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6128 RESULT=skip>
31359 10:58:36.274814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6144 RESULT=pass>
31360 10:58:36.275206 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6144 RESULT=pass
31362 10:58:36.318194 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6144 RESULT=skip
31364 10:58:36.318630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6144 RESULT=skip>
31365 10:58:36.366663 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6144 RESULT=skip
31367 10:58:36.367140 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6144 RESULT=skip>
31368 10:58:36.406330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6160 RESULT=pass>
31369 10:58:36.406714 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6160 RESULT=pass
31371 10:58:36.439141 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6160 RESULT=skip>
31372 10:58:36.439550 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6160 RESULT=skip
31374 10:58:36.482216 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6160 RESULT=skip
31376 10:58:36.482636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6160 RESULT=skip>
31377 10:58:36.513652 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6176 RESULT=pass>
31378 10:58:36.514093 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6176 RESULT=pass
31380 10:58:36.557959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6176 RESULT=skip>
31381 10:58:36.558376 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6176 RESULT=skip
31383 10:58:36.600926 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6176 RESULT=skip>
31384 10:58:36.601344 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6176 RESULT=skip
31386 10:58:36.644054 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6192 RESULT=pass
31388 10:58:36.644485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6192 RESULT=pass>
31389 10:58:36.687790 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6192 RESULT=skip
31391 10:58:36.688326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6192 RESULT=skip>
31392 10:58:36.731777 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6192 RESULT=skip
31394 10:58:36.732404 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6192 RESULT=skip>
31395 10:58:36.774636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6208 RESULT=pass>
31396 10:58:36.775054 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6208 RESULT=pass
31398 10:58:36.817714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6208 RESULT=skip>
31399 10:58:36.818110 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6208 RESULT=skip
31401 10:58:36.863843 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6208 RESULT=skip
31403 10:58:36.864289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6208 RESULT=skip>
31404 10:58:36.906605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6224 RESULT=pass>
31405 10:58:36.907004 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6224 RESULT=pass
31407 10:58:36.949991 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6224 RESULT=skip
31409 10:58:36.950420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6224 RESULT=skip>
31410 10:58:36.993056 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6224 RESULT=skip>
31411 10:58:36.993460 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6224 RESULT=skip
31413 10:58:37.034114 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6240 RESULT=pass
31415 10:58:37.034550 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6240 RESULT=pass>
31416 10:58:37.068222 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6240 RESULT=skip
31418 10:58:37.068775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6240 RESULT=skip>
31419 10:58:37.105284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6240 RESULT=skip>
31420 10:58:37.105702 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6240 RESULT=skip
31422 10:58:37.137251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6256 RESULT=pass>
31423 10:58:37.137677 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6256 RESULT=pass
31425 10:58:37.174898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6256 RESULT=skip>
31426 10:58:37.175313 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6256 RESULT=skip
31428 10:58:37.216450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6256 RESULT=skip>
31429 10:58:37.216847 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6256 RESULT=skip
31431 10:58:37.257324 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6272 RESULT=pass
31433 10:58:37.257749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6272 RESULT=pass>
31434 10:58:37.295383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6272 RESULT=skip>
31435 10:58:37.295784 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6272 RESULT=skip
31437 10:58:37.330019 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6272 RESULT=skip>
31438 10:58:37.330438 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6272 RESULT=skip
31440 10:58:37.362760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6288 RESULT=pass>
31441 10:58:37.363172 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6288 RESULT=pass
31443 10:58:37.395940 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6288 RESULT=skip
31445 10:58:37.396490 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6288 RESULT=skip>
31446 10:58:37.442273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6288 RESULT=skip>
31447 10:58:37.442622 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6288 RESULT=skip
31449 10:58:37.488543 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6304 RESULT=pass>
31450 10:58:37.488891 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6304 RESULT=pass
31452 10:58:37.535323 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6304 RESULT=skip
31454 10:58:37.535795 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6304 RESULT=skip>
31455 10:58:37.582288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6304 RESULT=skip>
31456 10:58:37.582703 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6304 RESULT=skip
31458 10:58:37.629198 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6320 RESULT=pass
31460 10:58:37.629683 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6320 RESULT=pass>
31461 10:58:37.676449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6320 RESULT=skip>
31462 10:58:37.676878 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6320 RESULT=skip
31464 10:58:37.723516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6320 RESULT=skip>
31465 10:58:37.723915 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6320 RESULT=skip
31467 10:58:37.769798 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6336 RESULT=pass
31469 10:58:37.770197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6336 RESULT=pass>
31470 10:58:37.816631 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6336 RESULT=skip>
31471 10:58:37.817038 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6336 RESULT=skip
31473 10:58:37.863074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6336 RESULT=skip>
31474 10:58:37.863477 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6336 RESULT=skip
31476 10:58:37.910400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6352 RESULT=pass>
31477 10:58:37.910825 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6352 RESULT=pass
31479 10:58:37.957268 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6352 RESULT=skip
31481 10:58:37.957704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6352 RESULT=skip>
31482 10:58:38.004433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6352 RESULT=skip>
31483 10:58:38.004870 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6352 RESULT=skip
31485 10:58:38.050748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6368 RESULT=pass>
31486 10:58:38.051161 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6368 RESULT=pass
31488 10:58:38.097447 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6368 RESULT=skip>
31489 10:58:38.097871 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6368 RESULT=skip
31491 10:58:38.143516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6368 RESULT=skip>
31492 10:58:38.143941 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6368 RESULT=skip
31494 10:58:38.189833 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6384 RESULT=pass
31496 10:58:38.190291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6384 RESULT=pass>
31497 10:58:38.235909 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6384 RESULT=skip
31499 10:58:38.236356 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6384 RESULT=skip>
31500 10:58:38.288818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6384 RESULT=skip>
31501 10:58:38.289247 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6384 RESULT=skip
31503 10:58:38.338968 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6400 RESULT=pass
31505 10:58:38.339423 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6400 RESULT=pass>
31506 10:58:38.386420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6400 RESULT=skip>
31507 10:58:38.386843 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6400 RESULT=skip
31509 10:58:38.438051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6400 RESULT=skip>
31510 10:58:38.438507 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6400 RESULT=skip
31512 10:58:38.486634 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6416 RESULT=pass
31514 10:58:38.487079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6416 RESULT=pass>
31515 10:58:38.538144 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6416 RESULT=skip>
31516 10:58:38.538538 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6416 RESULT=skip
31518 10:58:38.591168 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6416 RESULT=skip
31520 10:58:38.591643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6416 RESULT=skip>
31521 10:58:38.649714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6432 RESULT=pass>
31522 10:58:38.650136 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6432 RESULT=pass
31524 10:58:38.707516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6432 RESULT=skip>
31525 10:58:38.707929 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6432 RESULT=skip
31527 10:58:38.757421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6432 RESULT=skip>
31528 10:58:38.757864 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6432 RESULT=skip
31530 10:58:38.805070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6448 RESULT=pass>
31531 10:58:38.805488 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6448 RESULT=pass
31533 10:58:38.852950 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6448 RESULT=skip>
31534 10:58:38.853371 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6448 RESULT=skip
31536 10:58:38.899397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6448 RESULT=skip>
31537 10:58:38.899806 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6448 RESULT=skip
31539 10:58:38.949837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6464 RESULT=pass>
31540 10:58:38.950222 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6464 RESULT=pass
31542 10:58:39.001915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6464 RESULT=skip>
31543 10:58:39.002354 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6464 RESULT=skip
31545 10:58:39.052252 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6464 RESULT=skip
31547 10:58:39.052781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6464 RESULT=skip>
31548 10:58:39.100357 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6480 RESULT=pass
31550 10:58:39.100743 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6480 RESULT=pass>
31551 10:58:39.146883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6480 RESULT=skip>
31552 10:58:39.147298 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6480 RESULT=skip
31554 10:58:39.196372 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6480 RESULT=skip>
31555 10:58:39.196804 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6480 RESULT=skip
31557 10:58:39.247091 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6496 RESULT=pass>
31558 10:58:39.248276 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6496 RESULT=pass
31560 10:58:39.305444 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6496 RESULT=skip
31562 10:58:39.306488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6496 RESULT=skip>
31563 10:58:39.359015 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6496 RESULT=skip>
31564 10:58:39.359442 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6496 RESULT=skip
31566 10:58:39.405548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6512 RESULT=pass>
31567 10:58:39.405955 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6512 RESULT=pass
31569 10:58:39.452441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6512 RESULT=skip>
31570 10:58:39.452836 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6512 RESULT=skip
31572 10:58:39.498935 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6512 RESULT=skip>
31573 10:58:39.499442 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6512 RESULT=skip
31575 10:58:39.545043 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6528 RESULT=pass
31577 10:58:39.545586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6528 RESULT=pass>
31578 10:58:39.590026 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6528 RESULT=skip>
31579 10:58:39.590457 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6528 RESULT=skip
31581 10:58:39.636719 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6528 RESULT=skip
31583 10:58:39.637169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6528 RESULT=skip>
31584 10:58:39.681404 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6544 RESULT=pass
31586 10:58:39.681835 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6544 RESULT=pass>
31587 10:58:39.726581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6544 RESULT=skip>
31588 10:58:39.727002 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6544 RESULT=skip
31590 10:58:39.774667 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6544 RESULT=skip>
31591 10:58:39.775064 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6544 RESULT=skip
31593 10:58:39.822811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6560 RESULT=pass>
31594 10:58:39.823227 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6560 RESULT=pass
31596 10:58:39.869799 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6560 RESULT=skip>
31597 10:58:39.870224 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6560 RESULT=skip
31599 10:58:39.918344 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6560 RESULT=skip>
31600 10:58:39.918770 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6560 RESULT=skip
31602 10:58:39.964874 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6576 RESULT=pass
31604 10:58:39.965318 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6576 RESULT=pass>
31605 10:58:40.010908 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6576 RESULT=skip
31607 10:58:40.011344 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6576 RESULT=skip>
31608 10:58:40.057671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6576 RESULT=skip>
31609 10:58:40.058098 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6576 RESULT=skip
31611 10:58:40.106551 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6592 RESULT=pass
31613 10:58:40.106997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6592 RESULT=pass>
31614 10:58:40.154787 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6592 RESULT=skip>
31615 10:58:40.155230 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6592 RESULT=skip
31617 10:58:40.201682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6592 RESULT=skip>
31618 10:58:40.202124 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6592 RESULT=skip
31620 10:58:40.247417 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6608 RESULT=pass>
31621 10:58:40.247829 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6608 RESULT=pass
31623 10:58:40.293938 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6608 RESULT=skip>
31624 10:58:40.294340 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6608 RESULT=skip
31626 10:58:40.340905 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6608 RESULT=skip>
31627 10:58:40.341325 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6608 RESULT=skip
31629 10:58:40.386961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6624 RESULT=pass>
31630 10:58:40.387376 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6624 RESULT=pass
31632 10:58:40.433844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6624 RESULT=skip>
31633 10:58:40.434246 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6624 RESULT=skip
31635 10:58:40.481576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6624 RESULT=skip>
31636 10:58:40.481911 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6624 RESULT=skip
31638 10:58:40.527551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6640 RESULT=pass>
31639 10:58:40.527929 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6640 RESULT=pass
31641 10:58:40.573600 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6640 RESULT=skip
31643 10:58:40.574048 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6640 RESULT=skip>
31644 10:58:40.619486 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6640 RESULT=skip
31646 10:58:40.619897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6640 RESULT=skip>
31647 10:58:40.665408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6656 RESULT=pass>
31648 10:58:40.665821 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6656 RESULT=pass
31650 10:58:40.711111 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6656 RESULT=skip
31652 10:58:40.711521 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6656 RESULT=skip>
31653 10:58:40.758396 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6656 RESULT=skip
31655 10:58:40.758835 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6656 RESULT=skip>
31656 10:58:40.804879 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6672 RESULT=pass
31658 10:58:40.805306 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6672 RESULT=pass>
31659 10:58:40.852480 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6672 RESULT=skip>
31660 10:58:40.852892 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6672 RESULT=skip
31662 10:58:40.897953 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6672 RESULT=skip>
31663 10:58:40.898363 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6672 RESULT=skip
31665 10:58:40.940000 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6688 RESULT=pass
31667 10:58:40.940428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6688 RESULT=pass>
31668 10:58:40.973567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6688 RESULT=skip>
31669 10:58:40.973979 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6688 RESULT=skip
31671 10:58:41.017883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6688 RESULT=skip>
31672 10:58:41.018272 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6688 RESULT=skip
31674 10:58:41.063054 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6704 RESULT=pass
31676 10:58:41.063489 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6704 RESULT=pass>
31677 10:58:41.104284 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6704 RESULT=skip
31679 10:58:41.104670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6704 RESULT=skip>
31680 10:58:41.146287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6704 RESULT=skip>
31681 10:58:41.146673 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6704 RESULT=skip
31683 10:58:41.190931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6720 RESULT=pass>
31684 10:58:41.191306 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6720 RESULT=pass
31686 10:58:41.234079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6720 RESULT=skip>
31687 10:58:41.234476 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6720 RESULT=skip
31689 10:58:41.276970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6720 RESULT=skip>
31690 10:58:41.277366 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6720 RESULT=skip
31692 10:58:41.320763 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6736 RESULT=pass>
31693 10:58:41.321153 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6736 RESULT=pass
31695 10:58:41.364535 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6736 RESULT=skip>
31696 10:58:41.364972 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6736 RESULT=skip
31698 10:58:41.409225 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6736 RESULT=skip>
31699 10:58:41.409690 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6736 RESULT=skip
31701 10:58:41.452962 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6752 RESULT=pass
31703 10:58:41.453390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6752 RESULT=pass>
31704 10:58:41.497281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6752 RESULT=skip>
31705 10:58:41.497697 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6752 RESULT=skip
31707 10:58:41.541890 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6752 RESULT=skip>
31708 10:58:41.542337 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6752 RESULT=skip
31710 10:58:41.584995 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6768 RESULT=pass
31712 10:58:41.585437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6768 RESULT=pass>
31713 10:58:41.628587 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6768 RESULT=skip>
31714 10:58:41.629016 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6768 RESULT=skip
31716 10:58:41.671326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6768 RESULT=skip>
31717 10:58:41.671742 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6768 RESULT=skip
31719 10:58:41.715118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6784 RESULT=pass>
31720 10:58:41.715568 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6784 RESULT=pass
31722 10:58:41.758716 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6784 RESULT=skip
31724 10:58:41.759159 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6784 RESULT=skip>
31725 10:58:41.801880 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6784 RESULT=skip>
31726 10:58:41.802291 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6784 RESULT=skip
31728 10:58:41.845145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6800 RESULT=pass>
31729 10:58:41.845542 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6800 RESULT=pass
31731 10:58:41.889456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6800 RESULT=skip>
31732 10:58:41.889867 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6800 RESULT=skip
31734 10:58:41.930745 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6800 RESULT=skip>
31735 10:58:41.931151 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6800 RESULT=skip
31737 10:58:41.974373 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6816 RESULT=pass>
31738 10:58:41.974777 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6816 RESULT=pass
31740 10:58:42.018651 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6816 RESULT=skip>
31741 10:58:42.019052 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6816 RESULT=skip
31743 10:58:42.062251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6816 RESULT=skip>
31744 10:58:42.062668 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6816 RESULT=skip
31746 10:58:42.106504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6832 RESULT=pass>
31747 10:58:42.106908 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6832 RESULT=pass
31749 10:58:42.153082 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6832 RESULT=skip>
31750 10:58:42.153438 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6832 RESULT=skip
31752 10:58:42.196579 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6832 RESULT=skip>
31753 10:58:42.196999 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6832 RESULT=skip
31755 10:58:42.240655 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6848 RESULT=pass>
31756 10:58:42.241067 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6848 RESULT=pass
31758 10:58:42.282951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6848 RESULT=skip>
31759 10:58:42.283337 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6848 RESULT=skip
31761 10:58:42.326433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6848 RESULT=skip>
31762 10:58:42.326832 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6848 RESULT=skip
31764 10:58:42.372560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6864 RESULT=pass>
31765 10:58:42.372955 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6864 RESULT=pass
31767 10:58:42.418371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6864 RESULT=skip>
31768 10:58:42.418789 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6864 RESULT=skip
31770 10:58:42.462311 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6864 RESULT=skip>
31771 10:58:42.462720 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6864 RESULT=skip
31773 10:58:42.501874 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6880 RESULT=pass>
31774 10:58:42.502290 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6880 RESULT=pass
31776 10:58:42.553563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6880 RESULT=skip>
31777 10:58:42.554001 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6880 RESULT=skip
31779 10:58:42.596815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6880 RESULT=skip>
31780 10:58:42.597233 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6880 RESULT=skip
31782 10:58:42.632973 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6896 RESULT=pass>
31783 10:58:42.633363 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6896 RESULT=pass
31785 10:58:42.664697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6896 RESULT=skip>
31786 10:58:42.665097 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6896 RESULT=skip
31788 10:58:42.697622 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6896 RESULT=skip>
31789 10:58:42.698038 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6896 RESULT=skip
31791 10:58:42.740565 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6912 RESULT=pass>
31792 10:58:42.740970 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6912 RESULT=pass
31794 10:58:42.778383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6912 RESULT=skip>
31795 10:58:42.778789 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6912 RESULT=skip
31797 10:58:42.809832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6912 RESULT=skip>
31798 10:58:42.810266 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6912 RESULT=skip
31800 10:58:42.843413 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6928 RESULT=pass
31802 10:58:42.843892 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6928 RESULT=pass>
31803 10:58:42.889354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6928 RESULT=skip>
31804 10:58:42.889766 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6928 RESULT=skip
31806 10:58:42.924247 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6928 RESULT=skip>
31807 10:58:42.924657 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6928 RESULT=skip
31809 10:58:42.968783 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6944 RESULT=pass>
31810 10:58:42.969181 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6944 RESULT=pass
31812 10:58:43.013330 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6944 RESULT=skip
31814 10:58:43.013768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6944 RESULT=skip>
31815 10:58:43.057012 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6944 RESULT=skip
31817 10:58:43.057471 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6944 RESULT=skip>
31818 10:58:43.101339 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6960 RESULT=pass
31820 10:58:43.101796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6960 RESULT=pass>
31821 10:58:43.146658 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6960 RESULT=skip>
31822 10:58:43.147071 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6960 RESULT=skip
31824 10:58:43.191262 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6960 RESULT=skip>
31825 10:58:43.191685 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6960 RESULT=skip
31827 10:58:43.240006 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6976 RESULT=pass
31829 10:58:43.240465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6976 RESULT=pass>
31830 10:58:43.284939 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6976 RESULT=skip>
31831 10:58:43.285356 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6976 RESULT=skip
31833 10:58:43.328457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6976 RESULT=skip>
31834 10:58:43.328891 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6976 RESULT=skip
31836 10:58:43.372529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6992 RESULT=pass>
31837 10:58:43.372970 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6992 RESULT=pass
31839 10:58:43.415419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6992 RESULT=skip>
31840 10:58:43.415839 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6992 RESULT=skip
31842 10:58:43.459666 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6992 RESULT=skip>
31843 10:58:43.460096 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6992 RESULT=skip
31845 10:58:43.504820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7008 RESULT=pass>
31846 10:58:43.505257 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7008 RESULT=pass
31848 10:58:43.548661 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7008 RESULT=skip>
31849 10:58:43.549079 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7008 RESULT=skip
31851 10:58:43.592731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7008 RESULT=skip>
31852 10:58:43.593112 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7008 RESULT=skip
31854 10:58:43.628805 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7024 RESULT=pass>
31855 10:58:43.629238 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7024 RESULT=pass
31857 10:58:43.662772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7024 RESULT=skip>
31858 10:58:43.663188 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7024 RESULT=skip
31860 10:58:43.709064 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7024 RESULT=skip>
31861 10:58:43.709466 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7024 RESULT=skip
31863 10:58:43.753206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7040 RESULT=pass>
31864 10:58:43.753600 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7040 RESULT=pass
31866 10:58:43.820293 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7040 RESULT=skip>
31867 10:58:43.820704 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7040 RESULT=skip
31869 10:58:43.867242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7040 RESULT=skip>
31870 10:58:43.867643 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7040 RESULT=skip
31872 10:58:43.913449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7056 RESULT=pass>
31873 10:58:43.913869 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7056 RESULT=pass
31875 10:58:43.962922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7056 RESULT=skip>
31876 10:58:43.963357 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7056 RESULT=skip
31878 10:58:44.013376 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7056 RESULT=skip>
31879 10:58:44.013775 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7056 RESULT=skip
31881 10:58:44.061566 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7072 RESULT=pass>
31882 10:58:44.061965 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7072 RESULT=pass
31884 10:58:44.107254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7072 RESULT=skip>
31885 10:58:44.107662 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7072 RESULT=skip
31887 10:58:44.154815 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7072 RESULT=skip
31889 10:58:44.155255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7072 RESULT=skip>
31890 10:58:44.204503 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7088 RESULT=pass>
31891 10:58:44.204925 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7088 RESULT=pass
31893 10:58:44.257475 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7088 RESULT=skip
31895 10:58:44.257970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7088 RESULT=skip>
31896 10:58:44.307168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7088 RESULT=skip>
31897 10:58:44.307604 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7088 RESULT=skip
31899 10:58:44.354743 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7104 RESULT=pass>
31900 10:58:44.355175 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7104 RESULT=pass
31902 10:58:44.402065 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7104 RESULT=skip>
31903 10:58:44.402517 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7104 RESULT=skip
31905 10:58:44.449039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7104 RESULT=skip>
31906 10:58:44.449457 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7104 RESULT=skip
31908 10:58:44.494696 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7120 RESULT=pass>
31909 10:58:44.495121 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7120 RESULT=pass
31911 10:58:44.542865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7120 RESULT=skip>
31912 10:58:44.543252 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7120 RESULT=skip
31914 10:58:44.589653 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7120 RESULT=skip>
31915 10:58:44.590099 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7120 RESULT=skip
31917 10:58:44.636383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7136 RESULT=pass>
31918 10:58:44.636814 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7136 RESULT=pass
31920 10:58:44.682271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7136 RESULT=skip>
31921 10:58:44.682692 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7136 RESULT=skip
31923 10:58:44.729593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7136 RESULT=skip>
31924 10:58:44.730024 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7136 RESULT=skip
31926 10:58:44.773721 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7152 RESULT=pass>
31927 10:58:44.774149 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7152 RESULT=pass
31929 10:58:44.813043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7152 RESULT=skip>
31930 10:58:44.813449 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7152 RESULT=skip
31932 10:58:44.845223 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7152 RESULT=skip
31934 10:58:44.845660 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7152 RESULT=skip>
31935 10:58:44.887946 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7168 RESULT=pass
31937 10:58:44.888388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7168 RESULT=pass>
31938 10:58:44.919824 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7168 RESULT=skip
31940 10:58:44.920271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7168 RESULT=skip>
31941 10:58:44.956511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7168 RESULT=skip>
31942 10:58:44.956934 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7168 RESULT=skip
31944 10:58:44.999465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7184 RESULT=pass>
31945 10:58:44.999898 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7184 RESULT=pass
31947 10:58:45.040900 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7184 RESULT=skip>
31948 10:58:45.041334 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7184 RESULT=skip
31950 10:58:45.085175 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7184 RESULT=skip
31952 10:58:45.085626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7184 RESULT=skip>
31953 10:58:45.130487 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7200 RESULT=pass
31955 10:58:45.130947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7200 RESULT=pass>
31956 10:58:45.167475 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7200 RESULT=skip>
31957 10:58:45.167910 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7200 RESULT=skip
31959 10:58:45.200728 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7200 RESULT=skip
31961 10:58:45.201172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7200 RESULT=skip>
31962 10:58:45.244674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7216 RESULT=pass>
31963 10:58:45.245098 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7216 RESULT=pass
31965 10:58:45.287897 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7216 RESULT=skip
31967 10:58:45.288385 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7216 RESULT=skip>
31968 10:58:45.331961 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7216 RESULT=skip
31970 10:58:45.332402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7216 RESULT=skip>
31971 10:58:45.366552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7232 RESULT=pass>
31972 10:58:45.366970 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7232 RESULT=pass
31974 10:58:45.410684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7232 RESULT=skip>
31975 10:58:45.411078 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7232 RESULT=skip
31977 10:58:45.447622 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7232 RESULT=skip
31979 10:58:45.448051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7232 RESULT=skip>
31980 10:58:45.490642 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7248 RESULT=pass>
31981 10:58:45.491417 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7248 RESULT=pass
31983 10:58:45.533678 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7248 RESULT=skip>
31984 10:58:45.534094 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7248 RESULT=skip
31986 10:58:45.566027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7248 RESULT=skip>
31987 10:58:45.566447 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7248 RESULT=skip
31989 10:58:45.608832 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7264 RESULT=pass
31991 10:58:45.609323 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7264 RESULT=pass>
31992 10:58:45.646495 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7264 RESULT=skip
31994 10:58:45.646962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7264 RESULT=skip>
31995 10:58:45.690864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7264 RESULT=skip>
31996 10:58:45.691280 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7264 RESULT=skip
31998 10:58:45.731838 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7280 RESULT=pass
32000 10:58:45.732287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7280 RESULT=pass>
32001 10:58:45.763998 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7280 RESULT=skip
32003 10:58:45.764578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7280 RESULT=skip>
32004 10:58:45.807964 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7280 RESULT=skip
32006 10:58:45.808388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7280 RESULT=skip>
32007 10:58:45.851004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7296 RESULT=pass>
32008 10:58:45.851455 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7296 RESULT=pass
32010 10:58:45.894639 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7296 RESULT=skip>
32011 10:58:45.895046 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7296 RESULT=skip
32013 10:58:45.937992 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7296 RESULT=skip
32015 10:58:45.938431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7296 RESULT=skip>
32016 10:58:45.980739 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7312 RESULT=pass
32018 10:58:45.981160 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7312 RESULT=pass>
32019 10:58:46.025359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7312 RESULT=skip>
32020 10:58:46.025767 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7312 RESULT=skip
32022 10:58:46.069534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7312 RESULT=skip>
32023 10:58:46.069971 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7312 RESULT=skip
32025 10:58:46.111867 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7328 RESULT=pass
32027 10:58:46.112333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7328 RESULT=pass>
32028 10:58:46.155242 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7328 RESULT=skip
32030 10:58:46.155696 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7328 RESULT=skip>
32031 10:58:46.199050 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7328 RESULT=skip
32033 10:58:46.199483 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7328 RESULT=skip>
32034 10:58:46.242819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7344 RESULT=pass>
32035 10:58:46.243225 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7344 RESULT=pass
32037 10:58:46.287338 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7344 RESULT=skip
32039 10:58:46.287777 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7344 RESULT=skip>
32040 10:58:46.334960 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7344 RESULT=skip>
32041 10:58:46.335371 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7344 RESULT=skip
32043 10:58:46.367612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7360 RESULT=pass>
32044 10:58:46.368039 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7360 RESULT=pass
32046 10:58:46.411144 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7360 RESULT=skip>
32047 10:58:46.411545 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7360 RESULT=skip
32049 10:58:46.451489 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7360 RESULT=skip>
32050 10:58:46.451917 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7360 RESULT=skip
32052 10:58:46.485430 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7376 RESULT=pass>
32053 10:58:46.485844 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7376 RESULT=pass
32055 10:58:46.530147 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7376 RESULT=skip
32057 10:58:46.530581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7376 RESULT=skip>
32058 10:58:46.575514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7376 RESULT=skip>
32059 10:58:46.575905 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7376 RESULT=skip
32061 10:58:46.613331 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7392 RESULT=pass>
32062 10:58:46.613756 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7392 RESULT=pass
32064 10:58:46.656845 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7392 RESULT=skip
32066 10:58:46.657284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7392 RESULT=skip>
32067 10:58:46.700929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7392 RESULT=skip>
32068 10:58:46.701338 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7392 RESULT=skip
32070 10:58:46.744632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7408 RESULT=pass>
32071 10:58:46.745037 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7408 RESULT=pass
32073 10:58:46.786097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7408 RESULT=skip>
32074 10:58:46.786489 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7408 RESULT=skip
32076 10:58:46.829637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7408 RESULT=skip>
32077 10:58:46.830031 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7408 RESULT=skip
32079 10:58:46.872889 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7424 RESULT=pass
32081 10:58:46.873315 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7424 RESULT=pass>
32082 10:58:46.915238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7424 RESULT=skip>
32083 10:58:46.915641 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7424 RESULT=skip
32085 10:58:46.958870 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7424 RESULT=skip>
32086 10:58:46.959303 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7424 RESULT=skip
32088 10:58:46.999277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7440 RESULT=pass>
32089 10:58:46.999684 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7440 RESULT=pass
32091 10:58:47.040604 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7440 RESULT=skip
32093 10:58:47.041056 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7440 RESULT=skip>
32094 10:58:47.081345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7440 RESULT=skip>
32095 10:58:47.081759 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7440 RESULT=skip
32097 10:58:47.121856 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7456 RESULT=pass
32099 10:58:47.122304 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7456 RESULT=pass>
32100 10:58:47.166269 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7456 RESULT=skip
32102 10:58:47.166715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7456 RESULT=skip>
32103 10:58:47.210973 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7456 RESULT=skip>
32104 10:58:47.211389 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7456 RESULT=skip
32106 10:58:47.254450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7472 RESULT=pass>
32107 10:58:47.254861 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7472 RESULT=pass
32109 10:58:47.297726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7472 RESULT=skip>
32110 10:58:47.298141 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7472 RESULT=skip
32112 10:58:47.341992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7472 RESULT=skip>
32113 10:58:47.342409 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7472 RESULT=skip
32115 10:58:47.386382 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7488 RESULT=pass
32117 10:58:47.386813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7488 RESULT=pass>
32118 10:58:47.430744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7488 RESULT=skip>
32119 10:58:47.431143 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7488 RESULT=skip
32121 10:58:47.477662 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7488 RESULT=skip
32123 10:58:47.478132 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7488 RESULT=skip>
32124 10:58:47.521083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7504 RESULT=pass>
32125 10:58:47.521486 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7504 RESULT=pass
32127 10:58:47.565114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7504 RESULT=skip>
32128 10:58:47.565493 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7504 RESULT=skip
32130 10:58:47.604864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7504 RESULT=skip>
32131 10:58:47.605272 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7504 RESULT=skip
32133 10:58:47.649920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7520 RESULT=pass>
32134 10:58:47.650298 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7520 RESULT=pass
32136 10:58:47.692702 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7520 RESULT=skip>
32137 10:58:47.693126 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7520 RESULT=skip
32139 10:58:47.735184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7520 RESULT=skip>
32140 10:58:47.735609 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7520 RESULT=skip
32142 10:58:47.778204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7536 RESULT=pass>
32143 10:58:47.778645 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7536 RESULT=pass
32145 10:58:47.822270 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7536 RESULT=skip
32147 10:58:47.822722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7536 RESULT=skip>
32148 10:58:47.866266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7536 RESULT=skip>
32149 10:58:47.866702 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7536 RESULT=skip
32151 10:58:47.910210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7552 RESULT=pass>
32152 10:58:47.910638 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7552 RESULT=pass
32154 10:58:47.956364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7552 RESULT=skip>
32155 10:58:47.956782 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7552 RESULT=skip
32157 10:58:47.998093 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7552 RESULT=skip>
32158 10:58:47.998480 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7552 RESULT=skip
32160 10:58:48.042103 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7568 RESULT=pass
32162 10:58:48.042586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7568 RESULT=pass>
32163 10:58:48.086616 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7568 RESULT=skip
32165 10:58:48.087076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7568 RESULT=skip>
32166 10:58:48.133738 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7568 RESULT=skip>
32167 10:58:48.137593 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7568 RESULT=skip
32169 10:58:48.177617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7584 RESULT=pass>
32170 10:58:48.178083 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7584 RESULT=pass
32172 10:58:48.218892 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7584 RESULT=skip>
32173 10:58:48.219341 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7584 RESULT=skip
32175 10:58:48.263312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7584 RESULT=skip>
32176 10:58:48.263751 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7584 RESULT=skip
32178 10:58:48.308601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7600 RESULT=pass>
32179 10:58:48.309030 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7600 RESULT=pass
32181 10:58:48.351641 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7600 RESULT=skip
32183 10:58:48.352093 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7600 RESULT=skip>
32184 10:58:48.395250 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7600 RESULT=skip
32186 10:58:48.395718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7600 RESULT=skip>
32187 10:58:48.439447 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7616 RESULT=pass
32189 10:58:48.439884 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7616 RESULT=pass>
32190 10:58:48.479271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7616 RESULT=skip>
32191 10:58:48.479691 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7616 RESULT=skip
32193 10:58:48.522959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7616 RESULT=skip>
32194 10:58:48.523349 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7616 RESULT=skip
32196 10:58:48.566909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7632 RESULT=pass>
32197 10:58:48.567261 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7632 RESULT=pass
32199 10:58:48.611337 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7632 RESULT=skip>
32200 10:58:48.611779 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7632 RESULT=skip
32202 10:58:48.653302 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7632 RESULT=skip
32204 10:58:48.653775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7632 RESULT=skip>
32205 10:58:48.696612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7648 RESULT=pass>
32206 10:58:48.697060 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7648 RESULT=pass
32208 10:58:48.740958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7648 RESULT=skip>
32209 10:58:48.741385 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7648 RESULT=skip
32211 10:58:48.785586 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7648 RESULT=skip
32213 10:58:48.786051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7648 RESULT=skip>
32214 10:58:48.829210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7664 RESULT=pass>
32215 10:58:48.829660 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7664 RESULT=pass
32217 10:58:48.872482 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7664 RESULT=skip>
32218 10:58:48.872886 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7664 RESULT=skip
32220 10:58:48.938282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7664 RESULT=skip>
32221 10:58:48.938698 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7664 RESULT=skip
32223 10:58:48.982702 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7680 RESULT=pass>
32224 10:58:48.983132 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7680 RESULT=pass
32226 10:58:49.027681 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7680 RESULT=skip
32228 10:58:49.028168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7680 RESULT=skip>
32229 10:58:49.076367 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7680 RESULT=skip>
32230 10:58:49.076792 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7680 RESULT=skip
32232 10:58:49.121292 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7696 RESULT=pass
32234 10:58:49.121753 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7696 RESULT=pass>
32235 10:58:49.165003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7696 RESULT=skip>
32236 10:58:49.165428 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7696 RESULT=skip
32238 10:58:49.208624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7696 RESULT=skip>
32239 10:58:49.209040 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7696 RESULT=skip
32241 10:58:49.253224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7712 RESULT=pass>
32242 10:58:49.253670 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7712 RESULT=pass
32244 10:58:49.299296 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7712 RESULT=skip>
32245 10:58:49.299728 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7712 RESULT=skip
32247 10:58:49.345269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7712 RESULT=skip>
32248 10:58:49.345687 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7712 RESULT=skip
32250 10:58:49.389268 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7728 RESULT=pass>
32251 10:58:49.389679 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7728 RESULT=pass
32253 10:58:49.433130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7728 RESULT=skip>
32254 10:58:49.433576 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7728 RESULT=skip
32256 10:58:49.475591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7728 RESULT=skip>
32257 10:58:49.476018 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7728 RESULT=skip
32259 10:58:49.520281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7744 RESULT=pass>
32260 10:58:49.520733 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7744 RESULT=pass
32262 10:58:49.563900 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7744 RESULT=skip
32264 10:58:49.564307 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7744 RESULT=skip>
32265 10:58:49.607105 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7744 RESULT=skip
32267 10:58:49.607569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7744 RESULT=skip>
32268 10:58:49.650683 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7760 RESULT=pass>
32269 10:58:49.651119 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7760 RESULT=pass
32271 10:58:49.694891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7760 RESULT=skip>
32272 10:58:49.695257 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7760 RESULT=skip
32274 10:58:49.741325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7760 RESULT=skip>
32275 10:58:49.741772 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7760 RESULT=skip
32277 10:58:49.786888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7776 RESULT=pass>
32278 10:58:49.787308 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7776 RESULT=pass
32280 10:58:49.832718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7776 RESULT=skip>
32281 10:58:49.833105 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7776 RESULT=skip
32283 10:58:49.879261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7776 RESULT=skip>
32284 10:58:49.879663 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7776 RESULT=skip
32286 10:58:49.925900 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7792 RESULT=pass
32288 10:58:49.926386 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7792 RESULT=pass>
32289 10:58:49.973225 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7792 RESULT=skip>
32290 10:58:49.973610 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7792 RESULT=skip
32292 10:58:50.018798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7792 RESULT=skip>
32293 10:58:50.019218 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7792 RESULT=skip
32295 10:58:50.064853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7808 RESULT=pass>
32296 10:58:50.065228 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7808 RESULT=pass
32298 10:58:50.110074 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7808 RESULT=skip
32300 10:58:50.110524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7808 RESULT=skip>
32301 10:58:50.155759 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7808 RESULT=skip
32303 10:58:50.156329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7808 RESULT=skip>
32304 10:58:50.201853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7824 RESULT=pass>
32305 10:58:50.202302 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7824 RESULT=pass
32307 10:58:50.248441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7824 RESULT=skip>
32308 10:58:50.248811 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7824 RESULT=skip
32310 10:58:50.294169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7824 RESULT=skip>
32311 10:58:50.294553 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7824 RESULT=skip
32313 10:58:50.339486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7840 RESULT=pass>
32314 10:58:50.339906 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7840 RESULT=pass
32316 10:58:50.385565 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7840 RESULT=skip>
32317 10:58:50.386011 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7840 RESULT=skip
32319 10:58:50.430883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7840 RESULT=skip>
32320 10:58:50.431306 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7840 RESULT=skip
32322 10:58:50.477262 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7856 RESULT=pass
32324 10:58:50.477742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7856 RESULT=pass>
32325 10:58:50.523922 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7856 RESULT=skip
32327 10:58:50.524333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7856 RESULT=skip>
32328 10:58:50.570145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7856 RESULT=skip>
32329 10:58:50.570542 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7856 RESULT=skip
32331 10:58:50.616680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7872 RESULT=pass>
32332 10:58:50.617101 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7872 RESULT=pass
32334 10:58:50.663066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7872 RESULT=skip>
32335 10:58:50.663492 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7872 RESULT=skip
32337 10:58:50.709256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7872 RESULT=skip>
32338 10:58:50.709691 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7872 RESULT=skip
32340 10:58:50.757188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7888 RESULT=pass>
32341 10:58:50.757616 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7888 RESULT=pass
32343 10:58:50.803285 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7888 RESULT=skip>
32344 10:58:50.803711 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7888 RESULT=skip
32346 10:58:50.849462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7888 RESULT=skip>
32347 10:58:50.849879 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7888 RESULT=skip
32349 10:58:50.894754 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7904 RESULT=pass>
32350 10:58:50.895185 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7904 RESULT=pass
32352 10:58:50.941895 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7904 RESULT=skip>
32353 10:58:50.942323 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7904 RESULT=skip
32355 10:58:50.988951 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7904 RESULT=skip
32357 10:58:50.989415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7904 RESULT=skip>
32358 10:58:51.034212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7920 RESULT=pass>
32359 10:58:51.034634 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7920 RESULT=pass
32361 10:58:51.081017 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7920 RESULT=skip>
32362 10:58:51.081416 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7920 RESULT=skip
32364 10:58:51.126718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7920 RESULT=skip>
32365 10:58:51.127157 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7920 RESULT=skip
32367 10:58:51.172835 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7936 RESULT=pass>
32368 10:58:51.173293 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7936 RESULT=pass
32370 10:58:51.218874 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7936 RESULT=skip
32372 10:58:51.219353 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7936 RESULT=skip>
32373 10:58:51.265504 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7936 RESULT=skip
32375 10:58:51.265990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7936 RESULT=skip>
32376 10:58:51.311284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7952 RESULT=pass>
32377 10:58:51.311713 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7952 RESULT=pass
32379 10:58:51.362323 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7952 RESULT=skip>
32380 10:58:51.362746 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7952 RESULT=skip
32382 10:58:51.409159 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7952 RESULT=skip>
32383 10:58:51.409601 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7952 RESULT=skip
32385 10:58:51.456437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7968 RESULT=pass>
32386 10:58:51.456814 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7968 RESULT=pass
32388 10:58:51.503151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7968 RESULT=skip>
32389 10:58:51.503517 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7968 RESULT=skip
32391 10:58:51.549866 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7968 RESULT=skip
32393 10:58:51.550289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7968 RESULT=skip>
32394 10:58:51.597587 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7984 RESULT=pass>
32395 10:58:51.598019 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7984 RESULT=pass
32397 10:58:51.644568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7984 RESULT=skip>
32398 10:58:51.645004 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7984 RESULT=skip
32400 10:58:51.690886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7984 RESULT=skip>
32401 10:58:51.691383 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7984 RESULT=skip
32403 10:58:51.737061 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8000 RESULT=pass
32405 10:58:51.737509 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8000 RESULT=pass>
32406 10:58:51.782223 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8000 RESULT=skip
32408 10:58:51.782601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8000 RESULT=skip>
32409 10:58:51.828809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8000 RESULT=skip>
32410 10:58:51.829225 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8000 RESULT=skip
32412 10:58:51.873626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8016 RESULT=pass>
32413 10:58:51.874100 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8016 RESULT=pass
32415 10:58:51.918796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8016 RESULT=skip>
32416 10:58:51.919245 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8016 RESULT=skip
32418 10:58:51.965134 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8016 RESULT=skip
32420 10:58:51.965591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8016 RESULT=skip>
32421 10:58:52.013617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8032 RESULT=pass>
32422 10:58:52.014059 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8032 RESULT=pass
32424 10:58:52.060974 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8032 RESULT=skip>
32425 10:58:52.061405 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8032 RESULT=skip
32427 10:58:52.107152 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8032 RESULT=skip>
32428 10:58:52.107605 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8032 RESULT=skip
32430 10:58:52.153107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8048 RESULT=pass>
32431 10:58:52.153534 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8048 RESULT=pass
32433 10:58:52.201334 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8048 RESULT=skip
32435 10:58:52.201822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8048 RESULT=skip>
32436 10:58:52.247878 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8048 RESULT=skip
32438 10:58:52.248299 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8048 RESULT=skip>
32439 10:58:52.292988 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8064 RESULT=pass>
32440 10:58:52.293369 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8064 RESULT=pass
32442 10:58:52.324586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8064 RESULT=skip>
32443 10:58:52.324988 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8064 RESULT=skip
32445 10:58:52.368923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8064 RESULT=skip>
32446 10:58:52.369304 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8064 RESULT=skip
32448 10:58:52.414756 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8080 RESULT=pass>
32449 10:58:52.415362 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8080 RESULT=pass
32451 10:58:52.458216 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8080 RESULT=skip
32453 10:58:52.458643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8080 RESULT=skip>
32454 10:58:52.503829 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8080 RESULT=skip
32456 10:58:52.504260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8080 RESULT=skip>
32457 10:58:52.546703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8096 RESULT=pass>
32458 10:58:52.547089 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8096 RESULT=pass
32460 10:58:52.590227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8096 RESULT=skip>
32461 10:58:52.590618 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8096 RESULT=skip
32463 10:58:52.632573 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8096 RESULT=skip>
32464 10:58:52.632957 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8096 RESULT=skip
32466 10:58:52.674170 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8112 RESULT=pass>
32467 10:58:52.674600 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8112 RESULT=pass
32469 10:58:52.715348 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8112 RESULT=skip>
32470 10:58:52.715784 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8112 RESULT=skip
32472 10:58:52.749724 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8112 RESULT=skip
32474 10:58:52.750177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8112 RESULT=skip>
32475 10:58:52.782742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8128 RESULT=pass>
32476 10:58:52.783150 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8128 RESULT=pass
32478 10:58:52.821226 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8128 RESULT=skip>
32479 10:58:52.821617 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8128 RESULT=skip
32481 10:58:52.865139 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8128 RESULT=skip
32483 10:58:52.865565 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8128 RESULT=skip>
32484 10:58:52.906788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8144 RESULT=pass>
32485 10:58:52.907186 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8144 RESULT=pass
32487 10:58:52.950304 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8144 RESULT=skip>
32488 10:58:52.950690 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8144 RESULT=skip
32490 10:58:52.992955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8144 RESULT=skip>
32491 10:58:52.993379 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8144 RESULT=skip
32493 10:58:53.031068 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8160 RESULT=pass>
32494 10:58:53.031448 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8160 RESULT=pass
32496 10:58:53.073991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8160 RESULT=skip>
32497 10:58:53.074409 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8160 RESULT=skip
32499 10:58:53.116630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8160 RESULT=skip>
32500 10:58:53.117025 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8160 RESULT=skip
32502 10:58:53.156386 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8176 RESULT=pass>
32503 10:58:53.156808 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8176 RESULT=pass
32505 10:58:53.200001 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8176 RESULT=skip
32507 10:58:53.200429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8176 RESULT=skip>
32508 10:58:53.243436 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8176 RESULT=skip>
32509 10:58:53.243854 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8176 RESULT=skip
32511 10:58:53.287209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8192 RESULT=pass>
32512 10:58:53.287619 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8192 RESULT=pass
32514 10:58:53.330228 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8192 RESULT=skip>
32515 10:58:53.330643 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8192 RESULT=skip
32517 10:58:53.373862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8192 RESULT=skip>
32518 10:58:53.374298 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8192 RESULT=skip
32520 10:58:53.415785 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace RESULT=pass
32522 10:58:53.416246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace RESULT=pass>
32523 10:58:53.459362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_sync_err_mode_and_mmap_memory RESULT=pass>
32524 10:58:53.459784 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_sync_err_mode_and_mmap_memory RESULT=pass
32526 10:58:53.502849 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_async_err_mode_and_mmap_memory RESULT=pass>
32527 10:58:53.503234 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_async_err_mode_and_mmap_memory RESULT=pass
32529 10:58:53.547144 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_sync_err_mode_and_mmap_mprotect_memory RESULT=pass>
32530 10:58:53.547604 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_sync_err_mode_and_mmap_mprotect_memory RESULT=pass
32532 10:58:53.581079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_async_err_mode_and_mmap_mprotect_memory RESULT=pass>
32533 10:58:53.581458 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_async_err_mode_and_mmap_mprotect_memory RESULT=pass
32535 10:58:53.617190 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_sync_mode_and_mmap_memory RESULT=fail>
32536 10:58:53.617610 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_sync_mode_and_mmap_memory RESULT=fail
32538 10:58:53.657359 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_async_mode_and_mmap_memory RESULT=fail
32540 10:58:53.657804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_async_mode_and_mmap_memory RESULT=fail>
32541 10:58:53.702013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_tag_check_fault_ignore_and_mmap_memory RESULT=pass>
32542 10:58:53.702407 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_tag_check_fault_ignore_and_mmap_memory RESULT=pass
32544 10:58:53.744996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_sync_mode_and_mmap_memory RESULT=pass>
32545 10:58:53.745361 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_sync_mode_and_mmap_memory RESULT=pass
32547 10:58:53.786835 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_async_mode_and_mmap_memory RESULT=pass>
32548 10:58:53.787208 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_async_mode_and_mmap_memory RESULT=pass
32550 10:58:53.829884 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_tag_check_fault_ignore_and_mmap_memory RESULT=pass>
32551 10:58:53.830265 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_tag_check_fault_ignore_and_mmap_memory RESULT=pass
32553 10:58:53.871663 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_sync_mode_and_mmap_memory RESULT=fail
32555 10:58:53.872104 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_sync_mode_and_mmap_memory RESULT=fail>
32556 10:58:53.912752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_async_mode_and_mmap_memory RESULT=fail>
32557 10:58:53.913075 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_async_mode_and_mmap_memory RESULT=fail
32559 10:58:53.956455 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_tag_fault_ignore_mode_and_mmap_memory RESULT=pass
32561 10:58:53.956843 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_tag_fault_ignore_mode_and_mmap_memory RESULT=pass>
32562 10:58:54.004895 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_sync_mode_and_mmap_memory RESULT=fail
32564 10:58:54.005335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_sync_mode_and_mmap_memory RESULT=fail>
32565 10:58:54.066668 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_async_mode_and_mmap_memory RESULT=fail
32567 10:58:54.067126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_async_mode_and_mmap_memory RESULT=fail>
32568 10:58:54.113690 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_tag_fault_ignore_and_mmap_memory RESULT=pass
32570 10:58:54.114134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_tag_fault_ignore_and_mmap_memory RESULT=pass>
32571 10:58:54.161180 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_initial_tags_with_private_mapping_sync_error_mode_and_mmap_memory RESULT=pass>
32572 10:58:54.161542 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_initial_tags_with_private_mapping_sync_error_mode_and_mmap_memory RESULT=pass
32574 10:58:54.209712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_initial_tags_with_private_mapping_sync_error_mode_and_mmap_mprotect_memory RESULT=pass>
32575 10:58:54.210133 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_initial_tags_with_private_mapping_sync_error_mode_and_mmap_mprotect_memory RESULT=pass
32577 10:58:54.259638 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_initial_tags_with_shared_mapping_sync_error_mode_and_mmap_memory RESULT=pass
32579 10:58:54.260123 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_initial_tags_with_shared_mapping_sync_error_mode_and_mmap_memory RESULT=pass>
32580 10:58:54.310999 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_initial_tags_with_shared_mapping_sync_error_mode_and_mmap_mprotect_memory RESULT=pass>
32581 10:58:54.311436 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_initial_tags_with_shared_mapping_sync_error_mode_and_mmap_mprotect_memory RESULT=pass
32583 10:58:54.361424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill RESULT=fail>
32584 10:58:54.361847 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill RESULT=fail
32586 10:58:54.409134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_precise_mode_and_mmap_memory RESULT=fail>
32587 10:58:54.409568 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_precise_mode_and_mmap_memory RESULT=fail
32589 10:58:54.456112 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_precise_mode_and_mmap_memory RESULT=fail
32591 10:58:54.456571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_precise_mode_and_mmap_memory RESULT=fail>
32592 10:58:54.503234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_imprecise_mode_and_mmap_memory RESULT=fail>
32593 10:58:54.503658 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_imprecise_mode_and_mmap_memory RESULT=fail
32595 10:58:54.551017 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_imprecise_mode_and_mmap_memory RESULT=fail
32597 10:58:54.551456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_imprecise_mode_and_mmap_memory RESULT=fail>
32598 10:58:54.598562 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_precise_mode_and_mmap_mprotect_memory RESULT=fail
32600 10:58:54.598991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_precise_mode_and_mmap_mprotect_memory RESULT=fail>
32601 10:58:54.647093 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_precise_mode_and_mmap_mprotect_memory RESULT=fail>
32602 10:58:54.647494 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_precise_mode_and_mmap_mprotect_memory RESULT=fail
32604 10:58:54.694657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_private_mapping_precise_mode_and_mmap_memory RESULT=fail>
32605 10:58:54.695060 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_private_mapping_precise_mode_and_mmap_memory RESULT=fail
32607 10:58:54.741900 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_precise_mode_and_mmap_memory RESULT=fail
32609 10:58:54.742342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_precise_mode_and_mmap_memory RESULT=fail>
32610 10:58:54.789657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_private_mapping_imprecise_mode_and_mmap_memory RESULT=fail>
32611 10:58:54.790088 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_private_mapping_imprecise_mode_and_mmap_memory RESULT=fail
32613 10:58:54.836823 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_imprecise_mode_and_mmap_memory RESULT=fail
32615 10:58:54.837305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_imprecise_mode_and_mmap_memory RESULT=fail>
32616 10:58:54.883208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_private_mapping_precise_mode_and_mmap_mprotect_memory RESULT=fail>
32617 10:58:54.883600 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_private_mapping_precise_mode_and_mmap_mprotect_memory RESULT=fail
32619 10:58:54.930138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_precise_mode_and_mmap_mprotect_memory RESULT=fail>
32620 10:58:54.930574 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_precise_mode_and_mmap_mprotect_memory RESULT=fail
32622 10:58:54.978749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory RESULT=fail>
32623 10:58:54.979144 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory RESULT=fail
32625 10:58:55.025722 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_gcr_el1_cswitch RESULT=fail
32627 10:58:55.026208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_gcr_el1_cswitch RESULT=fail>
32628 10:58:55.071237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_ksm_options RESULT=fail>
32629 10:58:55.071647 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_ksm_options RESULT=fail
32631 10:58:55.119168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_off RESULT=pass>
32632 10:58:55.119568 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_off RESULT=pass
32634 10:58:55.167120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_off RESULT=pass>
32635 10:58:55.167552 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_off RESULT=pass
32637 10:58:55.215772 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_no_error_mode_mmap_memory_and_tag_check_off RESULT=pass
32639 10:58:55.216270 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_no_error_mode_mmap_memory_and_tag_check_off RESULT=pass>
32640 10:58:55.263706 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_no_error_mode_mmap_mprotect_memory_and_tag_check_off RESULT=pass
32642 10:58:55.264164 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_no_error_mode_mmap_mprotect_memory_and_tag_check_off RESULT=pass>
32643 10:58:55.311139 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_on RESULT=fail
32645 10:58:55.311733 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_on RESULT=fail>
32646 10:58:55.357778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail>
32647 10:58:55.358165 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail
32649 10:58:55.405103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_sync_error_mode_mmap_memory_and_tag_check_on RESULT=fail>
32650 10:58:55.405503 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_sync_error_mode_mmap_memory_and_tag_check_on RESULT=fail
32652 10:58:55.451836 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail
32654 10:58:55.452218 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail>
32655 10:58:55.499106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_async_error_mode_mmap_memory_and_tag_check_on RESULT=fail>
32656 10:58:55.499524 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_async_error_mode_mmap_memory_and_tag_check_on RESULT=fail
32658 10:58:55.546291 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail
32660 10:58:55.546737 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail>
32661 10:58:55.593560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_async_error_mode_mmap_memory_and_tag_check_on RESULT=fail>
32662 10:58:55.593991 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_async_error_mode_mmap_memory_and_tag_check_on RESULT=fail
32664 10:58:55.641277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail>
32665 10:58:55.641667 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail
32667 10:58:55.688044 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_on RESULT=fail
32669 10:58:55.688459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_on RESULT=fail>
32670 10:58:55.735930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail>
32671 10:58:55.736326 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail
32673 10:58:55.783191 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_shared_mapping_sync_error_mode_mmap_memory_and_tag_check_on RESULT=fail
32675 10:58:55.783649 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_shared_mapping_sync_error_mode_mmap_memory_and_tag_check_on RESULT=fail>
32676 10:58:55.830047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_shared_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail>
32677 10:58:55.830504 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_shared_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail
32679 10:58:55.876851 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_async_error_mode_mmap_memory_and_tag_check_on RESULT=fail>
32680 10:58:55.877295 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_async_error_mode_mmap_memory_and_tag_check_on RESULT=fail
32682 10:58:55.923352 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail
32684 10:58:55.923801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail>
32685 10:58:55.970522 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_shared_mapping_async_error_mode_mmap_memory_and_tag_check_on RESULT=fail>
32686 10:58:55.970931 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_shared_mapping_async_error_mode_mmap_memory_and_tag_check_on RESULT=fail
32688 10:58:56.017947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_shared_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail>
32689 10:58:56.018370 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_shared_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail
32691 10:58:56.064951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_clear_PROT_MTE_flags_with_private_mapping_sync_error_mode_and_mmap_memory RESULT=fail>
32692 10:58:56.065380 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_clear_PROT_MTE_flags_with_private_mapping_sync_error_mode_and_mmap_memory RESULT=fail
32694 10:58:56.111873 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_clear_PROT_MTE_flags_with_private_mapping_and_sync_error_mode_and_mmap_mprotect_memory RESULT=fail
32696 10:58:56.112313 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_clear_PROT_MTE_flags_with_private_mapping_and_sync_error_mode_and_mmap_mprotect_memory RESULT=fail>
32697 10:58:56.160674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options RESULT=fail>
32698 10:58:56.161075 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options RESULT=fail
32700 10:58:56.206158 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_check_basic_read RESULT=pass>
32701 10:58:56.206606 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_check_basic_read RESULT=pass
32703 10:58:56.252763 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_NONE RESULT=pass>
32704 10:58:56.253177 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_NONE RESULT=pass
32706 10:58:56.297930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_SYNC RESULT=pass>
32707 10:58:56.298351 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_SYNC RESULT=pass
32709 10:58:56.344621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_ASYNC RESULT=pass>
32710 10:58:56.344970 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_ASYNC RESULT=pass
32712 10:58:56.390418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_SYNC_ASYNC RESULT=pass>
32713 10:58:56.390801 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_SYNC_ASYNC RESULT=pass
32715 10:58:56.436421 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl RESULT=pass
32717 10:58:56.436881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl RESULT=pass>
32718 10:58:56.483616 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_tags_inclusion_Check_an_included_tag_value_with_sync_mode RESULT=fail
32720 10:58:56.484060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_tags_inclusion_Check_an_included_tag_value_with_sync_mode RESULT=fail>
32721 10:58:56.530716 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_tags_inclusion_Check_different_included_tags_value_with_sync_mode RESULT=fail>
32722 10:58:56.531146 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_tags_inclusion_Check_different_included_tags_value_with_sync_mode RESULT=fail
32724 10:58:56.578254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_tags_inclusion_Check_none_included_tags_value_with_sync_mode RESULT=pass>
32725 10:58:56.578615 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_tags_inclusion_Check_none_included_tags_value_with_sync_mode RESULT=pass
32727 10:58:56.625501 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_tags_inclusion_Check_all_included_tags_value_with_sync_mode RESULT=fail>
32728 10:58:56.625897 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_tags_inclusion_Check_all_included_tags_value_with_sync_mode RESULT=fail
32730 10:58:56.671973 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_tags_inclusion RESULT=fail
32732 10:58:56.672532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_tags_inclusion RESULT=fail>
32733 10:58:56.718287 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass
32735 10:58:56.718720 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass>
32736 10:58:56.762898 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass
32738 10:58:56.763327 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass>
32739 10:58:56.808301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass>
32740 10:58:56.808698 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass
32742 10:58:56.855108 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass
32744 10:58:56.855561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass>
32745 10:58:56.903504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass>
32746 10:58:56.903881 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass
32748 10:58:56.950329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass>
32749 10:58:56.950756 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass
32751 10:58:56.995876 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass
32753 10:58:56.996303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass>
32754 10:58:57.041320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass>
32755 10:58:57.041689 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass
32757 10:58:57.083081 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass
32759 10:58:57.083503 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass>
32760 10:58:57.127380 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass
32762 10:58:57.127794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass>
32763 10:58:57.171461 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass
32765 10:58:57.171918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass>
32766 10:58:57.217000 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass>
32767 10:58:57.217350 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass
32769 10:58:57.260028 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass
32771 10:58:57.260402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass>
32772 10:58:57.304452 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass
32774 10:58:57.304872 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass>
32775 10:58:57.348471 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass
32777 10:58:57.348899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass>
32778 10:58:57.392078 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass
32780 10:58:57.392453 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass>
32781 10:58:57.438576 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass
32783 10:58:57.439009 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass>
32784 10:58:57.483105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass>
32785 10:58:57.483519 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass
32787 10:58:57.526812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass>
32788 10:58:57.527170 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass
32790 10:58:57.570347 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass
32792 10:58:57.570784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass>
32793 10:58:57.615149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass>
32794 10:58:57.615582 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass
32796 10:58:57.658744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass>
32797 10:58:57.659117 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass
32799 10:58:57.704028 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass
32801 10:58:57.704512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass>
32802 10:58:57.737079 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass
32804 10:58:57.737529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass>
32805 10:58:57.780893 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass>
32806 10:58:57.781310 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass
32808 10:58:57.813499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass>
32809 10:58:57.813933 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass
32811 10:58:57.857086 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass
32813 10:58:57.857524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass>
32814 10:58:57.895218 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass>
32815 10:58:57.895581 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass
32817 10:58:57.938542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass>
32818 10:58:57.938978 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass
32820 10:58:57.981015 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass>
32821 10:58:57.981465 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass
32823 10:58:58.025224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass>
32824 10:58:58.025652 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass
32826 10:58:58.072685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass>
32827 10:58:58.073118 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass
32829 10:58:58.115869 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass
32831 10:58:58.116322 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass>
32832 10:58:58.166174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass>
32833 10:58:58.166601 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass
32835 10:58:58.213438 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass>
32836 10:58:58.213859 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass
32838 10:58:58.265003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass>
32839 10:58:58.265402 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass
32841 10:58:58.312964 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass
32843 10:58:58.313374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass>
32844 10:58:58.360572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass>
32845 10:58:58.360977 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass
32847 10:58:58.413799 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass>
32848 10:58:58.414161 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass
32850 10:58:58.462894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass>
32851 10:58:58.463301 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass
32853 10:58:58.513448 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass>
32854 10:58:58.513895 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass
32856 10:58:58.562735 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass>
32857 10:58:58.563126 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass
32859 10:58:58.610757 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass>
32860 10:58:58.611132 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass
32862 10:58:58.660958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass>
32863 10:58:58.661376 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass
32865 10:58:58.709781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass>
32866 10:58:58.710206 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass
32868 10:58:58.757455 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass>
32869 10:58:58.757879 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass
32871 10:58:58.804698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass>
32872 10:58:58.805115 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass
32874 10:58:58.852510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass>
32875 10:58:58.852898 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass
32877 10:58:58.899357 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass>
32878 10:58:58.899772 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass
32880 10:58:58.946548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass>
32881 10:58:58.946952 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass
32883 10:58:58.979694 <47>[ 370.507163] systemd-journald[105]: Sent WATCHDOG=1 notification.
32884 10:58:59.010261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass>
32885 10:58:59.010617 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass
32887 10:58:59.061484 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass>
32888 10:58:59.061910 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass
32890 10:58:59.112023 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass
32892 10:58:59.112478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass>
32893 10:58:59.174574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass>
32894 10:58:59.175005 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass
32896 10:58:59.217541 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass>
32897 10:58:59.217970 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass
32899 10:58:59.258496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass>
32900 10:58:59.258917 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass
32902 10:58:59.305077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass>
32903 10:58:59.305502 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass
32905 10:58:59.350375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass>
32906 10:58:59.350794 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass
32908 10:58:59.395371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass>
32909 10:58:59.398273 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass
32911 10:58:59.438176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass>
32912 10:58:59.438599 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass
32914 10:58:59.484643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass>
32915 10:58:59.485063 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass
32917 10:58:59.529948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass>
32918 10:58:59.530369 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass
32920 10:58:59.574938 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass
32922 10:58:59.575391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass>
32923 10:58:59.618668 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass
32925 10:58:59.619107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass>
32926 10:58:59.659190 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem RESULT=pass>
32927 10:58:59.659614 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem RESULT=pass
32929 10:58:59.694255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x0 RESULT=pass>
32930 10:58:59.694664 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x0 RESULT=pass
32932 10:58:59.727206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x16 RESULT=pass>
32933 10:58:59.727616 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x16 RESULT=pass
32935 10:58:59.766104 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_blr RESULT=pass
32937 10:58:59.766570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_blr RESULT=pass>
32938 10:58:59.809267 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x0 RESULT=pass
32940 10:58:59.809733 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x0 RESULT=pass>
32941 10:58:59.845723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x16 RESULT=pass>
32942 10:58:59.846140 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x16 RESULT=pass
32944 10:58:59.882281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_blr RESULT=pass>
32945 10:58:59.882687 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_blr RESULT=pass
32947 10:58:59.922551 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x0 RESULT=pass
32949 10:58:59.923015 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x0 RESULT=pass>
32950 10:58:59.962670 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x16 RESULT=pass
32952 10:58:59.963147 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x16 RESULT=pass>
32953 10:58:59.997720 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_blr RESULT=pass>
32954 10:58:59.998158 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_blr RESULT=pass
32956 10:59:00.033123 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x0 RESULT=pass
32958 10:59:00.033556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x0 RESULT=pass>
32959 10:59:00.069637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x16 RESULT=pass>
32960 10:59:00.070064 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x16 RESULT=pass
32962 10:59:00.102687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_blr RESULT=pass>
32963 10:59:00.103102 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_blr RESULT=pass
32965 10:59:00.135827 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x0 RESULT=pass
32967 10:59:00.136266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x0 RESULT=pass>
32968 10:59:00.174878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x16 RESULT=pass>
32969 10:59:00.175264 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x16 RESULT=pass
32971 10:59:00.218179 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_blr RESULT=pass>
32972 10:59:00.218604 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_blr RESULT=pass
32974 10:59:00.261538 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x0 RESULT=pass>
32975 10:59:00.261963 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x0 RESULT=pass
32977 10:59:00.302428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x16 RESULT=pass>
32978 10:59:00.302794 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x16 RESULT=pass
32980 10:59:00.335652 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_blr RESULT=pass
32982 10:59:00.336131 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_blr RESULT=pass>
32983 10:59:00.368987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest RESULT=pass>
32984 10:59:00.369428 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest RESULT=pass
32986 10:59:00.414818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x0 RESULT=pass>
32987 10:59:00.415230 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x0 RESULT=pass
32989 10:59:00.461211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x16 RESULT=pass>
32990 10:59:00.461607 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x16 RESULT=pass
32992 10:59:00.501419 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_blr RESULT=pass
32994 10:59:00.501896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_blr RESULT=pass>
32995 10:59:00.541937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x0 RESULT=pass>
32996 10:59:00.542362 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x0 RESULT=pass
32998 10:59:00.583144 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x16 RESULT=pass>
32999 10:59:00.583549 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x16 RESULT=pass
33001 10:59:00.628479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_blr RESULT=pass>
33002 10:59:00.628919 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_blr RESULT=pass
33004 10:59:00.673131 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x0 RESULT=pass
33006 10:59:00.673562 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x0 RESULT=pass>
33007 10:59:00.718779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x16 RESULT=pass>
33008 10:59:00.719190 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x16 RESULT=pass
33010 10:59:00.764920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_blr RESULT=pass>
33011 10:59:00.765338 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_blr RESULT=pass
33013 10:59:00.812054 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x0 RESULT=pass
33015 10:59:00.812410 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x0 RESULT=pass>
33016 10:59:00.854025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x16 RESULT=pass>
33017 10:59:00.854444 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x16 RESULT=pass
33019 10:59:00.898969 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_blr RESULT=pass
33021 10:59:00.899443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_blr RESULT=pass>
33022 10:59:00.943710 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x0 RESULT=pass
33024 10:59:00.944186 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x0 RESULT=pass>
33025 10:59:00.986456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x16 RESULT=pass>
33026 10:59:00.986862 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x16 RESULT=pass
33028 10:59:01.034217 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_blr RESULT=pass>
33029 10:59:01.034636 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_blr RESULT=pass
33031 10:59:01.082458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x0 RESULT=pass>
33032 10:59:01.082883 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x0 RESULT=pass
33034 10:59:01.129258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x16 RESULT=pass>
33035 10:59:01.129680 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x16 RESULT=pass
33037 10:59:01.173718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_blr RESULT=pass>
33038 10:59:01.174132 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_blr RESULT=pass
33040 10:59:01.217537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest RESULT=pass>
33041 10:59:01.217976 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest RESULT=pass
33043 10:59:01.264897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_RNG RESULT=pass>
33044 10:59:01.265309 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_RNG RESULT=pass
33046 10:59:01.310323 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_RNG RESULT=pass
33048 10:59:01.310755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_RNG RESULT=pass>
33049 10:59:01.353049 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SME RESULT=pass>
33050 10:59:01.353449 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SME RESULT=pass
33052 10:59:01.397483 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SME RESULT=pass>
33053 10:59:01.397891 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SME RESULT=pass
33055 10:59:01.445964 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE RESULT=pass>
33056 10:59:01.446354 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE RESULT=pass
33058 10:59:01.493062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE RESULT=pass>
33059 10:59:01.493449 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE RESULT=pass
33061 10:59:01.534754 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_2 RESULT=pass>
33062 10:59:01.535139 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_2 RESULT=pass
33064 10:59:01.576557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE_2 RESULT=pass>
33065 10:59:01.576975 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE_2 RESULT=pass
33067 10:59:01.610520 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_AES RESULT=pass
33069 10:59:01.610979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_AES RESULT=pass>
33070 10:59:01.657253 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE_AES RESULT=pass
33072 10:59:01.657746 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE_AES RESULT=pass>
33073 10:59:01.694609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_PMULL RESULT=pass>
33074 10:59:01.695010 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_PMULL RESULT=pass
33076 10:59:01.734682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_PMULL RESULT=pass>
33077 10:59:01.735080 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_PMULL RESULT=pass
33079 10:59:01.778455 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BITPERM RESULT=pass>
33080 10:59:01.778874 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BITPERM RESULT=pass
33082 10:59:01.822746 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BITPERM RESULT=pass>
33083 10:59:01.823204 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BITPERM RESULT=pass
33085 10:59:01.866797 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SHA3 RESULT=pass
33087 10:59:01.867264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SHA3 RESULT=pass>
33088 10:59:01.910854 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SHA3 RESULT=pass>
33089 10:59:01.911272 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SHA3 RESULT=pass
33091 10:59:01.956653 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SM4 RESULT=pass>
33092 10:59:01.957047 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SM4 RESULT=pass
33094 10:59:01.999544 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SM4 RESULT=pass
33096 10:59:02.000020 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SM4 RESULT=pass>
33097 10:59:02.046138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_I8MM RESULT=pass>
33098 10:59:02.046527 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_I8MM RESULT=pass
33100 10:59:02.089497 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_I8MM RESULT=pass>
33101 10:59:02.089922 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_I8MM RESULT=pass
33103 10:59:02.132949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F32MM RESULT=pass>
33104 10:59:02.133343 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F32MM RESULT=pass
33106 10:59:02.174006 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F32MM RESULT=pass>
33107 10:59:02.174447 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F32MM RESULT=pass
33109 10:59:02.215083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F64MM RESULT=pass>
33110 10:59:02.215517 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F64MM RESULT=pass
33112 10:59:02.259044 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F64MM RESULT=pass
33114 10:59:02.259497 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F64MM RESULT=pass>
33115 10:59:02.301232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BF16 RESULT=pass>
33116 10:59:02.301644 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BF16 RESULT=pass
33118 10:59:02.345955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BF16 RESULT=pass>
33119 10:59:02.346380 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BF16 RESULT=pass
33121 10:59:02.391005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_EBF16 RESULT=pass>
33122 10:59:02.391431 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_EBF16 RESULT=pass
33124 10:59:02.437049 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_EBF16 RESULT=skip>
33125 10:59:02.437430 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_EBF16 RESULT=skip
33127 10:59:02.481489 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap RESULT=pass>
33128 10:59:02.481922 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap RESULT=pass
33130 10:59:02.526319 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_read_tpidr_one RESULT=pass
33132 10:59:02.527036 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_read_tpidr_one RESULT=pass>
33133 10:59:02.573854 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_write_tpidr_one RESULT=pass>
33134 10:59:02.574295 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_write_tpidr_one RESULT=pass
33136 10:59:02.618891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_verify_tpidr_one RESULT=pass>
33137 10:59:02.619296 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_verify_tpidr_one RESULT=pass
33139 10:59:02.663028 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_count_tpidrs RESULT=pass>
33140 10:59:02.663426 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_count_tpidrs RESULT=pass
33142 10:59:02.701127 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_tpidr2_write RESULT=pass
33144 10:59:02.701536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_tpidr2_write RESULT=pass>
33145 10:59:02.747346 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_tpidr2_read RESULT=pass
33147 10:59:02.747884 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_tpidr2_read RESULT=pass>
33148 10:59:02.790529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_write_tpidr_only RESULT=pass>
33149 10:59:02.790949 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_write_tpidr_only RESULT=pass
33151 10:59:02.836442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace RESULT=pass>
33152 10:59:02.836888 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace RESULT=pass
33154 10:59:02.880847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_FPSIMD RESULT=pass>
33155 10:59:02.881275 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_FPSIMD RESULT=pass
33157 10:59:02.924553 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256 RESULT=pass>
33158 10:59:02.924985 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256 RESULT=pass
33160 10:59:02.969090 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_SM_ZA RESULT=pass
33162 10:59:02.969534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_SM_ZA RESULT=pass>
33163 10:59:03.014490 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_SM RESULT=pass>
33164 10:59:03.014917 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_SM RESULT=pass
33166 10:59:03.067208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_ZA RESULT=pass>
33167 10:59:03.067600 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_ZA RESULT=pass
33169 10:59:03.109615 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_SM_ZA RESULT=pass
33171 10:59:03.110101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_SM_ZA RESULT=pass>
33172 10:59:03.149432 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_SM RESULT=pass>
33173 10:59:03.149833 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_SM RESULT=pass
33175 10:59:03.193730 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_ZA RESULT=pass>
33176 10:59:03.194162 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_ZA RESULT=pass
33178 10:59:03.241903 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_SM_ZA RESULT=pass>
33179 10:59:03.242327 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_SM_ZA RESULT=pass
33181 10:59:03.287283 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_SM RESULT=pass>
33182 10:59:03.287700 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_SM RESULT=pass
33184 10:59:03.333231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_ZA RESULT=pass>
33185 10:59:03.333679 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_ZA RESULT=pass
33187 10:59:03.378474 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_SM_ZA RESULT=pass>
33188 10:59:03.378907 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_SM_ZA RESULT=pass
33190 10:59:03.423623 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_SM RESULT=pass>
33191 10:59:03.424056 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_SM RESULT=pass
33193 10:59:03.469216 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_ZA RESULT=pass>
33194 10:59:03.469650 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_ZA RESULT=pass
33196 10:59:03.514823 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_SM_ZA RESULT=pass>
33197 10:59:03.515238 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_SM_ZA RESULT=pass
33199 10:59:03.560514 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_SM RESULT=pass
33201 10:59:03.560945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_SM RESULT=pass>
33202 10:59:03.594611 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_ZA RESULT=pass>
33203 10:59:03.595050 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_ZA RESULT=pass
33205 10:59:03.639952 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240 RESULT=pass
33207 10:59:03.640426 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240 RESULT=pass>
33208 10:59:03.686511 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_SM_ZA RESULT=pass
33210 10:59:03.686962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_SM_ZA RESULT=pass>
33211 10:59:03.724419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_SM RESULT=pass>
33212 10:59:03.724845 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_SM RESULT=pass
33214 10:59:03.766123 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_ZA RESULT=pass>
33215 10:59:03.766539 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_ZA RESULT=pass
33217 10:59:03.814683 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_SM_ZA RESULT=pass>
33218 10:59:03.815082 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_SM_ZA RESULT=pass
33220 10:59:03.854930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_SM RESULT=pass>
33221 10:59:03.855380 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_SM RESULT=pass
33223 10:59:03.900884 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_ZA RESULT=pass>
33224 10:59:03.901295 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_ZA RESULT=pass
33226 10:59:03.946065 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_SM_ZA RESULT=pass>
33227 10:59:03.946478 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_SM_ZA RESULT=pass
33229 10:59:03.988169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_SM RESULT=pass>
33230 10:59:03.988586 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_SM RESULT=pass
33232 10:59:04.029226 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_ZA RESULT=pass
33234 10:59:04.029675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_ZA RESULT=pass>
33235 10:59:04.072475 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_SM_ZA RESULT=pass>
33236 10:59:04.072891 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_SM_ZA RESULT=pass
33238 10:59:04.112745 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_SM RESULT=pass>
33239 10:59:04.113174 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_SM RESULT=pass
33241 10:59:04.149722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_ZA RESULT=pass>
33242 10:59:04.150145 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_ZA RESULT=pass
33244 10:59:04.188721 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_SM_ZA RESULT=pass
33246 10:59:04.189181 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_SM_ZA RESULT=pass>
33247 10:59:04.226639 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_SM RESULT=pass>
33248 10:59:04.227045 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_SM RESULT=pass
33250 10:59:04.301399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_ZA RESULT=pass>
33251 10:59:04.301848 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_ZA RESULT=pass
33253 10:59:04.348545 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224 RESULT=pass
33255 10:59:04.349003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224 RESULT=pass>
33256 10:59:04.396561 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_SM_ZA RESULT=pass
33258 10:59:04.397023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_SM_ZA RESULT=pass>
33259 10:59:04.443280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_SM RESULT=pass>
33260 10:59:04.443702 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_SM RESULT=pass
33262 10:59:04.490914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_ZA RESULT=pass>
33263 10:59:04.491314 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_ZA RESULT=pass
33265 10:59:04.541296 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_SM_ZA RESULT=pass
33267 10:59:04.541758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_SM_ZA RESULT=pass>
33268 10:59:04.590424 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_SM RESULT=pass
33270 10:59:04.590887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_SM RESULT=pass>
33271 10:59:04.642950 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_ZA RESULT=pass>
33272 10:59:04.643346 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_ZA RESULT=pass
33274 10:59:04.695461 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_SM_ZA RESULT=pass
33276 10:59:04.695897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_SM_ZA RESULT=pass>
33277 10:59:04.745907 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_SM RESULT=pass
33279 10:59:04.746343 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_SM RESULT=pass>
33280 10:59:04.797398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_ZA RESULT=pass>
33281 10:59:04.797811 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_ZA RESULT=pass
33283 10:59:04.846117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_SM_ZA RESULT=pass>
33284 10:59:04.846510 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_SM_ZA RESULT=pass
33286 10:59:04.894186 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_SM RESULT=pass>
33287 10:59:04.894624 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_SM RESULT=pass
33289 10:59:04.943505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_ZA RESULT=pass>
33290 10:59:04.943934 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_ZA RESULT=pass
33292 10:59:04.993462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_SM_ZA RESULT=pass>
33293 10:59:04.993888 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_SM_ZA RESULT=pass
33295 10:59:05.044217 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_SM RESULT=pass
33297 10:59:05.044678 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_SM RESULT=pass>
33298 10:59:05.093779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_ZA RESULT=pass>
33299 10:59:05.094208 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_ZA RESULT=pass
33301 10:59:05.142660 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208 RESULT=pass>
33302 10:59:05.143106 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208 RESULT=pass
33304 10:59:05.192388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_SM_ZA RESULT=pass>
33305 10:59:05.192814 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_SM_ZA RESULT=pass
33307 10:59:05.240986 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_SM RESULT=pass
33309 10:59:05.241453 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_SM RESULT=pass>
33310 10:59:05.290138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_ZA RESULT=pass>
33311 10:59:05.290569 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_ZA RESULT=pass
33313 10:59:05.337875 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_SM_ZA RESULT=pass>
33314 10:59:05.338335 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_SM_ZA RESULT=pass
33316 10:59:05.387344 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_SM RESULT=pass>
33317 10:59:05.387786 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_SM RESULT=pass
33319 10:59:05.437043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_ZA RESULT=pass>
33320 10:59:05.437461 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_ZA RESULT=pass
33322 10:59:05.486051 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_SM_ZA RESULT=pass
33324 10:59:05.486505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_SM_ZA RESULT=pass>
33325 10:59:05.534420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_SM RESULT=pass>
33326 10:59:05.534868 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_SM RESULT=pass
33328 10:59:05.583711 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_ZA RESULT=pass
33330 10:59:05.584508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_ZA RESULT=pass>
33331 10:59:05.631716 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_SM_ZA RESULT=pass
33333 10:59:05.632556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_SM_ZA RESULT=pass>
33334 10:59:05.680686 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_SM RESULT=pass
33336 10:59:05.681152 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_SM RESULT=pass>
33337 10:59:05.728966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_ZA RESULT=pass>
33338 10:59:05.729383 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_ZA RESULT=pass
33340 10:59:05.779621 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_SM_ZA RESULT=pass
33342 10:59:05.780067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_SM_ZA RESULT=pass>
33343 10:59:05.832098 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_SM RESULT=pass
33345 10:59:05.833045 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_SM RESULT=pass>
33346 10:59:05.883421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_ZA RESULT=pass>
33347 10:59:05.883822 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_ZA RESULT=pass
33349 10:59:05.933970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192 RESULT=pass>
33350 10:59:05.934368 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192 RESULT=pass
33352 10:59:05.982884 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_SM_ZA RESULT=pass>
33353 10:59:05.983308 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_SM_ZA RESULT=pass
33355 10:59:06.034452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_SM RESULT=pass>
33356 10:59:06.034877 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_SM RESULT=pass
33358 10:59:06.085782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_ZA RESULT=pass>
33359 10:59:06.086198 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_ZA RESULT=pass
33361 10:59:06.135904 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_SM_ZA RESULT=pass
33363 10:59:06.136365 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_SM_ZA RESULT=pass>
33364 10:59:06.185476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_SM RESULT=pass>
33365 10:59:06.185919 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_SM RESULT=pass
33367 10:59:06.233539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_ZA RESULT=pass>
33368 10:59:06.233969 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_ZA RESULT=pass
33370 10:59:06.281525 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_SM_ZA RESULT=pass>
33371 10:59:06.281951 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_SM_ZA RESULT=pass
33373 10:59:06.328746 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_SM RESULT=pass>
33374 10:59:06.329428 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_SM RESULT=pass
33376 10:59:06.376456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_ZA RESULT=pass>
33377 10:59:06.376854 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_ZA RESULT=pass
33379 10:59:06.423883 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_SM_ZA RESULT=pass
33381 10:59:06.424330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_SM_ZA RESULT=pass>
33382 10:59:06.474639 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_SM RESULT=pass>
33383 10:59:06.475061 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_SM RESULT=pass
33385 10:59:06.526431 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_ZA RESULT=pass
33387 10:59:06.526914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_ZA RESULT=pass>
33388 10:59:06.579216 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_SM_ZA RESULT=pass>
33389 10:59:06.579679 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_SM_ZA RESULT=pass
33391 10:59:06.633196 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_SM RESULT=pass>
33392 10:59:06.633598 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_SM RESULT=pass
33394 10:59:06.687466 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_ZA RESULT=pass>
33395 10:59:06.687900 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_ZA RESULT=pass
33397 10:59:06.739565 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176 RESULT=pass>
33398 10:59:06.740009 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176 RESULT=pass
33400 10:59:06.791718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_SM_ZA RESULT=pass>
33401 10:59:06.792182 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_SM_ZA RESULT=pass
33403 10:59:06.843142 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_SM RESULT=pass>
33404 10:59:06.843566 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_SM RESULT=pass
33406 10:59:06.894697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_ZA RESULT=pass>
33407 10:59:06.895120 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_ZA RESULT=pass
33409 10:59:06.942322 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_SM_ZA RESULT=pass>
33410 10:59:06.942732 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_SM_ZA RESULT=pass
33412 10:59:06.989296 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_SM RESULT=pass>
33413 10:59:06.989686 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_SM RESULT=pass
33415 10:59:07.036256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_ZA RESULT=pass>
33416 10:59:07.036637 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_ZA RESULT=pass
33418 10:59:07.082861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_SM_ZA RESULT=pass>
33419 10:59:07.083259 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_SM_ZA RESULT=pass
33421 10:59:07.132920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_SM RESULT=pass>
33422 10:59:07.133315 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_SM RESULT=pass
33424 10:59:07.183960 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_ZA RESULT=pass
33426 10:59:07.184411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_ZA RESULT=pass>
33427 10:59:07.236499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_SM_ZA RESULT=pass>
33428 10:59:07.236908 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_SM_ZA RESULT=pass
33430 10:59:07.288488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_SM RESULT=pass>
33431 10:59:07.288903 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_SM RESULT=pass
33433 10:59:07.341544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_ZA RESULT=pass>
33434 10:59:07.341964 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_ZA RESULT=pass
33436 10:59:07.393126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_SM_ZA RESULT=pass>
33437 10:59:07.393555 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_SM_ZA RESULT=pass
33439 10:59:07.444853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_SM RESULT=pass>
33440 10:59:07.445272 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_SM RESULT=pass
33442 10:59:07.494849 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_ZA RESULT=pass>
33443 10:59:07.495265 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_ZA RESULT=pass
33445 10:59:07.546114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160 RESULT=pass>
33446 10:59:07.546562 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160 RESULT=pass
33448 10:59:07.598114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_SM_ZA RESULT=pass>
33449 10:59:07.598489 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_SM_ZA RESULT=pass
33451 10:59:07.649570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_SM RESULT=pass>
33452 10:59:07.649985 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_SM RESULT=pass
33454 10:59:07.702808 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_ZA RESULT=pass>
33455 10:59:07.703211 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_ZA RESULT=pass
33457 10:59:07.755023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_SM_ZA RESULT=pass>
33458 10:59:07.755429 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_SM_ZA RESULT=pass
33460 10:59:07.808158 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_SM RESULT=pass
33462 10:59:07.808603 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_SM RESULT=pass>
33463 10:59:07.859327 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_ZA RESULT=pass
33465 10:59:07.859775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_ZA RESULT=pass>
33466 10:59:07.911448 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_SM_ZA RESULT=pass>
33467 10:59:07.911872 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_SM_ZA RESULT=pass
33469 10:59:07.963505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_SM RESULT=pass>
33470 10:59:07.963934 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_SM RESULT=pass
33472 10:59:08.015221 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_ZA RESULT=pass
33474 10:59:08.015556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_ZA RESULT=pass>
33475 10:59:08.067359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_SM_ZA RESULT=pass>
33476 10:59:08.067705 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_SM_ZA RESULT=pass
33478 10:59:08.118873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_SM RESULT=pass>
33479 10:59:08.119280 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_SM RESULT=pass
33481 10:59:08.171698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_ZA RESULT=pass>
33482 10:59:08.172112 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_ZA RESULT=pass
33484 10:59:08.224299 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_SM_ZA RESULT=pass>
33485 10:59:08.224743 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_SM_ZA RESULT=pass
33487 10:59:08.281265 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_SM RESULT=pass
33489 10:59:08.281721 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_SM RESULT=pass>
33490 10:59:08.333030 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_ZA RESULT=pass
33492 10:59:08.333483 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_ZA RESULT=pass>
33493 10:59:08.383279 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144 RESULT=pass
33495 10:59:08.383729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144 RESULT=pass>
33496 10:59:08.434592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_SM_ZA RESULT=pass>
33497 10:59:08.435005 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_SM_ZA RESULT=pass
33499 10:59:08.486190 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_SM RESULT=pass>
33500 10:59:08.486549 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_SM RESULT=pass
33502 10:59:08.541509 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_ZA RESULT=pass
33504 10:59:08.541941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_ZA RESULT=pass>
33505 10:59:08.594983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_SM_ZA RESULT=pass>
33506 10:59:08.595351 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_SM_ZA RESULT=pass
33508 10:59:08.646852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_SM RESULT=pass>
33509 10:59:08.647252 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_SM RESULT=pass
33511 10:59:08.699145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_ZA RESULT=pass>
33512 10:59:08.699548 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_ZA RESULT=pass
33514 10:59:08.751687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_SM_ZA RESULT=pass>
33515 10:59:08.752092 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_SM_ZA RESULT=pass
33517 10:59:08.803239 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_SM RESULT=pass
33519 10:59:08.803591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_SM RESULT=pass>
33520 10:59:08.853427 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_ZA RESULT=pass>
33521 10:59:08.853853 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_ZA RESULT=pass
33523 10:59:08.901603 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_SM_ZA RESULT=pass>
33524 10:59:08.902015 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_SM_ZA RESULT=pass
33526 10:59:08.949341 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_SM RESULT=pass>
33527 10:59:08.949754 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_SM RESULT=pass
33529 10:59:08.997148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_ZA RESULT=pass>
33530 10:59:08.997556 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_ZA RESULT=pass
33532 10:59:09.047052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_SM_ZA RESULT=pass>
33533 10:59:09.047468 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_SM_ZA RESULT=pass
33535 10:59:09.099784 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_SM RESULT=pass
33537 10:59:09.100282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_SM RESULT=pass>
33538 10:59:09.149407 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_ZA RESULT=pass>
33539 10:59:09.149820 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_ZA RESULT=pass
33541 10:59:09.196822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128 RESULT=pass>
33542 10:59:09.197232 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128 RESULT=pass
33544 10:59:09.247539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_SM_ZA RESULT=pass>
33545 10:59:09.247947 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_SM_ZA RESULT=pass
33547 10:59:09.298088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_SM RESULT=pass>
33548 10:59:09.298501 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_SM RESULT=pass
33550 10:59:09.349609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_ZA RESULT=pass>
33551 10:59:09.350038 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_ZA RESULT=pass
33553 10:59:09.426157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_SM_ZA RESULT=pass>
33554 10:59:09.426571 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_SM_ZA RESULT=pass
33556 10:59:09.473215 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_SM RESULT=pass>
33557 10:59:09.473615 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_SM RESULT=pass
33559 10:59:09.520631 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_ZA RESULT=pass
33561 10:59:09.521091 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_ZA RESULT=pass>
33562 10:59:09.570022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_SM_ZA RESULT=pass>
33563 10:59:09.570428 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_SM_ZA RESULT=pass
33565 10:59:09.618698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_SM RESULT=pass>
33566 10:59:09.619101 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_SM RESULT=pass
33568 10:59:09.665498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_ZA RESULT=pass>
33569 10:59:09.665906 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_ZA RESULT=pass
33571 10:59:09.715923 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_SM_ZA RESULT=pass
33573 10:59:09.716355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_SM_ZA RESULT=pass>
33574 10:59:09.767241 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_SM RESULT=pass>
33575 10:59:09.767645 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_SM RESULT=pass
33577 10:59:09.819453 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_ZA RESULT=pass>
33578 10:59:09.819854 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_ZA RESULT=pass
33580 10:59:09.870941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_SM_ZA RESULT=pass>
33581 10:59:09.871358 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_SM_ZA RESULT=pass
33583 10:59:09.924556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_SM RESULT=pass>
33584 10:59:09.924972 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_SM RESULT=pass
33586 10:59:09.975960 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_ZA RESULT=pass
33588 10:59:09.976414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_ZA RESULT=pass>
33589 10:59:10.027234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112 RESULT=pass>
33590 10:59:10.027670 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112 RESULT=pass
33592 10:59:10.078087 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_SM_ZA RESULT=pass>
33593 10:59:10.078487 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_SM_ZA RESULT=pass
33595 10:59:10.125370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_SM RESULT=pass>
33596 10:59:10.125761 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_SM RESULT=pass
33598 10:59:10.174342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_ZA RESULT=pass>
33599 10:59:10.174730 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_ZA RESULT=pass
33601 10:59:10.221907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_SM_ZA RESULT=pass>
33602 10:59:10.222300 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_SM_ZA RESULT=pass
33604 10:59:10.269863 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_SM RESULT=pass>
33605 10:59:10.270252 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_SM RESULT=pass
33607 10:59:10.317641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_ZA RESULT=pass>
33608 10:59:10.318038 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_ZA RESULT=pass
33610 10:59:10.362341 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_SM_ZA RESULT=pass
33612 10:59:10.362756 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_SM_ZA RESULT=pass>
33613 10:59:10.402302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_SM RESULT=pass>
33614 10:59:10.402724 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_SM RESULT=pass
33616 10:59:10.447586 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_ZA RESULT=pass
33618 10:59:10.448043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_ZA RESULT=pass>
33619 10:59:10.493288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_SM_ZA RESULT=pass>
33620 10:59:10.493688 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_SM_ZA RESULT=pass
33622 10:59:10.533387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_SM RESULT=pass>
33623 10:59:10.533801 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_SM RESULT=pass
33625 10:59:10.581602 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_ZA RESULT=pass
33627 10:59:10.582083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_ZA RESULT=pass>
33628 10:59:10.629139 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_SM_ZA RESULT=pass>
33629 10:59:10.629553 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_SM_ZA RESULT=pass
33631 10:59:10.677522 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_SM RESULT=pass>
33632 10:59:10.677944 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_SM RESULT=pass
33634 10:59:10.724726 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_ZA RESULT=pass
33636 10:59:10.725139 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_ZA RESULT=pass>
33637 10:59:10.771130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96 RESULT=pass>
33638 10:59:10.771549 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96 RESULT=pass
33640 10:59:10.824460 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_SM_ZA RESULT=pass>
33641 10:59:10.824852 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_SM_ZA RESULT=pass
33643 10:59:10.876671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_SM RESULT=pass>
33644 10:59:10.877023 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_SM RESULT=pass
33646 10:59:10.929438 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_ZA RESULT=pass>
33647 10:59:10.929814 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_ZA RESULT=pass
33649 10:59:10.982828 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_SM_ZA RESULT=pass>
33650 10:59:10.983213 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_SM_ZA RESULT=pass
33652 10:59:11.037039 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_SM RESULT=pass
33654 10:59:11.037471 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_SM RESULT=pass>
33655 10:59:11.090111 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_ZA RESULT=pass
33657 10:59:11.090537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_ZA RESULT=pass>
33658 10:59:11.140712 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_SM_ZA RESULT=pass
33660 10:59:11.141183 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_SM_ZA RESULT=pass>
33661 10:59:11.186408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_SM RESULT=pass>
33662 10:59:11.186828 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_SM RESULT=pass
33664 10:59:11.232923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_ZA RESULT=pass>
33665 10:59:11.233351 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_ZA RESULT=pass
33667 10:59:11.279058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_SM_ZA RESULT=pass>
33668 10:59:11.279476 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_SM_ZA RESULT=pass
33670 10:59:11.325544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_SM RESULT=pass>
33671 10:59:11.325940 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_SM RESULT=pass
33673 10:59:11.371349 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_ZA RESULT=pass
33675 10:59:11.371792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_ZA RESULT=pass>
33676 10:59:11.417630 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_SM_ZA RESULT=pass
33678 10:59:11.418016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_SM_ZA RESULT=pass>
33679 10:59:11.463835 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_SM RESULT=pass
33681 10:59:11.464234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_SM RESULT=pass>
33682 10:59:11.509689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_ZA RESULT=pass>
33683 10:59:11.510086 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_ZA RESULT=pass
33685 10:59:11.555113 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80 RESULT=pass
33687 10:59:11.555539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80 RESULT=pass>
33688 10:59:11.601810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_SM_ZA RESULT=pass>
33689 10:59:11.602196 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_SM_ZA RESULT=pass
33691 10:59:11.648401 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_SM RESULT=pass>
33692 10:59:11.648803 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_SM RESULT=pass
33694 10:59:11.695762 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_ZA RESULT=pass
33696 10:59:11.696190 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_ZA RESULT=pass>
33697 10:59:11.742129 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_SM_ZA RESULT=pass>
33698 10:59:11.742525 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_SM_ZA RESULT=pass
33700 10:59:11.788376 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_SM RESULT=pass>
33701 10:59:11.788738 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_SM RESULT=pass
33703 10:59:11.836945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_ZA RESULT=pass>
33704 10:59:11.837362 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_ZA RESULT=pass
33706 10:59:11.882969 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_SM_ZA RESULT=pass
33708 10:59:11.883426 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_SM_ZA RESULT=pass>
33709 10:59:11.929136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_SM RESULT=pass>
33710 10:59:11.929540 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_SM RESULT=pass
33712 10:59:11.974789 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_ZA RESULT=pass>
33713 10:59:11.975200 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_ZA RESULT=pass
33715 10:59:12.021314 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_SM_ZA RESULT=pass
33717 10:59:12.021788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_SM_ZA RESULT=pass>
33718 10:59:12.067106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_SM RESULT=pass>
33719 10:59:12.067528 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_SM RESULT=pass
33721 10:59:12.113644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_ZA RESULT=pass>
33722 10:59:12.114063 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_ZA RESULT=pass
33724 10:59:12.161111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_SM_ZA RESULT=pass>
33725 10:59:12.161525 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_SM_ZA RESULT=pass
33727 10:59:12.209564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_SM RESULT=pass>
33728 10:59:12.210066 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_SM RESULT=pass
33730 10:59:12.257155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_ZA RESULT=pass>
33731 10:59:12.257595 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_ZA RESULT=pass
33733 10:59:12.303508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64 RESULT=pass>
33734 10:59:12.303935 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64 RESULT=pass
33736 10:59:12.350336 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_SM_ZA RESULT=pass>
33737 10:59:12.350730 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_SM_ZA RESULT=pass
33739 10:59:12.399230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_SM RESULT=pass>
33740 10:59:12.399641 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_SM RESULT=pass
33742 10:59:12.446879 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_ZA RESULT=pass>
33743 10:59:12.447303 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_ZA RESULT=pass
33745 10:59:12.494950 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_SM_ZA RESULT=pass>
33746 10:59:12.495369 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_SM_ZA RESULT=pass
33748 10:59:12.542086 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_SM RESULT=pass>
33749 10:59:12.542459 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_SM RESULT=pass
33751 10:59:12.589586 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_ZA RESULT=pass
33753 10:59:12.590046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_ZA RESULT=pass>
33754 10:59:12.641103 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_SM_ZA RESULT=pass
33756 10:59:12.641551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_SM_ZA RESULT=pass>
33757 10:59:12.690553 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_SM RESULT=pass>
33758 10:59:12.690946 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_SM RESULT=pass
33760 10:59:12.738399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_ZA RESULT=pass>
33761 10:59:12.738806 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_ZA RESULT=pass
33763 10:59:12.778045 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_SM_ZA RESULT=pass>
33764 10:59:12.778464 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_SM_ZA RESULT=pass
33766 10:59:12.821072 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_SM RESULT=pass
33768 10:59:12.821510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_SM RESULT=pass>
33769 10:59:12.867409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_ZA RESULT=pass>
33770 10:59:12.867847 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_ZA RESULT=pass
33772 10:59:12.907006 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_SM_ZA RESULT=pass>
33773 10:59:12.907411 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_SM_ZA RESULT=pass
33775 10:59:12.952544 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_SM RESULT=pass
33777 10:59:12.952990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_SM RESULT=pass>
33778 10:59:12.993315 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_ZA RESULT=pass>
33779 10:59:12.993696 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_ZA RESULT=pass
33781 10:59:13.036938 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48 RESULT=pass>
33782 10:59:13.037356 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48 RESULT=pass
33784 10:59:13.074253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_SM_ZA RESULT=pass>
33785 10:59:13.074674 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_SM_ZA RESULT=pass
33787 10:59:13.107121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_SM RESULT=pass>
33788 10:59:13.107533 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_SM RESULT=pass
33790 10:59:13.140624 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_ZA RESULT=pass
33792 10:59:13.141087 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_ZA RESULT=pass>
33793 10:59:13.181424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_SM_ZA RESULT=pass>
33794 10:59:13.181847 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_SM_ZA RESULT=pass
33796 10:59:13.221516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_SM RESULT=pass>
33797 10:59:13.221962 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_SM RESULT=pass
33799 10:59:13.255629 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_ZA RESULT=pass>
33800 10:59:13.256077 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_ZA RESULT=pass
33802 10:59:13.301366 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_SM_ZA RESULT=pass>
33803 10:59:13.301798 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_SM_ZA RESULT=pass
33805 10:59:13.346812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_SM RESULT=pass>
33806 10:59:13.347233 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_SM RESULT=pass
33808 10:59:13.395404 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_ZA RESULT=pass>
33809 10:59:13.395827 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_ZA RESULT=pass
33811 10:59:13.442049 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_SM_ZA RESULT=pass>
33812 10:59:13.442485 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_SM_ZA RESULT=pass
33814 10:59:13.493076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_SM RESULT=pass>
33815 10:59:13.493504 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_SM RESULT=pass
33817 10:59:13.530845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_ZA RESULT=pass>
33818 10:59:13.531241 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_ZA RESULT=pass
33820 10:59:13.575039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_SM_ZA RESULT=pass>
33821 10:59:13.575451 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_SM_ZA RESULT=pass
33823 10:59:13.618890 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_SM RESULT=pass>
33824 10:59:13.619313 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_SM RESULT=pass
33826 10:59:13.662850 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_ZA RESULT=pass
33828 10:59:13.663338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_ZA RESULT=pass>
33829 10:59:13.700725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32 RESULT=pass>
33830 10:59:13.701176 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32 RESULT=pass
33832 10:59:13.745069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_SM_ZA RESULT=pass>
33833 10:59:13.745494 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_SM_ZA RESULT=pass
33835 10:59:13.788638 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_SM RESULT=pass
33837 10:59:13.789100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_SM RESULT=pass>
33838 10:59:13.832020 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_ZA RESULT=pass
33840 10:59:13.832479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_ZA RESULT=pass>
33841 10:59:13.876172 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_SM_ZA RESULT=pass
33843 10:59:13.876605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_SM_ZA RESULT=pass>
33844 10:59:13.917881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_SM RESULT=pass>
33845 10:59:13.918289 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_SM RESULT=pass
33847 10:59:13.961131 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_ZA RESULT=pass>
33848 10:59:13.961520 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_ZA RESULT=pass
33850 10:59:14.006278 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_SM_ZA RESULT=pass>
33851 10:59:14.006678 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_SM_ZA RESULT=pass
33853 10:59:14.058999 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_SM RESULT=pass>
33854 10:59:14.059432 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_SM RESULT=pass
33856 10:59:14.111409 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_ZA RESULT=pass
33858 10:59:14.111839 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_ZA RESULT=pass>
33859 10:59:14.169539 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_SM_ZA RESULT=pass
33861 10:59:14.170040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_SM_ZA RESULT=pass>
33862 10:59:14.217246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_SM RESULT=pass>
33863 10:59:14.217662 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_SM RESULT=pass
33865 10:59:14.259222 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_ZA RESULT=pass
33867 10:59:14.259681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_ZA RESULT=pass>
33868 10:59:14.302911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_SM_ZA RESULT=pass>
33869 10:59:14.303331 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_SM_ZA RESULT=pass
33871 10:59:14.359116 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_SM RESULT=pass>
33872 10:59:14.359540 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_SM RESULT=pass
33874 10:59:14.410768 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_ZA RESULT=pass
33876 10:59:14.411138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_ZA RESULT=pass>
33877 10:59:14.449203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16 RESULT=pass>
33878 10:59:14.449629 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16 RESULT=pass
33880 10:59:14.501785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_SM_ZA RESULT=pass>
33881 10:59:14.502201 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_SM_ZA RESULT=pass
33883 10:59:14.554230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_SM RESULT=pass>
33884 10:59:14.554655 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_SM RESULT=pass
33886 10:59:14.602871 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_ZA RESULT=pass>
33887 10:59:14.603286 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_ZA RESULT=pass
33889 10:59:14.649667 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_SM_ZA RESULT=pass>
33890 10:59:14.650081 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_SM_ZA RESULT=pass
33892 10:59:14.697075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_SM RESULT=pass>
33893 10:59:14.697515 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_SM RESULT=pass
33895 10:59:14.743383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_ZA RESULT=pass>
33896 10:59:14.743772 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_ZA RESULT=pass
33898 10:59:14.790196 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_SM_ZA RESULT=pass
33900 10:59:14.790621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_SM_ZA RESULT=pass>
33901 10:59:14.837007 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_SM RESULT=pass
33903 10:59:14.837451 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_SM RESULT=pass>
33904 10:59:14.883133 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_ZA RESULT=pass>
33905 10:59:14.883528 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_ZA RESULT=pass
33907 10:59:14.929928 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_SM_ZA RESULT=pass>
33908 10:59:14.930339 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_SM_ZA RESULT=pass
33910 10:59:14.978585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_SM RESULT=pass>
33911 10:59:14.979012 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_SM RESULT=pass
33913 10:59:15.025998 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_ZA RESULT=pass>
33914 10:59:15.026399 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_ZA RESULT=pass
33916 10:59:15.073287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_SM_ZA RESULT=pass>
33917 10:59:15.073688 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_SM_ZA RESULT=pass
33919 10:59:15.121839 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_SM RESULT=pass
33921 10:59:15.122321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_SM RESULT=pass>
33922 10:59:15.168564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_ZA RESULT=pass>
33923 10:59:15.168985 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_ZA RESULT=pass
33925 10:59:15.214086 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_FPSIMD RESULT=pass>
33926 10:59:15.214490 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_FPSIMD RESULT=pass
33928 10:59:15.260462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256 RESULT=pass>
33929 10:59:15.260873 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256 RESULT=pass
33931 10:59:15.306771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_SM_ZA RESULT=pass>
33932 10:59:15.307177 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_SM_ZA RESULT=pass
33934 10:59:15.353582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_SM RESULT=pass>
33935 10:59:15.353979 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_SM RESULT=pass
33937 10:59:15.400023 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_ZA RESULT=pass
33939 10:59:15.400462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_ZA RESULT=pass>
33940 10:59:15.446420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_SM_ZA RESULT=pass>
33941 10:59:15.446796 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_SM_ZA RESULT=pass
33943 10:59:15.493620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_SM RESULT=pass>
33944 10:59:15.493967 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_SM RESULT=pass
33946 10:59:15.541281 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_ZA RESULT=pass
33948 10:59:15.541706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_ZA RESULT=pass>
33949 10:59:15.588577 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_SM_ZA RESULT=pass>
33950 10:59:15.589010 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_SM_ZA RESULT=pass
33952 10:59:15.634899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_SM RESULT=pass>
33953 10:59:15.635327 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_SM RESULT=pass
33955 10:59:15.683546 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_ZA RESULT=pass>
33956 10:59:15.683992 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_ZA RESULT=pass
33958 10:59:15.734457 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_SM_ZA RESULT=pass
33960 10:59:15.734907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_SM_ZA RESULT=pass>
33961 10:59:15.781992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_SM RESULT=pass>
33962 10:59:15.782383 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_SM RESULT=pass
33964 10:59:15.828800 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_ZA RESULT=pass>
33965 10:59:15.829204 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_ZA RESULT=pass
33967 10:59:15.876670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_SM_ZA RESULT=pass>
33968 10:59:15.877070 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_SM_ZA RESULT=pass
33970 10:59:15.923328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_SM RESULT=pass>
33971 10:59:15.923747 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_SM RESULT=pass
33973 10:59:15.969762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_ZA RESULT=pass>
33974 10:59:15.970194 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_ZA RESULT=pass
33976 10:59:16.016365 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240 RESULT=pass
33978 10:59:16.016851 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240 RESULT=pass>
33979 10:59:16.062491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_SM_ZA RESULT=pass>
33980 10:59:16.062915 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_SM_ZA RESULT=pass
33982 10:59:16.110485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_SM RESULT=pass>
33983 10:59:16.110895 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_SM RESULT=pass
33985 10:59:16.157583 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_ZA RESULT=pass>
33986 10:59:16.157988 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_ZA RESULT=pass
33988 10:59:16.204779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_SM_ZA RESULT=pass>
33989 10:59:16.205198 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_SM_ZA RESULT=pass
33991 10:59:16.251550 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_SM RESULT=pass>
33992 10:59:16.251975 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_SM RESULT=pass
33994 10:59:16.298784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_ZA RESULT=pass>
33995 10:59:16.299211 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_ZA RESULT=pass
33997 10:59:16.346249 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_SM_ZA RESULT=pass>
33998 10:59:16.346645 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_SM_ZA RESULT=pass
34000 10:59:16.393571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_SM RESULT=pass>
34001 10:59:16.393981 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_SM RESULT=pass
34003 10:59:16.431964 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_ZA RESULT=pass
34005 10:59:16.432394 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_ZA RESULT=pass>
34006 10:59:16.465000 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_SM_ZA RESULT=pass
34008 10:59:16.465452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_SM_ZA RESULT=pass>
34009 10:59:16.508157 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_SM RESULT=pass
34011 10:59:16.508611 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_SM RESULT=pass>
34012 10:59:16.552436 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_ZA RESULT=pass>
34013 10:59:16.552848 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_ZA RESULT=pass
34015 10:59:16.596783 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_SM_ZA RESULT=pass>
34016 10:59:16.597201 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_SM_ZA RESULT=pass
34018 10:59:16.629117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_SM RESULT=pass>
34019 10:59:16.629550 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_SM RESULT=pass
34021 10:59:16.671934 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_ZA RESULT=pass
34023 10:59:16.672403 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_ZA RESULT=pass>
34024 10:59:16.714968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224 RESULT=pass>
34025 10:59:16.715374 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224 RESULT=pass
34027 10:59:16.758298 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_SM_ZA RESULT=pass
34029 10:59:16.758666 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_SM_ZA RESULT=pass>
34030 10:59:16.800100 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_SM RESULT=pass
34032 10:59:16.800516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_SM RESULT=pass>
34033 10:59:16.844523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_ZA RESULT=pass>
34034 10:59:16.844937 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_ZA RESULT=pass
34036 10:59:16.887601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_SM_ZA RESULT=pass>
34037 10:59:16.888102 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_SM_ZA RESULT=pass
34039 10:59:16.931227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_SM RESULT=pass>
34040 10:59:16.931648 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_SM RESULT=pass
34042 10:59:16.976388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_ZA RESULT=pass>
34043 10:59:16.976821 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_ZA RESULT=pass
34045 10:59:17.020371 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_SM_ZA RESULT=pass
34047 10:59:17.020810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_SM_ZA RESULT=pass>
34048 10:59:17.063533 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_SM RESULT=pass>
34049 10:59:17.063933 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_SM RESULT=pass
34051 10:59:17.106187 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_ZA RESULT=pass>
34052 10:59:17.106602 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_ZA RESULT=pass
34054 10:59:17.149278 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_SM_ZA RESULT=pass
34056 10:59:17.149725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_SM_ZA RESULT=pass>
34057 10:59:17.192650 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_SM RESULT=pass>
34058 10:59:17.193061 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_SM RESULT=pass
34060 10:59:17.237324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_ZA RESULT=pass>
34061 10:59:17.237760 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_ZA RESULT=pass
34063 10:59:17.282179 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_SM_ZA RESULT=pass>
34064 10:59:17.282579 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_SM_ZA RESULT=pass
34066 10:59:17.325634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_SM RESULT=pass>
34067 10:59:17.326049 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_SM RESULT=pass
34069 10:59:17.369066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_ZA RESULT=pass>
34070 10:59:17.369446 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_ZA RESULT=pass
34072 10:59:17.412020 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208 RESULT=pass
34074 10:59:17.412473 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208 RESULT=pass>
34075 10:59:17.455990 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_SM_ZA RESULT=pass
34077 10:59:17.456467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_SM_ZA RESULT=pass>
34078 10:59:17.500792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_SM RESULT=pass>
34079 10:59:17.501226 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_SM RESULT=pass
34081 10:59:17.544561 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_ZA RESULT=pass
34083 10:59:17.545000 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_ZA RESULT=pass>
34084 10:59:17.587716 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_SM_ZA RESULT=pass
34086 10:59:17.588181 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_SM_ZA RESULT=pass>
34087 10:59:17.635368 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_SM RESULT=pass>
34088 10:59:17.635785 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_SM RESULT=pass
34090 10:59:17.682563 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_ZA RESULT=pass
34092 10:59:17.683019 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_ZA RESULT=pass>
34093 10:59:17.729457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_SM_ZA RESULT=pass>
34094 10:59:17.729897 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_SM_ZA RESULT=pass
34096 10:59:17.775950 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_SM RESULT=pass
34098 10:59:17.776367 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_SM RESULT=pass>
34099 10:59:17.822124 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_ZA RESULT=pass>
34100 10:59:17.822542 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_ZA RESULT=pass
34102 10:59:17.869859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_SM_ZA RESULT=pass>
34103 10:59:17.870339 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_SM_ZA RESULT=pass
34105 10:59:17.917464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_SM RESULT=pass>
34106 10:59:17.917883 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_SM RESULT=pass
34108 10:59:17.964594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_ZA RESULT=pass>
34109 10:59:17.965006 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_ZA RESULT=pass
34111 10:59:18.012632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_SM_ZA RESULT=pass>
34112 10:59:18.013038 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_SM_ZA RESULT=pass
34114 10:59:18.058946 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_SM RESULT=pass>
34115 10:59:18.059351 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_SM RESULT=pass
34117 10:59:18.105821 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_ZA RESULT=pass>
34118 10:59:18.106225 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_ZA RESULT=pass
34120 10:59:18.152837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192 RESULT=pass>
34121 10:59:18.153241 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192 RESULT=pass
34123 10:59:18.198996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_SM_ZA RESULT=pass>
34124 10:59:18.199421 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_SM_ZA RESULT=pass
34126 10:59:18.246003 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_SM RESULT=pass
34128 10:59:18.246448 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_SM RESULT=pass>
34129 10:59:18.293452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_ZA RESULT=pass>
34130 10:59:18.293873 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_ZA RESULT=pass
34132 10:59:18.340250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_SM_ZA RESULT=pass>
34133 10:59:18.340667 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_SM_ZA RESULT=pass
34135 10:59:18.387220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_SM RESULT=pass>
34136 10:59:18.387625 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_SM RESULT=pass
34138 10:59:18.434897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_ZA RESULT=pass>
34139 10:59:18.435260 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_ZA RESULT=pass
34141 10:59:18.482334 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_SM_ZA RESULT=pass
34143 10:59:18.482741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_SM_ZA RESULT=pass>
34144 10:59:18.529615 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_SM RESULT=pass
34146 10:59:18.530032 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_SM RESULT=pass>
34147 10:59:18.577041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_ZA RESULT=pass>
34148 10:59:18.577403 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_ZA RESULT=pass
34150 10:59:18.623598 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_SM_ZA RESULT=pass
34152 10:59:18.624030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_SM_ZA RESULT=pass>
34153 10:59:18.670438 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_SM RESULT=pass
34155 10:59:18.670865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_SM RESULT=pass>
34156 10:59:18.717367 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_ZA RESULT=pass>
34157 10:59:18.717767 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_ZA RESULT=pass
34159 10:59:18.764924 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_SM_ZA RESULT=pass>
34160 10:59:18.765319 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_SM_ZA RESULT=pass
34162 10:59:18.811262 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_SM RESULT=pass>
34163 10:59:18.811680 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_SM RESULT=pass
34165 10:59:18.857575 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_ZA RESULT=pass
34167 10:59:18.858010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_ZA RESULT=pass>
34168 10:59:18.904367 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176 RESULT=pass>
34169 10:59:18.904801 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176 RESULT=pass
34171 10:59:18.950110 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_SM_ZA RESULT=pass>
34172 10:59:18.950477 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_SM_ZA RESULT=pass
34174 10:59:18.997475 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_SM RESULT=pass>
34175 10:59:18.997885 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_SM RESULT=pass
34177 10:59:19.043192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_ZA RESULT=pass>
34178 10:59:19.043612 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_ZA RESULT=pass
34180 10:59:19.089857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_SM_ZA RESULT=pass>
34181 10:59:19.090280 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_SM_ZA RESULT=pass
34183 10:59:19.137034 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_SM RESULT=pass
34185 10:59:19.137523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_SM RESULT=pass>
34186 10:59:19.183244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_ZA RESULT=pass>
34187 10:59:19.183635 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_ZA RESULT=pass
34189 10:59:19.230642 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_SM_ZA RESULT=pass>
34190 10:59:19.231018 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_SM_ZA RESULT=pass
34192 10:59:19.277467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_SM RESULT=pass>
34193 10:59:19.277888 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_SM RESULT=pass
34195 10:59:19.325285 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_ZA RESULT=pass>
34196 10:59:19.325762 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_ZA RESULT=pass
34198 10:59:19.372820 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_SM_ZA RESULT=pass
34200 10:59:19.373318 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_SM_ZA RESULT=pass>
34201 10:59:19.419247 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_SM RESULT=pass>
34202 10:59:19.419621 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_SM RESULT=pass
34204 10:59:19.465983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_ZA RESULT=pass>
34205 10:59:19.466384 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_ZA RESULT=pass
34207 10:59:19.513588 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_SM_ZA RESULT=pass>
34208 10:59:19.514005 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_SM_ZA RESULT=pass
34210 10:59:19.560512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_SM RESULT=pass>
34211 10:59:19.560897 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_SM RESULT=pass
34213 10:59:19.626722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_ZA RESULT=pass>
34214 10:59:19.627125 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_ZA RESULT=pass
34216 10:59:19.678116 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160 RESULT=pass>
34217 10:59:19.678521 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160 RESULT=pass
34219 10:59:19.725307 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_SM_ZA RESULT=pass>
34220 10:59:19.725682 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_SM_ZA RESULT=pass
34222 10:59:19.772668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_SM RESULT=pass>
34223 10:59:19.773064 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_SM RESULT=pass
34225 10:59:19.822794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_ZA RESULT=pass>
34226 10:59:19.823229 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_ZA RESULT=pass
34228 10:59:19.869770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_SM_ZA RESULT=pass>
34229 10:59:19.870180 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_SM_ZA RESULT=pass
34231 10:59:19.919416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_SM RESULT=pass>
34232 10:59:19.919824 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_SM RESULT=pass
34234 10:59:19.968989 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_ZA RESULT=pass>
34235 10:59:19.969397 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_ZA RESULT=pass
34237 10:59:20.016461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_SM_ZA RESULT=pass>
34238 10:59:20.016879 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_SM_ZA RESULT=pass
34240 10:59:20.062951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_SM RESULT=pass>
34241 10:59:20.063382 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_SM RESULT=pass
34243 10:59:20.109978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_ZA RESULT=pass>
34244 10:59:20.110408 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_ZA RESULT=pass
34246 10:59:20.156673 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_SM_ZA RESULT=pass>
34247 10:59:20.157095 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_SM_ZA RESULT=pass
34249 10:59:20.202595 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_SM RESULT=pass
34251 10:59:20.203054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_SM RESULT=pass>
34252 10:59:20.249151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_ZA RESULT=pass>
34253 10:59:20.249567 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_ZA RESULT=pass
34255 10:59:20.296891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_SM_ZA RESULT=pass>
34256 10:59:20.297282 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_SM_ZA RESULT=pass
34258 10:59:20.342943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_SM RESULT=pass>
34259 10:59:20.343368 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_SM RESULT=pass
34261 10:59:20.389608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_ZA RESULT=pass>
34262 10:59:20.390006 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_ZA RESULT=pass
34264 10:59:20.435428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144 RESULT=pass>
34265 10:59:20.435806 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144 RESULT=pass
34267 10:59:20.481620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_SM_ZA RESULT=pass>
34268 10:59:20.482030 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_SM_ZA RESULT=pass
34270 10:59:20.528753 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_SM RESULT=pass>
34271 10:59:20.529163 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_SM RESULT=pass
34273 10:59:20.575104 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_ZA RESULT=pass>
34274 10:59:20.575481 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_ZA RESULT=pass
34276 10:59:20.621532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_SM_ZA RESULT=pass>
34277 10:59:20.621940 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_SM_ZA RESULT=pass
34279 10:59:20.667587 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_SM RESULT=pass>
34280 10:59:20.667988 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_SM RESULT=pass
34282 10:59:20.713844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_ZA RESULT=pass>
34283 10:59:20.714207 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_ZA RESULT=pass
34285 10:59:20.761371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_SM_ZA RESULT=pass>
34286 10:59:20.761825 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_SM_ZA RESULT=pass
34288 10:59:20.807141 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_SM RESULT=pass>
34289 10:59:20.807557 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_SM RESULT=pass
34291 10:59:20.853688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_ZA RESULT=pass>
34292 10:59:20.854082 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_ZA RESULT=pass
34294 10:59:20.900491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_SM_ZA RESULT=pass>
34295 10:59:20.900897 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_SM_ZA RESULT=pass
34297 10:59:20.946075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_SM RESULT=pass>
34298 10:59:20.946488 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_SM RESULT=pass
34300 10:59:20.992859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_ZA RESULT=pass>
34301 10:59:20.993273 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_ZA RESULT=pass
34303 10:59:21.042617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_SM_ZA RESULT=pass>
34304 10:59:21.043014 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_SM_ZA RESULT=pass
34306 10:59:21.090550 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_SM RESULT=pass>
34307 10:59:21.090976 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_SM RESULT=pass
34309 10:59:21.139906 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_ZA RESULT=pass
34311 10:59:21.140405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_ZA RESULT=pass>
34312 10:59:21.188877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128 RESULT=pass>
34313 10:59:21.189263 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128 RESULT=pass
34315 10:59:21.236999 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_SM_ZA RESULT=pass>
34316 10:59:21.237423 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_SM_ZA RESULT=pass
34318 10:59:21.285381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_SM RESULT=pass>
34319 10:59:21.285768 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_SM RESULT=pass
34321 10:59:21.332726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_ZA RESULT=pass>
34322 10:59:21.333155 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_ZA RESULT=pass
34324 10:59:21.382188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_SM_ZA RESULT=pass>
34325 10:59:21.382645 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_SM_ZA RESULT=pass
34327 10:59:21.429446 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_SM RESULT=pass>
34328 10:59:21.429868 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_SM RESULT=pass
34330 10:59:21.477388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_ZA RESULT=pass>
34331 10:59:21.477809 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_ZA RESULT=pass
34333 10:59:21.524489 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_SM_ZA RESULT=pass>
34334 10:59:21.524908 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_SM_ZA RESULT=pass
34336 10:59:21.570962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_SM RESULT=pass>
34337 10:59:21.571408 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_SM RESULT=pass
34339 10:59:21.617311 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_ZA RESULT=pass>
34340 10:59:21.617703 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_ZA RESULT=pass
34342 10:59:21.663237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_SM_ZA RESULT=pass>
34343 10:59:21.663652 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_SM_ZA RESULT=pass
34345 10:59:21.709617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_SM RESULT=pass>
34346 10:59:21.710021 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_SM RESULT=pass
34348 10:59:21.756412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_ZA RESULT=pass>
34349 10:59:21.756832 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_ZA RESULT=pass
34351 10:59:21.802884 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_SM_ZA RESULT=pass>
34352 10:59:21.803294 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_SM_ZA RESULT=pass
34354 10:59:21.849399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_SM RESULT=pass>
34355 10:59:21.849789 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_SM RESULT=pass
34357 10:59:21.895310 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_ZA RESULT=pass>
34358 10:59:21.895708 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_ZA RESULT=pass
34360 10:59:21.941520 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112 RESULT=pass
34362 10:59:21.941949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112 RESULT=pass>
34363 10:59:21.987887 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_SM_ZA RESULT=pass
34365 10:59:21.988283 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_SM_ZA RESULT=pass>
34366 10:59:22.037725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_SM RESULT=pass>
34367 10:59:22.038167 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_SM RESULT=pass
34369 10:59:22.085564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_ZA RESULT=pass>
34370 10:59:22.085996 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_ZA RESULT=pass
34372 10:59:22.132808 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_SM_ZA RESULT=pass>
34373 10:59:22.133166 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_SM_ZA RESULT=pass
34375 10:59:22.179282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_SM RESULT=pass>
34376 10:59:22.179646 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_SM RESULT=pass
34378 10:59:22.226193 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_ZA RESULT=pass
34380 10:59:22.226610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_ZA RESULT=pass>
34381 10:59:22.273535 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_SM_ZA RESULT=pass>
34382 10:59:22.273941 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_SM_ZA RESULT=pass
34384 10:59:22.319849 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_SM RESULT=pass
34386 10:59:22.320280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_SM RESULT=pass>
34387 10:59:22.366303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_ZA RESULT=pass>
34388 10:59:22.366681 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_ZA RESULT=pass
34390 10:59:22.414729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_SM_ZA RESULT=pass>
34391 10:59:22.415165 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_SM_ZA RESULT=pass
34393 10:59:22.465786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_SM RESULT=pass>
34394 10:59:22.466187 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_SM RESULT=pass
34396 10:59:22.518288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_ZA RESULT=pass>
34397 10:59:22.518724 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_ZA RESULT=pass
34399 10:59:22.570952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_SM_ZA RESULT=pass>
34400 10:59:22.571398 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_SM_ZA RESULT=pass
34402 10:59:22.622881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_SM RESULT=pass>
34403 10:59:22.623300 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_SM RESULT=pass
34405 10:59:22.666579 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_ZA RESULT=pass>
34406 10:59:22.667020 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_ZA RESULT=pass
34408 10:59:22.709994 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96 RESULT=pass>
34409 10:59:22.710416 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96 RESULT=pass
34411 10:59:22.753202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_SM_ZA RESULT=pass>
34412 10:59:22.753610 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_SM_ZA RESULT=pass
34414 10:59:22.793490 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_SM RESULT=pass>
34415 10:59:22.793912 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_SM RESULT=pass
34417 10:59:22.837314 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_ZA RESULT=pass>
34418 10:59:22.837696 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_ZA RESULT=pass
34420 10:59:22.881217 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_SM_ZA RESULT=pass>
34421 10:59:22.881645 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_SM_ZA RESULT=pass
34423 10:59:22.924821 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_SM RESULT=pass>
34424 10:59:22.925223 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_SM RESULT=pass
34426 10:59:22.970232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_ZA RESULT=pass>
34427 10:59:22.970675 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_ZA RESULT=pass
34429 10:59:23.013996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_SM_ZA RESULT=pass>
34430 10:59:23.014374 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_SM_ZA RESULT=pass
34432 10:59:23.056846 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_SM RESULT=pass>
34433 10:59:23.057265 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_SM RESULT=pass
34435 10:59:23.099747 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_ZA RESULT=pass
34437 10:59:23.100178 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_ZA RESULT=pass>
34438 10:59:23.142746 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_SM_ZA RESULT=pass>
34439 10:59:23.143149 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_SM_ZA RESULT=pass
34441 10:59:23.185883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_SM RESULT=pass>
34442 10:59:23.186276 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_SM RESULT=pass
34444 10:59:23.228683 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_ZA RESULT=pass>
34445 10:59:23.229107 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_ZA RESULT=pass
34447 10:59:23.270015 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_SM_ZA RESULT=pass
34449 10:59:23.270447 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_SM_ZA RESULT=pass>
34450 10:59:23.301558 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_SM RESULT=pass
34452 10:59:23.302037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_SM RESULT=pass>
34453 10:59:23.344456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_ZA RESULT=pass>
34454 10:59:23.344887 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_ZA RESULT=pass
34456 10:59:23.387457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80 RESULT=pass>
34457 10:59:23.387888 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80 RESULT=pass
34459 10:59:23.431338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_SM_ZA RESULT=pass>
34460 10:59:23.431721 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_SM_ZA RESULT=pass
34462 10:59:23.476925 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_SM RESULT=pass
34464 10:59:23.477373 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_SM RESULT=pass>
34465 10:59:23.521601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_ZA RESULT=pass>
34466 10:59:23.522045 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_ZA RESULT=pass
34468 10:59:23.556267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_SM_ZA RESULT=pass>
34469 10:59:23.556699 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_SM_ZA RESULT=pass
34471 10:59:23.594680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_SM RESULT=pass>
34472 10:59:23.595092 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_SM RESULT=pass
34474 10:59:23.638509 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_ZA RESULT=pass>
34475 10:59:23.638914 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_ZA RESULT=pass
34477 10:59:23.682706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_SM_ZA RESULT=pass>
34478 10:59:23.683117 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_SM_ZA RESULT=pass
34480 10:59:23.727162 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_SM RESULT=pass
34482 10:59:23.727579 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_SM RESULT=pass>
34483 10:59:23.771023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_ZA RESULT=pass>
34484 10:59:23.771444 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_ZA RESULT=pass
34486 10:59:23.814500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_SM_ZA RESULT=pass>
34487 10:59:23.814907 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_SM_ZA RESULT=pass
34489 10:59:23.857925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_SM RESULT=pass>
34490 10:59:23.858332 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_SM RESULT=pass
34492 10:59:23.901929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_ZA RESULT=pass>
34493 10:59:23.902351 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_ZA RESULT=pass
34495 10:59:23.947399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_SM_ZA RESULT=pass>
34496 10:59:23.947825 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_SM_ZA RESULT=pass
34498 10:59:23.991763 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_SM RESULT=pass
34500 10:59:23.992331 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_SM RESULT=pass>
34501 10:59:24.036105 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_ZA RESULT=pass
34503 10:59:24.036548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_ZA RESULT=pass>
34504 10:59:24.073195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64 RESULT=pass>
34505 10:59:24.073623 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64 RESULT=pass
34507 10:59:24.113014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_SM_ZA RESULT=pass>
34508 10:59:24.113449 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_SM_ZA RESULT=pass
34510 10:59:24.151544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_SM RESULT=pass>
34511 10:59:24.151958 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_SM RESULT=pass
34513 10:59:24.194004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_ZA RESULT=pass>
34514 10:59:24.194420 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_ZA RESULT=pass
34516 10:59:24.227454 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_SM_ZA RESULT=pass>
34517 10:59:24.227886 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_SM_ZA RESULT=pass
34519 10:59:24.273580 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_SM RESULT=pass>
34520 10:59:24.274015 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_SM RESULT=pass
34522 10:59:24.319153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_ZA RESULT=pass>
34523 10:59:24.319585 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_ZA RESULT=pass
34525 10:59:24.366121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_SM_ZA RESULT=pass>
34526 10:59:24.366521 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_SM_ZA RESULT=pass
34528 10:59:24.407343 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_SM RESULT=pass>
34529 10:59:24.407777 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_SM RESULT=pass
34531 10:59:24.450005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_ZA RESULT=pass>
34532 10:59:24.450425 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_ZA RESULT=pass
34534 10:59:24.493983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_SM_ZA RESULT=pass>
34535 10:59:24.494394 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_SM_ZA RESULT=pass
34537 10:59:24.534113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_SM RESULT=pass>
34538 10:59:24.534531 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_SM RESULT=pass
34540 10:59:24.573719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_ZA RESULT=pass>
34541 10:59:24.574109 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_ZA RESULT=pass
34543 10:59:24.607869 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_SM_ZA RESULT=pass
34545 10:59:24.608339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_SM_ZA RESULT=pass>
34546 10:59:24.648734 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_SM RESULT=pass>
34547 10:59:24.649172 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_SM RESULT=pass
34549 10:59:24.692872 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_ZA RESULT=pass>
34550 10:59:24.693292 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_ZA RESULT=pass
34552 10:59:24.759053 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48 RESULT=pass
34554 10:59:24.759461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48 RESULT=pass>
34555 10:59:24.803289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_SM_ZA RESULT=pass>
34556 10:59:24.803676 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_SM_ZA RESULT=pass
34558 10:59:24.848508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_SM RESULT=pass>
34559 10:59:24.848915 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_SM RESULT=pass
34561 10:59:24.892294 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_ZA RESULT=pass>
34562 10:59:24.892688 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_ZA RESULT=pass
34564 10:59:24.936597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_SM_ZA RESULT=pass>
34565 10:59:24.937008 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_SM_ZA RESULT=pass
34567 10:59:24.978161 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_SM RESULT=pass>
34568 10:59:24.978601 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_SM RESULT=pass
34570 10:59:25.021505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_ZA RESULT=pass>
34571 10:59:25.021937 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_ZA RESULT=pass
34573 10:59:25.064483 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_SM_ZA RESULT=pass>
34574 10:59:25.064897 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_SM_ZA RESULT=pass
34576 10:59:25.107790 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_SM RESULT=pass
34578 10:59:25.108197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_SM RESULT=pass>
34579 10:59:25.151302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_ZA RESULT=pass>
34580 10:59:25.151697 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_ZA RESULT=pass
34582 10:59:25.194396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_SM_ZA RESULT=pass>
34583 10:59:25.194783 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_SM_ZA RESULT=pass
34585 10:59:25.237818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_SM RESULT=pass>
34586 10:59:25.238213 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_SM RESULT=pass
34588 10:59:25.279618 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_ZA RESULT=pass>
34589 10:59:25.280030 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_ZA RESULT=pass
34591 10:59:25.323740 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_SM_ZA RESULT=pass
34593 10:59:25.324181 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_SM_ZA RESULT=pass>
34594 10:59:25.366593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_SM RESULT=pass>
34595 10:59:25.366959 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_SM RESULT=pass
34597 10:59:25.409455 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_ZA RESULT=pass
34599 10:59:25.409872 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_ZA RESULT=pass>
34600 10:59:25.451897 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32 RESULT=pass
34602 10:59:25.452540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32 RESULT=pass>
34603 10:59:25.494948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_SM_ZA RESULT=pass>
34604 10:59:25.495317 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_SM_ZA RESULT=pass
34606 10:59:25.537879 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_SM RESULT=pass>
34607 10:59:25.538379 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_SM RESULT=pass
34609 10:59:25.580997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_ZA RESULT=pass>
34610 10:59:25.581412 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_ZA RESULT=pass
34612 10:59:25.623966 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_SM_ZA RESULT=pass
34614 10:59:25.624390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_SM_ZA RESULT=pass>
34615 10:59:25.667072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_SM RESULT=pass>
34616 10:59:25.667471 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_SM RESULT=pass
34618 10:59:25.711221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_ZA RESULT=pass>
34619 10:59:25.711608 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_ZA RESULT=pass
34621 10:59:25.754774 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_SM_ZA RESULT=pass
34623 10:59:25.755203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_SM_ZA RESULT=pass>
34624 10:59:25.797928 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_SM RESULT=pass>
34625 10:59:25.798333 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_SM RESULT=pass
34627 10:59:25.841208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_ZA RESULT=pass>
34628 10:59:25.841603 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_ZA RESULT=pass
34630 10:59:25.884535 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_SM_ZA RESULT=pass
34632 10:59:25.884969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_SM_ZA RESULT=pass>
34633 10:59:25.927925 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_SM RESULT=pass
34635 10:59:25.928646 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_SM RESULT=pass>
34636 10:59:25.971810 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_ZA RESULT=pass
34638 10:59:25.972274 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_ZA RESULT=pass>
34639 10:59:26.015983 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_SM_ZA RESULT=pass
34641 10:59:26.016388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_SM_ZA RESULT=pass>
34642 10:59:26.061311 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_SM RESULT=pass>
34643 10:59:26.061688 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_SM RESULT=pass
34645 10:59:26.105166 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_ZA RESULT=pass>
34646 10:59:26.105583 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_ZA RESULT=pass
34648 10:59:26.148484 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16 RESULT=pass>
34649 10:59:26.148896 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16 RESULT=pass
34651 10:59:26.191590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_SM_ZA RESULT=pass>
34652 10:59:26.192085 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_SM_ZA RESULT=pass
34654 10:59:26.235512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_SM RESULT=pass>
34655 10:59:26.235939 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_SM RESULT=pass
34657 10:59:26.278787 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_ZA RESULT=pass>
34658 10:59:26.279203 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_ZA RESULT=pass
34660 10:59:26.322388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_SM_ZA RESULT=pass>
34661 10:59:26.322790 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_SM_ZA RESULT=pass
34663 10:59:26.365781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_SM RESULT=pass>
34664 10:59:26.366204 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_SM RESULT=pass
34666 10:59:26.408777 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_ZA RESULT=pass>
34667 10:59:26.409170 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_ZA RESULT=pass
34669 10:59:26.453121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_SM_ZA RESULT=pass>
34670 10:59:26.453530 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_SM_ZA RESULT=pass
34672 10:59:26.497203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_SM RESULT=pass>
34673 10:59:26.497607 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_SM RESULT=pass
34675 10:59:26.540728 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_ZA RESULT=pass>
34676 10:59:26.541132 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_ZA RESULT=pass
34678 10:59:26.584784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_SM_ZA RESULT=pass>
34679 10:59:26.585188 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_SM_ZA RESULT=pass
34681 10:59:26.629154 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_SM RESULT=pass>
34682 10:59:26.629551 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_SM RESULT=pass
34684 10:59:26.663727 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_ZA RESULT=pass
34686 10:59:26.664163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_ZA RESULT=pass>
34687 10:59:26.709335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_SM_ZA RESULT=pass>
34688 10:59:26.709749 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_SM_ZA RESULT=pass
34690 10:59:26.752878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_SM RESULT=pass>
34691 10:59:26.753295 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_SM RESULT=pass
34693 10:59:26.796746 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_ZA RESULT=pass>
34694 10:59:26.797155 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_ZA RESULT=pass
34696 10:59:26.840400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi RESULT=pass>
34697 10:59:26.840794 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi RESULT=pass
34699 10:59:26.882591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_default_value RESULT=pass>
34700 10:59:26.882991 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_default_value RESULT=pass
34702 10:59:26.925732 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_write_read RESULT=pass>
34703 10:59:26.926167 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_write_read RESULT=pass
34705 10:59:26.968892 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_write_sleep_read RESULT=pass>
34706 10:59:26.969294 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_write_sleep_read RESULT=pass
34708 10:59:27.012352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_write_fork_read RESULT=pass>
34709 10:59:27.012757 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_write_fork_read RESULT=pass
34711 10:59:27.055409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_write_clone_read RESULT=pass>
34712 10:59:27.055809 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_write_clone_read RESULT=pass
34714 10:59:27.099707 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2 RESULT=pass
34716 10:59:27.100192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2 RESULT=pass>
34717 10:59:27.103307 + set +x
34718 10:59:27.103625 <LAVA_SIGNAL_ENDRUN 1_kselftest-arm64_qemu 562531_1.1.3.5>
34719 10:59:27.103915 Received signal: <ENDRUN> 1_kselftest-arm64_qemu 562531_1.1.3.5
34720 10:59:27.104027 Ending use of test pattern.
34721 10:59:27.104121 Ending test lava.1_kselftest-arm64_qemu (562531_1.1.3.5), duration 376.95
34723 10:59:27.108746 ok: lava_test_shell seems to have completed
34724 10:59:27.187246 arm64_btitest: pass
arm64_btitest_bti_c_func_call_using_blr: pass
arm64_btitest_bti_c_func_call_using_br_x0: pass
arm64_btitest_bti_c_func_call_using_br_x16: pass
arm64_btitest_bti_j_func_call_using_blr: pass
arm64_btitest_bti_j_func_call_using_br_x0: pass
arm64_btitest_bti_j_func_call_using_br_x16: pass
arm64_btitest_bti_jc_func_call_using_blr: pass
arm64_btitest_bti_jc_func_call_using_br_x0: pass
arm64_btitest_bti_jc_func_call_using_br_x16: pass
arm64_btitest_bti_none_func_call_using_blr: pass
arm64_btitest_bti_none_func_call_using_br_x0: pass
arm64_btitest_bti_none_func_call_using_br_x16: pass
arm64_btitest_nohint_func_call_using_blr: pass
arm64_btitest_nohint_func_call_using_br_x0: pass
arm64_btitest_nohint_func_call_using_br_x16: pass
arm64_btitest_paciasp_func_call_using_blr: pass
arm64_btitest_paciasp_func_call_using_br_x0: pass
arm64_btitest_paciasp_func_call_using_br_x16: pass
arm64_check_buffer_fill: fail
arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_async_err_mode_and_mmap_memory: pass
arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_async_err_mode_and_mmap_mprotect_memory: pass
arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_sync_err_mode_and_mmap_memory: pass
arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_sync_err_mode_and_mmap_mprotect_memory: pass
arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_async_mode_and_mmap_memory: fail
arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_sync_mode_and_mmap_memory: fail
arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_tag_fault_ignore_and_mmap_memory: pass
arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_async_mode_and_mmap_memory: fail
arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_sync_mode_and_mmap_memory: fail
arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_tag_fault_ignore_mode_and_mmap_memory: pass
arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_async_mode_and_mmap_memory: pass
arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_sync_mode_and_mmap_memory: pass
arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_tag_check_fault_ignore_and_mmap_memory: pass
arm64_check_buffer_fill_Check_initial_tags_with_private_mapping_sync_error_mode_and_mmap_memory: pass
arm64_check_buffer_fill_Check_initial_tags_with_private_mapping_sync_error_mode_and_mmap_mprotect_memory: pass
arm64_check_buffer_fill_Check_initial_tags_with_shared_mapping_sync_error_mode_and_mmap_memory: pass
arm64_check_buffer_fill_Check_initial_tags_with_shared_mapping_sync_error_mode_and_mmap_mprotect_memory: pass
arm64_check_child_memory: fail
arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_imprecise_mode_and_mmap_memory: fail
arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_precise_mode_and_mmap_memory: fail
arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_precise_mode_and_mmap_mprotect_memory: fail
arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_imprecise_mode_and_mmap_memory: fail
arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_precise_mode_and_mmap_memory: fail
arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_precise_mode_and_mmap_mprotect_memory: fail
arm64_check_child_memory_Check_child_file_memory_with_private_mapping_imprecise_mode_and_mmap_memory: fail
arm64_check_child_memory_Check_child_file_memory_with_private_mapping_precise_mode_and_mmap_memory: fail
arm64_check_child_memory_Check_child_file_memory_with_private_mapping_precise_mode_and_mmap_mprotect_memory: fail
arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_imprecise_mode_and_mmap_memory: fail
arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_precise_mode_and_mmap_memory: fail
arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_precise_mode_and_mmap_mprotect_memory: fail
arm64_check_gcr_el1_cswitch: fail
arm64_check_ksm_options: fail
arm64_check_mmap_options: fail
arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_async_error_mode_mmap_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_no_error_mode_mmap_memory_and_tag_check_off: pass
arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_off: pass
arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_async_error_mode_mmap_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_sync_error_mode_mmap_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_clear_PROT_MTE_flags_with_private_mapping_and_sync_error_mode_and_mmap_mprotect_memory: fail
arm64_check_mmap_options_Check_clear_PROT_MTE_flags_with_private_mapping_sync_error_mode_and_mmap_memory: fail
arm64_check_mmap_options_Check_file_memory_with_private_mapping_async_error_mode_mmap_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_file_memory_with_private_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_file_memory_with_private_mapping_no_error_mode_mmap_mprotect_memory_and_tag_check_off: pass
arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_off: pass
arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_file_memory_with_shared_mapping_async_error_mode_mmap_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_file_memory_with_shared_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_file_memory_with_shared_mapping_sync_error_mode_mmap_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_file_memory_with_shared_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on: fail
arm64_check_prctl: pass
arm64_check_prctl_ASYNC: pass
arm64_check_prctl_NONE: pass
arm64_check_prctl_SYNC: pass
arm64_check_prctl_SYNC_ASYNC: pass
arm64_check_prctl_check_basic_read: pass
arm64_check_tags_inclusion: fail
arm64_check_tags_inclusion_Check_all_included_tags_value_with_sync_mode: fail
arm64_check_tags_inclusion_Check_an_included_tag_value_with_sync_mode: fail
arm64_check_tags_inclusion_Check_different_included_tags_value_with_sync_mode: fail
arm64_check_tags_inclusion_Check_none_included_tags_value_with_sync_mode: pass
arm64_check_user_mem: pass
arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16: pass
arm64_fake_sigreturn_bad_magic: pass
arm64_fake_sigreturn_bad_size: pass
arm64_fake_sigreturn_bad_size_for_magic0: pass
arm64_fake_sigreturn_duplicated_fpsimd: pass
arm64_fake_sigreturn_misaligned_sp: pass
arm64_fake_sigreturn_missing_fpsimd: pass
arm64_fake_sigreturn_sme_change_vl: pass
arm64_fake_sigreturn_sve_change_vl: pass
arm64_fp-stress: pass
arm64_fp-stress_FPSIMD-0-0: pass
arm64_fp-stress_SSVE-VL-128-0: pass
arm64_fp-stress_SSVE-VL-16-0: pass
arm64_fp-stress_SSVE-VL-256-0: pass
arm64_fp-stress_SSVE-VL-32-0: pass
arm64_fp-stress_SSVE-VL-64-0: pass
arm64_fp-stress_SVE-VL-112-0: pass
arm64_fp-stress_SVE-VL-128-0: pass
arm64_fp-stress_SVE-VL-144-0: pass
arm64_fp-stress_SVE-VL-16-0: pass
arm64_fp-stress_SVE-VL-160-0: pass
arm64_fp-stress_SVE-VL-176-0: pass
arm64_fp-stress_SVE-VL-192-0: pass
arm64_fp-stress_SVE-VL-208-0: pass
arm64_fp-stress_SVE-VL-224-0: pass
arm64_fp-stress_SVE-VL-240-0: pass
arm64_fp-stress_SVE-VL-256-0: pass
arm64_fp-stress_SVE-VL-32-0: pass
arm64_fp-stress_SVE-VL-48-0: pass
arm64_fp-stress_SVE-VL-64-0: pass
arm64_fp-stress_SVE-VL-80-0: pass
arm64_fp-stress_SVE-VL-96-0: pass
arm64_fp-stress_ZA-VL-128-0: pass
arm64_fp-stress_ZA-VL-16-0: pass
arm64_fp-stress_ZA-VL-256-0: pass
arm64_fp-stress_ZA-VL-32-0: pass
arm64_fp-stress_ZA-VL-64-0: pass
arm64_hwcap: pass
arm64_hwcap_cpuinfo_match_RNG: pass
arm64_hwcap_cpuinfo_match_SME: pass
arm64_hwcap_cpuinfo_match_SVE: pass
arm64_hwcap_cpuinfo_match_SVE2_BF16: pass
arm64_hwcap_cpuinfo_match_SVE2_BITPERM: pass
arm64_hwcap_cpuinfo_match_SVE2_EBF16: pass
arm64_hwcap_cpuinfo_match_SVE2_F32MM: pass
arm64_hwcap_cpuinfo_match_SVE2_F64MM: pass
arm64_hwcap_cpuinfo_match_SVE2_I8MM: pass
arm64_hwcap_cpuinfo_match_SVE2_PMULL: pass
arm64_hwcap_cpuinfo_match_SVE2_SHA3: pass
arm64_hwcap_cpuinfo_match_SVE2_SM4: pass
arm64_hwcap_cpuinfo_match_SVE_2: pass
arm64_hwcap_cpuinfo_match_SVE_AES: pass
arm64_hwcap_sigill_RNG: pass
arm64_hwcap_sigill_SME: pass
arm64_hwcap_sigill_SVE: pass
arm64_hwcap_sigill_SVE2_BF16: pass
arm64_hwcap_sigill_SVE2_BITPERM: pass
arm64_hwcap_sigill_SVE2_EBF16: skip
arm64_hwcap_sigill_SVE2_F32MM: pass
arm64_hwcap_sigill_SVE2_F64MM: pass
arm64_hwcap_sigill_SVE2_I8MM: pass
arm64_hwcap_sigill_SVE2_PMULL: pass
arm64_hwcap_sigill_SVE2_SHA3: pass
arm64_hwcap_sigill_SVE2_SM4: pass
arm64_hwcap_sigill_SVE_2: pass
arm64_hwcap_sigill_SVE_AES: pass
arm64_mangle_pstate_invalid_compat_toggle: pass
arm64_mangle_pstate_invalid_daif_bits: pass
arm64_mangle_pstate_invalid_mode_el1h: pass
arm64_mangle_pstate_invalid_mode_el1t: pass
arm64_mangle_pstate_invalid_mode_el2h: pass
arm64_mangle_pstate_invalid_mode_el2t: pass
arm64_mangle_pstate_invalid_mode_el3h: pass
arm64_mangle_pstate_invalid_mode_el3t: pass
arm64_nobtitest: pass
arm64_nobtitest_bti_c_func_call_using_blr: pass
arm64_nobtitest_bti_c_func_call_using_br_x0: pass
arm64_nobtitest_bti_c_func_call_using_br_x16: pass
arm64_nobtitest_bti_j_func_call_using_blr: pass
arm64_nobtitest_bti_j_func_call_using_br_x0: pass
arm64_nobtitest_bti_j_func_call_using_br_x16: pass
arm64_nobtitest_bti_jc_func_call_using_blr: pass
arm64_nobtitest_bti_jc_func_call_using_br_x0: pass
arm64_nobtitest_bti_jc_func_call_using_br_x16: pass
arm64_nobtitest_bti_none_func_call_using_blr: pass
arm64_nobtitest_bti_none_func_call_using_br_x0: pass
arm64_nobtitest_bti_none_func_call_using_br_x16: pass
arm64_nobtitest_nohint_func_call_using_blr: pass
arm64_nobtitest_nohint_func_call_using_br_x0: pass
arm64_nobtitest_nohint_func_call_using_br_x16: pass
arm64_nobtitest_paciasp_func_call_using_blr: pass
arm64_nobtitest_paciasp_func_call_using_br_x0: pass
arm64_nobtitest_paciasp_func_call_using_br_x16: pass
arm64_pac: pass
arm64_pac_global_context_switch_keep_keys: pass
arm64_pac_global_context_switch_keep_keys_generic: pass
arm64_pac_global_corrupt_pac: pass
arm64_pac_global_exec_changed_keys: pass
arm64_pac_global_pac_instructions_not_nop: pass
arm64_pac_global_pac_instructions_not_nop_generic: pass
arm64_pac_global_single_thread_different_keys: pass
arm64_ptrace: pass
arm64_ptrace_count_tpidrs: pass
arm64_ptrace_read_tpidr_one: pass
arm64_ptrace_tpidr2_read: pass
arm64_ptrace_tpidr2_write: pass
arm64_ptrace_verify_tpidr_one: pass
arm64_ptrace_write_tpidr_one: pass
arm64_ptrace_write_tpidr_only: pass
arm64_run_tags_test_sh: pass
arm64_sme_trap_no_sm: pass
arm64_sme_trap_non_streaming: skip
arm64_sme_trap_za: pass
arm64_sme_vl: pass
arm64_ssve_regs: pass
arm64_sve-probe-vls: pass
arm64_sve-probe-vls_All_vector_lengths_valid: pass
arm64_sve-probe-vls_Enumerated_16_vector_lengths: pass
arm64_sve-ptrace: pass
arm64_sve-ptrace_SVE_FPSIMD_set_via_SVE_0: pass
arm64_sve-ptrace_SVE_SVE_PT_VL_INHERIT_cleared: pass
arm64_sve-ptrace_SVE_SVE_PT_VL_INHERIT_set: pass
arm64_sve-ptrace_SVE_get_fpsimd_gave_same_state: pass
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1008: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1024: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1040: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1056: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1072: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1088: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1104: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1120: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1136: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1152: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1168: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1184: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1200: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1216: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1232: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1248: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1264: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1280: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1296: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1312: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1328: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1344: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1360: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1376: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1392: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1408: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1424: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1440: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1456: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1472: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1488: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1504: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1520: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1536: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1552: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1568: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1584: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1600: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1616: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1632: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1648: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1664: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1680: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1696: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1712: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1728: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1744: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1760: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1776: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1792: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1808: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1824: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1840: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1856: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1872: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1888: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1904: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1920: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1936: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1952: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1968: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1984: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2000: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2016: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2032: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2048: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2064: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2080: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2096: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2112: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2128: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2144: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2160: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2176: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2192: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2208: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2224: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2240: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2256: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2272: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2288: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2304: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2320: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2336: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2352: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2368: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2384: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2400: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2416: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2432: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2448: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2464: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2480: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2496: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2512: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2528: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2544: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2560: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2576: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2592: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2608: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2624: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2640: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2656: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2672: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2688: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2704: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_272: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2720: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2736: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2752: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2768: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2784: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2800: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2816: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2832: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2848: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2864: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_288: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2880: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2896: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2912: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2928: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2944: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2960: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2976: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2992: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3008: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3024: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_304: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3040: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3056: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3072: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3088: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3104: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3120: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3136: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3152: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3168: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3184: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_320: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3200: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3216: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3232: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3248: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3264: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3280: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3296: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3312: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3328: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3344: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_336: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3360: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3376: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3392: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3408: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3424: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3440: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3456: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3472: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3488: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3504: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_352: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3520: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3536: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3552: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3568: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3584: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3600: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3616: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3632: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3648: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3664: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_368: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3680: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3696: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3712: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3728: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3744: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3760: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3776: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3792: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3808: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3824: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_384: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3840: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3856: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3872: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3888: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3904: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3920: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3936: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3952: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3968: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3984: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_400: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4000: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4016: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4032: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4048: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4064: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4080: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4096: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4112: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4128: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4144: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_416: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4160: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4176: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4192: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4208: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4224: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4240: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4256: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4272: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4288: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4304: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_432: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4320: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4336: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4352: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4368: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4384: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4400: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4416: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4432: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4448: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4464: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_448: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4480: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4496: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4512: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4528: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4544: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4560: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4576: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4592: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4608: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4624: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_464: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4640: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4656: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4672: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4688: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4704: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4720: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4736: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4752: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4768: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4784: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_480: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4800: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4816: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4832: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4848: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4864: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4880: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4896: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4912: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4928: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4944: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_496: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4960: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4976: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4992: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5008: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5024: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5040: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5056: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5072: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5088: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5104: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_512: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5120: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5136: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5152: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5168: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5184: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5200: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5216: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5232: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5248: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5264: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_528: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5280: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5296: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5312: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5328: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5344: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5360: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5376: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5392: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5408: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5424: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_544: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5440: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5456: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5472: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5488: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5504: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5520: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5536: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5552: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5568: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5584: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_560: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5600: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5616: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5632: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5648: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5664: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5680: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5696: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5712: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5728: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5744: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_576: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5760: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5776: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5792: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5808: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5824: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5840: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5856: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5872: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5888: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5904: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_592: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5920: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5936: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5952: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5968: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5984: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6000: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6016: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6032: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6048: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6064: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_608: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6080: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6096: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6112: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6128: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6144: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6160: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6176: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6192: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6208: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6224: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_624: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6240: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6256: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6272: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6288: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6304: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6320: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6336: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6352: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6368: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6384: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_640: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6400: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6416: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6432: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6448: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6464: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6480: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6496: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6512: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6528: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6544: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_656: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6560: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6576: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6592: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6608: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6624: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6640: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6656: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6672: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6688: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6704: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_672: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6720: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6736: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6752: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6768: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6784: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6800: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6816: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6832: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6848: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6864: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_688: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6880: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6896: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6912: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6928: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6944: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6960: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6976: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6992: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7008: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7024: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_704: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7040: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7056: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7072: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7088: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7104: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7120: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7136: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7152: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7168: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7184: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_720: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7200: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7216: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7232: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7248: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7264: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7280: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7296: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7312: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7328: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7344: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_736: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7360: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7376: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7392: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7408: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7424: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7440: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7456: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7472: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7488: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7504: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_752: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7520: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7536: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7552: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7568: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7584: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7600: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7616: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7632: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7648: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7664: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_768: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7680: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7696: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7712: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7728: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7744: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7760: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7776: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7792: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7808: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7824: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_784: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7840: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7856: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7872: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7888: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7904: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7920: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7936: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7952: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7968: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7984: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_800: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8000: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8016: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8032: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8048: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8064: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8080: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8096: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8112: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8128: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8144: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_816: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8160: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8176: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8192: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_832: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_848: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_864: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_880: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_896: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_912: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_928: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_944: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_960: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_976: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_992: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1008: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1024: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1040: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1056: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1072: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1088: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1104: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1120: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1136: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1152: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1168: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1184: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1200: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1216: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1232: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1248: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1264: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1280: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1296: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1312: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1328: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1344: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1360: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1376: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1392: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1408: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1424: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1440: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1456: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1472: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1488: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1504: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1520: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1536: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1552: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1568: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1584: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1600: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1616: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1632: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1648: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1664: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1680: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1696: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1712: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1728: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1744: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1760: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1776: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1792: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1808: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1824: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1840: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1856: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1872: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1888: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1904: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1920: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1936: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1952: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1968: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1984: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2000: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2016: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2032: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2048: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2064: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2080: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2096: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2112: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2128: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2144: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2160: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2176: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2192: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2208: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2224: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2240: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2256: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2272: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2288: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2304: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2320: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2336: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2352: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2368: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2384: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2400: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2416: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2432: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2448: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2464: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2480: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2496: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2512: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2528: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2544: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2560: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2576: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2592: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2608: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2624: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2640: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2656: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2672: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2688: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2704: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_272: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2720: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2736: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2752: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2768: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2784: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2800: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2816: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2832: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2848: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2864: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_288: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2880: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2896: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2912: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2928: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2944: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2960: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2976: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2992: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3008: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3024: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_304: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3040: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3056: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3072: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3088: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3104: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3120: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3136: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3152: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3168: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3184: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_320: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3200: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3216: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3232: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3248: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3264: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3280: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3296: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3312: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3328: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3344: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_336: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3360: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3376: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3392: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3408: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3424: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3440: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3456: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3472: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3488: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3504: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_352: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3520: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3536: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3552: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3568: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3584: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3600: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3616: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3632: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3648: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3664: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_368: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3680: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3696: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3712: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3728: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3744: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3760: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3776: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3792: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3808: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3824: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_384: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3840: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3856: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3872: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3888: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3904: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3920: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3936: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3952: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3968: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3984: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_400: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4000: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4016: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4032: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4048: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4064: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4080: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4096: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4112: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4128: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4144: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_416: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4160: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4176: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4192: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4208: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4224: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4240: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4256: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4272: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4288: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4304: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_432: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4320: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4336: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4352: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4368: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4384: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4400: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4416: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4432: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4448: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4464: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_448: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4480: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4496: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4512: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4528: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4544: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4560: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4576: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4592: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4608: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4624: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_464: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4640: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4656: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4672: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4688: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4704: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4720: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4736: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4752: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4768: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4784: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_480: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4800: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4816: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4832: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4848: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4864: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4880: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4896: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4912: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4928: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4944: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_496: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4960: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4976: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4992: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5008: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5024: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5040: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5056: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5072: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5088: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5104: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_512: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5120: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5136: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5152: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5168: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5184: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5200: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5216: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5232: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5248: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5264: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_528: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5280: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5296: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5312: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5328: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5344: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5360: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5376: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5392: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5408: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5424: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_544: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5440: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5456: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5472: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5488: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5504: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5520: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5536: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5552: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5568: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5584: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_560: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5600: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5616: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5632: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5648: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5664: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5680: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5696: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5712: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5728: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5744: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_576: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5760: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5776: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5792: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5808: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5824: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5840: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5856: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5872: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5888: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5904: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_592: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5920: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5936: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5952: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5968: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5984: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6000: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6016: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6032: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6048: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6064: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_608: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6080: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6096: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6112: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6128: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6144: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6160: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6176: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6192: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6208: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6224: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_624: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6240: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6256: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6272: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6288: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6304: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6320: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6336: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6352: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6368: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6384: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_640: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6400: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6416: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6432: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6448: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6464: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6480: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6496: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6512: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6528: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6544: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_656: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6560: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6576: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6592: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6608: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6624: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6640: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6656: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6672: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6688: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6704: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_672: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6720: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6736: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6752: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6768: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6784: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6800: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6816: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6832: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6848: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6864: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_688: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6880: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6896: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6912: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6928: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6944: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6960: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6976: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6992: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7008: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7024: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_704: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7040: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7056: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7072: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7088: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7104: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7120: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7136: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7152: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7168: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7184: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_720: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7200: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7216: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7232: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7248: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7264: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7280: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7296: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7312: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7328: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7344: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_736: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7360: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7376: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7392: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7408: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7424: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7440: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7456: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7472: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7488: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7504: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_752: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7520: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7536: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7552: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7568: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7584: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7600: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7616: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7632: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7648: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7664: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_768: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7680: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7696: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7712: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7728: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7744: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7760: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7776: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7792: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7808: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7824: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_784: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7840: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7856: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7872: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7888: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7904: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7920: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7936: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7952: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7968: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7984: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_800: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8000: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8016: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8032: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8048: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8064: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8080: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8096: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8112: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8128: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8144: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_816: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8160: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8176: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8192: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_832: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_848: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_864: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_880: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_896: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_912: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_928: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_944: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_960: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_976: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_992: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1008: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1024: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1040: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1056: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1072: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1088: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1104: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1120: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1136: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1152: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1168: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1184: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1200: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1216: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1232: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1248: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1264: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1280: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1296: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1312: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1328: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1344: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1360: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1376: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1392: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1408: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1424: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1440: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1456: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1472: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1488: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1504: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1520: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1536: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1552: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1568: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1584: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1600: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1616: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1632: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1648: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1664: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1680: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1696: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1712: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1728: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1744: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1760: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1776: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1792: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1808: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1824: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1840: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1856: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1872: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1888: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1904: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1920: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1936: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1952: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1968: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1984: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2000: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2016: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2032: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2048: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2064: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2080: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2096: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2112: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2128: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2144: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2160: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2176: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2192: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2208: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2224: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2240: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2256: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2272: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2288: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2304: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2320: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2336: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2352: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2368: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2384: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2400: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2416: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2432: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2448: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2464: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2480: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2496: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2512: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2528: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2544: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2560: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2576: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2592: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2608: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2624: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2640: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2656: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2672: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2688: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2704: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_272: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2720: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2736: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2752: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2768: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2784: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2800: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2816: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2832: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2848: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2864: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_288: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2880: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2896: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2912: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2928: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2944: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2960: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2976: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2992: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3008: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3024: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_304: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3040: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3056: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3072: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3088: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3104: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3120: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3136: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3152: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3168: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3184: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_320: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3200: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3216: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3232: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3248: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3264: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3280: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3296: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3312: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3328: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3344: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_336: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3360: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3376: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3392: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3408: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3424: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3440: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3456: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3472: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3488: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3504: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_352: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3520: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3536: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3552: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3568: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3584: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3600: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3616: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3632: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3648: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3664: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_368: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3680: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3696: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3712: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3728: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3744: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3760: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3776: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3792: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3808: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3824: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_384: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3840: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3856: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3872: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3888: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3904: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3920: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3936: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3952: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3968: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3984: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_400: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4000: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4016: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4032: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4048: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4064: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4080: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4096: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4112: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4128: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4144: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_416: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4160: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4176: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4192: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4208: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4224: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4240: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4256: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4272: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4288: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4304: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_432: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4320: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4336: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4352: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4368: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4384: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4400: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4416: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4432: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4448: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4464: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_448: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4480: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4496: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4512: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4528: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4544: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4560: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4576: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4592: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4608: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4624: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_464: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4640: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4656: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4672: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4688: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4704: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4720: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4736: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4752: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4768: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4784: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_480: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4800: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4816: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4832: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4848: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4864: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4880: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4896: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4912: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4928: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4944: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_496: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4960: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4976: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4992: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5008: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5024: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5040: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5056: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5072: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5088: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5104: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_512: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5120: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5136: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5152: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5168: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5184: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5200: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5216: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5232: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5248: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5264: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_528: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5280: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5296: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5312: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5328: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5344: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5360: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5376: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5392: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5408: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5424: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_544: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5440: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5456: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5472: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5488: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5504: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5520: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5536: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5552: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5568: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5584: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_560: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5600: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5616: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5632: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5648: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5664: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5680: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5696: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5712: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5728: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5744: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_576: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5760: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5776: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5792: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5808: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5824: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5840: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5856: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5872: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5888: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5904: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_592: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5920: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5936: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5952: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5968: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5984: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6000: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6016: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6032: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6048: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6064: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_608: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6080: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6096: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6112: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6128: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6144: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6160: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6176: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6192: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6208: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6224: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_624: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6240: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6256: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6272: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6288: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6304: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6320: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6336: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6352: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6368: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6384: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_640: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6400: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6416: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6432: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6448: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6464: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6480: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6496: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6512: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6528: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6544: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_656: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6560: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6576: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6592: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6608: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6624: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6640: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6656: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6672: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6688: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6704: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_672: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6720: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6736: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6752: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6768: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6784: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6800: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6816: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6832: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6848: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6864: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_688: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6880: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6896: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6912: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6928: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6944: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6960: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6976: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6992: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7008: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7024: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_704: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7040: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7056: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7072: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7088: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7104: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7120: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7136: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7152: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7168: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7184: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_720: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7200: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7216: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7232: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7248: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7264: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7280: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7296: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7312: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7328: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7344: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_736: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7360: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7376: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7392: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7408: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7424: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7440: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7456: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7472: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7488: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7504: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_752: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7520: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7536: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7552: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7568: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7584: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7600: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7616: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7632: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7648: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7664: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_768: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7680: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7696: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7712: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7728: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7744: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7760: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7776: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7792: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7808: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7824: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_784: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7840: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7856: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7872: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7888: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7904: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7920: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7936: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7952: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7968: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7984: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_800: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8000: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8016: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8032: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8048: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8064: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8080: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8096: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8112: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8128: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8144: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_816: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8160: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8176: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8192: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_832: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_848: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_864: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_880: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_896: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_912: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_928: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_944: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_960: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_976: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_992: skip
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_112: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_128: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_144: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_16: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_160: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_176: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_192: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_208: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_224: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_240: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_256: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_32: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_48: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_64: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_80: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_96: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_128: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_16: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_256: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_32: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_64: pass
arm64_sve-ptrace_Set_SVE_VL_1008: pass
arm64_sve-ptrace_Set_SVE_VL_1024: pass
arm64_sve-ptrace_Set_SVE_VL_1040: pass
arm64_sve-ptrace_Set_SVE_VL_1056: pass
arm64_sve-ptrace_Set_SVE_VL_1072: pass
arm64_sve-ptrace_Set_SVE_VL_1088: pass
arm64_sve-ptrace_Set_SVE_VL_1104: pass
arm64_sve-ptrace_Set_SVE_VL_112: pass
arm64_sve-ptrace_Set_SVE_VL_1120: pass
arm64_sve-ptrace_Set_SVE_VL_1136: pass
arm64_sve-ptrace_Set_SVE_VL_1152: pass
arm64_sve-ptrace_Set_SVE_VL_1168: pass
arm64_sve-ptrace_Set_SVE_VL_1184: pass
arm64_sve-ptrace_Set_SVE_VL_1200: pass
arm64_sve-ptrace_Set_SVE_VL_1216: pass
arm64_sve-ptrace_Set_SVE_VL_1232: pass
arm64_sve-ptrace_Set_SVE_VL_1248: pass
arm64_sve-ptrace_Set_SVE_VL_1264: pass
arm64_sve-ptrace_Set_SVE_VL_128: pass
arm64_sve-ptrace_Set_SVE_VL_1280: pass
arm64_sve-ptrace_Set_SVE_VL_1296: pass
arm64_sve-ptrace_Set_SVE_VL_1312: pass
arm64_sve-ptrace_Set_SVE_VL_1328: pass
arm64_sve-ptrace_Set_SVE_VL_1344: pass
arm64_sve-ptrace_Set_SVE_VL_1360: pass
arm64_sve-ptrace_Set_SVE_VL_1376: pass
arm64_sve-ptrace_Set_SVE_VL_1392: pass
arm64_sve-ptrace_Set_SVE_VL_1408: pass
arm64_sve-ptrace_Set_SVE_VL_1424: pass
arm64_sve-ptrace_Set_SVE_VL_144: pass
arm64_sve-ptrace_Set_SVE_VL_1440: pass
arm64_sve-ptrace_Set_SVE_VL_1456: pass
arm64_sve-ptrace_Set_SVE_VL_1472: pass
arm64_sve-ptrace_Set_SVE_VL_1488: pass
arm64_sve-ptrace_Set_SVE_VL_1504: pass
arm64_sve-ptrace_Set_SVE_VL_1520: pass
arm64_sve-ptrace_Set_SVE_VL_1536: pass
arm64_sve-ptrace_Set_SVE_VL_1552: pass
arm64_sve-ptrace_Set_SVE_VL_1568: pass
arm64_sve-ptrace_Set_SVE_VL_1584: pass
arm64_sve-ptrace_Set_SVE_VL_16: pass
arm64_sve-ptrace_Set_SVE_VL_160: pass
arm64_sve-ptrace_Set_SVE_VL_1600: pass
arm64_sve-ptrace_Set_SVE_VL_1616: pass
arm64_sve-ptrace_Set_SVE_VL_1632: pass
arm64_sve-ptrace_Set_SVE_VL_1648: pass
arm64_sve-ptrace_Set_SVE_VL_1664: pass
arm64_sve-ptrace_Set_SVE_VL_1680: pass
arm64_sve-ptrace_Set_SVE_VL_1696: pass
arm64_sve-ptrace_Set_SVE_VL_1712: pass
arm64_sve-ptrace_Set_SVE_VL_1728: pass
arm64_sve-ptrace_Set_SVE_VL_1744: pass
arm64_sve-ptrace_Set_SVE_VL_176: pass
arm64_sve-ptrace_Set_SVE_VL_1760: pass
arm64_sve-ptrace_Set_SVE_VL_1776: pass
arm64_sve-ptrace_Set_SVE_VL_1792: pass
arm64_sve-ptrace_Set_SVE_VL_1808: pass
arm64_sve-ptrace_Set_SVE_VL_1824: pass
arm64_sve-ptrace_Set_SVE_VL_1840: pass
arm64_sve-ptrace_Set_SVE_VL_1856: pass
arm64_sve-ptrace_Set_SVE_VL_1872: pass
arm64_sve-ptrace_Set_SVE_VL_1888: pass
arm64_sve-ptrace_Set_SVE_VL_1904: pass
arm64_sve-ptrace_Set_SVE_VL_192: pass
arm64_sve-ptrace_Set_SVE_VL_1920: pass
arm64_sve-ptrace_Set_SVE_VL_1936: pass
arm64_sve-ptrace_Set_SVE_VL_1952: pass
arm64_sve-ptrace_Set_SVE_VL_1968: pass
arm64_sve-ptrace_Set_SVE_VL_1984: pass
arm64_sve-ptrace_Set_SVE_VL_2000: pass
arm64_sve-ptrace_Set_SVE_VL_2016: pass
arm64_sve-ptrace_Set_SVE_VL_2032: pass
arm64_sve-ptrace_Set_SVE_VL_2048: pass
arm64_sve-ptrace_Set_SVE_VL_2064: pass
arm64_sve-ptrace_Set_SVE_VL_208: pass
arm64_sve-ptrace_Set_SVE_VL_2080: pass
arm64_sve-ptrace_Set_SVE_VL_2096: pass
arm64_sve-ptrace_Set_SVE_VL_2112: pass
arm64_sve-ptrace_Set_SVE_VL_2128: pass
arm64_sve-ptrace_Set_SVE_VL_2144: pass
arm64_sve-ptrace_Set_SVE_VL_2160: pass
arm64_sve-ptrace_Set_SVE_VL_2176: pass
arm64_sve-ptrace_Set_SVE_VL_2192: pass
arm64_sve-ptrace_Set_SVE_VL_2208: pass
arm64_sve-ptrace_Set_SVE_VL_2224: pass
arm64_sve-ptrace_Set_SVE_VL_224: pass
arm64_sve-ptrace_Set_SVE_VL_2240: pass
arm64_sve-ptrace_Set_SVE_VL_2256: pass
arm64_sve-ptrace_Set_SVE_VL_2272: pass
arm64_sve-ptrace_Set_SVE_VL_2288: pass
arm64_sve-ptrace_Set_SVE_VL_2304: pass
arm64_sve-ptrace_Set_SVE_VL_2320: pass
arm64_sve-ptrace_Set_SVE_VL_2336: pass
arm64_sve-ptrace_Set_SVE_VL_2352: pass
arm64_sve-ptrace_Set_SVE_VL_2368: pass
arm64_sve-ptrace_Set_SVE_VL_2384: pass
arm64_sve-ptrace_Set_SVE_VL_240: pass
arm64_sve-ptrace_Set_SVE_VL_2400: pass
arm64_sve-ptrace_Set_SVE_VL_2416: pass
arm64_sve-ptrace_Set_SVE_VL_2432: pass
arm64_sve-ptrace_Set_SVE_VL_2448: pass
arm64_sve-ptrace_Set_SVE_VL_2464: pass
arm64_sve-ptrace_Set_SVE_VL_2480: pass
arm64_sve-ptrace_Set_SVE_VL_2496: pass
arm64_sve-ptrace_Set_SVE_VL_2512: pass
arm64_sve-ptrace_Set_SVE_VL_2528: pass
arm64_sve-ptrace_Set_SVE_VL_2544: pass
arm64_sve-ptrace_Set_SVE_VL_256: pass
arm64_sve-ptrace_Set_SVE_VL_2560: pass
arm64_sve-ptrace_Set_SVE_VL_2576: pass
arm64_sve-ptrace_Set_SVE_VL_2592: pass
arm64_sve-ptrace_Set_SVE_VL_2608: pass
arm64_sve-ptrace_Set_SVE_VL_2624: pass
arm64_sve-ptrace_Set_SVE_VL_2640: pass
arm64_sve-ptrace_Set_SVE_VL_2656: pass
arm64_sve-ptrace_Set_SVE_VL_2672: pass
arm64_sve-ptrace_Set_SVE_VL_2688: pass
arm64_sve-ptrace_Set_SVE_VL_2704: pass
arm64_sve-ptrace_Set_SVE_VL_272: pass
arm64_sve-ptrace_Set_SVE_VL_2720: pass
arm64_sve-ptrace_Set_SVE_VL_2736: pass
arm64_sve-ptrace_Set_SVE_VL_2752: pass
arm64_sve-ptrace_Set_SVE_VL_2768: pass
arm64_sve-ptrace_Set_SVE_VL_2784: pass
arm64_sve-ptrace_Set_SVE_VL_2800: pass
arm64_sve-ptrace_Set_SVE_VL_2816: pass
arm64_sve-ptrace_Set_SVE_VL_2832: pass
arm64_sve-ptrace_Set_SVE_VL_2848: pass
arm64_sve-ptrace_Set_SVE_VL_2864: pass
arm64_sve-ptrace_Set_SVE_VL_288: pass
arm64_sve-ptrace_Set_SVE_VL_2880: pass
arm64_sve-ptrace_Set_SVE_VL_2896: pass
arm64_sve-ptrace_Set_SVE_VL_2912: pass
arm64_sve-ptrace_Set_SVE_VL_2928: pass
arm64_sve-ptrace_Set_SVE_VL_2944: pass
arm64_sve-ptrace_Set_SVE_VL_2960: pass
arm64_sve-ptrace_Set_SVE_VL_2976: pass
arm64_sve-ptrace_Set_SVE_VL_2992: pass
arm64_sve-ptrace_Set_SVE_VL_3008: pass
arm64_sve-ptrace_Set_SVE_VL_3024: pass
arm64_sve-ptrace_Set_SVE_VL_304: pass
arm64_sve-ptrace_Set_SVE_VL_3040: pass
arm64_sve-ptrace_Set_SVE_VL_3056: pass
arm64_sve-ptrace_Set_SVE_VL_3072: pass
arm64_sve-ptrace_Set_SVE_VL_3088: pass
arm64_sve-ptrace_Set_SVE_VL_3104: pass
arm64_sve-ptrace_Set_SVE_VL_3120: pass
arm64_sve-ptrace_Set_SVE_VL_3136: pass
arm64_sve-ptrace_Set_SVE_VL_3152: pass
arm64_sve-ptrace_Set_SVE_VL_3168: pass
arm64_sve-ptrace_Set_SVE_VL_3184: pass
arm64_sve-ptrace_Set_SVE_VL_32: pass
arm64_sve-ptrace_Set_SVE_VL_320: pass
arm64_sve-ptrace_Set_SVE_VL_3200: pass
arm64_sve-ptrace_Set_SVE_VL_3216: pass
arm64_sve-ptrace_Set_SVE_VL_3232: pass
arm64_sve-ptrace_Set_SVE_VL_3248: pass
arm64_sve-ptrace_Set_SVE_VL_3264: pass
arm64_sve-ptrace_Set_SVE_VL_3280: pass
arm64_sve-ptrace_Set_SVE_VL_3296: pass
arm64_sve-ptrace_Set_SVE_VL_3312: pass
arm64_sve-ptrace_Set_SVE_VL_3328: pass
arm64_sve-ptrace_Set_SVE_VL_3344: pass
arm64_sve-ptrace_Set_SVE_VL_336: pass
arm64_sve-ptrace_Set_SVE_VL_3360: pass
arm64_sve-ptrace_Set_SVE_VL_3376: pass
arm64_sve-ptrace_Set_SVE_VL_3392: pass
arm64_sve-ptrace_Set_SVE_VL_3408: pass
arm64_sve-ptrace_Set_SVE_VL_3424: pass
arm64_sve-ptrace_Set_SVE_VL_3440: pass
arm64_sve-ptrace_Set_SVE_VL_3456: pass
arm64_sve-ptrace_Set_SVE_VL_3472: pass
arm64_sve-ptrace_Set_SVE_VL_3488: pass
arm64_sve-ptrace_Set_SVE_VL_3504: pass
arm64_sve-ptrace_Set_SVE_VL_352: pass
arm64_sve-ptrace_Set_SVE_VL_3520: pass
arm64_sve-ptrace_Set_SVE_VL_3536: pass
arm64_sve-ptrace_Set_SVE_VL_3552: pass
arm64_sve-ptrace_Set_SVE_VL_3568: pass
arm64_sve-ptrace_Set_SVE_VL_3584: pass
arm64_sve-ptrace_Set_SVE_VL_3600: pass
arm64_sve-ptrace_Set_SVE_VL_3616: pass
arm64_sve-ptrace_Set_SVE_VL_3632: pass
arm64_sve-ptrace_Set_SVE_VL_3648: pass
arm64_sve-ptrace_Set_SVE_VL_3664: pass
arm64_sve-ptrace_Set_SVE_VL_368: pass
arm64_sve-ptrace_Set_SVE_VL_3680: pass
arm64_sve-ptrace_Set_SVE_VL_3696: pass
arm64_sve-ptrace_Set_SVE_VL_3712: pass
arm64_sve-ptrace_Set_SVE_VL_3728: pass
arm64_sve-ptrace_Set_SVE_VL_3744: pass
arm64_sve-ptrace_Set_SVE_VL_3760: pass
arm64_sve-ptrace_Set_SVE_VL_3776: pass
arm64_sve-ptrace_Set_SVE_VL_3792: pass
arm64_sve-ptrace_Set_SVE_VL_3808: pass
arm64_sve-ptrace_Set_SVE_VL_3824: pass
arm64_sve-ptrace_Set_SVE_VL_384: pass
arm64_sve-ptrace_Set_SVE_VL_3840: pass
arm64_sve-ptrace_Set_SVE_VL_3856: pass
arm64_sve-ptrace_Set_SVE_VL_3872: pass
arm64_sve-ptrace_Set_SVE_VL_3888: pass
arm64_sve-ptrace_Set_SVE_VL_3904: pass
arm64_sve-ptrace_Set_SVE_VL_3920: pass
arm64_sve-ptrace_Set_SVE_VL_3936: pass
arm64_sve-ptrace_Set_SVE_VL_3952: pass
arm64_sve-ptrace_Set_SVE_VL_3968: pass
arm64_sve-ptrace_Set_SVE_VL_3984: pass
arm64_sve-ptrace_Set_SVE_VL_400: pass
arm64_sve-ptrace_Set_SVE_VL_4000: pass
arm64_sve-ptrace_Set_SVE_VL_4016: pass
arm64_sve-ptrace_Set_SVE_VL_4032: pass
arm64_sve-ptrace_Set_SVE_VL_4048: pass
arm64_sve-ptrace_Set_SVE_VL_4064: pass
arm64_sve-ptrace_Set_SVE_VL_4080: pass
arm64_sve-ptrace_Set_SVE_VL_4096: pass
arm64_sve-ptrace_Set_SVE_VL_4112: pass
arm64_sve-ptrace_Set_SVE_VL_4128: pass
arm64_sve-ptrace_Set_SVE_VL_4144: pass
arm64_sve-ptrace_Set_SVE_VL_416: pass
arm64_sve-ptrace_Set_SVE_VL_4160: pass
arm64_sve-ptrace_Set_SVE_VL_4176: pass
arm64_sve-ptrace_Set_SVE_VL_4192: pass
arm64_sve-ptrace_Set_SVE_VL_4208: pass
arm64_sve-ptrace_Set_SVE_VL_4224: pass
arm64_sve-ptrace_Set_SVE_VL_4240: pass
arm64_sve-ptrace_Set_SVE_VL_4256: pass
arm64_sve-ptrace_Set_SVE_VL_4272: pass
arm64_sve-ptrace_Set_SVE_VL_4288: pass
arm64_sve-ptrace_Set_SVE_VL_4304: pass
arm64_sve-ptrace_Set_SVE_VL_432: pass
arm64_sve-ptrace_Set_SVE_VL_4320: pass
arm64_sve-ptrace_Set_SVE_VL_4336: pass
arm64_sve-ptrace_Set_SVE_VL_4352: pass
arm64_sve-ptrace_Set_SVE_VL_4368: pass
arm64_sve-ptrace_Set_SVE_VL_4384: pass
arm64_sve-ptrace_Set_SVE_VL_4400: pass
arm64_sve-ptrace_Set_SVE_VL_4416: pass
arm64_sve-ptrace_Set_SVE_VL_4432: pass
arm64_sve-ptrace_Set_SVE_VL_4448: pass
arm64_sve-ptrace_Set_SVE_VL_4464: pass
arm64_sve-ptrace_Set_SVE_VL_448: pass
arm64_sve-ptrace_Set_SVE_VL_4480: pass
arm64_sve-ptrace_Set_SVE_VL_4496: pass
arm64_sve-ptrace_Set_SVE_VL_4512: pass
arm64_sve-ptrace_Set_SVE_VL_4528: pass
arm64_sve-ptrace_Set_SVE_VL_4544: pass
arm64_sve-ptrace_Set_SVE_VL_4560: pass
arm64_sve-ptrace_Set_SVE_VL_4576: pass
arm64_sve-ptrace_Set_SVE_VL_4592: pass
arm64_sve-ptrace_Set_SVE_VL_4608: pass
arm64_sve-ptrace_Set_SVE_VL_4624: pass
arm64_sve-ptrace_Set_SVE_VL_464: pass
arm64_sve-ptrace_Set_SVE_VL_4640: pass
arm64_sve-ptrace_Set_SVE_VL_4656: pass
arm64_sve-ptrace_Set_SVE_VL_4672: pass
arm64_sve-ptrace_Set_SVE_VL_4688: pass
arm64_sve-ptrace_Set_SVE_VL_4704: pass
arm64_sve-ptrace_Set_SVE_VL_4720: pass
arm64_sve-ptrace_Set_SVE_VL_4736: pass
arm64_sve-ptrace_Set_SVE_VL_4752: pass
arm64_sve-ptrace_Set_SVE_VL_4768: pass
arm64_sve-ptrace_Set_SVE_VL_4784: pass
arm64_sve-ptrace_Set_SVE_VL_48: pass
arm64_sve-ptrace_Set_SVE_VL_480: pass
arm64_sve-ptrace_Set_SVE_VL_4800: pass
arm64_sve-ptrace_Set_SVE_VL_4816: pass
arm64_sve-ptrace_Set_SVE_VL_4832: pass
arm64_sve-ptrace_Set_SVE_VL_4848: pass
arm64_sve-ptrace_Set_SVE_VL_4864: pass
arm64_sve-ptrace_Set_SVE_VL_4880: pass
arm64_sve-ptrace_Set_SVE_VL_4896: pass
arm64_sve-ptrace_Set_SVE_VL_4912: pass
arm64_sve-ptrace_Set_SVE_VL_4928: pass
arm64_sve-ptrace_Set_SVE_VL_4944: pass
arm64_sve-ptrace_Set_SVE_VL_496: pass
arm64_sve-ptrace_Set_SVE_VL_4960: pass
arm64_sve-ptrace_Set_SVE_VL_4976: pass
arm64_sve-ptrace_Set_SVE_VL_4992: pass
arm64_sve-ptrace_Set_SVE_VL_5008: pass
arm64_sve-ptrace_Set_SVE_VL_5024: pass
arm64_sve-ptrace_Set_SVE_VL_5040: pass
arm64_sve-ptrace_Set_SVE_VL_5056: pass
arm64_sve-ptrace_Set_SVE_VL_5072: pass
arm64_sve-ptrace_Set_SVE_VL_5088: pass
arm64_sve-ptrace_Set_SVE_VL_5104: pass
arm64_sve-ptrace_Set_SVE_VL_512: pass
arm64_sve-ptrace_Set_SVE_VL_5120: pass
arm64_sve-ptrace_Set_SVE_VL_5136: pass
arm64_sve-ptrace_Set_SVE_VL_5152: pass
arm64_sve-ptrace_Set_SVE_VL_5168: pass
arm64_sve-ptrace_Set_SVE_VL_5184: pass
arm64_sve-ptrace_Set_SVE_VL_5200: pass
arm64_sve-ptrace_Set_SVE_VL_5216: pass
arm64_sve-ptrace_Set_SVE_VL_5232: pass
arm64_sve-ptrace_Set_SVE_VL_5248: pass
arm64_sve-ptrace_Set_SVE_VL_5264: pass
arm64_sve-ptrace_Set_SVE_VL_528: pass
arm64_sve-ptrace_Set_SVE_VL_5280: pass
arm64_sve-ptrace_Set_SVE_VL_5296: pass
arm64_sve-ptrace_Set_SVE_VL_5312: pass
arm64_sve-ptrace_Set_SVE_VL_5328: pass
arm64_sve-ptrace_Set_SVE_VL_5344: pass
arm64_sve-ptrace_Set_SVE_VL_5360: pass
arm64_sve-ptrace_Set_SVE_VL_5376: pass
arm64_sve-ptrace_Set_SVE_VL_5392: pass
arm64_sve-ptrace_Set_SVE_VL_5408: pass
arm64_sve-ptrace_Set_SVE_VL_5424: pass
arm64_sve-ptrace_Set_SVE_VL_544: pass
arm64_sve-ptrace_Set_SVE_VL_5440: pass
arm64_sve-ptrace_Set_SVE_VL_5456: pass
arm64_sve-ptrace_Set_SVE_VL_5472: pass
arm64_sve-ptrace_Set_SVE_VL_5488: pass
arm64_sve-ptrace_Set_SVE_VL_5504: pass
arm64_sve-ptrace_Set_SVE_VL_5520: pass
arm64_sve-ptrace_Set_SVE_VL_5536: pass
arm64_sve-ptrace_Set_SVE_VL_5552: pass
arm64_sve-ptrace_Set_SVE_VL_5568: pass
arm64_sve-ptrace_Set_SVE_VL_5584: pass
arm64_sve-ptrace_Set_SVE_VL_560: pass
arm64_sve-ptrace_Set_SVE_VL_5600: pass
arm64_sve-ptrace_Set_SVE_VL_5616: pass
arm64_sve-ptrace_Set_SVE_VL_5632: pass
arm64_sve-ptrace_Set_SVE_VL_5648: pass
arm64_sve-ptrace_Set_SVE_VL_5664: pass
arm64_sve-ptrace_Set_SVE_VL_5680: pass
arm64_sve-ptrace_Set_SVE_VL_5696: pass
arm64_sve-ptrace_Set_SVE_VL_5712: pass
arm64_sve-ptrace_Set_SVE_VL_5728: pass
arm64_sve-ptrace_Set_SVE_VL_5744: pass
arm64_sve-ptrace_Set_SVE_VL_576: pass
arm64_sve-ptrace_Set_SVE_VL_5760: pass
arm64_sve-ptrace_Set_SVE_VL_5776: pass
arm64_sve-ptrace_Set_SVE_VL_5792: pass
arm64_sve-ptrace_Set_SVE_VL_5808: pass
arm64_sve-ptrace_Set_SVE_VL_5824: pass
arm64_sve-ptrace_Set_SVE_VL_5840: pass
arm64_sve-ptrace_Set_SVE_VL_5856: pass
arm64_sve-ptrace_Set_SVE_VL_5872: pass
arm64_sve-ptrace_Set_SVE_VL_5888: pass
arm64_sve-ptrace_Set_SVE_VL_5904: pass
arm64_sve-ptrace_Set_SVE_VL_592: pass
arm64_sve-ptrace_Set_SVE_VL_5920: pass
arm64_sve-ptrace_Set_SVE_VL_5936: pass
arm64_sve-ptrace_Set_SVE_VL_5952: pass
arm64_sve-ptrace_Set_SVE_VL_5968: pass
arm64_sve-ptrace_Set_SVE_VL_5984: pass
arm64_sve-ptrace_Set_SVE_VL_6000: pass
arm64_sve-ptrace_Set_SVE_VL_6016: pass
arm64_sve-ptrace_Set_SVE_VL_6032: pass
arm64_sve-ptrace_Set_SVE_VL_6048: pass
arm64_sve-ptrace_Set_SVE_VL_6064: pass
arm64_sve-ptrace_Set_SVE_VL_608: pass
arm64_sve-ptrace_Set_SVE_VL_6080: pass
arm64_sve-ptrace_Set_SVE_VL_6096: pass
arm64_sve-ptrace_Set_SVE_VL_6112: pass
arm64_sve-ptrace_Set_SVE_VL_6128: pass
arm64_sve-ptrace_Set_SVE_VL_6144: pass
arm64_sve-ptrace_Set_SVE_VL_6160: pass
arm64_sve-ptrace_Set_SVE_VL_6176: pass
arm64_sve-ptrace_Set_SVE_VL_6192: pass
arm64_sve-ptrace_Set_SVE_VL_6208: pass
arm64_sve-ptrace_Set_SVE_VL_6224: pass
arm64_sve-ptrace_Set_SVE_VL_624: pass
arm64_sve-ptrace_Set_SVE_VL_6240: pass
arm64_sve-ptrace_Set_SVE_VL_6256: pass
arm64_sve-ptrace_Set_SVE_VL_6272: pass
arm64_sve-ptrace_Set_SVE_VL_6288: pass
arm64_sve-ptrace_Set_SVE_VL_6304: pass
arm64_sve-ptrace_Set_SVE_VL_6320: pass
arm64_sve-ptrace_Set_SVE_VL_6336: pass
arm64_sve-ptrace_Set_SVE_VL_6352: pass
arm64_sve-ptrace_Set_SVE_VL_6368: pass
arm64_sve-ptrace_Set_SVE_VL_6384: pass
arm64_sve-ptrace_Set_SVE_VL_64: pass
arm64_sve-ptrace_Set_SVE_VL_640: pass
arm64_sve-ptrace_Set_SVE_VL_6400: pass
arm64_sve-ptrace_Set_SVE_VL_6416: pass
arm64_sve-ptrace_Set_SVE_VL_6432: pass
arm64_sve-ptrace_Set_SVE_VL_6448: pass
arm64_sve-ptrace_Set_SVE_VL_6464: pass
arm64_sve-ptrace_Set_SVE_VL_6480: pass
arm64_sve-ptrace_Set_SVE_VL_6496: pass
arm64_sve-ptrace_Set_SVE_VL_6512: pass
arm64_sve-ptrace_Set_SVE_VL_6528: pass
arm64_sve-ptrace_Set_SVE_VL_6544: pass
arm64_sve-ptrace_Set_SVE_VL_656: pass
arm64_sve-ptrace_Set_SVE_VL_6560: pass
arm64_sve-ptrace_Set_SVE_VL_6576: pass
arm64_sve-ptrace_Set_SVE_VL_6592: pass
arm64_sve-ptrace_Set_SVE_VL_6608: pass
arm64_sve-ptrace_Set_SVE_VL_6624: pass
arm64_sve-ptrace_Set_SVE_VL_6640: pass
arm64_sve-ptrace_Set_SVE_VL_6656: pass
arm64_sve-ptrace_Set_SVE_VL_6672: pass
arm64_sve-ptrace_Set_SVE_VL_6688: pass
arm64_sve-ptrace_Set_SVE_VL_6704: pass
arm64_sve-ptrace_Set_SVE_VL_672: pass
arm64_sve-ptrace_Set_SVE_VL_6720: pass
arm64_sve-ptrace_Set_SVE_VL_6736: pass
arm64_sve-ptrace_Set_SVE_VL_6752: pass
arm64_sve-ptrace_Set_SVE_VL_6768: pass
arm64_sve-ptrace_Set_SVE_VL_6784: pass
arm64_sve-ptrace_Set_SVE_VL_6800: pass
arm64_sve-ptrace_Set_SVE_VL_6816: pass
arm64_sve-ptrace_Set_SVE_VL_6832: pass
arm64_sve-ptrace_Set_SVE_VL_6848: pass
arm64_sve-ptrace_Set_SVE_VL_6864: pass
arm64_sve-ptrace_Set_SVE_VL_688: pass
arm64_sve-ptrace_Set_SVE_VL_6880: pass
arm64_sve-ptrace_Set_SVE_VL_6896: pass
arm64_sve-ptrace_Set_SVE_VL_6912: pass
arm64_sve-ptrace_Set_SVE_VL_6928: pass
arm64_sve-ptrace_Set_SVE_VL_6944: pass
arm64_sve-ptrace_Set_SVE_VL_6960: pass
arm64_sve-ptrace_Set_SVE_VL_6976: pass
arm64_sve-ptrace_Set_SVE_VL_6992: pass
arm64_sve-ptrace_Set_SVE_VL_7008: pass
arm64_sve-ptrace_Set_SVE_VL_7024: pass
arm64_sve-ptrace_Set_SVE_VL_704: pass
arm64_sve-ptrace_Set_SVE_VL_7040: pass
arm64_sve-ptrace_Set_SVE_VL_7056: pass
arm64_sve-ptrace_Set_SVE_VL_7072: pass
arm64_sve-ptrace_Set_SVE_VL_7088: pass
arm64_sve-ptrace_Set_SVE_VL_7104: pass
arm64_sve-ptrace_Set_SVE_VL_7120: pass
arm64_sve-ptrace_Set_SVE_VL_7136: pass
arm64_sve-ptrace_Set_SVE_VL_7152: pass
arm64_sve-ptrace_Set_SVE_VL_7168: pass
arm64_sve-ptrace_Set_SVE_VL_7184: pass
arm64_sve-ptrace_Set_SVE_VL_720: pass
arm64_sve-ptrace_Set_SVE_VL_7200: pass
arm64_sve-ptrace_Set_SVE_VL_7216: pass
arm64_sve-ptrace_Set_SVE_VL_7232: pass
arm64_sve-ptrace_Set_SVE_VL_7248: pass
arm64_sve-ptrace_Set_SVE_VL_7264: pass
arm64_sve-ptrace_Set_SVE_VL_7280: pass
arm64_sve-ptrace_Set_SVE_VL_7296: pass
arm64_sve-ptrace_Set_SVE_VL_7312: pass
arm64_sve-ptrace_Set_SVE_VL_7328: pass
arm64_sve-ptrace_Set_SVE_VL_7344: pass
arm64_sve-ptrace_Set_SVE_VL_736: pass
arm64_sve-ptrace_Set_SVE_VL_7360: pass
arm64_sve-ptrace_Set_SVE_VL_7376: pass
arm64_sve-ptrace_Set_SVE_VL_7392: pass
arm64_sve-ptrace_Set_SVE_VL_7408: pass
arm64_sve-ptrace_Set_SVE_VL_7424: pass
arm64_sve-ptrace_Set_SVE_VL_7440: pass
arm64_sve-ptrace_Set_SVE_VL_7456: pass
arm64_sve-ptrace_Set_SVE_VL_7472: pass
arm64_sve-ptrace_Set_SVE_VL_7488: pass
arm64_sve-ptrace_Set_SVE_VL_7504: pass
arm64_sve-ptrace_Set_SVE_VL_752: pass
arm64_sve-ptrace_Set_SVE_VL_7520: pass
arm64_sve-ptrace_Set_SVE_VL_7536: pass
arm64_sve-ptrace_Set_SVE_VL_7552: pass
arm64_sve-ptrace_Set_SVE_VL_7568: pass
arm64_sve-ptrace_Set_SVE_VL_7584: pass
arm64_sve-ptrace_Set_SVE_VL_7600: pass
arm64_sve-ptrace_Set_SVE_VL_7616: pass
arm64_sve-ptrace_Set_SVE_VL_7632: pass
arm64_sve-ptrace_Set_SVE_VL_7648: pass
arm64_sve-ptrace_Set_SVE_VL_7664: pass
arm64_sve-ptrace_Set_SVE_VL_768: pass
arm64_sve-ptrace_Set_SVE_VL_7680: pass
arm64_sve-ptrace_Set_SVE_VL_7696: pass
arm64_sve-ptrace_Set_SVE_VL_7712: pass
arm64_sve-ptrace_Set_SVE_VL_7728: pass
arm64_sve-ptrace_Set_SVE_VL_7744: pass
arm64_sve-ptrace_Set_SVE_VL_7760: pass
arm64_sve-ptrace_Set_SVE_VL_7776: pass
arm64_sve-ptrace_Set_SVE_VL_7792: pass
arm64_sve-ptrace_Set_SVE_VL_7808: pass
arm64_sve-ptrace_Set_SVE_VL_7824: pass
arm64_sve-ptrace_Set_SVE_VL_784: pass
arm64_sve-ptrace_Set_SVE_VL_7840: pass
arm64_sve-ptrace_Set_SVE_VL_7856: pass
arm64_sve-ptrace_Set_SVE_VL_7872: pass
arm64_sve-ptrace_Set_SVE_VL_7888: pass
arm64_sve-ptrace_Set_SVE_VL_7904: pass
arm64_sve-ptrace_Set_SVE_VL_7920: pass
arm64_sve-ptrace_Set_SVE_VL_7936: pass
arm64_sve-ptrace_Set_SVE_VL_7952: pass
arm64_sve-ptrace_Set_SVE_VL_7968: pass
arm64_sve-ptrace_Set_SVE_VL_7984: pass
arm64_sve-ptrace_Set_SVE_VL_80: pass
arm64_sve-ptrace_Set_SVE_VL_800: pass
arm64_sve-ptrace_Set_SVE_VL_8000: pass
arm64_sve-ptrace_Set_SVE_VL_8016: pass
arm64_sve-ptrace_Set_SVE_VL_8032: pass
arm64_sve-ptrace_Set_SVE_VL_8048: pass
arm64_sve-ptrace_Set_SVE_VL_8064: pass
arm64_sve-ptrace_Set_SVE_VL_8080: pass
arm64_sve-ptrace_Set_SVE_VL_8096: pass
arm64_sve-ptrace_Set_SVE_VL_8112: pass
arm64_sve-ptrace_Set_SVE_VL_8128: pass
arm64_sve-ptrace_Set_SVE_VL_8144: pass
arm64_sve-ptrace_Set_SVE_VL_816: pass
arm64_sve-ptrace_Set_SVE_VL_8160: pass
arm64_sve-ptrace_Set_SVE_VL_8176: pass
arm64_sve-ptrace_Set_SVE_VL_8192: pass
arm64_sve-ptrace_Set_SVE_VL_832: pass
arm64_sve-ptrace_Set_SVE_VL_848: pass
arm64_sve-ptrace_Set_SVE_VL_864: pass
arm64_sve-ptrace_Set_SVE_VL_880: pass
arm64_sve-ptrace_Set_SVE_VL_896: pass
arm64_sve-ptrace_Set_SVE_VL_912: pass
arm64_sve-ptrace_Set_SVE_VL_928: pass
arm64_sve-ptrace_Set_SVE_VL_944: pass
arm64_sve-ptrace_Set_SVE_VL_96: pass
arm64_sve-ptrace_Set_SVE_VL_960: pass
arm64_sve-ptrace_Set_SVE_VL_976: pass
arm64_sve-ptrace_Set_SVE_VL_992: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1008: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1024: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1040: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1056: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1072: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1088: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1104: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_112: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1120: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1136: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1152: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1168: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1184: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1200: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1216: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1232: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1248: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1264: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_128: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1280: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1296: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1312: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1328: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1344: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1360: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1376: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1392: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1408: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1424: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_144: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1440: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1456: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1472: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1488: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1504: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1520: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1536: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1552: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1568: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1584: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_16: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_160: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1600: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1616: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1632: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1648: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1664: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1680: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1696: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1712: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1728: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1744: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_176: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1760: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1776: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1792: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1808: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1824: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1840: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1856: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1872: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1888: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1904: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_192: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1920: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1936: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1952: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1968: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1984: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2000: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2016: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2032: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2048: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2064: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_208: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2080: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2096: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2112: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2128: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2144: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2160: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2176: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2192: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2208: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2224: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_224: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2240: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2256: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2272: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2288: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2304: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2320: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2336: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2352: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2368: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2384: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_240: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2400: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2416: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2432: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2448: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2464: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2480: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2496: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2512: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2528: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2544: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_256: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2560: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2576: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2592: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2608: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2624: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2640: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2656: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2672: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2688: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2704: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_272: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2720: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2736: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2752: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2768: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2784: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2800: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2816: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2832: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2848: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2864: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_288: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2880: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2896: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2912: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2928: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2944: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2960: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2976: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2992: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3008: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3024: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_304: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3040: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3056: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3072: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3088: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3104: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3120: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3136: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3152: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3168: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3184: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_32: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_320: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3200: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3216: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3232: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3248: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3264: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3280: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3296: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3312: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3328: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3344: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_336: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3360: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3376: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3392: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3408: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3424: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3440: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3456: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3472: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3488: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3504: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_352: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3520: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3536: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3552: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3568: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3584: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3600: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3616: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3632: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3648: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3664: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_368: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3680: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3696: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3712: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3728: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3744: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3760: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3776: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3792: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3808: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3824: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_384: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3840: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3856: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3872: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3888: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3904: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3920: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3936: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3952: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3968: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3984: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_400: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4000: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4016: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4032: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4048: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4064: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4080: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4096: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4112: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4128: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4144: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_416: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4160: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4176: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4192: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4208: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4224: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4240: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4256: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4272: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4288: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4304: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_432: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4320: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4336: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4352: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4368: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4384: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4400: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4416: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4432: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4448: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4464: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_448: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4480: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4496: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4512: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4528: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4544: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4560: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4576: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4592: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4608: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4624: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_464: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4640: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4656: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4672: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4688: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4704: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4720: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4736: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4752: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4768: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4784: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_48: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_480: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4800: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4816: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4832: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4848: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4864: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4880: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4896: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4912: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4928: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4944: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_496: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4960: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4976: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4992: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5008: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5024: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5040: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5056: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5072: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5088: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5104: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_512: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5120: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5136: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5152: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5168: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5184: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5200: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5216: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5232: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5248: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5264: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_528: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5280: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5296: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5312: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5328: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5344: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5360: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5376: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5392: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5408: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5424: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_544: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5440: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5456: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5472: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5488: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5504: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5520: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5536: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5552: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5568: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5584: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_560: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5600: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5616: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5632: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5648: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5664: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5680: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5696: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5712: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5728: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5744: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_576: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5760: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5776: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5792: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5808: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5824: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5840: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5856: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5872: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5888: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5904: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_592: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5920: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5936: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5952: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5968: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5984: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6000: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6016: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6032: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6048: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6064: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_608: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6080: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6096: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6112: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6128: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6144: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6160: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6176: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6192: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6208: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6224: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_624: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6240: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6256: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6272: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6288: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6304: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6320: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6336: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6352: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6368: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6384: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_64: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_640: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6400: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6416: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6432: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6448: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6464: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6480: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6496: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6512: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6528: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6544: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_656: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6560: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6576: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6592: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6608: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6624: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6640: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6656: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6672: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6688: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6704: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_672: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6720: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6736: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6752: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6768: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6784: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6800: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6816: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6832: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6848: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6864: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_688: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6880: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6896: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6912: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6928: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6944: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6960: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6976: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6992: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7008: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7024: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_704: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7040: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7056: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7072: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7088: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7104: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7120: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7136: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7152: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7168: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7184: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_720: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7200: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7216: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7232: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7248: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7264: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7280: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7296: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7312: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7328: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7344: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_736: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7360: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7376: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7392: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7408: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7424: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7440: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7456: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7472: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7488: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7504: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_752: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7520: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7536: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7552: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7568: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7584: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7600: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7616: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7632: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7648: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7664: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_768: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7680: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7696: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7712: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7728: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7744: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7760: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7776: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7792: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7808: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7824: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_784: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7840: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7856: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7872: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7888: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7904: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7920: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7936: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7952: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7968: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7984: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_80: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_800: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8000: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8016: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8032: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8048: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8064: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8080: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8096: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8112: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8128: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8144: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_816: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8160: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8176: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8192: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_832: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_848: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_864: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_880: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_896: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_912: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_928: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_944: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_96: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_960: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_976: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_992: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_112: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_128: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_144: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_16: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_160: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_176: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_192: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_208: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_224: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_240: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_256: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_32: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_48: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_64: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_80: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_96: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_128: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_16: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_256: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_32: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_64: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_112: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_128: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_144: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_16: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_160: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_176: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_192: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_208: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_224: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_240: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_256: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_32: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_48: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_64: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_80: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_96: pass
arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_128: pass
arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_16: pass
arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_256: pass
arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_32: pass
arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_64: pass
arm64_sve-ptrace_Streaming_SVE_FPSIMD_set_via_SVE_0: pass
arm64_sve-ptrace_Streaming_SVE_SVE_PT_VL_INHERIT_cleared: pass
arm64_sve-ptrace_Streaming_SVE_SVE_PT_VL_INHERIT_set: pass
arm64_sve-ptrace_Streaming_SVE_get_fpsimd_gave_same_state: pass
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1008: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1024: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1040: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1056: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1072: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1088: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1104: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_112: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1120: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1136: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1152: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1168: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1184: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1200: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1216: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1232: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1248: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1264: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1280: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1296: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1312: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1328: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1344: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1360: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1376: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1392: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1408: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1424: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_144: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1440: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1456: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1472: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1488: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1504: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1520: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1536: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1552: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1568: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1584: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_160: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1600: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1616: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1632: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1648: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1664: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1680: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1696: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1712: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1728: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1744: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_176: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1760: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1776: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1792: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1808: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1824: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1840: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1856: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1872: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1888: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1904: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_192: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1920: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1936: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1952: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1968: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1984: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2000: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2016: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2032: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2048: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2064: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_208: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2080: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2096: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2112: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2128: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2144: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2160: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2176: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2192: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2208: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2224: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_224: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2240: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2256: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2272: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2288: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2304: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2320: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2336: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2352: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2368: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2384: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_240: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2400: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2416: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2432: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2448: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2464: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2480: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2496: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2512: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2528: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2544: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2560: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2576: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2592: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2608: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2624: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2640: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2656: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2672: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2688: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2704: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_272: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2720: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2736: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2752: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2768: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2784: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2800: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2816: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2832: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2848: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2864: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_288: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2880: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2896: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2912: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2928: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2944: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2960: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2976: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2992: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3008: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3024: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_304: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3040: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3056: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3072: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3088: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3104: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3120: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3136: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3152: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3168: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3184: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_320: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3200: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3216: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3232: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3248: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3264: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3280: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3296: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3312: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3328: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3344: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_336: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3360: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3376: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3392: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3408: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3424: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3440: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3456: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3472: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3488: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3504: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_352: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3520: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3536: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3552: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3568: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3584: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3600: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3616: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3632: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3648: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3664: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_368: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3680: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3696: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3712: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3728: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3744: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3760: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3776: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3792: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3808: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3824: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_384: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3840: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3856: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3872: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3888: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3904: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3920: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3936: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3952: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3968: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3984: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_400: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4000: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4016: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4032: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4048: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4064: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4080: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4096: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4112: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4128: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4144: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_416: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4160: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4176: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4192: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4208: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4224: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4240: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4256: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4272: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4288: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4304: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_432: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4320: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4336: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4352: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4368: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4384: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4400: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4416: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4432: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4448: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4464: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_448: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4480: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4496: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4512: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4528: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4544: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4560: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4576: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4592: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4608: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4624: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_464: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4640: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4656: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4672: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4688: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4704: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4720: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4736: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4752: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4768: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4784: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_48: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_480: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4800: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4816: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4832: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4848: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4864: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4880: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4896: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4912: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4928: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4944: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_496: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4960: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4976: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4992: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5008: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5024: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5040: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5056: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5072: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5088: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5104: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_512: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5120: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5136: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5152: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5168: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5184: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5200: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5216: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5232: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5248: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5264: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_528: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5280: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5296: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5312: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5328: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5344: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5360: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5376: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5392: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5408: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5424: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_544: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5440: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5456: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5472: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5488: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5504: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5520: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5536: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5552: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5568: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5584: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_560: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5600: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5616: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5632: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5648: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5664: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5680: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5696: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5712: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5728: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5744: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_576: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5760: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5776: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5792: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5808: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5824: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5840: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5856: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5872: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5888: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5904: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_592: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5920: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5936: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5952: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5968: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5984: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6000: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6016: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6032: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6048: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6064: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_608: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6080: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6096: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6112: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6128: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6144: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6160: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6176: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6192: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6208: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6224: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_624: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6240: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6256: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6272: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6288: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6304: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6320: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6336: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6352: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6368: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6384: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_640: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6400: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6416: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6432: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6448: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6464: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6480: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6496: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6512: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6528: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6544: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_656: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6560: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6576: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6592: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6608: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6624: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6640: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6656: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6672: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6688: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6704: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_672: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6720: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6736: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6752: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6768: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6784: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6800: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6816: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6832: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6848: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6864: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_688: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6880: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6896: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6912: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6928: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6944: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6960: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6976: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6992: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7008: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7024: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_704: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7040: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7056: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7072: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7088: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7104: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7120: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7136: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7152: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7168: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7184: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_720: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7200: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7216: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7232: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7248: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7264: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7280: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7296: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7312: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7328: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7344: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_736: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7360: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7376: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7392: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7408: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7424: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7440: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7456: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7472: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7488: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7504: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_752: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7520: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7536: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7552: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7568: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7584: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7600: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7616: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7632: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7648: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7664: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_768: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7680: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7696: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7712: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7728: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7744: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7760: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7776: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7792: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7808: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7824: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_784: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7840: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7856: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7872: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7888: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7904: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7920: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7936: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7952: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7968: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7984: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_80: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_800: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8000: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8016: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8032: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8048: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8064: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8080: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8096: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8112: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8128: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8144: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_816: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8160: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8176: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8192: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_832: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_848: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_864: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_880: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_896: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_912: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_928: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_944: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_96: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_960: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_976: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_992: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1008: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1024: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1040: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1056: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1072: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1088: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1104: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_112: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1120: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1136: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1152: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1168: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1184: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1200: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1216: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1232: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1248: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1264: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1280: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1296: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1312: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1328: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1344: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1360: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1376: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1392: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1408: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1424: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_144: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1440: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1456: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1472: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1488: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1504: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1520: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1536: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1552: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1568: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1584: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_160: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1600: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1616: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1632: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1648: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1664: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1680: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1696: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1712: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1728: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1744: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_176: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1760: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1776: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1792: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1808: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1824: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1840: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1856: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1872: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1888: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1904: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_192: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1920: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1936: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1952: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1968: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1984: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2000: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2016: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2032: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2048: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2064: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_208: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2080: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2096: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2112: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2128: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2144: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2160: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2176: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2192: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2208: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2224: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_224: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2240: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2256: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2272: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2288: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2304: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2320: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2336: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2352: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2368: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2384: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_240: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2400: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2416: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2432: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2448: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2464: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2480: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2496: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2512: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2528: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2544: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2560: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2576: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2592: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2608: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2624: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2640: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2656: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2672: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2688: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2704: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_272: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2720: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2736: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2752: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2768: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2784: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2800: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2816: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2832: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2848: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2864: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_288: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2880: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2896: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2912: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2928: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2944: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2960: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2976: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2992: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3008: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3024: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_304: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3040: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3056: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3072: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3088: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3104: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3120: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3136: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3152: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3168: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3184: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_320: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3200: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3216: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3232: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3248: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3264: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3280: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3296: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3312: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3328: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3344: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_336: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3360: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3376: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3392: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3408: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3424: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3440: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3456: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3472: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3488: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3504: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_352: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3520: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3536: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3552: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3568: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3584: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3600: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3616: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3632: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3648: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3664: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_368: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3680: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3696: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3712: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3728: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3744: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3760: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3776: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3792: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3808: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3824: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_384: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3840: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3856: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3872: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3888: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3904: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3920: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3936: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3952: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3968: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3984: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_400: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4000: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4016: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4032: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4048: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4064: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4080: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4096: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4112: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4128: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4144: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_416: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4160: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4176: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4192: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4208: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4224: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4240: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4256: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4272: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4288: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4304: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_432: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4320: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4336: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4352: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4368: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4384: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4400: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4416: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4432: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4448: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4464: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_448: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4480: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4496: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4512: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4528: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4544: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4560: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4576: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4592: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4608: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4624: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_464: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4640: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4656: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4672: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4688: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4704: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4720: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4736: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4752: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4768: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4784: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_48: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_480: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4800: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4816: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4832: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4848: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4864: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4880: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4896: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4912: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4928: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4944: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_496: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4960: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4976: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4992: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5008: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5024: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5040: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5056: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5072: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5088: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5104: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_512: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5120: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5136: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5152: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5168: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5184: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5200: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5216: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5232: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5248: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5264: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_528: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5280: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5296: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5312: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5328: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5344: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5360: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5376: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5392: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5408: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5424: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_544: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5440: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5456: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5472: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5488: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5504: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5520: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5536: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5552: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5568: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5584: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_560: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5600: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5616: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5632: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5648: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5664: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5680: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5696: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5712: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5728: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5744: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_576: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5760: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5776: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5792: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5808: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5824: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5840: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5856: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5872: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5888: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5904: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_592: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5920: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5936: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5952: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5968: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5984: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6000: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6016: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6032: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6048: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6064: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_608: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6080: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6096: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6112: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6128: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6144: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6160: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6176: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6192: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6208: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6224: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_624: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6240: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6256: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6272: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6288: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6304: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6320: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6336: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6352: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6368: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6384: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_640: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6400: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6416: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6432: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6448: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6464: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6480: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6496: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6512: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6528: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6544: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_656: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6560: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6576: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6592: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6608: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6624: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6640: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6656: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6672: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6688: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6704: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_672: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6720: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6736: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6752: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6768: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6784: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6800: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6816: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6832: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6848: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6864: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_688: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6880: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6896: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6912: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6928: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6944: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6960: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6976: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6992: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7008: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7024: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_704: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7040: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7056: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7072: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7088: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7104: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7120: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7136: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7152: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7168: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7184: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_720: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7200: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7216: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7232: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7248: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7264: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7280: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7296: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7312: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7328: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7344: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_736: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7360: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7376: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7392: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7408: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7424: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7440: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7456: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7472: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7488: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7504: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_752: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7520: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7536: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7552: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7568: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7584: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7600: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7616: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7632: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7648: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7664: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_768: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7680: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7696: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7712: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7728: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7744: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7760: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7776: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7792: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7808: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7824: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_784: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7840: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7856: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7872: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7888: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7904: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7920: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7936: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7952: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7968: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7984: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_80: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_800: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8000: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8016: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8032: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8048: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8064: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8080: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8096: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8112: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8128: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8144: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_816: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8160: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8176: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8192: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_832: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_848: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_864: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_880: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_896: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_912: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_928: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_944: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_96: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_960: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_976: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_992: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1008: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1024: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1040: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1056: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1072: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1088: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1104: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_112: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1120: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1136: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1152: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1168: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1184: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1200: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1216: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1232: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1248: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1264: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1280: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1296: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1312: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1328: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1344: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1360: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1376: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1392: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1408: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1424: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_144: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1440: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1456: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1472: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1488: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1504: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1520: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1536: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1552: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1568: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1584: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_160: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1600: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1616: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1632: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1648: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1664: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1680: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1696: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1712: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1728: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1744: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_176: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1760: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1776: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1792: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1808: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1824: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1840: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1856: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1872: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1888: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1904: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_192: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1920: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1936: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1952: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1968: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1984: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2000: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2016: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2032: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2048: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2064: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_208: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2080: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2096: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2112: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2128: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2144: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2160: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2176: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2192: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2208: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2224: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_224: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2240: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2256: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2272: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2288: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2304: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2320: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2336: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2352: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2368: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2384: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_240: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2400: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2416: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2432: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2448: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2464: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2480: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2496: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2512: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2528: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2544: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2560: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2576: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2592: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2608: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2624: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2640: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2656: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2672: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2688: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2704: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_272: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2720: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2736: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2752: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2768: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2784: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2800: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2816: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2832: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2848: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2864: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_288: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2880: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2896: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2912: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2928: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2944: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2960: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2976: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2992: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3008: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3024: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_304: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3040: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3056: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3072: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3088: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3104: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3120: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3136: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3152: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3168: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3184: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_320: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3200: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3216: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3232: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3248: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3264: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3280: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3296: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3312: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3328: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3344: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_336: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3360: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3376: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3392: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3408: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3424: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3440: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3456: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3472: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3488: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3504: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_352: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3520: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3536: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3552: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3568: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3584: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3600: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3616: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3632: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3648: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3664: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_368: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3680: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3696: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3712: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3728: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3744: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3760: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3776: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3792: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3808: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3824: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_384: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3840: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3856: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3872: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3888: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3904: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3920: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3936: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3952: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3968: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3984: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_400: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4000: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4016: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4032: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4048: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4064: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4080: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4096: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4112: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4128: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4144: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_416: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4160: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4176: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4192: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4208: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4224: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4240: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4256: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4272: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4288: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4304: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_432: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4320: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4336: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4352: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4368: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4384: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4400: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4416: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4432: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4448: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4464: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_448: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4480: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4496: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4512: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4528: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4544: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4560: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4576: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4592: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4608: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4624: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_464: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4640: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4656: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4672: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4688: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4704: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4720: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4736: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4752: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4768: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4784: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_48: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_480: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4800: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4816: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4832: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4848: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4864: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4880: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4896: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4912: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4928: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4944: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_496: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4960: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4976: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4992: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5008: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5024: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5040: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5056: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5072: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5088: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5104: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_512: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5120: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5136: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5152: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5168: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5184: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5200: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5216: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5232: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5248: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5264: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_528: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5280: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5296: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5312: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5328: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5344: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5360: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5376: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5392: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5408: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5424: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_544: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5440: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5456: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5472: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5488: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5504: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5520: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5536: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5552: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5568: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5584: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_560: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5600: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5616: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5632: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5648: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5664: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5680: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5696: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5712: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5728: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5744: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_576: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5760: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5776: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5792: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5808: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5824: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5840: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5856: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5872: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5888: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5904: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_592: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5920: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5936: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5952: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5968: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5984: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6000: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6016: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6032: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6048: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6064: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_608: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6080: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6096: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6112: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6128: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6144: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6160: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6176: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6192: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6208: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6224: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_624: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6240: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6256: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6272: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6288: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6304: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6320: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6336: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6352: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6368: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6384: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_640: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6400: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6416: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6432: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6448: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6464: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6480: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6496: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6512: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6528: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6544: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_656: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6560: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6576: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6592: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6608: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6624: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6640: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6656: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6672: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6688: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6704: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_672: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6720: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6736: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6752: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6768: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6784: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6800: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6816: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6832: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6848: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6864: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_688: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6880: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6896: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6912: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6928: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6944: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6960: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6976: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6992: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7008: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7024: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_704: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7040: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7056: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7072: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7088: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7104: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7120: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7136: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7152: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7168: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7184: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_720: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7200: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7216: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7232: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7248: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7264: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7280: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7296: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7312: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7328: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7344: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_736: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7360: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7376: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7392: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7408: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7424: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7440: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7456: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7472: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7488: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7504: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_752: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7520: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7536: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7552: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7568: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7584: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7600: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7616: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7632: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7648: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7664: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_768: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7680: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7696: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7712: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7728: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7744: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7760: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7776: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7792: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7808: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7824: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_784: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7840: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7856: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7872: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7888: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7904: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7920: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7936: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7952: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7968: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7984: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_80: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_800: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8000: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8016: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8032: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8048: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8064: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8080: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8096: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8112: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8128: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8144: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_816: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8160: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8176: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8192: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_832: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_848: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_864: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_880: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_896: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_912: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_928: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_944: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_96: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_960: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_976: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_992: skip
arm64_sve_regs: pass
arm64_sve_vl: pass
arm64_syscall-abi: pass
arm64_syscall-abi_getpid_FPSIMD: pass
arm64_syscall-abi_getpid_SVE_VL_112: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_128: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_144: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_16: pass
arm64_syscall-abi_getpid_SVE_VL_160: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_176: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_192: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_208: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_224: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_240: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_256: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_32: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_48: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_64: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_80: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_96: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_FPSIMD: pass
arm64_syscall-abi_sched_yield_SVE_VL_112: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_128: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_144: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_16: pass
arm64_syscall-abi_sched_yield_SVE_VL_160: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_176: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_192: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_208: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_224: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_240: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_256: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_32: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_48: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_64: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_80: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_96: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_ZA: pass
arm64_tags_test: pass
arm64_tpidr2: pass
arm64_tpidr2_default_value: pass
arm64_tpidr2_write_clone_read: pass
arm64_tpidr2_write_fork_read: pass
arm64_tpidr2_write_read: pass
arm64_tpidr2_write_sleep_read: pass
arm64_vec-syscfg: pass
arm64_vec-syscfg_SME_current_VL_is_32: pass
arm64_vec-syscfg_SME_default_vector_length_32: pass
arm64_vec-syscfg_SME_maximum_vector_length_256: pass
arm64_vec-syscfg_SME_minimum_vector_length_16: pass
arm64_vec-syscfg_SME_prctl_set_all_VLs_0_errors: pass
arm64_vec-syscfg_SME_prctl_set_min_max: pass
arm64_vec-syscfg_SME_set_VL_32_and_have_VL_32: pass
arm64_vec-syscfg_SME_vector_length_set_on_exec: pass
arm64_vec-syscfg_SME_vector_length_used_default: pass
arm64_vec-syscfg_SME_vector_length_was_inherited: pass
arm64_vec-syscfg_SVE_current_VL_is_64: pass
arm64_vec-syscfg_SVE_default_vector_length_64: pass
arm64_vec-syscfg_SVE_maximum_vector_length_256: pass
arm64_vec-syscfg_SVE_minimum_vector_length_16: pass
arm64_vec-syscfg_SVE_prctl_set_all_VLs_0_errors: pass
arm64_vec-syscfg_SVE_prctl_set_min_max: pass
arm64_vec-syscfg_SVE_set_VL_64_and_have_VL_64: pass
arm64_vec-syscfg_SVE_vector_length_set_on_exec: pass
arm64_vec-syscfg_SVE_vector_length_used_default: pass
arm64_vec-syscfg_SVE_vector_length_was_inherited: pass
arm64_za-fork: pass
arm64_za-fork_fork_test: pass
arm64_za-ptrace: pass
arm64_za-ptrace_Data_match_for_VL_128: pass
arm64_za-ptrace_Data_match_for_VL_16: pass
arm64_za-ptrace_Data_match_for_VL_256: pass
arm64_za-ptrace_Data_match_for_VL_32: pass
arm64_za-ptrace_Data_match_for_VL_64: pass
arm64_za-ptrace_Disabled_ZA_for_VL_1008: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1024: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1040: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1056: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1072: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1088: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1104: skip
arm64_za-ptrace_Disabled_ZA_for_VL_112: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1120: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1136: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1152: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1168: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1184: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1200: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1216: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1232: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1248: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1264: skip
arm64_za-ptrace_Disabled_ZA_for_VL_128: pass
arm64_za-ptrace_Disabled_ZA_for_VL_1280: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1296: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1312: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1328: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1344: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1360: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1376: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1392: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1408: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1424: skip
arm64_za-ptrace_Disabled_ZA_for_VL_144: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1440: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1456: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1472: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1488: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1504: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1520: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1536: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1552: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1568: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1584: skip
arm64_za-ptrace_Disabled_ZA_for_VL_16: pass
arm64_za-ptrace_Disabled_ZA_for_VL_160: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1600: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1616: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1632: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1648: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1664: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1680: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1696: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1712: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1728: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1744: skip
arm64_za-ptrace_Disabled_ZA_for_VL_176: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1760: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1776: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1792: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1808: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1824: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1840: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1856: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1872: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1888: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1904: skip
arm64_za-ptrace_Disabled_ZA_for_VL_192: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1920: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1936: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1952: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1968: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1984: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2000: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2016: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2032: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2048: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2064: skip
arm64_za-ptrace_Disabled_ZA_for_VL_208: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2080: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2096: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2112: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2128: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2144: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2160: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2176: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2192: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2208: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2224: skip
arm64_za-ptrace_Disabled_ZA_for_VL_224: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2240: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2256: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2272: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2288: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2304: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2320: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2336: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2352: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2368: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2384: skip
arm64_za-ptrace_Disabled_ZA_for_VL_240: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2400: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2416: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2432: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2448: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2464: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2480: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2496: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2512: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2528: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2544: skip
arm64_za-ptrace_Disabled_ZA_for_VL_256: pass
arm64_za-ptrace_Disabled_ZA_for_VL_2560: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2576: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2592: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2608: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2624: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2640: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2656: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2672: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2688: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2704: skip
arm64_za-ptrace_Disabled_ZA_for_VL_272: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2720: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2736: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2752: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2768: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2784: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2800: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2816: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2832: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2848: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2864: skip
arm64_za-ptrace_Disabled_ZA_for_VL_288: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2880: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2896: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2912: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2928: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2944: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2960: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2976: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2992: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3008: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3024: skip
arm64_za-ptrace_Disabled_ZA_for_VL_304: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3040: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3056: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3072: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3088: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3104: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3120: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3136: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3152: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3168: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3184: skip
arm64_za-ptrace_Disabled_ZA_for_VL_32: pass
arm64_za-ptrace_Disabled_ZA_for_VL_320: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3200: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3216: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3232: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3248: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3264: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3280: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3296: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3312: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3328: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3344: skip
arm64_za-ptrace_Disabled_ZA_for_VL_336: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3360: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3376: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3392: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3408: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3424: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3440: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3456: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3472: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3488: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3504: skip
arm64_za-ptrace_Disabled_ZA_for_VL_352: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3520: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3536: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3552: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3568: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3584: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3600: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3616: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3632: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3648: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3664: skip
arm64_za-ptrace_Disabled_ZA_for_VL_368: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3680: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3696: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3712: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3728: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3744: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3760: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3776: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3792: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3808: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3824: skip
arm64_za-ptrace_Disabled_ZA_for_VL_384: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3840: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3856: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3872: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3888: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3904: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3920: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3936: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3952: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3968: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3984: skip
arm64_za-ptrace_Disabled_ZA_for_VL_400: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4000: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4016: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4032: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4048: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4064: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4080: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4096: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4112: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4128: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4144: skip
arm64_za-ptrace_Disabled_ZA_for_VL_416: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4160: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4176: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4192: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4208: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4224: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4240: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4256: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4272: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4288: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4304: skip
arm64_za-ptrace_Disabled_ZA_for_VL_432: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4320: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4336: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4352: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4368: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4384: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4400: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4416: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4432: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4448: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4464: skip
arm64_za-ptrace_Disabled_ZA_for_VL_448: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4480: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4496: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4512: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4528: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4544: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4560: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4576: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4592: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4608: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4624: skip
arm64_za-ptrace_Disabled_ZA_for_VL_464: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4640: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4656: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4672: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4688: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4704: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4720: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4736: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4752: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4768: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4784: skip
arm64_za-ptrace_Disabled_ZA_for_VL_48: skip
arm64_za-ptrace_Disabled_ZA_for_VL_480: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4800: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4816: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4832: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4848: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4864: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4880: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4896: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4912: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4928: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4944: skip
arm64_za-ptrace_Disabled_ZA_for_VL_496: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4960: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4976: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4992: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5008: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5024: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5040: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5056: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5072: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5088: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5104: skip
arm64_za-ptrace_Disabled_ZA_for_VL_512: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5120: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5136: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5152: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5168: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5184: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5200: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5216: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5232: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5248: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5264: skip
arm64_za-ptrace_Disabled_ZA_for_VL_528: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5280: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5296: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5312: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5328: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5344: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5360: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5376: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5392: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5408: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5424: skip
arm64_za-ptrace_Disabled_ZA_for_VL_544: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5440: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5456: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5472: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5488: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5504: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5520: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5536: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5552: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5568: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5584: skip
arm64_za-ptrace_Disabled_ZA_for_VL_560: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5600: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5616: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5632: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5648: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5664: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5680: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5696: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5712: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5728: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5744: skip
arm64_za-ptrace_Disabled_ZA_for_VL_576: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5760: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5776: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5792: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5808: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5824: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5840: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5856: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5872: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5888: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5904: skip
arm64_za-ptrace_Disabled_ZA_for_VL_592: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5920: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5936: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5952: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5968: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5984: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6000: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6016: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6032: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6048: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6064: skip
arm64_za-ptrace_Disabled_ZA_for_VL_608: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6080: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6096: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6112: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6128: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6144: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6160: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6176: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6192: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6208: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6224: skip
arm64_za-ptrace_Disabled_ZA_for_VL_624: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6240: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6256: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6272: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6288: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6304: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6320: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6336: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6352: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6368: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6384: skip
arm64_za-ptrace_Disabled_ZA_for_VL_64: pass
arm64_za-ptrace_Disabled_ZA_for_VL_640: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6400: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6416: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6432: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6448: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6464: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6480: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6496: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6512: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6528: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6544: skip
arm64_za-ptrace_Disabled_ZA_for_VL_656: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6560: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6576: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6592: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6608: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6624: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6640: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6656: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6672: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6688: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6704: skip
arm64_za-ptrace_Disabled_ZA_for_VL_672: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6720: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6736: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6752: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6768: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6784: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6800: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6816: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6832: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6848: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6864: skip
arm64_za-ptrace_Disabled_ZA_for_VL_688: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6880: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6896: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6912: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6928: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6944: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6960: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6976: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6992: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7008: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7024: skip
arm64_za-ptrace_Disabled_ZA_for_VL_704: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7040: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7056: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7072: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7088: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7104: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7120: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7136: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7152: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7168: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7184: skip
arm64_za-ptrace_Disabled_ZA_for_VL_720: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7200: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7216: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7232: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7248: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7264: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7280: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7296: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7312: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7328: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7344: skip
arm64_za-ptrace_Disabled_ZA_for_VL_736: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7360: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7376: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7392: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7408: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7424: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7440: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7456: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7472: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7488: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7504: skip
arm64_za-ptrace_Disabled_ZA_for_VL_752: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7520: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7536: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7552: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7568: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7584: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7600: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7616: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7632: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7648: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7664: skip
arm64_za-ptrace_Disabled_ZA_for_VL_768: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7680: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7696: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7712: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7728: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7744: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7760: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7776: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7792: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7808: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7824: skip
arm64_za-ptrace_Disabled_ZA_for_VL_784: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7840: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7856: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7872: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7888: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7904: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7920: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7936: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7952: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7968: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7984: skip
arm64_za-ptrace_Disabled_ZA_for_VL_80: skip
arm64_za-ptrace_Disabled_ZA_for_VL_800: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8000: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8016: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8032: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8048: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8064: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8080: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8096: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8112: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8128: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8144: skip
arm64_za-ptrace_Disabled_ZA_for_VL_816: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8160: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8176: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8192: skip
arm64_za-ptrace_Disabled_ZA_for_VL_832: skip
arm64_za-ptrace_Disabled_ZA_for_VL_848: skip
arm64_za-ptrace_Disabled_ZA_for_VL_864: skip
arm64_za-ptrace_Disabled_ZA_for_VL_880: skip
arm64_za-ptrace_Disabled_ZA_for_VL_896: skip
arm64_za-ptrace_Disabled_ZA_for_VL_912: skip
arm64_za-ptrace_Disabled_ZA_for_VL_928: skip
arm64_za-ptrace_Disabled_ZA_for_VL_944: skip
arm64_za-ptrace_Disabled_ZA_for_VL_96: skip
arm64_za-ptrace_Disabled_ZA_for_VL_960: skip
arm64_za-ptrace_Disabled_ZA_for_VL_976: skip
arm64_za-ptrace_Disabled_ZA_for_VL_992: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1008: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1024: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1040: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1056: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1072: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1088: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1104: skip
arm64_za-ptrace_Get_and_set_data_for_VL_112: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1120: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1136: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1152: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1168: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1184: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1200: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1216: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1232: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1248: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1264: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1280: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1296: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1312: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1328: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1344: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1360: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1376: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1392: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1408: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1424: skip
arm64_za-ptrace_Get_and_set_data_for_VL_144: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1440: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1456: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1472: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1488: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1504: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1520: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1536: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1552: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1568: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1584: skip
arm64_za-ptrace_Get_and_set_data_for_VL_160: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1600: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1616: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1632: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1648: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1664: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1680: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1696: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1712: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1728: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1744: skip
arm64_za-ptrace_Get_and_set_data_for_VL_176: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1760: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1776: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1792: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1808: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1824: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1840: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1856: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1872: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1888: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1904: skip
arm64_za-ptrace_Get_and_set_data_for_VL_192: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1920: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1936: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1952: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1968: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1984: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2000: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2016: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2032: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2048: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2064: skip
arm64_za-ptrace_Get_and_set_data_for_VL_208: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2080: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2096: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2112: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2128: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2144: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2160: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2176: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2192: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2208: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2224: skip
arm64_za-ptrace_Get_and_set_data_for_VL_224: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2240: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2256: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2272: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2288: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2304: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2320: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2336: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2352: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2368: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2384: skip
arm64_za-ptrace_Get_and_set_data_for_VL_240: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2400: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2416: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2432: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2448: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2464: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2480: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2496: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2512: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2528: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2544: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2560: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2576: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2592: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2608: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2624: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2640: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2656: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2672: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2688: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2704: skip
arm64_za-ptrace_Get_and_set_data_for_VL_272: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2720: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2736: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2752: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2768: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2784: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2800: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2816: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2832: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2848: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2864: skip
arm64_za-ptrace_Get_and_set_data_for_VL_288: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2880: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2896: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2912: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2928: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2944: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2960: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2976: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2992: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3008: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3024: skip
arm64_za-ptrace_Get_and_set_data_for_VL_304: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3040: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3056: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3072: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3088: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3104: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3120: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3136: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3152: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3168: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3184: skip
arm64_za-ptrace_Get_and_set_data_for_VL_320: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3200: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3216: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3232: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3248: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3264: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3280: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3296: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3312: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3328: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3344: skip
arm64_za-ptrace_Get_and_set_data_for_VL_336: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3360: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3376: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3392: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3408: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3424: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3440: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3456: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3472: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3488: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3504: skip
arm64_za-ptrace_Get_and_set_data_for_VL_352: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3520: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3536: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3552: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3568: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3584: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3600: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3616: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3632: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3648: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3664: skip
arm64_za-ptrace_Get_and_set_data_for_VL_368: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3680: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3696: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3712: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3728: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3744: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3760: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3776: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3792: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3808: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3824: skip
arm64_za-ptrace_Get_and_set_data_for_VL_384: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3840: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3856: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3872: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3888: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3904: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3920: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3936: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3952: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3968: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3984: skip
arm64_za-ptrace_Get_and_set_data_for_VL_400: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4000: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4016: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4032: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4048: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4064: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4080: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4096: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4112: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4128: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4144: skip
arm64_za-ptrace_Get_and_set_data_for_VL_416: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4160: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4176: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4192: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4208: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4224: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4240: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4256: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4272: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4288: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4304: skip
arm64_za-ptrace_Get_and_set_data_for_VL_432: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4320: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4336: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4352: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4368: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4384: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4400: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4416: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4432: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4448: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4464: skip
arm64_za-ptrace_Get_and_set_data_for_VL_448: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4480: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4496: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4512: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4528: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4544: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4560: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4576: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4592: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4608: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4624: skip
arm64_za-ptrace_Get_and_set_data_for_VL_464: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4640: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4656: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4672: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4688: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4704: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4720: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4736: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4752: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4768: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4784: skip
arm64_za-ptrace_Get_and_set_data_for_VL_48: skip
arm64_za-ptrace_Get_and_set_data_for_VL_480: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4800: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4816: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4832: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4848: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4864: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4880: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4896: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4912: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4928: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4944: skip
arm64_za-ptrace_Get_and_set_data_for_VL_496: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4960: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4976: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4992: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5008: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5024: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5040: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5056: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5072: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5088: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5104: skip
arm64_za-ptrace_Get_and_set_data_for_VL_512: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5120: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5136: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5152: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5168: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5184: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5200: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5216: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5232: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5248: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5264: skip
arm64_za-ptrace_Get_and_set_data_for_VL_528: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5280: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5296: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5312: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5328: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5344: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5360: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5376: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5392: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5408: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5424: skip
arm64_za-ptrace_Get_and_set_data_for_VL_544: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5440: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5456: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5472: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5488: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5504: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5520: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5536: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5552: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5568: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5584: skip
arm64_za-ptrace_Get_and_set_data_for_VL_560: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5600: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5616: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5632: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5648: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5664: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5680: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5696: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5712: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5728: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5744: skip
arm64_za-ptrace_Get_and_set_data_for_VL_576: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5760: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5776: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5792: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5808: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5824: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5840: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5856: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5872: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5888: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5904: skip
arm64_za-ptrace_Get_and_set_data_for_VL_592: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5920: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5936: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5952: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5968: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5984: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6000: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6016: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6032: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6048: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6064: skip
arm64_za-ptrace_Get_and_set_data_for_VL_608: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6080: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6096: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6112: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6128: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6144: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6160: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6176: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6192: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6208: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6224: skip
arm64_za-ptrace_Get_and_set_data_for_VL_624: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6240: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6256: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6272: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6288: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6304: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6320: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6336: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6352: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6368: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6384: skip
arm64_za-ptrace_Get_and_set_data_for_VL_640: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6400: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6416: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6432: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6448: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6464: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6480: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6496: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6512: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6528: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6544: skip
arm64_za-ptrace_Get_and_set_data_for_VL_656: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6560: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6576: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6592: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6608: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6624: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6640: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6656: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6672: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6688: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6704: skip
arm64_za-ptrace_Get_and_set_data_for_VL_672: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6720: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6736: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6752: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6768: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6784: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6800: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6816: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6832: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6848: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6864: skip
arm64_za-ptrace_Get_and_set_data_for_VL_688: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6880: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6896: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6912: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6928: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6944: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6960: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6976: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6992: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7008: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7024: skip
arm64_za-ptrace_Get_and_set_data_for_VL_704: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7040: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7056: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7072: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7088: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7104: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7120: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7136: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7152: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7168: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7184: skip
arm64_za-ptrace_Get_and_set_data_for_VL_720: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7200: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7216: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7232: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7248: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7264: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7280: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7296: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7312: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7328: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7344: skip
arm64_za-ptrace_Get_and_set_data_for_VL_736: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7360: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7376: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7392: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7408: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7424: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7440: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7456: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7472: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7488: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7504: skip
arm64_za-ptrace_Get_and_set_data_for_VL_752: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7520: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7536: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7552: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7568: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7584: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7600: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7616: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7632: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7648: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7664: skip
arm64_za-ptrace_Get_and_set_data_for_VL_768: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7680: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7696: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7712: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7728: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7744: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7760: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7776: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7792: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7808: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7824: skip
arm64_za-ptrace_Get_and_set_data_for_VL_784: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7840: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7856: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7872: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7888: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7904: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7920: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7936: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7952: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7968: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7984: skip
arm64_za-ptrace_Get_and_set_data_for_VL_80: skip
arm64_za-ptrace_Get_and_set_data_for_VL_800: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8000: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8016: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8032: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8048: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8064: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8080: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8096: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8112: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8128: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8144: skip
arm64_za-ptrace_Get_and_set_data_for_VL_816: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8160: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8176: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8192: skip
arm64_za-ptrace_Get_and_set_data_for_VL_832: skip
arm64_za-ptrace_Get_and_set_data_for_VL_848: skip
arm64_za-ptrace_Get_and_set_data_for_VL_864: skip
arm64_za-ptrace_Get_and_set_data_for_VL_880: skip
arm64_za-ptrace_Get_and_set_data_for_VL_896: skip
arm64_za-ptrace_Get_and_set_data_for_VL_912: skip
arm64_za-ptrace_Get_and_set_data_for_VL_928: skip
arm64_za-ptrace_Get_and_set_data_for_VL_944: skip
arm64_za-ptrace_Get_and_set_data_for_VL_96: skip
arm64_za-ptrace_Get_and_set_data_for_VL_960: skip
arm64_za-ptrace_Get_and_set_data_for_VL_976: skip
arm64_za-ptrace_Get_and_set_data_for_VL_992: skip
arm64_za-ptrace_Set_VL_1008: pass
arm64_za-ptrace_Set_VL_1024: pass
arm64_za-ptrace_Set_VL_1040: pass
arm64_za-ptrace_Set_VL_1056: pass
arm64_za-ptrace_Set_VL_1072: pass
arm64_za-ptrace_Set_VL_1088: pass
arm64_za-ptrace_Set_VL_1104: pass
arm64_za-ptrace_Set_VL_112: pass
arm64_za-ptrace_Set_VL_1120: pass
arm64_za-ptrace_Set_VL_1136: pass
arm64_za-ptrace_Set_VL_1152: pass
arm64_za-ptrace_Set_VL_1168: pass
arm64_za-ptrace_Set_VL_1184: pass
arm64_za-ptrace_Set_VL_1200: pass
arm64_za-ptrace_Set_VL_1216: pass
arm64_za-ptrace_Set_VL_1232: pass
arm64_za-ptrace_Set_VL_1248: pass
arm64_za-ptrace_Set_VL_1264: pass
arm64_za-ptrace_Set_VL_128: pass
arm64_za-ptrace_Set_VL_1280: pass
arm64_za-ptrace_Set_VL_1296: pass
arm64_za-ptrace_Set_VL_1312: pass
arm64_za-ptrace_Set_VL_1328: pass
arm64_za-ptrace_Set_VL_1344: pass
arm64_za-ptrace_Set_VL_1360: pass
arm64_za-ptrace_Set_VL_1376: pass
arm64_za-ptrace_Set_VL_1392: pass
arm64_za-ptrace_Set_VL_1408: pass
arm64_za-ptrace_Set_VL_1424: pass
arm64_za-ptrace_Set_VL_144: pass
arm64_za-ptrace_Set_VL_1440: pass
arm64_za-ptrace_Set_VL_1456: pass
arm64_za-ptrace_Set_VL_1472: pass
arm64_za-ptrace_Set_VL_1488: pass
arm64_za-ptrace_Set_VL_1504: pass
arm64_za-ptrace_Set_VL_1520: pass
arm64_za-ptrace_Set_VL_1536: pass
arm64_za-ptrace_Set_VL_1552: pass
arm64_za-ptrace_Set_VL_1568: pass
arm64_za-ptrace_Set_VL_1584: pass
arm64_za-ptrace_Set_VL_16: pass
arm64_za-ptrace_Set_VL_160: pass
arm64_za-ptrace_Set_VL_1600: pass
arm64_za-ptrace_Set_VL_1616: pass
arm64_za-ptrace_Set_VL_1632: pass
arm64_za-ptrace_Set_VL_1648: pass
arm64_za-ptrace_Set_VL_1664: pass
arm64_za-ptrace_Set_VL_1680: pass
arm64_za-ptrace_Set_VL_1696: pass
arm64_za-ptrace_Set_VL_1712: pass
arm64_za-ptrace_Set_VL_1728: pass
arm64_za-ptrace_Set_VL_1744: pass
arm64_za-ptrace_Set_VL_176: pass
arm64_za-ptrace_Set_VL_1760: pass
arm64_za-ptrace_Set_VL_1776: pass
arm64_za-ptrace_Set_VL_1792: pass
arm64_za-ptrace_Set_VL_1808: pass
arm64_za-ptrace_Set_VL_1824: pass
arm64_za-ptrace_Set_VL_1840: pass
arm64_za-ptrace_Set_VL_1856: pass
arm64_za-ptrace_Set_VL_1872: pass
arm64_za-ptrace_Set_VL_1888: pass
arm64_za-ptrace_Set_VL_1904: pass
arm64_za-ptrace_Set_VL_192: pass
arm64_za-ptrace_Set_VL_1920: pass
arm64_za-ptrace_Set_VL_1936: pass
arm64_za-ptrace_Set_VL_1952: pass
arm64_za-ptrace_Set_VL_1968: pass
arm64_za-ptrace_Set_VL_1984: pass
arm64_za-ptrace_Set_VL_2000: pass
arm64_za-ptrace_Set_VL_2016: pass
arm64_za-ptrace_Set_VL_2032: pass
arm64_za-ptrace_Set_VL_2048: pass
arm64_za-ptrace_Set_VL_2064: pass
arm64_za-ptrace_Set_VL_208: pass
arm64_za-ptrace_Set_VL_2080: pass
arm64_za-ptrace_Set_VL_2096: pass
arm64_za-ptrace_Set_VL_2112: pass
arm64_za-ptrace_Set_VL_2128: pass
arm64_za-ptrace_Set_VL_2144: pass
arm64_za-ptrace_Set_VL_2160: pass
arm64_za-ptrace_Set_VL_2176: pass
arm64_za-ptrace_Set_VL_2192: pass
arm64_za-ptrace_Set_VL_2208: pass
arm64_za-ptrace_Set_VL_2224: pass
arm64_za-ptrace_Set_VL_224: pass
arm64_za-ptrace_Set_VL_2240: pass
arm64_za-ptrace_Set_VL_2256: pass
arm64_za-ptrace_Set_VL_2272: pass
arm64_za-ptrace_Set_VL_2288: pass
arm64_za-ptrace_Set_VL_2304: pass
arm64_za-ptrace_Set_VL_2320: pass
arm64_za-ptrace_Set_VL_2336: pass
arm64_za-ptrace_Set_VL_2352: pass
arm64_za-ptrace_Set_VL_2368: pass
arm64_za-ptrace_Set_VL_2384: pass
arm64_za-ptrace_Set_VL_240: pass
arm64_za-ptrace_Set_VL_2400: pass
arm64_za-ptrace_Set_VL_2416: pass
arm64_za-ptrace_Set_VL_2432: pass
arm64_za-ptrace_Set_VL_2448: pass
arm64_za-ptrace_Set_VL_2464: pass
arm64_za-ptrace_Set_VL_2480: pass
arm64_za-ptrace_Set_VL_2496: pass
arm64_za-ptrace_Set_VL_2512: pass
arm64_za-ptrace_Set_VL_2528: pass
arm64_za-ptrace_Set_VL_2544: pass
arm64_za-ptrace_Set_VL_256: pass
arm64_za-ptrace_Set_VL_2560: pass
arm64_za-ptrace_Set_VL_2576: pass
arm64_za-ptrace_Set_VL_2592: pass
arm64_za-ptrace_Set_VL_2608: pass
arm64_za-ptrace_Set_VL_2624: pass
arm64_za-ptrace_Set_VL_2640: pass
arm64_za-ptrace_Set_VL_2656: pass
arm64_za-ptrace_Set_VL_2672: pass
arm64_za-ptrace_Set_VL_2688: pass
arm64_za-ptrace_Set_VL_2704: pass
arm64_za-ptrace_Set_VL_272: pass
arm64_za-ptrace_Set_VL_2720: pass
arm64_za-ptrace_Set_VL_2736: pass
arm64_za-ptrace_Set_VL_2752: pass
arm64_za-ptrace_Set_VL_2768: pass
arm64_za-ptrace_Set_VL_2784: pass
arm64_za-ptrace_Set_VL_2800: pass
arm64_za-ptrace_Set_VL_2816: pass
arm64_za-ptrace_Set_VL_2832: pass
arm64_za-ptrace_Set_VL_2848: pass
arm64_za-ptrace_Set_VL_2864: pass
arm64_za-ptrace_Set_VL_288: pass
arm64_za-ptrace_Set_VL_2880: pass
arm64_za-ptrace_Set_VL_2896: pass
arm64_za-ptrace_Set_VL_2912: pass
arm64_za-ptrace_Set_VL_2928: pass
arm64_za-ptrace_Set_VL_2944: pass
arm64_za-ptrace_Set_VL_2960: pass
arm64_za-ptrace_Set_VL_2976: pass
arm64_za-ptrace_Set_VL_2992: pass
arm64_za-ptrace_Set_VL_3008: pass
arm64_za-ptrace_Set_VL_3024: pass
arm64_za-ptrace_Set_VL_304: pass
arm64_za-ptrace_Set_VL_3040: pass
arm64_za-ptrace_Set_VL_3056: pass
arm64_za-ptrace_Set_VL_3072: pass
arm64_za-ptrace_Set_VL_3088: pass
arm64_za-ptrace_Set_VL_3104: pass
arm64_za-ptrace_Set_VL_3120: pass
arm64_za-ptrace_Set_VL_3136: pass
arm64_za-ptrace_Set_VL_3152: pass
arm64_za-ptrace_Set_VL_3168: pass
arm64_za-ptrace_Set_VL_3184: pass
arm64_za-ptrace_Set_VL_32: pass
arm64_za-ptrace_Set_VL_320: pass
arm64_za-ptrace_Set_VL_3200: pass
arm64_za-ptrace_Set_VL_3216: pass
arm64_za-ptrace_Set_VL_3232: pass
arm64_za-ptrace_Set_VL_3248: pass
arm64_za-ptrace_Set_VL_3264: pass
arm64_za-ptrace_Set_VL_3280: pass
arm64_za-ptrace_Set_VL_3296: pass
arm64_za-ptrace_Set_VL_3312: pass
arm64_za-ptrace_Set_VL_3328: pass
arm64_za-ptrace_Set_VL_3344: pass
arm64_za-ptrace_Set_VL_336: pass
arm64_za-ptrace_Set_VL_3360: pass
arm64_za-ptrace_Set_VL_3376: pass
arm64_za-ptrace_Set_VL_3392: pass
arm64_za-ptrace_Set_VL_3408: pass
arm64_za-ptrace_Set_VL_3424: pass
arm64_za-ptrace_Set_VL_3440: pass
arm64_za-ptrace_Set_VL_3456: pass
arm64_za-ptrace_Set_VL_3472: pass
arm64_za-ptrace_Set_VL_3488: pass
arm64_za-ptrace_Set_VL_3504: pass
arm64_za-ptrace_Set_VL_352: pass
arm64_za-ptrace_Set_VL_3520: pass
arm64_za-ptrace_Set_VL_3536: pass
arm64_za-ptrace_Set_VL_3552: pass
arm64_za-ptrace_Set_VL_3568: pass
arm64_za-ptrace_Set_VL_3584: pass
arm64_za-ptrace_Set_VL_3600: pass
arm64_za-ptrace_Set_VL_3616: pass
arm64_za-ptrace_Set_VL_3632: pass
arm64_za-ptrace_Set_VL_3648: pass
arm64_za-ptrace_Set_VL_3664: pass
arm64_za-ptrace_Set_VL_368: pass
arm64_za-ptrace_Set_VL_3680: pass
arm64_za-ptrace_Set_VL_3696: pass
arm64_za-ptrace_Set_VL_3712: pass
arm64_za-ptrace_Set_VL_3728: pass
arm64_za-ptrace_Set_VL_3744: pass
arm64_za-ptrace_Set_VL_3760: pass
arm64_za-ptrace_Set_VL_3776: pass
arm64_za-ptrace_Set_VL_3792: pass
arm64_za-ptrace_Set_VL_3808: pass
arm64_za-ptrace_Set_VL_3824: pass
arm64_za-ptrace_Set_VL_384: pass
arm64_za-ptrace_Set_VL_3840: pass
arm64_za-ptrace_Set_VL_3856: pass
arm64_za-ptrace_Set_VL_3872: pass
arm64_za-ptrace_Set_VL_3888: pass
arm64_za-ptrace_Set_VL_3904: pass
arm64_za-ptrace_Set_VL_3920: pass
arm64_za-ptrace_Set_VL_3936: pass
arm64_za-ptrace_Set_VL_3952: pass
arm64_za-ptrace_Set_VL_3968: pass
arm64_za-ptrace_Set_VL_3984: pass
arm64_za-ptrace_Set_VL_400: pass
arm64_za-ptrace_Set_VL_4000: pass
arm64_za-ptrace_Set_VL_4016: pass
arm64_za-ptrace_Set_VL_4032: pass
arm64_za-ptrace_Set_VL_4048: pass
arm64_za-ptrace_Set_VL_4064: pass
arm64_za-ptrace_Set_VL_4080: pass
arm64_za-ptrace_Set_VL_4096: pass
arm64_za-ptrace_Set_VL_4112: pass
arm64_za-ptrace_Set_VL_4128: pass
arm64_za-ptrace_Set_VL_4144: pass
arm64_za-ptrace_Set_VL_416: pass
arm64_za-ptrace_Set_VL_4160: pass
arm64_za-ptrace_Set_VL_4176: pass
arm64_za-ptrace_Set_VL_4192: pass
arm64_za-ptrace_Set_VL_4208: pass
arm64_za-ptrace_Set_VL_4224: pass
arm64_za-ptrace_Set_VL_4240: pass
arm64_za-ptrace_Set_VL_4256: pass
arm64_za-ptrace_Set_VL_4272: pass
arm64_za-ptrace_Set_VL_4288: pass
arm64_za-ptrace_Set_VL_4304: pass
arm64_za-ptrace_Set_VL_432: pass
arm64_za-ptrace_Set_VL_4320: pass
arm64_za-ptrace_Set_VL_4336: pass
arm64_za-ptrace_Set_VL_4352: pass
arm64_za-ptrace_Set_VL_4368: pass
arm64_za-ptrace_Set_VL_4384: pass
arm64_za-ptrace_Set_VL_4400: pass
arm64_za-ptrace_Set_VL_4416: pass
arm64_za-ptrace_Set_VL_4432: pass
arm64_za-ptrace_Set_VL_4448: pass
arm64_za-ptrace_Set_VL_4464: pass
arm64_za-ptrace_Set_VL_448: pass
arm64_za-ptrace_Set_VL_4480: pass
arm64_za-ptrace_Set_VL_4496: pass
arm64_za-ptrace_Set_VL_4512: pass
arm64_za-ptrace_Set_VL_4528: pass
arm64_za-ptrace_Set_VL_4544: pass
arm64_za-ptrace_Set_VL_4560: pass
arm64_za-ptrace_Set_VL_4576: pass
arm64_za-ptrace_Set_VL_4592: pass
arm64_za-ptrace_Set_VL_4608: pass
arm64_za-ptrace_Set_VL_4624: pass
arm64_za-ptrace_Set_VL_464: pass
arm64_za-ptrace_Set_VL_4640: pass
arm64_za-ptrace_Set_VL_4656: pass
arm64_za-ptrace_Set_VL_4672: pass
arm64_za-ptrace_Set_VL_4688: pass
arm64_za-ptrace_Set_VL_4704: pass
arm64_za-ptrace_Set_VL_4720: pass
arm64_za-ptrace_Set_VL_4736: pass
arm64_za-ptrace_Set_VL_4752: pass
arm64_za-ptrace_Set_VL_4768: pass
arm64_za-ptrace_Set_VL_4784: pass
arm64_za-ptrace_Set_VL_48: pass
arm64_za-ptrace_Set_VL_480: pass
arm64_za-ptrace_Set_VL_4800: pass
arm64_za-ptrace_Set_VL_4816: pass
arm64_za-ptrace_Set_VL_4832: pass
arm64_za-ptrace_Set_VL_4848: pass
arm64_za-ptrace_Set_VL_4864: pass
arm64_za-ptrace_Set_VL_4880: pass
arm64_za-ptrace_Set_VL_4896: pass
arm64_za-ptrace_Set_VL_4912: pass
arm64_za-ptrace_Set_VL_4928: pass
arm64_za-ptrace_Set_VL_4944: pass
arm64_za-ptrace_Set_VL_496: pass
arm64_za-ptrace_Set_VL_4960: pass
arm64_za-ptrace_Set_VL_4976: pass
arm64_za-ptrace_Set_VL_4992: pass
arm64_za-ptrace_Set_VL_5008: pass
arm64_za-ptrace_Set_VL_5024: pass
arm64_za-ptrace_Set_VL_5040: pass
arm64_za-ptrace_Set_VL_5056: pass
arm64_za-ptrace_Set_VL_5072: pass
arm64_za-ptrace_Set_VL_5088: pass
arm64_za-ptrace_Set_VL_5104: pass
arm64_za-ptrace_Set_VL_512: pass
arm64_za-ptrace_Set_VL_5120: pass
arm64_za-ptrace_Set_VL_5136: pass
arm64_za-ptrace_Set_VL_5152: pass
arm64_za-ptrace_Set_VL_5168: pass
arm64_za-ptrace_Set_VL_5184: pass
arm64_za-ptrace_Set_VL_5200: pass
arm64_za-ptrace_Set_VL_5216: pass
arm64_za-ptrace_Set_VL_5232: pass
arm64_za-ptrace_Set_VL_5248: pass
arm64_za-ptrace_Set_VL_5264: pass
arm64_za-ptrace_Set_VL_528: pass
arm64_za-ptrace_Set_VL_5280: pass
arm64_za-ptrace_Set_VL_5296: pass
arm64_za-ptrace_Set_VL_5312: pass
arm64_za-ptrace_Set_VL_5328: pass
arm64_za-ptrace_Set_VL_5344: pass
arm64_za-ptrace_Set_VL_5360: pass
arm64_za-ptrace_Set_VL_5376: pass
arm64_za-ptrace_Set_VL_5392: pass
arm64_za-ptrace_Set_VL_5408: pass
arm64_za-ptrace_Set_VL_5424: pass
arm64_za-ptrace_Set_VL_544: pass
arm64_za-ptrace_Set_VL_5440: pass
arm64_za-ptrace_Set_VL_5456: pass
arm64_za-ptrace_Set_VL_5472: pass
arm64_za-ptrace_Set_VL_5488: pass
arm64_za-ptrace_Set_VL_5504: pass
arm64_za-ptrace_Set_VL_5520: pass
arm64_za-ptrace_Set_VL_5536: pass
arm64_za-ptrace_Set_VL_5552: pass
arm64_za-ptrace_Set_VL_5568: pass
arm64_za-ptrace_Set_VL_5584: pass
arm64_za-ptrace_Set_VL_560: pass
arm64_za-ptrace_Set_VL_5600: pass
arm64_za-ptrace_Set_VL_5616: pass
arm64_za-ptrace_Set_VL_5632: pass
arm64_za-ptrace_Set_VL_5648: pass
arm64_za-ptrace_Set_VL_5664: pass
arm64_za-ptrace_Set_VL_5680: pass
arm64_za-ptrace_Set_VL_5696: pass
arm64_za-ptrace_Set_VL_5712: pass
arm64_za-ptrace_Set_VL_5728: pass
arm64_za-ptrace_Set_VL_5744: pass
arm64_za-ptrace_Set_VL_576: pass
arm64_za-ptrace_Set_VL_5760: pass
arm64_za-ptrace_Set_VL_5776: pass
arm64_za-ptrace_Set_VL_5792: pass
arm64_za-ptrace_Set_VL_5808: pass
arm64_za-ptrace_Set_VL_5824: pass
arm64_za-ptrace_Set_VL_5840: pass
arm64_za-ptrace_Set_VL_5856: pass
arm64_za-ptrace_Set_VL_5872: pass
arm64_za-ptrace_Set_VL_5888: pass
arm64_za-ptrace_Set_VL_5904: pass
arm64_za-ptrace_Set_VL_592: pass
arm64_za-ptrace_Set_VL_5920: pass
arm64_za-ptrace_Set_VL_5936: pass
arm64_za-ptrace_Set_VL_5952: pass
arm64_za-ptrace_Set_VL_5968: pass
arm64_za-ptrace_Set_VL_5984: pass
arm64_za-ptrace_Set_VL_6000: pass
arm64_za-ptrace_Set_VL_6016: pass
arm64_za-ptrace_Set_VL_6032: pass
arm64_za-ptrace_Set_VL_6048: pass
arm64_za-ptrace_Set_VL_6064: pass
arm64_za-ptrace_Set_VL_608: pass
arm64_za-ptrace_Set_VL_6080: pass
arm64_za-ptrace_Set_VL_6096: pass
arm64_za-ptrace_Set_VL_6112: pass
arm64_za-ptrace_Set_VL_6128: pass
arm64_za-ptrace_Set_VL_6144: pass
arm64_za-ptrace_Set_VL_6160: pass
arm64_za-ptrace_Set_VL_6176: pass
arm64_za-ptrace_Set_VL_6192: pass
arm64_za-ptrace_Set_VL_6208: pass
arm64_za-ptrace_Set_VL_6224: pass
arm64_za-ptrace_Set_VL_624: pass
arm64_za-ptrace_Set_VL_6240: pass
arm64_za-ptrace_Set_VL_6256: pass
arm64_za-ptrace_Set_VL_6272: pass
arm64_za-ptrace_Set_VL_6288: pass
arm64_za-ptrace_Set_VL_6304: pass
arm64_za-ptrace_Set_VL_6320: pass
arm64_za-ptrace_Set_VL_6336: pass
arm64_za-ptrace_Set_VL_6352: pass
arm64_za-ptrace_Set_VL_6368: pass
arm64_za-ptrace_Set_VL_6384: pass
arm64_za-ptrace_Set_VL_64: pass
arm64_za-ptrace_Set_VL_640: pass
arm64_za-ptrace_Set_VL_6400: pass
arm64_za-ptrace_Set_VL_6416: pass
arm64_za-ptrace_Set_VL_6432: pass
arm64_za-ptrace_Set_VL_6448: pass
arm64_za-ptrace_Set_VL_6464: pass
arm64_za-ptrace_Set_VL_6480: pass
arm64_za-ptrace_Set_VL_6496: pass
arm64_za-ptrace_Set_VL_6512: pass
arm64_za-ptrace_Set_VL_6528: pass
arm64_za-ptrace_Set_VL_6544: pass
arm64_za-ptrace_Set_VL_656: pass
arm64_za-ptrace_Set_VL_6560: pass
arm64_za-ptrace_Set_VL_6576: pass
arm64_za-ptrace_Set_VL_6592: pass
arm64_za-ptrace_Set_VL_6608: pass
arm64_za-ptrace_Set_VL_6624: pass
arm64_za-ptrace_Set_VL_6640: pass
arm64_za-ptrace_Set_VL_6656: pass
arm64_za-ptrace_Set_VL_6672: pass
arm64_za-ptrace_Set_VL_6688: pass
arm64_za-ptrace_Set_VL_6704: pass
arm64_za-ptrace_Set_VL_672: pass
arm64_za-ptrace_Set_VL_6720: pass
arm64_za-ptrace_Set_VL_6736: pass
arm64_za-ptrace_Set_VL_6752: pass
arm64_za-ptrace_Set_VL_6768: pass
arm64_za-ptrace_Set_VL_6784: pass
arm64_za-ptrace_Set_VL_6800: pass
arm64_za-ptrace_Set_VL_6816: pass
arm64_za-ptrace_Set_VL_6832: pass
arm64_za-ptrace_Set_VL_6848: pass
arm64_za-ptrace_Set_VL_6864: pass
arm64_za-ptrace_Set_VL_688: pass
arm64_za-ptrace_Set_VL_6880: pass
arm64_za-ptrace_Set_VL_6896: pass
arm64_za-ptrace_Set_VL_6912: pass
arm64_za-ptrace_Set_VL_6928: pass
arm64_za-ptrace_Set_VL_6944: pass
arm64_za-ptrace_Set_VL_6960: pass
arm64_za-ptrace_Set_VL_6976: pass
arm64_za-ptrace_Set_VL_6992: pass
arm64_za-ptrace_Set_VL_7008: pass
arm64_za-ptrace_Set_VL_7024: pass
arm64_za-ptrace_Set_VL_704: pass
arm64_za-ptrace_Set_VL_7040: pass
arm64_za-ptrace_Set_VL_7056: pass
arm64_za-ptrace_Set_VL_7072: pass
arm64_za-ptrace_Set_VL_7088: pass
arm64_za-ptrace_Set_VL_7104: pass
arm64_za-ptrace_Set_VL_7120: pass
arm64_za-ptrace_Set_VL_7136: pass
arm64_za-ptrace_Set_VL_7152: pass
arm64_za-ptrace_Set_VL_7168: pass
arm64_za-ptrace_Set_VL_7184: pass
arm64_za-ptrace_Set_VL_720: pass
arm64_za-ptrace_Set_VL_7200: pass
arm64_za-ptrace_Set_VL_7216: pass
arm64_za-ptrace_Set_VL_7232: pass
arm64_za-ptrace_Set_VL_7248: pass
arm64_za-ptrace_Set_VL_7264: pass
arm64_za-ptrace_Set_VL_7280: pass
arm64_za-ptrace_Set_VL_7296: pass
arm64_za-ptrace_Set_VL_7312: pass
arm64_za-ptrace_Set_VL_7328: pass
arm64_za-ptrace_Set_VL_7344: pass
arm64_za-ptrace_Set_VL_736: pass
arm64_za-ptrace_Set_VL_7360: pass
arm64_za-ptrace_Set_VL_7376: pass
arm64_za-ptrace_Set_VL_7392: pass
arm64_za-ptrace_Set_VL_7408: pass
arm64_za-ptrace_Set_VL_7424: pass
arm64_za-ptrace_Set_VL_7440: pass
arm64_za-ptrace_Set_VL_7456: pass
arm64_za-ptrace_Set_VL_7472: pass
arm64_za-ptrace_Set_VL_7488: pass
arm64_za-ptrace_Set_VL_7504: pass
arm64_za-ptrace_Set_VL_752: pass
arm64_za-ptrace_Set_VL_7520: pass
arm64_za-ptrace_Set_VL_7536: pass
arm64_za-ptrace_Set_VL_7552: pass
arm64_za-ptrace_Set_VL_7568: pass
arm64_za-ptrace_Set_VL_7584: pass
arm64_za-ptrace_Set_VL_7600: pass
arm64_za-ptrace_Set_VL_7616: pass
arm64_za-ptrace_Set_VL_7632: pass
arm64_za-ptrace_Set_VL_7648: pass
arm64_za-ptrace_Set_VL_7664: pass
arm64_za-ptrace_Set_VL_768: pass
arm64_za-ptrace_Set_VL_7680: pass
arm64_za-ptrace_Set_VL_7696: pass
arm64_za-ptrace_Set_VL_7712: pass
arm64_za-ptrace_Set_VL_7728: pass
arm64_za-ptrace_Set_VL_7744: pass
arm64_za-ptrace_Set_VL_7760: pass
arm64_za-ptrace_Set_VL_7776: pass
arm64_za-ptrace_Set_VL_7792: pass
arm64_za-ptrace_Set_VL_7808: pass
arm64_za-ptrace_Set_VL_7824: pass
arm64_za-ptrace_Set_VL_784: pass
arm64_za-ptrace_Set_VL_7840: pass
arm64_za-ptrace_Set_VL_7856: pass
arm64_za-ptrace_Set_VL_7872: pass
arm64_za-ptrace_Set_VL_7888: pass
arm64_za-ptrace_Set_VL_7904: pass
arm64_za-ptrace_Set_VL_7920: pass
arm64_za-ptrace_Set_VL_7936: pass
arm64_za-ptrace_Set_VL_7952: pass
arm64_za-ptrace_Set_VL_7968: pass
arm64_za-ptrace_Set_VL_7984: pass
arm64_za-ptrace_Set_VL_80: pass
arm64_za-ptrace_Set_VL_800: pass
arm64_za-ptrace_Set_VL_8000: pass
arm64_za-ptrace_Set_VL_8016: pass
arm64_za-ptrace_Set_VL_8032: pass
arm64_za-ptrace_Set_VL_8048: pass
arm64_za-ptrace_Set_VL_8064: pass
arm64_za-ptrace_Set_VL_8080: pass
arm64_za-ptrace_Set_VL_8096: pass
arm64_za-ptrace_Set_VL_8112: pass
arm64_za-ptrace_Set_VL_8128: pass
arm64_za-ptrace_Set_VL_8144: pass
arm64_za-ptrace_Set_VL_816: pass
arm64_za-ptrace_Set_VL_8160: pass
arm64_za-ptrace_Set_VL_8176: pass
arm64_za-ptrace_Set_VL_8192: pass
arm64_za-ptrace_Set_VL_832: pass
arm64_za-ptrace_Set_VL_848: pass
arm64_za-ptrace_Set_VL_864: pass
arm64_za-ptrace_Set_VL_880: pass
arm64_za-ptrace_Set_VL_896: pass
arm64_za-ptrace_Set_VL_912: pass
arm64_za-ptrace_Set_VL_928: pass
arm64_za-ptrace_Set_VL_944: pass
arm64_za-ptrace_Set_VL_96: pass
arm64_za-ptrace_Set_VL_960: pass
arm64_za-ptrace_Set_VL_976: pass
arm64_za-ptrace_Set_VL_992: pass
arm64_za_no_regs: pass
arm64_za_regs: pass
34725 10:59:27.192350 end: 3.1 lava-test-shell (duration 00:06:18) [common]
34726 10:59:27.192515 end: 3 lava-test-retry (duration 00:06:18) [common]
34727 10:59:27.192654 start: 4 finalize (timeout 00:02:32) [common]
34728 10:59:27.192788 start: 4.1 power-off (timeout 00:00:30) [common]
34729 10:59:27.192908 end: 4.1 power-off (duration 00:00:00) [common]
34730 10:59:27.193027 start: 4.2 read-feedback (timeout 00:02:32) [common]
34732 10:59:27.193603 Listened to connection for namespace 'common' for up to 1s
34733 10:59:28.197755 Finalising connection for namespace 'common'
34735 10:59:28.298718 / # poweroff
34736 10:59:28.299184 Already disconnected
34737 10:59:28.299308 poweroff
34738 10:59:28.400293 end: 4.2 read-feedback (duration 00:00:01) [common]
34739 10:59:28.400543 Already disconnected
34740 10:59:28.400662 end: 4 finalize (duration 00:00:01) [common]
34741 10:59:28.400793 Cleaning after the job
34742 10:59:28.400948 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/562531/deployimages-utwxp42y/kernel
34743 10:59:28.407224 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/562531/deployimages-utwxp42y/ramdisk
34744 10:59:28.421079 Stopping the qemu container lava-docker-qemu-562531-2.1.1-qhtg20u02p
34745 10:59:29.537371 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/562531
34746 10:59:29.611076 Job finished correctly