Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 37
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 30
1 22:17:04.671467 lava-dispatcher, installed at version: 2023.05.1
2 22:17:04.671669 start: 0 validate
3 22:17:04.671798 Start time: 2023-06-05 22:17:04.671790+00:00 (UTC)
4 22:17:04.671918 Using caching service: 'http://localhost/cache/?uri=%s'
5 22:17:04.672071 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20230527.0%2Farm64%2Finitrd.cpio.gz exists
6 22:17:04.987560 Using caching service: 'http://localhost/cache/?uri=%s'
7 22:17:04.988504 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1314-g1ab0ac1d7e2e3%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 22:17:05.297785 Using caching service: 'http://localhost/cache/?uri=%s'
9 22:17:05.298735 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1314-g1ab0ac1d7e2e3%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 22:17:05.612117 Using caching service: 'http://localhost/cache/?uri=%s'
11 22:17:05.612823 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20230527.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 22:17:05.912809 Using caching service: 'http://localhost/cache/?uri=%s'
13 22:17:05.913505 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1314-g1ab0ac1d7e2e3%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 22:17:06.226334 validate duration: 1.55
16 22:17:06.227481 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 22:17:06.227969 start: 1.1 download-retry (timeout 00:10:00) [common]
18 22:17:06.228455 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 22:17:06.229034 Not decompressing ramdisk as can be used compressed.
20 22:17:06.229459 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20230527.0/arm64/initrd.cpio.gz
21 22:17:06.229789 saving as /var/lib/lava/dispatcher/tmp/10597265/tftp-deploy-dqirrpjl/ramdisk/initrd.cpio.gz
22 22:17:06.230105 total size: 5624321 (5MB)
23 22:17:06.235056 progress 0% (0MB)
24 22:17:06.243290 progress 5% (0MB)
25 22:17:06.251224 progress 10% (0MB)
26 22:17:06.256985 progress 15% (0MB)
27 22:17:06.261564 progress 20% (1MB)
28 22:17:06.265076 progress 25% (1MB)
29 22:17:06.268454 progress 30% (1MB)
30 22:17:06.271259 progress 35% (1MB)
31 22:17:06.273715 progress 40% (2MB)
32 22:17:06.276116 progress 45% (2MB)
33 22:17:06.278255 progress 50% (2MB)
34 22:17:06.280396 progress 55% (2MB)
35 22:17:06.282276 progress 60% (3MB)
36 22:17:06.284287 progress 65% (3MB)
37 22:17:06.286022 progress 70% (3MB)
38 22:17:06.287371 progress 75% (4MB)
39 22:17:06.288921 progress 80% (4MB)
40 22:17:06.290272 progress 85% (4MB)
41 22:17:06.291780 progress 90% (4MB)
42 22:17:06.293323 progress 95% (5MB)
43 22:17:06.294693 progress 100% (5MB)
44 22:17:06.294878 5MB downloaded in 0.06s (82.80MB/s)
45 22:17:06.295038 end: 1.1.1 http-download (duration 00:00:00) [common]
47 22:17:06.295287 end: 1.1 download-retry (duration 00:00:00) [common]
48 22:17:06.295373 start: 1.2 download-retry (timeout 00:10:00) [common]
49 22:17:06.295456 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 22:17:06.295585 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1314-g1ab0ac1d7e2e3/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 22:17:06.295657 saving as /var/lib/lava/dispatcher/tmp/10597265/tftp-deploy-dqirrpjl/kernel/Image
52 22:17:06.295718 total size: 45746688 (43MB)
53 22:17:06.295777 No compression specified
54 22:17:06.296954 progress 0% (0MB)
55 22:17:06.308439 progress 5% (2MB)
56 22:17:06.319838 progress 10% (4MB)
57 22:17:06.331325 progress 15% (6MB)
58 22:17:06.342876 progress 20% (8MB)
59 22:17:06.354491 progress 25% (10MB)
60 22:17:06.365975 progress 30% (13MB)
61 22:17:06.377607 progress 35% (15MB)
62 22:17:06.389149 progress 40% (17MB)
63 22:17:06.400632 progress 45% (19MB)
64 22:17:06.412194 progress 50% (21MB)
65 22:17:06.423500 progress 55% (24MB)
66 22:17:06.434936 progress 60% (26MB)
67 22:17:06.446476 progress 65% (28MB)
68 22:17:06.458117 progress 70% (30MB)
69 22:17:06.469688 progress 75% (32MB)
70 22:17:06.481105 progress 80% (34MB)
71 22:17:06.492635 progress 85% (37MB)
72 22:17:06.504199 progress 90% (39MB)
73 22:17:06.515576 progress 95% (41MB)
74 22:17:06.526822 progress 100% (43MB)
75 22:17:06.526942 43MB downloaded in 0.23s (188.68MB/s)
76 22:17:06.527085 end: 1.2.1 http-download (duration 00:00:00) [common]
78 22:17:06.527313 end: 1.2 download-retry (duration 00:00:00) [common]
79 22:17:06.527404 start: 1.3 download-retry (timeout 00:10:00) [common]
80 22:17:06.527491 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 22:17:06.527623 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1314-g1ab0ac1d7e2e3/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 22:17:06.527693 saving as /var/lib/lava/dispatcher/tmp/10597265/tftp-deploy-dqirrpjl/dtb/mt8192-asurada-spherion-r0.dtb
83 22:17:06.527758 total size: 46924 (0MB)
84 22:17:06.527817 No compression specified
85 22:17:06.528964 progress 69% (0MB)
86 22:17:06.529232 progress 100% (0MB)
87 22:17:06.529383 0MB downloaded in 0.00s (27.57MB/s)
88 22:17:06.529503 end: 1.3.1 http-download (duration 00:00:00) [common]
90 22:17:06.529722 end: 1.3 download-retry (duration 00:00:00) [common]
91 22:17:06.529807 start: 1.4 download-retry (timeout 00:10:00) [common]
92 22:17:06.529889 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 22:17:06.529996 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20230527.0/arm64/full.rootfs.tar.xz
94 22:17:06.530064 saving as /var/lib/lava/dispatcher/tmp/10597265/tftp-deploy-dqirrpjl/nfsrootfs/full.rootfs.tar
95 22:17:06.530124 total size: 195125384 (186MB)
96 22:17:06.530184 Using unxz to decompress xz
97 22:17:06.533808 progress 0% (0MB)
98 22:17:07.072369 progress 5% (9MB)
99 22:17:07.575427 progress 10% (18MB)
100 22:17:08.141963 progress 15% (27MB)
101 22:17:08.412855 progress 20% (37MB)
102 22:17:08.855440 progress 25% (46MB)
103 22:17:09.414382 progress 30% (55MB)
104 22:17:09.955170 progress 35% (65MB)
105 22:17:10.509367 progress 40% (74MB)
106 22:17:11.101165 progress 45% (83MB)
107 22:17:11.733378 progress 50% (93MB)
108 22:17:12.356996 progress 55% (102MB)
109 22:17:13.022590 progress 60% (111MB)
110 22:17:13.423411 progress 65% (120MB)
111 22:17:13.502034 progress 70% (130MB)
112 22:17:13.653894 progress 75% (139MB)
113 22:17:13.727008 progress 80% (148MB)
114 22:17:13.773801 progress 85% (158MB)
115 22:17:13.866251 progress 90% (167MB)
116 22:17:14.255868 progress 95% (176MB)
117 22:17:14.838629 progress 100% (186MB)
118 22:17:14.844755 186MB downloaded in 8.31s (22.38MB/s)
119 22:17:14.845050 end: 1.4.1 http-download (duration 00:00:08) [common]
121 22:17:14.845314 end: 1.4 download-retry (duration 00:00:08) [common]
122 22:17:14.845408 start: 1.5 download-retry (timeout 00:09:51) [common]
123 22:17:14.845497 start: 1.5.1 http-download (timeout 00:09:51) [common]
124 22:17:14.845643 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1314-g1ab0ac1d7e2e3/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 22:17:14.845717 saving as /var/lib/lava/dispatcher/tmp/10597265/tftp-deploy-dqirrpjl/modules/modules.tar
126 22:17:14.845779 total size: 8543056 (8MB)
127 22:17:14.845842 Using unxz to decompress xz
128 22:17:14.849447 progress 0% (0MB)
129 22:17:14.871467 progress 5% (0MB)
130 22:17:14.897247 progress 10% (0MB)
131 22:17:14.923567 progress 15% (1MB)
132 22:17:14.948777 progress 20% (1MB)
133 22:17:14.972492 progress 25% (2MB)
134 22:17:14.999492 progress 30% (2MB)
135 22:17:15.024547 progress 35% (2MB)
136 22:17:15.048893 progress 40% (3MB)
137 22:17:15.073043 progress 45% (3MB)
138 22:17:15.098043 progress 50% (4MB)
139 22:17:15.121858 progress 55% (4MB)
140 22:17:15.147135 progress 60% (4MB)
141 22:17:15.174135 progress 65% (5MB)
142 22:17:15.198826 progress 70% (5MB)
143 22:17:15.222619 progress 75% (6MB)
144 22:17:15.246820 progress 80% (6MB)
145 22:17:15.272342 progress 85% (6MB)
146 22:17:15.301438 progress 90% (7MB)
147 22:17:15.327728 progress 95% (7MB)
148 22:17:15.352096 progress 100% (8MB)
149 22:17:15.357879 8MB downloaded in 0.51s (15.91MB/s)
150 22:17:15.358161 end: 1.5.1 http-download (duration 00:00:01) [common]
152 22:17:15.358450 end: 1.5 download-retry (duration 00:00:01) [common]
153 22:17:15.358559 start: 1.6 prepare-tftp-overlay (timeout 00:09:51) [common]
154 22:17:15.358667 start: 1.6.1 extract-nfsrootfs (timeout 00:09:51) [common]
155 22:17:18.795270 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/10597265/extract-nfsrootfs-jdvhjo22
156 22:17:18.795484 end: 1.6.1 extract-nfsrootfs (duration 00:00:03) [common]
157 22:17:18.795592 start: 1.6.2 lava-overlay (timeout 00:09:47) [common]
158 22:17:18.795757 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/10597265/lava-overlay-j4waxh_q
159 22:17:18.795886 makedir: /var/lib/lava/dispatcher/tmp/10597265/lava-overlay-j4waxh_q/lava-10597265/bin
160 22:17:18.796017 makedir: /var/lib/lava/dispatcher/tmp/10597265/lava-overlay-j4waxh_q/lava-10597265/tests
161 22:17:18.796156 makedir: /var/lib/lava/dispatcher/tmp/10597265/lava-overlay-j4waxh_q/lava-10597265/results
162 22:17:18.796261 Creating /var/lib/lava/dispatcher/tmp/10597265/lava-overlay-j4waxh_q/lava-10597265/bin/lava-add-keys
163 22:17:18.796397 Creating /var/lib/lava/dispatcher/tmp/10597265/lava-overlay-j4waxh_q/lava-10597265/bin/lava-add-sources
164 22:17:18.796527 Creating /var/lib/lava/dispatcher/tmp/10597265/lava-overlay-j4waxh_q/lava-10597265/bin/lava-background-process-start
165 22:17:18.796650 Creating /var/lib/lava/dispatcher/tmp/10597265/lava-overlay-j4waxh_q/lava-10597265/bin/lava-background-process-stop
166 22:17:18.796776 Creating /var/lib/lava/dispatcher/tmp/10597265/lava-overlay-j4waxh_q/lava-10597265/bin/lava-common-functions
167 22:17:18.796921 Creating /var/lib/lava/dispatcher/tmp/10597265/lava-overlay-j4waxh_q/lava-10597265/bin/lava-echo-ipv4
168 22:17:18.797061 Creating /var/lib/lava/dispatcher/tmp/10597265/lava-overlay-j4waxh_q/lava-10597265/bin/lava-install-packages
169 22:17:18.797180 Creating /var/lib/lava/dispatcher/tmp/10597265/lava-overlay-j4waxh_q/lava-10597265/bin/lava-installed-packages
170 22:17:18.797298 Creating /var/lib/lava/dispatcher/tmp/10597265/lava-overlay-j4waxh_q/lava-10597265/bin/lava-os-build
171 22:17:18.797417 Creating /var/lib/lava/dispatcher/tmp/10597265/lava-overlay-j4waxh_q/lava-10597265/bin/lava-probe-channel
172 22:17:18.797537 Creating /var/lib/lava/dispatcher/tmp/10597265/lava-overlay-j4waxh_q/lava-10597265/bin/lava-probe-ip
173 22:17:18.797654 Creating /var/lib/lava/dispatcher/tmp/10597265/lava-overlay-j4waxh_q/lava-10597265/bin/lava-target-ip
174 22:17:18.797774 Creating /var/lib/lava/dispatcher/tmp/10597265/lava-overlay-j4waxh_q/lava-10597265/bin/lava-target-mac
175 22:17:18.797907 Creating /var/lib/lava/dispatcher/tmp/10597265/lava-overlay-j4waxh_q/lava-10597265/bin/lava-target-storage
176 22:17:18.798063 Creating /var/lib/lava/dispatcher/tmp/10597265/lava-overlay-j4waxh_q/lava-10597265/bin/lava-test-case
177 22:17:18.798187 Creating /var/lib/lava/dispatcher/tmp/10597265/lava-overlay-j4waxh_q/lava-10597265/bin/lava-test-event
178 22:17:18.798307 Creating /var/lib/lava/dispatcher/tmp/10597265/lava-overlay-j4waxh_q/lava-10597265/bin/lava-test-feedback
179 22:17:18.798444 Creating /var/lib/lava/dispatcher/tmp/10597265/lava-overlay-j4waxh_q/lava-10597265/bin/lava-test-raise
180 22:17:18.798582 Creating /var/lib/lava/dispatcher/tmp/10597265/lava-overlay-j4waxh_q/lava-10597265/bin/lava-test-reference
181 22:17:18.798700 Creating /var/lib/lava/dispatcher/tmp/10597265/lava-overlay-j4waxh_q/lava-10597265/bin/lava-test-runner
182 22:17:18.798818 Creating /var/lib/lava/dispatcher/tmp/10597265/lava-overlay-j4waxh_q/lava-10597265/bin/lava-test-set
183 22:17:18.798936 Creating /var/lib/lava/dispatcher/tmp/10597265/lava-overlay-j4waxh_q/lava-10597265/bin/lava-test-shell
184 22:17:18.799055 Updating /var/lib/lava/dispatcher/tmp/10597265/lava-overlay-j4waxh_q/lava-10597265/bin/lava-add-keys (debian)
185 22:17:18.799206 Updating /var/lib/lava/dispatcher/tmp/10597265/lava-overlay-j4waxh_q/lava-10597265/bin/lava-add-sources (debian)
186 22:17:18.799343 Updating /var/lib/lava/dispatcher/tmp/10597265/lava-overlay-j4waxh_q/lava-10597265/bin/lava-install-packages (debian)
187 22:17:18.799547 Updating /var/lib/lava/dispatcher/tmp/10597265/lava-overlay-j4waxh_q/lava-10597265/bin/lava-installed-packages (debian)
188 22:17:18.799695 Updating /var/lib/lava/dispatcher/tmp/10597265/lava-overlay-j4waxh_q/lava-10597265/bin/lava-os-build (debian)
189 22:17:18.799819 Creating /var/lib/lava/dispatcher/tmp/10597265/lava-overlay-j4waxh_q/lava-10597265/environment
190 22:17:18.799999 LAVA metadata
191 22:17:18.800283 - LAVA_JOB_ID=10597265
192 22:17:18.800354 - LAVA_DISPATCHER_IP=192.168.201.1
193 22:17:18.800491 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:47) [common]
194 22:17:18.800577 skipped lava-vland-overlay
195 22:17:18.800656 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 22:17:18.800736 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:47) [common]
197 22:17:18.800798 skipped lava-multinode-overlay
198 22:17:18.800870 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 22:17:18.800948 start: 1.6.2.3 test-definition (timeout 00:09:47) [common]
200 22:17:18.801084 Loading test definitions
201 22:17:18.801176 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:47) [common]
202 22:17:18.801246 Using /lava-10597265 at stage 0
203 22:17:18.801507 uuid=10597265_1.6.2.3.1 testdef=None
204 22:17:18.801596 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 22:17:18.801744 start: 1.6.2.3.2 test-overlay (timeout 00:09:47) [common]
206 22:17:18.802214 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 22:17:18.802438 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:47) [common]
209 22:17:18.802976 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 22:17:18.803205 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:47) [common]
212 22:17:18.803729 runner path: /var/lib/lava/dispatcher/tmp/10597265/lava-overlay-j4waxh_q/lava-10597265/0/tests/0_timesync-off test_uuid 10597265_1.6.2.3.1
213 22:17:18.803879 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 22:17:18.804176 start: 1.6.2.3.5 git-repo-action (timeout 00:09:47) [common]
216 22:17:18.804279 Using /lava-10597265 at stage 0
217 22:17:18.804374 Fetching tests from https://github.com/kernelci/test-definitions.git
218 22:17:18.804452 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/10597265/lava-overlay-j4waxh_q/lava-10597265/0/tests/1_kselftest-alsa'
219 22:17:24.495445 Running '/usr/bin/git checkout kernelci.org
220 22:17:24.641819 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/10597265/lava-overlay-j4waxh_q/lava-10597265/0/tests/1_kselftest-alsa/automated/linux/kselftest/kselftest.yaml
221 22:17:24.642536 uuid=10597265_1.6.2.3.5 testdef=None
222 22:17:24.642695 end: 1.6.2.3.5 git-repo-action (duration 00:00:06) [common]
224 22:17:24.642946 start: 1.6.2.3.6 test-overlay (timeout 00:09:42) [common]
225 22:17:24.643683 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 22:17:24.643912 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:42) [common]
228 22:17:24.644888 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 22:17:24.645121 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:42) [common]
231 22:17:24.646044 runner path: /var/lib/lava/dispatcher/tmp/10597265/lava-overlay-j4waxh_q/lava-10597265/0/tests/1_kselftest-alsa test_uuid 10597265_1.6.2.3.5
232 22:17:24.646137 BOARD='mt8192-asurada-spherion-r0'
233 22:17:24.646203 BRANCH='cip-gitlab'
234 22:17:24.646265 SKIPFILE='/dev/null'
235 22:17:24.646325 SKIP_INSTALL='True'
236 22:17:24.646382 TESTPROG_URL='http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1314-g1ab0ac1d7e2e3/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 22:17:24.646441 TST_CASENAME=''
238 22:17:24.646498 TST_CMDFILES='alsa'
239 22:17:24.646637 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 22:17:24.646840 Creating lava-test-runner.conf files
242 22:17:24.646905 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10597265/lava-overlay-j4waxh_q/lava-10597265/0 for stage 0
243 22:17:24.646996 - 0_timesync-off
244 22:17:24.647064 - 1_kselftest-alsa
245 22:17:24.647156 end: 1.6.2.3 test-definition (duration 00:00:06) [common]
246 22:17:24.647251 start: 1.6.2.4 compress-overlay (timeout 00:09:42) [common]
247 22:17:32.130684 end: 1.6.2.4 compress-overlay (duration 00:00:07) [common]
248 22:17:32.130832 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:34) [common]
249 22:17:32.130961 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 22:17:32.131062 end: 1.6.2 lava-overlay (duration 00:00:13) [common]
251 22:17:32.131153 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:34) [common]
252 22:17:32.294950 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 22:17:32.295313 start: 1.6.4 extract-modules (timeout 00:09:34) [common]
254 22:17:32.295435 extracting modules file /var/lib/lava/dispatcher/tmp/10597265/tftp-deploy-dqirrpjl/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10597265/extract-nfsrootfs-jdvhjo22
255 22:17:32.509182 extracting modules file /var/lib/lava/dispatcher/tmp/10597265/tftp-deploy-dqirrpjl/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10597265/extract-overlay-ramdisk-6keffyu1/ramdisk
256 22:17:32.717529 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 22:17:32.717697 start: 1.6.5 apply-overlay-tftp (timeout 00:09:34) [common]
258 22:17:32.717791 [common] Applying overlay to NFS
259 22:17:32.717862 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10597265/compress-overlay-_trr_yl5/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/10597265/extract-nfsrootfs-jdvhjo22
260 22:17:33.614969 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 22:17:33.615138 start: 1.6.6 configure-preseed-file (timeout 00:09:33) [common]
262 22:17:33.615234 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 22:17:33.615324 start: 1.6.7 compress-ramdisk (timeout 00:09:33) [common]
264 22:17:33.615406 Building ramdisk /var/lib/lava/dispatcher/tmp/10597265/extract-overlay-ramdisk-6keffyu1/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/10597265/extract-overlay-ramdisk-6keffyu1/ramdisk
265 22:17:33.948205 >> 128929 blocks
266 22:17:36.025130 rename /var/lib/lava/dispatcher/tmp/10597265/extract-overlay-ramdisk-6keffyu1/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/10597265/tftp-deploy-dqirrpjl/ramdisk/ramdisk.cpio.gz
267 22:17:36.025573 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 22:17:36.025744 start: 1.6.8 prepare-kernel (timeout 00:09:30) [common]
269 22:17:36.025849 start: 1.6.8.1 prepare-fit (timeout 00:09:30) [common]
270 22:17:36.025948 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/10597265/tftp-deploy-dqirrpjl/kernel/Image'
271 22:17:47.959797 Returned 0 in 11 seconds
272 22:17:48.060444 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/10597265/tftp-deploy-dqirrpjl/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/10597265/tftp-deploy-dqirrpjl/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/10597265/tftp-deploy-dqirrpjl/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/10597265/tftp-deploy-dqirrpjl/kernel/image.itb
273 22:17:48.396735 output: FIT description: Kernel Image image with one or more FDT blobs
274 22:17:48.397092 output: Created: Mon Jun 5 23:17:48 2023
275 22:17:48.397207 output: Image 0 (kernel-1)
276 22:17:48.397295 output: Description:
277 22:17:48.397376 output: Created: Mon Jun 5 23:17:48 2023
278 22:17:48.397459 output: Type: Kernel Image
279 22:17:48.397560 output: Compression: lzma compressed
280 22:17:48.397660 output: Data Size: 10082307 Bytes = 9846.00 KiB = 9.62 MiB
281 22:17:48.397767 output: Architecture: AArch64
282 22:17:48.397849 output: OS: Linux
283 22:17:48.397949 output: Load Address: 0x00000000
284 22:17:48.398046 output: Entry Point: 0x00000000
285 22:17:48.398144 output: Hash algo: crc32
286 22:17:48.398237 output: Hash value: c242daf7
287 22:17:48.398337 output: Image 1 (fdt-1)
288 22:17:48.398433 output: Description: mt8192-asurada-spherion-r0
289 22:17:48.398525 output: Created: Mon Jun 5 23:17:48 2023
290 22:17:48.398618 output: Type: Flat Device Tree
291 22:17:48.398709 output: Compression: uncompressed
292 22:17:48.398801 output: Data Size: 46924 Bytes = 45.82 KiB = 0.04 MiB
293 22:17:48.398900 output: Architecture: AArch64
294 22:17:48.398995 output: Hash algo: crc32
295 22:17:48.399089 output: Hash value: 1df858fa
296 22:17:48.399181 output: Image 2 (ramdisk-1)
297 22:17:48.399272 output: Description: unavailable
298 22:17:48.399363 output: Created: Mon Jun 5 23:17:48 2023
299 22:17:48.399462 output: Type: RAMDisk Image
300 22:17:48.399557 output: Compression: Unknown Compression
301 22:17:48.399648 output: Data Size: 18594255 Bytes = 18158.45 KiB = 17.73 MiB
302 22:17:48.399740 output: Architecture: AArch64
303 22:17:48.399831 output: OS: Linux
304 22:17:48.399923 output: Load Address: unavailable
305 22:17:48.400021 output: Entry Point: unavailable
306 22:17:48.400154 output: Hash algo: crc32
307 22:17:48.400246 output: Hash value: 34288f8a
308 22:17:48.400338 output: Default Configuration: 'conf-1'
309 22:17:48.400429 output: Configuration 0 (conf-1)
310 22:17:48.400526 output: Description: mt8192-asurada-spherion-r0
311 22:17:48.400621 output: Kernel: kernel-1
312 22:17:48.400712 output: Init Ramdisk: ramdisk-1
313 22:17:48.400803 output: FDT: fdt-1
314 22:17:48.400894 output: Loadables: kernel-1
315 22:17:48.400984 output:
316 22:17:48.401251 end: 1.6.8.1 prepare-fit (duration 00:00:12) [common]
317 22:17:48.401391 end: 1.6.8 prepare-kernel (duration 00:00:12) [common]
318 22:17:48.401532 end: 1.6 prepare-tftp-overlay (duration 00:00:33) [common]
319 22:17:48.401675 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:18) [common]
320 22:17:48.401767 No LXC device requested
321 22:17:48.401888 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 22:17:48.402017 start: 1.8 deploy-device-env (timeout 00:09:18) [common]
323 22:17:48.402135 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 22:17:48.402247 Checking files for TFTP limit of 4294967296 bytes.
325 22:17:48.402916 end: 1 tftp-deploy (duration 00:00:42) [common]
326 22:17:48.403061 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 22:17:48.403196 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 22:17:48.403383 substitutions:
329 22:17:48.403486 - {DTB}: 10597265/tftp-deploy-dqirrpjl/dtb/mt8192-asurada-spherion-r0.dtb
330 22:17:48.403591 - {INITRD}: 10597265/tftp-deploy-dqirrpjl/ramdisk/ramdisk.cpio.gz
331 22:17:48.403691 - {KERNEL}: 10597265/tftp-deploy-dqirrpjl/kernel/Image
332 22:17:48.403790 - {LAVA_MAC}: None
333 22:17:48.403896 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/10597265/extract-nfsrootfs-jdvhjo22
334 22:17:48.403997 - {NFS_SERVER_IP}: 192.168.201.1
335 22:17:48.404121 - {PRESEED_CONFIG}: None
336 22:17:48.404218 - {PRESEED_LOCAL}: None
337 22:17:48.404313 - {RAMDISK}: 10597265/tftp-deploy-dqirrpjl/ramdisk/ramdisk.cpio.gz
338 22:17:48.404415 - {ROOT_PART}: None
339 22:17:48.404514 - {ROOT}: None
340 22:17:48.404611 - {SERVER_IP}: 192.168.201.1
341 22:17:48.404706 - {TEE}: None
342 22:17:48.404800 Parsed boot commands:
343 22:17:48.404893 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 22:17:48.405137 Parsed boot commands: tftpboot 192.168.201.1 10597265/tftp-deploy-dqirrpjl/kernel/image.itb 10597265/tftp-deploy-dqirrpjl/kernel/cmdline
345 22:17:48.405263 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 22:17:48.405388 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 22:17:48.405528 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 22:17:48.405661 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 22:17:48.405770 Not connected, no need to disconnect.
350 22:17:48.405888 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 22:17:48.406017 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 22:17:48.406130 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost mt8192-asurada-spherion-r0-cbg-2'
353 22:17:48.409682 Setting prompt string to ['lava-test: # ']
354 22:17:48.410077 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 22:17:48.410200 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 22:17:48.410312 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 22:17:48.410420 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 22:17:48.410742 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-2' '--port=1' '--command=reboot'
359 22:17:53.538535 >> Command sent successfully.
360 22:17:53.540903 Returned 0 in 5 seconds
361 22:17:53.641258 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 22:17:53.641592 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 22:17:53.641701 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 22:17:53.641790 Setting prompt string to 'Starting depthcharge on Spherion...'
366 22:17:53.641859 Changing prompt to 'Starting depthcharge on Spherion...'
367 22:17:53.641928 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 22:17:53.642196 [Enter `^Ec?' for help]
369 22:17:53.814156
370 22:17:53.814303
371 22:17:53.814372 F0: 102B 0000
372 22:17:53.814435
373 22:17:53.814495 F3: 1001 0000 [0200]
374 22:17:53.814554
375 22:17:53.817374 F3: 1001 0000
376 22:17:53.817459
377 22:17:53.817525 F7: 102D 0000
378 22:17:53.817585
379 22:17:53.820618 F1: 0000 0000
380 22:17:53.820702
381 22:17:53.820768 V0: 0000 0000 [0001]
382 22:17:53.820828
383 22:17:53.820887 00: 0007 8000
384 22:17:53.824228
385 22:17:53.824311 01: 0000 0000
386 22:17:53.824379
387 22:17:53.824442 BP: 0C00 0209 [0000]
388 22:17:53.824501
389 22:17:53.828197 G0: 1182 0000
390 22:17:53.828281
391 22:17:53.828346 EC: 0000 0021 [4000]
392 22:17:53.828406
393 22:17:53.831339 S7: 0000 0000 [0000]
394 22:17:53.831422
395 22:17:53.831487 CC: 0000 0000 [0001]
396 22:17:53.831547
397 22:17:53.834532 T0: 0000 0040 [010F]
398 22:17:53.834616
399 22:17:53.834682 Jump to BL
400 22:17:53.834743
401 22:17:53.861135
402 22:17:53.861227
403 22:17:53.861293
404 22:17:53.868392 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
405 22:17:53.872613 ARM64: Exception handlers installed.
406 22:17:53.875677 ARM64: Testing exception
407 22:17:53.880139 ARM64: Done test exception
408 22:17:53.886342 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
409 22:17:53.893568 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
410 22:17:53.900490 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
411 22:17:53.911281 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
412 22:17:53.918216 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
413 22:17:53.928192 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
414 22:17:53.938410 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
415 22:17:53.945169 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
416 22:17:53.963529 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
417 22:17:53.966874 WDT: Last reset was cold boot
418 22:17:53.970041 SPI1(PAD0) initialized at 2873684 Hz
419 22:17:53.973206 SPI5(PAD0) initialized at 992727 Hz
420 22:17:53.976658 VBOOT: Loading verstage.
421 22:17:53.983432 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 22:17:53.986757 FMAP: Found "FLASH" version 1.1 at 0x20000.
423 22:17:53.990177 FMAP: base = 0x0 size = 0x800000 #areas = 25
424 22:17:53.993129 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
425 22:17:54.000584 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
426 22:17:54.007078 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
427 22:17:54.018630 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
428 22:17:54.018718
429 22:17:54.018787
430 22:17:54.027993 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
431 22:17:54.031375 ARM64: Exception handlers installed.
432 22:17:54.035219 ARM64: Testing exception
433 22:17:54.035303 ARM64: Done test exception
434 22:17:54.041602 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
435 22:17:54.045715 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
436 22:17:54.059409 Probing TPM: . done!
437 22:17:54.059495 TPM ready after 0 ms
438 22:17:54.066747 Connected to device vid:did:rid of 1ae0:0028:00
439 22:17:54.074147 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523
440 22:17:54.132726 Initialized TPM device CR50 revision 0
441 22:17:54.144407 tlcl_send_startup: Startup return code is 0
442 22:17:54.144506 TPM: setup succeeded
443 22:17:54.155937 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
444 22:17:54.164628 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 22:17:54.176878 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
446 22:17:54.186883 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
447 22:17:54.190467 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
448 22:17:54.194939 in-header: 03 07 00 00 08 00 00 00
449 22:17:54.198852 in-data: aa e4 47 04 13 02 00 00
450 22:17:54.202255 Chrome EC: UHEPI supported
451 22:17:54.209519 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
452 22:17:54.212944 in-header: 03 95 00 00 08 00 00 00
453 22:17:54.216489 in-data: 18 20 20 08 00 00 00 00
454 22:17:54.217040 Phase 1
455 22:17:54.220521 FMAP: area GBB found @ 3f5000 (12032 bytes)
456 22:17:54.227830 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
457 22:17:54.231218 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
458 22:17:54.234697 Recovery requested (1009000e)
459 22:17:54.244002 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 22:17:54.249299 tlcl_extend: response is 0
461 22:17:54.258351 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 22:17:54.263536 tlcl_extend: response is 0
463 22:17:54.270731 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 22:17:54.291148 read SPI 0x210d4 0x2173b: 15140 us, 9050 KB/s, 72.400 Mbps
465 22:17:54.297700 BS: bootblock times (exec / console): total (unknown) / 148 ms
466 22:17:54.297818
467 22:17:54.297919
468 22:17:54.307401 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 22:17:54.310634 ARM64: Exception handlers installed.
470 22:17:54.314101 ARM64: Testing exception
471 22:17:54.314189 ARM64: Done test exception
472 22:17:54.335823 pmic_efuse_setting: Set efuses in 11 msecs
473 22:17:54.339466 pmwrap_interface_init: Select PMIF_VLD_RDY
474 22:17:54.346038 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 22:17:54.349665 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 22:17:54.356195 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 22:17:54.359877 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 22:17:54.363718 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 22:17:54.370968 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 22:17:54.374440 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 22:17:54.378044 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 22:17:54.382104 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 22:17:54.388558 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 22:17:54.391945 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 22:17:54.399497 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 22:17:54.403209 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 22:17:54.406981 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 22:17:54.414297 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 22:17:54.421773 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 22:17:54.425050 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 22:17:54.432600 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 22:17:54.435992 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 22:17:54.443761 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 22:17:54.447664 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 22:17:54.455354 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 22:17:54.458529 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 22:17:54.465705 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 22:17:54.469240 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 22:17:54.476631 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 22:17:54.480146 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 22:17:54.487703 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 22:17:54.490987 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 22:17:54.494516 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 22:17:54.502203 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 22:17:54.505491 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 22:17:54.509226 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 22:17:54.516489 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 22:17:54.519913 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 22:17:54.527486 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 22:17:54.530860 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 22:17:54.534658 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 22:17:54.538300 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 22:17:54.545419 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 22:17:54.548716 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 22:17:54.553080 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 22:17:54.556076 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 22:17:54.560456 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 22:17:54.567590 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 22:17:54.571635 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 22:17:54.575020 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 22:17:54.578895 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 22:17:54.582474 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 22:17:54.585929 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 22:17:54.593068 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 22:17:54.600762 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
526 22:17:54.607958 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 22:17:54.611984 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 22:17:54.622773 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 22:17:54.629870 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 22:17:54.633748 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 22:17:54.637735 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 22:17:54.641255 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 22:17:54.649838 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6b, sec=0x3
534 22:17:54.653315 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 22:17:54.662201 [RTC]rtc_osc_init,62: osc32con val = 0xde6b
536 22:17:54.665108 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 22:17:54.674024 [RTC]rtc_get_frequency_meter,154: input=15, output=853
538 22:17:54.683336 [RTC]rtc_get_frequency_meter,154: input=7, output=723
539 22:17:54.693035 [RTC]rtc_get_frequency_meter,154: input=11, output=789
540 22:17:54.702532 [RTC]rtc_get_frequency_meter,154: input=13, output=820
541 22:17:54.711617 [RTC]rtc_get_frequency_meter,154: input=12, output=804
542 22:17:54.721392 [RTC]rtc_get_frequency_meter,154: input=11, output=788
543 22:17:54.731583 [RTC]rtc_get_frequency_meter,154: input=12, output=804
544 22:17:54.735107 [RTC]rtc_eosc_cali,47: left: 11, middle: 11, right: 12
545 22:17:54.739075 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6b
546 22:17:54.742763 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
547 22:17:54.750548 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
548 22:17:54.754219 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
549 22:17:54.757499 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
550 22:17:54.761022 ADC[4]: Raw value=903325 ID=7
551 22:17:54.761462 ADC[3]: Raw value=213916 ID=1
552 22:17:54.764969 RAM Code: 0x71
553 22:17:54.768568 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
554 22:17:54.772359 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
555 22:17:54.783492 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
556 22:17:54.790362 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
557 22:17:54.790819 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
558 22:17:54.795163 in-header: 03 07 00 00 08 00 00 00
559 22:17:54.798783 in-data: aa e4 47 04 13 02 00 00
560 22:17:54.802224 Chrome EC: UHEPI supported
561 22:17:54.809944 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
562 22:17:54.813210 in-header: 03 95 00 00 08 00 00 00
563 22:17:54.817066 in-data: 18 20 20 08 00 00 00 00
564 22:17:54.817640 MRC: failed to locate region type 0.
565 22:17:54.824323 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
566 22:17:54.828077 DRAM-K: Running full calibration
567 22:17:54.835318 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
568 22:17:54.835756 header.status = 0x0
569 22:17:54.838880 header.version = 0x6 (expected: 0x6)
570 22:17:54.842380 header.size = 0xd00 (expected: 0xd00)
571 22:17:54.846053 header.flags = 0x0
572 22:17:54.849584 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
573 22:17:54.868567 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
574 22:17:54.876017 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
575 22:17:54.879620 dram_init: ddr_geometry: 2
576 22:17:54.880165 [EMI] MDL number = 2
577 22:17:54.883088 [EMI] Get MDL freq = 0
578 22:17:54.883611 dram_init: ddr_type: 0
579 22:17:54.886566 is_discrete_lpddr4: 1
580 22:17:54.889445 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
581 22:17:54.889883
582 22:17:54.890227
583 22:17:54.893607 [Bian_co] ETT version 0.0.0.1
584 22:17:54.897014 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
585 22:17:54.897519
586 22:17:54.901379 dramc_set_vcore_voltage set vcore to 650000
587 22:17:54.904835 Read voltage for 800, 4
588 22:17:54.905274 Vio18 = 0
589 22:17:54.905624 Vcore = 650000
590 22:17:54.908723 Vdram = 0
591 22:17:54.909161 Vddq = 0
592 22:17:54.909509 Vmddr = 0
593 22:17:54.912405 dram_init: config_dvfs: 1
594 22:17:54.915264 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
595 22:17:54.922496 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
596 22:17:54.925479 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
597 22:17:54.928707 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
598 22:17:54.932360 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
599 22:17:54.935710 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
600 22:17:54.938910 MEM_TYPE=3, freq_sel=18
601 22:17:54.941940 sv_algorithm_assistance_LP4_1600
602 22:17:54.945289 ============ PULL DRAM RESETB DOWN ============
603 22:17:54.948664 ========== PULL DRAM RESETB DOWN end =========
604 22:17:54.955648 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
605 22:17:54.958684 ===================================
606 22:17:54.959124 LPDDR4 DRAM CONFIGURATION
607 22:17:54.962097 ===================================
608 22:17:54.965121 EX_ROW_EN[0] = 0x0
609 22:17:54.968494 EX_ROW_EN[1] = 0x0
610 22:17:54.968973 LP4Y_EN = 0x0
611 22:17:54.972160 WORK_FSP = 0x0
612 22:17:54.972684 WL = 0x2
613 22:17:54.975394 RL = 0x2
614 22:17:54.975956 BL = 0x2
615 22:17:54.978539 RPST = 0x0
616 22:17:54.978971 RD_PRE = 0x0
617 22:17:54.982025 WR_PRE = 0x1
618 22:17:54.982502 WR_PST = 0x0
619 22:17:54.984982 DBI_WR = 0x0
620 22:17:54.985414 DBI_RD = 0x0
621 22:17:54.988465 OTF = 0x1
622 22:17:54.991765 ===================================
623 22:17:54.995149 ===================================
624 22:17:54.995599 ANA top config
625 22:17:54.998687 ===================================
626 22:17:55.001799 DLL_ASYNC_EN = 0
627 22:17:55.005185 ALL_SLAVE_EN = 1
628 22:17:55.008800 NEW_RANK_MODE = 1
629 22:17:55.009268 DLL_IDLE_MODE = 1
630 22:17:55.011607 LP45_APHY_COMB_EN = 1
631 22:17:55.015398 TX_ODT_DIS = 1
632 22:17:55.018607 NEW_8X_MODE = 1
633 22:17:55.022059 ===================================
634 22:17:55.025516 ===================================
635 22:17:55.026045 data_rate = 1600
636 22:17:55.028927 CKR = 1
637 22:17:55.031978 DQ_P2S_RATIO = 8
638 22:17:55.034998 ===================================
639 22:17:55.038674 CA_P2S_RATIO = 8
640 22:17:55.042066 DQ_CA_OPEN = 0
641 22:17:55.042505 DQ_SEMI_OPEN = 0
642 22:17:55.045812 CA_SEMI_OPEN = 0
643 22:17:55.049235 CA_FULL_RATE = 0
644 22:17:55.052476 DQ_CKDIV4_EN = 1
645 22:17:55.055492 CA_CKDIV4_EN = 1
646 22:17:55.059356 CA_PREDIV_EN = 0
647 22:17:55.059880 PH8_DLY = 0
648 22:17:55.062159 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
649 22:17:55.065890 DQ_AAMCK_DIV = 4
650 22:17:55.069128 CA_AAMCK_DIV = 4
651 22:17:55.072022 CA_ADMCK_DIV = 4
652 22:17:55.075792 DQ_TRACK_CA_EN = 0
653 22:17:55.076278 CA_PICK = 800
654 22:17:55.078834 CA_MCKIO = 800
655 22:17:55.081968 MCKIO_SEMI = 0
656 22:17:55.085559 PLL_FREQ = 3068
657 22:17:55.089017 DQ_UI_PI_RATIO = 32
658 22:17:55.092840 CA_UI_PI_RATIO = 0
659 22:17:55.093448 ===================================
660 22:17:55.097007 ===================================
661 22:17:55.100292 memory_type:LPDDR4
662 22:17:55.104090 GP_NUM : 10
663 22:17:55.104520 SRAM_EN : 1
664 22:17:55.107920 MD32_EN : 0
665 22:17:55.111683 ===================================
666 22:17:55.112155 [ANA_INIT] >>>>>>>>>>>>>>
667 22:17:55.114878 <<<<<< [CONFIGURE PHASE]: ANA_TX
668 22:17:55.119045 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
669 22:17:55.122521 ===================================
670 22:17:55.125778 data_rate = 1600,PCW = 0X7600
671 22:17:55.128639 ===================================
672 22:17:55.131892 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
673 22:17:55.135249 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
674 22:17:55.141886 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
675 22:17:55.144765 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
676 22:17:55.148372 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
677 22:17:55.151548 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
678 22:17:55.155356 [ANA_INIT] flow start
679 22:17:55.159000 [ANA_INIT] PLL >>>>>>>>
680 22:17:55.159084 [ANA_INIT] PLL <<<<<<<<
681 22:17:55.161696 [ANA_INIT] MIDPI >>>>>>>>
682 22:17:55.164714 [ANA_INIT] MIDPI <<<<<<<<
683 22:17:55.168051 [ANA_INIT] DLL >>>>>>>>
684 22:17:55.168147 [ANA_INIT] flow end
685 22:17:55.171901 ============ LP4 DIFF to SE enter ============
686 22:17:55.178684 ============ LP4 DIFF to SE exit ============
687 22:17:55.179117 [ANA_INIT] <<<<<<<<<<<<<
688 22:17:55.181574 [Flow] Enable top DCM control >>>>>
689 22:17:55.185241 [Flow] Enable top DCM control <<<<<
690 22:17:55.188420 Enable DLL master slave shuffle
691 22:17:55.195434 ==============================================================
692 22:17:55.195868 Gating Mode config
693 22:17:55.201565 ==============================================================
694 22:17:55.204996 Config description:
695 22:17:55.215385 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
696 22:17:55.221972 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
697 22:17:55.225045 SELPH_MODE 0: By rank 1: By Phase
698 22:17:55.231697 ==============================================================
699 22:17:55.235356 GAT_TRACK_EN = 1
700 22:17:55.235800 RX_GATING_MODE = 2
701 22:17:55.238621 RX_GATING_TRACK_MODE = 2
702 22:17:55.241998 SELPH_MODE = 1
703 22:17:55.245263 PICG_EARLY_EN = 1
704 22:17:55.248159 VALID_LAT_VALUE = 1
705 22:17:55.254808 ==============================================================
706 22:17:55.258051 Enter into Gating configuration >>>>
707 22:17:55.261672 Exit from Gating configuration <<<<
708 22:17:55.265147 Enter into DVFS_PRE_config >>>>>
709 22:17:55.274787 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
710 22:17:55.278284 Exit from DVFS_PRE_config <<<<<
711 22:17:55.281478 Enter into PICG configuration >>>>
712 22:17:55.284692 Exit from PICG configuration <<<<
713 22:17:55.287788 [RX_INPUT] configuration >>>>>
714 22:17:55.291169 [RX_INPUT] configuration <<<<<
715 22:17:55.294424 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
716 22:17:55.301162 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
717 22:17:55.307722 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
718 22:17:55.314411 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
719 22:17:55.317610 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
720 22:17:55.324435 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
721 22:17:55.327798 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
722 22:17:55.334673 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
723 22:17:55.337727 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
724 22:17:55.341238 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
725 22:17:55.344235 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
726 22:17:55.351219 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
727 22:17:55.354447 ===================================
728 22:17:55.354885 LPDDR4 DRAM CONFIGURATION
729 22:17:55.357839 ===================================
730 22:17:55.361097 EX_ROW_EN[0] = 0x0
731 22:17:55.364644 EX_ROW_EN[1] = 0x0
732 22:17:55.365074 LP4Y_EN = 0x0
733 22:17:55.368129 WORK_FSP = 0x0
734 22:17:55.368558 WL = 0x2
735 22:17:55.371315 RL = 0x2
736 22:17:55.371746 BL = 0x2
737 22:17:55.374647 RPST = 0x0
738 22:17:55.375074 RD_PRE = 0x0
739 22:17:55.377560 WR_PRE = 0x1
740 22:17:55.377986 WR_PST = 0x0
741 22:17:55.381173 DBI_WR = 0x0
742 22:17:55.381603 DBI_RD = 0x0
743 22:17:55.384419 OTF = 0x1
744 22:17:55.387373 ===================================
745 22:17:55.390873 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
746 22:17:55.394022 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
747 22:17:55.400825 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
748 22:17:55.404363 ===================================
749 22:17:55.404798 LPDDR4 DRAM CONFIGURATION
750 22:17:55.407462 ===================================
751 22:17:55.411117 EX_ROW_EN[0] = 0x10
752 22:17:55.413971 EX_ROW_EN[1] = 0x0
753 22:17:55.414457 LP4Y_EN = 0x0
754 22:17:55.417617 WORK_FSP = 0x0
755 22:17:55.418050 WL = 0x2
756 22:17:55.420508 RL = 0x2
757 22:17:55.420939 BL = 0x2
758 22:17:55.423942 RPST = 0x0
759 22:17:55.424419 RD_PRE = 0x0
760 22:17:55.427034 WR_PRE = 0x1
761 22:17:55.427465 WR_PST = 0x0
762 22:17:55.430519 DBI_WR = 0x0
763 22:17:55.430947 DBI_RD = 0x0
764 22:17:55.434003 OTF = 0x1
765 22:17:55.437514 ===================================
766 22:17:55.443846 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
767 22:17:55.447094 nWR fixed to 40
768 22:17:55.447830 [ModeRegInit_LP4] CH0 RK0
769 22:17:55.450468 [ModeRegInit_LP4] CH0 RK1
770 22:17:55.453652 [ModeRegInit_LP4] CH1 RK0
771 22:17:55.457438 [ModeRegInit_LP4] CH1 RK1
772 22:17:55.457869 match AC timing 13
773 22:17:55.463676 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
774 22:17:55.467298 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
775 22:17:55.470228 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
776 22:17:55.476974 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
777 22:17:55.480314 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
778 22:17:55.480752 [EMI DOE] emi_dcm 0
779 22:17:55.486678 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
780 22:17:55.487118 ==
781 22:17:55.489891 Dram Type= 6, Freq= 0, CH_0, rank 0
782 22:17:55.493086 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
783 22:17:55.493525 ==
784 22:17:55.499793 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
785 22:17:55.506603 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
786 22:17:55.513926 [CA 0] Center 37 (7~68) winsize 62
787 22:17:55.517547 [CA 1] Center 37 (6~68) winsize 63
788 22:17:55.520695 [CA 2] Center 35 (5~65) winsize 61
789 22:17:55.524092 [CA 3] Center 35 (4~66) winsize 63
790 22:17:55.527281 [CA 4] Center 33 (3~64) winsize 62
791 22:17:55.531328 [CA 5] Center 33 (3~64) winsize 62
792 22:17:55.531902
793 22:17:55.534129 [CmdBusTrainingLP45] Vref(ca) range 1: 32
794 22:17:55.534571
795 22:17:55.537284 [CATrainingPosCal] consider 1 rank data
796 22:17:55.540821 u2DelayCellTimex100 = 270/100 ps
797 22:17:55.544087 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
798 22:17:55.550904 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
799 22:17:55.553980 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
800 22:17:55.557333 CA3 delay=35 (4~66),Diff = 2 PI (14 cell)
801 22:17:55.560586 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
802 22:17:55.563757 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
803 22:17:55.564238
804 22:17:55.567562 CA PerBit enable=1, Macro0, CA PI delay=33
805 22:17:55.568010
806 22:17:55.570722 [CBTSetCACLKResult] CA Dly = 33
807 22:17:55.571163 CS Dly: 5 (0~36)
808 22:17:55.573875 ==
809 22:17:55.576966 Dram Type= 6, Freq= 0, CH_0, rank 1
810 22:17:55.580524 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
811 22:17:55.580962 ==
812 22:17:55.584155 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
813 22:17:55.590327 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
814 22:17:55.600162 [CA 0] Center 38 (7~69) winsize 63
815 22:17:55.603393 [CA 1] Center 37 (7~68) winsize 62
816 22:17:55.606961 [CA 2] Center 35 (4~66) winsize 63
817 22:17:55.610636 [CA 3] Center 35 (4~66) winsize 63
818 22:17:55.613659 [CA 4] Center 34 (3~65) winsize 63
819 22:17:55.616738 [CA 5] Center 33 (3~64) winsize 62
820 22:17:55.616840
821 22:17:55.620087 [CmdBusTrainingLP45] Vref(ca) range 1: 34
822 22:17:55.620189
823 22:17:55.623814 [CATrainingPosCal] consider 2 rank data
824 22:17:55.626899 u2DelayCellTimex100 = 270/100 ps
825 22:17:55.630149 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
826 22:17:55.633270 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
827 22:17:55.639703 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
828 22:17:55.643466 CA3 delay=35 (4~66),Diff = 2 PI (14 cell)
829 22:17:55.646471 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
830 22:17:55.650127 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
831 22:17:55.650283
832 22:17:55.653275 CA PerBit enable=1, Macro0, CA PI delay=33
833 22:17:55.653434
834 22:17:55.656695 [CBTSetCACLKResult] CA Dly = 33
835 22:17:55.656841 CS Dly: 6 (0~38)
836 22:17:55.660147
837 22:17:55.663010 ----->DramcWriteLeveling(PI) begin...
838 22:17:55.663167 ==
839 22:17:55.666845 Dram Type= 6, Freq= 0, CH_0, rank 0
840 22:17:55.671010 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
841 22:17:55.671179 ==
842 22:17:55.674731 Write leveling (Byte 0): 29 => 29
843 22:17:55.674893 Write leveling (Byte 1): 24 => 24
844 22:17:55.678140 DramcWriteLeveling(PI) end<-----
845 22:17:55.678299
846 22:17:55.678446 ==
847 22:17:55.681845 Dram Type= 6, Freq= 0, CH_0, rank 0
848 22:17:55.685267 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
849 22:17:55.688744 ==
850 22:17:55.688916 [Gating] SW mode calibration
851 22:17:55.695598 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
852 22:17:55.702623 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
853 22:17:55.705917 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
854 22:17:55.708987 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
855 22:17:55.715981 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
856 22:17:55.719290 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 22:17:55.722273 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 22:17:55.729125 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 22:17:55.732196 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 22:17:55.735687 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 22:17:55.742177 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 22:17:55.745940 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 22:17:55.748859 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 22:17:55.755291 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 22:17:55.758840 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 22:17:55.762235 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 22:17:55.768550 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 22:17:55.772254 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 22:17:55.775618 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 22:17:55.782536 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
871 22:17:55.785411 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
872 22:17:55.788571 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
873 22:17:55.795342 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 22:17:55.798759 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 22:17:55.802243 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 22:17:55.808817 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
877 22:17:55.811956 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
878 22:17:55.815752 0 9 4 | B1->B0 | 2323 2323 | 0 1 | (0 0) (1 1)
879 22:17:55.818856 0 9 8 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
880 22:17:55.825736 0 9 12 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 1)
881 22:17:55.828446 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
882 22:17:55.832404 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
883 22:17:55.838579 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
884 22:17:55.842054 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
885 22:17:55.845186 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
886 22:17:55.852217 0 10 4 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
887 22:17:55.855588 0 10 8 | B1->B0 | 3333 2424 | 0 0 | (0 1) (0 0)
888 22:17:55.858993 0 10 12 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
889 22:17:55.865386 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 22:17:55.868650 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
891 22:17:55.871853 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
892 22:17:55.878727 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
893 22:17:55.881931 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
894 22:17:55.885101 0 11 4 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (1 1)
895 22:17:55.891744 0 11 8 | B1->B0 | 2727 4343 | 0 0 | (0 0) (0 0)
896 22:17:55.895035 0 11 12 | B1->B0 | 3a3a 4646 | 0 0 | (1 1) (0 0)
897 22:17:55.898224 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 22:17:55.905318 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
899 22:17:55.908192 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
900 22:17:55.911584 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
901 22:17:55.918254 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
902 22:17:55.921427 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
903 22:17:55.925109 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
904 22:17:55.931537 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 22:17:55.934909 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 22:17:55.938029 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 22:17:55.944551 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 22:17:55.948305 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 22:17:55.951586 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 22:17:55.958036 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 22:17:55.961635 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 22:17:55.964743 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 22:17:55.971475 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
914 22:17:55.974847 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
915 22:17:55.978148 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
916 22:17:55.981550 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
917 22:17:55.988003 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
918 22:17:55.991148 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
919 22:17:55.994511 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
920 22:17:56.001142 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
921 22:17:56.004791 Total UI for P1: 0, mck2ui 16
922 22:17:56.007811 best dqsien dly found for B0: ( 0, 14, 6)
923 22:17:56.011023 Total UI for P1: 0, mck2ui 16
924 22:17:56.014731 best dqsien dly found for B1: ( 0, 14, 8)
925 22:17:56.017954 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
926 22:17:56.021361 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
927 22:17:56.021571
928 22:17:56.024453 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
929 22:17:56.028074 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
930 22:17:56.030973 [Gating] SW calibration Done
931 22:17:56.031181 ==
932 22:17:56.034362 Dram Type= 6, Freq= 0, CH_0, rank 0
933 22:17:56.038387 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 22:17:56.038597 ==
935 22:17:56.042362 RX Vref Scan: 0
936 22:17:56.042534
937 22:17:56.042669 RX Vref 0 -> 0, step: 1
938 22:17:56.042796
939 22:17:56.045767 RX Delay -130 -> 252, step: 16
940 22:17:56.048715 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
941 22:17:56.051921 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
942 22:17:56.058614 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
943 22:17:56.062154 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
944 22:17:56.065018 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
945 22:17:56.068535 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
946 22:17:56.071710 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
947 22:17:56.078600 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
948 22:17:56.081965 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
949 22:17:56.085262 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
950 22:17:56.088480 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
951 22:17:56.091837 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
952 22:17:56.098354 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
953 22:17:56.101961 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
954 22:17:56.104941 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
955 22:17:56.108196 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
956 22:17:56.108282 ==
957 22:17:56.111418 Dram Type= 6, Freq= 0, CH_0, rank 0
958 22:17:56.118070 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
959 22:17:56.118163 ==
960 22:17:56.118232 DQS Delay:
961 22:17:56.121571 DQS0 = 0, DQS1 = 0
962 22:17:56.121662 DQM Delay:
963 22:17:56.124986 DQM0 = 87, DQM1 = 75
964 22:17:56.125071 DQ Delay:
965 22:17:56.128193 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
966 22:17:56.131145 DQ4 =93, DQ5 =69, DQ6 =101, DQ7 =93
967 22:17:56.134642 DQ8 =69, DQ9 =53, DQ10 =69, DQ11 =69
968 22:17:56.137838 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
969 22:17:56.137922
970 22:17:56.137988
971 22:17:56.138049 ==
972 22:17:56.141462 Dram Type= 6, Freq= 0, CH_0, rank 0
973 22:17:56.144450 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
974 22:17:56.144535 ==
975 22:17:56.144602
976 22:17:56.144662
977 22:17:56.147976 TX Vref Scan disable
978 22:17:56.151089 == TX Byte 0 ==
979 22:17:56.154432 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
980 22:17:56.158135 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
981 22:17:56.161399 == TX Byte 1 ==
982 22:17:56.164836 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
983 22:17:56.167897 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
984 22:17:56.167985 ==
985 22:17:56.171389 Dram Type= 6, Freq= 0, CH_0, rank 0
986 22:17:56.174793 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
987 22:17:56.178040 ==
988 22:17:56.189829 TX Vref=22, minBit 4, minWin=26, winSum=437
989 22:17:56.192740 TX Vref=24, minBit 0, minWin=27, winSum=444
990 22:17:56.196317 TX Vref=26, minBit 0, minWin=27, winSum=449
991 22:17:56.199703 TX Vref=28, minBit 3, minWin=27, winSum=449
992 22:17:56.202752 TX Vref=30, minBit 4, minWin=27, winSum=450
993 22:17:56.205994 TX Vref=32, minBit 2, minWin=27, winSum=452
994 22:17:56.212928 [TxChooseVref] Worse bit 2, Min win 27, Win sum 452, Final Vref 32
995 22:17:56.213014
996 22:17:56.216191 Final TX Range 1 Vref 32
997 22:17:56.216278
998 22:17:56.216365 ==
999 22:17:56.219463 Dram Type= 6, Freq= 0, CH_0, rank 0
1000 22:17:56.222667 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1001 22:17:56.222753 ==
1002 22:17:56.225912
1003 22:17:56.225997
1004 22:17:56.226083 TX Vref Scan disable
1005 22:17:56.229701 == TX Byte 0 ==
1006 22:17:56.232914 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1007 22:17:56.239313 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1008 22:17:56.239425 == TX Byte 1 ==
1009 22:17:56.242681 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1010 22:17:56.249308 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1011 22:17:56.249393
1012 22:17:56.249461 [DATLAT]
1013 22:17:56.249523 Freq=800, CH0 RK0
1014 22:17:56.249583
1015 22:17:56.252650 DATLAT Default: 0xa
1016 22:17:56.252733 0, 0xFFFF, sum = 0
1017 22:17:56.256287 1, 0xFFFF, sum = 0
1018 22:17:56.256373 2, 0xFFFF, sum = 0
1019 22:17:56.259514 3, 0xFFFF, sum = 0
1020 22:17:56.262523 4, 0xFFFF, sum = 0
1021 22:17:56.262613 5, 0xFFFF, sum = 0
1022 22:17:56.266478 6, 0xFFFF, sum = 0
1023 22:17:56.266563 7, 0xFFFF, sum = 0
1024 22:17:56.269492 8, 0xFFFF, sum = 0
1025 22:17:56.269583 9, 0x0, sum = 1
1026 22:17:56.269651 10, 0x0, sum = 2
1027 22:17:56.272410 11, 0x0, sum = 3
1028 22:17:56.272494 12, 0x0, sum = 4
1029 22:17:56.276015 best_step = 10
1030 22:17:56.276122
1031 22:17:56.276190 ==
1032 22:17:56.279403 Dram Type= 6, Freq= 0, CH_0, rank 0
1033 22:17:56.282596 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1034 22:17:56.282679 ==
1035 22:17:56.286283 RX Vref Scan: 1
1036 22:17:56.286366
1037 22:17:56.286431 Set Vref Range= 32 -> 127
1038 22:17:56.289633
1039 22:17:56.289756 RX Vref 32 -> 127, step: 1
1040 22:17:56.289821
1041 22:17:56.292477 RX Delay -111 -> 252, step: 8
1042 22:17:56.292560
1043 22:17:56.295937 Set Vref, RX VrefLevel [Byte0]: 32
1044 22:17:56.299153 [Byte1]: 32
1045 22:17:56.299237
1046 22:17:56.302828 Set Vref, RX VrefLevel [Byte0]: 33
1047 22:17:56.305935 [Byte1]: 33
1048 22:17:56.309968
1049 22:17:56.310044 Set Vref, RX VrefLevel [Byte0]: 34
1050 22:17:56.313676 [Byte1]: 34
1051 22:17:56.317469
1052 22:17:56.317542 Set Vref, RX VrefLevel [Byte0]: 35
1053 22:17:56.321166 [Byte1]: 35
1054 22:17:56.325580
1055 22:17:56.325658 Set Vref, RX VrefLevel [Byte0]: 36
1056 22:17:56.328694 [Byte1]: 36
1057 22:17:56.332975
1058 22:17:56.333060 Set Vref, RX VrefLevel [Byte0]: 37
1059 22:17:56.336308 [Byte1]: 37
1060 22:17:56.341050
1061 22:17:56.341129 Set Vref, RX VrefLevel [Byte0]: 38
1062 22:17:56.344599 [Byte1]: 38
1063 22:17:56.348192
1064 22:17:56.348270 Set Vref, RX VrefLevel [Byte0]: 39
1065 22:17:56.351620 [Byte1]: 39
1066 22:17:56.355977
1067 22:17:56.356113 Set Vref, RX VrefLevel [Byte0]: 40
1068 22:17:56.359781 [Byte1]: 40
1069 22:17:56.364191
1070 22:17:56.364282 Set Vref, RX VrefLevel [Byte0]: 41
1071 22:17:56.367283 [Byte1]: 41
1072 22:17:56.371041
1073 22:17:56.371124 Set Vref, RX VrefLevel [Byte0]: 42
1074 22:17:56.374193 [Byte1]: 42
1075 22:17:56.378514
1076 22:17:56.378593 Set Vref, RX VrefLevel [Byte0]: 43
1077 22:17:56.382284 [Byte1]: 43
1078 22:17:56.386618
1079 22:17:56.386697 Set Vref, RX VrefLevel [Byte0]: 44
1080 22:17:56.389697 [Byte1]: 44
1081 22:17:56.394034
1082 22:17:56.394108 Set Vref, RX VrefLevel [Byte0]: 45
1083 22:17:56.397394 [Byte1]: 45
1084 22:17:56.401850
1085 22:17:56.401965 Set Vref, RX VrefLevel [Byte0]: 46
1086 22:17:56.405334 [Byte1]: 46
1087 22:17:56.409086
1088 22:17:56.409168 Set Vref, RX VrefLevel [Byte0]: 47
1089 22:17:56.412428 [Byte1]: 47
1090 22:17:56.417350
1091 22:17:56.417432 Set Vref, RX VrefLevel [Byte0]: 48
1092 22:17:56.420362 [Byte1]: 48
1093 22:17:56.424626
1094 22:17:56.424707 Set Vref, RX VrefLevel [Byte0]: 49
1095 22:17:56.428111 [Byte1]: 49
1096 22:17:56.432413
1097 22:17:56.432496 Set Vref, RX VrefLevel [Byte0]: 50
1098 22:17:56.435770 [Byte1]: 50
1099 22:17:56.439855
1100 22:17:56.439937 Set Vref, RX VrefLevel [Byte0]: 51
1101 22:17:56.443159 [Byte1]: 51
1102 22:17:56.447554
1103 22:17:56.447637 Set Vref, RX VrefLevel [Byte0]: 52
1104 22:17:56.450759 [Byte1]: 52
1105 22:17:56.455096
1106 22:17:56.455220 Set Vref, RX VrefLevel [Byte0]: 53
1107 22:17:56.458426 [Byte1]: 53
1108 22:17:56.463345
1109 22:17:56.463428 Set Vref, RX VrefLevel [Byte0]: 54
1110 22:17:56.466088 [Byte1]: 54
1111 22:17:56.470950
1112 22:17:56.471080 Set Vref, RX VrefLevel [Byte0]: 55
1113 22:17:56.473713 [Byte1]: 55
1114 22:17:56.478269
1115 22:17:56.478352 Set Vref, RX VrefLevel [Byte0]: 56
1116 22:17:56.481489 [Byte1]: 56
1117 22:17:56.485596
1118 22:17:56.485678 Set Vref, RX VrefLevel [Byte0]: 57
1119 22:17:56.489033 [Byte1]: 57
1120 22:17:56.493379
1121 22:17:56.493494 Set Vref, RX VrefLevel [Byte0]: 58
1122 22:17:56.496781 [Byte1]: 58
1123 22:17:56.500812
1124 22:17:56.500897 Set Vref, RX VrefLevel [Byte0]: 59
1125 22:17:56.504127 [Byte1]: 59
1126 22:17:56.508519
1127 22:17:56.508617 Set Vref, RX VrefLevel [Byte0]: 60
1128 22:17:56.512481 [Byte1]: 60
1129 22:17:56.516351
1130 22:17:56.516438 Set Vref, RX VrefLevel [Byte0]: 61
1131 22:17:56.519872 [Byte1]: 61
1132 22:17:56.523802
1133 22:17:56.523906 Set Vref, RX VrefLevel [Byte0]: 62
1134 22:17:56.527597 [Byte1]: 62
1135 22:17:56.531824
1136 22:17:56.531941 Set Vref, RX VrefLevel [Byte0]: 63
1137 22:17:56.534874 [Byte1]: 63
1138 22:17:56.539164
1139 22:17:56.539260 Set Vref, RX VrefLevel [Byte0]: 64
1140 22:17:56.542832 [Byte1]: 64
1141 22:17:56.546818
1142 22:17:56.546913 Set Vref, RX VrefLevel [Byte0]: 65
1143 22:17:56.549953 [Byte1]: 65
1144 22:17:56.554453
1145 22:17:56.554560 Set Vref, RX VrefLevel [Byte0]: 66
1146 22:17:56.557694 [Byte1]: 66
1147 22:17:56.562304
1148 22:17:56.562420 Set Vref, RX VrefLevel [Byte0]: 67
1149 22:17:56.565610 [Byte1]: 67
1150 22:17:56.569901
1151 22:17:56.569983 Set Vref, RX VrefLevel [Byte0]: 68
1152 22:17:56.573118 [Byte1]: 68
1153 22:17:56.577961
1154 22:17:56.578042 Set Vref, RX VrefLevel [Byte0]: 69
1155 22:17:56.580943 [Byte1]: 69
1156 22:17:56.585134
1157 22:17:56.585234 Set Vref, RX VrefLevel [Byte0]: 70
1158 22:17:56.588304 [Byte1]: 70
1159 22:17:56.592550
1160 22:17:56.592634 Set Vref, RX VrefLevel [Byte0]: 71
1161 22:17:56.596344 [Byte1]: 71
1162 22:17:56.600481
1163 22:17:56.600570 Final RX Vref Byte 0 = 56 to rank0
1164 22:17:56.604002 Final RX Vref Byte 1 = 58 to rank0
1165 22:17:56.607403 Final RX Vref Byte 0 = 56 to rank1
1166 22:17:56.610309 Final RX Vref Byte 1 = 58 to rank1==
1167 22:17:56.613859 Dram Type= 6, Freq= 0, CH_0, rank 0
1168 22:17:56.620339 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1169 22:17:56.620446 ==
1170 22:17:56.620549 DQS Delay:
1171 22:17:56.620640 DQS0 = 0, DQS1 = 0
1172 22:17:56.623572 DQM Delay:
1173 22:17:56.623678 DQM0 = 87, DQM1 = 76
1174 22:17:56.627316 DQ Delay:
1175 22:17:56.630480 DQ0 =88, DQ1 =88, DQ2 =84, DQ3 =84
1176 22:17:56.633570 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1177 22:17:56.633645 DQ8 =68, DQ9 =60, DQ10 =76, DQ11 =76
1178 22:17:56.639902 DQ12 =84, DQ13 =80, DQ14 =84, DQ15 =84
1179 22:17:56.640012
1180 22:17:56.640096
1181 22:17:56.646748 [DQSOSCAuto] RK0, (LSB)MR18= 0x2922, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 399 ps
1182 22:17:56.650041 CH0 RK0: MR19=606, MR18=2922
1183 22:17:56.656762 CH0_RK0: MR19=0x606, MR18=0x2922, DQSOSC=399, MR23=63, INC=92, DEC=61
1184 22:17:56.656845
1185 22:17:56.659984 ----->DramcWriteLeveling(PI) begin...
1186 22:17:56.660128 ==
1187 22:17:56.663185 Dram Type= 6, Freq= 0, CH_0, rank 1
1188 22:17:56.666852 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1189 22:17:56.666941 ==
1190 22:17:56.670058 Write leveling (Byte 0): 33 => 33
1191 22:17:56.673496 Write leveling (Byte 1): 29 => 29
1192 22:17:56.676900 DramcWriteLeveling(PI) end<-----
1193 22:17:56.676978
1194 22:17:56.677052 ==
1195 22:17:56.679965 Dram Type= 6, Freq= 0, CH_0, rank 1
1196 22:17:56.683553 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1197 22:17:56.683628 ==
1198 22:17:56.686823 [Gating] SW mode calibration
1199 22:17:56.693404 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1200 22:17:56.699909 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1201 22:17:56.703339 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1202 22:17:56.706448 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1203 22:17:56.713221 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1204 22:17:56.716420 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1205 22:17:56.719799 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1206 22:17:56.767235 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1207 22:17:56.767377 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1208 22:17:56.767793 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1209 22:17:56.768345 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1210 22:17:56.769075 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1211 22:17:56.769356 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1212 22:17:56.769454 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1213 22:17:56.769545 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1214 22:17:56.770146 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1215 22:17:56.770420 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1216 22:17:56.811233 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1217 22:17:56.811368 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1218 22:17:56.811631 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
1219 22:17:56.811708 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1220 22:17:56.811810 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1221 22:17:56.812066 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1222 22:17:56.812129 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1223 22:17:56.812204 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1224 22:17:56.812771 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 22:17:56.813046 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 22:17:56.856122 0 9 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1227 22:17:56.856240 0 9 8 | B1->B0 | 2323 3333 | 0 1 | (0 0) (1 1)
1228 22:17:56.856530 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1229 22:17:56.856598 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1230 22:17:56.856676 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1231 22:17:56.856783 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1232 22:17:56.856872 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1233 22:17:56.857410 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1234 22:17:56.858041 0 10 4 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 0)
1235 22:17:56.858315 0 10 8 | B1->B0 | 3030 2323 | 1 0 | (1 1) (0 0)
1236 22:17:56.871346 0 10 12 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
1237 22:17:56.871451 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1238 22:17:56.871772 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1239 22:17:56.874664 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1240 22:17:56.877933 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1241 22:17:56.881611 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1242 22:17:56.884858 0 11 4 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
1243 22:17:56.888149 0 11 8 | B1->B0 | 3131 4545 | 0 0 | (0 0) (0 0)
1244 22:17:56.891517 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1245 22:17:56.898016 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1246 22:17:56.901751 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1247 22:17:56.904444 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1248 22:17:56.911576 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1249 22:17:56.915249 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1250 22:17:56.919037 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1251 22:17:56.922922 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1252 22:17:56.926480 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1253 22:17:56.932880 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1254 22:17:56.935976 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1255 22:17:56.940026 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1256 22:17:56.946719 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1257 22:17:56.950032 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1258 22:17:56.953668 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1259 22:17:56.959893 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1260 22:17:56.963723 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1261 22:17:56.966630 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1262 22:17:56.970117 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1263 22:17:56.976660 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1264 22:17:56.980217 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1265 22:17:56.983298 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1266 22:17:56.990321 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1267 22:17:56.993523 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1268 22:17:56.996779 Total UI for P1: 0, mck2ui 16
1269 22:17:56.999941 best dqsien dly found for B0: ( 0, 14, 4)
1270 22:17:57.003528 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1271 22:17:57.010025 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1272 22:17:57.010108 Total UI for P1: 0, mck2ui 16
1273 22:17:57.016881 best dqsien dly found for B1: ( 0, 14, 8)
1274 22:17:57.020371 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1275 22:17:57.023401 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1276 22:17:57.023505
1277 22:17:57.027014 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1278 22:17:57.030353 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1279 22:17:57.033257 [Gating] SW calibration Done
1280 22:17:57.033338 ==
1281 22:17:57.037090 Dram Type= 6, Freq= 0, CH_0, rank 1
1282 22:17:57.039906 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1283 22:17:57.040039 ==
1284 22:17:57.043495 RX Vref Scan: 0
1285 22:17:57.043604
1286 22:17:57.043696 RX Vref 0 -> 0, step: 1
1287 22:17:57.043790
1288 22:17:57.046787 RX Delay -130 -> 252, step: 16
1289 22:17:57.050128 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1290 22:17:57.057228 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
1291 22:17:57.059981 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1292 22:17:57.063763 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1293 22:17:57.067005 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1294 22:17:57.070313 iDelay=206, Bit 5, Center 69 (-50 ~ 189) 240
1295 22:17:57.076529 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1296 22:17:57.080264 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
1297 22:17:57.083522 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1298 22:17:57.086700 iDelay=206, Bit 9, Center 61 (-50 ~ 173) 224
1299 22:17:57.089952 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1300 22:17:57.096526 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1301 22:17:57.099666 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1302 22:17:57.103610 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1303 22:17:57.106665 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1304 22:17:57.109766 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1305 22:17:57.113031 ==
1306 22:17:57.116688 Dram Type= 6, Freq= 0, CH_0, rank 1
1307 22:17:57.119714 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1308 22:17:57.119820 ==
1309 22:17:57.119918 DQS Delay:
1310 22:17:57.123359 DQS0 = 0, DQS1 = 0
1311 22:17:57.123493 DQM Delay:
1312 22:17:57.126289 DQM0 = 85, DQM1 = 76
1313 22:17:57.126399 DQ Delay:
1314 22:17:57.130238 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =85
1315 22:17:57.133095 DQ4 =93, DQ5 =69, DQ6 =93, DQ7 =93
1316 22:17:57.136358 DQ8 =69, DQ9 =61, DQ10 =69, DQ11 =69
1317 22:17:57.139513 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1318 22:17:57.139631
1319 22:17:57.139695
1320 22:17:57.139755 ==
1321 22:17:57.143182 Dram Type= 6, Freq= 0, CH_0, rank 1
1322 22:17:57.146104 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1323 22:17:57.146190 ==
1324 22:17:57.146318
1325 22:17:57.146412
1326 22:17:57.149623 TX Vref Scan disable
1327 22:17:57.153019 == TX Byte 0 ==
1328 22:17:57.156204 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1329 22:17:57.159976 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1330 22:17:57.163167 == TX Byte 1 ==
1331 22:17:57.166622 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1332 22:17:57.169665 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1333 22:17:57.169748 ==
1334 22:17:57.173011 Dram Type= 6, Freq= 0, CH_0, rank 1
1335 22:17:57.179620 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1336 22:17:57.179709 ==
1337 22:17:57.191229 TX Vref=22, minBit 1, minWin=27, winSum=443
1338 22:17:57.194598 TX Vref=24, minBit 4, minWin=27, winSum=447
1339 22:17:57.197813 TX Vref=26, minBit 1, minWin=27, winSum=444
1340 22:17:57.201237 TX Vref=28, minBit 5, minWin=27, winSum=450
1341 22:17:57.204825 TX Vref=30, minBit 5, minWin=27, winSum=452
1342 22:17:57.211367 TX Vref=32, minBit 0, minWin=27, winSum=448
1343 22:17:57.214606 [TxChooseVref] Worse bit 5, Min win 27, Win sum 452, Final Vref 30
1344 22:17:57.214682
1345 22:17:57.217610 Final TX Range 1 Vref 30
1346 22:17:57.217708
1347 22:17:57.217797 ==
1348 22:17:57.221383 Dram Type= 6, Freq= 0, CH_0, rank 1
1349 22:17:57.224663 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1350 22:17:57.224737 ==
1351 22:17:57.227830
1352 22:17:57.227926
1353 22:17:57.228013 TX Vref Scan disable
1354 22:17:57.231345 == TX Byte 0 ==
1355 22:17:57.234487 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1356 22:17:57.241065 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1357 22:17:57.241154 == TX Byte 1 ==
1358 22:17:57.244624 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1359 22:17:57.251296 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1360 22:17:57.251375
1361 22:17:57.251436 [DATLAT]
1362 22:17:57.251493 Freq=800, CH0 RK1
1363 22:17:57.251553
1364 22:17:57.254395 DATLAT Default: 0xa
1365 22:17:57.254489 0, 0xFFFF, sum = 0
1366 22:17:57.257788 1, 0xFFFF, sum = 0
1367 22:17:57.257894 2, 0xFFFF, sum = 0
1368 22:17:57.261009 3, 0xFFFF, sum = 0
1369 22:17:57.264360 4, 0xFFFF, sum = 0
1370 22:17:57.264442 5, 0xFFFF, sum = 0
1371 22:17:57.267854 6, 0xFFFF, sum = 0
1372 22:17:57.267936 7, 0xFFFF, sum = 0
1373 22:17:57.271140 8, 0xFFFF, sum = 0
1374 22:17:57.271226 9, 0x0, sum = 1
1375 22:17:57.274606 10, 0x0, sum = 2
1376 22:17:57.274689 11, 0x0, sum = 3
1377 22:17:57.274754 12, 0x0, sum = 4
1378 22:17:57.277703 best_step = 10
1379 22:17:57.277784
1380 22:17:57.277847 ==
1381 22:17:57.281315 Dram Type= 6, Freq= 0, CH_0, rank 1
1382 22:17:57.284421 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1383 22:17:57.284504 ==
1384 22:17:57.287632 RX Vref Scan: 0
1385 22:17:57.287712
1386 22:17:57.287775 RX Vref 0 -> 0, step: 1
1387 22:17:57.291070
1388 22:17:57.291150 RX Delay -95 -> 252, step: 8
1389 22:17:57.298120 iDelay=209, Bit 0, Center 84 (-23 ~ 192) 216
1390 22:17:57.300916 iDelay=209, Bit 1, Center 92 (-15 ~ 200) 216
1391 22:17:57.304763 iDelay=209, Bit 2, Center 80 (-31 ~ 192) 224
1392 22:17:57.307899 iDelay=209, Bit 3, Center 80 (-31 ~ 192) 224
1393 22:17:57.311021 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1394 22:17:57.318041 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1395 22:17:57.321051 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1396 22:17:57.324339 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1397 22:17:57.328193 iDelay=209, Bit 8, Center 64 (-47 ~ 176) 224
1398 22:17:57.331183 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
1399 22:17:57.337624 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1400 22:17:57.341281 iDelay=209, Bit 11, Center 72 (-39 ~ 184) 224
1401 22:17:57.344386 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
1402 22:17:57.347535 iDelay=209, Bit 13, Center 80 (-31 ~ 192) 224
1403 22:17:57.354774 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1404 22:17:57.357608 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
1405 22:17:57.357690 ==
1406 22:17:57.360696 Dram Type= 6, Freq= 0, CH_0, rank 1
1407 22:17:57.364267 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1408 22:17:57.364349 ==
1409 22:17:57.367299 DQS Delay:
1410 22:17:57.367419 DQS0 = 0, DQS1 = 0
1411 22:17:57.367482 DQM Delay:
1412 22:17:57.370668 DQM0 = 86, DQM1 = 76
1413 22:17:57.370749 DQ Delay:
1414 22:17:57.374090 DQ0 =84, DQ1 =92, DQ2 =80, DQ3 =80
1415 22:17:57.377301 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1416 22:17:57.380822 DQ8 =64, DQ9 =64, DQ10 =80, DQ11 =72
1417 22:17:57.383764 DQ12 =80, DQ13 =80, DQ14 =88, DQ15 =84
1418 22:17:57.383845
1419 22:17:57.383908
1420 22:17:57.394181 [DQSOSCAuto] RK1, (LSB)MR18= 0x2521, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 400 ps
1421 22:17:57.397449 CH0 RK1: MR19=606, MR18=2521
1422 22:17:57.400179 CH0_RK1: MR19=0x606, MR18=0x2521, DQSOSC=400, MR23=63, INC=92, DEC=61
1423 22:17:57.404168 [RxdqsGatingPostProcess] freq 800
1424 22:17:57.410466 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1425 22:17:57.413560 Pre-setting of DQS Precalculation
1426 22:17:57.416775 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1427 22:17:57.416858 ==
1428 22:17:57.420150 Dram Type= 6, Freq= 0, CH_1, rank 0
1429 22:17:57.427107 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1430 22:17:57.427190 ==
1431 22:17:57.430024 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1432 22:17:57.436712 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1433 22:17:57.446405 [CA 0] Center 36 (6~67) winsize 62
1434 22:17:57.449789 [CA 1] Center 37 (6~68) winsize 63
1435 22:17:57.452808 [CA 2] Center 35 (5~65) winsize 61
1436 22:17:57.456663 [CA 3] Center 34 (4~65) winsize 62
1437 22:17:57.459692 [CA 4] Center 34 (4~65) winsize 62
1438 22:17:57.463062 [CA 5] Center 34 (3~65) winsize 63
1439 22:17:57.463144
1440 22:17:57.466167 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1441 22:17:57.466250
1442 22:17:57.469584 [CATrainingPosCal] consider 1 rank data
1443 22:17:57.472822 u2DelayCellTimex100 = 270/100 ps
1444 22:17:57.475955 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1445 22:17:57.483095 CA1 delay=37 (6~68),Diff = 3 PI (21 cell)
1446 22:17:57.486133 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1447 22:17:57.489436 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1448 22:17:57.492685 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1449 22:17:57.496059 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1450 22:17:57.496155
1451 22:17:57.499286 CA PerBit enable=1, Macro0, CA PI delay=34
1452 22:17:57.499369
1453 22:17:57.502368 [CBTSetCACLKResult] CA Dly = 34
1454 22:17:57.502451 CS Dly: 4 (0~35)
1455 22:17:57.505632 ==
1456 22:17:57.509327 Dram Type= 6, Freq= 0, CH_1, rank 1
1457 22:17:57.512635 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1458 22:17:57.512718 ==
1459 22:17:57.515842 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1460 22:17:57.522378 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1461 22:17:57.532671 [CA 0] Center 36 (6~67) winsize 62
1462 22:17:57.535579 [CA 1] Center 36 (6~67) winsize 62
1463 22:17:57.538935 [CA 2] Center 34 (4~65) winsize 62
1464 22:17:57.542722 [CA 3] Center 34 (3~65) winsize 63
1465 22:17:57.545757 [CA 4] Center 34 (3~65) winsize 63
1466 22:17:57.549119 [CA 5] Center 33 (3~64) winsize 62
1467 22:17:57.549202
1468 22:17:57.552289 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1469 22:17:57.552371
1470 22:17:57.555973 [CATrainingPosCal] consider 2 rank data
1471 22:17:57.559367 u2DelayCellTimex100 = 270/100 ps
1472 22:17:57.562600 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1473 22:17:57.569204 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1474 22:17:57.572281 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
1475 22:17:57.575265 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1476 22:17:57.579461 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1477 22:17:57.582779 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1478 22:17:57.582863
1479 22:17:57.586246 CA PerBit enable=1, Macro0, CA PI delay=33
1480 22:17:57.586328
1481 22:17:57.590340 [CBTSetCACLKResult] CA Dly = 33
1482 22:17:57.590424 CS Dly: 5 (0~37)
1483 22:17:57.590489
1484 22:17:57.593974 ----->DramcWriteLeveling(PI) begin...
1485 22:17:57.594058 ==
1486 22:17:57.597957 Dram Type= 6, Freq= 0, CH_1, rank 0
1487 22:17:57.602001 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1488 22:17:57.602084 ==
1489 22:17:57.605111 Write leveling (Byte 0): 27 => 27
1490 22:17:57.609016 Write leveling (Byte 1): 27 => 27
1491 22:17:57.612846 DramcWriteLeveling(PI) end<-----
1492 22:17:57.612930
1493 22:17:57.612995 ==
1494 22:17:57.615780 Dram Type= 6, Freq= 0, CH_1, rank 0
1495 22:17:57.619031 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1496 22:17:57.619114 ==
1497 22:17:57.622332 [Gating] SW mode calibration
1498 22:17:57.629118 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1499 22:17:57.632309 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1500 22:17:57.639258 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1501 22:17:57.642190 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1502 22:17:57.645521 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1503 22:17:57.652217 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1504 22:17:57.655255 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1505 22:17:57.658605 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1506 22:17:57.665572 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1507 22:17:57.669257 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1508 22:17:57.671798 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1509 22:17:57.678519 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1510 22:17:57.682276 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1511 22:17:57.685464 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1512 22:17:57.691918 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1513 22:17:57.695345 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1514 22:17:57.698945 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1515 22:17:57.705157 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1516 22:17:57.708623 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1517 22:17:57.712016 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1518 22:17:57.718583 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1519 22:17:57.721910 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1520 22:17:57.725356 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1521 22:17:57.731798 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1522 22:17:57.735606 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 22:17:57.738800 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 22:17:57.745288 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 22:17:57.748448 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 22:17:57.752231 0 9 8 | B1->B0 | 2e2e 3434 | 1 0 | (1 1) (0 0)
1527 22:17:57.755303 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1528 22:17:57.761973 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1529 22:17:57.765269 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1530 22:17:57.771791 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1531 22:17:57.775379 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1532 22:17:57.778394 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1533 22:17:57.781873 0 10 4 | B1->B0 | 3232 2f2f | 1 0 | (1 0) (0 1)
1534 22:17:57.788261 0 10 8 | B1->B0 | 2727 2323 | 0 0 | (1 0) (0 0)
1535 22:17:57.791819 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1536 22:17:57.795241 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1537 22:17:57.801654 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1538 22:17:57.805271 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1539 22:17:57.808239 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1540 22:17:57.814940 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1541 22:17:57.818187 0 11 4 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
1542 22:17:57.821537 0 11 8 | B1->B0 | 3c3c 4545 | 0 0 | (0 0) (0 0)
1543 22:17:57.828296 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1544 22:17:57.831745 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1545 22:17:57.834922 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1546 22:17:57.841783 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1547 22:17:57.844932 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1548 22:17:57.848356 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1549 22:17:57.854868 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1550 22:17:57.857967 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1551 22:17:57.861873 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1552 22:17:57.867955 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1553 22:17:57.871309 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1554 22:17:57.874663 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1555 22:17:57.881236 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1556 22:17:57.884870 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1557 22:17:57.888065 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1558 22:17:57.894781 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1559 22:17:57.897887 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1560 22:17:57.901156 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1561 22:17:57.907662 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1562 22:17:57.911307 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1563 22:17:57.914258 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1564 22:17:57.921173 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1565 22:17:57.924839 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1566 22:17:57.927993 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1567 22:17:57.930771 Total UI for P1: 0, mck2ui 16
1568 22:17:57.934132 best dqsien dly found for B0: ( 0, 14, 4)
1569 22:17:57.937625 Total UI for P1: 0, mck2ui 16
1570 22:17:57.941068 best dqsien dly found for B1: ( 0, 14, 4)
1571 22:17:57.943985 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1572 22:17:57.947604 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1573 22:17:57.947674
1574 22:17:57.950733 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1575 22:17:57.957292 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1576 22:17:57.957368 [Gating] SW calibration Done
1577 22:17:57.957437 ==
1578 22:17:57.960669 Dram Type= 6, Freq= 0, CH_1, rank 0
1579 22:17:57.967543 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1580 22:17:57.967626 ==
1581 22:17:57.967699 RX Vref Scan: 0
1582 22:17:57.967799
1583 22:17:57.970840 RX Vref 0 -> 0, step: 1
1584 22:17:57.970922
1585 22:17:57.974173 RX Delay -130 -> 252, step: 16
1586 22:17:57.977211 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1587 22:17:57.980498 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1588 22:17:57.983704 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1589 22:17:57.990789 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1590 22:17:57.994309 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1591 22:17:57.996971 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1592 22:17:58.000988 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1593 22:17:58.003745 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1594 22:17:58.010595 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1595 22:17:58.013555 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1596 22:17:58.017028 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1597 22:17:58.020409 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1598 22:17:58.023826 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1599 22:17:58.030064 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1600 22:17:58.033467 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1601 22:17:58.037027 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1602 22:17:58.037124 ==
1603 22:17:58.040353 Dram Type= 6, Freq= 0, CH_1, rank 0
1604 22:17:58.043886 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1605 22:17:58.046898 ==
1606 22:17:58.047006 DQS Delay:
1607 22:17:58.047073 DQS0 = 0, DQS1 = 0
1608 22:17:58.050412 DQM Delay:
1609 22:17:58.050494 DQM0 = 87, DQM1 = 79
1610 22:17:58.053759 DQ Delay:
1611 22:17:58.056807 DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =85
1612 22:17:58.056895 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1613 22:17:58.060255 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =69
1614 22:17:58.066777 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1615 22:17:58.066859
1616 22:17:58.066940
1617 22:17:58.067023 ==
1618 22:17:58.070410 Dram Type= 6, Freq= 0, CH_1, rank 0
1619 22:17:58.073332 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1620 22:17:58.073448 ==
1621 22:17:58.073542
1622 22:17:58.073630
1623 22:17:58.076748 TX Vref Scan disable
1624 22:17:58.076830 == TX Byte 0 ==
1625 22:17:58.083762 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1626 22:17:58.087022 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1627 22:17:58.087104 == TX Byte 1 ==
1628 22:17:58.093665 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1629 22:17:58.096654 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1630 22:17:58.096753 ==
1631 22:17:58.099960 Dram Type= 6, Freq= 0, CH_1, rank 0
1632 22:17:58.103432 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1633 22:17:58.103514 ==
1634 22:17:58.117116 TX Vref=22, minBit 0, minWin=27, winSum=441
1635 22:17:58.119941 TX Vref=24, minBit 1, minWin=27, winSum=447
1636 22:17:58.123778 TX Vref=26, minBit 5, minWin=27, winSum=451
1637 22:17:58.126644 TX Vref=28, minBit 5, minWin=27, winSum=453
1638 22:17:58.130059 TX Vref=30, minBit 5, minWin=27, winSum=458
1639 22:17:58.136524 TX Vref=32, minBit 0, minWin=27, winSum=453
1640 22:17:58.140054 [TxChooseVref] Worse bit 5, Min win 27, Win sum 458, Final Vref 30
1641 22:17:58.140151
1642 22:17:58.143443 Final TX Range 1 Vref 30
1643 22:17:58.143548
1644 22:17:58.143652 ==
1645 22:17:58.146829 Dram Type= 6, Freq= 0, CH_1, rank 0
1646 22:17:58.149934 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1647 22:17:58.150017 ==
1648 22:17:58.153348
1649 22:17:58.153429
1650 22:17:58.153494 TX Vref Scan disable
1651 22:17:58.157001 == TX Byte 0 ==
1652 22:17:58.160638 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1653 22:17:58.164361 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1654 22:17:58.167968 == TX Byte 1 ==
1655 22:17:58.171226 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1656 22:17:58.174215 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1657 22:17:58.174328
1658 22:17:58.177956 [DATLAT]
1659 22:17:58.178055 Freq=800, CH1 RK0
1660 22:17:58.178152
1661 22:17:58.181260 DATLAT Default: 0xa
1662 22:17:58.181357 0, 0xFFFF, sum = 0
1663 22:17:58.184498 1, 0xFFFF, sum = 0
1664 22:17:58.184598 2, 0xFFFF, sum = 0
1665 22:17:58.187744 3, 0xFFFF, sum = 0
1666 22:17:58.187828 4, 0xFFFF, sum = 0
1667 22:17:58.190812 5, 0xFFFF, sum = 0
1668 22:17:58.190895 6, 0xFFFF, sum = 0
1669 22:17:58.194190 7, 0xFFFF, sum = 0
1670 22:17:58.194273 8, 0xFFFF, sum = 0
1671 22:17:58.197464 9, 0x0, sum = 1
1672 22:17:58.197547 10, 0x0, sum = 2
1673 22:17:58.201275 11, 0x0, sum = 3
1674 22:17:58.201376 12, 0x0, sum = 4
1675 22:17:58.204641 best_step = 10
1676 22:17:58.204722
1677 22:17:58.204787 ==
1678 22:17:58.207495 Dram Type= 6, Freq= 0, CH_1, rank 0
1679 22:17:58.210790 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1680 22:17:58.210879 ==
1681 22:17:58.210958 RX Vref Scan: 1
1682 22:17:58.214342
1683 22:17:58.214423 Set Vref Range= 32 -> 127
1684 22:17:58.214524
1685 22:17:58.217289 RX Vref 32 -> 127, step: 1
1686 22:17:58.217371
1687 22:17:58.220674 RX Delay -95 -> 252, step: 8
1688 22:17:58.220757
1689 22:17:58.224200 Set Vref, RX VrefLevel [Byte0]: 32
1690 22:17:58.227321 [Byte1]: 32
1691 22:17:58.227419
1692 22:17:58.230743 Set Vref, RX VrefLevel [Byte0]: 33
1693 22:17:58.234210 [Byte1]: 33
1694 22:17:58.234307
1695 22:17:58.237379 Set Vref, RX VrefLevel [Byte0]: 34
1696 22:17:58.240459 [Byte1]: 34
1697 22:17:58.245036
1698 22:17:58.245117 Set Vref, RX VrefLevel [Byte0]: 35
1699 22:17:58.247948 [Byte1]: 35
1700 22:17:58.252413
1701 22:17:58.252494 Set Vref, RX VrefLevel [Byte0]: 36
1702 22:17:58.255465 [Byte1]: 36
1703 22:17:58.259766
1704 22:17:58.259879 Set Vref, RX VrefLevel [Byte0]: 37
1705 22:17:58.263246 [Byte1]: 37
1706 22:17:58.267710
1707 22:17:58.267821 Set Vref, RX VrefLevel [Byte0]: 38
1708 22:17:58.270729 [Byte1]: 38
1709 22:17:58.274933
1710 22:17:58.275034 Set Vref, RX VrefLevel [Byte0]: 39
1711 22:17:58.278495 [Byte1]: 39
1712 22:17:58.282743
1713 22:17:58.282861 Set Vref, RX VrefLevel [Byte0]: 40
1714 22:17:58.286248 [Byte1]: 40
1715 22:17:58.290279
1716 22:17:58.290387 Set Vref, RX VrefLevel [Byte0]: 41
1717 22:17:58.293706 [Byte1]: 41
1718 22:17:58.297796
1719 22:17:58.297901 Set Vref, RX VrefLevel [Byte0]: 42
1720 22:17:58.301254 [Byte1]: 42
1721 22:17:58.305617
1722 22:17:58.305729 Set Vref, RX VrefLevel [Byte0]: 43
1723 22:17:58.308765 [Byte1]: 43
1724 22:17:58.313281
1725 22:17:58.313359 Set Vref, RX VrefLevel [Byte0]: 44
1726 22:17:58.316525 [Byte1]: 44
1727 22:17:58.320691
1728 22:17:58.320778 Set Vref, RX VrefLevel [Byte0]: 45
1729 22:17:58.323774 [Byte1]: 45
1730 22:17:58.328096
1731 22:17:58.328201 Set Vref, RX VrefLevel [Byte0]: 46
1732 22:17:58.331531 [Byte1]: 46
1733 22:17:58.336010
1734 22:17:58.336162 Set Vref, RX VrefLevel [Byte0]: 47
1735 22:17:58.339183 [Byte1]: 47
1736 22:17:58.343201
1737 22:17:58.343300 Set Vref, RX VrefLevel [Byte0]: 48
1738 22:17:58.346575 [Byte1]: 48
1739 22:17:58.351404
1740 22:17:58.351487 Set Vref, RX VrefLevel [Byte0]: 49
1741 22:17:58.354495 [Byte1]: 49
1742 22:17:58.358552
1743 22:17:58.358655 Set Vref, RX VrefLevel [Byte0]: 50
1744 22:17:58.362286 [Byte1]: 50
1745 22:17:58.366144
1746 22:17:58.366249 Set Vref, RX VrefLevel [Byte0]: 51
1747 22:17:58.369814 [Byte1]: 51
1748 22:17:58.373968
1749 22:17:58.374073 Set Vref, RX VrefLevel [Byte0]: 52
1750 22:17:58.377039 [Byte1]: 52
1751 22:17:58.381582
1752 22:17:58.381682 Set Vref, RX VrefLevel [Byte0]: 53
1753 22:17:58.384527 [Byte1]: 53
1754 22:17:58.389015
1755 22:17:58.389088 Set Vref, RX VrefLevel [Byte0]: 54
1756 22:17:58.392579 [Byte1]: 54
1757 22:17:58.396405
1758 22:17:58.396477 Set Vref, RX VrefLevel [Byte0]: 55
1759 22:17:58.400361 [Byte1]: 55
1760 22:17:58.404002
1761 22:17:58.404148 Set Vref, RX VrefLevel [Byte0]: 56
1762 22:17:58.407483 [Byte1]: 56
1763 22:17:58.411553
1764 22:17:58.411636 Set Vref, RX VrefLevel [Byte0]: 57
1765 22:17:58.414858 [Byte1]: 57
1766 22:17:58.419388
1767 22:17:58.419465 Set Vref, RX VrefLevel [Byte0]: 58
1768 22:17:58.422919 [Byte1]: 58
1769 22:17:58.426942
1770 22:17:58.427018 Set Vref, RX VrefLevel [Byte0]: 59
1771 22:17:58.430102 [Byte1]: 59
1772 22:17:58.434851
1773 22:17:58.434960 Set Vref, RX VrefLevel [Byte0]: 60
1774 22:17:58.438074 [Byte1]: 60
1775 22:17:58.442028
1776 22:17:58.442104 Set Vref, RX VrefLevel [Byte0]: 61
1777 22:17:58.445255 [Byte1]: 61
1778 22:17:58.449801
1779 22:17:58.449877 Set Vref, RX VrefLevel [Byte0]: 62
1780 22:17:58.452933 [Byte1]: 62
1781 22:17:58.457372
1782 22:17:58.457456 Set Vref, RX VrefLevel [Byte0]: 63
1783 22:17:58.460727 [Byte1]: 63
1784 22:17:58.465222
1785 22:17:58.465337 Set Vref, RX VrefLevel [Byte0]: 64
1786 22:17:58.468311 [Byte1]: 64
1787 22:17:58.472923
1788 22:17:58.473005 Set Vref, RX VrefLevel [Byte0]: 65
1789 22:17:58.475765 [Byte1]: 65
1790 22:17:58.480382
1791 22:17:58.480464 Set Vref, RX VrefLevel [Byte0]: 66
1792 22:17:58.483315 [Byte1]: 66
1793 22:17:58.487710
1794 22:17:58.487800 Set Vref, RX VrefLevel [Byte0]: 67
1795 22:17:58.490829 [Byte1]: 67
1796 22:17:58.495329
1797 22:17:58.495411 Set Vref, RX VrefLevel [Byte0]: 68
1798 22:17:58.499031 [Byte1]: 68
1799 22:17:58.502862
1800 22:17:58.502943 Set Vref, RX VrefLevel [Byte0]: 69
1801 22:17:58.505943 [Byte1]: 69
1802 22:17:58.510453
1803 22:17:58.510534 Set Vref, RX VrefLevel [Byte0]: 70
1804 22:17:58.513622 [Byte1]: 70
1805 22:17:58.517904
1806 22:17:58.517986 Set Vref, RX VrefLevel [Byte0]: 71
1807 22:17:58.521661 [Byte1]: 71
1808 22:17:58.525724
1809 22:17:58.525805 Set Vref, RX VrefLevel [Byte0]: 72
1810 22:17:58.529129 [Byte1]: 72
1811 22:17:58.533089
1812 22:17:58.533171 Set Vref, RX VrefLevel [Byte0]: 73
1813 22:17:58.536784 [Byte1]: 73
1814 22:17:58.541080
1815 22:17:58.541162 Set Vref, RX VrefLevel [Byte0]: 74
1816 22:17:58.544066 [Byte1]: 74
1817 22:17:58.548671
1818 22:17:58.548753 Final RX Vref Byte 0 = 59 to rank0
1819 22:17:58.551823 Final RX Vref Byte 1 = 57 to rank0
1820 22:17:58.555042 Final RX Vref Byte 0 = 59 to rank1
1821 22:17:58.558587 Final RX Vref Byte 1 = 57 to rank1==
1822 22:17:58.562195 Dram Type= 6, Freq= 0, CH_1, rank 0
1823 22:17:58.568182 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1824 22:17:58.568271 ==
1825 22:17:58.568337 DQS Delay:
1826 22:17:58.571893 DQS0 = 0, DQS1 = 0
1827 22:17:58.571970 DQM Delay:
1828 22:17:58.572057 DQM0 = 86, DQM1 = 80
1829 22:17:58.575084 DQ Delay:
1830 22:17:58.578376 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
1831 22:17:58.581961 DQ4 =84, DQ5 =96, DQ6 =96, DQ7 =84
1832 22:17:58.584997 DQ8 =68, DQ9 =72, DQ10 =80, DQ11 =72
1833 22:17:58.588156 DQ12 =88, DQ13 =88, DQ14 =84, DQ15 =88
1834 22:17:58.588254
1835 22:17:58.588334
1836 22:17:58.594694 [DQSOSCAuto] RK0, (LSB)MR18= 0x1d30, (MSB)MR19= 0x606, tDQSOscB0 = 397 ps tDQSOscB1 = 402 ps
1837 22:17:58.598583 CH1 RK0: MR19=606, MR18=1D30
1838 22:17:58.605007 CH1_RK0: MR19=0x606, MR18=0x1D30, DQSOSC=397, MR23=63, INC=93, DEC=62
1839 22:17:58.605090
1840 22:17:58.608355 ----->DramcWriteLeveling(PI) begin...
1841 22:17:58.608453 ==
1842 22:17:58.611713 Dram Type= 6, Freq= 0, CH_1, rank 1
1843 22:17:58.614593 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1844 22:17:58.614692 ==
1845 22:17:58.618313 Write leveling (Byte 0): 29 => 29
1846 22:17:58.621536 Write leveling (Byte 1): 26 => 26
1847 22:17:58.624684 DramcWriteLeveling(PI) end<-----
1848 22:17:58.624803
1849 22:17:58.624868 ==
1850 22:17:58.628464 Dram Type= 6, Freq= 0, CH_1, rank 1
1851 22:17:58.631736 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1852 22:17:58.631819 ==
1853 22:17:58.634433 [Gating] SW mode calibration
1854 22:17:58.641257 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1855 22:17:58.647597 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1856 22:17:58.651101 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1857 22:17:58.657991 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1858 22:17:58.661027 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1859 22:17:58.664556 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1860 22:17:58.670996 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1861 22:17:58.674572 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1862 22:17:58.677667 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1863 22:17:58.681128 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1864 22:17:58.687330 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1865 22:17:58.690610 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1866 22:17:58.693954 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1867 22:17:58.701146 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1868 22:17:58.704419 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1869 22:17:58.710588 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1870 22:17:58.714056 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1871 22:17:58.717592 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1872 22:17:58.720643 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1873 22:17:58.727187 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1874 22:17:58.730595 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1875 22:17:58.733946 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1876 22:17:58.740619 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1877 22:17:58.743961 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1878 22:17:58.747261 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1879 22:17:58.753965 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1880 22:17:58.757537 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1881 22:17:58.760510 0 9 4 | B1->B0 | 2323 2626 | 0 1 | (0 0) (0 0)
1882 22:17:58.767484 0 9 8 | B1->B0 | 2c2c 3434 | 1 1 | (1 1) (1 1)
1883 22:17:58.770323 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1884 22:17:58.773830 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1885 22:17:58.780414 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1886 22:17:58.783495 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1887 22:17:58.786914 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1888 22:17:58.793656 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1889 22:17:58.796751 0 10 4 | B1->B0 | 3333 2f2f | 1 0 | (1 0) (0 0)
1890 22:17:58.800045 0 10 8 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
1891 22:17:58.807229 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1892 22:17:58.810463 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1893 22:17:58.813592 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1894 22:17:58.820310 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1895 22:17:58.823391 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1896 22:17:58.827179 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1897 22:17:58.833513 0 11 4 | B1->B0 | 2323 3636 | 0 0 | (0 0) (0 0)
1898 22:17:58.836576 0 11 8 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
1899 22:17:58.839985 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1900 22:17:58.846388 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1901 22:17:58.849620 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1902 22:17:58.852945 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1903 22:17:58.859777 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1904 22:17:58.863195 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1905 22:17:58.866243 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1906 22:17:58.872823 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1907 22:17:58.876297 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1908 22:17:58.879287 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1909 22:17:58.886247 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1910 22:17:58.889111 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1911 22:17:58.892693 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1912 22:17:58.899212 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1913 22:17:58.902526 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1914 22:17:58.906460 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1915 22:17:58.912627 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1916 22:17:58.916034 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1917 22:17:58.919285 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1918 22:17:58.925741 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1919 22:17:58.929320 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1920 22:17:58.932728 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
1921 22:17:58.935771 Total UI for P1: 0, mck2ui 16
1922 22:17:58.938968 best dqsien dly found for B0: ( 0, 13, 30)
1923 22:17:58.942209 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1924 22:17:58.948757 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1925 22:17:58.952295 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1926 22:17:58.955677 Total UI for P1: 0, mck2ui 16
1927 22:17:58.958904 best dqsien dly found for B1: ( 0, 14, 6)
1928 22:17:58.962661 best DQS0 dly(MCK, UI, PI) = (0, 13, 30)
1929 22:17:58.965929 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1930 22:17:58.966012
1931 22:17:58.968974 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 30)
1932 22:17:58.975302 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1933 22:17:58.975380 [Gating] SW calibration Done
1934 22:17:58.975446 ==
1935 22:17:58.978854 Dram Type= 6, Freq= 0, CH_1, rank 1
1936 22:17:58.985340 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1937 22:17:58.985448 ==
1938 22:17:58.985542 RX Vref Scan: 0
1939 22:17:58.985632
1940 22:17:58.988498 RX Vref 0 -> 0, step: 1
1941 22:17:58.988567
1942 22:17:58.991907 RX Delay -130 -> 252, step: 16
1943 22:17:58.994932 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1944 22:17:58.998503 iDelay=206, Bit 1, Center 77 (-50 ~ 205) 256
1945 22:17:59.001494 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1946 22:17:59.008634 iDelay=206, Bit 3, Center 69 (-50 ~ 189) 240
1947 22:17:59.011544 iDelay=206, Bit 4, Center 77 (-50 ~ 205) 256
1948 22:17:59.014880 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1949 22:17:59.018434 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1950 22:17:59.021584 iDelay=206, Bit 7, Center 77 (-50 ~ 205) 256
1951 22:17:59.028427 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1952 22:17:59.031753 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1953 22:17:59.034997 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1954 22:17:59.038328 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1955 22:17:59.041768 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224
1956 22:17:59.048753 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1957 22:17:59.051342 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1958 22:17:59.054938 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1959 22:17:59.055007 ==
1960 22:17:59.058100 Dram Type= 6, Freq= 0, CH_1, rank 1
1961 22:17:59.062030 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1962 22:17:59.064592 ==
1963 22:17:59.064661 DQS Delay:
1964 22:17:59.064722 DQS0 = 0, DQS1 = 0
1965 22:17:59.068415 DQM Delay:
1966 22:17:59.068485 DQM0 = 80, DQM1 = 80
1967 22:17:59.071485 DQ Delay:
1968 22:17:59.074798 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =69
1969 22:17:59.074896 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1970 22:17:59.077680 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =69
1971 22:17:59.084369 DQ12 =93, DQ13 =85, DQ14 =85, DQ15 =85
1972 22:17:59.084445
1973 22:17:59.084508
1974 22:17:59.084565 ==
1975 22:17:59.087710 Dram Type= 6, Freq= 0, CH_1, rank 1
1976 22:17:59.091366 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1977 22:17:59.091450 ==
1978 22:17:59.091512
1979 22:17:59.091600
1980 22:17:59.094653 TX Vref Scan disable
1981 22:17:59.094720 == TX Byte 0 ==
1982 22:17:59.101417 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1983 22:17:59.104538 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1984 22:17:59.104609 == TX Byte 1 ==
1985 22:17:59.111175 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1986 22:17:59.114512 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1987 22:17:59.114614 ==
1988 22:17:59.117628 Dram Type= 6, Freq= 0, CH_1, rank 1
1989 22:17:59.121201 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1990 22:17:59.121274 ==
1991 22:17:59.135006 TX Vref=22, minBit 1, minWin=27, winSum=445
1992 22:17:59.138414 TX Vref=24, minBit 1, minWin=27, winSum=450
1993 22:17:59.142029 TX Vref=26, minBit 6, minWin=26, winSum=450
1994 22:17:59.145210 TX Vref=28, minBit 5, minWin=27, winSum=454
1995 22:17:59.148421 TX Vref=30, minBit 2, minWin=27, winSum=455
1996 22:17:59.154906 TX Vref=32, minBit 5, minWin=27, winSum=456
1997 22:17:59.158214 [TxChooseVref] Worse bit 5, Min win 27, Win sum 456, Final Vref 32
1998 22:17:59.158309
1999 22:17:59.161403 Final TX Range 1 Vref 32
2000 22:17:59.161475
2001 22:17:59.161536 ==
2002 22:17:59.165041 Dram Type= 6, Freq= 0, CH_1, rank 1
2003 22:17:59.168240 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2004 22:17:59.168334 ==
2005 22:17:59.171527
2006 22:17:59.171597
2007 22:17:59.171657 TX Vref Scan disable
2008 22:17:59.174907 == TX Byte 0 ==
2009 22:17:59.178600 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
2010 22:17:59.185062 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
2011 22:17:59.185135 == TX Byte 1 ==
2012 22:17:59.188274 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
2013 22:17:59.191765 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
2014 22:17:59.194898
2015 22:17:59.194972 [DATLAT]
2016 22:17:59.195039 Freq=800, CH1 RK1
2017 22:17:59.195098
2018 22:17:59.198174 DATLAT Default: 0xa
2019 22:17:59.198268 0, 0xFFFF, sum = 0
2020 22:17:59.201693 1, 0xFFFF, sum = 0
2021 22:17:59.201766 2, 0xFFFF, sum = 0
2022 22:17:59.205261 3, 0xFFFF, sum = 0
2023 22:17:59.205374 4, 0xFFFF, sum = 0
2024 22:17:59.208302 5, 0xFFFF, sum = 0
2025 22:17:59.211767 6, 0xFFFF, sum = 0
2026 22:17:59.211858 7, 0xFFFF, sum = 0
2027 22:17:59.215063 8, 0xFFFF, sum = 0
2028 22:17:59.215163 9, 0x0, sum = 1
2029 22:17:59.218004 10, 0x0, sum = 2
2030 22:17:59.218107 11, 0x0, sum = 3
2031 22:17:59.218242 12, 0x0, sum = 4
2032 22:17:59.221229 best_step = 10
2033 22:17:59.221342
2034 22:17:59.221446 ==
2035 22:17:59.224878 Dram Type= 6, Freq= 0, CH_1, rank 1
2036 22:17:59.227959 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2037 22:17:59.228091 ==
2038 22:17:59.231267 RX Vref Scan: 0
2039 22:17:59.231339
2040 22:17:59.231399 RX Vref 0 -> 0, step: 1
2041 22:17:59.234493
2042 22:17:59.234583 RX Delay -95 -> 252, step: 8
2043 22:17:59.241912 iDelay=209, Bit 0, Center 92 (-23 ~ 208) 232
2044 22:17:59.244996 iDelay=209, Bit 1, Center 80 (-39 ~ 200) 240
2045 22:17:59.248347 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
2046 22:17:59.251571 iDelay=209, Bit 3, Center 80 (-31 ~ 192) 224
2047 22:17:59.255418 iDelay=209, Bit 4, Center 84 (-31 ~ 200) 232
2048 22:17:59.261371 iDelay=209, Bit 5, Center 96 (-15 ~ 208) 224
2049 22:17:59.265210 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
2050 22:17:59.268453 iDelay=209, Bit 7, Center 84 (-31 ~ 200) 232
2051 22:17:59.271826 iDelay=209, Bit 8, Center 72 (-39 ~ 184) 224
2052 22:17:59.275017 iDelay=209, Bit 9, Center 72 (-39 ~ 184) 224
2053 22:17:59.281379 iDelay=209, Bit 10, Center 84 (-31 ~ 200) 232
2054 22:17:59.284919 iDelay=209, Bit 11, Center 76 (-39 ~ 192) 232
2055 22:17:59.288404 iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216
2056 22:17:59.291028 iDelay=209, Bit 13, Center 92 (-15 ~ 200) 216
2057 22:17:59.297846 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
2058 22:17:59.301521 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
2059 22:17:59.301611 ==
2060 22:17:59.304709 Dram Type= 6, Freq= 0, CH_1, rank 1
2061 22:17:59.307977 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2062 22:17:59.308334 ==
2063 22:17:59.311285 DQS Delay:
2064 22:17:59.311357 DQS0 = 0, DQS1 = 0
2065 22:17:59.311419 DQM Delay:
2066 22:17:59.314911 DQM0 = 86, DQM1 = 83
2067 22:17:59.315012 DQ Delay:
2068 22:17:59.317828 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =80
2069 22:17:59.321302 DQ4 =84, DQ5 =96, DQ6 =96, DQ7 =84
2070 22:17:59.324412 DQ8 =72, DQ9 =72, DQ10 =84, DQ11 =76
2071 22:17:59.327921 DQ12 =92, DQ13 =92, DQ14 =88, DQ15 =88
2072 22:17:59.328019
2073 22:17:59.328133
2074 22:17:59.337655 [DQSOSCAuto] RK1, (LSB)MR18= 0x223e, (MSB)MR19= 0x606, tDQSOscB0 = 394 ps tDQSOscB1 = 401 ps
2075 22:17:59.337731 CH1 RK1: MR19=606, MR18=223E
2076 22:17:59.344131 CH1_RK1: MR19=0x606, MR18=0x223E, DQSOSC=394, MR23=63, INC=95, DEC=63
2077 22:17:59.347828 [RxdqsGatingPostProcess] freq 800
2078 22:17:59.354150 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2079 22:17:59.357315 Pre-setting of DQS Precalculation
2080 22:17:59.361214 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2081 22:17:59.370878 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2082 22:17:59.377202 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2083 22:17:59.377306
2084 22:17:59.377403
2085 22:17:59.380617 [Calibration Summary] 1600 Mbps
2086 22:17:59.380692 CH 0, Rank 0
2087 22:17:59.384189 SW Impedance : PASS
2088 22:17:59.384260 DUTY Scan : NO K
2089 22:17:59.387364 ZQ Calibration : PASS
2090 22:17:59.390522 Jitter Meter : NO K
2091 22:17:59.390617 CBT Training : PASS
2092 22:17:59.393896 Write leveling : PASS
2093 22:17:59.397211 RX DQS gating : PASS
2094 22:17:59.397280 RX DQ/DQS(RDDQC) : PASS
2095 22:17:59.400968 TX DQ/DQS : PASS
2096 22:17:59.404142 RX DATLAT : PASS
2097 22:17:59.404216 RX DQ/DQS(Engine): PASS
2098 22:17:59.406936 TX OE : NO K
2099 22:17:59.407031 All Pass.
2100 22:17:59.407119
2101 22:17:59.410318 CH 0, Rank 1
2102 22:17:59.410394 SW Impedance : PASS
2103 22:17:59.413817 DUTY Scan : NO K
2104 22:17:59.413905 ZQ Calibration : PASS
2105 22:17:59.416979 Jitter Meter : NO K
2106 22:17:59.420503 CBT Training : PASS
2107 22:17:59.420575 Write leveling : PASS
2108 22:17:59.423736 RX DQS gating : PASS
2109 22:17:59.426900 RX DQ/DQS(RDDQC) : PASS
2110 22:17:59.426977 TX DQ/DQS : PASS
2111 22:17:59.430207 RX DATLAT : PASS
2112 22:17:59.434114 RX DQ/DQS(Engine): PASS
2113 22:17:59.434196 TX OE : NO K
2114 22:17:59.436648 All Pass.
2115 22:17:59.436724
2116 22:17:59.436787 CH 1, Rank 0
2117 22:17:59.440347 SW Impedance : PASS
2118 22:17:59.440420 DUTY Scan : NO K
2119 22:17:59.443558 ZQ Calibration : PASS
2120 22:17:59.447015 Jitter Meter : NO K
2121 22:17:59.447088 CBT Training : PASS
2122 22:17:59.450296 Write leveling : PASS
2123 22:17:59.453561 RX DQS gating : PASS
2124 22:17:59.453659 RX DQ/DQS(RDDQC) : PASS
2125 22:17:59.456783 TX DQ/DQS : PASS
2126 22:17:59.460399 RX DATLAT : PASS
2127 22:17:59.460477 RX DQ/DQS(Engine): PASS
2128 22:17:59.463446 TX OE : NO K
2129 22:17:59.463517 All Pass.
2130 22:17:59.463579
2131 22:17:59.466681 CH 1, Rank 1
2132 22:17:59.466778 SW Impedance : PASS
2133 22:17:59.469741 DUTY Scan : NO K
2134 22:17:59.473308 ZQ Calibration : PASS
2135 22:17:59.473380 Jitter Meter : NO K
2136 22:17:59.476786 CBT Training : PASS
2137 22:17:59.476861 Write leveling : PASS
2138 22:17:59.480352 RX DQS gating : PASS
2139 22:17:59.483377 RX DQ/DQS(RDDQC) : PASS
2140 22:17:59.483473 TX DQ/DQS : PASS
2141 22:17:59.486921 RX DATLAT : PASS
2142 22:17:59.490177 RX DQ/DQS(Engine): PASS
2143 22:17:59.490247 TX OE : NO K
2144 22:17:59.493305 All Pass.
2145 22:17:59.493374
2146 22:17:59.493434 DramC Write-DBI off
2147 22:17:59.496595 PER_BANK_REFRESH: Hybrid Mode
2148 22:17:59.496666 TX_TRACKING: ON
2149 22:17:59.502972 [GetDramInforAfterCalByMRR] Vendor 6.
2150 22:17:59.506742 [GetDramInforAfterCalByMRR] Revision 606.
2151 22:17:59.510202 [GetDramInforAfterCalByMRR] Revision 2 0.
2152 22:17:59.510303 MR0 0x3b3b
2153 22:17:59.510394 MR8 0x5151
2154 22:17:59.512934 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2155 22:17:59.516598
2156 22:17:59.516699 MR0 0x3b3b
2157 22:17:59.516789 MR8 0x5151
2158 22:17:59.519928 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2159 22:17:59.520024
2160 22:17:59.529902 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2161 22:17:59.532911 [FAST_K] Save calibration result to emmc
2162 22:17:59.536229 [FAST_K] Save calibration result to emmc
2163 22:17:59.539674 dram_init: config_dvfs: 1
2164 22:17:59.543151 dramc_set_vcore_voltage set vcore to 662500
2165 22:17:59.546346 Read voltage for 1200, 2
2166 22:17:59.546417 Vio18 = 0
2167 22:17:59.546481 Vcore = 662500
2168 22:17:59.549528 Vdram = 0
2169 22:17:59.549622 Vddq = 0
2170 22:17:59.549711 Vmddr = 0
2171 22:17:59.556047 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2172 22:17:59.559147 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2173 22:17:59.562814 MEM_TYPE=3, freq_sel=15
2174 22:17:59.565915 sv_algorithm_assistance_LP4_1600
2175 22:17:59.569229 ============ PULL DRAM RESETB DOWN ============
2176 22:17:59.575938 ========== PULL DRAM RESETB DOWN end =========
2177 22:17:59.579091 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2178 22:17:59.582824 ===================================
2179 22:17:59.586085 LPDDR4 DRAM CONFIGURATION
2180 22:17:59.589208 ===================================
2181 22:17:59.589276 EX_ROW_EN[0] = 0x0
2182 22:17:59.592375 EX_ROW_EN[1] = 0x0
2183 22:17:59.592442 LP4Y_EN = 0x0
2184 22:17:59.595985 WORK_FSP = 0x0
2185 22:17:59.596117 WL = 0x4
2186 22:17:59.598957 RL = 0x4
2187 22:17:59.599023 BL = 0x2
2188 22:17:59.602638 RPST = 0x0
2189 22:17:59.602733 RD_PRE = 0x0
2190 22:17:59.605847 WR_PRE = 0x1
2191 22:17:59.608880 WR_PST = 0x0
2192 22:17:59.608990 DBI_WR = 0x0
2193 22:17:59.611989 DBI_RD = 0x0
2194 22:17:59.612096 OTF = 0x1
2195 22:17:59.615729 ===================================
2196 22:17:59.618803 ===================================
2197 22:17:59.622221 ANA top config
2198 22:17:59.625273 ===================================
2199 22:17:59.625349 DLL_ASYNC_EN = 0
2200 22:17:59.628737 ALL_SLAVE_EN = 0
2201 22:17:59.631707 NEW_RANK_MODE = 1
2202 22:17:59.635407 DLL_IDLE_MODE = 1
2203 22:17:59.635489 LP45_APHY_COMB_EN = 1
2204 22:17:59.638698 TX_ODT_DIS = 1
2205 22:17:59.642040 NEW_8X_MODE = 1
2206 22:17:59.645104 ===================================
2207 22:17:59.648403 ===================================
2208 22:17:59.651840 data_rate = 2400
2209 22:17:59.655311 CKR = 1
2210 22:17:59.658722 DQ_P2S_RATIO = 8
2211 22:17:59.661869 ===================================
2212 22:17:59.661967 CA_P2S_RATIO = 8
2213 22:17:59.664898 DQ_CA_OPEN = 0
2214 22:17:59.668286 DQ_SEMI_OPEN = 0
2215 22:17:59.671589 CA_SEMI_OPEN = 0
2216 22:17:59.675344 CA_FULL_RATE = 0
2217 22:17:59.678536 DQ_CKDIV4_EN = 0
2218 22:17:59.678634 CA_CKDIV4_EN = 0
2219 22:17:59.681613 CA_PREDIV_EN = 0
2220 22:17:59.684976 PH8_DLY = 17
2221 22:17:59.688041 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2222 22:17:59.691726 DQ_AAMCK_DIV = 4
2223 22:17:59.695229 CA_AAMCK_DIV = 4
2224 22:17:59.695297 CA_ADMCK_DIV = 4
2225 22:17:59.698272 DQ_TRACK_CA_EN = 0
2226 22:17:59.701519 CA_PICK = 1200
2227 22:17:59.704756 CA_MCKIO = 1200
2228 22:17:59.708303 MCKIO_SEMI = 0
2229 22:17:59.711645 PLL_FREQ = 2366
2230 22:17:59.714825 DQ_UI_PI_RATIO = 32
2231 22:17:59.714922 CA_UI_PI_RATIO = 0
2232 22:17:59.717859 ===================================
2233 22:17:59.721573 ===================================
2234 22:17:59.724608 memory_type:LPDDR4
2235 22:17:59.727956 GP_NUM : 10
2236 22:17:59.728090 SRAM_EN : 1
2237 22:17:59.731283 MD32_EN : 0
2238 22:17:59.734503 ===================================
2239 22:17:59.737809 [ANA_INIT] >>>>>>>>>>>>>>
2240 22:17:59.741188 <<<<<< [CONFIGURE PHASE]: ANA_TX
2241 22:17:59.745013 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2242 22:17:59.747816 ===================================
2243 22:17:59.747891 data_rate = 2400,PCW = 0X5b00
2244 22:17:59.751027 ===================================
2245 22:17:59.754925 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2246 22:17:59.761251 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2247 22:17:59.767645 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2248 22:17:59.771168 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2249 22:17:59.774492 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2250 22:17:59.777574 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2251 22:17:59.780787 [ANA_INIT] flow start
2252 22:17:59.784212 [ANA_INIT] PLL >>>>>>>>
2253 22:17:59.784283 [ANA_INIT] PLL <<<<<<<<
2254 22:17:59.787389 [ANA_INIT] MIDPI >>>>>>>>
2255 22:17:59.790547 [ANA_INIT] MIDPI <<<<<<<<
2256 22:17:59.790642 [ANA_INIT] DLL >>>>>>>>
2257 22:17:59.794277 [ANA_INIT] DLL <<<<<<<<
2258 22:17:59.797481 [ANA_INIT] flow end
2259 22:17:59.800796 ============ LP4 DIFF to SE enter ============
2260 22:17:59.803935 ============ LP4 DIFF to SE exit ============
2261 22:17:59.806996 [ANA_INIT] <<<<<<<<<<<<<
2262 22:17:59.810383 [Flow] Enable top DCM control >>>>>
2263 22:17:59.814009 [Flow] Enable top DCM control <<<<<
2264 22:17:59.817170 Enable DLL master slave shuffle
2265 22:17:59.820510 ==============================================================
2266 22:17:59.823855 Gating Mode config
2267 22:17:59.830425 ==============================================================
2268 22:17:59.830502 Config description:
2269 22:17:59.840661 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2270 22:17:59.847517 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2271 22:17:59.853679 SELPH_MODE 0: By rank 1: By Phase
2272 22:17:59.857170 ==============================================================
2273 22:17:59.860315 GAT_TRACK_EN = 1
2274 22:17:59.863764 RX_GATING_MODE = 2
2275 22:17:59.866955 RX_GATING_TRACK_MODE = 2
2276 22:17:59.870250 SELPH_MODE = 1
2277 22:17:59.873690 PICG_EARLY_EN = 1
2278 22:17:59.877178 VALID_LAT_VALUE = 1
2279 22:17:59.880787 ==============================================================
2280 22:17:59.883828 Enter into Gating configuration >>>>
2281 22:17:59.887057 Exit from Gating configuration <<<<
2282 22:17:59.890255 Enter into DVFS_PRE_config >>>>>
2283 22:17:59.903566 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2284 22:17:59.903648 Exit from DVFS_PRE_config <<<<<
2285 22:17:59.907296 Enter into PICG configuration >>>>
2286 22:17:59.910507 Exit from PICG configuration <<<<
2287 22:17:59.913888 [RX_INPUT] configuration >>>>>
2288 22:17:59.917005 [RX_INPUT] configuration <<<<<
2289 22:17:59.923405 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2290 22:17:59.927367 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2291 22:17:59.933546 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2292 22:17:59.940366 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2293 22:17:59.946792 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2294 22:17:59.953621 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2295 22:17:59.956777 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2296 22:17:59.960176 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2297 22:17:59.963392 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2298 22:17:59.970019 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2299 22:17:59.973451 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2300 22:17:59.976268 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2301 22:17:59.979841 ===================================
2302 22:17:59.983097 LPDDR4 DRAM CONFIGURATION
2303 22:17:59.986078 ===================================
2304 22:17:59.989813 EX_ROW_EN[0] = 0x0
2305 22:17:59.989882 EX_ROW_EN[1] = 0x0
2306 22:17:59.992925 LP4Y_EN = 0x0
2307 22:17:59.992993 WORK_FSP = 0x0
2308 22:17:59.996205 WL = 0x4
2309 22:17:59.996273 RL = 0x4
2310 22:17:59.999644 BL = 0x2
2311 22:17:59.999738 RPST = 0x0
2312 22:18:00.002737 RD_PRE = 0x0
2313 22:18:00.002832 WR_PRE = 0x1
2314 22:18:00.006014 WR_PST = 0x0
2315 22:18:00.006082 DBI_WR = 0x0
2316 22:18:00.009980 DBI_RD = 0x0
2317 22:18:00.010050 OTF = 0x1
2318 22:18:00.013173 ===================================
2319 22:18:00.019405 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2320 22:18:00.022819 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2321 22:18:00.026587 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2322 22:18:00.029614 ===================================
2323 22:18:00.032763 LPDDR4 DRAM CONFIGURATION
2324 22:18:00.035985 ===================================
2325 22:18:00.036079 EX_ROW_EN[0] = 0x10
2326 22:18:00.039428 EX_ROW_EN[1] = 0x0
2327 22:18:00.043178 LP4Y_EN = 0x0
2328 22:18:00.043274 WORK_FSP = 0x0
2329 22:18:00.046087 WL = 0x4
2330 22:18:00.046156 RL = 0x4
2331 22:18:00.049771 BL = 0x2
2332 22:18:00.049872 RPST = 0x0
2333 22:18:00.052609 RD_PRE = 0x0
2334 22:18:00.052705 WR_PRE = 0x1
2335 22:18:00.056012 WR_PST = 0x0
2336 22:18:00.056099 DBI_WR = 0x0
2337 22:18:00.059407 DBI_RD = 0x0
2338 22:18:00.059497 OTF = 0x1
2339 22:18:00.062735 ===================================
2340 22:18:00.069059 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2341 22:18:00.069144 ==
2342 22:18:00.072207 Dram Type= 6, Freq= 0, CH_0, rank 0
2343 22:18:00.079471 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2344 22:18:00.079553 ==
2345 22:18:00.079619 [Duty_Offset_Calibration]
2346 22:18:00.082581 B0:2 B1:0 CA:4
2347 22:18:00.082663
2348 22:18:00.085694 [DutyScan_Calibration_Flow] k_type=0
2349 22:18:00.094025
2350 22:18:00.094108 ==CLK 0==
2351 22:18:00.097001 Final CLK duty delay cell = -4
2352 22:18:00.100057 [-4] MAX Duty = 5031%(X100), DQS PI = 14
2353 22:18:00.103492 [-4] MIN Duty = 4844%(X100), DQS PI = 8
2354 22:18:00.106924 [-4] AVG Duty = 4937%(X100)
2355 22:18:00.107007
2356 22:18:00.109941 CH0 CLK Duty spec in!! Max-Min= 187%
2357 22:18:00.113261 [DutyScan_Calibration_Flow] ====Done====
2358 22:18:00.113343
2359 22:18:00.116836 [DutyScan_Calibration_Flow] k_type=1
2360 22:18:00.133461
2361 22:18:00.133543 ==DQS 0 ==
2362 22:18:00.136611 Final DQS duty delay cell = 0
2363 22:18:00.139826 [0] MAX Duty = 5156%(X100), DQS PI = 18
2364 22:18:00.143494 [0] MIN Duty = 5093%(X100), DQS PI = 0
2365 22:18:00.143575 [0] AVG Duty = 5124%(X100)
2366 22:18:00.146501
2367 22:18:00.146581 ==DQS 1 ==
2368 22:18:00.150197 Final DQS duty delay cell = 0
2369 22:18:00.153699 [0] MAX Duty = 5125%(X100), DQS PI = 4
2370 22:18:00.156803 [0] MIN Duty = 5000%(X100), DQS PI = 0
2371 22:18:00.156884 [0] AVG Duty = 5062%(X100)
2372 22:18:00.160050
2373 22:18:00.163151 CH0 DQS 0 Duty spec in!! Max-Min= 63%
2374 22:18:00.163232
2375 22:18:00.166309 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2376 22:18:00.169898 [DutyScan_Calibration_Flow] ====Done====
2377 22:18:00.169978
2378 22:18:00.173289 [DutyScan_Calibration_Flow] k_type=3
2379 22:18:00.189652
2380 22:18:00.189733 ==DQM 0 ==
2381 22:18:00.192991 Final DQM duty delay cell = 0
2382 22:18:00.196264 [0] MAX Duty = 5125%(X100), DQS PI = 20
2383 22:18:00.199250 [0] MIN Duty = 4844%(X100), DQS PI = 54
2384 22:18:00.202793 [0] AVG Duty = 4984%(X100)
2385 22:18:00.202873
2386 22:18:00.202935 ==DQM 1 ==
2387 22:18:00.206247 Final DQM duty delay cell = 0
2388 22:18:00.209478 [0] MAX Duty = 4969%(X100), DQS PI = 2
2389 22:18:00.212858 [0] MIN Duty = 4876%(X100), DQS PI = 20
2390 22:18:00.215837 [0] AVG Duty = 4922%(X100)
2391 22:18:00.215917
2392 22:18:00.219269 CH0 DQM 0 Duty spec in!! Max-Min= 281%
2393 22:18:00.219350
2394 22:18:00.222714 CH0 DQM 1 Duty spec in!! Max-Min= 93%
2395 22:18:00.226096 [DutyScan_Calibration_Flow] ====Done====
2396 22:18:00.226176
2397 22:18:00.229259 [DutyScan_Calibration_Flow] k_type=2
2398 22:18:00.245712
2399 22:18:00.245790 ==DQ 0 ==
2400 22:18:00.249080 Final DQ duty delay cell = 0
2401 22:18:00.252517 [0] MAX Duty = 5125%(X100), DQS PI = 18
2402 22:18:00.255521 [0] MIN Duty = 4969%(X100), DQS PI = 50
2403 22:18:00.255603 [0] AVG Duty = 5047%(X100)
2404 22:18:00.259120
2405 22:18:00.259225 ==DQ 1 ==
2406 22:18:00.262530 Final DQ duty delay cell = 0
2407 22:18:00.265572 [0] MAX Duty = 5125%(X100), DQS PI = 4
2408 22:18:00.269010 [0] MIN Duty = 4938%(X100), DQS PI = 14
2409 22:18:00.269093 [0] AVG Duty = 5031%(X100)
2410 22:18:00.272546
2411 22:18:00.275348 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2412 22:18:00.275431
2413 22:18:00.278876 CH0 DQ 1 Duty spec in!! Max-Min= 187%
2414 22:18:00.282032 [DutyScan_Calibration_Flow] ====Done====
2415 22:18:00.282115 ==
2416 22:18:00.285477 Dram Type= 6, Freq= 0, CH_1, rank 0
2417 22:18:00.288745 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2418 22:18:00.288829 ==
2419 22:18:00.291988 [Duty_Offset_Calibration]
2420 22:18:00.292094 B0:0 B1:-1 CA:3
2421 22:18:00.292160
2422 22:18:00.295345 [DutyScan_Calibration_Flow] k_type=0
2423 22:18:00.305945
2424 22:18:00.306027 ==CLK 0==
2425 22:18:00.308916 Final CLK duty delay cell = 0
2426 22:18:00.312376 [0] MAX Duty = 5156%(X100), DQS PI = 0
2427 22:18:00.315828 [0] MIN Duty = 5000%(X100), DQS PI = 54
2428 22:18:00.315929 [0] AVG Duty = 5078%(X100)
2429 22:18:00.318883
2430 22:18:00.322090 CH1 CLK Duty spec in!! Max-Min= 156%
2431 22:18:00.325456 [DutyScan_Calibration_Flow] ====Done====
2432 22:18:00.325539
2433 22:18:00.328617 [DutyScan_Calibration_Flow] k_type=1
2434 22:18:00.345179
2435 22:18:00.345267 ==DQS 0 ==
2436 22:18:00.348384 Final DQS duty delay cell = 0
2437 22:18:00.351676 [0] MAX Duty = 5187%(X100), DQS PI = 18
2438 22:18:00.354770 [0] MIN Duty = 4907%(X100), DQS PI = 38
2439 22:18:00.354871 [0] AVG Duty = 5047%(X100)
2440 22:18:00.358709
2441 22:18:00.358807 ==DQS 1 ==
2442 22:18:00.361521 Final DQS duty delay cell = 0
2443 22:18:00.365156 [0] MAX Duty = 5156%(X100), DQS PI = 8
2444 22:18:00.368308 [0] MIN Duty = 5031%(X100), DQS PI = 18
2445 22:18:00.371550 [0] AVG Duty = 5093%(X100)
2446 22:18:00.371621
2447 22:18:00.374924 CH1 DQS 0 Duty spec in!! Max-Min= 280%
2448 22:18:00.375015
2449 22:18:00.378499 CH1 DQS 1 Duty spec in!! Max-Min= 125%
2450 22:18:00.381610 [DutyScan_Calibration_Flow] ====Done====
2451 22:18:00.381710
2452 22:18:00.384594 [DutyScan_Calibration_Flow] k_type=3
2453 22:18:00.401619
2454 22:18:00.401703 ==DQM 0 ==
2455 22:18:00.404815 Final DQM duty delay cell = 0
2456 22:18:00.408315 [0] MAX Duty = 5031%(X100), DQS PI = 28
2457 22:18:00.411320 [0] MIN Duty = 4813%(X100), DQS PI = 38
2458 22:18:00.414643 [0] AVG Duty = 4922%(X100)
2459 22:18:00.414716
2460 22:18:00.414778 ==DQM 1 ==
2461 22:18:00.418370 Final DQM duty delay cell = 0
2462 22:18:00.421326 [0] MAX Duty = 4969%(X100), DQS PI = 32
2463 22:18:00.424488 [0] MIN Duty = 4844%(X100), DQS PI = 0
2464 22:18:00.424558 [0] AVG Duty = 4906%(X100)
2465 22:18:00.428023
2466 22:18:00.431258 CH1 DQM 0 Duty spec in!! Max-Min= 218%
2467 22:18:00.431341
2468 22:18:00.434637 CH1 DQM 1 Duty spec in!! Max-Min= 125%
2469 22:18:00.438393 [DutyScan_Calibration_Flow] ====Done====
2470 22:18:00.438501
2471 22:18:00.441274 [DutyScan_Calibration_Flow] k_type=2
2472 22:18:00.456999
2473 22:18:00.457086 ==DQ 0 ==
2474 22:18:00.460241 Final DQ duty delay cell = -4
2475 22:18:00.463917 [-4] MAX Duty = 5031%(X100), DQS PI = 28
2476 22:18:00.467337 [-4] MIN Duty = 4844%(X100), DQS PI = 36
2477 22:18:00.470521 [-4] AVG Duty = 4937%(X100)
2478 22:18:00.470604
2479 22:18:00.470669 ==DQ 1 ==
2480 22:18:00.473744 Final DQ duty delay cell = 0
2481 22:18:00.477127 [0] MAX Duty = 5031%(X100), DQS PI = 32
2482 22:18:00.480812 [0] MIN Duty = 4844%(X100), DQS PI = 0
2483 22:18:00.480925 [0] AVG Duty = 4937%(X100)
2484 22:18:00.484107
2485 22:18:00.486985 CH1 DQ 0 Duty spec in!! Max-Min= 187%
2486 22:18:00.487093
2487 22:18:00.490247 CH1 DQ 1 Duty spec in!! Max-Min= 187%
2488 22:18:00.493598 [DutyScan_Calibration_Flow] ====Done====
2489 22:18:00.497363 nWR fixed to 30
2490 22:18:00.497438 [ModeRegInit_LP4] CH0 RK0
2491 22:18:00.500606 [ModeRegInit_LP4] CH0 RK1
2492 22:18:00.503676 [ModeRegInit_LP4] CH1 RK0
2493 22:18:00.507086 [ModeRegInit_LP4] CH1 RK1
2494 22:18:00.507169 match AC timing 7
2495 22:18:00.513476 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2496 22:18:00.517081 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2497 22:18:00.520450 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2498 22:18:00.526741 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2499 22:18:00.530262 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2500 22:18:00.530346 ==
2501 22:18:00.533368 Dram Type= 6, Freq= 0, CH_0, rank 0
2502 22:18:00.536552 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2503 22:18:00.536635 ==
2504 22:18:00.543157 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2505 22:18:00.549989 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2506 22:18:00.557478 [CA 0] Center 39 (9~70) winsize 62
2507 22:18:00.561053 [CA 1] Center 39 (9~70) winsize 62
2508 22:18:00.564088 [CA 2] Center 35 (5~66) winsize 62
2509 22:18:00.567544 [CA 3] Center 35 (5~66) winsize 62
2510 22:18:00.570567 [CA 4] Center 33 (3~64) winsize 62
2511 22:18:00.573804 [CA 5] Center 33 (3~63) winsize 61
2512 22:18:00.573887
2513 22:18:00.577531 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2514 22:18:00.577615
2515 22:18:00.580560 [CATrainingPosCal] consider 1 rank data
2516 22:18:00.584012 u2DelayCellTimex100 = 270/100 ps
2517 22:18:00.587123 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2518 22:18:00.593900 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2519 22:18:00.597526 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2520 22:18:00.600825 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2521 22:18:00.603838 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2522 22:18:00.607144 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2523 22:18:00.607228
2524 22:18:00.610335 CA PerBit enable=1, Macro0, CA PI delay=33
2525 22:18:00.610418
2526 22:18:00.613565 [CBTSetCACLKResult] CA Dly = 33
2527 22:18:00.616943 CS Dly: 7 (0~38)
2528 22:18:00.617025 ==
2529 22:18:00.620316 Dram Type= 6, Freq= 0, CH_0, rank 1
2530 22:18:00.623361 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2531 22:18:00.623444 ==
2532 22:18:00.629953 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2533 22:18:00.633425 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2534 22:18:00.643211 [CA 0] Center 39 (9~70) winsize 62
2535 22:18:00.646692 [CA 1] Center 39 (9~70) winsize 62
2536 22:18:00.649663 [CA 2] Center 35 (5~66) winsize 62
2537 22:18:00.653461 [CA 3] Center 35 (5~66) winsize 62
2538 22:18:00.656292 [CA 4] Center 34 (4~65) winsize 62
2539 22:18:00.659955 [CA 5] Center 33 (3~64) winsize 62
2540 22:18:00.660060
2541 22:18:00.663138 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2542 22:18:00.663221
2543 22:18:00.666581 [CATrainingPosCal] consider 2 rank data
2544 22:18:00.669570 u2DelayCellTimex100 = 270/100 ps
2545 22:18:00.672895 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2546 22:18:00.679939 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2547 22:18:00.682926 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2548 22:18:00.686450 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2549 22:18:00.689909 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
2550 22:18:00.693294 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2551 22:18:00.693376
2552 22:18:00.696217 CA PerBit enable=1, Macro0, CA PI delay=33
2553 22:18:00.696304
2554 22:18:00.699689 [CBTSetCACLKResult] CA Dly = 33
2555 22:18:00.699772 CS Dly: 8 (0~41)
2556 22:18:00.699853
2557 22:18:00.706243 ----->DramcWriteLeveling(PI) begin...
2558 22:18:00.706325 ==
2559 22:18:00.709466 Dram Type= 6, Freq= 0, CH_0, rank 0
2560 22:18:00.712745 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2561 22:18:00.712824 ==
2562 22:18:00.716363 Write leveling (Byte 0): 33 => 33
2563 22:18:00.719711 Write leveling (Byte 1): 26 => 26
2564 22:18:00.723240 DramcWriteLeveling(PI) end<-----
2565 22:18:00.723326
2566 22:18:00.723391 ==
2567 22:18:00.726132 Dram Type= 6, Freq= 0, CH_0, rank 0
2568 22:18:00.729776 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2569 22:18:00.729860 ==
2570 22:18:00.733185 [Gating] SW mode calibration
2571 22:18:00.739422 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2572 22:18:00.746574 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2573 22:18:00.749501 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2574 22:18:00.752963 0 15 4 | B1->B0 | 2a2a 3434 | 1 1 | (1 1) (1 1)
2575 22:18:00.759424 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2576 22:18:00.762892 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2577 22:18:00.766084 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2578 22:18:00.772622 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2579 22:18:00.775716 0 15 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
2580 22:18:00.779143 0 15 28 | B1->B0 | 3434 2424 | 1 0 | (1 1) (1 0)
2581 22:18:00.785590 1 0 0 | B1->B0 | 3333 2323 | 0 0 | (0 0) (0 0)
2582 22:18:00.789141 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2583 22:18:00.792301 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2584 22:18:00.799290 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2585 22:18:00.802103 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2586 22:18:00.805748 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2587 22:18:00.812145 1 0 24 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
2588 22:18:00.815358 1 0 28 | B1->B0 | 2424 4646 | 0 0 | (0 0) (0 0)
2589 22:18:00.818697 1 1 0 | B1->B0 | 2525 4646 | 1 0 | (0 0) (0 0)
2590 22:18:00.822067 1 1 4 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
2591 22:18:00.828697 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2592 22:18:00.831977 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2593 22:18:00.835417 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2594 22:18:00.842101 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2595 22:18:00.845471 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2596 22:18:00.848620 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
2597 22:18:00.855090 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2598 22:18:00.858793 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2599 22:18:00.861855 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2600 22:18:00.868450 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2601 22:18:00.871556 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2602 22:18:00.874829 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2603 22:18:00.881589 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2604 22:18:00.884887 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2605 22:18:00.888207 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2606 22:18:00.894762 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2607 22:18:00.898172 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2608 22:18:00.901646 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2609 22:18:00.908095 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2610 22:18:00.911680 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2611 22:18:00.914617 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2612 22:18:00.921268 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2613 22:18:00.924321 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2614 22:18:00.927810 Total UI for P1: 0, mck2ui 16
2615 22:18:00.931086 best dqsien dly found for B0: ( 1, 3, 26)
2616 22:18:00.934351 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2617 22:18:00.937793 Total UI for P1: 0, mck2ui 16
2618 22:18:00.940963 best dqsien dly found for B1: ( 1, 3, 30)
2619 22:18:00.944610 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2620 22:18:00.947635 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2621 22:18:00.947713
2622 22:18:00.954505 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2623 22:18:00.957665 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2624 22:18:00.960978 [Gating] SW calibration Done
2625 22:18:00.961112 ==
2626 22:18:00.964651 Dram Type= 6, Freq= 0, CH_0, rank 0
2627 22:18:00.967718 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2628 22:18:00.967796 ==
2629 22:18:00.967858 RX Vref Scan: 0
2630 22:18:00.967918
2631 22:18:00.970984 RX Vref 0 -> 0, step: 1
2632 22:18:00.971067
2633 22:18:00.974236 RX Delay -40 -> 252, step: 8
2634 22:18:00.978136 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2635 22:18:00.981329 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2636 22:18:00.988158 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2637 22:18:00.990879 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2638 22:18:00.994314 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2639 22:18:00.997761 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2640 22:18:01.000824 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2641 22:18:01.007724 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2642 22:18:01.011128 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2643 22:18:01.014044 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2644 22:18:01.017334 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2645 22:18:01.020706 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2646 22:18:01.027314 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
2647 22:18:01.030810 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2648 22:18:01.033947 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2649 22:18:01.037215 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2650 22:18:01.037292 ==
2651 22:18:01.040931 Dram Type= 6, Freq= 0, CH_0, rank 0
2652 22:18:01.047374 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2653 22:18:01.047450 ==
2654 22:18:01.047514 DQS Delay:
2655 22:18:01.047614 DQS0 = 0, DQS1 = 0
2656 22:18:01.050427 DQM Delay:
2657 22:18:01.050501 DQM0 = 118, DQM1 = 107
2658 22:18:01.053908 DQ Delay:
2659 22:18:01.057370 DQ0 =115, DQ1 =115, DQ2 =119, DQ3 =115
2660 22:18:01.060449 DQ4 =119, DQ5 =111, DQ6 =123, DQ7 =127
2661 22:18:01.063756 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2662 22:18:01.067389 DQ12 =119, DQ13 =111, DQ14 =119, DQ15 =111
2663 22:18:01.067470
2664 22:18:01.067535
2665 22:18:01.067594 ==
2666 22:18:01.070783 Dram Type= 6, Freq= 0, CH_0, rank 0
2667 22:18:01.073924 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2668 22:18:01.074007 ==
2669 22:18:01.074072
2670 22:18:01.077400
2671 22:18:01.077482 TX Vref Scan disable
2672 22:18:01.080487 == TX Byte 0 ==
2673 22:18:01.084183 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2674 22:18:01.086908 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2675 22:18:01.090719 == TX Byte 1 ==
2676 22:18:01.093474 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2677 22:18:01.097193 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2678 22:18:01.097276 ==
2679 22:18:01.100323 Dram Type= 6, Freq= 0, CH_0, rank 0
2680 22:18:01.106878 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2681 22:18:01.106962 ==
2682 22:18:01.118238 TX Vref=22, minBit 4, minWin=25, winSum=413
2683 22:18:01.121686 TX Vref=24, minBit 10, minWin=25, winSum=421
2684 22:18:01.125487 TX Vref=26, minBit 4, minWin=25, winSum=422
2685 22:18:01.128259 TX Vref=28, minBit 13, minWin=25, winSum=428
2686 22:18:01.131771 TX Vref=30, minBit 5, minWin=26, winSum=429
2687 22:18:01.138115 TX Vref=32, minBit 4, minWin=26, winSum=429
2688 22:18:01.141542 [TxChooseVref] Worse bit 5, Min win 26, Win sum 429, Final Vref 30
2689 22:18:01.141626
2690 22:18:01.145023 Final TX Range 1 Vref 30
2691 22:18:01.145105
2692 22:18:01.145192 ==
2693 22:18:01.147974 Dram Type= 6, Freq= 0, CH_0, rank 0
2694 22:18:01.151503 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2695 22:18:01.151607 ==
2696 22:18:01.155177
2697 22:18:01.155275
2698 22:18:01.155369 TX Vref Scan disable
2699 22:18:01.158227 == TX Byte 0 ==
2700 22:18:01.161163 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2701 22:18:01.168010 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2702 22:18:01.168149 == TX Byte 1 ==
2703 22:18:01.171208 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2704 22:18:01.177780 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2705 22:18:01.177880
2706 22:18:01.177971 [DATLAT]
2707 22:18:01.178062 Freq=1200, CH0 RK0
2708 22:18:01.178149
2709 22:18:01.181222 DATLAT Default: 0xd
2710 22:18:01.181308 0, 0xFFFF, sum = 0
2711 22:18:01.184782 1, 0xFFFF, sum = 0
2712 22:18:01.188214 2, 0xFFFF, sum = 0
2713 22:18:01.188301 3, 0xFFFF, sum = 0
2714 22:18:01.191098 4, 0xFFFF, sum = 0
2715 22:18:01.191208 5, 0xFFFF, sum = 0
2716 22:18:01.194928 6, 0xFFFF, sum = 0
2717 22:18:01.195034 7, 0xFFFF, sum = 0
2718 22:18:01.198203 8, 0xFFFF, sum = 0
2719 22:18:01.198328 9, 0xFFFF, sum = 0
2720 22:18:01.201361 10, 0xFFFF, sum = 0
2721 22:18:01.201479 11, 0xFFFF, sum = 0
2722 22:18:01.204793 12, 0x0, sum = 1
2723 22:18:01.204904 13, 0x0, sum = 2
2724 22:18:01.208538 14, 0x0, sum = 3
2725 22:18:01.208637 15, 0x0, sum = 4
2726 22:18:01.208709 best_step = 13
2727 22:18:01.211436
2728 22:18:01.211546 ==
2729 22:18:01.214612 Dram Type= 6, Freq= 0, CH_0, rank 0
2730 22:18:01.218272 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2731 22:18:01.218382 ==
2732 22:18:01.218481 RX Vref Scan: 1
2733 22:18:01.218586
2734 22:18:01.221609 Set Vref Range= 32 -> 127
2735 22:18:01.221692
2736 22:18:01.224524 RX Vref 32 -> 127, step: 1
2737 22:18:01.224610
2738 22:18:01.228022 RX Delay -21 -> 252, step: 4
2739 22:18:01.228126
2740 22:18:01.230969 Set Vref, RX VrefLevel [Byte0]: 32
2741 22:18:01.234895 [Byte1]: 32
2742 22:18:01.234981
2743 22:18:01.238075 Set Vref, RX VrefLevel [Byte0]: 33
2744 22:18:01.241209 [Byte1]: 33
2745 22:18:01.244448
2746 22:18:01.244560 Set Vref, RX VrefLevel [Byte0]: 34
2747 22:18:01.248329 [Byte1]: 34
2748 22:18:01.252371
2749 22:18:01.252486 Set Vref, RX VrefLevel [Byte0]: 35
2750 22:18:01.255950 [Byte1]: 35
2751 22:18:01.260450
2752 22:18:01.260534 Set Vref, RX VrefLevel [Byte0]: 36
2753 22:18:01.263654 [Byte1]: 36
2754 22:18:01.268854
2755 22:18:01.268955 Set Vref, RX VrefLevel [Byte0]: 37
2756 22:18:01.271989 [Byte1]: 37
2757 22:18:01.276369
2758 22:18:01.276457 Set Vref, RX VrefLevel [Byte0]: 38
2759 22:18:01.279679 [Byte1]: 38
2760 22:18:01.284102
2761 22:18:01.284179 Set Vref, RX VrefLevel [Byte0]: 39
2762 22:18:01.287599 [Byte1]: 39
2763 22:18:01.291984
2764 22:18:01.292125 Set Vref, RX VrefLevel [Byte0]: 40
2765 22:18:01.295596 [Byte1]: 40
2766 22:18:01.299924
2767 22:18:01.300008 Set Vref, RX VrefLevel [Byte0]: 41
2768 22:18:01.303406 [Byte1]: 41
2769 22:18:01.308287
2770 22:18:01.308368 Set Vref, RX VrefLevel [Byte0]: 42
2771 22:18:01.311506 [Byte1]: 42
2772 22:18:01.316247
2773 22:18:01.316329 Set Vref, RX VrefLevel [Byte0]: 43
2774 22:18:01.319619 [Byte1]: 43
2775 22:18:01.323975
2776 22:18:01.324324 Set Vref, RX VrefLevel [Byte0]: 44
2777 22:18:01.327096 [Byte1]: 44
2778 22:18:01.332170
2779 22:18:01.332248 Set Vref, RX VrefLevel [Byte0]: 45
2780 22:18:01.335298 [Byte1]: 45
2781 22:18:01.339835
2782 22:18:01.339911 Set Vref, RX VrefLevel [Byte0]: 46
2783 22:18:01.342927 [Byte1]: 46
2784 22:18:01.347873
2785 22:18:01.347984 Set Vref, RX VrefLevel [Byte0]: 47
2786 22:18:01.351368 [Byte1]: 47
2787 22:18:01.355768
2788 22:18:01.355874 Set Vref, RX VrefLevel [Byte0]: 48
2789 22:18:01.359145 [Byte1]: 48
2790 22:18:01.363295
2791 22:18:01.363406 Set Vref, RX VrefLevel [Byte0]: 49
2792 22:18:01.367291 [Byte1]: 49
2793 22:18:01.371285
2794 22:18:01.371395 Set Vref, RX VrefLevel [Byte0]: 50
2795 22:18:01.374889 [Byte1]: 50
2796 22:18:01.379341
2797 22:18:01.379452 Set Vref, RX VrefLevel [Byte0]: 51
2798 22:18:01.382705 [Byte1]: 51
2799 22:18:01.387302
2800 22:18:01.387406 Set Vref, RX VrefLevel [Byte0]: 52
2801 22:18:01.390577 [Byte1]: 52
2802 22:18:01.395529
2803 22:18:01.395621 Set Vref, RX VrefLevel [Byte0]: 53
2804 22:18:01.398636 [Byte1]: 53
2805 22:18:01.403050
2806 22:18:01.403165 Set Vref, RX VrefLevel [Byte0]: 54
2807 22:18:01.406608 [Byte1]: 54
2808 22:18:01.411037
2809 22:18:01.411141 Set Vref, RX VrefLevel [Byte0]: 55
2810 22:18:01.414322 [Byte1]: 55
2811 22:18:01.418998
2812 22:18:01.419106 Set Vref, RX VrefLevel [Byte0]: 56
2813 22:18:01.422371 [Byte1]: 56
2814 22:18:01.427011
2815 22:18:01.427095 Set Vref, RX VrefLevel [Byte0]: 57
2816 22:18:01.430022 [Byte1]: 57
2817 22:18:01.435069
2818 22:18:01.435179 Set Vref, RX VrefLevel [Byte0]: 58
2819 22:18:01.437959 [Byte1]: 58
2820 22:18:01.443033
2821 22:18:01.443143 Set Vref, RX VrefLevel [Byte0]: 59
2822 22:18:01.445921 [Byte1]: 59
2823 22:18:01.450448
2824 22:18:01.450563 Set Vref, RX VrefLevel [Byte0]: 60
2825 22:18:01.453818 [Byte1]: 60
2826 22:18:01.458779
2827 22:18:01.458888 Set Vref, RX VrefLevel [Byte0]: 61
2828 22:18:01.461749 [Byte1]: 61
2829 22:18:01.466929
2830 22:18:01.467041 Set Vref, RX VrefLevel [Byte0]: 62
2831 22:18:01.469797 [Byte1]: 62
2832 22:18:01.474255
2833 22:18:01.474333 Set Vref, RX VrefLevel [Byte0]: 63
2834 22:18:01.477955 [Byte1]: 63
2835 22:18:01.482180
2836 22:18:01.482288 Set Vref, RX VrefLevel [Byte0]: 64
2837 22:18:01.485507 [Byte1]: 64
2838 22:18:01.490515
2839 22:18:01.490594 Set Vref, RX VrefLevel [Byte0]: 65
2840 22:18:01.493657 [Byte1]: 65
2841 22:18:01.498838
2842 22:18:01.498954 Set Vref, RX VrefLevel [Byte0]: 66
2843 22:18:01.501539 [Byte1]: 66
2844 22:18:01.506310
2845 22:18:01.506393 Set Vref, RX VrefLevel [Byte0]: 67
2846 22:18:01.509472 [Byte1]: 67
2847 22:18:01.513941
2848 22:18:01.514026 Set Vref, RX VrefLevel [Byte0]: 68
2849 22:18:01.517724 [Byte1]: 68
2850 22:18:01.521819
2851 22:18:01.521895 Final RX Vref Byte 0 = 51 to rank0
2852 22:18:01.525236 Final RX Vref Byte 1 = 50 to rank0
2853 22:18:01.528734 Final RX Vref Byte 0 = 51 to rank1
2854 22:18:01.532179 Final RX Vref Byte 1 = 50 to rank1==
2855 22:18:01.535166 Dram Type= 6, Freq= 0, CH_0, rank 0
2856 22:18:01.541765 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2857 22:18:01.541852 ==
2858 22:18:01.541918 DQS Delay:
2859 22:18:01.541996 DQS0 = 0, DQS1 = 0
2860 22:18:01.545436 DQM Delay:
2861 22:18:01.545519 DQM0 = 117, DQM1 = 104
2862 22:18:01.548729 DQ Delay:
2863 22:18:01.552117 DQ0 =118, DQ1 =116, DQ2 =114, DQ3 =114
2864 22:18:01.555409 DQ4 =118, DQ5 =110, DQ6 =124, DQ7 =122
2865 22:18:01.558683 DQ8 =94, DQ9 =88, DQ10 =106, DQ11 =100
2866 22:18:01.561933 DQ12 =112, DQ13 =110, DQ14 =116, DQ15 =112
2867 22:18:01.562017
2868 22:18:01.562084
2869 22:18:01.568671 [DQSOSCAuto] RK0, (LSB)MR18= 0x500, (MSB)MR19= 0x404, tDQSOscB0 = 410 ps tDQSOscB1 = 408 ps
2870 22:18:01.572053 CH0 RK0: MR19=404, MR18=500
2871 22:18:01.578662 CH0_RK0: MR19=0x404, MR18=0x500, DQSOSC=408, MR23=63, INC=39, DEC=26
2872 22:18:01.578746
2873 22:18:01.582130 ----->DramcWriteLeveling(PI) begin...
2874 22:18:01.582240 ==
2875 22:18:01.585460 Dram Type= 6, Freq= 0, CH_0, rank 1
2876 22:18:01.588559 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2877 22:18:01.588641 ==
2878 22:18:01.591759 Write leveling (Byte 0): 31 => 31
2879 22:18:01.595141 Write leveling (Byte 1): 24 => 24
2880 22:18:01.598929 DramcWriteLeveling(PI) end<-----
2881 22:18:01.599015
2882 22:18:01.599081 ==
2883 22:18:01.601982 Dram Type= 6, Freq= 0, CH_0, rank 1
2884 22:18:01.608435 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2885 22:18:01.608519 ==
2886 22:18:01.608583 [Gating] SW mode calibration
2887 22:18:01.618270 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2888 22:18:01.621417 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2889 22:18:01.627932 0 15 0 | B1->B0 | 2525 3434 | 1 1 | (0 0) (1 1)
2890 22:18:01.631318 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2891 22:18:01.634659 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2892 22:18:01.641535 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2893 22:18:01.644679 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2894 22:18:01.648251 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2895 22:18:01.651199 0 15 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
2896 22:18:01.657746 0 15 28 | B1->B0 | 3434 2424 | 1 0 | (1 0) (0 0)
2897 22:18:01.661522 1 0 0 | B1->B0 | 2e2e 2323 | 0 0 | (0 1) (0 0)
2898 22:18:01.664710 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2899 22:18:01.671518 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2900 22:18:01.674624 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2901 22:18:01.677629 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2902 22:18:01.684815 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2903 22:18:01.687839 1 0 24 | B1->B0 | 2323 3636 | 0 0 | (0 0) (0 0)
2904 22:18:01.691102 1 0 28 | B1->B0 | 2a2a 4444 | 0 0 | (0 0) (0 0)
2905 22:18:01.698000 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2906 22:18:01.701109 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2907 22:18:01.704298 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2908 22:18:01.711319 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2909 22:18:01.714441 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2910 22:18:01.717755 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2911 22:18:01.724782 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2912 22:18:01.728047 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2913 22:18:01.731171 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2914 22:18:01.737958 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2915 22:18:01.741251 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2916 22:18:01.744453 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2917 22:18:01.751225 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2918 22:18:01.754657 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2919 22:18:01.758057 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2920 22:18:01.764245 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2921 22:18:01.768188 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2922 22:18:01.771326 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2923 22:18:01.774260 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2924 22:18:01.781202 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2925 22:18:01.784353 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2926 22:18:01.787493 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2927 22:18:01.794499 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2928 22:18:01.797490 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2929 22:18:01.800746 Total UI for P1: 0, mck2ui 16
2930 22:18:01.804739 best dqsien dly found for B0: ( 1, 3, 24)
2931 22:18:01.807264 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2932 22:18:01.811082 Total UI for P1: 0, mck2ui 16
2933 22:18:01.814262 best dqsien dly found for B1: ( 1, 3, 28)
2934 22:18:01.817607 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
2935 22:18:01.820691 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2936 22:18:01.824176
2937 22:18:01.827187 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
2938 22:18:01.830456 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2939 22:18:01.834092 [Gating] SW calibration Done
2940 22:18:01.834175 ==
2941 22:18:01.837660 Dram Type= 6, Freq= 0, CH_0, rank 1
2942 22:18:01.840602 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2943 22:18:01.840686 ==
2944 22:18:01.840751 RX Vref Scan: 0
2945 22:18:01.843998
2946 22:18:01.844094 RX Vref 0 -> 0, step: 1
2947 22:18:01.844161
2948 22:18:01.847081 RX Delay -40 -> 252, step: 8
2949 22:18:01.851074 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2950 22:18:01.854224 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2951 22:18:01.860040 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2952 22:18:01.863684 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2953 22:18:01.867288 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2954 22:18:01.870358 iDelay=200, Bit 5, Center 107 (40 ~ 175) 136
2955 22:18:01.873791 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2956 22:18:01.880128 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
2957 22:18:01.883331 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2958 22:18:01.886831 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2959 22:18:01.890181 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2960 22:18:01.893309 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2961 22:18:01.900068 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2962 22:18:01.903186 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2963 22:18:01.906716 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2964 22:18:01.910416 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2965 22:18:01.910499 ==
2966 22:18:01.913240 Dram Type= 6, Freq= 0, CH_0, rank 1
2967 22:18:01.919564 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2968 22:18:01.919647 ==
2969 22:18:01.919713 DQS Delay:
2970 22:18:01.922941 DQS0 = 0, DQS1 = 0
2971 22:18:01.923022 DQM Delay:
2972 22:18:01.926310 DQM0 = 115, DQM1 = 107
2973 22:18:01.926393 DQ Delay:
2974 22:18:01.930062 DQ0 =111, DQ1 =119, DQ2 =111, DQ3 =111
2975 22:18:01.932972 DQ4 =119, DQ5 =107, DQ6 =127, DQ7 =119
2976 22:18:01.936713 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2977 22:18:01.939786 DQ12 =115, DQ13 =111, DQ14 =119, DQ15 =115
2978 22:18:01.939869
2979 22:18:01.939934
2980 22:18:01.939994 ==
2981 22:18:01.943002 Dram Type= 6, Freq= 0, CH_0, rank 1
2982 22:18:01.949636 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2983 22:18:01.949720 ==
2984 22:18:01.949786
2985 22:18:01.949846
2986 22:18:01.949903 TX Vref Scan disable
2987 22:18:01.953002 == TX Byte 0 ==
2988 22:18:01.955980 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2989 22:18:01.962824 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2990 22:18:01.962907 == TX Byte 1 ==
2991 22:18:01.966246 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
2992 22:18:01.972770 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
2993 22:18:01.972883 ==
2994 22:18:01.976215 Dram Type= 6, Freq= 0, CH_0, rank 1
2995 22:18:01.979211 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2996 22:18:01.979320 ==
2997 22:18:01.991259 TX Vref=22, minBit 1, minWin=25, winSum=412
2998 22:18:01.994919 TX Vref=24, minBit 5, minWin=25, winSum=421
2999 22:18:01.998146 TX Vref=26, minBit 0, minWin=26, winSum=420
3000 22:18:02.001256 TX Vref=28, minBit 0, minWin=26, winSum=425
3001 22:18:02.004849 TX Vref=30, minBit 4, minWin=26, winSum=429
3002 22:18:02.008396 TX Vref=32, minBit 1, minWin=26, winSum=423
3003 22:18:02.014494 [TxChooseVref] Worse bit 4, Min win 26, Win sum 429, Final Vref 30
3004 22:18:02.014578
3005 22:18:02.017784 Final TX Range 1 Vref 30
3006 22:18:02.017868
3007 22:18:02.017933 ==
3008 22:18:02.021223 Dram Type= 6, Freq= 0, CH_0, rank 1
3009 22:18:02.024947 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3010 22:18:02.025030 ==
3011 22:18:02.025096
3012 22:18:02.028178
3013 22:18:02.028260 TX Vref Scan disable
3014 22:18:02.031402 == TX Byte 0 ==
3015 22:18:02.034752 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
3016 22:18:02.038396 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
3017 22:18:02.041120 == TX Byte 1 ==
3018 22:18:02.044424 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3019 22:18:02.048055 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3020 22:18:02.048152
3021 22:18:02.051543 [DATLAT]
3022 22:18:02.051625 Freq=1200, CH0 RK1
3023 22:18:02.051691
3024 22:18:02.054649 DATLAT Default: 0xd
3025 22:18:02.054731 0, 0xFFFF, sum = 0
3026 22:18:02.057978 1, 0xFFFF, sum = 0
3027 22:18:02.058062 2, 0xFFFF, sum = 0
3028 22:18:02.061314 3, 0xFFFF, sum = 0
3029 22:18:02.061397 4, 0xFFFF, sum = 0
3030 22:18:02.064520 5, 0xFFFF, sum = 0
3031 22:18:02.064604 6, 0xFFFF, sum = 0
3032 22:18:02.068166 7, 0xFFFF, sum = 0
3033 22:18:02.071461 8, 0xFFFF, sum = 0
3034 22:18:02.071550 9, 0xFFFF, sum = 0
3035 22:18:02.074362 10, 0xFFFF, sum = 0
3036 22:18:02.074446 11, 0xFFFF, sum = 0
3037 22:18:02.077821 12, 0x0, sum = 1
3038 22:18:02.077905 13, 0x0, sum = 2
3039 22:18:02.081028 14, 0x0, sum = 3
3040 22:18:02.081112 15, 0x0, sum = 4
3041 22:18:02.081180 best_step = 13
3042 22:18:02.081241
3043 22:18:02.084954 ==
3044 22:18:02.087822 Dram Type= 6, Freq= 0, CH_0, rank 1
3045 22:18:02.091325 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3046 22:18:02.091403 ==
3047 22:18:02.091472 RX Vref Scan: 0
3048 22:18:02.091535
3049 22:18:02.094816 RX Vref 0 -> 0, step: 1
3050 22:18:02.094891
3051 22:18:02.097440 RX Delay -21 -> 252, step: 4
3052 22:18:02.100697 iDelay=195, Bit 0, Center 114 (51 ~ 178) 128
3053 22:18:02.107517 iDelay=195, Bit 1, Center 116 (47 ~ 186) 140
3054 22:18:02.111006 iDelay=195, Bit 2, Center 110 (43 ~ 178) 136
3055 22:18:02.114489 iDelay=195, Bit 3, Center 112 (47 ~ 178) 132
3056 22:18:02.117375 iDelay=195, Bit 4, Center 118 (51 ~ 186) 136
3057 22:18:02.120831 iDelay=195, Bit 5, Center 108 (43 ~ 174) 132
3058 22:18:02.127248 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3059 22:18:02.130508 iDelay=195, Bit 7, Center 120 (55 ~ 186) 132
3060 22:18:02.134494 iDelay=195, Bit 8, Center 96 (27 ~ 166) 140
3061 22:18:02.137630 iDelay=195, Bit 9, Center 92 (23 ~ 162) 140
3062 22:18:02.140880 iDelay=195, Bit 10, Center 108 (39 ~ 178) 140
3063 22:18:02.147207 iDelay=195, Bit 11, Center 98 (31 ~ 166) 136
3064 22:18:02.150645 iDelay=195, Bit 12, Center 112 (47 ~ 178) 132
3065 22:18:02.154227 iDelay=195, Bit 13, Center 110 (43 ~ 178) 136
3066 22:18:02.157424 iDelay=195, Bit 14, Center 118 (51 ~ 186) 136
3067 22:18:02.160750 iDelay=195, Bit 15, Center 112 (47 ~ 178) 132
3068 22:18:02.164034 ==
3069 22:18:02.164136 Dram Type= 6, Freq= 0, CH_0, rank 1
3070 22:18:02.171098 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3071 22:18:02.171182 ==
3072 22:18:02.171249 DQS Delay:
3073 22:18:02.173786 DQS0 = 0, DQS1 = 0
3074 22:18:02.173869 DQM Delay:
3075 22:18:02.177503 DQM0 = 115, DQM1 = 105
3076 22:18:02.177587 DQ Delay:
3077 22:18:02.181093 DQ0 =114, DQ1 =116, DQ2 =110, DQ3 =112
3078 22:18:02.184025 DQ4 =118, DQ5 =108, DQ6 =126, DQ7 =120
3079 22:18:02.187370 DQ8 =96, DQ9 =92, DQ10 =108, DQ11 =98
3080 22:18:02.190869 DQ12 =112, DQ13 =110, DQ14 =118, DQ15 =112
3081 22:18:02.190954
3082 22:18:02.191047
3083 22:18:02.200528 [DQSOSCAuto] RK1, (LSB)MR18= 0xfdfa, (MSB)MR19= 0x303, tDQSOscB0 = 412 ps tDQSOscB1 = 411 ps
3084 22:18:02.200614 CH0 RK1: MR19=303, MR18=FDFA
3085 22:18:02.207188 CH0_RK1: MR19=0x303, MR18=0xFDFA, DQSOSC=411, MR23=63, INC=38, DEC=25
3086 22:18:02.210257 [RxdqsGatingPostProcess] freq 1200
3087 22:18:02.217163 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3088 22:18:02.220288 best DQS0 dly(2T, 0.5T) = (0, 11)
3089 22:18:02.223298 best DQS1 dly(2T, 0.5T) = (0, 11)
3090 22:18:02.226859 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3091 22:18:02.230222 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3092 22:18:02.233369 best DQS0 dly(2T, 0.5T) = (0, 11)
3093 22:18:02.236649 best DQS1 dly(2T, 0.5T) = (0, 11)
3094 22:18:02.240010 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3095 22:18:02.243848 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3096 22:18:02.243962 Pre-setting of DQS Precalculation
3097 22:18:02.250234 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3098 22:18:02.250318 ==
3099 22:18:02.253215 Dram Type= 6, Freq= 0, CH_1, rank 0
3100 22:18:02.256967 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3101 22:18:02.257051 ==
3102 22:18:02.263466 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3103 22:18:02.269830 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3104 22:18:02.277725 [CA 0] Center 38 (8~68) winsize 61
3105 22:18:02.280852 [CA 1] Center 37 (7~68) winsize 62
3106 22:18:02.284407 [CA 2] Center 35 (5~65) winsize 61
3107 22:18:02.287504 [CA 3] Center 34 (4~64) winsize 61
3108 22:18:02.290960 [CA 4] Center 34 (4~65) winsize 62
3109 22:18:02.293976 [CA 5] Center 33 (3~64) winsize 62
3110 22:18:02.294060
3111 22:18:02.297546 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3112 22:18:02.297631
3113 22:18:02.300782 [CATrainingPosCal] consider 1 rank data
3114 22:18:02.303768 u2DelayCellTimex100 = 270/100 ps
3115 22:18:02.307262 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3116 22:18:02.313944 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3117 22:18:02.317551 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3118 22:18:02.320488 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3119 22:18:02.323918 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
3120 22:18:02.327155 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3121 22:18:02.327273
3122 22:18:02.330819 CA PerBit enable=1, Macro0, CA PI delay=33
3123 22:18:02.330903
3124 22:18:02.333822 [CBTSetCACLKResult] CA Dly = 33
3125 22:18:02.333906 CS Dly: 5 (0~36)
3126 22:18:02.337288 ==
3127 22:18:02.337372 Dram Type= 6, Freq= 0, CH_1, rank 1
3128 22:18:02.344147 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3129 22:18:02.344237 ==
3130 22:18:02.347558 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3131 22:18:02.353826 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3132 22:18:02.363262 [CA 0] Center 37 (7~68) winsize 62
3133 22:18:02.366451 [CA 1] Center 38 (8~68) winsize 61
3134 22:18:02.369592 [CA 2] Center 35 (5~65) winsize 61
3135 22:18:02.373291 [CA 3] Center 33 (3~64) winsize 62
3136 22:18:02.376583 [CA 4] Center 34 (4~64) winsize 61
3137 22:18:02.379669 [CA 5] Center 33 (3~63) winsize 61
3138 22:18:02.379770
3139 22:18:02.383002 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3140 22:18:02.383074
3141 22:18:02.386275 [CATrainingPosCal] consider 2 rank data
3142 22:18:02.389803 u2DelayCellTimex100 = 270/100 ps
3143 22:18:02.393043 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3144 22:18:02.396217 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3145 22:18:02.403210 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3146 22:18:02.406270 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3147 22:18:02.409703 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3148 22:18:02.412697 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3149 22:18:02.412772
3150 22:18:02.415961 CA PerBit enable=1, Macro0, CA PI delay=33
3151 22:18:02.416107
3152 22:18:02.419186 [CBTSetCACLKResult] CA Dly = 33
3153 22:18:02.419265 CS Dly: 6 (0~39)
3154 22:18:02.422550
3155 22:18:02.426094 ----->DramcWriteLeveling(PI) begin...
3156 22:18:02.426176 ==
3157 22:18:02.429369 Dram Type= 6, Freq= 0, CH_1, rank 0
3158 22:18:02.432647 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3159 22:18:02.432730 ==
3160 22:18:02.435931 Write leveling (Byte 0): 25 => 25
3161 22:18:02.439328 Write leveling (Byte 1): 26 => 26
3162 22:18:02.442678 DramcWriteLeveling(PI) end<-----
3163 22:18:02.442756
3164 22:18:02.442827 ==
3165 22:18:02.445930 Dram Type= 6, Freq= 0, CH_1, rank 0
3166 22:18:02.449205 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3167 22:18:02.449284 ==
3168 22:18:02.452423 [Gating] SW mode calibration
3169 22:18:02.459349 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3170 22:18:02.465906 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3171 22:18:02.469003 0 15 0 | B1->B0 | 2d2d 3434 | 0 0 | (0 0) (0 0)
3172 22:18:02.472182 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3173 22:18:02.479369 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3174 22:18:02.482402 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3175 22:18:02.485513 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3176 22:18:02.492574 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3177 22:18:02.495623 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3178 22:18:02.498771 0 15 28 | B1->B0 | 2828 2323 | 0 0 | (1 0) (1 0)
3179 22:18:02.505243 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3180 22:18:02.509081 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3181 22:18:02.512124 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3182 22:18:02.519070 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3183 22:18:02.522540 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3184 22:18:02.525684 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3185 22:18:02.531941 1 0 24 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
3186 22:18:02.535478 1 0 28 | B1->B0 | 3d3d 4545 | 0 0 | (0 0) (0 0)
3187 22:18:02.538352 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3188 22:18:02.545206 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3189 22:18:02.548278 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3190 22:18:02.551532 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3191 22:18:02.558331 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3192 22:18:02.561616 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3193 22:18:02.564976 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3194 22:18:02.571749 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3195 22:18:02.574978 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3196 22:18:02.578273 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3197 22:18:02.581491 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3198 22:18:02.588542 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3199 22:18:02.591797 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3200 22:18:02.594904 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3201 22:18:02.601761 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3202 22:18:02.604917 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3203 22:18:02.608186 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3204 22:18:02.614565 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3205 22:18:02.618061 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3206 22:18:02.621180 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3207 22:18:02.627820 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3208 22:18:02.631283 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3209 22:18:02.634771 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3210 22:18:02.641387 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3211 22:18:02.644345 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3212 22:18:02.647868 Total UI for P1: 0, mck2ui 16
3213 22:18:02.651183 best dqsien dly found for B0: ( 1, 3, 26)
3214 22:18:02.654330 Total UI for P1: 0, mck2ui 16
3215 22:18:02.657769 best dqsien dly found for B1: ( 1, 3, 26)
3216 22:18:02.661505 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3217 22:18:02.664662 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3218 22:18:02.664746
3219 22:18:02.667904 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3220 22:18:02.670981 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3221 22:18:02.674188 [Gating] SW calibration Done
3222 22:18:02.674272 ==
3223 22:18:02.678051 Dram Type= 6, Freq= 0, CH_1, rank 0
3224 22:18:02.684499 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3225 22:18:02.684588 ==
3226 22:18:02.684655 RX Vref Scan: 0
3227 22:18:02.684743
3228 22:18:02.687640 RX Vref 0 -> 0, step: 1
3229 22:18:02.687728
3230 22:18:02.690755 RX Delay -40 -> 252, step: 8
3231 22:18:02.694163 iDelay=200, Bit 0, Center 123 (48 ~ 199) 152
3232 22:18:02.699108 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3233 22:18:02.700761 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3234 22:18:02.704066 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3235 22:18:02.710466 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3236 22:18:02.714266 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3237 22:18:02.717317 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3238 22:18:02.721341 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3239 22:18:02.724268 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3240 22:18:02.730447 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
3241 22:18:02.734291 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3242 22:18:02.737246 iDelay=200, Bit 11, Center 111 (48 ~ 175) 128
3243 22:18:02.740429 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3244 22:18:02.747522 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
3245 22:18:02.750279 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3246 22:18:02.753765 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3247 22:18:02.753848 ==
3248 22:18:02.757409 Dram Type= 6, Freq= 0, CH_1, rank 0
3249 22:18:02.760588 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3250 22:18:02.760671 ==
3251 22:18:02.763709 DQS Delay:
3252 22:18:02.763790 DQS0 = 0, DQS1 = 0
3253 22:18:02.766970 DQM Delay:
3254 22:18:02.767052 DQM0 = 117, DQM1 = 114
3255 22:18:02.767117 DQ Delay:
3256 22:18:02.770593 DQ0 =123, DQ1 =111, DQ2 =107, DQ3 =119
3257 22:18:02.777015 DQ4 =111, DQ5 =127, DQ6 =127, DQ7 =115
3258 22:18:02.780717 DQ8 =103, DQ9 =103, DQ10 =115, DQ11 =111
3259 22:18:02.783674 DQ12 =123, DQ13 =123, DQ14 =119, DQ15 =119
3260 22:18:02.783756
3261 22:18:02.783821
3262 22:18:02.783882 ==
3263 22:18:02.787504 Dram Type= 6, Freq= 0, CH_1, rank 0
3264 22:18:02.790400 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3265 22:18:02.790483 ==
3266 22:18:02.790548
3267 22:18:02.790606
3268 22:18:02.793698 TX Vref Scan disable
3269 22:18:02.797180 == TX Byte 0 ==
3270 22:18:02.800624 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3271 22:18:02.803645 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3272 22:18:02.807202 == TX Byte 1 ==
3273 22:18:02.810677 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3274 22:18:02.813663 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3275 22:18:02.813747 ==
3276 22:18:02.816986 Dram Type= 6, Freq= 0, CH_1, rank 0
3277 22:18:02.819882 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3278 22:18:02.823126 ==
3279 22:18:02.833163 TX Vref=22, minBit 9, minWin=23, winSum=405
3280 22:18:02.836423 TX Vref=24, minBit 9, minWin=23, winSum=414
3281 22:18:02.839708 TX Vref=26, minBit 9, minWin=25, winSum=421
3282 22:18:02.843358 TX Vref=28, minBit 9, minWin=25, winSum=422
3283 22:18:02.846650 TX Vref=30, minBit 11, minWin=25, winSum=424
3284 22:18:02.853016 TX Vref=32, minBit 11, minWin=25, winSum=422
3285 22:18:02.856572 [TxChooseVref] Worse bit 11, Min win 25, Win sum 424, Final Vref 30
3286 22:18:02.856657
3287 22:18:02.859787 Final TX Range 1 Vref 30
3288 22:18:02.859887
3289 22:18:02.859988 ==
3290 22:18:02.862897 Dram Type= 6, Freq= 0, CH_1, rank 0
3291 22:18:02.866406 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3292 22:18:02.869658 ==
3293 22:18:02.869730
3294 22:18:02.869792
3295 22:18:02.869851 TX Vref Scan disable
3296 22:18:02.872940 == TX Byte 0 ==
3297 22:18:02.876374 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3298 22:18:02.883381 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3299 22:18:02.883457 == TX Byte 1 ==
3300 22:18:02.886322 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3301 22:18:02.893200 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3302 22:18:02.893273
3303 22:18:02.893335 [DATLAT]
3304 22:18:02.893394 Freq=1200, CH1 RK0
3305 22:18:02.893453
3306 22:18:02.896047 DATLAT Default: 0xd
3307 22:18:02.896129 0, 0xFFFF, sum = 0
3308 22:18:02.900020 1, 0xFFFF, sum = 0
3309 22:18:02.903011 2, 0xFFFF, sum = 0
3310 22:18:02.903106 3, 0xFFFF, sum = 0
3311 22:18:02.906382 4, 0xFFFF, sum = 0
3312 22:18:02.906498 5, 0xFFFF, sum = 0
3313 22:18:02.909333 6, 0xFFFF, sum = 0
3314 22:18:02.909410 7, 0xFFFF, sum = 0
3315 22:18:02.912898 8, 0xFFFF, sum = 0
3316 22:18:02.912971 9, 0xFFFF, sum = 0
3317 22:18:02.916480 10, 0xFFFF, sum = 0
3318 22:18:02.916554 11, 0xFFFF, sum = 0
3319 22:18:02.919612 12, 0x0, sum = 1
3320 22:18:02.919708 13, 0x0, sum = 2
3321 22:18:02.922660 14, 0x0, sum = 3
3322 22:18:02.922733 15, 0x0, sum = 4
3323 22:18:02.925879 best_step = 13
3324 22:18:02.925976
3325 22:18:02.926047 ==
3326 22:18:02.929520 Dram Type= 6, Freq= 0, CH_1, rank 0
3327 22:18:02.932707 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3328 22:18:02.932777 ==
3329 22:18:02.932838 RX Vref Scan: 1
3330 22:18:02.936069
3331 22:18:02.936152 Set Vref Range= 32 -> 127
3332 22:18:02.936215
3333 22:18:02.939424 RX Vref 32 -> 127, step: 1
3334 22:18:02.939515
3335 22:18:02.942670 RX Delay -13 -> 252, step: 4
3336 22:18:02.942767
3337 22:18:02.945912 Set Vref, RX VrefLevel [Byte0]: 32
3338 22:18:02.949419 [Byte1]: 32
3339 22:18:02.949523
3340 22:18:02.952532 Set Vref, RX VrefLevel [Byte0]: 33
3341 22:18:02.956199 [Byte1]: 33
3342 22:18:02.959496
3343 22:18:02.959577 Set Vref, RX VrefLevel [Byte0]: 34
3344 22:18:02.962886 [Byte1]: 34
3345 22:18:02.967806
3346 22:18:02.967892 Set Vref, RX VrefLevel [Byte0]: 35
3347 22:18:02.970871 [Byte1]: 35
3348 22:18:02.975146
3349 22:18:02.975252 Set Vref, RX VrefLevel [Byte0]: 36
3350 22:18:02.978572 [Byte1]: 36
3351 22:18:02.982965
3352 22:18:02.983041 Set Vref, RX VrefLevel [Byte0]: 37
3353 22:18:02.986567 [Byte1]: 37
3354 22:18:02.991432
3355 22:18:02.991534 Set Vref, RX VrefLevel [Byte0]: 38
3356 22:18:02.994348 [Byte1]: 38
3357 22:18:02.999338
3358 22:18:02.999444 Set Vref, RX VrefLevel [Byte0]: 39
3359 22:18:03.002356 [Byte1]: 39
3360 22:18:03.006591
3361 22:18:03.006695 Set Vref, RX VrefLevel [Byte0]: 40
3362 22:18:03.010285 [Byte1]: 40
3363 22:18:03.014803
3364 22:18:03.014878 Set Vref, RX VrefLevel [Byte0]: 41
3365 22:18:03.018223 [Byte1]: 41
3366 22:18:03.022449
3367 22:18:03.022556 Set Vref, RX VrefLevel [Byte0]: 42
3368 22:18:03.026140 [Byte1]: 42
3369 22:18:03.030737
3370 22:18:03.030842 Set Vref, RX VrefLevel [Byte0]: 43
3371 22:18:03.033870 [Byte1]: 43
3372 22:18:03.038483
3373 22:18:03.038589 Set Vref, RX VrefLevel [Byte0]: 44
3374 22:18:03.041475 [Byte1]: 44
3375 22:18:03.046181
3376 22:18:03.046255 Set Vref, RX VrefLevel [Byte0]: 45
3377 22:18:03.049317 [Byte1]: 45
3378 22:18:03.054034
3379 22:18:03.054106 Set Vref, RX VrefLevel [Byte0]: 46
3380 22:18:03.057565 [Byte1]: 46
3381 22:18:03.062240
3382 22:18:03.062322 Set Vref, RX VrefLevel [Byte0]: 47
3383 22:18:03.065075 [Byte1]: 47
3384 22:18:03.069782
3385 22:18:03.069865 Set Vref, RX VrefLevel [Byte0]: 48
3386 22:18:03.073413 [Byte1]: 48
3387 22:18:03.078099
3388 22:18:03.078183 Set Vref, RX VrefLevel [Byte0]: 49
3389 22:18:03.081272 [Byte1]: 49
3390 22:18:03.085618
3391 22:18:03.085701 Set Vref, RX VrefLevel [Byte0]: 50
3392 22:18:03.089414 [Byte1]: 50
3393 22:18:03.093617
3394 22:18:03.093699 Set Vref, RX VrefLevel [Byte0]: 51
3395 22:18:03.097106 [Byte1]: 51
3396 22:18:03.101774
3397 22:18:03.101855 Set Vref, RX VrefLevel [Byte0]: 52
3398 22:18:03.104751 [Byte1]: 52
3399 22:18:03.109075
3400 22:18:03.109159 Set Vref, RX VrefLevel [Byte0]: 53
3401 22:18:03.112466 [Byte1]: 53
3402 22:18:03.117422
3403 22:18:03.117503 Set Vref, RX VrefLevel [Byte0]: 54
3404 22:18:03.120822 [Byte1]: 54
3405 22:18:03.124981
3406 22:18:03.125062 Set Vref, RX VrefLevel [Byte0]: 55
3407 22:18:03.128785 [Byte1]: 55
3408 22:18:03.132918
3409 22:18:03.132998 Set Vref, RX VrefLevel [Byte0]: 56
3410 22:18:03.136074 [Byte1]: 56
3411 22:18:03.141187
3412 22:18:03.141267 Set Vref, RX VrefLevel [Byte0]: 57
3413 22:18:03.144362 [Byte1]: 57
3414 22:18:03.148906
3415 22:18:03.148986 Set Vref, RX VrefLevel [Byte0]: 58
3416 22:18:03.152534 [Byte1]: 58
3417 22:18:03.156679
3418 22:18:03.156760 Set Vref, RX VrefLevel [Byte0]: 59
3419 22:18:03.160668 [Byte1]: 59
3420 22:18:03.164271
3421 22:18:03.164353 Set Vref, RX VrefLevel [Byte0]: 60
3422 22:18:03.167488 [Byte1]: 60
3423 22:18:03.172088
3424 22:18:03.172170 Set Vref, RX VrefLevel [Byte0]: 61
3425 22:18:03.175823 [Byte1]: 61
3426 22:18:03.180021
3427 22:18:03.180143 Set Vref, RX VrefLevel [Byte0]: 62
3428 22:18:03.183752 [Byte1]: 62
3429 22:18:03.187950
3430 22:18:03.188123 Set Vref, RX VrefLevel [Byte0]: 63
3431 22:18:03.191330 [Byte1]: 63
3432 22:18:03.195983
3433 22:18:03.196131 Set Vref, RX VrefLevel [Byte0]: 64
3434 22:18:03.199301 [Byte1]: 64
3435 22:18:03.203688
3436 22:18:03.203827 Set Vref, RX VrefLevel [Byte0]: 65
3437 22:18:03.207572 [Byte1]: 65
3438 22:18:03.212007
3439 22:18:03.212132 Set Vref, RX VrefLevel [Byte0]: 66
3440 22:18:03.215003 [Byte1]: 66
3441 22:18:03.219658
3442 22:18:03.219741 Final RX Vref Byte 0 = 49 to rank0
3443 22:18:03.222913 Final RX Vref Byte 1 = 53 to rank0
3444 22:18:03.226526 Final RX Vref Byte 0 = 49 to rank1
3445 22:18:03.229389 Final RX Vref Byte 1 = 53 to rank1==
3446 22:18:03.232686 Dram Type= 6, Freq= 0, CH_1, rank 0
3447 22:18:03.239585 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3448 22:18:03.239662 ==
3449 22:18:03.239727 DQS Delay:
3450 22:18:03.242815 DQS0 = 0, DQS1 = 0
3451 22:18:03.242886 DQM Delay:
3452 22:18:03.242951 DQM0 = 117, DQM1 = 114
3453 22:18:03.246478 DQ Delay:
3454 22:18:03.249523 DQ0 =122, DQ1 =112, DQ2 =108, DQ3 =116
3455 22:18:03.252666 DQ4 =112, DQ5 =126, DQ6 =130, DQ7 =112
3456 22:18:03.255968 DQ8 =100, DQ9 =104, DQ10 =116, DQ11 =108
3457 22:18:03.259734 DQ12 =124, DQ13 =122, DQ14 =120, DQ15 =124
3458 22:18:03.259806
3459 22:18:03.259866
3460 22:18:03.269646 [DQSOSCAuto] RK0, (LSB)MR18= 0xf0fd, (MSB)MR19= 0x303, tDQSOscB0 = 411 ps tDQSOscB1 = 416 ps
3461 22:18:03.269728 CH1 RK0: MR19=303, MR18=F0FD
3462 22:18:03.276254 CH1_RK0: MR19=0x303, MR18=0xF0FD, DQSOSC=411, MR23=63, INC=38, DEC=25
3463 22:18:03.276332
3464 22:18:03.279067 ----->DramcWriteLeveling(PI) begin...
3465 22:18:03.279143 ==
3466 22:18:03.282461 Dram Type= 6, Freq= 0, CH_1, rank 1
3467 22:18:03.289074 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3468 22:18:03.289154 ==
3469 22:18:03.292694 Write leveling (Byte 0): 26 => 26
3470 22:18:03.292768 Write leveling (Byte 1): 28 => 28
3471 22:18:03.296103 DramcWriteLeveling(PI) end<-----
3472 22:18:03.296175
3473 22:18:03.296239 ==
3474 22:18:03.299497 Dram Type= 6, Freq= 0, CH_1, rank 1
3475 22:18:03.306135 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3476 22:18:03.306216 ==
3477 22:18:03.309191 [Gating] SW mode calibration
3478 22:18:03.315694 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3479 22:18:03.319069 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3480 22:18:03.325906 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3481 22:18:03.328920 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3482 22:18:03.332312 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3483 22:18:03.339280 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3484 22:18:03.342230 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3485 22:18:03.345637 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3486 22:18:03.352014 0 15 24 | B1->B0 | 3434 2525 | 1 0 | (1 0) (1 0)
3487 22:18:03.355513 0 15 28 | B1->B0 | 3030 2323 | 0 0 | (0 1) (0 0)
3488 22:18:03.359065 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3489 22:18:03.365252 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3490 22:18:03.368788 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3491 22:18:03.372006 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3492 22:18:03.378949 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3493 22:18:03.382106 1 0 20 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
3494 22:18:03.385267 1 0 24 | B1->B0 | 2323 4545 | 0 0 | (0 0) (0 0)
3495 22:18:03.391742 1 0 28 | B1->B0 | 3434 4646 | 0 0 | (0 0) (0 0)
3496 22:18:03.395615 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3497 22:18:03.398590 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3498 22:18:03.405225 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3499 22:18:03.408846 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3500 22:18:03.412000 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3501 22:18:03.418532 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3502 22:18:03.422016 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3503 22:18:03.425569 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3504 22:18:03.431662 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3505 22:18:03.435054 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3506 22:18:03.438244 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3507 22:18:03.444674 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3508 22:18:03.448402 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3509 22:18:03.451540 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3510 22:18:03.458162 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3511 22:18:03.461500 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3512 22:18:03.464433 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3513 22:18:03.471192 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3514 22:18:03.474234 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3515 22:18:03.478158 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3516 22:18:03.484743 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3517 22:18:03.487843 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3518 22:18:03.490968 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3519 22:18:03.497497 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3520 22:18:03.497926 Total UI for P1: 0, mck2ui 16
3521 22:18:03.503926 best dqsien dly found for B0: ( 1, 3, 22)
3522 22:18:03.504373 Total UI for P1: 0, mck2ui 16
3523 22:18:03.510918 best dqsien dly found for B1: ( 1, 3, 26)
3524 22:18:03.513906 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3525 22:18:03.517194 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3526 22:18:03.517620
3527 22:18:03.520517 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3528 22:18:03.524007 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3529 22:18:03.527180 [Gating] SW calibration Done
3530 22:18:03.527682 ==
3531 22:18:03.530344 Dram Type= 6, Freq= 0, CH_1, rank 1
3532 22:18:03.533674 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3533 22:18:03.534104 ==
3534 22:18:03.537254 RX Vref Scan: 0
3535 22:18:03.537679
3536 22:18:03.538016 RX Vref 0 -> 0, step: 1
3537 22:18:03.538328
3538 22:18:03.540629 RX Delay -40 -> 252, step: 8
3539 22:18:03.543883 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3540 22:18:03.550148 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3541 22:18:03.553866 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3542 22:18:03.557169 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
3543 22:18:03.560263 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3544 22:18:03.567125 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3545 22:18:03.569908 iDelay=200, Bit 6, Center 123 (56 ~ 191) 136
3546 22:18:03.573247 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3547 22:18:03.576766 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3548 22:18:03.579810 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3549 22:18:03.586618 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3550 22:18:03.589903 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3551 22:18:03.593773 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3552 22:18:03.596400 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
3553 22:18:03.600119 iDelay=200, Bit 14, Center 119 (56 ~ 183) 128
3554 22:18:03.606049 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3555 22:18:03.606470 ==
3556 22:18:03.609571 Dram Type= 6, Freq= 0, CH_1, rank 1
3557 22:18:03.612639 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3558 22:18:03.613031 ==
3559 22:18:03.613367 DQS Delay:
3560 22:18:03.616133 DQS0 = 0, DQS1 = 0
3561 22:18:03.616529 DQM Delay:
3562 22:18:03.619100 DQM0 = 117, DQM1 = 114
3563 22:18:03.619547 DQ Delay:
3564 22:18:03.622390 DQ0 =123, DQ1 =111, DQ2 =103, DQ3 =115
3565 22:18:03.626007 DQ4 =119, DQ5 =127, DQ6 =123, DQ7 =115
3566 22:18:03.629327 DQ8 =103, DQ9 =99, DQ10 =115, DQ11 =107
3567 22:18:03.635669 DQ12 =123, DQ13 =123, DQ14 =119, DQ15 =123
3568 22:18:03.636140
3569 22:18:03.636495
3570 22:18:03.636821 ==
3571 22:18:03.639326 Dram Type= 6, Freq= 0, CH_1, rank 1
3572 22:18:03.642637 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3573 22:18:03.643091 ==
3574 22:18:03.643447
3575 22:18:03.643779
3576 22:18:03.645664 TX Vref Scan disable
3577 22:18:03.646041 == TX Byte 0 ==
3578 22:18:03.652517 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3579 22:18:03.655766 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3580 22:18:03.656250 == TX Byte 1 ==
3581 22:18:03.662540 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3582 22:18:03.665842 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3583 22:18:03.666446 ==
3584 22:18:03.669105 Dram Type= 6, Freq= 0, CH_1, rank 1
3585 22:18:03.672357 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3586 22:18:03.672805 ==
3587 22:18:03.685260 TX Vref=22, minBit 3, minWin=25, winSum=421
3588 22:18:03.688353 TX Vref=24, minBit 9, minWin=25, winSum=421
3589 22:18:03.691351 TX Vref=26, minBit 9, minWin=25, winSum=427
3590 22:18:03.694599 TX Vref=28, minBit 3, minWin=26, winSum=429
3591 22:18:03.697959 TX Vref=30, minBit 1, minWin=26, winSum=430
3592 22:18:03.704977 TX Vref=32, minBit 8, minWin=25, winSum=429
3593 22:18:03.707887 [TxChooseVref] Worse bit 1, Min win 26, Win sum 430, Final Vref 30
3594 22:18:03.708397
3595 22:18:03.711389 Final TX Range 1 Vref 30
3596 22:18:03.711821
3597 22:18:03.712198 ==
3598 22:18:03.714799 Dram Type= 6, Freq= 0, CH_1, rank 1
3599 22:18:03.717685 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3600 22:18:03.721016 ==
3601 22:18:03.721422
3602 22:18:03.721779
3603 22:18:03.722119 TX Vref Scan disable
3604 22:18:03.724673 == TX Byte 0 ==
3605 22:18:03.727568 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3606 22:18:03.734300 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3607 22:18:03.734765 == TX Byte 1 ==
3608 22:18:03.737936 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3609 22:18:03.744083 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3610 22:18:03.744541
3611 22:18:03.744898 [DATLAT]
3612 22:18:03.745243 Freq=1200, CH1 RK1
3613 22:18:03.745576
3614 22:18:03.747455 DATLAT Default: 0xd
3615 22:18:03.750833 0, 0xFFFF, sum = 0
3616 22:18:03.751236 1, 0xFFFF, sum = 0
3617 22:18:03.753948 2, 0xFFFF, sum = 0
3618 22:18:03.754424 3, 0xFFFF, sum = 0
3619 22:18:03.757513 4, 0xFFFF, sum = 0
3620 22:18:03.757973 5, 0xFFFF, sum = 0
3621 22:18:03.760824 6, 0xFFFF, sum = 0
3622 22:18:03.761288 7, 0xFFFF, sum = 0
3623 22:18:03.764082 8, 0xFFFF, sum = 0
3624 22:18:03.764591 9, 0xFFFF, sum = 0
3625 22:18:03.767262 10, 0xFFFF, sum = 0
3626 22:18:03.767731 11, 0xFFFF, sum = 0
3627 22:18:03.770554 12, 0x0, sum = 1
3628 22:18:03.771014 13, 0x0, sum = 2
3629 22:18:03.773619 14, 0x0, sum = 3
3630 22:18:03.774080 15, 0x0, sum = 4
3631 22:18:03.776698 best_step = 13
3632 22:18:03.776789
3633 22:18:03.776854 ==
3634 22:18:03.779991 Dram Type= 6, Freq= 0, CH_1, rank 1
3635 22:18:03.783219 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3636 22:18:03.783309 ==
3637 22:18:03.786548 RX Vref Scan: 0
3638 22:18:03.786630
3639 22:18:03.786696 RX Vref 0 -> 0, step: 1
3640 22:18:03.786756
3641 22:18:03.789652 RX Delay -13 -> 252, step: 4
3642 22:18:03.796362 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
3643 22:18:03.799934 iDelay=195, Bit 1, Center 112 (47 ~ 178) 132
3644 22:18:03.803189 iDelay=195, Bit 2, Center 108 (43 ~ 174) 132
3645 22:18:03.806407 iDelay=195, Bit 3, Center 116 (51 ~ 182) 132
3646 22:18:03.813294 iDelay=195, Bit 4, Center 116 (51 ~ 182) 132
3647 22:18:03.815967 iDelay=195, Bit 5, Center 124 (55 ~ 194) 140
3648 22:18:03.819091 iDelay=195, Bit 6, Center 124 (59 ~ 190) 132
3649 22:18:03.822445 iDelay=195, Bit 7, Center 114 (47 ~ 182) 136
3650 22:18:03.825969 iDelay=195, Bit 8, Center 102 (43 ~ 162) 120
3651 22:18:03.832436 iDelay=195, Bit 9, Center 104 (43 ~ 166) 124
3652 22:18:03.835674 iDelay=195, Bit 10, Center 116 (55 ~ 178) 124
3653 22:18:03.839050 iDelay=195, Bit 11, Center 110 (51 ~ 170) 120
3654 22:18:03.842476 iDelay=195, Bit 12, Center 122 (63 ~ 182) 120
3655 22:18:03.846008 iDelay=195, Bit 13, Center 120 (59 ~ 182) 124
3656 22:18:03.852141 iDelay=195, Bit 14, Center 120 (59 ~ 182) 124
3657 22:18:03.855900 iDelay=195, Bit 15, Center 124 (63 ~ 186) 124
3658 22:18:03.855994 ==
3659 22:18:03.859367 Dram Type= 6, Freq= 0, CH_1, rank 1
3660 22:18:03.862275 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3661 22:18:03.862384 ==
3662 22:18:03.865495 DQS Delay:
3663 22:18:03.865602 DQS0 = 0, DQS1 = 0
3664 22:18:03.868597 DQM Delay:
3665 22:18:03.868671 DQM0 = 116, DQM1 = 114
3666 22:18:03.868733 DQ Delay:
3667 22:18:03.871858 DQ0 =118, DQ1 =112, DQ2 =108, DQ3 =116
3668 22:18:03.878892 DQ4 =116, DQ5 =124, DQ6 =124, DQ7 =114
3669 22:18:03.881876 DQ8 =102, DQ9 =104, DQ10 =116, DQ11 =110
3670 22:18:03.884934 DQ12 =122, DQ13 =120, DQ14 =120, DQ15 =124
3671 22:18:03.885008
3672 22:18:03.885070
3673 22:18:03.891629 [DQSOSCAuto] RK1, (LSB)MR18= 0xf407, (MSB)MR19= 0x304, tDQSOscB0 = 407 ps tDQSOscB1 = 415 ps
3674 22:18:03.894936 CH1 RK1: MR19=304, MR18=F407
3675 22:18:03.901548 CH1_RK1: MR19=0x304, MR18=0xF407, DQSOSC=407, MR23=63, INC=39, DEC=26
3676 22:18:03.904657 [RxdqsGatingPostProcess] freq 1200
3677 22:18:03.911475 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3678 22:18:03.914474 best DQS0 dly(2T, 0.5T) = (0, 11)
3679 22:18:03.917831 best DQS1 dly(2T, 0.5T) = (0, 11)
3680 22:18:03.920906 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3681 22:18:03.924611 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3682 22:18:03.924688 best DQS0 dly(2T, 0.5T) = (0, 11)
3683 22:18:03.927588 best DQS1 dly(2T, 0.5T) = (0, 11)
3684 22:18:03.930712 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3685 22:18:03.934184 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3686 22:18:03.938011 Pre-setting of DQS Precalculation
3687 22:18:03.943992 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3688 22:18:03.950701 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3689 22:18:03.957554 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3690 22:18:03.957639
3691 22:18:03.957704
3692 22:18:03.960442 [Calibration Summary] 2400 Mbps
3693 22:18:03.964206 CH 0, Rank 0
3694 22:18:03.964278 SW Impedance : PASS
3695 22:18:03.967388 DUTY Scan : NO K
3696 22:18:03.967462 ZQ Calibration : PASS
3697 22:18:03.970781 Jitter Meter : NO K
3698 22:18:03.973673 CBT Training : PASS
3699 22:18:03.973743 Write leveling : PASS
3700 22:18:03.977534 RX DQS gating : PASS
3701 22:18:03.980339 RX DQ/DQS(RDDQC) : PASS
3702 22:18:03.980413 TX DQ/DQS : PASS
3703 22:18:03.983849 RX DATLAT : PASS
3704 22:18:03.986925 RX DQ/DQS(Engine): PASS
3705 22:18:03.987005 TX OE : NO K
3706 22:18:03.990582 All Pass.
3707 22:18:03.990661
3708 22:18:03.990723 CH 0, Rank 1
3709 22:18:03.993627 SW Impedance : PASS
3710 22:18:03.993697 DUTY Scan : NO K
3711 22:18:03.996871 ZQ Calibration : PASS
3712 22:18:04.000332 Jitter Meter : NO K
3713 22:18:04.000403 CBT Training : PASS
3714 22:18:04.003596 Write leveling : PASS
3715 22:18:04.006707 RX DQS gating : PASS
3716 22:18:04.006783 RX DQ/DQS(RDDQC) : PASS
3717 22:18:04.010428 TX DQ/DQS : PASS
3718 22:18:04.013431 RX DATLAT : PASS
3719 22:18:04.013503 RX DQ/DQS(Engine): PASS
3720 22:18:04.016510 TX OE : NO K
3721 22:18:04.016589 All Pass.
3722 22:18:04.016651
3723 22:18:04.019715 CH 1, Rank 0
3724 22:18:04.019784 SW Impedance : PASS
3725 22:18:04.022974 DUTY Scan : NO K
3726 22:18:04.026552 ZQ Calibration : PASS
3727 22:18:04.026624 Jitter Meter : NO K
3728 22:18:04.029671 CBT Training : PASS
3729 22:18:04.033062 Write leveling : PASS
3730 22:18:04.033135 RX DQS gating : PASS
3731 22:18:04.035996 RX DQ/DQS(RDDQC) : PASS
3732 22:18:04.039513 TX DQ/DQS : PASS
3733 22:18:04.039587 RX DATLAT : PASS
3734 22:18:04.043187 RX DQ/DQS(Engine): PASS
3735 22:18:04.043269 TX OE : NO K
3736 22:18:04.046205 All Pass.
3737 22:18:04.046276
3738 22:18:04.046337 CH 1, Rank 1
3739 22:18:04.049578 SW Impedance : PASS
3740 22:18:04.053079 DUTY Scan : NO K
3741 22:18:04.053153 ZQ Calibration : PASS
3742 22:18:04.056240 Jitter Meter : NO K
3743 22:18:04.056315 CBT Training : PASS
3744 22:18:04.059375 Write leveling : PASS
3745 22:18:04.062433 RX DQS gating : PASS
3746 22:18:04.062528 RX DQ/DQS(RDDQC) : PASS
3747 22:18:04.066093 TX DQ/DQS : PASS
3748 22:18:04.069363 RX DATLAT : PASS
3749 22:18:04.069466 RX DQ/DQS(Engine): PASS
3750 22:18:04.072852 TX OE : NO K
3751 22:18:04.072960 All Pass.
3752 22:18:04.073050
3753 22:18:04.076057 DramC Write-DBI off
3754 22:18:04.079247 PER_BANK_REFRESH: Hybrid Mode
3755 22:18:04.079366 TX_TRACKING: ON
3756 22:18:04.089134 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3757 22:18:04.092634 [FAST_K] Save calibration result to emmc
3758 22:18:04.095665 dramc_set_vcore_voltage set vcore to 650000
3759 22:18:04.098929 Read voltage for 600, 5
3760 22:18:04.099107 Vio18 = 0
3761 22:18:04.102344 Vcore = 650000
3762 22:18:04.102570 Vdram = 0
3763 22:18:04.102752 Vddq = 0
3764 22:18:04.102939 Vmddr = 0
3765 22:18:04.109056 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3766 22:18:04.115659 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3767 22:18:04.115735 MEM_TYPE=3, freq_sel=19
3768 22:18:04.118746 sv_algorithm_assistance_LP4_1600
3769 22:18:04.121902 ============ PULL DRAM RESETB DOWN ============
3770 22:18:04.128845 ========== PULL DRAM RESETB DOWN end =========
3771 22:18:04.131662 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3772 22:18:04.135086 ===================================
3773 22:18:04.138431 LPDDR4 DRAM CONFIGURATION
3774 22:18:04.141768 ===================================
3775 22:18:04.141842 EX_ROW_EN[0] = 0x0
3776 22:18:04.144711 EX_ROW_EN[1] = 0x0
3777 22:18:04.144781 LP4Y_EN = 0x0
3778 22:18:04.148017 WORK_FSP = 0x0
3779 22:18:04.151351 WL = 0x2
3780 22:18:04.151439 RL = 0x2
3781 22:18:04.154606 BL = 0x2
3782 22:18:04.154676 RPST = 0x0
3783 22:18:04.158290 RD_PRE = 0x0
3784 22:18:04.158364 WR_PRE = 0x1
3785 22:18:04.161360 WR_PST = 0x0
3786 22:18:04.161437 DBI_WR = 0x0
3787 22:18:04.164813 DBI_RD = 0x0
3788 22:18:04.164884 OTF = 0x1
3789 22:18:04.167936 ===================================
3790 22:18:04.171474 ===================================
3791 22:18:04.174206 ANA top config
3792 22:18:04.177917 ===================================
3793 22:18:04.178000 DLL_ASYNC_EN = 0
3794 22:18:04.181092 ALL_SLAVE_EN = 1
3795 22:18:04.184018 NEW_RANK_MODE = 1
3796 22:18:04.187595 DLL_IDLE_MODE = 1
3797 22:18:04.190643 LP45_APHY_COMB_EN = 1
3798 22:18:04.190725 TX_ODT_DIS = 1
3799 22:18:04.194320 NEW_8X_MODE = 1
3800 22:18:04.197284 ===================================
3801 22:18:04.200762 ===================================
3802 22:18:04.204163 data_rate = 1200
3803 22:18:04.207372 CKR = 1
3804 22:18:04.210706 DQ_P2S_RATIO = 8
3805 22:18:04.213712 ===================================
3806 22:18:04.217403 CA_P2S_RATIO = 8
3807 22:18:04.217490 DQ_CA_OPEN = 0
3808 22:18:04.220385 DQ_SEMI_OPEN = 0
3809 22:18:04.223714 CA_SEMI_OPEN = 0
3810 22:18:04.227152 CA_FULL_RATE = 0
3811 22:18:04.230622 DQ_CKDIV4_EN = 1
3812 22:18:04.233753 CA_CKDIV4_EN = 1
3813 22:18:04.233839 CA_PREDIV_EN = 0
3814 22:18:04.236597 PH8_DLY = 0
3815 22:18:04.239993 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3816 22:18:04.243328 DQ_AAMCK_DIV = 4
3817 22:18:04.246784 CA_AAMCK_DIV = 4
3818 22:18:04.250193 CA_ADMCK_DIV = 4
3819 22:18:04.253290 DQ_TRACK_CA_EN = 0
3820 22:18:04.253384 CA_PICK = 600
3821 22:18:04.256609 CA_MCKIO = 600
3822 22:18:04.259627 MCKIO_SEMI = 0
3823 22:18:04.262855 PLL_FREQ = 2288
3824 22:18:04.266394 DQ_UI_PI_RATIO = 32
3825 22:18:04.269558 CA_UI_PI_RATIO = 0
3826 22:18:04.273843 ===================================
3827 22:18:04.275969 ===================================
3828 22:18:04.279729 memory_type:LPDDR4
3829 22:18:04.279806 GP_NUM : 10
3830 22:18:04.282543 SRAM_EN : 1
3831 22:18:04.282620 MD32_EN : 0
3832 22:18:04.286288 ===================================
3833 22:18:04.289661 [ANA_INIT] >>>>>>>>>>>>>>
3834 22:18:04.292430 <<<<<< [CONFIGURE PHASE]: ANA_TX
3835 22:18:04.295566 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3836 22:18:04.299525 ===================================
3837 22:18:04.302370 data_rate = 1200,PCW = 0X5800
3838 22:18:04.305860 ===================================
3839 22:18:04.308892 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3840 22:18:04.315782 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3841 22:18:04.318767 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3842 22:18:04.325384 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3843 22:18:04.329022 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3844 22:18:04.331990 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3845 22:18:04.332143 [ANA_INIT] flow start
3846 22:18:04.335467 [ANA_INIT] PLL >>>>>>>>
3847 22:18:04.338881 [ANA_INIT] PLL <<<<<<<<
3848 22:18:04.338997 [ANA_INIT] MIDPI >>>>>>>>
3849 22:18:04.341772 [ANA_INIT] MIDPI <<<<<<<<
3850 22:18:04.345324 [ANA_INIT] DLL >>>>>>>>
3851 22:18:04.345478 [ANA_INIT] flow end
3852 22:18:04.352087 ============ LP4 DIFF to SE enter ============
3853 22:18:04.355077 ============ LP4 DIFF to SE exit ============
3854 22:18:04.358367 [ANA_INIT] <<<<<<<<<<<<<
3855 22:18:04.361865 [Flow] Enable top DCM control >>>>>
3856 22:18:04.365303 [Flow] Enable top DCM control <<<<<
3857 22:18:04.368299 Enable DLL master slave shuffle
3858 22:18:04.371970 ==============================================================
3859 22:18:04.375318 Gating Mode config
3860 22:18:04.378012 ==============================================================
3861 22:18:04.381944 Config description:
3862 22:18:04.391071 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3863 22:18:04.397533 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3864 22:18:04.401196 SELPH_MODE 0: By rank 1: By Phase
3865 22:18:04.407942 ==============================================================
3866 22:18:04.411136 GAT_TRACK_EN = 1
3867 22:18:04.414598 RX_GATING_MODE = 2
3868 22:18:04.417872 RX_GATING_TRACK_MODE = 2
3869 22:18:04.421018 SELPH_MODE = 1
3870 22:18:04.424492 PICG_EARLY_EN = 1
3871 22:18:04.428134 VALID_LAT_VALUE = 1
3872 22:18:04.431002 ==============================================================
3873 22:18:04.434245 Enter into Gating configuration >>>>
3874 22:18:04.438013 Exit from Gating configuration <<<<
3875 22:18:04.440605 Enter into DVFS_PRE_config >>>>>
3876 22:18:04.453994 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3877 22:18:04.457265 Exit from DVFS_PRE_config <<<<<
3878 22:18:04.460834 Enter into PICG configuration >>>>
3879 22:18:04.460918 Exit from PICG configuration <<<<
3880 22:18:04.463582 [RX_INPUT] configuration >>>>>
3881 22:18:04.467476 [RX_INPUT] configuration <<<<<
3882 22:18:04.473792 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3883 22:18:04.476758 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3884 22:18:04.483600 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3885 22:18:04.490419 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3886 22:18:04.496745 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3887 22:18:04.503054 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3888 22:18:04.506329 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3889 22:18:04.509992 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3890 22:18:04.516617 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3891 22:18:04.519939 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3892 22:18:04.523049 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3893 22:18:04.529475 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3894 22:18:04.532801 ===================================
3895 22:18:04.532885 LPDDR4 DRAM CONFIGURATION
3896 22:18:04.536002 ===================================
3897 22:18:04.539428 EX_ROW_EN[0] = 0x0
3898 22:18:04.539512 EX_ROW_EN[1] = 0x0
3899 22:18:04.542439 LP4Y_EN = 0x0
3900 22:18:04.546269 WORK_FSP = 0x0
3901 22:18:04.546352 WL = 0x2
3902 22:18:04.549086 RL = 0x2
3903 22:18:04.549170 BL = 0x2
3904 22:18:04.552375 RPST = 0x0
3905 22:18:04.552458 RD_PRE = 0x0
3906 22:18:04.555966 WR_PRE = 0x1
3907 22:18:04.556092 WR_PST = 0x0
3908 22:18:04.558994 DBI_WR = 0x0
3909 22:18:04.559077 DBI_RD = 0x0
3910 22:18:04.562410 OTF = 0x1
3911 22:18:04.565891 ===================================
3912 22:18:04.568991 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3913 22:18:04.572482 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3914 22:18:04.578656 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3915 22:18:04.581886 ===================================
3916 22:18:04.581992 LPDDR4 DRAM CONFIGURATION
3917 22:18:04.585278 ===================================
3918 22:18:04.588362 EX_ROW_EN[0] = 0x10
3919 22:18:04.591690 EX_ROW_EN[1] = 0x0
3920 22:18:04.591774 LP4Y_EN = 0x0
3921 22:18:04.595140 WORK_FSP = 0x0
3922 22:18:04.595224 WL = 0x2
3923 22:18:04.598590 RL = 0x2
3924 22:18:04.598674 BL = 0x2
3925 22:18:04.601849 RPST = 0x0
3926 22:18:04.601940 RD_PRE = 0x0
3927 22:18:04.605376 WR_PRE = 0x1
3928 22:18:04.605459 WR_PST = 0x0
3929 22:18:04.608574 DBI_WR = 0x0
3930 22:18:04.608680 DBI_RD = 0x0
3931 22:18:04.611602 OTF = 0x1
3932 22:18:04.614866 ===================================
3933 22:18:04.621618 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3934 22:18:04.624916 nWR fixed to 30
3935 22:18:04.627895 [ModeRegInit_LP4] CH0 RK0
3936 22:18:04.628014 [ModeRegInit_LP4] CH0 RK1
3937 22:18:04.631424 [ModeRegInit_LP4] CH1 RK0
3938 22:18:04.634626 [ModeRegInit_LP4] CH1 RK1
3939 22:18:04.634709 match AC timing 17
3940 22:18:04.641373 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3941 22:18:04.644398 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3942 22:18:04.647656 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3943 22:18:04.654082 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3944 22:18:04.657903 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3945 22:18:04.657987 ==
3946 22:18:04.660956 Dram Type= 6, Freq= 0, CH_0, rank 0
3947 22:18:04.663990 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3948 22:18:04.664117 ==
3949 22:18:04.670606 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3950 22:18:04.677438 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3951 22:18:04.680472 [CA 0] Center 36 (6~67) winsize 62
3952 22:18:04.683546 [CA 1] Center 36 (5~67) winsize 63
3953 22:18:04.686993 [CA 2] Center 34 (4~65) winsize 62
3954 22:18:04.690716 [CA 3] Center 34 (4~65) winsize 62
3955 22:18:04.693709 [CA 4] Center 33 (3~64) winsize 62
3956 22:18:04.696792 [CA 5] Center 33 (2~64) winsize 63
3957 22:18:04.696873
3958 22:18:04.700301 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3959 22:18:04.700383
3960 22:18:04.703471 [CATrainingPosCal] consider 1 rank data
3961 22:18:04.706657 u2DelayCellTimex100 = 270/100 ps
3962 22:18:04.710073 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3963 22:18:04.713247 CA1 delay=36 (5~67),Diff = 3 PI (28 cell)
3964 22:18:04.716700 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3965 22:18:04.723053 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3966 22:18:04.726248 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3967 22:18:04.730013 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
3968 22:18:04.730099
3969 22:18:04.733082 CA PerBit enable=1, Macro0, CA PI delay=33
3970 22:18:04.733164
3971 22:18:04.735999 [CBTSetCACLKResult] CA Dly = 33
3972 22:18:04.736105 CS Dly: 5 (0~36)
3973 22:18:04.736171 ==
3974 22:18:04.739634 Dram Type= 6, Freq= 0, CH_0, rank 1
3975 22:18:04.746425 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3976 22:18:04.746507 ==
3977 22:18:04.749548 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3978 22:18:04.755737 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3979 22:18:04.759355 [CA 0] Center 36 (6~67) winsize 62
3980 22:18:04.762735 [CA 1] Center 36 (6~67) winsize 62
3981 22:18:04.766169 [CA 2] Center 34 (4~65) winsize 62
3982 22:18:04.769806 [CA 3] Center 34 (4~65) winsize 62
3983 22:18:04.772461 [CA 4] Center 34 (3~65) winsize 63
3984 22:18:04.775944 [CA 5] Center 33 (3~64) winsize 62
3985 22:18:04.776027
3986 22:18:04.778956 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3987 22:18:04.779039
3988 22:18:04.785392 [CATrainingPosCal] consider 2 rank data
3989 22:18:04.785475 u2DelayCellTimex100 = 270/100 ps
3990 22:18:04.792765 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3991 22:18:04.795680 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3992 22:18:04.798808 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3993 22:18:04.801933 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3994 22:18:04.805157 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3995 22:18:04.809208 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3996 22:18:04.809291
3997 22:18:04.811937 CA PerBit enable=1, Macro0, CA PI delay=33
3998 22:18:04.812019
3999 22:18:04.815139 [CBTSetCACLKResult] CA Dly = 33
4000 22:18:04.818464 CS Dly: 5 (0~36)
4001 22:18:04.818546
4002 22:18:04.821774 ----->DramcWriteLeveling(PI) begin...
4003 22:18:04.821858 ==
4004 22:18:04.825075 Dram Type= 6, Freq= 0, CH_0, rank 0
4005 22:18:04.828351 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4006 22:18:04.828434 ==
4007 22:18:04.831842 Write leveling (Byte 0): 34 => 34
4008 22:18:04.835114 Write leveling (Byte 1): 30 => 30
4009 22:18:04.838374 DramcWriteLeveling(PI) end<-----
4010 22:18:04.838457
4011 22:18:04.838522 ==
4012 22:18:04.841760 Dram Type= 6, Freq= 0, CH_0, rank 0
4013 22:18:04.845142 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4014 22:18:04.845225 ==
4015 22:18:04.848233 [Gating] SW mode calibration
4016 22:18:04.854636 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4017 22:18:04.861414 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4018 22:18:04.864401 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4019 22:18:04.871186 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4020 22:18:04.874523 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4021 22:18:04.877660 0 9 12 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
4022 22:18:04.884790 0 9 16 | B1->B0 | 2d2d 2424 | 0 0 | (0 0) (0 0)
4023 22:18:04.888006 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4024 22:18:04.891054 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4025 22:18:04.897300 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4026 22:18:04.900891 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4027 22:18:04.904340 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4028 22:18:04.910925 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4029 22:18:04.914278 0 10 12 | B1->B0 | 2a2a 3131 | 1 0 | (0 0) (0 0)
4030 22:18:04.916970 0 10 16 | B1->B0 | 3535 4343 | 0 0 | (0 0) (0 0)
4031 22:18:04.923925 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4032 22:18:04.927060 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4033 22:18:04.930078 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4034 22:18:04.937373 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4035 22:18:04.940571 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4036 22:18:04.943422 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4037 22:18:04.950048 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4038 22:18:04.953146 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4039 22:18:04.956329 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4040 22:18:04.963124 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4041 22:18:04.966192 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4042 22:18:04.970047 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4043 22:18:04.976346 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4044 22:18:04.979737 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4045 22:18:04.983026 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4046 22:18:04.989413 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4047 22:18:04.993134 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4048 22:18:04.996180 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4049 22:18:05.002647 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4050 22:18:05.006128 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4051 22:18:05.009171 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4052 22:18:05.015944 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4053 22:18:05.019047 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4054 22:18:05.022261 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4055 22:18:05.025936 Total UI for P1: 0, mck2ui 16
4056 22:18:05.028719 best dqsien dly found for B0: ( 0, 13, 12)
4057 22:18:05.035504 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4058 22:18:05.035599 Total UI for P1: 0, mck2ui 16
4059 22:18:05.041927 best dqsien dly found for B1: ( 0, 13, 18)
4060 22:18:05.045494 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4061 22:18:05.048811 best DQS1 dly(MCK, UI, PI) = (0, 13, 18)
4062 22:18:05.048916
4063 22:18:05.051749 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4064 22:18:05.055506 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 18)
4065 22:18:05.058904 [Gating] SW calibration Done
4066 22:18:05.059013 ==
4067 22:18:05.061914 Dram Type= 6, Freq= 0, CH_0, rank 0
4068 22:18:05.065284 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4069 22:18:05.065392 ==
4070 22:18:05.068726 RX Vref Scan: 0
4071 22:18:05.068831
4072 22:18:05.071943 RX Vref 0 -> 0, step: 1
4073 22:18:05.072091
4074 22:18:05.072161 RX Delay -230 -> 252, step: 16
4075 22:18:05.078237 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4076 22:18:05.081710 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4077 22:18:05.084923 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4078 22:18:05.088036 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4079 22:18:05.094657 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4080 22:18:05.097814 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4081 22:18:05.101653 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4082 22:18:05.104695 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4083 22:18:05.111262 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4084 22:18:05.114378 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4085 22:18:05.117663 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4086 22:18:05.121064 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4087 22:18:05.127458 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4088 22:18:05.130690 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4089 22:18:05.134225 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4090 22:18:05.137635 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4091 22:18:05.137734 ==
4092 22:18:05.140750 Dram Type= 6, Freq= 0, CH_0, rank 0
4093 22:18:05.147284 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4094 22:18:05.147385 ==
4095 22:18:05.147487 DQS Delay:
4096 22:18:05.150575 DQS0 = 0, DQS1 = 0
4097 22:18:05.150671 DQM Delay:
4098 22:18:05.154108 DQM0 = 42, DQM1 = 34
4099 22:18:05.154194 DQ Delay:
4100 22:18:05.156986 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4101 22:18:05.160222 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4102 22:18:05.163779 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =33
4103 22:18:05.166851 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4104 22:18:05.166954
4105 22:18:05.167048
4106 22:18:05.167136 ==
4107 22:18:05.170273 Dram Type= 6, Freq= 0, CH_0, rank 0
4108 22:18:05.173930 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4109 22:18:05.174030 ==
4110 22:18:05.174120
4111 22:18:05.174217
4112 22:18:05.177093 TX Vref Scan disable
4113 22:18:05.179940 == TX Byte 0 ==
4114 22:18:05.183317 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4115 22:18:05.186728 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4116 22:18:05.189789 == TX Byte 1 ==
4117 22:18:05.193206 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4118 22:18:05.196631 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4119 22:18:05.196717 ==
4120 22:18:05.200233 Dram Type= 6, Freq= 0, CH_0, rank 0
4121 22:18:05.206578 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4122 22:18:05.206681 ==
4123 22:18:05.206781
4124 22:18:05.206871
4125 22:18:05.206958 TX Vref Scan disable
4126 22:18:05.210955 == TX Byte 0 ==
4127 22:18:05.214557 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4128 22:18:05.220697 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4129 22:18:05.220772 == TX Byte 1 ==
4130 22:18:05.224396 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4131 22:18:05.231024 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4132 22:18:05.231132
4133 22:18:05.231200 [DATLAT]
4134 22:18:05.231258 Freq=600, CH0 RK0
4135 22:18:05.231317
4136 22:18:05.234017 DATLAT Default: 0x9
4137 22:18:05.234093 0, 0xFFFF, sum = 0
4138 22:18:05.237298 1, 0xFFFF, sum = 0
4139 22:18:05.240575 2, 0xFFFF, sum = 0
4140 22:18:05.240649 3, 0xFFFF, sum = 0
4141 22:18:05.244295 4, 0xFFFF, sum = 0
4142 22:18:05.244398 5, 0xFFFF, sum = 0
4143 22:18:05.247129 6, 0xFFFF, sum = 0
4144 22:18:05.247240 7, 0xFFFF, sum = 0
4145 22:18:05.250839 8, 0x0, sum = 1
4146 22:18:05.250938 9, 0x0, sum = 2
4147 22:18:05.253898 10, 0x0, sum = 3
4148 22:18:05.253997 11, 0x0, sum = 4
4149 22:18:05.254097 best_step = 9
4150 22:18:05.254187
4151 22:18:05.257655 ==
4152 22:18:05.257729 Dram Type= 6, Freq= 0, CH_0, rank 0
4153 22:18:05.263719 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4154 22:18:05.263820 ==
4155 22:18:05.263919 RX Vref Scan: 1
4156 22:18:05.264007
4157 22:18:05.267062 RX Vref 0 -> 0, step: 1
4158 22:18:05.267160
4159 22:18:05.270435 RX Delay -195 -> 252, step: 8
4160 22:18:05.270545
4161 22:18:05.273644 Set Vref, RX VrefLevel [Byte0]: 51
4162 22:18:05.277118 [Byte1]: 50
4163 22:18:05.277195
4164 22:18:05.280291 Final RX Vref Byte 0 = 51 to rank0
4165 22:18:05.283467 Final RX Vref Byte 1 = 50 to rank0
4166 22:18:05.287337 Final RX Vref Byte 0 = 51 to rank1
4167 22:18:05.290248 Final RX Vref Byte 1 = 50 to rank1==
4168 22:18:05.293475 Dram Type= 6, Freq= 0, CH_0, rank 0
4169 22:18:05.296927 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4170 22:18:05.299986 ==
4171 22:18:05.300129 DQS Delay:
4172 22:18:05.300196 DQS0 = 0, DQS1 = 0
4173 22:18:05.303263 DQM Delay:
4174 22:18:05.303358 DQM0 = 41, DQM1 = 34
4175 22:18:05.306704 DQ Delay:
4176 22:18:05.309880 DQ0 =44, DQ1 =40, DQ2 =36, DQ3 =36
4177 22:18:05.309989 DQ4 =44, DQ5 =32, DQ6 =52, DQ7 =48
4178 22:18:05.313180 DQ8 =24, DQ9 =24, DQ10 =36, DQ11 =28
4179 22:18:05.316339 DQ12 =40, DQ13 =40, DQ14 =44, DQ15 =40
4180 22:18:05.319733
4181 22:18:05.319831
4182 22:18:05.326778 [DQSOSCAuto] RK0, (LSB)MR18= 0x4e45, (MSB)MR19= 0x808, tDQSOscB0 = 396 ps tDQSOscB1 = 395 ps
4183 22:18:05.329979 CH0 RK0: MR19=808, MR18=4E45
4184 22:18:05.336205 CH0_RK0: MR19=0x808, MR18=0x4E45, DQSOSC=395, MR23=63, INC=168, DEC=112
4185 22:18:05.336282
4186 22:18:05.339933 ----->DramcWriteLeveling(PI) begin...
4187 22:18:05.340069 ==
4188 22:18:05.343136 Dram Type= 6, Freq= 0, CH_0, rank 1
4189 22:18:05.346396 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4190 22:18:05.346495 ==
4191 22:18:05.349773 Write leveling (Byte 0): 35 => 35
4192 22:18:05.352900 Write leveling (Byte 1): 29 => 29
4193 22:18:05.356212 DramcWriteLeveling(PI) end<-----
4194 22:18:05.356302
4195 22:18:05.356366 ==
4196 22:18:05.359337 Dram Type= 6, Freq= 0, CH_0, rank 1
4197 22:18:05.363149 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4198 22:18:05.363249 ==
4199 22:18:05.365783 [Gating] SW mode calibration
4200 22:18:05.372335 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4201 22:18:05.379166 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4202 22:18:05.382620 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4203 22:18:05.389095 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4204 22:18:05.392289 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4205 22:18:05.395494 0 9 12 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 1)
4206 22:18:05.402072 0 9 16 | B1->B0 | 2e2e 2323 | 0 0 | (0 0) (0 0)
4207 22:18:05.405722 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4208 22:18:05.408928 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4209 22:18:05.415182 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4210 22:18:05.418400 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4211 22:18:05.421617 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4212 22:18:05.428514 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4213 22:18:05.431793 0 10 12 | B1->B0 | 2323 3636 | 0 0 | (0 0) (0 0)
4214 22:18:05.434709 0 10 16 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
4215 22:18:05.441980 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4216 22:18:05.444587 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4217 22:18:05.448131 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4218 22:18:05.454643 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4219 22:18:05.457666 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4220 22:18:05.461164 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4221 22:18:05.467635 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4222 22:18:05.471453 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4223 22:18:05.474278 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4224 22:18:05.480802 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4225 22:18:05.483932 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4226 22:18:05.487496 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4227 22:18:05.494008 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4228 22:18:05.497603 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4229 22:18:05.500528 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4230 22:18:05.507521 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4231 22:18:05.510730 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4232 22:18:05.513884 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4233 22:18:05.520534 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4234 22:18:05.524003 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4235 22:18:05.527516 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4236 22:18:05.533552 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4237 22:18:05.537137 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4238 22:18:05.540008 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4239 22:18:05.543769 Total UI for P1: 0, mck2ui 16
4240 22:18:05.546563 best dqsien dly found for B0: ( 0, 13, 12)
4241 22:18:05.549924 Total UI for P1: 0, mck2ui 16
4242 22:18:05.553693 best dqsien dly found for B1: ( 0, 13, 14)
4243 22:18:05.556993 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4244 22:18:05.563175 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4245 22:18:05.563253
4246 22:18:05.566498 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4247 22:18:05.569636 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4248 22:18:05.572991 [Gating] SW calibration Done
4249 22:18:05.573066 ==
4250 22:18:05.576387 Dram Type= 6, Freq= 0, CH_0, rank 1
4251 22:18:05.579684 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4252 22:18:05.579769 ==
4253 22:18:05.583433 RX Vref Scan: 0
4254 22:18:05.583516
4255 22:18:05.583582 RX Vref 0 -> 0, step: 1
4256 22:18:05.583642
4257 22:18:05.586149 RX Delay -230 -> 252, step: 16
4258 22:18:05.589341 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4259 22:18:05.595934 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4260 22:18:05.599591 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4261 22:18:05.602701 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4262 22:18:05.606329 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4263 22:18:05.613179 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4264 22:18:05.615878 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4265 22:18:05.619034 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4266 22:18:05.622987 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4267 22:18:05.628846 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4268 22:18:05.632268 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4269 22:18:05.635800 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4270 22:18:05.639162 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4271 22:18:05.645575 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4272 22:18:05.648707 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4273 22:18:05.651903 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4274 22:18:05.651990 ==
4275 22:18:05.655108 Dram Type= 6, Freq= 0, CH_0, rank 1
4276 22:18:05.658691 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4277 22:18:05.662014 ==
4278 22:18:05.662101 DQS Delay:
4279 22:18:05.662186 DQS0 = 0, DQS1 = 0
4280 22:18:05.664952 DQM Delay:
4281 22:18:05.665038 DQM0 = 47, DQM1 = 34
4282 22:18:05.668861 DQ Delay:
4283 22:18:05.668947 DQ0 =41, DQ1 =49, DQ2 =49, DQ3 =49
4284 22:18:05.671641 DQ4 =49, DQ5 =33, DQ6 =57, DQ7 =49
4285 22:18:05.675028 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
4286 22:18:05.678463 DQ12 =33, DQ13 =33, DQ14 =57, DQ15 =49
4287 22:18:05.681383
4288 22:18:05.681473
4289 22:18:05.681591 ==
4290 22:18:05.684898 Dram Type= 6, Freq= 0, CH_0, rank 1
4291 22:18:05.687996 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4292 22:18:05.688138 ==
4293 22:18:05.688238
4294 22:18:05.688325
4295 22:18:05.691358 TX Vref Scan disable
4296 22:18:05.691503 == TX Byte 0 ==
4297 22:18:05.698071 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4298 22:18:05.701685 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4299 22:18:05.701824 == TX Byte 1 ==
4300 22:18:05.707988 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4301 22:18:05.711126 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4302 22:18:05.711229 ==
4303 22:18:05.714440 Dram Type= 6, Freq= 0, CH_0, rank 1
4304 22:18:05.718415 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4305 22:18:05.718502 ==
4306 22:18:05.718588
4307 22:18:05.718669
4308 22:18:05.721840 TX Vref Scan disable
4309 22:18:05.724651 == TX Byte 0 ==
4310 22:18:05.728351 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4311 22:18:05.734373 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4312 22:18:05.734461 == TX Byte 1 ==
4313 22:18:05.738012 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4314 22:18:05.744675 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4315 22:18:05.744762
4316 22:18:05.744848 [DATLAT]
4317 22:18:05.744930 Freq=600, CH0 RK1
4318 22:18:05.745010
4319 22:18:05.747801 DATLAT Default: 0x9
4320 22:18:05.751046 0, 0xFFFF, sum = 0
4321 22:18:05.751133 1, 0xFFFF, sum = 0
4322 22:18:05.754422 2, 0xFFFF, sum = 0
4323 22:18:05.754509 3, 0xFFFF, sum = 0
4324 22:18:05.758228 4, 0xFFFF, sum = 0
4325 22:18:05.758315 5, 0xFFFF, sum = 0
4326 22:18:05.760653 6, 0xFFFF, sum = 0
4327 22:18:05.760765 7, 0xFFFF, sum = 0
4328 22:18:05.763911 8, 0x0, sum = 1
4329 22:18:05.763998 9, 0x0, sum = 2
4330 22:18:05.767442 10, 0x0, sum = 3
4331 22:18:05.767529 11, 0x0, sum = 4
4332 22:18:05.767616 best_step = 9
4333 22:18:05.767697
4334 22:18:05.770517 ==
4335 22:18:05.774034 Dram Type= 6, Freq= 0, CH_0, rank 1
4336 22:18:05.777226 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4337 22:18:05.777327 ==
4338 22:18:05.777427 RX Vref Scan: 0
4339 22:18:05.777526
4340 22:18:05.780568 RX Vref 0 -> 0, step: 1
4341 22:18:05.780654
4342 22:18:05.783986 RX Delay -195 -> 252, step: 8
4343 22:18:05.790413 iDelay=197, Bit 0, Center 40 (-107 ~ 188) 296
4344 22:18:05.794037 iDelay=197, Bit 1, Center 44 (-107 ~ 196) 304
4345 22:18:05.797277 iDelay=197, Bit 2, Center 36 (-115 ~ 188) 304
4346 22:18:05.800439 iDelay=197, Bit 3, Center 40 (-107 ~ 188) 296
4347 22:18:05.806834 iDelay=197, Bit 4, Center 44 (-107 ~ 196) 304
4348 22:18:05.810154 iDelay=197, Bit 5, Center 28 (-123 ~ 180) 304
4349 22:18:05.813648 iDelay=197, Bit 6, Center 48 (-99 ~ 196) 296
4350 22:18:05.816734 iDelay=197, Bit 7, Center 44 (-107 ~ 196) 304
4351 22:18:05.820167 iDelay=197, Bit 8, Center 24 (-131 ~ 180) 312
4352 22:18:05.826644 iDelay=197, Bit 9, Center 20 (-139 ~ 180) 320
4353 22:18:05.829819 iDelay=197, Bit 10, Center 36 (-115 ~ 188) 304
4354 22:18:05.833422 iDelay=197, Bit 11, Center 28 (-123 ~ 180) 304
4355 22:18:05.836671 iDelay=197, Bit 12, Center 40 (-115 ~ 196) 312
4356 22:18:05.843269 iDelay=197, Bit 13, Center 40 (-115 ~ 196) 312
4357 22:18:05.846655 iDelay=197, Bit 14, Center 44 (-107 ~ 196) 304
4358 22:18:05.849684 iDelay=197, Bit 15, Center 40 (-115 ~ 196) 312
4359 22:18:05.849773 ==
4360 22:18:05.853303 Dram Type= 6, Freq= 0, CH_0, rank 1
4361 22:18:05.856393 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4362 22:18:05.859696 ==
4363 22:18:05.859778 DQS Delay:
4364 22:18:05.859842 DQS0 = 0, DQS1 = 0
4365 22:18:05.863172 DQM Delay:
4366 22:18:05.863253 DQM0 = 40, DQM1 = 34
4367 22:18:05.866322 DQ Delay:
4368 22:18:05.869659 DQ0 =40, DQ1 =44, DQ2 =36, DQ3 =40
4369 22:18:05.869741 DQ4 =44, DQ5 =28, DQ6 =48, DQ7 =44
4370 22:18:05.873171 DQ8 =24, DQ9 =20, DQ10 =36, DQ11 =28
4371 22:18:05.880133 DQ12 =40, DQ13 =40, DQ14 =44, DQ15 =40
4372 22:18:05.880216
4373 22:18:05.880280
4374 22:18:05.886119 [DQSOSCAuto] RK1, (LSB)MR18= 0x3d38, (MSB)MR19= 0x808, tDQSOscB0 = 399 ps tDQSOscB1 = 398 ps
4375 22:18:05.889353 CH0 RK1: MR19=808, MR18=3D38
4376 22:18:05.895950 CH0_RK1: MR19=0x808, MR18=0x3D38, DQSOSC=398, MR23=63, INC=165, DEC=110
4377 22:18:05.899771 [RxdqsGatingPostProcess] freq 600
4378 22:18:05.903401 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4379 22:18:05.906090 Pre-setting of DQS Precalculation
4380 22:18:05.912743 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4381 22:18:05.912825 ==
4382 22:18:05.915945 Dram Type= 6, Freq= 0, CH_1, rank 0
4383 22:18:05.919177 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4384 22:18:05.919293 ==
4385 22:18:05.925885 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4386 22:18:05.932343 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4387 22:18:05.935259 [CA 0] Center 35 (5~66) winsize 62
4388 22:18:05.938730 [CA 1] Center 35 (5~66) winsize 62
4389 22:18:05.942023 [CA 2] Center 35 (5~65) winsize 61
4390 22:18:05.945297 [CA 3] Center 34 (4~65) winsize 62
4391 22:18:05.948745 [CA 4] Center 34 (4~65) winsize 62
4392 22:18:05.951816 [CA 5] Center 33 (3~64) winsize 62
4393 22:18:05.951887
4394 22:18:05.955080 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4395 22:18:05.955151
4396 22:18:05.958436 [CATrainingPosCal] consider 1 rank data
4397 22:18:05.961862 u2DelayCellTimex100 = 270/100 ps
4398 22:18:05.964647 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4399 22:18:05.967993 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4400 22:18:05.971849 CA2 delay=35 (5~65),Diff = 2 PI (19 cell)
4401 22:18:05.974525 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4402 22:18:05.977865 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4403 22:18:05.984633 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4404 22:18:05.984717
4405 22:18:05.987643 CA PerBit enable=1, Macro0, CA PI delay=33
4406 22:18:05.987755
4407 22:18:05.991083 [CBTSetCACLKResult] CA Dly = 33
4408 22:18:05.991157 CS Dly: 5 (0~36)
4409 22:18:05.991226 ==
4410 22:18:05.994914 Dram Type= 6, Freq= 0, CH_1, rank 1
4411 22:18:05.998288 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4412 22:18:06.001344 ==
4413 22:18:06.004489 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4414 22:18:06.010933 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4415 22:18:06.013976 [CA 0] Center 36 (6~66) winsize 61
4416 22:18:06.017902 [CA 1] Center 36 (6~66) winsize 61
4417 22:18:06.021374 [CA 2] Center 34 (4~65) winsize 62
4418 22:18:06.024368 [CA 3] Center 34 (3~65) winsize 63
4419 22:18:06.027269 [CA 4] Center 34 (4~65) winsize 62
4420 22:18:06.030646 [CA 5] Center 34 (3~65) winsize 63
4421 22:18:06.030724
4422 22:18:06.034027 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4423 22:18:06.034101
4424 22:18:06.037655 [CATrainingPosCal] consider 2 rank data
4425 22:18:06.040765 u2DelayCellTimex100 = 270/100 ps
4426 22:18:06.043515 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4427 22:18:06.047348 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4428 22:18:06.053670 CA2 delay=35 (5~65),Diff = 2 PI (19 cell)
4429 22:18:06.056934 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4430 22:18:06.060106 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4431 22:18:06.063712 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4432 22:18:06.063786
4433 22:18:06.067065 CA PerBit enable=1, Macro0, CA PI delay=33
4434 22:18:06.067137
4435 22:18:06.070195 [CBTSetCACLKResult] CA Dly = 33
4436 22:18:06.073759 CS Dly: 5 (0~36)
4437 22:18:06.073837
4438 22:18:06.076643 ----->DramcWriteLeveling(PI) begin...
4439 22:18:06.076725 ==
4440 22:18:06.080023 Dram Type= 6, Freq= 0, CH_1, rank 0
4441 22:18:06.083032 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4442 22:18:06.083105 ==
4443 22:18:06.086422 Write leveling (Byte 0): 29 => 29
4444 22:18:06.089788 Write leveling (Byte 1): 31 => 31
4445 22:18:06.093227 DramcWriteLeveling(PI) end<-----
4446 22:18:06.093303
4447 22:18:06.093366 ==
4448 22:18:06.096739 Dram Type= 6, Freq= 0, CH_1, rank 0
4449 22:18:06.099756 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4450 22:18:06.099831 ==
4451 22:18:06.102875 [Gating] SW mode calibration
4452 22:18:06.109642 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4453 22:18:06.115915 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4454 22:18:06.119435 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4455 22:18:06.122770 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4456 22:18:06.129830 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4457 22:18:06.132777 0 9 12 | B1->B0 | 3232 3030 | 1 1 | (0 1) (0 1)
4458 22:18:06.135838 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4459 22:18:06.142487 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4460 22:18:06.145656 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4461 22:18:06.148964 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4462 22:18:06.155766 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4463 22:18:06.158933 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4464 22:18:06.161884 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4465 22:18:06.168607 0 10 12 | B1->B0 | 3030 3232 | 0 0 | (0 0) (0 0)
4466 22:18:06.171828 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4467 22:18:06.175232 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4468 22:18:06.182027 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4469 22:18:06.186016 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4470 22:18:06.188809 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4471 22:18:06.195200 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4472 22:18:06.198378 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4473 22:18:06.201957 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4474 22:18:06.208310 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4475 22:18:06.211789 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4476 22:18:06.214833 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4477 22:18:06.221589 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4478 22:18:06.225453 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4479 22:18:06.228096 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4480 22:18:06.234756 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4481 22:18:06.237947 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4482 22:18:06.241335 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4483 22:18:06.248265 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4484 22:18:06.251336 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4485 22:18:06.254523 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4486 22:18:06.261226 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4487 22:18:06.264532 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4488 22:18:06.268466 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4489 22:18:06.274833 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4490 22:18:06.277854 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4491 22:18:06.281237 Total UI for P1: 0, mck2ui 16
4492 22:18:06.284236 best dqsien dly found for B0: ( 0, 13, 12)
4493 22:18:06.287955 Total UI for P1: 0, mck2ui 16
4494 22:18:06.291014 best dqsien dly found for B1: ( 0, 13, 12)
4495 22:18:06.294517 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4496 22:18:06.297410 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4497 22:18:06.297482
4498 22:18:06.301073 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4499 22:18:06.307299 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4500 22:18:06.307375 [Gating] SW calibration Done
4501 22:18:06.307438 ==
4502 22:18:06.310644 Dram Type= 6, Freq= 0, CH_1, rank 0
4503 22:18:06.317400 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4504 22:18:06.317480 ==
4505 22:18:06.317546 RX Vref Scan: 0
4506 22:18:06.317605
4507 22:18:06.320522 RX Vref 0 -> 0, step: 1
4508 22:18:06.320593
4509 22:18:06.323879 RX Delay -230 -> 252, step: 16
4510 22:18:06.326655 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4511 22:18:06.330063 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4512 22:18:06.336855 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4513 22:18:06.340112 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4514 22:18:06.343263 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4515 22:18:06.346768 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4516 22:18:06.349795 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4517 22:18:06.356928 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4518 22:18:06.359646 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4519 22:18:06.362976 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4520 22:18:06.366437 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4521 22:18:06.373240 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4522 22:18:06.376150 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4523 22:18:06.379279 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4524 22:18:06.382893 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4525 22:18:06.389489 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4526 22:18:06.389668 ==
4527 22:18:06.392675 Dram Type= 6, Freq= 0, CH_1, rank 0
4528 22:18:06.396257 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4529 22:18:06.396344 ==
4530 22:18:06.399150 DQS Delay:
4531 22:18:06.399239 DQS0 = 0, DQS1 = 0
4532 22:18:06.399305 DQM Delay:
4533 22:18:06.402405 DQM0 = 45, DQM1 = 39
4534 22:18:06.402557 DQ Delay:
4535 22:18:06.405653 DQ0 =57, DQ1 =41, DQ2 =25, DQ3 =41
4536 22:18:06.409494 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4537 22:18:06.412550 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =33
4538 22:18:06.415805 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =41
4539 22:18:06.415920
4540 22:18:06.416017
4541 22:18:06.416147 ==
4542 22:18:06.419177 Dram Type= 6, Freq= 0, CH_1, rank 0
4543 22:18:06.425583 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4544 22:18:06.425698 ==
4545 22:18:06.425798
4546 22:18:06.425889
4547 22:18:06.425983 TX Vref Scan disable
4548 22:18:06.429154 == TX Byte 0 ==
4549 22:18:06.432714 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4550 22:18:06.436053 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4551 22:18:06.439433 == TX Byte 1 ==
4552 22:18:06.442369 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4553 22:18:06.448784 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4554 22:18:06.448880 ==
4555 22:18:06.452165 Dram Type= 6, Freq= 0, CH_1, rank 0
4556 22:18:06.455702 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4557 22:18:06.455797 ==
4558 22:18:06.455866
4559 22:18:06.455930
4560 22:18:06.458736 TX Vref Scan disable
4561 22:18:06.462227 == TX Byte 0 ==
4562 22:18:06.466036 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4563 22:18:06.468719 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4564 22:18:06.472126 == TX Byte 1 ==
4565 22:18:06.475300 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4566 22:18:06.478536 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4567 22:18:06.478651
4568 22:18:06.478769 [DATLAT]
4569 22:18:06.481821 Freq=600, CH1 RK0
4570 22:18:06.481902
4571 22:18:06.485001 DATLAT Default: 0x9
4572 22:18:06.485080 0, 0xFFFF, sum = 0
4573 22:18:06.488829 1, 0xFFFF, sum = 0
4574 22:18:06.488912 2, 0xFFFF, sum = 0
4575 22:18:06.491957 3, 0xFFFF, sum = 0
4576 22:18:06.492065 4, 0xFFFF, sum = 0
4577 22:18:06.494846 5, 0xFFFF, sum = 0
4578 22:18:06.494952 6, 0xFFFF, sum = 0
4579 22:18:06.498514 7, 0xFFFF, sum = 0
4580 22:18:06.498599 8, 0x0, sum = 1
4581 22:18:06.501826 9, 0x0, sum = 2
4582 22:18:06.501915 10, 0x0, sum = 3
4583 22:18:06.504776 11, 0x0, sum = 4
4584 22:18:06.504883 best_step = 9
4585 22:18:06.504980
4586 22:18:06.505074 ==
4587 22:18:06.508184 Dram Type= 6, Freq= 0, CH_1, rank 0
4588 22:18:06.511262 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4589 22:18:06.514747 ==
4590 22:18:06.514857 RX Vref Scan: 1
4591 22:18:06.514947
4592 22:18:06.517938 RX Vref 0 -> 0, step: 1
4593 22:18:06.518014
4594 22:18:06.521362 RX Delay -179 -> 252, step: 8
4595 22:18:06.521444
4596 22:18:06.524276 Set Vref, RX VrefLevel [Byte0]: 49
4597 22:18:06.527848 [Byte1]: 53
4598 22:18:06.527922
4599 22:18:06.531354 Final RX Vref Byte 0 = 49 to rank0
4600 22:18:06.534572 Final RX Vref Byte 1 = 53 to rank0
4601 22:18:06.537543 Final RX Vref Byte 0 = 49 to rank1
4602 22:18:06.541172 Final RX Vref Byte 1 = 53 to rank1==
4603 22:18:06.544123 Dram Type= 6, Freq= 0, CH_1, rank 0
4604 22:18:06.547370 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4605 22:18:06.547452 ==
4606 22:18:06.551069 DQS Delay:
4607 22:18:06.551174 DQS0 = 0, DQS1 = 0
4608 22:18:06.551277 DQM Delay:
4609 22:18:06.554303 DQM0 = 44, DQM1 = 38
4610 22:18:06.554390 DQ Delay:
4611 22:18:06.557938 DQ0 =52, DQ1 =40, DQ2 =36, DQ3 =44
4612 22:18:06.560950 DQ4 =40, DQ5 =52, DQ6 =52, DQ7 =40
4613 22:18:06.564490 DQ8 =24, DQ9 =28, DQ10 =36, DQ11 =32
4614 22:18:06.567378 DQ12 =48, DQ13 =44, DQ14 =48, DQ15 =44
4615 22:18:06.567464
4616 22:18:06.567564
4617 22:18:06.577101 [DQSOSCAuto] RK0, (LSB)MR18= 0x2a43, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 401 ps
4618 22:18:06.580504 CH1 RK0: MR19=808, MR18=2A43
4619 22:18:06.583863 CH1_RK0: MR19=0x808, MR18=0x2A43, DQSOSC=397, MR23=63, INC=166, DEC=110
4620 22:18:06.583961
4621 22:18:06.587425 ----->DramcWriteLeveling(PI) begin...
4622 22:18:06.590879 ==
4623 22:18:06.593535 Dram Type= 6, Freq= 0, CH_1, rank 1
4624 22:18:06.596935 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4625 22:18:06.597020 ==
4626 22:18:06.600487 Write leveling (Byte 0): 28 => 28
4627 22:18:06.603562 Write leveling (Byte 1): 28 => 28
4628 22:18:06.607359 DramcWriteLeveling(PI) end<-----
4629 22:18:06.607467
4630 22:18:06.607559 ==
4631 22:18:06.610200 Dram Type= 6, Freq= 0, CH_1, rank 1
4632 22:18:06.613631 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4633 22:18:06.613717 ==
4634 22:18:06.616538 [Gating] SW mode calibration
4635 22:18:06.623296 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4636 22:18:06.630111 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4637 22:18:06.633185 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4638 22:18:06.636655 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4639 22:18:06.643426 0 9 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
4640 22:18:06.646576 0 9 12 | B1->B0 | 3131 2e2e | 1 0 | (0 0) (0 0)
4641 22:18:06.649873 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4642 22:18:06.656458 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4643 22:18:06.660129 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4644 22:18:06.663263 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4645 22:18:06.669459 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4646 22:18:06.673296 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4647 22:18:06.676248 0 10 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
4648 22:18:06.682854 0 10 12 | B1->B0 | 3030 3c3c | 0 0 | (0 0) (0 0)
4649 22:18:06.685985 0 10 16 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
4650 22:18:06.689227 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4651 22:18:06.695824 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4652 22:18:06.699421 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4653 22:18:06.702807 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4654 22:18:06.709134 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4655 22:18:06.712314 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4656 22:18:06.715530 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4657 22:18:06.722265 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4658 22:18:06.725390 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4659 22:18:06.728635 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4660 22:18:06.735325 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4661 22:18:06.739088 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4662 22:18:06.742014 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4663 22:18:06.748425 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4664 22:18:06.752065 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4665 22:18:06.755241 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4666 22:18:06.761672 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4667 22:18:06.764902 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4668 22:18:06.768678 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4669 22:18:06.775414 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4670 22:18:06.778148 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4671 22:18:06.781606 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4672 22:18:06.788201 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4673 22:18:06.791492 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4674 22:18:06.795017 Total UI for P1: 0, mck2ui 16
4675 22:18:06.798345 best dqsien dly found for B0: ( 0, 13, 10)
4676 22:18:06.801157 Total UI for P1: 0, mck2ui 16
4677 22:18:06.804871 best dqsien dly found for B1: ( 0, 13, 12)
4678 22:18:06.808268 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4679 22:18:06.811109 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4680 22:18:06.811193
4681 22:18:06.814353 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4682 22:18:06.817799 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4683 22:18:06.820958 [Gating] SW calibration Done
4684 22:18:06.821041 ==
4685 22:18:06.824234 Dram Type= 6, Freq= 0, CH_1, rank 1
4686 22:18:06.830868 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4687 22:18:06.830953 ==
4688 22:18:06.831019 RX Vref Scan: 0
4689 22:18:06.831108
4690 22:18:06.834247 RX Vref 0 -> 0, step: 1
4691 22:18:06.834330
4692 22:18:06.837360 RX Delay -230 -> 252, step: 16
4693 22:18:06.840938 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4694 22:18:06.844482 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4695 22:18:06.847371 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4696 22:18:06.854250 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4697 22:18:06.857494 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4698 22:18:06.860226 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4699 22:18:06.863489 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4700 22:18:06.869916 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4701 22:18:06.874299 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4702 22:18:06.876467 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4703 22:18:06.879858 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4704 22:18:06.886401 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4705 22:18:06.890188 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4706 22:18:06.892887 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4707 22:18:06.896063 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4708 22:18:06.902708 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4709 22:18:06.902816 ==
4710 22:18:06.906610 Dram Type= 6, Freq= 0, CH_1, rank 1
4711 22:18:06.909931 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4712 22:18:06.910020 ==
4713 22:18:06.910127 DQS Delay:
4714 22:18:06.912984 DQS0 = 0, DQS1 = 0
4715 22:18:06.913067 DQM Delay:
4716 22:18:06.916010 DQM0 = 41, DQM1 = 39
4717 22:18:06.916100 DQ Delay:
4718 22:18:06.919286 DQ0 =41, DQ1 =33, DQ2 =33, DQ3 =41
4719 22:18:06.922611 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =41
4720 22:18:06.926200 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =33
4721 22:18:06.929626 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =49
4722 22:18:06.929709
4723 22:18:06.929775
4724 22:18:06.929835 ==
4725 22:18:06.932668 Dram Type= 6, Freq= 0, CH_1, rank 1
4726 22:18:06.939234 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4727 22:18:06.939318 ==
4728 22:18:06.939384
4729 22:18:06.939444
4730 22:18:06.939502 TX Vref Scan disable
4731 22:18:06.942482 == TX Byte 0 ==
4732 22:18:06.945852 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4733 22:18:06.952817 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4734 22:18:06.952900 == TX Byte 1 ==
4735 22:18:06.955685 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4736 22:18:06.962304 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4737 22:18:06.962386 ==
4738 22:18:06.965567 Dram Type= 6, Freq= 0, CH_1, rank 1
4739 22:18:06.968909 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4740 22:18:06.968996 ==
4741 22:18:06.969061
4742 22:18:06.969121
4743 22:18:06.972542 TX Vref Scan disable
4744 22:18:06.975312 == TX Byte 0 ==
4745 22:18:06.979004 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4746 22:18:06.981816 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4747 22:18:06.985169 == TX Byte 1 ==
4748 22:18:06.989036 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4749 22:18:06.992020 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4750 22:18:06.992139
4751 22:18:06.995042 [DATLAT]
4752 22:18:06.995149 Freq=600, CH1 RK1
4753 22:18:06.995233
4754 22:18:06.998341 DATLAT Default: 0x9
4755 22:18:06.998440 0, 0xFFFF, sum = 0
4756 22:18:07.001627 1, 0xFFFF, sum = 0
4757 22:18:07.001704 2, 0xFFFF, sum = 0
4758 22:18:07.004977 3, 0xFFFF, sum = 0
4759 22:18:07.005060 4, 0xFFFF, sum = 0
4760 22:18:07.008258 5, 0xFFFF, sum = 0
4761 22:18:07.008342 6, 0xFFFF, sum = 0
4762 22:18:07.011868 7, 0xFFFF, sum = 0
4763 22:18:07.011952 8, 0x0, sum = 1
4764 22:18:07.014838 9, 0x0, sum = 2
4765 22:18:07.014987 10, 0x0, sum = 3
4766 22:18:07.017958 11, 0x0, sum = 4
4767 22:18:07.018041 best_step = 9
4768 22:18:07.018107
4769 22:18:07.018167 ==
4770 22:18:07.021455 Dram Type= 6, Freq= 0, CH_1, rank 1
4771 22:18:07.024640 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4772 22:18:07.028145 ==
4773 22:18:07.028228 RX Vref Scan: 0
4774 22:18:07.028294
4775 22:18:07.031208 RX Vref 0 -> 0, step: 1
4776 22:18:07.031302
4777 22:18:07.035136 RX Delay -179 -> 252, step: 8
4778 22:18:07.038075 iDelay=205, Bit 0, Center 44 (-107 ~ 196) 304
4779 22:18:07.041336 iDelay=205, Bit 1, Center 40 (-115 ~ 196) 312
4780 22:18:07.047782 iDelay=205, Bit 2, Center 28 (-123 ~ 180) 304
4781 22:18:07.051190 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4782 22:18:07.054246 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4783 22:18:07.057996 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4784 22:18:07.064281 iDelay=205, Bit 6, Center 44 (-107 ~ 196) 304
4785 22:18:07.067222 iDelay=205, Bit 7, Center 36 (-115 ~ 188) 304
4786 22:18:07.070727 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4787 22:18:07.074386 iDelay=205, Bit 9, Center 28 (-123 ~ 180) 304
4788 22:18:07.080376 iDelay=205, Bit 10, Center 44 (-107 ~ 196) 304
4789 22:18:07.084027 iDelay=205, Bit 11, Center 32 (-123 ~ 188) 312
4790 22:18:07.087284 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4791 22:18:07.090260 iDelay=205, Bit 13, Center 44 (-107 ~ 196) 304
4792 22:18:07.097009 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4793 22:18:07.100410 iDelay=205, Bit 15, Center 48 (-107 ~ 204) 312
4794 22:18:07.100498 ==
4795 22:18:07.103683 Dram Type= 6, Freq= 0, CH_1, rank 1
4796 22:18:07.106623 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4797 22:18:07.106702 ==
4798 22:18:07.110332 DQS Delay:
4799 22:18:07.110407 DQS0 = 0, DQS1 = 0
4800 22:18:07.110471 DQM Delay:
4801 22:18:07.113451 DQM0 = 40, DQM1 = 38
4802 22:18:07.113529 DQ Delay:
4803 22:18:07.116731 DQ0 =44, DQ1 =40, DQ2 =28, DQ3 =40
4804 22:18:07.119839 DQ4 =44, DQ5 =48, DQ6 =44, DQ7 =36
4805 22:18:07.123033 DQ8 =24, DQ9 =28, DQ10 =44, DQ11 =32
4806 22:18:07.126775 DQ12 =44, DQ13 =44, DQ14 =44, DQ15 =48
4807 22:18:07.126856
4808 22:18:07.126921
4809 22:18:07.136478 [DQSOSCAuto] RK1, (LSB)MR18= 0x3257, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 400 ps
4810 22:18:07.139941 CH1 RK1: MR19=808, MR18=3257
4811 22:18:07.146413 CH1_RK1: MR19=0x808, MR18=0x3257, DQSOSC=393, MR23=63, INC=169, DEC=113
4812 22:18:07.146492 [RxdqsGatingPostProcess] freq 600
4813 22:18:07.152690 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4814 22:18:07.155986 Pre-setting of DQS Precalculation
4815 22:18:07.159576 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4816 22:18:07.169286 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4817 22:18:07.175617 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4818 22:18:07.175700
4819 22:18:07.175766
4820 22:18:07.179060 [Calibration Summary] 1200 Mbps
4821 22:18:07.179140 CH 0, Rank 0
4822 22:18:07.182155 SW Impedance : PASS
4823 22:18:07.185891 DUTY Scan : NO K
4824 22:18:07.185968 ZQ Calibration : PASS
4825 22:18:07.188764 Jitter Meter : NO K
4826 22:18:07.188839 CBT Training : PASS
4827 22:18:07.192385 Write leveling : PASS
4828 22:18:07.196216 RX DQS gating : PASS
4829 22:18:07.196297 RX DQ/DQS(RDDQC) : PASS
4830 22:18:07.198761 TX DQ/DQS : PASS
4831 22:18:07.202049 RX DATLAT : PASS
4832 22:18:07.202124 RX DQ/DQS(Engine): PASS
4833 22:18:07.205294 TX OE : NO K
4834 22:18:07.205367 All Pass.
4835 22:18:07.205429
4836 22:18:07.208590 CH 0, Rank 1
4837 22:18:07.208668 SW Impedance : PASS
4838 22:18:07.212133 DUTY Scan : NO K
4839 22:18:07.215112 ZQ Calibration : PASS
4840 22:18:07.215192 Jitter Meter : NO K
4841 22:18:07.218755 CBT Training : PASS
4842 22:18:07.222122 Write leveling : PASS
4843 22:18:07.222197 RX DQS gating : PASS
4844 22:18:07.225770 RX DQ/DQS(RDDQC) : PASS
4845 22:18:07.228508 TX DQ/DQS : PASS
4846 22:18:07.228582 RX DATLAT : PASS
4847 22:18:07.231755 RX DQ/DQS(Engine): PASS
4848 22:18:07.235246 TX OE : NO K
4849 22:18:07.235322 All Pass.
4850 22:18:07.235407
4851 22:18:07.235481 CH 1, Rank 0
4852 22:18:07.238774 SW Impedance : PASS
4853 22:18:07.241613 DUTY Scan : NO K
4854 22:18:07.241692 ZQ Calibration : PASS
4855 22:18:07.245364 Jitter Meter : NO K
4856 22:18:07.247968 CBT Training : PASS
4857 22:18:07.248076 Write leveling : PASS
4858 22:18:07.251673 RX DQS gating : PASS
4859 22:18:07.254760 RX DQ/DQS(RDDQC) : PASS
4860 22:18:07.254833 TX DQ/DQS : PASS
4861 22:18:07.258152 RX DATLAT : PASS
4862 22:18:07.261212 RX DQ/DQS(Engine): PASS
4863 22:18:07.261284 TX OE : NO K
4864 22:18:07.261346 All Pass.
4865 22:18:07.264940
4866 22:18:07.265011 CH 1, Rank 1
4867 22:18:07.268165 SW Impedance : PASS
4868 22:18:07.268237 DUTY Scan : NO K
4869 22:18:07.271420 ZQ Calibration : PASS
4870 22:18:07.271524 Jitter Meter : NO K
4871 22:18:07.274899 CBT Training : PASS
4872 22:18:07.278082 Write leveling : PASS
4873 22:18:07.278171 RX DQS gating : PASS
4874 22:18:07.281740 RX DQ/DQS(RDDQC) : PASS
4875 22:18:07.284600 TX DQ/DQS : PASS
4876 22:18:07.284677 RX DATLAT : PASS
4877 22:18:07.287923 RX DQ/DQS(Engine): PASS
4878 22:18:07.291218 TX OE : NO K
4879 22:18:07.291302 All Pass.
4880 22:18:07.291365
4881 22:18:07.294462 DramC Write-DBI off
4882 22:18:07.294536 PER_BANK_REFRESH: Hybrid Mode
4883 22:18:07.297944 TX_TRACKING: ON
4884 22:18:07.307798 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4885 22:18:07.310660 [FAST_K] Save calibration result to emmc
4886 22:18:07.314334 dramc_set_vcore_voltage set vcore to 662500
4887 22:18:07.314420 Read voltage for 933, 3
4888 22:18:07.317558 Vio18 = 0
4889 22:18:07.317632 Vcore = 662500
4890 22:18:07.317694 Vdram = 0
4891 22:18:07.320815 Vddq = 0
4892 22:18:07.320886 Vmddr = 0
4893 22:18:07.324373 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4894 22:18:07.330510 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4895 22:18:07.334003 MEM_TYPE=3, freq_sel=17
4896 22:18:07.337555 sv_algorithm_assistance_LP4_1600
4897 22:18:07.340542 ============ PULL DRAM RESETB DOWN ============
4898 22:18:07.343635 ========== PULL DRAM RESETB DOWN end =========
4899 22:18:07.350138 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4900 22:18:07.353884 ===================================
4901 22:18:07.353993 LPDDR4 DRAM CONFIGURATION
4902 22:18:07.357880 ===================================
4903 22:18:07.360209 EX_ROW_EN[0] = 0x0
4904 22:18:07.363611 EX_ROW_EN[1] = 0x0
4905 22:18:07.363695 LP4Y_EN = 0x0
4906 22:18:07.367074 WORK_FSP = 0x0
4907 22:18:07.367158 WL = 0x3
4908 22:18:07.369891 RL = 0x3
4909 22:18:07.370003 BL = 0x2
4910 22:18:07.373264 RPST = 0x0
4911 22:18:07.373348 RD_PRE = 0x0
4912 22:18:07.376906 WR_PRE = 0x1
4913 22:18:07.376990 WR_PST = 0x0
4914 22:18:07.379945 DBI_WR = 0x0
4915 22:18:07.380074 DBI_RD = 0x0
4916 22:18:07.383325 OTF = 0x1
4917 22:18:07.386793 ===================================
4918 22:18:07.389969 ===================================
4919 22:18:07.390054 ANA top config
4920 22:18:07.393444 ===================================
4921 22:18:07.397080 DLL_ASYNC_EN = 0
4922 22:18:07.400221 ALL_SLAVE_EN = 1
4923 22:18:07.403745 NEW_RANK_MODE = 1
4924 22:18:07.403829 DLL_IDLE_MODE = 1
4925 22:18:07.406711 LP45_APHY_COMB_EN = 1
4926 22:18:07.409513 TX_ODT_DIS = 1
4927 22:18:07.412705 NEW_8X_MODE = 1
4928 22:18:07.416410 ===================================
4929 22:18:07.419242 ===================================
4930 22:18:07.422652 data_rate = 1866
4931 22:18:07.425875 CKR = 1
4932 22:18:07.425959 DQ_P2S_RATIO = 8
4933 22:18:07.429158 ===================================
4934 22:18:07.432452 CA_P2S_RATIO = 8
4935 22:18:07.435952 DQ_CA_OPEN = 0
4936 22:18:07.439276 DQ_SEMI_OPEN = 0
4937 22:18:07.442348 CA_SEMI_OPEN = 0
4938 22:18:07.445741 CA_FULL_RATE = 0
4939 22:18:07.445829 DQ_CKDIV4_EN = 1
4940 22:18:07.448944 CA_CKDIV4_EN = 1
4941 22:18:07.452411 CA_PREDIV_EN = 0
4942 22:18:07.455652 PH8_DLY = 0
4943 22:18:07.459291 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4944 22:18:07.461916 DQ_AAMCK_DIV = 4
4945 22:18:07.461996 CA_AAMCK_DIV = 4
4946 22:18:07.465561 CA_ADMCK_DIV = 4
4947 22:18:07.468598 DQ_TRACK_CA_EN = 0
4948 22:18:07.472255 CA_PICK = 933
4949 22:18:07.475597 CA_MCKIO = 933
4950 22:18:07.478705 MCKIO_SEMI = 0
4951 22:18:07.481966 PLL_FREQ = 3732
4952 22:18:07.485266 DQ_UI_PI_RATIO = 32
4953 22:18:07.485352 CA_UI_PI_RATIO = 0
4954 22:18:07.488906 ===================================
4955 22:18:07.492152 ===================================
4956 22:18:07.495325 memory_type:LPDDR4
4957 22:18:07.498160 GP_NUM : 10
4958 22:18:07.498244 SRAM_EN : 1
4959 22:18:07.501792 MD32_EN : 0
4960 22:18:07.505016 ===================================
4961 22:18:07.508045 [ANA_INIT] >>>>>>>>>>>>>>
4962 22:18:07.511801 <<<<<< [CONFIGURE PHASE]: ANA_TX
4963 22:18:07.514637 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4964 22:18:07.518231 ===================================
4965 22:18:07.518315 data_rate = 1866,PCW = 0X8f00
4966 22:18:07.521248 ===================================
4967 22:18:07.524842 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4968 22:18:07.531207 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4969 22:18:07.538198 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4970 22:18:07.540919 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4971 22:18:07.544199 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4972 22:18:07.547853 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4973 22:18:07.551013 [ANA_INIT] flow start
4974 22:18:07.554358 [ANA_INIT] PLL >>>>>>>>
4975 22:18:07.554442 [ANA_INIT] PLL <<<<<<<<
4976 22:18:07.557900 [ANA_INIT] MIDPI >>>>>>>>
4977 22:18:07.561391 [ANA_INIT] MIDPI <<<<<<<<
4978 22:18:07.561475 [ANA_INIT] DLL >>>>>>>>
4979 22:18:07.564238 [ANA_INIT] flow end
4980 22:18:07.567389 ============ LP4 DIFF to SE enter ============
4981 22:18:07.573877 ============ LP4 DIFF to SE exit ============
4982 22:18:07.573963 [ANA_INIT] <<<<<<<<<<<<<
4983 22:18:07.577196 [Flow] Enable top DCM control >>>>>
4984 22:18:07.580878 [Flow] Enable top DCM control <<<<<
4985 22:18:07.584230 Enable DLL master slave shuffle
4986 22:18:07.590552 ==============================================================
4987 22:18:07.590636 Gating Mode config
4988 22:18:07.597348 ==============================================================
4989 22:18:07.600559 Config description:
4990 22:18:07.607279 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4991 22:18:07.616893 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4992 22:18:07.620134 SELPH_MODE 0: By rank 1: By Phase
4993 22:18:07.626847 ==============================================================
4994 22:18:07.630497 GAT_TRACK_EN = 1
4995 22:18:07.630582 RX_GATING_MODE = 2
4996 22:18:07.633272 RX_GATING_TRACK_MODE = 2
4997 22:18:07.636879 SELPH_MODE = 1
4998 22:18:07.640278 PICG_EARLY_EN = 1
4999 22:18:07.643500 VALID_LAT_VALUE = 1
5000 22:18:07.650213 ==============================================================
5001 22:18:07.653133 Enter into Gating configuration >>>>
5002 22:18:07.656304 Exit from Gating configuration <<<<
5003 22:18:07.659663 Enter into DVFS_PRE_config >>>>>
5004 22:18:07.669552 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5005 22:18:07.673224 Exit from DVFS_PRE_config <<<<<
5006 22:18:07.675978 Enter into PICG configuration >>>>
5007 22:18:07.679776 Exit from PICG configuration <<<<
5008 22:18:07.682611 [RX_INPUT] configuration >>>>>
5009 22:18:07.685849 [RX_INPUT] configuration <<<<<
5010 22:18:07.689650 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5011 22:18:07.695942 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5012 22:18:07.702495 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5013 22:18:07.709070 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5014 22:18:07.715663 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5015 22:18:07.719215 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5016 22:18:07.725876 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5017 22:18:07.728842 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5018 22:18:07.732297 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5019 22:18:07.735506 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5020 22:18:07.742103 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5021 22:18:07.745429 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5022 22:18:07.748527 ===================================
5023 22:18:07.752257 LPDDR4 DRAM CONFIGURATION
5024 22:18:07.755758 ===================================
5025 22:18:07.755843 EX_ROW_EN[0] = 0x0
5026 22:18:07.758716 EX_ROW_EN[1] = 0x0
5027 22:18:07.758800 LP4Y_EN = 0x0
5028 22:18:07.761819 WORK_FSP = 0x0
5029 22:18:07.761902 WL = 0x3
5030 22:18:07.765458 RL = 0x3
5031 22:18:07.765541 BL = 0x2
5032 22:18:07.768703 RPST = 0x0
5033 22:18:07.771675 RD_PRE = 0x0
5034 22:18:07.771758 WR_PRE = 0x1
5035 22:18:07.775436 WR_PST = 0x0
5036 22:18:07.775520 DBI_WR = 0x0
5037 22:18:07.778536 DBI_RD = 0x0
5038 22:18:07.778620 OTF = 0x1
5039 22:18:07.781646 ===================================
5040 22:18:07.784938 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5041 22:18:07.791793 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5042 22:18:07.794670 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5043 22:18:07.798462 ===================================
5044 22:18:07.801759 LPDDR4 DRAM CONFIGURATION
5045 22:18:07.804798 ===================================
5046 22:18:07.804882 EX_ROW_EN[0] = 0x10
5047 22:18:07.808139 EX_ROW_EN[1] = 0x0
5048 22:18:07.808252 LP4Y_EN = 0x0
5049 22:18:07.811622 WORK_FSP = 0x0
5050 22:18:07.811706 WL = 0x3
5051 22:18:07.814530 RL = 0x3
5052 22:18:07.817930 BL = 0x2
5053 22:18:07.818014 RPST = 0x0
5054 22:18:07.821422 RD_PRE = 0x0
5055 22:18:07.821506 WR_PRE = 0x1
5056 22:18:07.824263 WR_PST = 0x0
5057 22:18:07.824346 DBI_WR = 0x0
5058 22:18:07.827626 DBI_RD = 0x0
5059 22:18:07.827709 OTF = 0x1
5060 22:18:07.830906 ===================================
5061 22:18:07.837756 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5062 22:18:07.841575 nWR fixed to 30
5063 22:18:07.845330 [ModeRegInit_LP4] CH0 RK0
5064 22:18:07.845413 [ModeRegInit_LP4] CH0 RK1
5065 22:18:07.847930 [ModeRegInit_LP4] CH1 RK0
5066 22:18:07.851280 [ModeRegInit_LP4] CH1 RK1
5067 22:18:07.851364 match AC timing 9
5068 22:18:07.858687 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5069 22:18:07.861536 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5070 22:18:07.864714 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5071 22:18:07.871594 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5072 22:18:07.874371 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5073 22:18:07.874456 ==
5074 22:18:07.878029 Dram Type= 6, Freq= 0, CH_0, rank 0
5075 22:18:07.881151 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5076 22:18:07.881236 ==
5077 22:18:07.887773 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5078 22:18:07.894298 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5079 22:18:07.898025 [CA 0] Center 38 (8~68) winsize 61
5080 22:18:07.900793 [CA 1] Center 37 (7~68) winsize 62
5081 22:18:07.904183 [CA 2] Center 34 (4~65) winsize 62
5082 22:18:07.907911 [CA 3] Center 34 (4~65) winsize 62
5083 22:18:07.911078 [CA 4] Center 33 (3~63) winsize 61
5084 22:18:07.914138 [CA 5] Center 32 (2~63) winsize 62
5085 22:18:07.914222
5086 22:18:07.917375 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5087 22:18:07.917459
5088 22:18:07.920627 [CATrainingPosCal] consider 1 rank data
5089 22:18:07.923965 u2DelayCellTimex100 = 270/100 ps
5090 22:18:07.927348 CA0 delay=38 (8~68),Diff = 6 PI (37 cell)
5091 22:18:07.930493 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5092 22:18:07.934338 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5093 22:18:07.940777 CA3 delay=34 (4~65),Diff = 2 PI (12 cell)
5094 22:18:07.943834 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5095 22:18:07.946856 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5096 22:18:07.946941
5097 22:18:07.950405 CA PerBit enable=1, Macro0, CA PI delay=32
5098 22:18:07.950489
5099 22:18:07.954006 [CBTSetCACLKResult] CA Dly = 32
5100 22:18:07.954090 CS Dly: 5 (0~36)
5101 22:18:07.954156 ==
5102 22:18:07.957116 Dram Type= 6, Freq= 0, CH_0, rank 1
5103 22:18:07.963501 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5104 22:18:07.963587 ==
5105 22:18:07.966963 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5106 22:18:07.973489 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5107 22:18:07.977083 [CA 0] Center 37 (7~68) winsize 62
5108 22:18:07.980451 [CA 1] Center 37 (7~68) winsize 62
5109 22:18:07.983866 [CA 2] Center 34 (4~65) winsize 62
5110 22:18:07.987056 [CA 3] Center 34 (4~65) winsize 62
5111 22:18:07.989953 [CA 4] Center 33 (3~64) winsize 62
5112 22:18:07.993721 [CA 5] Center 32 (2~63) winsize 62
5113 22:18:07.993806
5114 22:18:07.996627 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5115 22:18:07.996712
5116 22:18:07.999872 [CATrainingPosCal] consider 2 rank data
5117 22:18:08.003344 u2DelayCellTimex100 = 270/100 ps
5118 22:18:08.006840 CA0 delay=38 (8~68),Diff = 6 PI (37 cell)
5119 22:18:08.013304 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5120 22:18:08.016545 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5121 22:18:08.019430 CA3 delay=34 (4~65),Diff = 2 PI (12 cell)
5122 22:18:08.022936 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5123 22:18:08.026656 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5124 22:18:08.026739
5125 22:18:08.029628 CA PerBit enable=1, Macro0, CA PI delay=32
5126 22:18:08.029712
5127 22:18:08.032987 [CBTSetCACLKResult] CA Dly = 32
5128 22:18:08.036069 CS Dly: 6 (0~39)
5129 22:18:08.036152
5130 22:18:08.039780 ----->DramcWriteLeveling(PI) begin...
5131 22:18:08.039865 ==
5132 22:18:08.042629 Dram Type= 6, Freq= 0, CH_0, rank 0
5133 22:18:08.046678 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5134 22:18:08.046777 ==
5135 22:18:08.049344 Write leveling (Byte 0): 32 => 32
5136 22:18:08.052866 Write leveling (Byte 1): 29 => 29
5137 22:18:08.056170 DramcWriteLeveling(PI) end<-----
5138 22:18:08.056254
5139 22:18:08.056319 ==
5140 22:18:08.059345 Dram Type= 6, Freq= 0, CH_0, rank 0
5141 22:18:08.062546 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5142 22:18:08.062643 ==
5143 22:18:08.066026 [Gating] SW mode calibration
5144 22:18:08.072626 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5145 22:18:08.079117 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5146 22:18:08.082643 0 14 0 | B1->B0 | 2828 3434 | 1 1 | (1 1) (1 1)
5147 22:18:08.085971 0 14 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5148 22:18:08.092101 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5149 22:18:08.095513 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5150 22:18:08.099188 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5151 22:18:08.105778 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5152 22:18:08.108888 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5153 22:18:08.111941 0 14 28 | B1->B0 | 3434 2b2b | 1 0 | (1 0) (0 0)
5154 22:18:08.118729 0 15 0 | B1->B0 | 3030 2525 | 1 0 | (1 0) (0 0)
5155 22:18:08.122015 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
5156 22:18:08.125219 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5157 22:18:08.131878 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5158 22:18:08.135128 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5159 22:18:08.138590 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5160 22:18:08.144826 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5161 22:18:08.148918 0 15 28 | B1->B0 | 2323 3a3a | 0 0 | (0 0) (0 0)
5162 22:18:08.151605 1 0 0 | B1->B0 | 3737 4646 | 1 0 | (0 0) (0 0)
5163 22:18:08.158006 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5164 22:18:08.161217 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5165 22:18:08.164573 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5166 22:18:08.171493 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5167 22:18:08.174867 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5168 22:18:08.181159 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5169 22:18:08.184450 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5170 22:18:08.188670 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5171 22:18:08.194209 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5172 22:18:08.197548 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5173 22:18:08.200976 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5174 22:18:08.207087 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5175 22:18:08.210400 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5176 22:18:08.213960 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5177 22:18:08.220550 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5178 22:18:08.224472 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5179 22:18:08.227153 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5180 22:18:08.233752 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5181 22:18:08.237148 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5182 22:18:08.240222 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5183 22:18:08.246906 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5184 22:18:08.250362 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5185 22:18:08.253415 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5186 22:18:08.259924 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
5187 22:18:08.260008 Total UI for P1: 0, mck2ui 16
5188 22:18:08.266355 best dqsien dly found for B0: ( 1, 2, 28)
5189 22:18:08.269841 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5190 22:18:08.272959 Total UI for P1: 0, mck2ui 16
5191 22:18:08.276701 best dqsien dly found for B1: ( 1, 3, 2)
5192 22:18:08.279811 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5193 22:18:08.282705 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5194 22:18:08.282788
5195 22:18:08.286306 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5196 22:18:08.290768 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5197 22:18:08.293012 [Gating] SW calibration Done
5198 22:18:08.293096 ==
5199 22:18:08.296027 Dram Type= 6, Freq= 0, CH_0, rank 0
5200 22:18:08.299225 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5201 22:18:08.302795 ==
5202 22:18:08.302880 RX Vref Scan: 0
5203 22:18:08.302946
5204 22:18:08.305969 RX Vref 0 -> 0, step: 1
5205 22:18:08.306053
5206 22:18:08.309110 RX Delay -80 -> 252, step: 8
5207 22:18:08.312334 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5208 22:18:08.315829 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5209 22:18:08.319388 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5210 22:18:08.322398 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5211 22:18:08.325725 iDelay=208, Bit 4, Center 103 (8 ~ 199) 192
5212 22:18:08.332432 iDelay=208, Bit 5, Center 91 (-8 ~ 191) 200
5213 22:18:08.335450 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5214 22:18:08.338945 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5215 22:18:08.342363 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5216 22:18:08.345610 iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184
5217 22:18:08.352139 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5218 22:18:08.355203 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5219 22:18:08.358503 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5220 22:18:08.361814 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5221 22:18:08.364973 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5222 22:18:08.368359 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5223 22:18:08.371864 ==
5224 22:18:08.375635 Dram Type= 6, Freq= 0, CH_0, rank 0
5225 22:18:08.378459 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5226 22:18:08.378543 ==
5227 22:18:08.378609 DQS Delay:
5228 22:18:08.381559 DQS0 = 0, DQS1 = 0
5229 22:18:08.381643 DQM Delay:
5230 22:18:08.384892 DQM0 = 99, DQM1 = 88
5231 22:18:08.384976 DQ Delay:
5232 22:18:08.387918 DQ0 =99, DQ1 =99, DQ2 =95, DQ3 =95
5233 22:18:08.391519 DQ4 =103, DQ5 =91, DQ6 =107, DQ7 =107
5234 22:18:08.394733 DQ8 =83, DQ9 =75, DQ10 =87, DQ11 =83
5235 22:18:08.398554 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5236 22:18:08.398637
5237 22:18:08.398702
5238 22:18:08.398761 ==
5239 22:18:08.401457 Dram Type= 6, Freq= 0, CH_0, rank 0
5240 22:18:08.404941 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5241 22:18:08.405026 ==
5242 22:18:08.405092
5243 22:18:08.407742
5244 22:18:08.407825 TX Vref Scan disable
5245 22:18:08.411156 == TX Byte 0 ==
5246 22:18:08.414752 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5247 22:18:08.418041 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5248 22:18:08.421098 == TX Byte 1 ==
5249 22:18:08.424701 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5250 22:18:08.427755 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5251 22:18:08.427839 ==
5252 22:18:08.430767 Dram Type= 6, Freq= 0, CH_0, rank 0
5253 22:18:08.437764 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5254 22:18:08.437848 ==
5255 22:18:08.437914
5256 22:18:08.437975
5257 22:18:08.441159 TX Vref Scan disable
5258 22:18:08.441242 == TX Byte 0 ==
5259 22:18:08.447709 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5260 22:18:08.450765 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5261 22:18:08.450849 == TX Byte 1 ==
5262 22:18:08.457326 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5263 22:18:08.460882 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5264 22:18:08.460965
5265 22:18:08.461032 [DATLAT]
5266 22:18:08.464182 Freq=933, CH0 RK0
5267 22:18:08.464266
5268 22:18:08.464331 DATLAT Default: 0xd
5269 22:18:08.466895 0, 0xFFFF, sum = 0
5270 22:18:08.466980 1, 0xFFFF, sum = 0
5271 22:18:08.470112 2, 0xFFFF, sum = 0
5272 22:18:08.470197 3, 0xFFFF, sum = 0
5273 22:18:08.473885 4, 0xFFFF, sum = 0
5274 22:18:08.476803 5, 0xFFFF, sum = 0
5275 22:18:08.476888 6, 0xFFFF, sum = 0
5276 22:18:08.480385 7, 0xFFFF, sum = 0
5277 22:18:08.480469 8, 0xFFFF, sum = 0
5278 22:18:08.483462 9, 0xFFFF, sum = 0
5279 22:18:08.483574 10, 0x0, sum = 1
5280 22:18:08.486574 11, 0x0, sum = 2
5281 22:18:08.486659 12, 0x0, sum = 3
5282 22:18:08.490163 13, 0x0, sum = 4
5283 22:18:08.490246 best_step = 11
5284 22:18:08.490312
5285 22:18:08.490372 ==
5286 22:18:08.493610 Dram Type= 6, Freq= 0, CH_0, rank 0
5287 22:18:08.496674 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5288 22:18:08.496759 ==
5289 22:18:08.499802 RX Vref Scan: 1
5290 22:18:08.499886
5291 22:18:08.502999 RX Vref 0 -> 0, step: 1
5292 22:18:08.503082
5293 22:18:08.503148 RX Delay -61 -> 252, step: 4
5294 22:18:08.503208
5295 22:18:08.506347 Set Vref, RX VrefLevel [Byte0]: 51
5296 22:18:08.509755 [Byte1]: 50
5297 22:18:08.514345
5298 22:18:08.514428 Final RX Vref Byte 0 = 51 to rank0
5299 22:18:08.517864 Final RX Vref Byte 1 = 50 to rank0
5300 22:18:08.521399 Final RX Vref Byte 0 = 51 to rank1
5301 22:18:08.525021 Final RX Vref Byte 1 = 50 to rank1==
5302 22:18:08.527909 Dram Type= 6, Freq= 0, CH_0, rank 0
5303 22:18:08.534391 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5304 22:18:08.534486 ==
5305 22:18:08.534556 DQS Delay:
5306 22:18:08.537222 DQS0 = 0, DQS1 = 0
5307 22:18:08.537312 DQM Delay:
5308 22:18:08.537406 DQM0 = 99, DQM1 = 87
5309 22:18:08.540705 DQ Delay:
5310 22:18:08.544674 DQ0 =100, DQ1 =102, DQ2 =94, DQ3 =96
5311 22:18:08.547382 DQ4 =100, DQ5 =92, DQ6 =108, DQ7 =106
5312 22:18:08.550921 DQ8 =80, DQ9 =74, DQ10 =88, DQ11 =82
5313 22:18:08.554338 DQ12 =94, DQ13 =90, DQ14 =98, DQ15 =94
5314 22:18:08.554421
5315 22:18:08.554486
5316 22:18:08.560573 [DQSOSCAuto] RK0, (LSB)MR18= 0x1813, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 414 ps
5317 22:18:08.564059 CH0 RK0: MR19=505, MR18=1813
5318 22:18:08.570286 CH0_RK0: MR19=0x505, MR18=0x1813, DQSOSC=414, MR23=63, INC=63, DEC=42
5319 22:18:08.570369
5320 22:18:08.573894 ----->DramcWriteLeveling(PI) begin...
5321 22:18:08.574005 ==
5322 22:18:08.576901 Dram Type= 6, Freq= 0, CH_0, rank 1
5323 22:18:08.581438 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5324 22:18:08.583682 ==
5325 22:18:08.583765 Write leveling (Byte 0): 33 => 33
5326 22:18:08.586879 Write leveling (Byte 1): 26 => 26
5327 22:18:08.590749 DramcWriteLeveling(PI) end<-----
5328 22:18:08.590835
5329 22:18:08.590901 ==
5330 22:18:08.593326 Dram Type= 6, Freq= 0, CH_0, rank 1
5331 22:18:08.600355 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5332 22:18:08.600439 ==
5333 22:18:08.603306 [Gating] SW mode calibration
5334 22:18:08.609999 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5335 22:18:08.613288 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5336 22:18:08.619482 0 14 0 | B1->B0 | 2a2a 3333 | 1 1 | (1 1) (1 1)
5337 22:18:08.622834 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5338 22:18:08.626326 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5339 22:18:08.632711 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5340 22:18:08.636244 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5341 22:18:08.639401 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5342 22:18:08.646078 0 14 24 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
5343 22:18:08.649292 0 14 28 | B1->B0 | 3434 2929 | 0 1 | (0 0) (1 0)
5344 22:18:08.652888 0 15 0 | B1->B0 | 3030 2525 | 0 0 | (1 1) (0 0)
5345 22:18:08.659840 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5346 22:18:08.662487 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5347 22:18:08.666058 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5348 22:18:08.672840 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5349 22:18:08.675888 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5350 22:18:08.678904 0 15 24 | B1->B0 | 2323 2d2d | 0 1 | (0 0) (0 0)
5351 22:18:08.685375 0 15 28 | B1->B0 | 2c2c 3f3f | 0 0 | (1 1) (0 0)
5352 22:18:08.688546 1 0 0 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
5353 22:18:08.691844 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5354 22:18:08.699267 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5355 22:18:08.702014 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5356 22:18:08.705694 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5357 22:18:08.711634 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5358 22:18:08.714941 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5359 22:18:08.718369 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5360 22:18:08.724811 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5361 22:18:08.727964 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5362 22:18:08.731721 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5363 22:18:08.738025 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5364 22:18:08.741353 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5365 22:18:08.745093 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5366 22:18:08.751091 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5367 22:18:08.754586 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5368 22:18:08.757895 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5369 22:18:08.764570 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5370 22:18:08.767976 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5371 22:18:08.771018 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5372 22:18:08.777585 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5373 22:18:08.781135 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5374 22:18:08.784076 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5375 22:18:08.790751 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5376 22:18:08.794275 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5377 22:18:08.797299 Total UI for P1: 0, mck2ui 16
5378 22:18:08.800695 best dqsien dly found for B0: ( 1, 2, 28)
5379 22:18:08.804013 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5380 22:18:08.807496 Total UI for P1: 0, mck2ui 16
5381 22:18:08.810523 best dqsien dly found for B1: ( 1, 2, 30)
5382 22:18:08.813649 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5383 22:18:08.817506 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5384 22:18:08.820575
5385 22:18:08.823657 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5386 22:18:08.827057 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5387 22:18:08.830507 [Gating] SW calibration Done
5388 22:18:08.830589 ==
5389 22:18:08.833579 Dram Type= 6, Freq= 0, CH_0, rank 1
5390 22:18:08.836729 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5391 22:18:08.836811 ==
5392 22:18:08.836876 RX Vref Scan: 0
5393 22:18:08.840298
5394 22:18:08.840379 RX Vref 0 -> 0, step: 1
5395 22:18:08.840444
5396 22:18:08.843114 RX Delay -80 -> 252, step: 8
5397 22:18:08.846438 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5398 22:18:08.850251 iDelay=200, Bit 1, Center 99 (0 ~ 199) 200
5399 22:18:08.856484 iDelay=200, Bit 2, Center 95 (0 ~ 191) 192
5400 22:18:08.860066 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5401 22:18:08.863420 iDelay=200, Bit 4, Center 99 (0 ~ 199) 200
5402 22:18:08.866914 iDelay=200, Bit 5, Center 87 (-8 ~ 183) 192
5403 22:18:08.869804 iDelay=200, Bit 6, Center 107 (16 ~ 199) 184
5404 22:18:08.873436 iDelay=200, Bit 7, Center 107 (16 ~ 199) 184
5405 22:18:08.879498 iDelay=200, Bit 8, Center 83 (-8 ~ 175) 184
5406 22:18:08.882772 iDelay=200, Bit 9, Center 75 (-16 ~ 167) 184
5407 22:18:08.886088 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5408 22:18:08.889832 iDelay=200, Bit 11, Center 83 (-8 ~ 175) 184
5409 22:18:08.892785 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5410 22:18:08.899801 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5411 22:18:08.902478 iDelay=200, Bit 14, Center 99 (8 ~ 191) 184
5412 22:18:08.905973 iDelay=200, Bit 15, Center 91 (0 ~ 183) 184
5413 22:18:08.906057 ==
5414 22:18:08.909358 Dram Type= 6, Freq= 0, CH_0, rank 1
5415 22:18:08.912345 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5416 22:18:08.912430 ==
5417 22:18:08.915783 DQS Delay:
5418 22:18:08.915867 DQS0 = 0, DQS1 = 0
5419 22:18:08.918946 DQM Delay:
5420 22:18:08.919029 DQM0 = 98, DQM1 = 88
5421 22:18:08.919094 DQ Delay:
5422 22:18:08.922592 DQ0 =95, DQ1 =99, DQ2 =95, DQ3 =95
5423 22:18:08.925717 DQ4 =99, DQ5 =87, DQ6 =107, DQ7 =107
5424 22:18:08.928933 DQ8 =83, DQ9 =75, DQ10 =87, DQ11 =83
5425 22:18:08.932085 DQ12 =95, DQ13 =95, DQ14 =99, DQ15 =91
5426 22:18:08.932168
5427 22:18:08.932234
5428 22:18:08.935516 ==
5429 22:18:08.938759 Dram Type= 6, Freq= 0, CH_0, rank 1
5430 22:18:08.942096 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5431 22:18:08.942180 ==
5432 22:18:08.942246
5433 22:18:08.942308
5434 22:18:08.945521 TX Vref Scan disable
5435 22:18:08.945604 == TX Byte 0 ==
5436 22:18:08.952290 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5437 22:18:08.955373 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5438 22:18:08.955456 == TX Byte 1 ==
5439 22:18:08.961860 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5440 22:18:08.965133 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5441 22:18:08.965216 ==
5442 22:18:08.968413 Dram Type= 6, Freq= 0, CH_0, rank 1
5443 22:18:08.971720 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5444 22:18:08.971804 ==
5445 22:18:08.971871
5446 22:18:08.971932
5447 22:18:08.975364 TX Vref Scan disable
5448 22:18:08.978162 == TX Byte 0 ==
5449 22:18:08.981700 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5450 22:18:08.984877 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5451 22:18:08.988480 == TX Byte 1 ==
5452 22:18:08.991360 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5453 22:18:08.994665 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5454 22:18:08.994748
5455 22:18:08.998069 [DATLAT]
5456 22:18:08.998182 Freq=933, CH0 RK1
5457 22:18:08.998252
5458 22:18:09.001231 DATLAT Default: 0xb
5459 22:18:09.001313 0, 0xFFFF, sum = 0
5460 22:18:09.004940 1, 0xFFFF, sum = 0
5461 22:18:09.005024 2, 0xFFFF, sum = 0
5462 22:18:09.008155 3, 0xFFFF, sum = 0
5463 22:18:09.008239 4, 0xFFFF, sum = 0
5464 22:18:09.011354 5, 0xFFFF, sum = 0
5465 22:18:09.011437 6, 0xFFFF, sum = 0
5466 22:18:09.014364 7, 0xFFFF, sum = 0
5467 22:18:09.017802 8, 0xFFFF, sum = 0
5468 22:18:09.017887 9, 0xFFFF, sum = 0
5469 22:18:09.020992 10, 0x0, sum = 1
5470 22:18:09.021077 11, 0x0, sum = 2
5471 22:18:09.021144 12, 0x0, sum = 3
5472 22:18:09.024352 13, 0x0, sum = 4
5473 22:18:09.024436 best_step = 11
5474 22:18:09.024502
5475 22:18:09.027931 ==
5476 22:18:09.028065 Dram Type= 6, Freq= 0, CH_0, rank 1
5477 22:18:09.034189 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5478 22:18:09.034299 ==
5479 22:18:09.034395 RX Vref Scan: 0
5480 22:18:09.034460
5481 22:18:09.037692 RX Vref 0 -> 0, step: 1
5482 22:18:09.037776
5483 22:18:09.040813 RX Delay -61 -> 252, step: 4
5484 22:18:09.044221 iDelay=195, Bit 0, Center 96 (11 ~ 182) 172
5485 22:18:09.050827 iDelay=195, Bit 1, Center 98 (7 ~ 190) 184
5486 22:18:09.054357 iDelay=195, Bit 2, Center 94 (3 ~ 186) 184
5487 22:18:09.057747 iDelay=195, Bit 3, Center 96 (7 ~ 186) 180
5488 22:18:09.060880 iDelay=195, Bit 4, Center 100 (7 ~ 194) 188
5489 22:18:09.064410 iDelay=195, Bit 5, Center 90 (3 ~ 178) 176
5490 22:18:09.067724 iDelay=195, Bit 6, Center 104 (15 ~ 194) 180
5491 22:18:09.073983 iDelay=195, Bit 7, Center 104 (15 ~ 194) 180
5492 22:18:09.077145 iDelay=195, Bit 8, Center 80 (-9 ~ 170) 180
5493 22:18:09.080364 iDelay=195, Bit 9, Center 76 (-13 ~ 166) 180
5494 22:18:09.083898 iDelay=195, Bit 10, Center 90 (3 ~ 178) 176
5495 22:18:09.086942 iDelay=195, Bit 11, Center 82 (-5 ~ 170) 176
5496 22:18:09.093823 iDelay=195, Bit 12, Center 94 (7 ~ 182) 176
5497 22:18:09.097043 iDelay=195, Bit 13, Center 92 (3 ~ 182) 180
5498 22:18:09.100385 iDelay=195, Bit 14, Center 98 (7 ~ 190) 184
5499 22:18:09.103218 iDelay=195, Bit 15, Center 94 (3 ~ 186) 184
5500 22:18:09.103301 ==
5501 22:18:09.106703 Dram Type= 6, Freq= 0, CH_0, rank 1
5502 22:18:09.109898 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5503 22:18:09.113555 ==
5504 22:18:09.113638 DQS Delay:
5505 22:18:09.113703 DQS0 = 0, DQS1 = 0
5506 22:18:09.116504 DQM Delay:
5507 22:18:09.116586 DQM0 = 97, DQM1 = 88
5508 22:18:09.119777 DQ Delay:
5509 22:18:09.123060 DQ0 =96, DQ1 =98, DQ2 =94, DQ3 =96
5510 22:18:09.126234 DQ4 =100, DQ5 =90, DQ6 =104, DQ7 =104
5511 22:18:09.129587 DQ8 =80, DQ9 =76, DQ10 =90, DQ11 =82
5512 22:18:09.132991 DQ12 =94, DQ13 =92, DQ14 =98, DQ15 =94
5513 22:18:09.133099
5514 22:18:09.133185
5515 22:18:09.139607 [DQSOSCAuto] RK1, (LSB)MR18= 0x1714, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 414 ps
5516 22:18:09.142944 CH0 RK1: MR19=505, MR18=1714
5517 22:18:09.149531 CH0_RK1: MR19=0x505, MR18=0x1714, DQSOSC=414, MR23=63, INC=63, DEC=42
5518 22:18:09.152677 [RxdqsGatingPostProcess] freq 933
5519 22:18:09.155828 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5520 22:18:09.159387 best DQS0 dly(2T, 0.5T) = (0, 10)
5521 22:18:09.162762 best DQS1 dly(2T, 0.5T) = (0, 11)
5522 22:18:09.165961 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5523 22:18:09.168875 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5524 22:18:09.172236 best DQS0 dly(2T, 0.5T) = (0, 10)
5525 22:18:09.175801 best DQS1 dly(2T, 0.5T) = (0, 10)
5526 22:18:09.179040 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5527 22:18:09.182700 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5528 22:18:09.185372 Pre-setting of DQS Precalculation
5529 22:18:09.191971 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5530 22:18:09.192118 ==
5531 22:18:09.195205 Dram Type= 6, Freq= 0, CH_1, rank 0
5532 22:18:09.198595 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5533 22:18:09.198679 ==
5534 22:18:09.205490 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5535 22:18:09.208515 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5536 22:18:09.212709 [CA 0] Center 36 (6~67) winsize 62
5537 22:18:09.215681 [CA 1] Center 36 (6~67) winsize 62
5538 22:18:09.219287 [CA 2] Center 35 (5~65) winsize 61
5539 22:18:09.222655 [CA 3] Center 34 (4~64) winsize 61
5540 22:18:09.225957 [CA 4] Center 34 (4~65) winsize 62
5541 22:18:09.228807 [CA 5] Center 34 (4~64) winsize 61
5542 22:18:09.228889
5543 22:18:09.232167 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5544 22:18:09.232271
5545 22:18:09.235668 [CATrainingPosCal] consider 1 rank data
5546 22:18:09.238855 u2DelayCellTimex100 = 270/100 ps
5547 22:18:09.242254 CA0 delay=36 (6~67),Diff = 2 PI (12 cell)
5548 22:18:09.248638 CA1 delay=36 (6~67),Diff = 2 PI (12 cell)
5549 22:18:09.252290 CA2 delay=35 (5~65),Diff = 1 PI (6 cell)
5550 22:18:09.255159 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
5551 22:18:09.258480 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5552 22:18:09.262217 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5553 22:18:09.262300
5554 22:18:09.265468 CA PerBit enable=1, Macro0, CA PI delay=34
5555 22:18:09.265550
5556 22:18:09.268639 [CBTSetCACLKResult] CA Dly = 34
5557 22:18:09.271673 CS Dly: 5 (0~36)
5558 22:18:09.271756 ==
5559 22:18:09.275009 Dram Type= 6, Freq= 0, CH_1, rank 1
5560 22:18:09.278842 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5561 22:18:09.278926 ==
5562 22:18:09.285035 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5563 22:18:09.288439 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5564 22:18:09.292459 [CA 0] Center 36 (6~67) winsize 62
5565 22:18:09.295753 [CA 1] Center 36 (6~67) winsize 62
5566 22:18:09.298951 [CA 2] Center 34 (4~65) winsize 62
5567 22:18:09.302237 [CA 3] Center 34 (3~65) winsize 63
5568 22:18:09.305581 [CA 4] Center 34 (4~65) winsize 62
5569 22:18:09.309230 [CA 5] Center 33 (3~64) winsize 62
5570 22:18:09.309313
5571 22:18:09.312298 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5572 22:18:09.312381
5573 22:18:09.315448 [CATrainingPosCal] consider 2 rank data
5574 22:18:09.318653 u2DelayCellTimex100 = 270/100 ps
5575 22:18:09.322086 CA0 delay=36 (6~67),Diff = 2 PI (12 cell)
5576 22:18:09.328667 CA1 delay=36 (6~67),Diff = 2 PI (12 cell)
5577 22:18:09.331767 CA2 delay=35 (5~65),Diff = 1 PI (6 cell)
5578 22:18:09.335374 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
5579 22:18:09.338424 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5580 22:18:09.341972 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5581 22:18:09.342055
5582 22:18:09.344992 CA PerBit enable=1, Macro0, CA PI delay=34
5583 22:18:09.345075
5584 22:18:09.348346 [CBTSetCACLKResult] CA Dly = 34
5585 22:18:09.352000 CS Dly: 6 (0~38)
5586 22:18:09.352120
5587 22:18:09.355279 ----->DramcWriteLeveling(PI) begin...
5588 22:18:09.355363 ==
5589 22:18:09.358873 Dram Type= 6, Freq= 0, CH_1, rank 0
5590 22:18:09.361753 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5591 22:18:09.361836 ==
5592 22:18:09.364841 Write leveling (Byte 0): 26 => 26
5593 22:18:09.368327 Write leveling (Byte 1): 29 => 29
5594 22:18:09.371727 DramcWriteLeveling(PI) end<-----
5595 22:18:09.371809
5596 22:18:09.371874 ==
5597 22:18:09.375123 Dram Type= 6, Freq= 0, CH_1, rank 0
5598 22:18:09.378217 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5599 22:18:09.378301 ==
5600 22:18:09.381385 [Gating] SW mode calibration
5601 22:18:09.387903 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5602 22:18:09.394687 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5603 22:18:09.397918 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5604 22:18:09.404065 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5605 22:18:09.407920 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5606 22:18:09.411111 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5607 22:18:09.417492 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5608 22:18:09.420850 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5609 22:18:09.423776 0 14 24 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 1)
5610 22:18:09.430602 0 14 28 | B1->B0 | 2e2e 2626 | 0 0 | (0 0) (0 0)
5611 22:18:09.434153 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5612 22:18:09.437236 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5613 22:18:09.444471 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5614 22:18:09.447554 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5615 22:18:09.450308 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5616 22:18:09.457373 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5617 22:18:09.461286 0 15 24 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
5618 22:18:09.463331 0 15 28 | B1->B0 | 3636 3e3e | 0 0 | (0 0) (0 0)
5619 22:18:09.470194 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5620 22:18:09.473395 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5621 22:18:09.476682 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5622 22:18:09.483283 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5623 22:18:09.486637 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5624 22:18:09.489765 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5625 22:18:09.496482 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5626 22:18:09.499905 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5627 22:18:09.503318 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5628 22:18:09.509910 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5629 22:18:09.512646 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5630 22:18:09.516259 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5631 22:18:09.522902 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5632 22:18:09.526122 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5633 22:18:09.529318 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5634 22:18:09.536287 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5635 22:18:09.539038 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5636 22:18:09.542471 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5637 22:18:09.549066 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5638 22:18:09.552619 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5639 22:18:09.555408 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5640 22:18:09.562279 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5641 22:18:09.565539 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5642 22:18:09.568592 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5643 22:18:09.571783 Total UI for P1: 0, mck2ui 16
5644 22:18:09.575269 best dqsien dly found for B1: ( 1, 2, 24)
5645 22:18:09.582212 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5646 22:18:09.582300 Total UI for P1: 0, mck2ui 16
5647 22:18:09.588478 best dqsien dly found for B0: ( 1, 2, 26)
5648 22:18:09.591929 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5649 22:18:09.595426 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5650 22:18:09.595511
5651 22:18:09.598155 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5652 22:18:09.601602 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5653 22:18:09.604892 [Gating] SW calibration Done
5654 22:18:09.604977 ==
5655 22:18:09.608350 Dram Type= 6, Freq= 0, CH_1, rank 0
5656 22:18:09.611969 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5657 22:18:09.612114 ==
5658 22:18:09.614837 RX Vref Scan: 0
5659 22:18:09.614921
5660 22:18:09.615003 RX Vref 0 -> 0, step: 1
5661 22:18:09.615082
5662 22:18:09.618279 RX Delay -80 -> 252, step: 8
5663 22:18:09.624703 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5664 22:18:09.628228 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5665 22:18:09.631262 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5666 22:18:09.634923 iDelay=208, Bit 3, Center 99 (0 ~ 199) 200
5667 22:18:09.637941 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5668 22:18:09.641520 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5669 22:18:09.647932 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5670 22:18:09.651252 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5671 22:18:09.654098 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5672 22:18:09.657688 iDelay=208, Bit 9, Center 83 (-16 ~ 183) 200
5673 22:18:09.660849 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5674 22:18:09.664207 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5675 22:18:09.670978 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5676 22:18:09.674413 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5677 22:18:09.677392 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5678 22:18:09.680651 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5679 22:18:09.680735 ==
5680 22:18:09.684359 Dram Type= 6, Freq= 0, CH_1, rank 0
5681 22:18:09.690605 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5682 22:18:09.690691 ==
5683 22:18:09.690775 DQS Delay:
5684 22:18:09.693726 DQS0 = 0, DQS1 = 0
5685 22:18:09.693810 DQM Delay:
5686 22:18:09.693892 DQM0 = 98, DQM1 = 93
5687 22:18:09.696974 DQ Delay:
5688 22:18:09.700535 DQ0 =103, DQ1 =91, DQ2 =87, DQ3 =99
5689 22:18:09.703803 DQ4 =95, DQ5 =107, DQ6 =107, DQ7 =95
5690 22:18:09.706703 DQ8 =79, DQ9 =83, DQ10 =95, DQ11 =87
5691 22:18:09.710084 DQ12 =103, DQ13 =103, DQ14 =99, DQ15 =99
5692 22:18:09.710169
5693 22:18:09.710252
5694 22:18:09.710330 ==
5695 22:18:09.713496 Dram Type= 6, Freq= 0, CH_1, rank 0
5696 22:18:09.716867 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5697 22:18:09.716951 ==
5698 22:18:09.717035
5699 22:18:09.717113
5700 22:18:09.719974 TX Vref Scan disable
5701 22:18:09.723210 == TX Byte 0 ==
5702 22:18:09.726531 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5703 22:18:09.729763 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5704 22:18:09.733228 == TX Byte 1 ==
5705 22:18:09.736717 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5706 22:18:09.740147 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5707 22:18:09.740231 ==
5708 22:18:09.742981 Dram Type= 6, Freq= 0, CH_1, rank 0
5709 22:18:09.749370 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5710 22:18:09.749455 ==
5711 22:18:09.749556
5712 22:18:09.749657
5713 22:18:09.749728 TX Vref Scan disable
5714 22:18:09.753557 == TX Byte 0 ==
5715 22:18:09.757626 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5716 22:18:09.760503 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5717 22:18:09.764169 == TX Byte 1 ==
5718 22:18:09.766935 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5719 22:18:09.773513 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5720 22:18:09.773595
5721 22:18:09.773660 [DATLAT]
5722 22:18:09.773718 Freq=933, CH1 RK0
5723 22:18:09.773776
5724 22:18:09.777093 DATLAT Default: 0xd
5725 22:18:09.777176 0, 0xFFFF, sum = 0
5726 22:18:09.780715 1, 0xFFFF, sum = 0
5727 22:18:09.780799 2, 0xFFFF, sum = 0
5728 22:18:09.784077 3, 0xFFFF, sum = 0
5729 22:18:09.787122 4, 0xFFFF, sum = 0
5730 22:18:09.787215 5, 0xFFFF, sum = 0
5731 22:18:09.790208 6, 0xFFFF, sum = 0
5732 22:18:09.790292 7, 0xFFFF, sum = 0
5733 22:18:09.793433 8, 0xFFFF, sum = 0
5734 22:18:09.793517 9, 0xFFFF, sum = 0
5735 22:18:09.796860 10, 0x0, sum = 1
5736 22:18:09.796944 11, 0x0, sum = 2
5737 22:18:09.799991 12, 0x0, sum = 3
5738 22:18:09.800127 13, 0x0, sum = 4
5739 22:18:09.800194 best_step = 11
5740 22:18:09.803270
5741 22:18:09.803352 ==
5742 22:18:09.806326 Dram Type= 6, Freq= 0, CH_1, rank 0
5743 22:18:09.810258 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5744 22:18:09.810342 ==
5745 22:18:09.810407 RX Vref Scan: 1
5746 22:18:09.810466
5747 22:18:09.813130 RX Vref 0 -> 0, step: 1
5748 22:18:09.813212
5749 22:18:09.816220 RX Delay -61 -> 252, step: 4
5750 22:18:09.816303
5751 22:18:09.819781 Set Vref, RX VrefLevel [Byte0]: 49
5752 22:18:09.823235 [Byte1]: 53
5753 22:18:09.826197
5754 22:18:09.826279 Final RX Vref Byte 0 = 49 to rank0
5755 22:18:09.829364 Final RX Vref Byte 1 = 53 to rank0
5756 22:18:09.833155 Final RX Vref Byte 0 = 49 to rank1
5757 22:18:09.836535 Final RX Vref Byte 1 = 53 to rank1==
5758 22:18:09.839396 Dram Type= 6, Freq= 0, CH_1, rank 0
5759 22:18:09.845895 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5760 22:18:09.845978 ==
5761 22:18:09.846044 DQS Delay:
5762 22:18:09.849694 DQS0 = 0, DQS1 = 0
5763 22:18:09.849777 DQM Delay:
5764 22:18:09.849842 DQM0 = 98, DQM1 = 95
5765 22:18:09.852435 DQ Delay:
5766 22:18:09.856195 DQ0 =104, DQ1 =94, DQ2 =88, DQ3 =98
5767 22:18:09.859635 DQ4 =96, DQ5 =108, DQ6 =110, DQ7 =92
5768 22:18:09.862705 DQ8 =80, DQ9 =84, DQ10 =92, DQ11 =86
5769 22:18:09.865914 DQ12 =106, DQ13 =106, DQ14 =102, DQ15 =106
5770 22:18:09.866000
5771 22:18:09.866065
5772 22:18:09.872000 [DQSOSCAuto] RK0, (LSB)MR18= 0x515, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 420 ps
5773 22:18:09.875687 CH1 RK0: MR19=505, MR18=515
5774 22:18:09.882308 CH1_RK0: MR19=0x505, MR18=0x515, DQSOSC=415, MR23=63, INC=62, DEC=41
5775 22:18:09.882393
5776 22:18:09.885426 ----->DramcWriteLeveling(PI) begin...
5777 22:18:09.885510 ==
5778 22:18:09.889283 Dram Type= 6, Freq= 0, CH_1, rank 1
5779 22:18:09.892443 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5780 22:18:09.892527 ==
5781 22:18:09.895146 Write leveling (Byte 0): 25 => 25
5782 22:18:09.898887 Write leveling (Byte 1): 25 => 25
5783 22:18:09.902007 DramcWriteLeveling(PI) end<-----
5784 22:18:09.902091
5785 22:18:09.902156 ==
5786 22:18:09.905178 Dram Type= 6, Freq= 0, CH_1, rank 1
5787 22:18:09.911967 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5788 22:18:09.912112 ==
5789 22:18:09.912178 [Gating] SW mode calibration
5790 22:18:09.921747 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5791 22:18:09.925113 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5792 22:18:09.931257 0 14 0 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
5793 22:18:09.934832 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5794 22:18:09.938247 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5795 22:18:09.944396 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5796 22:18:09.947658 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5797 22:18:09.951332 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5798 22:18:09.957588 0 14 24 | B1->B0 | 3434 3030 | 0 0 | (0 0) (0 1)
5799 22:18:09.961263 0 14 28 | B1->B0 | 2a2a 2323 | 1 0 | (1 0) (0 0)
5800 22:18:09.964670 0 15 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5801 22:18:09.971368 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5802 22:18:09.974208 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5803 22:18:09.977617 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5804 22:18:09.984262 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5805 22:18:09.987438 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5806 22:18:09.990630 0 15 24 | B1->B0 | 2626 2f2f | 0 0 | (0 0) (0 0)
5807 22:18:09.997837 0 15 28 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
5808 22:18:10.000931 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5809 22:18:10.004024 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5810 22:18:10.010334 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5811 22:18:10.013422 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5812 22:18:10.016940 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5813 22:18:10.023691 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5814 22:18:10.026889 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5815 22:18:10.029837 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5816 22:18:10.036392 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5817 22:18:10.039959 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5818 22:18:10.042964 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5819 22:18:10.049451 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5820 22:18:10.053139 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5821 22:18:10.056722 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5822 22:18:10.062968 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5823 22:18:10.066155 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5824 22:18:10.069305 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5825 22:18:10.076328 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5826 22:18:10.079388 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5827 22:18:10.082385 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5828 22:18:10.089175 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5829 22:18:10.092153 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5830 22:18:10.095896 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5831 22:18:10.102595 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5832 22:18:10.105386 Total UI for P1: 0, mck2ui 16
5833 22:18:10.108589 best dqsien dly found for B0: ( 1, 2, 24)
5834 22:18:10.111828 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5835 22:18:10.115280 Total UI for P1: 0, mck2ui 16
5836 22:18:10.118725 best dqsien dly found for B1: ( 1, 2, 28)
5837 22:18:10.122217 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5838 22:18:10.125250 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5839 22:18:10.125334
5840 22:18:10.128328 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5841 22:18:10.134911 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5842 22:18:10.134996 [Gating] SW calibration Done
5843 22:18:10.135063 ==
5844 22:18:10.138211 Dram Type= 6, Freq= 0, CH_1, rank 1
5845 22:18:10.144724 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5846 22:18:10.144813 ==
5847 22:18:10.144880 RX Vref Scan: 0
5848 22:18:10.144942
5849 22:18:10.147856 RX Vref 0 -> 0, step: 1
5850 22:18:10.147968
5851 22:18:10.151355 RX Delay -80 -> 252, step: 8
5852 22:18:10.154609 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5853 22:18:10.158300 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5854 22:18:10.161392 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5855 22:18:10.167949 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5856 22:18:10.171451 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5857 22:18:10.174948 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5858 22:18:10.177593 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5859 22:18:10.180777 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5860 22:18:10.184496 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5861 22:18:10.190932 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5862 22:18:10.194085 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5863 22:18:10.197521 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5864 22:18:10.200556 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5865 22:18:10.204280 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5866 22:18:10.210475 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5867 22:18:10.216684 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5868 22:18:10.216769 ==
5869 22:18:10.217015 Dram Type= 6, Freq= 0, CH_1, rank 1
5870 22:18:10.220643 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5871 22:18:10.220726 ==
5872 22:18:10.223881 DQS Delay:
5873 22:18:10.223990 DQS0 = 0, DQS1 = 0
5874 22:18:10.224110 DQM Delay:
5875 22:18:10.227185 DQM0 = 97, DQM1 = 93
5876 22:18:10.227267 DQ Delay:
5877 22:18:10.230207 DQ0 =103, DQ1 =95, DQ2 =83, DQ3 =99
5878 22:18:10.233675 DQ4 =95, DQ5 =107, DQ6 =103, DQ7 =95
5879 22:18:10.237129 DQ8 =79, DQ9 =79, DQ10 =95, DQ11 =87
5880 22:18:10.240267 DQ12 =103, DQ13 =103, DQ14 =99, DQ15 =103
5881 22:18:10.240351
5882 22:18:10.240416
5883 22:18:10.243732 ==
5884 22:18:10.243815 Dram Type= 6, Freq= 0, CH_1, rank 1
5885 22:18:10.250203 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5886 22:18:10.250287 ==
5887 22:18:10.250350
5888 22:18:10.250411
5889 22:18:10.253581 TX Vref Scan disable
5890 22:18:10.253663 == TX Byte 0 ==
5891 22:18:10.257191 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5892 22:18:10.263435 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5893 22:18:10.263517 == TX Byte 1 ==
5894 22:18:10.269958 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5895 22:18:10.273026 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5896 22:18:10.273109 ==
5897 22:18:10.276614 Dram Type= 6, Freq= 0, CH_1, rank 1
5898 22:18:10.279721 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5899 22:18:10.279810 ==
5900 22:18:10.279876
5901 22:18:10.279937
5902 22:18:10.283169 TX Vref Scan disable
5903 22:18:10.286398 == TX Byte 0 ==
5904 22:18:10.289636 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5905 22:18:10.292995 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5906 22:18:10.296166 == TX Byte 1 ==
5907 22:18:10.299717 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5908 22:18:10.302544 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5909 22:18:10.302627
5910 22:18:10.306037 [DATLAT]
5911 22:18:10.306120 Freq=933, CH1 RK1
5912 22:18:10.306186
5913 22:18:10.309588 DATLAT Default: 0xb
5914 22:18:10.309671 0, 0xFFFF, sum = 0
5915 22:18:10.312518 1, 0xFFFF, sum = 0
5916 22:18:10.312606 2, 0xFFFF, sum = 0
5917 22:18:10.316130 3, 0xFFFF, sum = 0
5918 22:18:10.316215 4, 0xFFFF, sum = 0
5919 22:18:10.319398 5, 0xFFFF, sum = 0
5920 22:18:10.319482 6, 0xFFFF, sum = 0
5921 22:18:10.322587 7, 0xFFFF, sum = 0
5922 22:18:10.322672 8, 0xFFFF, sum = 0
5923 22:18:10.325616 9, 0xFFFF, sum = 0
5924 22:18:10.325703 10, 0x0, sum = 1
5925 22:18:10.328915 11, 0x0, sum = 2
5926 22:18:10.328999 12, 0x0, sum = 3
5927 22:18:10.332456 13, 0x0, sum = 4
5928 22:18:10.332540 best_step = 11
5929 22:18:10.332606
5930 22:18:10.332666 ==
5931 22:18:10.335687 Dram Type= 6, Freq= 0, CH_1, rank 1
5932 22:18:10.342066 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5933 22:18:10.342151 ==
5934 22:18:10.342216 RX Vref Scan: 0
5935 22:18:10.342276
5936 22:18:10.345509 RX Vref 0 -> 0, step: 1
5937 22:18:10.345596
5938 22:18:10.348975 RX Delay -61 -> 252, step: 4
5939 22:18:10.352205 iDelay=199, Bit 0, Center 100 (11 ~ 190) 180
5940 22:18:10.358835 iDelay=199, Bit 1, Center 94 (3 ~ 186) 184
5941 22:18:10.362212 iDelay=199, Bit 2, Center 86 (-5 ~ 178) 184
5942 22:18:10.365079 iDelay=199, Bit 3, Center 96 (7 ~ 186) 180
5943 22:18:10.368561 iDelay=199, Bit 4, Center 98 (7 ~ 190) 184
5944 22:18:10.371763 iDelay=199, Bit 5, Center 106 (15 ~ 198) 184
5945 22:18:10.378114 iDelay=199, Bit 6, Center 104 (15 ~ 194) 180
5946 22:18:10.381815 iDelay=199, Bit 7, Center 96 (7 ~ 186) 180
5947 22:18:10.385130 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5948 22:18:10.388505 iDelay=199, Bit 9, Center 86 (-1 ~ 174) 176
5949 22:18:10.391382 iDelay=199, Bit 10, Center 96 (7 ~ 186) 180
5950 22:18:10.394987 iDelay=199, Bit 11, Center 88 (-1 ~ 178) 180
5951 22:18:10.401103 iDelay=199, Bit 12, Center 104 (19 ~ 190) 172
5952 22:18:10.404435 iDelay=199, Bit 13, Center 102 (15 ~ 190) 176
5953 22:18:10.407711 iDelay=199, Bit 14, Center 100 (15 ~ 186) 172
5954 22:18:10.411047 iDelay=199, Bit 15, Center 104 (15 ~ 194) 180
5955 22:18:10.411132 ==
5956 22:18:10.414874 Dram Type= 6, Freq= 0, CH_1, rank 1
5957 22:18:10.420993 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5958 22:18:10.421079 ==
5959 22:18:10.421146 DQS Delay:
5960 22:18:10.424179 DQS0 = 0, DQS1 = 0
5961 22:18:10.424288 DQM Delay:
5962 22:18:10.427663 DQM0 = 97, DQM1 = 95
5963 22:18:10.427748 DQ Delay:
5964 22:18:10.430860 DQ0 =100, DQ1 =94, DQ2 =86, DQ3 =96
5965 22:18:10.434005 DQ4 =98, DQ5 =106, DQ6 =104, DQ7 =96
5966 22:18:10.438129 DQ8 =84, DQ9 =86, DQ10 =96, DQ11 =88
5967 22:18:10.440628 DQ12 =104, DQ13 =102, DQ14 =100, DQ15 =104
5968 22:18:10.440712
5969 22:18:10.440778
5970 22:18:10.447106 [DQSOSCAuto] RK1, (LSB)MR18= 0xa21, (MSB)MR19= 0x505, tDQSOscB0 = 411 ps tDQSOscB1 = 418 ps
5971 22:18:10.450612 CH1 RK1: MR19=505, MR18=A21
5972 22:18:10.457155 CH1_RK1: MR19=0x505, MR18=0xA21, DQSOSC=411, MR23=63, INC=64, DEC=42
5973 22:18:10.460686 [RxdqsGatingPostProcess] freq 933
5974 22:18:10.466955 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5975 22:18:10.470301 best DQS0 dly(2T, 0.5T) = (0, 10)
5976 22:18:10.473339 best DQS1 dly(2T, 0.5T) = (0, 10)
5977 22:18:10.476662 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5978 22:18:10.479942 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5979 22:18:10.480037 best DQS0 dly(2T, 0.5T) = (0, 10)
5980 22:18:10.483481 best DQS1 dly(2T, 0.5T) = (0, 10)
5981 22:18:10.486651 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5982 22:18:10.490194 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5983 22:18:10.493923 Pre-setting of DQS Precalculation
5984 22:18:10.499870 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5985 22:18:10.506440 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5986 22:18:10.513365 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5987 22:18:10.513452
5988 22:18:10.513518
5989 22:18:10.516594 [Calibration Summary] 1866 Mbps
5990 22:18:10.516677 CH 0, Rank 0
5991 22:18:10.519507 SW Impedance : PASS
5992 22:18:10.522958 DUTY Scan : NO K
5993 22:18:10.523042 ZQ Calibration : PASS
5994 22:18:10.526712 Jitter Meter : NO K
5995 22:18:10.529602 CBT Training : PASS
5996 22:18:10.529686 Write leveling : PASS
5997 22:18:10.533268 RX DQS gating : PASS
5998 22:18:10.536333 RX DQ/DQS(RDDQC) : PASS
5999 22:18:10.536442 TX DQ/DQS : PASS
6000 22:18:10.539660 RX DATLAT : PASS
6001 22:18:10.542619 RX DQ/DQS(Engine): PASS
6002 22:18:10.542702 TX OE : NO K
6003 22:18:10.546058 All Pass.
6004 22:18:10.546141
6005 22:18:10.546210 CH 0, Rank 1
6006 22:18:10.549685 SW Impedance : PASS
6007 22:18:10.549768 DUTY Scan : NO K
6008 22:18:10.552192 ZQ Calibration : PASS
6009 22:18:10.555721 Jitter Meter : NO K
6010 22:18:10.555805 CBT Training : PASS
6011 22:18:10.558840 Write leveling : PASS
6012 22:18:10.561980 RX DQS gating : PASS
6013 22:18:10.562070 RX DQ/DQS(RDDQC) : PASS
6014 22:18:10.565409 TX DQ/DQS : PASS
6015 22:18:10.569018 RX DATLAT : PASS
6016 22:18:10.569102 RX DQ/DQS(Engine): PASS
6017 22:18:10.572263 TX OE : NO K
6018 22:18:10.572346 All Pass.
6019 22:18:10.572412
6020 22:18:10.575166 CH 1, Rank 0
6021 22:18:10.575248 SW Impedance : PASS
6022 22:18:10.578892 DUTY Scan : NO K
6023 22:18:10.581872 ZQ Calibration : PASS
6024 22:18:10.581955 Jitter Meter : NO K
6025 22:18:10.585238 CBT Training : PASS
6026 22:18:10.588481 Write leveling : PASS
6027 22:18:10.588565 RX DQS gating : PASS
6028 22:18:10.591658 RX DQ/DQS(RDDQC) : PASS
6029 22:18:10.595292 TX DQ/DQS : PASS
6030 22:18:10.595376 RX DATLAT : PASS
6031 22:18:10.598413 RX DQ/DQS(Engine): PASS
6032 22:18:10.601558 TX OE : NO K
6033 22:18:10.601641 All Pass.
6034 22:18:10.601708
6035 22:18:10.601769 CH 1, Rank 1
6036 22:18:10.605122 SW Impedance : PASS
6037 22:18:10.608321 DUTY Scan : NO K
6038 22:18:10.608404 ZQ Calibration : PASS
6039 22:18:10.611283 Jitter Meter : NO K
6040 22:18:10.615094 CBT Training : PASS
6041 22:18:10.615177 Write leveling : PASS
6042 22:18:10.617945 RX DQS gating : PASS
6043 22:18:10.618028 RX DQ/DQS(RDDQC) : PASS
6044 22:18:10.621333 TX DQ/DQS : PASS
6045 22:18:10.624853 RX DATLAT : PASS
6046 22:18:10.624936 RX DQ/DQS(Engine): PASS
6047 22:18:10.627989 TX OE : NO K
6048 22:18:10.628114 All Pass.
6049 22:18:10.628181
6050 22:18:10.631062 DramC Write-DBI off
6051 22:18:10.634431 PER_BANK_REFRESH: Hybrid Mode
6052 22:18:10.634514 TX_TRACKING: ON
6053 22:18:10.644290 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6054 22:18:10.648004 [FAST_K] Save calibration result to emmc
6055 22:18:10.651064 dramc_set_vcore_voltage set vcore to 650000
6056 22:18:10.653998 Read voltage for 400, 6
6057 22:18:10.654081 Vio18 = 0
6058 22:18:10.657390 Vcore = 650000
6059 22:18:10.657473 Vdram = 0
6060 22:18:10.657538 Vddq = 0
6061 22:18:10.657598 Vmddr = 0
6062 22:18:10.664003 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6063 22:18:10.671211 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6064 22:18:10.671297 MEM_TYPE=3, freq_sel=20
6065 22:18:10.674155 sv_algorithm_assistance_LP4_800
6066 22:18:10.677663 ============ PULL DRAM RESETB DOWN ============
6067 22:18:10.683876 ========== PULL DRAM RESETB DOWN end =========
6068 22:18:10.687171 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6069 22:18:10.690384 ===================================
6070 22:18:10.693431 LPDDR4 DRAM CONFIGURATION
6071 22:18:10.697015 ===================================
6072 22:18:10.697099 EX_ROW_EN[0] = 0x0
6073 22:18:10.700522 EX_ROW_EN[1] = 0x0
6074 22:18:10.704018 LP4Y_EN = 0x0
6075 22:18:10.704138 WORK_FSP = 0x0
6076 22:18:10.706775 WL = 0x2
6077 22:18:10.706858 RL = 0x2
6078 22:18:10.710103 BL = 0x2
6079 22:18:10.710186 RPST = 0x0
6080 22:18:10.713313 RD_PRE = 0x0
6081 22:18:10.713396 WR_PRE = 0x1
6082 22:18:10.716533 WR_PST = 0x0
6083 22:18:10.716615 DBI_WR = 0x0
6084 22:18:10.720232 DBI_RD = 0x0
6085 22:18:10.720315 OTF = 0x1
6086 22:18:10.723329 ===================================
6087 22:18:10.726697 ===================================
6088 22:18:10.729691 ANA top config
6089 22:18:10.733723 ===================================
6090 22:18:10.733807 DLL_ASYNC_EN = 0
6091 22:18:10.736609 ALL_SLAVE_EN = 1
6092 22:18:10.739912 NEW_RANK_MODE = 1
6093 22:18:10.743205 DLL_IDLE_MODE = 1
6094 22:18:10.746729 LP45_APHY_COMB_EN = 1
6095 22:18:10.746812 TX_ODT_DIS = 1
6096 22:18:10.749495 NEW_8X_MODE = 1
6097 22:18:10.752922 ===================================
6098 22:18:10.755993 ===================================
6099 22:18:10.759322 data_rate = 800
6100 22:18:10.762750 CKR = 1
6101 22:18:10.765830 DQ_P2S_RATIO = 4
6102 22:18:10.769447 ===================================
6103 22:18:10.772478 CA_P2S_RATIO = 4
6104 22:18:10.772561 DQ_CA_OPEN = 0
6105 22:18:10.775881 DQ_SEMI_OPEN = 1
6106 22:18:10.779391 CA_SEMI_OPEN = 1
6107 22:18:10.782275 CA_FULL_RATE = 0
6108 22:18:10.785920 DQ_CKDIV4_EN = 0
6109 22:18:10.789349 CA_CKDIV4_EN = 1
6110 22:18:10.789433 CA_PREDIV_EN = 0
6111 22:18:10.792144 PH8_DLY = 0
6112 22:18:10.795502 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6113 22:18:10.798992 DQ_AAMCK_DIV = 0
6114 22:18:10.802117 CA_AAMCK_DIV = 0
6115 22:18:10.805404 CA_ADMCK_DIV = 4
6116 22:18:10.808736 DQ_TRACK_CA_EN = 0
6117 22:18:10.808822 CA_PICK = 800
6118 22:18:10.812385 CA_MCKIO = 400
6119 22:18:10.815501 MCKIO_SEMI = 400
6120 22:18:10.818580 PLL_FREQ = 3016
6121 22:18:10.821787 DQ_UI_PI_RATIO = 32
6122 22:18:10.825533 CA_UI_PI_RATIO = 32
6123 22:18:10.828471 ===================================
6124 22:18:10.831839 ===================================
6125 22:18:10.835427 memory_type:LPDDR4
6126 22:18:10.835513 GP_NUM : 10
6127 22:18:10.838653 SRAM_EN : 1
6128 22:18:10.838736 MD32_EN : 0
6129 22:18:10.841751 ===================================
6130 22:18:10.844992 [ANA_INIT] >>>>>>>>>>>>>>
6131 22:18:10.848429 <<<<<< [CONFIGURE PHASE]: ANA_TX
6132 22:18:10.851827 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6133 22:18:10.855320 ===================================
6134 22:18:10.858514 data_rate = 800,PCW = 0X7400
6135 22:18:10.861447 ===================================
6136 22:18:10.864896 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6137 22:18:10.871342 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6138 22:18:10.881269 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6139 22:18:10.884327 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6140 22:18:10.888235 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6141 22:18:10.894373 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6142 22:18:10.894460 [ANA_INIT] flow start
6143 22:18:10.897581 [ANA_INIT] PLL >>>>>>>>
6144 22:18:10.900864 [ANA_INIT] PLL <<<<<<<<
6145 22:18:10.900948 [ANA_INIT] MIDPI >>>>>>>>
6146 22:18:10.904234 [ANA_INIT] MIDPI <<<<<<<<
6147 22:18:10.907469 [ANA_INIT] DLL >>>>>>>>
6148 22:18:10.907553 [ANA_INIT] flow end
6149 22:18:10.910968 ============ LP4 DIFF to SE enter ============
6150 22:18:10.917553 ============ LP4 DIFF to SE exit ============
6151 22:18:10.917638 [ANA_INIT] <<<<<<<<<<<<<
6152 22:18:10.920509 [Flow] Enable top DCM control >>>>>
6153 22:18:10.923984 [Flow] Enable top DCM control <<<<<
6154 22:18:10.927260 Enable DLL master slave shuffle
6155 22:18:10.934154 ==============================================================
6156 22:18:10.937485 Gating Mode config
6157 22:18:10.940584 ==============================================================
6158 22:18:10.944229 Config description:
6159 22:18:10.953550 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6160 22:18:10.960013 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6161 22:18:10.963266 SELPH_MODE 0: By rank 1: By Phase
6162 22:18:10.970526 ==============================================================
6163 22:18:10.973065 GAT_TRACK_EN = 0
6164 22:18:10.976576 RX_GATING_MODE = 2
6165 22:18:10.979915 RX_GATING_TRACK_MODE = 2
6166 22:18:10.983328 SELPH_MODE = 1
6167 22:18:10.986734 PICG_EARLY_EN = 1
6168 22:18:10.986820 VALID_LAT_VALUE = 1
6169 22:18:10.993048 ==============================================================
6170 22:18:10.996463 Enter into Gating configuration >>>>
6171 22:18:10.999419 Exit from Gating configuration <<<<
6172 22:18:11.003213 Enter into DVFS_PRE_config >>>>>
6173 22:18:11.012957 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6174 22:18:11.016001 Exit from DVFS_PRE_config <<<<<
6175 22:18:11.019209 Enter into PICG configuration >>>>
6176 22:18:11.022569 Exit from PICG configuration <<<<
6177 22:18:11.026275 [RX_INPUT] configuration >>>>>
6178 22:18:11.029026 [RX_INPUT] configuration <<<<<
6179 22:18:11.035832 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6180 22:18:11.039219 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6181 22:18:11.045453 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6182 22:18:11.052024 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6183 22:18:11.058533 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6184 22:18:11.065267 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6185 22:18:11.068868 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6186 22:18:11.072155 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6187 22:18:11.074975 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6188 22:18:11.081624 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6189 22:18:11.085186 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6190 22:18:11.088529 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6191 22:18:11.091725 ===================================
6192 22:18:11.095293 LPDDR4 DRAM CONFIGURATION
6193 22:18:11.098621 ===================================
6194 22:18:11.102089 EX_ROW_EN[0] = 0x0
6195 22:18:11.102174 EX_ROW_EN[1] = 0x0
6196 22:18:11.104870 LP4Y_EN = 0x0
6197 22:18:11.104953 WORK_FSP = 0x0
6198 22:18:11.108256 WL = 0x2
6199 22:18:11.108339 RL = 0x2
6200 22:18:11.112916 BL = 0x2
6201 22:18:11.113030 RPST = 0x0
6202 22:18:11.114898 RD_PRE = 0x0
6203 22:18:11.114981 WR_PRE = 0x1
6204 22:18:11.118110 WR_PST = 0x0
6205 22:18:11.118193 DBI_WR = 0x0
6206 22:18:11.121524 DBI_RD = 0x0
6207 22:18:11.121607 OTF = 0x1
6208 22:18:11.124735 ===================================
6209 22:18:11.131445 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6210 22:18:11.134627 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6211 22:18:11.137818 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6212 22:18:11.141185 ===================================
6213 22:18:11.144138 LPDDR4 DRAM CONFIGURATION
6214 22:18:11.147957 ===================================
6215 22:18:11.150943 EX_ROW_EN[0] = 0x10
6216 22:18:11.151025 EX_ROW_EN[1] = 0x0
6217 22:18:11.154066 LP4Y_EN = 0x0
6218 22:18:11.154149 WORK_FSP = 0x0
6219 22:18:11.157316 WL = 0x2
6220 22:18:11.157399 RL = 0x2
6221 22:18:11.161163 BL = 0x2
6222 22:18:11.161247 RPST = 0x0
6223 22:18:11.164407 RD_PRE = 0x0
6224 22:18:11.164489 WR_PRE = 0x1
6225 22:18:11.167640 WR_PST = 0x0
6226 22:18:11.170788 DBI_WR = 0x0
6227 22:18:11.170870 DBI_RD = 0x0
6228 22:18:11.173983 OTF = 0x1
6229 22:18:11.177287 ===================================
6230 22:18:11.180898 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6231 22:18:11.186161 nWR fixed to 30
6232 22:18:11.189020 [ModeRegInit_LP4] CH0 RK0
6233 22:18:11.189104 [ModeRegInit_LP4] CH0 RK1
6234 22:18:11.192364 [ModeRegInit_LP4] CH1 RK0
6235 22:18:11.195885 [ModeRegInit_LP4] CH1 RK1
6236 22:18:11.195994 match AC timing 19
6237 22:18:11.202288 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6238 22:18:11.205485 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6239 22:18:11.208694 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6240 22:18:11.215438 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6241 22:18:11.218431 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6242 22:18:11.218516 ==
6243 22:18:11.222031 Dram Type= 6, Freq= 0, CH_0, rank 0
6244 22:18:11.225319 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6245 22:18:11.225403 ==
6246 22:18:11.231830 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6247 22:18:11.238844 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6248 22:18:11.242029 [CA 0] Center 36 (8~64) winsize 57
6249 22:18:11.245234 [CA 1] Center 36 (8~64) winsize 57
6250 22:18:11.248240 [CA 2] Center 36 (8~64) winsize 57
6251 22:18:11.251434 [CA 3] Center 36 (8~64) winsize 57
6252 22:18:11.254995 [CA 4] Center 36 (8~64) winsize 57
6253 22:18:11.258177 [CA 5] Center 36 (8~64) winsize 57
6254 22:18:11.258260
6255 22:18:11.261331 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6256 22:18:11.261415
6257 22:18:11.264808 [CATrainingPosCal] consider 1 rank data
6258 22:18:11.267874 u2DelayCellTimex100 = 270/100 ps
6259 22:18:11.271546 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6260 22:18:11.274564 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6261 22:18:11.277768 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6262 22:18:11.281370 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6263 22:18:11.284193 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6264 22:18:11.287566 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6265 22:18:11.287648
6266 22:18:11.294264 CA PerBit enable=1, Macro0, CA PI delay=36
6267 22:18:11.294348
6268 22:18:11.297387 [CBTSetCACLKResult] CA Dly = 36
6269 22:18:11.297471 CS Dly: 1 (0~32)
6270 22:18:11.297537 ==
6271 22:18:11.300983 Dram Type= 6, Freq= 0, CH_0, rank 1
6272 22:18:11.303841 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6273 22:18:11.303925 ==
6274 22:18:11.310807 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6275 22:18:11.317446 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6276 22:18:11.320762 [CA 0] Center 36 (8~64) winsize 57
6277 22:18:11.323987 [CA 1] Center 36 (8~64) winsize 57
6278 22:18:11.327321 [CA 2] Center 36 (8~64) winsize 57
6279 22:18:11.330664 [CA 3] Center 36 (8~64) winsize 57
6280 22:18:11.333771 [CA 4] Center 36 (8~64) winsize 57
6281 22:18:11.337217 [CA 5] Center 36 (8~64) winsize 57
6282 22:18:11.337301
6283 22:18:11.340073 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6284 22:18:11.340169
6285 22:18:11.343363 [CATrainingPosCal] consider 2 rank data
6286 22:18:11.346935 u2DelayCellTimex100 = 270/100 ps
6287 22:18:11.350250 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6288 22:18:11.353787 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6289 22:18:11.356971 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6290 22:18:11.360186 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6291 22:18:11.363217 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6292 22:18:11.366561 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6293 22:18:11.366644
6294 22:18:11.370189 CA PerBit enable=1, Macro0, CA PI delay=36
6295 22:18:11.373175
6296 22:18:11.373257 [CBTSetCACLKResult] CA Dly = 36
6297 22:18:11.376756 CS Dly: 1 (0~32)
6298 22:18:11.376838
6299 22:18:11.379645 ----->DramcWriteLeveling(PI) begin...
6300 22:18:11.379731 ==
6301 22:18:11.383360 Dram Type= 6, Freq= 0, CH_0, rank 0
6302 22:18:11.386450 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6303 22:18:11.386535 ==
6304 22:18:11.389620 Write leveling (Byte 0): 40 => 8
6305 22:18:11.392902 Write leveling (Byte 1): 40 => 8
6306 22:18:11.396578 DramcWriteLeveling(PI) end<-----
6307 22:18:11.396662
6308 22:18:11.396728 ==
6309 22:18:11.399744 Dram Type= 6, Freq= 0, CH_0, rank 0
6310 22:18:11.402973 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6311 22:18:11.406219 ==
6312 22:18:11.406303 [Gating] SW mode calibration
6313 22:18:11.416325 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6314 22:18:11.419041 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6315 22:18:11.422487 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6316 22:18:11.428892 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6317 22:18:11.432295 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6318 22:18:11.435456 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6319 22:18:11.441984 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6320 22:18:11.445609 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6321 22:18:11.449109 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6322 22:18:11.455382 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6323 22:18:11.458642 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6324 22:18:11.461947 Total UI for P1: 0, mck2ui 16
6325 22:18:11.465134 best dqsien dly found for B0: ( 0, 14, 24)
6326 22:18:11.468410 Total UI for P1: 0, mck2ui 16
6327 22:18:11.472004 best dqsien dly found for B1: ( 0, 14, 24)
6328 22:18:11.475284 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6329 22:18:11.478489 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6330 22:18:11.478574
6331 22:18:11.481535 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6332 22:18:11.488614 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6333 22:18:11.488703 [Gating] SW calibration Done
6334 22:18:11.491713 ==
6335 22:18:11.491796 Dram Type= 6, Freq= 0, CH_0, rank 0
6336 22:18:11.498420 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6337 22:18:11.498506 ==
6338 22:18:11.498573 RX Vref Scan: 0
6339 22:18:11.498636
6340 22:18:11.501331 RX Vref 0 -> 0, step: 1
6341 22:18:11.501414
6342 22:18:11.504497 RX Delay -410 -> 252, step: 16
6343 22:18:11.508381 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6344 22:18:11.511666 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6345 22:18:11.518790 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6346 22:18:11.521309 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6347 22:18:11.525030 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6348 22:18:11.528274 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6349 22:18:11.534716 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6350 22:18:11.538112 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6351 22:18:11.541400 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6352 22:18:11.547472 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6353 22:18:11.550856 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6354 22:18:11.554095 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6355 22:18:11.557462 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6356 22:18:11.564244 iDelay=230, Bit 13, Center -27 (-266 ~ 213) 480
6357 22:18:11.567699 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6358 22:18:11.570969 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6359 22:18:11.571053 ==
6360 22:18:11.573906 Dram Type= 6, Freq= 0, CH_0, rank 0
6361 22:18:11.580569 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6362 22:18:11.580657 ==
6363 22:18:11.580722 DQS Delay:
6364 22:18:11.583623 DQS0 = 35, DQS1 = 51
6365 22:18:11.583705 DQM Delay:
6366 22:18:11.583769 DQM0 = 7, DQM1 = 13
6367 22:18:11.587234 DQ Delay:
6368 22:18:11.590434 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =0
6369 22:18:11.590516 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6370 22:18:11.594079 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6371 22:18:11.596863 DQ12 =16, DQ13 =24, DQ14 =24, DQ15 =16
6372 22:18:11.596945
6373 22:18:11.600168
6374 22:18:11.600249 ==
6375 22:18:11.603459 Dram Type= 6, Freq= 0, CH_0, rank 0
6376 22:18:11.606577 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6377 22:18:11.606659 ==
6378 22:18:11.606723
6379 22:18:11.606783
6380 22:18:11.610181 TX Vref Scan disable
6381 22:18:11.610262 == TX Byte 0 ==
6382 22:18:11.613094 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6383 22:18:11.619955 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6384 22:18:11.620085 == TX Byte 1 ==
6385 22:18:11.623001 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6386 22:18:11.629632 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6387 22:18:11.629715 ==
6388 22:18:11.633305 Dram Type= 6, Freq= 0, CH_0, rank 0
6389 22:18:11.636358 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6390 22:18:11.636440 ==
6391 22:18:11.636504
6392 22:18:11.636564
6393 22:18:11.639448 TX Vref Scan disable
6394 22:18:11.639530 == TX Byte 0 ==
6395 22:18:11.646182 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6396 22:18:11.649543 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6397 22:18:11.649627 == TX Byte 1 ==
6398 22:18:11.656380 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6399 22:18:11.659150 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6400 22:18:11.659232
6401 22:18:11.659296 [DATLAT]
6402 22:18:11.662996 Freq=400, CH0 RK0
6403 22:18:11.663079
6404 22:18:11.663143 DATLAT Default: 0xf
6405 22:18:11.666001 0, 0xFFFF, sum = 0
6406 22:18:11.666084 1, 0xFFFF, sum = 0
6407 22:18:11.669205 2, 0xFFFF, sum = 0
6408 22:18:11.669288 3, 0xFFFF, sum = 0
6409 22:18:11.672608 4, 0xFFFF, sum = 0
6410 22:18:11.672692 5, 0xFFFF, sum = 0
6411 22:18:11.675801 6, 0xFFFF, sum = 0
6412 22:18:11.675883 7, 0xFFFF, sum = 0
6413 22:18:11.679026 8, 0xFFFF, sum = 0
6414 22:18:11.679109 9, 0xFFFF, sum = 0
6415 22:18:11.682366 10, 0xFFFF, sum = 0
6416 22:18:11.685991 11, 0xFFFF, sum = 0
6417 22:18:11.686074 12, 0xFFFF, sum = 0
6418 22:18:11.689318 13, 0x0, sum = 1
6419 22:18:11.689401 14, 0x0, sum = 2
6420 22:18:11.692276 15, 0x0, sum = 3
6421 22:18:11.692421 16, 0x0, sum = 4
6422 22:18:11.692552 best_step = 14
6423 22:18:11.692676
6424 22:18:11.695615 ==
6425 22:18:11.698802 Dram Type= 6, Freq= 0, CH_0, rank 0
6426 22:18:11.702414 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6427 22:18:11.702525 ==
6428 22:18:11.702620 RX Vref Scan: 1
6429 22:18:11.702711
6430 22:18:11.705518 RX Vref 0 -> 0, step: 1
6431 22:18:11.705633
6432 22:18:11.709255 RX Delay -343 -> 252, step: 8
6433 22:18:11.709364
6434 22:18:11.711765 Set Vref, RX VrefLevel [Byte0]: 51
6435 22:18:11.715712 [Byte1]: 50
6436 22:18:11.719257
6437 22:18:11.719360 Final RX Vref Byte 0 = 51 to rank0
6438 22:18:11.722655 Final RX Vref Byte 1 = 50 to rank0
6439 22:18:11.725354 Final RX Vref Byte 0 = 51 to rank1
6440 22:18:11.728857 Final RX Vref Byte 1 = 50 to rank1==
6441 22:18:11.732190 Dram Type= 6, Freq= 0, CH_0, rank 0
6442 22:18:11.739031 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6443 22:18:11.739176 ==
6444 22:18:11.739256 DQS Delay:
6445 22:18:11.742332 DQS0 = 44, DQS1 = 60
6446 22:18:11.742494 DQM Delay:
6447 22:18:11.745226 DQM0 = 10, DQM1 = 17
6448 22:18:11.745357 DQ Delay:
6449 22:18:11.748603 DQ0 =12, DQ1 =12, DQ2 =4, DQ3 =4
6450 22:18:11.752010 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6451 22:18:11.755426 DQ8 =8, DQ9 =0, DQ10 =20, DQ11 =12
6452 22:18:11.758245 DQ12 =24, DQ13 =24, DQ14 =28, DQ15 =24
6453 22:18:11.758328
6454 22:18:11.758393
6455 22:18:11.765482 [DQSOSCAuto] RK0, (LSB)MR18= 0x988b, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 390 ps
6456 22:18:11.768744 CH0 RK0: MR19=C0C, MR18=988B
6457 22:18:11.774747 CH0_RK0: MR19=0xC0C, MR18=0x988B, DQSOSC=390, MR23=63, INC=388, DEC=258
6458 22:18:11.774833 ==
6459 22:18:11.778507 Dram Type= 6, Freq= 0, CH_0, rank 1
6460 22:18:11.781396 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6461 22:18:11.781482 ==
6462 22:18:11.784910 [Gating] SW mode calibration
6463 22:18:11.791480 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6464 22:18:11.798049 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6465 22:18:11.801488 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6466 22:18:11.804613 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6467 22:18:11.811428 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6468 22:18:11.814472 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6469 22:18:11.818026 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6470 22:18:11.824321 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6471 22:18:11.827804 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6472 22:18:11.831160 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6473 22:18:11.837981 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6474 22:18:11.841061 Total UI for P1: 0, mck2ui 16
6475 22:18:11.844691 best dqsien dly found for B0: ( 0, 14, 24)
6476 22:18:11.847320 Total UI for P1: 0, mck2ui 16
6477 22:18:11.850701 best dqsien dly found for B1: ( 0, 14, 24)
6478 22:18:11.854088 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6479 22:18:11.857560 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6480 22:18:11.857675
6481 22:18:11.861146 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6482 22:18:11.864232 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6483 22:18:11.867423 [Gating] SW calibration Done
6484 22:18:11.867525 ==
6485 22:18:11.870538 Dram Type= 6, Freq= 0, CH_0, rank 1
6486 22:18:11.873818 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6487 22:18:11.873901 ==
6488 22:18:11.877419 RX Vref Scan: 0
6489 22:18:11.877502
6490 22:18:11.880587 RX Vref 0 -> 0, step: 1
6491 22:18:11.880670
6492 22:18:11.883508 RX Delay -410 -> 252, step: 16
6493 22:18:11.886819 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6494 22:18:11.890273 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6495 22:18:11.893842 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6496 22:18:11.900574 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6497 22:18:11.903512 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6498 22:18:11.906652 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6499 22:18:11.909992 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6500 22:18:11.916701 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6501 22:18:11.920437 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6502 22:18:11.923148 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6503 22:18:11.926643 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6504 22:18:11.933370 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6505 22:18:11.936122 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6506 22:18:11.939944 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6507 22:18:11.946117 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6508 22:18:11.949442 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6509 22:18:11.949542 ==
6510 22:18:11.952584 Dram Type= 6, Freq= 0, CH_0, rank 1
6511 22:18:11.956419 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6512 22:18:11.956504 ==
6513 22:18:11.959146 DQS Delay:
6514 22:18:11.959229 DQS0 = 35, DQS1 = 59
6515 22:18:11.962840 DQM Delay:
6516 22:18:11.962922 DQM0 = 7, DQM1 = 17
6517 22:18:11.962988 DQ Delay:
6518 22:18:11.965974 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =0
6519 22:18:11.970176 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6520 22:18:11.972619 DQ8 =8, DQ9 =0, DQ10 =24, DQ11 =8
6521 22:18:11.975595 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6522 22:18:11.975704
6523 22:18:11.975797
6524 22:18:11.975887 ==
6525 22:18:11.979151 Dram Type= 6, Freq= 0, CH_0, rank 1
6526 22:18:11.982374 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6527 22:18:11.985616 ==
6528 22:18:11.985699
6529 22:18:11.985764
6530 22:18:11.985824 TX Vref Scan disable
6531 22:18:11.988967 == TX Byte 0 ==
6532 22:18:11.991969 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6533 22:18:11.995690 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6534 22:18:11.999174 == TX Byte 1 ==
6535 22:18:12.002234 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6536 22:18:12.005478 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6537 22:18:12.005561 ==
6538 22:18:12.008839 Dram Type= 6, Freq= 0, CH_0, rank 1
6539 22:18:12.015212 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6540 22:18:12.015295 ==
6541 22:18:12.015361
6542 22:18:12.015422
6543 22:18:12.015480 TX Vref Scan disable
6544 22:18:12.018679 == TX Byte 0 ==
6545 22:18:12.021855 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6546 22:18:12.025560 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6547 22:18:12.028710 == TX Byte 1 ==
6548 22:18:12.032130 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6549 22:18:12.035302 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6550 22:18:12.035386
6551 22:18:12.038538 [DATLAT]
6552 22:18:12.038621 Freq=400, CH0 RK1
6553 22:18:12.038688
6554 22:18:12.041538 DATLAT Default: 0xe
6555 22:18:12.041621 0, 0xFFFF, sum = 0
6556 22:18:12.044869 1, 0xFFFF, sum = 0
6557 22:18:12.044953 2, 0xFFFF, sum = 0
6558 22:18:12.048320 3, 0xFFFF, sum = 0
6559 22:18:12.048404 4, 0xFFFF, sum = 0
6560 22:18:12.051310 5, 0xFFFF, sum = 0
6561 22:18:12.051394 6, 0xFFFF, sum = 0
6562 22:18:12.054782 7, 0xFFFF, sum = 0
6563 22:18:12.057841 8, 0xFFFF, sum = 0
6564 22:18:12.057925 9, 0xFFFF, sum = 0
6565 22:18:12.061315 10, 0xFFFF, sum = 0
6566 22:18:12.061399 11, 0xFFFF, sum = 0
6567 22:18:12.064403 12, 0xFFFF, sum = 0
6568 22:18:12.064502 13, 0x0, sum = 1
6569 22:18:12.067987 14, 0x0, sum = 2
6570 22:18:12.068123 15, 0x0, sum = 3
6571 22:18:12.071571 16, 0x0, sum = 4
6572 22:18:12.071656 best_step = 14
6573 22:18:12.071722
6574 22:18:12.071782 ==
6575 22:18:12.074568 Dram Type= 6, Freq= 0, CH_0, rank 1
6576 22:18:12.077806 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6577 22:18:12.080807 ==
6578 22:18:12.080891 RX Vref Scan: 0
6579 22:18:12.080957
6580 22:18:12.084430 RX Vref 0 -> 0, step: 1
6581 22:18:12.084514
6582 22:18:12.087518 RX Delay -359 -> 252, step: 8
6583 22:18:12.094326 iDelay=209, Bit 0, Center -36 (-271 ~ 200) 472
6584 22:18:12.097395 iDelay=209, Bit 1, Center -32 (-271 ~ 208) 480
6585 22:18:12.100693 iDelay=209, Bit 2, Center -36 (-271 ~ 200) 472
6586 22:18:12.104147 iDelay=209, Bit 3, Center -36 (-271 ~ 200) 472
6587 22:18:12.110623 iDelay=209, Bit 4, Center -32 (-271 ~ 208) 480
6588 22:18:12.113920 iDelay=209, Bit 5, Center -44 (-279 ~ 192) 472
6589 22:18:12.117149 iDelay=209, Bit 6, Center -28 (-263 ~ 208) 472
6590 22:18:12.120247 iDelay=209, Bit 7, Center -28 (-263 ~ 208) 472
6591 22:18:12.126965 iDelay=209, Bit 8, Center -52 (-295 ~ 192) 488
6592 22:18:12.130699 iDelay=209, Bit 9, Center -60 (-303 ~ 184) 488
6593 22:18:12.133761 iDelay=209, Bit 10, Center -44 (-287 ~ 200) 488
6594 22:18:12.136779 iDelay=209, Bit 11, Center -52 (-295 ~ 192) 488
6595 22:18:12.143276 iDelay=209, Bit 12, Center -40 (-279 ~ 200) 480
6596 22:18:12.146694 iDelay=209, Bit 13, Center -40 (-279 ~ 200) 480
6597 22:18:12.149994 iDelay=209, Bit 14, Center -32 (-271 ~ 208) 480
6598 22:18:12.156704 iDelay=209, Bit 15, Center -40 (-279 ~ 200) 480
6599 22:18:12.156789 ==
6600 22:18:12.159948 Dram Type= 6, Freq= 0, CH_0, rank 1
6601 22:18:12.162966 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6602 22:18:12.163051 ==
6603 22:18:12.163117 DQS Delay:
6604 22:18:12.166589 DQS0 = 44, DQS1 = 60
6605 22:18:12.166673 DQM Delay:
6606 22:18:12.170287 DQM0 = 10, DQM1 = 15
6607 22:18:12.170370 DQ Delay:
6608 22:18:12.173145 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =8
6609 22:18:12.176302 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =16
6610 22:18:12.179790 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6611 22:18:12.183072 DQ12 =20, DQ13 =20, DQ14 =28, DQ15 =20
6612 22:18:12.183156
6613 22:18:12.183222
6614 22:18:12.189957 [DQSOSCAuto] RK1, (LSB)MR18= 0x827b, (MSB)MR19= 0xc0c, tDQSOscB0 = 394 ps tDQSOscB1 = 393 ps
6615 22:18:12.192873 CH0 RK1: MR19=C0C, MR18=827B
6616 22:18:12.199416 CH0_RK1: MR19=0xC0C, MR18=0x827B, DQSOSC=393, MR23=63, INC=382, DEC=254
6617 22:18:12.202979 [RxdqsGatingPostProcess] freq 400
6618 22:18:12.209492 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6619 22:18:12.212551 best DQS0 dly(2T, 0.5T) = (0, 10)
6620 22:18:12.212635 best DQS1 dly(2T, 0.5T) = (0, 10)
6621 22:18:12.215980 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6622 22:18:12.219245 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6623 22:18:12.222510 best DQS0 dly(2T, 0.5T) = (0, 10)
6624 22:18:12.225895 best DQS1 dly(2T, 0.5T) = (0, 10)
6625 22:18:12.228707 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6626 22:18:12.232464 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6627 22:18:12.235361 Pre-setting of DQS Precalculation
6628 22:18:12.242010 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6629 22:18:12.242094 ==
6630 22:18:12.245523 Dram Type= 6, Freq= 0, CH_1, rank 0
6631 22:18:12.248830 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6632 22:18:12.248914 ==
6633 22:18:12.255427 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6634 22:18:12.261895 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6635 22:18:12.265120 [CA 0] Center 36 (8~64) winsize 57
6636 22:18:12.265204 [CA 1] Center 36 (8~64) winsize 57
6637 22:18:12.268316 [CA 2] Center 36 (8~64) winsize 57
6638 22:18:12.272413 [CA 3] Center 36 (8~64) winsize 57
6639 22:18:12.275221 [CA 4] Center 36 (8~64) winsize 57
6640 22:18:12.278223 [CA 5] Center 36 (8~64) winsize 57
6641 22:18:12.278307
6642 22:18:12.281291 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6643 22:18:12.284856
6644 22:18:12.287944 [CATrainingPosCal] consider 1 rank data
6645 22:18:12.288095 u2DelayCellTimex100 = 270/100 ps
6646 22:18:12.294660 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6647 22:18:12.298339 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6648 22:18:12.301334 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6649 22:18:12.304555 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6650 22:18:12.307628 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6651 22:18:12.311029 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6652 22:18:12.311113
6653 22:18:12.314527 CA PerBit enable=1, Macro0, CA PI delay=36
6654 22:18:12.314610
6655 22:18:12.317633 [CBTSetCACLKResult] CA Dly = 36
6656 22:18:12.321162 CS Dly: 1 (0~32)
6657 22:18:12.321246 ==
6658 22:18:12.324680 Dram Type= 6, Freq= 0, CH_1, rank 1
6659 22:18:12.327195 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6660 22:18:12.327280 ==
6661 22:18:12.333803 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6662 22:18:12.340951 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6663 22:18:12.344304 [CA 0] Center 36 (8~64) winsize 57
6664 22:18:12.344389 [CA 1] Center 36 (8~64) winsize 57
6665 22:18:12.347391 [CA 2] Center 36 (8~64) winsize 57
6666 22:18:12.350844 [CA 3] Center 36 (8~64) winsize 57
6667 22:18:12.353706 [CA 4] Center 36 (8~64) winsize 57
6668 22:18:12.356955 [CA 5] Center 36 (8~64) winsize 57
6669 22:18:12.357038
6670 22:18:12.360570 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6671 22:18:12.360654
6672 22:18:12.366891 [CATrainingPosCal] consider 2 rank data
6673 22:18:12.366975 u2DelayCellTimex100 = 270/100 ps
6674 22:18:12.374552 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6675 22:18:12.376949 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6676 22:18:12.380469 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6677 22:18:12.383369 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6678 22:18:12.386779 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6679 22:18:12.389958 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6680 22:18:12.390043
6681 22:18:12.393797 CA PerBit enable=1, Macro0, CA PI delay=36
6682 22:18:12.393881
6683 22:18:12.396757 [CBTSetCACLKResult] CA Dly = 36
6684 22:18:12.399778 CS Dly: 1 (0~32)
6685 22:18:12.399878
6686 22:18:12.403411 ----->DramcWriteLeveling(PI) begin...
6687 22:18:12.403498 ==
6688 22:18:12.406944 Dram Type= 6, Freq= 0, CH_1, rank 0
6689 22:18:12.409731 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6690 22:18:12.409817 ==
6691 22:18:12.413205 Write leveling (Byte 0): 40 => 8
6692 22:18:12.416740 Write leveling (Byte 1): 40 => 8
6693 22:18:12.420191 DramcWriteLeveling(PI) end<-----
6694 22:18:12.420275
6695 22:18:12.420341 ==
6696 22:18:12.423108 Dram Type= 6, Freq= 0, CH_1, rank 0
6697 22:18:12.426320 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6698 22:18:12.426405 ==
6699 22:18:12.429983 [Gating] SW mode calibration
6700 22:18:12.436204 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6701 22:18:12.443114 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6702 22:18:12.446498 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6703 22:18:12.449535 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6704 22:18:12.456050 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6705 22:18:12.459445 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6706 22:18:12.462868 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6707 22:18:12.469486 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6708 22:18:12.472458 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6709 22:18:12.476000 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6710 22:18:12.482262 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6711 22:18:12.485327 Total UI for P1: 0, mck2ui 16
6712 22:18:12.489342 best dqsien dly found for B0: ( 0, 14, 24)
6713 22:18:12.491906 Total UI for P1: 0, mck2ui 16
6714 22:18:12.495538 best dqsien dly found for B1: ( 0, 14, 24)
6715 22:18:12.498866 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6716 22:18:12.501899 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6717 22:18:12.501984
6718 22:18:12.505474 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6719 22:18:12.508497 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6720 22:18:12.512284 [Gating] SW calibration Done
6721 22:18:12.512367 ==
6722 22:18:12.515413 Dram Type= 6, Freq= 0, CH_1, rank 0
6723 22:18:12.518377 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6724 22:18:12.518461 ==
6725 22:18:12.521838 RX Vref Scan: 0
6726 22:18:12.521922
6727 22:18:12.525026 RX Vref 0 -> 0, step: 1
6728 22:18:12.525109
6729 22:18:12.528254 RX Delay -410 -> 252, step: 16
6730 22:18:12.532571 iDelay=230, Bit 0, Center -19 (-266 ~ 229) 496
6731 22:18:12.534916 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6732 22:18:12.538366 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6733 22:18:12.545039 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6734 22:18:12.548238 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6735 22:18:12.551145 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6736 22:18:12.554652 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6737 22:18:12.561520 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6738 22:18:12.565026 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6739 22:18:12.567710 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6740 22:18:12.570894 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6741 22:18:12.577622 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6742 22:18:12.580816 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6743 22:18:12.584217 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6744 22:18:12.591015 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6745 22:18:12.594341 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6746 22:18:12.594425 ==
6747 22:18:12.597523 Dram Type= 6, Freq= 0, CH_1, rank 0
6748 22:18:12.600595 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6749 22:18:12.600688 ==
6750 22:18:12.603994 DQS Delay:
6751 22:18:12.604102 DQS0 = 35, DQS1 = 51
6752 22:18:12.607601 DQM Delay:
6753 22:18:12.607686 DQM0 = 6, DQM1 = 13
6754 22:18:12.607751 DQ Delay:
6755 22:18:12.610546 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =0
6756 22:18:12.613699 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6757 22:18:12.617484 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6758 22:18:12.620471 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =16
6759 22:18:12.620556
6760 22:18:12.620622
6761 22:18:12.620682 ==
6762 22:18:12.623921 Dram Type= 6, Freq= 0, CH_1, rank 0
6763 22:18:12.630648 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6764 22:18:12.630744 ==
6765 22:18:12.630811
6766 22:18:12.630872
6767 22:18:12.630931 TX Vref Scan disable
6768 22:18:12.633538 == TX Byte 0 ==
6769 22:18:12.636723 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6770 22:18:12.640166 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6771 22:18:12.643682 == TX Byte 1 ==
6772 22:18:12.647014 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6773 22:18:12.650127 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6774 22:18:12.650212 ==
6775 22:18:12.653209 Dram Type= 6, Freq= 0, CH_1, rank 0
6776 22:18:12.659986 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6777 22:18:12.660083 ==
6778 22:18:12.660151
6779 22:18:12.660212
6780 22:18:12.660270 TX Vref Scan disable
6781 22:18:12.663377 == TX Byte 0 ==
6782 22:18:12.666640 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6783 22:18:12.669954 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6784 22:18:12.673069 == TX Byte 1 ==
6785 22:18:12.676280 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6786 22:18:12.679506 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6787 22:18:12.683189
6788 22:18:12.683275 [DATLAT]
6789 22:18:12.683341 Freq=400, CH1 RK0
6790 22:18:12.683402
6791 22:18:12.686404 DATLAT Default: 0xf
6792 22:18:12.686488 0, 0xFFFF, sum = 0
6793 22:18:12.689578 1, 0xFFFF, sum = 0
6794 22:18:12.689664 2, 0xFFFF, sum = 0
6795 22:18:12.692831 3, 0xFFFF, sum = 0
6796 22:18:12.696293 4, 0xFFFF, sum = 0
6797 22:18:12.696382 5, 0xFFFF, sum = 0
6798 22:18:12.699638 6, 0xFFFF, sum = 0
6799 22:18:12.699723 7, 0xFFFF, sum = 0
6800 22:18:12.702405 8, 0xFFFF, sum = 0
6801 22:18:12.702489 9, 0xFFFF, sum = 0
6802 22:18:12.706109 10, 0xFFFF, sum = 0
6803 22:18:12.706206 11, 0xFFFF, sum = 0
6804 22:18:12.709464 12, 0xFFFF, sum = 0
6805 22:18:12.709560 13, 0x0, sum = 1
6806 22:18:12.712599 14, 0x0, sum = 2
6807 22:18:12.712689 15, 0x0, sum = 3
6808 22:18:12.715608 16, 0x0, sum = 4
6809 22:18:12.715699 best_step = 14
6810 22:18:12.715767
6811 22:18:12.715830 ==
6812 22:18:12.718919 Dram Type= 6, Freq= 0, CH_1, rank 0
6813 22:18:12.722418 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6814 22:18:12.725812 ==
6815 22:18:12.725906 RX Vref Scan: 1
6816 22:18:12.725973
6817 22:18:12.728961 RX Vref 0 -> 0, step: 1
6818 22:18:12.729043
6819 22:18:12.732942 RX Delay -343 -> 252, step: 8
6820 22:18:12.733026
6821 22:18:12.735526 Set Vref, RX VrefLevel [Byte0]: 49
6822 22:18:12.738789 [Byte1]: 53
6823 22:18:12.738880
6824 22:18:12.742643 Final RX Vref Byte 0 = 49 to rank0
6825 22:18:12.745373 Final RX Vref Byte 1 = 53 to rank0
6826 22:18:12.748505 Final RX Vref Byte 0 = 49 to rank1
6827 22:18:12.752171 Final RX Vref Byte 1 = 53 to rank1==
6828 22:18:12.755595 Dram Type= 6, Freq= 0, CH_1, rank 0
6829 22:18:12.759035 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6830 22:18:12.761957 ==
6831 22:18:12.762046 DQS Delay:
6832 22:18:12.762114 DQS0 = 44, DQS1 = 52
6833 22:18:12.765145 DQM Delay:
6834 22:18:12.765228 DQM0 = 10, DQM1 = 10
6835 22:18:12.768762 DQ Delay:
6836 22:18:12.768845 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =12
6837 22:18:12.771783 DQ4 =4, DQ5 =20, DQ6 =24, DQ7 =4
6838 22:18:12.774961 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =4
6839 22:18:12.778676 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =16
6840 22:18:12.778764
6841 22:18:12.778829
6842 22:18:12.788533 [DQSOSCAuto] RK0, (LSB)MR18= 0x658b, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 397 ps
6843 22:18:12.791924 CH1 RK0: MR19=C0C, MR18=658B
6844 22:18:12.797982 CH1_RK0: MR19=0xC0C, MR18=0x658B, DQSOSC=392, MR23=63, INC=384, DEC=256
6845 22:18:12.798094 ==
6846 22:18:12.801774 Dram Type= 6, Freq= 0, CH_1, rank 1
6847 22:18:12.804576 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6848 22:18:12.804665 ==
6849 22:18:12.808240 [Gating] SW mode calibration
6850 22:18:12.815708 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6851 22:18:12.821312 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6852 22:18:12.824492 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6853 22:18:12.827795 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6854 22:18:12.834441 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6855 22:18:12.837415 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6856 22:18:12.841158 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6857 22:18:12.847640 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6858 22:18:12.850983 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6859 22:18:12.854063 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6860 22:18:12.860647 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6861 22:18:12.860731 Total UI for P1: 0, mck2ui 16
6862 22:18:12.867135 best dqsien dly found for B0: ( 0, 14, 24)
6863 22:18:12.867218 Total UI for P1: 0, mck2ui 16
6864 22:18:12.870961 best dqsien dly found for B1: ( 0, 14, 24)
6865 22:18:12.877632 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6866 22:18:12.880589 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6867 22:18:12.880673
6868 22:18:12.884276 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6869 22:18:12.887271 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6870 22:18:12.890292 [Gating] SW calibration Done
6871 22:18:12.890377 ==
6872 22:18:12.893448 Dram Type= 6, Freq= 0, CH_1, rank 1
6873 22:18:12.897024 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6874 22:18:12.897109 ==
6875 22:18:12.900455 RX Vref Scan: 0
6876 22:18:12.900539
6877 22:18:12.900603 RX Vref 0 -> 0, step: 1
6878 22:18:12.900664
6879 22:18:12.903615 RX Delay -410 -> 252, step: 16
6880 22:18:12.910304 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6881 22:18:12.913344 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6882 22:18:12.916736 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6883 22:18:12.919691 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6884 22:18:12.927469 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6885 22:18:12.929658 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6886 22:18:12.933007 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6887 22:18:12.936325 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6888 22:18:12.942997 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6889 22:18:12.946636 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6890 22:18:12.949727 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6891 22:18:12.953017 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6892 22:18:12.959204 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6893 22:18:12.962919 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6894 22:18:12.966490 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6895 22:18:12.972382 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6896 22:18:12.972498 ==
6897 22:18:12.975659 Dram Type= 6, Freq= 0, CH_1, rank 1
6898 22:18:12.979210 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6899 22:18:12.979305 ==
6900 22:18:12.979374 DQS Delay:
6901 22:18:12.982361 DQS0 = 43, DQS1 = 51
6902 22:18:12.982451 DQM Delay:
6903 22:18:12.985571 DQM0 = 9, DQM1 = 14
6904 22:18:12.985657 DQ Delay:
6905 22:18:12.989007 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6906 22:18:12.992348 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =8
6907 22:18:12.995884 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6908 22:18:12.998793 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =24
6909 22:18:12.998887
6910 22:18:12.998952
6911 22:18:12.999011 ==
6912 22:18:13.002272 Dram Type= 6, Freq= 0, CH_1, rank 1
6913 22:18:13.005461 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6914 22:18:13.005550 ==
6915 22:18:13.005617
6916 22:18:13.005676
6917 22:18:13.009310 TX Vref Scan disable
6918 22:18:13.011990 == TX Byte 0 ==
6919 22:18:13.015622 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6920 22:18:13.018742 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6921 22:18:13.018824 == TX Byte 1 ==
6922 22:18:13.025658 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6923 22:18:13.028479 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6924 22:18:13.028565 ==
6925 22:18:13.031978 Dram Type= 6, Freq= 0, CH_1, rank 1
6926 22:18:13.035193 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6927 22:18:13.035278 ==
6928 22:18:13.038328
6929 22:18:13.038411
6930 22:18:13.038476 TX Vref Scan disable
6931 22:18:13.042141 == TX Byte 0 ==
6932 22:18:13.044887 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6933 22:18:13.048356 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6934 22:18:13.051676 == TX Byte 1 ==
6935 22:18:13.054981 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6936 22:18:13.058222 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6937 22:18:13.058324
6938 22:18:13.058396 [DATLAT]
6939 22:18:13.061420 Freq=400, CH1 RK1
6940 22:18:13.061509
6941 22:18:13.064541 DATLAT Default: 0xe
6942 22:18:13.064631 0, 0xFFFF, sum = 0
6943 22:18:13.067949 1, 0xFFFF, sum = 0
6944 22:18:13.068081 2, 0xFFFF, sum = 0
6945 22:18:13.071565 3, 0xFFFF, sum = 0
6946 22:18:13.071655 4, 0xFFFF, sum = 0
6947 22:18:13.074601 5, 0xFFFF, sum = 0
6948 22:18:13.074691 6, 0xFFFF, sum = 0
6949 22:18:13.077773 7, 0xFFFF, sum = 0
6950 22:18:13.077864 8, 0xFFFF, sum = 0
6951 22:18:13.081144 9, 0xFFFF, sum = 0
6952 22:18:13.081234 10, 0xFFFF, sum = 0
6953 22:18:13.084570 11, 0xFFFF, sum = 0
6954 22:18:13.084665 12, 0xFFFF, sum = 0
6955 22:18:13.087906 13, 0x0, sum = 1
6956 22:18:13.087997 14, 0x0, sum = 2
6957 22:18:13.090829 15, 0x0, sum = 3
6958 22:18:13.090919 16, 0x0, sum = 4
6959 22:18:13.094448 best_step = 14
6960 22:18:13.094538
6961 22:18:13.094604 ==
6962 22:18:13.097467 Dram Type= 6, Freq= 0, CH_1, rank 1
6963 22:18:13.101092 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6964 22:18:13.101180 ==
6965 22:18:13.103921 RX Vref Scan: 0
6966 22:18:13.104005
6967 22:18:13.104110 RX Vref 0 -> 0, step: 1
6968 22:18:13.104175
6969 22:18:13.107091 RX Delay -343 -> 252, step: 8
6970 22:18:13.115394 iDelay=217, Bit 0, Center -32 (-271 ~ 208) 480
6971 22:18:13.118844 iDelay=217, Bit 1, Center -40 (-287 ~ 208) 496
6972 22:18:13.121978 iDelay=217, Bit 2, Center -48 (-295 ~ 200) 496
6973 22:18:13.128599 iDelay=217, Bit 3, Center -40 (-287 ~ 208) 496
6974 22:18:13.131983 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6975 22:18:13.135208 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6976 22:18:13.138738 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6977 22:18:13.145077 iDelay=217, Bit 7, Center -40 (-287 ~ 208) 496
6978 22:18:13.148475 iDelay=217, Bit 8, Center -52 (-295 ~ 192) 488
6979 22:18:13.151459 iDelay=217, Bit 9, Center -52 (-295 ~ 192) 488
6980 22:18:13.155454 iDelay=217, Bit 10, Center -40 (-287 ~ 208) 496
6981 22:18:13.161837 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6982 22:18:13.164995 iDelay=217, Bit 12, Center -32 (-271 ~ 208) 480
6983 22:18:13.168391 iDelay=217, Bit 13, Center -36 (-279 ~ 208) 488
6984 22:18:13.171423 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6985 22:18:13.177957 iDelay=217, Bit 15, Center -32 (-279 ~ 216) 496
6986 22:18:13.178042 ==
6987 22:18:13.181458 Dram Type= 6, Freq= 0, CH_1, rank 1
6988 22:18:13.184793 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6989 22:18:13.184877 ==
6990 22:18:13.184943 DQS Delay:
6991 22:18:13.188799 DQS0 = 48, DQS1 = 52
6992 22:18:13.188884 DQM Delay:
6993 22:18:13.191422 DQM0 = 11, DQM1 = 10
6994 22:18:13.191506 DQ Delay:
6995 22:18:13.194317 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6996 22:18:13.197664 DQ4 =12, DQ5 =20, DQ6 =20, DQ7 =8
6997 22:18:13.201143 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =0
6998 22:18:13.204419 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =20
6999 22:18:13.204506
7000 22:18:13.204572
7001 22:18:13.214283 [DQSOSCAuto] RK1, (LSB)MR18= 0x6aa3, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps
7002 22:18:13.214372 CH1 RK1: MR19=C0C, MR18=6AA3
7003 22:18:13.220776 CH1_RK1: MR19=0xC0C, MR18=0x6AA3, DQSOSC=389, MR23=63, INC=390, DEC=260
7004 22:18:13.224057 [RxdqsGatingPostProcess] freq 400
7005 22:18:13.230622 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7006 22:18:13.233689 best DQS0 dly(2T, 0.5T) = (0, 10)
7007 22:18:13.236995 best DQS1 dly(2T, 0.5T) = (0, 10)
7008 22:18:13.240588 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7009 22:18:13.243898 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7010 22:18:13.247355 best DQS0 dly(2T, 0.5T) = (0, 10)
7011 22:18:13.250614 best DQS1 dly(2T, 0.5T) = (0, 10)
7012 22:18:13.253736 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7013 22:18:13.256784 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7014 22:18:13.260133 Pre-setting of DQS Precalculation
7015 22:18:13.263905 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7016 22:18:13.270095 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7017 22:18:13.276670 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7018 22:18:13.279922
7019 22:18:13.280035
7020 22:18:13.280117 [Calibration Summary] 800 Mbps
7021 22:18:13.282665 CH 0, Rank 0
7022 22:18:13.282796 SW Impedance : PASS
7023 22:18:13.286145 DUTY Scan : NO K
7024 22:18:13.289833 ZQ Calibration : PASS
7025 22:18:13.289938 Jitter Meter : NO K
7026 22:18:13.292571 CBT Training : PASS
7027 22:18:13.295980 Write leveling : PASS
7028 22:18:13.296130 RX DQS gating : PASS
7029 22:18:13.299321 RX DQ/DQS(RDDQC) : PASS
7030 22:18:13.302584 TX DQ/DQS : PASS
7031 22:18:13.302666 RX DATLAT : PASS
7032 22:18:13.305940 RX DQ/DQS(Engine): PASS
7033 22:18:13.309351 TX OE : NO K
7034 22:18:13.309433 All Pass.
7035 22:18:13.309498
7036 22:18:13.309558 CH 0, Rank 1
7037 22:18:13.312402 SW Impedance : PASS
7038 22:18:13.315659 DUTY Scan : NO K
7039 22:18:13.315741 ZQ Calibration : PASS
7040 22:18:13.319284 Jitter Meter : NO K
7041 22:18:13.322292 CBT Training : PASS
7042 22:18:13.322375 Write leveling : NO K
7043 22:18:13.325702 RX DQS gating : PASS
7044 22:18:13.329163 RX DQ/DQS(RDDQC) : PASS
7045 22:18:13.329247 TX DQ/DQS : PASS
7046 22:18:13.332486 RX DATLAT : PASS
7047 22:18:13.335486 RX DQ/DQS(Engine): PASS
7048 22:18:13.335569 TX OE : NO K
7049 22:18:13.335636 All Pass.
7050 22:18:13.339002
7051 22:18:13.339085 CH 1, Rank 0
7052 22:18:13.342225 SW Impedance : PASS
7053 22:18:13.342323 DUTY Scan : NO K
7054 22:18:13.345384 ZQ Calibration : PASS
7055 22:18:13.348657 Jitter Meter : NO K
7056 22:18:13.348740 CBT Training : PASS
7057 22:18:13.352619 Write leveling : PASS
7058 22:18:13.352703 RX DQS gating : PASS
7059 22:18:13.355240 RX DQ/DQS(RDDQC) : PASS
7060 22:18:13.358943 TX DQ/DQS : PASS
7061 22:18:13.359028 RX DATLAT : PASS
7062 22:18:13.362260 RX DQ/DQS(Engine): PASS
7063 22:18:13.365386 TX OE : NO K
7064 22:18:13.365472 All Pass.
7065 22:18:13.365538
7066 22:18:13.365598 CH 1, Rank 1
7067 22:18:13.368413 SW Impedance : PASS
7068 22:18:13.371688 DUTY Scan : NO K
7069 22:18:13.371771 ZQ Calibration : PASS
7070 22:18:13.375493 Jitter Meter : NO K
7071 22:18:13.378250 CBT Training : PASS
7072 22:18:13.378363 Write leveling : NO K
7073 22:18:13.381672 RX DQS gating : PASS
7074 22:18:13.384744 RX DQ/DQS(RDDQC) : PASS
7075 22:18:13.384834 TX DQ/DQS : PASS
7076 22:18:13.388300 RX DATLAT : PASS
7077 22:18:13.391446 RX DQ/DQS(Engine): PASS
7078 22:18:13.391532 TX OE : NO K
7079 22:18:13.395077 All Pass.
7080 22:18:13.395164
7081 22:18:13.395231 DramC Write-DBI off
7082 22:18:13.398865 PER_BANK_REFRESH: Hybrid Mode
7083 22:18:13.401543 TX_TRACKING: ON
7084 22:18:13.408171 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7085 22:18:13.411383 [FAST_K] Save calibration result to emmc
7086 22:18:13.414724 dramc_set_vcore_voltage set vcore to 725000
7087 22:18:13.417752 Read voltage for 1600, 0
7088 22:18:13.417838 Vio18 = 0
7089 22:18:13.421278 Vcore = 725000
7090 22:18:13.421363 Vdram = 0
7091 22:18:13.421430 Vddq = 0
7092 22:18:13.424310 Vmddr = 0
7093 22:18:13.427850 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7094 22:18:13.434227 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7095 22:18:13.437250 MEM_TYPE=3, freq_sel=13
7096 22:18:13.437340 sv_algorithm_assistance_LP4_3733
7097 22:18:13.444277 ============ PULL DRAM RESETB DOWN ============
7098 22:18:13.447086 ========== PULL DRAM RESETB DOWN end =========
7099 22:18:13.450822 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7100 22:18:13.454003 ===================================
7101 22:18:13.457199 LPDDR4 DRAM CONFIGURATION
7102 22:18:13.460539 ===================================
7103 22:18:13.464170 EX_ROW_EN[0] = 0x0
7104 22:18:13.464254 EX_ROW_EN[1] = 0x0
7105 22:18:13.467212 LP4Y_EN = 0x0
7106 22:18:13.467296 WORK_FSP = 0x1
7107 22:18:13.470309 WL = 0x5
7108 22:18:13.470397 RL = 0x5
7109 22:18:13.473774 BL = 0x2
7110 22:18:13.473858 RPST = 0x0
7111 22:18:13.477152 RD_PRE = 0x0
7112 22:18:13.477235 WR_PRE = 0x1
7113 22:18:13.480243 WR_PST = 0x1
7114 22:18:13.483580 DBI_WR = 0x0
7115 22:18:13.483663 DBI_RD = 0x0
7116 22:18:13.487151 OTF = 0x1
7117 22:18:13.490210 ===================================
7118 22:18:13.493523 ===================================
7119 22:18:13.493608 ANA top config
7120 22:18:13.496877 ===================================
7121 22:18:13.499948 DLL_ASYNC_EN = 0
7122 22:18:13.503055 ALL_SLAVE_EN = 0
7123 22:18:13.503138 NEW_RANK_MODE = 1
7124 22:18:13.506552 DLL_IDLE_MODE = 1
7125 22:18:13.509656 LP45_APHY_COMB_EN = 1
7126 22:18:13.512820 TX_ODT_DIS = 0
7127 22:18:13.516360 NEW_8X_MODE = 1
7128 22:18:13.519734 ===================================
7129 22:18:13.522901 ===================================
7130 22:18:13.522983 data_rate = 3200
7131 22:18:13.526008 CKR = 1
7132 22:18:13.529351 DQ_P2S_RATIO = 8
7133 22:18:13.533082 ===================================
7134 22:18:13.535837 CA_P2S_RATIO = 8
7135 22:18:13.539274 DQ_CA_OPEN = 0
7136 22:18:13.542346 DQ_SEMI_OPEN = 0
7137 22:18:13.542459 CA_SEMI_OPEN = 0
7138 22:18:13.545766 CA_FULL_RATE = 0
7139 22:18:13.549342 DQ_CKDIV4_EN = 0
7140 22:18:13.552318 CA_CKDIV4_EN = 0
7141 22:18:13.555571 CA_PREDIV_EN = 0
7142 22:18:13.559308 PH8_DLY = 12
7143 22:18:13.562059 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7144 22:18:13.562143 DQ_AAMCK_DIV = 4
7145 22:18:13.565958 CA_AAMCK_DIV = 4
7146 22:18:13.568625 CA_ADMCK_DIV = 4
7147 22:18:13.571977 DQ_TRACK_CA_EN = 0
7148 22:18:13.575550 CA_PICK = 1600
7149 22:18:13.578697 CA_MCKIO = 1600
7150 22:18:13.581976 MCKIO_SEMI = 0
7151 22:18:13.582065 PLL_FREQ = 3068
7152 22:18:13.585559 DQ_UI_PI_RATIO = 32
7153 22:18:13.588560 CA_UI_PI_RATIO = 0
7154 22:18:13.591768 ===================================
7155 22:18:13.594814 ===================================
7156 22:18:13.598425 memory_type:LPDDR4
7157 22:18:13.601770 GP_NUM : 10
7158 22:18:13.601862 SRAM_EN : 1
7159 22:18:13.605121 MD32_EN : 0
7160 22:18:13.609007 ===================================
7161 22:18:13.611537 [ANA_INIT] >>>>>>>>>>>>>>
7162 22:18:13.611620 <<<<<< [CONFIGURE PHASE]: ANA_TX
7163 22:18:13.614688 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7164 22:18:13.617963 ===================================
7165 22:18:13.621634 data_rate = 3200,PCW = 0X7600
7166 22:18:13.624874 ===================================
7167 22:18:13.627846 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7168 22:18:13.635017 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7169 22:18:13.641076 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7170 22:18:13.644258 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7171 22:18:13.647631 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7172 22:18:13.651121 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7173 22:18:13.654413 [ANA_INIT] flow start
7174 22:18:13.654497 [ANA_INIT] PLL >>>>>>>>
7175 22:18:13.658049 [ANA_INIT] PLL <<<<<<<<
7176 22:18:13.660756 [ANA_INIT] MIDPI >>>>>>>>
7177 22:18:13.664509 [ANA_INIT] MIDPI <<<<<<<<
7178 22:18:13.664595 [ANA_INIT] DLL >>>>>>>>
7179 22:18:13.667565 [ANA_INIT] DLL <<<<<<<<
7180 22:18:13.667652 [ANA_INIT] flow end
7181 22:18:13.674463 ============ LP4 DIFF to SE enter ============
7182 22:18:13.677490 ============ LP4 DIFF to SE exit ============
7183 22:18:13.681202 [ANA_INIT] <<<<<<<<<<<<<
7184 22:18:13.684307 [Flow] Enable top DCM control >>>>>
7185 22:18:13.687546 [Flow] Enable top DCM control <<<<<
7186 22:18:13.690417 Enable DLL master slave shuffle
7187 22:18:13.693991 ==============================================================
7188 22:18:13.697088 Gating Mode config
7189 22:18:13.703904 ==============================================================
7190 22:18:13.704016 Config description:
7191 22:18:13.713292 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7192 22:18:13.719958 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7193 22:18:13.726708 SELPH_MODE 0: By rank 1: By Phase
7194 22:18:13.730235 ==============================================================
7195 22:18:13.733778 GAT_TRACK_EN = 1
7196 22:18:13.736573 RX_GATING_MODE = 2
7197 22:18:13.739889 RX_GATING_TRACK_MODE = 2
7198 22:18:13.743371 SELPH_MODE = 1
7199 22:18:13.746277 PICG_EARLY_EN = 1
7200 22:18:13.749687 VALID_LAT_VALUE = 1
7201 22:18:13.752838 ==============================================================
7202 22:18:13.756485 Enter into Gating configuration >>>>
7203 22:18:13.759922 Exit from Gating configuration <<<<
7204 22:18:13.762838 Enter into DVFS_PRE_config >>>>>
7205 22:18:13.775990 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7206 22:18:13.779923 Exit from DVFS_PRE_config <<<<<
7207 22:18:13.782375 Enter into PICG configuration >>>>
7208 22:18:13.785754 Exit from PICG configuration <<<<
7209 22:18:13.785839 [RX_INPUT] configuration >>>>>
7210 22:18:13.789477 [RX_INPUT] configuration <<<<<
7211 22:18:13.795732 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7212 22:18:13.802675 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7213 22:18:13.805969 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7214 22:18:13.811995 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7215 22:18:13.818646 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7216 22:18:13.825074 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7217 22:18:13.828507 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7218 22:18:13.831976 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7219 22:18:13.838516 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7220 22:18:13.841947 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7221 22:18:13.845061 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7222 22:18:13.851833 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7223 22:18:13.854987 ===================================
7224 22:18:13.855072 LPDDR4 DRAM CONFIGURATION
7225 22:18:13.858484 ===================================
7226 22:18:13.861861 EX_ROW_EN[0] = 0x0
7227 22:18:13.861945 EX_ROW_EN[1] = 0x0
7228 22:18:13.864596 LP4Y_EN = 0x0
7229 22:18:13.868299 WORK_FSP = 0x1
7230 22:18:13.868383 WL = 0x5
7231 22:18:13.871517 RL = 0x5
7232 22:18:13.871601 BL = 0x2
7233 22:18:13.874746 RPST = 0x0
7234 22:18:13.874829 RD_PRE = 0x0
7235 22:18:13.878167 WR_PRE = 0x1
7236 22:18:13.878251 WR_PST = 0x1
7237 22:18:13.881317 DBI_WR = 0x0
7238 22:18:13.881400 DBI_RD = 0x0
7239 22:18:13.884832 OTF = 0x1
7240 22:18:13.887678 ===================================
7241 22:18:13.891263 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7242 22:18:13.894635 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7243 22:18:13.901050 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7244 22:18:13.904025 ===================================
7245 22:18:13.904147 LPDDR4 DRAM CONFIGURATION
7246 22:18:13.907510 ===================================
7247 22:18:13.910518 EX_ROW_EN[0] = 0x10
7248 22:18:13.913820 EX_ROW_EN[1] = 0x0
7249 22:18:13.913905 LP4Y_EN = 0x0
7250 22:18:13.917161 WORK_FSP = 0x1
7251 22:18:13.917245 WL = 0x5
7252 22:18:13.920309 RL = 0x5
7253 22:18:13.920392 BL = 0x2
7254 22:18:13.923841 RPST = 0x0
7255 22:18:13.924002 RD_PRE = 0x0
7256 22:18:13.927070 WR_PRE = 0x1
7257 22:18:13.927228 WR_PST = 0x1
7258 22:18:13.930097 DBI_WR = 0x0
7259 22:18:13.930183 DBI_RD = 0x0
7260 22:18:13.933498 OTF = 0x1
7261 22:18:13.937166 ===================================
7262 22:18:13.943986 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7263 22:18:13.944326 ==
7264 22:18:13.946782 Dram Type= 6, Freq= 0, CH_0, rank 0
7265 22:18:13.950554 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7266 22:18:13.950803 ==
7267 22:18:13.953637 [Duty_Offset_Calibration]
7268 22:18:13.953884 B0:2 B1:0 CA:4
7269 22:18:13.954077
7270 22:18:13.956661 [DutyScan_Calibration_Flow] k_type=0
7271 22:18:13.967133
7272 22:18:13.967448 ==CLK 0==
7273 22:18:13.970198 Final CLK duty delay cell = -4
7274 22:18:13.973575 [-4] MAX Duty = 5031%(X100), DQS PI = 30
7275 22:18:13.977095 [-4] MIN Duty = 4813%(X100), DQS PI = 8
7276 22:18:13.980599 [-4] AVG Duty = 4922%(X100)
7277 22:18:13.980846
7278 22:18:13.983887 CH0 CLK Duty spec in!! Max-Min= 218%
7279 22:18:13.987294 [DutyScan_Calibration_Flow] ====Done====
7280 22:18:13.987541
7281 22:18:13.990119 [DutyScan_Calibration_Flow] k_type=1
7282 22:18:14.007147
7283 22:18:14.007286 ==DQS 0 ==
7284 22:18:14.010574 Final DQS duty delay cell = 0
7285 22:18:14.013595 [0] MAX Duty = 5249%(X100), DQS PI = 38
7286 22:18:14.017245 [0] MIN Duty = 5093%(X100), DQS PI = 14
7287 22:18:14.020242 [0] AVG Duty = 5171%(X100)
7288 22:18:14.020350
7289 22:18:14.020433 ==DQS 1 ==
7290 22:18:14.023754 Final DQS duty delay cell = 0
7291 22:18:14.026983 [0] MAX Duty = 5187%(X100), DQS PI = 0
7292 22:18:14.030260 [0] MIN Duty = 4969%(X100), DQS PI = 12
7293 22:18:14.033497 [0] AVG Duty = 5078%(X100)
7294 22:18:14.033592
7295 22:18:14.036500 CH0 DQS 0 Duty spec in!! Max-Min= 156%
7296 22:18:14.036582
7297 22:18:14.039779 CH0 DQS 1 Duty spec in!! Max-Min= 218%
7298 22:18:14.043666 [DutyScan_Calibration_Flow] ====Done====
7299 22:18:14.043748
7300 22:18:14.046267 [DutyScan_Calibration_Flow] k_type=3
7301 22:18:14.064270
7302 22:18:14.064351 ==DQM 0 ==
7303 22:18:14.067779 Final DQM duty delay cell = 0
7304 22:18:14.070808 [0] MAX Duty = 5124%(X100), DQS PI = 20
7305 22:18:14.074434 [0] MIN Duty = 4875%(X100), DQS PI = 54
7306 22:18:14.077626 [0] AVG Duty = 4999%(X100)
7307 22:18:14.077708
7308 22:18:14.077773 ==DQM 1 ==
7309 22:18:14.080749 Final DQM duty delay cell = 0
7310 22:18:14.084066 [0] MAX Duty = 4969%(X100), DQS PI = 0
7311 22:18:14.087236 [0] MIN Duty = 4844%(X100), DQS PI = 10
7312 22:18:14.090461 [0] AVG Duty = 4906%(X100)
7313 22:18:14.090543
7314 22:18:14.094169 CH0 DQM 0 Duty spec in!! Max-Min= 249%
7315 22:18:14.094251
7316 22:18:14.097466 CH0 DQM 1 Duty spec in!! Max-Min= 125%
7317 22:18:14.100574 [DutyScan_Calibration_Flow] ====Done====
7318 22:18:14.100656
7319 22:18:14.104222 [DutyScan_Calibration_Flow] k_type=2
7320 22:18:14.121350
7321 22:18:14.121432 ==DQ 0 ==
7322 22:18:14.124683 Final DQ duty delay cell = 0
7323 22:18:14.128411 [0] MAX Duty = 5124%(X100), DQS PI = 20
7324 22:18:14.131334 [0] MIN Duty = 4969%(X100), DQS PI = 10
7325 22:18:14.131417 [0] AVG Duty = 5046%(X100)
7326 22:18:14.134644
7327 22:18:14.134726 ==DQ 1 ==
7328 22:18:14.138337 Final DQ duty delay cell = 0
7329 22:18:14.141214 [0] MAX Duty = 5187%(X100), DQS PI = 2
7330 22:18:14.144622 [0] MIN Duty = 4938%(X100), DQS PI = 12
7331 22:18:14.144704 [0] AVG Duty = 5062%(X100)
7332 22:18:14.147960
7333 22:18:14.151315 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7334 22:18:14.151397
7335 22:18:14.154529 CH0 DQ 1 Duty spec in!! Max-Min= 249%
7336 22:18:14.157978 [DutyScan_Calibration_Flow] ====Done====
7337 22:18:14.158060 ==
7338 22:18:14.160900 Dram Type= 6, Freq= 0, CH_1, rank 0
7339 22:18:14.164609 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7340 22:18:14.164691 ==
7341 22:18:14.167516 [Duty_Offset_Calibration]
7342 22:18:14.167598 B0:0 B1:-1 CA:3
7343 22:18:14.167663
7344 22:18:14.170893 [DutyScan_Calibration_Flow] k_type=0
7345 22:18:14.181159
7346 22:18:14.181241 ==CLK 0==
7347 22:18:14.184234 Final CLK duty delay cell = -4
7348 22:18:14.187350 [-4] MAX Duty = 5000%(X100), DQS PI = 4
7349 22:18:14.191192 [-4] MIN Duty = 4844%(X100), DQS PI = 38
7350 22:18:14.193901 [-4] AVG Duty = 4922%(X100)
7351 22:18:14.193983
7352 22:18:14.197294 CH1 CLK Duty spec in!! Max-Min= 156%
7353 22:18:14.200911 [DutyScan_Calibration_Flow] ====Done====
7354 22:18:14.200994
7355 22:18:14.204569 [DutyScan_Calibration_Flow] k_type=1
7356 22:18:14.220426
7357 22:18:14.220508 ==DQS 0 ==
7358 22:18:14.223403 Final DQS duty delay cell = 0
7359 22:18:14.226830 [0] MAX Duty = 5250%(X100), DQS PI = 30
7360 22:18:14.229954 [0] MIN Duty = 4907%(X100), DQS PI = 60
7361 22:18:14.233252 [0] AVG Duty = 5078%(X100)
7362 22:18:14.233343
7363 22:18:14.233407 ==DQS 1 ==
7364 22:18:14.236393 Final DQS duty delay cell = -4
7365 22:18:14.239975 [-4] MAX Duty = 5031%(X100), DQS PI = 30
7366 22:18:14.243222 [-4] MIN Duty = 4844%(X100), DQS PI = 62
7367 22:18:14.247107 [-4] AVG Duty = 4937%(X100)
7368 22:18:14.247215
7369 22:18:14.249990 CH1 DQS 0 Duty spec in!! Max-Min= 343%
7370 22:18:14.250071
7371 22:18:14.253250 CH1 DQS 1 Duty spec in!! Max-Min= 187%
7372 22:18:14.256851 [DutyScan_Calibration_Flow] ====Done====
7373 22:18:14.256930
7374 22:18:14.259644 [DutyScan_Calibration_Flow] k_type=3
7375 22:18:14.277505
7376 22:18:14.277584 ==DQM 0 ==
7377 22:18:14.280902 Final DQM duty delay cell = 0
7378 22:18:14.283863 [0] MAX Duty = 5062%(X100), DQS PI = 30
7379 22:18:14.287496 [0] MIN Duty = 4782%(X100), DQS PI = 38
7380 22:18:14.290864 [0] AVG Duty = 4922%(X100)
7381 22:18:14.290944
7382 22:18:14.291007 ==DQM 1 ==
7383 22:18:14.294018 Final DQM duty delay cell = 0
7384 22:18:14.297233 [0] MAX Duty = 5000%(X100), DQS PI = 30
7385 22:18:14.300496 [0] MIN Duty = 4813%(X100), DQS PI = 12
7386 22:18:14.303830 [0] AVG Duty = 4906%(X100)
7387 22:18:14.303910
7388 22:18:14.307256 CH1 DQM 0 Duty spec in!! Max-Min= 280%
7389 22:18:14.307336
7390 22:18:14.310442 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7391 22:18:14.313570 [DutyScan_Calibration_Flow] ====Done====
7392 22:18:14.313650
7393 22:18:14.316544 [DutyScan_Calibration_Flow] k_type=2
7394 22:18:14.333614
7395 22:18:14.333693 ==DQ 0 ==
7396 22:18:14.336911 Final DQ duty delay cell = -4
7397 22:18:14.340001 [-4] MAX Duty = 4969%(X100), DQS PI = 30
7398 22:18:14.343255 [-4] MIN Duty = 4813%(X100), DQS PI = 36
7399 22:18:14.346882 [-4] AVG Duty = 4891%(X100)
7400 22:18:14.346962
7401 22:18:14.347025 ==DQ 1 ==
7402 22:18:14.350016 Final DQ duty delay cell = 0
7403 22:18:14.353690 [0] MAX Duty = 5031%(X100), DQS PI = 30
7404 22:18:14.356403 [0] MIN Duty = 4844%(X100), DQS PI = 60
7405 22:18:14.360011 [0] AVG Duty = 4937%(X100)
7406 22:18:14.360116
7407 22:18:14.362938 CH1 DQ 0 Duty spec in!! Max-Min= 156%
7408 22:18:14.363017
7409 22:18:14.366221 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7410 22:18:14.369377 [DutyScan_Calibration_Flow] ====Done====
7411 22:18:14.373036 nWR fixed to 30
7412 22:18:14.376426 [ModeRegInit_LP4] CH0 RK0
7413 22:18:14.376505 [ModeRegInit_LP4] CH0 RK1
7414 22:18:14.379983 [ModeRegInit_LP4] CH1 RK0
7415 22:18:14.382808 [ModeRegInit_LP4] CH1 RK1
7416 22:18:14.382887 match AC timing 5
7417 22:18:14.389421 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7418 22:18:14.393067 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7419 22:18:14.396316 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7420 22:18:14.402725 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7421 22:18:14.406093 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7422 22:18:14.409424 [MiockJmeterHQA]
7423 22:18:14.409506
7424 22:18:14.412658 [DramcMiockJmeter] u1RxGatingPI = 0
7425 22:18:14.412739 0 : 4255, 4027
7426 22:18:14.412805 4 : 4363, 4137
7427 22:18:14.415660 8 : 4252, 4027
7428 22:18:14.415743 12 : 4255, 4029
7429 22:18:14.418859 16 : 4252, 4027
7430 22:18:14.418943 20 : 4252, 4027
7431 22:18:14.422166 24 : 4257, 4031
7432 22:18:14.422249 28 : 4252, 4027
7433 22:18:14.422316 32 : 4363, 4138
7434 22:18:14.425457 36 : 4252, 4027
7435 22:18:14.425541 40 : 4252, 4027
7436 22:18:14.428859 44 : 4254, 4029
7437 22:18:14.428941 48 : 4254, 4029
7438 22:18:14.431934 52 : 4363, 4138
7439 22:18:14.432019 56 : 4252, 4027
7440 22:18:14.435779 60 : 4363, 4140
7441 22:18:14.435877 64 : 4253, 4027
7442 22:18:14.435944 68 : 4250, 4026
7443 22:18:14.438602 72 : 4250, 4027
7444 22:18:14.438701 76 : 4249, 4027
7445 22:18:14.441729 80 : 4361, 4137
7446 22:18:14.441817 84 : 4250, 4027
7447 22:18:14.445133 88 : 4360, 4137
7448 22:18:14.445216 92 : 4363, 4140
7449 22:18:14.448375 96 : 4250, 2967
7450 22:18:14.448458 100 : 4252, 0
7451 22:18:14.448524 104 : 4253, 0
7452 22:18:14.451625 108 : 4252, 0
7453 22:18:14.451722 112 : 4250, 0
7454 22:18:14.455055 116 : 4252, 0
7455 22:18:14.455138 120 : 4360, 0
7456 22:18:14.455204 124 : 4366, 0
7457 22:18:14.458965 128 : 4363, 0
7458 22:18:14.459048 132 : 4249, 0
7459 22:18:14.461678 136 : 4250, 0
7460 22:18:14.461826 140 : 4363, 0
7461 22:18:14.461894 144 : 4249, 0
7462 22:18:14.465211 148 : 4250, 0
7463 22:18:14.465294 152 : 4360, 0
7464 22:18:14.465360 156 : 4250, 0
7465 22:18:14.468305 160 : 4250, 0
7466 22:18:14.468388 164 : 4250, 0
7467 22:18:14.471758 168 : 4254, 0
7468 22:18:14.471840 172 : 4360, 0
7469 22:18:14.471906 176 : 4250, 0
7470 22:18:14.475212 180 : 4250, 0
7471 22:18:14.475295 184 : 4250, 0
7472 22:18:14.478892 188 : 4361, 0
7473 22:18:14.478975 192 : 4250, 0
7474 22:18:14.479041 196 : 4249, 0
7475 22:18:14.481818 200 : 4250, 0
7476 22:18:14.481901 204 : 4250, 0
7477 22:18:14.485169 208 : 4252, 0
7478 22:18:14.485300 212 : 4250, 0
7479 22:18:14.485404 216 : 4250, 0
7480 22:18:14.488063 220 : 4254, 607
7481 22:18:14.488174 224 : 4360, 4115
7482 22:18:14.491614 228 : 4253, 4029
7483 22:18:14.491704 232 : 4252, 4029
7484 22:18:14.494994 236 : 4363, 4140
7485 22:18:14.495078 240 : 4361, 4137
7486 22:18:14.498293 244 : 4250, 4027
7487 22:18:14.498376 248 : 4250, 4027
7488 22:18:14.501501 252 : 4252, 4029
7489 22:18:14.501584 256 : 4250, 4026
7490 22:18:14.504846 260 : 4363, 4140
7491 22:18:14.504929 264 : 4250, 4027
7492 22:18:14.504995 268 : 4250, 4027
7493 22:18:14.507980 272 : 4250, 4026
7494 22:18:14.508135 276 : 4363, 4140
7495 22:18:14.511716 280 : 4361, 4137
7496 22:18:14.511829 284 : 4247, 4024
7497 22:18:14.514404 288 : 4363, 4140
7498 22:18:14.514486 292 : 4252, 4029
7499 22:18:14.517681 296 : 4250, 4027
7500 22:18:14.517764 300 : 4250, 4027
7501 22:18:14.521147 304 : 4252, 4029
7502 22:18:14.521232 308 : 4252, 4029
7503 22:18:14.524253 312 : 4363, 4140
7504 22:18:14.524338 316 : 4250, 4027
7505 22:18:14.527622 320 : 4249, 4027
7506 22:18:14.527733 324 : 4250, 4026
7507 22:18:14.530929 328 : 4363, 4140
7508 22:18:14.531014 332 : 4361, 4119
7509 22:18:14.531081 336 : 4250, 1990
7510 22:18:14.534117
7511 22:18:14.534200 MIOCK jitter meter ch=0
7512 22:18:14.534265
7513 22:18:14.537746 1T = (336-100) = 236 dly cells
7514 22:18:14.544145 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7515 22:18:14.544229 ==
7516 22:18:14.547601 Dram Type= 6, Freq= 0, CH_0, rank 0
7517 22:18:14.550972 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7518 22:18:14.551057 ==
7519 22:18:14.557209 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7520 22:18:14.561077 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7521 22:18:14.563797 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7522 22:18:14.570449 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7523 22:18:14.580391 [CA 0] Center 43 (13~74) winsize 62
7524 22:18:14.583140 [CA 1] Center 42 (12~73) winsize 62
7525 22:18:14.586737 [CA 2] Center 37 (8~67) winsize 60
7526 22:18:14.590313 [CA 3] Center 37 (8~67) winsize 60
7527 22:18:14.593161 [CA 4] Center 36 (6~66) winsize 61
7528 22:18:14.596204 [CA 5] Center 35 (5~66) winsize 62
7529 22:18:14.596288
7530 22:18:14.599693 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7531 22:18:14.599776
7532 22:18:14.606730 [CATrainingPosCal] consider 1 rank data
7533 22:18:14.606814 u2DelayCellTimex100 = 275/100 ps
7534 22:18:14.612974 CA0 delay=43 (13~74),Diff = 8 PI (28 cell)
7535 22:18:14.616406 CA1 delay=42 (12~73),Diff = 7 PI (24 cell)
7536 22:18:14.619910 CA2 delay=37 (8~67),Diff = 2 PI (7 cell)
7537 22:18:14.623268 CA3 delay=37 (8~67),Diff = 2 PI (7 cell)
7538 22:18:14.626297 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7539 22:18:14.629448 CA5 delay=35 (5~66),Diff = 0 PI (0 cell)
7540 22:18:14.629531
7541 22:18:14.632721 CA PerBit enable=1, Macro0, CA PI delay=35
7542 22:18:14.632804
7543 22:18:14.636716 [CBTSetCACLKResult] CA Dly = 35
7544 22:18:14.639339 CS Dly: 10 (0~41)
7545 22:18:14.642674 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7546 22:18:14.646078 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7547 22:18:14.646161 ==
7548 22:18:14.649614 Dram Type= 6, Freq= 0, CH_0, rank 1
7549 22:18:14.656134 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7550 22:18:14.656218 ==
7551 22:18:14.659674 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7552 22:18:14.662744 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7553 22:18:14.669341 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7554 22:18:14.675890 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7555 22:18:14.683512 [CA 0] Center 43 (13~74) winsize 62
7556 22:18:14.686960 [CA 1] Center 43 (13~73) winsize 61
7557 22:18:14.689848 [CA 2] Center 38 (9~68) winsize 60
7558 22:18:14.693381 [CA 3] Center 38 (9~68) winsize 60
7559 22:18:14.696647 [CA 4] Center 37 (7~67) winsize 61
7560 22:18:14.700297 [CA 5] Center 36 (6~66) winsize 61
7561 22:18:14.700378
7562 22:18:14.703471 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7563 22:18:14.703553
7564 22:18:14.706534 [CATrainingPosCal] consider 2 rank data
7565 22:18:14.709686 u2DelayCellTimex100 = 275/100 ps
7566 22:18:14.716152 CA0 delay=43 (13~74),Diff = 7 PI (24 cell)
7567 22:18:14.719773 CA1 delay=43 (13~73),Diff = 7 PI (24 cell)
7568 22:18:14.723471 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
7569 22:18:14.726333 CA3 delay=38 (9~67),Diff = 2 PI (7 cell)
7570 22:18:14.729719 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7571 22:18:14.732674 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7572 22:18:14.732754
7573 22:18:14.735949 CA PerBit enable=1, Macro0, CA PI delay=36
7574 22:18:14.736037
7575 22:18:14.739235 [CBTSetCACLKResult] CA Dly = 36
7576 22:18:14.742747 CS Dly: 11 (0~43)
7577 22:18:14.746292 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7578 22:18:14.749718 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7579 22:18:14.749799
7580 22:18:14.752592 ----->DramcWriteLeveling(PI) begin...
7581 22:18:14.752673 ==
7582 22:18:14.756355 Dram Type= 6, Freq= 0, CH_0, rank 0
7583 22:18:14.762559 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7584 22:18:14.762639 ==
7585 22:18:14.765906 Write leveling (Byte 0): 34 => 34
7586 22:18:14.769633 Write leveling (Byte 1): 24 => 24
7587 22:18:14.769713 DramcWriteLeveling(PI) end<-----
7588 22:18:14.772579
7589 22:18:14.772658 ==
7590 22:18:14.775465 Dram Type= 6, Freq= 0, CH_0, rank 0
7591 22:18:14.779108 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7592 22:18:14.779188 ==
7593 22:18:14.782078 [Gating] SW mode calibration
7594 22:18:14.788922 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7595 22:18:14.795619 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7596 22:18:14.798617 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7597 22:18:14.802813 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7598 22:18:14.808628 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7599 22:18:14.811984 1 4 12 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
7600 22:18:14.815118 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7601 22:18:14.821880 1 4 20 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)
7602 22:18:14.824812 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7603 22:18:14.828580 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7604 22:18:14.835267 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7605 22:18:14.838225 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7606 22:18:14.841352 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7607 22:18:14.847918 1 5 12 | B1->B0 | 3434 2a2a | 1 1 | (1 1) (0 0)
7608 22:18:14.851296 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
7609 22:18:14.854508 1 5 20 | B1->B0 | 2e2e 2323 | 0 0 | (0 0) (0 0)
7610 22:18:14.861590 1 5 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
7611 22:18:14.864728 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7612 22:18:14.867973 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7613 22:18:14.874557 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7614 22:18:14.877868 1 6 8 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
7615 22:18:14.881017 1 6 12 | B1->B0 | 2323 4141 | 0 0 | (0 0) (0 0)
7616 22:18:14.887491 1 6 16 | B1->B0 | 2626 4646 | 0 0 | (0 0) (0 0)
7617 22:18:14.890849 1 6 20 | B1->B0 | 3c3c 4646 | 1 0 | (0 0) (0 0)
7618 22:18:14.894356 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7619 22:18:14.900595 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7620 22:18:14.904239 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7621 22:18:14.907199 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7622 22:18:14.914105 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7623 22:18:14.917089 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7624 22:18:14.920573 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7625 22:18:14.927393 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7626 22:18:14.930763 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7627 22:18:14.933451 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7628 22:18:14.939917 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7629 22:18:14.943790 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7630 22:18:14.946912 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7631 22:18:14.953733 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7632 22:18:14.956882 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7633 22:18:14.960140 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7634 22:18:14.966441 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7635 22:18:14.970371 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7636 22:18:14.973036 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7637 22:18:14.979761 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7638 22:18:14.983576 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7639 22:18:14.986223 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7640 22:18:14.993181 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7641 22:18:14.993268 Total UI for P1: 0, mck2ui 16
7642 22:18:14.999530 best dqsien dly found for B0: ( 1, 9, 10)
7643 22:18:15.003020 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7644 22:18:15.006249 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7645 22:18:15.012668 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7646 22:18:15.012754 Total UI for P1: 0, mck2ui 16
7647 22:18:15.015922 best dqsien dly found for B1: ( 1, 9, 24)
7648 22:18:15.022733 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7649 22:18:15.026531 best DQS1 dly(MCK, UI, PI) = (1, 9, 24)
7650 22:18:15.026615
7651 22:18:15.029154 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7652 22:18:15.032657 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 24)
7653 22:18:15.035740 [Gating] SW calibration Done
7654 22:18:15.035848 ==
7655 22:18:15.039195 Dram Type= 6, Freq= 0, CH_0, rank 0
7656 22:18:15.042200 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7657 22:18:15.042299 ==
7658 22:18:15.045417 RX Vref Scan: 0
7659 22:18:15.045501
7660 22:18:15.045584 RX Vref 0 -> 0, step: 1
7661 22:18:15.049210
7662 22:18:15.049294 RX Delay 0 -> 252, step: 8
7663 22:18:15.051979 iDelay=192, Bit 0, Center 131 (80 ~ 183) 104
7664 22:18:15.058630 iDelay=192, Bit 1, Center 135 (80 ~ 191) 112
7665 22:18:15.061998 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
7666 22:18:15.065884 iDelay=192, Bit 3, Center 127 (72 ~ 183) 112
7667 22:18:15.068415 iDelay=192, Bit 4, Center 135 (80 ~ 191) 112
7668 22:18:15.075014 iDelay=192, Bit 5, Center 119 (64 ~ 175) 112
7669 22:18:15.078384 iDelay=192, Bit 6, Center 139 (88 ~ 191) 104
7670 22:18:15.081697 iDelay=192, Bit 7, Center 139 (88 ~ 191) 104
7671 22:18:15.085120 iDelay=192, Bit 8, Center 119 (64 ~ 175) 112
7672 22:18:15.088341 iDelay=192, Bit 9, Center 111 (56 ~ 167) 112
7673 22:18:15.094830 iDelay=192, Bit 10, Center 123 (72 ~ 175) 104
7674 22:18:15.098559 iDelay=192, Bit 11, Center 123 (72 ~ 175) 104
7675 22:18:15.101543 iDelay=192, Bit 12, Center 135 (80 ~ 191) 112
7676 22:18:15.104544 iDelay=192, Bit 13, Center 131 (80 ~ 183) 104
7677 22:18:15.108596 iDelay=192, Bit 14, Center 135 (80 ~ 191) 112
7678 22:18:15.114704 iDelay=192, Bit 15, Center 135 (80 ~ 191) 112
7679 22:18:15.114789 ==
7680 22:18:15.117846 Dram Type= 6, Freq= 0, CH_0, rank 0
7681 22:18:15.121386 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7682 22:18:15.121471 ==
7683 22:18:15.121555 DQS Delay:
7684 22:18:15.124418 DQS0 = 0, DQS1 = 0
7685 22:18:15.124532 DQM Delay:
7686 22:18:15.127743 DQM0 = 131, DQM1 = 126
7687 22:18:15.127826 DQ Delay:
7688 22:18:15.130854 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
7689 22:18:15.134589 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =139
7690 22:18:15.137800 DQ8 =119, DQ9 =111, DQ10 =123, DQ11 =123
7691 22:18:15.144673 DQ12 =135, DQ13 =131, DQ14 =135, DQ15 =135
7692 22:18:15.144757
7693 22:18:15.144841
7694 22:18:15.144921 ==
7695 22:18:15.147722 Dram Type= 6, Freq= 0, CH_0, rank 0
7696 22:18:15.150847 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7697 22:18:15.150931 ==
7698 22:18:15.151016
7699 22:18:15.151094
7700 22:18:15.154205 TX Vref Scan disable
7701 22:18:15.154289 == TX Byte 0 ==
7702 22:18:15.160960 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7703 22:18:15.164457 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7704 22:18:15.164541 == TX Byte 1 ==
7705 22:18:15.170459 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7706 22:18:15.173858 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7707 22:18:15.173942 ==
7708 22:18:15.177089 Dram Type= 6, Freq= 0, CH_0, rank 0
7709 22:18:15.180465 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7710 22:18:15.180550 ==
7711 22:18:15.197016
7712 22:18:15.200240 TX Vref early break, caculate TX vref
7713 22:18:15.203264 TX Vref=16, minBit 1, minWin=22, winSum=363
7714 22:18:15.206486 TX Vref=18, minBit 7, minWin=22, winSum=378
7715 22:18:15.209719 TX Vref=20, minBit 0, minWin=24, winSum=388
7716 22:18:15.213225 TX Vref=22, minBit 8, minWin=23, winSum=395
7717 22:18:15.216278 TX Vref=24, minBit 1, minWin=24, winSum=408
7718 22:18:15.222901 TX Vref=26, minBit 1, minWin=25, winSum=413
7719 22:18:15.226353 TX Vref=28, minBit 2, minWin=25, winSum=415
7720 22:18:15.230225 TX Vref=30, minBit 2, minWin=25, winSum=413
7721 22:18:15.233069 TX Vref=32, minBit 1, minWin=24, winSum=402
7722 22:18:15.236563 TX Vref=34, minBit 1, minWin=24, winSum=396
7723 22:18:15.242835 TX Vref=36, minBit 2, minWin=23, winSum=383
7724 22:18:15.246009 [TxChooseVref] Worse bit 2, Min win 25, Win sum 415, Final Vref 28
7725 22:18:15.246094
7726 22:18:15.249370 Final TX Range 0 Vref 28
7727 22:18:15.249454
7728 22:18:15.249538 ==
7729 22:18:15.252644 Dram Type= 6, Freq= 0, CH_0, rank 0
7730 22:18:15.256298 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7731 22:18:15.259382 ==
7732 22:18:15.259465
7733 22:18:15.259548
7734 22:18:15.259627 TX Vref Scan disable
7735 22:18:15.266534 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7736 22:18:15.266618 == TX Byte 0 ==
7737 22:18:15.269714 u2DelayCellOfst[0]=10 cells (3 PI)
7738 22:18:15.272733 u2DelayCellOfst[1]=14 cells (4 PI)
7739 22:18:15.276616 u2DelayCellOfst[2]=10 cells (3 PI)
7740 22:18:15.279438 u2DelayCellOfst[3]=10 cells (3 PI)
7741 22:18:15.282824 u2DelayCellOfst[4]=7 cells (2 PI)
7742 22:18:15.286086 u2DelayCellOfst[5]=0 cells (0 PI)
7743 22:18:15.289306 u2DelayCellOfst[6]=17 cells (5 PI)
7744 22:18:15.292334 u2DelayCellOfst[7]=17 cells (5 PI)
7745 22:18:15.295680 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7746 22:18:15.299278 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7747 22:18:15.302936 == TX Byte 1 ==
7748 22:18:15.305920 u2DelayCellOfst[8]=0 cells (0 PI)
7749 22:18:15.308952 u2DelayCellOfst[9]=0 cells (0 PI)
7750 22:18:15.312165 u2DelayCellOfst[10]=3 cells (1 PI)
7751 22:18:15.315467 u2DelayCellOfst[11]=0 cells (0 PI)
7752 22:18:15.318834 u2DelayCellOfst[12]=7 cells (2 PI)
7753 22:18:15.322316 u2DelayCellOfst[13]=7 cells (2 PI)
7754 22:18:15.325410 u2DelayCellOfst[14]=14 cells (4 PI)
7755 22:18:15.325499 u2DelayCellOfst[15]=10 cells (3 PI)
7756 22:18:15.331601 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
7757 22:18:15.334999 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7758 22:18:15.338522 DramC Write-DBI on
7759 22:18:15.338607 ==
7760 22:18:15.341622 Dram Type= 6, Freq= 0, CH_0, rank 0
7761 22:18:15.345131 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7762 22:18:15.345217 ==
7763 22:18:15.345303
7764 22:18:15.345384
7765 22:18:15.348468 TX Vref Scan disable
7766 22:18:15.351736 == TX Byte 0 ==
7767 22:18:15.355076 Update DQM dly =733 (2 ,6, 29) DQM OEN =(3 ,3)
7768 22:18:15.355161 == TX Byte 1 ==
7769 22:18:15.361287 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
7770 22:18:15.361373 DramC Write-DBI off
7771 22:18:15.361458
7772 22:18:15.361538 [DATLAT]
7773 22:18:15.364756 Freq=1600, CH0 RK0
7774 22:18:15.364842
7775 22:18:15.367824 DATLAT Default: 0xf
7776 22:18:15.367909 0, 0xFFFF, sum = 0
7777 22:18:15.371210 1, 0xFFFF, sum = 0
7778 22:18:15.371296 2, 0xFFFF, sum = 0
7779 22:18:15.374850 3, 0xFFFF, sum = 0
7780 22:18:15.374936 4, 0xFFFF, sum = 0
7781 22:18:15.377973 5, 0xFFFF, sum = 0
7782 22:18:15.378059 6, 0xFFFF, sum = 0
7783 22:18:15.381329 7, 0xFFFF, sum = 0
7784 22:18:15.381416 8, 0xFFFF, sum = 0
7785 22:18:15.384759 9, 0xFFFF, sum = 0
7786 22:18:15.384846 10, 0xFFFF, sum = 0
7787 22:18:15.388173 11, 0xFFFF, sum = 0
7788 22:18:15.388260 12, 0xFFFF, sum = 0
7789 22:18:15.391001 13, 0xFFFF, sum = 0
7790 22:18:15.391087 14, 0x0, sum = 1
7791 22:18:15.394449 15, 0x0, sum = 2
7792 22:18:15.394535 16, 0x0, sum = 3
7793 22:18:15.397703 17, 0x0, sum = 4
7794 22:18:15.397790 best_step = 15
7795 22:18:15.397874
7796 22:18:15.397954 ==
7797 22:18:15.400634 Dram Type= 6, Freq= 0, CH_0, rank 0
7798 22:18:15.407506 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7799 22:18:15.407593 ==
7800 22:18:15.407678 RX Vref Scan: 1
7801 22:18:15.407758
7802 22:18:15.410686 Set Vref Range= 24 -> 127
7803 22:18:15.410771
7804 22:18:15.414025 RX Vref 24 -> 127, step: 1
7805 22:18:15.414110
7806 22:18:15.418208 RX Delay 11 -> 252, step: 4
7807 22:18:15.418293
7808 22:18:15.420474 Set Vref, RX VrefLevel [Byte0]: 24
7809 22:18:15.423763 [Byte1]: 24
7810 22:18:15.423847
7811 22:18:15.427913 Set Vref, RX VrefLevel [Byte0]: 25
7812 22:18:15.430686 [Byte1]: 25
7813 22:18:15.430770
7814 22:18:15.433699 Set Vref, RX VrefLevel [Byte0]: 26
7815 22:18:15.437035 [Byte1]: 26
7816 22:18:15.440956
7817 22:18:15.441040 Set Vref, RX VrefLevel [Byte0]: 27
7818 22:18:15.443732 [Byte1]: 27
7819 22:18:15.448027
7820 22:18:15.448128 Set Vref, RX VrefLevel [Byte0]: 28
7821 22:18:15.451149 [Byte1]: 28
7822 22:18:15.455795
7823 22:18:15.455879 Set Vref, RX VrefLevel [Byte0]: 29
7824 22:18:15.458886 [Byte1]: 29
7825 22:18:15.463167
7826 22:18:15.463251 Set Vref, RX VrefLevel [Byte0]: 30
7827 22:18:15.466623 [Byte1]: 30
7828 22:18:15.470896
7829 22:18:15.471054 Set Vref, RX VrefLevel [Byte0]: 31
7830 22:18:15.474377 [Byte1]: 31
7831 22:18:15.478388
7832 22:18:15.478471 Set Vref, RX VrefLevel [Byte0]: 32
7833 22:18:15.481979 [Byte1]: 32
7834 22:18:15.486176
7835 22:18:15.486260 Set Vref, RX VrefLevel [Byte0]: 33
7836 22:18:15.489456 [Byte1]: 33
7837 22:18:15.494161
7838 22:18:15.494244 Set Vref, RX VrefLevel [Byte0]: 34
7839 22:18:15.497098 [Byte1]: 34
7840 22:18:15.501347
7841 22:18:15.501429 Set Vref, RX VrefLevel [Byte0]: 35
7842 22:18:15.504500 [Byte1]: 35
7843 22:18:15.509125
7844 22:18:15.509206 Set Vref, RX VrefLevel [Byte0]: 36
7845 22:18:15.511978 [Byte1]: 36
7846 22:18:15.516840
7847 22:18:15.516921 Set Vref, RX VrefLevel [Byte0]: 37
7848 22:18:15.520021 [Byte1]: 37
7849 22:18:15.524378
7850 22:18:15.524460 Set Vref, RX VrefLevel [Byte0]: 38
7851 22:18:15.527412 [Byte1]: 38
7852 22:18:15.531811
7853 22:18:15.531893 Set Vref, RX VrefLevel [Byte0]: 39
7854 22:18:15.535323 [Byte1]: 39
7855 22:18:15.539463
7856 22:18:15.539545 Set Vref, RX VrefLevel [Byte0]: 40
7857 22:18:15.542566 [Byte1]: 40
7858 22:18:15.547187
7859 22:18:15.547335 Set Vref, RX VrefLevel [Byte0]: 41
7860 22:18:15.550202 [Byte1]: 41
7861 22:18:15.554812
7862 22:18:15.554894 Set Vref, RX VrefLevel [Byte0]: 42
7863 22:18:15.557924 [Byte1]: 42
7864 22:18:15.562330
7865 22:18:15.562412 Set Vref, RX VrefLevel [Byte0]: 43
7866 22:18:15.566067 [Byte1]: 43
7867 22:18:15.569647
7868 22:18:15.569728 Set Vref, RX VrefLevel [Byte0]: 44
7869 22:18:15.576425 [Byte1]: 44
7870 22:18:15.576507
7871 22:18:15.579691 Set Vref, RX VrefLevel [Byte0]: 45
7872 22:18:15.583608 [Byte1]: 45
7873 22:18:15.583691
7874 22:18:15.586219 Set Vref, RX VrefLevel [Byte0]: 46
7875 22:18:15.589341 [Byte1]: 46
7876 22:18:15.592787
7877 22:18:15.592868 Set Vref, RX VrefLevel [Byte0]: 47
7878 22:18:15.595962 [Byte1]: 47
7879 22:18:15.600249
7880 22:18:15.600331 Set Vref, RX VrefLevel [Byte0]: 48
7881 22:18:15.603674 [Byte1]: 48
7882 22:18:15.608278
7883 22:18:15.608359 Set Vref, RX VrefLevel [Byte0]: 49
7884 22:18:15.611075 [Byte1]: 49
7885 22:18:15.615235
7886 22:18:15.615317 Set Vref, RX VrefLevel [Byte0]: 50
7887 22:18:15.618655 [Byte1]: 50
7888 22:18:15.623193
7889 22:18:15.623289 Set Vref, RX VrefLevel [Byte0]: 51
7890 22:18:15.626367 [Byte1]: 51
7891 22:18:15.630963
7892 22:18:15.631046 Set Vref, RX VrefLevel [Byte0]: 52
7893 22:18:15.634059 [Byte1]: 52
7894 22:18:15.638900
7895 22:18:15.638983 Set Vref, RX VrefLevel [Byte0]: 53
7896 22:18:15.641802 [Byte1]: 53
7897 22:18:15.646010
7898 22:18:15.646092 Set Vref, RX VrefLevel [Byte0]: 54
7899 22:18:15.649171 [Byte1]: 54
7900 22:18:15.653445
7901 22:18:15.653527 Set Vref, RX VrefLevel [Byte0]: 55
7902 22:18:15.656758 [Byte1]: 55
7903 22:18:15.661014
7904 22:18:15.661097 Set Vref, RX VrefLevel [Byte0]: 56
7905 22:18:15.664491 [Byte1]: 56
7906 22:18:15.668988
7907 22:18:15.669071 Set Vref, RX VrefLevel [Byte0]: 57
7908 22:18:15.675362 [Byte1]: 57
7909 22:18:15.675445
7910 22:18:15.678359 Set Vref, RX VrefLevel [Byte0]: 58
7911 22:18:15.681953 [Byte1]: 58
7912 22:18:15.682036
7913 22:18:15.685282 Set Vref, RX VrefLevel [Byte0]: 59
7914 22:18:15.688506 [Byte1]: 59
7915 22:18:15.691968
7916 22:18:15.692119 Set Vref, RX VrefLevel [Byte0]: 60
7917 22:18:15.695059 [Byte1]: 60
7918 22:18:15.699038
7919 22:18:15.699120 Set Vref, RX VrefLevel [Byte0]: 61
7920 22:18:15.702508 [Byte1]: 61
7921 22:18:15.707209
7922 22:18:15.707292 Set Vref, RX VrefLevel [Byte0]: 62
7923 22:18:15.710362 [Byte1]: 62
7924 22:18:15.714704
7925 22:18:15.714786 Set Vref, RX VrefLevel [Byte0]: 63
7926 22:18:15.717913 [Byte1]: 63
7927 22:18:15.722357
7928 22:18:15.722439 Set Vref, RX VrefLevel [Byte0]: 64
7929 22:18:15.725245 [Byte1]: 64
7930 22:18:15.729659
7931 22:18:15.729740 Set Vref, RX VrefLevel [Byte0]: 65
7932 22:18:15.733107 [Byte1]: 65
7933 22:18:15.737196
7934 22:18:15.737277 Set Vref, RX VrefLevel [Byte0]: 66
7935 22:18:15.740784 [Byte1]: 66
7936 22:18:15.744766
7937 22:18:15.744847 Set Vref, RX VrefLevel [Byte0]: 67
7938 22:18:15.748164 [Byte1]: 67
7939 22:18:15.752943
7940 22:18:15.753025 Set Vref, RX VrefLevel [Byte0]: 68
7941 22:18:15.755726 [Byte1]: 68
7942 22:18:15.760525
7943 22:18:15.760606 Set Vref, RX VrefLevel [Byte0]: 69
7944 22:18:15.763307 [Byte1]: 69
7945 22:18:15.767918
7946 22:18:15.768025 Set Vref, RX VrefLevel [Byte0]: 70
7947 22:18:15.771207 [Byte1]: 70
7948 22:18:15.775480
7949 22:18:15.775562 Set Vref, RX VrefLevel [Byte0]: 71
7950 22:18:15.778958 [Byte1]: 71
7951 22:18:15.783158
7952 22:18:15.783240 Set Vref, RX VrefLevel [Byte0]: 72
7953 22:18:15.786041 [Byte1]: 72
7954 22:18:15.790687
7955 22:18:15.790769 Final RX Vref Byte 0 = 54 to rank0
7956 22:18:15.793935 Final RX Vref Byte 1 = 58 to rank0
7957 22:18:15.797087 Final RX Vref Byte 0 = 54 to rank1
7958 22:18:15.800452 Final RX Vref Byte 1 = 58 to rank1==
7959 22:18:15.803643 Dram Type= 6, Freq= 0, CH_0, rank 0
7960 22:18:15.810450 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7961 22:18:15.810531 ==
7962 22:18:15.810596 DQS Delay:
7963 22:18:15.813581 DQS0 = 0, DQS1 = 0
7964 22:18:15.813662 DQM Delay:
7965 22:18:15.813726 DQM0 = 129, DQM1 = 123
7966 22:18:15.817013 DQ Delay:
7967 22:18:15.820428 DQ0 =130, DQ1 =130, DQ2 =128, DQ3 =124
7968 22:18:15.823969 DQ4 =132, DQ5 =118, DQ6 =136, DQ7 =134
7969 22:18:15.826783 DQ8 =112, DQ9 =110, DQ10 =124, DQ11 =120
7970 22:18:15.829885 DQ12 =130, DQ13 =130, DQ14 =134, DQ15 =130
7971 22:18:15.829966
7972 22:18:15.830029
7973 22:18:15.830086
7974 22:18:15.833708 [DramC_TX_OE_Calibration] TA2
7975 22:18:15.836668 Original DQ_B0 (3 6) =30, OEN = 27
7976 22:18:15.840272 Original DQ_B1 (3 6) =30, OEN = 27
7977 22:18:15.843240 24, 0x0, End_B0=24 End_B1=24
7978 22:18:15.846926 25, 0x0, End_B0=25 End_B1=25
7979 22:18:15.847007 26, 0x0, End_B0=26 End_B1=26
7980 22:18:15.850101 27, 0x0, End_B0=27 End_B1=27
7981 22:18:15.853061 28, 0x0, End_B0=28 End_B1=28
7982 22:18:15.856485 29, 0x0, End_B0=29 End_B1=29
7983 22:18:15.856567 30, 0x0, End_B0=30 End_B1=30
7984 22:18:15.859984 31, 0x4141, End_B0=30 End_B1=30
7985 22:18:15.862714 Byte0 end_step=30 best_step=27
7986 22:18:15.866208 Byte1 end_step=30 best_step=27
7987 22:18:15.869954 Byte0 TX OE(2T, 0.5T) = (3, 3)
7988 22:18:15.872630 Byte1 TX OE(2T, 0.5T) = (3, 3)
7989 22:18:15.872743
7990 22:18:15.872813
7991 22:18:15.879600 [DQSOSCAuto] RK0, (LSB)MR18= 0x1714, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 398 ps
7992 22:18:15.882558 CH0 RK0: MR19=303, MR18=1714
7993 22:18:15.889351 CH0_RK0: MR19=0x303, MR18=0x1714, DQSOSC=398, MR23=63, INC=23, DEC=15
7994 22:18:15.889459
7995 22:18:15.892296 ----->DramcWriteLeveling(PI) begin...
7996 22:18:15.892378 ==
7997 22:18:15.895783 Dram Type= 6, Freq= 0, CH_0, rank 1
7998 22:18:15.899196 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7999 22:18:15.899278 ==
8000 22:18:15.902331 Write leveling (Byte 0): 35 => 35
8001 22:18:15.905344 Write leveling (Byte 1): 25 => 25
8002 22:18:15.908853 DramcWriteLeveling(PI) end<-----
8003 22:18:15.908935
8004 22:18:15.908999 ==
8005 22:18:15.912217 Dram Type= 6, Freq= 0, CH_0, rank 1
8006 22:18:15.918687 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8007 22:18:15.918769 ==
8008 22:18:15.918834 [Gating] SW mode calibration
8009 22:18:15.928849 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8010 22:18:15.931705 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8011 22:18:15.939100 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8012 22:18:15.941868 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8013 22:18:15.945309 1 4 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8014 22:18:15.951660 1 4 12 | B1->B0 | 2323 3333 | 0 1 | (0 0) (1 1)
8015 22:18:15.955439 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8016 22:18:15.958134 1 4 20 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
8017 22:18:15.964967 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8018 22:18:15.967951 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8019 22:18:15.971306 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8020 22:18:15.977908 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8021 22:18:15.981321 1 5 8 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
8022 22:18:15.984522 1 5 12 | B1->B0 | 3434 2929 | 1 0 | (1 1) (0 0)
8023 22:18:15.990900 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
8024 22:18:15.994213 1 5 20 | B1->B0 | 2a2a 2323 | 1 0 | (1 0) (0 0)
8025 22:18:15.997983 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8026 22:18:16.004417 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8027 22:18:16.007687 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8028 22:18:16.011202 1 6 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8029 22:18:16.017594 1 6 8 | B1->B0 | 2323 3f3f | 0 0 | (0 0) (0 0)
8030 22:18:16.020902 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8031 22:18:16.024446 1 6 16 | B1->B0 | 3030 4646 | 0 0 | (0 0) (0 0)
8032 22:18:16.030927 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8033 22:18:16.034100 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8034 22:18:16.037536 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8035 22:18:16.043999 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8036 22:18:16.047262 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8037 22:18:16.050499 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8038 22:18:16.057363 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8039 22:18:16.060488 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8040 22:18:16.063836 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8041 22:18:16.070324 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8042 22:18:16.073767 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8043 22:18:16.076868 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8044 22:18:16.083246 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8045 22:18:16.086402 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8046 22:18:16.089766 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8047 22:18:16.096388 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8048 22:18:16.099597 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8049 22:18:16.103062 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8050 22:18:16.109414 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8051 22:18:16.114045 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8052 22:18:16.116411 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8053 22:18:16.122527 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8054 22:18:16.122644 Total UI for P1: 0, mck2ui 16
8055 22:18:16.129250 best dqsien dly found for B0: ( 1, 9, 6)
8056 22:18:16.132437 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8057 22:18:16.135690 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8058 22:18:16.142370 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8059 22:18:16.142470 Total UI for P1: 0, mck2ui 16
8060 22:18:16.149248 best dqsien dly found for B1: ( 1, 9, 16)
8061 22:18:16.152167 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8062 22:18:16.155665 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8063 22:18:16.155771
8064 22:18:16.159132 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8065 22:18:16.162515 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8066 22:18:16.165668 [Gating] SW calibration Done
8067 22:18:16.165754 ==
8068 22:18:16.169049 Dram Type= 6, Freq= 0, CH_0, rank 1
8069 22:18:16.172130 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8070 22:18:16.172216 ==
8071 22:18:16.175227 RX Vref Scan: 0
8072 22:18:16.175310
8073 22:18:16.178748 RX Vref 0 -> 0, step: 1
8074 22:18:16.178831
8075 22:18:16.178896 RX Delay 0 -> 252, step: 8
8076 22:18:16.184909 iDelay=192, Bit 0, Center 131 (80 ~ 183) 104
8077 22:18:16.188500 iDelay=192, Bit 1, Center 131 (72 ~ 191) 120
8078 22:18:16.191986 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
8079 22:18:16.195320 iDelay=192, Bit 3, Center 127 (72 ~ 183) 112
8080 22:18:16.198173 iDelay=192, Bit 4, Center 135 (80 ~ 191) 112
8081 22:18:16.205405 iDelay=192, Bit 5, Center 119 (64 ~ 175) 112
8082 22:18:16.208335 iDelay=192, Bit 6, Center 139 (88 ~ 191) 104
8083 22:18:16.211951 iDelay=192, Bit 7, Center 135 (80 ~ 191) 112
8084 22:18:16.215083 iDelay=192, Bit 8, Center 119 (64 ~ 175) 112
8085 22:18:16.217871 iDelay=192, Bit 9, Center 111 (56 ~ 167) 112
8086 22:18:16.224574 iDelay=192, Bit 10, Center 127 (72 ~ 183) 112
8087 22:18:16.227616 iDelay=192, Bit 11, Center 119 (64 ~ 175) 112
8088 22:18:16.231314 iDelay=192, Bit 12, Center 131 (72 ~ 191) 120
8089 22:18:16.234806 iDelay=192, Bit 13, Center 135 (80 ~ 191) 112
8090 22:18:16.240786 iDelay=192, Bit 14, Center 135 (80 ~ 191) 112
8091 22:18:16.244302 iDelay=192, Bit 15, Center 135 (80 ~ 191) 112
8092 22:18:16.244390 ==
8093 22:18:16.247428 Dram Type= 6, Freq= 0, CH_0, rank 1
8094 22:18:16.250859 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8095 22:18:16.250944 ==
8096 22:18:16.254031 DQS Delay:
8097 22:18:16.254115 DQS0 = 0, DQS1 = 0
8098 22:18:16.254181 DQM Delay:
8099 22:18:16.257602 DQM0 = 130, DQM1 = 126
8100 22:18:16.257687 DQ Delay:
8101 22:18:16.260501 DQ0 =131, DQ1 =131, DQ2 =127, DQ3 =127
8102 22:18:16.263674 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =135
8103 22:18:16.270138 DQ8 =119, DQ9 =111, DQ10 =127, DQ11 =119
8104 22:18:16.273688 DQ12 =131, DQ13 =135, DQ14 =135, DQ15 =135
8105 22:18:16.273775
8106 22:18:16.273840
8107 22:18:16.273899 ==
8108 22:18:16.277156 Dram Type= 6, Freq= 0, CH_0, rank 1
8109 22:18:16.280457 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8110 22:18:16.280543 ==
8111 22:18:16.280609
8112 22:18:16.280670
8113 22:18:16.283377 TX Vref Scan disable
8114 22:18:16.286542 == TX Byte 0 ==
8115 22:18:16.289841 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8116 22:18:16.293838 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8117 22:18:16.296758 == TX Byte 1 ==
8118 22:18:16.299615 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8119 22:18:16.303312 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8120 22:18:16.303403 ==
8121 22:18:16.306237 Dram Type= 6, Freq= 0, CH_0, rank 1
8122 22:18:16.312999 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8123 22:18:16.313094 ==
8124 22:18:16.327193
8125 22:18:16.329935 TX Vref early break, caculate TX vref
8126 22:18:16.333573 TX Vref=16, minBit 1, minWin=23, winSum=380
8127 22:18:16.336962 TX Vref=18, minBit 1, minWin=23, winSum=384
8128 22:18:16.339597 TX Vref=20, minBit 8, minWin=23, winSum=388
8129 22:18:16.342919 TX Vref=22, minBit 2, minWin=24, winSum=401
8130 22:18:16.349624 TX Vref=24, minBit 10, minWin=24, winSum=408
8131 22:18:16.353316 TX Vref=26, minBit 4, minWin=25, winSum=416
8132 22:18:16.356603 TX Vref=28, minBit 9, minWin=25, winSum=417
8133 22:18:16.359966 TX Vref=30, minBit 2, minWin=25, winSum=412
8134 22:18:16.362843 TX Vref=32, minBit 7, minWin=24, winSum=403
8135 22:18:16.366368 TX Vref=34, minBit 0, minWin=24, winSum=396
8136 22:18:16.373072 TX Vref=36, minBit 11, minWin=23, winSum=388
8137 22:18:16.375954 [TxChooseVref] Worse bit 9, Min win 25, Win sum 417, Final Vref 28
8138 22:18:16.376049
8139 22:18:16.379129 Final TX Range 0 Vref 28
8140 22:18:16.379212
8141 22:18:16.379277 ==
8142 22:18:16.382556 Dram Type= 6, Freq= 0, CH_0, rank 1
8143 22:18:16.389412 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8144 22:18:16.389521 ==
8145 22:18:16.389588
8146 22:18:16.389648
8147 22:18:16.389704 TX Vref Scan disable
8148 22:18:16.396519 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8149 22:18:16.396619 == TX Byte 0 ==
8150 22:18:16.399268 u2DelayCellOfst[0]=10 cells (3 PI)
8151 22:18:16.402609 u2DelayCellOfst[1]=14 cells (4 PI)
8152 22:18:16.406180 u2DelayCellOfst[2]=7 cells (2 PI)
8153 22:18:16.409629 u2DelayCellOfst[3]=10 cells (3 PI)
8154 22:18:16.413135 u2DelayCellOfst[4]=7 cells (2 PI)
8155 22:18:16.416183 u2DelayCellOfst[5]=0 cells (0 PI)
8156 22:18:16.419236 u2DelayCellOfst[6]=14 cells (4 PI)
8157 22:18:16.422464 u2DelayCellOfst[7]=14 cells (4 PI)
8158 22:18:16.426196 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8159 22:18:16.429438 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8160 22:18:16.432869 == TX Byte 1 ==
8161 22:18:16.435867 u2DelayCellOfst[8]=0 cells (0 PI)
8162 22:18:16.439289 u2DelayCellOfst[9]=0 cells (0 PI)
8163 22:18:16.442153 u2DelayCellOfst[10]=3 cells (1 PI)
8164 22:18:16.445917 u2DelayCellOfst[11]=3 cells (1 PI)
8165 22:18:16.449056 u2DelayCellOfst[12]=10 cells (3 PI)
8166 22:18:16.452159 u2DelayCellOfst[13]=10 cells (3 PI)
8167 22:18:16.455314 u2DelayCellOfst[14]=14 cells (4 PI)
8168 22:18:16.455403 u2DelayCellOfst[15]=10 cells (3 PI)
8169 22:18:16.462409 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8170 22:18:16.465382 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8171 22:18:16.469036 DramC Write-DBI on
8172 22:18:16.469128 ==
8173 22:18:16.471928 Dram Type= 6, Freq= 0, CH_0, rank 1
8174 22:18:16.475753 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8175 22:18:16.475844 ==
8176 22:18:16.475946
8177 22:18:16.476076
8178 22:18:16.478612 TX Vref Scan disable
8179 22:18:16.478698 == TX Byte 0 ==
8180 22:18:16.485299 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
8181 22:18:16.485393 == TX Byte 1 ==
8182 22:18:16.492020 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8183 22:18:16.492180 DramC Write-DBI off
8184 22:18:16.492248
8185 22:18:16.492308 [DATLAT]
8186 22:18:16.495144 Freq=1600, CH0 RK1
8187 22:18:16.495253
8188 22:18:16.495362 DATLAT Default: 0xf
8189 22:18:16.498444 0, 0xFFFF, sum = 0
8190 22:18:16.501746 1, 0xFFFF, sum = 0
8191 22:18:16.501836 2, 0xFFFF, sum = 0
8192 22:18:16.505298 3, 0xFFFF, sum = 0
8193 22:18:16.505383 4, 0xFFFF, sum = 0
8194 22:18:16.507974 5, 0xFFFF, sum = 0
8195 22:18:16.508109 6, 0xFFFF, sum = 0
8196 22:18:16.511576 7, 0xFFFF, sum = 0
8197 22:18:16.511660 8, 0xFFFF, sum = 0
8198 22:18:16.514939 9, 0xFFFF, sum = 0
8199 22:18:16.515025 10, 0xFFFF, sum = 0
8200 22:18:16.518193 11, 0xFFFF, sum = 0
8201 22:18:16.518292 12, 0xFFFF, sum = 0
8202 22:18:16.521470 13, 0xFFFF, sum = 0
8203 22:18:16.521558 14, 0x0, sum = 1
8204 22:18:16.525002 15, 0x0, sum = 2
8205 22:18:16.525088 16, 0x0, sum = 3
8206 22:18:16.527968 17, 0x0, sum = 4
8207 22:18:16.528093 best_step = 15
8208 22:18:16.528159
8209 22:18:16.528220 ==
8210 22:18:16.531236 Dram Type= 6, Freq= 0, CH_0, rank 1
8211 22:18:16.537946 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8212 22:18:16.538051 ==
8213 22:18:16.538119 RX Vref Scan: 0
8214 22:18:16.538180
8215 22:18:16.541267 RX Vref 0 -> 0, step: 1
8216 22:18:16.541352
8217 22:18:16.544337 RX Delay 11 -> 252, step: 4
8218 22:18:16.547781 iDelay=191, Bit 0, Center 126 (75 ~ 178) 104
8219 22:18:16.551038 iDelay=191, Bit 1, Center 130 (79 ~ 182) 104
8220 22:18:16.557572 iDelay=191, Bit 2, Center 124 (71 ~ 178) 108
8221 22:18:16.560606 iDelay=191, Bit 3, Center 126 (75 ~ 178) 104
8222 22:18:16.563830 iDelay=191, Bit 4, Center 132 (83 ~ 182) 100
8223 22:18:16.567817 iDelay=191, Bit 5, Center 118 (63 ~ 174) 112
8224 22:18:16.570731 iDelay=191, Bit 6, Center 136 (87 ~ 186) 100
8225 22:18:16.576973 iDelay=191, Bit 7, Center 134 (83 ~ 186) 104
8226 22:18:16.580488 iDelay=191, Bit 8, Center 114 (63 ~ 166) 104
8227 22:18:16.583759 iDelay=191, Bit 9, Center 110 (59 ~ 162) 104
8228 22:18:16.587199 iDelay=191, Bit 10, Center 124 (71 ~ 178) 108
8229 22:18:16.590326 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8230 22:18:16.596934 iDelay=191, Bit 12, Center 128 (75 ~ 182) 108
8231 22:18:16.600168 iDelay=191, Bit 13, Center 130 (79 ~ 182) 104
8232 22:18:16.603617 iDelay=191, Bit 14, Center 136 (83 ~ 190) 108
8233 22:18:16.606803 iDelay=191, Bit 15, Center 132 (79 ~ 186) 108
8234 22:18:16.609920 ==
8235 22:18:16.610015 Dram Type= 6, Freq= 0, CH_0, rank 1
8236 22:18:16.616736 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8237 22:18:16.616840 ==
8238 22:18:16.616909 DQS Delay:
8239 22:18:16.619932 DQS0 = 0, DQS1 = 0
8240 22:18:16.620018 DQM Delay:
8241 22:18:16.623285 DQM0 = 128, DQM1 = 124
8242 22:18:16.623372 DQ Delay:
8243 22:18:16.626484 DQ0 =126, DQ1 =130, DQ2 =124, DQ3 =126
8244 22:18:16.629804 DQ4 =132, DQ5 =118, DQ6 =136, DQ7 =134
8245 22:18:16.633079 DQ8 =114, DQ9 =110, DQ10 =124, DQ11 =118
8246 22:18:16.636867 DQ12 =128, DQ13 =130, DQ14 =136, DQ15 =132
8247 22:18:16.636959
8248 22:18:16.637025
8249 22:18:16.637084
8250 22:18:16.639701 [DramC_TX_OE_Calibration] TA2
8251 22:18:16.643193 Original DQ_B0 (3 6) =30, OEN = 27
8252 22:18:16.646861 Original DQ_B1 (3 6) =30, OEN = 27
8253 22:18:16.649610 24, 0x0, End_B0=24 End_B1=24
8254 22:18:16.652763 25, 0x0, End_B0=25 End_B1=25
8255 22:18:16.652855 26, 0x0, End_B0=26 End_B1=26
8256 22:18:16.656518 27, 0x0, End_B0=27 End_B1=27
8257 22:18:16.659764 28, 0x0, End_B0=28 End_B1=28
8258 22:18:16.662602 29, 0x0, End_B0=29 End_B1=29
8259 22:18:16.665866 30, 0x0, End_B0=30 End_B1=30
8260 22:18:16.665955 31, 0x4545, End_B0=30 End_B1=30
8261 22:18:16.669182 Byte0 end_step=30 best_step=27
8262 22:18:16.672510 Byte1 end_step=30 best_step=27
8263 22:18:16.675785 Byte0 TX OE(2T, 0.5T) = (3, 3)
8264 22:18:16.679100 Byte1 TX OE(2T, 0.5T) = (3, 3)
8265 22:18:16.679191
8266 22:18:16.679257
8267 22:18:16.686329 [DQSOSCAuto] RK1, (LSB)MR18= 0x1513, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 399 ps
8268 22:18:16.689490 CH0 RK1: MR19=303, MR18=1513
8269 22:18:16.695784 CH0_RK1: MR19=0x303, MR18=0x1513, DQSOSC=399, MR23=63, INC=23, DEC=15
8270 22:18:16.699327 [RxdqsGatingPostProcess] freq 1600
8271 22:18:16.706164 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8272 22:18:16.708652 best DQS0 dly(2T, 0.5T) = (1, 1)
8273 22:18:16.711935 best DQS1 dly(2T, 0.5T) = (1, 1)
8274 22:18:16.712096 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8275 22:18:16.715143 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8276 22:18:16.718528 best DQS0 dly(2T, 0.5T) = (1, 1)
8277 22:18:16.722016 best DQS1 dly(2T, 0.5T) = (1, 1)
8278 22:18:16.725312 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8279 22:18:16.728358 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8280 22:18:16.731527 Pre-setting of DQS Precalculation
8281 22:18:16.738251 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8282 22:18:16.738366 ==
8283 22:18:16.741700 Dram Type= 6, Freq= 0, CH_1, rank 0
8284 22:18:16.744788 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8285 22:18:16.744906 ==
8286 22:18:16.751199 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8287 22:18:16.755011 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8288 22:18:16.758117 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8289 22:18:16.764545 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8290 22:18:16.773306 [CA 0] Center 42 (13~72) winsize 60
8291 22:18:16.777387 [CA 1] Center 43 (13~73) winsize 61
8292 22:18:16.780022 [CA 2] Center 38 (9~68) winsize 60
8293 22:18:16.783305 [CA 3] Center 37 (8~67) winsize 60
8294 22:18:16.786401 [CA 4] Center 38 (8~68) winsize 61
8295 22:18:16.790263 [CA 5] Center 37 (7~67) winsize 61
8296 22:18:16.790363
8297 22:18:16.793635 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8298 22:18:16.793725
8299 22:18:16.796752 [CATrainingPosCal] consider 1 rank data
8300 22:18:16.799927 u2DelayCellTimex100 = 275/100 ps
8301 22:18:16.806484 CA0 delay=42 (13~72),Diff = 5 PI (17 cell)
8302 22:18:16.809702 CA1 delay=43 (13~73),Diff = 6 PI (21 cell)
8303 22:18:16.813361 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8304 22:18:16.816320 CA3 delay=37 (8~67),Diff = 0 PI (0 cell)
8305 22:18:16.819785 CA4 delay=38 (8~68),Diff = 1 PI (3 cell)
8306 22:18:16.823082 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
8307 22:18:16.823173
8308 22:18:16.826069 CA PerBit enable=1, Macro0, CA PI delay=37
8309 22:18:16.826156
8310 22:18:16.829725 [CBTSetCACLKResult] CA Dly = 37
8311 22:18:16.832886 CS Dly: 8 (0~39)
8312 22:18:16.836266 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8313 22:18:16.839416 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8314 22:18:16.839521 ==
8315 22:18:16.842862 Dram Type= 6, Freq= 0, CH_1, rank 1
8316 22:18:16.849012 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8317 22:18:16.849118 ==
8318 22:18:16.852542 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8319 22:18:16.858895 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8320 22:18:16.862389 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8321 22:18:16.869019 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8322 22:18:16.876983 [CA 0] Center 42 (12~72) winsize 61
8323 22:18:16.880026 [CA 1] Center 42 (13~72) winsize 60
8324 22:18:16.882973 [CA 2] Center 38 (9~68) winsize 60
8325 22:18:16.886316 [CA 3] Center 37 (8~67) winsize 60
8326 22:18:16.890468 [CA 4] Center 37 (8~67) winsize 60
8327 22:18:16.893197 [CA 5] Center 37 (7~67) winsize 61
8328 22:18:16.893295
8329 22:18:16.896488 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8330 22:18:16.896576
8331 22:18:16.899685 [CATrainingPosCal] consider 2 rank data
8332 22:18:16.903112 u2DelayCellTimex100 = 275/100 ps
8333 22:18:16.909635 CA0 delay=42 (13~72),Diff = 5 PI (17 cell)
8334 22:18:16.912912 CA1 delay=42 (13~72),Diff = 5 PI (17 cell)
8335 22:18:16.916154 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8336 22:18:16.919578 CA3 delay=37 (8~67),Diff = 0 PI (0 cell)
8337 22:18:16.922580 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
8338 22:18:16.925937 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
8339 22:18:16.926030
8340 22:18:16.929307 CA PerBit enable=1, Macro0, CA PI delay=37
8341 22:18:16.929454
8342 22:18:16.932403 [CBTSetCACLKResult] CA Dly = 37
8343 22:18:16.935962 CS Dly: 9 (0~42)
8344 22:18:16.939437 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8345 22:18:16.942449 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8346 22:18:16.942540
8347 22:18:16.945571 ----->DramcWriteLeveling(PI) begin...
8348 22:18:16.945703 ==
8349 22:18:16.948743 Dram Type= 6, Freq= 0, CH_1, rank 0
8350 22:18:16.955974 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8351 22:18:16.956127 ==
8352 22:18:16.958742 Write leveling (Byte 0): 24 => 24
8353 22:18:16.962195 Write leveling (Byte 1): 28 => 28
8354 22:18:16.965512 DramcWriteLeveling(PI) end<-----
8355 22:18:16.965602
8356 22:18:16.965690 ==
8357 22:18:16.968408 Dram Type= 6, Freq= 0, CH_1, rank 0
8358 22:18:16.972519 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8359 22:18:16.972608 ==
8360 22:18:16.975106 [Gating] SW mode calibration
8361 22:18:16.982097 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8362 22:18:16.988292 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8363 22:18:16.991686 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8364 22:18:16.995298 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8365 22:18:17.001261 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8366 22:18:17.004849 1 4 12 | B1->B0 | 2525 3434 | 0 1 | (0 0) (1 1)
8367 22:18:17.007787 1 4 16 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
8368 22:18:17.014481 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8369 22:18:17.017855 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8370 22:18:17.021306 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8371 22:18:17.027743 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8372 22:18:17.030807 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8373 22:18:17.034525 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8374 22:18:17.040589 1 5 12 | B1->B0 | 3434 2525 | 0 0 | (0 1) (1 0)
8375 22:18:17.044073 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8376 22:18:17.047328 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8377 22:18:17.053822 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8378 22:18:17.057077 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8379 22:18:17.060684 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8380 22:18:17.067154 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8381 22:18:17.070607 1 6 8 | B1->B0 | 2323 2423 | 0 1 | (0 0) (0 0)
8382 22:18:17.073499 1 6 12 | B1->B0 | 2b2b 4646 | 1 0 | (0 0) (0 0)
8383 22:18:17.080058 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8384 22:18:17.083284 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8385 22:18:17.087126 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8386 22:18:17.093836 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8387 22:18:17.096609 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8388 22:18:17.099863 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8389 22:18:17.106652 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8390 22:18:17.109637 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8391 22:18:17.112942 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8392 22:18:17.120019 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8393 22:18:17.122835 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8394 22:18:17.126013 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8395 22:18:17.133360 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8396 22:18:17.136424 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8397 22:18:17.139753 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8398 22:18:17.146006 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8399 22:18:17.149300 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8400 22:18:17.152708 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8401 22:18:17.159464 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8402 22:18:17.162602 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8403 22:18:17.165590 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8404 22:18:17.172394 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8405 22:18:17.175427 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8406 22:18:17.179275 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8407 22:18:17.185566 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8408 22:18:17.188807 Total UI for P1: 0, mck2ui 16
8409 22:18:17.192064 best dqsien dly found for B0: ( 1, 9, 10)
8410 22:18:17.195584 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8411 22:18:17.198836 Total UI for P1: 0, mck2ui 16
8412 22:18:17.202145 best dqsien dly found for B1: ( 1, 9, 14)
8413 22:18:17.205055 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8414 22:18:17.208735 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8415 22:18:17.208831
8416 22:18:17.212015 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8417 22:18:17.218846 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8418 22:18:17.218943 [Gating] SW calibration Done
8419 22:18:17.219033 ==
8420 22:18:17.222119 Dram Type= 6, Freq= 0, CH_1, rank 0
8421 22:18:17.228361 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8422 22:18:17.228462 ==
8423 22:18:17.228531 RX Vref Scan: 0
8424 22:18:17.228592
8425 22:18:17.231744 RX Vref 0 -> 0, step: 1
8426 22:18:17.231826
8427 22:18:17.235460 RX Delay 0 -> 252, step: 8
8428 22:18:17.238433 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8429 22:18:17.241856 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8430 22:18:17.245649 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
8431 22:18:17.248070 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8432 22:18:17.254654 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8433 22:18:17.258406 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8434 22:18:17.261546 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8435 22:18:17.264740 iDelay=200, Bit 7, Center 131 (80 ~ 183) 104
8436 22:18:17.271491 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8437 22:18:17.274906 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
8438 22:18:17.277810 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8439 22:18:17.281491 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8440 22:18:17.284048 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8441 22:18:17.290961 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8442 22:18:17.294064 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8443 22:18:17.297588 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8444 22:18:17.297681 ==
8445 22:18:17.300956 Dram Type= 6, Freq= 0, CH_1, rank 0
8446 22:18:17.304233 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8447 22:18:17.307164 ==
8448 22:18:17.307266 DQS Delay:
8449 22:18:17.307359 DQS0 = 0, DQS1 = 0
8450 22:18:17.311023 DQM Delay:
8451 22:18:17.311107 DQM0 = 135, DQM1 = 132
8452 22:18:17.313736 DQ Delay:
8453 22:18:17.317152 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8454 22:18:17.320665 DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =131
8455 22:18:17.324027 DQ8 =115, DQ9 =123, DQ10 =131, DQ11 =127
8456 22:18:17.327165 DQ12 =139, DQ13 =143, DQ14 =139, DQ15 =139
8457 22:18:17.327250
8458 22:18:17.327316
8459 22:18:17.327374 ==
8460 22:18:17.330454 Dram Type= 6, Freq= 0, CH_1, rank 0
8461 22:18:17.334545 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8462 22:18:17.334635 ==
8463 22:18:17.337175
8464 22:18:17.337259
8465 22:18:17.337324 TX Vref Scan disable
8466 22:18:17.340186 == TX Byte 0 ==
8467 22:18:17.343942 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8468 22:18:17.347050 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8469 22:18:17.350033 == TX Byte 1 ==
8470 22:18:17.353334 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8471 22:18:17.356954 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8472 22:18:17.357053 ==
8473 22:18:17.360217 Dram Type= 6, Freq= 0, CH_1, rank 0
8474 22:18:17.366593 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8475 22:18:17.366701 ==
8476 22:18:17.379920
8477 22:18:17.383574 TX Vref early break, caculate TX vref
8478 22:18:17.386655 TX Vref=16, minBit 8, minWin=22, winSum=369
8479 22:18:17.389892 TX Vref=18, minBit 9, minWin=22, winSum=376
8480 22:18:17.392989 TX Vref=20, minBit 1, minWin=23, winSum=383
8481 22:18:17.396579 TX Vref=22, minBit 8, minWin=23, winSum=398
8482 22:18:17.400213 TX Vref=24, minBit 8, minWin=24, winSum=408
8483 22:18:17.406122 TX Vref=26, minBit 3, minWin=25, winSum=412
8484 22:18:17.409322 TX Vref=28, minBit 0, minWin=26, winSum=421
8485 22:18:17.412736 TX Vref=30, minBit 0, minWin=25, winSum=417
8486 22:18:17.415897 TX Vref=32, minBit 9, minWin=24, winSum=407
8487 22:18:17.419498 TX Vref=34, minBit 0, minWin=24, winSum=399
8488 22:18:17.426028 TX Vref=36, minBit 9, minWin=22, winSum=387
8489 22:18:17.429246 [TxChooseVref] Worse bit 0, Min win 26, Win sum 421, Final Vref 28
8490 22:18:17.429344
8491 22:18:17.432998 Final TX Range 0 Vref 28
8492 22:18:17.433088
8493 22:18:17.433156 ==
8494 22:18:17.435572 Dram Type= 6, Freq= 0, CH_1, rank 0
8495 22:18:17.439192 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8496 22:18:17.442338 ==
8497 22:18:17.442429
8498 22:18:17.442495
8499 22:18:17.442556 TX Vref Scan disable
8500 22:18:17.449439 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8501 22:18:17.449542 == TX Byte 0 ==
8502 22:18:17.452388 u2DelayCellOfst[0]=17 cells (5 PI)
8503 22:18:17.456011 u2DelayCellOfst[1]=10 cells (3 PI)
8504 22:18:17.458924 u2DelayCellOfst[2]=0 cells (0 PI)
8505 22:18:17.462788 u2DelayCellOfst[3]=7 cells (2 PI)
8506 22:18:17.465636 u2DelayCellOfst[4]=7 cells (2 PI)
8507 22:18:17.468808 u2DelayCellOfst[5]=17 cells (5 PI)
8508 22:18:17.472415 u2DelayCellOfst[6]=17 cells (5 PI)
8509 22:18:17.475652 u2DelayCellOfst[7]=7 cells (2 PI)
8510 22:18:17.479077 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8511 22:18:17.482380 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8512 22:18:17.485675 == TX Byte 1 ==
8513 22:18:17.488522 u2DelayCellOfst[8]=0 cells (0 PI)
8514 22:18:17.491811 u2DelayCellOfst[9]=7 cells (2 PI)
8515 22:18:17.495030 u2DelayCellOfst[10]=10 cells (3 PI)
8516 22:18:17.498566 u2DelayCellOfst[11]=7 cells (2 PI)
8517 22:18:17.501683 u2DelayCellOfst[12]=14 cells (4 PI)
8518 22:18:17.505274 u2DelayCellOfst[13]=14 cells (4 PI)
8519 22:18:17.508605 u2DelayCellOfst[14]=17 cells (5 PI)
8520 22:18:17.508699 u2DelayCellOfst[15]=17 cells (5 PI)
8521 22:18:17.515213 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8522 22:18:17.518438 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8523 22:18:17.521694 DramC Write-DBI on
8524 22:18:17.521785 ==
8525 22:18:17.525507 Dram Type= 6, Freq= 0, CH_1, rank 0
8526 22:18:17.528560 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8527 22:18:17.528647 ==
8528 22:18:17.528717
8529 22:18:17.528779
8530 22:18:17.531782 TX Vref Scan disable
8531 22:18:17.531867 == TX Byte 0 ==
8532 22:18:17.538119 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8533 22:18:17.538213 == TX Byte 1 ==
8534 22:18:17.541631 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8535 22:18:17.544874 DramC Write-DBI off
8536 22:18:17.544961
8537 22:18:17.545028 [DATLAT]
8538 22:18:17.548314 Freq=1600, CH1 RK0
8539 22:18:17.548400
8540 22:18:17.548466 DATLAT Default: 0xf
8541 22:18:17.551250 0, 0xFFFF, sum = 0
8542 22:18:17.551336 1, 0xFFFF, sum = 0
8543 22:18:17.555421 2, 0xFFFF, sum = 0
8544 22:18:17.558346 3, 0xFFFF, sum = 0
8545 22:18:17.558433 4, 0xFFFF, sum = 0
8546 22:18:17.561128 5, 0xFFFF, sum = 0
8547 22:18:17.561216 6, 0xFFFF, sum = 0
8548 22:18:17.564667 7, 0xFFFF, sum = 0
8549 22:18:17.564754 8, 0xFFFF, sum = 0
8550 22:18:17.567952 9, 0xFFFF, sum = 0
8551 22:18:17.568049 10, 0xFFFF, sum = 0
8552 22:18:17.571300 11, 0xFFFF, sum = 0
8553 22:18:17.571392 12, 0xFFFF, sum = 0
8554 22:18:17.574408 13, 0xFFFF, sum = 0
8555 22:18:17.574496 14, 0x0, sum = 1
8556 22:18:17.578347 15, 0x0, sum = 2
8557 22:18:17.578434 16, 0x0, sum = 3
8558 22:18:17.581107 17, 0x0, sum = 4
8559 22:18:17.581193 best_step = 15
8560 22:18:17.581260
8561 22:18:17.581332 ==
8562 22:18:17.584390 Dram Type= 6, Freq= 0, CH_1, rank 0
8563 22:18:17.591509 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8564 22:18:17.591624 ==
8565 22:18:17.591695 RX Vref Scan: 1
8566 22:18:17.591757
8567 22:18:17.594008 Set Vref Range= 24 -> 127
8568 22:18:17.594096
8569 22:18:17.597306 RX Vref 24 -> 127, step: 1
8570 22:18:17.597397
8571 22:18:17.600886 RX Delay 19 -> 252, step: 4
8572 22:18:17.600975
8573 22:18:17.601043 Set Vref, RX VrefLevel [Byte0]: 24
8574 22:18:17.603920 [Byte1]: 24
8575 22:18:17.608018
8576 22:18:17.608136 Set Vref, RX VrefLevel [Byte0]: 25
8577 22:18:17.611432 [Byte1]: 25
8578 22:18:17.615899
8579 22:18:17.615988 Set Vref, RX VrefLevel [Byte0]: 26
8580 22:18:17.619079 [Byte1]: 26
8581 22:18:17.623673
8582 22:18:17.623766 Set Vref, RX VrefLevel [Byte0]: 27
8583 22:18:17.626833 [Byte1]: 27
8584 22:18:17.630923
8585 22:18:17.631022 Set Vref, RX VrefLevel [Byte0]: 28
8586 22:18:17.634135 [Byte1]: 28
8587 22:18:17.638975
8588 22:18:17.639066 Set Vref, RX VrefLevel [Byte0]: 29
8589 22:18:17.642364 [Byte1]: 29
8590 22:18:17.646087
8591 22:18:17.646202 Set Vref, RX VrefLevel [Byte0]: 30
8592 22:18:17.649464 [Byte1]: 30
8593 22:18:17.654074
8594 22:18:17.654163 Set Vref, RX VrefLevel [Byte0]: 31
8595 22:18:17.656936 [Byte1]: 31
8596 22:18:17.661208
8597 22:18:17.661297 Set Vref, RX VrefLevel [Byte0]: 32
8598 22:18:17.664976 [Byte1]: 32
8599 22:18:17.668825
8600 22:18:17.668924 Set Vref, RX VrefLevel [Byte0]: 33
8601 22:18:17.671990 [Byte1]: 33
8602 22:18:17.676275
8603 22:18:17.676372 Set Vref, RX VrefLevel [Byte0]: 34
8604 22:18:17.680151 [Byte1]: 34
8605 22:18:17.683953
8606 22:18:17.684067 Set Vref, RX VrefLevel [Byte0]: 35
8607 22:18:17.687208 [Byte1]: 35
8608 22:18:17.691543
8609 22:18:17.691646 Set Vref, RX VrefLevel [Byte0]: 36
8610 22:18:17.695036 [Byte1]: 36
8611 22:18:17.699839
8612 22:18:17.699939 Set Vref, RX VrefLevel [Byte0]: 37
8613 22:18:17.702858 [Byte1]: 37
8614 22:18:17.706949
8615 22:18:17.707043 Set Vref, RX VrefLevel [Byte0]: 38
8616 22:18:17.709943 [Byte1]: 38
8617 22:18:17.714443
8618 22:18:17.714536 Set Vref, RX VrefLevel [Byte0]: 39
8619 22:18:17.717825 [Byte1]: 39
8620 22:18:17.722169
8621 22:18:17.722263 Set Vref, RX VrefLevel [Byte0]: 40
8622 22:18:17.725371 [Byte1]: 40
8623 22:18:17.729493
8624 22:18:17.729588 Set Vref, RX VrefLevel [Byte0]: 41
8625 22:18:17.732646 [Byte1]: 41
8626 22:18:17.736955
8627 22:18:17.737046 Set Vref, RX VrefLevel [Byte0]: 42
8628 22:18:17.740536 [Byte1]: 42
8629 22:18:17.744933
8630 22:18:17.745026 Set Vref, RX VrefLevel [Byte0]: 43
8631 22:18:17.747845 [Byte1]: 43
8632 22:18:17.751998
8633 22:18:17.752101 Set Vref, RX VrefLevel [Byte0]: 44
8634 22:18:17.755327 [Byte1]: 44
8635 22:18:17.759883
8636 22:18:17.759977 Set Vref, RX VrefLevel [Byte0]: 45
8637 22:18:17.762956 [Byte1]: 45
8638 22:18:17.767453
8639 22:18:17.767551 Set Vref, RX VrefLevel [Byte0]: 46
8640 22:18:17.770755 [Byte1]: 46
8641 22:18:17.774688
8642 22:18:17.774776 Set Vref, RX VrefLevel [Byte0]: 47
8643 22:18:17.778073 [Byte1]: 47
8644 22:18:17.782252
8645 22:18:17.782340 Set Vref, RX VrefLevel [Byte0]: 48
8646 22:18:17.786055 [Byte1]: 48
8647 22:18:17.790449
8648 22:18:17.790542 Set Vref, RX VrefLevel [Byte0]: 49
8649 22:18:17.793160 [Byte1]: 49
8650 22:18:17.797437
8651 22:18:17.797564 Set Vref, RX VrefLevel [Byte0]: 50
8652 22:18:17.800855 [Byte1]: 50
8653 22:18:17.804923
8654 22:18:17.805033 Set Vref, RX VrefLevel [Byte0]: 51
8655 22:18:17.808361 [Byte1]: 51
8656 22:18:17.812516
8657 22:18:17.812615 Set Vref, RX VrefLevel [Byte0]: 52
8658 22:18:17.815764 [Byte1]: 52
8659 22:18:17.820245
8660 22:18:17.820347 Set Vref, RX VrefLevel [Byte0]: 53
8661 22:18:17.823426 [Byte1]: 53
8662 22:18:17.827871
8663 22:18:17.827964 Set Vref, RX VrefLevel [Byte0]: 54
8664 22:18:17.831262 [Byte1]: 54
8665 22:18:17.835635
8666 22:18:17.835730 Set Vref, RX VrefLevel [Byte0]: 55
8667 22:18:17.838474 [Byte1]: 55
8668 22:18:17.843070
8669 22:18:17.843165 Set Vref, RX VrefLevel [Byte0]: 56
8670 22:18:17.846345 [Byte1]: 56
8671 22:18:17.850705
8672 22:18:17.850800 Set Vref, RX VrefLevel [Byte0]: 57
8673 22:18:17.853644 [Byte1]: 57
8674 22:18:17.858271
8675 22:18:17.858368 Set Vref, RX VrefLevel [Byte0]: 58
8676 22:18:17.861414 [Byte1]: 58
8677 22:18:17.865686
8678 22:18:17.865795 Set Vref, RX VrefLevel [Byte0]: 59
8679 22:18:17.869099 [Byte1]: 59
8680 22:18:17.873050
8681 22:18:17.873144 Set Vref, RX VrefLevel [Byte0]: 60
8682 22:18:17.876443 [Byte1]: 60
8683 22:18:17.881109
8684 22:18:17.881202 Set Vref, RX VrefLevel [Byte0]: 61
8685 22:18:17.884018 [Byte1]: 61
8686 22:18:17.888339
8687 22:18:17.888430 Set Vref, RX VrefLevel [Byte0]: 62
8688 22:18:17.891952 [Byte1]: 62
8689 22:18:17.895805
8690 22:18:17.895905 Set Vref, RX VrefLevel [Byte0]: 63
8691 22:18:17.899307 [Byte1]: 63
8692 22:18:17.903747
8693 22:18:17.903844 Set Vref, RX VrefLevel [Byte0]: 64
8694 22:18:17.906798 [Byte1]: 64
8695 22:18:17.911127
8696 22:18:17.911222 Set Vref, RX VrefLevel [Byte0]: 65
8697 22:18:17.914482 [Byte1]: 65
8698 22:18:17.918848
8699 22:18:17.918939 Set Vref, RX VrefLevel [Byte0]: 66
8700 22:18:17.921787 [Byte1]: 66
8701 22:18:17.926106
8702 22:18:17.926200 Set Vref, RX VrefLevel [Byte0]: 67
8703 22:18:17.929574 [Byte1]: 67
8704 22:18:17.934148
8705 22:18:17.934241 Set Vref, RX VrefLevel [Byte0]: 68
8706 22:18:17.937244 [Byte1]: 68
8707 22:18:17.941341
8708 22:18:17.941433 Set Vref, RX VrefLevel [Byte0]: 69
8709 22:18:17.944586 [Byte1]: 69
8710 22:18:17.948999
8711 22:18:17.949092 Set Vref, RX VrefLevel [Byte0]: 70
8712 22:18:17.952327 [Byte1]: 70
8713 22:18:17.956735
8714 22:18:17.956831 Set Vref, RX VrefLevel [Byte0]: 71
8715 22:18:17.960016 [Byte1]: 71
8716 22:18:17.963991
8717 22:18:17.964142 Final RX Vref Byte 0 = 56 to rank0
8718 22:18:17.967419 Final RX Vref Byte 1 = 60 to rank0
8719 22:18:17.970820 Final RX Vref Byte 0 = 56 to rank1
8720 22:18:17.974524 Final RX Vref Byte 1 = 60 to rank1==
8721 22:18:17.977607 Dram Type= 6, Freq= 0, CH_1, rank 0
8722 22:18:17.984169 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8723 22:18:17.984270 ==
8724 22:18:17.984339 DQS Delay:
8725 22:18:17.987083 DQS0 = 0, DQS1 = 0
8726 22:18:17.987180 DQM Delay:
8727 22:18:17.987247 DQM0 = 133, DQM1 = 130
8728 22:18:17.990436 DQ Delay:
8729 22:18:17.993725 DQ0 =142, DQ1 =130, DQ2 =118, DQ3 =132
8730 22:18:17.997196 DQ4 =130, DQ5 =142, DQ6 =146, DQ7 =126
8731 22:18:18.000184 DQ8 =116, DQ9 =118, DQ10 =132, DQ11 =120
8732 22:18:18.003713 DQ12 =142, DQ13 =140, DQ14 =136, DQ15 =140
8733 22:18:18.003829
8734 22:18:18.003926
8735 22:18:18.004015
8736 22:18:18.007501 [DramC_TX_OE_Calibration] TA2
8737 22:18:18.010337 Original DQ_B0 (3 6) =30, OEN = 27
8738 22:18:18.013622 Original DQ_B1 (3 6) =30, OEN = 27
8739 22:18:18.016554 24, 0x0, End_B0=24 End_B1=24
8740 22:18:18.020320 25, 0x0, End_B0=25 End_B1=25
8741 22:18:18.020411 26, 0x0, End_B0=26 End_B1=26
8742 22:18:18.023486 27, 0x0, End_B0=27 End_B1=27
8743 22:18:18.026851 28, 0x0, End_B0=28 End_B1=28
8744 22:18:18.029971 29, 0x0, End_B0=29 End_B1=29
8745 22:18:18.030061 30, 0x0, End_B0=30 End_B1=30
8746 22:18:18.033572 31, 0x4141, End_B0=30 End_B1=30
8747 22:18:18.036455 Byte0 end_step=30 best_step=27
8748 22:18:18.040066 Byte1 end_step=30 best_step=27
8749 22:18:18.043086 Byte0 TX OE(2T, 0.5T) = (3, 3)
8750 22:18:18.046155 Byte1 TX OE(2T, 0.5T) = (3, 3)
8751 22:18:18.046242
8752 22:18:18.046309
8753 22:18:18.053061 [DQSOSCAuto] RK0, (LSB)MR18= 0xb15, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 404 ps
8754 22:18:18.055923 CH1 RK0: MR19=303, MR18=B15
8755 22:18:18.062894 CH1_RK0: MR19=0x303, MR18=0xB15, DQSOSC=399, MR23=63, INC=23, DEC=15
8756 22:18:18.063004
8757 22:18:18.066070 ----->DramcWriteLeveling(PI) begin...
8758 22:18:18.066158 ==
8759 22:18:18.069472 Dram Type= 6, Freq= 0, CH_1, rank 1
8760 22:18:18.072765 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8761 22:18:18.072856 ==
8762 22:18:18.075781 Write leveling (Byte 0): 26 => 26
8763 22:18:18.079445 Write leveling (Byte 1): 28 => 28
8764 22:18:18.082388 DramcWriteLeveling(PI) end<-----
8765 22:18:18.082474
8766 22:18:18.082539 ==
8767 22:18:18.085731 Dram Type= 6, Freq= 0, CH_1, rank 1
8768 22:18:18.089211 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8769 22:18:18.092657 ==
8770 22:18:18.092752 [Gating] SW mode calibration
8771 22:18:18.102655 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8772 22:18:18.105411 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8773 22:18:18.109311 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8774 22:18:18.115564 1 4 4 | B1->B0 | 2323 2323 | 0 1 | (0 0) (1 1)
8775 22:18:18.118899 1 4 8 | B1->B0 | 2323 3333 | 0 1 | (0 0) (1 1)
8776 22:18:18.122310 1 4 12 | B1->B0 | 2625 3434 | 1 1 | (0 0) (1 1)
8777 22:18:18.128719 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8778 22:18:18.131862 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8779 22:18:18.135144 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8780 22:18:18.141597 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8781 22:18:18.145111 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8782 22:18:18.148768 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8783 22:18:18.155063 1 5 8 | B1->B0 | 3434 2323 | 1 0 | (1 0) (1 0)
8784 22:18:18.158083 1 5 12 | B1->B0 | 3434 2323 | 0 0 | (0 0) (0 0)
8785 22:18:18.161614 1 5 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8786 22:18:18.168351 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8787 22:18:18.171599 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8788 22:18:18.177713 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8789 22:18:18.181284 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8790 22:18:18.184248 1 6 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
8791 22:18:18.190936 1 6 8 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8792 22:18:18.194598 1 6 12 | B1->B0 | 2929 4646 | 1 0 | (0 0) (0 0)
8793 22:18:18.197341 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8794 22:18:18.204108 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8795 22:18:18.207491 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8796 22:18:18.211141 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8797 22:18:18.217490 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8798 22:18:18.220462 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8799 22:18:18.223587 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8800 22:18:18.230163 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8801 22:18:18.234001 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8802 22:18:18.237050 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8803 22:18:18.243694 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8804 22:18:18.246595 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8805 22:18:18.249999 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8806 22:18:18.257228 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8807 22:18:18.260161 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8808 22:18:18.263631 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8809 22:18:18.270176 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8810 22:18:18.273181 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8811 22:18:18.276284 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8812 22:18:18.282745 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8813 22:18:18.286148 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8814 22:18:18.289564 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8815 22:18:18.296469 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8816 22:18:18.299597 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8817 22:18:18.302883 Total UI for P1: 0, mck2ui 16
8818 22:18:18.306031 best dqsien dly found for B0: ( 1, 9, 8)
8819 22:18:18.309673 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8820 22:18:18.316152 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8821 22:18:18.316257 Total UI for P1: 0, mck2ui 16
8822 22:18:18.322729 best dqsien dly found for B1: ( 1, 9, 14)
8823 22:18:18.325964 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8824 22:18:18.329266 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8825 22:18:18.329356
8826 22:18:18.333582 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8827 22:18:18.336004 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8828 22:18:18.339278 [Gating] SW calibration Done
8829 22:18:18.339365 ==
8830 22:18:18.342171 Dram Type= 6, Freq= 0, CH_1, rank 1
8831 22:18:18.345541 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8832 22:18:18.345630 ==
8833 22:18:18.348866 RX Vref Scan: 0
8834 22:18:18.348953
8835 22:18:18.349018 RX Vref 0 -> 0, step: 1
8836 22:18:18.349078
8837 22:18:18.352170 RX Delay 0 -> 252, step: 8
8838 22:18:18.355382 iDelay=200, Bit 0, Center 143 (88 ~ 199) 112
8839 22:18:18.362556 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8840 22:18:18.365209 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
8841 22:18:18.368639 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8842 22:18:18.371841 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8843 22:18:18.375032 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8844 22:18:18.382392 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8845 22:18:18.385116 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8846 22:18:18.388979 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8847 22:18:18.391519 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8848 22:18:18.398242 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8849 22:18:18.401285 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8850 22:18:18.404590 iDelay=200, Bit 12, Center 139 (80 ~ 199) 120
8851 22:18:18.408312 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8852 22:18:18.411182 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8853 22:18:18.417965 iDelay=200, Bit 15, Center 143 (88 ~ 199) 112
8854 22:18:18.418070 ==
8855 22:18:18.421249 Dram Type= 6, Freq= 0, CH_1, rank 1
8856 22:18:18.424290 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8857 22:18:18.424379 ==
8858 22:18:18.424444 DQS Delay:
8859 22:18:18.428011 DQS0 = 0, DQS1 = 0
8860 22:18:18.428137 DQM Delay:
8861 22:18:18.431202 DQM0 = 136, DQM1 = 131
8862 22:18:18.431286 DQ Delay:
8863 22:18:18.434363 DQ0 =143, DQ1 =135, DQ2 =123, DQ3 =131
8864 22:18:18.437638 DQ4 =131, DQ5 =147, DQ6 =143, DQ7 =135
8865 22:18:18.441427 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =127
8866 22:18:18.447699 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =143
8867 22:18:18.447810
8868 22:18:18.447912
8869 22:18:18.448011 ==
8870 22:18:18.451093 Dram Type= 6, Freq= 0, CH_1, rank 1
8871 22:18:18.454014 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8872 22:18:18.454104 ==
8873 22:18:18.454190
8874 22:18:18.454270
8875 22:18:18.457364 TX Vref Scan disable
8876 22:18:18.457450 == TX Byte 0 ==
8877 22:18:18.464449 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8878 22:18:18.467516 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8879 22:18:18.467612 == TX Byte 1 ==
8880 22:18:18.474070 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8881 22:18:18.477426 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8882 22:18:18.477525 ==
8883 22:18:18.480634 Dram Type= 6, Freq= 0, CH_1, rank 1
8884 22:18:18.484077 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8885 22:18:18.484180 ==
8886 22:18:18.498638
8887 22:18:18.502330 TX Vref early break, caculate TX vref
8888 22:18:18.505210 TX Vref=16, minBit 9, minWin=21, winSum=375
8889 22:18:18.508897 TX Vref=18, minBit 9, minWin=22, winSum=387
8890 22:18:18.512073 TX Vref=20, minBit 9, minWin=22, winSum=390
8891 22:18:18.515185 TX Vref=22, minBit 9, minWin=23, winSum=400
8892 22:18:18.518742 TX Vref=24, minBit 9, minWin=24, winSum=408
8893 22:18:18.524933 TX Vref=26, minBit 9, minWin=24, winSum=415
8894 22:18:18.528208 TX Vref=28, minBit 9, minWin=24, winSum=418
8895 22:18:18.531404 TX Vref=30, minBit 8, minWin=25, winSum=415
8896 22:18:18.534874 TX Vref=32, minBit 9, minWin=24, winSum=410
8897 22:18:18.538318 TX Vref=34, minBit 0, minWin=24, winSum=402
8898 22:18:18.544798 TX Vref=36, minBit 0, minWin=24, winSum=394
8899 22:18:18.548255 [TxChooseVref] Worse bit 8, Min win 25, Win sum 415, Final Vref 30
8900 22:18:18.548353
8901 22:18:18.551278 Final TX Range 0 Vref 30
8902 22:18:18.551366
8903 22:18:18.551451 ==
8904 22:18:18.554568 Dram Type= 6, Freq= 0, CH_1, rank 1
8905 22:18:18.557783 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8906 22:18:18.561177 ==
8907 22:18:18.561270
8908 22:18:18.561356
8909 22:18:18.561435 TX Vref Scan disable
8910 22:18:18.567691 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8911 22:18:18.567788 == TX Byte 0 ==
8912 22:18:18.571031 u2DelayCellOfst[0]=14 cells (4 PI)
8913 22:18:18.574226 u2DelayCellOfst[1]=10 cells (3 PI)
8914 22:18:18.577319 u2DelayCellOfst[2]=0 cells (0 PI)
8915 22:18:18.580967 u2DelayCellOfst[3]=7 cells (2 PI)
8916 22:18:18.584010 u2DelayCellOfst[4]=7 cells (2 PI)
8917 22:18:18.587593 u2DelayCellOfst[5]=14 cells (4 PI)
8918 22:18:18.590679 u2DelayCellOfst[6]=14 cells (4 PI)
8919 22:18:18.594361 u2DelayCellOfst[7]=7 cells (2 PI)
8920 22:18:18.597434 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8921 22:18:18.600541 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8922 22:18:18.603750 == TX Byte 1 ==
8923 22:18:18.607316 u2DelayCellOfst[8]=0 cells (0 PI)
8924 22:18:18.610758 u2DelayCellOfst[9]=3 cells (1 PI)
8925 22:18:18.613915 u2DelayCellOfst[10]=10 cells (3 PI)
8926 22:18:18.616996 u2DelayCellOfst[11]=7 cells (2 PI)
8927 22:18:18.620762 u2DelayCellOfst[12]=14 cells (4 PI)
8928 22:18:18.623617 u2DelayCellOfst[13]=17 cells (5 PI)
8929 22:18:18.627170 u2DelayCellOfst[14]=17 cells (5 PI)
8930 22:18:18.630334 u2DelayCellOfst[15]=17 cells (5 PI)
8931 22:18:18.634135 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8932 22:18:18.637186 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8933 22:18:18.640355 DramC Write-DBI on
8934 22:18:18.640445 ==
8935 22:18:18.644249 Dram Type= 6, Freq= 0, CH_1, rank 1
8936 22:18:18.647197 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8937 22:18:18.647288 ==
8938 22:18:18.647354
8939 22:18:18.647415
8940 22:18:18.650006 TX Vref Scan disable
8941 22:18:18.650092 == TX Byte 0 ==
8942 22:18:18.656802 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8943 22:18:18.656901 == TX Byte 1 ==
8944 22:18:18.663130 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8945 22:18:18.663227 DramC Write-DBI off
8946 22:18:18.663295
8947 22:18:18.663357 [DATLAT]
8948 22:18:18.666796 Freq=1600, CH1 RK1
8949 22:18:18.666883
8950 22:18:18.669962 DATLAT Default: 0xf
8951 22:18:18.670048 0, 0xFFFF, sum = 0
8952 22:18:18.673513 1, 0xFFFF, sum = 0
8953 22:18:18.673601 2, 0xFFFF, sum = 0
8954 22:18:18.676434 3, 0xFFFF, sum = 0
8955 22:18:18.676520 4, 0xFFFF, sum = 0
8956 22:18:18.679855 5, 0xFFFF, sum = 0
8957 22:18:18.679942 6, 0xFFFF, sum = 0
8958 22:18:18.682960 7, 0xFFFF, sum = 0
8959 22:18:18.683047 8, 0xFFFF, sum = 0
8960 22:18:18.686513 9, 0xFFFF, sum = 0
8961 22:18:18.686601 10, 0xFFFF, sum = 0
8962 22:18:18.689810 11, 0xFFFF, sum = 0
8963 22:18:18.689898 12, 0xFFFF, sum = 0
8964 22:18:18.693193 13, 0xFFFF, sum = 0
8965 22:18:18.693285 14, 0x0, sum = 1
8966 22:18:18.696189 15, 0x0, sum = 2
8967 22:18:18.696280 16, 0x0, sum = 3
8968 22:18:18.699570 17, 0x0, sum = 4
8969 22:18:18.699657 best_step = 15
8970 22:18:18.699724
8971 22:18:18.699785 ==
8972 22:18:18.703606 Dram Type= 6, Freq= 0, CH_1, rank 1
8973 22:18:18.709646 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8974 22:18:18.709750 ==
8975 22:18:18.709821 RX Vref Scan: 0
8976 22:18:18.709882
8977 22:18:18.712841 RX Vref 0 -> 0, step: 1
8978 22:18:18.712926
8979 22:18:18.716152 RX Delay 19 -> 252, step: 4
8980 22:18:18.719510 iDelay=195, Bit 0, Center 136 (87 ~ 186) 100
8981 22:18:18.722703 iDelay=195, Bit 1, Center 130 (79 ~ 182) 104
8982 22:18:18.725936 iDelay=195, Bit 2, Center 120 (67 ~ 174) 108
8983 22:18:18.732502 iDelay=195, Bit 3, Center 130 (79 ~ 182) 104
8984 22:18:18.735891 iDelay=195, Bit 4, Center 130 (75 ~ 186) 112
8985 22:18:18.739434 iDelay=195, Bit 5, Center 144 (95 ~ 194) 100
8986 22:18:18.742679 iDelay=195, Bit 6, Center 142 (91 ~ 194) 104
8987 22:18:18.745959 iDelay=195, Bit 7, Center 130 (79 ~ 182) 104
8988 22:18:18.752480 iDelay=195, Bit 8, Center 114 (59 ~ 170) 112
8989 22:18:18.755660 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8990 22:18:18.758798 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
8991 22:18:18.762038 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8992 22:18:18.768735 iDelay=195, Bit 12, Center 136 (83 ~ 190) 108
8993 22:18:18.771837 iDelay=195, Bit 13, Center 136 (83 ~ 190) 108
8994 22:18:18.775159 iDelay=195, Bit 14, Center 132 (79 ~ 186) 108
8995 22:18:18.778979 iDelay=195, Bit 15, Center 138 (87 ~ 190) 104
8996 22:18:18.779074 ==
8997 22:18:18.782220 Dram Type= 6, Freq= 0, CH_1, rank 1
8998 22:18:18.788314 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8999 22:18:18.788420 ==
9000 22:18:18.788490 DQS Delay:
9001 22:18:18.791976 DQS0 = 0, DQS1 = 0
9002 22:18:18.792104 DQM Delay:
9003 22:18:18.795086 DQM0 = 132, DQM1 = 127
9004 22:18:18.795175 DQ Delay:
9005 22:18:18.798310 DQ0 =136, DQ1 =130, DQ2 =120, DQ3 =130
9006 22:18:18.801987 DQ4 =130, DQ5 =144, DQ6 =142, DQ7 =130
9007 22:18:18.804897 DQ8 =114, DQ9 =118, DQ10 =128, DQ11 =120
9008 22:18:18.808356 DQ12 =136, DQ13 =136, DQ14 =132, DQ15 =138
9009 22:18:18.808448
9010 22:18:18.808515
9011 22:18:18.808575
9012 22:18:18.811291 [DramC_TX_OE_Calibration] TA2
9013 22:18:18.814983 Original DQ_B0 (3 6) =30, OEN = 27
9014 22:18:18.818076 Original DQ_B1 (3 6) =30, OEN = 27
9015 22:18:18.821766 24, 0x0, End_B0=24 End_B1=24
9016 22:18:18.824612 25, 0x0, End_B0=25 End_B1=25
9017 22:18:18.824702 26, 0x0, End_B0=26 End_B1=26
9018 22:18:18.828269 27, 0x0, End_B0=27 End_B1=27
9019 22:18:18.831298 28, 0x0, End_B0=28 End_B1=28
9020 22:18:18.834667 29, 0x0, End_B0=29 End_B1=29
9021 22:18:18.837802 30, 0x0, End_B0=30 End_B1=30
9022 22:18:18.837891 31, 0x4141, End_B0=30 End_B1=30
9023 22:18:18.841302 Byte0 end_step=30 best_step=27
9024 22:18:18.844239 Byte1 end_step=30 best_step=27
9025 22:18:18.847572 Byte0 TX OE(2T, 0.5T) = (3, 3)
9026 22:18:18.850924 Byte1 TX OE(2T, 0.5T) = (3, 3)
9027 22:18:18.851015
9028 22:18:18.851082
9029 22:18:18.857234 [DQSOSCAuto] RK1, (LSB)MR18= 0xc1a, (MSB)MR19= 0x303, tDQSOscB0 = 396 ps tDQSOscB1 = 403 ps
9030 22:18:18.860691 CH1 RK1: MR19=303, MR18=C1A
9031 22:18:18.867722 CH1_RK1: MR19=0x303, MR18=0xC1A, DQSOSC=396, MR23=63, INC=23, DEC=15
9032 22:18:18.870662 [RxdqsGatingPostProcess] freq 1600
9033 22:18:18.877140 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9034 22:18:18.877251 best DQS0 dly(2T, 0.5T) = (1, 1)
9035 22:18:18.880711 best DQS1 dly(2T, 0.5T) = (1, 1)
9036 22:18:18.883539 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9037 22:18:18.887002 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9038 22:18:18.890488 best DQS0 dly(2T, 0.5T) = (1, 1)
9039 22:18:18.893539 best DQS1 dly(2T, 0.5T) = (1, 1)
9040 22:18:18.896936 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9041 22:18:18.899921 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9042 22:18:18.903372 Pre-setting of DQS Precalculation
9043 22:18:18.906779 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9044 22:18:18.916618 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9045 22:18:18.922989 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9046 22:18:18.923106
9047 22:18:18.923176
9048 22:18:18.926124 [Calibration Summary] 3200 Mbps
9049 22:18:18.926210 CH 0, Rank 0
9050 22:18:18.929432 SW Impedance : PASS
9051 22:18:18.932672 DUTY Scan : NO K
9052 22:18:18.932760 ZQ Calibration : PASS
9053 22:18:18.935913 Jitter Meter : NO K
9054 22:18:18.939525 CBT Training : PASS
9055 22:18:18.939613 Write leveling : PASS
9056 22:18:18.942690 RX DQS gating : PASS
9057 22:18:18.946255 RX DQ/DQS(RDDQC) : PASS
9058 22:18:18.946341 TX DQ/DQS : PASS
9059 22:18:18.949438 RX DATLAT : PASS
9060 22:18:18.949523 RX DQ/DQS(Engine): PASS
9061 22:18:18.952827 TX OE : PASS
9062 22:18:18.952912 All Pass.
9063 22:18:18.952978
9064 22:18:18.956206 CH 0, Rank 1
9065 22:18:18.956291 SW Impedance : PASS
9066 22:18:18.959203 DUTY Scan : NO K
9067 22:18:18.962799 ZQ Calibration : PASS
9068 22:18:18.962887 Jitter Meter : NO K
9069 22:18:18.965505 CBT Training : PASS
9070 22:18:18.968878 Write leveling : PASS
9071 22:18:18.968963 RX DQS gating : PASS
9072 22:18:18.972455 RX DQ/DQS(RDDQC) : PASS
9073 22:18:18.975767 TX DQ/DQS : PASS
9074 22:18:18.975855 RX DATLAT : PASS
9075 22:18:18.979233 RX DQ/DQS(Engine): PASS
9076 22:18:18.981990 TX OE : PASS
9077 22:18:18.982076 All Pass.
9078 22:18:18.982142
9079 22:18:18.982204 CH 1, Rank 0
9080 22:18:18.985367 SW Impedance : PASS
9081 22:18:18.988776 DUTY Scan : NO K
9082 22:18:18.988862 ZQ Calibration : PASS
9083 22:18:18.991940 Jitter Meter : NO K
9084 22:18:18.995518 CBT Training : PASS
9085 22:18:18.995613 Write leveling : PASS
9086 22:18:18.998766 RX DQS gating : PASS
9087 22:18:19.001862 RX DQ/DQS(RDDQC) : PASS
9088 22:18:19.001953 TX DQ/DQS : PASS
9089 22:18:19.004983 RX DATLAT : PASS
9090 22:18:19.008293 RX DQ/DQS(Engine): PASS
9091 22:18:19.008381 TX OE : PASS
9092 22:18:19.011729 All Pass.
9093 22:18:19.011815
9094 22:18:19.011882 CH 1, Rank 1
9095 22:18:19.014891 SW Impedance : PASS
9096 22:18:19.014976 DUTY Scan : NO K
9097 22:18:19.018573 ZQ Calibration : PASS
9098 22:18:19.021293 Jitter Meter : NO K
9099 22:18:19.021381 CBT Training : PASS
9100 22:18:19.024672 Write leveling : PASS
9101 22:18:19.028159 RX DQS gating : PASS
9102 22:18:19.028246 RX DQ/DQS(RDDQC) : PASS
9103 22:18:19.031750 TX DQ/DQS : PASS
9104 22:18:19.035037 RX DATLAT : PASS
9105 22:18:19.035125 RX DQ/DQS(Engine): PASS
9106 22:18:19.038148 TX OE : PASS
9107 22:18:19.038235 All Pass.
9108 22:18:19.038302
9109 22:18:19.041125 DramC Write-DBI on
9110 22:18:19.044616 PER_BANK_REFRESH: Hybrid Mode
9111 22:18:19.044705 TX_TRACKING: ON
9112 22:18:19.054577 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9113 22:18:19.061304 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9114 22:18:19.067831 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9115 22:18:19.070973 [FAST_K] Save calibration result to emmc
9116 22:18:19.074296 sync common calibartion params.
9117 22:18:19.077620 sync cbt_mode0:1, 1:1
9118 22:18:19.080742 dram_init: ddr_geometry: 2
9119 22:18:19.080835 dram_init: ddr_geometry: 2
9120 22:18:19.084062 dram_init: ddr_geometry: 2
9121 22:18:19.087711 0:dram_rank_size:100000000
9122 22:18:19.090826 1:dram_rank_size:100000000
9123 22:18:19.093877 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9124 22:18:19.097329 DFS_SHUFFLE_HW_MODE: ON
9125 22:18:19.100866 dramc_set_vcore_voltage set vcore to 725000
9126 22:18:19.104015 Read voltage for 1600, 0
9127 22:18:19.104129 Vio18 = 0
9128 22:18:19.104197 Vcore = 725000
9129 22:18:19.107186 Vdram = 0
9130 22:18:19.107271 Vddq = 0
9131 22:18:19.107338 Vmddr = 0
9132 22:18:19.110421 switch to 3200 Mbps bootup
9133 22:18:19.113711 [DramcRunTimeConfig]
9134 22:18:19.113799 PHYPLL
9135 22:18:19.113867 DPM_CONTROL_AFTERK: ON
9136 22:18:19.117210 PER_BANK_REFRESH: ON
9137 22:18:19.120620 REFRESH_OVERHEAD_REDUCTION: ON
9138 22:18:19.120709 CMD_PICG_NEW_MODE: OFF
9139 22:18:19.123913 XRTWTW_NEW_MODE: ON
9140 22:18:19.127126 XRTRTR_NEW_MODE: ON
9141 22:18:19.127213 TX_TRACKING: ON
9142 22:18:19.130584 RDSEL_TRACKING: OFF
9143 22:18:19.130669 DQS Precalculation for DVFS: ON
9144 22:18:19.133614 RX_TRACKING: OFF
9145 22:18:19.133699 HW_GATING DBG: ON
9146 22:18:19.137359 ZQCS_ENABLE_LP4: ON
9147 22:18:19.140142 RX_PICG_NEW_MODE: ON
9148 22:18:19.140228 TX_PICG_NEW_MODE: ON
9149 22:18:19.143723 ENABLE_RX_DCM_DPHY: ON
9150 22:18:19.146612 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9151 22:18:19.146698 DUMMY_READ_FOR_TRACKING: OFF
9152 22:18:19.150174 !!! SPM_CONTROL_AFTERK: OFF
9153 22:18:19.153484 !!! SPM could not control APHY
9154 22:18:19.156894 IMPEDANCE_TRACKING: ON
9155 22:18:19.156982 TEMP_SENSOR: ON
9156 22:18:19.160066 HW_SAVE_FOR_SR: OFF
9157 22:18:19.163065 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9158 22:18:19.166790 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9159 22:18:19.166918 Read ODT Tracking: ON
9160 22:18:19.170348 Refresh Rate DeBounce: ON
9161 22:18:19.173386 DFS_NO_QUEUE_FLUSH: ON
9162 22:18:19.176444 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9163 22:18:19.176532 ENABLE_DFS_RUNTIME_MRW: OFF
9164 22:18:19.179487 DDR_RESERVE_NEW_MODE: ON
9165 22:18:19.182939 MR_CBT_SWITCH_FREQ: ON
9166 22:18:19.183025 =========================
9167 22:18:19.202835 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9168 22:18:19.206311 dram_init: ddr_geometry: 2
9169 22:18:19.224669 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9170 22:18:19.227895 dram_init: dram init end (result: 0)
9171 22:18:19.235004 DRAM-K: Full calibration passed in 24395 msecs
9172 22:18:19.237777 MRC: failed to locate region type 0.
9173 22:18:19.237883 DRAM rank0 size:0x100000000,
9174 22:18:19.240849 DRAM rank1 size=0x100000000
9175 22:18:19.251434 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9176 22:18:19.257522 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9177 22:18:19.263936 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9178 22:18:19.274079 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9179 22:18:19.274216 DRAM rank0 size:0x100000000,
9180 22:18:19.277231 DRAM rank1 size=0x100000000
9181 22:18:19.277318 CBMEM:
9182 22:18:19.280800 IMD: root @ 0xfffff000 254 entries.
9183 22:18:19.284285 IMD: root @ 0xffffec00 62 entries.
9184 22:18:19.287039 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9185 22:18:19.293625 WARNING: RO_VPD is uninitialized or empty.
9186 22:18:19.297205 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9187 22:18:19.304817 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9188 22:18:19.317400 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9189 22:18:19.328663 BS: romstage times (exec / console): total (unknown) / 23926 ms
9190 22:18:19.328810
9191 22:18:19.328878
9192 22:18:19.338489 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9193 22:18:19.341898 ARM64: Exception handlers installed.
9194 22:18:19.345507 ARM64: Testing exception
9195 22:18:19.348381 ARM64: Done test exception
9196 22:18:19.348473 Enumerating buses...
9197 22:18:19.351703 Show all devs... Before device enumeration.
9198 22:18:19.355178 Root Device: enabled 1
9199 22:18:19.358579 CPU_CLUSTER: 0: enabled 1
9200 22:18:19.358685 CPU: 00: enabled 1
9201 22:18:19.361815 Compare with tree...
9202 22:18:19.361889 Root Device: enabled 1
9203 22:18:19.364971 CPU_CLUSTER: 0: enabled 1
9204 22:18:19.368230 CPU: 00: enabled 1
9205 22:18:19.368341 Root Device scanning...
9206 22:18:19.371400 scan_static_bus for Root Device
9207 22:18:19.374835 CPU_CLUSTER: 0 enabled
9208 22:18:19.377807 scan_static_bus for Root Device done
9209 22:18:19.381657 scan_bus: bus Root Device finished in 8 msecs
9210 22:18:19.381749 done
9211 22:18:19.388013 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9212 22:18:19.392088 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9213 22:18:19.398553 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9214 22:18:19.403996 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9215 22:18:19.404152 Allocating resources...
9216 22:18:19.407600 Reading resources...
9217 22:18:19.411017 Root Device read_resources bus 0 link: 0
9218 22:18:19.414150 DRAM rank0 size:0x100000000,
9219 22:18:19.414246 DRAM rank1 size=0x100000000
9220 22:18:19.421287 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9221 22:18:19.421389 CPU: 00 missing read_resources
9222 22:18:19.427165 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9223 22:18:19.430953 Root Device read_resources bus 0 link: 0 done
9224 22:18:19.434366 Done reading resources.
9225 22:18:19.436935 Show resources in subtree (Root Device)...After reading.
9226 22:18:19.440791 Root Device child on link 0 CPU_CLUSTER: 0
9227 22:18:19.444256 CPU_CLUSTER: 0 child on link 0 CPU: 00
9228 22:18:19.453687 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9229 22:18:19.453814 CPU: 00
9230 22:18:19.460423 Root Device assign_resources, bus 0 link: 0
9231 22:18:19.463512 CPU_CLUSTER: 0 missing set_resources
9232 22:18:19.466916 Root Device assign_resources, bus 0 link: 0 done
9233 22:18:19.470289 Done setting resources.
9234 22:18:19.473128 Show resources in subtree (Root Device)...After assigning values.
9235 22:18:19.479805 Root Device child on link 0 CPU_CLUSTER: 0
9236 22:18:19.483456 CPU_CLUSTER: 0 child on link 0 CPU: 00
9237 22:18:19.489729 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9238 22:18:19.493025 CPU: 00
9239 22:18:19.493126 Done allocating resources.
9240 22:18:19.499643 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9241 22:18:19.502912 Enabling resources...
9242 22:18:19.503043 done.
9243 22:18:19.506202 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9244 22:18:19.509378 Initializing devices...
9245 22:18:19.509473 Root Device init
9246 22:18:19.512809 init hardware done!
9247 22:18:19.516352 0x00000018: ctrlr->caps
9248 22:18:19.516451 52.000 MHz: ctrlr->f_max
9249 22:18:19.519672 0.400 MHz: ctrlr->f_min
9250 22:18:19.522573 0x40ff8080: ctrlr->voltages
9251 22:18:19.522663 sclk: 390625
9252 22:18:19.522730 Bus Width = 1
9253 22:18:19.526059 sclk: 390625
9254 22:18:19.526146 Bus Width = 1
9255 22:18:19.529315 Early init status = 3
9256 22:18:19.532618 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9257 22:18:19.536346 in-header: 03 fc 00 00 01 00 00 00
9258 22:18:19.539555 in-data: 00
9259 22:18:19.542564 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9260 22:18:19.547539 in-header: 03 fd 00 00 00 00 00 00
9261 22:18:19.550740 in-data:
9262 22:18:19.553768 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9263 22:18:19.557479 in-header: 03 fc 00 00 01 00 00 00
9264 22:18:19.560622 in-data: 00
9265 22:18:19.563887 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9266 22:18:19.568932 in-header: 03 fd 00 00 00 00 00 00
9267 22:18:19.572343 in-data:
9268 22:18:19.575177 [SSUSB] Setting up USB HOST controller...
9269 22:18:19.578666 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9270 22:18:19.581873 [SSUSB] phy power-on done.
9271 22:18:19.585063 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9272 22:18:19.591952 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9273 22:18:19.595366 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9274 22:18:19.601637 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9275 22:18:19.608538 read SPI 0x50eb0 0x2ad3: 1175 us, 9330 KB/s, 74.640 Mbps
9276 22:18:19.614709 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9277 22:18:19.621225 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9278 22:18:19.627961 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9279 22:18:19.631543 SPM: binary array size = 0x9dc
9280 22:18:19.634500 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9281 22:18:19.641963 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9282 22:18:19.647732 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9283 22:18:19.654323 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9284 22:18:19.657725 configure_display: Starting display init
9285 22:18:19.691883 anx7625_power_on_init: Init interface.
9286 22:18:19.695521 anx7625_disable_pd_protocol: Disabled PD feature.
9287 22:18:19.698635 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9288 22:18:19.726421 anx7625_start_dp_work: Secure OCM version=00
9289 22:18:19.730034 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9290 22:18:19.744356 sp_tx_get_edid_block: EDID Block = 1
9291 22:18:19.847111 Extracted contents:
9292 22:18:19.850237 header: 00 ff ff ff ff ff ff 00
9293 22:18:19.853507 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9294 22:18:19.856946 version: 01 04
9295 22:18:19.860380 basic params: 95 1f 11 78 0a
9296 22:18:19.863801 chroma info: 76 90 94 55 54 90 27 21 50 54
9297 22:18:19.866685 established: 00 00 00
9298 22:18:19.873751 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9299 22:18:19.879806 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9300 22:18:19.883206 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9301 22:18:19.889960 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9302 22:18:19.896203 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9303 22:18:19.899629 extensions: 00
9304 22:18:19.899735 checksum: fb
9305 22:18:19.899802
9306 22:18:19.906270 Manufacturer: IVO Model 57d Serial Number 0
9307 22:18:19.906372 Made week 0 of 2020
9308 22:18:19.909456 EDID version: 1.4
9309 22:18:19.909564 Digital display
9310 22:18:19.913173 6 bits per primary color channel
9311 22:18:19.913264 DisplayPort interface
9312 22:18:19.915999 Maximum image size: 31 cm x 17 cm
9313 22:18:19.919653 Gamma: 220%
9314 22:18:19.919744 Check DPMS levels
9315 22:18:19.926087 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9316 22:18:19.929406 First detailed timing is preferred timing
9317 22:18:19.932742 Established timings supported:
9318 22:18:19.932835 Standard timings supported:
9319 22:18:19.935666 Detailed timings
9320 22:18:19.938917 Hex of detail: 383680a07038204018303c0035ae10000019
9321 22:18:19.946046 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9322 22:18:19.948975 0780 0798 07c8 0820 hborder 0
9323 22:18:19.952317 0438 043b 0447 0458 vborder 0
9324 22:18:19.955924 -hsync -vsync
9325 22:18:19.956017 Did detailed timing
9326 22:18:19.962028 Hex of detail: 000000000000000000000000000000000000
9327 22:18:19.965523 Manufacturer-specified data, tag 0
9328 22:18:19.969138 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9329 22:18:19.972957 ASCII string: InfoVision
9330 22:18:19.975582 Hex of detail: 000000fe00523134304e574635205248200a
9331 22:18:19.979052 ASCII string: R140NWF5 RH
9332 22:18:19.979145 Checksum
9333 22:18:19.982639 Checksum: 0xfb (valid)
9334 22:18:19.985542 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9335 22:18:19.988528 DSI data_rate: 832800000 bps
9336 22:18:19.995203 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9337 22:18:19.998325 anx7625_parse_edid: pixelclock(138800).
9338 22:18:20.001892 hactive(1920), hsync(48), hfp(24), hbp(88)
9339 22:18:20.005298 vactive(1080), vsync(12), vfp(3), vbp(17)
9340 22:18:20.008172 anx7625_dsi_config: config dsi.
9341 22:18:20.015023 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9342 22:18:20.028970 anx7625_dsi_config: success to config DSI
9343 22:18:20.032528 anx7625_dp_start: MIPI phy setup OK.
9344 22:18:20.035881 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9345 22:18:20.038991 mtk_ddp_mode_set invalid vrefresh 60
9346 22:18:20.043248 main_disp_path_setup
9347 22:18:20.043348 ovl_layer_smi_id_en
9348 22:18:20.045356 ovl_layer_smi_id_en
9349 22:18:20.045442 ccorr_config
9350 22:18:20.045508 aal_config
9351 22:18:20.049114 gamma_config
9352 22:18:20.049201 postmask_config
9353 22:18:20.052163 dither_config
9354 22:18:20.055362 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9355 22:18:20.061997 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9356 22:18:20.065255 Root Device init finished in 551 msecs
9357 22:18:20.068883 CPU_CLUSTER: 0 init
9358 22:18:20.075419 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9359 22:18:20.081806 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9360 22:18:20.081928 APU_MBOX 0x190000b0 = 0x10001
9361 22:18:20.085102 APU_MBOX 0x190001b0 = 0x10001
9362 22:18:20.088292 APU_MBOX 0x190005b0 = 0x10001
9363 22:18:20.091632 APU_MBOX 0x190006b0 = 0x10001
9364 22:18:20.098836 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9365 22:18:20.107861 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9366 22:18:20.120439 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9367 22:18:20.127112 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9368 22:18:20.138985 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9369 22:18:20.147991 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9370 22:18:20.151027 CPU_CLUSTER: 0 init finished in 81 msecs
9371 22:18:20.154647 Devices initialized
9372 22:18:20.157700 Show all devs... After init.
9373 22:18:20.157788 Root Device: enabled 1
9374 22:18:20.161092 CPU_CLUSTER: 0: enabled 1
9375 22:18:20.163992 CPU: 00: enabled 1
9376 22:18:20.167899 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9377 22:18:20.171180 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9378 22:18:20.174270 ELOG: NV offset 0x57f000 size 0x1000
9379 22:18:20.181089 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9380 22:18:20.187351 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9381 22:18:20.191373 ELOG: Event(17) added with size 13 at 2023-06-05 22:18:24 UTC
9382 22:18:20.197518 out: cmd=0x121: 03 db 21 01 00 00 00 00
9383 22:18:20.200593 in-header: 03 4b 00 00 2c 00 00 00
9384 22:18:20.210685 in-data: 14 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9385 22:18:20.217799 ELOG: Event(A1) added with size 10 at 2023-06-05 22:18:24 UTC
9386 22:18:20.223855 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9387 22:18:20.230664 ELOG: Event(A0) added with size 9 at 2023-06-05 22:18:24 UTC
9388 22:18:20.233553 elog_add_boot_reason: Logged dev mode boot
9389 22:18:20.240236 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9390 22:18:20.240353 Finalize devices...
9391 22:18:20.243356 Devices finalized
9392 22:18:20.247096 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9393 22:18:20.250111 Writing coreboot table at 0xffe64000
9394 22:18:20.253490 0. 000000000010a000-0000000000113fff: RAMSTAGE
9395 22:18:20.260244 1. 0000000040000000-00000000400fffff: RAM
9396 22:18:20.263832 2. 0000000040100000-000000004032afff: RAMSTAGE
9397 22:18:20.266970 3. 000000004032b000-00000000545fffff: RAM
9398 22:18:20.270129 4. 0000000054600000-000000005465ffff: BL31
9399 22:18:20.273443 5. 0000000054660000-00000000ffe63fff: RAM
9400 22:18:20.280040 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9401 22:18:20.283246 7. 0000000100000000-000000023fffffff: RAM
9402 22:18:20.286414 Passing 5 GPIOs to payload:
9403 22:18:20.289517 NAME | PORT | POLARITY | VALUE
9404 22:18:20.296067 EC in RW | 0x000000aa | low | undefined
9405 22:18:20.299654 EC interrupt | 0x00000005 | low | undefined
9406 22:18:20.302952 TPM interrupt | 0x000000ab | high | undefined
9407 22:18:20.309812 SD card detect | 0x00000011 | high | undefined
9408 22:18:20.312780 speaker enable | 0x00000093 | high | undefined
9409 22:18:20.316269 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9410 22:18:20.319544 in-header: 03 f9 00 00 02 00 00 00
9411 22:18:20.323430 in-data: 02 00
9412 22:18:20.326114 ADC[4]: Raw value=903325 ID=7
9413 22:18:20.329143 ADC[3]: Raw value=213546 ID=1
9414 22:18:20.329230 RAM Code: 0x71
9415 22:18:20.333023 ADC[6]: Raw value=75000 ID=0
9416 22:18:20.336149 ADC[5]: Raw value=213546 ID=1
9417 22:18:20.336237 SKU Code: 0x1
9418 22:18:20.342542 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum a53a
9419 22:18:20.342640 coreboot table: 964 bytes.
9420 22:18:20.345933 IMD ROOT 0. 0xfffff000 0x00001000
9421 22:18:20.348767 IMD SMALL 1. 0xffffe000 0x00001000
9422 22:18:20.352901 RO MCACHE 2. 0xffffc000 0x00001104
9423 22:18:20.355354 CONSOLE 3. 0xfff7c000 0x00080000
9424 22:18:20.359020 FMAP 4. 0xfff7b000 0x00000452
9425 22:18:20.362139 TIME STAMP 5. 0xfff7a000 0x00000910
9426 22:18:20.365635 VBOOT WORK 6. 0xfff66000 0x00014000
9427 22:18:20.368988 RAMOOPS 7. 0xffe66000 0x00100000
9428 22:18:20.372411 COREBOOT 8. 0xffe64000 0x00002000
9429 22:18:20.375375 IMD small region:
9430 22:18:20.378419 IMD ROOT 0. 0xffffec00 0x00000400
9431 22:18:20.381611 VPD 1. 0xffffeba0 0x0000004c
9432 22:18:20.385254 MMC STATUS 2. 0xffffeb80 0x00000004
9433 22:18:20.392337 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9434 22:18:20.392453 Probing TPM: done!
9435 22:18:20.398297 Connected to device vid:did:rid of 1ae0:0028:00
9436 22:18:20.405213 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523
9437 22:18:20.408576 Initialized TPM device CR50 revision 0
9438 22:18:20.411993 Checking cr50 for pending updates
9439 22:18:20.417395 Reading cr50 TPM mode
9440 22:18:20.426298 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9441 22:18:20.433217 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9442 22:18:20.472929 read SPI 0x3990ec 0x4f1b0: 34850 us, 9297 KB/s, 74.376 Mbps
9443 22:18:20.476232 Checking segment from ROM address 0x40100000
9444 22:18:20.479765 Checking segment from ROM address 0x4010001c
9445 22:18:20.486334 Loading segment from ROM address 0x40100000
9446 22:18:20.486446 code (compression=0)
9447 22:18:20.496090 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9448 22:18:20.502885 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9449 22:18:20.503020 it's not compressed!
9450 22:18:20.510029 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9451 22:18:20.516711 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9452 22:18:20.533401 Loading segment from ROM address 0x4010001c
9453 22:18:20.533564 Entry Point 0x80000000
9454 22:18:20.536470 Loaded segments
9455 22:18:20.539746 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9456 22:18:20.546552 Jumping to boot code at 0x80000000(0xffe64000)
9457 22:18:20.553247 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9458 22:18:20.559733 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9459 22:18:20.567696 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9460 22:18:20.571182 Checking segment from ROM address 0x40100000
9461 22:18:20.574445 Checking segment from ROM address 0x4010001c
9462 22:18:20.581412 Loading segment from ROM address 0x40100000
9463 22:18:20.581528 code (compression=1)
9464 22:18:20.587890 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9465 22:18:20.597927 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9466 22:18:20.598059 using LZMA
9467 22:18:20.605901 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9468 22:18:20.612705 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9469 22:18:20.616039 Loading segment from ROM address 0x4010001c
9470 22:18:20.616178 Entry Point 0x54601000
9471 22:18:20.619234 Loaded segments
9472 22:18:20.622638 NOTICE: MT8192 bl31_setup
9473 22:18:20.630000 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9474 22:18:20.633015 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9475 22:18:20.636786 WARNING: region 0:
9476 22:18:20.639559 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9477 22:18:20.639654 WARNING: region 1:
9478 22:18:20.646256 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9479 22:18:20.649880 WARNING: region 2:
9480 22:18:20.653415 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9481 22:18:20.657003 WARNING: region 3:
9482 22:18:20.659761 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9483 22:18:20.662938 WARNING: region 4:
9484 22:18:20.669613 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9485 22:18:20.669725 WARNING: region 5:
9486 22:18:20.673070 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9487 22:18:20.676467 WARNING: region 6:
9488 22:18:20.679806 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9489 22:18:20.683157 WARNING: region 7:
9490 22:18:20.686368 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9491 22:18:20.692760 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9492 22:18:20.696048 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9493 22:18:20.699577 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9494 22:18:20.706237 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9495 22:18:20.709933 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9496 22:18:20.712926 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9497 22:18:20.720460 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9498 22:18:20.722770 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9499 22:18:20.729249 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9500 22:18:20.732995 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9501 22:18:20.736390 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9502 22:18:20.742717 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9503 22:18:20.746222 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9504 22:18:20.749294 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9505 22:18:20.756278 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9506 22:18:20.759267 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9507 22:18:20.765757 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9508 22:18:20.769472 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9509 22:18:20.772532 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9510 22:18:20.779328 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9511 22:18:20.782318 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9512 22:18:20.789275 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9513 22:18:20.792797 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9514 22:18:20.796214 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9515 22:18:20.802199 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9516 22:18:20.805685 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9517 22:18:20.812804 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9518 22:18:20.815564 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9519 22:18:20.818873 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9520 22:18:20.825391 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9521 22:18:20.828660 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9522 22:18:20.835778 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9523 22:18:20.839447 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9524 22:18:20.842228 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9525 22:18:20.845497 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9526 22:18:20.851945 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9527 22:18:20.855730 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9528 22:18:20.858734 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9529 22:18:20.862653 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9530 22:18:20.868534 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9531 22:18:20.872529 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9532 22:18:20.875475 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9533 22:18:20.878671 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9534 22:18:20.885411 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9535 22:18:20.888756 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9536 22:18:20.892446 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9537 22:18:20.895435 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9538 22:18:20.901875 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9539 22:18:20.904993 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9540 22:18:20.912278 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9541 22:18:20.915366 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9542 22:18:20.918246 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9543 22:18:20.925055 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9544 22:18:20.928353 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9545 22:18:20.934732 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9546 22:18:20.938527 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9547 22:18:20.945654 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9548 22:18:20.949065 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9549 22:18:20.951385 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9550 22:18:20.957991 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9551 22:18:20.961360 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9552 22:18:20.968085 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9553 22:18:20.971314 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9554 22:18:20.977966 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9555 22:18:20.981611 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9556 22:18:20.987603 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9557 22:18:20.991490 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9558 22:18:20.994349 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9559 22:18:21.000972 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9560 22:18:21.004521 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9561 22:18:21.011073 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9562 22:18:21.014271 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9563 22:18:21.020741 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9564 22:18:21.024089 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9565 22:18:21.030787 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9566 22:18:21.034284 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9567 22:18:21.037556 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9568 22:18:21.044065 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9569 22:18:21.047970 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9570 22:18:21.054700 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9571 22:18:21.057737 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9572 22:18:21.064316 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9573 22:18:21.067516 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9574 22:18:21.070601 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9575 22:18:21.077454 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9576 22:18:21.080895 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9577 22:18:21.087254 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9578 22:18:21.090777 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9579 22:18:21.097311 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9580 22:18:21.100783 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9581 22:18:21.103754 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9582 22:18:21.110786 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9583 22:18:21.114019 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9584 22:18:21.120479 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9585 22:18:21.124327 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9586 22:18:21.130748 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9587 22:18:21.134005 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9588 22:18:21.137474 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9589 22:18:21.140798 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9590 22:18:21.147056 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9591 22:18:21.150478 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9592 22:18:21.153764 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9593 22:18:21.160360 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9594 22:18:21.163855 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9595 22:18:21.170239 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9596 22:18:21.173819 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9597 22:18:21.177114 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9598 22:18:21.183594 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9599 22:18:21.186851 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9600 22:18:21.193270 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9601 22:18:21.196505 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9602 22:18:21.200311 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9603 22:18:21.206659 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9604 22:18:21.210067 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9605 22:18:21.216579 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9606 22:18:21.219733 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9607 22:18:21.223594 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9608 22:18:21.229732 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9609 22:18:21.233153 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9610 22:18:21.236692 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9611 22:18:21.239707 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9612 22:18:21.246462 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9613 22:18:21.249826 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9614 22:18:21.252993 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9615 22:18:21.260066 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9616 22:18:21.263149 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9617 22:18:21.267078 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9618 22:18:21.272779 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9619 22:18:21.276168 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9620 22:18:21.283156 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9621 22:18:21.286236 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9622 22:18:21.289373 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9623 22:18:21.296017 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9624 22:18:21.299533 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9625 22:18:21.306111 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9626 22:18:21.309211 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9627 22:18:21.312514 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9628 22:18:21.319128 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9629 22:18:21.322640 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9630 22:18:21.329114 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9631 22:18:21.332329 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9632 22:18:21.335440 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9633 22:18:21.342338 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9634 22:18:21.345995 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9635 22:18:21.352433 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9636 22:18:21.355731 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9637 22:18:21.358891 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9638 22:18:21.365275 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9639 22:18:21.369327 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9640 22:18:21.375207 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9641 22:18:21.378303 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9642 22:18:21.382055 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9643 22:18:21.388516 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9644 22:18:21.391972 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9645 22:18:21.398661 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9646 22:18:21.401720 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9647 22:18:21.405029 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9648 22:18:21.411561 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9649 22:18:21.414697 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9650 22:18:21.421524 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9651 22:18:21.425074 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9652 22:18:21.428333 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9653 22:18:21.434997 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9654 22:18:21.438148 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9655 22:18:21.444562 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9656 22:18:21.447569 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9657 22:18:21.451379 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9658 22:18:21.457645 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9659 22:18:21.460907 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9660 22:18:21.467413 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9661 22:18:21.470747 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9662 22:18:21.474409 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9663 22:18:21.480672 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9664 22:18:21.483945 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9665 22:18:21.491029 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9666 22:18:21.493652 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9667 22:18:21.499966 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9668 22:18:21.503614 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9669 22:18:21.506990 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9670 22:18:21.513699 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9671 22:18:21.516700 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9672 22:18:21.523580 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9673 22:18:21.526429 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9674 22:18:21.529897 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9675 22:18:21.536356 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9676 22:18:21.539727 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9677 22:18:21.543329 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9678 22:18:21.549958 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9679 22:18:21.552775 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9680 22:18:21.559733 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9681 22:18:21.562723 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9682 22:18:21.569422 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9683 22:18:21.572355 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9684 22:18:21.579434 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9685 22:18:21.582423 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9686 22:18:21.585871 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9687 22:18:21.592405 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9688 22:18:21.595655 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9689 22:18:21.602465 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9690 22:18:21.605691 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9691 22:18:21.608840 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9692 22:18:21.615243 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9693 22:18:21.618919 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9694 22:18:21.625305 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9695 22:18:21.628742 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9696 22:18:21.635789 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9697 22:18:21.638467 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9698 22:18:21.641824 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9699 22:18:21.648294 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9700 22:18:21.651617 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9701 22:18:21.658214 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9702 22:18:21.661716 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9703 22:18:21.668905 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9704 22:18:21.671656 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9705 22:18:21.674460 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9706 22:18:21.680983 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9707 22:18:21.684948 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9708 22:18:21.690908 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9709 22:18:21.694665 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9710 22:18:21.701206 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9711 22:18:21.704525 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9712 22:18:21.708224 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9713 22:18:21.714203 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9714 22:18:21.717395 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9715 22:18:21.723927 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9716 22:18:21.727413 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9717 22:18:21.733803 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9718 22:18:21.736934 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9719 22:18:21.740865 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9720 22:18:21.747259 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9721 22:18:21.750732 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9722 22:18:21.753874 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9723 22:18:21.756902 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9724 22:18:21.763820 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9725 22:18:21.766931 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9726 22:18:21.769971 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9727 22:18:21.776816 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9728 22:18:21.780051 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9729 22:18:21.786625 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9730 22:18:21.790032 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9731 22:18:21.793021 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9732 22:18:21.799869 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9733 22:18:21.803379 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9734 22:18:21.806046 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9735 22:18:21.813065 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9736 22:18:21.816310 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9737 22:18:21.822655 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9738 22:18:21.826155 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9739 22:18:21.829291 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9740 22:18:21.835985 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9741 22:18:21.838935 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9742 22:18:21.845560 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9743 22:18:21.849010 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9744 22:18:21.853015 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9745 22:18:21.858739 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9746 22:18:21.862365 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9747 22:18:21.865363 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9748 22:18:21.872110 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9749 22:18:21.875305 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9750 22:18:21.881965 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9751 22:18:21.885128 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9752 22:18:21.888535 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9753 22:18:21.894912 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9754 22:18:21.898806 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9755 22:18:21.901810 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9756 22:18:21.908290 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9757 22:18:21.911734 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9758 22:18:21.918685 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9759 22:18:21.921921 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9760 22:18:21.924706 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9761 22:18:21.928196 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9762 22:18:21.934482 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9763 22:18:21.937855 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9764 22:18:21.941242 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9765 22:18:21.944731 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9766 22:18:21.951063 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9767 22:18:21.954115 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9768 22:18:21.957692 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9769 22:18:21.960741 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9770 22:18:21.967660 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9771 22:18:21.970814 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9772 22:18:21.974180 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9773 22:18:21.980986 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9774 22:18:21.983938 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9775 22:18:21.990448 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9776 22:18:21.993518 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9777 22:18:21.997067 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9778 22:18:22.003976 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9779 22:18:22.006930 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9780 22:18:22.013235 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9781 22:18:22.016688 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9782 22:18:22.023385 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9783 22:18:22.026543 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9784 22:18:22.030073 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9785 22:18:22.036913 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9786 22:18:22.039677 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9787 22:18:22.046377 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9788 22:18:22.049647 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9789 22:18:22.053021 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9790 22:18:22.059925 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9791 22:18:22.062778 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9792 22:18:22.069781 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9793 22:18:22.072570 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9794 22:18:22.079159 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9795 22:18:22.082791 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9796 22:18:22.085754 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9797 22:18:22.092548 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9798 22:18:22.095971 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9799 22:18:22.102063 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9800 22:18:22.105568 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9801 22:18:22.112007 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9802 22:18:22.115862 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9803 22:18:22.118631 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9804 22:18:22.125558 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9805 22:18:22.128757 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9806 22:18:22.135225 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9807 22:18:22.138287 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9808 22:18:22.142387 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9809 22:18:22.148543 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9810 22:18:22.151614 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9811 22:18:22.158147 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9812 22:18:22.161923 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9813 22:18:22.165202 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9814 22:18:22.171730 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9815 22:18:22.174827 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9816 22:18:22.181429 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9817 22:18:22.184678 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9818 22:18:22.191497 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9819 22:18:22.194541 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9820 22:18:22.197746 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9821 22:18:22.204568 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9822 22:18:22.207994 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9823 22:18:22.214407 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9824 22:18:22.217829 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9825 22:18:22.224384 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9826 22:18:22.227628 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9827 22:18:22.234077 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9828 22:18:22.237770 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9829 22:18:22.240624 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9830 22:18:22.247192 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9831 22:18:22.250973 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9832 22:18:22.257040 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9833 22:18:22.260364 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9834 22:18:22.263769 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9835 22:18:22.270166 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9836 22:18:22.273305 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9837 22:18:22.280285 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9838 22:18:22.284162 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9839 22:18:22.286408 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9840 22:18:22.293105 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9841 22:18:22.296944 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9842 22:18:22.303213 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9843 22:18:22.306382 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9844 22:18:22.313037 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9845 22:18:22.316034 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9846 22:18:22.319698 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9847 22:18:22.325882 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9848 22:18:22.329748 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9849 22:18:22.335904 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9850 22:18:22.339083 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9851 22:18:22.346259 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9852 22:18:22.349210 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9853 22:18:22.356134 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9854 22:18:22.359438 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9855 22:18:22.362487 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9856 22:18:22.369236 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9857 22:18:22.372655 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9858 22:18:22.379553 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9859 22:18:22.382385 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9860 22:18:22.389021 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9861 22:18:22.391978 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9862 22:18:22.398590 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9863 22:18:22.401890 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9864 22:18:22.408442 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9865 22:18:22.411726 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9866 22:18:22.415374 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9867 22:18:22.421631 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9868 22:18:22.425107 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9869 22:18:22.431580 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9870 22:18:22.434801 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9871 22:18:22.441529 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9872 22:18:22.445216 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9873 22:18:22.451263 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9874 22:18:22.454821 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9875 22:18:22.461255 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9876 22:18:22.464463 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9877 22:18:22.467626 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9878 22:18:22.474124 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9879 22:18:22.477806 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9880 22:18:22.484305 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9881 22:18:22.487503 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9882 22:18:22.493908 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9883 22:18:22.497568 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9884 22:18:22.501031 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9885 22:18:22.507495 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9886 22:18:22.510648 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9887 22:18:22.517069 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9888 22:18:22.520769 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9889 22:18:22.527467 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9890 22:18:22.530493 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9891 22:18:22.536907 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9892 22:18:22.540264 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9893 22:18:22.543445 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9894 22:18:22.549970 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9895 22:18:22.553747 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9896 22:18:22.559991 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9897 22:18:22.563437 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9898 22:18:22.569984 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9899 22:18:22.573034 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9900 22:18:22.580323 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9901 22:18:22.582809 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9902 22:18:22.589599 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9903 22:18:22.593599 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9904 22:18:22.599617 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9905 22:18:22.602718 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9906 22:18:22.609586 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9907 22:18:22.612906 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9908 22:18:22.619162 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9909 22:18:22.622600 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9910 22:18:22.628990 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9911 22:18:22.632969 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9912 22:18:22.638818 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9913 22:18:22.642481 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9914 22:18:22.649009 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9915 22:18:22.651924 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9916 22:18:22.658722 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9917 22:18:22.662187 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9918 22:18:22.668376 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9919 22:18:22.671709 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9920 22:18:22.678173 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9921 22:18:22.681895 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9922 22:18:22.688722 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9923 22:18:22.691207 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9924 22:18:22.697996 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9925 22:18:22.701519 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9926 22:18:22.704501 INFO: [APUAPC] vio 0
9927 22:18:22.707910 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9928 22:18:22.714629 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9929 22:18:22.717580 INFO: [APUAPC] D0_APC_0: 0x400510
9930 22:18:22.721330 INFO: [APUAPC] D0_APC_1: 0x0
9931 22:18:22.721413 INFO: [APUAPC] D0_APC_2: 0x1540
9932 22:18:22.724216 INFO: [APUAPC] D0_APC_3: 0x0
9933 22:18:22.727837 INFO: [APUAPC] D1_APC_0: 0xffffffff
9934 22:18:22.731199 INFO: [APUAPC] D1_APC_1: 0xffffffff
9935 22:18:22.734299 INFO: [APUAPC] D1_APC_2: 0x3fffff
9936 22:18:22.737583 INFO: [APUAPC] D1_APC_3: 0x0
9937 22:18:22.740763 INFO: [APUAPC] D2_APC_0: 0xffffffff
9938 22:18:22.744381 INFO: [APUAPC] D2_APC_1: 0xffffffff
9939 22:18:22.747632 INFO: [APUAPC] D2_APC_2: 0x3fffff
9940 22:18:22.750646 INFO: [APUAPC] D2_APC_3: 0x0
9941 22:18:22.754020 INFO: [APUAPC] D3_APC_0: 0xffffffff
9942 22:18:22.757737 INFO: [APUAPC] D3_APC_1: 0xffffffff
9943 22:18:22.760907 INFO: [APUAPC] D3_APC_2: 0x3fffff
9944 22:18:22.764249 INFO: [APUAPC] D3_APC_3: 0x0
9945 22:18:22.767330 INFO: [APUAPC] D4_APC_0: 0xffffffff
9946 22:18:22.770779 INFO: [APUAPC] D4_APC_1: 0xffffffff
9947 22:18:22.773655 INFO: [APUAPC] D4_APC_2: 0x3fffff
9948 22:18:22.777341 INFO: [APUAPC] D4_APC_3: 0x0
9949 22:18:22.780272 INFO: [APUAPC] D5_APC_0: 0xffffffff
9950 22:18:22.783594 INFO: [APUAPC] D5_APC_1: 0xffffffff
9951 22:18:22.787161 INFO: [APUAPC] D5_APC_2: 0x3fffff
9952 22:18:22.790291 INFO: [APUAPC] D5_APC_3: 0x0
9953 22:18:22.794036 INFO: [APUAPC] D6_APC_0: 0xffffffff
9954 22:18:22.797099 INFO: [APUAPC] D6_APC_1: 0xffffffff
9955 22:18:22.799986 INFO: [APUAPC] D6_APC_2: 0x3fffff
9956 22:18:22.803266 INFO: [APUAPC] D6_APC_3: 0x0
9957 22:18:22.806538 INFO: [APUAPC] D7_APC_0: 0xffffffff
9958 22:18:22.809863 INFO: [APUAPC] D7_APC_1: 0xffffffff
9959 22:18:22.813167 INFO: [APUAPC] D7_APC_2: 0x3fffff
9960 22:18:22.816456 INFO: [APUAPC] D7_APC_3: 0x0
9961 22:18:22.819968 INFO: [APUAPC] D8_APC_0: 0xffffffff
9962 22:18:22.823297 INFO: [APUAPC] D8_APC_1: 0xffffffff
9963 22:18:22.826279 INFO: [APUAPC] D8_APC_2: 0x3fffff
9964 22:18:22.829640 INFO: [APUAPC] D8_APC_3: 0x0
9965 22:18:22.832773 INFO: [APUAPC] D9_APC_0: 0xffffffff
9966 22:18:22.836725 INFO: [APUAPC] D9_APC_1: 0xffffffff
9967 22:18:22.839530 INFO: [APUAPC] D9_APC_2: 0x3fffff
9968 22:18:22.842685 INFO: [APUAPC] D9_APC_3: 0x0
9969 22:18:22.846207 INFO: [APUAPC] D10_APC_0: 0xffffffff
9970 22:18:22.849636 INFO: [APUAPC] D10_APC_1: 0xffffffff
9971 22:18:22.852575 INFO: [APUAPC] D10_APC_2: 0x3fffff
9972 22:18:22.855892 INFO: [APUAPC] D10_APC_3: 0x0
9973 22:18:22.859691 INFO: [APUAPC] D11_APC_0: 0xffffffff
9974 22:18:22.862640 INFO: [APUAPC] D11_APC_1: 0xffffffff
9975 22:18:22.866153 INFO: [APUAPC] D11_APC_2: 0x3fffff
9976 22:18:22.869194 INFO: [APUAPC] D11_APC_3: 0x0
9977 22:18:22.872668 INFO: [APUAPC] D12_APC_0: 0xffffffff
9978 22:18:22.875921 INFO: [APUAPC] D12_APC_1: 0xffffffff
9979 22:18:22.879975 INFO: [APUAPC] D12_APC_2: 0x3fffff
9980 22:18:22.882430 INFO: [APUAPC] D12_APC_3: 0x0
9981 22:18:22.885597 INFO: [APUAPC] D13_APC_0: 0xffffffff
9982 22:18:22.889146 INFO: [APUAPC] D13_APC_1: 0xffffffff
9983 22:18:22.892416 INFO: [APUAPC] D13_APC_2: 0x3fffff
9984 22:18:22.895703 INFO: [APUAPC] D13_APC_3: 0x0
9985 22:18:22.898865 INFO: [APUAPC] D14_APC_0: 0xffffffff
9986 22:18:22.902137 INFO: [APUAPC] D14_APC_1: 0xffffffff
9987 22:18:22.905676 INFO: [APUAPC] D14_APC_2: 0x3fffff
9988 22:18:22.908940 INFO: [APUAPC] D14_APC_3: 0x0
9989 22:18:22.912190 INFO: [APUAPC] D15_APC_0: 0xffffffff
9990 22:18:22.915477 INFO: [APUAPC] D15_APC_1: 0xffffffff
9991 22:18:22.918361 INFO: [APUAPC] D15_APC_2: 0x3fffff
9992 22:18:22.921776 INFO: [APUAPC] D15_APC_3: 0x0
9993 22:18:22.925483 INFO: [APUAPC] APC_CON: 0x4
9994 22:18:22.928392 INFO: [NOCDAPC] D0_APC_0: 0x0
9995 22:18:22.931881 INFO: [NOCDAPC] D0_APC_1: 0x0
9996 22:18:22.935000 INFO: [NOCDAPC] D1_APC_0: 0x0
9997 22:18:22.938216 INFO: [NOCDAPC] D1_APC_1: 0xfff
9998 22:18:22.941697 INFO: [NOCDAPC] D2_APC_0: 0x0
9999 22:18:22.944852 INFO: [NOCDAPC] D2_APC_1: 0xfff
10000 22:18:22.944939 INFO: [NOCDAPC] D3_APC_0: 0x0
10001 22:18:22.948054 INFO: [NOCDAPC] D3_APC_1: 0xfff
10002 22:18:22.951558 INFO: [NOCDAPC] D4_APC_0: 0x0
10003 22:18:22.954817 INFO: [NOCDAPC] D4_APC_1: 0xfff
10004 22:18:22.958215 INFO: [NOCDAPC] D5_APC_0: 0x0
10005 22:18:22.961330 INFO: [NOCDAPC] D5_APC_1: 0xfff
10006 22:18:22.964680 INFO: [NOCDAPC] D6_APC_0: 0x0
10007 22:18:22.968039 INFO: [NOCDAPC] D6_APC_1: 0xfff
10008 22:18:22.971336 INFO: [NOCDAPC] D7_APC_0: 0x0
10009 22:18:22.974538 INFO: [NOCDAPC] D7_APC_1: 0xfff
10010 22:18:22.977953 INFO: [NOCDAPC] D8_APC_0: 0x0
10011 22:18:22.981258 INFO: [NOCDAPC] D8_APC_1: 0xfff
10012 22:18:22.981334 INFO: [NOCDAPC] D9_APC_0: 0x0
10013 22:18:22.984699 INFO: [NOCDAPC] D9_APC_1: 0xfff
10014 22:18:22.987602 INFO: [NOCDAPC] D10_APC_0: 0x0
10015 22:18:22.991087 INFO: [NOCDAPC] D10_APC_1: 0xfff
10016 22:18:22.994222 INFO: [NOCDAPC] D11_APC_0: 0x0
10017 22:18:22.997518 INFO: [NOCDAPC] D11_APC_1: 0xfff
10018 22:18:23.000917 INFO: [NOCDAPC] D12_APC_0: 0x0
10019 22:18:23.004020 INFO: [NOCDAPC] D12_APC_1: 0xfff
10020 22:18:23.007105 INFO: [NOCDAPC] D13_APC_0: 0x0
10021 22:18:23.011176 INFO: [NOCDAPC] D13_APC_1: 0xfff
10022 22:18:23.014263 INFO: [NOCDAPC] D14_APC_0: 0x0
10023 22:18:23.016990 INFO: [NOCDAPC] D14_APC_1: 0xfff
10024 22:18:23.020358 INFO: [NOCDAPC] D15_APC_0: 0x0
10025 22:18:23.023926 INFO: [NOCDAPC] D15_APC_1: 0xfff
10026 22:18:23.027669 INFO: [NOCDAPC] APC_CON: 0x4
10027 22:18:23.030406 INFO: [APUAPC] set_apusys_apc done
10028 22:18:23.034241 INFO: [DEVAPC] devapc_init done
10029 22:18:23.037144 INFO: GICv3 without legacy support detected.
10030 22:18:23.040534 INFO: ARM GICv3 driver initialized in EL3
10031 22:18:23.043312 INFO: Maximum SPI INTID supported: 639
10032 22:18:23.046944 INFO: BL31: Initializing runtime services
10033 22:18:23.053342 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10034 22:18:23.056857 INFO: SPM: enable CPC mode
10035 22:18:23.063428 INFO: mcdi ready for mcusys-off-idle and system suspend
10036 22:18:23.066512 INFO: BL31: Preparing for EL3 exit to normal world
10037 22:18:23.069854 INFO: Entry point address = 0x80000000
10038 22:18:23.072874 INFO: SPSR = 0x8
10039 22:18:23.077594
10040 22:18:23.077677
10041 22:18:23.077742
10042 22:18:23.081089 Starting depthcharge on Spherion...
10043 22:18:23.081172
10044 22:18:23.081236 Wipe memory regions:
10045 22:18:23.081297
10046 22:18:23.081948 end: 2.2.3 depthcharge-start (duration 00:00:29) [common]
10047 22:18:23.082053 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10048 22:18:23.082136 Setting prompt string to ['asurada:']
10049 22:18:23.082216 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10050 22:18:23.084080 [0x00000040000000, 0x00000054600000)
10051 22:18:23.206710
10052 22:18:23.206850 [0x00000054660000, 0x00000080000000)
10053 22:18:23.467088
10054 22:18:23.467245 [0x000000821a7280, 0x000000ffe64000)
10055 22:18:24.212186
10056 22:18:24.212348 [0x00000100000000, 0x00000240000000)
10057 22:18:26.102435
10058 22:18:26.105747 Initializing XHCI USB controller at 0x11200000.
10059 22:18:27.144022
10060 22:18:27.146577 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10061 22:18:27.146671
10062 22:18:27.146735
10063 22:18:27.146794
10064 22:18:27.147079 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10066 22:18:27.247454 asurada: tftpboot 192.168.201.1 10597265/tftp-deploy-dqirrpjl/kernel/image.itb 10597265/tftp-deploy-dqirrpjl/kernel/cmdline
10067 22:18:27.247674 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10068 22:18:27.247805 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10069 22:18:27.252475 tftpboot 192.168.201.1 10597265/tftp-deploy-dqirrpjl/kernel/image.itp-deploy-dqirrpjl/kernel/cmdline
10070 22:18:27.252559
10071 22:18:27.252623 Waiting for link
10072 22:18:27.413225
10073 22:18:27.413413 R8152: Initializing
10074 22:18:27.413509
10075 22:18:27.416286 Version 6 (ocp_data = 5c30)
10076 22:18:27.416470
10077 22:18:27.419671 R8152: Done initializing
10078 22:18:27.419870
10079 22:18:27.419978 Adding net device
10080 22:18:29.463598
10081 22:18:29.463756 done.
10082 22:18:29.463825
10083 22:18:29.463885 MAC: 00:24:32:30:7c:7b
10084 22:18:29.463942
10085 22:18:29.466845 Sending DHCP discover... done.
10086 22:18:29.466928
10087 22:18:29.469864 Waiting for reply... done.
10088 22:18:29.469961
10089 22:18:29.473168 Sending DHCP request... done.
10090 22:18:29.473302
10091 22:18:29.473418 Waiting for reply... done.
10092 22:18:29.473495
10093 22:18:29.476313 My ip is 192.168.201.14
10094 22:18:29.476394
10095 22:18:29.479860 The DHCP server ip is 192.168.201.1
10096 22:18:29.479982
10097 22:18:29.483306 TFTP server IP predefined by user: 192.168.201.1
10098 22:18:29.483401
10099 22:18:29.490134 Bootfile predefined by user: 10597265/tftp-deploy-dqirrpjl/kernel/image.itb
10100 22:18:29.490215
10101 22:18:29.493144 Sending tftp read request... done.
10102 22:18:29.493225
10103 22:18:29.496290 Waiting for the transfer...
10104 22:18:29.496371
10105 22:18:30.061950 00000000 ################################################################
10106 22:18:30.062104
10107 22:18:30.633339 00080000 ################################################################
10108 22:18:30.633520
10109 22:18:31.203436 00100000 ################################################################
10110 22:18:31.203588
10111 22:18:31.761795 00180000 ################################################################
10112 22:18:31.761945
10113 22:18:32.352526 00200000 ################################################################
10114 22:18:32.352676
10115 22:18:32.910075 00280000 ################################################################
10116 22:18:32.910239
10117 22:18:33.459390 00300000 ################################################################
10118 22:18:33.459629
10119 22:18:33.993044 00380000 ################################################################
10120 22:18:33.993210
10121 22:18:34.539858 00400000 ################################################################
10122 22:18:34.540010
10123 22:18:35.072528 00480000 ################################################################
10124 22:18:35.072662
10125 22:18:35.631427 00500000 ################################################################
10126 22:18:35.631607
10127 22:18:36.193278 00580000 ################################################################
10128 22:18:36.193425
10129 22:18:36.737765 00600000 ################################################################
10130 22:18:36.737917
10131 22:18:37.301600 00680000 ################################################################
10132 22:18:37.301763
10133 22:18:37.867146 00700000 ################################################################
10134 22:18:37.867302
10135 22:18:38.443520 00780000 ################################################################
10136 22:18:38.443703
10137 22:18:39.005496 00800000 ################################################################
10138 22:18:39.005679
10139 22:18:39.568497 00880000 ################################################################
10140 22:18:39.568661
10141 22:18:40.120050 00900000 ################################################################
10142 22:18:40.120202
10143 22:18:40.694825 00980000 ################################################################
10144 22:18:40.694974
10145 22:18:41.255503 00a00000 ################################################################
10146 22:18:41.255648
10147 22:18:41.791365 00a80000 ################################################################
10148 22:18:41.791516
10149 22:18:42.322977 00b00000 ################################################################
10150 22:18:42.323124
10151 22:18:42.868370 00b80000 ################################################################
10152 22:18:42.868512
10153 22:18:43.417723 00c00000 ################################################################
10154 22:18:43.417862
10155 22:18:43.956146 00c80000 ################################################################
10156 22:18:43.956291
10157 22:18:44.490022 00d00000 ################################################################
10158 22:18:44.490177
10159 22:18:45.016216 00d80000 ################################################################
10160 22:18:45.016372
10161 22:18:45.551413 00e00000 ################################################################
10162 22:18:45.551567
10163 22:18:46.088567 00e80000 ################################################################
10164 22:18:46.088716
10165 22:18:46.629839 00f00000 ################################################################
10166 22:18:46.629976
10167 22:18:47.188023 00f80000 ################################################################
10168 22:18:47.188211
10169 22:18:47.747695 01000000 ################################################################
10170 22:18:47.747850
10171 22:18:48.287498 01080000 ################################################################
10172 22:18:48.287639
10173 22:18:48.801837 01100000 ################################################################
10174 22:18:48.801984
10175 22:18:49.336892 01180000 ################################################################
10176 22:18:49.337033
10177 22:18:49.847519 01200000 ################################################################
10178 22:18:49.847671
10179 22:18:50.358895 01280000 ################################################################
10180 22:18:50.359031
10181 22:18:50.870924 01300000 ################################################################
10182 22:18:50.871076
10183 22:18:51.385646 01380000 ################################################################
10184 22:18:51.385798
10185 22:18:51.891771 01400000 ################################################################
10186 22:18:51.891918
10187 22:18:52.403367 01480000 ################################################################
10188 22:18:52.403516
10189 22:18:52.917928 01500000 ################################################################
10190 22:18:52.918079
10191 22:18:53.448222 01580000 ################################################################
10192 22:18:53.448366
10193 22:18:53.984017 01600000 ################################################################
10194 22:18:53.984193
10195 22:18:54.503576 01680000 ################################################################
10196 22:18:54.503718
10197 22:18:55.027516 01700000 ################################################################
10198 22:18:55.027676
10199 22:18:55.619771 01780000 ################################################################
10200 22:18:55.619917
10201 22:18:56.268836 01800000 ################################################################
10202 22:18:56.268985
10203 22:18:56.912477 01880000 ################################################################
10204 22:18:56.912646
10205 22:18:57.525427 01900000 ################################################################
10206 22:18:57.525928
10207 22:18:58.071059 01980000 ################################################################
10208 22:18:58.071195
10209 22:18:58.622043 01a00000 ################################################################
10210 22:18:58.622186
10211 22:18:59.220963 01a80000 ################################################################
10212 22:18:59.221104
10213 22:18:59.684449 01b00000 ################################################### done.
10214 22:18:59.685006
10215 22:18:59.687686 The bootfile was 28725518 bytes long.
10216 22:18:59.688144
10217 22:18:59.690810 Sending tftp read request... done.
10218 22:18:59.691251
10219 22:18:59.694168 Waiting for the transfer...
10220 22:18:59.694642
10221 22:18:59.694974 00000000 # done.
10222 22:18:59.695306
10223 22:18:59.700903 Command line loaded dynamically from TFTP file: 10597265/tftp-deploy-dqirrpjl/kernel/cmdline
10224 22:18:59.701328
10225 22:18:59.720698 The command line is: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/10597265/extract-nfsrootfs-jdvhjo22,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10226 22:18:59.721255
10227 22:18:59.724156 Loading FIT.
10228 22:18:59.724683
10229 22:18:59.727599 Image ramdisk-1 has 18594255 bytes.
10230 22:18:59.728158
10231 22:18:59.728497 Image fdt-1 has 46924 bytes.
10232 22:18:59.730923
10233 22:18:59.731347 Image kernel-1 has 10082307 bytes.
10234 22:18:59.731683
10235 22:18:59.740927 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10236 22:18:59.741452
10237 22:18:59.757022 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10238 22:18:59.760369
10239 22:18:59.763457 Choosing best match conf-1 for compat google,spherion-rev2.
10240 22:18:59.768024
10241 22:18:59.772569 Connected to device vid:did:rid of 1ae0:0028:00
10242 22:18:59.779462
10243 22:18:59.783291 tpm_get_response: command 0x17b, return code 0x0
10244 22:18:59.783823
10245 22:18:59.786327 ec_init: CrosEC protocol v3 supported (256, 248)
10246 22:18:59.790175
10247 22:18:59.793415 tpm_cleanup: add release locality here.
10248 22:18:59.793838
10249 22:18:59.794171 Shutting down all USB controllers.
10250 22:18:59.796868
10251 22:18:59.797308 Removing current net device
10252 22:18:59.797647
10253 22:18:59.803755 Exiting depthcharge with code 4 at timestamp: 65938613
10254 22:18:59.804376
10255 22:18:59.806666 LZMA decompressing kernel-1 to 0x821a6718
10256 22:18:59.807117
10257 22:18:59.810607 LZMA decompressing kernel-1 to 0x40000000
10258 22:19:01.077343
10259 22:19:01.077909 jumping to kernel
10260 22:19:01.079347 end: 2.2.4 bootloader-commands (duration 00:00:38) [common]
10261 22:19:01.080093 start: 2.2.5 auto-login-action (timeout 00:03:47) [common]
10262 22:19:01.080635 Setting prompt string to ['Linux version [0-9]']
10263 22:19:01.081098 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10264 22:19:01.081659 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10265 22:19:01.159769
10266 22:19:01.162860 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10267 22:19:01.166731 start: 2.2.5.1 login-action (timeout 00:03:47) [common]
10268 22:19:01.167312 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10269 22:19:01.167931 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10270 22:19:01.168624 Using line separator: #'\n'#
10271 22:19:01.169040 No login prompt set.
10272 22:19:01.169652 Parsing kernel messages
10273 22:19:01.170146 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10274 22:19:01.170739 [login-action] Waiting for messages, (timeout 00:03:47)
10275 22:19:01.185859 [ 0.000000] Linux version 6.1.31 (KernelCI@build-j1612341-arm64-gcc-10-defconfig-arm64-chromebook-n674v) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Mon Jun 5 22:04:07 UTC 2023
10276 22:19:01.188957 [ 0.000000] random: crng init done
10277 22:19:01.195996 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10278 22:19:01.198906 [ 0.000000] efi: UEFI not found.
10279 22:19:01.206080 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10280 22:19:01.212466 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10281 22:19:01.222147 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10282 22:19:01.232122 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10283 22:19:01.238759 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10284 22:19:01.245135 [ 0.000000] printk: bootconsole [mtk8250] enabled
10285 22:19:01.251562 [ 0.000000] NUMA: No NUMA configuration found
10286 22:19:01.258190 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10287 22:19:01.261843 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcda00-0x23efcffff]
10288 22:19:01.264834 [ 0.000000] Zone ranges:
10289 22:19:01.271215 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10290 22:19:01.274840 [ 0.000000] DMA32 empty
10291 22:19:01.281176 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10292 22:19:01.284904 [ 0.000000] Movable zone start for each node
10293 22:19:01.288405 [ 0.000000] Early memory node ranges
10294 22:19:01.294976 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10295 22:19:01.301028 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10296 22:19:01.307516 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10297 22:19:01.314074 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10298 22:19:01.320986 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10299 22:19:01.327809 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10300 22:19:01.384001 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10301 22:19:01.390515 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10302 22:19:01.396724 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10303 22:19:01.400209 [ 0.000000] psci: probing for conduit method from DT.
10304 22:19:01.406949 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10305 22:19:01.410271 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10306 22:19:01.416738 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10307 22:19:01.420419 [ 0.000000] psci: SMC Calling Convention v1.2
10308 22:19:01.427272 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10309 22:19:01.430885 [ 0.000000] Detected VIPT I-cache on CPU0
10310 22:19:01.437421 [ 0.000000] CPU features: detected: GIC system register CPU interface
10311 22:19:01.443694 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10312 22:19:01.450333 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10313 22:19:01.456578 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10314 22:19:01.466903 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10315 22:19:01.473510 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10316 22:19:01.476154 [ 0.000000] alternatives: applying boot alternatives
10317 22:19:01.482684 [ 0.000000] Fallback order for Node 0: 0
10318 22:19:01.489394 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10319 22:19:01.492399 [ 0.000000] Policy zone: Normal
10320 22:19:01.513669 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/10597265/extract-nfsrootfs-jdvhjo22,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10321 22:19:01.522516 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10322 22:19:01.534587 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10323 22:19:01.544452 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10324 22:19:01.550986 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10325 22:19:01.554587 <6>[ 0.000000] software IO TLB: area num 8.
10326 22:19:01.611358 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10327 22:19:01.759952 <6>[ 0.000000] Memory: 7954788K/8385536K available (17984K kernel code, 4098K rwdata, 14068K rodata, 8384K init, 615K bss, 397980K reserved, 32768K cma-reserved)
10328 22:19:01.766739 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10329 22:19:01.772660 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10330 22:19:01.776207 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10331 22:19:01.783188 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10332 22:19:01.789501 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10333 22:19:01.796162 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10334 22:19:01.802505 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10335 22:19:01.808836 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10336 22:19:01.815778 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10337 22:19:01.822600 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10338 22:19:01.825811 <6>[ 0.000000] GICv3: 608 SPIs implemented
10339 22:19:01.828952 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10340 22:19:01.835722 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10341 22:19:01.839079 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10342 22:19:01.845407 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10343 22:19:01.858624 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10344 22:19:01.871768 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10345 22:19:01.878239 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10346 22:19:01.886657 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10347 22:19:01.899728 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10348 22:19:01.906020 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10349 22:19:01.913304 <6>[ 0.009182] Console: colour dummy device 80x25
10350 22:19:01.923120 <6>[ 0.013908] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10351 22:19:01.929355 <6>[ 0.024350] pid_max: default: 32768 minimum: 301
10352 22:19:01.932602 <6>[ 0.029224] LSM: Security Framework initializing
10353 22:19:01.939703 <6>[ 0.034192] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10354 22:19:01.949335 <6>[ 0.042006] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10355 22:19:01.958922 <6>[ 0.051283] cblist_init_generic: Setting adjustable number of callback queues.
10356 22:19:01.962203 <6>[ 0.058736] cblist_init_generic: Setting shift to 3 and lim to 1.
10357 22:19:01.969526 <6>[ 0.065077] cblist_init_generic: Setting shift to 3 and lim to 1.
10358 22:19:01.975380 <6>[ 0.071526] rcu: Hierarchical SRCU implementation.
10359 22:19:01.982119 <6>[ 0.076539] rcu: Max phase no-delay instances is 1000.
10360 22:19:01.988514 <6>[ 0.083555] EFI services will not be available.
10361 22:19:01.992216 <6>[ 0.088525] smp: Bringing up secondary CPUs ...
10362 22:19:01.999390 <6>[ 0.093578] Detected VIPT I-cache on CPU1
10363 22:19:02.006600 <6>[ 0.093649] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10364 22:19:02.012478 <6>[ 0.093680] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10365 22:19:02.016095 <6>[ 0.094011] Detected VIPT I-cache on CPU2
10366 22:19:02.026159 <6>[ 0.094059] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10367 22:19:02.032691 <6>[ 0.094074] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10368 22:19:02.036416 <6>[ 0.094330] Detected VIPT I-cache on CPU3
10369 22:19:02.043017 <6>[ 0.094376] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10370 22:19:02.048814 <6>[ 0.094390] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10371 22:19:02.055577 <6>[ 0.094697] CPU features: detected: Spectre-v4
10372 22:19:02.058879 <6>[ 0.094704] CPU features: detected: Spectre-BHB
10373 22:19:02.062139 <6>[ 0.094710] Detected PIPT I-cache on CPU4
10374 22:19:02.068920 <6>[ 0.094766] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10375 22:19:02.078361 <6>[ 0.094782] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10376 22:19:02.082177 <6>[ 0.095080] Detected PIPT I-cache on CPU5
10377 22:19:02.088672 <6>[ 0.095143] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10378 22:19:02.095218 <6>[ 0.095159] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10379 22:19:02.098298 <6>[ 0.095445] Detected PIPT I-cache on CPU6
10380 22:19:02.108317 <6>[ 0.095509] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10381 22:19:02.114874 <6>[ 0.095525] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10382 22:19:02.118105 <6>[ 0.095823] Detected PIPT I-cache on CPU7
10383 22:19:02.124656 <6>[ 0.095888] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10384 22:19:02.131569 <6>[ 0.095904] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10385 22:19:02.134549 <6>[ 0.095952] smp: Brought up 1 node, 8 CPUs
10386 22:19:02.141407 <6>[ 0.237272] SMP: Total of 8 processors activated.
10387 22:19:02.147657 <6>[ 0.242193] CPU features: detected: 32-bit EL0 Support
10388 22:19:02.154306 <6>[ 0.247556] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10389 22:19:02.160761 <6>[ 0.256356] CPU features: detected: Common not Private translations
10390 22:19:02.167796 <6>[ 0.262872] CPU features: detected: CRC32 instructions
10391 22:19:02.173985 <6>[ 0.268223] CPU features: detected: RCpc load-acquire (LDAPR)
10392 22:19:02.177395 <6>[ 0.274183] CPU features: detected: LSE atomic instructions
10393 22:19:02.183799 <6>[ 0.279969] CPU features: detected: Privileged Access Never
10394 22:19:02.190326 <6>[ 0.285748] CPU features: detected: RAS Extension Support
10395 22:19:02.197131 <6>[ 0.291357] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10396 22:19:02.200147 <6>[ 0.298576] CPU: All CPU(s) started at EL2
10397 22:19:02.207030 <6>[ 0.302892] alternatives: applying system-wide alternatives
10398 22:19:02.217366 <6>[ 0.313602] devtmpfs: initialized
10399 22:19:02.232414 <6>[ 0.322457] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10400 22:19:02.239090 <6>[ 0.332419] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10401 22:19:02.246059 <6>[ 0.340624] pinctrl core: initialized pinctrl subsystem
10402 22:19:02.249553 <6>[ 0.347262] DMI not present or invalid.
10403 22:19:02.255806 <6>[ 0.351668] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10404 22:19:02.265864 <6>[ 0.358555] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10405 22:19:02.272425 <6>[ 0.366138] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10406 22:19:02.282518 <6>[ 0.374367] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10407 22:19:02.285819 <6>[ 0.382605] audit: initializing netlink subsys (disabled)
10408 22:19:02.295986 <5>[ 0.388296] audit: type=2000 audit(0.276:1): state=initialized audit_enabled=0 res=1
10409 22:19:02.302100 <6>[ 0.388995] thermal_sys: Registered thermal governor 'step_wise'
10410 22:19:02.308707 <6>[ 0.396263] thermal_sys: Registered thermal governor 'power_allocator'
10411 22:19:02.312142 <6>[ 0.402514] cpuidle: using governor menu
10412 22:19:02.318423 <6>[ 0.413477] NET: Registered PF_QIPCRTR protocol family
10413 22:19:02.325659 <6>[ 0.418973] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10414 22:19:02.332188 <6>[ 0.426073] ASID allocator initialised with 32768 entries
10415 22:19:02.335338 <6>[ 0.432630] Serial: AMBA PL011 UART driver
10416 22:19:02.345106 <4>[ 0.441225] Trying to register duplicate clock ID: 134
10417 22:19:02.398803 <6>[ 0.498428] KASLR enabled
10418 22:19:02.413693 <6>[ 0.506156] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10419 22:19:02.419511 <6>[ 0.513170] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10420 22:19:02.426398 <6>[ 0.519659] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10421 22:19:02.432885 <6>[ 0.526663] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10422 22:19:02.439533 <6>[ 0.533149] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10423 22:19:02.446458 <6>[ 0.540154] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10424 22:19:02.453017 <6>[ 0.546641] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10425 22:19:02.459192 <6>[ 0.553645] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10426 22:19:02.462484 <6>[ 0.561171] ACPI: Interpreter disabled.
10427 22:19:02.471446 <6>[ 0.567572] iommu: Default domain type: Translated
10428 22:19:02.478123 <6>[ 0.572686] iommu: DMA domain TLB invalidation policy: strict mode
10429 22:19:02.480973 <5>[ 0.579340] SCSI subsystem initialized
10430 22:19:02.488258 <6>[ 0.583506] usbcore: registered new interface driver usbfs
10431 22:19:02.494442 <6>[ 0.589238] usbcore: registered new interface driver hub
10432 22:19:02.497832 <6>[ 0.594792] usbcore: registered new device driver usb
10433 22:19:02.504751 <6>[ 0.600882] pps_core: LinuxPPS API ver. 1 registered
10434 22:19:02.514360 <6>[ 0.606075] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10435 22:19:02.518226 <6>[ 0.615425] PTP clock support registered
10436 22:19:02.521293 <6>[ 0.619667] EDAC MC: Ver: 3.0.0
10437 22:19:02.528860 <6>[ 0.624804] FPGA manager framework
10438 22:19:02.535118 <6>[ 0.628483] Advanced Linux Sound Architecture Driver Initialized.
10439 22:19:02.538474 <6>[ 0.635247] vgaarb: loaded
10440 22:19:02.545341 <6>[ 0.638420] clocksource: Switched to clocksource arch_sys_counter
10441 22:19:02.548377 <5>[ 0.644861] VFS: Disk quotas dquot_6.6.0
10442 22:19:02.554935 <6>[ 0.649044] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10443 22:19:02.558162 <6>[ 0.656233] pnp: PnP ACPI: disabled
10444 22:19:02.566510 <6>[ 0.663020] NET: Registered PF_INET protocol family
10445 22:19:02.576878 <6>[ 0.668620] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10446 22:19:02.587757 <6>[ 0.680933] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10447 22:19:02.597819 <6>[ 0.689751] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10448 22:19:02.604657 <6>[ 0.697723] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10449 22:19:02.614294 <6>[ 0.706426] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10450 22:19:02.621031 <6>[ 0.716176] TCP: Hash tables configured (established 65536 bind 65536)
10451 22:19:02.627980 <6>[ 0.723040] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10452 22:19:02.637562 <6>[ 0.730240] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10453 22:19:02.644196 <6>[ 0.737917] NET: Registered PF_UNIX/PF_LOCAL protocol family
10454 22:19:02.647562 <6>[ 0.743993] RPC: Registered named UNIX socket transport module.
10455 22:19:02.654050 <6>[ 0.750139] RPC: Registered udp transport module.
10456 22:19:02.657670 <6>[ 0.755070] RPC: Registered tcp transport module.
10457 22:19:02.666906 <6>[ 0.760002] RPC: Registered tcp NFSv4.1 backchannel transport module.
10458 22:19:02.670358 <6>[ 0.766666] PCI: CLS 0 bytes, default 64
10459 22:19:02.673606 <6>[ 0.770986] Unpacking initramfs...
10460 22:19:02.683421 <6>[ 0.774782] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10461 22:19:02.690007 <6>[ 0.783425] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10462 22:19:02.696602 <6>[ 0.792222] kvm [1]: IPA Size Limit: 40 bits
10463 22:19:02.699869 <6>[ 0.796746] kvm [1]: GICv3: no GICV resource entry
10464 22:19:02.706639 <6>[ 0.801768] kvm [1]: disabling GICv2 emulation
10465 22:19:02.709866 <6>[ 0.806458] kvm [1]: GIC system register CPU interface enabled
10466 22:19:02.716561 <6>[ 0.812623] kvm [1]: vgic interrupt IRQ18
10467 22:19:02.719493 <6>[ 0.816982] kvm [1]: VHE mode initialized successfully
10468 22:19:02.727575 <5>[ 0.823331] Initialise system trusted keyrings
10469 22:19:02.733394 <6>[ 0.828137] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10470 22:19:02.742033 <6>[ 0.838367] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10471 22:19:02.749144 <5>[ 0.844766] NFS: Registering the id_resolver key type
10472 22:19:02.751712 <5>[ 0.850071] Key type id_resolver registered
10473 22:19:02.758928 <5>[ 0.854484] Key type id_legacy registered
10474 22:19:02.765676 <6>[ 0.858763] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10475 22:19:02.771909 <6>[ 0.865685] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10476 22:19:02.778341 <6>[ 0.873390] 9p: Installing v9fs 9p2000 file system support
10477 22:19:02.814926 <5>[ 0.910592] Key type asymmetric registered
10478 22:19:02.817503 <5>[ 0.914924] Asymmetric key parser 'x509' registered
10479 22:19:02.827242 <6>[ 0.920065] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10480 22:19:02.830693 <6>[ 0.927679] io scheduler mq-deadline registered
10481 22:19:02.834551 <6>[ 0.932441] io scheduler kyber registered
10482 22:19:02.852881 <6>[ 0.949478] EINJ: ACPI disabled.
10483 22:19:02.885174 <4>[ 0.975047] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10484 22:19:02.895536 <4>[ 0.985687] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10485 22:19:02.909942 <6>[ 1.006443] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10486 22:19:02.918704 <6>[ 1.014463] printk: console [ttyS0] disabled
10487 22:19:02.946235 <6>[ 1.039110] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10488 22:19:02.952385 <6>[ 1.048596] printk: console [ttyS0] enabled
10489 22:19:02.955860 <6>[ 1.048596] printk: console [ttyS0] enabled
10490 22:19:02.962904 <6>[ 1.057495] printk: bootconsole [mtk8250] disabled
10491 22:19:02.965796 <6>[ 1.057495] printk: bootconsole [mtk8250] disabled
10492 22:19:02.972286 <6>[ 1.068776] SuperH (H)SCI(F) driver initialized
10493 22:19:02.976003 <6>[ 1.074061] msm_serial: driver initialized
10494 22:19:02.989758 <6>[ 1.082983] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10495 22:19:03.000304 <6>[ 1.091531] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10496 22:19:03.006586 <6>[ 1.100077] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10497 22:19:03.016371 <6>[ 1.108706] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10498 22:19:03.027271 <6>[ 1.117413] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10499 22:19:03.032802 <6>[ 1.126127] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10500 22:19:03.043074 <6>[ 1.134668] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10501 22:19:03.049596 <6>[ 1.143474] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10502 22:19:03.059424 <6>[ 1.152018] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10503 22:19:03.071274 <6>[ 1.167679] loop: module loaded
10504 22:19:03.077879 <6>[ 1.173676] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10505 22:19:03.100727 <4>[ 1.197034] mtk-pmic-keys: Failed to locate of_node [id: -1]
10506 22:19:03.107387 <6>[ 1.203812] megasas: 07.719.03.00-rc1
10507 22:19:03.117481 <6>[ 1.213412] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10508 22:19:03.125725 <6>[ 1.221800] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10509 22:19:03.142641 <6>[ 1.238501] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10510 22:19:03.198829 <6>[ 1.288671] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9
10511 22:19:03.458003 <6>[ 1.553802] Freeing initrd memory: 18152K
10512 22:19:03.469197 <6>[ 1.565320] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10513 22:19:03.479885 <6>[ 1.576176] tun: Universal TUN/TAP device driver, 1.6
10514 22:19:03.482950 <6>[ 1.582221] thunder_xcv, ver 1.0
10515 22:19:03.486139 <6>[ 1.585726] thunder_bgx, ver 1.0
10516 22:19:03.490119 <6>[ 1.589222] nicpf, ver 1.0
10517 22:19:03.500158 <6>[ 1.593229] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10518 22:19:03.503725 <6>[ 1.600705] hns3: Copyright (c) 2017 Huawei Corporation.
10519 22:19:03.510445 <6>[ 1.606291] hclge is initializing
10520 22:19:03.513210 <6>[ 1.609871] e1000: Intel(R) PRO/1000 Network Driver
10521 22:19:03.520565 <6>[ 1.615000] e1000: Copyright (c) 1999-2006 Intel Corporation.
10522 22:19:03.523361 <6>[ 1.621012] e1000e: Intel(R) PRO/1000 Network Driver
10523 22:19:03.529848 <6>[ 1.626228] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10524 22:19:03.536740 <6>[ 1.632412] igb: Intel(R) Gigabit Ethernet Network Driver
10525 22:19:03.543598 <6>[ 1.638062] igb: Copyright (c) 2007-2014 Intel Corporation.
10526 22:19:03.550679 <6>[ 1.643901] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10527 22:19:03.556737 <6>[ 1.650418] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10528 22:19:03.560171 <6>[ 1.656875] sky2: driver version 1.30
10529 22:19:03.566443 <6>[ 1.661851] VFIO - User Level meta-driver version: 0.3
10530 22:19:03.573702 <6>[ 1.670047] usbcore: registered new interface driver usb-storage
10531 22:19:03.580226 <6>[ 1.676498] usbcore: registered new device driver onboard-usb-hub
10532 22:19:03.589128 <6>[ 1.685576] mt6397-rtc mt6359-rtc: registered as rtc0
10533 22:19:03.599136 <6>[ 1.691038] mt6397-rtc mt6359-rtc: setting system clock to 2023-06-05T22:19:08 UTC (1686003548)
10534 22:19:03.602151 <6>[ 1.700595] i2c_dev: i2c /dev entries driver
10535 22:19:03.619024 <6>[ 1.712175] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10536 22:19:03.626500 <6>[ 1.722349] sdhci: Secure Digital Host Controller Interface driver
10537 22:19:03.632978 <6>[ 1.728786] sdhci: Copyright(c) Pierre Ossman
10538 22:19:03.639494 <6>[ 1.734173] Synopsys Designware Multimedia Card Interface Driver
10539 22:19:03.642910 <6>[ 1.740777] mmc0: CQHCI version 5.10
10540 22:19:03.649227 <6>[ 1.741324] sdhci-pltfm: SDHCI platform and OF driver helper
10541 22:19:03.656580 <6>[ 1.752966] ledtrig-cpu: registered to indicate activity on CPUs
10542 22:19:03.667128 <6>[ 1.760217] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10543 22:19:03.674457 <6>[ 1.767648] usbcore: registered new interface driver usbhid
10544 22:19:03.677043 <6>[ 1.773479] usbhid: USB HID core driver
10545 22:19:03.683426 <6>[ 1.777728] spi_master spi0: will run message pump with realtime priority
10546 22:19:03.732112 <6>[ 1.821685] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10547 22:19:03.750665 <6>[ 1.836844] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10548 22:19:03.754259 <6>[ 1.850404] mmc0: Command Queue Engine enabled
10549 22:19:03.761218 <6>[ 1.855198] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10550 22:19:03.767715 <6>[ 1.862324] cros-ec-spi spi0.0: Chrome EC device registered
10551 22:19:03.770772 <6>[ 1.862571] mmcblk0: mmc0:0001 DA4128 116 GiB
10552 22:19:03.781441 <6>[ 1.877771] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10553 22:19:03.789006 <6>[ 1.885274] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10554 22:19:03.796116 <6>[ 1.891137] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10555 22:19:03.802171 <6>[ 1.897173] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10556 22:19:03.818825 <6>[ 1.911997] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10557 22:19:03.827688 <6>[ 1.923473] NET: Registered PF_PACKET protocol family
10558 22:19:03.830136 <6>[ 1.928915] 9pnet: Installing 9P2000 support
10559 22:19:03.837170 <5>[ 1.933504] Key type dns_resolver registered
10560 22:19:03.840697 <6>[ 1.938688] registered taskstats version 1
10561 22:19:03.847023 <5>[ 1.943110] Loading compiled-in X.509 certificates
10562 22:19:03.881833 <4>[ 1.970944] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10563 22:19:03.890794 <4>[ 1.981618] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10564 22:19:03.901121 <3>[ 1.994151] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10565 22:19:03.913094 <6>[ 2.009549] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10566 22:19:03.920313 <6>[ 2.016302] xhci-mtk 11200000.usb: xHCI Host Controller
10567 22:19:03.926770 <6>[ 2.021796] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10568 22:19:03.937092 <6>[ 2.029645] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10569 22:19:03.943619 <6>[ 2.039080] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10570 22:19:03.950403 <6>[ 2.045263] xhci-mtk 11200000.usb: xHCI Host Controller
10571 22:19:03.956571 <6>[ 2.050776] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10572 22:19:03.963039 <6>[ 2.058433] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10573 22:19:03.969949 <6>[ 2.066308] hub 1-0:1.0: USB hub found
10574 22:19:03.973631 <6>[ 2.070362] hub 1-0:1.0: 1 port detected
10575 22:19:03.983551 <6>[ 2.074713] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10576 22:19:03.986245 <6>[ 2.083333] hub 2-0:1.0: USB hub found
10577 22:19:03.989517 <6>[ 2.087348] hub 2-0:1.0: 1 port detected
10578 22:19:03.997895 <6>[ 2.094493] mtk-msdc 11f70000.mmc: Got CD GPIO
10579 22:19:04.015439 <6>[ 2.108161] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10580 22:19:04.021863 <6>[ 2.116189] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10581 22:19:04.031765 <4>[ 2.124156] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10582 22:19:04.041649 <6>[ 2.133823] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10583 22:19:04.048323 <6>[ 2.141906] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10584 22:19:04.057751 <6>[ 2.149943] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10585 22:19:04.064813 <6>[ 2.157860] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10586 22:19:04.071375 <6>[ 2.165680] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10587 22:19:04.082095 <6>[ 2.173508] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10588 22:19:04.092001 <6>[ 2.184153] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10589 22:19:04.097935 <6>[ 2.192523] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10590 22:19:04.107944 <6>[ 2.200877] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10591 22:19:04.114494 <6>[ 2.209225] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10592 22:19:04.124485 <6>[ 2.217568] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10593 22:19:04.130948 <6>[ 2.225912] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10594 22:19:04.141958 <6>[ 2.234255] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10595 22:19:04.151211 <6>[ 2.242599] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10596 22:19:04.157701 <6>[ 2.250942] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10597 22:19:04.167420 <6>[ 2.259285] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10598 22:19:04.174678 <6>[ 2.267629] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10599 22:19:04.184280 <6>[ 2.275972] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10600 22:19:04.190423 <6>[ 2.284316] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10601 22:19:04.201000 <6>[ 2.292659] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10602 22:19:04.207505 <6>[ 2.301003] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10603 22:19:04.213429 <6>[ 2.309899] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10604 22:19:04.220590 <6>[ 2.317382] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10605 22:19:04.228435 <6>[ 2.324447] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10606 22:19:04.238334 <6>[ 2.331566] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10607 22:19:04.244999 <6>[ 2.338868] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10608 22:19:04.254793 <6>[ 2.345771] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10609 22:19:04.261664 <6>[ 2.354911] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10610 22:19:04.271313 <6>[ 2.364039] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10611 22:19:04.281784 <6>[ 2.373341] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10612 22:19:04.291112 <6>[ 2.382816] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10613 22:19:04.301336 <6>[ 2.392291] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10614 22:19:04.310903 <6>[ 2.401417] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10615 22:19:04.317883 <6>[ 2.410895] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10616 22:19:04.327492 <6>[ 2.420029] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10617 22:19:04.337912 <6>[ 2.429343] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10618 22:19:04.347739 <6>[ 2.439509] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10619 22:19:04.358084 <6>[ 2.451426] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10620 22:19:04.364608 <6>[ 2.461376] Trying to probe devices needed for running init ...
10621 22:19:04.405472 <6>[ 2.498561] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10622 22:19:04.559748 <6>[ 2.656053] hub 1-1:1.0: USB hub found
10623 22:19:04.563021 <6>[ 2.660529] hub 1-1:1.0: 4 ports detected
10624 22:19:04.686287 <6>[ 2.778913] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10625 22:19:04.711162 <6>[ 2.807215] hub 2-1:1.0: USB hub found
10626 22:19:04.713874 <6>[ 2.811611] hub 2-1:1.0: 3 ports detected
10627 22:19:04.885402 <6>[ 2.978694] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10628 22:19:05.018324 <6>[ 3.114972] hub 1-1.4:1.0: USB hub found
10629 22:19:05.021549 <6>[ 3.119621] hub 1-1.4:1.0: 2 ports detected
10630 22:19:05.097379 <6>[ 3.190935] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10631 22:19:05.321472 <6>[ 3.414693] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10632 22:19:05.513475 <6>[ 3.606700] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10633 22:19:16.661824 <6>[ 14.763250] ALSA device list:
10634 22:19:16.668056 <6>[ 14.766507] No soundcards found.
10635 22:19:16.680562 <6>[ 14.778898] Freeing unused kernel memory: 8384K
10636 22:19:16.683737 <6>[ 14.783832] Run /init as init process
10637 22:19:16.696366 Loading, please wait...
10638 22:19:16.724559 Starting systemd-udevd version 252.6-1
10639 22:19:17.124108 <6>[ 15.219023] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10640 22:19:17.135297 <6>[ 15.229864] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10641 22:19:17.145112 <6>[ 15.237888] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10642 22:19:17.148373 <6>[ 15.243105] remoteproc remoteproc0: scp is available
10643 22:19:17.158958 <4>[ 15.253801] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10644 22:19:17.168865 <6>[ 15.256568] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10645 22:19:17.175953 <6>[ 15.263689] remoteproc remoteproc0: powering up scp
10646 22:19:17.182304 <6>[ 15.275129] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10647 22:19:17.191858 <4>[ 15.278168] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10648 22:19:17.198386 <3>[ 15.295006] remoteproc remoteproc0: request_firmware failed: -2
10649 22:19:17.205542 <3>[ 15.296252] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10650 22:19:17.214905 <4>[ 15.305946] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10651 22:19:17.218304 <4>[ 15.305946] Fallback method does not support PEC.
10652 22:19:17.225419 <6>[ 15.306149] mc: Linux media interface: v0.10
10653 22:19:17.231841 <3>[ 15.309410] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10654 22:19:17.238090 <4>[ 15.310072] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10655 22:19:17.248540 <4>[ 15.310196] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10656 22:19:17.251529 <6>[ 15.325523] usbcore: registered new interface driver r8152
10657 22:19:17.261556 <3>[ 15.330182] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10658 22:19:17.268152 <3>[ 15.349127] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10659 22:19:17.278962 <3>[ 15.350726] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10660 22:19:17.282383 <6>[ 15.369558] videodev: Linux video capture interface: v2.00
10661 22:19:17.292187 <3>[ 15.372988] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10662 22:19:17.298939 <3>[ 15.373001] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10663 22:19:17.308312 <3>[ 15.373015] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10664 22:19:17.315177 <3>[ 15.378401] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10665 22:19:17.321799 <6>[ 15.391802] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10666 22:19:17.331871 <3>[ 15.394913] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10667 22:19:17.338360 <3>[ 15.394956] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10668 22:19:17.345162 <6>[ 15.403012] pci_bus 0000:00: root bus resource [bus 00-ff]
10669 22:19:17.354873 <3>[ 15.411131] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10670 22:19:17.361237 <6>[ 15.414710] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10671 22:19:17.371282 <6>[ 15.415036] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10672 22:19:17.381519 <6>[ 15.415314] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10673 22:19:17.387791 <6>[ 15.419873] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10674 22:19:17.394692 <6>[ 15.420116] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10675 22:19:17.404218 <3>[ 15.426733] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10676 22:19:17.414474 <6>[ 15.434829] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10677 22:19:17.421272 <6>[ 15.434872] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10678 22:19:17.427960 <6>[ 15.435335] usbcore: registered new interface driver cdc_ether
10679 22:19:17.433956 <3>[ 15.442929] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10680 22:19:17.440846 <6>[ 15.443295] usbcore: registered new interface driver r8153_ecm
10681 22:19:17.450940 <4>[ 15.446674] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10682 22:19:17.457020 <4>[ 15.446715] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10683 22:19:17.463757 <6>[ 15.448692] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10684 22:19:17.470603 <6>[ 15.455053] Bluetooth: Core ver 2.22
10685 22:19:17.473862 <6>[ 15.455122] NET: Registered PF_BLUETOOTH protocol family
10686 22:19:17.480878 <6>[ 15.455125] Bluetooth: HCI device and connection manager initialized
10687 22:19:17.487075 <6>[ 15.455142] Bluetooth: HCI socket layer initialized
10688 22:19:17.490309 <6>[ 15.455147] Bluetooth: L2CAP socket layer initialized
10689 22:19:17.496990 <6>[ 15.455157] Bluetooth: SCO socket layer initialized
10690 22:19:17.503456 <3>[ 15.456841] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10691 22:19:17.510213 <6>[ 15.466186] pci 0000:00:00.0: supports D1 D2
10692 22:19:17.516558 <6>[ 15.467316] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10693 22:19:17.530093 <6>[ 15.468473] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10694 22:19:17.533263 <6>[ 15.468632] usbcore: registered new interface driver uvcvideo
10695 22:19:17.543198 <3>[ 15.476175] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10696 22:19:17.549650 <6>[ 15.485220] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10697 22:19:17.556367 <6>[ 15.487317] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10698 22:19:17.566300 <3>[ 15.492366] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10699 22:19:17.569607 <6>[ 15.498591] r8152 2-1.3:1.0 eth0: v1.12.13
10700 22:19:17.576239 <6>[ 15.499620] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10701 22:19:17.582744 <6>[ 15.500412] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10702 22:19:17.589403 <6>[ 15.500649] usbcore: registered new interface driver btusb
10703 22:19:17.599265 <4>[ 15.501938] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10704 22:19:17.605887 <3>[ 15.501947] Bluetooth: hci0: Failed to load firmware file (-2)
10705 22:19:17.612487 <3>[ 15.501951] Bluetooth: hci0: Failed to set up firmware (-2)
10706 22:19:17.622406 <4>[ 15.501955] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10707 22:19:17.629588 <3>[ 15.507570] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10708 22:19:17.638942 <3>[ 15.507577] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10709 22:19:17.645653 <3>[ 15.507615] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10710 22:19:17.651868 <6>[ 15.508765] r8152 2-1.3:1.0 enx002432307c7b: renamed from eth0
10711 22:19:17.658432 <6>[ 15.517521] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10712 22:19:17.668521 <6>[ 15.762912] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10713 22:19:17.675101 <6>[ 15.770404] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10714 22:19:17.678353 <6>[ 15.778146] pci 0000:01:00.0: supports D1 D2
10715 22:19:17.685024 <6>[ 15.782679] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10716 22:19:17.708016 <6>[ 15.802582] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10717 22:19:17.714062 <6>[ 15.809509] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10718 22:19:17.720942 <6>[ 15.817600] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10719 22:19:17.730751 <6>[ 15.825606] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10720 22:19:17.737050 <6>[ 15.833614] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10721 22:19:17.747195 <6>[ 15.841620] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10722 22:19:17.750345 <6>[ 15.849628] pci 0000:00:00.0: PCI bridge to [bus 01]
10723 22:19:17.760101 <6>[ 15.854850] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10724 22:19:17.767180 <6>[ 15.863010] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10725 22:19:17.773617 <6>[ 15.870227] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10726 22:19:17.780047 <6>[ 15.876879] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10727 22:19:17.798049 <5>[ 15.893295] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10728 22:19:17.820721 <5>[ 15.914783] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10729 22:19:17.826467 <4>[ 15.921664] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10730 22:19:17.833174 <6>[ 15.930545] cfg80211: failed to load regulatory.db
10731 22:19:17.883047 <6>[ 15.978119] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10732 22:19:17.889620 <6>[ 15.985633] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10733 22:19:17.914022 <6>[ 16.012487] mt7921e 0000:01:00.0: ASIC revision: 79610010
10734 22:19:18.018468 <4>[ 16.110362] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10735 22:19:18.038713 Begin: Loading essential drivers ... done.
10736 22:19:18.042456 Begin: Running /scripts/init-premount ... done.
10737 22:19:18.048355 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10738 22:19:18.059244 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10739 22:19:18.061557 Device /sys/class/net/enx002432307c7b found
10740 22:19:18.061640 done.
10741 22:19:18.087842 Begin: Waiting up to 180 secs for any network device to become available ... done.
10742 22:19:18.137394 <4>[ 16.229205] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10743 22:19:18.155923 IP-Config: enx002432307c7b hardware address 00:24:32:30:7c:7b mtu 1500 DHCP
10744 22:19:18.257601 <4>[ 16.348809] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10745 22:19:18.376537 <4>[ 16.468437] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10746 22:19:18.492877 <4>[ 16.584388] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10747 22:19:18.608538 <4>[ 16.700169] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10748 22:19:18.724713 <4>[ 16.816147] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10749 22:19:18.840691 <4>[ 16.932113] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10750 22:19:18.956634 <4>[ 17.048136] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10751 22:19:19.072765 <4>[ 17.164108] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10752 22:19:19.179720 <3>[ 17.277936] mt7921e 0000:01:00.0: hardware init failed
10753 22:19:19.250649 <6>[ 17.348928] r8152 2-1.3:1.0 enx002432307c7b: carrier on
10754 22:19:20.093273 IP-Config: no response after 2 secs - giving up
10755 22:19:20.148091 IP-Config: enx002432307c7b hardware address 00:24:32:30:7c:7b mtu 1500 DHCP
10756 22:19:20.151010 IP-Config: enx002432307c7b complete (dhcp from 192.168.201.1):
10757 22:19:20.157484 address: 192.168.201.14 broadcast: 192.168.201.255 netmask: 255.255.255.0
10758 22:19:20.167160 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10759 22:19:20.173975 host : mt8192-asurada-spherion-r0-cbg-2
10760 22:19:20.180471 domain : lava-rack
10761 22:19:20.183710 rootserver: 192.168.201.1 rootpath:
10762 22:19:20.184182 filename :
10763 22:19:20.236355 done.
10764 22:19:20.244228 Begin: Running /scripts/nfs-bottom ... done.
10765 22:19:20.264961 Begin: Running /scripts/init-bottom ... done.
10766 22:19:21.564630 <6>[ 19.663591] NET: Registered PF_INET6 protocol family
10767 22:19:21.571593 <6>[ 19.670297] Segment Routing with IPv6
10768 22:19:21.574575 <6>[ 19.674267] In-situ OAM (IOAM) with IPv6
10769 22:19:21.765792 <30>[ 19.838048] systemd[1]: systemd 252.6-1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10770 22:19:21.772216 <30>[ 19.870489] systemd[1]: Detected architecture arm64.
10771 22:19:21.782241
10772 22:19:21.785914 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10773 22:19:21.786128
10774 22:19:21.809811 <30>[ 19.908747] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10775 22:19:22.633374 <30>[ 20.728967] systemd[1]: Queued start job for default target graphical.target.
10776 22:19:22.677431 <30>[ 20.772700] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10777 22:19:22.683620 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10778 22:19:22.703924 <30>[ 20.799507] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10779 22:19:22.714219 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10780 22:19:22.732789 <30>[ 20.828116] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10781 22:19:22.742693 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10782 22:19:22.760341 <30>[ 20.855342] systemd[1]: Created slice user.slice - User and Session Slice.
10783 22:19:22.766621 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10784 22:19:22.786852 <30>[ 20.878936] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10785 22:19:22.793319 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10786 22:19:22.814582 <30>[ 20.906862] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10787 22:19:22.821562 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10788 22:19:22.849274 <30>[ 20.935041] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10789 22:19:22.859684 <30>[ 20.954926] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10790 22:19:22.866094 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10791 22:19:22.883436 <30>[ 20.978785] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10792 22:19:22.893072 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10793 22:19:22.908015 <30>[ 21.006691] systemd[1]: Reached target paths.target - Path Units.
10794 22:19:22.914562 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10795 22:19:22.935607 <30>[ 21.030959] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10796 22:19:22.941863 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10797 22:19:22.955876 <30>[ 21.054684] systemd[1]: Reached target slices.target - Slice Units.
10798 22:19:22.965773 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10799 22:19:22.980164 <30>[ 21.079022] systemd[1]: Reached target swap.target - Swaps.
10800 22:19:22.987111 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10801 22:19:23.007089 <30>[ 21.102795] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10802 22:19:23.017081 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10803 22:19:23.036430 <30>[ 21.131363] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10804 22:19:23.045853 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10805 22:19:23.065222 <30>[ 21.160647] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10806 22:19:23.075669 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10807 22:19:23.092671 <30>[ 21.188105] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10808 22:19:23.102470 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10809 22:19:23.119520 <30>[ 21.215086] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10810 22:19:23.126484 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10811 22:19:23.144493 <30>[ 21.240025] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10812 22:19:23.154143 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10813 22:19:23.174584 <30>[ 21.269780] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10814 22:19:23.184237 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10815 22:19:23.199319 <30>[ 21.294929] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10816 22:19:23.209246 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10817 22:19:23.259235 <30>[ 21.354963] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10818 22:19:23.266106 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10819 22:19:23.285273 <30>[ 21.381170] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10820 22:19:23.291704 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10821 22:19:23.313385 <30>[ 21.409286] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10822 22:19:23.319725 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10823 22:19:23.345939 <30>[ 21.434927] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10824 22:19:23.358256 <30>[ 21.453829] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10825 22:19:23.367694 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10826 22:19:23.385738 <30>[ 21.481508] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10827 22:19:23.392511 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10828 22:19:23.413807 <30>[ 21.509609] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10829 22:19:23.420512 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10830 22:19:23.441530 <30>[ 21.537501] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10831 22:19:23.448477 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10832 22:19:23.458024 <6>[ 21.553159] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10833 22:19:23.470328 <30>[ 21.566276] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10834 22:19:23.477254 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10835 22:19:23.501999 <30>[ 21.597742] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
10836 22:19:23.508235 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
10837 22:19:23.529870 <30>[ 21.625893] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10838 22:19:23.540007 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop..<6>[ 21.640374] fuse: init (API version 7.37)
10839 22:19:23.540115 .
10840 22:19:23.564655 <30>[ 21.660072] systemd[1]: Starting systemd-journald.service - Journal Service...
10841 22:19:23.570655 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10842 22:19:23.596626 <30>[ 21.692209] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10843 22:19:23.602675 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10844 22:19:23.663360 <30>[ 21.755630] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10845 22:19:23.669798 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10846 22:19:23.690007 <30>[ 21.785697] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10847 22:19:23.699771 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10848 22:19:23.722362 <30>[ 21.817888] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10849 22:19:23.732679 <3>[ 21.825533] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10850 22:19:23.738931 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10851 22:19:23.762124 <3>[ 21.857519] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10852 22:19:23.768552 <30>[ 21.858689] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
10853 22:19:23.778244 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10854 22:19:23.795982 <30>[ 21.891358] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
10855 22:19:23.803161 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10856 22:19:23.812666 <3>[ 21.907175] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10857 22:19:23.823554 <30>[ 21.919225] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
10858 22:19:23.830035 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10859 22:19:23.844646 <3>[ 21.940382] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10860 22:19:23.854581 <30>[ 21.950051] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
10861 22:19:23.864882 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10862 22:19:23.874605 <3>[ 21.969817] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10863 22:19:23.884454 <30>[ 21.979780] systemd[1]: modprobe@configfs.service: Deactivated successfully.
10864 22:19:23.891464 <30>[ 21.987710] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
10865 22:19:23.908276 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - <3>[ 22.000659] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10866 22:19:23.908366 Load Kernel Module configfs.
10867 22:19:23.928607 <30>[ 22.024025] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
10868 22:19:23.935442 <30>[ 22.031735] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
10869 22:19:23.945449 <3>[ 22.037247] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10870 22:19:23.951887 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10871 22:19:23.971785 <30>[ 22.067622] systemd[1]: modprobe@drm.service: Deactivated successfully.
10872 22:19:23.978399 <3>[ 22.072728] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10873 22:19:23.988315 <30>[ 22.075176] systemd[1]: Finished modprobe@drm.service - Load Kernel Module drm.
10874 22:19:23.994731 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10875 22:19:24.010368 <3>[ 22.105965] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10876 22:19:24.019974 <30>[ 22.116037] systemd[1]: modprobe@efi_pstore.service: Deactivated successfully.
10877 22:19:24.030369 <30>[ 22.124284] systemd[1]: Finished modprobe@efi_pstore.service - Load Kernel Module efi_pstore.
10878 22:19:24.036976 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10879 22:19:24.051129 <3>[ 22.146524] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10880 22:19:24.060791 <30>[ 22.156592] systemd[1]: modprobe@fuse.service: Deactivated successfully.
10881 22:19:24.067841 <30>[ 22.164050] systemd[1]: Finished modprobe@fuse.service - Load Kernel Module fuse.
10882 22:19:24.074514 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
10883 22:19:24.093245 <30>[ 22.191635] systemd[1]: modprobe@loop.service: Deactivated successfully.
10884 22:19:24.103308 <30>[ 22.199089] systemd[1]: Finished modprobe@loop.service - Load Kernel Module loop.
10885 22:19:24.109789 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10886 22:19:24.127612 <30>[ 22.223519] systemd[1]: Started systemd-journald.service - Journal Service.
10887 22:19:24.134317 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10888 22:19:24.153281 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10889 22:19:24.172275 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10890 22:19:24.191672 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
10891 22:19:24.212576 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10892 22:19:24.263855 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
10893 22:19:24.286588 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10894 22:19:24.310376 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10895 22:19:24.332887 <4>[ 22.421923] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10896 22:19:24.339359 <3>[ 22.437612] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10897 22:19:24.349774 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10898 22:19:24.382138 Starting [0;1;39msyste<46>[ 22.476362] systemd-journald[297]: Received client request to flush runtime journal.
10899 22:19:24.385404 md-sysctl.se…ce[0m - Apply Kernel Variables...
10900 22:19:24.407936 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10901 22:19:24.524964 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10902 22:19:24.547646 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
10903 22:19:24.563658 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10904 22:19:24.583678 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10905 22:19:25.158667 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10906 22:19:25.762800 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10907 22:19:25.779911 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10908 22:19:25.823707 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10909 22:19:25.943784 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10910 22:19:25.967466 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10911 22:19:25.982975 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10912 22:19:26.027201 Starting [0;1;39msystemd-binfmt.se…et Up Additional Binary Formats...
10913 22:19:26.046856 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10914 22:19:26.067085 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10915 22:19:26.096146 [[0;1;31mFAILED[0m] Failed to start [0;1;39msystemd-bi… Set Up Additional Binary Formats.
10916 22:19:26.111220 See 'systemctl status systemd-binfmt.service' for details.
10917 22:19:26.339956 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10918 22:19:26.400824 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
10919 22:19:26.471789 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10920 22:19:26.601215 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10921 22:19:26.791568 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10922 22:19:26.822795 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10923 22:19:26.920000 <6>[ 25.019156] remoteproc remoteproc0: powering up scp
10924 22:19:26.930724 <4>[ 25.026441] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10925 22:19:26.937069 <3>[ 25.036299] remoteproc remoteproc0: request_firmware failed: -2
10926 22:19:26.946830 <3>[ 25.042477] fops_vcodec_open(),166: [MTK_V4L2][ERROR] vpu_load_firmware failed!
10927 22:19:26.959865 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
10928 22:19:26.979670 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
10929 22:19:26.996014 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
10930 22:19:27.035574 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
10931 22:19:27.055456 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
10932 22:19:27.083774 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
10933 22:19:27.128583 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
10934 22:19:27.152443 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
10935 22:19:27.173672 [[0;32m OK [0m] Finished [0<46>[ 25.271302] systemd-journald[297]: Time jumped backwards, rotating.
10936 22:19:27.179710 ;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
10937 22:19:27.199711 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
10938 22:19:27.219757 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
10939 22:19:27.240957 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
10940 22:19:27.260946 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
10941 22:19:27.968545 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
10942 22:19:28.298003 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
10943 22:19:28.315036 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
10944 22:19:28.657512 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
10945 22:19:28.678342 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
10946 22:19:28.694493 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
10947 22:19:28.710266 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
10948 22:19:29.036024 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
10949 22:19:29.054635 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
10950 22:19:29.074964 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
10951 22:19:29.123934 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
10952 22:19:29.163062 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
10953 22:19:29.250992 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
10954 22:19:29.274309 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
10955 22:19:29.418821 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
10956 22:19:29.467093 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
10957 22:19:29.486883 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
10958 22:19:29.508102 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
10959 22:19:29.523978 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
10960 22:19:29.549939 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
10961 22:19:29.574197 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
10962 22:19:29.598358 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
10963 22:19:29.615034 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
10964 22:19:29.671878 Starting [0;1;39msystemd-hostnamed.service[0m - Hostname Service...
10965 22:19:29.691092 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
10966 22:19:29.742787 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
10967 22:19:29.845434 [[0;32m OK [0m] Started [0;1;39msystemd-hostnamed.service[0m - Hostname Service.
10968 22:19:29.929107
10969 22:19:29.929245
10970 22:19:29.932177 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
10971 22:19:29.932253
10972 22:19:29.935510 debian-bookworm-arm64 login: root (automatic login)
10973 22:19:29.935587
10974 22:19:29.935652
10975 22:19:30.228884 Linux debian-bookworm-arm64 6.1.31 #1 SMP PREEMPT Mon Jun 5 22:04:07 UTC 2023 aarch64
10976 22:19:30.229064
10977 22:19:30.235259 The programs included with the Debian GNU/Linux system are free software;
10978 22:19:30.242095 the exact distribution terms for each program are described in the
10979 22:19:30.245675 individual files in /usr/share/doc/*/copyright.
10980 22:19:30.245837
10981 22:19:30.252095 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10982 22:19:30.255342 permitted by applicable law.
10983 22:19:31.262516 Matched prompt #10: / #
10985 22:19:31.263674 Setting prompt string to ['/ #']
10986 22:19:31.264133 end: 2.2.5.1 login-action (duration 00:00:30) [common]
10988 22:19:31.265108 end: 2.2.5 auto-login-action (duration 00:00:30) [common]
10989 22:19:31.265555 start: 2.2.6 expect-shell-connection (timeout 00:03:17) [common]
10990 22:19:31.265920 Setting prompt string to ['/ #']
10991 22:19:31.266232 Forcing a shell prompt, looking for ['/ #']
10993 22:19:31.316997 / #
10994 22:19:31.317672 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10995 22:19:31.318181 Waiting using forced prompt support (timeout 00:02:30)
10996 22:19:31.322828
10997 22:19:31.323687 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10998 22:19:31.324348 start: 2.2.7 export-device-env (timeout 00:03:17) [common]
11000 22:19:31.425650 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/10597265/extract-nfsrootfs-jdvhjo22'
11001 22:19:31.432220 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/10597265/extract-nfsrootfs-jdvhjo22'
11003 22:19:31.534009 / # export NFS_SERVER_IP='192.168.201.1'
11004 22:19:31.540936 export NFS_SERVER_IP='192.168.201.1'
11005 22:19:31.541864 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11006 22:19:31.542419 end: 2.2 depthcharge-retry (duration 00:01:43) [common]
11007 22:19:31.542923 end: 2 depthcharge-action (duration 00:01:43) [common]
11008 22:19:31.543409 start: 3 lava-test-retry (timeout 00:07:35) [common]
11009 22:19:31.543971 start: 3.1 lava-test-shell (timeout 00:07:35) [common]
11010 22:19:31.544427 Using namespace: common
11012 22:19:31.645598 / # #
11013 22:19:31.646174 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11014 22:19:31.651406 #
11015 22:19:31.652153 Using /lava-10597265
11017 22:19:31.753221 / # export SHELL=/bin/bash
11018 22:19:31.759226 export SHELL=/bin/bash
11020 22:19:31.860728 / # . /lava-10597265/environment
11021 22:19:31.866640 . /lava-10597265/environment
11023 22:19:31.973998 / # /lava-10597265/bin/lava-test-runner /lava-10597265/0
11024 22:19:31.974645 Test shell timeout: 10s (minimum of the action and connection timeout)
11025 22:19:31.980146 /lava-10597265/bin/lava-test-runner /lava-10597265/0
11026 22:19:32.275206 + export TESTRUN_ID=0_timesync-off
11027 22:19:32.278293 + TESTRUN_ID=0_timesync-off
11028 22:19:32.281483 + cd /lava-10597265/0/tests/0_timesync-off
11029 22:19:32.284501 ++ cat uuid
11030 22:19:32.294051 + UUID=10597265_1.6.2.3.1
11031 22:19:32.294479 + set +x
11032 22:19:32.300459 <LAVA_SIGNAL_STARTRUN 0_timesync-off 10597265_1.6.2.3.1>
11033 22:19:32.301150 Received signal: <STARTRUN> 0_timesync-off 10597265_1.6.2.3.1
11034 22:19:32.301523 Starting test lava.0_timesync-off (10597265_1.6.2.3.1)
11035 22:19:32.301984 Skipping test definition patterns.
11036 22:19:32.303929 + systemctl stop systemd-timesyncd
11037 22:19:32.369383 + set +x
11038 22:19:32.372411 <LAVA_SIGNAL_ENDRUN 0_timesync-off 10597265_1.6.2.3.1>
11039 22:19:32.373086 Received signal: <ENDRUN> 0_timesync-off 10597265_1.6.2.3.1
11040 22:19:32.373505 Ending use of test pattern.
11041 22:19:32.373820 Ending test lava.0_timesync-off (10597265_1.6.2.3.1), duration 0.07
11043 22:19:32.464262 + export TESTRUN_ID=1_kselftest-alsa
11044 22:19:32.467580 + TESTRUN_ID=1_kselftest-alsa
11045 22:19:32.473965 + cd /lava-10597265/0/tests/1_kselftest-alsa
11046 22:19:32.474395 ++ cat uuid
11047 22:19:32.479749 + UUID=10597265_1.6.2.3.5
11048 22:19:32.480218 + set +x
11049 22:19:32.486942 <LAVA_SIGNAL_STARTRUN 1_kselftest-alsa 10597265_1.6.2.3.5>
11050 22:19:32.487615 Received signal: <STARTRUN> 1_kselftest-alsa 10597265_1.6.2.3.5
11051 22:19:32.487970 Starting test lava.1_kselftest-alsa (10597265_1.6.2.3.5)
11052 22:19:32.488408 Skipping test definition patterns.
11053 22:19:32.489718 + cd ./automated/linux/kselftest/
11054 22:19:32.516203 + ./kselftest.sh -c alsa -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1314-g1ab0ac1d7e2e3/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip-gitlab -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11055 22:19:32.578101 INFO: install_deps skipped
11056 22:19:33.078930 --2023-06-05 22:19:33-- http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1314-g1ab0ac1d7e2e3/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11057 22:19:33.085198 Resolving storage.kernelci.org (storage.kernelci.org)... 52.250.1.28
11058 22:19:33.229938 Connecting to storage.kernelci.org (storage.kernelci.org)|52.250.1.28|:80... connected.
11059 22:19:33.381207 HTTP request sent, awaiting response... 200 OK
11060 22:19:33.384100 Length: 2860080 (2.7M) [application/octet-stream]
11061 22:19:33.387086 Saving to: 'kselftest.tar.xz'
11062 22:19:33.387552
11063 22:19:33.387922
11064 22:19:33.681525 kselftest.tar.xz 0%[ ] 0 --.-KB/s
11065 22:19:33.982195 kselftest.tar.xz 1%[ ] 47.81K 160KB/s
11066 22:19:34.482396 kselftest.tar.xz 7%[> ] 217.50K 362KB/s
11067 22:19:34.790443 kselftest.tar.xz 28%[====> ] 807.16K 734KB/s
11068 22:19:34.887091 kselftest.tar.xz 84%[===============> ] 2.32M 1.64MB/s
11069 22:19:34.893682 kselftest.tar.xz 100%[===================>] 2.73M 1.81MB/s in 1.5s
11070 22:19:34.894351
11071 22:19:35.140897 2023-06-05 22:19:35 (1.81 MB/s) - 'kselftest.tar.xz' saved [2860080/2860080]
11072 22:19:35.141037
11073 22:19:42.008447 skiplist:
11074 22:19:42.012024 ========================================
11075 22:19:42.014233 ========================================
11076 22:19:42.066880 alsa:mixer-test
11077 22:19:42.088415 ============== Tests to run ===============
11078 22:19:42.092001 alsa:mixer-test
11079 22:19:42.095061 ===========End Tests to run ===============
11080 22:19:42.198866 <12>[ 40.299582] kselftest: Running tests in alsa
11081 22:19:42.207654 TAP version 13
11082 22:19:42.223712 1..1
11083 22:19:42.242168 # selftests: alsa: mixer-test
11084 22:19:42.715270 # TAP version 13
11085 22:19:42.715804 # 1..0
11086 22:19:42.722102 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:0 error:0
11087 22:19:42.725196 ok 1 selftests: alsa: mixer-test
11088 22:19:43.414441 alsa_mixer-test pass
11089 22:19:43.446627 + ../../utils/send-to-lava.sh ./output/result.txt
11090 22:19:43.536025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test RESULT=pass>
11091 22:19:43.536581 + set +x
11092 22:19:43.537189 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test RESULT=pass
11094 22:19:43.543049 <LAVA_SIGNAL_ENDRUN 1_kselftest-alsa 10597265_1.6.2.3.5>
11095 22:19:43.543845 Received signal: <ENDRUN> 1_kselftest-alsa 10597265_1.6.2.3.5
11096 22:19:43.544289 Ending use of test pattern.
11097 22:19:43.544616 Ending test lava.1_kselftest-alsa (10597265_1.6.2.3.5), duration 11.06
11099 22:19:43.545959 <LAVA_TEST_RUNNER EXIT>
11100 22:19:43.546646 ok: lava_test_shell seems to have completed
11101 22:19:43.547130 alsa_mixer-test: pass
11102 22:19:43.547554 end: 3.1 lava-test-shell (duration 00:00:12) [common]
11103 22:19:43.548000 end: 3 lava-test-retry (duration 00:00:12) [common]
11104 22:19:43.548500 start: 4 finalize (timeout 00:07:23) [common]
11105 22:19:43.548959 start: 4.1 power-off (timeout 00:00:30) [common]
11106 22:19:43.549707 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-2' '--port=1' '--command=off'
11107 22:19:43.668831 >> Command sent successfully.
11108 22:19:43.678864 Returned 0 in 0 seconds
11109 22:19:43.780108 end: 4.1 power-off (duration 00:00:00) [common]
11111 22:19:43.781577 start: 4.2 read-feedback (timeout 00:07:22) [common]
11112 22:19:43.782726 Listened to connection for namespace 'common' for up to 1s
11113 22:19:44.783442 Finalising connection for namespace 'common'
11114 22:19:44.784138 Disconnecting from shell: Finalise
11115 22:19:44.784616 / #
11116 22:19:44.885623 end: 4.2 read-feedback (duration 00:00:01) [common]
11117 22:19:44.886246 end: 4 finalize (duration 00:00:01) [common]
11118 22:19:44.886807 Cleaning after the job
11119 22:19:44.887318 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10597265/tftp-deploy-dqirrpjl/ramdisk
11120 22:19:44.897948 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10597265/tftp-deploy-dqirrpjl/kernel
11121 22:19:44.925859 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10597265/tftp-deploy-dqirrpjl/dtb
11122 22:19:44.926236 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10597265/tftp-deploy-dqirrpjl/nfsrootfs
11123 22:19:45.005633 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10597265/tftp-deploy-dqirrpjl/modules
11124 22:19:45.011046 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/10597265
11125 22:19:45.533014 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/10597265
11126 22:19:45.533203 Job finished correctly