Boot log: mt8192-asurada-spherion-r0
- Errors: 2
- Kernel Errors: 35
- Boot result: FAIL
- Warnings: 1
- Kernel Warnings: 28
1 22:14:06.971811 lava-dispatcher, installed at version: 2023.05.1
2 22:14:06.972029 start: 0 validate
3 22:14:06.972161 Start time: 2023-06-05 22:14:06.972153+00:00 (UTC)
4 22:14:06.972298 Using caching service: 'http://localhost/cache/?uri=%s'
5 22:14:06.972430 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye%2F20230527.0%2Farm64%2Frootfs.cpio.gz exists
6 22:14:07.271071 Using caching service: 'http://localhost/cache/?uri=%s'
7 22:14:07.271897 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1314-g1ab0ac1d7e2e3%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 22:14:24.281809 Using caching service: 'http://localhost/cache/?uri=%s'
9 22:14:24.282568 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1314-g1ab0ac1d7e2e3%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 22:14:24.581123 Using caching service: 'http://localhost/cache/?uri=%s'
11 22:14:24.581876 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1314-g1ab0ac1d7e2e3%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 22:14:28.878051 validate duration: 21.91
14 22:14:28.878311 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 22:14:28.878405 start: 1.1 download-retry (timeout 00:10:00) [common]
16 22:14:28.878497 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 22:14:28.878617 Not decompressing ramdisk as can be used compressed.
18 22:14:28.878699 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye/20230527.0/arm64/rootfs.cpio.gz
19 22:14:28.878762 saving as /var/lib/lava/dispatcher/tmp/10597240/tftp-deploy-g8u9ngxh/ramdisk/rootfs.cpio.gz
20 22:14:28.878822 total size: 84903995 (80MB)
21 22:14:29.189451 progress 0% (0MB)
22 22:14:29.210895 progress 5% (4MB)
23 22:14:29.231990 progress 10% (8MB)
24 22:14:29.253278 progress 15% (12MB)
25 22:14:29.274549 progress 20% (16MB)
26 22:14:29.296008 progress 25% (20MB)
27 22:14:29.317817 progress 30% (24MB)
28 22:14:29.339097 progress 35% (28MB)
29 22:14:29.360455 progress 40% (32MB)
30 22:14:29.381594 progress 45% (36MB)
31 22:14:29.403096 progress 50% (40MB)
32 22:14:29.424471 progress 55% (44MB)
33 22:14:29.445850 progress 60% (48MB)
34 22:14:29.467006 progress 65% (52MB)
35 22:14:29.488650 progress 70% (56MB)
36 22:14:29.510552 progress 75% (60MB)
37 22:14:29.532149 progress 80% (64MB)
38 22:14:29.553684 progress 85% (68MB)
39 22:14:29.574708 progress 90% (72MB)
40 22:14:29.596359 progress 95% (76MB)
41 22:14:29.617346 progress 100% (80MB)
42 22:14:29.617511 80MB downloaded in 0.74s (109.61MB/s)
43 22:14:29.617718 end: 1.1.1 http-download (duration 00:00:01) [common]
45 22:14:29.617953 end: 1.1 download-retry (duration 00:00:01) [common]
46 22:14:29.618038 start: 1.2 download-retry (timeout 00:09:59) [common]
47 22:14:29.618120 start: 1.2.1 http-download (timeout 00:09:59) [common]
48 22:14:29.618252 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1314-g1ab0ac1d7e2e3/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 22:14:29.618324 saving as /var/lib/lava/dispatcher/tmp/10597240/tftp-deploy-g8u9ngxh/kernel/Image
50 22:14:29.618386 total size: 45746688 (43MB)
51 22:14:29.618446 No compression specified
52 22:14:29.619548 progress 0% (0MB)
53 22:14:29.630946 progress 5% (2MB)
54 22:14:29.642657 progress 10% (4MB)
55 22:14:29.654281 progress 15% (6MB)
56 22:14:29.665872 progress 20% (8MB)
57 22:14:29.677319 progress 25% (10MB)
58 22:14:29.688688 progress 30% (13MB)
59 22:14:29.700488 progress 35% (15MB)
60 22:14:29.712150 progress 40% (17MB)
61 22:14:29.723728 progress 45% (19MB)
62 22:14:29.735462 progress 50% (21MB)
63 22:14:29.746943 progress 55% (24MB)
64 22:14:29.758591 progress 60% (26MB)
65 22:14:29.770007 progress 65% (28MB)
66 22:14:29.781510 progress 70% (30MB)
67 22:14:29.792964 progress 75% (32MB)
68 22:14:29.804680 progress 80% (34MB)
69 22:14:29.816482 progress 85% (37MB)
70 22:14:29.828163 progress 90% (39MB)
71 22:14:29.839767 progress 95% (41MB)
72 22:14:29.851258 progress 100% (43MB)
73 22:14:29.851467 43MB downloaded in 0.23s (187.18MB/s)
74 22:14:29.851618 end: 1.2.1 http-download (duration 00:00:00) [common]
76 22:14:29.851844 end: 1.2 download-retry (duration 00:00:00) [common]
77 22:14:29.851930 start: 1.3 download-retry (timeout 00:09:59) [common]
78 22:14:29.852015 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 22:14:29.852151 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1314-g1ab0ac1d7e2e3/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 22:14:29.852224 saving as /var/lib/lava/dispatcher/tmp/10597240/tftp-deploy-g8u9ngxh/dtb/mt8192-asurada-spherion-r0.dtb
81 22:14:29.852288 total size: 46924 (0MB)
82 22:14:29.852348 No compression specified
83 22:14:29.853462 progress 69% (0MB)
84 22:14:29.853770 progress 100% (0MB)
85 22:14:29.853922 0MB downloaded in 0.00s (27.42MB/s)
86 22:14:29.854041 end: 1.3.1 http-download (duration 00:00:00) [common]
88 22:14:29.854259 end: 1.3 download-retry (duration 00:00:00) [common]
89 22:14:29.854342 start: 1.4 download-retry (timeout 00:09:59) [common]
90 22:14:29.854423 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 22:14:29.854530 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1314-g1ab0ac1d7e2e3/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 22:14:29.854597 saving as /var/lib/lava/dispatcher/tmp/10597240/tftp-deploy-g8u9ngxh/modules/modules.tar
93 22:14:29.854657 total size: 8543056 (8MB)
94 22:14:29.854717 Using unxz to decompress xz
95 22:14:29.858416 progress 0% (0MB)
96 22:14:29.879782 progress 5% (0MB)
97 22:14:29.904866 progress 10% (0MB)
98 22:14:29.930326 progress 15% (1MB)
99 22:14:29.955673 progress 20% (1MB)
100 22:14:29.978941 progress 25% (2MB)
101 22:14:30.005437 progress 30% (2MB)
102 22:14:30.030217 progress 35% (2MB)
103 22:14:30.054924 progress 40% (3MB)
104 22:14:30.078866 progress 45% (3MB)
105 22:14:30.103760 progress 50% (4MB)
106 22:14:30.126920 progress 55% (4MB)
107 22:14:30.151709 progress 60% (4MB)
108 22:14:30.177025 progress 65% (5MB)
109 22:14:30.201741 progress 70% (5MB)
110 22:14:30.224878 progress 75% (6MB)
111 22:14:30.249321 progress 80% (6MB)
112 22:14:30.273923 progress 85% (6MB)
113 22:14:30.302844 progress 90% (7MB)
114 22:14:30.327757 progress 95% (7MB)
115 22:14:30.352275 progress 100% (8MB)
116 22:14:30.358022 8MB downloaded in 0.50s (16.19MB/s)
117 22:14:30.358315 end: 1.4.1 http-download (duration 00:00:01) [common]
119 22:14:30.358589 end: 1.4 download-retry (duration 00:00:01) [common]
120 22:14:30.358719 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 22:14:30.358815 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 22:14:30.358901 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 22:14:30.358988 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 22:14:30.359209 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/10597240/lava-overlay-xavrg6qh
125 22:14:30.359363 makedir: /var/lib/lava/dispatcher/tmp/10597240/lava-overlay-xavrg6qh/lava-10597240/bin
126 22:14:30.359483 makedir: /var/lib/lava/dispatcher/tmp/10597240/lava-overlay-xavrg6qh/lava-10597240/tests
127 22:14:30.359578 makedir: /var/lib/lava/dispatcher/tmp/10597240/lava-overlay-xavrg6qh/lava-10597240/results
128 22:14:30.359690 Creating /var/lib/lava/dispatcher/tmp/10597240/lava-overlay-xavrg6qh/lava-10597240/bin/lava-add-keys
129 22:14:30.359838 Creating /var/lib/lava/dispatcher/tmp/10597240/lava-overlay-xavrg6qh/lava-10597240/bin/lava-add-sources
130 22:14:30.359965 Creating /var/lib/lava/dispatcher/tmp/10597240/lava-overlay-xavrg6qh/lava-10597240/bin/lava-background-process-start
131 22:14:30.360093 Creating /var/lib/lava/dispatcher/tmp/10597240/lava-overlay-xavrg6qh/lava-10597240/bin/lava-background-process-stop
132 22:14:30.360214 Creating /var/lib/lava/dispatcher/tmp/10597240/lava-overlay-xavrg6qh/lava-10597240/bin/lava-common-functions
133 22:14:30.360334 Creating /var/lib/lava/dispatcher/tmp/10597240/lava-overlay-xavrg6qh/lava-10597240/bin/lava-echo-ipv4
134 22:14:30.360454 Creating /var/lib/lava/dispatcher/tmp/10597240/lava-overlay-xavrg6qh/lava-10597240/bin/lava-install-packages
135 22:14:30.360574 Creating /var/lib/lava/dispatcher/tmp/10597240/lava-overlay-xavrg6qh/lava-10597240/bin/lava-installed-packages
136 22:14:30.360733 Creating /var/lib/lava/dispatcher/tmp/10597240/lava-overlay-xavrg6qh/lava-10597240/bin/lava-os-build
137 22:14:30.360854 Creating /var/lib/lava/dispatcher/tmp/10597240/lava-overlay-xavrg6qh/lava-10597240/bin/lava-probe-channel
138 22:14:30.360974 Creating /var/lib/lava/dispatcher/tmp/10597240/lava-overlay-xavrg6qh/lava-10597240/bin/lava-probe-ip
139 22:14:30.361098 Creating /var/lib/lava/dispatcher/tmp/10597240/lava-overlay-xavrg6qh/lava-10597240/bin/lava-target-ip
140 22:14:30.361219 Creating /var/lib/lava/dispatcher/tmp/10597240/lava-overlay-xavrg6qh/lava-10597240/bin/lava-target-mac
141 22:14:30.361338 Creating /var/lib/lava/dispatcher/tmp/10597240/lava-overlay-xavrg6qh/lava-10597240/bin/lava-target-storage
142 22:14:30.361462 Creating /var/lib/lava/dispatcher/tmp/10597240/lava-overlay-xavrg6qh/lava-10597240/bin/lava-test-case
143 22:14:30.361583 Creating /var/lib/lava/dispatcher/tmp/10597240/lava-overlay-xavrg6qh/lava-10597240/bin/lava-test-event
144 22:14:30.361701 Creating /var/lib/lava/dispatcher/tmp/10597240/lava-overlay-xavrg6qh/lava-10597240/bin/lava-test-feedback
145 22:14:30.361820 Creating /var/lib/lava/dispatcher/tmp/10597240/lava-overlay-xavrg6qh/lava-10597240/bin/lava-test-raise
146 22:14:30.361940 Creating /var/lib/lava/dispatcher/tmp/10597240/lava-overlay-xavrg6qh/lava-10597240/bin/lava-test-reference
147 22:14:30.362061 Creating /var/lib/lava/dispatcher/tmp/10597240/lava-overlay-xavrg6qh/lava-10597240/bin/lava-test-runner
148 22:14:30.362180 Creating /var/lib/lava/dispatcher/tmp/10597240/lava-overlay-xavrg6qh/lava-10597240/bin/lava-test-set
149 22:14:30.362302 Creating /var/lib/lava/dispatcher/tmp/10597240/lava-overlay-xavrg6qh/lava-10597240/bin/lava-test-shell
150 22:14:30.362425 Updating /var/lib/lava/dispatcher/tmp/10597240/lava-overlay-xavrg6qh/lava-10597240/bin/lava-install-packages (oe)
151 22:14:30.362574 Updating /var/lib/lava/dispatcher/tmp/10597240/lava-overlay-xavrg6qh/lava-10597240/bin/lava-installed-packages (oe)
152 22:14:30.362743 Creating /var/lib/lava/dispatcher/tmp/10597240/lava-overlay-xavrg6qh/lava-10597240/environment
153 22:14:30.362841 LAVA metadata
154 22:14:30.362920 - LAVA_JOB_ID=10597240
155 22:14:30.362987 - LAVA_DISPATCHER_IP=192.168.201.1
156 22:14:30.363091 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 22:14:30.363159 skipped lava-vland-overlay
158 22:14:30.363236 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 22:14:30.363318 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 22:14:30.363424 skipped lava-multinode-overlay
161 22:14:30.363499 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 22:14:30.363583 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 22:14:30.363660 Loading test definitions
164 22:14:30.363752 start: 1.5.2.3.1 git-repo-action (timeout 00:09:59) [common]
165 22:14:30.363827 Using /lava-10597240 at stage 0
166 22:14:30.363923 Fetching tests from https://github.com/kernelci/kernelci-core
167 22:14:30.364006 Running '/usr/bin/git clone -b kernelci.org --depth=1 https://github.com/kernelci/kernelci-core /var/lib/lava/dispatcher/tmp/10597240/lava-overlay-xavrg6qh/lava-10597240/0/tests/0_sleep'
168 22:14:31.006592 Removing '.git' directory in /var/lib/lava/dispatcher/tmp/10597240/lava-overlay-xavrg6qh/lava-10597240/0/tests/0_sleep
169 22:14:31.007850 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/10597240/lava-overlay-xavrg6qh/lava-10597240/0/tests/0_sleep/config/lava/sleep/sleep.yaml
170 22:14:31.008246 uuid=10597240_1.5.2.3.1 testdef=None
171 22:14:31.008394 end: 1.5.2.3.1 git-repo-action (duration 00:00:01) [common]
173 22:14:31.008644 start: 1.5.2.3.2 test-overlay (timeout 00:09:58) [common]
174 22:14:31.009188 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
176 22:14:31.009426 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:58) [common]
177 22:14:31.010153 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
179 22:14:31.010398 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:58) [common]
180 22:14:31.011044 runner path: /var/lib/lava/dispatcher/tmp/10597240/lava-overlay-xavrg6qh/lava-10597240/0/tests/0_sleep test_uuid 10597240_1.5.2.3.1
181 22:14:31.011129 sleep_params='mem freeze'
182 22:14:31.011267 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
184 22:14:31.011552 Creating lava-test-runner.conf files
185 22:14:31.011617 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10597240/lava-overlay-xavrg6qh/lava-10597240/0 for stage 0
186 22:14:31.011707 - 0_sleep
187 22:14:31.011813 end: 1.5.2.3 test-definition (duration 00:00:01) [common]
188 22:14:31.011900 start: 1.5.2.4 compress-overlay (timeout 00:09:58) [common]
189 22:14:31.132527 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
190 22:14:31.132684 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:58) [common]
191 22:14:31.132779 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
192 22:14:31.132878 end: 1.5.2 lava-overlay (duration 00:00:01) [common]
193 22:14:31.132965 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:58) [common]
194 22:14:33.469365 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:02) [common]
195 22:14:33.469729 start: 1.5.4 extract-modules (timeout 00:09:55) [common]
196 22:14:33.469854 extracting modules file /var/lib/lava/dispatcher/tmp/10597240/tftp-deploy-g8u9ngxh/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10597240/extract-overlay-ramdisk-ew4ldsm_/ramdisk
197 22:14:33.683253 end: 1.5.4 extract-modules (duration 00:00:00) [common]
198 22:14:33.683472 start: 1.5.5 apply-overlay-tftp (timeout 00:09:55) [common]
199 22:14:33.683572 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10597240/compress-overlay-72zposfr/overlay-1.5.2.4.tar.gz to ramdisk
200 22:14:33.683648 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10597240/compress-overlay-72zposfr/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/10597240/extract-overlay-ramdisk-ew4ldsm_/ramdisk
201 22:14:33.771856 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
202 22:14:33.772017 start: 1.5.6 configure-preseed-file (timeout 00:09:55) [common]
203 22:14:33.772114 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
204 22:14:33.772204 start: 1.5.7 compress-ramdisk (timeout 00:09:55) [common]
205 22:14:33.772291 Building ramdisk /var/lib/lava/dispatcher/tmp/10597240/extract-overlay-ramdisk-ew4ldsm_/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/10597240/extract-overlay-ramdisk-ew4ldsm_/ramdisk
206 22:14:35.149472 >> 561596 blocks
207 22:14:44.779826 rename /var/lib/lava/dispatcher/tmp/10597240/extract-overlay-ramdisk-ew4ldsm_/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/10597240/tftp-deploy-g8u9ngxh/ramdisk/ramdisk.cpio.gz
208 22:14:44.780374 end: 1.5.7 compress-ramdisk (duration 00:00:11) [common]
209 22:14:44.780547 start: 1.5.8 prepare-kernel (timeout 00:09:44) [common]
210 22:14:44.780694 start: 1.5.8.1 prepare-fit (timeout 00:09:44) [common]
211 22:14:44.780852 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/10597240/tftp-deploy-g8u9ngxh/kernel/Image'
212 22:14:56.645605 Returned 0 in 11 seconds
213 22:14:56.746503 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/10597240/tftp-deploy-g8u9ngxh/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/10597240/tftp-deploy-g8u9ngxh/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/10597240/tftp-deploy-g8u9ngxh/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/10597240/tftp-deploy-g8u9ngxh/kernel/image.itb
214 22:14:58.008550 output: FIT description: Kernel Image image with one or more FDT blobs
215 22:14:58.008894 output: Created: Mon Jun 5 23:14:57 2023
216 22:14:58.008968 output: Image 0 (kernel-1)
217 22:14:58.009034 output: Description:
218 22:14:58.009126 output: Created: Mon Jun 5 23:14:57 2023
219 22:14:58.009214 output: Type: Kernel Image
220 22:14:58.009273 output: Compression: lzma compressed
221 22:14:58.009347 output: Data Size: 10082307 Bytes = 9846.00 KiB = 9.62 MiB
222 22:14:58.009420 output: Architecture: AArch64
223 22:14:58.009482 output: OS: Linux
224 22:14:58.009558 output: Load Address: 0x00000000
225 22:14:58.009618 output: Entry Point: 0x00000000
226 22:14:58.009677 output: Hash algo: crc32
227 22:14:58.009732 output: Hash value: c242daf7
228 22:14:58.009785 output: Image 1 (fdt-1)
229 22:14:58.009837 output: Description: mt8192-asurada-spherion-r0
230 22:14:58.009890 output: Created: Mon Jun 5 23:14:57 2023
231 22:14:58.009943 output: Type: Flat Device Tree
232 22:14:58.009996 output: Compression: uncompressed
233 22:14:58.010048 output: Data Size: 46924 Bytes = 45.82 KiB = 0.04 MiB
234 22:14:58.010100 output: Architecture: AArch64
235 22:14:58.010152 output: Hash algo: crc32
236 22:14:58.010205 output: Hash value: 1df858fa
237 22:14:58.010257 output: Image 2 (ramdisk-1)
238 22:14:58.010308 output: Description: unavailable
239 22:14:58.010360 output: Created: Mon Jun 5 23:14:57 2023
240 22:14:58.010413 output: Type: RAMDisk Image
241 22:14:58.010465 output: Compression: Unknown Compression
242 22:14:58.010517 output: Data Size: 98142370 Bytes = 95842.16 KiB = 93.60 MiB
243 22:14:58.010569 output: Architecture: AArch64
244 22:14:58.010621 output: OS: Linux
245 22:14:58.010673 output: Load Address: unavailable
246 22:14:58.010725 output: Entry Point: unavailable
247 22:14:58.010777 output: Hash algo: crc32
248 22:14:58.010829 output: Hash value: e9e1b497
249 22:14:58.010881 output: Default Configuration: 'conf-1'
250 22:14:58.010933 output: Configuration 0 (conf-1)
251 22:14:58.010984 output: Description: mt8192-asurada-spherion-r0
252 22:14:58.011036 output: Kernel: kernel-1
253 22:14:58.011089 output: Init Ramdisk: ramdisk-1
254 22:14:58.011141 output: FDT: fdt-1
255 22:14:58.011192 output: Loadables: kernel-1
256 22:14:58.011243 output:
257 22:14:58.011480 end: 1.5.8.1 prepare-fit (duration 00:00:13) [common]
258 22:14:58.011579 end: 1.5.8 prepare-kernel (duration 00:00:13) [common]
259 22:14:58.011687 end: 1.5 prepare-tftp-overlay (duration 00:00:28) [common]
260 22:14:58.011785 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:31) [common]
261 22:14:58.011869 No LXC device requested
262 22:14:58.011947 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
263 22:14:58.012033 start: 1.7 deploy-device-env (timeout 00:09:31) [common]
264 22:14:58.012109 end: 1.7 deploy-device-env (duration 00:00:00) [common]
265 22:14:58.012177 Checking files for TFTP limit of 4294967296 bytes.
266 22:14:58.012770 end: 1 tftp-deploy (duration 00:00:29) [common]
267 22:14:58.012877 start: 2 depthcharge-action (timeout 00:05:00) [common]
268 22:14:58.012968 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
269 22:14:58.013124 substitutions:
270 22:14:58.013209 - {DTB}: 10597240/tftp-deploy-g8u9ngxh/dtb/mt8192-asurada-spherion-r0.dtb
271 22:14:58.013286 - {INITRD}: 10597240/tftp-deploy-g8u9ngxh/ramdisk/ramdisk.cpio.gz
272 22:14:58.013345 - {KERNEL}: 10597240/tftp-deploy-g8u9ngxh/kernel/Image
273 22:14:58.013401 - {LAVA_MAC}: None
274 22:14:58.013455 - {PRESEED_CONFIG}: None
275 22:14:58.013509 - {PRESEED_LOCAL}: None
276 22:14:58.013562 - {RAMDISK}: 10597240/tftp-deploy-g8u9ngxh/ramdisk/ramdisk.cpio.gz
277 22:14:58.013615 - {ROOT_PART}: None
278 22:14:58.013669 - {ROOT}: None
279 22:14:58.013723 - {SERVER_IP}: 192.168.201.1
280 22:14:58.013777 - {TEE}: None
281 22:14:58.013830 Parsed boot commands:
282 22:14:58.013883 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
283 22:14:58.014079 Parsed boot commands: tftpboot 192.168.201.1 10597240/tftp-deploy-g8u9ngxh/kernel/image.itb 10597240/tftp-deploy-g8u9ngxh/kernel/cmdline
284 22:14:58.014167 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
285 22:14:58.014251 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
286 22:14:58.014345 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
287 22:14:58.014429 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
288 22:14:58.014498 Not connected, no need to disconnect.
289 22:14:58.014572 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
290 22:14:58.014652 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
291 22:14:58.014724 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost mt8192-asurada-spherion-r0-cbg-0'
292 22:14:58.018181 Setting prompt string to ['lava-test: # ']
293 22:14:58.018512 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
294 22:14:58.018616 end: 2.2.1 reset-connection (duration 00:00:00) [common]
295 22:14:58.018716 start: 2.2.2 reset-device (timeout 00:05:00) [common]
296 22:14:58.018808 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
297 22:14:58.019095 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=reboot'
298 22:15:03.154169 >> Command sent successfully.
299 22:15:03.156523 Returned 0 in 5 seconds
300 22:15:03.256888 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
302 22:15:03.257224 end: 2.2.2 reset-device (duration 00:00:05) [common]
303 22:15:03.257331 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
304 22:15:03.257429 Setting prompt string to 'Starting depthcharge on Spherion...'
305 22:15:03.257506 Changing prompt to 'Starting depthcharge on Spherion...'
306 22:15:03.257577 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
307 22:15:03.257848 [Enter `^Ec?' for help]
308 22:15:03.429861
309 22:15:03.430005
310 22:15:03.430073 F0: 102B 0000
311 22:15:03.430137
312 22:15:03.430200 F3: 1001 0000 [0200]
313 22:15:03.430260
314 22:15:03.432833 F3: 1001 0000
315 22:15:03.432905
316 22:15:03.432965 F7: 102D 0000
317 22:15:03.433023
318 22:15:03.436419 F1: 0000 0000
319 22:15:03.436487
320 22:15:03.436547 V0: 0000 0000 [0001]
321 22:15:03.436606
322 22:15:03.439900 00: 0007 8000
323 22:15:03.439988
324 22:15:03.440055 01: 0000 0000
325 22:15:03.440118
326 22:15:03.443220 BP: 0C00 0209 [0000]
327 22:15:03.443321
328 22:15:03.443413 G0: 1182 0000
329 22:15:03.443476
330 22:15:03.447317 EC: 0000 0021 [4000]
331 22:15:03.447444
332 22:15:03.447511 S7: 0000 0000 [0000]
333 22:15:03.447573
334 22:15:03.447632 CC: 0000 0000 [0001]
335 22:15:03.450120
336 22:15:03.450204 T0: 0000 0040 [010F]
337 22:15:03.450272
338 22:15:03.450334 Jump to BL
339 22:15:03.450394
340 22:15:03.476792
341 22:15:03.476878
342 22:15:03.476944
343 22:15:03.484096 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
344 22:15:03.487478 ARM64: Exception handlers installed.
345 22:15:03.491457 ARM64: Testing exception
346 22:15:03.494713 ARM64: Done test exception
347 22:15:03.501341 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
348 22:15:03.511358 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
349 22:15:03.518638 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
350 22:15:03.528455 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
351 22:15:03.535154 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
352 22:15:03.541850 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
353 22:15:03.553482 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
354 22:15:03.560120 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
355 22:15:03.579238 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
356 22:15:03.582629 WDT: Last reset was cold boot
357 22:15:03.586346 SPI1(PAD0) initialized at 2873684 Hz
358 22:15:03.589729 SPI5(PAD0) initialized at 992727 Hz
359 22:15:03.592753 VBOOT: Loading verstage.
360 22:15:03.599553 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
361 22:15:03.602889 FMAP: Found "FLASH" version 1.1 at 0x20000.
362 22:15:03.606067 FMAP: base = 0x0 size = 0x800000 #areas = 25
363 22:15:03.609752 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
364 22:15:03.616722 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
365 22:15:03.623824 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
366 22:15:03.634300 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
367 22:15:03.634412
368 22:15:03.634482
369 22:15:03.645334 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
370 22:15:03.648604 ARM64: Exception handlers installed.
371 22:15:03.648685 ARM64: Testing exception
372 22:15:03.651721 ARM64: Done test exception
373 22:15:03.655320 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
374 22:15:03.662067 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
375 22:15:03.675510 Probing TPM: . done!
376 22:15:03.675618 TPM ready after 0 ms
377 22:15:03.683257 Connected to device vid:did:rid of 1ae0:0028:00
378 22:15:03.689793 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.153/cr50_v3.94_pp.113-620c9b9523
379 22:15:03.749601 Initialized TPM device CR50 revision 0
380 22:15:03.762001 tlcl_send_startup: Startup return code is 0
381 22:15:03.762118 TPM: setup succeeded
382 22:15:03.773049 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
383 22:15:03.781913 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
384 22:15:03.794445 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
385 22:15:03.804368 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
386 22:15:03.808164 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
387 22:15:03.812096 in-header: 03 07 00 00 08 00 00 00
388 22:15:03.815485 in-data: aa e4 47 04 13 02 00 00
389 22:15:03.815569 Chrome EC: UHEPI supported
390 22:15:03.823024 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
391 22:15:03.827190 in-header: 03 95 00 00 08 00 00 00
392 22:15:03.830673 in-data: 18 20 20 08 00 00 00 00
393 22:15:03.834547 Phase 1
394 22:15:03.838120 FMAP: area GBB found @ 3f5000 (12032 bytes)
395 22:15:03.841503 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
396 22:15:03.849172 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
397 22:15:03.852696 Recovery requested (1009000e)
398 22:15:03.859974 TPM: Extending digest for VBOOT: boot mode into PCR 0
399 22:15:03.865649 tlcl_extend: response is 0
400 22:15:03.875088 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
401 22:15:03.881036 tlcl_extend: response is 0
402 22:15:03.887847 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
403 22:15:03.906884 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
404 22:15:03.913796 BS: bootblock times (exec / console): total (unknown) / 148 ms
405 22:15:03.913890
406 22:15:03.913956
407 22:15:03.923630 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
408 22:15:03.927240 ARM64: Exception handlers installed.
409 22:15:03.930757 ARM64: Testing exception
410 22:15:03.930871 ARM64: Done test exception
411 22:15:03.953135 pmic_efuse_setting: Set efuses in 11 msecs
412 22:15:03.955988 pmwrap_interface_init: Select PMIF_VLD_RDY
413 22:15:03.963087 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
414 22:15:03.966292 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
415 22:15:03.970214 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
416 22:15:03.977433 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
417 22:15:03.981096 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
418 22:15:03.985139 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
419 22:15:03.992156 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
420 22:15:03.996026 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
421 22:15:03.999771 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
422 22:15:04.003247 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
423 22:15:04.011094 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
424 22:15:04.015287 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
425 22:15:04.018416 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
426 22:15:04.026409 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
427 22:15:04.030178 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
428 22:15:04.037315 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
429 22:15:04.040789 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
430 22:15:04.048810 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
431 22:15:04.052454 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
432 22:15:04.059298 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
433 22:15:04.063569 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
434 22:15:04.070790 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
435 22:15:04.077880 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
436 22:15:04.081545 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
437 22:15:04.085577 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
438 22:15:04.093491 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
439 22:15:04.096968 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
440 22:15:04.100287 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
441 22:15:04.107879 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
442 22:15:04.111638 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
443 22:15:04.115304 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
444 22:15:04.123239 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
445 22:15:04.126727 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
446 22:15:04.130578 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
447 22:15:04.137719 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
448 22:15:04.141549 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
449 22:15:04.145320 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
450 22:15:04.153120 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
451 22:15:04.156624 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
452 22:15:04.160827 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
453 22:15:04.164231 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
454 22:15:04.168056 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
455 22:15:04.175321 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
456 22:15:04.178908 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
457 22:15:04.183010 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
458 22:15:04.186588 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
459 22:15:04.190178 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
460 22:15:04.193691 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
461 22:15:04.201547 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
462 22:15:04.205082 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
463 22:15:04.208671 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
464 22:15:04.216014 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
465 22:15:04.223732 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
466 22:15:04.227107 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
467 22:15:04.238464 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
468 22:15:04.246024 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
469 22:15:04.250249 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
470 22:15:04.253790 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
471 22:15:04.257260 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
472 22:15:04.266297 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x0
473 22:15:04.270008 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
474 22:15:04.275092 [RTC]rtc_osc_init,62: osc32con val = 0xde70
475 22:15:04.281708 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
476 22:15:04.290297 [RTC]rtc_get_frequency_meter,154: input=15, output=758
477 22:15:04.300020 [RTC]rtc_get_frequency_meter,154: input=23, output=940
478 22:15:04.309674 [RTC]rtc_get_frequency_meter,154: input=19, output=850
479 22:15:04.318852 [RTC]rtc_get_frequency_meter,154: input=17, output=805
480 22:15:04.328475 [RTC]rtc_get_frequency_meter,154: input=16, output=782
481 22:15:04.338349 [RTC]rtc_get_frequency_meter,154: input=16, output=782
482 22:15:04.347886 [RTC]rtc_get_frequency_meter,154: input=17, output=805
483 22:15:04.351890 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
484 22:15:04.355650 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
485 22:15:04.359121 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
486 22:15:04.366592 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
487 22:15:04.370314 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
488 22:15:04.373837 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
489 22:15:04.377802 ADC[4]: Raw value=906573 ID=7
490 22:15:04.377887 ADC[3]: Raw value=213810 ID=1
491 22:15:04.381019 RAM Code: 0x71
492 22:15:04.385259 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
493 22:15:04.388688 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
494 22:15:04.400249 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
495 22:15:04.403893 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
496 22:15:04.407967 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
497 22:15:04.411741 in-header: 03 07 00 00 08 00 00 00
498 22:15:04.415627 in-data: aa e4 47 04 13 02 00 00
499 22:15:04.419097 Chrome EC: UHEPI supported
500 22:15:04.422845 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
501 22:15:04.426718 in-header: 03 95 00 00 08 00 00 00
502 22:15:04.430172 in-data: 18 20 20 08 00 00 00 00
503 22:15:04.434181 MRC: failed to locate region type 0.
504 22:15:04.441743 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
505 22:15:04.444907 DRAM-K: Running full calibration
506 22:15:04.448595 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
507 22:15:04.452556 header.status = 0x0
508 22:15:04.456677 header.version = 0x6 (expected: 0x6)
509 22:15:04.460113 header.size = 0xd00 (expected: 0xd00)
510 22:15:04.460218 header.flags = 0x0
511 22:15:04.467633 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
512 22:15:04.485293 read SPI 0x72590 0x1c583: 12497 us, 9290 KB/s, 74.320 Mbps
513 22:15:04.492604 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
514 22:15:04.492690 dram_init: ddr_geometry: 2
515 22:15:04.496132 [EMI] MDL number = 2
516 22:15:04.499680 [EMI] Get MDL freq = 0
517 22:15:04.499762 dram_init: ddr_type: 0
518 22:15:04.503881 is_discrete_lpddr4: 1
519 22:15:04.503964 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
520 22:15:04.504029
521 22:15:04.507653
522 22:15:04.507735 [Bian_co] ETT version 0.0.0.1
523 22:15:04.515158 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
524 22:15:04.515244
525 22:15:04.518382 dramc_set_vcore_voltage set vcore to 650000
526 22:15:04.518465 Read voltage for 800, 4
527 22:15:04.518531 Vio18 = 0
528 22:15:04.522611 Vcore = 650000
529 22:15:04.522693 Vdram = 0
530 22:15:04.522759 Vddq = 0
531 22:15:04.525879 Vmddr = 0
532 22:15:04.525962 dram_init: config_dvfs: 1
533 22:15:04.529878 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
534 22:15:04.536951 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
535 22:15:04.540734 [SwImpedanceCal] DRVP=10, DRVN=16, ODTN=9
536 22:15:04.544984 freq_region=0, Reg: DRVP=10, DRVN=16, ODTN=9
537 22:15:04.548297 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
538 22:15:04.552373 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
539 22:15:04.555816 MEM_TYPE=3, freq_sel=18
540 22:15:04.555899 sv_algorithm_assistance_LP4_1600
541 22:15:04.562603 ============ PULL DRAM RESETB DOWN ============
542 22:15:04.566114 ========== PULL DRAM RESETB DOWN end =========
543 22:15:04.569206 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
544 22:15:04.572753 ===================================
545 22:15:04.576574 LPDDR4 DRAM CONFIGURATION
546 22:15:04.579781 ===================================
547 22:15:04.579867 EX_ROW_EN[0] = 0x0
548 22:15:04.583806 EX_ROW_EN[1] = 0x0
549 22:15:04.583892 LP4Y_EN = 0x0
550 22:15:04.587239 WORK_FSP = 0x0
551 22:15:04.587332 WL = 0x2
552 22:15:04.591289 RL = 0x2
553 22:15:04.591398 BL = 0x2
554 22:15:04.595142 RPST = 0x0
555 22:15:04.595227 RD_PRE = 0x0
556 22:15:04.598051 WR_PRE = 0x1
557 22:15:04.598137 WR_PST = 0x0
558 22:15:04.601666 DBI_WR = 0x0
559 22:15:04.601752 DBI_RD = 0x0
560 22:15:04.605018 OTF = 0x1
561 22:15:04.608644 ===================================
562 22:15:04.611675 ===================================
563 22:15:04.611762 ANA top config
564 22:15:04.614706 ===================================
565 22:15:04.618281 DLL_ASYNC_EN = 0
566 22:15:04.621777 ALL_SLAVE_EN = 1
567 22:15:04.621863 NEW_RANK_MODE = 1
568 22:15:04.625156 DLL_IDLE_MODE = 1
569 22:15:04.628831 LP45_APHY_COMB_EN = 1
570 22:15:04.631559 TX_ODT_DIS = 1
571 22:15:04.631672 NEW_8X_MODE = 1
572 22:15:04.635127 ===================================
573 22:15:04.638751 ===================================
574 22:15:04.642376 data_rate = 1600
575 22:15:04.645761 CKR = 1
576 22:15:04.649190 DQ_P2S_RATIO = 8
577 22:15:04.652315 ===================================
578 22:15:04.655911 CA_P2S_RATIO = 8
579 22:15:04.655994 DQ_CA_OPEN = 0
580 22:15:04.659268 DQ_SEMI_OPEN = 0
581 22:15:04.662077 CA_SEMI_OPEN = 0
582 22:15:04.665477 CA_FULL_RATE = 0
583 22:15:04.668816 DQ_CKDIV4_EN = 1
584 22:15:04.672177 CA_CKDIV4_EN = 1
585 22:15:04.672280 CA_PREDIV_EN = 0
586 22:15:04.676051 PH8_DLY = 0
587 22:15:04.679571 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
588 22:15:04.682910 DQ_AAMCK_DIV = 4
589 22:15:04.685801 CA_AAMCK_DIV = 4
590 22:15:04.685878 CA_ADMCK_DIV = 4
591 22:15:04.689016 DQ_TRACK_CA_EN = 0
592 22:15:04.692398 CA_PICK = 800
593 22:15:04.696532 CA_MCKIO = 800
594 22:15:04.699799 MCKIO_SEMI = 0
595 22:15:04.703779 PLL_FREQ = 3068
596 22:15:04.703892 DQ_UI_PI_RATIO = 32
597 22:15:04.707482 CA_UI_PI_RATIO = 0
598 22:15:04.711192 ===================================
599 22:15:04.714974 ===================================
600 22:15:04.715081 memory_type:LPDDR4
601 22:15:04.718530 GP_NUM : 10
602 22:15:04.722091 SRAM_EN : 1
603 22:15:04.722200 MD32_EN : 0
604 22:15:04.726113 ===================================
605 22:15:04.730154 [ANA_INIT] >>>>>>>>>>>>>>
606 22:15:04.730267 <<<<<< [CONFIGURE PHASE]: ANA_TX
607 22:15:04.733293 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
608 22:15:04.737165 ===================================
609 22:15:04.740121 data_rate = 1600,PCW = 0X7600
610 22:15:04.743506 ===================================
611 22:15:04.746755 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
612 22:15:04.753658 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
613 22:15:04.756840 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
614 22:15:04.763667 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
615 22:15:04.766570 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
616 22:15:04.770414 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
617 22:15:04.770499 [ANA_INIT] flow start
618 22:15:04.773506 [ANA_INIT] PLL >>>>>>>>
619 22:15:04.776584 [ANA_INIT] PLL <<<<<<<<
620 22:15:04.780342 [ANA_INIT] MIDPI >>>>>>>>
621 22:15:04.780427 [ANA_INIT] MIDPI <<<<<<<<
622 22:15:04.783567 [ANA_INIT] DLL >>>>>>>>
623 22:15:04.783646 [ANA_INIT] flow end
624 22:15:04.790053 ============ LP4 DIFF to SE enter ============
625 22:15:04.793739 ============ LP4 DIFF to SE exit ============
626 22:15:04.797109 [ANA_INIT] <<<<<<<<<<<<<
627 22:15:04.800029 [Flow] Enable top DCM control >>>>>
628 22:15:04.803487 [Flow] Enable top DCM control <<<<<
629 22:15:04.803592 Enable DLL master slave shuffle
630 22:15:04.810236 ==============================================================
631 22:15:04.813326 Gating Mode config
632 22:15:04.816824 ==============================================================
633 22:15:04.820509 Config description:
634 22:15:04.830675 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
635 22:15:04.836963 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
636 22:15:04.840665 SELPH_MODE 0: By rank 1: By Phase
637 22:15:04.847023 ==============================================================
638 22:15:04.850070 GAT_TRACK_EN = 1
639 22:15:04.853688 RX_GATING_MODE = 2
640 22:15:04.857083 RX_GATING_TRACK_MODE = 2
641 22:15:04.860292 SELPH_MODE = 1
642 22:15:04.860397 PICG_EARLY_EN = 1
643 22:15:04.863655 VALID_LAT_VALUE = 1
644 22:15:04.870171 ==============================================================
645 22:15:04.873767 Enter into Gating configuration >>>>
646 22:15:04.877142 Exit from Gating configuration <<<<
647 22:15:04.879989 Enter into DVFS_PRE_config >>>>>
648 22:15:04.890765 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
649 22:15:04.893630 Exit from DVFS_PRE_config <<<<<
650 22:15:04.896840 Enter into PICG configuration >>>>
651 22:15:04.900265 Exit from PICG configuration <<<<
652 22:15:04.904086 [RX_INPUT] configuration >>>>>
653 22:15:04.907005 [RX_INPUT] configuration <<<<<
654 22:15:04.910834 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
655 22:15:04.917079 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
656 22:15:04.923807 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
657 22:15:04.927453 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
658 22:15:04.933722 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
659 22:15:04.940628 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
660 22:15:04.944413 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
661 22:15:04.950885 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
662 22:15:04.953832 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
663 22:15:04.957323 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
664 22:15:04.960931 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
665 22:15:04.966953 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
666 22:15:04.970366 ===================================
667 22:15:04.970467 LPDDR4 DRAM CONFIGURATION
668 22:15:04.973608 ===================================
669 22:15:04.977464 EX_ROW_EN[0] = 0x0
670 22:15:04.980874 EX_ROW_EN[1] = 0x0
671 22:15:04.980973 LP4Y_EN = 0x0
672 22:15:04.983648 WORK_FSP = 0x0
673 22:15:04.983746 WL = 0x2
674 22:15:04.987485 RL = 0x2
675 22:15:04.987559 BL = 0x2
676 22:15:04.991164 RPST = 0x0
677 22:15:04.991263 RD_PRE = 0x0
678 22:15:04.994265 WR_PRE = 0x1
679 22:15:04.994335 WR_PST = 0x0
680 22:15:04.997221 DBI_WR = 0x0
681 22:15:04.997306 DBI_RD = 0x0
682 22:15:05.001099 OTF = 0x1
683 22:15:05.004172 ===================================
684 22:15:05.007124 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
685 22:15:05.010706 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
686 22:15:05.017217 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
687 22:15:05.017335 ===================================
688 22:15:05.020588 LPDDR4 DRAM CONFIGURATION
689 22:15:05.023955 ===================================
690 22:15:05.027484 EX_ROW_EN[0] = 0x10
691 22:15:05.027569 EX_ROW_EN[1] = 0x0
692 22:15:05.030923 LP4Y_EN = 0x0
693 22:15:05.031023 WORK_FSP = 0x0
694 22:15:05.034079 WL = 0x2
695 22:15:05.034178 RL = 0x2
696 22:15:05.037077 BL = 0x2
697 22:15:05.037151 RPST = 0x0
698 22:15:05.040502 RD_PRE = 0x0
699 22:15:05.043896 WR_PRE = 0x1
700 22:15:05.043971 WR_PST = 0x0
701 22:15:05.047496 DBI_WR = 0x0
702 22:15:05.047602 DBI_RD = 0x0
703 22:15:05.050585 OTF = 0x1
704 22:15:05.053951 ===================================
705 22:15:05.057528 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
706 22:15:05.062343 nWR fixed to 40
707 22:15:05.065699 [ModeRegInit_LP4] CH0 RK0
708 22:15:05.065773 [ModeRegInit_LP4] CH0 RK1
709 22:15:05.069476 [ModeRegInit_LP4] CH1 RK0
710 22:15:05.072491 [ModeRegInit_LP4] CH1 RK1
711 22:15:05.072597 match AC timing 13
712 22:15:05.079594 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
713 22:15:05.082444 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
714 22:15:05.086132 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
715 22:15:05.092637 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
716 22:15:05.095970 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
717 22:15:05.096054 [EMI DOE] emi_dcm 0
718 22:15:05.102937 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
719 22:15:05.103021 ==
720 22:15:05.106400 Dram Type= 6, Freq= 0, CH_0, rank 0
721 22:15:05.109418 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
722 22:15:05.109507 ==
723 22:15:05.116187 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
724 22:15:05.119874 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
725 22:15:05.130362 [CA 0] Center 36 (6~67) winsize 62
726 22:15:05.133170 [CA 1] Center 36 (6~67) winsize 62
727 22:15:05.136508 [CA 2] Center 34 (4~65) winsize 62
728 22:15:05.140148 [CA 3] Center 33 (3~64) winsize 62
729 22:15:05.142968 [CA 4] Center 33 (3~64) winsize 62
730 22:15:05.146419 [CA 5] Center 32 (3~62) winsize 60
731 22:15:05.146503
732 22:15:05.149788 [CmdBusTrainingLP45] Vref(ca) range 1: 34
733 22:15:05.149873
734 22:15:05.153271 [CATrainingPosCal] consider 1 rank data
735 22:15:05.156999 u2DelayCellTimex100 = 270/100 ps
736 22:15:05.160117 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
737 22:15:05.163503 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
738 22:15:05.170564 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
739 22:15:05.173464 CA3 delay=33 (3~64),Diff = 1 PI (7 cell)
740 22:15:05.177032 CA4 delay=33 (3~64),Diff = 1 PI (7 cell)
741 22:15:05.180450 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
742 22:15:05.180527
743 22:15:05.183463 CA PerBit enable=1, Macro0, CA PI delay=32
744 22:15:05.183542
745 22:15:05.186998 [CBTSetCACLKResult] CA Dly = 32
746 22:15:05.187098 CS Dly: 5 (0~36)
747 22:15:05.187196 ==
748 22:15:05.190338 Dram Type= 6, Freq= 0, CH_0, rank 1
749 22:15:05.196758 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
750 22:15:05.196835 ==
751 22:15:05.200444 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
752 22:15:05.206485 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
753 22:15:05.215952 [CA 0] Center 36 (6~67) winsize 62
754 22:15:05.219511 [CA 1] Center 36 (6~67) winsize 62
755 22:15:05.222839 [CA 2] Center 34 (4~65) winsize 62
756 22:15:05.225921 [CA 3] Center 33 (3~64) winsize 62
757 22:15:05.229521 [CA 4] Center 33 (3~63) winsize 61
758 22:15:05.232518 [CA 5] Center 32 (2~63) winsize 62
759 22:15:05.232593
760 22:15:05.236589 [CmdBusTrainingLP45] Vref(ca) range 1: 32
761 22:15:05.236669
762 22:15:05.239277 [CATrainingPosCal] consider 2 rank data
763 22:15:05.243153 u2DelayCellTimex100 = 270/100 ps
764 22:15:05.246236 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
765 22:15:05.249730 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
766 22:15:05.256086 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
767 22:15:05.259301 CA3 delay=33 (3~64),Diff = 1 PI (7 cell)
768 22:15:05.262697 CA4 delay=33 (3~63),Diff = 1 PI (7 cell)
769 22:15:05.266401 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
770 22:15:05.266506
771 22:15:05.269838 CA PerBit enable=1, Macro0, CA PI delay=32
772 22:15:05.269943
773 22:15:05.272895 [CBTSetCACLKResult] CA Dly = 32
774 22:15:05.272977 CS Dly: 5 (0~36)
775 22:15:05.273038
776 22:15:05.276444 ----->DramcWriteLeveling(PI) begin...
777 22:15:05.276520 ==
778 22:15:05.280024 Dram Type= 6, Freq= 0, CH_0, rank 0
779 22:15:05.284354 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
780 22:15:05.284438 ==
781 22:15:05.287540 Write leveling (Byte 0): 34 => 34
782 22:15:05.291200 Write leveling (Byte 1): 29 => 29
783 22:15:05.294678 DramcWriteLeveling(PI) end<-----
784 22:15:05.294756
785 22:15:05.294820 ==
786 22:15:05.298443 Dram Type= 6, Freq= 0, CH_0, rank 0
787 22:15:05.301721 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
788 22:15:05.301827 ==
789 22:15:05.305556 [Gating] SW mode calibration
790 22:15:05.312658 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
791 22:15:05.319431 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
792 22:15:05.322318 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
793 22:15:05.325705 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
794 22:15:05.329276 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
795 22:15:05.335997 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 22:15:05.339127 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 22:15:05.342483 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 22:15:05.348959 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 22:15:05.352406 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 22:15:05.355645 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 22:15:05.362570 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 22:15:05.366192 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 22:15:05.369261 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
804 22:15:05.375687 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 22:15:05.379222 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 22:15:05.382563 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 22:15:05.389344 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 22:15:05.392844 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 22:15:05.396044 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
810 22:15:05.402641 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
811 22:15:05.406214 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
812 22:15:05.409857 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
813 22:15:05.412606 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
814 22:15:05.419679 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
815 22:15:05.423094 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
816 22:15:05.426457 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
817 22:15:05.432735 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
818 22:15:05.436059 0 9 8 | B1->B0 | 2323 2f2e | 0 1 | (1 1) (1 1)
819 22:15:05.439544 0 9 12 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
820 22:15:05.445988 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
821 22:15:05.449393 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
822 22:15:05.452605 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
823 22:15:05.459735 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
824 22:15:05.462496 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
825 22:15:05.466370 0 10 4 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
826 22:15:05.472821 0 10 8 | B1->B0 | 3030 2525 | 1 0 | (1 0) (1 0)
827 22:15:05.476244 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
828 22:15:05.479321 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
829 22:15:05.485985 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
830 22:15:05.489731 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
831 22:15:05.492768 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
832 22:15:05.496360 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
833 22:15:05.502987 0 11 4 | B1->B0 | 2323 2727 | 0 1 | (0 0) (0 0)
834 22:15:05.506278 0 11 8 | B1->B0 | 2c2c 4444 | 0 0 | (0 0) (0 0)
835 22:15:05.509247 0 11 12 | B1->B0 | 4141 4646 | 1 0 | (0 0) (0 0)
836 22:15:05.516114 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
837 22:15:05.519982 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
838 22:15:05.522770 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
839 22:15:05.529589 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
840 22:15:05.532951 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
841 22:15:05.536119 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
842 22:15:05.542669 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
843 22:15:05.546072 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 22:15:05.549357 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 22:15:05.556501 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 22:15:05.559478 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 22:15:05.563201 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 22:15:05.569618 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 22:15:05.573288 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 22:15:05.576281 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 22:15:05.579759 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
852 22:15:05.586325 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
853 22:15:05.589926 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
854 22:15:05.592962 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
855 22:15:05.599538 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
856 22:15:05.603202 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
857 22:15:05.607317 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
858 22:15:05.613169 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
859 22:15:05.613254 Total UI for P1: 0, mck2ui 16
860 22:15:05.619937 best dqsien dly found for B0: ( 0, 14, 4)
861 22:15:05.623507 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
862 22:15:05.626769 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
863 22:15:05.630675 Total UI for P1: 0, mck2ui 16
864 22:15:05.634530 best dqsien dly found for B1: ( 0, 14, 10)
865 22:15:05.638042 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
866 22:15:05.641071 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
867 22:15:05.641154
868 22:15:05.644138 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
869 22:15:05.647818 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
870 22:15:05.651095 [Gating] SW calibration Done
871 22:15:05.651178 ==
872 22:15:05.654278 Dram Type= 6, Freq= 0, CH_0, rank 0
873 22:15:05.657878 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
874 22:15:05.657962 ==
875 22:15:05.661371 RX Vref Scan: 0
876 22:15:05.661454
877 22:15:05.664433 RX Vref 0 -> 0, step: 1
878 22:15:05.664516
879 22:15:05.664581 RX Delay -130 -> 252, step: 16
880 22:15:05.671007 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
881 22:15:05.674548 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
882 22:15:05.677428 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
883 22:15:05.681151 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
884 22:15:05.684487 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
885 22:15:05.691252 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
886 22:15:05.694119 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
887 22:15:05.697941 iDelay=222, Bit 7, Center 109 (-2 ~ 221) 224
888 22:15:05.700830 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
889 22:15:05.704469 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
890 22:15:05.710900 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
891 22:15:05.714693 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
892 22:15:05.717834 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
893 22:15:05.721028 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
894 22:15:05.724489 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
895 22:15:05.731095 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
896 22:15:05.731179 ==
897 22:15:05.734088 Dram Type= 6, Freq= 0, CH_0, rank 0
898 22:15:05.737729 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
899 22:15:05.737814 ==
900 22:15:05.737879 DQS Delay:
901 22:15:05.740817 DQS0 = 0, DQS1 = 0
902 22:15:05.740901 DQM Delay:
903 22:15:05.743951 DQM0 = 92, DQM1 = 82
904 22:15:05.744034 DQ Delay:
905 22:15:05.747524 DQ0 =93, DQ1 =93, DQ2 =85, DQ3 =85
906 22:15:05.750961 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =109
907 22:15:05.753951 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
908 22:15:05.757447 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
909 22:15:05.757531
910 22:15:05.757596
911 22:15:05.757656 ==
912 22:15:05.760872 Dram Type= 6, Freq= 0, CH_0, rank 0
913 22:15:05.764166 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
914 22:15:05.767561 ==
915 22:15:05.767644
916 22:15:05.767709
917 22:15:05.767770 TX Vref Scan disable
918 22:15:05.770806 == TX Byte 0 ==
919 22:15:05.774061 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
920 22:15:05.777440 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
921 22:15:05.780830 == TX Byte 1 ==
922 22:15:05.784416 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
923 22:15:05.787410 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
924 22:15:05.787522 ==
925 22:15:05.790778 Dram Type= 6, Freq= 0, CH_0, rank 0
926 22:15:05.797306 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
927 22:15:05.797390 ==
928 22:15:05.810115 TX Vref=22, minBit 8, minWin=27, winSum=447
929 22:15:05.813503 TX Vref=24, minBit 8, minWin=27, winSum=448
930 22:15:05.817119 TX Vref=26, minBit 10, minWin=27, winSum=457
931 22:15:05.820232 TX Vref=28, minBit 8, minWin=28, winSum=456
932 22:15:05.823788 TX Vref=30, minBit 4, minWin=28, winSum=456
933 22:15:05.826894 TX Vref=32, minBit 2, minWin=28, winSum=454
934 22:15:05.833479 [TxChooseVref] Worse bit 8, Min win 28, Win sum 456, Final Vref 28
935 22:15:05.833563
936 22:15:05.836944 Final TX Range 1 Vref 28
937 22:15:05.837045
938 22:15:05.837126 ==
939 22:15:05.840576 Dram Type= 6, Freq= 0, CH_0, rank 0
940 22:15:05.844021 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
941 22:15:05.844110 ==
942 22:15:05.844175
943 22:15:05.844235
944 22:15:05.846941 TX Vref Scan disable
945 22:15:05.850240 == TX Byte 0 ==
946 22:15:05.853483 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
947 22:15:05.857212 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
948 22:15:05.860625 == TX Byte 1 ==
949 22:15:05.863618 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
950 22:15:05.866795 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
951 22:15:05.870350
952 22:15:05.870427 [DATLAT]
953 22:15:05.870527 Freq=800, CH0 RK0
954 22:15:05.870618
955 22:15:05.873595 DATLAT Default: 0xa
956 22:15:05.873702 0, 0xFFFF, sum = 0
957 22:15:05.876709 1, 0xFFFF, sum = 0
958 22:15:05.876818 2, 0xFFFF, sum = 0
959 22:15:05.880188 3, 0xFFFF, sum = 0
960 22:15:05.880268 4, 0xFFFF, sum = 0
961 22:15:05.883505 5, 0xFFFF, sum = 0
962 22:15:05.883579 6, 0xFFFF, sum = 0
963 22:15:05.886964 7, 0xFFFF, sum = 0
964 22:15:05.887073 8, 0xFFFF, sum = 0
965 22:15:05.890063 9, 0x0, sum = 1
966 22:15:05.890172 10, 0x0, sum = 2
967 22:15:05.893463 11, 0x0, sum = 3
968 22:15:05.893567 12, 0x0, sum = 4
969 22:15:05.896795 best_step = 10
970 22:15:05.896868
971 22:15:05.896951 ==
972 22:15:05.900047 Dram Type= 6, Freq= 0, CH_0, rank 0
973 22:15:05.903523 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
974 22:15:05.903596 ==
975 22:15:05.907250 RX Vref Scan: 1
976 22:15:05.907393
977 22:15:05.907485 Set Vref Range= 32 -> 127
978 22:15:05.907585
979 22:15:05.910198 RX Vref 32 -> 127, step: 1
980 22:15:05.910301
981 22:15:05.913714 RX Delay -95 -> 252, step: 8
982 22:15:05.913816
983 22:15:05.917193 Set Vref, RX VrefLevel [Byte0]: 32
984 22:15:05.920217 [Byte1]: 32
985 22:15:05.920315
986 22:15:05.923772 Set Vref, RX VrefLevel [Byte0]: 33
987 22:15:05.927393 [Byte1]: 33
988 22:15:05.930455
989 22:15:05.930551 Set Vref, RX VrefLevel [Byte0]: 34
990 22:15:05.933750 [Byte1]: 34
991 22:15:05.938270
992 22:15:05.938369 Set Vref, RX VrefLevel [Byte0]: 35
993 22:15:05.941379 [Byte1]: 35
994 22:15:05.945873
995 22:15:05.945956 Set Vref, RX VrefLevel [Byte0]: 36
996 22:15:05.949597 [Byte1]: 36
997 22:15:05.953753
998 22:15:05.953856 Set Vref, RX VrefLevel [Byte0]: 37
999 22:15:05.957153 [Byte1]: 37
1000 22:15:05.961220
1001 22:15:05.961328 Set Vref, RX VrefLevel [Byte0]: 38
1002 22:15:05.964772 [Byte1]: 38
1003 22:15:05.968996
1004 22:15:05.969098 Set Vref, RX VrefLevel [Byte0]: 39
1005 22:15:05.972259 [Byte1]: 39
1006 22:15:05.976614
1007 22:15:05.976714 Set Vref, RX VrefLevel [Byte0]: 40
1008 22:15:05.979963 [Byte1]: 40
1009 22:15:05.984114
1010 22:15:05.984196 Set Vref, RX VrefLevel [Byte0]: 41
1011 22:15:05.986786 [Byte1]: 41
1012 22:15:05.991261
1013 22:15:05.991384 Set Vref, RX VrefLevel [Byte0]: 42
1014 22:15:05.994298 [Byte1]: 42
1015 22:15:05.998492
1016 22:15:06.001995 Set Vref, RX VrefLevel [Byte0]: 43
1017 22:15:06.005080 [Byte1]: 43
1018 22:15:06.005180
1019 22:15:06.008570 Set Vref, RX VrefLevel [Byte0]: 44
1020 22:15:06.012126 [Byte1]: 44
1021 22:15:06.012230
1022 22:15:06.015383 Set Vref, RX VrefLevel [Byte0]: 45
1023 22:15:06.018739 [Byte1]: 45
1024 22:15:06.018840
1025 22:15:06.022275 Set Vref, RX VrefLevel [Byte0]: 46
1026 22:15:06.025207 [Byte1]: 46
1027 22:15:06.029052
1028 22:15:06.029154 Set Vref, RX VrefLevel [Byte0]: 47
1029 22:15:06.032837 [Byte1]: 47
1030 22:15:06.037010
1031 22:15:06.037116 Set Vref, RX VrefLevel [Byte0]: 48
1032 22:15:06.040421 [Byte1]: 48
1033 22:15:06.044607
1034 22:15:06.044682 Set Vref, RX VrefLevel [Byte0]: 49
1035 22:15:06.047581 [Byte1]: 49
1036 22:15:06.052029
1037 22:15:06.052104 Set Vref, RX VrefLevel [Byte0]: 50
1038 22:15:06.055577 [Byte1]: 50
1039 22:15:06.059920
1040 22:15:06.059997 Set Vref, RX VrefLevel [Byte0]: 51
1041 22:15:06.062972 [Byte1]: 51
1042 22:15:06.067115
1043 22:15:06.067189 Set Vref, RX VrefLevel [Byte0]: 52
1044 22:15:06.070763 [Byte1]: 52
1045 22:15:06.074933
1046 22:15:06.075001 Set Vref, RX VrefLevel [Byte0]: 53
1047 22:15:06.078343 [Byte1]: 53
1048 22:15:06.082572
1049 22:15:06.082673 Set Vref, RX VrefLevel [Byte0]: 54
1050 22:15:06.086010 [Byte1]: 54
1051 22:15:06.090002
1052 22:15:06.090105 Set Vref, RX VrefLevel [Byte0]: 55
1053 22:15:06.093212 [Byte1]: 55
1054 22:15:06.097590
1055 22:15:06.097686 Set Vref, RX VrefLevel [Byte0]: 56
1056 22:15:06.100999 [Byte1]: 56
1057 22:15:06.105372
1058 22:15:06.105473 Set Vref, RX VrefLevel [Byte0]: 57
1059 22:15:06.108415 [Byte1]: 57
1060 22:15:06.112944
1061 22:15:06.113057 Set Vref, RX VrefLevel [Byte0]: 58
1062 22:15:06.116032 [Byte1]: 58
1063 22:15:06.120521
1064 22:15:06.120621 Set Vref, RX VrefLevel [Byte0]: 59
1065 22:15:06.123954 [Byte1]: 59
1066 22:15:06.127747
1067 22:15:06.127823 Set Vref, RX VrefLevel [Byte0]: 60
1068 22:15:06.131252 [Byte1]: 60
1069 22:15:06.135452
1070 22:15:06.135550 Set Vref, RX VrefLevel [Byte0]: 61
1071 22:15:06.139122 [Byte1]: 61
1072 22:15:06.143464
1073 22:15:06.143545 Set Vref, RX VrefLevel [Byte0]: 62
1074 22:15:06.146952 [Byte1]: 62
1075 22:15:06.151142
1076 22:15:06.151238 Set Vref, RX VrefLevel [Byte0]: 63
1077 22:15:06.154023 [Byte1]: 63
1078 22:15:06.158564
1079 22:15:06.158634 Set Vref, RX VrefLevel [Byte0]: 64
1080 22:15:06.161669 [Byte1]: 64
1081 22:15:06.166241
1082 22:15:06.166327 Set Vref, RX VrefLevel [Byte0]: 65
1083 22:15:06.169357 [Byte1]: 65
1084 22:15:06.173814
1085 22:15:06.173896 Set Vref, RX VrefLevel [Byte0]: 66
1086 22:15:06.176987 [Byte1]: 66
1087 22:15:06.180995
1088 22:15:06.181077 Set Vref, RX VrefLevel [Byte0]: 67
1089 22:15:06.184757 [Byte1]: 67
1090 22:15:06.188712
1091 22:15:06.188794 Set Vref, RX VrefLevel [Byte0]: 68
1092 22:15:06.192207 [Byte1]: 68
1093 22:15:06.196481
1094 22:15:06.196562 Set Vref, RX VrefLevel [Byte0]: 69
1095 22:15:06.199876 [Byte1]: 69
1096 22:15:06.203752
1097 22:15:06.203834 Set Vref, RX VrefLevel [Byte0]: 70
1098 22:15:06.207300 [Byte1]: 70
1099 22:15:06.211413
1100 22:15:06.211522 Set Vref, RX VrefLevel [Byte0]: 71
1101 22:15:06.214868 [Byte1]: 71
1102 22:15:06.219207
1103 22:15:06.219289 Set Vref, RX VrefLevel [Byte0]: 72
1104 22:15:06.222970 [Byte1]: 72
1105 22:15:06.226569
1106 22:15:06.226650 Set Vref, RX VrefLevel [Byte0]: 73
1107 22:15:06.230041 [Byte1]: 73
1108 22:15:06.234223
1109 22:15:06.234304 Set Vref, RX VrefLevel [Byte0]: 74
1110 22:15:06.237664 [Byte1]: 74
1111 22:15:06.242084
1112 22:15:06.242168 Set Vref, RX VrefLevel [Byte0]: 75
1113 22:15:06.245569 [Byte1]: 75
1114 22:15:06.249442
1115 22:15:06.249524 Set Vref, RX VrefLevel [Byte0]: 76
1116 22:15:06.253241 [Byte1]: 76
1117 22:15:06.257288
1118 22:15:06.257370 Final RX Vref Byte 0 = 59 to rank0
1119 22:15:06.260793 Final RX Vref Byte 1 = 60 to rank0
1120 22:15:06.264103 Final RX Vref Byte 0 = 59 to rank1
1121 22:15:06.267575 Final RX Vref Byte 1 = 60 to rank1==
1122 22:15:06.271007 Dram Type= 6, Freq= 0, CH_0, rank 0
1123 22:15:06.274328 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1124 22:15:06.277242 ==
1125 22:15:06.277324 DQS Delay:
1126 22:15:06.277390 DQS0 = 0, DQS1 = 0
1127 22:15:06.280695 DQM Delay:
1128 22:15:06.280777 DQM0 = 91, DQM1 = 85
1129 22:15:06.284024 DQ Delay:
1130 22:15:06.284109 DQ0 =88, DQ1 =96, DQ2 =88, DQ3 =88
1131 22:15:06.287674 DQ4 =96, DQ5 =80, DQ6 =96, DQ7 =100
1132 22:15:06.291146 DQ8 =76, DQ9 =76, DQ10 =84, DQ11 =80
1133 22:15:06.294043 DQ12 =92, DQ13 =92, DQ14 =92, DQ15 =92
1134 22:15:06.297363
1135 22:15:06.297439
1136 22:15:06.304108 [DQSOSCAuto] RK0, (LSB)MR18= 0x4f45, (MSB)MR19= 0x606, tDQSOscB0 = 392 ps tDQSOscB1 = 390 ps
1137 22:15:06.307259 CH0 RK0: MR19=606, MR18=4F45
1138 22:15:06.313920 CH0_RK0: MR19=0x606, MR18=0x4F45, DQSOSC=390, MR23=63, INC=97, DEC=64
1139 22:15:06.314010
1140 22:15:06.317130 ----->DramcWriteLeveling(PI) begin...
1141 22:15:06.317209 ==
1142 22:15:06.320587 Dram Type= 6, Freq= 0, CH_0, rank 1
1143 22:15:06.324085 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1144 22:15:06.324170 ==
1145 22:15:06.327689 Write leveling (Byte 0): 33 => 33
1146 22:15:06.330654 Write leveling (Byte 1): 29 => 29
1147 22:15:06.334017 DramcWriteLeveling(PI) end<-----
1148 22:15:06.334102
1149 22:15:06.334186 ==
1150 22:15:06.337692 Dram Type= 6, Freq= 0, CH_0, rank 1
1151 22:15:06.340576 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1152 22:15:06.340662 ==
1153 22:15:06.344568 [Gating] SW mode calibration
1154 22:15:06.350776 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1155 22:15:06.367822 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1156 22:15:06.368305 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1157 22:15:06.368569 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1158 22:15:06.378000 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1159 22:15:06.378113 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 22:15:06.390210 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 22:15:06.390472 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 22:15:06.390542 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 22:15:06.400870 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 22:15:06.400953 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 22:15:06.401505 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 22:15:06.411252 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 22:15:06.411901 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 22:15:06.423188 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 22:15:06.423305 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 22:15:06.423427 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 22:15:06.433866 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 22:15:06.434132 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 22:15:06.446254 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1174 22:15:06.446370 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1175 22:15:06.446892 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 22:15:06.466743 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 22:15:06.467552 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 22:15:06.467837 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 22:15:06.467915 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 22:15:06.468013 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1181 22:15:06.510601 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1182 22:15:06.510872 0 9 8 | B1->B0 | 3232 2b2b | 0 0 | (1 1) (0 0)
1183 22:15:06.510948 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1184 22:15:06.511072 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1185 22:15:06.511204 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1186 22:15:06.511300 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1187 22:15:06.511404 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1188 22:15:06.511496 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1189 22:15:06.511798 0 10 4 | B1->B0 | 3434 3434 | 0 0 | (0 0) (0 0)
1190 22:15:06.512342 0 10 8 | B1->B0 | 2929 2d2d | 0 0 | (1 0) (0 0)
1191 22:15:06.554979 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 22:15:06.555252 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 22:15:06.555352 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1194 22:15:06.555502 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1195 22:15:06.555577 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1196 22:15:06.556336 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1197 22:15:06.556648 0 11 4 | B1->B0 | 2929 2626 | 0 0 | (1 1) (1 1)
1198 22:15:06.556757 0 11 8 | B1->B0 | 3b3b 3a3a | 0 0 | (0 0) (1 1)
1199 22:15:06.556843 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1200 22:15:06.556957 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1201 22:15:06.597991 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1202 22:15:06.598279 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1203 22:15:06.598359 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1204 22:15:06.598442 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1205 22:15:06.598565 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1206 22:15:06.598661 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1207 22:15:06.598764 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 22:15:06.598861 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 22:15:06.598973 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 22:15:06.599104 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 22:15:06.639110 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 22:15:06.639776 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 22:15:06.639864 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 22:15:06.640271 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 22:15:06.640883 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 22:15:06.641514 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 22:15:06.642147 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1218 22:15:06.642234 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1219 22:15:06.642520 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1220 22:15:06.645071 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1221 22:15:06.648439 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1222 22:15:06.652077 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1223 22:15:06.652164 Total UI for P1: 0, mck2ui 16
1224 22:15:06.658538 best dqsien dly found for B0: ( 0, 14, 6)
1225 22:15:06.658624 Total UI for P1: 0, mck2ui 16
1226 22:15:06.664989 best dqsien dly found for B1: ( 0, 14, 4)
1227 22:15:06.668422 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1228 22:15:06.671361 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1229 22:15:06.671444
1230 22:15:06.674800 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1231 22:15:06.678560 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1232 22:15:06.681585 [Gating] SW calibration Done
1233 22:15:06.681668 ==
1234 22:15:06.685221 Dram Type= 6, Freq= 0, CH_0, rank 1
1235 22:15:06.688760 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1236 22:15:06.688846 ==
1237 22:15:06.691714 RX Vref Scan: 0
1238 22:15:06.691799
1239 22:15:06.691914 RX Vref 0 -> 0, step: 1
1240 22:15:06.691995
1241 22:15:06.695088 RX Delay -130 -> 252, step: 16
1242 22:15:06.698241 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1243 22:15:06.705303 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1244 22:15:06.708920 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1245 22:15:06.712099 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1246 22:15:06.715253 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1247 22:15:06.718605 iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240
1248 22:15:06.721674 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1249 22:15:06.728523 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1250 22:15:06.731959 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1251 22:15:06.734970 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1252 22:15:06.738368 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1253 22:15:06.742191 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1254 22:15:06.748378 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1255 22:15:06.751666 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1256 22:15:06.755298 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1257 22:15:06.758372 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1258 22:15:06.758458 ==
1259 22:15:06.761974 Dram Type= 6, Freq= 0, CH_0, rank 1
1260 22:15:06.768412 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1261 22:15:06.768498 ==
1262 22:15:06.768594 DQS Delay:
1263 22:15:06.772003 DQS0 = 0, DQS1 = 0
1264 22:15:06.772092 DQM Delay:
1265 22:15:06.772157 DQM0 = 91, DQM1 = 80
1266 22:15:06.775503 DQ Delay:
1267 22:15:06.778459 DQ0 =93, DQ1 =93, DQ2 =85, DQ3 =85
1268 22:15:06.781934 DQ4 =93, DQ5 =85, DQ6 =93, DQ7 =101
1269 22:15:06.785547 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =77
1270 22:15:06.788465 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =85
1271 22:15:06.788553
1272 22:15:06.788652
1273 22:15:06.788731 ==
1274 22:15:06.792069 Dram Type= 6, Freq= 0, CH_0, rank 1
1275 22:15:06.795585 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1276 22:15:06.795669 ==
1277 22:15:06.795735
1278 22:15:06.795795
1279 22:15:06.798619 TX Vref Scan disable
1280 22:15:06.798701 == TX Byte 0 ==
1281 22:15:06.805456 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1282 22:15:06.808902 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1283 22:15:06.808988 == TX Byte 1 ==
1284 22:15:06.815530 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1285 22:15:06.818659 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1286 22:15:06.818759 ==
1287 22:15:06.822111 Dram Type= 6, Freq= 0, CH_0, rank 1
1288 22:15:06.824997 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1289 22:15:06.825080 ==
1290 22:15:06.839650 TX Vref=22, minBit 9, minWin=27, winSum=451
1291 22:15:06.843442 TX Vref=24, minBit 1, minWin=28, winSum=454
1292 22:15:06.846236 TX Vref=26, minBit 2, minWin=28, winSum=456
1293 22:15:06.849944 TX Vref=28, minBit 2, minWin=28, winSum=455
1294 22:15:06.852974 TX Vref=30, minBit 2, minWin=28, winSum=455
1295 22:15:06.856672 TX Vref=32, minBit 0, minWin=28, winSum=453
1296 22:15:06.862910 [TxChooseVref] Worse bit 2, Min win 28, Win sum 456, Final Vref 26
1297 22:15:06.863018
1298 22:15:06.866447 Final TX Range 1 Vref 26
1299 22:15:06.866523
1300 22:15:06.866599 ==
1301 22:15:06.869625 Dram Type= 6, Freq= 0, CH_0, rank 1
1302 22:15:06.873041 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1303 22:15:06.873114 ==
1304 22:15:06.873174
1305 22:15:06.873231
1306 22:15:06.876433 TX Vref Scan disable
1307 22:15:06.880066 == TX Byte 0 ==
1308 22:15:06.882965 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1309 22:15:06.886709 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1310 22:15:06.889773 == TX Byte 1 ==
1311 22:15:06.893189 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1312 22:15:06.896321 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1313 22:15:06.899831
1314 22:15:06.899912 [DATLAT]
1315 22:15:06.900001 Freq=800, CH0 RK1
1316 22:15:06.900074
1317 22:15:06.903740 DATLAT Default: 0xa
1318 22:15:06.903824 0, 0xFFFF, sum = 0
1319 22:15:06.906329 1, 0xFFFF, sum = 0
1320 22:15:06.906403 2, 0xFFFF, sum = 0
1321 22:15:06.910059 3, 0xFFFF, sum = 0
1322 22:15:06.910145 4, 0xFFFF, sum = 0
1323 22:15:06.913242 5, 0xFFFF, sum = 0
1324 22:15:06.913328 6, 0xFFFF, sum = 0
1325 22:15:06.916356 7, 0xFFFF, sum = 0
1326 22:15:06.916442 8, 0xFFFF, sum = 0
1327 22:15:06.920291 9, 0x0, sum = 1
1328 22:15:06.920391 10, 0x0, sum = 2
1329 22:15:06.923542 11, 0x0, sum = 3
1330 22:15:06.923627 12, 0x0, sum = 4
1331 22:15:06.926519 best_step = 10
1332 22:15:06.926603
1333 22:15:06.926668 ==
1334 22:15:06.930304 Dram Type= 6, Freq= 0, CH_0, rank 1
1335 22:15:06.933603 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1336 22:15:06.933733 ==
1337 22:15:06.936649 RX Vref Scan: 0
1338 22:15:06.936752
1339 22:15:06.936843 RX Vref 0 -> 0, step: 1
1340 22:15:06.936929
1341 22:15:06.939964 RX Delay -95 -> 252, step: 8
1342 22:15:06.946785 iDelay=209, Bit 0, Center 92 (-15 ~ 200) 216
1343 22:15:06.949985 iDelay=209, Bit 1, Center 96 (-7 ~ 200) 208
1344 22:15:06.953157 iDelay=209, Bit 2, Center 92 (-15 ~ 200) 216
1345 22:15:06.956966 iDelay=209, Bit 3, Center 88 (-23 ~ 200) 224
1346 22:15:06.960008 iDelay=209, Bit 4, Center 96 (-15 ~ 208) 224
1347 22:15:06.963531 iDelay=209, Bit 5, Center 88 (-23 ~ 200) 224
1348 22:15:06.970340 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1349 22:15:06.973212 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1350 22:15:06.976795 iDelay=209, Bit 8, Center 72 (-39 ~ 184) 224
1351 22:15:06.980324 iDelay=209, Bit 9, Center 72 (-31 ~ 176) 208
1352 22:15:06.983401 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
1353 22:15:06.990019 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
1354 22:15:06.993796 iDelay=209, Bit 12, Center 88 (-23 ~ 200) 224
1355 22:15:06.996661 iDelay=209, Bit 13, Center 92 (-15 ~ 200) 216
1356 22:15:07.000149 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1357 22:15:07.004051 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1358 22:15:07.006754 ==
1359 22:15:07.006835 Dram Type= 6, Freq= 0, CH_0, rank 1
1360 22:15:07.013302 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1361 22:15:07.013388 ==
1362 22:15:07.013462 DQS Delay:
1363 22:15:07.016799 DQS0 = 0, DQS1 = 0
1364 22:15:07.016885 DQM Delay:
1365 22:15:07.020265 DQM0 = 94, DQM1 = 83
1366 22:15:07.020344 DQ Delay:
1367 22:15:07.024182 DQ0 =92, DQ1 =96, DQ2 =92, DQ3 =88
1368 22:15:07.026967 DQ4 =96, DQ5 =88, DQ6 =100, DQ7 =100
1369 22:15:07.030373 DQ8 =72, DQ9 =72, DQ10 =84, DQ11 =76
1370 22:15:07.033635 DQ12 =88, DQ13 =92, DQ14 =92, DQ15 =88
1371 22:15:07.033711
1372 22:15:07.033782
1373 22:15:07.039972 [DQSOSCAuto] RK1, (LSB)MR18= 0x4314, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 393 ps
1374 22:15:07.043396 CH0 RK1: MR19=606, MR18=4314
1375 22:15:07.050519 CH0_RK1: MR19=0x606, MR18=0x4314, DQSOSC=393, MR23=63, INC=95, DEC=63
1376 22:15:07.053703 [RxdqsGatingPostProcess] freq 800
1377 22:15:07.057213 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1378 22:15:07.060746 Pre-setting of DQS Precalculation
1379 22:15:07.067266 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1380 22:15:07.067357 ==
1381 22:15:07.070687 Dram Type= 6, Freq= 0, CH_1, rank 0
1382 22:15:07.073527 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1383 22:15:07.073611 ==
1384 22:15:07.080268 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1385 22:15:07.087109 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1386 22:15:07.094979 [CA 0] Center 36 (6~67) winsize 62
1387 22:15:07.098045 [CA 1] Center 36 (6~67) winsize 62
1388 22:15:07.101723 [CA 2] Center 35 (5~66) winsize 62
1389 22:15:07.104785 [CA 3] Center 34 (4~65) winsize 62
1390 22:15:07.108355 [CA 4] Center 34 (4~65) winsize 62
1391 22:15:07.111222 [CA 5] Center 34 (4~65) winsize 62
1392 22:15:07.111329
1393 22:15:07.114847 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1394 22:15:07.114936
1395 22:15:07.118318 [CATrainingPosCal] consider 1 rank data
1396 22:15:07.121914 u2DelayCellTimex100 = 270/100 ps
1397 22:15:07.124879 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1398 22:15:07.128385 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1399 22:15:07.131720 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
1400 22:15:07.138417 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1401 22:15:07.141665 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1402 22:15:07.144783 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1403 22:15:07.144869
1404 22:15:07.148321 CA PerBit enable=1, Macro0, CA PI delay=34
1405 22:15:07.148408
1406 22:15:07.151608 [CBTSetCACLKResult] CA Dly = 34
1407 22:15:07.151693 CS Dly: 6 (0~37)
1408 22:15:07.151781 ==
1409 22:15:07.155240 Dram Type= 6, Freq= 0, CH_1, rank 1
1410 22:15:07.161422 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1411 22:15:07.161509 ==
1412 22:15:07.164820 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1413 22:15:07.171513 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1414 22:15:07.180939 [CA 0] Center 37 (6~68) winsize 63
1415 22:15:07.184348 [CA 1] Center 36 (6~67) winsize 62
1416 22:15:07.188085 [CA 2] Center 35 (5~66) winsize 62
1417 22:15:07.191580 [CA 3] Center 34 (4~65) winsize 62
1418 22:15:07.196000 [CA 4] Center 35 (4~66) winsize 63
1419 22:15:07.199606 [CA 5] Center 34 (4~65) winsize 62
1420 22:15:07.199732
1421 22:15:07.202982 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1422 22:15:07.203069
1423 22:15:07.206833 [CATrainingPosCal] consider 2 rank data
1424 22:15:07.206916 u2DelayCellTimex100 = 270/100 ps
1425 22:15:07.210648 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1426 22:15:07.214375 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1427 22:15:07.217967 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
1428 22:15:07.221382 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1429 22:15:07.228084 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1430 22:15:07.231450 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1431 22:15:07.231535
1432 22:15:07.234958 CA PerBit enable=1, Macro0, CA PI delay=34
1433 22:15:07.235041
1434 22:15:07.238610 [CBTSetCACLKResult] CA Dly = 34
1435 22:15:07.238693 CS Dly: 7 (0~39)
1436 22:15:07.238759
1437 22:15:07.241717 ----->DramcWriteLeveling(PI) begin...
1438 22:15:07.241803 ==
1439 22:15:07.244748 Dram Type= 6, Freq= 0, CH_1, rank 0
1440 22:15:07.248669 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1441 22:15:07.251626 ==
1442 22:15:07.254850 Write leveling (Byte 0): 28 => 28
1443 22:15:07.254934 Write leveling (Byte 1): 27 => 27
1444 22:15:07.258377 DramcWriteLeveling(PI) end<-----
1445 22:15:07.258460
1446 22:15:07.258526 ==
1447 22:15:07.262414 Dram Type= 6, Freq= 0, CH_1, rank 0
1448 22:15:07.268175 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1449 22:15:07.268279 ==
1450 22:15:07.272134 [Gating] SW mode calibration
1451 22:15:07.278588 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1452 22:15:07.282106 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1453 22:15:07.285001 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1454 22:15:07.291721 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1455 22:15:07.295024 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 22:15:07.298543 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 22:15:07.305297 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 22:15:07.309052 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 22:15:07.311812 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 22:15:07.318750 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 22:15:07.322242 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 22:15:07.325265 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 22:15:07.332077 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 22:15:07.335012 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 22:15:07.338685 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 22:15:07.345134 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 22:15:07.348475 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 22:15:07.351926 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 22:15:07.358695 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1470 22:15:07.361950 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1471 22:15:07.365250 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 22:15:07.368973 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 22:15:07.375439 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 22:15:07.378311 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 22:15:07.381613 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 22:15:07.388484 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 22:15:07.391986 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1478 22:15:07.395135 0 9 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
1479 22:15:07.401777 0 9 8 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
1480 22:15:07.405278 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1481 22:15:07.408478 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1482 22:15:07.415173 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1483 22:15:07.418887 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1484 22:15:07.421781 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1485 22:15:07.428442 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
1486 22:15:07.431916 0 10 4 | B1->B0 | 3232 2d2d | 1 1 | (1 0) (0 0)
1487 22:15:07.435281 0 10 8 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
1488 22:15:07.442523 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 22:15:07.445670 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 22:15:07.449150 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 22:15:07.451997 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1492 22:15:07.458744 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1493 22:15:07.461988 0 11 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1494 22:15:07.465790 0 11 4 | B1->B0 | 2b2b 3333 | 0 0 | (0 0) (0 0)
1495 22:15:07.472031 0 11 8 | B1->B0 | 4444 4646 | 1 0 | (0 0) (0 0)
1496 22:15:07.475447 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1497 22:15:07.478857 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1498 22:15:07.485449 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1499 22:15:07.488699 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1500 22:15:07.492112 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1501 22:15:07.499248 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1502 22:15:07.502146 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1503 22:15:07.505489 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1504 22:15:07.512567 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 22:15:07.515662 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 22:15:07.519011 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 22:15:07.522106 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 22:15:07.528750 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 22:15:07.532292 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 22:15:07.535765 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 22:15:07.542370 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 22:15:07.545851 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 22:15:07.548984 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 22:15:07.556065 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1515 22:15:07.558969 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1516 22:15:07.562187 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1517 22:15:07.568890 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1518 22:15:07.572445 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1519 22:15:07.575626 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1520 22:15:07.578848 Total UI for P1: 0, mck2ui 16
1521 22:15:07.582447 best dqsien dly found for B0: ( 0, 14, 4)
1522 22:15:07.585615 Total UI for P1: 0, mck2ui 16
1523 22:15:07.588801 best dqsien dly found for B1: ( 0, 14, 4)
1524 22:15:07.592473 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1525 22:15:07.595790 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1526 22:15:07.595887
1527 22:15:07.599438 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1528 22:15:07.605441 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1529 22:15:07.605522 [Gating] SW calibration Done
1530 22:15:07.605587 ==
1531 22:15:07.608925 Dram Type= 6, Freq= 0, CH_1, rank 0
1532 22:15:07.615367 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1533 22:15:07.615450 ==
1534 22:15:07.615515 RX Vref Scan: 0
1535 22:15:07.615575
1536 22:15:07.618982 RX Vref 0 -> 0, step: 1
1537 22:15:07.619063
1538 22:15:07.622717 RX Delay -130 -> 252, step: 16
1539 22:15:07.625464 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1540 22:15:07.629320 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1541 22:15:07.632203 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1542 22:15:07.638866 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1543 22:15:07.642221 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1544 22:15:07.645751 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1545 22:15:07.649300 iDelay=222, Bit 6, Center 109 (-2 ~ 221) 224
1546 22:15:07.652562 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1547 22:15:07.656029 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1548 22:15:07.662127 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1549 22:15:07.665773 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1550 22:15:07.669199 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1551 22:15:07.672343 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1552 22:15:07.678711 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1553 22:15:07.682479 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1554 22:15:07.685815 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1555 22:15:07.685896 ==
1556 22:15:07.688685 Dram Type= 6, Freq= 0, CH_1, rank 0
1557 22:15:07.692414 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1558 22:15:07.692496 ==
1559 22:15:07.695981 DQS Delay:
1560 22:15:07.696062 DQS0 = 0, DQS1 = 0
1561 22:15:07.699086 DQM Delay:
1562 22:15:07.699168 DQM0 = 94, DQM1 = 87
1563 22:15:07.699232 DQ Delay:
1564 22:15:07.702494 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93
1565 22:15:07.705679 DQ4 =93, DQ5 =109, DQ6 =109, DQ7 =93
1566 22:15:07.708947 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =85
1567 22:15:07.712019 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1568 22:15:07.712102
1569 22:15:07.712165
1570 22:15:07.715716 ==
1571 22:15:07.715798 Dram Type= 6, Freq= 0, CH_1, rank 0
1572 22:15:07.721989 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1573 22:15:07.722071 ==
1574 22:15:07.722136
1575 22:15:07.722194
1576 22:15:07.726067 TX Vref Scan disable
1577 22:15:07.726148 == TX Byte 0 ==
1578 22:15:07.728940 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1579 22:15:07.735500 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1580 22:15:07.735582 == TX Byte 1 ==
1581 22:15:07.739125 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1582 22:15:07.745637 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1583 22:15:07.745717 ==
1584 22:15:07.748614 Dram Type= 6, Freq= 0, CH_1, rank 0
1585 22:15:07.751976 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1586 22:15:07.752058 ==
1587 22:15:07.765705 TX Vref=22, minBit 3, minWin=26, winSum=440
1588 22:15:07.769995 TX Vref=24, minBit 3, minWin=26, winSum=441
1589 22:15:07.772792 TX Vref=26, minBit 0, minWin=27, winSum=448
1590 22:15:07.776652 TX Vref=28, minBit 2, minWin=27, winSum=448
1591 22:15:07.779990 TX Vref=30, minBit 2, minWin=27, winSum=449
1592 22:15:07.782919 TX Vref=32, minBit 0, minWin=27, winSum=448
1593 22:15:07.789710 [TxChooseVref] Worse bit 2, Min win 27, Win sum 449, Final Vref 30
1594 22:15:07.789791
1595 22:15:07.793376 Final TX Range 1 Vref 30
1596 22:15:07.793459
1597 22:15:07.793522 ==
1598 22:15:07.796259 Dram Type= 6, Freq= 0, CH_1, rank 0
1599 22:15:07.799872 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1600 22:15:07.799954 ==
1601 22:15:07.800019
1602 22:15:07.800077
1603 22:15:07.803349 TX Vref Scan disable
1604 22:15:07.806493 == TX Byte 0 ==
1605 22:15:07.810106 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1606 22:15:07.813209 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1607 22:15:07.816268 == TX Byte 1 ==
1608 22:15:07.819562 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1609 22:15:07.823321 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1610 22:15:07.823424
1611 22:15:07.823488 [DATLAT]
1612 22:15:07.826528 Freq=800, CH1 RK0
1613 22:15:07.826609
1614 22:15:07.830056 DATLAT Default: 0xa
1615 22:15:07.830136 0, 0xFFFF, sum = 0
1616 22:15:07.833052 1, 0xFFFF, sum = 0
1617 22:15:07.833134 2, 0xFFFF, sum = 0
1618 22:15:07.836778 3, 0xFFFF, sum = 0
1619 22:15:07.836861 4, 0xFFFF, sum = 0
1620 22:15:07.839636 5, 0xFFFF, sum = 0
1621 22:15:07.839719 6, 0xFFFF, sum = 0
1622 22:15:07.843413 7, 0xFFFF, sum = 0
1623 22:15:07.843521 8, 0xFFFF, sum = 0
1624 22:15:07.846381 9, 0x0, sum = 1
1625 22:15:07.846463 10, 0x0, sum = 2
1626 22:15:07.849972 11, 0x0, sum = 3
1627 22:15:07.850054 12, 0x0, sum = 4
1628 22:15:07.850120 best_step = 10
1629 22:15:07.850179
1630 22:15:07.853518 ==
1631 22:15:07.856311 Dram Type= 6, Freq= 0, CH_1, rank 0
1632 22:15:07.859891 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1633 22:15:07.859986 ==
1634 22:15:07.860077 RX Vref Scan: 1
1635 22:15:07.860166
1636 22:15:07.862903 Set Vref Range= 32 -> 127
1637 22:15:07.862984
1638 22:15:07.866455 RX Vref 32 -> 127, step: 1
1639 22:15:07.866561
1640 22:15:07.869539 RX Delay -79 -> 252, step: 8
1641 22:15:07.869644
1642 22:15:07.873100 Set Vref, RX VrefLevel [Byte0]: 32
1643 22:15:07.876351 [Byte1]: 32
1644 22:15:07.876457
1645 22:15:07.879763 Set Vref, RX VrefLevel [Byte0]: 33
1646 22:15:07.883065 [Byte1]: 33
1647 22:15:07.883146
1648 22:15:07.886281 Set Vref, RX VrefLevel [Byte0]: 34
1649 22:15:07.890059 [Byte1]: 34
1650 22:15:07.893285
1651 22:15:07.893366 Set Vref, RX VrefLevel [Byte0]: 35
1652 22:15:07.896184 [Byte1]: 35
1653 22:15:07.900312
1654 22:15:07.900393 Set Vref, RX VrefLevel [Byte0]: 36
1655 22:15:07.904373 [Byte1]: 36
1656 22:15:07.908007
1657 22:15:07.908087 Set Vref, RX VrefLevel [Byte0]: 37
1658 22:15:07.911540 [Byte1]: 37
1659 22:15:07.915790
1660 22:15:07.915872 Set Vref, RX VrefLevel [Byte0]: 38
1661 22:15:07.918847 [Byte1]: 38
1662 22:15:07.923310
1663 22:15:07.923442 Set Vref, RX VrefLevel [Byte0]: 39
1664 22:15:07.926955 [Byte1]: 39
1665 22:15:07.931236
1666 22:15:07.931373 Set Vref, RX VrefLevel [Byte0]: 40
1667 22:15:07.934003 [Byte1]: 40
1668 22:15:07.938600
1669 22:15:07.938684 Set Vref, RX VrefLevel [Byte0]: 41
1670 22:15:07.941614 [Byte1]: 41
1671 22:15:07.945908
1672 22:15:07.945991 Set Vref, RX VrefLevel [Byte0]: 42
1673 22:15:07.949637 [Byte1]: 42
1674 22:15:07.953578
1675 22:15:07.953686 Set Vref, RX VrefLevel [Byte0]: 43
1676 22:15:07.957141 [Byte1]: 43
1677 22:15:07.961203
1678 22:15:07.961311 Set Vref, RX VrefLevel [Byte0]: 44
1679 22:15:07.964146 [Byte1]: 44
1680 22:15:07.968907
1681 22:15:07.968987 Set Vref, RX VrefLevel [Byte0]: 45
1682 22:15:07.972036 [Byte1]: 45
1683 22:15:07.976050
1684 22:15:07.976149 Set Vref, RX VrefLevel [Byte0]: 46
1685 22:15:07.979120 [Byte1]: 46
1686 22:15:07.983866
1687 22:15:07.983968 Set Vref, RX VrefLevel [Byte0]: 47
1688 22:15:07.987030 [Byte1]: 47
1689 22:15:07.991030
1690 22:15:07.991137 Set Vref, RX VrefLevel [Byte0]: 48
1691 22:15:07.994336 [Byte1]: 48
1692 22:15:07.998592
1693 22:15:07.998693 Set Vref, RX VrefLevel [Byte0]: 49
1694 22:15:08.002051 [Byte1]: 49
1695 22:15:08.005969
1696 22:15:08.006070 Set Vref, RX VrefLevel [Byte0]: 50
1697 22:15:08.009515 [Byte1]: 50
1698 22:15:08.013639
1699 22:15:08.013728 Set Vref, RX VrefLevel [Byte0]: 51
1700 22:15:08.017162 [Byte1]: 51
1701 22:15:08.021165
1702 22:15:08.021244 Set Vref, RX VrefLevel [Byte0]: 52
1703 22:15:08.024384 [Byte1]: 52
1704 22:15:08.029091
1705 22:15:08.029202 Set Vref, RX VrefLevel [Byte0]: 53
1706 22:15:08.032424 [Byte1]: 53
1707 22:15:08.036773
1708 22:15:08.036855 Set Vref, RX VrefLevel [Byte0]: 54
1709 22:15:08.039989 [Byte1]: 54
1710 22:15:08.044081
1711 22:15:08.044163 Set Vref, RX VrefLevel [Byte0]: 55
1712 22:15:08.047135 [Byte1]: 55
1713 22:15:08.051427
1714 22:15:08.051508 Set Vref, RX VrefLevel [Byte0]: 56
1715 22:15:08.055027 [Byte1]: 56
1716 22:15:08.059106
1717 22:15:08.059215 Set Vref, RX VrefLevel [Byte0]: 57
1718 22:15:08.062116 [Byte1]: 57
1719 22:15:08.066559
1720 22:15:08.066641 Set Vref, RX VrefLevel [Byte0]: 58
1721 22:15:08.070169 [Byte1]: 58
1722 22:15:08.073963
1723 22:15:08.074072 Set Vref, RX VrefLevel [Byte0]: 59
1724 22:15:08.077436 [Byte1]: 59
1725 22:15:08.081646
1726 22:15:08.081756 Set Vref, RX VrefLevel [Byte0]: 60
1727 22:15:08.085350 [Byte1]: 60
1728 22:15:08.089733
1729 22:15:08.089842 Set Vref, RX VrefLevel [Byte0]: 61
1730 22:15:08.092650 [Byte1]: 61
1731 22:15:08.096710
1732 22:15:08.096790 Set Vref, RX VrefLevel [Byte0]: 62
1733 22:15:08.100005 [Byte1]: 62
1734 22:15:08.104390
1735 22:15:08.104471 Set Vref, RX VrefLevel [Byte0]: 63
1736 22:15:08.107742 [Byte1]: 63
1737 22:15:08.111775
1738 22:15:08.111855 Set Vref, RX VrefLevel [Byte0]: 64
1739 22:15:08.115046 [Byte1]: 64
1740 22:15:08.119707
1741 22:15:08.119787 Set Vref, RX VrefLevel [Byte0]: 65
1742 22:15:08.122700 [Byte1]: 65
1743 22:15:08.126891
1744 22:15:08.126971 Set Vref, RX VrefLevel [Byte0]: 66
1745 22:15:08.130039 [Byte1]: 66
1746 22:15:08.134718
1747 22:15:08.134804 Set Vref, RX VrefLevel [Byte0]: 67
1748 22:15:08.138213 [Byte1]: 67
1749 22:15:08.142141
1750 22:15:08.142221 Set Vref, RX VrefLevel [Byte0]: 68
1751 22:15:08.145269 [Byte1]: 68
1752 22:15:08.150014
1753 22:15:08.150095 Set Vref, RX VrefLevel [Byte0]: 69
1754 22:15:08.152839 [Byte1]: 69
1755 22:15:08.157603
1756 22:15:08.157684 Set Vref, RX VrefLevel [Byte0]: 70
1757 22:15:08.160478 [Byte1]: 70
1758 22:15:08.165186
1759 22:15:08.165266 Set Vref, RX VrefLevel [Byte0]: 71
1760 22:15:08.167891 [Byte1]: 71
1761 22:15:08.172045
1762 22:15:08.172127 Set Vref, RX VrefLevel [Byte0]: 72
1763 22:15:08.175398 [Byte1]: 72
1764 22:15:08.180084
1765 22:15:08.180195 Final RX Vref Byte 0 = 59 to rank0
1766 22:15:08.182998 Final RX Vref Byte 1 = 57 to rank0
1767 22:15:08.186550 Final RX Vref Byte 0 = 59 to rank1
1768 22:15:08.190076 Final RX Vref Byte 1 = 57 to rank1==
1769 22:15:08.193787 Dram Type= 6, Freq= 0, CH_1, rank 0
1770 22:15:08.199764 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1771 22:15:08.199872 ==
1772 22:15:08.199937 DQS Delay:
1773 22:15:08.200002 DQS0 = 0, DQS1 = 0
1774 22:15:08.202983 DQM Delay:
1775 22:15:08.203084 DQM0 = 97, DQM1 = 90
1776 22:15:08.206579 DQ Delay:
1777 22:15:08.210152 DQ0 =100, DQ1 =88, DQ2 =84, DQ3 =96
1778 22:15:08.212994 DQ4 =96, DQ5 =108, DQ6 =108, DQ7 =96
1779 22:15:08.216709 DQ8 =80, DQ9 =80, DQ10 =92, DQ11 =84
1780 22:15:08.220182 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =96
1781 22:15:08.220287
1782 22:15:08.220379
1783 22:15:08.226542 [DQSOSCAuto] RK0, (LSB)MR18= 0x2c48, (MSB)MR19= 0x606, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps
1784 22:15:08.229983 CH1 RK0: MR19=606, MR18=2C48
1785 22:15:08.236738 CH1_RK0: MR19=0x606, MR18=0x2C48, DQSOSC=391, MR23=63, INC=96, DEC=64
1786 22:15:08.236841
1787 22:15:08.240280 ----->DramcWriteLeveling(PI) begin...
1788 22:15:08.240385 ==
1789 22:15:08.243251 Dram Type= 6, Freq= 0, CH_1, rank 1
1790 22:15:08.246549 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1791 22:15:08.246657 ==
1792 22:15:08.249947 Write leveling (Byte 0): 25 => 25
1793 22:15:08.253311 Write leveling (Byte 1): 26 => 26
1794 22:15:08.256454 DramcWriteLeveling(PI) end<-----
1795 22:15:08.256530
1796 22:15:08.256593 ==
1797 22:15:08.259933 Dram Type= 6, Freq= 0, CH_1, rank 1
1798 22:15:08.263472 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1799 22:15:08.263550 ==
1800 22:15:08.267043 [Gating] SW mode calibration
1801 22:15:08.273150 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1802 22:15:08.280382 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1803 22:15:08.283585 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1804 22:15:08.287008 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1805 22:15:08.293301 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1806 22:15:08.297017 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1807 22:15:08.299950 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1808 22:15:08.306499 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1809 22:15:08.309944 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1810 22:15:08.313634 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1811 22:15:08.320474 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1812 22:15:08.323725 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1813 22:15:08.326750 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1814 22:15:08.330152 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1815 22:15:08.336780 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 22:15:08.340295 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 22:15:08.343155 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 22:15:08.350416 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 22:15:08.353617 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1820 22:15:08.356774 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 1)
1821 22:15:08.363578 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 22:15:08.367013 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 22:15:08.370379 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 22:15:08.376855 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 22:15:08.380305 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 22:15:08.383289 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 22:15:08.390759 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 22:15:08.393651 0 9 4 | B1->B0 | 2525 2323 | 1 0 | (0 0) (0 0)
1829 22:15:08.396900 0 9 8 | B1->B0 | 3434 3130 | 1 1 | (1 1) (1 1)
1830 22:15:08.403519 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1831 22:15:08.407152 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1832 22:15:08.410159 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1833 22:15:08.416997 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1834 22:15:08.420317 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1835 22:15:08.423707 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1836 22:15:08.426841 0 10 4 | B1->B0 | 2e2e 3030 | 0 1 | (0 0) (1 0)
1837 22:15:08.433736 0 10 8 | B1->B0 | 2323 2323 | 0 1 | (1 0) (1 0)
1838 22:15:08.436899 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 22:15:08.440426 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1840 22:15:08.447466 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1841 22:15:08.450744 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1842 22:15:08.454424 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1843 22:15:08.460616 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1844 22:15:08.463897 0 11 4 | B1->B0 | 3c3c 2929 | 0 0 | (1 1) (0 0)
1845 22:15:08.467033 0 11 8 | B1->B0 | 4646 4343 | 0 0 | (0 0) (0 0)
1846 22:15:08.473975 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1847 22:15:08.477537 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1848 22:15:08.480306 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1849 22:15:08.487237 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1850 22:15:08.490436 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1851 22:15:08.493881 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1852 22:15:08.500481 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1853 22:15:08.503474 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1854 22:15:08.507202 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1855 22:15:08.510273 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1856 22:15:08.517044 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1857 22:15:08.519990 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1858 22:15:08.523371 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1859 22:15:08.530522 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1860 22:15:08.533892 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1861 22:15:08.537053 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1862 22:15:08.543675 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1863 22:15:08.547300 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1864 22:15:08.550495 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1865 22:15:08.557026 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1866 22:15:08.560451 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1867 22:15:08.564082 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1868 22:15:08.570318 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1869 22:15:08.570401 Total UI for P1: 0, mck2ui 16
1870 22:15:08.577314 best dqsien dly found for B1: ( 0, 14, 2)
1871 22:15:08.580374 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1872 22:15:08.583958 Total UI for P1: 0, mck2ui 16
1873 22:15:08.587094 best dqsien dly found for B0: ( 0, 14, 4)
1874 22:15:08.590797 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1875 22:15:08.594067 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1876 22:15:08.594180
1877 22:15:08.597163 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1878 22:15:08.600745 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1879 22:15:08.604509 [Gating] SW calibration Done
1880 22:15:08.604592 ==
1881 22:15:08.607498 Dram Type= 6, Freq= 0, CH_1, rank 1
1882 22:15:08.611143 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1883 22:15:08.611227 ==
1884 22:15:08.614004 RX Vref Scan: 0
1885 22:15:08.614086
1886 22:15:08.614156 RX Vref 0 -> 0, step: 1
1887 22:15:08.614248
1888 22:15:08.617605 RX Delay -130 -> 252, step: 16
1889 22:15:08.624007 iDelay=222, Bit 0, Center 101 (-2 ~ 205) 208
1890 22:15:08.627061 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1891 22:15:08.630600 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1892 22:15:08.633974 iDelay=222, Bit 3, Center 85 (-18 ~ 189) 208
1893 22:15:08.637146 iDelay=222, Bit 4, Center 85 (-18 ~ 189) 208
1894 22:15:08.640873 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1895 22:15:08.647604 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1896 22:15:08.651054 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1897 22:15:08.654105 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1898 22:15:08.657286 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1899 22:15:08.660503 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1900 22:15:08.667525 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1901 22:15:08.671133 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1902 22:15:08.674059 iDelay=222, Bit 13, Center 101 (-2 ~ 205) 208
1903 22:15:08.677349 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1904 22:15:08.680957 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1905 22:15:08.684353 ==
1906 22:15:08.687525 Dram Type= 6, Freq= 0, CH_1, rank 1
1907 22:15:08.691130 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1908 22:15:08.691217 ==
1909 22:15:08.691332 DQS Delay:
1910 22:15:08.694001 DQS0 = 0, DQS1 = 0
1911 22:15:08.694081 DQM Delay:
1912 22:15:08.697811 DQM0 = 92, DQM1 = 88
1913 22:15:08.697897 DQ Delay:
1914 22:15:08.700699 DQ0 =101, DQ1 =85, DQ2 =77, DQ3 =85
1915 22:15:08.704186 DQ4 =85, DQ5 =109, DQ6 =101, DQ7 =93
1916 22:15:08.707577 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =85
1917 22:15:08.710679 DQ12 =93, DQ13 =101, DQ14 =93, DQ15 =93
1918 22:15:08.710764
1919 22:15:08.710845
1920 22:15:08.710919 ==
1921 22:15:08.714265 Dram Type= 6, Freq= 0, CH_1, rank 1
1922 22:15:08.717870 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1923 22:15:08.717959 ==
1924 22:15:08.718042
1925 22:15:08.718117
1926 22:15:08.720950 TX Vref Scan disable
1927 22:15:08.724160 == TX Byte 0 ==
1928 22:15:08.727946 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1929 22:15:08.730887 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1930 22:15:08.734436 == TX Byte 1 ==
1931 22:15:08.737829 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1932 22:15:08.741074 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1933 22:15:08.741150 ==
1934 22:15:08.744253 Dram Type= 6, Freq= 0, CH_1, rank 1
1935 22:15:08.747756 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1936 22:15:08.750995 ==
1937 22:15:08.762201 TX Vref=22, minBit 0, minWin=26, winSum=434
1938 22:15:08.765466 TX Vref=24, minBit 1, minWin=26, winSum=442
1939 22:15:08.769089 TX Vref=26, minBit 1, minWin=26, winSum=440
1940 22:15:08.772312 TX Vref=28, minBit 3, minWin=26, winSum=444
1941 22:15:08.775715 TX Vref=30, minBit 3, minWin=26, winSum=443
1942 22:15:08.779418 TX Vref=32, minBit 0, minWin=26, winSum=443
1943 22:15:08.785848 [TxChooseVref] Worse bit 3, Min win 26, Win sum 444, Final Vref 28
1944 22:15:08.785930
1945 22:15:08.789337 Final TX Range 1 Vref 28
1946 22:15:08.789440
1947 22:15:08.789529 ==
1948 22:15:08.792360 Dram Type= 6, Freq= 0, CH_1, rank 1
1949 22:15:08.795795 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1950 22:15:08.795900 ==
1951 22:15:08.795992
1952 22:15:08.796066
1953 22:15:08.799052 TX Vref Scan disable
1954 22:15:08.802255 == TX Byte 0 ==
1955 22:15:08.805916 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1956 22:15:08.809712 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1957 22:15:08.812314 == TX Byte 1 ==
1958 22:15:08.815550 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1959 22:15:08.819250 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1960 22:15:08.819359
1961 22:15:08.822770 [DATLAT]
1962 22:15:08.822851 Freq=800, CH1 RK1
1963 22:15:08.822915
1964 22:15:08.826205 DATLAT Default: 0xa
1965 22:15:08.826313 0, 0xFFFF, sum = 0
1966 22:15:08.829063 1, 0xFFFF, sum = 0
1967 22:15:08.829166 2, 0xFFFF, sum = 0
1968 22:15:08.832731 3, 0xFFFF, sum = 0
1969 22:15:08.832831 4, 0xFFFF, sum = 0
1970 22:15:08.835872 5, 0xFFFF, sum = 0
1971 22:15:08.835946 6, 0xFFFF, sum = 0
1972 22:15:08.839134 7, 0xFFFF, sum = 0
1973 22:15:08.839237 8, 0xFFFF, sum = 0
1974 22:15:08.842957 9, 0x0, sum = 1
1975 22:15:08.843059 10, 0x0, sum = 2
1976 22:15:08.846285 11, 0x0, sum = 3
1977 22:15:08.846383 12, 0x0, sum = 4
1978 22:15:08.849827 best_step = 10
1979 22:15:08.849927
1980 22:15:08.850013 ==
1981 22:15:08.852720 Dram Type= 6, Freq= 0, CH_1, rank 1
1982 22:15:08.856340 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1983 22:15:08.856441 ==
1984 22:15:08.856528 RX Vref Scan: 0
1985 22:15:08.856620
1986 22:15:08.859846 RX Vref 0 -> 0, step: 1
1987 22:15:08.859940
1988 22:15:08.863383 RX Delay -79 -> 252, step: 8
1989 22:15:08.866256 iDelay=209, Bit 0, Center 104 (9 ~ 200) 192
1990 22:15:08.873100 iDelay=209, Bit 1, Center 92 (-7 ~ 192) 200
1991 22:15:08.876402 iDelay=209, Bit 2, Center 84 (-15 ~ 184) 200
1992 22:15:08.879645 iDelay=209, Bit 3, Center 92 (-7 ~ 192) 200
1993 22:15:08.882942 iDelay=209, Bit 4, Center 92 (-7 ~ 192) 200
1994 22:15:08.886539 iDelay=209, Bit 5, Center 112 (17 ~ 208) 192
1995 22:15:08.889614 iDelay=209, Bit 6, Center 108 (9 ~ 208) 200
1996 22:15:08.896546 iDelay=209, Bit 7, Center 96 (-7 ~ 200) 208
1997 22:15:08.899775 iDelay=209, Bit 8, Center 80 (-23 ~ 184) 208
1998 22:15:08.902837 iDelay=209, Bit 9, Center 80 (-23 ~ 184) 208
1999 22:15:08.906602 iDelay=209, Bit 10, Center 92 (-7 ~ 192) 200
2000 22:15:08.909756 iDelay=209, Bit 11, Center 88 (-15 ~ 192) 208
2001 22:15:08.916263 iDelay=209, Bit 12, Center 100 (-7 ~ 208) 216
2002 22:15:08.919761 iDelay=209, Bit 13, Center 96 (-7 ~ 200) 208
2003 22:15:08.923203 iDelay=209, Bit 14, Center 96 (-7 ~ 200) 208
2004 22:15:08.926374 iDelay=209, Bit 15, Center 96 (-7 ~ 200) 208
2005 22:15:08.926457 ==
2006 22:15:08.929968 Dram Type= 6, Freq= 0, CH_1, rank 1
2007 22:15:08.932853 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2008 22:15:08.932936 ==
2009 22:15:08.936386 DQS Delay:
2010 22:15:08.936467 DQS0 = 0, DQS1 = 0
2011 22:15:08.939867 DQM Delay:
2012 22:15:08.939948 DQM0 = 97, DQM1 = 91
2013 22:15:08.940013 DQ Delay:
2014 22:15:08.943112 DQ0 =104, DQ1 =92, DQ2 =84, DQ3 =92
2015 22:15:08.946133 DQ4 =92, DQ5 =112, DQ6 =108, DQ7 =96
2016 22:15:08.949688 DQ8 =80, DQ9 =80, DQ10 =92, DQ11 =88
2017 22:15:08.953264 DQ12 =100, DQ13 =96, DQ14 =96, DQ15 =96
2018 22:15:08.956358
2019 22:15:08.956439
2020 22:15:08.963268 [DQSOSCAuto] RK1, (LSB)MR18= 0x4811, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 391 ps
2021 22:15:08.966221 CH1 RK1: MR19=606, MR18=4811
2022 22:15:08.973052 CH1_RK1: MR19=0x606, MR18=0x4811, DQSOSC=391, MR23=63, INC=96, DEC=64
2023 22:15:08.976321 [RxdqsGatingPostProcess] freq 800
2024 22:15:08.979711 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2025 22:15:08.983067 Pre-setting of DQS Precalculation
2026 22:15:08.989661 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2027 22:15:08.996238 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2028 22:15:09.003142 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2029 22:15:09.003250
2030 22:15:09.003367
2031 22:15:09.006527 [Calibration Summary] 1600 Mbps
2032 22:15:09.006626 CH 0, Rank 0
2033 22:15:09.009677 SW Impedance : PASS
2034 22:15:09.012831 DUTY Scan : NO K
2035 22:15:09.012931 ZQ Calibration : PASS
2036 22:15:09.016828 Jitter Meter : NO K
2037 22:15:09.016934 CBT Training : PASS
2038 22:15:09.020141 Write leveling : PASS
2039 22:15:09.023274 RX DQS gating : PASS
2040 22:15:09.023406 RX DQ/DQS(RDDQC) : PASS
2041 22:15:09.026700 TX DQ/DQS : PASS
2042 22:15:09.030011 RX DATLAT : PASS
2043 22:15:09.030113 RX DQ/DQS(Engine): PASS
2044 22:15:09.033012 TX OE : NO K
2045 22:15:09.033114 All Pass.
2046 22:15:09.033205
2047 22:15:09.036669 CH 0, Rank 1
2048 22:15:09.036766 SW Impedance : PASS
2049 22:15:09.039675 DUTY Scan : NO K
2050 22:15:09.043057 ZQ Calibration : PASS
2051 22:15:09.043155 Jitter Meter : NO K
2052 22:15:09.046659 CBT Training : PASS
2053 22:15:09.049592 Write leveling : PASS
2054 22:15:09.049694 RX DQS gating : PASS
2055 22:15:09.053043 RX DQ/DQS(RDDQC) : PASS
2056 22:15:09.053135 TX DQ/DQS : PASS
2057 22:15:09.056141 RX DATLAT : PASS
2058 22:15:09.059865 RX DQ/DQS(Engine): PASS
2059 22:15:09.059938 TX OE : NO K
2060 22:15:09.062960 All Pass.
2061 22:15:09.063057
2062 22:15:09.063145 CH 1, Rank 0
2063 22:15:09.066598 SW Impedance : PASS
2064 22:15:09.066692 DUTY Scan : NO K
2065 22:15:09.069855 ZQ Calibration : PASS
2066 22:15:09.073228 Jitter Meter : NO K
2067 22:15:09.073328 CBT Training : PASS
2068 22:15:09.076124 Write leveling : PASS
2069 22:15:09.080021 RX DQS gating : PASS
2070 22:15:09.080117 RX DQ/DQS(RDDQC) : PASS
2071 22:15:09.082942 TX DQ/DQS : PASS
2072 22:15:09.086827 RX DATLAT : PASS
2073 22:15:09.086928 RX DQ/DQS(Engine): PASS
2074 22:15:09.089460 TX OE : NO K
2075 22:15:09.089570 All Pass.
2076 22:15:09.089662
2077 22:15:09.092964 CH 1, Rank 1
2078 22:15:09.093043 SW Impedance : PASS
2079 22:15:09.096610 DUTY Scan : NO K
2080 22:15:09.096695 ZQ Calibration : PASS
2081 22:15:09.100157 Jitter Meter : NO K
2082 22:15:09.102979 CBT Training : PASS
2083 22:15:09.103078 Write leveling : PASS
2084 22:15:09.106355 RX DQS gating : PASS
2085 22:15:09.109965 RX DQ/DQS(RDDQC) : PASS
2086 22:15:09.110067 TX DQ/DQS : PASS
2087 22:15:09.113232 RX DATLAT : PASS
2088 22:15:09.116790 RX DQ/DQS(Engine): PASS
2089 22:15:09.116942 TX OE : NO K
2090 22:15:09.120211 All Pass.
2091 22:15:09.120312
2092 22:15:09.120412 DramC Write-DBI off
2093 22:15:09.123060 PER_BANK_REFRESH: Hybrid Mode
2094 22:15:09.123158 TX_TRACKING: ON
2095 22:15:09.126313 [GetDramInforAfterCalByMRR] Vendor 6.
2096 22:15:09.133317 [GetDramInforAfterCalByMRR] Revision 606.
2097 22:15:09.136871 [GetDramInforAfterCalByMRR] Revision 2 0.
2098 22:15:09.136970 MR0 0x3b3b
2099 22:15:09.137070 MR8 0x5151
2100 22:15:09.139947 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2101 22:15:09.140022
2102 22:15:09.143011 MR0 0x3b3b
2103 22:15:09.143116 MR8 0x5151
2104 22:15:09.146817 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2105 22:15:09.146892
2106 22:15:09.156209 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2107 22:15:09.159910 [FAST_K] Save calibration result to emmc
2108 22:15:09.162857 [FAST_K] Save calibration result to emmc
2109 22:15:09.166267 dram_init: config_dvfs: 1
2110 22:15:09.169852 dramc_set_vcore_voltage set vcore to 662500
2111 22:15:09.173068 Read voltage for 1200, 2
2112 22:15:09.173166 Vio18 = 0
2113 22:15:09.173242 Vcore = 662500
2114 22:15:09.176245 Vdram = 0
2115 22:15:09.176319 Vddq = 0
2116 22:15:09.176381 Vmddr = 0
2117 22:15:09.183255 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2118 22:15:09.186487 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2119 22:15:09.189728 MEM_TYPE=3, freq_sel=15
2120 22:15:09.193351 sv_algorithm_assistance_LP4_1600
2121 22:15:09.196528 ============ PULL DRAM RESETB DOWN ============
2122 22:15:09.199621 ========== PULL DRAM RESETB DOWN end =========
2123 22:15:09.207216 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2124 22:15:09.210178 ===================================
2125 22:15:09.210281 LPDDR4 DRAM CONFIGURATION
2126 22:15:09.213189 ===================================
2127 22:15:09.216693 EX_ROW_EN[0] = 0x0
2128 22:15:09.220018 EX_ROW_EN[1] = 0x0
2129 22:15:09.220118 LP4Y_EN = 0x0
2130 22:15:09.223304 WORK_FSP = 0x0
2131 22:15:09.223407 WL = 0x4
2132 22:15:09.226563 RL = 0x4
2133 22:15:09.226658 BL = 0x2
2134 22:15:09.230162 RPST = 0x0
2135 22:15:09.230257 RD_PRE = 0x0
2136 22:15:09.233588 WR_PRE = 0x1
2137 22:15:09.233695 WR_PST = 0x0
2138 22:15:09.236574 DBI_WR = 0x0
2139 22:15:09.236671 DBI_RD = 0x0
2140 22:15:09.239795 OTF = 0x1
2141 22:15:09.243358 ===================================
2142 22:15:09.246479 ===================================
2143 22:15:09.246560 ANA top config
2144 22:15:09.250300 ===================================
2145 22:15:09.253491 DLL_ASYNC_EN = 0
2146 22:15:09.256956 ALL_SLAVE_EN = 0
2147 22:15:09.257054 NEW_RANK_MODE = 1
2148 22:15:09.259840 DLL_IDLE_MODE = 1
2149 22:15:09.263372 LP45_APHY_COMB_EN = 1
2150 22:15:09.267178 TX_ODT_DIS = 1
2151 22:15:09.267278 NEW_8X_MODE = 1
2152 22:15:09.270076 ===================================
2153 22:15:09.273207 ===================================
2154 22:15:09.276836 data_rate = 2400
2155 22:15:09.280361 CKR = 1
2156 22:15:09.283253 DQ_P2S_RATIO = 8
2157 22:15:09.286580 ===================================
2158 22:15:09.289827 CA_P2S_RATIO = 8
2159 22:15:09.293559 DQ_CA_OPEN = 0
2160 22:15:09.293661 DQ_SEMI_OPEN = 0
2161 22:15:09.296630 CA_SEMI_OPEN = 0
2162 22:15:09.299771 CA_FULL_RATE = 0
2163 22:15:09.303718 DQ_CKDIV4_EN = 0
2164 22:15:09.307085 CA_CKDIV4_EN = 0
2165 22:15:09.310279 CA_PREDIV_EN = 0
2166 22:15:09.310391 PH8_DLY = 17
2167 22:15:09.313223 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2168 22:15:09.316904 DQ_AAMCK_DIV = 4
2169 22:15:09.320300 CA_AAMCK_DIV = 4
2170 22:15:09.323058 CA_ADMCK_DIV = 4
2171 22:15:09.326638 DQ_TRACK_CA_EN = 0
2172 22:15:09.326738 CA_PICK = 1200
2173 22:15:09.330232 CA_MCKIO = 1200
2174 22:15:09.333232 MCKIO_SEMI = 0
2175 22:15:09.336767 PLL_FREQ = 2366
2176 22:15:09.340124 DQ_UI_PI_RATIO = 32
2177 22:15:09.343289 CA_UI_PI_RATIO = 0
2178 22:15:09.347183 ===================================
2179 22:15:09.349909 ===================================
2180 22:15:09.350008 memory_type:LPDDR4
2181 22:15:09.353639 GP_NUM : 10
2182 22:15:09.356631 SRAM_EN : 1
2183 22:15:09.356736 MD32_EN : 0
2184 22:15:09.360285 ===================================
2185 22:15:09.363302 [ANA_INIT] >>>>>>>>>>>>>>
2186 22:15:09.366657 <<<<<< [CONFIGURE PHASE]: ANA_TX
2187 22:15:09.370373 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2188 22:15:09.373991 ===================================
2189 22:15:09.376912 data_rate = 2400,PCW = 0X5b00
2190 22:15:09.380539 ===================================
2191 22:15:09.384088 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2192 22:15:09.387083 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2193 22:15:09.393943 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2194 22:15:09.396815 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2195 22:15:09.400459 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2196 22:15:09.403494 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2197 22:15:09.407225 [ANA_INIT] flow start
2198 22:15:09.410019 [ANA_INIT] PLL >>>>>>>>
2199 22:15:09.410117 [ANA_INIT] PLL <<<<<<<<
2200 22:15:09.413653 [ANA_INIT] MIDPI >>>>>>>>
2201 22:15:09.417036 [ANA_INIT] MIDPI <<<<<<<<
2202 22:15:09.417151 [ANA_INIT] DLL >>>>>>>>
2203 22:15:09.420295 [ANA_INIT] DLL <<<<<<<<
2204 22:15:09.423658 [ANA_INIT] flow end
2205 22:15:09.426914 ============ LP4 DIFF to SE enter ============
2206 22:15:09.430291 ============ LP4 DIFF to SE exit ============
2207 22:15:09.433497 [ANA_INIT] <<<<<<<<<<<<<
2208 22:15:09.436975 [Flow] Enable top DCM control >>>>>
2209 22:15:09.440521 [Flow] Enable top DCM control <<<<<
2210 22:15:09.443929 Enable DLL master slave shuffle
2211 22:15:09.447241 ==============================================================
2212 22:15:09.450504 Gating Mode config
2213 22:15:09.457482 ==============================================================
2214 22:15:09.457585 Config description:
2215 22:15:09.467142 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2216 22:15:09.474162 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2217 22:15:09.477126 SELPH_MODE 0: By rank 1: By Phase
2218 22:15:09.484352 ==============================================================
2219 22:15:09.487057 GAT_TRACK_EN = 1
2220 22:15:09.490666 RX_GATING_MODE = 2
2221 22:15:09.494421 RX_GATING_TRACK_MODE = 2
2222 22:15:09.497342 SELPH_MODE = 1
2223 22:15:09.501165 PICG_EARLY_EN = 1
2224 22:15:09.501275 VALID_LAT_VALUE = 1
2225 22:15:09.507479 ==============================================================
2226 22:15:09.510362 Enter into Gating configuration >>>>
2227 22:15:09.514100 Exit from Gating configuration <<<<
2228 22:15:09.517516 Enter into DVFS_PRE_config >>>>>
2229 22:15:09.527272 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2230 22:15:09.530659 Exit from DVFS_PRE_config <<<<<
2231 22:15:09.534056 Enter into PICG configuration >>>>
2232 22:15:09.537166 Exit from PICG configuration <<<<
2233 22:15:09.540671 [RX_INPUT] configuration >>>>>
2234 22:15:09.544207 [RX_INPUT] configuration <<<<<
2235 22:15:09.547582 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2236 22:15:09.553904 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2237 22:15:09.560783 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2238 22:15:09.567485 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2239 22:15:09.574048 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2240 22:15:09.577760 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2241 22:15:09.584197 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2242 22:15:09.587836 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2243 22:15:09.590802 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2244 22:15:09.594299 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2245 22:15:09.597512 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2246 22:15:09.604623 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2247 22:15:09.607762 ===================================
2248 22:15:09.607859 LPDDR4 DRAM CONFIGURATION
2249 22:15:09.611427 ===================================
2250 22:15:09.614313 EX_ROW_EN[0] = 0x0
2251 22:15:09.617760 EX_ROW_EN[1] = 0x0
2252 22:15:09.617864 LP4Y_EN = 0x0
2253 22:15:09.621475 WORK_FSP = 0x0
2254 22:15:09.621583 WL = 0x4
2255 22:15:09.624327 RL = 0x4
2256 22:15:09.624427 BL = 0x2
2257 22:15:09.628032 RPST = 0x0
2258 22:15:09.628136 RD_PRE = 0x0
2259 22:15:09.631192 WR_PRE = 0x1
2260 22:15:09.631299 WR_PST = 0x0
2261 22:15:09.634584 DBI_WR = 0x0
2262 22:15:09.634693 DBI_RD = 0x0
2263 22:15:09.637896 OTF = 0x1
2264 22:15:09.641312 ===================================
2265 22:15:09.644664 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2266 22:15:09.648526 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2267 22:15:09.654737 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2268 22:15:09.658191 ===================================
2269 22:15:09.658291 LPDDR4 DRAM CONFIGURATION
2270 22:15:09.661539 ===================================
2271 22:15:09.664867 EX_ROW_EN[0] = 0x10
2272 22:15:09.664971 EX_ROW_EN[1] = 0x0
2273 22:15:09.668207 LP4Y_EN = 0x0
2274 22:15:09.668311 WORK_FSP = 0x0
2275 22:15:09.671152 WL = 0x4
2276 22:15:09.674552 RL = 0x4
2277 22:15:09.674651 BL = 0x2
2278 22:15:09.678106 RPST = 0x0
2279 22:15:09.678202 RD_PRE = 0x0
2280 22:15:09.681416 WR_PRE = 0x1
2281 22:15:09.681513 WR_PST = 0x0
2282 22:15:09.684656 DBI_WR = 0x0
2283 22:15:09.684752 DBI_RD = 0x0
2284 22:15:09.688348 OTF = 0x1
2285 22:15:09.691579 ===================================
2286 22:15:09.694972 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2287 22:15:09.697950 ==
2288 22:15:09.701705 Dram Type= 6, Freq= 0, CH_0, rank 0
2289 22:15:09.704756 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2290 22:15:09.704863 ==
2291 22:15:09.708207 [Duty_Offset_Calibration]
2292 22:15:09.708304 B0:2 B1:1 CA:1
2293 22:15:09.708400
2294 22:15:09.711385 [DutyScan_Calibration_Flow] k_type=0
2295 22:15:09.721255
2296 22:15:09.721359 ==CLK 0==
2297 22:15:09.724006 Final CLK duty delay cell = 0
2298 22:15:09.727728 [0] MAX Duty = 5187%(X100), DQS PI = 24
2299 22:15:09.730728 [0] MIN Duty = 4844%(X100), DQS PI = 48
2300 22:15:09.730823 [0] AVG Duty = 5015%(X100)
2301 22:15:09.734267
2302 22:15:09.737584 CH0 CLK Duty spec in!! Max-Min= 343%
2303 22:15:09.740715 [DutyScan_Calibration_Flow] ====Done====
2304 22:15:09.740816
2305 22:15:09.744187 [DutyScan_Calibration_Flow] k_type=1
2306 22:15:09.759135
2307 22:15:09.759236 ==DQS 0 ==
2308 22:15:09.762660 Final DQS duty delay cell = -4
2309 22:15:09.766019 [-4] MAX Duty = 5124%(X100), DQS PI = 24
2310 22:15:09.769274 [-4] MIN Duty = 4751%(X100), DQS PI = 0
2311 22:15:09.772618 [-4] AVG Duty = 4937%(X100)
2312 22:15:09.772724
2313 22:15:09.772812 ==DQS 1 ==
2314 22:15:09.776196 Final DQS duty delay cell = 0
2315 22:15:09.779028 [0] MAX Duty = 5156%(X100), DQS PI = 62
2316 22:15:09.782679 [0] MIN Duty = 5000%(X100), DQS PI = 36
2317 22:15:09.786065 [0] AVG Duty = 5078%(X100)
2318 22:15:09.786161
2319 22:15:09.789326 CH0 DQS 0 Duty spec in!! Max-Min= 373%
2320 22:15:09.789423
2321 22:15:09.792607 CH0 DQS 1 Duty spec in!! Max-Min= 156%
2322 22:15:09.796358 [DutyScan_Calibration_Flow] ====Done====
2323 22:15:09.796442
2324 22:15:09.799261 [DutyScan_Calibration_Flow] k_type=3
2325 22:15:09.816479
2326 22:15:09.816595 ==DQM 0 ==
2327 22:15:09.819518 Final DQM duty delay cell = 0
2328 22:15:09.822857 [0] MAX Duty = 5156%(X100), DQS PI = 30
2329 22:15:09.826479 [0] MIN Duty = 4906%(X100), DQS PI = 52
2330 22:15:09.829449 [0] AVG Duty = 5031%(X100)
2331 22:15:09.829545
2332 22:15:09.829644 ==DQM 1 ==
2333 22:15:09.833254 Final DQM duty delay cell = 0
2334 22:15:09.836101 [0] MAX Duty = 5124%(X100), DQS PI = 6
2335 22:15:09.840071 [0] MIN Duty = 5031%(X100), DQS PI = 36
2336 22:15:09.840167 [0] AVG Duty = 5077%(X100)
2337 22:15:09.840266
2338 22:15:09.846276 CH0 DQM 0 Duty spec in!! Max-Min= 250%
2339 22:15:09.846382
2340 22:15:09.849818 CH0 DQM 1 Duty spec in!! Max-Min= 93%
2341 22:15:09.853042 [DutyScan_Calibration_Flow] ====Done====
2342 22:15:09.853144
2343 22:15:09.856062 [DutyScan_Calibration_Flow] k_type=2
2344 22:15:09.872535
2345 22:15:09.872643 ==DQ 0 ==
2346 22:15:09.875861 Final DQ duty delay cell = 0
2347 22:15:09.879511 [0] MAX Duty = 5031%(X100), DQS PI = 24
2348 22:15:09.882996 [0] MIN Duty = 4906%(X100), DQS PI = 0
2349 22:15:09.883093 [0] AVG Duty = 4968%(X100)
2350 22:15:09.883183
2351 22:15:09.885868 ==DQ 1 ==
2352 22:15:09.889408 Final DQ duty delay cell = 0
2353 22:15:09.892814 [0] MAX Duty = 5093%(X100), DQS PI = 24
2354 22:15:09.896134 [0] MIN Duty = 4907%(X100), DQS PI = 36
2355 22:15:09.896216 [0] AVG Duty = 5000%(X100)
2356 22:15:09.896280
2357 22:15:09.899523 CH0 DQ 0 Duty spec in!! Max-Min= 125%
2358 22:15:09.899604
2359 22:15:09.902615 CH0 DQ 1 Duty spec in!! Max-Min= 186%
2360 22:15:09.909449 [DutyScan_Calibration_Flow] ====Done====
2361 22:15:09.909530 ==
2362 22:15:09.913291 Dram Type= 6, Freq= 0, CH_1, rank 0
2363 22:15:09.916503 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2364 22:15:09.916585 ==
2365 22:15:09.919504 [Duty_Offset_Calibration]
2366 22:15:09.919585 B0:1 B1:0 CA:0
2367 22:15:09.919649
2368 22:15:09.922985 [DutyScan_Calibration_Flow] k_type=0
2369 22:15:09.932292
2370 22:15:09.932372 ==CLK 0==
2371 22:15:09.935585 Final CLK duty delay cell = -4
2372 22:15:09.938455 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2373 22:15:09.942000 [-4] MIN Duty = 4907%(X100), DQS PI = 50
2374 22:15:09.945452 [-4] AVG Duty = 4969%(X100)
2375 22:15:09.945532
2376 22:15:09.948946 CH1 CLK Duty spec in!! Max-Min= 124%
2377 22:15:09.951827 [DutyScan_Calibration_Flow] ====Done====
2378 22:15:09.951908
2379 22:15:09.954963 [DutyScan_Calibration_Flow] k_type=1
2380 22:15:09.971345
2381 22:15:09.971441 ==DQS 0 ==
2382 22:15:09.975234 Final DQS duty delay cell = 0
2383 22:15:09.978814 [0] MAX Duty = 5062%(X100), DQS PI = 10
2384 22:15:09.981511 [0] MIN Duty = 4875%(X100), DQS PI = 0
2385 22:15:09.981595 [0] AVG Duty = 4968%(X100)
2386 22:15:09.985321
2387 22:15:09.985403 ==DQS 1 ==
2388 22:15:09.988243 Final DQS duty delay cell = 0
2389 22:15:09.991871 [0] MAX Duty = 5218%(X100), DQS PI = 20
2390 22:15:09.995151 [0] MIN Duty = 4969%(X100), DQS PI = 8
2391 22:15:09.995233 [0] AVG Duty = 5093%(X100)
2392 22:15:09.995299
2393 22:15:10.001543 CH1 DQS 0 Duty spec in!! Max-Min= 187%
2394 22:15:10.001626
2395 22:15:10.004999 CH1 DQS 1 Duty spec in!! Max-Min= 249%
2396 22:15:10.008296 [DutyScan_Calibration_Flow] ====Done====
2397 22:15:10.008378
2398 22:15:10.011954 [DutyScan_Calibration_Flow] k_type=3
2399 22:15:10.027948
2400 22:15:10.028031 ==DQM 0 ==
2401 22:15:10.031224 Final DQM duty delay cell = 0
2402 22:15:10.034767 [0] MAX Duty = 5156%(X100), DQS PI = 6
2403 22:15:10.037981 [0] MIN Duty = 5031%(X100), DQS PI = 0
2404 22:15:10.038109 [0] AVG Duty = 5093%(X100)
2405 22:15:10.038203
2406 22:15:10.041436 ==DQM 1 ==
2407 22:15:10.045260 Final DQM duty delay cell = 0
2408 22:15:10.047974 [0] MAX Duty = 5062%(X100), DQS PI = 28
2409 22:15:10.051533 [0] MIN Duty = 4907%(X100), DQS PI = 36
2410 22:15:10.051608 [0] AVG Duty = 4984%(X100)
2411 22:15:10.051670
2412 22:15:10.054898 CH1 DQM 0 Duty spec in!! Max-Min= 125%
2413 22:15:10.058486
2414 22:15:10.061333 CH1 DQM 1 Duty spec in!! Max-Min= 155%
2415 22:15:10.064789 [DutyScan_Calibration_Flow] ====Done====
2416 22:15:10.064871
2417 22:15:10.068113 [DutyScan_Calibration_Flow] k_type=2
2418 22:15:10.083745
2419 22:15:10.083827 ==DQ 0 ==
2420 22:15:10.087068 Final DQ duty delay cell = -4
2421 22:15:10.090810 [-4] MAX Duty = 5062%(X100), DQS PI = 8
2422 22:15:10.094089 [-4] MIN Duty = 4938%(X100), DQS PI = 0
2423 22:15:10.094171 [-4] AVG Duty = 5000%(X100)
2424 22:15:10.097313
2425 22:15:10.097395 ==DQ 1 ==
2426 22:15:10.100422 Final DQ duty delay cell = 0
2427 22:15:10.103708 [0] MAX Duty = 5125%(X100), DQS PI = 20
2428 22:15:10.107580 [0] MIN Duty = 4938%(X100), DQS PI = 34
2429 22:15:10.107664 [0] AVG Duty = 5031%(X100)
2430 22:15:10.107730
2431 22:15:10.110640 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2432 22:15:10.110721
2433 22:15:10.113952 CH1 DQ 1 Duty spec in!! Max-Min= 187%
2434 22:15:10.120429 [DutyScan_Calibration_Flow] ====Done====
2435 22:15:10.124390 nWR fixed to 30
2436 22:15:10.124472 [ModeRegInit_LP4] CH0 RK0
2437 22:15:10.127480 [ModeRegInit_LP4] CH0 RK1
2438 22:15:10.130503 [ModeRegInit_LP4] CH1 RK0
2439 22:15:10.130599 [ModeRegInit_LP4] CH1 RK1
2440 22:15:10.133947 match AC timing 7
2441 22:15:10.137532 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2442 22:15:10.140593 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2443 22:15:10.147229 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2444 22:15:10.150845 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2445 22:15:10.157701 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2446 22:15:10.157783 ==
2447 22:15:10.161072 Dram Type= 6, Freq= 0, CH_0, rank 0
2448 22:15:10.164014 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2449 22:15:10.164119 ==
2450 22:15:10.170654 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2451 22:15:10.174092 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2452 22:15:10.184138 [CA 0] Center 39 (8~70) winsize 63
2453 22:15:10.187104 [CA 1] Center 39 (8~70) winsize 63
2454 22:15:10.190450 [CA 2] Center 35 (5~66) winsize 62
2455 22:15:10.194126 [CA 3] Center 34 (4~65) winsize 62
2456 22:15:10.197598 [CA 4] Center 33 (3~64) winsize 62
2457 22:15:10.200674 [CA 5] Center 32 (3~62) winsize 60
2458 22:15:10.200756
2459 22:15:10.204710 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2460 22:15:10.204795
2461 22:15:10.207715 [CATrainingPosCal] consider 1 rank data
2462 22:15:10.211084 u2DelayCellTimex100 = 270/100 ps
2463 22:15:10.214238 CA0 delay=39 (8~70),Diff = 7 PI (33 cell)
2464 22:15:10.217656 CA1 delay=39 (8~70),Diff = 7 PI (33 cell)
2465 22:15:10.221196 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2466 22:15:10.227784 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2467 22:15:10.231126 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2468 22:15:10.234232 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2469 22:15:10.234313
2470 22:15:10.237749 CA PerBit enable=1, Macro0, CA PI delay=32
2471 22:15:10.237852
2472 22:15:10.241026 [CBTSetCACLKResult] CA Dly = 32
2473 22:15:10.241127 CS Dly: 6 (0~37)
2474 22:15:10.241213 ==
2475 22:15:10.243990 Dram Type= 6, Freq= 0, CH_0, rank 1
2476 22:15:10.251321 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2477 22:15:10.251456 ==
2478 22:15:10.254267 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2479 22:15:10.260583 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2480 22:15:10.269540 [CA 0] Center 38 (8~69) winsize 62
2481 22:15:10.273317 [CA 1] Center 38 (8~69) winsize 62
2482 22:15:10.276322 [CA 2] Center 35 (4~66) winsize 63
2483 22:15:10.279765 [CA 3] Center 34 (4~65) winsize 62
2484 22:15:10.283168 [CA 4] Center 33 (3~64) winsize 62
2485 22:15:10.286178 [CA 5] Center 32 (3~62) winsize 60
2486 22:15:10.286275
2487 22:15:10.289479 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2488 22:15:10.289581
2489 22:15:10.292717 [CATrainingPosCal] consider 2 rank data
2490 22:15:10.296060 u2DelayCellTimex100 = 270/100 ps
2491 22:15:10.299719 CA0 delay=38 (8~69),Diff = 6 PI (28 cell)
2492 22:15:10.302961 CA1 delay=38 (8~69),Diff = 6 PI (28 cell)
2493 22:15:10.309461 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2494 22:15:10.312946 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2495 22:15:10.316106 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2496 22:15:10.319672 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2497 22:15:10.319755
2498 22:15:10.323026 CA PerBit enable=1, Macro0, CA PI delay=32
2499 22:15:10.323109
2500 22:15:10.326550 [CBTSetCACLKResult] CA Dly = 32
2501 22:15:10.326633 CS Dly: 6 (0~38)
2502 22:15:10.326699
2503 22:15:10.329494 ----->DramcWriteLeveling(PI) begin...
2504 22:15:10.333060 ==
2505 22:15:10.336144 Dram Type= 6, Freq= 0, CH_0, rank 0
2506 22:15:10.339766 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2507 22:15:10.339849 ==
2508 22:15:10.343210 Write leveling (Byte 0): 33 => 33
2509 22:15:10.346182 Write leveling (Byte 1): 30 => 30
2510 22:15:10.350055 DramcWriteLeveling(PI) end<-----
2511 22:15:10.350138
2512 22:15:10.350202 ==
2513 22:15:10.352881 Dram Type= 6, Freq= 0, CH_0, rank 0
2514 22:15:10.356581 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2515 22:15:10.356665 ==
2516 22:15:10.359592 [Gating] SW mode calibration
2517 22:15:10.366575 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2518 22:15:10.369839 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2519 22:15:10.376432 0 15 0 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
2520 22:15:10.379426 0 15 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
2521 22:15:10.383130 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2522 22:15:10.390001 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2523 22:15:10.392901 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2524 22:15:10.396173 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2525 22:15:10.402768 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2526 22:15:10.406572 0 15 28 | B1->B0 | 3333 2727 | 1 0 | (1 1) (0 0)
2527 22:15:10.409958 1 0 0 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
2528 22:15:10.416557 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2529 22:15:10.419379 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2530 22:15:10.423016 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2531 22:15:10.429497 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2532 22:15:10.433188 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2533 22:15:10.436063 1 0 24 | B1->B0 | 2323 2c2b | 0 1 | (0 0) (0 0)
2534 22:15:10.442983 1 0 28 | B1->B0 | 2525 4545 | 0 0 | (0 0) (0 0)
2535 22:15:10.446227 1 1 0 | B1->B0 | 3737 4646 | 1 0 | (0 0) (0 0)
2536 22:15:10.449708 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2537 22:15:10.453187 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2538 22:15:10.459791 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2539 22:15:10.463448 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2540 22:15:10.466231 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2541 22:15:10.473118 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2542 22:15:10.476731 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2543 22:15:10.479655 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2544 22:15:10.486596 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2545 22:15:10.490161 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2546 22:15:10.493452 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2547 22:15:10.499998 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2548 22:15:10.503560 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2549 22:15:10.506634 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2550 22:15:10.513282 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2551 22:15:10.516714 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2552 22:15:10.520149 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2553 22:15:10.523477 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2554 22:15:10.530063 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2555 22:15:10.533395 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2556 22:15:10.536714 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2557 22:15:10.543808 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2558 22:15:10.546777 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2559 22:15:10.550607 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2560 22:15:10.553269 Total UI for P1: 0, mck2ui 16
2561 22:15:10.557120 best dqsien dly found for B0: ( 1, 3, 28)
2562 22:15:10.560045 Total UI for P1: 0, mck2ui 16
2563 22:15:10.563698 best dqsien dly found for B1: ( 1, 3, 30)
2564 22:15:10.566805 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2565 22:15:10.569867 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2566 22:15:10.569964
2567 22:15:10.576971 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2568 22:15:10.580029 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2569 22:15:10.580118 [Gating] SW calibration Done
2570 22:15:10.583347 ==
2571 22:15:10.586574 Dram Type= 6, Freq= 0, CH_0, rank 0
2572 22:15:10.589987 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2573 22:15:10.590085 ==
2574 22:15:10.590177 RX Vref Scan: 0
2575 22:15:10.590267
2576 22:15:10.592894 RX Vref 0 -> 0, step: 1
2577 22:15:10.592991
2578 22:15:10.596374 RX Delay -40 -> 252, step: 8
2579 22:15:10.600267 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2580 22:15:10.603656 iDelay=200, Bit 1, Center 123 (48 ~ 199) 152
2581 22:15:10.606656 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2582 22:15:10.613736 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2583 22:15:10.616907 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2584 22:15:10.620097 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2585 22:15:10.623564 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2586 22:15:10.626577 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2587 22:15:10.633181 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2588 22:15:10.636402 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
2589 22:15:10.639723 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2590 22:15:10.643110 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2591 22:15:10.646757 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2592 22:15:10.653602 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2593 22:15:10.656821 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2594 22:15:10.659948 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
2595 22:15:10.660020 ==
2596 22:15:10.663518 Dram Type= 6, Freq= 0, CH_0, rank 0
2597 22:15:10.667142 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2598 22:15:10.667241 ==
2599 22:15:10.669995 DQS Delay:
2600 22:15:10.670088 DQS0 = 0, DQS1 = 0
2601 22:15:10.673701 DQM Delay:
2602 22:15:10.673801 DQM0 = 121, DQM1 = 113
2603 22:15:10.673895 DQ Delay:
2604 22:15:10.680378 DQ0 =119, DQ1 =123, DQ2 =119, DQ3 =119
2605 22:15:10.683301 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2606 22:15:10.687189 DQ8 =99, DQ9 =107, DQ10 =111, DQ11 =107
2607 22:15:10.689997 DQ12 =115, DQ13 =123, DQ14 =123, DQ15 =119
2608 22:15:10.690103
2609 22:15:10.690192
2610 22:15:10.690278 ==
2611 22:15:10.693378 Dram Type= 6, Freq= 0, CH_0, rank 0
2612 22:15:10.696897 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2613 22:15:10.696998 ==
2614 22:15:10.697092
2615 22:15:10.697178
2616 22:15:10.699938 TX Vref Scan disable
2617 22:15:10.703610 == TX Byte 0 ==
2618 22:15:10.707173 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2619 22:15:10.709996 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2620 22:15:10.713484 == TX Byte 1 ==
2621 22:15:10.716839 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2622 22:15:10.720331 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2623 22:15:10.720413 ==
2624 22:15:10.723620 Dram Type= 6, Freq= 0, CH_0, rank 0
2625 22:15:10.726842 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2626 22:15:10.726945 ==
2627 22:15:10.740328 TX Vref=22, minBit 0, minWin=25, winSum=409
2628 22:15:10.743651 TX Vref=24, minBit 0, minWin=25, winSum=412
2629 22:15:10.746499 TX Vref=26, minBit 7, minWin=25, winSum=421
2630 22:15:10.749845 TX Vref=28, minBit 0, minWin=26, winSum=424
2631 22:15:10.753384 TX Vref=30, minBit 12, minWin=25, winSum=425
2632 22:15:10.760125 TX Vref=32, minBit 0, minWin=26, winSum=420
2633 22:15:10.763268 [TxChooseVref] Worse bit 0, Min win 26, Win sum 424, Final Vref 28
2634 22:15:10.763407
2635 22:15:10.766559 Final TX Range 1 Vref 28
2636 22:15:10.766641
2637 22:15:10.766706 ==
2638 22:15:10.770396 Dram Type= 6, Freq= 0, CH_0, rank 0
2639 22:15:10.773386 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2640 22:15:10.773469 ==
2641 22:15:10.773534
2642 22:15:10.776624
2643 22:15:10.776706 TX Vref Scan disable
2644 22:15:10.780069 == TX Byte 0 ==
2645 22:15:10.783802 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2646 22:15:10.786700 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2647 22:15:10.790042 == TX Byte 1 ==
2648 22:15:10.793717 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2649 22:15:10.796814 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2650 22:15:10.796896
2651 22:15:10.800443 [DATLAT]
2652 22:15:10.800525 Freq=1200, CH0 RK0
2653 22:15:10.800590
2654 22:15:10.803806 DATLAT Default: 0xd
2655 22:15:10.803887 0, 0xFFFF, sum = 0
2656 22:15:10.806870 1, 0xFFFF, sum = 0
2657 22:15:10.806954 2, 0xFFFF, sum = 0
2658 22:15:10.810368 3, 0xFFFF, sum = 0
2659 22:15:10.810452 4, 0xFFFF, sum = 0
2660 22:15:10.813444 5, 0xFFFF, sum = 0
2661 22:15:10.813527 6, 0xFFFF, sum = 0
2662 22:15:10.817048 7, 0xFFFF, sum = 0
2663 22:15:10.817130 8, 0xFFFF, sum = 0
2664 22:15:10.819830 9, 0xFFFF, sum = 0
2665 22:15:10.823474 10, 0xFFFF, sum = 0
2666 22:15:10.823557 11, 0xFFFF, sum = 0
2667 22:15:10.826611 12, 0x0, sum = 1
2668 22:15:10.826710 13, 0x0, sum = 2
2669 22:15:10.826777 14, 0x0, sum = 3
2670 22:15:10.829997 15, 0x0, sum = 4
2671 22:15:10.830080 best_step = 13
2672 22:15:10.830144
2673 22:15:10.830204 ==
2674 22:15:10.833721 Dram Type= 6, Freq= 0, CH_0, rank 0
2675 22:15:10.840106 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2676 22:15:10.840189 ==
2677 22:15:10.840253 RX Vref Scan: 1
2678 22:15:10.840313
2679 22:15:10.843595 Set Vref Range= 32 -> 127
2680 22:15:10.843680
2681 22:15:10.846694 RX Vref 32 -> 127, step: 1
2682 22:15:10.846776
2683 22:15:10.850065 RX Delay -13 -> 252, step: 4
2684 22:15:10.850147
2685 22:15:10.853942 Set Vref, RX VrefLevel [Byte0]: 32
2686 22:15:10.857466 [Byte1]: 32
2687 22:15:10.857542
2688 22:15:10.860336 Set Vref, RX VrefLevel [Byte0]: 33
2689 22:15:10.863572 [Byte1]: 33
2690 22:15:10.863647
2691 22:15:10.866885 Set Vref, RX VrefLevel [Byte0]: 34
2692 22:15:10.870271 [Byte1]: 34
2693 22:15:10.874250
2694 22:15:10.874325 Set Vref, RX VrefLevel [Byte0]: 35
2695 22:15:10.877281 [Byte1]: 35
2696 22:15:10.882008
2697 22:15:10.882081 Set Vref, RX VrefLevel [Byte0]: 36
2698 22:15:10.885946 [Byte1]: 36
2699 22:15:10.889862
2700 22:15:10.889939 Set Vref, RX VrefLevel [Byte0]: 37
2701 22:15:10.893610 [Byte1]: 37
2702 22:15:10.898138
2703 22:15:10.898211 Set Vref, RX VrefLevel [Byte0]: 38
2704 22:15:10.901039 [Byte1]: 38
2705 22:15:10.905972
2706 22:15:10.906040 Set Vref, RX VrefLevel [Byte0]: 39
2707 22:15:10.908952 [Byte1]: 39
2708 22:15:10.913679
2709 22:15:10.913748 Set Vref, RX VrefLevel [Byte0]: 40
2710 22:15:10.916889 [Byte1]: 40
2711 22:15:10.921553
2712 22:15:10.921637 Set Vref, RX VrefLevel [Byte0]: 41
2713 22:15:10.924708 [Byte1]: 41
2714 22:15:10.929713
2715 22:15:10.929785 Set Vref, RX VrefLevel [Byte0]: 42
2716 22:15:10.932698 [Byte1]: 42
2717 22:15:10.937442
2718 22:15:10.937520 Set Vref, RX VrefLevel [Byte0]: 43
2719 22:15:10.940836 [Byte1]: 43
2720 22:15:10.945350
2721 22:15:10.945427 Set Vref, RX VrefLevel [Byte0]: 44
2722 22:15:10.948633 [Byte1]: 44
2723 22:15:10.953279
2724 22:15:10.953356 Set Vref, RX VrefLevel [Byte0]: 45
2725 22:15:10.956155 [Byte1]: 45
2726 22:15:10.960981
2727 22:15:10.961071 Set Vref, RX VrefLevel [Byte0]: 46
2728 22:15:10.964429 [Byte1]: 46
2729 22:15:10.968814
2730 22:15:10.968885 Set Vref, RX VrefLevel [Byte0]: 47
2731 22:15:10.972158 [Byte1]: 47
2732 22:15:10.976580
2733 22:15:10.976658 Set Vref, RX VrefLevel [Byte0]: 48
2734 22:15:10.979897 [Byte1]: 48
2735 22:15:10.984727
2736 22:15:10.984804 Set Vref, RX VrefLevel [Byte0]: 49
2737 22:15:10.987702 [Byte1]: 49
2738 22:15:10.992696
2739 22:15:10.992770 Set Vref, RX VrefLevel [Byte0]: 50
2740 22:15:10.996196 [Byte1]: 50
2741 22:15:11.000289
2742 22:15:11.000373 Set Vref, RX VrefLevel [Byte0]: 51
2743 22:15:11.003867 [Byte1]: 51
2744 22:15:11.008186
2745 22:15:11.008269 Set Vref, RX VrefLevel [Byte0]: 52
2746 22:15:11.011496 [Byte1]: 52
2747 22:15:11.016329
2748 22:15:11.016411 Set Vref, RX VrefLevel [Byte0]: 53
2749 22:15:11.019347 [Byte1]: 53
2750 22:15:11.024201
2751 22:15:11.024305 Set Vref, RX VrefLevel [Byte0]: 54
2752 22:15:11.027812 [Byte1]: 54
2753 22:15:11.031746
2754 22:15:11.031842 Set Vref, RX VrefLevel [Byte0]: 55
2755 22:15:11.035680 [Byte1]: 55
2756 22:15:11.039682
2757 22:15:11.039755 Set Vref, RX VrefLevel [Byte0]: 56
2758 22:15:11.043550 [Byte1]: 56
2759 22:15:11.047527
2760 22:15:11.047626 Set Vref, RX VrefLevel [Byte0]: 57
2761 22:15:11.050874 [Byte1]: 57
2762 22:15:11.055447
2763 22:15:11.055527 Set Vref, RX VrefLevel [Byte0]: 58
2764 22:15:11.059041 [Byte1]: 58
2765 22:15:11.063696
2766 22:15:11.063769 Set Vref, RX VrefLevel [Byte0]: 59
2767 22:15:11.067165 [Byte1]: 59
2768 22:15:11.071192
2769 22:15:11.071314 Set Vref, RX VrefLevel [Byte0]: 60
2770 22:15:11.074402 [Byte1]: 60
2771 22:15:11.079480
2772 22:15:11.079598 Set Vref, RX VrefLevel [Byte0]: 61
2773 22:15:11.083061 [Byte1]: 61
2774 22:15:11.087203
2775 22:15:11.087340 Set Vref, RX VrefLevel [Byte0]: 62
2776 22:15:11.090625 [Byte1]: 62
2777 22:15:11.094849
2778 22:15:11.094966 Set Vref, RX VrefLevel [Byte0]: 63
2779 22:15:11.098442 [Byte1]: 63
2780 22:15:11.103038
2781 22:15:11.103143 Set Vref, RX VrefLevel [Byte0]: 64
2782 22:15:11.106548 [Byte1]: 64
2783 22:15:11.110946
2784 22:15:11.111044 Set Vref, RX VrefLevel [Byte0]: 65
2785 22:15:11.113914 [Byte1]: 65
2786 22:15:11.118754
2787 22:15:11.118830 Set Vref, RX VrefLevel [Byte0]: 66
2788 22:15:11.122117 [Byte1]: 66
2789 22:15:11.126361
2790 22:15:11.126442 Set Vref, RX VrefLevel [Byte0]: 67
2791 22:15:11.129723 [Byte1]: 67
2792 22:15:11.134628
2793 22:15:11.134708 Set Vref, RX VrefLevel [Byte0]: 68
2794 22:15:11.137628 [Byte1]: 68
2795 22:15:11.142179
2796 22:15:11.142259 Set Vref, RX VrefLevel [Byte0]: 69
2797 22:15:11.145655 [Byte1]: 69
2798 22:15:11.150369
2799 22:15:11.150450 Final RX Vref Byte 0 = 55 to rank0
2800 22:15:11.153382 Final RX Vref Byte 1 = 49 to rank0
2801 22:15:11.157444 Final RX Vref Byte 0 = 55 to rank1
2802 22:15:11.160437 Final RX Vref Byte 1 = 49 to rank1==
2803 22:15:11.163984 Dram Type= 6, Freq= 0, CH_0, rank 0
2804 22:15:11.170285 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2805 22:15:11.170368 ==
2806 22:15:11.170433 DQS Delay:
2807 22:15:11.170490 DQS0 = 0, DQS1 = 0
2808 22:15:11.173815 DQM Delay:
2809 22:15:11.173895 DQM0 = 120, DQM1 = 112
2810 22:15:11.177080 DQ Delay:
2811 22:15:11.180703 DQ0 =120, DQ1 =120, DQ2 =118, DQ3 =118
2812 22:15:11.184058 DQ4 =122, DQ5 =112, DQ6 =126, DQ7 =126
2813 22:15:11.187067 DQ8 =100, DQ9 =102, DQ10 =112, DQ11 =106
2814 22:15:11.190410 DQ12 =116, DQ13 =116, DQ14 =124, DQ15 =120
2815 22:15:11.190491
2816 22:15:11.190555
2817 22:15:11.197208 [DQSOSCAuto] RK0, (LSB)MR18= 0x1811, (MSB)MR19= 0x404, tDQSOscB0 = 403 ps tDQSOscB1 = 400 ps
2818 22:15:11.200609 CH0 RK0: MR19=404, MR18=1811
2819 22:15:11.206945 CH0_RK0: MR19=0x404, MR18=0x1811, DQSOSC=400, MR23=63, INC=40, DEC=27
2820 22:15:11.207028
2821 22:15:11.210928 ----->DramcWriteLeveling(PI) begin...
2822 22:15:11.211012 ==
2823 22:15:11.213831 Dram Type= 6, Freq= 0, CH_0, rank 1
2824 22:15:11.217374 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2825 22:15:11.217457 ==
2826 22:15:11.220591 Write leveling (Byte 0): 34 => 34
2827 22:15:11.223947 Write leveling (Byte 1): 27 => 27
2828 22:15:11.227002 DramcWriteLeveling(PI) end<-----
2829 22:15:11.227103
2830 22:15:11.227205 ==
2831 22:15:11.230665 Dram Type= 6, Freq= 0, CH_0, rank 1
2832 22:15:11.237160 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2833 22:15:11.237268 ==
2834 22:15:11.237368 [Gating] SW mode calibration
2835 22:15:11.247476 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2836 22:15:11.250590 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2837 22:15:11.254205 0 15 0 | B1->B0 | 3434 2f2e | 0 1 | (0 0) (0 0)
2838 22:15:11.260370 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2839 22:15:11.264100 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2840 22:15:11.267052 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2841 22:15:11.274175 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2842 22:15:11.277549 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2843 22:15:11.280658 0 15 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
2844 22:15:11.287721 0 15 28 | B1->B0 | 2f2f 2d2d | 1 1 | (1 0) (1 0)
2845 22:15:11.290970 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2846 22:15:11.293978 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2847 22:15:11.300496 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2848 22:15:11.304189 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2849 22:15:11.307362 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2850 22:15:11.313898 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2851 22:15:11.317196 1 0 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
2852 22:15:11.320747 1 0 28 | B1->B0 | 3737 3939 | 1 1 | (0 0) (0 0)
2853 22:15:11.324165 1 1 0 | B1->B0 | 4646 4545 | 0 1 | (0 0) (0 0)
2854 22:15:11.330739 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2855 22:15:11.333965 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2856 22:15:11.337592 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2857 22:15:11.344186 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2858 22:15:11.347613 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2859 22:15:11.350540 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2860 22:15:11.357384 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2861 22:15:11.361013 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2862 22:15:11.364096 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2863 22:15:11.370551 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2864 22:15:11.374163 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2865 22:15:11.377484 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2866 22:15:11.383965 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2867 22:15:11.387789 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2868 22:15:11.390899 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2869 22:15:11.394075 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2870 22:15:11.400785 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2871 22:15:11.404356 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2872 22:15:11.407555 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2873 22:15:11.414224 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2874 22:15:11.417806 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2875 22:15:11.421125 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2876 22:15:11.427823 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2877 22:15:11.431241 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2878 22:15:11.435035 Total UI for P1: 0, mck2ui 16
2879 22:15:11.437985 best dqsien dly found for B0: ( 1, 3, 28)
2880 22:15:11.440975 Total UI for P1: 0, mck2ui 16
2881 22:15:11.444852 best dqsien dly found for B1: ( 1, 3, 28)
2882 22:15:11.448003 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2883 22:15:11.451455 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2884 22:15:11.451530
2885 22:15:11.454667 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2886 22:15:11.458323 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2887 22:15:11.461086 [Gating] SW calibration Done
2888 22:15:11.461160 ==
2889 22:15:11.464656 Dram Type= 6, Freq= 0, CH_0, rank 1
2890 22:15:11.468273 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2891 22:15:11.468347 ==
2892 22:15:11.471264 RX Vref Scan: 0
2893 22:15:11.471339
2894 22:15:11.474361 RX Vref 0 -> 0, step: 1
2895 22:15:11.474447
2896 22:15:11.474516 RX Delay -40 -> 252, step: 8
2897 22:15:11.481073 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2898 22:15:11.484469 iDelay=200, Bit 1, Center 123 (56 ~ 191) 136
2899 22:15:11.488009 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2900 22:15:11.491429 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2901 22:15:11.495006 iDelay=200, Bit 4, Center 127 (56 ~ 199) 144
2902 22:15:11.501401 iDelay=200, Bit 5, Center 119 (48 ~ 191) 144
2903 22:15:11.504632 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2904 22:15:11.508105 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2905 22:15:11.511474 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2906 22:15:11.514849 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
2907 22:15:11.518103 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2908 22:15:11.524793 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2909 22:15:11.528199 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2910 22:15:11.531473 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2911 22:15:11.534737 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2912 22:15:11.541430 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
2913 22:15:11.541516 ==
2914 22:15:11.544507 Dram Type= 6, Freq= 0, CH_0, rank 1
2915 22:15:11.548045 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2916 22:15:11.548146 ==
2917 22:15:11.548236 DQS Delay:
2918 22:15:11.551735 DQS0 = 0, DQS1 = 0
2919 22:15:11.551839 DQM Delay:
2920 22:15:11.554744 DQM0 = 122, DQM1 = 113
2921 22:15:11.554825 DQ Delay:
2922 22:15:11.557893 DQ0 =119, DQ1 =123, DQ2 =119, DQ3 =119
2923 22:15:11.561304 DQ4 =127, DQ5 =119, DQ6 =127, DQ7 =127
2924 22:15:11.564475 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
2925 22:15:11.567956 DQ12 =115, DQ13 =123, DQ14 =123, DQ15 =123
2926 22:15:11.568042
2927 22:15:11.568117
2928 22:15:11.568213 ==
2929 22:15:11.571479 Dram Type= 6, Freq= 0, CH_0, rank 1
2930 22:15:11.578243 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2931 22:15:11.578328 ==
2932 22:15:11.578393
2933 22:15:11.578450
2934 22:15:11.578512 TX Vref Scan disable
2935 22:15:11.581873 == TX Byte 0 ==
2936 22:15:11.585437 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2937 22:15:11.588947 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2938 22:15:11.591847 == TX Byte 1 ==
2939 22:15:11.594977 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2940 22:15:11.599034 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2941 22:15:11.601856 ==
2942 22:15:11.605386 Dram Type= 6, Freq= 0, CH_0, rank 1
2943 22:15:11.608466 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2944 22:15:11.608537 ==
2945 22:15:11.620831 TX Vref=22, minBit 2, minWin=25, winSum=409
2946 22:15:11.624124 TX Vref=24, minBit 2, minWin=25, winSum=416
2947 22:15:11.627154 TX Vref=26, minBit 0, minWin=26, winSum=421
2948 22:15:11.630599 TX Vref=28, minBit 13, minWin=25, winSum=423
2949 22:15:11.633983 TX Vref=30, minBit 2, minWin=26, winSum=423
2950 22:15:11.636889 TX Vref=32, minBit 0, minWin=26, winSum=423
2951 22:15:11.643903 [TxChooseVref] Worse bit 2, Min win 26, Win sum 423, Final Vref 30
2952 22:15:11.643989
2953 22:15:11.647004 Final TX Range 1 Vref 30
2954 22:15:11.647107
2955 22:15:11.647195 ==
2956 22:15:11.650471 Dram Type= 6, Freq= 0, CH_0, rank 1
2957 22:15:11.654087 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2958 22:15:11.654157 ==
2959 22:15:11.654215
2960 22:15:11.654278
2961 22:15:11.657127 TX Vref Scan disable
2962 22:15:11.660764 == TX Byte 0 ==
2963 22:15:11.663846 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2964 22:15:11.666907 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2965 22:15:11.670542 == TX Byte 1 ==
2966 22:15:11.673783 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2967 22:15:11.677330 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2968 22:15:11.677406
2969 22:15:11.680483 [DATLAT]
2970 22:15:11.680562 Freq=1200, CH0 RK1
2971 22:15:11.680627
2972 22:15:11.684065 DATLAT Default: 0xd
2973 22:15:11.684136 0, 0xFFFF, sum = 0
2974 22:15:11.687906 1, 0xFFFF, sum = 0
2975 22:15:11.687977 2, 0xFFFF, sum = 0
2976 22:15:11.690778 3, 0xFFFF, sum = 0
2977 22:15:11.690849 4, 0xFFFF, sum = 0
2978 22:15:11.693941 5, 0xFFFF, sum = 0
2979 22:15:11.694020 6, 0xFFFF, sum = 0
2980 22:15:11.697693 7, 0xFFFF, sum = 0
2981 22:15:11.697771 8, 0xFFFF, sum = 0
2982 22:15:11.700832 9, 0xFFFF, sum = 0
2983 22:15:11.700905 10, 0xFFFF, sum = 0
2984 22:15:11.704072 11, 0xFFFF, sum = 0
2985 22:15:11.704145 12, 0x0, sum = 1
2986 22:15:11.707309 13, 0x0, sum = 2
2987 22:15:11.707456 14, 0x0, sum = 3
2988 22:15:11.711080 15, 0x0, sum = 4
2989 22:15:11.711152 best_step = 13
2990 22:15:11.711211
2991 22:15:11.711272 ==
2992 22:15:11.714078 Dram Type= 6, Freq= 0, CH_0, rank 1
2993 22:15:11.720739 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2994 22:15:11.720818 ==
2995 22:15:11.720881 RX Vref Scan: 0
2996 22:15:11.720977
2997 22:15:11.723959 RX Vref 0 -> 0, step: 1
2998 22:15:11.724035
2999 22:15:11.727266 RX Delay -13 -> 252, step: 4
3000 22:15:11.730934 iDelay=195, Bit 0, Center 120 (51 ~ 190) 140
3001 22:15:11.734284 iDelay=195, Bit 1, Center 120 (55 ~ 186) 132
3002 22:15:11.740804 iDelay=195, Bit 2, Center 118 (51 ~ 186) 136
3003 22:15:11.744259 iDelay=195, Bit 3, Center 118 (51 ~ 186) 136
3004 22:15:11.747745 iDelay=195, Bit 4, Center 122 (55 ~ 190) 136
3005 22:15:11.750975 iDelay=195, Bit 5, Center 116 (51 ~ 182) 132
3006 22:15:11.754542 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3007 22:15:11.758027 iDelay=195, Bit 7, Center 126 (59 ~ 194) 136
3008 22:15:11.764302 iDelay=195, Bit 8, Center 100 (35 ~ 166) 132
3009 22:15:11.767877 iDelay=195, Bit 9, Center 98 (31 ~ 166) 136
3010 22:15:11.770874 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3011 22:15:11.774507 iDelay=195, Bit 11, Center 104 (39 ~ 170) 132
3012 22:15:11.777464 iDelay=195, Bit 12, Center 116 (55 ~ 178) 124
3013 22:15:11.784044 iDelay=195, Bit 13, Center 116 (55 ~ 178) 124
3014 22:15:11.787686 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3015 22:15:11.790691 iDelay=195, Bit 15, Center 120 (55 ~ 186) 132
3016 22:15:11.790762 ==
3017 22:15:11.794218 Dram Type= 6, Freq= 0, CH_0, rank 1
3018 22:15:11.797715 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3019 22:15:11.797795 ==
3020 22:15:11.801321 DQS Delay:
3021 22:15:11.801394 DQS0 = 0, DQS1 = 0
3022 22:15:11.804548 DQM Delay:
3023 22:15:11.804617 DQM0 = 120, DQM1 = 110
3024 22:15:11.808010 DQ Delay:
3025 22:15:11.811142 DQ0 =120, DQ1 =120, DQ2 =118, DQ3 =118
3026 22:15:11.814347 DQ4 =122, DQ5 =116, DQ6 =126, DQ7 =126
3027 22:15:11.817845 DQ8 =100, DQ9 =98, DQ10 =110, DQ11 =104
3028 22:15:11.821057 DQ12 =116, DQ13 =116, DQ14 =122, DQ15 =120
3029 22:15:11.821142
3030 22:15:11.821210
3031 22:15:11.827612 [DQSOSCAuto] RK1, (LSB)MR18= 0xff0, (MSB)MR19= 0x403, tDQSOscB0 = 416 ps tDQSOscB1 = 404 ps
3032 22:15:11.831136 CH0 RK1: MR19=403, MR18=FF0
3033 22:15:11.837833 CH0_RK1: MR19=0x403, MR18=0xFF0, DQSOSC=404, MR23=63, INC=40, DEC=26
3034 22:15:11.840648 [RxdqsGatingPostProcess] freq 1200
3035 22:15:11.844004 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3036 22:15:11.847677 best DQS0 dly(2T, 0.5T) = (0, 11)
3037 22:15:11.850727 best DQS1 dly(2T, 0.5T) = (0, 11)
3038 22:15:11.854494 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3039 22:15:11.857552 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3040 22:15:11.860767 best DQS0 dly(2T, 0.5T) = (0, 11)
3041 22:15:11.864394 best DQS1 dly(2T, 0.5T) = (0, 11)
3042 22:15:11.867844 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3043 22:15:11.871396 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3044 22:15:11.874466 Pre-setting of DQS Precalculation
3045 22:15:11.877939 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3046 22:15:11.878045 ==
3047 22:15:11.881137 Dram Type= 6, Freq= 0, CH_1, rank 0
3048 22:15:11.888156 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3049 22:15:11.888234 ==
3050 22:15:11.891292 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3051 22:15:11.897741 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3052 22:15:11.906472 [CA 0] Center 37 (7~68) winsize 62
3053 22:15:11.910163 [CA 1] Center 37 (7~68) winsize 62
3054 22:15:11.913572 [CA 2] Center 35 (5~65) winsize 61
3055 22:15:11.916815 [CA 3] Center 34 (4~65) winsize 62
3056 22:15:11.919612 [CA 4] Center 34 (4~64) winsize 61
3057 22:15:11.923301 [CA 5] Center 33 (3~63) winsize 61
3058 22:15:11.923422
3059 22:15:11.926765 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3060 22:15:11.926845
3061 22:15:11.930087 [CATrainingPosCal] consider 1 rank data
3062 22:15:11.933385 u2DelayCellTimex100 = 270/100 ps
3063 22:15:11.936704 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3064 22:15:11.940243 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3065 22:15:11.946484 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3066 22:15:11.949836 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3067 22:15:11.953215 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3068 22:15:11.956393 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3069 22:15:11.956469
3070 22:15:11.960029 CA PerBit enable=1, Macro0, CA PI delay=33
3071 22:15:11.960106
3072 22:15:11.963600 [CBTSetCACLKResult] CA Dly = 33
3073 22:15:11.963671 CS Dly: 8 (0~39)
3074 22:15:11.963731 ==
3075 22:15:11.966419 Dram Type= 6, Freq= 0, CH_1, rank 1
3076 22:15:11.973396 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3077 22:15:11.973469 ==
3078 22:15:11.977004 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3079 22:15:11.983487 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3080 22:15:11.992391 [CA 0] Center 37 (7~68) winsize 62
3081 22:15:11.995514 [CA 1] Center 37 (7~68) winsize 62
3082 22:15:11.999071 [CA 2] Center 35 (5~65) winsize 61
3083 22:15:12.002201 [CA 3] Center 34 (4~65) winsize 62
3084 22:15:12.005622 [CA 4] Center 35 (5~65) winsize 61
3085 22:15:12.009198 [CA 5] Center 34 (4~64) winsize 61
3086 22:15:12.009273
3087 22:15:12.012112 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3088 22:15:12.012192
3089 22:15:12.015599 [CATrainingPosCal] consider 2 rank data
3090 22:15:12.019100 u2DelayCellTimex100 = 270/100 ps
3091 22:15:12.022148 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3092 22:15:12.025865 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3093 22:15:12.032292 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3094 22:15:12.035602 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3095 22:15:12.039098 CA4 delay=34 (5~64),Diff = 1 PI (4 cell)
3096 22:15:12.042226 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3097 22:15:12.042320
3098 22:15:12.045824 CA PerBit enable=1, Macro0, CA PI delay=33
3099 22:15:12.045921
3100 22:15:12.048993 [CBTSetCACLKResult] CA Dly = 33
3101 22:15:12.049073 CS Dly: 9 (0~41)
3102 22:15:12.049137
3103 22:15:12.052345 ----->DramcWriteLeveling(PI) begin...
3104 22:15:12.052421 ==
3105 22:15:12.055690 Dram Type= 6, Freq= 0, CH_1, rank 0
3106 22:15:12.062514 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3107 22:15:12.062598 ==
3108 22:15:12.065881 Write leveling (Byte 0): 27 => 27
3109 22:15:12.069267 Write leveling (Byte 1): 27 => 27
3110 22:15:12.069348 DramcWriteLeveling(PI) end<-----
3111 22:15:12.072360
3112 22:15:12.072437 ==
3113 22:15:12.075634 Dram Type= 6, Freq= 0, CH_1, rank 0
3114 22:15:12.079087 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3115 22:15:12.079164 ==
3116 22:15:12.082238 [Gating] SW mode calibration
3117 22:15:12.089303 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3118 22:15:12.092543 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3119 22:15:12.098952 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3120 22:15:12.102664 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3121 22:15:12.105645 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3122 22:15:12.112509 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3123 22:15:12.115762 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3124 22:15:12.119249 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3125 22:15:12.125985 0 15 24 | B1->B0 | 3434 2b2b | 1 0 | (1 0) (0 0)
3126 22:15:12.128873 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
3127 22:15:12.132525 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3128 22:15:12.139363 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3129 22:15:12.142600 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3130 22:15:12.146077 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3131 22:15:12.152380 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3132 22:15:12.155863 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3133 22:15:12.159255 1 0 24 | B1->B0 | 2f2f 3e3e | 1 0 | (0 0) (0 0)
3134 22:15:12.162451 1 0 28 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
3135 22:15:12.169092 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3136 22:15:12.172671 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3137 22:15:12.176245 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3138 22:15:12.182812 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3139 22:15:12.186120 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3140 22:15:12.189630 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3141 22:15:12.196128 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3142 22:15:12.199063 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3143 22:15:12.202679 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3144 22:15:12.209352 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3145 22:15:12.212607 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3146 22:15:12.215744 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3147 22:15:12.222529 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3148 22:15:12.226185 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3149 22:15:12.229065 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3150 22:15:12.232504 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3151 22:15:12.239038 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3152 22:15:12.242510 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3153 22:15:12.246064 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3154 22:15:12.252696 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3155 22:15:12.256325 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3156 22:15:12.259160 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3157 22:15:12.265974 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3158 22:15:12.269361 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3159 22:15:12.272794 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3160 22:15:12.276108 Total UI for P1: 0, mck2ui 16
3161 22:15:12.279522 best dqsien dly found for B0: ( 1, 3, 26)
3162 22:15:12.283277 Total UI for P1: 0, mck2ui 16
3163 22:15:12.286316 best dqsien dly found for B1: ( 1, 3, 26)
3164 22:15:12.289413 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3165 22:15:12.292782 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3166 22:15:12.292883
3167 22:15:12.296401 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3168 22:15:12.303250 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3169 22:15:12.303394 [Gating] SW calibration Done
3170 22:15:12.303458 ==
3171 22:15:12.305998 Dram Type= 6, Freq= 0, CH_1, rank 0
3172 22:15:12.312658 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3173 22:15:12.312757 ==
3174 22:15:12.312825 RX Vref Scan: 0
3175 22:15:12.312887
3176 22:15:12.316007 RX Vref 0 -> 0, step: 1
3177 22:15:12.316093
3178 22:15:12.319540 RX Delay -40 -> 252, step: 8
3179 22:15:12.322719 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3180 22:15:12.326556 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3181 22:15:12.329423 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3182 22:15:12.336442 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3183 22:15:12.339961 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3184 22:15:12.343119 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3185 22:15:12.346514 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3186 22:15:12.349940 iDelay=200, Bit 7, Center 123 (56 ~ 191) 136
3187 22:15:12.353311 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3188 22:15:12.360047 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3189 22:15:12.362958 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3190 22:15:12.366691 iDelay=200, Bit 11, Center 111 (48 ~ 175) 128
3191 22:15:12.369531 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3192 22:15:12.372929 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3193 22:15:12.380185 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3194 22:15:12.383389 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3195 22:15:12.383472 ==
3196 22:15:12.386269 Dram Type= 6, Freq= 0, CH_1, rank 0
3197 22:15:12.390093 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3198 22:15:12.390176 ==
3199 22:15:12.393081 DQS Delay:
3200 22:15:12.393162 DQS0 = 0, DQS1 = 0
3201 22:15:12.393227 DQM Delay:
3202 22:15:12.396557 DQM0 = 120, DQM1 = 116
3203 22:15:12.396651 DQ Delay:
3204 22:15:12.400065 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3205 22:15:12.403036 DQ4 =119, DQ5 =127, DQ6 =131, DQ7 =123
3206 22:15:12.406621 DQ8 =103, DQ9 =107, DQ10 =115, DQ11 =111
3207 22:15:12.413064 DQ12 =123, DQ13 =127, DQ14 =123, DQ15 =123
3208 22:15:12.413146
3209 22:15:12.413210
3210 22:15:12.413268 ==
3211 22:15:12.416725 Dram Type= 6, Freq= 0, CH_1, rank 0
3212 22:15:12.419732 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3213 22:15:12.419835 ==
3214 22:15:12.419914
3215 22:15:12.419974
3216 22:15:12.422913 TX Vref Scan disable
3217 22:15:12.422994 == TX Byte 0 ==
3218 22:15:12.430219 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3219 22:15:12.433051 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3220 22:15:12.433132 == TX Byte 1 ==
3221 22:15:12.439905 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3222 22:15:12.443080 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3223 22:15:12.443162 ==
3224 22:15:12.446695 Dram Type= 6, Freq= 0, CH_1, rank 0
3225 22:15:12.450119 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3226 22:15:12.450217 ==
3227 22:15:12.462394 TX Vref=22, minBit 9, minWin=24, winSum=410
3228 22:15:12.465817 TX Vref=24, minBit 9, minWin=24, winSum=416
3229 22:15:12.468908 TX Vref=26, minBit 1, minWin=25, winSum=420
3230 22:15:12.472479 TX Vref=28, minBit 1, minWin=26, winSum=426
3231 22:15:12.475941 TX Vref=30, minBit 10, minWin=25, winSum=429
3232 22:15:12.482301 TX Vref=32, minBit 10, minWin=25, winSum=428
3233 22:15:12.485631 [TxChooseVref] Worse bit 1, Min win 26, Win sum 426, Final Vref 28
3234 22:15:12.485727
3235 22:15:12.489540 Final TX Range 1 Vref 28
3236 22:15:12.489623
3237 22:15:12.489687 ==
3238 22:15:12.492673 Dram Type= 6, Freq= 0, CH_1, rank 0
3239 22:15:12.496209 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3240 22:15:12.496324 ==
3241 22:15:12.496420
3242 22:15:12.496512
3243 22:15:12.499223 TX Vref Scan disable
3244 22:15:12.502483 == TX Byte 0 ==
3245 22:15:12.505823 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3246 22:15:12.509375 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3247 22:15:12.512531 == TX Byte 1 ==
3248 22:15:12.515726 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3249 22:15:12.519138 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3250 22:15:12.519219
3251 22:15:12.522927 [DATLAT]
3252 22:15:12.523009 Freq=1200, CH1 RK0
3253 22:15:12.523075
3254 22:15:12.526139 DATLAT Default: 0xd
3255 22:15:12.526261 0, 0xFFFF, sum = 0
3256 22:15:12.529299 1, 0xFFFF, sum = 0
3257 22:15:12.529381 2, 0xFFFF, sum = 0
3258 22:15:12.532972 3, 0xFFFF, sum = 0
3259 22:15:12.533054 4, 0xFFFF, sum = 0
3260 22:15:12.536353 5, 0xFFFF, sum = 0
3261 22:15:12.536434 6, 0xFFFF, sum = 0
3262 22:15:12.539647 7, 0xFFFF, sum = 0
3263 22:15:12.539725 8, 0xFFFF, sum = 0
3264 22:15:12.542839 9, 0xFFFF, sum = 0
3265 22:15:12.542917 10, 0xFFFF, sum = 0
3266 22:15:12.546249 11, 0xFFFF, sum = 0
3267 22:15:12.546325 12, 0x0, sum = 1
3268 22:15:12.549192 13, 0x0, sum = 2
3269 22:15:12.549267 14, 0x0, sum = 3
3270 22:15:12.553007 15, 0x0, sum = 4
3271 22:15:12.553090 best_step = 13
3272 22:15:12.553154
3273 22:15:12.553241 ==
3274 22:15:12.556039 Dram Type= 6, Freq= 0, CH_1, rank 0
3275 22:15:12.563144 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3276 22:15:12.563251 ==
3277 22:15:12.563319 RX Vref Scan: 1
3278 22:15:12.563410
3279 22:15:12.566466 Set Vref Range= 32 -> 127
3280 22:15:12.566566
3281 22:15:12.569824 RX Vref 32 -> 127, step: 1
3282 22:15:12.569908
3283 22:15:12.569974 RX Delay -5 -> 252, step: 4
3284 22:15:12.570054
3285 22:15:12.573118 Set Vref, RX VrefLevel [Byte0]: 32
3286 22:15:12.576185 [Byte1]: 32
3287 22:15:12.580503
3288 22:15:12.580587 Set Vref, RX VrefLevel [Byte0]: 33
3289 22:15:12.584093 [Byte1]: 33
3290 22:15:12.588296
3291 22:15:12.588380 Set Vref, RX VrefLevel [Byte0]: 34
3292 22:15:12.591731 [Byte1]: 34
3293 22:15:12.596034
3294 22:15:12.596134 Set Vref, RX VrefLevel [Byte0]: 35
3295 22:15:12.599519 [Byte1]: 35
3296 22:15:12.604379
3297 22:15:12.604563 Set Vref, RX VrefLevel [Byte0]: 36
3298 22:15:12.607260 [Byte1]: 36
3299 22:15:12.612047
3300 22:15:12.612173 Set Vref, RX VrefLevel [Byte0]: 37
3301 22:15:12.615060 [Byte1]: 37
3302 22:15:12.619617
3303 22:15:12.619724 Set Vref, RX VrefLevel [Byte0]: 38
3304 22:15:12.623378 [Byte1]: 38
3305 22:15:12.627855
3306 22:15:12.627937 Set Vref, RX VrefLevel [Byte0]: 39
3307 22:15:12.630872 [Byte1]: 39
3308 22:15:12.635606
3309 22:15:12.635688 Set Vref, RX VrefLevel [Byte0]: 40
3310 22:15:12.638687 [Byte1]: 40
3311 22:15:12.643805
3312 22:15:12.643886 Set Vref, RX VrefLevel [Byte0]: 41
3313 22:15:12.646619 [Byte1]: 41
3314 22:15:12.650959
3315 22:15:12.651041 Set Vref, RX VrefLevel [Byte0]: 42
3316 22:15:12.654414 [Byte1]: 42
3317 22:15:12.659445
3318 22:15:12.659526 Set Vref, RX VrefLevel [Byte0]: 43
3319 22:15:12.662508 [Byte1]: 43
3320 22:15:12.667001
3321 22:15:12.667093 Set Vref, RX VrefLevel [Byte0]: 44
3322 22:15:12.670383 [Byte1]: 44
3323 22:15:12.674806
3324 22:15:12.674891 Set Vref, RX VrefLevel [Byte0]: 45
3325 22:15:12.678248 [Byte1]: 45
3326 22:15:12.682636
3327 22:15:12.682720 Set Vref, RX VrefLevel [Byte0]: 46
3328 22:15:12.685713 [Byte1]: 46
3329 22:15:12.690791
3330 22:15:12.690874 Set Vref, RX VrefLevel [Byte0]: 47
3331 22:15:12.693547 [Byte1]: 47
3332 22:15:12.698443
3333 22:15:12.698518 Set Vref, RX VrefLevel [Byte0]: 48
3334 22:15:12.701748 [Byte1]: 48
3335 22:15:12.706077
3336 22:15:12.706180 Set Vref, RX VrefLevel [Byte0]: 49
3337 22:15:12.709531 [Byte1]: 49
3338 22:15:12.713960
3339 22:15:12.714066 Set Vref, RX VrefLevel [Byte0]: 50
3340 22:15:12.717453 [Byte1]: 50
3341 22:15:12.722175
3342 22:15:12.722289 Set Vref, RX VrefLevel [Byte0]: 51
3343 22:15:12.725099 [Byte1]: 51
3344 22:15:12.729862
3345 22:15:12.729960 Set Vref, RX VrefLevel [Byte0]: 52
3346 22:15:12.732813 [Byte1]: 52
3347 22:15:12.737636
3348 22:15:12.737710 Set Vref, RX VrefLevel [Byte0]: 53
3349 22:15:12.740872 [Byte1]: 53
3350 22:15:12.745622
3351 22:15:12.745695 Set Vref, RX VrefLevel [Byte0]: 54
3352 22:15:12.748581 [Byte1]: 54
3353 22:15:12.753283
3354 22:15:12.753385 Set Vref, RX VrefLevel [Byte0]: 55
3355 22:15:12.756843 [Byte1]: 55
3356 22:15:12.761242
3357 22:15:12.761317 Set Vref, RX VrefLevel [Byte0]: 56
3358 22:15:12.764515 [Byte1]: 56
3359 22:15:12.768928
3360 22:15:12.769018 Set Vref, RX VrefLevel [Byte0]: 57
3361 22:15:12.772149 [Byte1]: 57
3362 22:15:12.776505
3363 22:15:12.776585 Set Vref, RX VrefLevel [Byte0]: 58
3364 22:15:12.779812 [Byte1]: 58
3365 22:15:12.784523
3366 22:15:12.784600 Set Vref, RX VrefLevel [Byte0]: 59
3367 22:15:12.787874 [Byte1]: 59
3368 22:15:12.792287
3369 22:15:12.792359 Set Vref, RX VrefLevel [Byte0]: 60
3370 22:15:12.795557 [Byte1]: 60
3371 22:15:12.800365
3372 22:15:12.800447 Set Vref, RX VrefLevel [Byte0]: 61
3373 22:15:12.803353 [Byte1]: 61
3374 22:15:12.808163
3375 22:15:12.808270 Set Vref, RX VrefLevel [Byte0]: 62
3376 22:15:12.811576 [Byte1]: 62
3377 22:15:12.816343
3378 22:15:12.816441 Set Vref, RX VrefLevel [Byte0]: 63
3379 22:15:12.819194 [Byte1]: 63
3380 22:15:12.823925
3381 22:15:12.824007 Set Vref, RX VrefLevel [Byte0]: 64
3382 22:15:12.827483 [Byte1]: 64
3383 22:15:12.832148
3384 22:15:12.832232 Set Vref, RX VrefLevel [Byte0]: 65
3385 22:15:12.834896 [Byte1]: 65
3386 22:15:12.839897
3387 22:15:12.840044 Set Vref, RX VrefLevel [Byte0]: 66
3388 22:15:12.842814 [Byte1]: 66
3389 22:15:12.847921
3390 22:15:12.848044 Set Vref, RX VrefLevel [Byte0]: 67
3391 22:15:12.850878 [Byte1]: 67
3392 22:15:12.855562
3393 22:15:12.855676 Set Vref, RX VrefLevel [Byte0]: 68
3394 22:15:12.858446 [Byte1]: 68
3395 22:15:12.863362
3396 22:15:12.863456 Set Vref, RX VrefLevel [Byte0]: 69
3397 22:15:12.866380 [Byte1]: 69
3398 22:15:12.871306
3399 22:15:12.871442 Final RX Vref Byte 0 = 54 to rank0
3400 22:15:12.874573 Final RX Vref Byte 1 = 51 to rank0
3401 22:15:12.877501 Final RX Vref Byte 0 = 54 to rank1
3402 22:15:12.880953 Final RX Vref Byte 1 = 51 to rank1==
3403 22:15:12.884460 Dram Type= 6, Freq= 0, CH_1, rank 0
3404 22:15:12.888009 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3405 22:15:12.891159 ==
3406 22:15:12.891243 DQS Delay:
3407 22:15:12.891309 DQS0 = 0, DQS1 = 0
3408 22:15:12.894516 DQM Delay:
3409 22:15:12.894598 DQM0 = 120, DQM1 = 116
3410 22:15:12.897827 DQ Delay:
3411 22:15:12.901343 DQ0 =124, DQ1 =114, DQ2 =110, DQ3 =116
3412 22:15:12.904662 DQ4 =118, DQ5 =128, DQ6 =130, DQ7 =120
3413 22:15:12.907918 DQ8 =104, DQ9 =106, DQ10 =118, DQ11 =108
3414 22:15:12.911295 DQ12 =124, DQ13 =124, DQ14 =124, DQ15 =126
3415 22:15:12.911393
3416 22:15:12.911459
3417 22:15:12.918032 [DQSOSCAuto] RK0, (LSB)MR18= 0x214, (MSB)MR19= 0x404, tDQSOscB0 = 402 ps tDQSOscB1 = 409 ps
3418 22:15:12.921589 CH1 RK0: MR19=404, MR18=214
3419 22:15:12.927858 CH1_RK0: MR19=0x404, MR18=0x214, DQSOSC=402, MR23=63, INC=40, DEC=27
3420 22:15:12.927944
3421 22:15:12.931128 ----->DramcWriteLeveling(PI) begin...
3422 22:15:12.931213 ==
3423 22:15:12.934879 Dram Type= 6, Freq= 0, CH_1, rank 1
3424 22:15:12.937934 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3425 22:15:12.938046 ==
3426 22:15:12.941101 Write leveling (Byte 0): 25 => 25
3427 22:15:12.944573 Write leveling (Byte 1): 29 => 29
3428 22:15:12.947853 DramcWriteLeveling(PI) end<-----
3429 22:15:12.947973
3430 22:15:12.948072 ==
3431 22:15:12.951197 Dram Type= 6, Freq= 0, CH_1, rank 1
3432 22:15:12.954802 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3433 22:15:12.958114 ==
3434 22:15:12.958197 [Gating] SW mode calibration
3435 22:15:12.964895 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3436 22:15:12.972041 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3437 22:15:12.974965 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3438 22:15:12.981628 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3439 22:15:12.985112 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3440 22:15:12.988682 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3441 22:15:12.994782 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3442 22:15:12.998063 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
3443 22:15:13.001902 0 15 24 | B1->B0 | 2727 3333 | 0 0 | (0 0) (0 0)
3444 22:15:13.005021 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
3445 22:15:13.011624 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3446 22:15:13.014857 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3447 22:15:13.018158 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3448 22:15:13.024622 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3449 22:15:13.028577 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3450 22:15:13.031505 1 0 20 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
3451 22:15:13.038646 1 0 24 | B1->B0 | 4343 2727 | 0 0 | (0 0) (0 0)
3452 22:15:13.042147 1 0 28 | B1->B0 | 4646 4343 | 0 0 | (0 0) (0 0)
3453 22:15:13.044705 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3454 22:15:13.051645 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3455 22:15:13.054615 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3456 22:15:13.058282 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3457 22:15:13.064721 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3458 22:15:13.068254 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3459 22:15:13.071332 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3460 22:15:13.078003 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3461 22:15:13.081100 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3462 22:15:13.084944 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3463 22:15:13.091647 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3464 22:15:13.094432 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3465 22:15:13.098120 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3466 22:15:13.104348 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3467 22:15:13.108300 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3468 22:15:13.110942 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3469 22:15:13.117690 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3470 22:15:13.121296 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3471 22:15:13.124613 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3472 22:15:13.131149 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3473 22:15:13.134261 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3474 22:15:13.137722 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3475 22:15:13.140894 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3476 22:15:13.144376 Total UI for P1: 0, mck2ui 16
3477 22:15:13.147812 best dqsien dly found for B1: ( 1, 3, 20)
3478 22:15:13.154310 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3479 22:15:13.157424 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3480 22:15:13.160687 Total UI for P1: 0, mck2ui 16
3481 22:15:13.164516 best dqsien dly found for B0: ( 1, 3, 26)
3482 22:15:13.167572 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3483 22:15:13.170888 best DQS1 dly(MCK, UI, PI) = (1, 3, 20)
3484 22:15:13.170969
3485 22:15:13.174357 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3486 22:15:13.177342 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 20)
3487 22:15:13.181141 [Gating] SW calibration Done
3488 22:15:13.181223 ==
3489 22:15:13.184740 Dram Type= 6, Freq= 0, CH_1, rank 1
3490 22:15:13.191472 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3491 22:15:13.191553 ==
3492 22:15:13.191617 RX Vref Scan: 0
3493 22:15:13.191676
3494 22:15:13.194436 RX Vref 0 -> 0, step: 1
3495 22:15:13.194532
3496 22:15:13.197190 RX Delay -40 -> 252, step: 8
3497 22:15:13.200729 iDelay=200, Bit 0, Center 127 (64 ~ 191) 128
3498 22:15:13.203912 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
3499 22:15:13.207493 iDelay=200, Bit 2, Center 111 (48 ~ 175) 128
3500 22:15:13.214073 iDelay=200, Bit 3, Center 119 (56 ~ 183) 128
3501 22:15:13.217415 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3502 22:15:13.220613 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3503 22:15:13.224103 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3504 22:15:13.227583 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3505 22:15:13.233582 iDelay=200, Bit 8, Center 107 (40 ~ 175) 136
3506 22:15:13.236942 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3507 22:15:13.240101 iDelay=200, Bit 10, Center 119 (48 ~ 191) 144
3508 22:15:13.243504 iDelay=200, Bit 11, Center 115 (48 ~ 183) 136
3509 22:15:13.247067 iDelay=200, Bit 12, Center 127 (56 ~ 199) 144
3510 22:15:13.253619 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3511 22:15:13.257098 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3512 22:15:13.260457 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3513 22:15:13.260539 ==
3514 22:15:13.263779 Dram Type= 6, Freq= 0, CH_1, rank 1
3515 22:15:13.267168 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3516 22:15:13.270539 ==
3517 22:15:13.270625 DQS Delay:
3518 22:15:13.270693 DQS0 = 0, DQS1 = 0
3519 22:15:13.273478 DQM Delay:
3520 22:15:13.273550 DQM0 = 121, DQM1 = 118
3521 22:15:13.276970 DQ Delay:
3522 22:15:13.279968 DQ0 =127, DQ1 =119, DQ2 =111, DQ3 =119
3523 22:15:13.283133 DQ4 =115, DQ5 =131, DQ6 =131, DQ7 =119
3524 22:15:13.286699 DQ8 =107, DQ9 =107, DQ10 =119, DQ11 =115
3525 22:15:13.290220 DQ12 =127, DQ13 =127, DQ14 =123, DQ15 =123
3526 22:15:13.290306
3527 22:15:13.290369
3528 22:15:13.290426 ==
3529 22:15:13.293371 Dram Type= 6, Freq= 0, CH_1, rank 1
3530 22:15:13.297077 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3531 22:15:13.297157 ==
3532 22:15:13.297217
3533 22:15:13.299856
3534 22:15:13.299929 TX Vref Scan disable
3535 22:15:13.303387 == TX Byte 0 ==
3536 22:15:13.307015 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3537 22:15:13.310196 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3538 22:15:13.313569 == TX Byte 1 ==
3539 22:15:13.316686 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3540 22:15:13.320157 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3541 22:15:13.320261 ==
3542 22:15:13.323404 Dram Type= 6, Freq= 0, CH_1, rank 1
3543 22:15:13.329942 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3544 22:15:13.330019 ==
3545 22:15:13.340393 TX Vref=22, minBit 1, minWin=25, winSum=417
3546 22:15:13.343790 TX Vref=24, minBit 2, minWin=26, winSum=425
3547 22:15:13.346720 TX Vref=26, minBit 2, minWin=26, winSum=427
3548 22:15:13.350272 TX Vref=28, minBit 10, minWin=25, winSum=432
3549 22:15:13.353495 TX Vref=30, minBit 9, minWin=26, winSum=435
3550 22:15:13.360243 TX Vref=32, minBit 9, minWin=26, winSum=435
3551 22:15:13.363397 [TxChooseVref] Worse bit 9, Min win 26, Win sum 435, Final Vref 30
3552 22:15:13.363473
3553 22:15:13.366995 Final TX Range 1 Vref 30
3554 22:15:13.367070
3555 22:15:13.367142 ==
3556 22:15:13.370569 Dram Type= 6, Freq= 0, CH_1, rank 1
3557 22:15:13.373162 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3558 22:15:13.376514 ==
3559 22:15:13.376636
3560 22:15:13.376730
3561 22:15:13.376855 TX Vref Scan disable
3562 22:15:13.380331 == TX Byte 0 ==
3563 22:15:13.383296 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3564 22:15:13.390021 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3565 22:15:13.390104 == TX Byte 1 ==
3566 22:15:13.393056 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3567 22:15:13.399768 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3568 22:15:13.399847
3569 22:15:13.399909 [DATLAT]
3570 22:15:13.399973 Freq=1200, CH1 RK1
3571 22:15:13.400034
3572 22:15:13.403412 DATLAT Default: 0xd
3573 22:15:13.406667 0, 0xFFFF, sum = 0
3574 22:15:13.406757 1, 0xFFFF, sum = 0
3575 22:15:13.409667 2, 0xFFFF, sum = 0
3576 22:15:13.409743 3, 0xFFFF, sum = 0
3577 22:15:13.413485 4, 0xFFFF, sum = 0
3578 22:15:13.413559 5, 0xFFFF, sum = 0
3579 22:15:13.416698 6, 0xFFFF, sum = 0
3580 22:15:13.416779 7, 0xFFFF, sum = 0
3581 22:15:13.420418 8, 0xFFFF, sum = 0
3582 22:15:13.420530 9, 0xFFFF, sum = 0
3583 22:15:13.423438 10, 0xFFFF, sum = 0
3584 22:15:13.423526 11, 0xFFFF, sum = 0
3585 22:15:13.426792 12, 0x0, sum = 1
3586 22:15:13.426866 13, 0x0, sum = 2
3587 22:15:13.429806 14, 0x0, sum = 3
3588 22:15:13.429877 15, 0x0, sum = 4
3589 22:15:13.433272 best_step = 13
3590 22:15:13.433344
3591 22:15:13.433414 ==
3592 22:15:13.436389 Dram Type= 6, Freq= 0, CH_1, rank 1
3593 22:15:13.440116 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3594 22:15:13.440193 ==
3595 22:15:13.440255 RX Vref Scan: 0
3596 22:15:13.440313
3597 22:15:13.443316 RX Vref 0 -> 0, step: 1
3598 22:15:13.443441
3599 22:15:13.446789 RX Delay -5 -> 252, step: 4
3600 22:15:13.449900 iDelay=195, Bit 0, Center 122 (59 ~ 186) 128
3601 22:15:13.456739 iDelay=195, Bit 1, Center 116 (55 ~ 178) 124
3602 22:15:13.459799 iDelay=195, Bit 2, Center 110 (51 ~ 170) 120
3603 22:15:13.463157 iDelay=195, Bit 3, Center 118 (59 ~ 178) 120
3604 22:15:13.466292 iDelay=195, Bit 4, Center 116 (55 ~ 178) 124
3605 22:15:13.469775 iDelay=195, Bit 5, Center 130 (67 ~ 194) 128
3606 22:15:13.476323 iDelay=195, Bit 6, Center 130 (67 ~ 194) 128
3607 22:15:13.479713 iDelay=195, Bit 7, Center 120 (59 ~ 182) 124
3608 22:15:13.483081 iDelay=195, Bit 8, Center 106 (47 ~ 166) 120
3609 22:15:13.486276 iDelay=195, Bit 9, Center 108 (47 ~ 170) 124
3610 22:15:13.489549 iDelay=195, Bit 10, Center 116 (55 ~ 178) 124
3611 22:15:13.496473 iDelay=195, Bit 11, Center 112 (51 ~ 174) 124
3612 22:15:13.499928 iDelay=195, Bit 12, Center 126 (63 ~ 190) 128
3613 22:15:13.502941 iDelay=195, Bit 13, Center 124 (67 ~ 182) 116
3614 22:15:13.506542 iDelay=195, Bit 14, Center 124 (67 ~ 182) 116
3615 22:15:13.509439 iDelay=195, Bit 15, Center 126 (67 ~ 186) 120
3616 22:15:13.512972 ==
3617 22:15:13.516885 Dram Type= 6, Freq= 0, CH_1, rank 1
3618 22:15:13.519657 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3619 22:15:13.519740 ==
3620 22:15:13.519806 DQS Delay:
3621 22:15:13.522743 DQS0 = 0, DQS1 = 0
3622 22:15:13.522825 DQM Delay:
3623 22:15:13.526019 DQM0 = 120, DQM1 = 117
3624 22:15:13.526132 DQ Delay:
3625 22:15:13.529517 DQ0 =122, DQ1 =116, DQ2 =110, DQ3 =118
3626 22:15:13.533054 DQ4 =116, DQ5 =130, DQ6 =130, DQ7 =120
3627 22:15:13.536085 DQ8 =106, DQ9 =108, DQ10 =116, DQ11 =112
3628 22:15:13.539746 DQ12 =126, DQ13 =124, DQ14 =124, DQ15 =126
3629 22:15:13.539820
3630 22:15:13.539881
3631 22:15:13.549200 [DQSOSCAuto] RK1, (LSB)MR18= 0x13f1, (MSB)MR19= 0x403, tDQSOscB0 = 416 ps tDQSOscB1 = 402 ps
3632 22:15:13.552861 CH1 RK1: MR19=403, MR18=13F1
3633 22:15:13.556107 CH1_RK1: MR19=0x403, MR18=0x13F1, DQSOSC=402, MR23=63, INC=40, DEC=27
3634 22:15:13.559529 [RxdqsGatingPostProcess] freq 1200
3635 22:15:13.566132 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3636 22:15:13.569216 best DQS0 dly(2T, 0.5T) = (0, 11)
3637 22:15:13.572558 best DQS1 dly(2T, 0.5T) = (0, 11)
3638 22:15:13.576144 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3639 22:15:13.579103 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3640 22:15:13.582649 best DQS0 dly(2T, 0.5T) = (0, 11)
3641 22:15:13.586019 best DQS1 dly(2T, 0.5T) = (0, 11)
3642 22:15:13.589317 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3643 22:15:13.592800 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3644 22:15:13.596074 Pre-setting of DQS Precalculation
3645 22:15:13.599597 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3646 22:15:13.606141 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3647 22:15:13.612339 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3648 22:15:13.612448
3649 22:15:13.612539
3650 22:15:13.615772 [Calibration Summary] 2400 Mbps
3651 22:15:13.619437 CH 0, Rank 0
3652 22:15:13.619534 SW Impedance : PASS
3653 22:15:13.622848 DUTY Scan : NO K
3654 22:15:13.625879 ZQ Calibration : PASS
3655 22:15:13.625977 Jitter Meter : NO K
3656 22:15:13.629383 CBT Training : PASS
3657 22:15:13.632495 Write leveling : PASS
3658 22:15:13.632567 RX DQS gating : PASS
3659 22:15:13.635623 RX DQ/DQS(RDDQC) : PASS
3660 22:15:13.639106 TX DQ/DQS : PASS
3661 22:15:13.639212 RX DATLAT : PASS
3662 22:15:13.642648 RX DQ/DQS(Engine): PASS
3663 22:15:13.642746 TX OE : NO K
3664 22:15:13.645738 All Pass.
3665 22:15:13.645839
3666 22:15:13.645930 CH 0, Rank 1
3667 22:15:13.649022 SW Impedance : PASS
3668 22:15:13.649119 DUTY Scan : NO K
3669 22:15:13.652581 ZQ Calibration : PASS
3670 22:15:13.655684 Jitter Meter : NO K
3671 22:15:13.655790 CBT Training : PASS
3672 22:15:13.659235 Write leveling : PASS
3673 22:15:13.662331 RX DQS gating : PASS
3674 22:15:13.662435 RX DQ/DQS(RDDQC) : PASS
3675 22:15:13.665636 TX DQ/DQS : PASS
3676 22:15:13.669045 RX DATLAT : PASS
3677 22:15:13.669142 RX DQ/DQS(Engine): PASS
3678 22:15:13.672828 TX OE : NO K
3679 22:15:13.672910 All Pass.
3680 22:15:13.672973
3681 22:15:13.675935 CH 1, Rank 0
3682 22:15:13.676006 SW Impedance : PASS
3683 22:15:13.678734 DUTY Scan : NO K
3684 22:15:13.682112 ZQ Calibration : PASS
3685 22:15:13.682191 Jitter Meter : NO K
3686 22:15:13.685715 CBT Training : PASS
3687 22:15:13.688963 Write leveling : PASS
3688 22:15:13.689056 RX DQS gating : PASS
3689 22:15:13.692219 RX DQ/DQS(RDDQC) : PASS
3690 22:15:13.692302 TX DQ/DQS : PASS
3691 22:15:13.695655 RX DATLAT : PASS
3692 22:15:13.699100 RX DQ/DQS(Engine): PASS
3693 22:15:13.699183 TX OE : NO K
3694 22:15:13.702402 All Pass.
3695 22:15:13.702502
3696 22:15:13.702591 CH 1, Rank 1
3697 22:15:13.705608 SW Impedance : PASS
3698 22:15:13.705707 DUTY Scan : NO K
3699 22:15:13.709098 ZQ Calibration : PASS
3700 22:15:13.712329 Jitter Meter : NO K
3701 22:15:13.712434 CBT Training : PASS
3702 22:15:13.715872 Write leveling : PASS
3703 22:15:13.719301 RX DQS gating : PASS
3704 22:15:13.719436 RX DQ/DQS(RDDQC) : PASS
3705 22:15:13.722203 TX DQ/DQS : PASS
3706 22:15:13.725458 RX DATLAT : PASS
3707 22:15:13.725535 RX DQ/DQS(Engine): PASS
3708 22:15:13.728986 TX OE : NO K
3709 22:15:13.729069 All Pass.
3710 22:15:13.729135
3711 22:15:13.732477 DramC Write-DBI off
3712 22:15:13.735630 PER_BANK_REFRESH: Hybrid Mode
3713 22:15:13.735713 TX_TRACKING: ON
3714 22:15:13.745601 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3715 22:15:13.749103 [FAST_K] Save calibration result to emmc
3716 22:15:13.752093 dramc_set_vcore_voltage set vcore to 650000
3717 22:15:13.755440 Read voltage for 600, 5
3718 22:15:13.755527 Vio18 = 0
3719 22:15:13.755593 Vcore = 650000
3720 22:15:13.758975 Vdram = 0
3721 22:15:13.759057 Vddq = 0
3722 22:15:13.759122 Vmddr = 0
3723 22:15:13.765751 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3724 22:15:13.769011 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3725 22:15:13.772303 MEM_TYPE=3, freq_sel=19
3726 22:15:13.775358 sv_algorithm_assistance_LP4_1600
3727 22:15:13.778552 ============ PULL DRAM RESETB DOWN ============
3728 22:15:13.782128 ========== PULL DRAM RESETB DOWN end =========
3729 22:15:13.788719 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3730 22:15:13.792159 ===================================
3731 22:15:13.792242 LPDDR4 DRAM CONFIGURATION
3732 22:15:13.795211 ===================================
3733 22:15:13.798481 EX_ROW_EN[0] = 0x0
3734 22:15:13.802438 EX_ROW_EN[1] = 0x0
3735 22:15:13.802551 LP4Y_EN = 0x0
3736 22:15:13.805290 WORK_FSP = 0x0
3737 22:15:13.805374 WL = 0x2
3738 22:15:13.808517 RL = 0x2
3739 22:15:13.808600 BL = 0x2
3740 22:15:13.812334 RPST = 0x0
3741 22:15:13.812416 RD_PRE = 0x0
3742 22:15:13.815236 WR_PRE = 0x1
3743 22:15:13.815379 WR_PST = 0x0
3744 22:15:13.818864 DBI_WR = 0x0
3745 22:15:13.818946 DBI_RD = 0x0
3746 22:15:13.822201 OTF = 0x1
3747 22:15:13.825034 ===================================
3748 22:15:13.828768 ===================================
3749 22:15:13.828852 ANA top config
3750 22:15:13.832347 ===================================
3751 22:15:13.834967 DLL_ASYNC_EN = 0
3752 22:15:13.838747 ALL_SLAVE_EN = 1
3753 22:15:13.841768 NEW_RANK_MODE = 1
3754 22:15:13.841852 DLL_IDLE_MODE = 1
3755 22:15:13.844992 LP45_APHY_COMB_EN = 1
3756 22:15:13.848650 TX_ODT_DIS = 1
3757 22:15:13.851722 NEW_8X_MODE = 1
3758 22:15:13.855168 ===================================
3759 22:15:13.858556 ===================================
3760 22:15:13.861501 data_rate = 1200
3761 22:15:13.861584 CKR = 1
3762 22:15:13.864809 DQ_P2S_RATIO = 8
3763 22:15:13.868546 ===================================
3764 22:15:13.871468 CA_P2S_RATIO = 8
3765 22:15:13.874863 DQ_CA_OPEN = 0
3766 22:15:13.878340 DQ_SEMI_OPEN = 0
3767 22:15:13.881565 CA_SEMI_OPEN = 0
3768 22:15:13.881665 CA_FULL_RATE = 0
3769 22:15:13.885245 DQ_CKDIV4_EN = 1
3770 22:15:13.888266 CA_CKDIV4_EN = 1
3771 22:15:13.891430 CA_PREDIV_EN = 0
3772 22:15:13.894627 PH8_DLY = 0
3773 22:15:13.897932 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3774 22:15:13.898036 DQ_AAMCK_DIV = 4
3775 22:15:13.902007 CA_AAMCK_DIV = 4
3776 22:15:13.904779 CA_ADMCK_DIV = 4
3777 22:15:13.907965 DQ_TRACK_CA_EN = 0
3778 22:15:13.911504 CA_PICK = 600
3779 22:15:13.914715 CA_MCKIO = 600
3780 22:15:13.914798 MCKIO_SEMI = 0
3781 22:15:13.918297 PLL_FREQ = 2288
3782 22:15:13.921447 DQ_UI_PI_RATIO = 32
3783 22:15:13.924467 CA_UI_PI_RATIO = 0
3784 22:15:13.928057 ===================================
3785 22:15:13.931662 ===================================
3786 22:15:13.934681 memory_type:LPDDR4
3787 22:15:13.934796 GP_NUM : 10
3788 22:15:13.938228 SRAM_EN : 1
3789 22:15:13.941515 MD32_EN : 0
3790 22:15:13.944296 ===================================
3791 22:15:13.944378 [ANA_INIT] >>>>>>>>>>>>>>
3792 22:15:13.947820 <<<<<< [CONFIGURE PHASE]: ANA_TX
3793 22:15:13.951561 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3794 22:15:13.954412 ===================================
3795 22:15:13.958377 data_rate = 1200,PCW = 0X5800
3796 22:15:13.960993 ===================================
3797 22:15:13.964650 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3798 22:15:13.971012 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3799 22:15:13.974585 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3800 22:15:13.980955 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3801 22:15:13.984592 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3802 22:15:13.987495 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3803 22:15:13.987595 [ANA_INIT] flow start
3804 22:15:13.990941 [ANA_INIT] PLL >>>>>>>>
3805 22:15:13.994304 [ANA_INIT] PLL <<<<<<<<
3806 22:15:13.997731 [ANA_INIT] MIDPI >>>>>>>>
3807 22:15:13.997834 [ANA_INIT] MIDPI <<<<<<<<
3808 22:15:14.001228 [ANA_INIT] DLL >>>>>>>>
3809 22:15:14.001303 [ANA_INIT] flow end
3810 22:15:14.007747 ============ LP4 DIFF to SE enter ============
3811 22:15:14.011256 ============ LP4 DIFF to SE exit ============
3812 22:15:14.014431 [ANA_INIT] <<<<<<<<<<<<<
3813 22:15:14.017507 [Flow] Enable top DCM control >>>>>
3814 22:15:14.020837 [Flow] Enable top DCM control <<<<<
3815 22:15:14.024182 Enable DLL master slave shuffle
3816 22:15:14.027810 ==============================================================
3817 22:15:14.031253 Gating Mode config
3818 22:15:14.034306 ==============================================================
3819 22:15:14.037277 Config description:
3820 22:15:14.047710 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3821 22:15:14.054461 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3822 22:15:14.058015 SELPH_MODE 0: By rank 1: By Phase
3823 22:15:14.064172 ==============================================================
3824 22:15:14.067741 GAT_TRACK_EN = 1
3825 22:15:14.070669 RX_GATING_MODE = 2
3826 22:15:14.074218 RX_GATING_TRACK_MODE = 2
3827 22:15:14.077497 SELPH_MODE = 1
3828 22:15:14.077581 PICG_EARLY_EN = 1
3829 22:15:14.080820 VALID_LAT_VALUE = 1
3830 22:15:14.087482 ==============================================================
3831 22:15:14.090539 Enter into Gating configuration >>>>
3832 22:15:14.094118 Exit from Gating configuration <<<<
3833 22:15:14.097528 Enter into DVFS_PRE_config >>>>>
3834 22:15:14.107042 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3835 22:15:14.110360 Exit from DVFS_PRE_config <<<<<
3836 22:15:14.113702 Enter into PICG configuration >>>>
3837 22:15:14.117129 Exit from PICG configuration <<<<
3838 22:15:14.120268 [RX_INPUT] configuration >>>>>
3839 22:15:14.123754 [RX_INPUT] configuration <<<<<
3840 22:15:14.126946 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3841 22:15:14.133728 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3842 22:15:14.140166 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3843 22:15:14.147502 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3844 22:15:14.153874 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3845 22:15:14.160574 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3846 22:15:14.163485 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3847 22:15:14.167238 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3848 22:15:14.170118 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3849 22:15:14.173705 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3850 22:15:14.180620 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3851 22:15:14.184209 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3852 22:15:14.187086 ===================================
3853 22:15:14.190465 LPDDR4 DRAM CONFIGURATION
3854 22:15:14.194089 ===================================
3855 22:15:14.194165 EX_ROW_EN[0] = 0x0
3856 22:15:14.197123 EX_ROW_EN[1] = 0x0
3857 22:15:14.197198 LP4Y_EN = 0x0
3858 22:15:14.200238 WORK_FSP = 0x0
3859 22:15:14.200319 WL = 0x2
3860 22:15:14.203754 RL = 0x2
3861 22:15:14.203830 BL = 0x2
3862 22:15:14.207283 RPST = 0x0
3863 22:15:14.207380 RD_PRE = 0x0
3864 22:15:14.210597 WR_PRE = 0x1
3865 22:15:14.210678 WR_PST = 0x0
3866 22:15:14.213850 DBI_WR = 0x0
3867 22:15:14.217219 DBI_RD = 0x0
3868 22:15:14.217292 OTF = 0x1
3869 22:15:14.220231 ===================================
3870 22:15:14.224106 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3871 22:15:14.227096 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3872 22:15:14.233676 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3873 22:15:14.237268 ===================================
3874 22:15:14.237349 LPDDR4 DRAM CONFIGURATION
3875 22:15:14.240317 ===================================
3876 22:15:14.243560 EX_ROW_EN[0] = 0x10
3877 22:15:14.247398 EX_ROW_EN[1] = 0x0
3878 22:15:14.247478 LP4Y_EN = 0x0
3879 22:15:14.250370 WORK_FSP = 0x0
3880 22:15:14.250443 WL = 0x2
3881 22:15:14.253923 RL = 0x2
3882 22:15:14.254007 BL = 0x2
3883 22:15:14.256974 RPST = 0x0
3884 22:15:14.257057 RD_PRE = 0x0
3885 22:15:14.260293 WR_PRE = 0x1
3886 22:15:14.260376 WR_PST = 0x0
3887 22:15:14.264097 DBI_WR = 0x0
3888 22:15:14.264185 DBI_RD = 0x0
3889 22:15:14.266997 OTF = 0x1
3890 22:15:14.270521 ===================================
3891 22:15:14.277077 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3892 22:15:14.280718 nWR fixed to 30
3893 22:15:14.283958 [ModeRegInit_LP4] CH0 RK0
3894 22:15:14.284041 [ModeRegInit_LP4] CH0 RK1
3895 22:15:14.287239 [ModeRegInit_LP4] CH1 RK0
3896 22:15:14.290405 [ModeRegInit_LP4] CH1 RK1
3897 22:15:14.290488 match AC timing 17
3898 22:15:14.297439 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3899 22:15:14.300214 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3900 22:15:14.304166 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3901 22:15:14.310431 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3902 22:15:14.313520 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3903 22:15:14.313603 ==
3904 22:15:14.317163 Dram Type= 6, Freq= 0, CH_0, rank 0
3905 22:15:14.320491 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3906 22:15:14.320574 ==
3907 22:15:14.327265 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3908 22:15:14.333444 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3909 22:15:14.336829 [CA 0] Center 35 (5~66) winsize 62
3910 22:15:14.340302 [CA 1] Center 35 (5~66) winsize 62
3911 22:15:14.343741 [CA 2] Center 33 (3~64) winsize 62
3912 22:15:14.347058 [CA 3] Center 33 (2~64) winsize 63
3913 22:15:14.350170 [CA 4] Center 33 (2~64) winsize 63
3914 22:15:14.353526 [CA 5] Center 32 (2~63) winsize 62
3915 22:15:14.353616
3916 22:15:14.356840 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3917 22:15:14.356925
3918 22:15:14.359983 [CATrainingPosCal] consider 1 rank data
3919 22:15:14.363518 u2DelayCellTimex100 = 270/100 ps
3920 22:15:14.367019 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3921 22:15:14.369912 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
3922 22:15:14.373678 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3923 22:15:14.376753 CA3 delay=33 (2~64),Diff = 1 PI (9 cell)
3924 22:15:14.380490 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3925 22:15:14.383806 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3926 22:15:14.383891
3927 22:15:14.390165 CA PerBit enable=1, Macro0, CA PI delay=32
3928 22:15:14.390250
3929 22:15:14.390334 [CBTSetCACLKResult] CA Dly = 32
3930 22:15:14.393482 CS Dly: 4 (0~35)
3931 22:15:14.393568 ==
3932 22:15:14.396349 Dram Type= 6, Freq= 0, CH_0, rank 1
3933 22:15:14.399948 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3934 22:15:14.400034 ==
3935 22:15:14.406303 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3936 22:15:14.413377 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3937 22:15:14.416265 [CA 0] Center 35 (5~66) winsize 62
3938 22:15:14.419999 [CA 1] Center 35 (5~66) winsize 62
3939 22:15:14.423049 [CA 2] Center 34 (3~65) winsize 63
3940 22:15:14.426558 [CA 3] Center 33 (3~64) winsize 62
3941 22:15:14.430189 [CA 4] Center 33 (2~64) winsize 63
3942 22:15:14.432810 [CA 5] Center 32 (2~63) winsize 62
3943 22:15:14.432894
3944 22:15:14.436170 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3945 22:15:14.436254
3946 22:15:14.439348 [CATrainingPosCal] consider 2 rank data
3947 22:15:14.442944 u2DelayCellTimex100 = 270/100 ps
3948 22:15:14.446342 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3949 22:15:14.449897 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
3950 22:15:14.453329 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3951 22:15:14.456435 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
3952 22:15:14.459352 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3953 22:15:14.466282 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3954 22:15:14.466363
3955 22:15:14.469408 CA PerBit enable=1, Macro0, CA PI delay=32
3956 22:15:14.469496
3957 22:15:14.472586 [CBTSetCACLKResult] CA Dly = 32
3958 22:15:14.472671 CS Dly: 4 (0~35)
3959 22:15:14.472734
3960 22:15:14.476148 ----->DramcWriteLeveling(PI) begin...
3961 22:15:14.476221 ==
3962 22:15:14.479889 Dram Type= 6, Freq= 0, CH_0, rank 0
3963 22:15:14.482832 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3964 22:15:14.486638 ==
3965 22:15:14.486735 Write leveling (Byte 0): 34 => 34
3966 22:15:14.489459 Write leveling (Byte 1): 32 => 32
3967 22:15:14.493182 DramcWriteLeveling(PI) end<-----
3968 22:15:14.493253
3969 22:15:14.493311 ==
3970 22:15:14.496057 Dram Type= 6, Freq= 0, CH_0, rank 0
3971 22:15:14.502775 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3972 22:15:14.502874 ==
3973 22:15:14.502972 [Gating] SW mode calibration
3974 22:15:14.513175 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3975 22:15:14.515938 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3976 22:15:14.522518 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3977 22:15:14.526210 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3978 22:15:14.529243 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3979 22:15:14.536133 0 9 12 | B1->B0 | 3434 2a2a | 1 1 | (1 1) (0 0)
3980 22:15:14.539197 0 9 16 | B1->B0 | 3030 2323 | 0 0 | (0 1) (0 0)
3981 22:15:14.542670 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3982 22:15:14.546383 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3983 22:15:14.552525 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3984 22:15:14.555671 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3985 22:15:14.562607 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3986 22:15:14.565826 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (1 1)
3987 22:15:14.568980 0 10 12 | B1->B0 | 2323 3c3c | 0 1 | (0 0) (0 0)
3988 22:15:14.572407 0 10 16 | B1->B0 | 3434 4646 | 0 0 | (0 0) (0 0)
3989 22:15:14.578841 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3990 22:15:14.581898 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3991 22:15:14.588473 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3992 22:15:14.591948 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3993 22:15:14.595499 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3994 22:15:14.598853 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3995 22:15:14.605242 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
3996 22:15:14.608672 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3997 22:15:14.611800 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3998 22:15:14.618234 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3999 22:15:14.621975 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4000 22:15:14.625184 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4001 22:15:14.631774 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4002 22:15:14.635216 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4003 22:15:14.638659 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4004 22:15:14.645244 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4005 22:15:14.648823 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4006 22:15:14.651964 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4007 22:15:14.658428 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4008 22:15:14.662233 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4009 22:15:14.665351 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4010 22:15:14.671465 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4011 22:15:14.675127 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4012 22:15:14.678465 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4013 22:15:14.681769 Total UI for P1: 0, mck2ui 16
4014 22:15:14.685241 best dqsien dly found for B0: ( 0, 13, 12)
4015 22:15:14.691967 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4016 22:15:14.692050 Total UI for P1: 0, mck2ui 16
4017 22:15:14.695479 best dqsien dly found for B1: ( 0, 13, 16)
4018 22:15:14.702015 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4019 22:15:14.704680 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4020 22:15:14.704761
4021 22:15:14.708281 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4022 22:15:14.711354 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4023 22:15:14.715010 [Gating] SW calibration Done
4024 22:15:14.715090 ==
4025 22:15:14.718036 Dram Type= 6, Freq= 0, CH_0, rank 0
4026 22:15:14.721430 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4027 22:15:14.721512 ==
4028 22:15:14.725022 RX Vref Scan: 0
4029 22:15:14.725125
4030 22:15:14.725197 RX Vref 0 -> 0, step: 1
4031 22:15:14.725258
4032 22:15:14.728011 RX Delay -230 -> 252, step: 16
4033 22:15:14.734487 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4034 22:15:14.737991 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4035 22:15:14.741738 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4036 22:15:14.744540 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4037 22:15:14.747992 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4038 22:15:14.754338 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4039 22:15:14.758039 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4040 22:15:14.761346 iDelay=218, Bit 7, Center 65 (-86 ~ 217) 304
4041 22:15:14.764640 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4042 22:15:14.768053 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4043 22:15:14.774264 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4044 22:15:14.777676 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4045 22:15:14.781424 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4046 22:15:14.784397 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4047 22:15:14.790904 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4048 22:15:14.794949 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4049 22:15:14.795031 ==
4050 22:15:14.798497 Dram Type= 6, Freq= 0, CH_0, rank 0
4051 22:15:14.801231 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4052 22:15:14.801339 ==
4053 22:15:14.804907 DQS Delay:
4054 22:15:14.805031 DQS0 = 0, DQS1 = 0
4055 22:15:14.805127 DQM Delay:
4056 22:15:14.807749 DQM0 = 51, DQM1 = 46
4057 22:15:14.807830 DQ Delay:
4058 22:15:14.811184 DQ0 =49, DQ1 =57, DQ2 =41, DQ3 =41
4059 22:15:14.814464 DQ4 =49, DQ5 =41, DQ6 =65, DQ7 =65
4060 22:15:14.817865 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4061 22:15:14.820914 DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =57
4062 22:15:14.820996
4063 22:15:14.821060
4064 22:15:14.821118 ==
4065 22:15:14.824385 Dram Type= 6, Freq= 0, CH_0, rank 0
4066 22:15:14.831093 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4067 22:15:14.831176 ==
4068 22:15:14.831241
4069 22:15:14.831300
4070 22:15:14.831399 TX Vref Scan disable
4071 22:15:14.835169 == TX Byte 0 ==
4072 22:15:14.838319 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4073 22:15:14.844683 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4074 22:15:14.844765 == TX Byte 1 ==
4075 22:15:14.847979 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4076 22:15:14.854809 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4077 22:15:14.854891 ==
4078 22:15:14.857789 Dram Type= 6, Freq= 0, CH_0, rank 0
4079 22:15:14.861290 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4080 22:15:14.861373 ==
4081 22:15:14.861438
4082 22:15:14.861497
4083 22:15:14.864712 TX Vref Scan disable
4084 22:15:14.864794 == TX Byte 0 ==
4085 22:15:14.871375 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4086 22:15:14.874578 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4087 22:15:14.878298 == TX Byte 1 ==
4088 22:15:14.881065 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4089 22:15:14.884479 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4090 22:15:14.884561
4091 22:15:14.884626 [DATLAT]
4092 22:15:14.888120 Freq=600, CH0 RK0
4093 22:15:14.888202
4094 22:15:14.888267 DATLAT Default: 0x9
4095 22:15:14.891372 0, 0xFFFF, sum = 0
4096 22:15:14.891469 1, 0xFFFF, sum = 0
4097 22:15:14.894694 2, 0xFFFF, sum = 0
4098 22:15:14.894777 3, 0xFFFF, sum = 0
4099 22:15:14.898029 4, 0xFFFF, sum = 0
4100 22:15:14.901538 5, 0xFFFF, sum = 0
4101 22:15:14.901621 6, 0xFFFF, sum = 0
4102 22:15:14.904969 7, 0xFFFF, sum = 0
4103 22:15:14.905052 8, 0x0, sum = 1
4104 22:15:14.905118 9, 0x0, sum = 2
4105 22:15:14.907811 10, 0x0, sum = 3
4106 22:15:14.907895 11, 0x0, sum = 4
4107 22:15:14.911211 best_step = 9
4108 22:15:14.911292
4109 22:15:14.911381 ==
4110 22:15:14.914828 Dram Type= 6, Freq= 0, CH_0, rank 0
4111 22:15:14.918175 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4112 22:15:14.918258 ==
4113 22:15:14.921285 RX Vref Scan: 1
4114 22:15:14.921384
4115 22:15:14.921493 RX Vref 0 -> 0, step: 1
4116 22:15:14.921585
4117 22:15:14.924876 RX Delay -163 -> 252, step: 8
4118 22:15:14.924966
4119 22:15:14.928030 Set Vref, RX VrefLevel [Byte0]: 55
4120 22:15:14.931594 [Byte1]: 49
4121 22:15:14.935047
4122 22:15:14.935144 Final RX Vref Byte 0 = 55 to rank0
4123 22:15:14.938673 Final RX Vref Byte 1 = 49 to rank0
4124 22:15:14.941830 Final RX Vref Byte 0 = 55 to rank1
4125 22:15:14.945016 Final RX Vref Byte 1 = 49 to rank1==
4126 22:15:14.948745 Dram Type= 6, Freq= 0, CH_0, rank 0
4127 22:15:14.955154 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4128 22:15:14.955236 ==
4129 22:15:14.955301 DQS Delay:
4130 22:15:14.958062 DQS0 = 0, DQS1 = 0
4131 22:15:14.958157 DQM Delay:
4132 22:15:14.958238 DQM0 = 53, DQM1 = 46
4133 22:15:14.961912 DQ Delay:
4134 22:15:14.964647 DQ0 =52, DQ1 =56, DQ2 =48, DQ3 =52
4135 22:15:14.968293 DQ4 =52, DQ5 =44, DQ6 =60, DQ7 =60
4136 22:15:14.971458 DQ8 =36, DQ9 =36, DQ10 =48, DQ11 =40
4137 22:15:14.975194 DQ12 =56, DQ13 =48, DQ14 =56, DQ15 =52
4138 22:15:14.975291
4139 22:15:14.975380
4140 22:15:14.981397 [DQSOSCAuto] RK0, (LSB)MR18= 0x7265, (MSB)MR19= 0x808, tDQSOscB0 = 390 ps tDQSOscB1 = 388 ps
4141 22:15:14.985103 CH0 RK0: MR19=808, MR18=7265
4142 22:15:14.991526 CH0_RK0: MR19=0x808, MR18=0x7265, DQSOSC=388, MR23=63, INC=174, DEC=116
4143 22:15:14.991609
4144 22:15:14.994629 ----->DramcWriteLeveling(PI) begin...
4145 22:15:14.994713 ==
4146 22:15:14.998066 Dram Type= 6, Freq= 0, CH_0, rank 1
4147 22:15:15.001244 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4148 22:15:15.001327 ==
4149 22:15:15.004711 Write leveling (Byte 0): 33 => 33
4150 22:15:15.007923 Write leveling (Byte 1): 33 => 33
4151 22:15:15.011523 DramcWriteLeveling(PI) end<-----
4152 22:15:15.011604
4153 22:15:15.011669 ==
4154 22:15:15.014857 Dram Type= 6, Freq= 0, CH_0, rank 1
4155 22:15:15.018295 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4156 22:15:15.018392 ==
4157 22:15:15.021294 [Gating] SW mode calibration
4158 22:15:15.027887 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4159 22:15:15.034896 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4160 22:15:15.038026 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4161 22:15:15.044760 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4162 22:15:15.047606 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4163 22:15:15.051050 0 9 12 | B1->B0 | 3333 3434 | 1 1 | (1 0) (1 0)
4164 22:15:15.057858 0 9 16 | B1->B0 | 2929 2626 | 0 0 | (0 0) (0 0)
4165 22:15:15.061299 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4166 22:15:15.064367 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4167 22:15:15.067751 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4168 22:15:15.074321 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4169 22:15:15.077807 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4170 22:15:15.081489 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4171 22:15:15.087902 0 10 12 | B1->B0 | 2828 2929 | 0 0 | (0 0) (1 1)
4172 22:15:15.090803 0 10 16 | B1->B0 | 4444 4444 | 0 0 | (0 0) (1 1)
4173 22:15:15.094173 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4174 22:15:15.101254 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4175 22:15:15.104183 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4176 22:15:15.107805 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4177 22:15:15.114137 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4178 22:15:15.117355 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4179 22:15:15.120996 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4180 22:15:15.127238 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4181 22:15:15.130867 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4182 22:15:15.134628 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4183 22:15:15.141262 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4184 22:15:15.144368 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4185 22:15:15.147661 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4186 22:15:15.154062 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4187 22:15:15.157889 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4188 22:15:15.160558 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4189 22:15:15.167500 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4190 22:15:15.170537 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4191 22:15:15.174076 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4192 22:15:15.180798 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4193 22:15:15.184430 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4194 22:15:15.187319 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4195 22:15:15.194318 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4196 22:15:15.197642 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4197 22:15:15.200428 Total UI for P1: 0, mck2ui 16
4198 22:15:15.203859 best dqsien dly found for B0: ( 0, 13, 12)
4199 22:15:15.207215 Total UI for P1: 0, mck2ui 16
4200 22:15:15.210909 best dqsien dly found for B1: ( 0, 13, 14)
4201 22:15:15.214240 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4202 22:15:15.217733 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4203 22:15:15.217810
4204 22:15:15.220397 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4205 22:15:15.224044 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4206 22:15:15.227454 [Gating] SW calibration Done
4207 22:15:15.227535 ==
4208 22:15:15.230380 Dram Type= 6, Freq= 0, CH_0, rank 1
4209 22:15:15.233688 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4210 22:15:15.233770 ==
4211 22:15:15.237108 RX Vref Scan: 0
4212 22:15:15.237181
4213 22:15:15.240388 RX Vref 0 -> 0, step: 1
4214 22:15:15.240461
4215 22:15:15.240529 RX Delay -230 -> 252, step: 16
4216 22:15:15.247534 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4217 22:15:15.250440 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4218 22:15:15.254250 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4219 22:15:15.256899 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4220 22:15:15.264036 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4221 22:15:15.267322 iDelay=218, Bit 5, Center 49 (-102 ~ 201) 304
4222 22:15:15.270476 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4223 22:15:15.273931 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4224 22:15:15.277527 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4225 22:15:15.284098 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4226 22:15:15.287013 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4227 22:15:15.290516 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4228 22:15:15.293601 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4229 22:15:15.300459 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4230 22:15:15.303842 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4231 22:15:15.307024 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4232 22:15:15.307130 ==
4233 22:15:15.310472 Dram Type= 6, Freq= 0, CH_0, rank 1
4234 22:15:15.313456 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4235 22:15:15.317320 ==
4236 22:15:15.317419 DQS Delay:
4237 22:15:15.317508 DQS0 = 0, DQS1 = 0
4238 22:15:15.320343 DQM Delay:
4239 22:15:15.320419 DQM0 = 52, DQM1 = 43
4240 22:15:15.323542 DQ Delay:
4241 22:15:15.326835 DQ0 =49, DQ1 =49, DQ2 =49, DQ3 =49
4242 22:15:15.326912 DQ4 =57, DQ5 =49, DQ6 =57, DQ7 =57
4243 22:15:15.330450 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =33
4244 22:15:15.333616 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4245 22:15:15.336700
4246 22:15:15.336773
4247 22:15:15.336833 ==
4248 22:15:15.339973 Dram Type= 6, Freq= 0, CH_0, rank 1
4249 22:15:15.343016 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4250 22:15:15.343090 ==
4251 22:15:15.343150
4252 22:15:15.343232
4253 22:15:15.346654 TX Vref Scan disable
4254 22:15:15.346759 == TX Byte 0 ==
4255 22:15:15.353459 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4256 22:15:15.356607 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4257 22:15:15.356681 == TX Byte 1 ==
4258 22:15:15.363058 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4259 22:15:15.366546 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4260 22:15:15.366628 ==
4261 22:15:15.370087 Dram Type= 6, Freq= 0, CH_0, rank 1
4262 22:15:15.373059 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4263 22:15:15.373140 ==
4264 22:15:15.373205
4265 22:15:15.376526
4266 22:15:15.376638 TX Vref Scan disable
4267 22:15:15.379709 == TX Byte 0 ==
4268 22:15:15.383315 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4269 22:15:15.386390 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4270 22:15:15.389955 == TX Byte 1 ==
4271 22:15:15.393570 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4272 22:15:15.396540 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4273 22:15:15.399709
4274 22:15:15.399814 [DATLAT]
4275 22:15:15.399905 Freq=600, CH0 RK1
4276 22:15:15.400004
4277 22:15:15.403251 DATLAT Default: 0x9
4278 22:15:15.403391 0, 0xFFFF, sum = 0
4279 22:15:15.406613 1, 0xFFFF, sum = 0
4280 22:15:15.406719 2, 0xFFFF, sum = 0
4281 22:15:15.409507 3, 0xFFFF, sum = 0
4282 22:15:15.409608 4, 0xFFFF, sum = 0
4283 22:15:15.412731 5, 0xFFFF, sum = 0
4284 22:15:15.416082 6, 0xFFFF, sum = 0
4285 22:15:15.416186 7, 0xFFFF, sum = 0
4286 22:15:15.419475 8, 0x0, sum = 1
4287 22:15:15.419581 9, 0x0, sum = 2
4288 22:15:15.419664 10, 0x0, sum = 3
4289 22:15:15.422988 11, 0x0, sum = 4
4290 22:15:15.423102 best_step = 9
4291 22:15:15.423193
4292 22:15:15.423278 ==
4293 22:15:15.426080 Dram Type= 6, Freq= 0, CH_0, rank 1
4294 22:15:15.433090 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4295 22:15:15.433181 ==
4296 22:15:15.433246 RX Vref Scan: 0
4297 22:15:15.433313
4298 22:15:15.436299 RX Vref 0 -> 0, step: 1
4299 22:15:15.436389
4300 22:15:15.439544 RX Delay -163 -> 252, step: 8
4301 22:15:15.442780 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4302 22:15:15.449991 iDelay=205, Bit 1, Center 56 (-83 ~ 196) 280
4303 22:15:15.452917 iDelay=205, Bit 2, Center 52 (-91 ~ 196) 288
4304 22:15:15.456711 iDelay=205, Bit 3, Center 52 (-91 ~ 196) 288
4305 22:15:15.459408 iDelay=205, Bit 4, Center 52 (-91 ~ 196) 288
4306 22:15:15.463050 iDelay=205, Bit 5, Center 48 (-91 ~ 188) 280
4307 22:15:15.469474 iDelay=205, Bit 6, Center 56 (-83 ~ 196) 280
4308 22:15:15.473199 iDelay=205, Bit 7, Center 64 (-75 ~ 204) 280
4309 22:15:15.475812 iDelay=205, Bit 8, Center 36 (-107 ~ 180) 288
4310 22:15:15.479592 iDelay=205, Bit 9, Center 36 (-107 ~ 180) 288
4311 22:15:15.483116 iDelay=205, Bit 10, Center 48 (-91 ~ 188) 280
4312 22:15:15.489518 iDelay=205, Bit 11, Center 40 (-99 ~ 180) 280
4313 22:15:15.492914 iDelay=205, Bit 12, Center 48 (-91 ~ 188) 280
4314 22:15:15.495698 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4315 22:15:15.499317 iDelay=205, Bit 14, Center 56 (-83 ~ 196) 280
4316 22:15:15.502462 iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288
4317 22:15:15.506254 ==
4318 22:15:15.509127 Dram Type= 6, Freq= 0, CH_0, rank 1
4319 22:15:15.512543 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4320 22:15:15.512701 ==
4321 22:15:15.512767 DQS Delay:
4322 22:15:15.516092 DQS0 = 0, DQS1 = 0
4323 22:15:15.516173 DQM Delay:
4324 22:15:15.519299 DQM0 = 54, DQM1 = 46
4325 22:15:15.519416 DQ Delay:
4326 22:15:15.522876 DQ0 =52, DQ1 =56, DQ2 =52, DQ3 =52
4327 22:15:15.525644 DQ4 =52, DQ5 =48, DQ6 =56, DQ7 =64
4328 22:15:15.529347 DQ8 =36, DQ9 =36, DQ10 =48, DQ11 =40
4329 22:15:15.532821 DQ12 =48, DQ13 =52, DQ14 =56, DQ15 =52
4330 22:15:15.532947
4331 22:15:15.533045
4332 22:15:15.539306 [DQSOSCAuto] RK1, (LSB)MR18= 0x6424, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 391 ps
4333 22:15:15.542629 CH0 RK1: MR19=808, MR18=6424
4334 22:15:15.548966 CH0_RK1: MR19=0x808, MR18=0x6424, DQSOSC=391, MR23=63, INC=171, DEC=114
4335 22:15:15.552602 [RxdqsGatingPostProcess] freq 600
4336 22:15:15.556036 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4337 22:15:15.559141 Pre-setting of DQS Precalculation
4338 22:15:15.565695 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4339 22:15:15.565777 ==
4340 22:15:15.569281 Dram Type= 6, Freq= 0, CH_1, rank 0
4341 22:15:15.572455 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4342 22:15:15.572531 ==
4343 22:15:15.579286 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4344 22:15:15.585764 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4345 22:15:15.588876 [CA 0] Center 36 (5~67) winsize 63
4346 22:15:15.592142 [CA 1] Center 36 (5~67) winsize 63
4347 22:15:15.595855 [CA 2] Center 34 (4~65) winsize 62
4348 22:15:15.599140 [CA 3] Center 34 (3~65) winsize 63
4349 22:15:15.602444 [CA 4] Center 34 (4~65) winsize 62
4350 22:15:15.605559 [CA 5] Center 34 (3~65) winsize 63
4351 22:15:15.605662
4352 22:15:15.609182 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4353 22:15:15.609282
4354 22:15:15.612091 [CATrainingPosCal] consider 1 rank data
4355 22:15:15.615968 u2DelayCellTimex100 = 270/100 ps
4356 22:15:15.618741 CA0 delay=36 (5~67),Diff = 2 PI (19 cell)
4357 22:15:15.622570 CA1 delay=36 (5~67),Diff = 2 PI (19 cell)
4358 22:15:15.625712 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4359 22:15:15.629301 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
4360 22:15:15.632456 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4361 22:15:15.635367 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4362 22:15:15.635451
4363 22:15:15.642551 CA PerBit enable=1, Macro0, CA PI delay=34
4364 22:15:15.642633
4365 22:15:15.642718 [CBTSetCACLKResult] CA Dly = 34
4366 22:15:15.645834 CS Dly: 6 (0~37)
4367 22:15:15.645915 ==
4368 22:15:15.648833 Dram Type= 6, Freq= 0, CH_1, rank 1
4369 22:15:15.652295 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4370 22:15:15.652378 ==
4371 22:15:15.658860 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4372 22:15:15.665820 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4373 22:15:15.668731 [CA 0] Center 36 (5~67) winsize 63
4374 22:15:15.672294 [CA 1] Center 36 (5~67) winsize 63
4375 22:15:15.675922 [CA 2] Center 35 (4~66) winsize 63
4376 22:15:15.678946 [CA 3] Center 34 (4~65) winsize 62
4377 22:15:15.682356 [CA 4] Center 34 (4~65) winsize 62
4378 22:15:15.685513 [CA 5] Center 34 (4~65) winsize 62
4379 22:15:15.685596
4380 22:15:15.688982 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4381 22:15:15.689064
4382 22:15:15.692484 [CATrainingPosCal] consider 2 rank data
4383 22:15:15.695359 u2DelayCellTimex100 = 270/100 ps
4384 22:15:15.699062 CA0 delay=36 (5~67),Diff = 2 PI (19 cell)
4385 22:15:15.701994 CA1 delay=36 (5~67),Diff = 2 PI (19 cell)
4386 22:15:15.705876 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4387 22:15:15.708811 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4388 22:15:15.712305 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4389 22:15:15.715842 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4390 22:15:15.715925
4391 22:15:15.722497 CA PerBit enable=1, Macro0, CA PI delay=34
4392 22:15:15.722579
4393 22:15:15.725185 [CBTSetCACLKResult] CA Dly = 34
4394 22:15:15.725267 CS Dly: 6 (0~37)
4395 22:15:15.725361
4396 22:15:15.729560 ----->DramcWriteLeveling(PI) begin...
4397 22:15:15.729644 ==
4398 22:15:15.732268 Dram Type= 6, Freq= 0, CH_1, rank 0
4399 22:15:15.735588 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4400 22:15:15.735671 ==
4401 22:15:15.738969 Write leveling (Byte 0): 29 => 29
4402 22:15:15.742083 Write leveling (Byte 1): 29 => 29
4403 22:15:15.745819 DramcWriteLeveling(PI) end<-----
4404 22:15:15.745901
4405 22:15:15.745965 ==
4406 22:15:15.749122 Dram Type= 6, Freq= 0, CH_1, rank 0
4407 22:15:15.755618 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4408 22:15:15.755701 ==
4409 22:15:15.755765 [Gating] SW mode calibration
4410 22:15:15.765287 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4411 22:15:15.768559 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4412 22:15:15.772261 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4413 22:15:15.778720 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4414 22:15:15.781848 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4415 22:15:15.785313 0 9 12 | B1->B0 | 2f2f 2f2f | 1 0 | (1 1) (0 1)
4416 22:15:15.791853 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4417 22:15:15.795449 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4418 22:15:15.798459 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4419 22:15:15.805012 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4420 22:15:15.808143 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4421 22:15:15.812022 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4422 22:15:15.818119 0 10 8 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
4423 22:15:15.821715 0 10 12 | B1->B0 | 3939 3838 | 0 0 | (0 0) (0 0)
4424 22:15:15.825515 0 10 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
4425 22:15:15.831271 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4426 22:15:15.834612 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4427 22:15:15.838292 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4428 22:15:15.844792 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4429 22:15:15.848054 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4430 22:15:15.851575 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4431 22:15:15.858241 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4432 22:15:15.861401 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4433 22:15:15.864832 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4434 22:15:15.871499 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4435 22:15:15.875118 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4436 22:15:15.877824 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4437 22:15:15.884724 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4438 22:15:15.887763 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4439 22:15:15.891356 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4440 22:15:15.897857 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4441 22:15:15.901356 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4442 22:15:15.904504 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4443 22:15:15.911091 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4444 22:15:15.914272 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4445 22:15:15.917794 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4446 22:15:15.921036 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4447 22:15:15.928258 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4448 22:15:15.931201 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4449 22:15:15.934846 Total UI for P1: 0, mck2ui 16
4450 22:15:15.937758 best dqsien dly found for B0: ( 0, 13, 14)
4451 22:15:15.941188 Total UI for P1: 0, mck2ui 16
4452 22:15:15.944580 best dqsien dly found for B1: ( 0, 13, 14)
4453 22:15:15.947706 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4454 22:15:15.950953 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4455 22:15:15.951034
4456 22:15:15.954561 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4457 22:15:15.961412 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4458 22:15:15.961495 [Gating] SW calibration Done
4459 22:15:15.961560 ==
4460 22:15:15.964279 Dram Type= 6, Freq= 0, CH_1, rank 0
4461 22:15:15.970909 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4462 22:15:15.970992 ==
4463 22:15:15.971057 RX Vref Scan: 0
4464 22:15:15.971155
4465 22:15:15.974480 RX Vref 0 -> 0, step: 1
4466 22:15:15.974561
4467 22:15:15.977835 RX Delay -230 -> 252, step: 16
4468 22:15:15.980890 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4469 22:15:15.984377 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4470 22:15:15.987469 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4471 22:15:15.994121 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4472 22:15:15.997522 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4473 22:15:16.001022 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4474 22:15:16.004665 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4475 22:15:16.007581 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4476 22:15:16.014556 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4477 22:15:16.017541 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4478 22:15:16.021124 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4479 22:15:16.024496 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4480 22:15:16.030891 iDelay=218, Bit 12, Center 65 (-86 ~ 217) 304
4481 22:15:16.034639 iDelay=218, Bit 13, Center 57 (-86 ~ 201) 288
4482 22:15:16.037974 iDelay=218, Bit 14, Center 57 (-86 ~ 201) 288
4483 22:15:16.041024 iDelay=218, Bit 15, Center 65 (-86 ~ 217) 304
4484 22:15:16.041106 ==
4485 22:15:16.044091 Dram Type= 6, Freq= 0, CH_1, rank 0
4486 22:15:16.050995 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4487 22:15:16.051078 ==
4488 22:15:16.051143 DQS Delay:
4489 22:15:16.051223 DQS0 = 0, DQS1 = 0
4490 22:15:16.054824 DQM Delay:
4491 22:15:16.054905 DQM0 = 52, DQM1 = 50
4492 22:15:16.057699 DQ Delay:
4493 22:15:16.060771 DQ0 =57, DQ1 =41, DQ2 =41, DQ3 =49
4494 22:15:16.060853 DQ4 =49, DQ5 =65, DQ6 =65, DQ7 =49
4495 22:15:16.064672 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4496 22:15:16.067498 DQ12 =65, DQ13 =57, DQ14 =57, DQ15 =65
4497 22:15:16.071596
4498 22:15:16.071677
4499 22:15:16.071741 ==
4500 22:15:16.074286 Dram Type= 6, Freq= 0, CH_1, rank 0
4501 22:15:16.077625 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4502 22:15:16.077708 ==
4503 22:15:16.077772
4504 22:15:16.077842
4505 22:15:16.080921 TX Vref Scan disable
4506 22:15:16.081003 == TX Byte 0 ==
4507 22:15:16.087688 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4508 22:15:16.091427 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4509 22:15:16.091536 == TX Byte 1 ==
4510 22:15:16.097839 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4511 22:15:16.101471 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4512 22:15:16.101548 ==
4513 22:15:16.104442 Dram Type= 6, Freq= 0, CH_1, rank 0
4514 22:15:16.107967 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4515 22:15:16.108045 ==
4516 22:15:16.108108
4517 22:15:16.108165
4518 22:15:16.110899 TX Vref Scan disable
4519 22:15:16.114772 == TX Byte 0 ==
4520 22:15:16.117616 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4521 22:15:16.121134 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4522 22:15:16.124423 == TX Byte 1 ==
4523 22:15:16.127782 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4524 22:15:16.131226 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4525 22:15:16.131357
4526 22:15:16.134670 [DATLAT]
4527 22:15:16.134752 Freq=600, CH1 RK0
4528 22:15:16.134818
4529 22:15:16.137667 DATLAT Default: 0x9
4530 22:15:16.137748 0, 0xFFFF, sum = 0
4531 22:15:16.141267 1, 0xFFFF, sum = 0
4532 22:15:16.141350 2, 0xFFFF, sum = 0
4533 22:15:16.144105 3, 0xFFFF, sum = 0
4534 22:15:16.144188 4, 0xFFFF, sum = 0
4535 22:15:16.147495 5, 0xFFFF, sum = 0
4536 22:15:16.147578 6, 0xFFFF, sum = 0
4537 22:15:16.151079 7, 0xFFFF, sum = 0
4538 22:15:16.151162 8, 0x0, sum = 1
4539 22:15:16.154180 9, 0x0, sum = 2
4540 22:15:16.154288 10, 0x0, sum = 3
4541 22:15:16.158001 11, 0x0, sum = 4
4542 22:15:16.158084 best_step = 9
4543 22:15:16.158148
4544 22:15:16.158207 ==
4545 22:15:16.161262 Dram Type= 6, Freq= 0, CH_1, rank 0
4546 22:15:16.164451 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4547 22:15:16.167465 ==
4548 22:15:16.167547 RX Vref Scan: 1
4549 22:15:16.167610
4550 22:15:16.170950 RX Vref 0 -> 0, step: 1
4551 22:15:16.171032
4552 22:15:16.174378 RX Delay -163 -> 252, step: 8
4553 22:15:16.174459
4554 22:15:16.177649 Set Vref, RX VrefLevel [Byte0]: 54
4555 22:15:16.181119 [Byte1]: 51
4556 22:15:16.181200
4557 22:15:16.184397 Final RX Vref Byte 0 = 54 to rank0
4558 22:15:16.187258 Final RX Vref Byte 1 = 51 to rank0
4559 22:15:16.190724 Final RX Vref Byte 0 = 54 to rank1
4560 22:15:16.194034 Final RX Vref Byte 1 = 51 to rank1==
4561 22:15:16.197604 Dram Type= 6, Freq= 0, CH_1, rank 0
4562 22:15:16.201086 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4563 22:15:16.201169 ==
4564 22:15:16.201265 DQS Delay:
4565 22:15:16.204639 DQS0 = 0, DQS1 = 0
4566 22:15:16.204748 DQM Delay:
4567 22:15:16.207485 DQM0 = 47, DQM1 = 46
4568 22:15:16.207567 DQ Delay:
4569 22:15:16.210905 DQ0 =52, DQ1 =40, DQ2 =36, DQ3 =44
4570 22:15:16.214582 DQ4 =48, DQ5 =56, DQ6 =56, DQ7 =48
4571 22:15:16.217629 DQ8 =36, DQ9 =36, DQ10 =44, DQ11 =40
4572 22:15:16.221114 DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =56
4573 22:15:16.221196
4574 22:15:16.221260
4575 22:15:16.230664 [DQSOSCAuto] RK0, (LSB)MR18= 0x4b70, (MSB)MR19= 0x808, tDQSOscB0 = 388 ps tDQSOscB1 = 395 ps
4576 22:15:16.230748 CH1 RK0: MR19=808, MR18=4B70
4577 22:15:16.237676 CH1_RK0: MR19=0x808, MR18=0x4B70, DQSOSC=388, MR23=63, INC=174, DEC=116
4578 22:15:16.237775
4579 22:15:16.241165 ----->DramcWriteLeveling(PI) begin...
4580 22:15:16.241294 ==
4581 22:15:16.244291 Dram Type= 6, Freq= 0, CH_1, rank 1
4582 22:15:16.250745 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4583 22:15:16.250843 ==
4584 22:15:16.254293 Write leveling (Byte 0): 33 => 33
4585 22:15:16.257881 Write leveling (Byte 1): 31 => 31
4586 22:15:16.257963 DramcWriteLeveling(PI) end<-----
4587 22:15:16.258028
4588 22:15:16.260617 ==
4589 22:15:16.264143 Dram Type= 6, Freq= 0, CH_1, rank 1
4590 22:15:16.267122 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4591 22:15:16.267203 ==
4592 22:15:16.270733 [Gating] SW mode calibration
4593 22:15:16.277590 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4594 22:15:16.280822 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4595 22:15:16.287403 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4596 22:15:16.290653 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4597 22:15:16.293957 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
4598 22:15:16.300709 0 9 12 | B1->B0 | 2f2f 3030 | 0 0 | (1 1) (1 1)
4599 22:15:16.303820 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4600 22:15:16.307103 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4601 22:15:16.314151 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4602 22:15:16.317288 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4603 22:15:16.321003 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4604 22:15:16.327115 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4605 22:15:16.330593 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4606 22:15:16.333622 0 10 12 | B1->B0 | 3a3a 3737 | 0 0 | (0 0) (0 0)
4607 22:15:16.340390 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4608 22:15:16.343761 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4609 22:15:16.347088 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4610 22:15:16.350510 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4611 22:15:16.357024 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4612 22:15:16.360195 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4613 22:15:16.363676 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4614 22:15:16.370317 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4615 22:15:16.373928 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4616 22:15:16.377024 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4617 22:15:16.383532 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4618 22:15:16.387087 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4619 22:15:16.390057 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4620 22:15:16.397031 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4621 22:15:16.399968 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4622 22:15:16.403168 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4623 22:15:16.410434 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4624 22:15:16.413631 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4625 22:15:16.416814 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4626 22:15:16.423640 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4627 22:15:16.426712 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4628 22:15:16.430400 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4629 22:15:16.436454 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4630 22:15:16.440004 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4631 22:15:16.443400 Total UI for P1: 0, mck2ui 16
4632 22:15:16.446731 best dqsien dly found for B0: ( 0, 13, 8)
4633 22:15:16.450251 Total UI for P1: 0, mck2ui 16
4634 22:15:16.453637 best dqsien dly found for B1: ( 0, 13, 8)
4635 22:15:16.456491 best DQS0 dly(MCK, UI, PI) = (0, 13, 8)
4636 22:15:16.460182 best DQS1 dly(MCK, UI, PI) = (0, 13, 8)
4637 22:15:16.460258
4638 22:15:16.463248 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 8)
4639 22:15:16.466799 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 8)
4640 22:15:16.470040 [Gating] SW calibration Done
4641 22:15:16.470116 ==
4642 22:15:16.473089 Dram Type= 6, Freq= 0, CH_1, rank 1
4643 22:15:16.476910 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4644 22:15:16.476992 ==
4645 22:15:16.480419 RX Vref Scan: 0
4646 22:15:16.480492
4647 22:15:16.483311 RX Vref 0 -> 0, step: 1
4648 22:15:16.483428
4649 22:15:16.483493 RX Delay -230 -> 252, step: 16
4650 22:15:16.490045 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4651 22:15:16.493392 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4652 22:15:16.497031 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4653 22:15:16.500239 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4654 22:15:16.506873 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4655 22:15:16.510157 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4656 22:15:16.513445 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4657 22:15:16.517077 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4658 22:15:16.519970 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4659 22:15:16.526543 iDelay=218, Bit 9, Center 41 (-118 ~ 201) 320
4660 22:15:16.530242 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4661 22:15:16.533247 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4662 22:15:16.536672 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4663 22:15:16.543257 iDelay=218, Bit 13, Center 57 (-102 ~ 217) 320
4664 22:15:16.546779 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4665 22:15:16.550186 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4666 22:15:16.550265 ==
4667 22:15:16.553321 Dram Type= 6, Freq= 0, CH_1, rank 1
4668 22:15:16.556487 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4669 22:15:16.556565 ==
4670 22:15:16.559712 DQS Delay:
4671 22:15:16.559803 DQS0 = 0, DQS1 = 0
4672 22:15:16.563251 DQM Delay:
4673 22:15:16.563371 DQM0 = 50, DQM1 = 48
4674 22:15:16.563434 DQ Delay:
4675 22:15:16.566420 DQ0 =49, DQ1 =49, DQ2 =33, DQ3 =49
4676 22:15:16.569888 DQ4 =49, DQ5 =65, DQ6 =57, DQ7 =49
4677 22:15:16.573181 DQ8 =33, DQ9 =41, DQ10 =49, DQ11 =41
4678 22:15:16.576827 DQ12 =57, DQ13 =57, DQ14 =49, DQ15 =57
4679 22:15:16.576899
4680 22:15:16.576960
4681 22:15:16.580204 ==
4682 22:15:16.583422 Dram Type= 6, Freq= 0, CH_1, rank 1
4683 22:15:16.587103 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4684 22:15:16.587176 ==
4685 22:15:16.587235
4686 22:15:16.587299
4687 22:15:16.590076 TX Vref Scan disable
4688 22:15:16.590147 == TX Byte 0 ==
4689 22:15:16.593599 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4690 22:15:16.600112 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4691 22:15:16.600188 == TX Byte 1 ==
4692 22:15:16.606558 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4693 22:15:16.609745 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4694 22:15:16.609824 ==
4695 22:15:16.613077 Dram Type= 6, Freq= 0, CH_1, rank 1
4696 22:15:16.616334 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4697 22:15:16.616411 ==
4698 22:15:16.616483
4699 22:15:16.616545
4700 22:15:16.619551 TX Vref Scan disable
4701 22:15:16.623088 == TX Byte 0 ==
4702 22:15:16.626354 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4703 22:15:16.630085 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4704 22:15:16.633439 == TX Byte 1 ==
4705 22:15:16.636576 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4706 22:15:16.639639 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4707 22:15:16.639724
4708 22:15:16.643199 [DATLAT]
4709 22:15:16.643284 Freq=600, CH1 RK1
4710 22:15:16.643411
4711 22:15:16.646086 DATLAT Default: 0x9
4712 22:15:16.646171 0, 0xFFFF, sum = 0
4713 22:15:16.649825 1, 0xFFFF, sum = 0
4714 22:15:16.649912 2, 0xFFFF, sum = 0
4715 22:15:16.653023 3, 0xFFFF, sum = 0
4716 22:15:16.653110 4, 0xFFFF, sum = 0
4717 22:15:16.656722 5, 0xFFFF, sum = 0
4718 22:15:16.656809 6, 0xFFFF, sum = 0
4719 22:15:16.659825 7, 0xFFFF, sum = 0
4720 22:15:16.659912 8, 0x0, sum = 1
4721 22:15:16.663265 9, 0x0, sum = 2
4722 22:15:16.663388 10, 0x0, sum = 3
4723 22:15:16.666414 11, 0x0, sum = 4
4724 22:15:16.666501 best_step = 9
4725 22:15:16.666585
4726 22:15:16.666665 ==
4727 22:15:16.669746 Dram Type= 6, Freq= 0, CH_1, rank 1
4728 22:15:16.672890 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4729 22:15:16.676235 ==
4730 22:15:16.676317 RX Vref Scan: 0
4731 22:15:16.676382
4732 22:15:16.679914 RX Vref 0 -> 0, step: 1
4733 22:15:16.679996
4734 22:15:16.682969 RX Delay -163 -> 252, step: 8
4735 22:15:16.686011 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4736 22:15:16.689669 iDelay=205, Bit 1, Center 44 (-99 ~ 188) 288
4737 22:15:16.696460 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4738 22:15:16.699444 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4739 22:15:16.703013 iDelay=205, Bit 4, Center 44 (-99 ~ 188) 288
4740 22:15:16.706359 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4741 22:15:16.709794 iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288
4742 22:15:16.716180 iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296
4743 22:15:16.719943 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4744 22:15:16.722959 iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296
4745 22:15:16.726635 iDelay=205, Bit 10, Center 48 (-99 ~ 196) 296
4746 22:15:16.729364 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4747 22:15:16.736006 iDelay=205, Bit 12, Center 56 (-91 ~ 204) 296
4748 22:15:16.739191 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4749 22:15:16.743120 iDelay=205, Bit 14, Center 52 (-91 ~ 196) 288
4750 22:15:16.745998 iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288
4751 22:15:16.746080 ==
4752 22:15:16.749201 Dram Type= 6, Freq= 0, CH_1, rank 1
4753 22:15:16.756080 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4754 22:15:16.756162 ==
4755 22:15:16.756227 DQS Delay:
4756 22:15:16.759448 DQS0 = 0, DQS1 = 0
4757 22:15:16.759530 DQM Delay:
4758 22:15:16.759594 DQM0 = 48, DQM1 = 45
4759 22:15:16.762903 DQ Delay:
4760 22:15:16.765977 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4761 22:15:16.769460 DQ4 =44, DQ5 =60, DQ6 =60, DQ7 =48
4762 22:15:16.773138 DQ8 =32, DQ9 =32, DQ10 =48, DQ11 =40
4763 22:15:16.776311 DQ12 =56, DQ13 =52, DQ14 =52, DQ15 =52
4764 22:15:16.776393
4765 22:15:16.776457
4766 22:15:16.782851 [DQSOSCAuto] RK1, (LSB)MR18= 0x671f, (MSB)MR19= 0x808, tDQSOscB0 = 404 ps tDQSOscB1 = 390 ps
4767 22:15:16.786466 CH1 RK1: MR19=808, MR18=671F
4768 22:15:16.792382 CH1_RK1: MR19=0x808, MR18=0x671F, DQSOSC=390, MR23=63, INC=172, DEC=114
4769 22:15:16.796015 [RxdqsGatingPostProcess] freq 600
4770 22:15:16.799453 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4771 22:15:16.802740 Pre-setting of DQS Precalculation
4772 22:15:16.809224 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4773 22:15:16.816184 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4774 22:15:16.822646 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4775 22:15:16.822728
4776 22:15:16.822793
4777 22:15:16.825827 [Calibration Summary] 1200 Mbps
4778 22:15:16.825908 CH 0, Rank 0
4779 22:15:16.829426 SW Impedance : PASS
4780 22:15:16.832498 DUTY Scan : NO K
4781 22:15:16.832580 ZQ Calibration : PASS
4782 22:15:16.835953 Jitter Meter : NO K
4783 22:15:16.839166 CBT Training : PASS
4784 22:15:16.839248 Write leveling : PASS
4785 22:15:16.842912 RX DQS gating : PASS
4786 22:15:16.842993 RX DQ/DQS(RDDQC) : PASS
4787 22:15:16.845840 TX DQ/DQS : PASS
4788 22:15:16.849292 RX DATLAT : PASS
4789 22:15:16.849374 RX DQ/DQS(Engine): PASS
4790 22:15:16.852458 TX OE : NO K
4791 22:15:16.852540 All Pass.
4792 22:15:16.852604
4793 22:15:16.855758 CH 0, Rank 1
4794 22:15:16.855839 SW Impedance : PASS
4795 22:15:16.859299 DUTY Scan : NO K
4796 22:15:16.862631 ZQ Calibration : PASS
4797 22:15:16.862712 Jitter Meter : NO K
4798 22:15:16.866114 CBT Training : PASS
4799 22:15:16.869432 Write leveling : PASS
4800 22:15:16.869514 RX DQS gating : PASS
4801 22:15:16.872541 RX DQ/DQS(RDDQC) : PASS
4802 22:15:16.875846 TX DQ/DQS : PASS
4803 22:15:16.875927 RX DATLAT : PASS
4804 22:15:16.879302 RX DQ/DQS(Engine): PASS
4805 22:15:16.882307 TX OE : NO K
4806 22:15:16.882389 All Pass.
4807 22:15:16.882454
4808 22:15:16.882513 CH 1, Rank 0
4809 22:15:16.886052 SW Impedance : PASS
4810 22:15:16.889285 DUTY Scan : NO K
4811 22:15:16.889367 ZQ Calibration : PASS
4812 22:15:16.892733 Jitter Meter : NO K
4813 22:15:16.895891 CBT Training : PASS
4814 22:15:16.895974 Write leveling : PASS
4815 22:15:16.898764 RX DQS gating : PASS
4816 22:15:16.898846 RX DQ/DQS(RDDQC) : PASS
4817 22:15:16.902331 TX DQ/DQS : PASS
4818 22:15:16.905819 RX DATLAT : PASS
4819 22:15:16.905901 RX DQ/DQS(Engine): PASS
4820 22:15:16.909068 TX OE : NO K
4821 22:15:16.909150 All Pass.
4822 22:15:16.909215
4823 22:15:16.912593 CH 1, Rank 1
4824 22:15:16.912674 SW Impedance : PASS
4825 22:15:16.915847 DUTY Scan : NO K
4826 22:15:16.918972 ZQ Calibration : PASS
4827 22:15:16.919054 Jitter Meter : NO K
4828 22:15:16.921918 CBT Training : PASS
4829 22:15:16.925513 Write leveling : PASS
4830 22:15:16.925594 RX DQS gating : PASS
4831 22:15:16.928993 RX DQ/DQS(RDDQC) : PASS
4832 22:15:16.932526 TX DQ/DQS : PASS
4833 22:15:16.932608 RX DATLAT : PASS
4834 22:15:16.935526 RX DQ/DQS(Engine): PASS
4835 22:15:16.939001 TX OE : NO K
4836 22:15:16.939083 All Pass.
4837 22:15:16.939147
4838 22:15:16.939207 DramC Write-DBI off
4839 22:15:16.941997 PER_BANK_REFRESH: Hybrid Mode
4840 22:15:16.945398 TX_TRACKING: ON
4841 22:15:16.952066 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4842 22:15:16.955263 [FAST_K] Save calibration result to emmc
4843 22:15:16.962194 dramc_set_vcore_voltage set vcore to 662500
4844 22:15:16.962276 Read voltage for 933, 3
4845 22:15:16.965365 Vio18 = 0
4846 22:15:16.965447 Vcore = 662500
4847 22:15:16.965511 Vdram = 0
4848 22:15:16.968654 Vddq = 0
4849 22:15:16.968736 Vmddr = 0
4850 22:15:16.972444 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4851 22:15:16.978595 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4852 22:15:16.982198 MEM_TYPE=3, freq_sel=17
4853 22:15:16.982279 sv_algorithm_assistance_LP4_1600
4854 22:15:16.988406 ============ PULL DRAM RESETB DOWN ============
4855 22:15:16.991820 ========== PULL DRAM RESETB DOWN end =========
4856 22:15:16.995182 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4857 22:15:16.998617 ===================================
4858 22:15:17.001835 LPDDR4 DRAM CONFIGURATION
4859 22:15:17.005233 ===================================
4860 22:15:17.008938 EX_ROW_EN[0] = 0x0
4861 22:15:17.009020 EX_ROW_EN[1] = 0x0
4862 22:15:17.012102 LP4Y_EN = 0x0
4863 22:15:17.012183 WORK_FSP = 0x0
4864 22:15:17.015085 WL = 0x3
4865 22:15:17.015166 RL = 0x3
4866 22:15:17.018660 BL = 0x2
4867 22:15:17.018763 RPST = 0x0
4868 22:15:17.021448 RD_PRE = 0x0
4869 22:15:17.021530 WR_PRE = 0x1
4870 22:15:17.025151 WR_PST = 0x0
4871 22:15:17.025233 DBI_WR = 0x0
4872 22:15:17.028373 DBI_RD = 0x0
4873 22:15:17.031735 OTF = 0x1
4874 22:15:17.034784 ===================================
4875 22:15:17.034866 ===================================
4876 22:15:17.038154 ANA top config
4877 22:15:17.041716 ===================================
4878 22:15:17.044892 DLL_ASYNC_EN = 0
4879 22:15:17.044974 ALL_SLAVE_EN = 1
4880 22:15:17.048517 NEW_RANK_MODE = 1
4881 22:15:17.051734 DLL_IDLE_MODE = 1
4882 22:15:17.055106 LP45_APHY_COMB_EN = 1
4883 22:15:17.058509 TX_ODT_DIS = 1
4884 22:15:17.058603 NEW_8X_MODE = 1
4885 22:15:17.061578 ===================================
4886 22:15:17.065150 ===================================
4887 22:15:17.068003 data_rate = 1866
4888 22:15:17.071517 CKR = 1
4889 22:15:17.074688 DQ_P2S_RATIO = 8
4890 22:15:17.078010 ===================================
4891 22:15:17.081339 CA_P2S_RATIO = 8
4892 22:15:17.085142 DQ_CA_OPEN = 0
4893 22:15:17.085224 DQ_SEMI_OPEN = 0
4894 22:15:17.088107 CA_SEMI_OPEN = 0
4895 22:15:17.091968 CA_FULL_RATE = 0
4896 22:15:17.095054 DQ_CKDIV4_EN = 1
4897 22:15:17.097952 CA_CKDIV4_EN = 1
4898 22:15:17.098033 CA_PREDIV_EN = 0
4899 22:15:17.101526 PH8_DLY = 0
4900 22:15:17.105097 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4901 22:15:17.108138 DQ_AAMCK_DIV = 4
4902 22:15:17.111438 CA_AAMCK_DIV = 4
4903 22:15:17.115045 CA_ADMCK_DIV = 4
4904 22:15:17.115127 DQ_TRACK_CA_EN = 0
4905 22:15:17.117951 CA_PICK = 933
4906 22:15:17.121517 CA_MCKIO = 933
4907 22:15:17.125051 MCKIO_SEMI = 0
4908 22:15:17.128497 PLL_FREQ = 3732
4909 22:15:17.131575 DQ_UI_PI_RATIO = 32
4910 22:15:17.135066 CA_UI_PI_RATIO = 0
4911 22:15:17.137979 ===================================
4912 22:15:17.141717 ===================================
4913 22:15:17.141800 memory_type:LPDDR4
4914 22:15:17.144793 GP_NUM : 10
4915 22:15:17.148391 SRAM_EN : 1
4916 22:15:17.148488 MD32_EN : 0
4917 22:15:17.151321 ===================================
4918 22:15:17.154501 [ANA_INIT] >>>>>>>>>>>>>>
4919 22:15:17.158250 <<<<<< [CONFIGURE PHASE]: ANA_TX
4920 22:15:17.161780 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4921 22:15:17.164713 ===================================
4922 22:15:17.167972 data_rate = 1866,PCW = 0X8f00
4923 22:15:17.170998 ===================================
4924 22:15:17.174301 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4925 22:15:17.177821 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4926 22:15:17.184512 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4927 22:15:17.188111 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4928 22:15:17.190939 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4929 22:15:17.194751 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4930 22:15:17.197717 [ANA_INIT] flow start
4931 22:15:17.201356 [ANA_INIT] PLL >>>>>>>>
4932 22:15:17.201458 [ANA_INIT] PLL <<<<<<<<
4933 22:15:17.204374 [ANA_INIT] MIDPI >>>>>>>>
4934 22:15:17.207546 [ANA_INIT] MIDPI <<<<<<<<
4935 22:15:17.210867 [ANA_INIT] DLL >>>>>>>>
4936 22:15:17.210968 [ANA_INIT] flow end
4937 22:15:17.214272 ============ LP4 DIFF to SE enter ============
4938 22:15:17.220958 ============ LP4 DIFF to SE exit ============
4939 22:15:17.221058 [ANA_INIT] <<<<<<<<<<<<<
4940 22:15:17.224936 [Flow] Enable top DCM control >>>>>
4941 22:15:17.227574 [Flow] Enable top DCM control <<<<<
4942 22:15:17.231001 Enable DLL master slave shuffle
4943 22:15:17.238105 ==============================================================
4944 22:15:17.238187 Gating Mode config
4945 22:15:17.244064 ==============================================================
4946 22:15:17.248230 Config description:
4947 22:15:17.254087 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4948 22:15:17.260688 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4949 22:15:17.267248 SELPH_MODE 0: By rank 1: By Phase
4950 22:15:17.274472 ==============================================================
4951 22:15:17.277860 GAT_TRACK_EN = 1
4952 22:15:17.277941 RX_GATING_MODE = 2
4953 22:15:17.281128 RX_GATING_TRACK_MODE = 2
4954 22:15:17.283944 SELPH_MODE = 1
4955 22:15:17.287234 PICG_EARLY_EN = 1
4956 22:15:17.290996 VALID_LAT_VALUE = 1
4957 22:15:17.297770 ==============================================================
4958 22:15:17.300973 Enter into Gating configuration >>>>
4959 22:15:17.303851 Exit from Gating configuration <<<<
4960 22:15:17.307422 Enter into DVFS_PRE_config >>>>>
4961 22:15:17.317323 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4962 22:15:17.320621 Exit from DVFS_PRE_config <<<<<
4963 22:15:17.324317 Enter into PICG configuration >>>>
4964 22:15:17.327024 Exit from PICG configuration <<<<
4965 22:15:17.330584 [RX_INPUT] configuration >>>>>
4966 22:15:17.330666 [RX_INPUT] configuration <<<<<
4967 22:15:17.337203 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4968 22:15:17.343884 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4969 22:15:17.350695 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4970 22:15:17.354339 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4971 22:15:17.360774 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4972 22:15:17.367172 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4973 22:15:17.370681 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4974 22:15:17.374005 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4975 22:15:17.380488 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4976 22:15:17.383635 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4977 22:15:17.386940 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4978 22:15:17.394367 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4979 22:15:17.397134 ===================================
4980 22:15:17.397244 LPDDR4 DRAM CONFIGURATION
4981 22:15:17.400535 ===================================
4982 22:15:17.403640 EX_ROW_EN[0] = 0x0
4983 22:15:17.407143 EX_ROW_EN[1] = 0x0
4984 22:15:17.407245 LP4Y_EN = 0x0
4985 22:15:17.410459 WORK_FSP = 0x0
4986 22:15:17.410560 WL = 0x3
4987 22:15:17.413990 RL = 0x3
4988 22:15:17.414090 BL = 0x2
4989 22:15:17.416969 RPST = 0x0
4990 22:15:17.417076 RD_PRE = 0x0
4991 22:15:17.420331 WR_PRE = 0x1
4992 22:15:17.420436 WR_PST = 0x0
4993 22:15:17.423629 DBI_WR = 0x0
4994 22:15:17.423703 DBI_RD = 0x0
4995 22:15:17.427030 OTF = 0x1
4996 22:15:17.430571 ===================================
4997 22:15:17.433482 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4998 22:15:17.436910 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4999 22:15:17.443571 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5000 22:15:17.447089 ===================================
5001 22:15:17.447198 LPDDR4 DRAM CONFIGURATION
5002 22:15:17.450035 ===================================
5003 22:15:17.453510 EX_ROW_EN[0] = 0x10
5004 22:15:17.453608 EX_ROW_EN[1] = 0x0
5005 22:15:17.457063 LP4Y_EN = 0x0
5006 22:15:17.457161 WORK_FSP = 0x0
5007 22:15:17.460680 WL = 0x3
5008 22:15:17.460783 RL = 0x3
5009 22:15:17.463726 BL = 0x2
5010 22:15:17.463823 RPST = 0x0
5011 22:15:17.466837 RD_PRE = 0x0
5012 22:15:17.466952 WR_PRE = 0x1
5013 22:15:17.470176 WR_PST = 0x0
5014 22:15:17.473825 DBI_WR = 0x0
5015 22:15:17.473934 DBI_RD = 0x0
5016 22:15:17.477060 OTF = 0x1
5017 22:15:17.480113 ===================================
5018 22:15:17.483729 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5019 22:15:17.489273 nWR fixed to 30
5020 22:15:17.492596 [ModeRegInit_LP4] CH0 RK0
5021 22:15:17.492699 [ModeRegInit_LP4] CH0 RK1
5022 22:15:17.495402 [ModeRegInit_LP4] CH1 RK0
5023 22:15:17.498887 [ModeRegInit_LP4] CH1 RK1
5024 22:15:17.498986 match AC timing 9
5025 22:15:17.505714 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5026 22:15:17.509157 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5027 22:15:17.512331 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5028 22:15:17.518863 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5029 22:15:17.522408 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5030 22:15:17.522486 ==
5031 22:15:17.525472 Dram Type= 6, Freq= 0, CH_0, rank 0
5032 22:15:17.528953 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5033 22:15:17.529030 ==
5034 22:15:17.535512 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5035 22:15:17.542579 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5036 22:15:17.545417 [CA 0] Center 37 (6~68) winsize 63
5037 22:15:17.549153 [CA 1] Center 37 (7~68) winsize 62
5038 22:15:17.552648 [CA 2] Center 34 (4~65) winsize 62
5039 22:15:17.555525 [CA 3] Center 34 (3~65) winsize 63
5040 22:15:17.558542 [CA 4] Center 33 (3~64) winsize 62
5041 22:15:17.562254 [CA 5] Center 32 (2~62) winsize 61
5042 22:15:17.562326
5043 22:15:17.565156 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5044 22:15:17.565227
5045 22:15:17.568817 [CATrainingPosCal] consider 1 rank data
5046 22:15:17.572340 u2DelayCellTimex100 = 270/100 ps
5047 22:15:17.575334 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5048 22:15:17.578383 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5049 22:15:17.581737 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5050 22:15:17.585312 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5051 22:15:17.588609 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5052 22:15:17.591961 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5053 22:15:17.595397
5054 22:15:17.598706 CA PerBit enable=1, Macro0, CA PI delay=32
5055 22:15:17.598775
5056 22:15:17.601922 [CBTSetCACLKResult] CA Dly = 32
5057 22:15:17.602017 CS Dly: 5 (0~36)
5058 22:15:17.602103 ==
5059 22:15:17.605126 Dram Type= 6, Freq= 0, CH_0, rank 1
5060 22:15:17.608978 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5061 22:15:17.609049 ==
5062 22:15:17.615569 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5063 22:15:17.621724 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5064 22:15:17.625594 [CA 0] Center 37 (6~68) winsize 63
5065 22:15:17.628479 [CA 1] Center 37 (7~68) winsize 62
5066 22:15:17.631662 [CA 2] Center 34 (4~65) winsize 62
5067 22:15:17.634943 [CA 3] Center 34 (4~65) winsize 62
5068 22:15:17.638479 [CA 4] Center 33 (3~63) winsize 61
5069 22:15:17.641920 [CA 5] Center 32 (2~62) winsize 61
5070 22:15:17.642002
5071 22:15:17.645579 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5072 22:15:17.645661
5073 22:15:17.648499 [CATrainingPosCal] consider 2 rank data
5074 22:15:17.651967 u2DelayCellTimex100 = 270/100 ps
5075 22:15:17.654979 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5076 22:15:17.658447 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5077 22:15:17.662153 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5078 22:15:17.665053 CA3 delay=34 (4~65),Diff = 2 PI (12 cell)
5079 22:15:17.668655 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5080 22:15:17.674968 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5081 22:15:17.675050
5082 22:15:17.678524 CA PerBit enable=1, Macro0, CA PI delay=32
5083 22:15:17.678606
5084 22:15:17.681250 [CBTSetCACLKResult] CA Dly = 32
5085 22:15:17.681332 CS Dly: 5 (0~37)
5086 22:15:17.681396
5087 22:15:17.684830 ----->DramcWriteLeveling(PI) begin...
5088 22:15:17.684913 ==
5089 22:15:17.688090 Dram Type= 6, Freq= 0, CH_0, rank 0
5090 22:15:17.691807 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5091 22:15:17.695059 ==
5092 22:15:17.695141 Write leveling (Byte 0): 32 => 32
5093 22:15:17.698623 Write leveling (Byte 1): 30 => 30
5094 22:15:17.701645 DramcWriteLeveling(PI) end<-----
5095 22:15:17.701726
5096 22:15:17.701790 ==
5097 22:15:17.705203 Dram Type= 6, Freq= 0, CH_0, rank 0
5098 22:15:17.712067 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5099 22:15:17.712149 ==
5100 22:15:17.712214 [Gating] SW mode calibration
5101 22:15:17.721429 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5102 22:15:17.724918 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5103 22:15:17.731630 0 14 0 | B1->B0 | 2c2c 3434 | 0 1 | (0 0) (1 1)
5104 22:15:17.735066 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5105 22:15:17.738608 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5106 22:15:17.741760 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5107 22:15:17.748183 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5108 22:15:17.751491 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5109 22:15:17.754944 0 14 24 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 1)
5110 22:15:17.761926 0 14 28 | B1->B0 | 3434 2626 | 0 1 | (0 0) (1 0)
5111 22:15:17.764998 0 15 0 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
5112 22:15:17.768358 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5113 22:15:17.775274 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5114 22:15:17.778244 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5115 22:15:17.781729 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5116 22:15:17.787803 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5117 22:15:17.791242 0 15 24 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
5118 22:15:17.794494 0 15 28 | B1->B0 | 2424 3c3c | 0 0 | (0 0) (0 0)
5119 22:15:17.801615 1 0 0 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
5120 22:15:17.804841 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5121 22:15:17.808375 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5122 22:15:17.814982 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5123 22:15:17.817698 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5124 22:15:17.821256 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5125 22:15:17.827776 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5126 22:15:17.831281 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5127 22:15:17.834918 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5128 22:15:17.841030 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5129 22:15:17.844366 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5130 22:15:17.847811 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5131 22:15:17.854382 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5132 22:15:17.857752 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5133 22:15:17.861052 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5134 22:15:17.867609 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5135 22:15:17.870668 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5136 22:15:17.874327 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5137 22:15:17.880943 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5138 22:15:17.884509 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5139 22:15:17.887509 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5140 22:15:17.891127 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5141 22:15:17.897758 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5142 22:15:17.900770 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5143 22:15:17.904499 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5144 22:15:17.908190 Total UI for P1: 0, mck2ui 16
5145 22:15:17.911360 best dqsien dly found for B0: ( 1, 2, 26)
5146 22:15:17.914311 Total UI for P1: 0, mck2ui 16
5147 22:15:17.917234 best dqsien dly found for B1: ( 1, 2, 28)
5148 22:15:17.920758 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5149 22:15:17.927623 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5150 22:15:17.927705
5151 22:15:17.931009 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5152 22:15:17.934228 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5153 22:15:17.937344 [Gating] SW calibration Done
5154 22:15:17.937425 ==
5155 22:15:17.940546 Dram Type= 6, Freq= 0, CH_0, rank 0
5156 22:15:17.944038 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5157 22:15:17.944120 ==
5158 22:15:17.944184 RX Vref Scan: 0
5159 22:15:17.947264
5160 22:15:17.947370 RX Vref 0 -> 0, step: 1
5161 22:15:17.947434
5162 22:15:17.950644 RX Delay -80 -> 252, step: 8
5163 22:15:17.954108 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5164 22:15:17.957103 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5165 22:15:17.963941 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5166 22:15:17.967573 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5167 22:15:17.970362 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5168 22:15:17.974218 iDelay=208, Bit 5, Center 91 (0 ~ 183) 184
5169 22:15:17.977699 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5170 22:15:17.980725 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5171 22:15:17.987770 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5172 22:15:17.990684 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5173 22:15:17.994409 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5174 22:15:17.997189 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5175 22:15:18.000403 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5176 22:15:18.003901 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5177 22:15:18.010813 iDelay=208, Bit 14, Center 107 (16 ~ 199) 184
5178 22:15:18.014500 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5179 22:15:18.014581 ==
5180 22:15:18.017402 Dram Type= 6, Freq= 0, CH_0, rank 0
5181 22:15:18.020389 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5182 22:15:18.020471 ==
5183 22:15:18.023812 DQS Delay:
5184 22:15:18.023892 DQS0 = 0, DQS1 = 0
5185 22:15:18.023956 DQM Delay:
5186 22:15:18.027301 DQM0 = 104, DQM1 = 95
5187 22:15:18.027407 DQ Delay:
5188 22:15:18.030821 DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =99
5189 22:15:18.033847 DQ4 =107, DQ5 =91, DQ6 =111, DQ7 =115
5190 22:15:18.037293 DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =91
5191 22:15:18.040701 DQ12 =99, DQ13 =103, DQ14 =107, DQ15 =99
5192 22:15:18.040781
5193 22:15:18.040845
5194 22:15:18.044246 ==
5195 22:15:18.047448 Dram Type= 6, Freq= 0, CH_0, rank 0
5196 22:15:18.050847 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5197 22:15:18.050928 ==
5198 22:15:18.050992
5199 22:15:18.051050
5200 22:15:18.054119 TX Vref Scan disable
5201 22:15:18.054200 == TX Byte 0 ==
5202 22:15:18.056928 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5203 22:15:18.063570 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5204 22:15:18.063652 == TX Byte 1 ==
5205 22:15:18.066993 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5206 22:15:18.073610 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5207 22:15:18.073691 ==
5208 22:15:18.077178 Dram Type= 6, Freq= 0, CH_0, rank 0
5209 22:15:18.080546 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5210 22:15:18.080628 ==
5211 22:15:18.080692
5212 22:15:18.080749
5213 22:15:18.083592 TX Vref Scan disable
5214 22:15:18.087033 == TX Byte 0 ==
5215 22:15:18.090683 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5216 22:15:18.093637 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5217 22:15:18.096962 == TX Byte 1 ==
5218 22:15:18.100398 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5219 22:15:18.103462 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5220 22:15:18.103557
5221 22:15:18.106854 [DATLAT]
5222 22:15:18.106935 Freq=933, CH0 RK0
5223 22:15:18.106999
5224 22:15:18.110226 DATLAT Default: 0xd
5225 22:15:18.110307 0, 0xFFFF, sum = 0
5226 22:15:18.113803 1, 0xFFFF, sum = 0
5227 22:15:18.113909 2, 0xFFFF, sum = 0
5228 22:15:18.116667 3, 0xFFFF, sum = 0
5229 22:15:18.116748 4, 0xFFFF, sum = 0
5230 22:15:18.120341 5, 0xFFFF, sum = 0
5231 22:15:18.120423 6, 0xFFFF, sum = 0
5232 22:15:18.123347 7, 0xFFFF, sum = 0
5233 22:15:18.123444 8, 0xFFFF, sum = 0
5234 22:15:18.126810 9, 0xFFFF, sum = 0
5235 22:15:18.126891 10, 0x0, sum = 1
5236 22:15:18.130467 11, 0x0, sum = 2
5237 22:15:18.130549 12, 0x0, sum = 3
5238 22:15:18.133517 13, 0x0, sum = 4
5239 22:15:18.133599 best_step = 11
5240 22:15:18.133663
5241 22:15:18.133721 ==
5242 22:15:18.136990 Dram Type= 6, Freq= 0, CH_0, rank 0
5243 22:15:18.140055 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5244 22:15:18.143454 ==
5245 22:15:18.143534 RX Vref Scan: 1
5246 22:15:18.143598
5247 22:15:18.146586 RX Vref 0 -> 0, step: 1
5248 22:15:18.146668
5249 22:15:18.146731 RX Delay -53 -> 252, step: 4
5250 22:15:18.150015
5251 22:15:18.150095 Set Vref, RX VrefLevel [Byte0]: 55
5252 22:15:18.153306 [Byte1]: 49
5253 22:15:18.158428
5254 22:15:18.158508 Final RX Vref Byte 0 = 55 to rank0
5255 22:15:18.161567 Final RX Vref Byte 1 = 49 to rank0
5256 22:15:18.165501 Final RX Vref Byte 0 = 55 to rank1
5257 22:15:18.168850 Final RX Vref Byte 1 = 49 to rank1==
5258 22:15:18.171505 Dram Type= 6, Freq= 0, CH_0, rank 0
5259 22:15:18.178382 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5260 22:15:18.178463 ==
5261 22:15:18.178528 DQS Delay:
5262 22:15:18.181778 DQS0 = 0, DQS1 = 0
5263 22:15:18.181860 DQM Delay:
5264 22:15:18.181924 DQM0 = 104, DQM1 = 96
5265 22:15:18.184801 DQ Delay:
5266 22:15:18.188303 DQ0 =104, DQ1 =106, DQ2 =102, DQ3 =102
5267 22:15:18.191372 DQ4 =104, DQ5 =96, DQ6 =112, DQ7 =110
5268 22:15:18.194864 DQ8 =86, DQ9 =86, DQ10 =98, DQ11 =90
5269 22:15:18.197914 DQ12 =100, DQ13 =100, DQ14 =108, DQ15 =104
5270 22:15:18.197995
5271 22:15:18.198058
5272 22:15:18.204960 [DQSOSCAuto] RK0, (LSB)MR18= 0x3027, (MSB)MR19= 0x505, tDQSOscB0 = 409 ps tDQSOscB1 = 406 ps
5273 22:15:18.207901 CH0 RK0: MR19=505, MR18=3027
5274 22:15:18.214933 CH0_RK0: MR19=0x505, MR18=0x3027, DQSOSC=406, MR23=63, INC=65, DEC=43
5275 22:15:18.215015
5276 22:15:18.218227 ----->DramcWriteLeveling(PI) begin...
5277 22:15:18.218309 ==
5278 22:15:18.221227 Dram Type= 6, Freq= 0, CH_0, rank 1
5279 22:15:18.225183 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5280 22:15:18.228494 ==
5281 22:15:18.228576 Write leveling (Byte 0): 32 => 32
5282 22:15:18.231282 Write leveling (Byte 1): 28 => 28
5283 22:15:18.234798 DramcWriteLeveling(PI) end<-----
5284 22:15:18.234879
5285 22:15:18.234943 ==
5286 22:15:18.237916 Dram Type= 6, Freq= 0, CH_0, rank 1
5287 22:15:18.244494 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5288 22:15:18.244577 ==
5289 22:15:18.244643 [Gating] SW mode calibration
5290 22:15:18.255014 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5291 22:15:18.257960 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5292 22:15:18.261360 0 14 0 | B1->B0 | 3434 3232 | 0 1 | (0 0) (1 1)
5293 22:15:18.268064 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5294 22:15:18.271110 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5295 22:15:18.274392 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5296 22:15:18.281278 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5297 22:15:18.284475 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5298 22:15:18.288202 0 14 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5299 22:15:18.295029 0 14 28 | B1->B0 | 2727 2a2a | 0 1 | (0 0) (1 0)
5300 22:15:18.297724 0 15 0 | B1->B0 | 2424 2424 | 0 0 | (0 0) (0 0)
5301 22:15:18.301041 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5302 22:15:18.307843 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5303 22:15:18.310996 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5304 22:15:18.314669 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5305 22:15:18.321164 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5306 22:15:18.324651 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5307 22:15:18.327752 0 15 28 | B1->B0 | 3838 3838 | 0 1 | (0 0) (0 0)
5308 22:15:18.334554 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5309 22:15:18.337685 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5310 22:15:18.341301 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5311 22:15:18.347899 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5312 22:15:18.351485 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5313 22:15:18.355123 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5314 22:15:18.361150 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5315 22:15:18.364909 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5316 22:15:18.367789 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5317 22:15:18.374415 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5318 22:15:18.377613 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5319 22:15:18.380601 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5320 22:15:18.387333 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5321 22:15:18.390849 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5322 22:15:18.394100 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5323 22:15:18.400586 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5324 22:15:18.403994 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5325 22:15:18.407208 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5326 22:15:18.410780 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5327 22:15:18.417439 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5328 22:15:18.420854 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5329 22:15:18.424026 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5330 22:15:18.430620 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5331 22:15:18.433856 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5332 22:15:18.437403 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5333 22:15:18.440948 Total UI for P1: 0, mck2ui 16
5334 22:15:18.443717 best dqsien dly found for B0: ( 1, 2, 28)
5335 22:15:18.447312 Total UI for P1: 0, mck2ui 16
5336 22:15:18.450350 best dqsien dly found for B1: ( 1, 2, 28)
5337 22:15:18.453419 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5338 22:15:18.459974 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5339 22:15:18.460054
5340 22:15:18.463630 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5341 22:15:18.467088 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5342 22:15:18.470232 [Gating] SW calibration Done
5343 22:15:18.470311 ==
5344 22:15:18.473525 Dram Type= 6, Freq= 0, CH_0, rank 1
5345 22:15:18.476907 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5346 22:15:18.476986 ==
5347 22:15:18.477049 RX Vref Scan: 0
5348 22:15:18.479993
5349 22:15:18.480072 RX Vref 0 -> 0, step: 1
5350 22:15:18.480134
5351 22:15:18.483459 RX Delay -80 -> 252, step: 8
5352 22:15:18.486725 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5353 22:15:18.490360 iDelay=208, Bit 1, Center 111 (24 ~ 199) 176
5354 22:15:18.497063 iDelay=208, Bit 2, Center 103 (8 ~ 199) 192
5355 22:15:18.499962 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5356 22:15:18.503131 iDelay=208, Bit 4, Center 103 (8 ~ 199) 192
5357 22:15:18.506586 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5358 22:15:18.510145 iDelay=208, Bit 6, Center 111 (24 ~ 199) 176
5359 22:15:18.513827 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5360 22:15:18.520199 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5361 22:15:18.523068 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5362 22:15:18.526751 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5363 22:15:18.530001 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5364 22:15:18.533488 iDelay=208, Bit 12, Center 95 (8 ~ 183) 176
5365 22:15:18.537124 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5366 22:15:18.543696 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5367 22:15:18.546540 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5368 22:15:18.546621 ==
5369 22:15:18.550191 Dram Type= 6, Freq= 0, CH_0, rank 1
5370 22:15:18.553689 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5371 22:15:18.553771 ==
5372 22:15:18.553835 DQS Delay:
5373 22:15:18.556705 DQS0 = 0, DQS1 = 0
5374 22:15:18.556786 DQM Delay:
5375 22:15:18.560176 DQM0 = 105, DQM1 = 93
5376 22:15:18.560257 DQ Delay:
5377 22:15:18.563578 DQ0 =103, DQ1 =111, DQ2 =103, DQ3 =99
5378 22:15:18.566507 DQ4 =103, DQ5 =95, DQ6 =111, DQ7 =115
5379 22:15:18.570036 DQ8 =83, DQ9 =87, DQ10 =95, DQ11 =87
5380 22:15:18.573130 DQ12 =95, DQ13 =99, DQ14 =99, DQ15 =99
5381 22:15:18.573211
5382 22:15:18.573275
5383 22:15:18.573334 ==
5384 22:15:18.576376 Dram Type= 6, Freq= 0, CH_0, rank 1
5385 22:15:18.582967 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5386 22:15:18.583075 ==
5387 22:15:18.583166
5388 22:15:18.583252
5389 22:15:18.583343 TX Vref Scan disable
5390 22:15:18.586842 == TX Byte 0 ==
5391 22:15:18.590326 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5392 22:15:18.596905 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5393 22:15:18.596987 == TX Byte 1 ==
5394 22:15:18.600211 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5395 22:15:18.606978 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5396 22:15:18.607059 ==
5397 22:15:18.609819 Dram Type= 6, Freq= 0, CH_0, rank 1
5398 22:15:18.613341 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5399 22:15:18.613422 ==
5400 22:15:18.613486
5401 22:15:18.613544
5402 22:15:18.616471 TX Vref Scan disable
5403 22:15:18.616552 == TX Byte 0 ==
5404 22:15:18.623486 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5405 22:15:18.626509 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5406 22:15:18.626594 == TX Byte 1 ==
5407 22:15:18.633516 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5408 22:15:18.636701 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5409 22:15:18.636782
5410 22:15:18.636846 [DATLAT]
5411 22:15:18.639937 Freq=933, CH0 RK1
5412 22:15:18.640019
5413 22:15:18.640083 DATLAT Default: 0xb
5414 22:15:18.643615 0, 0xFFFF, sum = 0
5415 22:15:18.643698 1, 0xFFFF, sum = 0
5416 22:15:18.646749 2, 0xFFFF, sum = 0
5417 22:15:18.646831 3, 0xFFFF, sum = 0
5418 22:15:18.650113 4, 0xFFFF, sum = 0
5419 22:15:18.653027 5, 0xFFFF, sum = 0
5420 22:15:18.653109 6, 0xFFFF, sum = 0
5421 22:15:18.656562 7, 0xFFFF, sum = 0
5422 22:15:18.656645 8, 0xFFFF, sum = 0
5423 22:15:18.660127 9, 0xFFFF, sum = 0
5424 22:15:18.660209 10, 0x0, sum = 1
5425 22:15:18.663004 11, 0x0, sum = 2
5426 22:15:18.663086 12, 0x0, sum = 3
5427 22:15:18.663151 13, 0x0, sum = 4
5428 22:15:18.666683 best_step = 11
5429 22:15:18.666764
5430 22:15:18.666828 ==
5431 22:15:18.670257 Dram Type= 6, Freq= 0, CH_0, rank 1
5432 22:15:18.673076 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5433 22:15:18.673161 ==
5434 22:15:18.676498 RX Vref Scan: 0
5435 22:15:18.676579
5436 22:15:18.676642 RX Vref 0 -> 0, step: 1
5437 22:15:18.679705
5438 22:15:18.679785 RX Delay -53 -> 252, step: 4
5439 22:15:18.687340 iDelay=199, Bit 0, Center 104 (15 ~ 194) 180
5440 22:15:18.691195 iDelay=199, Bit 1, Center 108 (23 ~ 194) 172
5441 22:15:18.693970 iDelay=199, Bit 2, Center 102 (15 ~ 190) 176
5442 22:15:18.697367 iDelay=199, Bit 3, Center 100 (11 ~ 190) 180
5443 22:15:18.701035 iDelay=199, Bit 4, Center 106 (19 ~ 194) 176
5444 22:15:18.707567 iDelay=199, Bit 5, Center 98 (11 ~ 186) 176
5445 22:15:18.711055 iDelay=199, Bit 6, Center 108 (23 ~ 194) 172
5446 22:15:18.714109 iDelay=199, Bit 7, Center 112 (27 ~ 198) 172
5447 22:15:18.717371 iDelay=199, Bit 8, Center 86 (3 ~ 170) 168
5448 22:15:18.720492 iDelay=199, Bit 9, Center 86 (3 ~ 170) 168
5449 22:15:18.724066 iDelay=199, Bit 10, Center 94 (11 ~ 178) 168
5450 22:15:18.730590 iDelay=199, Bit 11, Center 88 (7 ~ 170) 164
5451 22:15:18.734090 iDelay=199, Bit 12, Center 98 (15 ~ 182) 168
5452 22:15:18.737028 iDelay=199, Bit 13, Center 98 (15 ~ 182) 168
5453 22:15:18.740407 iDelay=199, Bit 14, Center 106 (23 ~ 190) 168
5454 22:15:18.743626 iDelay=199, Bit 15, Center 102 (19 ~ 186) 168
5455 22:15:18.747580 ==
5456 22:15:18.750452 Dram Type= 6, Freq= 0, CH_0, rank 1
5457 22:15:18.754123 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5458 22:15:18.754204 ==
5459 22:15:18.754268 DQS Delay:
5460 22:15:18.757165 DQS0 = 0, DQS1 = 0
5461 22:15:18.757246 DQM Delay:
5462 22:15:18.760598 DQM0 = 104, DQM1 = 94
5463 22:15:18.760679 DQ Delay:
5464 22:15:18.763577 DQ0 =104, DQ1 =108, DQ2 =102, DQ3 =100
5465 22:15:18.767274 DQ4 =106, DQ5 =98, DQ6 =108, DQ7 =112
5466 22:15:18.770940 DQ8 =86, DQ9 =86, DQ10 =94, DQ11 =88
5467 22:15:18.773714 DQ12 =98, DQ13 =98, DQ14 =106, DQ15 =102
5468 22:15:18.773795
5469 22:15:18.773859
5470 22:15:18.783660 [DQSOSCAuto] RK1, (LSB)MR18= 0x2a03, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 408 ps
5471 22:15:18.783743 CH0 RK1: MR19=505, MR18=2A03
5472 22:15:18.790675 CH0_RK1: MR19=0x505, MR18=0x2A03, DQSOSC=408, MR23=63, INC=65, DEC=43
5473 22:15:18.793580 [RxdqsGatingPostProcess] freq 933
5474 22:15:18.800435 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5475 22:15:18.803743 best DQS0 dly(2T, 0.5T) = (0, 10)
5476 22:15:18.807060 best DQS1 dly(2T, 0.5T) = (0, 10)
5477 22:15:18.810310 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5478 22:15:18.813361 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5479 22:15:18.813444 best DQS0 dly(2T, 0.5T) = (0, 10)
5480 22:15:18.817225 best DQS1 dly(2T, 0.5T) = (0, 10)
5481 22:15:18.819971 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5482 22:15:18.823706 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5483 22:15:18.826657 Pre-setting of DQS Precalculation
5484 22:15:18.833890 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5485 22:15:18.833972 ==
5486 22:15:18.836922 Dram Type= 6, Freq= 0, CH_1, rank 0
5487 22:15:18.840036 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5488 22:15:18.840118 ==
5489 22:15:18.847267 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5490 22:15:18.853388 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5491 22:15:18.856614 [CA 0] Center 36 (6~67) winsize 62
5492 22:15:18.860157 [CA 1] Center 37 (6~68) winsize 63
5493 22:15:18.863493 [CA 2] Center 35 (5~65) winsize 61
5494 22:15:18.866670 [CA 3] Center 34 (4~65) winsize 62
5495 22:15:18.870219 [CA 4] Center 34 (4~64) winsize 61
5496 22:15:18.870302 [CA 5] Center 33 (3~64) winsize 62
5497 22:15:18.873645
5498 22:15:18.876675 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5499 22:15:18.876757
5500 22:15:18.880139 [CATrainingPosCal] consider 1 rank data
5501 22:15:18.883763 u2DelayCellTimex100 = 270/100 ps
5502 22:15:18.886745 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5503 22:15:18.889742 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5504 22:15:18.893145 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5505 22:15:18.896634 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5506 22:15:18.900062 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5507 22:15:18.903097 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5508 22:15:18.903183
5509 22:15:18.906550 CA PerBit enable=1, Macro0, CA PI delay=33
5510 22:15:18.906632
5511 22:15:18.909993 [CBTSetCACLKResult] CA Dly = 33
5512 22:15:18.913179 CS Dly: 7 (0~38)
5513 22:15:18.913261 ==
5514 22:15:18.916529 Dram Type= 6, Freq= 0, CH_1, rank 1
5515 22:15:18.919943 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5516 22:15:18.920025 ==
5517 22:15:18.926505 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5518 22:15:18.933150 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5519 22:15:18.936076 [CA 0] Center 36 (6~67) winsize 62
5520 22:15:18.939524 [CA 1] Center 37 (6~68) winsize 63
5521 22:15:18.943039 [CA 2] Center 35 (5~65) winsize 61
5522 22:15:18.946558 [CA 3] Center 34 (4~65) winsize 62
5523 22:15:18.949431 [CA 4] Center 34 (4~65) winsize 62
5524 22:15:18.952780 [CA 5] Center 34 (4~64) winsize 61
5525 22:15:18.952862
5526 22:15:18.956249 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5527 22:15:18.956331
5528 22:15:18.959530 [CATrainingPosCal] consider 2 rank data
5529 22:15:18.963155 u2DelayCellTimex100 = 270/100 ps
5530 22:15:18.966061 CA0 delay=36 (6~67),Diff = 2 PI (12 cell)
5531 22:15:18.969201 CA1 delay=37 (6~68),Diff = 3 PI (18 cell)
5532 22:15:18.972862 CA2 delay=35 (5~65),Diff = 1 PI (6 cell)
5533 22:15:18.976206 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5534 22:15:18.979263 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5535 22:15:18.982961 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5536 22:15:18.983043
5537 22:15:18.989530 CA PerBit enable=1, Macro0, CA PI delay=34
5538 22:15:18.989612
5539 22:15:18.989676 [CBTSetCACLKResult] CA Dly = 34
5540 22:15:18.992674 CS Dly: 7 (0~39)
5541 22:15:18.992756
5542 22:15:18.996122 ----->DramcWriteLeveling(PI) begin...
5543 22:15:18.996205 ==
5544 22:15:18.999251 Dram Type= 6, Freq= 0, CH_1, rank 0
5545 22:15:19.002711 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5546 22:15:19.002816 ==
5547 22:15:19.005905 Write leveling (Byte 0): 26 => 26
5548 22:15:19.009533 Write leveling (Byte 1): 26 => 26
5549 22:15:19.012623 DramcWriteLeveling(PI) end<-----
5550 22:15:19.012699
5551 22:15:19.012780 ==
5552 22:15:19.015939 Dram Type= 6, Freq= 0, CH_1, rank 0
5553 22:15:19.019704 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5554 22:15:19.022505 ==
5555 22:15:19.022583 [Gating] SW mode calibration
5556 22:15:19.032698 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5557 22:15:19.036021 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5558 22:15:19.039017 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5559 22:15:19.045663 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5560 22:15:19.049313 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5561 22:15:19.052866 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5562 22:15:19.058847 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5563 22:15:19.062386 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
5564 22:15:19.065682 0 14 24 | B1->B0 | 3232 2a2a | 0 1 | (0 0) (1 0)
5565 22:15:19.072625 0 14 28 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
5566 22:15:19.075541 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5567 22:15:19.079204 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5568 22:15:19.086067 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5569 22:15:19.088712 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5570 22:15:19.092332 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5571 22:15:19.098874 0 15 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5572 22:15:19.101961 0 15 24 | B1->B0 | 2424 3131 | 0 0 | (0 0) (1 1)
5573 22:15:19.105726 0 15 28 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
5574 22:15:19.111805 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5575 22:15:19.115396 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5576 22:15:19.118512 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5577 22:15:19.125395 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5578 22:15:19.128724 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5579 22:15:19.131898 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5580 22:15:19.138424 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5581 22:15:19.141862 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5582 22:15:19.145011 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5583 22:15:19.152276 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5584 22:15:19.155092 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5585 22:15:19.158573 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5586 22:15:19.164966 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5587 22:15:19.168412 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5588 22:15:19.171707 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5589 22:15:19.178267 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5590 22:15:19.181892 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5591 22:15:19.184957 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5592 22:15:19.188593 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5593 22:15:19.194889 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5594 22:15:19.198594 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5595 22:15:19.202105 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5596 22:15:19.208769 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5597 22:15:19.211479 Total UI for P1: 0, mck2ui 16
5598 22:15:19.215126 best dqsien dly found for B0: ( 1, 2, 22)
5599 22:15:19.215228 Total UI for P1: 0, mck2ui 16
5600 22:15:19.221776 best dqsien dly found for B1: ( 1, 2, 22)
5601 22:15:19.225119 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5602 22:15:19.228478 best DQS1 dly(MCK, UI, PI) = (1, 2, 22)
5603 22:15:19.228582
5604 22:15:19.231894 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5605 22:15:19.235057 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 22)
5606 22:15:19.238263 [Gating] SW calibration Done
5607 22:15:19.238346 ==
5608 22:15:19.241711 Dram Type= 6, Freq= 0, CH_1, rank 0
5609 22:15:19.244854 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5610 22:15:19.244937 ==
5611 22:15:19.248653 RX Vref Scan: 0
5612 22:15:19.248735
5613 22:15:19.248799 RX Vref 0 -> 0, step: 1
5614 22:15:19.248860
5615 22:15:19.251460 RX Delay -80 -> 252, step: 8
5616 22:15:19.254764 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5617 22:15:19.261562 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5618 22:15:19.265141 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5619 22:15:19.268597 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5620 22:15:19.271955 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5621 22:15:19.275233 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5622 22:15:19.278501 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5623 22:15:19.285262 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5624 22:15:19.288224 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5625 22:15:19.291758 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5626 22:15:19.295263 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5627 22:15:19.298157 iDelay=208, Bit 11, Center 95 (8 ~ 183) 176
5628 22:15:19.301368 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5629 22:15:19.308432 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5630 22:15:19.311528 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5631 22:15:19.315053 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5632 22:15:19.315134 ==
5633 22:15:19.318570 Dram Type= 6, Freq= 0, CH_1, rank 0
5634 22:15:19.321440 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5635 22:15:19.321525 ==
5636 22:15:19.324865 DQS Delay:
5637 22:15:19.324946 DQS0 = 0, DQS1 = 0
5638 22:15:19.328110 DQM Delay:
5639 22:15:19.328191 DQM0 = 102, DQM1 = 98
5640 22:15:19.328256 DQ Delay:
5641 22:15:19.331159 DQ0 =103, DQ1 =95, DQ2 =91, DQ3 =99
5642 22:15:19.334958 DQ4 =99, DQ5 =115, DQ6 =111, DQ7 =103
5643 22:15:19.337679 DQ8 =87, DQ9 =87, DQ10 =99, DQ11 =95
5644 22:15:19.344315 DQ12 =107, DQ13 =103, DQ14 =99, DQ15 =107
5645 22:15:19.344398
5646 22:15:19.344462
5647 22:15:19.344522 ==
5648 22:15:19.347821 Dram Type= 6, Freq= 0, CH_1, rank 0
5649 22:15:19.351102 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5650 22:15:19.351191 ==
5651 22:15:19.351261
5652 22:15:19.351330
5653 22:15:19.355008 TX Vref Scan disable
5654 22:15:19.355102 == TX Byte 0 ==
5655 22:15:19.361637 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5656 22:15:19.364617 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5657 22:15:19.364736 == TX Byte 1 ==
5658 22:15:19.371015 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5659 22:15:19.374608 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5660 22:15:19.374744 ==
5661 22:15:19.378118 Dram Type= 6, Freq= 0, CH_1, rank 0
5662 22:15:19.381315 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5663 22:15:19.381470 ==
5664 22:15:19.381629
5665 22:15:19.381798
5666 22:15:19.384455 TX Vref Scan disable
5667 22:15:19.388057 == TX Byte 0 ==
5668 22:15:19.391255 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5669 22:15:19.394260 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5670 22:15:19.397748 == TX Byte 1 ==
5671 22:15:19.400801 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5672 22:15:19.404200 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5673 22:15:19.404283
5674 22:15:19.407456 [DATLAT]
5675 22:15:19.407542 Freq=933, CH1 RK0
5676 22:15:19.407606
5677 22:15:19.410929 DATLAT Default: 0xd
5678 22:15:19.411019 0, 0xFFFF, sum = 0
5679 22:15:19.414642 1, 0xFFFF, sum = 0
5680 22:15:19.414736 2, 0xFFFF, sum = 0
5681 22:15:19.417506 3, 0xFFFF, sum = 0
5682 22:15:19.417591 4, 0xFFFF, sum = 0
5683 22:15:19.421260 5, 0xFFFF, sum = 0
5684 22:15:19.421379 6, 0xFFFF, sum = 0
5685 22:15:19.424379 7, 0xFFFF, sum = 0
5686 22:15:19.427189 8, 0xFFFF, sum = 0
5687 22:15:19.427262 9, 0xFFFF, sum = 0
5688 22:15:19.430744 10, 0x0, sum = 1
5689 22:15:19.430823 11, 0x0, sum = 2
5690 22:15:19.430895 12, 0x0, sum = 3
5691 22:15:19.433958 13, 0x0, sum = 4
5692 22:15:19.434035 best_step = 11
5693 22:15:19.434097
5694 22:15:19.434156 ==
5695 22:15:19.437521 Dram Type= 6, Freq= 0, CH_1, rank 0
5696 22:15:19.444450 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5697 22:15:19.444551 ==
5698 22:15:19.444636 RX Vref Scan: 1
5699 22:15:19.444697
5700 22:15:19.447271 RX Vref 0 -> 0, step: 1
5701 22:15:19.447402
5702 22:15:19.450757 RX Delay -45 -> 252, step: 4
5703 22:15:19.450838
5704 22:15:19.453716 Set Vref, RX VrefLevel [Byte0]: 54
5705 22:15:19.457120 [Byte1]: 51
5706 22:15:19.457201
5707 22:15:19.460422 Final RX Vref Byte 0 = 54 to rank0
5708 22:15:19.463952 Final RX Vref Byte 1 = 51 to rank0
5709 22:15:19.466996 Final RX Vref Byte 0 = 54 to rank1
5710 22:15:19.470578 Final RX Vref Byte 1 = 51 to rank1==
5711 22:15:19.473886 Dram Type= 6, Freq= 0, CH_1, rank 0
5712 22:15:19.476985 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5713 22:15:19.477063 ==
5714 22:15:19.480636 DQS Delay:
5715 22:15:19.480719 DQS0 = 0, DQS1 = 0
5716 22:15:19.484027 DQM Delay:
5717 22:15:19.484109 DQM0 = 103, DQM1 = 100
5718 22:15:19.484175 DQ Delay:
5719 22:15:19.487561 DQ0 =106, DQ1 =98, DQ2 =94, DQ3 =100
5720 22:15:19.490262 DQ4 =102, DQ5 =112, DQ6 =112, DQ7 =102
5721 22:15:19.494157 DQ8 =88, DQ9 =90, DQ10 =100, DQ11 =94
5722 22:15:19.500433 DQ12 =108, DQ13 =106, DQ14 =110, DQ15 =110
5723 22:15:19.500516
5724 22:15:19.500581
5725 22:15:19.507329 [DQSOSCAuto] RK0, (LSB)MR18= 0x172e, (MSB)MR19= 0x505, tDQSOscB0 = 407 ps tDQSOscB1 = 414 ps
5726 22:15:19.510409 CH1 RK0: MR19=505, MR18=172E
5727 22:15:19.517155 CH1_RK0: MR19=0x505, MR18=0x172E, DQSOSC=407, MR23=63, INC=65, DEC=43
5728 22:15:19.517238
5729 22:15:19.520768 ----->DramcWriteLeveling(PI) begin...
5730 22:15:19.520852 ==
5731 22:15:19.523900 Dram Type= 6, Freq= 0, CH_1, rank 1
5732 22:15:19.527119 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5733 22:15:19.527203 ==
5734 22:15:19.530241 Write leveling (Byte 0): 28 => 28
5735 22:15:19.534049 Write leveling (Byte 1): 30 => 30
5736 22:15:19.537430 DramcWriteLeveling(PI) end<-----
5737 22:15:19.537512
5738 22:15:19.537576 ==
5739 22:15:19.540459 Dram Type= 6, Freq= 0, CH_1, rank 1
5740 22:15:19.543768 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5741 22:15:19.543891 ==
5742 22:15:19.546980 [Gating] SW mode calibration
5743 22:15:19.553774 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5744 22:15:19.560127 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5745 22:15:19.563574 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5746 22:15:19.570236 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5747 22:15:19.573318 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5748 22:15:19.576725 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5749 22:15:19.583818 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5750 22:15:19.586921 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5751 22:15:19.590103 0 14 24 | B1->B0 | 2c2c 3232 | 1 0 | (1 1) (0 0)
5752 22:15:19.593332 0 14 28 | B1->B0 | 2323 2323 | 0 1 | (1 0) (1 0)
5753 22:15:19.600001 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5754 22:15:19.603896 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5755 22:15:19.606871 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5756 22:15:19.613509 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5757 22:15:19.617073 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5758 22:15:19.619957 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5759 22:15:19.627281 0 15 24 | B1->B0 | 3535 2424 | 0 0 | (0 0) (0 0)
5760 22:15:19.630172 0 15 28 | B1->B0 | 4646 4141 | 0 0 | (0 0) (0 0)
5761 22:15:19.633643 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5762 22:15:19.640084 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5763 22:15:19.643748 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5764 22:15:19.647073 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5765 22:15:19.653980 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5766 22:15:19.657039 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5767 22:15:19.660487 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5768 22:15:19.667183 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5769 22:15:19.670610 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5770 22:15:19.673473 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5771 22:15:19.680222 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5772 22:15:19.683668 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5773 22:15:19.686490 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5774 22:15:19.690695 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5775 22:15:19.696941 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5776 22:15:19.700311 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5777 22:15:19.703918 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5778 22:15:19.710076 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5779 22:15:19.713531 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5780 22:15:19.717451 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5781 22:15:19.723712 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5782 22:15:19.726653 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5783 22:15:19.730533 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5784 22:15:19.736873 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5785 22:15:19.736999 Total UI for P1: 0, mck2ui 16
5786 22:15:19.743188 best dqsien dly found for B0: ( 1, 2, 26)
5787 22:15:19.743299 Total UI for P1: 0, mck2ui 16
5788 22:15:19.750050 best dqsien dly found for B1: ( 1, 2, 24)
5789 22:15:19.753362 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5790 22:15:19.756401 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5791 22:15:19.756506
5792 22:15:19.759814 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5793 22:15:19.762930 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5794 22:15:19.766667 [Gating] SW calibration Done
5795 22:15:19.766784 ==
5796 22:15:19.769974 Dram Type= 6, Freq= 0, CH_1, rank 1
5797 22:15:19.773172 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5798 22:15:19.773248 ==
5799 22:15:19.776353 RX Vref Scan: 0
5800 22:15:19.776451
5801 22:15:19.776548 RX Vref 0 -> 0, step: 1
5802 22:15:19.776636
5803 22:15:19.779789 RX Delay -80 -> 252, step: 8
5804 22:15:19.786561 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5805 22:15:19.789837 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5806 22:15:19.793502 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5807 22:15:19.796508 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5808 22:15:19.799589 iDelay=208, Bit 4, Center 95 (8 ~ 183) 176
5809 22:15:19.803213 iDelay=208, Bit 5, Center 119 (32 ~ 207) 176
5810 22:15:19.806389 iDelay=208, Bit 6, Center 119 (32 ~ 207) 176
5811 22:15:19.813198 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5812 22:15:19.816411 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5813 22:15:19.820060 iDelay=208, Bit 9, Center 91 (0 ~ 183) 184
5814 22:15:19.823066 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5815 22:15:19.826271 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5816 22:15:19.830008 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5817 22:15:19.836938 iDelay=208, Bit 13, Center 107 (16 ~ 199) 184
5818 22:15:19.839993 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5819 22:15:19.843144 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5820 22:15:19.843263 ==
5821 22:15:19.846461 Dram Type= 6, Freq= 0, CH_1, rank 1
5822 22:15:19.849380 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5823 22:15:19.849477 ==
5824 22:15:19.853151 DQS Delay:
5825 22:15:19.853231 DQS0 = 0, DQS1 = 0
5826 22:15:19.856164 DQM Delay:
5827 22:15:19.856245 DQM0 = 103, DQM1 = 97
5828 22:15:19.856338 DQ Delay:
5829 22:15:19.859446 DQ0 =107, DQ1 =99, DQ2 =91, DQ3 =99
5830 22:15:19.863171 DQ4 =95, DQ5 =119, DQ6 =119, DQ7 =99
5831 22:15:19.866630 DQ8 =83, DQ9 =91, DQ10 =99, DQ11 =91
5832 22:15:19.869920 DQ12 =103, DQ13 =107, DQ14 =99, DQ15 =107
5833 22:15:19.873205
5834 22:15:19.873286
5835 22:15:19.873351 ==
5836 22:15:19.876266 Dram Type= 6, Freq= 0, CH_1, rank 1
5837 22:15:19.879549 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5838 22:15:19.879633 ==
5839 22:15:19.879700
5840 22:15:19.879763
5841 22:15:19.882833 TX Vref Scan disable
5842 22:15:19.882908 == TX Byte 0 ==
5843 22:15:19.889622 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5844 22:15:19.892970 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5845 22:15:19.893044 == TX Byte 1 ==
5846 22:15:19.899448 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5847 22:15:19.903147 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5848 22:15:19.903224 ==
5849 22:15:19.906542 Dram Type= 6, Freq= 0, CH_1, rank 1
5850 22:15:19.909578 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5851 22:15:19.909657 ==
5852 22:15:19.909722
5853 22:15:19.909779
5854 22:15:19.913008 TX Vref Scan disable
5855 22:15:19.916316 == TX Byte 0 ==
5856 22:15:19.919493 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5857 22:15:19.922777 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5858 22:15:19.926128 == TX Byte 1 ==
5859 22:15:19.929302 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5860 22:15:19.933066 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5861 22:15:19.933145
5862 22:15:19.935907 [DATLAT]
5863 22:15:19.935983 Freq=933, CH1 RK1
5864 22:15:19.936055
5865 22:15:19.939638 DATLAT Default: 0xb
5866 22:15:19.939707 0, 0xFFFF, sum = 0
5867 22:15:19.942514 1, 0xFFFF, sum = 0
5868 22:15:19.942585 2, 0xFFFF, sum = 0
5869 22:15:19.946078 3, 0xFFFF, sum = 0
5870 22:15:19.946149 4, 0xFFFF, sum = 0
5871 22:15:19.949844 5, 0xFFFF, sum = 0
5872 22:15:19.949934 6, 0xFFFF, sum = 0
5873 22:15:19.953070 7, 0xFFFF, sum = 0
5874 22:15:19.953144 8, 0xFFFF, sum = 0
5875 22:15:19.956109 9, 0xFFFF, sum = 0
5876 22:15:19.956193 10, 0x0, sum = 1
5877 22:15:19.959512 11, 0x0, sum = 2
5878 22:15:19.959612 12, 0x0, sum = 3
5879 22:15:19.962839 13, 0x0, sum = 4
5880 22:15:19.962922 best_step = 11
5881 22:15:19.962986
5882 22:15:19.963044 ==
5883 22:15:19.965958 Dram Type= 6, Freq= 0, CH_1, rank 1
5884 22:15:19.969475 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5885 22:15:19.973151 ==
5886 22:15:19.973272 RX Vref Scan: 0
5887 22:15:19.973355
5888 22:15:19.976338 RX Vref 0 -> 0, step: 1
5889 22:15:19.976421
5890 22:15:19.979442 RX Delay -53 -> 252, step: 4
5891 22:15:19.982554 iDelay=203, Bit 0, Center 110 (27 ~ 194) 168
5892 22:15:19.986048 iDelay=203, Bit 1, Center 98 (15 ~ 182) 168
5893 22:15:19.993017 iDelay=203, Bit 2, Center 94 (11 ~ 178) 168
5894 22:15:19.995816 iDelay=203, Bit 3, Center 100 (19 ~ 182) 164
5895 22:15:19.999168 iDelay=203, Bit 4, Center 100 (19 ~ 182) 164
5896 22:15:20.002415 iDelay=203, Bit 5, Center 118 (35 ~ 202) 168
5897 22:15:20.005708 iDelay=203, Bit 6, Center 114 (31 ~ 198) 168
5898 22:15:20.012812 iDelay=203, Bit 7, Center 102 (19 ~ 186) 168
5899 22:15:20.016003 iDelay=203, Bit 8, Center 92 (11 ~ 174) 164
5900 22:15:20.019236 iDelay=203, Bit 9, Center 92 (7 ~ 178) 172
5901 22:15:20.022261 iDelay=203, Bit 10, Center 102 (19 ~ 186) 168
5902 22:15:20.025627 iDelay=203, Bit 11, Center 94 (11 ~ 178) 168
5903 22:15:20.029365 iDelay=203, Bit 12, Center 110 (23 ~ 198) 176
5904 22:15:20.036046 iDelay=203, Bit 13, Center 106 (23 ~ 190) 168
5905 22:15:20.038907 iDelay=203, Bit 14, Center 106 (23 ~ 190) 168
5906 22:15:20.042717 iDelay=203, Bit 15, Center 108 (23 ~ 194) 172
5907 22:15:20.042791 ==
5908 22:15:20.046077 Dram Type= 6, Freq= 0, CH_1, rank 1
5909 22:15:20.049086 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5910 22:15:20.052586 ==
5911 22:15:20.052659 DQS Delay:
5912 22:15:20.052739 DQS0 = 0, DQS1 = 0
5913 22:15:20.055964 DQM Delay:
5914 22:15:20.056069 DQM0 = 104, DQM1 = 101
5915 22:15:20.058908 DQ Delay:
5916 22:15:20.062271 DQ0 =110, DQ1 =98, DQ2 =94, DQ3 =100
5917 22:15:20.065471 DQ4 =100, DQ5 =118, DQ6 =114, DQ7 =102
5918 22:15:20.068796 DQ8 =92, DQ9 =92, DQ10 =102, DQ11 =94
5919 22:15:20.072455 DQ12 =110, DQ13 =106, DQ14 =106, DQ15 =108
5920 22:15:20.072565
5921 22:15:20.072662
5922 22:15:20.079072 [DQSOSCAuto] RK1, (LSB)MR18= 0x3003, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 406 ps
5923 22:15:20.082247 CH1 RK1: MR19=505, MR18=3003
5924 22:15:20.088796 CH1_RK1: MR19=0x505, MR18=0x3003, DQSOSC=406, MR23=63, INC=65, DEC=43
5925 22:15:20.092046 [RxdqsGatingPostProcess] freq 933
5926 22:15:20.098715 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5927 22:15:20.098796 best DQS0 dly(2T, 0.5T) = (0, 10)
5928 22:15:20.101977 best DQS1 dly(2T, 0.5T) = (0, 10)
5929 22:15:20.105492 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5930 22:15:20.109355 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5931 22:15:20.112109 best DQS0 dly(2T, 0.5T) = (0, 10)
5932 22:15:20.115408 best DQS1 dly(2T, 0.5T) = (0, 10)
5933 22:15:20.118750 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5934 22:15:20.122177 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5935 22:15:20.125480 Pre-setting of DQS Precalculation
5936 22:15:20.128649 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5937 22:15:20.138562 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5938 22:15:20.145178 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5939 22:15:20.145285
5940 22:15:20.145380
5941 22:15:20.148737 [Calibration Summary] 1866 Mbps
5942 22:15:20.148837 CH 0, Rank 0
5943 22:15:20.151534 SW Impedance : PASS
5944 22:15:20.155477 DUTY Scan : NO K
5945 22:15:20.155577 ZQ Calibration : PASS
5946 22:15:20.158587 Jitter Meter : NO K
5947 22:15:20.158658 CBT Training : PASS
5948 22:15:20.161996 Write leveling : PASS
5949 22:15:20.165178 RX DQS gating : PASS
5950 22:15:20.165279 RX DQ/DQS(RDDQC) : PASS
5951 22:15:20.168485 TX DQ/DQS : PASS
5952 22:15:20.171554 RX DATLAT : PASS
5953 22:15:20.171655 RX DQ/DQS(Engine): PASS
5954 22:15:20.175065 TX OE : NO K
5955 22:15:20.175169 All Pass.
5956 22:15:20.175258
5957 22:15:20.178413 CH 0, Rank 1
5958 22:15:20.178509 SW Impedance : PASS
5959 22:15:20.182051 DUTY Scan : NO K
5960 22:15:20.185265 ZQ Calibration : PASS
5961 22:15:20.185360 Jitter Meter : NO K
5962 22:15:20.188210 CBT Training : PASS
5963 22:15:20.191831 Write leveling : PASS
5964 22:15:20.191906 RX DQS gating : PASS
5965 22:15:20.195197 RX DQ/DQS(RDDQC) : PASS
5966 22:15:20.198519 TX DQ/DQS : PASS
5967 22:15:20.198598 RX DATLAT : PASS
5968 22:15:20.201943 RX DQ/DQS(Engine): PASS
5969 22:15:20.202043 TX OE : NO K
5970 22:15:20.205035 All Pass.
5971 22:15:20.205149
5972 22:15:20.205217 CH 1, Rank 0
5973 22:15:20.208430 SW Impedance : PASS
5974 22:15:20.208535 DUTY Scan : NO K
5975 22:15:20.211710 ZQ Calibration : PASS
5976 22:15:20.214961 Jitter Meter : NO K
5977 22:15:20.215036 CBT Training : PASS
5978 22:15:20.218467 Write leveling : PASS
5979 22:15:20.221629 RX DQS gating : PASS
5980 22:15:20.221732 RX DQ/DQS(RDDQC) : PASS
5981 22:15:20.225119 TX DQ/DQS : PASS
5982 22:15:20.228471 RX DATLAT : PASS
5983 22:15:20.228578 RX DQ/DQS(Engine): PASS
5984 22:15:20.231931 TX OE : NO K
5985 22:15:20.232038 All Pass.
5986 22:15:20.232100
5987 22:15:20.235526 CH 1, Rank 1
5988 22:15:20.235618 SW Impedance : PASS
5989 22:15:20.238411 DUTY Scan : NO K
5990 22:15:20.241868 ZQ Calibration : PASS
5991 22:15:20.241975 Jitter Meter : NO K
5992 22:15:20.245371 CBT Training : PASS
5993 22:15:20.245480 Write leveling : PASS
5994 22:15:20.248163 RX DQS gating : PASS
5995 22:15:20.251753 RX DQ/DQS(RDDQC) : PASS
5996 22:15:20.251827 TX DQ/DQS : PASS
5997 22:15:20.254979 RX DATLAT : PASS
5998 22:15:20.258196 RX DQ/DQS(Engine): PASS
5999 22:15:20.258303 TX OE : NO K
6000 22:15:20.261848 All Pass.
6001 22:15:20.261925
6002 22:15:20.261988 DramC Write-DBI off
6003 22:15:20.265327 PER_BANK_REFRESH: Hybrid Mode
6004 22:15:20.268460 TX_TRACKING: ON
6005 22:15:20.275141 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6006 22:15:20.278181 [FAST_K] Save calibration result to emmc
6007 22:15:20.281723 dramc_set_vcore_voltage set vcore to 650000
6008 22:15:20.284876 Read voltage for 400, 6
6009 22:15:20.284985 Vio18 = 0
6010 22:15:20.288686 Vcore = 650000
6011 22:15:20.288792 Vdram = 0
6012 22:15:20.288889 Vddq = 0
6013 22:15:20.291654 Vmddr = 0
6014 22:15:20.295246 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6015 22:15:20.301603 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6016 22:15:20.301714 MEM_TYPE=3, freq_sel=20
6017 22:15:20.305093 sv_algorithm_assistance_LP4_800
6018 22:15:20.311410 ============ PULL DRAM RESETB DOWN ============
6019 22:15:20.314826 ========== PULL DRAM RESETB DOWN end =========
6020 22:15:20.318367 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6021 22:15:20.321578 ===================================
6022 22:15:20.324876 LPDDR4 DRAM CONFIGURATION
6023 22:15:20.327925 ===================================
6024 22:15:20.328034 EX_ROW_EN[0] = 0x0
6025 22:15:20.331462 EX_ROW_EN[1] = 0x0
6026 22:15:20.334919 LP4Y_EN = 0x0
6027 22:15:20.335041 WORK_FSP = 0x0
6028 22:15:20.338295 WL = 0x2
6029 22:15:20.338389 RL = 0x2
6030 22:15:20.341337 BL = 0x2
6031 22:15:20.341445 RPST = 0x0
6032 22:15:20.345167 RD_PRE = 0x0
6033 22:15:20.345269 WR_PRE = 0x1
6034 22:15:20.348045 WR_PST = 0x0
6035 22:15:20.348141 DBI_WR = 0x0
6036 22:15:20.351492 DBI_RD = 0x0
6037 22:15:20.351581 OTF = 0x1
6038 22:15:20.354947 ===================================
6039 22:15:20.357860 ===================================
6040 22:15:20.361356 ANA top config
6041 22:15:20.364534 ===================================
6042 22:15:20.364617 DLL_ASYNC_EN = 0
6043 22:15:20.368192 ALL_SLAVE_EN = 1
6044 22:15:20.371222 NEW_RANK_MODE = 1
6045 22:15:20.374563 DLL_IDLE_MODE = 1
6046 22:15:20.377905 LP45_APHY_COMB_EN = 1
6047 22:15:20.378016 TX_ODT_DIS = 1
6048 22:15:20.381340 NEW_8X_MODE = 1
6049 22:15:20.384445 ===================================
6050 22:15:20.388030 ===================================
6051 22:15:20.391739 data_rate = 800
6052 22:15:20.394771 CKR = 1
6053 22:15:20.397751 DQ_P2S_RATIO = 4
6054 22:15:20.401228 ===================================
6055 22:15:20.401384 CA_P2S_RATIO = 4
6056 22:15:20.404705 DQ_CA_OPEN = 0
6057 22:15:20.408045 DQ_SEMI_OPEN = 1
6058 22:15:20.411666 CA_SEMI_OPEN = 1
6059 22:15:20.414691 CA_FULL_RATE = 0
6060 22:15:20.418165 DQ_CKDIV4_EN = 0
6061 22:15:20.418247 CA_CKDIV4_EN = 1
6062 22:15:20.421001 CA_PREDIV_EN = 0
6063 22:15:20.424412 PH8_DLY = 0
6064 22:15:20.427933 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6065 22:15:20.430944 DQ_AAMCK_DIV = 0
6066 22:15:20.434332 CA_AAMCK_DIV = 0
6067 22:15:20.434446 CA_ADMCK_DIV = 4
6068 22:15:20.438028 DQ_TRACK_CA_EN = 0
6069 22:15:20.441158 CA_PICK = 800
6070 22:15:20.444874 CA_MCKIO = 400
6071 22:15:20.447829 MCKIO_SEMI = 400
6072 22:15:20.451138 PLL_FREQ = 3016
6073 22:15:20.454507 DQ_UI_PI_RATIO = 32
6074 22:15:20.454593 CA_UI_PI_RATIO = 32
6075 22:15:20.457724 ===================================
6076 22:15:20.460856 ===================================
6077 22:15:20.464559 memory_type:LPDDR4
6078 22:15:20.467790 GP_NUM : 10
6079 22:15:20.467876 SRAM_EN : 1
6080 22:15:20.470991 MD32_EN : 0
6081 22:15:20.474345 ===================================
6082 22:15:20.477422 [ANA_INIT] >>>>>>>>>>>>>>
6083 22:15:20.481011 <<<<<< [CONFIGURE PHASE]: ANA_TX
6084 22:15:20.484885 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6085 22:15:20.487578 ===================================
6086 22:15:20.487706 data_rate = 800,PCW = 0X7400
6087 22:15:20.491281 ===================================
6088 22:15:20.494774 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6089 22:15:20.501334 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6090 22:15:20.514262 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6091 22:15:20.517318 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6092 22:15:20.520738 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6093 22:15:20.524126 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6094 22:15:20.527358 [ANA_INIT] flow start
6095 22:15:20.527439 [ANA_INIT] PLL >>>>>>>>
6096 22:15:20.531028 [ANA_INIT] PLL <<<<<<<<
6097 22:15:20.534252 [ANA_INIT] MIDPI >>>>>>>>
6098 22:15:20.534333 [ANA_INIT] MIDPI <<<<<<<<
6099 22:15:20.537279 [ANA_INIT] DLL >>>>>>>>
6100 22:15:20.540954 [ANA_INIT] flow end
6101 22:15:20.543788 ============ LP4 DIFF to SE enter ============
6102 22:15:20.547031 ============ LP4 DIFF to SE exit ============
6103 22:15:20.550454 [ANA_INIT] <<<<<<<<<<<<<
6104 22:15:20.553990 [Flow] Enable top DCM control >>>>>
6105 22:15:20.557094 [Flow] Enable top DCM control <<<<<
6106 22:15:20.560697 Enable DLL master slave shuffle
6107 22:15:20.563725 ==============================================================
6108 22:15:20.567495 Gating Mode config
6109 22:15:20.573695 ==============================================================
6110 22:15:20.573778 Config description:
6111 22:15:20.583718 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6112 22:15:20.590467 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6113 22:15:20.597054 SELPH_MODE 0: By rank 1: By Phase
6114 22:15:20.600172 ==============================================================
6115 22:15:20.603201 GAT_TRACK_EN = 0
6116 22:15:20.606952 RX_GATING_MODE = 2
6117 22:15:20.609907 RX_GATING_TRACK_MODE = 2
6118 22:15:20.613460 SELPH_MODE = 1
6119 22:15:20.616869 PICG_EARLY_EN = 1
6120 22:15:20.620072 VALID_LAT_VALUE = 1
6121 22:15:20.623509 ==============================================================
6122 22:15:20.626779 Enter into Gating configuration >>>>
6123 22:15:20.630414 Exit from Gating configuration <<<<
6124 22:15:20.633213 Enter into DVFS_PRE_config >>>>>
6125 22:15:20.646329 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6126 22:15:20.649741 Exit from DVFS_PRE_config <<<<<
6127 22:15:20.653160 Enter into PICG configuration >>>>
6128 22:15:20.656849 Exit from PICG configuration <<<<
6129 22:15:20.656931 [RX_INPUT] configuration >>>>>
6130 22:15:20.659476 [RX_INPUT] configuration <<<<<
6131 22:15:20.666452 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6132 22:15:20.669772 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6133 22:15:20.676090 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6134 22:15:20.683132 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6135 22:15:20.689577 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6136 22:15:20.696289 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6137 22:15:20.699810 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6138 22:15:20.702792 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6139 22:15:20.709397 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6140 22:15:20.713090 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6141 22:15:20.715945 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6142 22:15:20.719546 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6143 22:15:20.722532 ===================================
6144 22:15:20.726419 LPDDR4 DRAM CONFIGURATION
6145 22:15:20.729235 ===================================
6146 22:15:20.732723 EX_ROW_EN[0] = 0x0
6147 22:15:20.732813 EX_ROW_EN[1] = 0x0
6148 22:15:20.735725 LP4Y_EN = 0x0
6149 22:15:20.735807 WORK_FSP = 0x0
6150 22:15:20.739039 WL = 0x2
6151 22:15:20.739120 RL = 0x2
6152 22:15:20.742443 BL = 0x2
6153 22:15:20.742551 RPST = 0x0
6154 22:15:20.745943 RD_PRE = 0x0
6155 22:15:20.746053 WR_PRE = 0x1
6156 22:15:20.749114 WR_PST = 0x0
6157 22:15:20.752686 DBI_WR = 0x0
6158 22:15:20.752767 DBI_RD = 0x0
6159 22:15:20.756036 OTF = 0x1
6160 22:15:20.759073 ===================================
6161 22:15:20.762560 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6162 22:15:20.766009 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6163 22:15:20.769024 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6164 22:15:20.772694 ===================================
6165 22:15:20.775669 LPDDR4 DRAM CONFIGURATION
6166 22:15:20.779190 ===================================
6167 22:15:20.782416 EX_ROW_EN[0] = 0x10
6168 22:15:20.782496 EX_ROW_EN[1] = 0x0
6169 22:15:20.785448 LP4Y_EN = 0x0
6170 22:15:20.785551 WORK_FSP = 0x0
6171 22:15:20.789087 WL = 0x2
6172 22:15:20.789190 RL = 0x2
6173 22:15:20.791988 BL = 0x2
6174 22:15:20.792071 RPST = 0x0
6175 22:15:20.795796 RD_PRE = 0x0
6176 22:15:20.795906 WR_PRE = 0x1
6177 22:15:20.798670 WR_PST = 0x0
6178 22:15:20.798773 DBI_WR = 0x0
6179 22:15:20.802288 DBI_RD = 0x0
6180 22:15:20.802396 OTF = 0x1
6181 22:15:20.805771 ===================================
6182 22:15:20.812235 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6183 22:15:20.816974 nWR fixed to 30
6184 22:15:20.820753 [ModeRegInit_LP4] CH0 RK0
6185 22:15:20.820861 [ModeRegInit_LP4] CH0 RK1
6186 22:15:20.823684 [ModeRegInit_LP4] CH1 RK0
6187 22:15:20.826901 [ModeRegInit_LP4] CH1 RK1
6188 22:15:20.827007 match AC timing 19
6189 22:15:20.834203 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6190 22:15:20.837104 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6191 22:15:20.840488 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6192 22:15:20.847280 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6193 22:15:20.850638 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6194 22:15:20.850753 ==
6195 22:15:20.854215 Dram Type= 6, Freq= 0, CH_0, rank 0
6196 22:15:20.857202 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6197 22:15:20.857304 ==
6198 22:15:20.863604 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6199 22:15:20.870298 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6200 22:15:20.873826 [CA 0] Center 36 (8~64) winsize 57
6201 22:15:20.876979 [CA 1] Center 36 (8~64) winsize 57
6202 22:15:20.880487 [CA 2] Center 36 (8~64) winsize 57
6203 22:15:20.880571 [CA 3] Center 36 (8~64) winsize 57
6204 22:15:20.883582 [CA 4] Center 36 (8~64) winsize 57
6205 22:15:20.887029 [CA 5] Center 36 (8~64) winsize 57
6206 22:15:20.887136
6207 22:15:20.893773 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6208 22:15:20.893854
6209 22:15:20.896907 [CATrainingPosCal] consider 1 rank data
6210 22:15:20.900060 u2DelayCellTimex100 = 270/100 ps
6211 22:15:20.903554 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6212 22:15:20.906908 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6213 22:15:20.910420 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6214 22:15:20.913436 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6215 22:15:20.916661 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6216 22:15:20.920413 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6217 22:15:20.920495
6218 22:15:20.923410 CA PerBit enable=1, Macro0, CA PI delay=36
6219 22:15:20.923484
6220 22:15:20.926838 [CBTSetCACLKResult] CA Dly = 36
6221 22:15:20.929936 CS Dly: 1 (0~32)
6222 22:15:20.930015 ==
6223 22:15:20.933782 Dram Type= 6, Freq= 0, CH_0, rank 1
6224 22:15:20.936824 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6225 22:15:20.936900 ==
6226 22:15:20.943166 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6227 22:15:20.946375 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6228 22:15:20.950105 [CA 0] Center 36 (8~64) winsize 57
6229 22:15:20.953411 [CA 1] Center 36 (8~64) winsize 57
6230 22:15:20.956520 [CA 2] Center 36 (8~64) winsize 57
6231 22:15:20.960106 [CA 3] Center 36 (8~64) winsize 57
6232 22:15:20.963286 [CA 4] Center 36 (8~64) winsize 57
6233 22:15:20.966398 [CA 5] Center 36 (8~64) winsize 57
6234 22:15:20.966484
6235 22:15:20.969936 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6236 22:15:20.970017
6237 22:15:20.973121 [CATrainingPosCal] consider 2 rank data
6238 22:15:20.976623 u2DelayCellTimex100 = 270/100 ps
6239 22:15:20.979819 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6240 22:15:20.982963 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6241 22:15:20.986487 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6242 22:15:20.993304 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6243 22:15:20.996831 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6244 22:15:20.999905 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6245 22:15:21.000001
6246 22:15:21.003137 CA PerBit enable=1, Macro0, CA PI delay=36
6247 22:15:21.003218
6248 22:15:21.006257 [CBTSetCACLKResult] CA Dly = 36
6249 22:15:21.006337 CS Dly: 1 (0~32)
6250 22:15:21.006402
6251 22:15:21.009563 ----->DramcWriteLeveling(PI) begin...
6252 22:15:21.012934 ==
6253 22:15:21.013102 Dram Type= 6, Freq= 0, CH_0, rank 0
6254 22:15:21.019973 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6255 22:15:21.020057 ==
6256 22:15:21.022711 Write leveling (Byte 0): 40 => 8
6257 22:15:21.026337 Write leveling (Byte 1): 40 => 8
6258 22:15:21.026412 DramcWriteLeveling(PI) end<-----
6259 22:15:21.029476
6260 22:15:21.029551 ==
6261 22:15:21.033036 Dram Type= 6, Freq= 0, CH_0, rank 0
6262 22:15:21.036706 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6263 22:15:21.036786 ==
6264 22:15:21.039680 [Gating] SW mode calibration
6265 22:15:21.046045 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6266 22:15:21.049582 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6267 22:15:21.056137 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6268 22:15:21.059418 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6269 22:15:21.062959 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6270 22:15:21.069529 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6271 22:15:21.072746 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6272 22:15:21.076001 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6273 22:15:21.082269 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6274 22:15:21.085595 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6275 22:15:21.089414 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6276 22:15:21.092597 Total UI for P1: 0, mck2ui 16
6277 22:15:21.095833 best dqsien dly found for B0: ( 0, 14, 24)
6278 22:15:21.099267 Total UI for P1: 0, mck2ui 16
6279 22:15:21.102352 best dqsien dly found for B1: ( 0, 14, 24)
6280 22:15:21.106012 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6281 22:15:21.109211 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6282 22:15:21.112223
6283 22:15:21.115467 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6284 22:15:21.119204 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6285 22:15:21.122592 [Gating] SW calibration Done
6286 22:15:21.122669 ==
6287 22:15:21.125403 Dram Type= 6, Freq= 0, CH_0, rank 0
6288 22:15:21.128975 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6289 22:15:21.129064 ==
6290 22:15:21.129133 RX Vref Scan: 0
6291 22:15:21.132766
6292 22:15:21.132838 RX Vref 0 -> 0, step: 1
6293 22:15:21.132900
6294 22:15:21.135777 RX Delay -410 -> 252, step: 16
6295 22:15:21.139273 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6296 22:15:21.145300 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6297 22:15:21.148998 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6298 22:15:21.152106 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6299 22:15:21.155605 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6300 22:15:21.162380 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6301 22:15:21.165598 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6302 22:15:21.168968 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6303 22:15:21.172445 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6304 22:15:21.178943 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6305 22:15:21.182086 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6306 22:15:21.185525 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6307 22:15:21.189006 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6308 22:15:21.195781 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6309 22:15:21.198547 iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448
6310 22:15:21.202038 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6311 22:15:21.202111 ==
6312 22:15:21.205567 Dram Type= 6, Freq= 0, CH_0, rank 0
6313 22:15:21.208766 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6314 22:15:21.212310 ==
6315 22:15:21.212384 DQS Delay:
6316 22:15:21.212444 DQS0 = 27, DQS1 = 35
6317 22:15:21.215597 DQM Delay:
6318 22:15:21.215664 DQM0 = 12, DQM1 = 12
6319 22:15:21.218723 DQ Delay:
6320 22:15:21.218804 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6321 22:15:21.222054 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =24
6322 22:15:21.225412 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6323 22:15:21.228727 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6324 22:15:21.228802
6325 22:15:21.228867
6326 22:15:21.231945 ==
6327 22:15:21.235092 Dram Type= 6, Freq= 0, CH_0, rank 0
6328 22:15:21.238431 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6329 22:15:21.238509 ==
6330 22:15:21.238572
6331 22:15:21.238637
6332 22:15:21.241866 TX Vref Scan disable
6333 22:15:21.241933 == TX Byte 0 ==
6334 22:15:21.244952 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6335 22:15:21.252023 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6336 22:15:21.252099 == TX Byte 1 ==
6337 22:15:21.254941 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6338 22:15:21.258637 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6339 22:15:21.261985 ==
6340 22:15:21.265295 Dram Type= 6, Freq= 0, CH_0, rank 0
6341 22:15:21.268331 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6342 22:15:21.268413 ==
6343 22:15:21.268476
6344 22:15:21.268535
6345 22:15:21.271656 TX Vref Scan disable
6346 22:15:21.271736 == TX Byte 0 ==
6347 22:15:21.275527 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6348 22:15:21.282130 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6349 22:15:21.282230 == TX Byte 1 ==
6350 22:15:21.285102 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6351 22:15:21.288820 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6352 22:15:21.292178
6353 22:15:21.292260 [DATLAT]
6354 22:15:21.292325 Freq=400, CH0 RK0
6355 22:15:21.292386
6356 22:15:21.295300 DATLAT Default: 0xf
6357 22:15:21.295431 0, 0xFFFF, sum = 0
6358 22:15:21.298457 1, 0xFFFF, sum = 0
6359 22:15:21.298541 2, 0xFFFF, sum = 0
6360 22:15:21.302144 3, 0xFFFF, sum = 0
6361 22:15:21.302242 4, 0xFFFF, sum = 0
6362 22:15:21.305513 5, 0xFFFF, sum = 0
6363 22:15:21.305613 6, 0xFFFF, sum = 0
6364 22:15:21.308851 7, 0xFFFF, sum = 0
6365 22:15:21.311994 8, 0xFFFF, sum = 0
6366 22:15:21.312078 9, 0xFFFF, sum = 0
6367 22:15:21.315529 10, 0xFFFF, sum = 0
6368 22:15:21.315613 11, 0xFFFF, sum = 0
6369 22:15:21.318555 12, 0xFFFF, sum = 0
6370 22:15:21.318638 13, 0x0, sum = 1
6371 22:15:21.322131 14, 0x0, sum = 2
6372 22:15:21.322215 15, 0x0, sum = 3
6373 22:15:21.325756 16, 0x0, sum = 4
6374 22:15:21.325840 best_step = 14
6375 22:15:21.325905
6376 22:15:21.325966 ==
6377 22:15:21.329005 Dram Type= 6, Freq= 0, CH_0, rank 0
6378 22:15:21.332435 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6379 22:15:21.332519 ==
6380 22:15:21.335242 RX Vref Scan: 1
6381 22:15:21.335390
6382 22:15:21.338519 RX Vref 0 -> 0, step: 1
6383 22:15:21.338602
6384 22:15:21.338666 RX Delay -311 -> 252, step: 8
6385 22:15:21.338727
6386 22:15:21.341706 Set Vref, RX VrefLevel [Byte0]: 55
6387 22:15:21.345379 [Byte1]: 49
6388 22:15:21.350231
6389 22:15:21.350313 Final RX Vref Byte 0 = 55 to rank0
6390 22:15:21.353948 Final RX Vref Byte 1 = 49 to rank0
6391 22:15:21.356905 Final RX Vref Byte 0 = 55 to rank1
6392 22:15:21.360705 Final RX Vref Byte 1 = 49 to rank1==
6393 22:15:21.363727 Dram Type= 6, Freq= 0, CH_0, rank 0
6394 22:15:21.370983 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6395 22:15:21.371066 ==
6396 22:15:21.371131 DQS Delay:
6397 22:15:21.373795 DQS0 = 28, DQS1 = 36
6398 22:15:21.373878 DQM Delay:
6399 22:15:21.373943 DQM0 = 11, DQM1 = 13
6400 22:15:21.376798 DQ Delay:
6401 22:15:21.380690 DQ0 =12, DQ1 =16, DQ2 =8, DQ3 =8
6402 22:15:21.380773 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6403 22:15:21.383674 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6404 22:15:21.387345 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6405 22:15:21.387427
6406 22:15:21.390279
6407 22:15:21.396804 [DQSOSCAuto] RK0, (LSB)MR18= 0xcbb8, (MSB)MR19= 0xc0c, tDQSOscB0 = 386 ps tDQSOscB1 = 384 ps
6408 22:15:21.400054 CH0 RK0: MR19=C0C, MR18=CBB8
6409 22:15:21.406670 CH0_RK0: MR19=0xC0C, MR18=0xCBB8, DQSOSC=384, MR23=63, INC=400, DEC=267
6410 22:15:21.406753 ==
6411 22:15:21.410046 Dram Type= 6, Freq= 0, CH_0, rank 1
6412 22:15:21.413340 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6413 22:15:21.413423 ==
6414 22:15:21.416758 [Gating] SW mode calibration
6415 22:15:21.423510 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6416 22:15:21.429777 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6417 22:15:21.433150 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6418 22:15:21.436773 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6419 22:15:21.443485 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6420 22:15:21.446820 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6421 22:15:21.450290 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6422 22:15:21.453217 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6423 22:15:21.459988 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6424 22:15:21.463595 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6425 22:15:21.466566 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6426 22:15:21.470381 Total UI for P1: 0, mck2ui 16
6427 22:15:21.473307 best dqsien dly found for B0: ( 0, 14, 24)
6428 22:15:21.477027 Total UI for P1: 0, mck2ui 16
6429 22:15:21.479960 best dqsien dly found for B1: ( 0, 14, 24)
6430 22:15:21.483457 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6431 22:15:21.489987 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6432 22:15:21.490070
6433 22:15:21.493501 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6434 22:15:21.496563 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6435 22:15:21.499763 [Gating] SW calibration Done
6436 22:15:21.499846 ==
6437 22:15:21.503123 Dram Type= 6, Freq= 0, CH_0, rank 1
6438 22:15:21.506719 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6439 22:15:21.506803 ==
6440 22:15:21.510122 RX Vref Scan: 0
6441 22:15:21.510205
6442 22:15:21.510270 RX Vref 0 -> 0, step: 1
6443 22:15:21.510330
6444 22:15:21.513008 RX Delay -410 -> 252, step: 16
6445 22:15:21.516599 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6446 22:15:21.522980 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6447 22:15:21.526291 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6448 22:15:21.529642 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6449 22:15:21.533244 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6450 22:15:21.539663 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6451 22:15:21.542921 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6452 22:15:21.546308 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6453 22:15:21.549599 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6454 22:15:21.556365 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6455 22:15:21.560102 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6456 22:15:21.562873 iDelay=230, Bit 11, Center -27 (-250 ~ 197) 448
6457 22:15:21.566012 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6458 22:15:21.572643 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6459 22:15:21.576365 iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448
6460 22:15:21.579148 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6461 22:15:21.579229 ==
6462 22:15:21.582682 Dram Type= 6, Freq= 0, CH_0, rank 1
6463 22:15:21.589206 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6464 22:15:21.589288 ==
6465 22:15:21.589352 DQS Delay:
6466 22:15:21.592803 DQS0 = 27, DQS1 = 35
6467 22:15:21.592883 DQM Delay:
6468 22:15:21.592947 DQM0 = 12, DQM1 = 12
6469 22:15:21.595944 DQ Delay:
6470 22:15:21.599226 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6471 22:15:21.599307 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6472 22:15:21.602363 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6473 22:15:21.606122 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6474 22:15:21.606202
6475 22:15:21.609198
6476 22:15:21.609279 ==
6477 22:15:21.612403 Dram Type= 6, Freq= 0, CH_0, rank 1
6478 22:15:21.615856 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6479 22:15:21.615937 ==
6480 22:15:21.616001
6481 22:15:21.616058
6482 22:15:21.619239 TX Vref Scan disable
6483 22:15:21.619330 == TX Byte 0 ==
6484 22:15:21.622153 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6485 22:15:21.629331 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6486 22:15:21.629413 == TX Byte 1 ==
6487 22:15:21.632934 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6488 22:15:21.638773 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6489 22:15:21.638880 ==
6490 22:15:21.642485 Dram Type= 6, Freq= 0, CH_0, rank 1
6491 22:15:21.646270 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6492 22:15:21.646412 ==
6493 22:15:21.646504
6494 22:15:21.646591
6495 22:15:21.648895 TX Vref Scan disable
6496 22:15:21.648993 == TX Byte 0 ==
6497 22:15:21.652294 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6498 22:15:21.659023 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6499 22:15:21.659105 == TX Byte 1 ==
6500 22:15:21.662413 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6501 22:15:21.669206 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6502 22:15:21.669315
6503 22:15:21.669393 [DATLAT]
6504 22:15:21.669476 Freq=400, CH0 RK1
6505 22:15:21.669567
6506 22:15:21.672849 DATLAT Default: 0xe
6507 22:15:21.672958 0, 0xFFFF, sum = 0
6508 22:15:21.675865 1, 0xFFFF, sum = 0
6509 22:15:21.679116 2, 0xFFFF, sum = 0
6510 22:15:21.679198 3, 0xFFFF, sum = 0
6511 22:15:21.682677 4, 0xFFFF, sum = 0
6512 22:15:21.682759 5, 0xFFFF, sum = 0
6513 22:15:21.685522 6, 0xFFFF, sum = 0
6514 22:15:21.685612 7, 0xFFFF, sum = 0
6515 22:15:21.689222 8, 0xFFFF, sum = 0
6516 22:15:21.689323 9, 0xFFFF, sum = 0
6517 22:15:21.692285 10, 0xFFFF, sum = 0
6518 22:15:21.692356 11, 0xFFFF, sum = 0
6519 22:15:21.695742 12, 0xFFFF, sum = 0
6520 22:15:21.695812 13, 0x0, sum = 1
6521 22:15:21.698704 14, 0x0, sum = 2
6522 22:15:21.698770 15, 0x0, sum = 3
6523 22:15:21.702078 16, 0x0, sum = 4
6524 22:15:21.702189 best_step = 14
6525 22:15:21.702252
6526 22:15:21.702340 ==
6527 22:15:21.705432 Dram Type= 6, Freq= 0, CH_0, rank 1
6528 22:15:21.709041 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6529 22:15:21.712048 ==
6530 22:15:21.712148 RX Vref Scan: 0
6531 22:15:21.712269
6532 22:15:21.715294 RX Vref 0 -> 0, step: 1
6533 22:15:21.715399
6534 22:15:21.718797 RX Delay -311 -> 252, step: 8
6535 22:15:21.722462 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6536 22:15:21.728639 iDelay=217, Bit 1, Center -12 (-231 ~ 208) 440
6537 22:15:21.732189 iDelay=217, Bit 2, Center -16 (-239 ~ 208) 448
6538 22:15:21.735276 iDelay=217, Bit 3, Center -16 (-239 ~ 208) 448
6539 22:15:21.739029 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6540 22:15:21.745713 iDelay=217, Bit 5, Center -24 (-247 ~ 200) 448
6541 22:15:21.748855 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
6542 22:15:21.752510 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6543 22:15:21.755567 iDelay=217, Bit 8, Center -28 (-247 ~ 192) 440
6544 22:15:21.762227 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6545 22:15:21.765542 iDelay=217, Bit 10, Center -20 (-239 ~ 200) 440
6546 22:15:21.768745 iDelay=217, Bit 11, Center -28 (-247 ~ 192) 440
6547 22:15:21.772216 iDelay=217, Bit 12, Center -20 (-239 ~ 200) 440
6548 22:15:21.778999 iDelay=217, Bit 13, Center -20 (-239 ~ 200) 440
6549 22:15:21.782046 iDelay=217, Bit 14, Center -12 (-231 ~ 208) 440
6550 22:15:21.785531 iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448
6551 22:15:21.785636 ==
6552 22:15:21.788651 Dram Type= 6, Freq= 0, CH_0, rank 1
6553 22:15:21.795276 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6554 22:15:21.795414 ==
6555 22:15:21.795517 DQS Delay:
6556 22:15:21.798844 DQS0 = 24, DQS1 = 32
6557 22:15:21.798948 DQM Delay:
6558 22:15:21.799042 DQM0 = 9, DQM1 = 10
6559 22:15:21.801939 DQ Delay:
6560 22:15:21.805645 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =8
6561 22:15:21.805748 DQ4 =8, DQ5 =0, DQ6 =12, DQ7 =16
6562 22:15:21.808475 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =4
6563 22:15:21.811833 DQ12 =12, DQ13 =12, DQ14 =20, DQ15 =16
6564 22:15:21.811912
6565 22:15:21.812000
6566 22:15:21.821732 [DQSOSCAuto] RK1, (LSB)MR18= 0xb858, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 386 ps
6567 22:15:21.825126 CH0 RK1: MR19=C0C, MR18=B858
6568 22:15:21.831765 CH0_RK1: MR19=0xC0C, MR18=0xB858, DQSOSC=386, MR23=63, INC=396, DEC=264
6569 22:15:21.831844 [RxdqsGatingPostProcess] freq 400
6570 22:15:21.838654 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6571 22:15:21.841587 best DQS0 dly(2T, 0.5T) = (0, 10)
6572 22:15:21.845509 best DQS1 dly(2T, 0.5T) = (0, 10)
6573 22:15:21.848274 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6574 22:15:21.851965 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6575 22:15:21.855137 best DQS0 dly(2T, 0.5T) = (0, 10)
6576 22:15:21.858526 best DQS1 dly(2T, 0.5T) = (0, 10)
6577 22:15:21.861600 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6578 22:15:21.865197 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6579 22:15:21.868276 Pre-setting of DQS Precalculation
6580 22:15:21.871773 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6581 22:15:21.871862 ==
6582 22:15:21.874934 Dram Type= 6, Freq= 0, CH_1, rank 0
6583 22:15:21.878410 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6584 22:15:21.881983 ==
6585 22:15:21.884951 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6586 22:15:21.891541 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6587 22:15:21.895008 [CA 0] Center 36 (8~64) winsize 57
6588 22:15:21.898177 [CA 1] Center 36 (8~64) winsize 57
6589 22:15:21.901589 [CA 2] Center 36 (8~64) winsize 57
6590 22:15:21.905044 [CA 3] Center 36 (8~64) winsize 57
6591 22:15:21.908199 [CA 4] Center 36 (8~64) winsize 57
6592 22:15:21.911644 [CA 5] Center 36 (8~64) winsize 57
6593 22:15:21.911729
6594 22:15:21.915195 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6595 22:15:21.915308
6596 22:15:21.918061 [CATrainingPosCal] consider 1 rank data
6597 22:15:21.921670 u2DelayCellTimex100 = 270/100 ps
6598 22:15:21.925010 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6599 22:15:21.928642 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6600 22:15:21.931539 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6601 22:15:21.935148 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6602 22:15:21.938669 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6603 22:15:21.941946 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6604 22:15:21.942057
6605 22:15:21.944812 CA PerBit enable=1, Macro0, CA PI delay=36
6606 22:15:21.944896
6607 22:15:21.948245 [CBTSetCACLKResult] CA Dly = 36
6608 22:15:21.951254 CS Dly: 1 (0~32)
6609 22:15:21.951373 ==
6610 22:15:21.955211 Dram Type= 6, Freq= 0, CH_1, rank 1
6611 22:15:21.958128 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6612 22:15:21.958211 ==
6613 22:15:21.964393 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6614 22:15:21.971593 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6615 22:15:21.974585 [CA 0] Center 36 (8~64) winsize 57
6616 22:15:21.978153 [CA 1] Center 36 (8~64) winsize 57
6617 22:15:21.978243 [CA 2] Center 36 (8~64) winsize 57
6618 22:15:21.981074 [CA 3] Center 36 (8~64) winsize 57
6619 22:15:21.984577 [CA 4] Center 36 (8~64) winsize 57
6620 22:15:21.987923 [CA 5] Center 36 (8~64) winsize 57
6621 22:15:21.988000
6622 22:15:21.991744 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6623 22:15:21.991818
6624 22:15:21.994842 [CATrainingPosCal] consider 2 rank data
6625 22:15:21.998230 u2DelayCellTimex100 = 270/100 ps
6626 22:15:22.001168 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6627 22:15:22.007871 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6628 22:15:22.011560 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6629 22:15:22.014920 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6630 22:15:22.018074 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6631 22:15:22.021395 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6632 22:15:22.021492
6633 22:15:22.025379 CA PerBit enable=1, Macro0, CA PI delay=36
6634 22:15:22.025474
6635 22:15:22.028070 [CBTSetCACLKResult] CA Dly = 36
6636 22:15:22.028172 CS Dly: 1 (0~32)
6637 22:15:22.028260
6638 22:15:22.031581 ----->DramcWriteLeveling(PI) begin...
6639 22:15:22.034850 ==
6640 22:15:22.037921 Dram Type= 6, Freq= 0, CH_1, rank 0
6641 22:15:22.041471 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6642 22:15:22.041545 ==
6643 22:15:22.045111 Write leveling (Byte 0): 40 => 8
6644 22:15:22.048030 Write leveling (Byte 1): 40 => 8
6645 22:15:22.051230 DramcWriteLeveling(PI) end<-----
6646 22:15:22.051315
6647 22:15:22.051403 ==
6648 22:15:22.054751 Dram Type= 6, Freq= 0, CH_1, rank 0
6649 22:15:22.058113 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6650 22:15:22.058197 ==
6651 22:15:22.061472 [Gating] SW mode calibration
6652 22:15:22.067766 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6653 22:15:22.074843 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6654 22:15:22.077563 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6655 22:15:22.081067 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6656 22:15:22.087958 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6657 22:15:22.091063 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6658 22:15:22.094748 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6659 22:15:22.097479 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6660 22:15:22.104550 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6661 22:15:22.107542 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6662 22:15:22.110907 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6663 22:15:22.114591 Total UI for P1: 0, mck2ui 16
6664 22:15:22.117510 best dqsien dly found for B0: ( 0, 14, 24)
6665 22:15:22.120872 Total UI for P1: 0, mck2ui 16
6666 22:15:22.124416 best dqsien dly found for B1: ( 0, 14, 24)
6667 22:15:22.128088 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6668 22:15:22.131312 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6669 22:15:22.134808
6670 22:15:22.137510 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6671 22:15:22.141196 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6672 22:15:22.144141 [Gating] SW calibration Done
6673 22:15:22.144214 ==
6674 22:15:22.147719 Dram Type= 6, Freq= 0, CH_1, rank 0
6675 22:15:22.151274 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6676 22:15:22.151415 ==
6677 22:15:22.151480 RX Vref Scan: 0
6678 22:15:22.154280
6679 22:15:22.154383 RX Vref 0 -> 0, step: 1
6680 22:15:22.154471
6681 22:15:22.157430 RX Delay -410 -> 252, step: 16
6682 22:15:22.160841 iDelay=230, Bit 0, Center -11 (-250 ~ 229) 480
6683 22:15:22.167472 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6684 22:15:22.171050 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6685 22:15:22.174155 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6686 22:15:22.177753 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6687 22:15:22.184517 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6688 22:15:22.187888 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6689 22:15:22.191135 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6690 22:15:22.193968 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6691 22:15:22.201338 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6692 22:15:22.204578 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6693 22:15:22.207603 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6694 22:15:22.210669 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6695 22:15:22.217542 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6696 22:15:22.221368 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6697 22:15:22.224496 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6698 22:15:22.224572 ==
6699 22:15:22.227421 Dram Type= 6, Freq= 0, CH_1, rank 0
6700 22:15:22.230915 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6701 22:15:22.234500 ==
6702 22:15:22.234607 DQS Delay:
6703 22:15:22.234673 DQS0 = 27, DQS1 = 35
6704 22:15:22.237620 DQM Delay:
6705 22:15:22.237698 DQM0 = 10, DQM1 = 13
6706 22:15:22.240681 DQ Delay:
6707 22:15:22.240765 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =8
6708 22:15:22.244129 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6709 22:15:22.247513 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6710 22:15:22.250943 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6711 22:15:22.251026
6712 22:15:22.251091
6713 22:15:22.251151 ==
6714 22:15:22.254373 Dram Type= 6, Freq= 0, CH_1, rank 0
6715 22:15:22.261347 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6716 22:15:22.261447 ==
6717 22:15:22.261541
6718 22:15:22.261602
6719 22:15:22.261674 TX Vref Scan disable
6720 22:15:22.264139 == TX Byte 0 ==
6721 22:15:22.267783 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6722 22:15:22.271437 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6723 22:15:22.274538 == TX Byte 1 ==
6724 22:15:22.277676 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6725 22:15:22.281059 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6726 22:15:22.281134 ==
6727 22:15:22.284066 Dram Type= 6, Freq= 0, CH_1, rank 0
6728 22:15:22.290638 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6729 22:15:22.290721 ==
6730 22:15:22.290786
6731 22:15:22.290846
6732 22:15:22.290903 TX Vref Scan disable
6733 22:15:22.294143 == TX Byte 0 ==
6734 22:15:22.297569 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6735 22:15:22.301072 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6736 22:15:22.304066 == TX Byte 1 ==
6737 22:15:22.307330 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6738 22:15:22.311195 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6739 22:15:22.311299
6740 22:15:22.314163 [DATLAT]
6741 22:15:22.314270 Freq=400, CH1 RK0
6742 22:15:22.314364
6743 22:15:22.317576 DATLAT Default: 0xf
6744 22:15:22.317675 0, 0xFFFF, sum = 0
6745 22:15:22.320539 1, 0xFFFF, sum = 0
6746 22:15:22.320637 2, 0xFFFF, sum = 0
6747 22:15:22.324577 3, 0xFFFF, sum = 0
6748 22:15:22.324675 4, 0xFFFF, sum = 0
6749 22:15:22.327693 5, 0xFFFF, sum = 0
6750 22:15:22.327765 6, 0xFFFF, sum = 0
6751 22:15:22.330740 7, 0xFFFF, sum = 0
6752 22:15:22.330826 8, 0xFFFF, sum = 0
6753 22:15:22.334352 9, 0xFFFF, sum = 0
6754 22:15:22.337413 10, 0xFFFF, sum = 0
6755 22:15:22.337528 11, 0xFFFF, sum = 0
6756 22:15:22.340441 12, 0xFFFF, sum = 0
6757 22:15:22.340527 13, 0x0, sum = 1
6758 22:15:22.344307 14, 0x0, sum = 2
6759 22:15:22.344380 15, 0x0, sum = 3
6760 22:15:22.344441 16, 0x0, sum = 4
6761 22:15:22.347584 best_step = 14
6762 22:15:22.347683
6763 22:15:22.347782 ==
6764 22:15:22.350521 Dram Type= 6, Freq= 0, CH_1, rank 0
6765 22:15:22.353976 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6766 22:15:22.354083 ==
6767 22:15:22.357600 RX Vref Scan: 1
6768 22:15:22.357711
6769 22:15:22.360626 RX Vref 0 -> 0, step: 1
6770 22:15:22.360722
6771 22:15:22.360810 RX Delay -311 -> 252, step: 8
6772 22:15:22.360902
6773 22:15:22.363984 Set Vref, RX VrefLevel [Byte0]: 54
6774 22:15:22.367299 [Byte1]: 51
6775 22:15:22.372233
6776 22:15:22.372310 Final RX Vref Byte 0 = 54 to rank0
6777 22:15:22.375809 Final RX Vref Byte 1 = 51 to rank0
6778 22:15:22.378878 Final RX Vref Byte 0 = 54 to rank1
6779 22:15:22.382393 Final RX Vref Byte 1 = 51 to rank1==
6780 22:15:22.385539 Dram Type= 6, Freq= 0, CH_1, rank 0
6781 22:15:22.392716 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6782 22:15:22.392800 ==
6783 22:15:22.392865 DQS Delay:
6784 22:15:22.392926 DQS0 = 32, DQS1 = 32
6785 22:15:22.395882 DQM Delay:
6786 22:15:22.395980 DQM0 = 13, DQM1 = 11
6787 22:15:22.399296 DQ Delay:
6788 22:15:22.402678 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6789 22:15:22.402787 DQ4 =16, DQ5 =24, DQ6 =20, DQ7 =12
6790 22:15:22.405457 DQ8 =0, DQ9 =4, DQ10 =8, DQ11 =4
6791 22:15:22.408766 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =24
6792 22:15:22.408849
6793 22:15:22.412172
6794 22:15:22.419212 [DQSOSCAuto] RK0, (LSB)MR18= 0x95cd, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 391 ps
6795 22:15:22.422342 CH1 RK0: MR19=C0C, MR18=95CD
6796 22:15:22.429092 CH1_RK0: MR19=0xC0C, MR18=0x95CD, DQSOSC=384, MR23=63, INC=400, DEC=267
6797 22:15:22.429178 ==
6798 22:15:22.432153 Dram Type= 6, Freq= 0, CH_1, rank 1
6799 22:15:22.435790 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6800 22:15:22.435880 ==
6801 22:15:22.439177 [Gating] SW mode calibration
6802 22:15:22.446085 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6803 22:15:22.449224 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6804 22:15:22.455596 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6805 22:15:22.458614 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6806 22:15:22.462362 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6807 22:15:22.469154 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6808 22:15:22.472054 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6809 22:15:22.475577 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6810 22:15:22.482266 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6811 22:15:22.485497 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6812 22:15:22.488976 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6813 22:15:22.491827 Total UI for P1: 0, mck2ui 16
6814 22:15:22.495403 best dqsien dly found for B0: ( 0, 14, 24)
6815 22:15:22.499212 Total UI for P1: 0, mck2ui 16
6816 22:15:22.502307 best dqsien dly found for B1: ( 0, 14, 24)
6817 22:15:22.505827 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6818 22:15:22.508882 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6819 22:15:22.508971
6820 22:15:22.515525 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6821 22:15:22.518634 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6822 22:15:22.522373 [Gating] SW calibration Done
6823 22:15:22.522459 ==
6824 22:15:22.525620 Dram Type= 6, Freq= 0, CH_1, rank 1
6825 22:15:22.528850 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6826 22:15:22.528933 ==
6827 22:15:22.528999 RX Vref Scan: 0
6828 22:15:22.529058
6829 22:15:22.532284 RX Vref 0 -> 0, step: 1
6830 22:15:22.532367
6831 22:15:22.535753 RX Delay -410 -> 252, step: 16
6832 22:15:22.538910 iDelay=230, Bit 0, Center -11 (-234 ~ 213) 448
6833 22:15:22.545666 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6834 22:15:22.548566 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6835 22:15:22.552284 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6836 22:15:22.555315 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6837 22:15:22.558652 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6838 22:15:22.565412 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6839 22:15:22.568575 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6840 22:15:22.572313 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6841 22:15:22.575625 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6842 22:15:22.582155 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6843 22:15:22.585272 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6844 22:15:22.588850 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6845 22:15:22.595246 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6846 22:15:22.598358 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6847 22:15:22.601864 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6848 22:15:22.601947 ==
6849 22:15:22.605549 Dram Type= 6, Freq= 0, CH_1, rank 1
6850 22:15:22.608667 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6851 22:15:22.608750 ==
6852 22:15:22.611996 DQS Delay:
6853 22:15:22.612078 DQS0 = 35, DQS1 = 35
6854 22:15:22.615163 DQM Delay:
6855 22:15:22.615245 DQM0 = 19, DQM1 = 13
6856 22:15:22.618574 DQ Delay:
6857 22:15:22.618656 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6858 22:15:22.622171 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6859 22:15:22.625001 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6860 22:15:22.628835 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6861 22:15:22.628918
6862 22:15:22.628981
6863 22:15:22.631780 ==
6864 22:15:22.631863 Dram Type= 6, Freq= 0, CH_1, rank 1
6865 22:15:22.638381 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6866 22:15:22.638465 ==
6867 22:15:22.638530
6868 22:15:22.638589
6869 22:15:22.641799 TX Vref Scan disable
6870 22:15:22.641882 == TX Byte 0 ==
6871 22:15:22.645368 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6872 22:15:22.648883 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6873 22:15:22.651719 == TX Byte 1 ==
6874 22:15:22.655297 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6875 22:15:22.658189 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6876 22:15:22.661974 ==
6877 22:15:22.665270 Dram Type= 6, Freq= 0, CH_1, rank 1
6878 22:15:22.668500 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6879 22:15:22.668584 ==
6880 22:15:22.668649
6881 22:15:22.668708
6882 22:15:22.671916 TX Vref Scan disable
6883 22:15:22.671998 == TX Byte 0 ==
6884 22:15:22.674893 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6885 22:15:22.681330 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6886 22:15:22.681445 == TX Byte 1 ==
6887 22:15:22.685105 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6888 22:15:22.688062 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6889 22:15:22.691848
6890 22:15:22.691921 [DATLAT]
6891 22:15:22.691999 Freq=400, CH1 RK1
6892 22:15:22.692060
6893 22:15:22.694714 DATLAT Default: 0xe
6894 22:15:22.694794 0, 0xFFFF, sum = 0
6895 22:15:22.698470 1, 0xFFFF, sum = 0
6896 22:15:22.698566 2, 0xFFFF, sum = 0
6897 22:15:22.701739 3, 0xFFFF, sum = 0
6898 22:15:22.701838 4, 0xFFFF, sum = 0
6899 22:15:22.705027 5, 0xFFFF, sum = 0
6900 22:15:22.705130 6, 0xFFFF, sum = 0
6901 22:15:22.708076 7, 0xFFFF, sum = 0
6902 22:15:22.711889 8, 0xFFFF, sum = 0
6903 22:15:22.711978 9, 0xFFFF, sum = 0
6904 22:15:22.714892 10, 0xFFFF, sum = 0
6905 22:15:22.714977 11, 0xFFFF, sum = 0
6906 22:15:22.718311 12, 0xFFFF, sum = 0
6907 22:15:22.718394 13, 0x0, sum = 1
6908 22:15:22.722054 14, 0x0, sum = 2
6909 22:15:22.722137 15, 0x0, sum = 3
6910 22:15:22.724899 16, 0x0, sum = 4
6911 22:15:22.724981 best_step = 14
6912 22:15:22.725046
6913 22:15:22.725105 ==
6914 22:15:22.728298 Dram Type= 6, Freq= 0, CH_1, rank 1
6915 22:15:22.731382 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6916 22:15:22.731464 ==
6917 22:15:22.735189 RX Vref Scan: 0
6918 22:15:22.735271
6919 22:15:22.737902 RX Vref 0 -> 0, step: 1
6920 22:15:22.738019
6921 22:15:22.738086 RX Delay -311 -> 252, step: 8
6922 22:15:22.746820 iDelay=217, Bit 0, Center -12 (-231 ~ 208) 440
6923 22:15:22.750081 iDelay=217, Bit 1, Center -24 (-247 ~ 200) 448
6924 22:15:22.753644 iDelay=217, Bit 2, Center -28 (-247 ~ 192) 440
6925 22:15:22.756482 iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448
6926 22:15:22.763269 iDelay=217, Bit 4, Center -20 (-239 ~ 200) 440
6927 22:15:22.766695 iDelay=217, Bit 5, Center -8 (-231 ~ 216) 448
6928 22:15:22.769827 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6929 22:15:22.773474 iDelay=217, Bit 7, Center -20 (-247 ~ 208) 456
6930 22:15:22.780042 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6931 22:15:22.783497 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6932 22:15:22.786446 iDelay=217, Bit 10, Center -20 (-247 ~ 208) 456
6933 22:15:22.790109 iDelay=217, Bit 11, Center -24 (-247 ~ 200) 448
6934 22:15:22.796639 iDelay=217, Bit 12, Center -12 (-239 ~ 216) 456
6935 22:15:22.799988 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
6936 22:15:22.803167 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
6937 22:15:22.809689 iDelay=217, Bit 15, Center -12 (-239 ~ 216) 456
6938 22:15:22.809771 ==
6939 22:15:22.813353 Dram Type= 6, Freq= 0, CH_1, rank 1
6940 22:15:22.816815 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6941 22:15:22.816897 ==
6942 22:15:22.816963 DQS Delay:
6943 22:15:22.819769 DQS0 = 28, DQS1 = 36
6944 22:15:22.819854 DQM Delay:
6945 22:15:22.822952 DQM0 = 10, DQM1 = 15
6946 22:15:22.823034 DQ Delay:
6947 22:15:22.826388 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =4
6948 22:15:22.830195 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =8
6949 22:15:22.833075 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =12
6950 22:15:22.836337 DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =24
6951 22:15:22.836419
6952 22:15:22.836484
6953 22:15:22.843366 [DQSOSCAuto] RK1, (LSB)MR18= 0xca5b, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 384 ps
6954 22:15:22.846932 CH1 RK1: MR19=C0C, MR18=CA5B
6955 22:15:22.853019 CH1_RK1: MR19=0xC0C, MR18=0xCA5B, DQSOSC=384, MR23=63, INC=400, DEC=267
6956 22:15:22.856428 [RxdqsGatingPostProcess] freq 400
6957 22:15:22.859848 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6958 22:15:22.863620 best DQS0 dly(2T, 0.5T) = (0, 10)
6959 22:15:22.866800 best DQS1 dly(2T, 0.5T) = (0, 10)
6960 22:15:22.870230 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6961 22:15:22.873374 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6962 22:15:22.876690 best DQS0 dly(2T, 0.5T) = (0, 10)
6963 22:15:22.880180 best DQS1 dly(2T, 0.5T) = (0, 10)
6964 22:15:22.883101 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6965 22:15:22.886642 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6966 22:15:22.889987 Pre-setting of DQS Precalculation
6967 22:15:22.893216 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6968 22:15:22.903308 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6969 22:15:22.910144 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6970 22:15:22.910238
6971 22:15:22.910303
6972 22:15:22.913544 [Calibration Summary] 800 Mbps
6973 22:15:22.913626 CH 0, Rank 0
6974 22:15:22.916624 SW Impedance : PASS
6975 22:15:22.916706 DUTY Scan : NO K
6976 22:15:22.919997 ZQ Calibration : PASS
6977 22:15:22.923118 Jitter Meter : NO K
6978 22:15:22.923200 CBT Training : PASS
6979 22:15:22.926673 Write leveling : PASS
6980 22:15:22.929808 RX DQS gating : PASS
6981 22:15:22.929893 RX DQ/DQS(RDDQC) : PASS
6982 22:15:22.933033 TX DQ/DQS : PASS
6983 22:15:22.936250 RX DATLAT : PASS
6984 22:15:22.936348 RX DQ/DQS(Engine): PASS
6985 22:15:22.939868 TX OE : NO K
6986 22:15:22.939956 All Pass.
6987 22:15:22.940018
6988 22:15:22.943107 CH 0, Rank 1
6989 22:15:22.943189 SW Impedance : PASS
6990 22:15:22.946544 DUTY Scan : NO K
6991 22:15:22.946625 ZQ Calibration : PASS
6992 22:15:22.949794 Jitter Meter : NO K
6993 22:15:22.953273 CBT Training : PASS
6994 22:15:22.953355 Write leveling : NO K
6995 22:15:22.956474 RX DQS gating : PASS
6996 22:15:22.959966 RX DQ/DQS(RDDQC) : PASS
6997 22:15:22.960048 TX DQ/DQS : PASS
6998 22:15:22.963101 RX DATLAT : PASS
6999 22:15:22.966488 RX DQ/DQS(Engine): PASS
7000 22:15:22.966570 TX OE : NO K
7001 22:15:22.969991 All Pass.
7002 22:15:22.970072
7003 22:15:22.970136 CH 1, Rank 0
7004 22:15:22.973647 SW Impedance : PASS
7005 22:15:22.973729 DUTY Scan : NO K
7006 22:15:22.976043 ZQ Calibration : PASS
7007 22:15:22.979703 Jitter Meter : NO K
7008 22:15:22.979785 CBT Training : PASS
7009 22:15:22.982859 Write leveling : PASS
7010 22:15:22.986403 RX DQS gating : PASS
7011 22:15:22.986485 RX DQ/DQS(RDDQC) : PASS
7012 22:15:22.989532 TX DQ/DQS : PASS
7013 22:15:22.989614 RX DATLAT : PASS
7014 22:15:22.992825 RX DQ/DQS(Engine): PASS
7015 22:15:22.996393 TX OE : NO K
7016 22:15:22.996476 All Pass.
7017 22:15:22.996539
7018 22:15:22.996597 CH 1, Rank 1
7019 22:15:23.000098 SW Impedance : PASS
7020 22:15:23.003271 DUTY Scan : NO K
7021 22:15:23.003390 ZQ Calibration : PASS
7022 22:15:23.006155 Jitter Meter : NO K
7023 22:15:23.009755 CBT Training : PASS
7024 22:15:23.009837 Write leveling : NO K
7025 22:15:23.013199 RX DQS gating : PASS
7026 22:15:23.016674 RX DQ/DQS(RDDQC) : PASS
7027 22:15:23.016755 TX DQ/DQS : PASS
7028 22:15:23.019339 RX DATLAT : PASS
7029 22:15:23.022707 RX DQ/DQS(Engine): PASS
7030 22:15:23.022788 TX OE : NO K
7031 22:15:23.026251 All Pass.
7032 22:15:23.026333
7033 22:15:23.026397 DramC Write-DBI off
7034 22:15:23.029312 PER_BANK_REFRESH: Hybrid Mode
7035 22:15:23.029394 TX_TRACKING: ON
7036 22:15:23.039478 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7037 22:15:23.042840 [FAST_K] Save calibration result to emmc
7038 22:15:23.046299 dramc_set_vcore_voltage set vcore to 725000
7039 22:15:23.049500 Read voltage for 1600, 0
7040 22:15:23.049582 Vio18 = 0
7041 22:15:23.053005 Vcore = 725000
7042 22:15:23.053086 Vdram = 0
7043 22:15:23.053150 Vddq = 0
7044 22:15:23.053208 Vmddr = 0
7045 22:15:23.059475 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7046 22:15:23.066090 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7047 22:15:23.066172 MEM_TYPE=3, freq_sel=13
7048 22:15:23.069257 sv_algorithm_assistance_LP4_3733
7049 22:15:23.072499 ============ PULL DRAM RESETB DOWN ============
7050 22:15:23.079211 ========== PULL DRAM RESETB DOWN end =========
7051 22:15:23.082556 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7052 22:15:23.086221 ===================================
7053 22:15:23.088997 LPDDR4 DRAM CONFIGURATION
7054 22:15:23.092520 ===================================
7055 22:15:23.092602 EX_ROW_EN[0] = 0x0
7056 22:15:23.095754 EX_ROW_EN[1] = 0x0
7057 22:15:23.099361 LP4Y_EN = 0x0
7058 22:15:23.099442 WORK_FSP = 0x1
7059 22:15:23.102647 WL = 0x5
7060 22:15:23.102728 RL = 0x5
7061 22:15:23.105848 BL = 0x2
7062 22:15:23.105930 RPST = 0x0
7063 22:15:23.108862 RD_PRE = 0x0
7064 22:15:23.108944 WR_PRE = 0x1
7065 22:15:23.112373 WR_PST = 0x1
7066 22:15:23.112455 DBI_WR = 0x0
7067 22:15:23.116146 DBI_RD = 0x0
7068 22:15:23.116227 OTF = 0x1
7069 22:15:23.119217 ===================================
7070 22:15:23.121995 ===================================
7071 22:15:23.125063 ANA top config
7072 22:15:23.128402 ===================================
7073 22:15:23.128484 DLL_ASYNC_EN = 0
7074 22:15:23.132198 ALL_SLAVE_EN = 0
7075 22:15:23.135717 NEW_RANK_MODE = 1
7076 22:15:23.138655 DLL_IDLE_MODE = 1
7077 22:15:23.142010 LP45_APHY_COMB_EN = 1
7078 22:15:23.142093 TX_ODT_DIS = 0
7079 22:15:23.145328 NEW_8X_MODE = 1
7080 22:15:23.148723 ===================================
7081 22:15:23.151868 ===================================
7082 22:15:23.155195 data_rate = 3200
7083 22:15:23.158869 CKR = 1
7084 22:15:23.161792 DQ_P2S_RATIO = 8
7085 22:15:23.165187 ===================================
7086 22:15:23.165269 CA_P2S_RATIO = 8
7087 22:15:23.168850 DQ_CA_OPEN = 0
7088 22:15:23.171831 DQ_SEMI_OPEN = 0
7089 22:15:23.175186 CA_SEMI_OPEN = 0
7090 22:15:23.178423 CA_FULL_RATE = 0
7091 22:15:23.182008 DQ_CKDIV4_EN = 0
7092 22:15:23.182090 CA_CKDIV4_EN = 0
7093 22:15:23.185808 CA_PREDIV_EN = 0
7094 22:15:23.188689 PH8_DLY = 12
7095 22:15:23.191699 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7096 22:15:23.195614 DQ_AAMCK_DIV = 4
7097 22:15:23.198479 CA_AAMCK_DIV = 4
7098 22:15:23.198560 CA_ADMCK_DIV = 4
7099 22:15:23.202039 DQ_TRACK_CA_EN = 0
7100 22:15:23.204900 CA_PICK = 1600
7101 22:15:23.208520 CA_MCKIO = 1600
7102 22:15:23.212170 MCKIO_SEMI = 0
7103 22:15:23.215308 PLL_FREQ = 3068
7104 22:15:23.218961 DQ_UI_PI_RATIO = 32
7105 22:15:23.221797 CA_UI_PI_RATIO = 0
7106 22:15:23.225444 ===================================
7107 22:15:23.225526 ===================================
7108 22:15:23.228246 memory_type:LPDDR4
7109 22:15:23.231584 GP_NUM : 10
7110 22:15:23.231665 SRAM_EN : 1
7111 22:15:23.234953 MD32_EN : 0
7112 22:15:23.238276 ===================================
7113 22:15:23.241461 [ANA_INIT] >>>>>>>>>>>>>>
7114 22:15:23.244851 <<<<<< [CONFIGURE PHASE]: ANA_TX
7115 22:15:23.248397 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7116 22:15:23.251585 ===================================
7117 22:15:23.251659 data_rate = 3200,PCW = 0X7600
7118 22:15:23.254834 ===================================
7119 22:15:23.261586 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7120 22:15:23.265051 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7121 22:15:23.271919 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7122 22:15:23.274870 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7123 22:15:23.278266 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7124 22:15:23.281457 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7125 22:15:23.284821 [ANA_INIT] flow start
7126 22:15:23.288577 [ANA_INIT] PLL >>>>>>>>
7127 22:15:23.288651 [ANA_INIT] PLL <<<<<<<<
7128 22:15:23.291321 [ANA_INIT] MIDPI >>>>>>>>
7129 22:15:23.295141 [ANA_INIT] MIDPI <<<<<<<<
7130 22:15:23.295237 [ANA_INIT] DLL >>>>>>>>
7131 22:15:23.298546 [ANA_INIT] DLL <<<<<<<<
7132 22:15:23.301779 [ANA_INIT] flow end
7133 22:15:23.305248 ============ LP4 DIFF to SE enter ============
7134 22:15:23.308304 ============ LP4 DIFF to SE exit ============
7135 22:15:23.311315 [ANA_INIT] <<<<<<<<<<<<<
7136 22:15:23.314726 [Flow] Enable top DCM control >>>>>
7137 22:15:23.318320 [Flow] Enable top DCM control <<<<<
7138 22:15:23.321618 Enable DLL master slave shuffle
7139 22:15:23.324998 ==============================================================
7140 22:15:23.328653 Gating Mode config
7141 22:15:23.335046 ==============================================================
7142 22:15:23.335148 Config description:
7143 22:15:23.344812 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7144 22:15:23.351277 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7145 22:15:23.355060 SELPH_MODE 0: By rank 1: By Phase
7146 22:15:23.361415 ==============================================================
7147 22:15:23.364804 GAT_TRACK_EN = 1
7148 22:15:23.368383 RX_GATING_MODE = 2
7149 22:15:23.371314 RX_GATING_TRACK_MODE = 2
7150 22:15:23.374911 SELPH_MODE = 1
7151 22:15:23.377900 PICG_EARLY_EN = 1
7152 22:15:23.381297 VALID_LAT_VALUE = 1
7153 22:15:23.384730 ==============================================================
7154 22:15:23.387991 Enter into Gating configuration >>>>
7155 22:15:23.391161 Exit from Gating configuration <<<<
7156 22:15:23.394792 Enter into DVFS_PRE_config >>>>>
7157 22:15:23.404846 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7158 22:15:23.407659 Exit from DVFS_PRE_config <<<<<
7159 22:15:23.411545 Enter into PICG configuration >>>>
7160 22:15:23.414827 Exit from PICG configuration <<<<
7161 22:15:23.417685 [RX_INPUT] configuration >>>>>
7162 22:15:23.421361 [RX_INPUT] configuration <<<<<
7163 22:15:23.428020 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7164 22:15:23.431574 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7165 22:15:23.438104 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7166 22:15:23.444513 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7167 22:15:23.451591 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7168 22:15:23.457766 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7169 22:15:23.461171 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7170 22:15:23.464684 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7171 22:15:23.468051 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7172 22:15:23.471292 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7173 22:15:23.478057 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7174 22:15:23.481336 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7175 22:15:23.485091 ===================================
7176 22:15:23.488136 LPDDR4 DRAM CONFIGURATION
7177 22:15:23.491010 ===================================
7178 22:15:23.491085 EX_ROW_EN[0] = 0x0
7179 22:15:23.494331 EX_ROW_EN[1] = 0x0
7180 22:15:23.494404 LP4Y_EN = 0x0
7181 22:15:23.497780 WORK_FSP = 0x1
7182 22:15:23.497855 WL = 0x5
7183 22:15:23.501107 RL = 0x5
7184 22:15:23.501189 BL = 0x2
7185 22:15:23.504643 RPST = 0x0
7186 22:15:23.507564 RD_PRE = 0x0
7187 22:15:23.507652 WR_PRE = 0x1
7188 22:15:23.510806 WR_PST = 0x1
7189 22:15:23.510880 DBI_WR = 0x0
7190 22:15:23.514371 DBI_RD = 0x0
7191 22:15:23.514443 OTF = 0x1
7192 22:15:23.517882 ===================================
7193 22:15:23.521012 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7194 22:15:23.527507 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7195 22:15:23.531145 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7196 22:15:23.534268 ===================================
7197 22:15:23.537712 LPDDR4 DRAM CONFIGURATION
7198 22:15:23.541267 ===================================
7199 22:15:23.541350 EX_ROW_EN[0] = 0x10
7200 22:15:23.544171 EX_ROW_EN[1] = 0x0
7201 22:15:23.544254 LP4Y_EN = 0x0
7202 22:15:23.547314 WORK_FSP = 0x1
7203 22:15:23.547421 WL = 0x5
7204 22:15:23.551275 RL = 0x5
7205 22:15:23.551400 BL = 0x2
7206 22:15:23.554652 RPST = 0x0
7207 22:15:23.554734 RD_PRE = 0x0
7208 22:15:23.557501 WR_PRE = 0x1
7209 22:15:23.557584 WR_PST = 0x1
7210 22:15:23.560842 DBI_WR = 0x0
7211 22:15:23.563958 DBI_RD = 0x0
7212 22:15:23.564040 OTF = 0x1
7213 22:15:23.567239 ===================================
7214 22:15:23.574384 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7215 22:15:23.574467 ==
7216 22:15:23.577644 Dram Type= 6, Freq= 0, CH_0, rank 0
7217 22:15:23.580891 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7218 22:15:23.580974 ==
7219 22:15:23.584169 [Duty_Offset_Calibration]
7220 22:15:23.584250 B0:2 B1:1 CA:1
7221 22:15:23.584315
7222 22:15:23.587476 [DutyScan_Calibration_Flow] k_type=0
7223 22:15:23.598879
7224 22:15:23.598961 ==CLK 0==
7225 22:15:23.602142 Final CLK duty delay cell = 0
7226 22:15:23.605797 [0] MAX Duty = 5156%(X100), DQS PI = 22
7227 22:15:23.608788 [0] MIN Duty = 4907%(X100), DQS PI = 0
7228 22:15:23.608871 [0] AVG Duty = 5031%(X100)
7229 22:15:23.612039
7230 22:15:23.615360 CH0 CLK Duty spec in!! Max-Min= 249%
7231 22:15:23.618709 [DutyScan_Calibration_Flow] ====Done====
7232 22:15:23.618789
7233 22:15:23.621867 [DutyScan_Calibration_Flow] k_type=1
7234 22:15:23.637694
7235 22:15:23.637777 ==DQS 0 ==
7236 22:15:23.641380 Final DQS duty delay cell = -4
7237 22:15:23.644713 [-4] MAX Duty = 5125%(X100), DQS PI = 26
7238 22:15:23.647760 [-4] MIN Duty = 4657%(X100), DQS PI = 0
7239 22:15:23.651273 [-4] AVG Duty = 4891%(X100)
7240 22:15:23.651399
7241 22:15:23.651483 ==DQS 1 ==
7242 22:15:23.654692 Final DQS duty delay cell = 0
7243 22:15:23.657644 [0] MAX Duty = 5187%(X100), DQS PI = 4
7244 22:15:23.661241 [0] MIN Duty = 5031%(X100), DQS PI = 52
7245 22:15:23.664773 [0] AVG Duty = 5109%(X100)
7246 22:15:23.664856
7247 22:15:23.668433 CH0 DQS 0 Duty spec in!! Max-Min= 468%
7248 22:15:23.668517
7249 22:15:23.671261 CH0 DQS 1 Duty spec in!! Max-Min= 156%
7250 22:15:23.674504 [DutyScan_Calibration_Flow] ====Done====
7251 22:15:23.674585
7252 22:15:23.678167 [DutyScan_Calibration_Flow] k_type=3
7253 22:15:23.694326
7254 22:15:23.694407 ==DQM 0 ==
7255 22:15:23.697643 Final DQM duty delay cell = 0
7256 22:15:23.700962 [0] MAX Duty = 5218%(X100), DQS PI = 32
7257 22:15:23.704646 [0] MIN Duty = 4907%(X100), DQS PI = 54
7258 22:15:23.707617 [0] AVG Duty = 5062%(X100)
7259 22:15:23.707698
7260 22:15:23.707761 ==DQM 1 ==
7261 22:15:23.711193 Final DQM duty delay cell = -4
7262 22:15:23.714601 [-4] MAX Duty = 4969%(X100), DQS PI = 20
7263 22:15:23.718082 [-4] MIN Duty = 4844%(X100), DQS PI = 34
7264 22:15:23.720713 [-4] AVG Duty = 4906%(X100)
7265 22:15:23.720801
7266 22:15:23.724100 CH0 DQM 0 Duty spec in!! Max-Min= 311%
7267 22:15:23.724182
7268 22:15:23.727474 CH0 DQM 1 Duty spec in!! Max-Min= 125%
7269 22:15:23.730902 [DutyScan_Calibration_Flow] ====Done====
7270 22:15:23.730983
7271 22:15:23.734307 [DutyScan_Calibration_Flow] k_type=2
7272 22:15:23.751930
7273 22:15:23.752013 ==DQ 0 ==
7274 22:15:23.755318 Final DQ duty delay cell = 0
7275 22:15:23.758881 [0] MAX Duty = 5062%(X100), DQS PI = 26
7276 22:15:23.761888 [0] MIN Duty = 4907%(X100), DQS PI = 0
7277 22:15:23.761969 [0] AVG Duty = 4984%(X100)
7278 22:15:23.765027
7279 22:15:23.765107 ==DQ 1 ==
7280 22:15:23.768789 Final DQ duty delay cell = 0
7281 22:15:23.771759 [0] MAX Duty = 5125%(X100), DQS PI = 6
7282 22:15:23.775360 [0] MIN Duty = 4907%(X100), DQS PI = 34
7283 22:15:23.775442 [0] AVG Duty = 5016%(X100)
7284 22:15:23.775507
7285 22:15:23.778402 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7286 22:15:23.782048
7287 22:15:23.785603 CH0 DQ 1 Duty spec in!! Max-Min= 218%
7288 22:15:23.788478 [DutyScan_Calibration_Flow] ====Done====
7289 22:15:23.788560 ==
7290 22:15:23.791861 Dram Type= 6, Freq= 0, CH_1, rank 0
7291 22:15:23.795464 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7292 22:15:23.795546 ==
7293 22:15:23.798652 [Duty_Offset_Calibration]
7294 22:15:23.798734 B0:1 B1:0 CA:0
7295 22:15:23.798798
7296 22:15:23.801999 [DutyScan_Calibration_Flow] k_type=0
7297 22:15:23.811571
7298 22:15:23.811652 ==CLK 0==
7299 22:15:23.814361 Final CLK duty delay cell = -4
7300 22:15:23.817908 [-4] MAX Duty = 5000%(X100), DQS PI = 22
7301 22:15:23.821451 [-4] MIN Duty = 4844%(X100), DQS PI = 50
7302 22:15:23.824778 [-4] AVG Duty = 4922%(X100)
7303 22:15:23.824857
7304 22:15:23.827636 CH1 CLK Duty spec in!! Max-Min= 156%
7305 22:15:23.830968 [DutyScan_Calibration_Flow] ====Done====
7306 22:15:23.831048
7307 22:15:23.834343 [DutyScan_Calibration_Flow] k_type=1
7308 22:15:23.851476
7309 22:15:23.851582 ==DQS 0 ==
7310 22:15:23.854392 Final DQS duty delay cell = 0
7311 22:15:23.858008 [0] MAX Duty = 5094%(X100), DQS PI = 14
7312 22:15:23.861771 [0] MIN Duty = 4844%(X100), DQS PI = 48
7313 22:15:23.861851 [0] AVG Duty = 4969%(X100)
7314 22:15:23.864870
7315 22:15:23.864949 ==DQS 1 ==
7316 22:15:23.868299 Final DQS duty delay cell = 0
7317 22:15:23.871124 [0] MAX Duty = 5249%(X100), DQS PI = 16
7318 22:15:23.874821 [0] MIN Duty = 4969%(X100), DQS PI = 6
7319 22:15:23.874901 [0] AVG Duty = 5109%(X100)
7320 22:15:23.878459
7321 22:15:23.881458 CH1 DQS 0 Duty spec in!! Max-Min= 250%
7322 22:15:23.881537
7323 22:15:23.885122 CH1 DQS 1 Duty spec in!! Max-Min= 280%
7324 22:15:23.888203 [DutyScan_Calibration_Flow] ====Done====
7325 22:15:23.888282
7326 22:15:23.891042 [DutyScan_Calibration_Flow] k_type=3
7327 22:15:23.908414
7328 22:15:23.908493 ==DQM 0 ==
7329 22:15:23.911820 Final DQM duty delay cell = 0
7330 22:15:23.915212 [0] MAX Duty = 5218%(X100), DQS PI = 18
7331 22:15:23.917882 [0] MIN Duty = 4969%(X100), DQS PI = 48
7332 22:15:23.921885 [0] AVG Duty = 5093%(X100)
7333 22:15:23.921965
7334 22:15:23.922027 ==DQM 1 ==
7335 22:15:23.924692 Final DQM duty delay cell = 0
7336 22:15:23.927921 [0] MAX Duty = 5062%(X100), DQS PI = 14
7337 22:15:23.931450 [0] MIN Duty = 4907%(X100), DQS PI = 52
7338 22:15:23.934759 [0] AVG Duty = 4984%(X100)
7339 22:15:23.934838
7340 22:15:23.937985 CH1 DQM 0 Duty spec in!! Max-Min= 249%
7341 22:15:23.938067
7342 22:15:23.941479 CH1 DQM 1 Duty spec in!! Max-Min= 155%
7343 22:15:23.944961 [DutyScan_Calibration_Flow] ====Done====
7344 22:15:23.945048
7345 22:15:23.948042 [DutyScan_Calibration_Flow] k_type=2
7346 22:15:23.964092
7347 22:15:23.964199 ==DQ 0 ==
7348 22:15:23.967378 Final DQ duty delay cell = -4
7349 22:15:23.970981 [-4] MAX Duty = 5062%(X100), DQS PI = 12
7350 22:15:23.974160 [-4] MIN Duty = 4875%(X100), DQS PI = 46
7351 22:15:23.977735 [-4] AVG Duty = 4968%(X100)
7352 22:15:23.977817
7353 22:15:23.977882 ==DQ 1 ==
7354 22:15:23.980812 Final DQ duty delay cell = 0
7355 22:15:23.984421 [0] MAX Duty = 5124%(X100), DQS PI = 18
7356 22:15:23.988080 [0] MIN Duty = 4938%(X100), DQS PI = 8
7357 22:15:23.990747 [0] AVG Duty = 5031%(X100)
7358 22:15:23.990829
7359 22:15:23.994390 CH1 DQ 0 Duty spec in!! Max-Min= 187%
7360 22:15:23.994472
7361 22:15:23.997366 CH1 DQ 1 Duty spec in!! Max-Min= 186%
7362 22:15:24.001144 [DutyScan_Calibration_Flow] ====Done====
7363 22:15:24.003965 nWR fixed to 30
7364 22:15:24.007708 [ModeRegInit_LP4] CH0 RK0
7365 22:15:24.007790 [ModeRegInit_LP4] CH0 RK1
7366 22:15:24.010825 [ModeRegInit_LP4] CH1 RK0
7367 22:15:24.014196 [ModeRegInit_LP4] CH1 RK1
7368 22:15:24.014277 match AC timing 5
7369 22:15:24.020482 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7370 22:15:24.023959 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7371 22:15:24.027426 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7372 22:15:24.033755 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7373 22:15:24.037438 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7374 22:15:24.037521 [MiockJmeterHQA]
7375 22:15:24.037607
7376 22:15:24.040268 [DramcMiockJmeter] u1RxGatingPI = 0
7377 22:15:24.043725 0 : 4252, 4027
7378 22:15:24.043808 4 : 4255, 4030
7379 22:15:24.047004 8 : 4254, 4029
7380 22:15:24.047087 12 : 4252, 4027
7381 22:15:24.047173 16 : 4252, 4027
7382 22:15:24.050360 20 : 4252, 4027
7383 22:15:24.050442 24 : 4363, 4137
7384 22:15:24.053797 28 : 4363, 4138
7385 22:15:24.053880 32 : 4253, 4026
7386 22:15:24.057154 36 : 4252, 4027
7387 22:15:24.057237 40 : 4253, 4026
7388 22:15:24.060452 44 : 4363, 4140
7389 22:15:24.060535 48 : 4253, 4027
7390 22:15:24.060601 52 : 4361, 4137
7391 22:15:24.063760 56 : 4250, 4027
7392 22:15:24.063842 60 : 4250, 4026
7393 22:15:24.067295 64 : 4250, 4026
7394 22:15:24.067423 68 : 4252, 4030
7395 22:15:24.071137 72 : 4361, 4137
7396 22:15:24.071220 76 : 4250, 4027
7397 22:15:24.071284 80 : 4360, 4137
7398 22:15:24.074202 84 : 4250, 4026
7399 22:15:24.074285 88 : 4250, 165
7400 22:15:24.077590 92 : 4361, 0
7401 22:15:24.077673 96 : 4360, 0
7402 22:15:24.077738 100 : 4253, 0
7403 22:15:24.080675 104 : 4250, 0
7404 22:15:24.080757 108 : 4250, 0
7405 22:15:24.084377 112 : 4250, 0
7406 22:15:24.084460 116 : 4252, 0
7407 22:15:24.084525 120 : 4250, 0
7408 22:15:24.087304 124 : 4250, 0
7409 22:15:24.087426 128 : 4252, 0
7410 22:15:24.090671 132 : 4361, 0
7411 22:15:24.090754 136 : 4250, 0
7412 22:15:24.090819 140 : 4250, 0
7413 22:15:24.094475 144 : 4250, 0
7414 22:15:24.094558 148 : 4361, 0
7415 22:15:24.094623 152 : 4361, 0
7416 22:15:24.097384 156 : 4250, 0
7417 22:15:24.097467 160 : 4250, 0
7418 22:15:24.101078 164 : 4250, 0
7419 22:15:24.101161 168 : 4253, 0
7420 22:15:24.101227 172 : 4250, 0
7421 22:15:24.104260 176 : 4250, 0
7422 22:15:24.104343 180 : 4250, 0
7423 22:15:24.107905 184 : 4361, 0
7424 22:15:24.107988 188 : 4250, 0
7425 22:15:24.108053 192 : 4250, 0
7426 22:15:24.110730 196 : 4250, 0
7427 22:15:24.110813 200 : 4361, 0
7428 22:15:24.114091 204 : 4361, 1322
7429 22:15:24.114174 208 : 4361, 4085
7430 22:15:24.117306 212 : 4250, 4026
7431 22:15:24.117388 216 : 4250, 4027
7432 22:15:24.117454 220 : 4250, 4027
7433 22:15:24.120538 224 : 4250, 4026
7434 22:15:24.120620 228 : 4250, 4026
7435 22:15:24.124322 232 : 4250, 4027
7436 22:15:24.124405 236 : 4252, 4029
7437 22:15:24.127841 240 : 4250, 4026
7438 22:15:24.127924 244 : 4361, 4137
7439 22:15:24.130757 248 : 4361, 4137
7440 22:15:24.130840 252 : 4250, 4027
7441 22:15:24.133869 256 : 4364, 4140
7442 22:15:24.133951 260 : 4361, 4137
7443 22:15:24.137404 264 : 4250, 4027
7444 22:15:24.137486 268 : 4250, 4027
7445 22:15:24.137551 272 : 4250, 4027
7446 22:15:24.140518 276 : 4250, 4027
7447 22:15:24.140601 280 : 4250, 4026
7448 22:15:24.144121 284 : 4250, 4027
7449 22:15:24.144203 288 : 4252, 4030
7450 22:15:24.147506 292 : 4250, 4027
7451 22:15:24.147589 296 : 4363, 4140
7452 22:15:24.151037 300 : 4361, 4137
7453 22:15:24.151119 304 : 4253, 4029
7454 22:15:24.153999 308 : 4363, 4099
7455 22:15:24.154082 312 : 4361, 2304
7456 22:15:24.157310 316 : 4250, 19
7457 22:15:24.157392
7458 22:15:24.157456 MIOCK jitter meter ch=0
7459 22:15:24.157515
7460 22:15:24.160613 1T = (316-88) = 228 dly cells
7461 22:15:24.167625 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 285/100 ps
7462 22:15:24.167708 ==
7463 22:15:24.170587 Dram Type= 6, Freq= 0, CH_0, rank 0
7464 22:15:24.173822 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7465 22:15:24.173905 ==
7466 22:15:24.180793 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7467 22:15:24.183974 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7468 22:15:24.187202 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7469 22:15:24.194064 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7470 22:15:24.203457 [CA 0] Center 43 (12~74) winsize 63
7471 22:15:24.206764 [CA 1] Center 43 (13~74) winsize 62
7472 22:15:24.209812 [CA 2] Center 38 (9~68) winsize 60
7473 22:15:24.213711 [CA 3] Center 38 (8~68) winsize 61
7474 22:15:24.217186 [CA 4] Center 37 (7~67) winsize 61
7475 22:15:24.220165 [CA 5] Center 36 (7~65) winsize 59
7476 22:15:24.220247
7477 22:15:24.223106 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7478 22:15:24.223188
7479 22:15:24.226504 [CATrainingPosCal] consider 1 rank data
7480 22:15:24.230097 u2DelayCellTimex100 = 285/100 ps
7481 22:15:24.233360 CA0 delay=43 (12~74),Diff = 7 PI (23 cell)
7482 22:15:24.239918 CA1 delay=43 (13~74),Diff = 7 PI (23 cell)
7483 22:15:24.243514 CA2 delay=38 (9~68),Diff = 2 PI (6 cell)
7484 22:15:24.246471 CA3 delay=38 (8~68),Diff = 2 PI (6 cell)
7485 22:15:24.249803 CA4 delay=37 (7~67),Diff = 1 PI (3 cell)
7486 22:15:24.253180 CA5 delay=36 (7~65),Diff = 0 PI (0 cell)
7487 22:15:24.253261
7488 22:15:24.256422 CA PerBit enable=1, Macro0, CA PI delay=36
7489 22:15:24.256504
7490 22:15:24.259994 [CBTSetCACLKResult] CA Dly = 36
7491 22:15:24.263028 CS Dly: 9 (0~40)
7492 22:15:24.266659 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7493 22:15:24.269926 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7494 22:15:24.270008 ==
7495 22:15:24.273025 Dram Type= 6, Freq= 0, CH_0, rank 1
7496 22:15:24.276632 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7497 22:15:24.276715 ==
7498 22:15:24.283267 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7499 22:15:24.286532 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7500 22:15:24.293115 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7501 22:15:24.296485 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7502 22:15:24.306380 [CA 0] Center 42 (12~73) winsize 62
7503 22:15:24.309552 [CA 1] Center 42 (12~73) winsize 62
7504 22:15:24.313196 [CA 2] Center 37 (8~67) winsize 60
7505 22:15:24.316774 [CA 3] Center 38 (8~68) winsize 61
7506 22:15:24.319738 [CA 4] Center 35 (6~65) winsize 60
7507 22:15:24.322986 [CA 5] Center 35 (5~65) winsize 61
7508 22:15:24.323058
7509 22:15:24.326849 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7510 22:15:24.326953
7511 22:15:24.330352 [CATrainingPosCal] consider 2 rank data
7512 22:15:24.333083 u2DelayCellTimex100 = 285/100 ps
7513 22:15:24.336498 CA0 delay=42 (12~73),Diff = 6 PI (20 cell)
7514 22:15:24.343458 CA1 delay=43 (13~73),Diff = 7 PI (23 cell)
7515 22:15:24.346408 CA2 delay=38 (9~67),Diff = 2 PI (6 cell)
7516 22:15:24.349837 CA3 delay=38 (8~68),Diff = 2 PI (6 cell)
7517 22:15:24.352952 CA4 delay=36 (7~65),Diff = 0 PI (0 cell)
7518 22:15:24.356456 CA5 delay=36 (7~65),Diff = 0 PI (0 cell)
7519 22:15:24.356536
7520 22:15:24.359766 CA PerBit enable=1, Macro0, CA PI delay=36
7521 22:15:24.359846
7522 22:15:24.363038 [CBTSetCACLKResult] CA Dly = 36
7523 22:15:24.363118 CS Dly: 10 (0~42)
7524 22:15:24.370302 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7525 22:15:24.373617 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7526 22:15:24.373699
7527 22:15:24.376829 ----->DramcWriteLeveling(PI) begin...
7528 22:15:24.376912 ==
7529 22:15:24.380026 Dram Type= 6, Freq= 0, CH_0, rank 0
7530 22:15:24.383079 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7531 22:15:24.383161 ==
7532 22:15:24.386848 Write leveling (Byte 0): 34 => 34
7533 22:15:24.389762 Write leveling (Byte 1): 28 => 28
7534 22:15:24.393551 DramcWriteLeveling(PI) end<-----
7535 22:15:24.393628
7536 22:15:24.393699 ==
7537 22:15:24.396856 Dram Type= 6, Freq= 0, CH_0, rank 0
7538 22:15:24.403221 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7539 22:15:24.403297 ==
7540 22:15:24.403404 [Gating] SW mode calibration
7541 22:15:24.413014 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7542 22:15:24.416264 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7543 22:15:24.419726 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7544 22:15:24.426679 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7545 22:15:24.429737 1 4 8 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
7546 22:15:24.433004 1 4 12 | B1->B0 | 2323 3535 | 0 0 | (0 0) (0 0)
7547 22:15:24.439565 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7548 22:15:24.443147 1 4 20 | B1->B0 | 3434 3636 | 1 1 | (1 1) (1 1)
7549 22:15:24.446193 1 4 24 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
7550 22:15:24.453209 1 4 28 | B1->B0 | 3434 3636 | 1 1 | (1 1) (0 0)
7551 22:15:24.456643 1 5 0 | B1->B0 | 3434 3636 | 1 0 | (1 1) (0 0)
7552 22:15:24.459620 1 5 4 | B1->B0 | 3434 3535 | 1 1 | (1 1) (0 0)
7553 22:15:24.466233 1 5 8 | B1->B0 | 3434 3333 | 1 0 | (1 1) (1 1)
7554 22:15:24.469305 1 5 12 | B1->B0 | 3434 2525 | 1 0 | (1 1) (0 0)
7555 22:15:24.472907 1 5 16 | B1->B0 | 3333 2323 | 1 0 | (1 0) (0 0)
7556 22:15:24.479431 1 5 20 | B1->B0 | 2525 2525 | 0 0 | (1 1) (0 0)
7557 22:15:24.482785 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7558 22:15:24.486720 1 5 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7559 22:15:24.493157 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7560 22:15:24.496046 1 6 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7561 22:15:24.499441 1 6 8 | B1->B0 | 2323 3332 | 0 1 | (0 0) (1 1)
7562 22:15:24.506436 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7563 22:15:24.509264 1 6 16 | B1->B0 | 2828 4646 | 0 0 | (0 0) (0 0)
7564 22:15:24.512850 1 6 20 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
7565 22:15:24.519319 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7566 22:15:24.522516 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7567 22:15:24.526073 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7568 22:15:24.532771 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7569 22:15:24.536408 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7570 22:15:24.539213 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7571 22:15:24.545854 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7572 22:15:24.549439 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7573 22:15:24.552781 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7574 22:15:24.555788 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7575 22:15:24.562800 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7576 22:15:24.566096 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7577 22:15:24.569565 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7578 22:15:24.575654 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7579 22:15:24.579204 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7580 22:15:24.582409 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7581 22:15:24.589238 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7582 22:15:24.592776 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7583 22:15:24.595789 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7584 22:15:24.602445 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7585 22:15:24.605964 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7586 22:15:24.609448 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7587 22:15:24.612785 Total UI for P1: 0, mck2ui 16
7588 22:15:24.615710 best dqsien dly found for B0: ( 1, 9, 8)
7589 22:15:24.622283 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7590 22:15:24.625820 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7591 22:15:24.629560 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7592 22:15:24.632441 Total UI for P1: 0, mck2ui 16
7593 22:15:24.636118 best dqsien dly found for B1: ( 1, 9, 16)
7594 22:15:24.638990 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
7595 22:15:24.642519 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
7596 22:15:24.642601
7597 22:15:24.645678 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
7598 22:15:24.652172 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
7599 22:15:24.652255 [Gating] SW calibration Done
7600 22:15:24.655603 ==
7601 22:15:24.659062 Dram Type= 6, Freq= 0, CH_0, rank 0
7602 22:15:24.662281 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7603 22:15:24.662364 ==
7604 22:15:24.662428 RX Vref Scan: 0
7605 22:15:24.662486
7606 22:15:24.665863 RX Vref 0 -> 0, step: 1
7607 22:15:24.665944
7608 22:15:24.669237 RX Delay 0 -> 252, step: 8
7609 22:15:24.672250 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
7610 22:15:24.675811 iDelay=200, Bit 1, Center 143 (88 ~ 199) 112
7611 22:15:24.678738 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
7612 22:15:24.685783 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7613 22:15:24.688861 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7614 22:15:24.692141 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7615 22:15:24.695619 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7616 22:15:24.698610 iDelay=200, Bit 7, Center 143 (96 ~ 191) 96
7617 22:15:24.704983 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
7618 22:15:24.708436 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
7619 22:15:24.711891 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
7620 22:15:24.715285 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
7621 22:15:24.718976 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7622 22:15:24.725208 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
7623 22:15:24.728969 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7624 22:15:24.732029 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7625 22:15:24.732111 ==
7626 22:15:24.735275 Dram Type= 6, Freq= 0, CH_0, rank 0
7627 22:15:24.739013 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7628 22:15:24.739096 ==
7629 22:15:24.741839 DQS Delay:
7630 22:15:24.741920 DQS0 = 0, DQS1 = 0
7631 22:15:24.745507 DQM Delay:
7632 22:15:24.745589 DQM0 = 136, DQM1 = 129
7633 22:15:24.745653 DQ Delay:
7634 22:15:24.751781 DQ0 =135, DQ1 =143, DQ2 =131, DQ3 =131
7635 22:15:24.755538 DQ4 =139, DQ5 =123, DQ6 =147, DQ7 =143
7636 22:15:24.758702 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
7637 22:15:24.762264 DQ12 =131, DQ13 =139, DQ14 =139, DQ15 =135
7638 22:15:24.762346
7639 22:15:24.762410
7640 22:15:24.762470 ==
7641 22:15:24.765196 Dram Type= 6, Freq= 0, CH_0, rank 0
7642 22:15:24.768812 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7643 22:15:24.768895 ==
7644 22:15:24.768959
7645 22:15:24.769017
7646 22:15:24.772079 TX Vref Scan disable
7647 22:15:24.775302 == TX Byte 0 ==
7648 22:15:24.778823 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7649 22:15:24.781833 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7650 22:15:24.785388 == TX Byte 1 ==
7651 22:15:24.788720 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7652 22:15:24.791783 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7653 22:15:24.791865 ==
7654 22:15:24.795182 Dram Type= 6, Freq= 0, CH_0, rank 0
7655 22:15:24.798711 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7656 22:15:24.801789 ==
7657 22:15:24.813553
7658 22:15:24.816609 TX Vref early break, caculate TX vref
7659 22:15:24.819897 TX Vref=16, minBit 0, minWin=23, winSum=377
7660 22:15:24.823594 TX Vref=18, minBit 7, minWin=23, winSum=388
7661 22:15:24.826779 TX Vref=20, minBit 7, minWin=23, winSum=400
7662 22:15:24.829929 TX Vref=22, minBit 0, minWin=25, winSum=407
7663 22:15:24.833621 TX Vref=24, minBit 2, minWin=25, winSum=417
7664 22:15:24.840179 TX Vref=26, minBit 0, minWin=26, winSum=426
7665 22:15:24.843670 TX Vref=28, minBit 0, minWin=25, winSum=422
7666 22:15:24.846845 TX Vref=30, minBit 6, minWin=24, winSum=414
7667 22:15:24.850408 TX Vref=32, minBit 0, minWin=24, winSum=406
7668 22:15:24.853492 TX Vref=34, minBit 1, minWin=23, winSum=398
7669 22:15:24.859995 [TxChooseVref] Worse bit 0, Min win 26, Win sum 426, Final Vref 26
7670 22:15:24.860078
7671 22:15:24.863830 Final TX Range 0 Vref 26
7672 22:15:24.863912
7673 22:15:24.863976 ==
7674 22:15:24.867160 Dram Type= 6, Freq= 0, CH_0, rank 0
7675 22:15:24.870645 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7676 22:15:24.870728 ==
7677 22:15:24.870792
7678 22:15:24.870850
7679 22:15:24.873368 TX Vref Scan disable
7680 22:15:24.880439 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
7681 22:15:24.880521 == TX Byte 0 ==
7682 22:15:24.883831 u2DelayCellOfst[0]=10 cells (3 PI)
7683 22:15:24.886990 u2DelayCellOfst[1]=13 cells (4 PI)
7684 22:15:24.890615 u2DelayCellOfst[2]=10 cells (3 PI)
7685 22:15:24.893567 u2DelayCellOfst[3]=10 cells (3 PI)
7686 22:15:24.896730 u2DelayCellOfst[4]=10 cells (3 PI)
7687 22:15:24.900422 u2DelayCellOfst[5]=0 cells (0 PI)
7688 22:15:24.900504 u2DelayCellOfst[6]=17 cells (5 PI)
7689 22:15:24.903458 u2DelayCellOfst[7]=17 cells (5 PI)
7690 22:15:24.910028 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7691 22:15:24.913349 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7692 22:15:24.913431 == TX Byte 1 ==
7693 22:15:24.917182 u2DelayCellOfst[8]=0 cells (0 PI)
7694 22:15:24.919865 u2DelayCellOfst[9]=0 cells (0 PI)
7695 22:15:24.923418 u2DelayCellOfst[10]=10 cells (3 PI)
7696 22:15:24.926531 u2DelayCellOfst[11]=6 cells (2 PI)
7697 22:15:24.930403 u2DelayCellOfst[12]=10 cells (3 PI)
7698 22:15:24.933657 u2DelayCellOfst[13]=13 cells (4 PI)
7699 22:15:24.937043 u2DelayCellOfst[14]=13 cells (4 PI)
7700 22:15:24.939787 u2DelayCellOfst[15]=10 cells (3 PI)
7701 22:15:24.943526 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7702 22:15:24.950040 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7703 22:15:24.950122 DramC Write-DBI on
7704 22:15:24.950186 ==
7705 22:15:24.953042 Dram Type= 6, Freq= 0, CH_0, rank 0
7706 22:15:24.956817 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7707 22:15:24.956900 ==
7708 22:15:24.956965
7709 22:15:24.959914
7710 22:15:24.959995 TX Vref Scan disable
7711 22:15:24.963467 == TX Byte 0 ==
7712 22:15:24.966290 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
7713 22:15:24.970170 == TX Byte 1 ==
7714 22:15:24.973061 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
7715 22:15:24.973142 DramC Write-DBI off
7716 22:15:24.973206
7717 22:15:24.976532 [DATLAT]
7718 22:15:24.976614 Freq=1600, CH0 RK0
7719 22:15:24.976679
7720 22:15:24.979735 DATLAT Default: 0xf
7721 22:15:24.979817 0, 0xFFFF, sum = 0
7722 22:15:24.982895 1, 0xFFFF, sum = 0
7723 22:15:24.982979 2, 0xFFFF, sum = 0
7724 22:15:24.986641 3, 0xFFFF, sum = 0
7725 22:15:24.986724 4, 0xFFFF, sum = 0
7726 22:15:24.989922 5, 0xFFFF, sum = 0
7727 22:15:24.993258 6, 0xFFFF, sum = 0
7728 22:15:24.993341 7, 0xFFFF, sum = 0
7729 22:15:24.996779 8, 0xFFFF, sum = 0
7730 22:15:24.996862 9, 0xFFFF, sum = 0
7731 22:15:24.999712 10, 0xFFFF, sum = 0
7732 22:15:24.999794 11, 0xFFFF, sum = 0
7733 22:15:25.003285 12, 0xFFFF, sum = 0
7734 22:15:25.003408 13, 0xFFFF, sum = 0
7735 22:15:25.006812 14, 0x0, sum = 1
7736 22:15:25.006895 15, 0x0, sum = 2
7737 22:15:25.009978 16, 0x0, sum = 3
7738 22:15:25.010060 17, 0x0, sum = 4
7739 22:15:25.010125 best_step = 15
7740 22:15:25.013141
7741 22:15:25.013222 ==
7742 22:15:25.016762 Dram Type= 6, Freq= 0, CH_0, rank 0
7743 22:15:25.019636 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7744 22:15:25.019719 ==
7745 22:15:25.019784 RX Vref Scan: 1
7746 22:15:25.019844
7747 22:15:25.022983 Set Vref Range= 24 -> 127
7748 22:15:25.023064
7749 22:15:25.026470 RX Vref 24 -> 127, step: 1
7750 22:15:25.026551
7751 22:15:25.030102 RX Delay 19 -> 252, step: 4
7752 22:15:25.030185
7753 22:15:25.033437 Set Vref, RX VrefLevel [Byte0]: 24
7754 22:15:25.036826 [Byte1]: 24
7755 22:15:25.036907
7756 22:15:25.040029 Set Vref, RX VrefLevel [Byte0]: 25
7757 22:15:25.042965 [Byte1]: 25
7758 22:15:25.043046
7759 22:15:25.046472 Set Vref, RX VrefLevel [Byte0]: 26
7760 22:15:25.049880 [Byte1]: 26
7761 22:15:25.053710
7762 22:15:25.053791 Set Vref, RX VrefLevel [Byte0]: 27
7763 22:15:25.056813 [Byte1]: 27
7764 22:15:25.060949
7765 22:15:25.061031 Set Vref, RX VrefLevel [Byte0]: 28
7766 22:15:25.063963 [Byte1]: 28
7767 22:15:25.069026
7768 22:15:25.069107 Set Vref, RX VrefLevel [Byte0]: 29
7769 22:15:25.071673 [Byte1]: 29
7770 22:15:25.075843
7771 22:15:25.075923 Set Vref, RX VrefLevel [Byte0]: 30
7772 22:15:25.079495 [Byte1]: 30
7773 22:15:25.083529
7774 22:15:25.083610 Set Vref, RX VrefLevel [Byte0]: 31
7775 22:15:25.086790 [Byte1]: 31
7776 22:15:25.090990
7777 22:15:25.091071 Set Vref, RX VrefLevel [Byte0]: 32
7778 22:15:25.094274 [Byte1]: 32
7779 22:15:25.098729
7780 22:15:25.098810 Set Vref, RX VrefLevel [Byte0]: 33
7781 22:15:25.102039 [Byte1]: 33
7782 22:15:25.106428
7783 22:15:25.106509 Set Vref, RX VrefLevel [Byte0]: 34
7784 22:15:25.109534 [Byte1]: 34
7785 22:15:25.114140
7786 22:15:25.114224 Set Vref, RX VrefLevel [Byte0]: 35
7787 22:15:25.117613 [Byte1]: 35
7788 22:15:25.121704
7789 22:15:25.121786 Set Vref, RX VrefLevel [Byte0]: 36
7790 22:15:25.124999 [Byte1]: 36
7791 22:15:25.129200
7792 22:15:25.129281 Set Vref, RX VrefLevel [Byte0]: 37
7793 22:15:25.132498 [Byte1]: 37
7794 22:15:25.136647
7795 22:15:25.136729 Set Vref, RX VrefLevel [Byte0]: 38
7796 22:15:25.140207 [Byte1]: 38
7797 22:15:25.144389
7798 22:15:25.144471 Set Vref, RX VrefLevel [Byte0]: 39
7799 22:15:25.147302 [Byte1]: 39
7800 22:15:25.151790
7801 22:15:25.151871 Set Vref, RX VrefLevel [Byte0]: 40
7802 22:15:25.155636 [Byte1]: 40
7803 22:15:25.159144
7804 22:15:25.159226 Set Vref, RX VrefLevel [Byte0]: 41
7805 22:15:25.162843 [Byte1]: 41
7806 22:15:25.167132
7807 22:15:25.167213 Set Vref, RX VrefLevel [Byte0]: 42
7808 22:15:25.170494 [Byte1]: 42
7809 22:15:25.174548
7810 22:15:25.174629 Set Vref, RX VrefLevel [Byte0]: 43
7811 22:15:25.177582 [Byte1]: 43
7812 22:15:25.181967
7813 22:15:25.182048 Set Vref, RX VrefLevel [Byte0]: 44
7814 22:15:25.185652 [Byte1]: 44
7815 22:15:25.189621
7816 22:15:25.189703 Set Vref, RX VrefLevel [Byte0]: 45
7817 22:15:25.192791 [Byte1]: 45
7818 22:15:25.197340
7819 22:15:25.197421 Set Vref, RX VrefLevel [Byte0]: 46
7820 22:15:25.200797 [Byte1]: 46
7821 22:15:25.204507
7822 22:15:25.204627 Set Vref, RX VrefLevel [Byte0]: 47
7823 22:15:25.207769 [Byte1]: 47
7824 22:15:25.212059
7825 22:15:25.212140 Set Vref, RX VrefLevel [Byte0]: 48
7826 22:15:25.215703 [Byte1]: 48
7827 22:15:25.219740
7828 22:15:25.219822 Set Vref, RX VrefLevel [Byte0]: 49
7829 22:15:25.223537 [Byte1]: 49
7830 22:15:25.227512
7831 22:15:25.227593 Set Vref, RX VrefLevel [Byte0]: 50
7832 22:15:25.231021 [Byte1]: 50
7833 22:15:25.235363
7834 22:15:25.235459 Set Vref, RX VrefLevel [Byte0]: 51
7835 22:15:25.238242 [Byte1]: 51
7836 22:15:25.242396
7837 22:15:25.242477 Set Vref, RX VrefLevel [Byte0]: 52
7838 22:15:25.245861 [Byte1]: 52
7839 22:15:25.250480
7840 22:15:25.250561 Set Vref, RX VrefLevel [Byte0]: 53
7841 22:15:25.253604 [Byte1]: 53
7842 22:15:25.257597
7843 22:15:25.257678 Set Vref, RX VrefLevel [Byte0]: 54
7844 22:15:25.261238 [Byte1]: 54
7845 22:15:25.265657
7846 22:15:25.265739 Set Vref, RX VrefLevel [Byte0]: 55
7847 22:15:25.268547 [Byte1]: 55
7848 22:15:25.272825
7849 22:15:25.272909 Set Vref, RX VrefLevel [Byte0]: 56
7850 22:15:25.276500 [Byte1]: 56
7851 22:15:25.280627
7852 22:15:25.280708 Set Vref, RX VrefLevel [Byte0]: 57
7853 22:15:25.284234 [Byte1]: 57
7854 22:15:25.287870
7855 22:15:25.287951 Set Vref, RX VrefLevel [Byte0]: 58
7856 22:15:25.291161 [Byte1]: 58
7857 22:15:25.295780
7858 22:15:25.295861 Set Vref, RX VrefLevel [Byte0]: 59
7859 22:15:25.298898 [Byte1]: 59
7860 22:15:25.303466
7861 22:15:25.303547 Set Vref, RX VrefLevel [Byte0]: 60
7862 22:15:25.306922 [Byte1]: 60
7863 22:15:25.310832
7864 22:15:25.310914 Set Vref, RX VrefLevel [Byte0]: 61
7865 22:15:25.314272 [Byte1]: 61
7866 22:15:25.318591
7867 22:15:25.318672 Set Vref, RX VrefLevel [Byte0]: 62
7868 22:15:25.321976 [Byte1]: 62
7869 22:15:25.325778
7870 22:15:25.325860 Set Vref, RX VrefLevel [Byte0]: 63
7871 22:15:25.329331 [Byte1]: 63
7872 22:15:25.333521
7873 22:15:25.333603 Set Vref, RX VrefLevel [Byte0]: 64
7874 22:15:25.337111 [Byte1]: 64
7875 22:15:25.341227
7876 22:15:25.341308 Set Vref, RX VrefLevel [Byte0]: 65
7877 22:15:25.344418 [Byte1]: 65
7878 22:15:25.348786
7879 22:15:25.348867 Set Vref, RX VrefLevel [Byte0]: 66
7880 22:15:25.351783 [Byte1]: 66
7881 22:15:25.356107
7882 22:15:25.356188 Set Vref, RX VrefLevel [Byte0]: 67
7883 22:15:25.359456 [Byte1]: 67
7884 22:15:25.363603
7885 22:15:25.363684 Set Vref, RX VrefLevel [Byte0]: 68
7886 22:15:25.366937 [Byte1]: 68
7887 22:15:25.371138
7888 22:15:25.371219 Set Vref, RX VrefLevel [Byte0]: 69
7889 22:15:25.374574 [Byte1]: 69
7890 22:15:25.378932
7891 22:15:25.379014 Set Vref, RX VrefLevel [Byte0]: 70
7892 22:15:25.382290 [Byte1]: 70
7893 22:15:25.386566
7894 22:15:25.386647 Set Vref, RX VrefLevel [Byte0]: 71
7895 22:15:25.389684 [Byte1]: 71
7896 22:15:25.394044
7897 22:15:25.394125 Set Vref, RX VrefLevel [Byte0]: 72
7898 22:15:25.397241 [Byte1]: 72
7899 22:15:25.402065
7900 22:15:25.402147 Final RX Vref Byte 0 = 59 to rank0
7901 22:15:25.404893 Final RX Vref Byte 1 = 66 to rank0
7902 22:15:25.408107 Final RX Vref Byte 0 = 59 to rank1
7903 22:15:25.412046 Final RX Vref Byte 1 = 66 to rank1==
7904 22:15:25.415340 Dram Type= 6, Freq= 0, CH_0, rank 0
7905 22:15:25.421548 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7906 22:15:25.421630 ==
7907 22:15:25.421696 DQS Delay:
7908 22:15:25.421756 DQS0 = 0, DQS1 = 0
7909 22:15:25.424931 DQM Delay:
7910 22:15:25.425012 DQM0 = 134, DQM1 = 128
7911 22:15:25.428604 DQ Delay:
7912 22:15:25.431879 DQ0 =134, DQ1 =138, DQ2 =134, DQ3 =134
7913 22:15:25.434968 DQ4 =134, DQ5 =124, DQ6 =140, DQ7 =140
7914 22:15:25.438462 DQ8 =118, DQ9 =118, DQ10 =132, DQ11 =122
7915 22:15:25.441946 DQ12 =132, DQ13 =132, DQ14 =140, DQ15 =136
7916 22:15:25.442052
7917 22:15:25.442144
7918 22:15:25.442231
7919 22:15:25.445294 [DramC_TX_OE_Calibration] TA2
7920 22:15:25.448452 Original DQ_B0 (3 6) =30, OEN = 27
7921 22:15:25.451789 Original DQ_B1 (3 6) =30, OEN = 27
7922 22:15:25.451871 24, 0x0, End_B0=24 End_B1=24
7923 22:15:25.455291 25, 0x0, End_B0=25 End_B1=25
7924 22:15:25.458406 26, 0x0, End_B0=26 End_B1=26
7925 22:15:25.461638 27, 0x0, End_B0=27 End_B1=27
7926 22:15:25.464793 28, 0x0, End_B0=28 End_B1=28
7927 22:15:25.464876 29, 0x0, End_B0=29 End_B1=29
7928 22:15:25.468268 30, 0x0, End_B0=30 End_B1=30
7929 22:15:25.471580 31, 0x4141, End_B0=30 End_B1=30
7930 22:15:25.474917 Byte0 end_step=30 best_step=27
7931 22:15:25.478105 Byte1 end_step=30 best_step=27
7932 22:15:25.481632 Byte0 TX OE(2T, 0.5T) = (3, 3)
7933 22:15:25.481713 Byte1 TX OE(2T, 0.5T) = (3, 3)
7934 22:15:25.481778
7935 22:15:25.484537
7936 22:15:25.491338 [DQSOSCAuto] RK0, (LSB)MR18= 0x2723, (MSB)MR19= 0x303, tDQSOscB0 = 392 ps tDQSOscB1 = 390 ps
7937 22:15:25.494924 CH0 RK0: MR19=303, MR18=2723
7938 22:15:25.501446 CH0_RK0: MR19=0x303, MR18=0x2723, DQSOSC=390, MR23=63, INC=24, DEC=16
7939 22:15:25.501530
7940 22:15:25.504872 ----->DramcWriteLeveling(PI) begin...
7941 22:15:25.504955 ==
7942 22:15:25.507953 Dram Type= 6, Freq= 0, CH_0, rank 1
7943 22:15:25.511246 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7944 22:15:25.511357 ==
7945 22:15:25.514719 Write leveling (Byte 0): 35 => 35
7946 22:15:25.517943 Write leveling (Byte 1): 28 => 28
7947 22:15:25.521184 DramcWriteLeveling(PI) end<-----
7948 22:15:25.521266
7949 22:15:25.521329 ==
7950 22:15:25.524866 Dram Type= 6, Freq= 0, CH_0, rank 1
7951 22:15:25.528403 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7952 22:15:25.528485 ==
7953 22:15:25.531638 [Gating] SW mode calibration
7954 22:15:25.537812 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7955 22:15:25.544589 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7956 22:15:25.548108 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7957 22:15:25.551270 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7958 22:15:25.557943 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7959 22:15:25.561360 1 4 12 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
7960 22:15:25.564562 1 4 16 | B1->B0 | 2e2e 3737 | 1 1 | (1 1) (1 1)
7961 22:15:25.571055 1 4 20 | B1->B0 | 3434 3534 | 1 1 | (1 1) (0 0)
7962 22:15:25.574798 1 4 24 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
7963 22:15:25.577941 1 4 28 | B1->B0 | 3434 3635 | 1 1 | (1 1) (1 1)
7964 22:15:25.584413 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7965 22:15:25.587507 1 5 4 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
7966 22:15:25.590925 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7967 22:15:25.597577 1 5 12 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (0 1)
7968 22:15:25.601598 1 5 16 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (1 0)
7969 22:15:25.604464 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7970 22:15:25.611297 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7971 22:15:25.614763 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7972 22:15:25.617737 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7973 22:15:25.624384 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7974 22:15:25.627879 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7975 22:15:25.631152 1 6 12 | B1->B0 | 2525 3b3b | 0 0 | (0 0) (0 0)
7976 22:15:25.634465 1 6 16 | B1->B0 | 4343 4645 | 0 1 | (0 0) (0 0)
7977 22:15:25.641204 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7978 22:15:25.644139 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7979 22:15:25.647918 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7980 22:15:25.654323 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7981 22:15:25.657935 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7982 22:15:25.661166 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7983 22:15:25.667775 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7984 22:15:25.670865 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7985 22:15:25.674271 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7986 22:15:25.681433 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7987 22:15:25.684069 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7988 22:15:25.687338 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7989 22:15:25.694455 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7990 22:15:25.697385 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7991 22:15:25.701029 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7992 22:15:25.707474 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7993 22:15:25.710843 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7994 22:15:25.713849 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7995 22:15:25.721053 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7996 22:15:25.723998 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7997 22:15:25.727624 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7998 22:15:25.734167 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7999 22:15:25.737253 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8000 22:15:25.741248 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8001 22:15:25.747394 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8002 22:15:25.747475 Total UI for P1: 0, mck2ui 16
8003 22:15:25.750747 best dqsien dly found for B0: ( 1, 9, 14)
8004 22:15:25.753922 Total UI for P1: 0, mck2ui 16
8005 22:15:25.757285 best dqsien dly found for B1: ( 1, 9, 14)
8006 22:15:25.763945 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8007 22:15:25.767279 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8008 22:15:25.767404
8009 22:15:25.770678 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8010 22:15:25.774291 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8011 22:15:25.777088 [Gating] SW calibration Done
8012 22:15:25.777170 ==
8013 22:15:25.780715 Dram Type= 6, Freq= 0, CH_0, rank 1
8014 22:15:25.784066 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8015 22:15:25.784149 ==
8016 22:15:25.787063 RX Vref Scan: 0
8017 22:15:25.787145
8018 22:15:25.787209 RX Vref 0 -> 0, step: 1
8019 22:15:25.787285
8020 22:15:25.790939 RX Delay 0 -> 252, step: 8
8021 22:15:25.793814 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8022 22:15:25.797317 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8023 22:15:25.803789 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8024 22:15:25.807357 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8025 22:15:25.810786 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8026 22:15:25.813673 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8027 22:15:25.817441 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8028 22:15:25.823952 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8029 22:15:25.827619 iDelay=200, Bit 8, Center 123 (72 ~ 175) 104
8030 22:15:25.830405 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8031 22:15:25.834190 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8032 22:15:25.837010 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8033 22:15:25.844173 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8034 22:15:25.847274 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
8035 22:15:25.850594 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8036 22:15:25.853934 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8037 22:15:25.854018 ==
8038 22:15:25.857046 Dram Type= 6, Freq= 0, CH_0, rank 1
8039 22:15:25.863602 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8040 22:15:25.863685 ==
8041 22:15:25.863748 DQS Delay:
8042 22:15:25.867047 DQS0 = 0, DQS1 = 0
8043 22:15:25.867129 DQM Delay:
8044 22:15:25.867193 DQM0 = 137, DQM1 = 131
8045 22:15:25.870218 DQ Delay:
8046 22:15:25.873833 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
8047 22:15:25.876757 DQ4 =139, DQ5 =127, DQ6 =143, DQ7 =143
8048 22:15:25.880380 DQ8 =123, DQ9 =119, DQ10 =131, DQ11 =123
8049 22:15:25.883971 DQ12 =135, DQ13 =139, DQ14 =139, DQ15 =139
8050 22:15:25.884053
8051 22:15:25.884115
8052 22:15:25.884173 ==
8053 22:15:25.886803 Dram Type= 6, Freq= 0, CH_0, rank 1
8054 22:15:25.890384 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8055 22:15:25.893399 ==
8056 22:15:25.893494
8057 22:15:25.893558
8058 22:15:25.893615 TX Vref Scan disable
8059 22:15:25.897021 == TX Byte 0 ==
8060 22:15:25.900589 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
8061 22:15:25.904062 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8062 22:15:25.907108 == TX Byte 1 ==
8063 22:15:25.910012 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8064 22:15:25.913761 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8065 22:15:25.916999 ==
8066 22:15:25.920115 Dram Type= 6, Freq= 0, CH_0, rank 1
8067 22:15:25.923252 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8068 22:15:25.923343 ==
8069 22:15:25.936325
8070 22:15:25.939846 TX Vref early break, caculate TX vref
8071 22:15:25.942962 TX Vref=16, minBit 1, minWin=23, winSum=389
8072 22:15:25.946456 TX Vref=18, minBit 0, minWin=23, winSum=393
8073 22:15:25.949663 TX Vref=20, minBit 7, minWin=23, winSum=406
8074 22:15:25.953103 TX Vref=22, minBit 1, minWin=24, winSum=416
8075 22:15:25.956361 TX Vref=24, minBit 0, minWin=25, winSum=422
8076 22:15:25.962919 TX Vref=26, minBit 1, minWin=25, winSum=427
8077 22:15:25.966244 TX Vref=28, minBit 1, minWin=25, winSum=426
8078 22:15:25.969968 TX Vref=30, minBit 0, minWin=25, winSum=416
8079 22:15:25.972896 TX Vref=32, minBit 0, minWin=24, winSum=410
8080 22:15:25.976113 TX Vref=34, minBit 4, minWin=24, winSum=404
8081 22:15:25.982882 [TxChooseVref] Worse bit 1, Min win 25, Win sum 427, Final Vref 26
8082 22:15:25.982964
8083 22:15:25.986417 Final TX Range 0 Vref 26
8084 22:15:25.986499
8085 22:15:25.986562 ==
8086 22:15:25.989901 Dram Type= 6, Freq= 0, CH_0, rank 1
8087 22:15:25.992807 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8088 22:15:25.992889 ==
8089 22:15:25.992953
8090 22:15:25.993011
8091 22:15:25.996101 TX Vref Scan disable
8092 22:15:26.002875 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8093 22:15:26.002959 == TX Byte 0 ==
8094 22:15:26.006481 u2DelayCellOfst[0]=13 cells (4 PI)
8095 22:15:26.010149 u2DelayCellOfst[1]=13 cells (4 PI)
8096 22:15:26.013495 u2DelayCellOfst[2]=10 cells (3 PI)
8097 22:15:26.016458 u2DelayCellOfst[3]=10 cells (3 PI)
8098 22:15:26.020161 u2DelayCellOfst[4]=3 cells (1 PI)
8099 22:15:26.022915 u2DelayCellOfst[5]=0 cells (0 PI)
8100 22:15:26.026362 u2DelayCellOfst[6]=13 cells (4 PI)
8101 22:15:26.026443 u2DelayCellOfst[7]=17 cells (5 PI)
8102 22:15:26.033013 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8103 22:15:26.036099 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8104 22:15:26.036181 == TX Byte 1 ==
8105 22:15:26.039817 u2DelayCellOfst[8]=3 cells (1 PI)
8106 22:15:26.042916 u2DelayCellOfst[9]=0 cells (0 PI)
8107 22:15:26.046412 u2DelayCellOfst[10]=6 cells (2 PI)
8108 22:15:26.050002 u2DelayCellOfst[11]=3 cells (1 PI)
8109 22:15:26.053170 u2DelayCellOfst[12]=10 cells (3 PI)
8110 22:15:26.056216 u2DelayCellOfst[13]=13 cells (4 PI)
8111 22:15:26.059820 u2DelayCellOfst[14]=13 cells (4 PI)
8112 22:15:26.062639 u2DelayCellOfst[15]=10 cells (3 PI)
8113 22:15:26.066133 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8114 22:15:26.072778 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8115 22:15:26.072860 DramC Write-DBI on
8116 22:15:26.072924 ==
8117 22:15:26.075953 Dram Type= 6, Freq= 0, CH_0, rank 1
8118 22:15:26.079555 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8119 22:15:26.079662 ==
8120 22:15:26.082621
8121 22:15:26.082726
8122 22:15:26.082817 TX Vref Scan disable
8123 22:15:26.086046 == TX Byte 0 ==
8124 22:15:26.089396 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
8125 22:15:26.092379 == TX Byte 1 ==
8126 22:15:26.095976 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8127 22:15:26.099614 DramC Write-DBI off
8128 22:15:26.099695
8129 22:15:26.099758 [DATLAT]
8130 22:15:26.099816 Freq=1600, CH0 RK1
8131 22:15:26.099874
8132 22:15:26.102478 DATLAT Default: 0xf
8133 22:15:26.102558 0, 0xFFFF, sum = 0
8134 22:15:26.105883 1, 0xFFFF, sum = 0
8135 22:15:26.109164 2, 0xFFFF, sum = 0
8136 22:15:26.109274 3, 0xFFFF, sum = 0
8137 22:15:26.112804 4, 0xFFFF, sum = 0
8138 22:15:26.112887 5, 0xFFFF, sum = 0
8139 22:15:26.115801 6, 0xFFFF, sum = 0
8140 22:15:26.115883 7, 0xFFFF, sum = 0
8141 22:15:26.119489 8, 0xFFFF, sum = 0
8142 22:15:26.119599 9, 0xFFFF, sum = 0
8143 22:15:26.122749 10, 0xFFFF, sum = 0
8144 22:15:26.122858 11, 0xFFFF, sum = 0
8145 22:15:26.125728 12, 0xFFFF, sum = 0
8146 22:15:26.125810 13, 0xFFFF, sum = 0
8147 22:15:26.129241 14, 0x0, sum = 1
8148 22:15:26.129323 15, 0x0, sum = 2
8149 22:15:26.132474 16, 0x0, sum = 3
8150 22:15:26.132557 17, 0x0, sum = 4
8151 22:15:26.135785 best_step = 15
8152 22:15:26.135866
8153 22:15:26.135930 ==
8154 22:15:26.139443 Dram Type= 6, Freq= 0, CH_0, rank 1
8155 22:15:26.142378 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8156 22:15:26.142460 ==
8157 22:15:26.142523 RX Vref Scan: 0
8158 22:15:26.146080
8159 22:15:26.146160 RX Vref 0 -> 0, step: 1
8160 22:15:26.146224
8161 22:15:26.149438 RX Delay 19 -> 252, step: 4
8162 22:15:26.152482 iDelay=191, Bit 0, Center 134 (83 ~ 186) 104
8163 22:15:26.159264 iDelay=191, Bit 1, Center 138 (91 ~ 186) 96
8164 22:15:26.162790 iDelay=191, Bit 2, Center 132 (83 ~ 182) 100
8165 22:15:26.166213 iDelay=191, Bit 3, Center 134 (83 ~ 186) 104
8166 22:15:26.169011 iDelay=191, Bit 4, Center 136 (87 ~ 186) 100
8167 22:15:26.172622 iDelay=191, Bit 5, Center 124 (71 ~ 178) 108
8168 22:15:26.179553 iDelay=191, Bit 6, Center 138 (87 ~ 190) 104
8169 22:15:26.182314 iDelay=191, Bit 7, Center 140 (91 ~ 190) 100
8170 22:15:26.185742 iDelay=191, Bit 8, Center 120 (71 ~ 170) 100
8171 22:15:26.189512 iDelay=191, Bit 9, Center 116 (67 ~ 166) 100
8172 22:15:26.192757 iDelay=191, Bit 10, Center 128 (79 ~ 178) 100
8173 22:15:26.196150 iDelay=191, Bit 11, Center 120 (71 ~ 170) 100
8174 22:15:26.202736 iDelay=191, Bit 12, Center 134 (83 ~ 186) 104
8175 22:15:26.206269 iDelay=191, Bit 13, Center 132 (83 ~ 182) 100
8176 22:15:26.209363 iDelay=191, Bit 14, Center 136 (87 ~ 186) 100
8177 22:15:26.212754 iDelay=191, Bit 15, Center 134 (87 ~ 182) 96
8178 22:15:26.212835 ==
8179 22:15:26.215596 Dram Type= 6, Freq= 0, CH_0, rank 1
8180 22:15:26.222823 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8181 22:15:26.222905 ==
8182 22:15:26.222969 DQS Delay:
8183 22:15:26.226733 DQS0 = 0, DQS1 = 0
8184 22:15:26.226814 DQM Delay:
8185 22:15:26.226877 DQM0 = 134, DQM1 = 127
8186 22:15:26.229155 DQ Delay:
8187 22:15:26.232558 DQ0 =134, DQ1 =138, DQ2 =132, DQ3 =134
8188 22:15:26.236176 DQ4 =136, DQ5 =124, DQ6 =138, DQ7 =140
8189 22:15:26.239203 DQ8 =120, DQ9 =116, DQ10 =128, DQ11 =120
8190 22:15:26.242479 DQ12 =134, DQ13 =132, DQ14 =136, DQ15 =134
8191 22:15:26.242560
8192 22:15:26.242624
8193 22:15:26.242683
8194 22:15:26.245982 [DramC_TX_OE_Calibration] TA2
8195 22:15:26.249146 Original DQ_B0 (3 6) =30, OEN = 27
8196 22:15:26.252236 Original DQ_B1 (3 6) =30, OEN = 27
8197 22:15:26.255782 24, 0x0, End_B0=24 End_B1=24
8198 22:15:26.255865 25, 0x0, End_B0=25 End_B1=25
8199 22:15:26.259278 26, 0x0, End_B0=26 End_B1=26
8200 22:15:26.262387 27, 0x0, End_B0=27 End_B1=27
8201 22:15:26.266062 28, 0x0, End_B0=28 End_B1=28
8202 22:15:26.269137 29, 0x0, End_B0=29 End_B1=29
8203 22:15:26.269221 30, 0x0, End_B0=30 End_B1=30
8204 22:15:26.272885 31, 0x4141, End_B0=30 End_B1=30
8205 22:15:26.276238 Byte0 end_step=30 best_step=27
8206 22:15:26.279629 Byte1 end_step=30 best_step=27
8207 22:15:26.282338 Byte0 TX OE(2T, 0.5T) = (3, 3)
8208 22:15:26.286084 Byte1 TX OE(2T, 0.5T) = (3, 3)
8209 22:15:26.286175
8210 22:15:26.286239
8211 22:15:26.292332 [DQSOSCAuto] RK1, (LSB)MR18= 0x2009, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 393 ps
8212 22:15:26.295759 CH0 RK1: MR19=303, MR18=2009
8213 22:15:26.302547 CH0_RK1: MR19=0x303, MR18=0x2009, DQSOSC=393, MR23=63, INC=23, DEC=15
8214 22:15:26.306219 [RxdqsGatingPostProcess] freq 1600
8215 22:15:26.309046 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8216 22:15:26.312587 best DQS0 dly(2T, 0.5T) = (1, 1)
8217 22:15:26.315550 best DQS1 dly(2T, 0.5T) = (1, 1)
8218 22:15:26.318878 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8219 22:15:26.322561 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8220 22:15:26.326032 best DQS0 dly(2T, 0.5T) = (1, 1)
8221 22:15:26.328954 best DQS1 dly(2T, 0.5T) = (1, 1)
8222 22:15:26.332757 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8223 22:15:26.336328 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8224 22:15:26.339299 Pre-setting of DQS Precalculation
8225 22:15:26.342204 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8226 22:15:26.342307 ==
8227 22:15:26.345862 Dram Type= 6, Freq= 0, CH_1, rank 0
8228 22:15:26.349279 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8229 22:15:26.349379 ==
8230 22:15:26.355591 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8231 22:15:26.358978 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8232 22:15:26.365540 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8233 22:15:26.369056 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8234 22:15:26.379265 [CA 0] Center 41 (12~71) winsize 60
8235 22:15:26.382527 [CA 1] Center 41 (12~71) winsize 60
8236 22:15:26.385657 [CA 2] Center 38 (9~68) winsize 60
8237 22:15:26.389142 [CA 3] Center 38 (9~67) winsize 59
8238 22:15:26.392698 [CA 4] Center 38 (9~67) winsize 59
8239 22:15:26.395404 [CA 5] Center 37 (8~66) winsize 59
8240 22:15:26.395477
8241 22:15:26.398682 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8242 22:15:26.398786
8243 22:15:26.401950 [CATrainingPosCal] consider 1 rank data
8244 22:15:26.405715 u2DelayCellTimex100 = 285/100 ps
8245 22:15:26.409094 CA0 delay=41 (12~71),Diff = 4 PI (13 cell)
8246 22:15:26.415435 CA1 delay=41 (12~71),Diff = 4 PI (13 cell)
8247 22:15:26.418487 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8248 22:15:26.422471 CA3 delay=38 (9~67),Diff = 1 PI (3 cell)
8249 22:15:26.425410 CA4 delay=38 (9~67),Diff = 1 PI (3 cell)
8250 22:15:26.428635 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8251 22:15:26.428714
8252 22:15:26.431821 CA PerBit enable=1, Macro0, CA PI delay=37
8253 22:15:26.431894
8254 22:15:26.435336 [CBTSetCACLKResult] CA Dly = 37
8255 22:15:26.438308 CS Dly: 10 (0~41)
8256 22:15:26.441677 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8257 22:15:26.444966 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8258 22:15:26.445048 ==
8259 22:15:26.448703 Dram Type= 6, Freq= 0, CH_1, rank 1
8260 22:15:26.451771 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8261 22:15:26.455433 ==
8262 22:15:26.458400 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8263 22:15:26.461727 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8264 22:15:26.468344 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8265 22:15:26.471737 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8266 22:15:26.482124 [CA 0] Center 42 (12~72) winsize 61
8267 22:15:26.485695 [CA 1] Center 42 (12~72) winsize 61
8268 22:15:26.489131 [CA 2] Center 38 (9~68) winsize 60
8269 22:15:26.492185 [CA 3] Center 37 (8~67) winsize 60
8270 22:15:26.495297 [CA 4] Center 38 (8~68) winsize 61
8271 22:15:26.498775 [CA 5] Center 36 (7~66) winsize 60
8272 22:15:26.498857
8273 22:15:26.502070 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8274 22:15:26.502151
8275 22:15:26.505530 [CATrainingPosCal] consider 2 rank data
8276 22:15:26.509002 u2DelayCellTimex100 = 285/100 ps
8277 22:15:26.511971 CA0 delay=41 (12~71),Diff = 4 PI (13 cell)
8278 22:15:26.518614 CA1 delay=41 (12~71),Diff = 4 PI (13 cell)
8279 22:15:26.521956 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8280 22:15:26.525086 CA3 delay=38 (9~67),Diff = 1 PI (3 cell)
8281 22:15:26.528502 CA4 delay=38 (9~67),Diff = 1 PI (3 cell)
8282 22:15:26.532091 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8283 22:15:26.532173
8284 22:15:26.535469 CA PerBit enable=1, Macro0, CA PI delay=37
8285 22:15:26.535551
8286 22:15:26.538542 [CBTSetCACLKResult] CA Dly = 37
8287 22:15:26.542094 CS Dly: 12 (0~45)
8288 22:15:26.545187 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8289 22:15:26.549137 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8290 22:15:26.549219
8291 22:15:26.552054 ----->DramcWriteLeveling(PI) begin...
8292 22:15:26.552137 ==
8293 22:15:26.555582 Dram Type= 6, Freq= 0, CH_1, rank 0
8294 22:15:26.558947 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8295 22:15:26.559030 ==
8296 22:15:26.562384 Write leveling (Byte 0): 25 => 25
8297 22:15:26.565493 Write leveling (Byte 1): 27 => 27
8298 22:15:26.568777 DramcWriteLeveling(PI) end<-----
8299 22:15:26.568861
8300 22:15:26.568928 ==
8301 22:15:26.572446 Dram Type= 6, Freq= 0, CH_1, rank 0
8302 22:15:26.578852 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8303 22:15:26.578942 ==
8304 22:15:26.579010 [Gating] SW mode calibration
8305 22:15:26.589483 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8306 22:15:26.592218 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8307 22:15:26.595745 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8308 22:15:26.601926 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8309 22:15:26.605714 1 4 8 | B1->B0 | 2323 2a2a | 0 1 | (0 0) (0 0)
8310 22:15:26.609151 1 4 12 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
8311 22:15:26.615659 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8312 22:15:26.618971 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8313 22:15:26.622173 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8314 22:15:26.628438 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8315 22:15:26.631778 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8316 22:15:26.635338 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8317 22:15:26.641593 1 5 8 | B1->B0 | 3434 3333 | 1 1 | (1 0) (1 0)
8318 22:15:26.645064 1 5 12 | B1->B0 | 2626 2424 | 1 0 | (1 0) (1 0)
8319 22:15:26.648677 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8320 22:15:26.655043 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8321 22:15:26.658695 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8322 22:15:26.661791 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8323 22:15:26.668297 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8324 22:15:26.672005 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8325 22:15:26.674987 1 6 8 | B1->B0 | 2b2b 3f3f | 0 0 | (0 0) (0 0)
8326 22:15:26.681531 1 6 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8327 22:15:26.684611 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8328 22:15:26.688467 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8329 22:15:26.694887 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8330 22:15:26.698028 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8331 22:15:26.701745 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8332 22:15:26.708456 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8333 22:15:26.711565 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8334 22:15:26.715125 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8335 22:15:26.721695 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8336 22:15:26.725095 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8337 22:15:26.728139 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8338 22:15:26.731479 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8339 22:15:26.738275 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8340 22:15:26.741204 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8341 22:15:26.744604 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8342 22:15:26.751323 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8343 22:15:26.754750 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8344 22:15:26.758373 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8345 22:15:26.764957 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8346 22:15:26.767878 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8347 22:15:26.771607 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8348 22:15:26.778106 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8349 22:15:26.781857 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8350 22:15:26.785014 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8351 22:15:26.791245 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8352 22:15:26.791354 Total UI for P1: 0, mck2ui 16
8353 22:15:26.798379 best dqsien dly found for B0: ( 1, 9, 10)
8354 22:15:26.798461 Total UI for P1: 0, mck2ui 16
8355 22:15:26.804821 best dqsien dly found for B1: ( 1, 9, 10)
8356 22:15:26.807883 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8357 22:15:26.811395 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8358 22:15:26.811476
8359 22:15:26.814783 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8360 22:15:26.818317 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8361 22:15:26.821178 [Gating] SW calibration Done
8362 22:15:26.821259 ==
8363 22:15:26.824378 Dram Type= 6, Freq= 0, CH_1, rank 0
8364 22:15:26.827846 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8365 22:15:26.827928 ==
8366 22:15:26.831113 RX Vref Scan: 0
8367 22:15:26.831194
8368 22:15:26.831257 RX Vref 0 -> 0, step: 1
8369 22:15:26.831316
8370 22:15:26.834674 RX Delay 0 -> 252, step: 8
8371 22:15:26.837989 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8372 22:15:26.844397 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8373 22:15:26.847881 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8374 22:15:26.851180 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8375 22:15:26.854477 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8376 22:15:26.858315 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8377 22:15:26.864598 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8378 22:15:26.867624 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8379 22:15:26.871034 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
8380 22:15:26.874408 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
8381 22:15:26.877892 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8382 22:15:26.884678 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8383 22:15:26.887631 iDelay=200, Bit 12, Center 143 (88 ~ 199) 112
8384 22:15:26.891247 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8385 22:15:26.894273 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8386 22:15:26.897442 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8387 22:15:26.900746 ==
8388 22:15:26.900832 Dram Type= 6, Freq= 0, CH_1, rank 0
8389 22:15:26.907520 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8390 22:15:26.907602 ==
8391 22:15:26.907692 DQS Delay:
8392 22:15:26.910847 DQS0 = 0, DQS1 = 0
8393 22:15:26.910921 DQM Delay:
8394 22:15:26.914185 DQM0 = 136, DQM1 = 133
8395 22:15:26.914264 DQ Delay:
8396 22:15:26.917408 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8397 22:15:26.920718 DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =135
8398 22:15:26.924531 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =127
8399 22:15:26.927527 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =139
8400 22:15:26.927605
8401 22:15:26.927685
8402 22:15:26.927767 ==
8403 22:15:26.930842 Dram Type= 6, Freq= 0, CH_1, rank 0
8404 22:15:26.937351 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8405 22:15:26.937438 ==
8406 22:15:26.937520
8407 22:15:26.937595
8408 22:15:26.937671 TX Vref Scan disable
8409 22:15:26.940804 == TX Byte 0 ==
8410 22:15:26.944153 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8411 22:15:26.951045 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8412 22:15:26.951131 == TX Byte 1 ==
8413 22:15:26.954022 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8414 22:15:26.961111 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8415 22:15:26.961191 ==
8416 22:15:26.963938 Dram Type= 6, Freq= 0, CH_1, rank 0
8417 22:15:26.967583 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8418 22:15:26.967663 ==
8419 22:15:26.979299
8420 22:15:26.982580 TX Vref early break, caculate TX vref
8421 22:15:26.986206 TX Vref=16, minBit 0, minWin=23, winSum=378
8422 22:15:26.989720 TX Vref=18, minBit 0, minWin=23, winSum=387
8423 22:15:26.992724 TX Vref=20, minBit 1, minWin=23, winSum=398
8424 22:15:26.996213 TX Vref=22, minBit 0, minWin=25, winSum=408
8425 22:15:26.999666 TX Vref=24, minBit 1, minWin=25, winSum=417
8426 22:15:27.005952 TX Vref=26, minBit 0, minWin=25, winSum=425
8427 22:15:27.009238 TX Vref=28, minBit 0, minWin=25, winSum=428
8428 22:15:27.012731 TX Vref=30, minBit 0, minWin=24, winSum=419
8429 22:15:27.016183 TX Vref=32, minBit 0, minWin=24, winSum=416
8430 22:15:27.019208 TX Vref=34, minBit 0, minWin=24, winSum=403
8431 22:15:27.026044 [TxChooseVref] Worse bit 0, Min win 25, Win sum 428, Final Vref 28
8432 22:15:27.026127
8433 22:15:27.029407 Final TX Range 0 Vref 28
8434 22:15:27.029483
8435 22:15:27.029562 ==
8436 22:15:27.032724 Dram Type= 6, Freq= 0, CH_1, rank 0
8437 22:15:27.036120 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8438 22:15:27.036200 ==
8439 22:15:27.036282
8440 22:15:27.036366
8441 22:15:27.039449 TX Vref Scan disable
8442 22:15:27.046065 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8443 22:15:27.046147 == TX Byte 0 ==
8444 22:15:27.049468 u2DelayCellOfst[0]=17 cells (5 PI)
8445 22:15:27.052745 u2DelayCellOfst[1]=10 cells (3 PI)
8446 22:15:27.056370 u2DelayCellOfst[2]=0 cells (0 PI)
8447 22:15:27.059273 u2DelayCellOfst[3]=6 cells (2 PI)
8448 22:15:27.062793 u2DelayCellOfst[4]=6 cells (2 PI)
8449 22:15:27.065933 u2DelayCellOfst[5]=17 cells (5 PI)
8450 22:15:27.069594 u2DelayCellOfst[6]=17 cells (5 PI)
8451 22:15:27.069674 u2DelayCellOfst[7]=3 cells (1 PI)
8452 22:15:27.075731 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8453 22:15:27.079208 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8454 22:15:27.079281 == TX Byte 1 ==
8455 22:15:27.082518 u2DelayCellOfst[8]=0 cells (0 PI)
8456 22:15:27.085923 u2DelayCellOfst[9]=3 cells (1 PI)
8457 22:15:27.089527 u2DelayCellOfst[10]=10 cells (3 PI)
8458 22:15:27.092810 u2DelayCellOfst[11]=3 cells (1 PI)
8459 22:15:27.095871 u2DelayCellOfst[12]=17 cells (5 PI)
8460 22:15:27.099189 u2DelayCellOfst[13]=17 cells (5 PI)
8461 22:15:27.102437 u2DelayCellOfst[14]=17 cells (5 PI)
8462 22:15:27.105877 u2DelayCellOfst[15]=17 cells (5 PI)
8463 22:15:27.109435 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8464 22:15:27.112376 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8465 22:15:27.115983 DramC Write-DBI on
8466 22:15:27.116065 ==
8467 22:15:27.119607 Dram Type= 6, Freq= 0, CH_1, rank 0
8468 22:15:27.122432 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8469 22:15:27.122515 ==
8470 22:15:27.122580
8471 22:15:27.122640
8472 22:15:27.126095 TX Vref Scan disable
8473 22:15:27.129016 == TX Byte 0 ==
8474 22:15:27.132830 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8475 22:15:27.136177 == TX Byte 1 ==
8476 22:15:27.138961 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8477 22:15:27.139044 DramC Write-DBI off
8478 22:15:27.139109
8479 22:15:27.142173 [DATLAT]
8480 22:15:27.142256 Freq=1600, CH1 RK0
8481 22:15:27.142322
8482 22:15:27.145750 DATLAT Default: 0xf
8483 22:15:27.145832 0, 0xFFFF, sum = 0
8484 22:15:27.149200 1, 0xFFFF, sum = 0
8485 22:15:27.149284 2, 0xFFFF, sum = 0
8486 22:15:27.152610 3, 0xFFFF, sum = 0
8487 22:15:27.152694 4, 0xFFFF, sum = 0
8488 22:15:27.155829 5, 0xFFFF, sum = 0
8489 22:15:27.155941 6, 0xFFFF, sum = 0
8490 22:15:27.159169 7, 0xFFFF, sum = 0
8491 22:15:27.159279 8, 0xFFFF, sum = 0
8492 22:15:27.162178 9, 0xFFFF, sum = 0
8493 22:15:27.165687 10, 0xFFFF, sum = 0
8494 22:15:27.165771 11, 0xFFFF, sum = 0
8495 22:15:27.169201 12, 0xFFFF, sum = 0
8496 22:15:27.169299 13, 0xFFFF, sum = 0
8497 22:15:27.172185 14, 0x0, sum = 1
8498 22:15:27.172269 15, 0x0, sum = 2
8499 22:15:27.175601 16, 0x0, sum = 3
8500 22:15:27.175685 17, 0x0, sum = 4
8501 22:15:27.175787 best_step = 15
8502 22:15:27.179252
8503 22:15:27.179360 ==
8504 22:15:27.182547 Dram Type= 6, Freq= 0, CH_1, rank 0
8505 22:15:27.185453 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8506 22:15:27.185536 ==
8507 22:15:27.185601 RX Vref Scan: 1
8508 22:15:27.185660
8509 22:15:27.188958 Set Vref Range= 24 -> 127
8510 22:15:27.189041
8511 22:15:27.192312 RX Vref 24 -> 127, step: 1
8512 22:15:27.192394
8513 22:15:27.195727 RX Delay 27 -> 252, step: 4
8514 22:15:27.195810
8515 22:15:27.198798 Set Vref, RX VrefLevel [Byte0]: 24
8516 22:15:27.202456 [Byte1]: 24
8517 22:15:27.202538
8518 22:15:27.205364 Set Vref, RX VrefLevel [Byte0]: 25
8519 22:15:27.209354 [Byte1]: 25
8520 22:15:27.209437
8521 22:15:27.212345 Set Vref, RX VrefLevel [Byte0]: 26
8522 22:15:27.215289 [Byte1]: 26
8523 22:15:27.219031
8524 22:15:27.219113 Set Vref, RX VrefLevel [Byte0]: 27
8525 22:15:27.222206 [Byte1]: 27
8526 22:15:27.226699
8527 22:15:27.226781 Set Vref, RX VrefLevel [Byte0]: 28
8528 22:15:27.229554 [Byte1]: 28
8529 22:15:27.233857
8530 22:15:27.233939 Set Vref, RX VrefLevel [Byte0]: 29
8531 22:15:27.236942 [Byte1]: 29
8532 22:15:27.241303
8533 22:15:27.241385 Set Vref, RX VrefLevel [Byte0]: 30
8534 22:15:27.244943 [Byte1]: 30
8535 22:15:27.248889
8536 22:15:27.248971 Set Vref, RX VrefLevel [Byte0]: 31
8537 22:15:27.252738 [Byte1]: 31
8538 22:15:27.256470
8539 22:15:27.256552 Set Vref, RX VrefLevel [Byte0]: 32
8540 22:15:27.259950 [Byte1]: 32
8541 22:15:27.263889
8542 22:15:27.263972 Set Vref, RX VrefLevel [Byte0]: 33
8543 22:15:27.267304 [Byte1]: 33
8544 22:15:27.271447
8545 22:15:27.271529 Set Vref, RX VrefLevel [Byte0]: 34
8546 22:15:27.275033 [Byte1]: 34
8547 22:15:27.279591
8548 22:15:27.279673 Set Vref, RX VrefLevel [Byte0]: 35
8549 22:15:27.282460 [Byte1]: 35
8550 22:15:27.287085
8551 22:15:27.287167 Set Vref, RX VrefLevel [Byte0]: 36
8552 22:15:27.290279 [Byte1]: 36
8553 22:15:27.294278
8554 22:15:27.294360 Set Vref, RX VrefLevel [Byte0]: 37
8555 22:15:27.297837 [Byte1]: 37
8556 22:15:27.301559
8557 22:15:27.301641 Set Vref, RX VrefLevel [Byte0]: 38
8558 22:15:27.304994 [Byte1]: 38
8559 22:15:27.309505
8560 22:15:27.309587 Set Vref, RX VrefLevel [Byte0]: 39
8561 22:15:27.312799 [Byte1]: 39
8562 22:15:27.316717
8563 22:15:27.316800 Set Vref, RX VrefLevel [Byte0]: 40
8564 22:15:27.320418 [Byte1]: 40
8565 22:15:27.324455
8566 22:15:27.324537 Set Vref, RX VrefLevel [Byte0]: 41
8567 22:15:27.327474 [Byte1]: 41
8568 22:15:27.331861
8569 22:15:27.331943 Set Vref, RX VrefLevel [Byte0]: 42
8570 22:15:27.335265 [Byte1]: 42
8571 22:15:27.339536
8572 22:15:27.339618 Set Vref, RX VrefLevel [Byte0]: 43
8573 22:15:27.343176 [Byte1]: 43
8574 22:15:27.347254
8575 22:15:27.347389 Set Vref, RX VrefLevel [Byte0]: 44
8576 22:15:27.349991 [Byte1]: 44
8577 22:15:27.354372
8578 22:15:27.354449 Set Vref, RX VrefLevel [Byte0]: 45
8579 22:15:27.357964 [Byte1]: 45
8580 22:15:27.361714
8581 22:15:27.361787 Set Vref, RX VrefLevel [Byte0]: 46
8582 22:15:27.365034 [Byte1]: 46
8583 22:15:27.369542
8584 22:15:27.372593 Set Vref, RX VrefLevel [Byte0]: 47
8585 22:15:27.375852 [Byte1]: 47
8586 22:15:27.375956
8587 22:15:27.379301 Set Vref, RX VrefLevel [Byte0]: 48
8588 22:15:27.382460 [Byte1]: 48
8589 22:15:27.382532
8590 22:15:27.386071 Set Vref, RX VrefLevel [Byte0]: 49
8591 22:15:27.389554 [Byte1]: 49
8592 22:15:27.389626
8593 22:15:27.392511 Set Vref, RX VrefLevel [Byte0]: 50
8594 22:15:27.396156 [Byte1]: 50
8595 22:15:27.399613
8596 22:15:27.399685 Set Vref, RX VrefLevel [Byte0]: 51
8597 22:15:27.405950 [Byte1]: 51
8598 22:15:27.406049
8599 22:15:27.409252 Set Vref, RX VrefLevel [Byte0]: 52
8600 22:15:27.412921 [Byte1]: 52
8601 22:15:27.413025
8602 22:15:27.416455 Set Vref, RX VrefLevel [Byte0]: 53
8603 22:15:27.419451 [Byte1]: 53
8604 22:15:27.419524
8605 22:15:27.423001 Set Vref, RX VrefLevel [Byte0]: 54
8606 22:15:27.425823 [Byte1]: 54
8607 22:15:27.430128
8608 22:15:27.430200 Set Vref, RX VrefLevel [Byte0]: 55
8609 22:15:27.432846 [Byte1]: 55
8610 22:15:27.437142
8611 22:15:27.437224 Set Vref, RX VrefLevel [Byte0]: 56
8612 22:15:27.440883 [Byte1]: 56
8613 22:15:27.444925
8614 22:15:27.445008 Set Vref, RX VrefLevel [Byte0]: 57
8615 22:15:27.448157 [Byte1]: 57
8616 22:15:27.452339
8617 22:15:27.452448 Set Vref, RX VrefLevel [Byte0]: 58
8618 22:15:27.455527 [Byte1]: 58
8619 22:15:27.459659
8620 22:15:27.459741 Set Vref, RX VrefLevel [Byte0]: 59
8621 22:15:27.463137 [Byte1]: 59
8622 22:15:27.467676
8623 22:15:27.467757 Set Vref, RX VrefLevel [Byte0]: 60
8624 22:15:27.470441 [Byte1]: 60
8625 22:15:27.474898
8626 22:15:27.475008 Set Vref, RX VrefLevel [Byte0]: 61
8627 22:15:27.478219 [Byte1]: 61
8628 22:15:27.482950
8629 22:15:27.483032 Set Vref, RX VrefLevel [Byte0]: 62
8630 22:15:27.485854 [Byte1]: 62
8631 22:15:27.490192
8632 22:15:27.490278 Set Vref, RX VrefLevel [Byte0]: 63
8633 22:15:27.493391 [Byte1]: 63
8634 22:15:27.497623
8635 22:15:27.497704 Set Vref, RX VrefLevel [Byte0]: 64
8636 22:15:27.500774 [Byte1]: 64
8637 22:15:27.505144
8638 22:15:27.505225 Set Vref, RX VrefLevel [Byte0]: 65
8639 22:15:27.508243 [Byte1]: 65
8640 22:15:27.512761
8641 22:15:27.512842 Set Vref, RX VrefLevel [Byte0]: 66
8642 22:15:27.515983 [Byte1]: 66
8643 22:15:27.520136
8644 22:15:27.520217 Set Vref, RX VrefLevel [Byte0]: 67
8645 22:15:27.523726 [Byte1]: 67
8646 22:15:27.527863
8647 22:15:27.527944 Set Vref, RX VrefLevel [Byte0]: 68
8648 22:15:27.530942 [Byte1]: 68
8649 22:15:27.535052
8650 22:15:27.535134 Set Vref, RX VrefLevel [Byte0]: 69
8651 22:15:27.538318 [Byte1]: 69
8652 22:15:27.542706
8653 22:15:27.542788 Set Vref, RX VrefLevel [Byte0]: 70
8654 22:15:27.546197 [Byte1]: 70
8655 22:15:27.550619
8656 22:15:27.550699 Set Vref, RX VrefLevel [Byte0]: 71
8657 22:15:27.553445 [Byte1]: 71
8658 22:15:27.557649
8659 22:15:27.557729 Set Vref, RX VrefLevel [Byte0]: 72
8660 22:15:27.561011 [Byte1]: 72
8661 22:15:27.565258
8662 22:15:27.565339 Set Vref, RX VrefLevel [Byte0]: 73
8663 22:15:27.568471 [Byte1]: 73
8664 22:15:27.572868
8665 22:15:27.572949 Set Vref, RX VrefLevel [Byte0]: 74
8666 22:15:27.576369 [Byte1]: 74
8667 22:15:27.580660
8668 22:15:27.580740 Set Vref, RX VrefLevel [Byte0]: 75
8669 22:15:27.584037 [Byte1]: 75
8670 22:15:27.587804
8671 22:15:27.587886 Set Vref, RX VrefLevel [Byte0]: 76
8672 22:15:27.591257 [Byte1]: 76
8673 22:15:27.595812
8674 22:15:27.595892 Final RX Vref Byte 0 = 58 to rank0
8675 22:15:27.598732 Final RX Vref Byte 1 = 53 to rank0
8676 22:15:27.602255 Final RX Vref Byte 0 = 58 to rank1
8677 22:15:27.605850 Final RX Vref Byte 1 = 53 to rank1==
8678 22:15:27.608932 Dram Type= 6, Freq= 0, CH_1, rank 0
8679 22:15:27.615654 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8680 22:15:27.615737 ==
8681 22:15:27.615801 DQS Delay:
8682 22:15:27.615860 DQS0 = 0, DQS1 = 0
8683 22:15:27.618686 DQM Delay:
8684 22:15:27.618767 DQM0 = 134, DQM1 = 131
8685 22:15:27.622327 DQ Delay:
8686 22:15:27.625180 DQ0 =140, DQ1 =128, DQ2 =124, DQ3 =130
8687 22:15:27.628722 DQ4 =134, DQ5 =144, DQ6 =142, DQ7 =132
8688 22:15:27.631958 DQ8 =116, DQ9 =120, DQ10 =130, DQ11 =124
8689 22:15:27.635339 DQ12 =140, DQ13 =138, DQ14 =140, DQ15 =140
8690 22:15:27.635420
8691 22:15:27.635483
8692 22:15:27.635541
8693 22:15:27.639136 [DramC_TX_OE_Calibration] TA2
8694 22:15:27.641883 Original DQ_B0 (3 6) =30, OEN = 27
8695 22:15:27.645583 Original DQ_B1 (3 6) =30, OEN = 27
8696 22:15:27.648647 24, 0x0, End_B0=24 End_B1=24
8697 22:15:27.648729 25, 0x0, End_B0=25 End_B1=25
8698 22:15:27.652158 26, 0x0, End_B0=26 End_B1=26
8699 22:15:27.655258 27, 0x0, End_B0=27 End_B1=27
8700 22:15:27.658819 28, 0x0, End_B0=28 End_B1=28
8701 22:15:27.658901 29, 0x0, End_B0=29 End_B1=29
8702 22:15:27.662391 30, 0x0, End_B0=30 End_B1=30
8703 22:15:27.665827 31, 0x4141, End_B0=30 End_B1=30
8704 22:15:27.669272 Byte0 end_step=30 best_step=27
8705 22:15:27.672050 Byte1 end_step=30 best_step=27
8706 22:15:27.675584 Byte0 TX OE(2T, 0.5T) = (3, 3)
8707 22:15:27.675666 Byte1 TX OE(2T, 0.5T) = (3, 3)
8708 22:15:27.675737
8709 22:15:27.675816
8710 22:15:27.685366 [DQSOSCAuto] RK0, (LSB)MR18= 0x1725, (MSB)MR19= 0x303, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps
8711 22:15:27.688947 CH1 RK0: MR19=303, MR18=1725
8712 22:15:27.695689 CH1_RK0: MR19=0x303, MR18=0x1725, DQSOSC=391, MR23=63, INC=24, DEC=16
8713 22:15:27.695772
8714 22:15:27.699001 ----->DramcWriteLeveling(PI) begin...
8715 22:15:27.699083 ==
8716 22:15:27.702138 Dram Type= 6, Freq= 0, CH_1, rank 1
8717 22:15:27.705295 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8718 22:15:27.705376 ==
8719 22:15:27.708900 Write leveling (Byte 0): 28 => 28
8720 22:15:27.711971 Write leveling (Byte 1): 28 => 28
8721 22:15:27.715154 DramcWriteLeveling(PI) end<-----
8722 22:15:27.715234
8723 22:15:27.715297 ==
8724 22:15:27.719085 Dram Type= 6, Freq= 0, CH_1, rank 1
8725 22:15:27.722116 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8726 22:15:27.722199 ==
8727 22:15:27.725428 [Gating] SW mode calibration
8728 22:15:27.732162 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8729 22:15:27.738949 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8730 22:15:27.742254 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8731 22:15:27.745184 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8732 22:15:27.752449 1 4 8 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
8733 22:15:27.755292 1 4 12 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
8734 22:15:27.758980 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8735 22:15:27.765290 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8736 22:15:27.768789 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8737 22:15:27.772100 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8738 22:15:27.778825 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8739 22:15:27.782296 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8740 22:15:27.785559 1 5 8 | B1->B0 | 3030 3434 | 1 1 | (1 0) (1 0)
8741 22:15:27.788691 1 5 12 | B1->B0 | 2323 2d2d | 0 1 | (0 0) (1 0)
8742 22:15:27.795405 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8743 22:15:27.798887 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8744 22:15:27.802124 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8745 22:15:27.808466 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8746 22:15:27.811648 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8747 22:15:27.815479 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8748 22:15:27.821941 1 6 8 | B1->B0 | 3030 2323 | 0 0 | (0 0) (0 0)
8749 22:15:27.825091 1 6 12 | B1->B0 | 4646 4343 | 0 0 | (0 0) (0 0)
8750 22:15:27.828719 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8751 22:15:27.835059 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8752 22:15:27.838462 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8753 22:15:27.842349 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8754 22:15:27.848367 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8755 22:15:27.851700 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8756 22:15:27.855519 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8757 22:15:27.861963 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8758 22:15:27.865060 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8759 22:15:27.868566 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8760 22:15:27.875162 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8761 22:15:27.878363 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8762 22:15:27.881968 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8763 22:15:27.888843 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8764 22:15:27.891968 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8765 22:15:27.894806 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8766 22:15:27.901572 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8767 22:15:27.904893 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8768 22:15:27.908205 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8769 22:15:27.915059 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8770 22:15:27.918507 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8771 22:15:27.921860 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8772 22:15:27.925085 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8773 22:15:27.931483 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8774 22:15:27.934743 Total UI for P1: 0, mck2ui 16
8775 22:15:27.938173 best dqsien dly found for B1: ( 1, 9, 6)
8776 22:15:27.941730 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8777 22:15:27.945302 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8778 22:15:27.948416 Total UI for P1: 0, mck2ui 16
8779 22:15:27.951982 best dqsien dly found for B0: ( 1, 9, 12)
8780 22:15:27.954819 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8781 22:15:27.958304 best DQS1 dly(MCK, UI, PI) = (1, 9, 6)
8782 22:15:27.958386
8783 22:15:27.965316 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8784 22:15:27.968616 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 6)
8785 22:15:27.968698 [Gating] SW calibration Done
8786 22:15:27.971785 ==
8787 22:15:27.975109 Dram Type= 6, Freq= 0, CH_1, rank 1
8788 22:15:27.978210 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8789 22:15:27.978292 ==
8790 22:15:27.978358 RX Vref Scan: 0
8791 22:15:27.978418
8792 22:15:27.981566 RX Vref 0 -> 0, step: 1
8793 22:15:27.981647
8794 22:15:27.985143 RX Delay 0 -> 252, step: 8
8795 22:15:27.988561 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8796 22:15:27.991436 iDelay=208, Bit 1, Center 135 (80 ~ 191) 112
8797 22:15:27.995120 iDelay=208, Bit 2, Center 123 (72 ~ 175) 104
8798 22:15:28.001628 iDelay=208, Bit 3, Center 131 (80 ~ 183) 104
8799 22:15:28.005211 iDelay=208, Bit 4, Center 131 (80 ~ 183) 104
8800 22:15:28.008237 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8801 22:15:28.011577 iDelay=208, Bit 6, Center 143 (88 ~ 199) 112
8802 22:15:28.014857 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8803 22:15:28.021574 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8804 22:15:28.024785 iDelay=208, Bit 9, Center 119 (64 ~ 175) 112
8805 22:15:28.028143 iDelay=208, Bit 10, Center 135 (80 ~ 191) 112
8806 22:15:28.031846 iDelay=208, Bit 11, Center 131 (80 ~ 183) 104
8807 22:15:28.034778 iDelay=208, Bit 12, Center 143 (88 ~ 199) 112
8808 22:15:28.041323 iDelay=208, Bit 13, Center 143 (88 ~ 199) 112
8809 22:15:28.044940 iDelay=208, Bit 14, Center 139 (88 ~ 191) 104
8810 22:15:28.047962 iDelay=208, Bit 15, Center 143 (88 ~ 199) 112
8811 22:15:28.048046 ==
8812 22:15:28.051280 Dram Type= 6, Freq= 0, CH_1, rank 1
8813 22:15:28.054716 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8814 22:15:28.058227 ==
8815 22:15:28.058304 DQS Delay:
8816 22:15:28.058367 DQS0 = 0, DQS1 = 0
8817 22:15:28.061612 DQM Delay:
8818 22:15:28.061683 DQM0 = 136, DQM1 = 134
8819 22:15:28.064385 DQ Delay:
8820 22:15:28.067992 DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =131
8821 22:15:28.071092 DQ4 =131, DQ5 =151, DQ6 =143, DQ7 =135
8822 22:15:28.075060 DQ8 =119, DQ9 =119, DQ10 =135, DQ11 =131
8823 22:15:28.077734 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =143
8824 22:15:28.077805
8825 22:15:28.077865
8826 22:15:28.077959 ==
8827 22:15:28.081049 Dram Type= 6, Freq= 0, CH_1, rank 1
8828 22:15:28.084498 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8829 22:15:28.084596 ==
8830 22:15:28.084683
8831 22:15:28.088146
8832 22:15:28.088247 TX Vref Scan disable
8833 22:15:28.091028 == TX Byte 0 ==
8834 22:15:28.094427 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8835 22:15:28.097541 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8836 22:15:28.101329 == TX Byte 1 ==
8837 22:15:28.104282 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8838 22:15:28.107678 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8839 22:15:28.107774 ==
8840 22:15:28.111116 Dram Type= 6, Freq= 0, CH_1, rank 1
8841 22:15:28.117600 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8842 22:15:28.117696 ==
8843 22:15:28.130383
8844 22:15:28.133500 TX Vref early break, caculate TX vref
8845 22:15:28.136824 TX Vref=16, minBit 1, minWin=23, winSum=381
8846 22:15:28.140177 TX Vref=18, minBit 1, minWin=23, winSum=392
8847 22:15:28.143300 TX Vref=20, minBit 0, minWin=24, winSum=401
8848 22:15:28.146685 TX Vref=22, minBit 0, minWin=25, winSum=408
8849 22:15:28.149953 TX Vref=24, minBit 2, minWin=24, winSum=415
8850 22:15:28.156594 TX Vref=26, minBit 2, minWin=24, winSum=423
8851 22:15:28.160268 TX Vref=28, minBit 0, minWin=26, winSum=426
8852 22:15:28.163696 TX Vref=30, minBit 0, minWin=26, winSum=421
8853 22:15:28.167238 TX Vref=32, minBit 0, minWin=25, winSum=412
8854 22:15:28.170078 TX Vref=34, minBit 0, minWin=24, winSum=405
8855 22:15:28.173630 TX Vref=36, minBit 1, minWin=24, winSum=396
8856 22:15:28.180294 [TxChooseVref] Worse bit 0, Min win 26, Win sum 426, Final Vref 28
8857 22:15:28.180394
8858 22:15:28.183296 Final TX Range 0 Vref 28
8859 22:15:28.183384
8860 22:15:28.183444 ==
8861 22:15:28.186748 Dram Type= 6, Freq= 0, CH_1, rank 1
8862 22:15:28.190236 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8863 22:15:28.190331 ==
8864 22:15:28.190427
8865 22:15:28.190512
8866 22:15:28.193215 TX Vref Scan disable
8867 22:15:28.200032 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8868 22:15:28.200106 == TX Byte 0 ==
8869 22:15:28.203108 u2DelayCellOfst[0]=17 cells (5 PI)
8870 22:15:28.206499 u2DelayCellOfst[1]=10 cells (3 PI)
8871 22:15:28.209985 u2DelayCellOfst[2]=0 cells (0 PI)
8872 22:15:28.213651 u2DelayCellOfst[3]=6 cells (2 PI)
8873 22:15:28.216543 u2DelayCellOfst[4]=6 cells (2 PI)
8874 22:15:28.219958 u2DelayCellOfst[5]=17 cells (5 PI)
8875 22:15:28.223626 u2DelayCellOfst[6]=17 cells (5 PI)
8876 22:15:28.226775 u2DelayCellOfst[7]=6 cells (2 PI)
8877 22:15:28.230259 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8878 22:15:28.233135 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8879 22:15:28.236495 == TX Byte 1 ==
8880 22:15:28.236567 u2DelayCellOfst[8]=0 cells (0 PI)
8881 22:15:28.239833 u2DelayCellOfst[9]=3 cells (1 PI)
8882 22:15:28.243239 u2DelayCellOfst[10]=10 cells (3 PI)
8883 22:15:28.246724 u2DelayCellOfst[11]=3 cells (1 PI)
8884 22:15:28.249893 u2DelayCellOfst[12]=13 cells (4 PI)
8885 22:15:28.253116 u2DelayCellOfst[13]=13 cells (4 PI)
8886 22:15:28.256467 u2DelayCellOfst[14]=17 cells (5 PI)
8887 22:15:28.259802 u2DelayCellOfst[15]=17 cells (5 PI)
8888 22:15:28.263457 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8889 22:15:28.269743 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8890 22:15:28.269817 DramC Write-DBI on
8891 22:15:28.269878 ==
8892 22:15:28.272924 Dram Type= 6, Freq= 0, CH_1, rank 1
8893 22:15:28.276377 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8894 22:15:28.280102 ==
8895 22:15:28.280173
8896 22:15:28.280234
8897 22:15:28.280291 TX Vref Scan disable
8898 22:15:28.283309 == TX Byte 0 ==
8899 22:15:28.286404 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
8900 22:15:28.290243 == TX Byte 1 ==
8901 22:15:28.293139 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8902 22:15:28.296598 DramC Write-DBI off
8903 22:15:28.296670
8904 22:15:28.296747 [DATLAT]
8905 22:15:28.296806 Freq=1600, CH1 RK1
8906 22:15:28.296863
8907 22:15:28.300070 DATLAT Default: 0xf
8908 22:15:28.300150 0, 0xFFFF, sum = 0
8909 22:15:28.303078 1, 0xFFFF, sum = 0
8910 22:15:28.306529 2, 0xFFFF, sum = 0
8911 22:15:28.306626 3, 0xFFFF, sum = 0
8912 22:15:28.310173 4, 0xFFFF, sum = 0
8913 22:15:28.310252 5, 0xFFFF, sum = 0
8914 22:15:28.313336 6, 0xFFFF, sum = 0
8915 22:15:28.313432 7, 0xFFFF, sum = 0
8916 22:15:28.316502 8, 0xFFFF, sum = 0
8917 22:15:28.316573 9, 0xFFFF, sum = 0
8918 22:15:28.319712 10, 0xFFFF, sum = 0
8919 22:15:28.319781 11, 0xFFFF, sum = 0
8920 22:15:28.323308 12, 0xFFFF, sum = 0
8921 22:15:28.323387 13, 0xFFFF, sum = 0
8922 22:15:28.327040 14, 0x0, sum = 1
8923 22:15:28.327111 15, 0x0, sum = 2
8924 22:15:28.329825 16, 0x0, sum = 3
8925 22:15:28.329928 17, 0x0, sum = 4
8926 22:15:28.333228 best_step = 15
8927 22:15:28.333328
8928 22:15:28.333415 ==
8929 22:15:28.336512 Dram Type= 6, Freq= 0, CH_1, rank 1
8930 22:15:28.339608 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8931 22:15:28.339678 ==
8932 22:15:28.339737 RX Vref Scan: 0
8933 22:15:28.343244
8934 22:15:28.343381 RX Vref 0 -> 0, step: 1
8935 22:15:28.343468
8936 22:15:28.346830 RX Delay 19 -> 252, step: 4
8937 22:15:28.350121 iDelay=195, Bit 0, Center 138 (91 ~ 186) 96
8938 22:15:28.356754 iDelay=195, Bit 1, Center 130 (83 ~ 178) 96
8939 22:15:28.360050 iDelay=195, Bit 2, Center 122 (71 ~ 174) 104
8940 22:15:28.362789 iDelay=195, Bit 3, Center 130 (83 ~ 178) 96
8941 22:15:28.366593 iDelay=195, Bit 4, Center 130 (83 ~ 178) 96
8942 22:15:28.369683 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
8943 22:15:28.373081 iDelay=195, Bit 6, Center 144 (95 ~ 194) 100
8944 22:15:28.379594 iDelay=195, Bit 7, Center 134 (83 ~ 186) 104
8945 22:15:28.383771 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
8946 22:15:28.386653 iDelay=195, Bit 9, Center 120 (67 ~ 174) 108
8947 22:15:28.389612 iDelay=195, Bit 10, Center 130 (79 ~ 182) 104
8948 22:15:28.393136 iDelay=195, Bit 11, Center 126 (75 ~ 178) 104
8949 22:15:28.399542 iDelay=195, Bit 12, Center 140 (87 ~ 194) 108
8950 22:15:28.403039 iDelay=195, Bit 13, Center 136 (87 ~ 186) 100
8951 22:15:28.406536 iDelay=195, Bit 14, Center 136 (87 ~ 186) 100
8952 22:15:28.409514 iDelay=195, Bit 15, Center 140 (91 ~ 190) 100
8953 22:15:28.409611 ==
8954 22:15:28.412769 Dram Type= 6, Freq= 0, CH_1, rank 1
8955 22:15:28.419336 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8956 22:15:28.419424 ==
8957 22:15:28.419495 DQS Delay:
8958 22:15:28.422738 DQS0 = 0, DQS1 = 0
8959 22:15:28.422840 DQM Delay:
8960 22:15:28.422928 DQM0 = 134, DQM1 = 130
8961 22:15:28.426324 DQ Delay:
8962 22:15:28.429999 DQ0 =138, DQ1 =130, DQ2 =122, DQ3 =130
8963 22:15:28.432693 DQ4 =130, DQ5 =146, DQ6 =144, DQ7 =134
8964 22:15:28.436636 DQ8 =116, DQ9 =120, DQ10 =130, DQ11 =126
8965 22:15:28.439480 DQ12 =140, DQ13 =136, DQ14 =136, DQ15 =140
8966 22:15:28.439563
8967 22:15:28.439627
8968 22:15:28.439685
8969 22:15:28.443233 [DramC_TX_OE_Calibration] TA2
8970 22:15:28.446377 Original DQ_B0 (3 6) =30, OEN = 27
8971 22:15:28.449602 Original DQ_B1 (3 6) =30, OEN = 27
8972 22:15:28.452933 24, 0x0, End_B0=24 End_B1=24
8973 22:15:28.453016 25, 0x0, End_B0=25 End_B1=25
8974 22:15:28.456564 26, 0x0, End_B0=26 End_B1=26
8975 22:15:28.459916 27, 0x0, End_B0=27 End_B1=27
8976 22:15:28.463226 28, 0x0, End_B0=28 End_B1=28
8977 22:15:28.466536 29, 0x0, End_B0=29 End_B1=29
8978 22:15:28.466619 30, 0x0, End_B0=30 End_B1=30
8979 22:15:28.469738 31, 0x4545, End_B0=30 End_B1=30
8980 22:15:28.472873 Byte0 end_step=30 best_step=27
8981 22:15:28.476677 Byte1 end_step=30 best_step=27
8982 22:15:28.479617 Byte0 TX OE(2T, 0.5T) = (3, 3)
8983 22:15:28.482674 Byte1 TX OE(2T, 0.5T) = (3, 3)
8984 22:15:28.482756
8985 22:15:28.482820
8986 22:15:28.490001 [DQSOSCAuto] RK1, (LSB)MR18= 0x2208, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 392 ps
8987 22:15:28.493132 CH1 RK1: MR19=303, MR18=2208
8988 22:15:28.499623 CH1_RK1: MR19=0x303, MR18=0x2208, DQSOSC=392, MR23=63, INC=24, DEC=16
8989 22:15:28.502983 [RxdqsGatingPostProcess] freq 1600
8990 22:15:28.505977 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8991 22:15:28.509239 best DQS0 dly(2T, 0.5T) = (1, 1)
8992 22:15:28.513049 best DQS1 dly(2T, 0.5T) = (1, 1)
8993 22:15:28.515944 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8994 22:15:28.519752 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8995 22:15:28.522474 best DQS0 dly(2T, 0.5T) = (1, 1)
8996 22:15:28.526145 best DQS1 dly(2T, 0.5T) = (1, 1)
8997 22:15:28.529614 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8998 22:15:28.532801 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8999 22:15:28.536012 Pre-setting of DQS Precalculation
9000 22:15:28.539058 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9001 22:15:28.546244 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9002 22:15:28.552771 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9003 22:15:28.556038
9004 22:15:28.556122
9005 22:15:28.556191 [Calibration Summary] 3200 Mbps
9006 22:15:28.558886 CH 0, Rank 0
9007 22:15:28.558958 SW Impedance : PASS
9008 22:15:28.562485 DUTY Scan : NO K
9009 22:15:28.565848 ZQ Calibration : PASS
9010 22:15:28.565925 Jitter Meter : NO K
9011 22:15:28.569131 CBT Training : PASS
9012 22:15:28.572128 Write leveling : PASS
9013 22:15:28.572209 RX DQS gating : PASS
9014 22:15:28.575761 RX DQ/DQS(RDDQC) : PASS
9015 22:15:28.579212 TX DQ/DQS : PASS
9016 22:15:28.579289 RX DATLAT : PASS
9017 22:15:28.582405 RX DQ/DQS(Engine): PASS
9018 22:15:28.585317 TX OE : PASS
9019 22:15:28.585397 All Pass.
9020 22:15:28.585462
9021 22:15:28.585521 CH 0, Rank 1
9022 22:15:28.589400 SW Impedance : PASS
9023 22:15:28.592351 DUTY Scan : NO K
9024 22:15:28.592434 ZQ Calibration : PASS
9025 22:15:28.595443 Jitter Meter : NO K
9026 22:15:28.599233 CBT Training : PASS
9027 22:15:28.599359 Write leveling : PASS
9028 22:15:28.602114 RX DQS gating : PASS
9029 22:15:28.602189 RX DQ/DQS(RDDQC) : PASS
9030 22:15:28.605741 TX DQ/DQS : PASS
9031 22:15:28.608663 RX DATLAT : PASS
9032 22:15:28.608739 RX DQ/DQS(Engine): PASS
9033 22:15:28.612262 TX OE : PASS
9034 22:15:28.612351 All Pass.
9035 22:15:28.612418
9036 22:15:28.615736 CH 1, Rank 0
9037 22:15:28.615807 SW Impedance : PASS
9038 22:15:28.618782 DUTY Scan : NO K
9039 22:15:28.622230 ZQ Calibration : PASS
9040 22:15:28.622302 Jitter Meter : NO K
9041 22:15:28.626045 CBT Training : PASS
9042 22:15:28.628986 Write leveling : PASS
9043 22:15:28.629069 RX DQS gating : PASS
9044 22:15:28.632443 RX DQ/DQS(RDDQC) : PASS
9045 22:15:28.635579 TX DQ/DQS : PASS
9046 22:15:28.635662 RX DATLAT : PASS
9047 22:15:28.638912 RX DQ/DQS(Engine): PASS
9048 22:15:28.641991 TX OE : PASS
9049 22:15:28.642074 All Pass.
9050 22:15:28.642139
9051 22:15:28.642199 CH 1, Rank 1
9052 22:15:28.645453 SW Impedance : PASS
9053 22:15:28.648660 DUTY Scan : NO K
9054 22:15:28.648743 ZQ Calibration : PASS
9055 22:15:28.651916 Jitter Meter : NO K
9056 22:15:28.655962 CBT Training : PASS
9057 22:15:28.656044 Write leveling : PASS
9058 22:15:28.658868 RX DQS gating : PASS
9059 22:15:28.658951 RX DQ/DQS(RDDQC) : PASS
9060 22:15:28.662231 TX DQ/DQS : PASS
9061 22:15:28.665376 RX DATLAT : PASS
9062 22:15:28.665459 RX DQ/DQS(Engine): PASS
9063 22:15:28.668657 TX OE : PASS
9064 22:15:28.668741 All Pass.
9065 22:15:28.668805
9066 22:15:28.672262 DramC Write-DBI on
9067 22:15:28.675553 PER_BANK_REFRESH: Hybrid Mode
9068 22:15:28.675637 TX_TRACKING: ON
9069 22:15:28.685551 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9070 22:15:28.692039 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9071 22:15:28.698402 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9072 22:15:28.705415 [FAST_K] Save calibration result to emmc
9073 22:15:28.705498 sync common calibartion params.
9074 22:15:28.708384 sync cbt_mode0:1, 1:1
9075 22:15:28.711885 dram_init: ddr_geometry: 2
9076 22:15:28.711960 dram_init: ddr_geometry: 2
9077 22:15:28.715554 dram_init: ddr_geometry: 2
9078 22:15:28.718265 0:dram_rank_size:100000000
9079 22:15:28.721839 1:dram_rank_size:100000000
9080 22:15:28.725317 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9081 22:15:28.728398 DFS_SHUFFLE_HW_MODE: ON
9082 22:15:28.731697 dramc_set_vcore_voltage set vcore to 725000
9083 22:15:28.735169 Read voltage for 1600, 0
9084 22:15:28.735252 Vio18 = 0
9085 22:15:28.735316 Vcore = 725000
9086 22:15:28.738312 Vdram = 0
9087 22:15:28.738395 Vddq = 0
9088 22:15:28.738461 Vmddr = 0
9089 22:15:28.741710 switch to 3200 Mbps bootup
9090 22:15:28.745294 [DramcRunTimeConfig]
9091 22:15:28.745377 PHYPLL
9092 22:15:28.745442 DPM_CONTROL_AFTERK: ON
9093 22:15:28.748772 PER_BANK_REFRESH: ON
9094 22:15:28.751797 REFRESH_OVERHEAD_REDUCTION: ON
9095 22:15:28.751879 CMD_PICG_NEW_MODE: OFF
9096 22:15:28.755092 XRTWTW_NEW_MODE: ON
9097 22:15:28.758460 XRTRTR_NEW_MODE: ON
9098 22:15:28.758543 TX_TRACKING: ON
9099 22:15:28.761568 RDSEL_TRACKING: OFF
9100 22:15:28.761650 DQS Precalculation for DVFS: ON
9101 22:15:28.764958 RX_TRACKING: OFF
9102 22:15:28.765041 HW_GATING DBG: ON
9103 22:15:28.768402 ZQCS_ENABLE_LP4: ON
9104 22:15:28.768485 RX_PICG_NEW_MODE: ON
9105 22:15:28.771558 TX_PICG_NEW_MODE: ON
9106 22:15:28.774963 ENABLE_RX_DCM_DPHY: ON
9107 22:15:28.778303 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9108 22:15:28.778386 DUMMY_READ_FOR_TRACKING: OFF
9109 22:15:28.781788 !!! SPM_CONTROL_AFTERK: OFF
9110 22:15:28.785029 !!! SPM could not control APHY
9111 22:15:28.788467 IMPEDANCE_TRACKING: ON
9112 22:15:28.788551 TEMP_SENSOR: ON
9113 22:15:28.791438 HW_SAVE_FOR_SR: OFF
9114 22:15:28.791521 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9115 22:15:28.798088 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9116 22:15:28.798171 Read ODT Tracking: ON
9117 22:15:28.801386 Refresh Rate DeBounce: ON
9118 22:15:28.805198 DFS_NO_QUEUE_FLUSH: ON
9119 22:15:28.805281 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9120 22:15:28.808089 ENABLE_DFS_RUNTIME_MRW: OFF
9121 22:15:28.811166 DDR_RESERVE_NEW_MODE: ON
9122 22:15:28.814609 MR_CBT_SWITCH_FREQ: ON
9123 22:15:28.814692 =========================
9124 22:15:28.834284 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9125 22:15:28.837857 dram_init: ddr_geometry: 2
9126 22:15:28.855921 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9127 22:15:28.858961 dram_init: dram init end (result: 0)
9128 22:15:28.865950 DRAM-K: Full calibration passed in 24410 msecs
9129 22:15:28.869269 MRC: failed to locate region type 0.
9130 22:15:28.869351 DRAM rank0 size:0x100000000,
9131 22:15:28.872428 DRAM rank1 size=0x100000000
9132 22:15:28.882167 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9133 22:15:28.888830 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9134 22:15:28.895821 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9135 22:15:28.902522 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9136 22:15:28.906079 DRAM rank0 size:0x100000000,
9137 22:15:28.908806 DRAM rank1 size=0x100000000
9138 22:15:28.908888 CBMEM:
9139 22:15:28.912447 IMD: root @ 0xfffff000 254 entries.
9140 22:15:28.915821 IMD: root @ 0xffffec00 62 entries.
9141 22:15:28.918753 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9142 22:15:28.922462 WARNING: RO_VPD is uninitialized or empty.
9143 22:15:28.929041 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9144 22:15:28.936071 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9145 22:15:28.948711 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9146 22:15:28.960238 BS: romstage times (exec / console): total (unknown) / 23943 ms
9147 22:15:28.960320
9148 22:15:28.960384
9149 22:15:28.970284 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9150 22:15:28.973092 ARM64: Exception handlers installed.
9151 22:15:28.976721 ARM64: Testing exception
9152 22:15:28.979957 ARM64: Done test exception
9153 22:15:28.980039 Enumerating buses...
9154 22:15:28.983025 Show all devs... Before device enumeration.
9155 22:15:28.986450 Root Device: enabled 1
9156 22:15:28.990308 CPU_CLUSTER: 0: enabled 1
9157 22:15:28.990390 CPU: 00: enabled 1
9158 22:15:28.993509 Compare with tree...
9159 22:15:28.993591 Root Device: enabled 1
9160 22:15:28.996703 CPU_CLUSTER: 0: enabled 1
9161 22:15:29.000124 CPU: 00: enabled 1
9162 22:15:29.000205 Root Device scanning...
9163 22:15:29.003359 scan_static_bus for Root Device
9164 22:15:29.006818 CPU_CLUSTER: 0 enabled
9165 22:15:29.009889 scan_static_bus for Root Device done
9166 22:15:29.013164 scan_bus: bus Root Device finished in 8 msecs
9167 22:15:29.013247 done
9168 22:15:29.019792 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9169 22:15:29.023259 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9170 22:15:29.029979 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9171 22:15:29.032731 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9172 22:15:29.036179 Allocating resources...
9173 22:15:29.039619 Reading resources...
9174 22:15:29.043304 Root Device read_resources bus 0 link: 0
9175 22:15:29.043423 DRAM rank0 size:0x100000000,
9176 22:15:29.046452 DRAM rank1 size=0x100000000
9177 22:15:29.049721 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9178 22:15:29.053463 CPU: 00 missing read_resources
9179 22:15:29.056471 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9180 22:15:29.063270 Root Device read_resources bus 0 link: 0 done
9181 22:15:29.063389 Done reading resources.
9182 22:15:29.069739 Show resources in subtree (Root Device)...After reading.
9183 22:15:29.072948 Root Device child on link 0 CPU_CLUSTER: 0
9184 22:15:29.076356 CPU_CLUSTER: 0 child on link 0 CPU: 00
9185 22:15:29.086162 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9186 22:15:29.086246 CPU: 00
9187 22:15:29.089462 Root Device assign_resources, bus 0 link: 0
9188 22:15:29.092750 CPU_CLUSTER: 0 missing set_resources
9189 22:15:29.099611 Root Device assign_resources, bus 0 link: 0 done
9190 22:15:29.099691 Done setting resources.
9191 22:15:29.105904 Show resources in subtree (Root Device)...After assigning values.
9192 22:15:29.109197 Root Device child on link 0 CPU_CLUSTER: 0
9193 22:15:29.112748 CPU_CLUSTER: 0 child on link 0 CPU: 00
9194 22:15:29.122818 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9195 22:15:29.122901 CPU: 00
9196 22:15:29.126498 Done allocating resources.
9197 22:15:29.129440 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9198 22:15:29.132454 Enabling resources...
9199 22:15:29.132528 done.
9200 22:15:29.139224 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9201 22:15:29.139298 Initializing devices...
9202 22:15:29.142828 Root Device init
9203 22:15:29.142925 init hardware done!
9204 22:15:29.145884 0x00000018: ctrlr->caps
9205 22:15:29.149534 52.000 MHz: ctrlr->f_max
9206 22:15:29.149640 0.400 MHz: ctrlr->f_min
9207 22:15:29.152448 0x40ff8080: ctrlr->voltages
9208 22:15:29.152527 sclk: 390625
9209 22:15:29.155814 Bus Width = 1
9210 22:15:29.155912 sclk: 390625
9211 22:15:29.159094 Bus Width = 1
9212 22:15:29.159196 Early init status = 3
9213 22:15:29.165745 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9214 22:15:29.168723 in-header: 03 fc 00 00 01 00 00 00
9215 22:15:29.168805 in-data: 00
9216 22:15:29.175773 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9217 22:15:29.178766 in-header: 03 fd 00 00 00 00 00 00
9218 22:15:29.182218 in-data:
9219 22:15:29.185321 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9220 22:15:29.188926 in-header: 03 fc 00 00 01 00 00 00
9221 22:15:29.191929 in-data: 00
9222 22:15:29.195250 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9223 22:15:29.199722 in-header: 03 fd 00 00 00 00 00 00
9224 22:15:29.203031 in-data:
9225 22:15:29.206675 [SSUSB] Setting up USB HOST controller...
9226 22:15:29.210162 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9227 22:15:29.213390 [SSUSB] phy power-on done.
9228 22:15:29.216322 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9229 22:15:29.223265 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9230 22:15:29.226856 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9231 22:15:29.233314 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9232 22:15:29.239871 read SPI 0x50eb0 0x2ad3: 1175 us, 9330 KB/s, 74.640 Mbps
9233 22:15:29.246792 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9234 22:15:29.253349 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9235 22:15:29.259937 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9236 22:15:29.262944 SPM: binary array size = 0x9dc
9237 22:15:29.266495 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9238 22:15:29.273144 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9239 22:15:29.279573 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9240 22:15:29.282794 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9241 22:15:29.289341 configure_display: Starting display init
9242 22:15:29.323426 anx7625_power_on_init: Init interface.
9243 22:15:29.326737 anx7625_disable_pd_protocol: Disabled PD feature.
9244 22:15:29.329921 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9245 22:15:29.357651 anx7625_start_dp_work: Secure OCM version=00
9246 22:15:29.361107 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9247 22:15:29.375442 sp_tx_get_edid_block: EDID Block = 1
9248 22:15:29.478660 Extracted contents:
9249 22:15:29.481352 header: 00 ff ff ff ff ff ff 00
9250 22:15:29.485298 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9251 22:15:29.488205 version: 01 04
9252 22:15:29.491594 basic params: 95 1f 11 78 0a
9253 22:15:29.495213 chroma info: 76 90 94 55 54 90 27 21 50 54
9254 22:15:29.498267 established: 00 00 00
9255 22:15:29.504895 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9256 22:15:29.508300 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9257 22:15:29.514970 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9258 22:15:29.521283 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9259 22:15:29.528040 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9260 22:15:29.531655 extensions: 00
9261 22:15:29.531737 checksum: fb
9262 22:15:29.531800
9263 22:15:29.534901 Manufacturer: IVO Model 57d Serial Number 0
9264 22:15:29.538178 Made week 0 of 2020
9265 22:15:29.538260 EDID version: 1.4
9266 22:15:29.541580 Digital display
9267 22:15:29.544741 6 bits per primary color channel
9268 22:15:29.544824 DisplayPort interface
9269 22:15:29.548243 Maximum image size: 31 cm x 17 cm
9270 22:15:29.551270 Gamma: 220%
9271 22:15:29.551359 Check DPMS levels
9272 22:15:29.554548 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9273 22:15:29.558028 First detailed timing is preferred timing
9274 22:15:29.561462 Established timings supported:
9275 22:15:29.564734 Standard timings supported:
9276 22:15:29.564817 Detailed timings
9277 22:15:29.571663 Hex of detail: 383680a07038204018303c0035ae10000019
9278 22:15:29.575102 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9279 22:15:29.581380 0780 0798 07c8 0820 hborder 0
9280 22:15:29.584575 0438 043b 0447 0458 vborder 0
9281 22:15:29.584658 -hsync -vsync
9282 22:15:29.588152 Did detailed timing
9283 22:15:29.591649 Hex of detail: 000000000000000000000000000000000000
9284 22:15:29.594781 Manufacturer-specified data, tag 0
9285 22:15:29.601236 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9286 22:15:29.601318 ASCII string: InfoVision
9287 22:15:29.608490 Hex of detail: 000000fe00523134304e574635205248200a
9288 22:15:29.608572 ASCII string: R140NWF5 RH
9289 22:15:29.611748 Checksum
9290 22:15:29.611829 Checksum: 0xfb (valid)
9291 22:15:29.618208 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9292 22:15:29.621124 DSI data_rate: 832800000 bps
9293 22:15:29.624563 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9294 22:15:29.627993 anx7625_parse_edid: pixelclock(138800).
9295 22:15:29.634841 hactive(1920), hsync(48), hfp(24), hbp(88)
9296 22:15:29.637780 vactive(1080), vsync(12), vfp(3), vbp(17)
9297 22:15:29.641012 anx7625_dsi_config: config dsi.
9298 22:15:29.647815 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9299 22:15:29.660527 anx7625_dsi_config: success to config DSI
9300 22:15:29.663416 anx7625_dp_start: MIPI phy setup OK.
9301 22:15:29.667286 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9302 22:15:29.670128 mtk_ddp_mode_set invalid vrefresh 60
9303 22:15:29.673995 main_disp_path_setup
9304 22:15:29.674076 ovl_layer_smi_id_en
9305 22:15:29.676636 ovl_layer_smi_id_en
9306 22:15:29.676716 ccorr_config
9307 22:15:29.676779 aal_config
9308 22:15:29.680078 gamma_config
9309 22:15:29.680160 postmask_config
9310 22:15:29.683778 dither_config
9311 22:15:29.686635 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9312 22:15:29.693247 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9313 22:15:29.697004 Root Device init finished in 551 msecs
9314 22:15:29.700241 CPU_CLUSTER: 0 init
9315 22:15:29.706600 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9316 22:15:29.710182 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9317 22:15:29.713557 APU_MBOX 0x190000b0 = 0x10001
9318 22:15:29.716647 APU_MBOX 0x190001b0 = 0x10001
9319 22:15:29.720212 APU_MBOX 0x190005b0 = 0x10001
9320 22:15:29.723074 APU_MBOX 0x190006b0 = 0x10001
9321 22:15:29.726538 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9322 22:15:29.739198 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9323 22:15:29.751561 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9324 22:15:29.758281 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9325 22:15:29.770058 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9326 22:15:29.778938 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9327 22:15:29.782979 CPU_CLUSTER: 0 init finished in 81 msecs
9328 22:15:29.785490 Devices initialized
9329 22:15:29.789092 Show all devs... After init.
9330 22:15:29.789172 Root Device: enabled 1
9331 22:15:29.792343 CPU_CLUSTER: 0: enabled 1
9332 22:15:29.795880 CPU: 00: enabled 1
9333 22:15:29.799076 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9334 22:15:29.802477 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9335 22:15:29.806007 ELOG: NV offset 0x57f000 size 0x1000
9336 22:15:29.812676 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9337 22:15:29.819052 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9338 22:15:29.822285 ELOG: Event(17) added with size 13 at 2023-06-05 22:15:22 UTC
9339 22:15:29.825908 out: cmd=0x121: 03 db 21 01 00 00 00 00
9340 22:15:29.829393 in-header: 03 0d 00 00 2c 00 00 00
9341 22:15:29.843112 in-data: 52 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9342 22:15:29.849717 ELOG: Event(A1) added with size 10 at 2023-06-05 22:15:22 UTC
9343 22:15:29.855963 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9344 22:15:29.862258 ELOG: Event(A0) added with size 9 at 2023-06-05 22:15:22 UTC
9345 22:15:29.865954 elog_add_boot_reason: Logged dev mode boot
9346 22:15:29.869055 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9347 22:15:29.872582 Finalize devices...
9348 22:15:29.872665 Devices finalized
9349 22:15:29.879295 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9350 22:15:29.882525 Writing coreboot table at 0xffe64000
9351 22:15:29.885563 0. 000000000010a000-0000000000113fff: RAMSTAGE
9352 22:15:29.889458 1. 0000000040000000-00000000400fffff: RAM
9353 22:15:29.895868 2. 0000000040100000-000000004032afff: RAMSTAGE
9354 22:15:29.898929 3. 000000004032b000-00000000545fffff: RAM
9355 22:15:29.902762 4. 0000000054600000-000000005465ffff: BL31
9356 22:15:29.905469 5. 0000000054660000-00000000ffe63fff: RAM
9357 22:15:29.912642 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9358 22:15:29.915658 7. 0000000100000000-000000023fffffff: RAM
9359 22:15:29.915739 Passing 5 GPIOs to payload:
9360 22:15:29.922503 NAME | PORT | POLARITY | VALUE
9361 22:15:29.925544 EC in RW | 0x000000aa | low | undefined
9362 22:15:29.932042 EC interrupt | 0x00000005 | low | undefined
9363 22:15:29.935644 TPM interrupt | 0x000000ab | high | undefined
9364 22:15:29.939220 SD card detect | 0x00000011 | high | undefined
9365 22:15:29.945570 speaker enable | 0x00000093 | high | undefined
9366 22:15:29.949063 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9367 22:15:29.952144 in-header: 03 f9 00 00 02 00 00 00
9368 22:15:29.952226 in-data: 02 00
9369 22:15:29.955577 ADC[4]: Raw value=904726 ID=7
9370 22:15:29.959006 ADC[3]: Raw value=213810 ID=1
9371 22:15:29.959087 RAM Code: 0x71
9372 22:15:29.962201 ADC[6]: Raw value=75701 ID=0
9373 22:15:29.965463 ADC[5]: Raw value=213072 ID=1
9374 22:15:29.965545 SKU Code: 0x1
9375 22:15:29.972271 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 4e98
9376 22:15:29.975708 coreboot table: 964 bytes.
9377 22:15:29.979206 IMD ROOT 0. 0xfffff000 0x00001000
9378 22:15:29.982365 IMD SMALL 1. 0xffffe000 0x00001000
9379 22:15:29.985696 RO MCACHE 2. 0xffffc000 0x00001104
9380 22:15:29.989266 CONSOLE 3. 0xfff7c000 0x00080000
9381 22:15:29.992113 FMAP 4. 0xfff7b000 0x00000452
9382 22:15:29.995848 TIME STAMP 5. 0xfff7a000 0x00000910
9383 22:15:29.999334 VBOOT WORK 6. 0xfff66000 0x00014000
9384 22:15:30.002248 RAMOOPS 7. 0xffe66000 0x00100000
9385 22:15:30.005928 COREBOOT 8. 0xffe64000 0x00002000
9386 22:15:30.006011 IMD small region:
9387 22:15:30.008598 IMD ROOT 0. 0xffffec00 0x00000400
9388 22:15:30.012182 VPD 1. 0xffffeba0 0x0000004c
9389 22:15:30.015631 MMC STATUS 2. 0xffffeb80 0x00000004
9390 22:15:30.023031 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9391 22:15:30.023113 Probing TPM: done!
9392 22:15:30.029229 Connected to device vid:did:rid of 1ae0:0028:00
9393 22:15:30.035961 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.153/cr50_v3.94_pp.113-620c9b9523
9394 22:15:30.039239 Initialized TPM device CR50 revision 0
9395 22:15:30.043459 Checking cr50 for pending updates
9396 22:15:30.048618 Reading cr50 TPM mode
9397 22:15:30.057752 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9398 22:15:30.064419 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9399 22:15:30.104463 read SPI 0x3990ec 0x4f1b0: 34849 us, 9297 KB/s, 74.376 Mbps
9400 22:15:30.107494 Checking segment from ROM address 0x40100000
9401 22:15:30.110963 Checking segment from ROM address 0x4010001c
9402 22:15:30.117885 Loading segment from ROM address 0x40100000
9403 22:15:30.117971 code (compression=0)
9404 22:15:30.124274 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9405 22:15:30.134415 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9406 22:15:30.134505 it's not compressed!
9407 22:15:30.141044 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9408 22:15:30.144386 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9409 22:15:30.164729 Loading segment from ROM address 0x4010001c
9410 22:15:30.164813 Entry Point 0x80000000
9411 22:15:30.168193 Loaded segments
9412 22:15:30.171249 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9413 22:15:30.177960 Jumping to boot code at 0x80000000(0xffe64000)
9414 22:15:30.184517 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9415 22:15:30.191122 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9416 22:15:30.199247 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9417 22:15:30.202254 Checking segment from ROM address 0x40100000
9418 22:15:30.206022 Checking segment from ROM address 0x4010001c
9419 22:15:30.212624 Loading segment from ROM address 0x40100000
9420 22:15:30.212707 code (compression=1)
9421 22:15:30.219307 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9422 22:15:30.228926 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9423 22:15:30.229009 using LZMA
9424 22:15:30.237427 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9425 22:15:30.244188 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9426 22:15:30.247690 Loading segment from ROM address 0x4010001c
9427 22:15:30.247774 Entry Point 0x54601000
9428 22:15:30.250802 Loaded segments
9429 22:15:30.253843 NOTICE: MT8192 bl31_setup
9430 22:15:30.261500 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9431 22:15:30.264356 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9432 22:15:30.267788 WARNING: region 0:
9433 22:15:30.271456 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9434 22:15:30.271539 WARNING: region 1:
9435 22:15:30.278149 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9436 22:15:30.278232 WARNING: region 2:
9437 22:15:30.284951 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9438 22:15:30.287741 WARNING: region 3:
9439 22:15:30.291691 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9440 22:15:30.294711 WARNING: region 4:
9441 22:15:30.297951 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9442 22:15:30.301317 WARNING: region 5:
9443 22:15:30.304715 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9444 22:15:30.307901 WARNING: region 6:
9445 22:15:30.311205 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9446 22:15:30.311315 WARNING: region 7:
9447 22:15:30.318333 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9448 22:15:30.324660 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9449 22:15:30.328405 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9450 22:15:30.331211 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9451 22:15:30.334766 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9452 22:15:30.341537 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9453 22:15:30.345061 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9454 22:15:30.352184 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9455 22:15:30.355047 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9456 22:15:30.358308 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9457 22:15:30.365270 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9458 22:15:30.368345 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9459 22:15:30.371896 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9460 22:15:30.378860 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9461 22:15:30.381763 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9462 22:15:30.385328 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9463 22:15:30.392121 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9464 22:15:30.395256 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9465 22:15:30.402015 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9466 22:15:30.405234 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9467 22:15:30.408394 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9468 22:15:30.415292 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9469 22:15:30.418791 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9470 22:15:30.425399 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9471 22:15:30.428744 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9472 22:15:30.432013 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9473 22:15:30.438759 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9474 22:15:30.441726 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9475 22:15:30.445416 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9476 22:15:30.452036 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9477 22:15:30.454999 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9478 22:15:30.462278 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9479 22:15:30.465064 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9480 22:15:30.468724 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9481 22:15:30.475252 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9482 22:15:30.478377 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9483 22:15:30.482167 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9484 22:15:30.485680 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9485 22:15:30.488468 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9486 22:15:30.495534 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9487 22:15:30.498478 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9488 22:15:30.502044 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9489 22:15:30.505377 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9490 22:15:30.511825 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9491 22:15:30.515360 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9492 22:15:30.518728 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9493 22:15:30.522249 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9494 22:15:30.528797 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9495 22:15:30.532161 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9496 22:15:30.535603 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9497 22:15:30.542025 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9498 22:15:30.545342 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9499 22:15:30.552186 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9500 22:15:30.555251 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9501 22:15:30.562329 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9502 22:15:30.565335 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9503 22:15:30.568707 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9504 22:15:30.575313 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9505 22:15:30.578614 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9506 22:15:30.585696 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9507 22:15:30.589238 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9508 22:15:30.595654 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9509 22:15:30.598780 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9510 22:15:30.602220 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9511 22:15:30.608579 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9512 22:15:30.612105 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9513 22:15:30.619249 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9514 22:15:30.621958 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9515 22:15:30.629173 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9516 22:15:30.632338 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9517 22:15:30.635571 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9518 22:15:30.642291 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9519 22:15:30.645438 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9520 22:15:30.652001 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9521 22:15:30.655931 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9522 22:15:30.659517 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9523 22:15:30.665932 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9524 22:15:30.669388 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9525 22:15:30.675962 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9526 22:15:30.678947 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9527 22:15:30.685837 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9528 22:15:30.689096 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9529 22:15:30.695874 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9530 22:15:30.699048 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9531 22:15:30.702655 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9532 22:15:30.708948 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9533 22:15:30.712473 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9534 22:15:30.718956 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9535 22:15:30.722460 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9536 22:15:30.725736 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9537 22:15:30.732403 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9538 22:15:30.735687 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9539 22:15:30.742488 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9540 22:15:30.745885 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9541 22:15:30.752492 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9542 22:15:30.756014 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9543 22:15:30.762631 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9544 22:15:30.765788 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9545 22:15:30.769275 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9546 22:15:30.772417 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9547 22:15:30.775977 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9548 22:15:30.782393 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9549 22:15:30.786043 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9550 22:15:30.792690 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9551 22:15:30.795699 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9552 22:15:30.799591 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9553 22:15:30.805819 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9554 22:15:30.809278 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9555 22:15:30.815850 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9556 22:15:30.819052 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9557 22:15:30.822392 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9558 22:15:30.828950 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9559 22:15:30.832343 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9560 22:15:30.839204 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9561 22:15:30.842345 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9562 22:15:30.845802 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9563 22:15:30.852399 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9564 22:15:30.855934 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9565 22:15:30.859316 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9566 22:15:30.865704 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9567 22:15:30.869220 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9568 22:15:30.872759 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9569 22:15:30.876054 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9570 22:15:30.879631 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9571 22:15:30.885990 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9572 22:15:30.889270 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9573 22:15:30.896214 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9574 22:15:30.899206 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9575 22:15:30.902775 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9576 22:15:30.909424 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9577 22:15:30.912519 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9578 22:15:30.915947 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9579 22:15:30.922906 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9580 22:15:30.926196 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9581 22:15:30.933053 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9582 22:15:30.936046 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9583 22:15:30.939541 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9584 22:15:30.946099 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9585 22:15:30.949639 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9586 22:15:30.952974 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9587 22:15:30.959557 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9588 22:15:30.962701 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9589 22:15:30.969368 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9590 22:15:30.972783 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9591 22:15:30.976154 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9592 22:15:30.982888 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9593 22:15:30.986476 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9594 22:15:30.993186 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9595 22:15:30.996147 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9596 22:15:30.999492 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9597 22:15:31.006481 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9598 22:15:31.009717 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9599 22:15:31.013120 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9600 22:15:31.019812 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9601 22:15:31.023098 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9602 22:15:31.030027 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9603 22:15:31.033217 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9604 22:15:31.036719 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9605 22:15:31.043474 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9606 22:15:31.046867 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9607 22:15:31.049848 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9608 22:15:31.056525 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9609 22:15:31.059869 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9610 22:15:31.066781 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9611 22:15:31.069738 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9612 22:15:31.073397 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9613 22:15:31.079957 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9614 22:15:31.083259 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9615 22:15:31.090040 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9616 22:15:31.093649 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9617 22:15:31.096775 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9618 22:15:31.102954 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9619 22:15:31.106276 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9620 22:15:31.109925 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9621 22:15:31.116670 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9622 22:15:31.119708 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9623 22:15:31.126299 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9624 22:15:31.129870 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9625 22:15:31.133212 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9626 22:15:31.139621 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9627 22:15:31.142945 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9628 22:15:31.150353 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9629 22:15:31.153313 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9630 22:15:31.156519 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9631 22:15:31.162987 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9632 22:15:31.166274 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9633 22:15:31.173094 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9634 22:15:31.176699 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9635 22:15:31.180030 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9636 22:15:31.186706 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9637 22:15:31.189872 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9638 22:15:31.196644 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9639 22:15:31.199739 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9640 22:15:31.202843 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9641 22:15:31.209595 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9642 22:15:31.213277 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9643 22:15:31.219637 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9644 22:15:31.223099 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9645 22:15:31.226276 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9646 22:15:31.233005 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9647 22:15:31.236441 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9648 22:15:31.242654 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9649 22:15:31.246228 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9650 22:15:31.252646 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9651 22:15:31.256160 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9652 22:15:31.259291 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9653 22:15:31.265907 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9654 22:15:31.269276 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9655 22:15:31.275994 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9656 22:15:31.279322 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9657 22:15:31.282453 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9658 22:15:31.289352 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9659 22:15:31.293153 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9660 22:15:31.299182 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9661 22:15:31.302548 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9662 22:15:31.306082 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9663 22:15:31.312774 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9664 22:15:31.316519 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9665 22:15:31.322331 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9666 22:15:31.325697 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9667 22:15:31.332325 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9668 22:15:31.336003 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9669 22:15:31.339123 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9670 22:15:31.345648 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9671 22:15:31.349323 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9672 22:15:31.355726 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9673 22:15:31.359244 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9674 22:15:31.365917 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9675 22:15:31.368802 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9676 22:15:31.372402 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9677 22:15:31.378853 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9678 22:15:31.382257 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9679 22:15:31.385735 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9680 22:15:31.389209 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9681 22:15:31.392478 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9682 22:15:31.398789 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9683 22:15:31.402417 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9684 22:15:31.409392 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9685 22:15:31.412009 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9686 22:15:31.415604 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9687 22:15:31.422203 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9688 22:15:31.425514 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9689 22:15:31.429167 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9690 22:15:31.435295 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9691 22:15:31.438706 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9692 22:15:31.442433 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9693 22:15:31.448738 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9694 22:15:31.452044 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9695 22:15:31.458308 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9696 22:15:31.461994 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9697 22:15:31.465128 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9698 22:15:31.471719 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9699 22:15:31.475271 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9700 22:15:31.478709 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9701 22:15:31.485350 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9702 22:15:31.488782 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9703 22:15:31.492055 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9704 22:15:31.498791 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9705 22:15:31.502643 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9706 22:15:31.505568 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9707 22:15:31.512472 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9708 22:15:31.515317 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9709 22:15:31.522240 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9710 22:15:31.525090 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9711 22:15:31.528839 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9712 22:15:31.535304 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9713 22:15:31.538725 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9714 22:15:31.545338 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9715 22:15:31.548584 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9716 22:15:31.551874 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9717 22:15:31.555282 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9718 22:15:31.561641 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9719 22:15:31.565274 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9720 22:15:31.568265 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9721 22:15:31.571864 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9722 22:15:31.578573 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9723 22:15:31.581819 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9724 22:15:31.585453 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9725 22:15:31.588221 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9726 22:15:31.591448 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9727 22:15:31.598705 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9728 22:15:31.602002 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9729 22:15:31.605191 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9730 22:15:31.611517 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9731 22:15:31.615021 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9732 22:15:31.621917 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9733 22:15:31.624692 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9734 22:15:31.628494 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9735 22:15:31.635313 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9736 22:15:31.638045 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9737 22:15:31.644933 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9738 22:15:31.648247 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9739 22:15:31.651631 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9740 22:15:31.657972 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9741 22:15:31.661622 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9742 22:15:31.668109 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9743 22:15:31.671089 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9744 22:15:31.678069 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9745 22:15:31.681114 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9746 22:15:31.684843 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9747 22:15:31.691425 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9748 22:15:31.694768 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9749 22:15:31.701457 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9750 22:15:31.704674 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9751 22:15:31.708098 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9752 22:15:31.715014 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9753 22:15:31.717793 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9754 22:15:31.724413 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9755 22:15:31.727966 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9756 22:15:31.731299 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9757 22:15:31.737663 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9758 22:15:31.741206 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9759 22:15:31.748285 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9760 22:15:31.751110 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9761 22:15:31.754947 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9762 22:15:31.761497 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9763 22:15:31.764493 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9764 22:15:31.770953 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9765 22:15:31.774567 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9766 22:15:31.777530 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9767 22:15:31.784131 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9768 22:15:31.787565 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9769 22:15:31.794480 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9770 22:15:31.797924 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9771 22:15:31.801334 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9772 22:15:31.807604 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9773 22:15:31.811445 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9774 22:15:31.817458 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9775 22:15:31.820973 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9776 22:15:31.827851 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9777 22:15:31.830975 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9778 22:15:31.834578 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9779 22:15:31.840923 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9780 22:15:31.844480 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9781 22:15:31.850926 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9782 22:15:31.854450 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9783 22:15:31.857523 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9784 22:15:31.864116 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9785 22:15:31.867890 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9786 22:15:31.871028 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9787 22:15:31.877985 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9788 22:15:31.880912 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9789 22:15:31.887570 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9790 22:15:31.891248 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9791 22:15:31.898107 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9792 22:15:31.900836 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9793 22:15:31.904402 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9794 22:15:31.911077 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9795 22:15:31.914455 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9796 22:15:31.920702 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9797 22:15:31.924560 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9798 22:15:31.927662 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9799 22:15:31.934228 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9800 22:15:31.937329 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9801 22:15:31.944365 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9802 22:15:31.947876 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9803 22:15:31.950643 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9804 22:15:31.957668 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9805 22:15:31.960648 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9806 22:15:31.967290 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9807 22:15:31.970932 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9808 22:15:31.977238 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9809 22:15:31.980580 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9810 22:15:31.984216 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9811 22:15:31.990778 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9812 22:15:31.993789 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9813 22:15:32.000614 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9814 22:15:32.004196 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9815 22:15:32.010685 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9816 22:15:32.014102 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9817 22:15:32.017460 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9818 22:15:32.023618 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9819 22:15:32.027484 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9820 22:15:32.033856 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9821 22:15:32.037126 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9822 22:15:32.044064 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9823 22:15:32.047462 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9824 22:15:32.053745 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9825 22:15:32.057331 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9826 22:15:32.060121 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9827 22:15:32.067248 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9828 22:15:32.070660 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9829 22:15:32.077310 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9830 22:15:32.080422 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9831 22:15:32.086879 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9832 22:15:32.090514 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9833 22:15:32.093661 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9834 22:15:32.100212 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9835 22:15:32.103844 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9836 22:15:32.110482 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9837 22:15:32.113937 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9838 22:15:32.120154 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9839 22:15:32.123665 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9840 22:15:32.130640 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9841 22:15:32.133444 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9842 22:15:32.137120 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9843 22:15:32.144234 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9844 22:15:32.146771 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9845 22:15:32.153727 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9846 22:15:32.156761 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9847 22:15:32.163949 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9848 22:15:32.167170 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9849 22:15:32.170068 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9850 22:15:32.176929 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9851 22:15:32.179920 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9852 22:15:32.187216 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9853 22:15:32.190591 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9854 22:15:32.196868 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9855 22:15:32.199950 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9856 22:15:32.203442 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9857 22:15:32.210350 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9858 22:15:32.213197 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9859 22:15:32.220339 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9860 22:15:32.223421 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9861 22:15:32.229931 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9862 22:15:32.233371 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9863 22:15:32.239894 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9864 22:15:32.243444 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9865 22:15:32.250081 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9866 22:15:32.253161 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9867 22:15:32.260105 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9868 22:15:32.262989 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9869 22:15:32.269584 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9870 22:15:32.273351 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9871 22:15:32.279703 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9872 22:15:32.283429 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9873 22:15:32.290316 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9874 22:15:32.293206 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9875 22:15:32.299802 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9876 22:15:32.303283 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9877 22:15:32.309650 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9878 22:15:32.312876 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9879 22:15:32.319579 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9880 22:15:32.323235 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9881 22:15:32.329534 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9882 22:15:32.332779 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9883 22:15:32.335990 INFO: [APUAPC] vio 0
9884 22:15:32.339315 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9885 22:15:32.345973 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9886 22:15:32.349682 INFO: [APUAPC] D0_APC_0: 0x400510
9887 22:15:32.349767 INFO: [APUAPC] D0_APC_1: 0x0
9888 22:15:32.352655 INFO: [APUAPC] D0_APC_2: 0x1540
9889 22:15:32.355991 INFO: [APUAPC] D0_APC_3: 0x0
9890 22:15:32.359263 INFO: [APUAPC] D1_APC_0: 0xffffffff
9891 22:15:32.363104 INFO: [APUAPC] D1_APC_1: 0xffffffff
9892 22:15:32.366610 INFO: [APUAPC] D1_APC_2: 0x3fffff
9893 22:15:32.369477 INFO: [APUAPC] D1_APC_3: 0x0
9894 22:15:32.372911 INFO: [APUAPC] D2_APC_0: 0xffffffff
9895 22:15:32.376227 INFO: [APUAPC] D2_APC_1: 0xffffffff
9896 22:15:32.379289 INFO: [APUAPC] D2_APC_2: 0x3fffff
9897 22:15:32.382915 INFO: [APUAPC] D2_APC_3: 0x0
9898 22:15:32.386179 INFO: [APUAPC] D3_APC_0: 0xffffffff
9899 22:15:32.389327 INFO: [APUAPC] D3_APC_1: 0xffffffff
9900 22:15:32.392545 INFO: [APUAPC] D3_APC_2: 0x3fffff
9901 22:15:32.396134 INFO: [APUAPC] D3_APC_3: 0x0
9902 22:15:32.399644 INFO: [APUAPC] D4_APC_0: 0xffffffff
9903 22:15:32.402746 INFO: [APUAPC] D4_APC_1: 0xffffffff
9904 22:15:32.406195 INFO: [APUAPC] D4_APC_2: 0x3fffff
9905 22:15:32.409253 INFO: [APUAPC] D4_APC_3: 0x0
9906 22:15:32.412723 INFO: [APUAPC] D5_APC_0: 0xffffffff
9907 22:15:32.416414 INFO: [APUAPC] D5_APC_1: 0xffffffff
9908 22:15:32.419573 INFO: [APUAPC] D5_APC_2: 0x3fffff
9909 22:15:32.422492 INFO: [APUAPC] D5_APC_3: 0x0
9910 22:15:32.426270 INFO: [APUAPC] D6_APC_0: 0xffffffff
9911 22:15:32.429437 INFO: [APUAPC] D6_APC_1: 0xffffffff
9912 22:15:32.432525 INFO: [APUAPC] D6_APC_2: 0x3fffff
9913 22:15:32.436312 INFO: [APUAPC] D6_APC_3: 0x0
9914 22:15:32.439533 INFO: [APUAPC] D7_APC_0: 0xffffffff
9915 22:15:32.442856 INFO: [APUAPC] D7_APC_1: 0xffffffff
9916 22:15:32.446218 INFO: [APUAPC] D7_APC_2: 0x3fffff
9917 22:15:32.449416 INFO: [APUAPC] D7_APC_3: 0x0
9918 22:15:32.452964 INFO: [APUAPC] D8_APC_0: 0xffffffff
9919 22:15:32.456020 INFO: [APUAPC] D8_APC_1: 0xffffffff
9920 22:15:32.458947 INFO: [APUAPC] D8_APC_2: 0x3fffff
9921 22:15:32.459031 INFO: [APUAPC] D8_APC_3: 0x0
9922 22:15:32.462519 INFO: [APUAPC] D9_APC_0: 0xffffffff
9923 22:15:32.466317 INFO: [APUAPC] D9_APC_1: 0xffffffff
9924 22:15:32.469177 INFO: [APUAPC] D9_APC_2: 0x3fffff
9925 22:15:32.472718 INFO: [APUAPC] D9_APC_3: 0x0
9926 22:15:32.476047 INFO: [APUAPC] D10_APC_0: 0xffffffff
9927 22:15:32.479073 INFO: [APUAPC] D10_APC_1: 0xffffffff
9928 22:15:32.482537 INFO: [APUAPC] D10_APC_2: 0x3fffff
9929 22:15:32.486187 INFO: [APUAPC] D10_APC_3: 0x0
9930 22:15:32.489517 INFO: [APUAPC] D11_APC_0: 0xffffffff
9931 22:15:32.492513 INFO: [APUAPC] D11_APC_1: 0xffffffff
9932 22:15:32.495837 INFO: [APUAPC] D11_APC_2: 0x3fffff
9933 22:15:32.499392 INFO: [APUAPC] D11_APC_3: 0x0
9934 22:15:32.502629 INFO: [APUAPC] D12_APC_0: 0xffffffff
9935 22:15:32.505794 INFO: [APUAPC] D12_APC_1: 0xffffffff
9936 22:15:32.509190 INFO: [APUAPC] D12_APC_2: 0x3fffff
9937 22:15:32.512871 INFO: [APUAPC] D12_APC_3: 0x0
9938 22:15:32.516129 INFO: [APUAPC] D13_APC_0: 0xffffffff
9939 22:15:32.519057 INFO: [APUAPC] D13_APC_1: 0xffffffff
9940 22:15:32.522847 INFO: [APUAPC] D13_APC_2: 0x3fffff
9941 22:15:32.525893 INFO: [APUAPC] D13_APC_3: 0x0
9942 22:15:32.529447 INFO: [APUAPC] D14_APC_0: 0xffffffff
9943 22:15:32.533079 INFO: [APUAPC] D14_APC_1: 0xffffffff
9944 22:15:32.536030 INFO: [APUAPC] D14_APC_2: 0x3fffff
9945 22:15:32.539669 INFO: [APUAPC] D14_APC_3: 0x0
9946 22:15:32.542559 INFO: [APUAPC] D15_APC_0: 0xffffffff
9947 22:15:32.545899 INFO: [APUAPC] D15_APC_1: 0xffffffff
9948 22:15:32.549312 INFO: [APUAPC] D15_APC_2: 0x3fffff
9949 22:15:32.552562 INFO: [APUAPC] D15_APC_3: 0x0
9950 22:15:32.555995 INFO: [APUAPC] APC_CON: 0x4
9951 22:15:32.559379 INFO: [NOCDAPC] D0_APC_0: 0x0
9952 22:15:32.562757 INFO: [NOCDAPC] D0_APC_1: 0x0
9953 22:15:32.566006 INFO: [NOCDAPC] D1_APC_0: 0x0
9954 22:15:32.569485 INFO: [NOCDAPC] D1_APC_1: 0xfff
9955 22:15:32.572735 INFO: [NOCDAPC] D2_APC_0: 0x0
9956 22:15:32.575748 INFO: [NOCDAPC] D2_APC_1: 0xfff
9957 22:15:32.575829 INFO: [NOCDAPC] D3_APC_0: 0x0
9958 22:15:32.578910 INFO: [NOCDAPC] D3_APC_1: 0xfff
9959 22:15:32.582698 INFO: [NOCDAPC] D4_APC_0: 0x0
9960 22:15:32.585831 INFO: [NOCDAPC] D4_APC_1: 0xfff
9961 22:15:32.589247 INFO: [NOCDAPC] D5_APC_0: 0x0
9962 22:15:32.592399 INFO: [NOCDAPC] D5_APC_1: 0xfff
9963 22:15:32.595973 INFO: [NOCDAPC] D6_APC_0: 0x0
9964 22:15:32.599431 INFO: [NOCDAPC] D6_APC_1: 0xfff
9965 22:15:32.602440 INFO: [NOCDAPC] D7_APC_0: 0x0
9966 22:15:32.606247 INFO: [NOCDAPC] D7_APC_1: 0xfff
9967 22:15:32.609022 INFO: [NOCDAPC] D8_APC_0: 0x0
9968 22:15:32.609104 INFO: [NOCDAPC] D8_APC_1: 0xfff
9969 22:15:32.613071 INFO: [NOCDAPC] D9_APC_0: 0x0
9970 22:15:32.615770 INFO: [NOCDAPC] D9_APC_1: 0xfff
9971 22:15:32.619622 INFO: [NOCDAPC] D10_APC_0: 0x0
9972 22:15:32.622351 INFO: [NOCDAPC] D10_APC_1: 0xfff
9973 22:15:32.625742 INFO: [NOCDAPC] D11_APC_0: 0x0
9974 22:15:32.629407 INFO: [NOCDAPC] D11_APC_1: 0xfff
9975 22:15:32.632552 INFO: [NOCDAPC] D12_APC_0: 0x0
9976 22:15:32.636136 INFO: [NOCDAPC] D12_APC_1: 0xfff
9977 22:15:32.639052 INFO: [NOCDAPC] D13_APC_0: 0x0
9978 22:15:32.642628 INFO: [NOCDAPC] D13_APC_1: 0xfff
9979 22:15:32.646101 INFO: [NOCDAPC] D14_APC_0: 0x0
9980 22:15:32.649073 INFO: [NOCDAPC] D14_APC_1: 0xfff
9981 22:15:32.652391 INFO: [NOCDAPC] D15_APC_0: 0x0
9982 22:15:32.652473 INFO: [NOCDAPC] D15_APC_1: 0xfff
9983 22:15:32.655823 INFO: [NOCDAPC] APC_CON: 0x4
9984 22:15:32.659130 INFO: [APUAPC] set_apusys_apc done
9985 22:15:32.662354 INFO: [DEVAPC] devapc_init done
9986 22:15:32.669610 INFO: GICv3 without legacy support detected.
9987 22:15:32.672200 INFO: ARM GICv3 driver initialized in EL3
9988 22:15:32.675467 INFO: Maximum SPI INTID supported: 639
9989 22:15:32.679025 INFO: BL31: Initializing runtime services
9990 22:15:32.685727 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
9991 22:15:32.688862 INFO: SPM: enable CPC mode
9992 22:15:32.692626 INFO: mcdi ready for mcusys-off-idle and system suspend
9993 22:15:32.699222 INFO: BL31: Preparing for EL3 exit to normal world
9994 22:15:32.702284 INFO: Entry point address = 0x80000000
9995 22:15:32.702365 INFO: SPSR = 0x8
9996 22:15:32.708842
9997 22:15:32.708922
9998 22:15:32.708986
9999 22:15:32.712349 Starting depthcharge on Spherion...
10000 22:15:32.712430
10001 22:15:32.712494 Wipe memory regions:
10002 22:15:32.712553
10003 22:15:32.713141 end: 2.2.3 depthcharge-start (duration 00:00:29) [common]
10004 22:15:32.713237 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10005 22:15:32.713318 Setting prompt string to ['asurada:']
10006 22:15:32.713395 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10007 22:15:32.715723 [0x00000040000000, 0x00000054600000)
10008 22:15:32.837808
10009 22:15:32.837929 [0x00000054660000, 0x00000080000000)
10010 22:15:33.098793
10011 22:15:33.098933 [0x000000821a7280, 0x000000ffe64000)
10012 22:15:33.843409
10013 22:15:33.843549 [0x00000100000000, 0x00000240000000)
10014 22:15:35.733867
10015 22:15:35.736595 Initializing XHCI USB controller at 0x11200000.
10016 22:15:36.775371
10017 22:15:36.778692 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10018 22:15:36.779160
10019 22:15:36.779584
10020 22:15:36.779935
10021 22:15:36.780728 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10023 22:15:36.881971 asurada: tftpboot 192.168.201.1 10597240/tftp-deploy-g8u9ngxh/kernel/image.itb 10597240/tftp-deploy-g8u9ngxh/kernel/cmdline
10024 22:15:36.882635 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10025 22:15:36.883168 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10026 22:15:36.887821 tftpboot 192.168.201.1 10597240/tftp-deploy-g8u9ngxh/kernel/image.itp-deploy-g8u9ngxh/kernel/cmdline
10027 22:15:36.888252
10028 22:15:36.888731 Waiting for link
10029 22:15:37.045626
10030 22:15:37.046177 R8152: Initializing
10031 22:15:37.046546
10032 22:15:37.049076 Version 9 (ocp_data = 6010)
10033 22:15:37.049545
10034 22:15:37.052680 R8152: Done initializing
10035 22:15:37.053145
10036 22:15:37.053512 Adding net device
10037 22:15:38.997215
10038 22:15:38.998125 done.
10039 22:15:38.998805
10040 22:15:38.999453 MAC: 00:e0:4c:78:7a:aa
10041 22:15:39.000027
10042 22:15:39.000864 Sending DHCP discover... done.
10043 22:15:39.001249
10044 22:15:39.003410 Waiting for reply... done.
10045 22:15:39.003919
10046 22:15:39.007037 Sending DHCP request... done.
10047 22:15:39.007651
10048 22:15:39.008032 Waiting for reply... done.
10049 22:15:39.008381
10050 22:15:39.010628 My ip is 192.168.201.12
10051 22:15:39.011100
10052 22:15:39.013510 The DHCP server ip is 192.168.201.1
10053 22:15:39.013982
10054 22:15:39.016833 TFTP server IP predefined by user: 192.168.201.1
10055 22:15:39.017306
10056 22:15:39.023997 Bootfile predefined by user: 10597240/tftp-deploy-g8u9ngxh/kernel/image.itb
10057 22:15:39.024602
10058 22:15:39.027512 Sending tftp read request... done.
10059 22:15:39.028104
10060 22:15:39.035494 Waiting for the transfer...
10061 22:15:39.036029
10062 22:15:39.363340 00000000 ################################################################
10063 22:15:39.363496
10064 22:15:39.659266 00080000 ################################################################
10065 22:15:39.659442
10066 22:15:39.951654 00100000 ################################################################
10067 22:15:39.951782
10068 22:15:40.213127 00180000 ################################################################
10069 22:15:40.213261
10070 22:15:40.477004 00200000 ################################################################
10071 22:15:40.477141
10072 22:15:40.743982 00280000 ################################################################
10073 22:15:40.744117
10074 22:15:41.024975 00300000 ################################################################
10075 22:15:41.025118
10076 22:15:41.313316 00380000 ################################################################
10077 22:15:41.313464
10078 22:15:41.578153 00400000 ################################################################
10079 22:15:41.578287
10080 22:15:41.848022 00480000 ################################################################
10081 22:15:41.848164
10082 22:15:42.126931 00500000 ################################################################
10083 22:15:42.127074
10084 22:15:42.380396 00580000 ################################################################
10085 22:15:42.380528
10086 22:15:42.637142 00600000 ################################################################
10087 22:15:42.637287
10088 22:15:42.888172 00680000 ################################################################
10089 22:15:42.888312
10090 22:15:43.142403 00700000 ################################################################
10091 22:15:43.142545
10092 22:15:43.417214 00780000 ################################################################
10093 22:15:43.417367
10094 22:15:43.690134 00800000 ################################################################
10095 22:15:43.690266
10096 22:15:43.953566 00880000 ################################################################
10097 22:15:43.953697
10098 22:15:44.222931 00900000 ################################################################
10099 22:15:44.223065
10100 22:15:44.489832 00980000 ################################################################
10101 22:15:44.489988
10102 22:15:44.755240 00a00000 ################################################################
10103 22:15:44.755396
10104 22:15:45.013460 00a80000 ################################################################
10105 22:15:45.013593
10106 22:15:45.275722 00b00000 ################################################################
10107 22:15:45.275859
10108 22:15:45.530765 00b80000 ################################################################
10109 22:15:45.530924
10110 22:15:45.840978 00c00000 ################################################################
10111 22:15:45.841140
10112 22:15:46.188468 00c80000 ################################################################
10113 22:15:46.188651
10114 22:15:46.527640 00d00000 ################################################################
10115 22:15:46.527810
10116 22:15:46.839671 00d80000 ################################################################
10117 22:15:46.839806
10118 22:15:47.154138 00e00000 ################################################################
10119 22:15:47.154286
10120 22:15:47.418856 00e80000 ################################################################
10121 22:15:47.419007
10122 22:15:47.678596 00f00000 ################################################################
10123 22:15:47.678729
10124 22:15:47.949263 00f80000 ################################################################
10125 22:15:47.949413
10126 22:15:48.211240 01000000 ################################################################
10127 22:15:48.211440
10128 22:15:48.478652 01080000 ################################################################
10129 22:15:48.478787
10130 22:15:48.748642 01100000 ################################################################
10131 22:15:48.748776
10132 22:15:49.013561 01180000 ################################################################
10133 22:15:49.013696
10134 22:15:49.281468 01200000 ################################################################
10135 22:15:49.281614
10136 22:15:49.551295 01280000 ################################################################
10137 22:15:49.551447
10138 22:15:49.810875 01300000 ################################################################
10139 22:15:49.811011
10140 22:15:50.080424 01380000 ################################################################
10141 22:15:50.080563
10142 22:15:50.363254 01400000 ################################################################
10143 22:15:50.363439
10144 22:15:50.634335 01480000 ################################################################
10145 22:15:50.634473
10146 22:15:50.909501 01500000 ################################################################
10147 22:15:50.909641
10148 22:15:51.184072 01580000 ################################################################
10149 22:15:51.184209
10150 22:15:51.451962 01600000 ################################################################
10151 22:15:51.452118
10152 22:15:51.741162 01680000 ################################################################
10153 22:15:51.741324
10154 22:15:52.018831 01700000 ################################################################
10155 22:15:52.018990
10156 22:15:52.314526 01780000 ################################################################
10157 22:15:52.314665
10158 22:15:52.579475 01800000 ################################################################
10159 22:15:52.579636
10160 22:15:52.853786 01880000 ################################################################
10161 22:15:52.853923
10162 22:15:53.141994 01900000 ################################################################
10163 22:15:53.142159
10164 22:15:53.402102 01980000 ################################################################
10165 22:15:53.402261
10166 22:15:53.657455 01a00000 ################################################################
10167 22:15:53.657591
10168 22:15:53.941454 01a80000 ################################################################
10169 22:15:53.941607
10170 22:15:54.218050 01b00000 ################################################################
10171 22:15:54.218210
10172 22:15:54.481463 01b80000 ################################################################
10173 22:15:54.481623
10174 22:15:54.748751 01c00000 ################################################################
10175 22:15:54.748896
10176 22:15:55.006994 01c80000 ################################################################
10177 22:15:55.007129
10178 22:15:55.259712 01d00000 ################################################################
10179 22:15:55.259849
10180 22:15:55.510469 01d80000 ################################################################
10181 22:15:55.510601
10182 22:15:55.775331 01e00000 ################################################################
10183 22:15:55.775480
10184 22:15:56.031475 01e80000 ################################################################
10185 22:15:56.031614
10186 22:15:56.282731 01f00000 ################################################################
10187 22:15:56.282886
10188 22:15:56.542576 01f80000 ################################################################
10189 22:15:56.542710
10190 22:15:56.795030 02000000 ################################################################
10191 22:15:56.795169
10192 22:15:57.055164 02080000 ################################################################
10193 22:15:57.055298
10194 22:15:57.309286 02100000 ################################################################
10195 22:15:57.309420
10196 22:15:57.571037 02180000 ################################################################
10197 22:15:57.571173
10198 22:15:57.829564 02200000 ################################################################
10199 22:15:57.829726
10200 22:15:58.077616 02280000 ################################################################
10201 22:15:58.077778
10202 22:15:58.340687 02300000 ################################################################
10203 22:15:58.340822
10204 22:15:58.619779 02380000 ################################################################
10205 22:15:58.619920
10206 22:15:58.910367 02400000 ################################################################
10207 22:15:58.910498
10208 22:15:59.193563 02480000 ################################################################
10209 22:15:59.193732
10210 22:15:59.482213 02500000 ################################################################
10211 22:15:59.482345
10212 22:15:59.781068 02580000 ################################################################
10213 22:15:59.781214
10214 22:16:00.078579 02600000 ################################################################
10215 22:16:00.078717
10216 22:16:00.372121 02680000 ################################################################
10217 22:16:00.372264
10218 22:16:00.669701 02700000 ################################################################
10219 22:16:00.669849
10220 22:16:00.960384 02780000 ################################################################
10221 22:16:00.960518
10222 22:16:01.243266 02800000 ################################################################
10223 22:16:01.243418
10224 22:16:01.515499 02880000 ################################################################
10225 22:16:01.515632
10226 22:16:01.767544 02900000 ################################################################
10227 22:16:01.767684
10228 22:16:02.050505 02980000 ################################################################
10229 22:16:02.050646
10230 22:16:02.349636 02a00000 ################################################################
10231 22:16:02.349776
10232 22:16:02.649034 02a80000 ################################################################
10233 22:16:02.649171
10234 22:16:02.940809 02b00000 ################################################################
10235 22:16:02.940949
10236 22:16:03.223915 02b80000 ################################################################
10237 22:16:03.224058
10238 22:16:03.513328 02c00000 ################################################################
10239 22:16:03.513473
10240 22:16:03.798329 02c80000 ################################################################
10241 22:16:03.798475
10242 22:16:04.095759 02d00000 ################################################################
10243 22:16:04.095904
10244 22:16:04.392580 02d80000 ################################################################
10245 22:16:04.392721
10246 22:16:04.692971 02e00000 ################################################################
10247 22:16:04.693108
10248 22:16:04.992310 02e80000 ################################################################
10249 22:16:04.992451
10250 22:16:05.281468 02f00000 ################################################################
10251 22:16:05.281604
10252 22:16:05.572161 02f80000 ################################################################
10253 22:16:05.572328
10254 22:16:05.871794 03000000 ################################################################
10255 22:16:05.871938
10256 22:16:06.171759 03080000 ################################################################
10257 22:16:06.171903
10258 22:16:06.461019 03100000 ################################################################
10259 22:16:06.461158
10260 22:16:06.748178 03180000 ################################################################
10261 22:16:06.748322
10262 22:16:07.038857 03200000 ################################################################
10263 22:16:07.039002
10264 22:16:07.334829 03280000 ################################################################
10265 22:16:07.334969
10266 22:16:07.627724 03300000 ################################################################
10267 22:16:07.627869
10268 22:16:07.910275 03380000 ################################################################
10269 22:16:07.910421
10270 22:16:08.196027 03400000 ################################################################
10271 22:16:08.196166
10272 22:16:08.495412 03480000 ################################################################
10273 22:16:08.495557
10274 22:16:08.794944 03500000 ################################################################
10275 22:16:08.795090
10276 22:16:09.095235 03580000 ################################################################
10277 22:16:09.095409
10278 22:16:09.394973 03600000 ################################################################
10279 22:16:09.395112
10280 22:16:09.696161 03680000 ################################################################
10281 22:16:09.696298
10282 22:16:09.996405 03700000 ################################################################
10283 22:16:09.996545
10284 22:16:10.295914 03780000 ################################################################
10285 22:16:10.296078
10286 22:16:10.595445 03800000 ################################################################
10287 22:16:10.595585
10288 22:16:10.894924 03880000 ################################################################
10289 22:16:10.895097
10290 22:16:11.193534 03900000 ################################################################
10291 22:16:11.193677
10292 22:16:11.491273 03980000 ################################################################
10293 22:16:11.491422
10294 22:16:11.791701 03a00000 ################################################################
10295 22:16:11.791852
10296 22:16:12.082720 03a80000 ################################################################
10297 22:16:12.082864
10298 22:16:12.363257 03b00000 ################################################################
10299 22:16:12.363453
10300 22:16:12.646963 03b80000 ################################################################
10301 22:16:12.647107
10302 22:16:12.946684 03c00000 ################################################################
10303 22:16:12.946839
10304 22:16:13.242718 03c80000 ################################################################
10305 22:16:13.242864
10306 22:16:13.539859 03d00000 ################################################################
10307 22:16:13.540002
10308 22:16:13.838224 03d80000 ################################################################
10309 22:16:13.838372
10310 22:16:14.136556 03e00000 ################################################################
10311 22:16:14.136700
10312 22:16:14.426783 03e80000 ################################################################
10313 22:16:14.426922
10314 22:16:14.721139 03f00000 ################################################################
10315 22:16:14.721283
10316 22:16:15.006647 03f80000 ################################################################
10317 22:16:15.006789
10318 22:16:15.298859 04000000 ################################################################
10319 22:16:15.299003
10320 22:16:15.598683 04080000 ################################################################
10321 22:16:15.598822
10322 22:16:15.899703 04100000 ################################################################
10323 22:16:15.899865
10324 22:16:16.296256 04180000 ################################################################
10325 22:16:16.296770
10326 22:16:16.690603 04200000 ################################################################
10327 22:16:16.691180
10328 22:16:16.990218 04280000 ################################################################
10329 22:16:16.990388
10330 22:16:17.285926 04300000 ################################################################
10331 22:16:17.286091
10332 22:16:17.586462 04380000 ################################################################
10333 22:16:17.586634
10334 22:16:17.882836 04400000 ################################################################
10335 22:16:17.882981
10336 22:16:18.179229 04480000 ################################################################
10337 22:16:18.179405
10338 22:16:18.479059 04500000 ################################################################
10339 22:16:18.479228
10340 22:16:18.779805 04580000 ################################################################
10341 22:16:18.779945
10342 22:16:19.078419 04600000 ################################################################
10343 22:16:19.078587
10344 22:16:19.377073 04680000 ################################################################
10345 22:16:19.377215
10346 22:16:19.677421 04700000 ################################################################
10347 22:16:19.677559
10348 22:16:19.977854 04780000 ################################################################
10349 22:16:19.978019
10350 22:16:20.278552 04800000 ################################################################
10351 22:16:20.278710
10352 22:16:20.575990 04880000 ################################################################
10353 22:16:20.576155
10354 22:16:20.875732 04900000 ################################################################
10355 22:16:20.875876
10356 22:16:21.170487 04980000 ################################################################
10357 22:16:21.170632
10358 22:16:21.466672 04a00000 ################################################################
10359 22:16:21.466814
10360 22:16:21.764762 04a80000 ################################################################
10361 22:16:21.764902
10362 22:16:22.061519 04b00000 ################################################################
10363 22:16:22.061677
10364 22:16:22.361936 04b80000 ################################################################
10365 22:16:22.362077
10366 22:16:22.653087 04c00000 ################################################################
10367 22:16:22.653227
10368 22:16:22.952752 04c80000 ################################################################
10369 22:16:22.952892
10370 22:16:23.252299 04d00000 ################################################################
10371 22:16:23.252437
10372 22:16:23.551298 04d80000 ################################################################
10373 22:16:23.551471
10374 22:16:23.848427 04e00000 ################################################################
10375 22:16:23.848566
10376 22:16:24.147807 04e80000 ################################################################
10377 22:16:24.147950
10378 22:16:24.447333 04f00000 ################################################################
10379 22:16:24.447482
10380 22:16:24.746046 04f80000 ################################################################
10381 22:16:24.746190
10382 22:16:25.041453 05000000 ################################################################
10383 22:16:25.041596
10384 22:16:25.338914 05080000 ################################################################
10385 22:16:25.339054
10386 22:16:25.626991 05100000 ################################################################
10387 22:16:25.627135
10388 22:16:25.886937 05180000 ################################################################
10389 22:16:25.887108
10390 22:16:26.155441 05200000 ################################################################
10391 22:16:26.155589
10392 22:16:26.432019 05280000 ################################################################
10393 22:16:26.432166
10394 22:16:26.752221 05300000 ################################################################
10395 22:16:26.752363
10396 22:16:27.036263 05380000 ################################################################
10397 22:16:27.036407
10398 22:16:27.327463 05400000 ################################################################
10399 22:16:27.327608
10400 22:16:27.618862 05480000 ################################################################
10401 22:16:27.619008
10402 22:16:27.918515 05500000 ################################################################
10403 22:16:27.918662
10404 22:16:28.214874 05580000 ################################################################
10405 22:16:28.215019
10406 22:16:28.511892 05600000 ################################################################
10407 22:16:28.512044
10408 22:16:28.811285 05680000 ################################################################
10409 22:16:28.811470
10410 22:16:29.110673 05700000 ################################################################
10411 22:16:29.110816
10412 22:16:29.408785 05780000 ################################################################
10413 22:16:29.408931
10414 22:16:29.709311 05800000 ################################################################
10415 22:16:29.709454
10416 22:16:30.008602 05880000 ################################################################
10417 22:16:30.008741
10418 22:16:30.310168 05900000 ################################################################
10419 22:16:30.310306
10420 22:16:30.610549 05980000 ################################################################
10421 22:16:30.610692
10422 22:16:30.906644 05a00000 ################################################################
10423 22:16:30.906790
10424 22:16:31.206225 05a80000 ################################################################
10425 22:16:31.206389
10426 22:16:31.497563 05b00000 ################################################################
10427 22:16:31.497700
10428 22:16:31.792640 05b80000 ################################################################
10429 22:16:31.792782
10430 22:16:32.094347 05c00000 ################################################################
10431 22:16:32.094494
10432 22:16:32.395426 05c80000 ################################################################
10433 22:16:32.395573
10434 22:16:32.693560 05d00000 ################################################################
10435 22:16:32.693707
10436 22:16:32.990805 05d80000 ################################################################
10437 22:16:32.990953
10438 22:16:33.290047 05e00000 ################################################################
10439 22:16:33.290198
10440 22:16:33.574591 05e80000 ################################################################
10441 22:16:33.574735
10442 22:16:33.865959 05f00000 ################################################################
10443 22:16:33.866093
10444 22:16:34.165240 05f80000 ################################################################
10445 22:16:34.165375
10446 22:16:34.465477 06000000 ################################################################
10447 22:16:34.465614
10448 22:16:34.765155 06080000 ################################################################
10449 22:16:34.765289
10450 22:16:35.063166 06100000 ################################################################
10451 22:16:35.063304
10452 22:16:35.361269 06180000 ################################################################
10453 22:16:35.361402
10454 22:16:35.653028 06200000 ################################################################
10455 22:16:35.653159
10456 22:16:35.947947 06280000 ################################################################
10457 22:16:35.948081
10458 22:16:36.246496 06300000 ################################################################
10459 22:16:36.246628
10460 22:16:36.519434 06380000 ################################################################
10461 22:16:36.519567
10462 22:16:36.768242 06400000 ################################################################
10463 22:16:36.768376
10464 22:16:37.017628 06480000 ################################################################
10465 22:16:37.017778
10466 22:16:37.272820 06500000 ################################################################
10467 22:16:37.272949
10468 22:16:37.547958 06580000 ################################################################
10469 22:16:37.548090
10470 22:16:37.820133 06600000 ################################################################
10471 22:16:37.820261
10472 22:16:38.108656 06680000 ################################################################
10473 22:16:38.108784
10474 22:16:38.262952 06700000 ################################# done.
10475 22:16:38.263071
10476 22:16:38.266113 The bootfile was 108273634 bytes long.
10477 22:16:38.266205
10478 22:16:38.269757 Sending tftp read request... done.
10479 22:16:38.269854
10480 22:16:38.269929 Waiting for the transfer...
10481 22:16:38.273063
10482 22:16:38.273158 00000000 # done.
10483 22:16:38.273235
10484 22:16:38.279722 Command line loaded dynamically from TFTP file: 10597240/tftp-deploy-g8u9ngxh/kernel/cmdline
10485 22:16:38.279872
10486 22:16:38.293000 The command line is: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10487 22:16:38.293140
10488 22:16:38.293248 Loading FIT.
10489 22:16:38.293348
10490 22:16:38.296575 Image ramdisk-1 has 98142370 bytes.
10491 22:16:38.296729
10492 22:16:38.299355 Image fdt-1 has 46924 bytes.
10493 22:16:38.299529
10494 22:16:38.302938 Image kernel-1 has 10082307 bytes.
10495 22:16:38.303114
10496 22:16:38.309858 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10497 22:16:38.312875
10498 22:16:38.329983 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10499 22:16:38.330538
10500 22:16:38.332905 Choosing best match conf-1 for compat google,spherion-rev2.
10501 22:16:38.338949
10502 22:16:38.342822 Connected to device vid:did:rid of 1ae0:0028:00
10503 22:16:38.351497
10504 22:16:38.354580 tpm_get_response: command 0x17b, return code 0x0
10505 22:16:38.355050
10506 22:16:38.361087 ec_init: CrosEC protocol v3 supported (256, 248)
10507 22:16:38.361560
10508 22:16:38.364822 tpm_cleanup: add release locality here.
10509 22:16:38.365292
10510 22:16:38.368125 Shutting down all USB controllers.
10511 22:16:38.368593
10512 22:16:38.371536 Removing current net device
10513 22:16:38.372114
10514 22:16:38.375087 Exiting depthcharge with code 4 at timestamp: 94896307
10515 22:16:38.375582
10516 22:16:38.381612 LZMA decompressing kernel-1 to 0x821a6718
10517 22:16:38.382161
10518 22:16:38.384772 LZMA decompressing kernel-1 to 0x40000000
10519 22:16:39.651084
10520 22:16:39.651686 jumping to kernel
10521 22:16:39.653477 end: 2.2.4 bootloader-commands (duration 00:01:07) [common]
10522 22:16:39.654004 start: 2.2.5 auto-login-action (timeout 00:03:18) [common]
10523 22:16:39.654415 Setting prompt string to ['Linux version [0-9]']
10524 22:16:39.654795 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10525 22:16:39.655171 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10526 22:16:39.732752
10527 22:16:39.735877 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10528 22:16:39.739791 start: 2.2.5.1 login-action (timeout 00:03:18) [common]
10529 22:16:39.740362 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10530 22:16:39.740839 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10531 22:16:39.741265 Using line separator: #'\n'#
10532 22:16:39.741608 No login prompt set.
10533 22:16:39.741949 Parsing kernel messages
10534 22:16:39.742294 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10535 22:16:39.742985 [login-action] Waiting for messages, (timeout 00:03:18)
10536 22:16:39.759049 [ 0.000000] Linux version 6.1.31 (KernelCI@build-j1612341-arm64-gcc-10-defconfig-arm64-chromebook-n674v) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Mon Jun 5 22:04:07 UTC 2023
10537 22:16:39.762740 [ 0.000000] random: crng init done
10538 22:16:39.766273 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10539 22:16:39.769557 [ 0.000000] efi: UEFI not found.
10540 22:16:39.779089 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10541 22:16:39.786073 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10542 22:16:39.795583 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10543 22:16:39.805453 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10544 22:16:39.812394 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10545 22:16:39.815367 [ 0.000000] printk: bootconsole [mtk8250] enabled
10546 22:16:39.823896 [ 0.000000] NUMA: No NUMA configuration found
10547 22:16:39.830668 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10548 22:16:39.837282 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcda00-0x23efcffff]
10549 22:16:39.837835 [ 0.000000] Zone ranges:
10550 22:16:39.844666 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10551 22:16:39.847591 [ 0.000000] DMA32 empty
10552 22:16:39.853867 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10553 22:16:39.857217 [ 0.000000] Movable zone start for each node
10554 22:16:39.860694 [ 0.000000] Early memory node ranges
10555 22:16:39.867822 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10556 22:16:39.874025 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10557 22:16:39.880880 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10558 22:16:39.886924 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10559 22:16:39.893971 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10560 22:16:39.900262 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10561 22:16:39.957051 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10562 22:16:39.963565 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10563 22:16:39.970242 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10564 22:16:39.973235 [ 0.000000] psci: probing for conduit method from DT.
10565 22:16:39.979714 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10566 22:16:39.982971 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10567 22:16:39.989875 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10568 22:16:39.993423 [ 0.000000] psci: SMC Calling Convention v1.2
10569 22:16:39.999313 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10570 22:16:40.002608 [ 0.000000] Detected VIPT I-cache on CPU0
10571 22:16:40.009761 [ 0.000000] CPU features: detected: GIC system register CPU interface
10572 22:16:40.016027 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10573 22:16:40.023181 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10574 22:16:40.029684 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10575 22:16:40.035892 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10576 22:16:40.046363 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10577 22:16:40.049049 [ 0.000000] alternatives: applying boot alternatives
10578 22:16:40.052864 [ 0.000000] Fallback order for Node 0: 0
10579 22:16:40.062710 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10580 22:16:40.063363 [ 0.000000] Policy zone: Normal
10581 22:16:40.075674 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10582 22:16:40.085855 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10583 22:16:40.098926 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10584 22:16:40.109012 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10585 22:16:40.115315 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10586 22:16:40.118465 <6>[ 0.000000] software IO TLB: area num 8.
10587 22:16:40.175864 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10588 22:16:40.324980 <6>[ 0.000000] Memory: 7877100K/8385536K available (17984K kernel code, 4098K rwdata, 14068K rodata, 8384K init, 615K bss, 475668K reserved, 32768K cma-reserved)
10589 22:16:40.331716 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10590 22:16:40.338218 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10591 22:16:40.341167 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10592 22:16:40.347794 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10593 22:16:40.354694 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10594 22:16:40.357811 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10595 22:16:40.367641 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10596 22:16:40.374405 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10597 22:16:40.377791 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10598 22:16:40.386113 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10599 22:16:40.389086 <6>[ 0.000000] GICv3: 608 SPIs implemented
10600 22:16:40.395909 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10601 22:16:40.399470 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10602 22:16:40.402389 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10603 22:16:40.412270 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10604 22:16:40.422776 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10605 22:16:40.435676 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10606 22:16:40.442143 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10607 22:16:40.451322 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10608 22:16:40.464349 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10609 22:16:40.471449 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10610 22:16:40.478123 <6>[ 0.009225] Console: colour dummy device 80x25
10611 22:16:40.487926 <6>[ 0.013952] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10612 22:16:40.494216 <6>[ 0.024394] pid_max: default: 32768 minimum: 301
10613 22:16:40.497532 <6>[ 0.029297] LSM: Security Framework initializing
10614 22:16:40.504324 <6>[ 0.034234] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10615 22:16:40.514629 <6>[ 0.042046] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10616 22:16:40.521085 <6>[ 0.051488] cblist_init_generic: Setting adjustable number of callback queues.
10617 22:16:40.527809 <6>[ 0.058942] cblist_init_generic: Setting shift to 3 and lim to 1.
10618 22:16:40.534771 <6>[ 0.065281] cblist_init_generic: Setting shift to 3 and lim to 1.
10619 22:16:40.541169 <6>[ 0.071729] rcu: Hierarchical SRCU implementation.
10620 22:16:40.544082 <6>[ 0.076741] rcu: Max phase no-delay instances is 1000.
10621 22:16:40.552406 <6>[ 0.083767] EFI services will not be available.
10622 22:16:40.556105 <6>[ 0.088772] smp: Bringing up secondary CPUs ...
10623 22:16:40.565382 <6>[ 0.093830] Detected VIPT I-cache on CPU1
10624 22:16:40.571811 <6>[ 0.093902] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10625 22:16:40.578091 <6>[ 0.093932] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10626 22:16:40.582093 <6>[ 0.094263] Detected VIPT I-cache on CPU2
10627 22:16:40.588610 <6>[ 0.094314] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10628 22:16:40.595272 <6>[ 0.094329] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10629 22:16:40.602065 <6>[ 0.094585] Detected VIPT I-cache on CPU3
10630 22:16:40.608472 <6>[ 0.094632] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10631 22:16:40.614909 <6>[ 0.094645] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10632 22:16:40.618687 <6>[ 0.094953] CPU features: detected: Spectre-v4
10633 22:16:40.625198 <6>[ 0.094960] CPU features: detected: Spectre-BHB
10634 22:16:40.628477 <6>[ 0.094966] Detected PIPT I-cache on CPU4
10635 22:16:40.635109 <6>[ 0.095023] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10636 22:16:40.641872 <6>[ 0.095039] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10637 22:16:40.644827 <6>[ 0.095338] Detected PIPT I-cache on CPU5
10638 22:16:40.654823 <6>[ 0.095402] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10639 22:16:40.661341 <6>[ 0.095418] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10640 22:16:40.664687 <6>[ 0.095704] Detected PIPT I-cache on CPU6
10641 22:16:40.671215 <6>[ 0.095769] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10642 22:16:40.677540 <6>[ 0.095785] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10643 22:16:40.684323 <6>[ 0.096083] Detected PIPT I-cache on CPU7
10644 22:16:40.691192 <6>[ 0.096148] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10645 22:16:40.697979 <6>[ 0.096164] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10646 22:16:40.700892 <6>[ 0.096210] smp: Brought up 1 node, 8 CPUs
10647 22:16:40.707883 <6>[ 0.237453] SMP: Total of 8 processors activated.
10648 22:16:40.711157 <6>[ 0.242405] CPU features: detected: 32-bit EL0 Support
10649 22:16:40.720607 <6>[ 0.247768] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10650 22:16:40.728043 <6>[ 0.256568] CPU features: detected: Common not Private translations
10651 22:16:40.730766 <6>[ 0.263044] CPU features: detected: CRC32 instructions
10652 22:16:40.737918 <6>[ 0.268395] CPU features: detected: RCpc load-acquire (LDAPR)
10653 22:16:40.744416 <6>[ 0.274354] CPU features: detected: LSE atomic instructions
10654 22:16:40.750984 <6>[ 0.280135] CPU features: detected: Privileged Access Never
10655 22:16:40.754530 <6>[ 0.285915] CPU features: detected: RAS Extension Support
10656 22:16:40.763862 <6>[ 0.291524] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10657 22:16:40.767567 <6>[ 0.298744] CPU: All CPU(s) started at EL2
10658 22:16:40.774133 <6>[ 0.303060] alternatives: applying system-wide alternatives
10659 22:16:40.782315 <6>[ 0.313799] devtmpfs: initialized
10660 22:16:40.795010 <6>[ 0.322684] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10661 22:16:40.804593 <6>[ 0.332646] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10662 22:16:40.811534 <6>[ 0.340718] pinctrl core: initialized pinctrl subsystem
10663 22:16:40.814427 <6>[ 0.347350] DMI not present or invalid.
10664 22:16:40.820967 <6>[ 0.351753] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10665 22:16:40.831415 <6>[ 0.358648] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10666 22:16:40.838140 <6>[ 0.366225] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10667 22:16:40.848167 <6>[ 0.374430] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10668 22:16:40.851245 <6>[ 0.382673] audit: initializing netlink subsys (disabled)
10669 22:16:40.861412 <5>[ 0.388363] audit: type=2000 audit(0.276:1): state=initialized audit_enabled=0 res=1
10670 22:16:40.867889 <6>[ 0.389064] thermal_sys: Registered thermal governor 'step_wise'
10671 22:16:40.874423 <6>[ 0.396332] thermal_sys: Registered thermal governor 'power_allocator'
10672 22:16:40.877400 <6>[ 0.402585] cpuidle: using governor menu
10673 22:16:40.881044 <6>[ 0.413543] NET: Registered PF_QIPCRTR protocol family
10674 22:16:40.890874 <6>[ 0.419018] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10675 22:16:40.894621 <6>[ 0.426121] ASID allocator initialised with 32768 entries
10676 22:16:40.901441 <6>[ 0.432695] Serial: AMBA PL011 UART driver
10677 22:16:40.909693 <4>[ 0.441266] Trying to register duplicate clock ID: 134
10678 22:16:40.964067 <6>[ 0.498418] KASLR enabled
10679 22:16:40.978612 <6>[ 0.506167] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10680 22:16:40.984579 <6>[ 0.513181] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10681 22:16:40.991424 <6>[ 0.519671] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10682 22:16:40.998425 <6>[ 0.526676] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10683 22:16:41.005216 <6>[ 0.533162] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10684 22:16:41.011402 <6>[ 0.540166] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10685 22:16:41.018145 <6>[ 0.546654] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10686 22:16:41.024847 <6>[ 0.553657] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10687 22:16:41.028413 <6>[ 0.561172] ACPI: Interpreter disabled.
10688 22:16:41.036574 <6>[ 0.567573] iommu: Default domain type: Translated
10689 22:16:41.042881 <6>[ 0.572685] iommu: DMA domain TLB invalidation policy: strict mode
10690 22:16:41.045788 <5>[ 0.579341] SCSI subsystem initialized
10691 22:16:41.053587 <6>[ 0.583508] usbcore: registered new interface driver usbfs
10692 22:16:41.060145 <6>[ 0.589239] usbcore: registered new interface driver hub
10693 22:16:41.062775 <6>[ 0.594789] usbcore: registered new device driver usb
10694 22:16:41.069735 <6>[ 0.600873] pps_core: LinuxPPS API ver. 1 registered
10695 22:16:41.079151 <6>[ 0.606068] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10696 22:16:41.083216 <6>[ 0.615412] PTP clock support registered
10697 22:16:41.086163 <6>[ 0.619654] EDAC MC: Ver: 3.0.0
10698 22:16:41.093409 <6>[ 0.624784] FPGA manager framework
10699 22:16:41.096880 <6>[ 0.628461] Advanced Linux Sound Architecture Driver Initialized.
10700 22:16:41.100796 <6>[ 0.635223] vgaarb: loaded
10701 22:16:41.107306 <6>[ 0.638380] clocksource: Switched to clocksource arch_sys_counter
10702 22:16:41.114062 <5>[ 0.644821] VFS: Disk quotas dquot_6.6.0
10703 22:16:41.120798 <6>[ 0.649007] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10704 22:16:41.123892 <6>[ 0.656198] pnp: PnP ACPI: disabled
10705 22:16:41.131384 <6>[ 0.662915] NET: Registered PF_INET protocol family
10706 22:16:41.141349 <6>[ 0.668509] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10707 22:16:41.152935 <6>[ 0.680810] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10708 22:16:41.162731 <6>[ 0.689627] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10709 22:16:41.169567 <6>[ 0.697602] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10710 22:16:41.176002 <6>[ 0.706302] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10711 22:16:41.187894 <6>[ 0.716044] TCP: Hash tables configured (established 65536 bind 65536)
10712 22:16:41.194580 <6>[ 0.722904] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10713 22:16:41.201843 <6>[ 0.730104] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10714 22:16:41.207834 <6>[ 0.737810] NET: Registered PF_UNIX/PF_LOCAL protocol family
10715 22:16:41.214874 <6>[ 0.743972] RPC: Registered named UNIX socket transport module.
10716 22:16:41.217747 <6>[ 0.750128] RPC: Registered udp transport module.
10717 22:16:41.225146 <6>[ 0.755062] RPC: Registered tcp transport module.
10718 22:16:41.231465 <6>[ 0.759996] RPC: Registered tcp NFSv4.1 backchannel transport module.
10719 22:16:41.234797 <6>[ 0.766663] PCI: CLS 0 bytes, default 64
10720 22:16:41.238001 <6>[ 0.771034] Unpacking initramfs...
10721 22:16:41.255301 <6>[ 0.782936] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10722 22:16:41.264806 <6>[ 0.791601] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10723 22:16:41.268204 <6>[ 0.800445] kvm [1]: IPA Size Limit: 40 bits
10724 22:16:41.274554 <6>[ 0.804971] kvm [1]: GICv3: no GICV resource entry
10725 22:16:41.277717 <6>[ 0.809992] kvm [1]: disabling GICv2 emulation
10726 22:16:41.285233 <6>[ 0.814680] kvm [1]: GIC system register CPU interface enabled
10727 22:16:41.288220 <6>[ 0.820852] kvm [1]: vgic interrupt IRQ18
10728 22:16:41.294833 <6>[ 0.825218] kvm [1]: VHE mode initialized successfully
10729 22:16:41.301390 <5>[ 0.831646] Initialise system trusted keyrings
10730 22:16:41.308308 <6>[ 0.836440] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10731 22:16:41.315009 <6>[ 0.846359] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10732 22:16:41.321722 <5>[ 0.852746] NFS: Registering the id_resolver key type
10733 22:16:41.324851 <5>[ 0.858044] Key type id_resolver registered
10734 22:16:41.331448 <5>[ 0.862460] Key type id_legacy registered
10735 22:16:41.338042 <6>[ 0.866739] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10736 22:16:41.344514 <6>[ 0.873661] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10737 22:16:41.351592 <6>[ 0.881368] 9p: Installing v9fs 9p2000 file system support
10738 22:16:41.386748 <5>[ 0.918287] Key type asymmetric registered
10739 22:16:41.390314 <5>[ 0.922617] Asymmetric key parser 'x509' registered
10740 22:16:41.400609 <6>[ 0.927767] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10741 22:16:41.404245 <6>[ 0.935385] io scheduler mq-deadline registered
10742 22:16:41.407269 <6>[ 0.940144] io scheduler kyber registered
10743 22:16:41.425674 <6>[ 0.956876] EINJ: ACPI disabled.
10744 22:16:41.457663 <4>[ 0.982188] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10745 22:16:41.467118 <4>[ 0.992840] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10746 22:16:41.481723 <6>[ 1.013239] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10747 22:16:41.490100 <6>[ 1.021195] printk: console [ttyS0] disabled
10748 22:16:41.517991 <6>[ 1.045852] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10749 22:16:41.524662 <6>[ 1.055341] printk: console [ttyS0] enabled
10750 22:16:41.528017 <6>[ 1.055341] printk: console [ttyS0] enabled
10751 22:16:41.534695 <6>[ 1.064253] printk: bootconsole [mtk8250] disabled
10752 22:16:41.538062 <6>[ 1.064253] printk: bootconsole [mtk8250] disabled
10753 22:16:41.544233 <6>[ 1.075487] SuperH (H)SCI(F) driver initialized
10754 22:16:41.547667 <6>[ 1.080768] msm_serial: driver initialized
10755 22:16:41.561840 <6>[ 1.089703] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10756 22:16:41.571209 <6>[ 1.098248] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10757 22:16:41.578130 <6>[ 1.106791] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10758 22:16:41.588596 <6>[ 1.115419] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10759 22:16:41.594871 <6>[ 1.124124] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10760 22:16:41.604861 <6>[ 1.132837] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10761 22:16:41.614749 <6>[ 1.141377] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10762 22:16:41.621713 <6>[ 1.150185] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10763 22:16:41.631190 <6>[ 1.158728] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10764 22:16:41.642794 <6>[ 1.174339] loop: module loaded
10765 22:16:41.649540 <6>[ 1.180075] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10766 22:16:41.672058 <4>[ 1.203577] mtk-pmic-keys: Failed to locate of_node [id: -1]
10767 22:16:41.678795 <6>[ 1.210504] megasas: 07.719.03.00-rc1
10768 22:16:41.688797 <6>[ 1.220188] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10769 22:16:41.698696 <6>[ 1.229781] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10770 22:16:41.715444 <6>[ 1.246612] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10771 22:16:41.772192 <6>[ 1.297289] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.153/cr50_v3.94_pp.113-620c9
10772 22:16:45.227725 <6>[ 4.759281] Freeing initrd memory: 95836K
10773 22:16:45.237160 <6>[ 4.769314] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10774 22:16:45.247937 <6>[ 4.780205] tun: Universal TUN/TAP device driver, 1.6
10775 22:16:45.251301 <6>[ 4.786253] thunder_xcv, ver 1.0
10776 22:16:45.254814 <6>[ 4.789761] thunder_bgx, ver 1.0
10777 22:16:45.257895 <6>[ 4.793256] nicpf, ver 1.0
10778 22:16:45.268515 <6>[ 4.797257] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10779 22:16:45.271660 <6>[ 4.804733] hns3: Copyright (c) 2017 Huawei Corporation.
10780 22:16:45.275379 <6>[ 4.810319] hclge is initializing
10781 22:16:45.281933 <6>[ 4.813899] e1000: Intel(R) PRO/1000 Network Driver
10782 22:16:45.288650 <6>[ 4.819028] e1000: Copyright (c) 1999-2006 Intel Corporation.
10783 22:16:45.292248 <6>[ 4.825041] e1000e: Intel(R) PRO/1000 Network Driver
10784 22:16:45.299108 <6>[ 4.830256] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10785 22:16:45.305438 <6>[ 4.836440] igb: Intel(R) Gigabit Ethernet Network Driver
10786 22:16:45.311920 <6>[ 4.842090] igb: Copyright (c) 2007-2014 Intel Corporation.
10787 22:16:45.319113 <6>[ 4.847929] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10788 22:16:45.322606 <6>[ 4.854446] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10789 22:16:45.329243 <6>[ 4.860901] sky2: driver version 1.30
10790 22:16:45.335530 <6>[ 4.865866] VFIO - User Level meta-driver version: 0.3
10791 22:16:45.342378 <6>[ 4.874072] usbcore: registered new interface driver usb-storage
10792 22:16:45.348603 <6>[ 4.880521] usbcore: registered new device driver onboard-usb-hub
10793 22:16:45.357863 <6>[ 4.889585] mt6397-rtc mt6359-rtc: registered as rtc0
10794 22:16:45.367708 <6>[ 4.895051] mt6397-rtc mt6359-rtc: setting system clock to 2023-06-05T22:16:37 UTC (1686003397)
10795 22:16:45.371132 <6>[ 4.904605] i2c_dev: i2c /dev entries driver
10796 22:16:45.387455 <6>[ 4.916181] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10797 22:16:45.394468 <6>[ 4.926365] sdhci: Secure Digital Host Controller Interface driver
10798 22:16:45.401146 <6>[ 4.932808] sdhci: Copyright(c) Pierre Ossman
10799 22:16:45.408585 <6>[ 4.938205] Synopsys Designware Multimedia Card Interface Driver
10800 22:16:45.411310 <6>[ 4.944808] mmc0: CQHCI version 5.10
10801 22:16:45.417789 <6>[ 4.945355] sdhci-pltfm: SDHCI platform and OF driver helper
10802 22:16:45.424909 <6>[ 4.956705] ledtrig-cpu: registered to indicate activity on CPUs
10803 22:16:45.435686 <6>[ 4.964053] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10804 22:16:45.439442 <6>[ 4.971447] usbcore: registered new interface driver usbhid
10805 22:16:45.445394 <6>[ 4.977279] usbhid: USB HID core driver
10806 22:16:45.451840 <6>[ 4.981518] spi_master spi0: will run message pump with realtime priority
10807 22:16:45.496533 <6>[ 5.021881] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10808 22:16:45.515734 <6>[ 5.036863] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10809 22:16:45.518661 <6>[ 5.050476] mmc0: Command Queue Engine enabled
10810 22:16:45.525900 <6>[ 5.052292] cros-ec-spi spi0.0: Chrome EC device registered
10811 22:16:45.532610 <6>[ 5.055200] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10812 22:16:45.535312 <6>[ 5.055785] mmcblk0: mmc0:0001 DA4128 116 GiB
10813 22:16:45.546069 <6>[ 5.077250] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10814 22:16:45.555623 <6>[ 5.078418] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10815 22:16:45.562817 <6>[ 5.084656] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10816 22:16:45.565299 <6>[ 5.094578] NET: Registered PF_PACKET protocol family
10817 22:16:45.572134 <6>[ 5.098353] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10818 22:16:45.575098 <6>[ 5.103114] 9pnet: Installing 9P2000 support
10819 22:16:45.582168 <6>[ 5.108863] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10820 22:16:45.588594 <5>[ 5.112801] Key type dns_resolver registered
10821 22:16:45.592526 <6>[ 5.124306] registered taskstats version 1
10822 22:16:45.595260 <5>[ 5.128700] Loading compiled-in X.509 certificates
10823 22:16:45.629479 <4>[ 5.154301] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10824 22:16:45.639050 <4>[ 5.164995] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10825 22:16:45.649507 <3>[ 5.177740] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10826 22:16:45.661169 <6>[ 5.193188] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10827 22:16:45.668063 <6>[ 5.199940] xhci-mtk 11200000.usb: xHCI Host Controller
10828 22:16:45.674872 <6>[ 5.205445] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10829 22:16:45.684777 <6>[ 5.213315] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10830 22:16:45.691668 <6>[ 5.222770] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10831 22:16:45.698262 <6>[ 5.228867] xhci-mtk 11200000.usb: xHCI Host Controller
10832 22:16:45.704829 <6>[ 5.234451] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10833 22:16:45.711306 <6>[ 5.242121] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10834 22:16:45.718251 <6>[ 5.250022] hub 1-0:1.0: USB hub found
10835 22:16:45.721642 <6>[ 5.254069] hub 1-0:1.0: 1 port detected
10836 22:16:45.732184 <6>[ 5.258424] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10837 22:16:45.734975 <6>[ 5.267225] hub 2-0:1.0: USB hub found
10838 22:16:45.738502 <6>[ 5.271262] hub 2-0:1.0: 1 port detected
10839 22:16:45.746567 <6>[ 5.278600] mtk-msdc 11f70000.mmc: Got CD GPIO
10840 22:16:45.767852 <6>[ 5.296211] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10841 22:16:45.774274 <6>[ 5.304243] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10842 22:16:45.783979 <4>[ 5.312231] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10843 22:16:45.794225 <6>[ 5.321900] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10844 22:16:45.800792 <6>[ 5.329983] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10845 22:16:45.807410 <6>[ 5.338008] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10846 22:16:45.817488 <6>[ 5.345926] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10847 22:16:45.823966 <6>[ 5.353747] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10848 22:16:45.834067 <6>[ 5.361569] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10849 22:16:45.844002 <6>[ 5.372196] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10850 22:16:45.850651 <6>[ 5.380574] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10851 22:16:45.861066 <6>[ 5.388927] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10852 22:16:45.870485 <6>[ 5.397271] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10853 22:16:45.877100 <6>[ 5.405615] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10854 22:16:45.887123 <6>[ 5.413958] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10855 22:16:45.893508 <6>[ 5.422301] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10856 22:16:45.903413 <6>[ 5.430645] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10857 22:16:45.910684 <6>[ 5.438988] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10858 22:16:45.920770 <6>[ 5.447332] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10859 22:16:45.927179 <6>[ 5.455675] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10860 22:16:45.937064 <6>[ 5.464019] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10861 22:16:45.943530 <6>[ 5.472369] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10862 22:16:45.953866 <6>[ 5.480712] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10863 22:16:45.960051 <6>[ 5.489056] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10864 22:16:45.966718 <6>[ 5.497964] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10865 22:16:45.974028 <6>[ 5.505434] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10866 22:16:45.980702 <6>[ 5.512538] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10867 22:16:45.991179 <6>[ 5.519683] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10868 22:16:45.997930 <6>[ 5.527015] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10869 22:16:46.007641 <6>[ 5.533968] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10870 22:16:46.014434 <6>[ 5.543111] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10871 22:16:46.023949 <6>[ 5.552239] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10872 22:16:46.034259 <6>[ 5.561541] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10873 22:16:46.044368 <6>[ 5.571017] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10874 22:16:46.054013 <6>[ 5.580490] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10875 22:16:46.061164 <6>[ 5.589619] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10876 22:16:46.070753 <6>[ 5.599093] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10877 22:16:46.080800 <6>[ 5.608220] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10878 22:16:46.090896 <6>[ 5.617522] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10879 22:16:46.100282 <6>[ 5.627688] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10880 22:16:46.110413 <6>[ 5.639118] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10881 22:16:46.146083 <6>[ 5.674655] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10882 22:16:46.300585 <6>[ 5.832025] hub 1-1:1.0: USB hub found
10883 22:16:46.303511 <6>[ 5.836486] hub 1-1:1.0: 4 ports detected
10884 22:16:46.426458 <6>[ 5.954895] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10885 22:16:46.451485 <6>[ 5.982916] hub 2-1:1.0: USB hub found
10886 22:16:46.454609 <6>[ 5.987313] hub 2-1:1.0: 3 ports detected
10887 22:16:46.626021 <6>[ 6.154688] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10888 22:16:46.759102 <6>[ 6.290515] hub 1-1.4:1.0: USB hub found
10889 22:16:46.762398 <6>[ 6.295176] hub 1-1.4:1.0: 2 ports detected
10890 22:16:46.838190 <6>[ 6.366910] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10891 22:16:47.057540 <6>[ 6.586651] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10892 22:16:47.249732 <6>[ 6.778652] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10893 22:16:58.393995 <6>[ 17.931249] ALSA device list:
10894 22:16:58.400894 <6>[ 17.934498] No soundcards found.
10895 22:16:58.413090 <6>[ 17.946896] Freeing unused kernel memory: 8384K
10896 22:16:58.416556 <6>[ 17.951809] Run /init as init process
10897 22:16:58.446636 <6>[ 17.980324] NET: Registered PF_INET6 protocol family
10898 22:16:58.453047 <6>[ 17.986451] Segment Routing with IPv6
10899 22:16:58.456314 <6>[ 17.990401] In-situ OAM (IOAM) with IPv6
10900 22:16:58.490986 <30>[ 18.004971] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10901 22:16:58.493988 <30>[ 18.028852] systemd[1]: Detected architecture arm64.
10902 22:16:58.497330
10903 22:16:58.501222 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10904 22:16:58.501303
10905 22:16:58.517256 <30>[ 18.050884] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10906 22:16:58.659657 <30>[ 18.190076] systemd[1]: Queued start job for default target Graphical Interface.
10907 22:16:58.690621 <30>[ 18.224074] systemd[1]: Created slice system-getty.slice.
10908 22:16:58.697100 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10909 22:16:58.713474 <30>[ 18.247369] systemd[1]: Created slice system-modprobe.slice.
10910 22:16:58.720241 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10911 22:16:58.737284 <30>[ 18.271295] systemd[1]: Created slice system-serial\x2dgetty.slice.
10912 22:16:58.747669 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10913 22:16:58.761307 <30>[ 18.295145] systemd[1]: Created slice User and Session Slice.
10914 22:16:58.768218 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10915 22:16:58.788962 <30>[ 18.319238] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10916 22:16:58.795748 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10917 22:16:58.816705 <30>[ 18.347154] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10918 22:16:58.823452 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10919 22:16:58.843689 <30>[ 18.370746] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10920 22:16:58.850123 <30>[ 18.382781] systemd[1]: Reached target Local Encrypted Volumes.
10921 22:16:58.856877 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10922 22:16:58.873053 <30>[ 18.406993] systemd[1]: Reached target Paths.
10923 22:16:58.876508 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10924 22:16:58.892906 <30>[ 18.426704] systemd[1]: Reached target Remote File Systems.
10925 22:16:58.899647 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10926 22:16:58.913105 <30>[ 18.446654] systemd[1]: Reached target Slices.
10927 22:16:58.916119 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10928 22:16:58.932738 <30>[ 18.466699] systemd[1]: Reached target Swap.
10929 22:16:58.935969 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10930 22:16:58.956810 <30>[ 18.487002] systemd[1]: Listening on initctl Compatibility Named Pipe.
10931 22:16:58.962912 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10932 22:16:58.969907 <30>[ 18.501686] systemd[1]: Listening on Journal Audit Socket.
10933 22:16:58.976186 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10934 22:16:58.989312 <30>[ 18.522958] systemd[1]: Listening on Journal Socket (/dev/log).
10935 22:16:58.995519 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10936 22:16:59.013126 <30>[ 18.546978] systemd[1]: Listening on Journal Socket.
10937 22:16:59.019889 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10938 22:16:59.033138 <30>[ 18.566954] systemd[1]: Listening on udev Control Socket.
10939 22:16:59.039916 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10940 22:16:59.057537 <30>[ 18.591310] systemd[1]: Listening on udev Kernel Socket.
10941 22:16:59.064265 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10942 22:16:59.096847 <30>[ 18.630828] systemd[1]: Mounting Huge Pages File System...
10943 22:16:59.103389 Mounting [0;1;39mHuge Pages File System[0m...
10944 22:16:59.118657 <30>[ 18.652752] systemd[1]: Mounting POSIX Message Queue File System...
10945 22:16:59.126051 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10946 22:16:59.142819 <30>[ 18.676762] systemd[1]: Mounting Kernel Debug File System...
10947 22:16:59.149185 Mounting [0;1;39mKernel Debug File System[0m...
10948 22:16:59.168488 <30>[ 18.698968] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10949 22:16:59.179676 <30>[ 18.710068] systemd[1]: Starting Create list of static device nodes for the current kernel...
10950 22:16:59.185956 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10951 22:16:59.213263 <30>[ 18.747155] systemd[1]: Starting Load Kernel Module configfs...
10952 22:16:59.219949 Starting [0;1;39mLoad Kernel Module configfs[0m...
10953 22:16:59.235286 <30>[ 18.768856] systemd[1]: Starting Load Kernel Module drm...
10954 22:16:59.241578 Starting [0;1;39mLoad Kernel Module drm[0m...
10955 22:16:59.260522 <30>[ 18.790879] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10956 22:16:59.281531 <30>[ 18.815247] systemd[1]: Starting Journal Service...
10957 22:16:59.284933 Starting [0;1;39mJournal Service[0m...
10958 22:16:59.303642 <30>[ 18.837544] systemd[1]: Starting Load Kernel Modules...
10959 22:16:59.310292 Starting [0;1;39mLoad Kernel Modules[0m...
10960 22:16:59.330832 <30>[ 18.861396] systemd[1]: Starting Remount Root and Kernel File Systems...
10961 22:16:59.337734 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10962 22:16:59.355322 <30>[ 18.889202] systemd[1]: Starting Coldplug All udev Devices...
10963 22:16:59.362315 Starting [0;1;39mColdplug All udev Devices[0m...
10964 22:16:59.379524 <30>[ 18.913252] systemd[1]: Mounted Huge Pages File System.
10965 22:16:59.385905 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10966 22:16:59.401353 <30>[ 18.935319] systemd[1]: Started Journal Service.
10967 22:16:59.407898 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10968 22:16:59.422201 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10969 22:16:59.437348 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10970 22:16:59.457229 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10971 22:16:59.474661 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10972 22:16:59.490631 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10973 22:16:59.505958 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10974 22:16:59.525964 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10975 22:16:59.541158 See 'systemctl status systemd-remount-fs.service' for details.
10976 22:16:59.594421 Mounting [0;1;39mKernel Configuration File System[0m...
10977 22:16:59.611606 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10978 22:16:59.629079 <46>[ 19.159624] systemd-journald[176]: Received client request to flush runtime journal.
10979 22:16:59.638137 Starting [0;1;39mLoad/Save Random Seed[0m...
10980 22:16:59.659561 Starting [0;1;39mApply Kernel Variables[0m...
10981 22:16:59.679794 Starting [0;1;39mCreate System Users[0m...
10982 22:16:59.702040 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10983 22:16:59.725139 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10984 22:16:59.742064 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10985 22:16:59.758172 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10986 22:16:59.773578 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10987 22:16:59.789765 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10988 22:16:59.833456 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10989 22:16:59.857011 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10990 22:16:59.869290 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10991 22:16:59.884986 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10992 22:16:59.925718 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10993 22:16:59.948620 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10994 22:16:59.966021 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10995 22:16:59.986128 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10996 22:17:00.038171 Starting [0;1;39mNetwork Time Synchronization[0m...
10997 22:17:00.059330 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10998 22:17:00.098260 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10999 22:17:00.153792 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
11000 22:17:00.173144 <6>[ 19.704005] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
11001 22:17:00.185906 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
11002 22:17:00.195832 <3>[ 19.725622] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11003 22:17:00.202259 <3>[ 19.733822] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11004 22:17:00.212531 <3>[ 19.742439] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11005 22:17:00.215563 <6>[ 19.743062] remoteproc remoteproc0: scp is available
11006 22:17:00.225427 <3>[ 19.750708] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11007 22:17:00.235682 <4>[ 19.756359] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
11008 22:17:00.242292 <3>[ 19.764053] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11009 22:17:00.249045 <6>[ 19.773774] remoteproc remoteproc0: powering up scp
11010 22:17:00.259071 <4>[ 19.773807] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
11011 22:17:00.265573 <3>[ 19.773813] remoteproc remoteproc0: request_firmware failed: -2
11012 22:17:00.271639 <3>[ 19.781935] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11013 22:17:00.278363 <6>[ 19.808839] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
11014 22:17:00.288161 <3>[ 19.811106] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11015 22:17:00.294891 <6>[ 19.812769] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
11016 22:17:00.305026 <6>[ 19.818700] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
11017 22:17:00.308579 <6>[ 19.820658] mc: Linux media interface: v0.10
11018 22:17:00.318635 <3>[ 19.826753] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11019 22:17:00.324802 <3>[ 19.826933] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11020 22:17:00.334917 <6>[ 19.834435] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
11021 22:17:00.342424 <3>[ 19.843197] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11022 22:17:00.349206 <6>[ 19.846493] usbcore: registered new interface driver r8152
11023 22:17:00.356128 <4>[ 19.852311] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
11024 22:17:00.362659 <4>[ 19.852311] Fallback method does not support PEC.
11025 22:17:00.369190 <4>[ 19.854681] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
11026 22:17:00.375973 <4>[ 19.855108] elants_i2c 4-0010: supply vccio not found, using dummy regulator
11027 22:17:00.382241 <3>[ 19.855772] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11028 22:17:00.392245 <3>[ 19.855779] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11029 22:17:00.399664 <3>[ 19.860511] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11030 22:17:00.406775 <6>[ 19.877096] videodev: Linux video capture interface: v2.00
11031 22:17:00.413019 <3>[ 19.880902] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11032 22:17:00.422904 <3>[ 19.888176] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11033 22:17:00.429509 <3>[ 19.900612] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11034 22:17:00.440285 <6>[ 19.915193] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
11035 22:17:00.449937 <3>[ 19.922954] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11036 22:17:00.457129 <3>[ 19.922966] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11037 22:17:00.466526 <3>[ 19.923240] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11038 22:17:00.473788 <6>[ 19.935278] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
11039 22:17:00.483572 <6>[ 19.944683] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
11040 22:17:00.490278 <6>[ 19.966441] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
11041 22:17:00.499829 <6>[ 19.967735] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
11042 22:17:00.503241 <6>[ 19.967743] pci_bus 0000:00: root bus resource [bus 00-ff]
11043 22:17:00.510461 <6>[ 19.967754] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
11044 22:17:00.521317 <6>[ 19.967760] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
11045 22:17:00.528095 <6>[ 19.967795] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
11046 22:17:00.534391 <6>[ 19.967821] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
11047 22:17:00.537790 <6>[ 19.967911] pci 0000:00:00.0: supports D1 D2
11048 22:17:00.548405 <6>[ 19.967914] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
11049 22:17:00.555300 <6>[ 19.969479] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
11050 22:17:00.562387 <6>[ 19.969581] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
11051 22:17:00.569488 <6>[ 19.969612] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
11052 22:17:00.576631 <6>[ 19.969632] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
11053 22:17:00.583548 <6>[ 19.969651] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
11054 22:17:00.586977 <6>[ 19.969764] pci 0000:01:00.0: supports D1 D2
11055 22:17:00.593195 <6>[ 19.969767] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
11056 22:17:00.603424 <3>[ 19.974967] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11057 22:17:00.610596 <6>[ 19.980132] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
11058 22:17:00.617437 <6>[ 20.005226] usbcore: registered new interface driver cdc_ether
11059 22:17:00.624228 <4>[ 20.007947] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
11060 22:17:00.634330 <4>[ 20.007961] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
11061 22:17:00.640623 <6>[ 20.013665] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
11062 22:17:00.647492 <6>[ 20.021699] Bluetooth: Core ver 2.22
11063 22:17:00.653595 <6>[ 20.030241] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
11064 22:17:00.661019 <6>[ 20.030322] usbcore: registered new interface driver r8153_ecm
11065 22:17:00.664206 <6>[ 20.037061] NET: Registered PF_BLUETOOTH protocol family
11066 22:17:00.674069 <6>[ 20.042720] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
11067 22:17:00.681404 <6>[ 20.043014] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
11068 22:17:00.695191 <6>[ 20.044350] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
11069 22:17:00.698279 <6>[ 20.044492] usbcore: registered new interface driver uvcvideo
11070 22:17:00.705092 <6>[ 20.050341] Bluetooth: HCI device and connection manager initialized
11071 22:17:00.712283 <6>[ 20.059782] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
11072 22:17:00.722179 <3>[ 20.060544] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11073 22:17:00.728769 <6>[ 20.066073] Bluetooth: HCI socket layer initialized
11074 22:17:00.732472 <6>[ 20.070462] r8152 2-1.3:1.0 eth0: v1.12.13
11075 22:17:00.739413 <6>[ 20.073525] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
11076 22:17:00.746009 <6>[ 20.078055] Bluetooth: L2CAP socket layer initialized
11077 22:17:00.753412 <6>[ 20.078866] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
11078 22:17:00.756776 <6>[ 20.083363] remoteproc remoteproc0: powering up scp
11079 22:17:00.767119 <4>[ 20.083415] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
11080 22:17:00.773672 <3>[ 20.083424] remoteproc remoteproc0: request_firmware failed: -2
11081 22:17:00.781313 <3>[ 20.083427] fops_vcodec_open(),166: [MTK_V4L2][ERROR] vpu_load_firmware failed!
11082 22:17:00.787794 <6>[ 20.084077] r8152 2-1.3:1.0 enx00e04c787aaa: renamed from eth0
11083 22:17:00.790739 <6>[ 20.084924] pci 0000:00:00.0: PCI bridge to [bus 01]
11084 22:17:00.797686 <6>[ 20.093191] Bluetooth: SCO socket layer initialized
11085 22:17:00.804152 <3>[ 20.094538] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
11086 22:17:00.814128 <3>[ 20.095362] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11087 22:17:00.820602 <6>[ 20.099426] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
11088 22:17:00.830731 <3>[ 20.099914] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11089 22:17:00.840547 <3>[ 20.119933] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11090 22:17:00.847473 <6>[ 20.122114] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
11091 22:17:00.854390 <3>[ 20.149174] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11092 22:17:00.860519 <6>[ 20.156333] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
11093 22:17:00.867227 <6>[ 20.164925] usbcore: registered new interface driver btusb
11094 22:17:00.873628 <6>[ 20.172559] pcieport 0000:00:00.0: AER: enabled with IRQ 283
11095 22:17:00.883513 <4>[ 20.180709] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
11096 22:17:00.893483 <3>[ 20.199534] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11097 22:17:00.896799 <3>[ 20.203939] Bluetooth: hci0: Failed to load firmware file (-2)
11098 22:17:00.903532 <3>[ 20.203946] Bluetooth: hci0: Failed to set up firmware (-2)
11099 22:17:00.913450 <5>[ 20.207443] cfg80211: Loading compiled-in X.509 certificates for regulatory database
11100 22:17:00.919869 <5>[ 20.218875] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
11101 22:17:00.930079 <4>[ 20.218987] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
11102 22:17:00.936187 <4>[ 20.231464] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
11103 22:17:00.947212 <3>[ 20.233887] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11104 22:17:00.953033 <6>[ 20.332219] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
11105 22:17:00.960147 <6>[ 20.335293] cfg80211: failed to load regulatory.db
11106 22:17:00.966375 <6>[ 20.344160] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
11107 22:17:00.973072 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
11108 22:17:00.992584 [[0;32m OK [0m] Reached targ<6>[ 20.524411] mt7921e 0000:01:00.0: ASIC revision: 79610010
11109 22:17:00.995462 et [0;1;39mSystem Time Set[0m.
11110 22:17:01.011989 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
11111 22:17:01.060779 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
11112 22:17:01.083897 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
11113 22:17:01.099943 <4>[ 20.626978] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11114 22:17:01.216919 <4>[ 20.744537] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11115 22:17:01.265267 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
11116 22:17:01.280488 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
11117 22:17:01.300370 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
11118 22:17:01.316061 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
11119 22:17:01.322252 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
11120 22:17:01.337385 <4>[ 20.865249] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11121 22:17:01.348489 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
11122 22:17:01.364528 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
11123 22:17:01.380903 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
11124 22:17:01.400073 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
11125 22:17:01.441696 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
11126 22:17:01.457663 <4>[ 20.985404] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11127 22:17:01.479495 Starting [0;1;39mUser Login Management[0m...
11128 22:17:01.498741 Starting [0;1;39mPermit User Sessions[0m...
11129 22:17:01.518103 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
11130 22:17:01.541100 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
11131 22:17:01.581389 [[0;32m OK [<4>[ 21.109571] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11132 22:17:01.588034 0m] Started [0;1;39mSerial Getty on ttyS0[0m.
11133 22:17:01.594447 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
11134 22:17:01.611864 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
11135 22:17:01.633227 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
11136 22:17:01.649858 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
11137 22:17:01.669287 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
11138 22:17:01.685854 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
11139 22:17:01.701682 <4>[ 21.229001] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11140 22:17:01.756783 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
11141 22:17:01.784322 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
11142 22:17:01.800822
11143 22:17:01.800908
11144 22:17:01.803565 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
11145 22:17:01.803648
11146 22:17:01.806914 debian-bullseye-arm64 login: root (automatic login)
11147 22:17:01.806998
11148 22:17:01.807063
11149 22:17:01.823824 <4>[ 21.351399] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11150 22:17:01.830434 Linux debian-bullseye-arm64 6.1.31 #1 SMP PREEMPT Mon Jun 5 22:04:07 UTC 2023 aarch64
11151 22:17:01.830520
11152 22:17:01.837026 The programs included with the Debian GNU/Linux system are free software;
11153 22:17:01.843654 the exact distribution terms for each program are described in the
11154 22:17:01.846989 individual files in /usr/share/doc/*/copyright.
11155 22:17:01.847071
11156 22:17:01.853901 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11157 22:17:01.857382 permitted by applicable law.
11158 22:17:01.857951 Matched prompt #10: / #
11160 22:17:01.858352 Setting prompt string to ['/ #']
11161 22:17:01.858504 end: 2.2.5.1 login-action (duration 00:00:22) [common]
11163 22:17:01.858899 end: 2.2.5 auto-login-action (duration 00:00:22) [common]
11164 22:17:01.859045 start: 2.2.6 expect-shell-connection (timeout 00:02:56) [common]
11165 22:17:01.859174 Setting prompt string to ['/ #']
11166 22:17:01.859286 Forcing a shell prompt, looking for ['/ #']
11168 22:17:01.909741 / #
11169 22:17:01.910348 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11170 22:17:01.910739 Waiting using forced prompt support (timeout 00:02:30)
11171 22:17:01.915426
11172 22:17:01.916175 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11173 22:17:01.916640 start: 2.2.7 export-device-env (timeout 00:02:56) [common]
11174 22:17:01.917099 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11175 22:17:01.917534 end: 2.2 depthcharge-retry (duration 00:02:04) [common]
11176 22:17:01.917966 end: 2 depthcharge-action (duration 00:02:04) [common]
11177 22:17:01.918391 start: 3 lava-test-retry (timeout 00:05:00) [common]
11178 22:17:01.918803 start: 3.1 lava-test-shell (timeout 00:05:00) [common]
11179 22:17:01.919179 Using namespace: common
11181 22:17:02.020156 / # #
11182 22:17:02.020427 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:05:00)
11183 22:17:02.020626 <4>[ 21.472829] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11184 22:17:02.026296 #
11185 22:17:02.026657 Using /lava-10597240
11187 22:17:02.127192 / # export SHELL=/bin/sh
11188 22:17:02.128008 <4>[ 21.593045] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11189 22:17:02.133413 export SHELL=/bin/sh
11191 22:17:02.234722 / # . /lava-10597240/environment
11192 22:17:02.234918 <4>[ 21.712560] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11193 22:17:02.240461 . /lava-10597240/environment
11195 22:17:02.341015 / # /lava-10597240/bin/lava-test-runner /lava-10597240/0
11196 22:17:02.341219 Test shell timeout: 10s (minimum of the action and connection timeout)
11197 22:17:02.341682 <3>[ 21.830720] mt7921e 0000:01:00.0: hardware init failed
11198 22:17:02.346469 /lava-10597240/bin/lava-test-run /lava-10597240/0
11199 22:17:02.349723 -sh: 5: /lava-10597240/bin/lava-test-run: not found
11200 22:17:28.662540 / # <6>[ 48.202769] vpu: disabling
11201 22:17:28.665670 <6>[ 48.205849] vproc2: disabling
11202 22:17:28.669322 <6>[ 48.209125] vproc1: disabling
11203 22:17:28.672940 <6>[ 48.212386] vaud18: disabling
11204 22:17:28.679212 <6>[ 48.215791] vsram_others: disabling
11205 22:17:28.679663 <6>[ 48.219664] va09: disabling
11206 22:17:28.685617 <6>[ 48.222767] vsram_md: disabling
11207 22:17:28.686043 <6>[ 48.226251] Vgpu: disabling
11209 22:22:01.919774 end: 3.1 lava-test-shell (duration 00:05:00) [common]
11211 22:22:01.921706 lava-test-retry failed: 1 of 1 attempts. 'lava-test-shell timed out after 300 seconds'
11213 22:22:01.922542 end: 3 lava-test-retry (duration 00:05:00) [common]
11215 22:22:01.923738 Cleaning after the job
11216 22:22:01.924198 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10597240/tftp-deploy-g8u9ngxh/ramdisk
11217 22:22:01.962607 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10597240/tftp-deploy-g8u9ngxh/kernel
11218 22:22:01.983423 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10597240/tftp-deploy-g8u9ngxh/dtb
11219 22:22:01.983648 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10597240/tftp-deploy-g8u9ngxh/modules
11220 22:22:01.988943 start: 4.1 power-off (timeout 00:00:30) [common]
11221 22:22:01.989122 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=off'
11222 22:22:02.059361 >> Command sent successfully.
11223 22:22:02.063212 Returned 0 in 0 seconds
11224 22:22:02.164049 end: 4.1 power-off (duration 00:00:00) [common]
11226 22:22:02.165695 start: 4.2 read-feedback (timeout 00:10:00) [common]
11227 22:22:02.167000 Listened to connection for namespace 'common' for up to 1s
11228 22:22:03.167529 Finalising connection for namespace 'common'
11229 22:22:03.168227 Disconnecting from shell: Finalise
11230 22:22:03.269243 end: 4.2 read-feedback (duration 00:00:01) [common]
11231 22:22:03.269848 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/10597240
11232 22:22:03.429695 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/10597240
11233 22:22:03.429874 TestError: A test failed to run, look at the error message.