Boot log: mt8192-asurada-spherion-r0
- Errors: 2
- Kernel Errors: 30
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 22
1 22:13:29.697343 lava-dispatcher, installed at version: 2023.05.1
2 22:13:29.697551 start: 0 validate
3 22:13:29.697683 Start time: 2023-06-05 22:13:29.697676+00:00 (UTC)
4 22:13:29.697811 Using caching service: 'http://localhost/cache/?uri=%s'
5 22:13:29.697942 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230527.0%2Farm64%2Frootfs.cpio.gz exists
6 22:13:30.001293 Using caching service: 'http://localhost/cache/?uri=%s'
7 22:13:30.002100 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1314-g1ab0ac1d7e2e3%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 22:13:30.300932 Using caching service: 'http://localhost/cache/?uri=%s'
9 22:13:30.301751 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1314-g1ab0ac1d7e2e3%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 22:13:56.960974 Using caching service: 'http://localhost/cache/?uri=%s'
11 22:13:56.962016 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1314-g1ab0ac1d7e2e3%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 22:13:57.569662 validate duration: 27.87
14 22:13:57.569923 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 22:13:57.570021 start: 1.1 download-retry (timeout 00:10:00) [common]
16 22:13:57.570109 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 22:13:57.570233 Not decompressing ramdisk as can be used compressed.
18 22:13:57.570321 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230527.0/arm64/rootfs.cpio.gz
19 22:13:57.570388 saving as /var/lib/lava/dispatcher/tmp/10597232/tftp-deploy-73mp9zex/ramdisk/rootfs.cpio.gz
20 22:13:57.570450 total size: 8186575 (7MB)
21 22:14:00.747667 progress 0% (0MB)
22 22:14:00.753267 progress 5% (0MB)
23 22:14:00.755289 progress 10% (0MB)
24 22:14:00.757577 progress 15% (1MB)
25 22:14:00.759569 progress 20% (1MB)
26 22:14:00.761815 progress 25% (1MB)
27 22:14:00.763830 progress 30% (2MB)
28 22:14:00.766064 progress 35% (2MB)
29 22:14:00.768045 progress 40% (3MB)
30 22:14:00.770265 progress 45% (3MB)
31 22:14:00.772280 progress 50% (3MB)
32 22:14:00.774451 progress 55% (4MB)
33 22:14:00.776436 progress 60% (4MB)
34 22:14:00.778584 progress 65% (5MB)
35 22:14:00.780558 progress 70% (5MB)
36 22:14:00.782694 progress 75% (5MB)
37 22:14:00.784638 progress 80% (6MB)
38 22:14:00.786774 progress 85% (6MB)
39 22:14:00.788718 progress 90% (7MB)
40 22:14:00.790887 progress 95% (7MB)
41 22:14:00.792920 progress 100% (7MB)
42 22:14:00.793163 7MB downloaded in 3.22s (2.42MB/s)
43 22:14:00.793309 end: 1.1.1 http-download (duration 00:00:03) [common]
45 22:14:00.793552 end: 1.1 download-retry (duration 00:00:03) [common]
46 22:14:00.793640 start: 1.2 download-retry (timeout 00:09:57) [common]
47 22:14:00.793727 start: 1.2.1 http-download (timeout 00:09:57) [common]
48 22:14:00.793858 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1314-g1ab0ac1d7e2e3/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 22:14:00.793946 saving as /var/lib/lava/dispatcher/tmp/10597232/tftp-deploy-73mp9zex/kernel/Image
50 22:14:00.794011 total size: 45746688 (43MB)
51 22:14:00.794087 No compression specified
52 22:14:00.795294 progress 0% (0MB)
53 22:14:00.806565 progress 5% (2MB)
54 22:14:00.818006 progress 10% (4MB)
55 22:14:00.829311 progress 15% (6MB)
56 22:14:00.840560 progress 20% (8MB)
57 22:14:00.851962 progress 25% (10MB)
58 22:14:00.863306 progress 30% (13MB)
59 22:14:00.874755 progress 35% (15MB)
60 22:14:00.886140 progress 40% (17MB)
61 22:14:00.897697 progress 45% (19MB)
62 22:14:00.909261 progress 50% (21MB)
63 22:14:00.920552 progress 55% (24MB)
64 22:14:00.931881 progress 60% (26MB)
65 22:14:00.943197 progress 65% (28MB)
66 22:14:00.954606 progress 70% (30MB)
67 22:14:00.966187 progress 75% (32MB)
68 22:14:00.977629 progress 80% (34MB)
69 22:14:00.989051 progress 85% (37MB)
70 22:14:01.000392 progress 90% (39MB)
71 22:14:01.011713 progress 95% (41MB)
72 22:14:01.022746 progress 100% (43MB)
73 22:14:01.022866 43MB downloaded in 0.23s (190.64MB/s)
74 22:14:01.023013 end: 1.2.1 http-download (duration 00:00:00) [common]
76 22:14:01.023246 end: 1.2 download-retry (duration 00:00:00) [common]
77 22:14:01.023339 start: 1.3 download-retry (timeout 00:09:57) [common]
78 22:14:01.023428 start: 1.3.1 http-download (timeout 00:09:57) [common]
79 22:14:01.023568 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1314-g1ab0ac1d7e2e3/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 22:14:01.023640 saving as /var/lib/lava/dispatcher/tmp/10597232/tftp-deploy-73mp9zex/dtb/mt8192-asurada-spherion-r0.dtb
81 22:14:01.023702 total size: 46924 (0MB)
82 22:14:01.023763 No compression specified
83 22:14:01.024865 progress 69% (0MB)
84 22:14:01.025129 progress 100% (0MB)
85 22:14:01.025284 0MB downloaded in 0.00s (28.34MB/s)
86 22:14:01.025403 end: 1.3.1 http-download (duration 00:00:00) [common]
88 22:14:01.025625 end: 1.3 download-retry (duration 00:00:00) [common]
89 22:14:01.025710 start: 1.4 download-retry (timeout 00:09:57) [common]
90 22:14:01.025793 start: 1.4.1 http-download (timeout 00:09:57) [common]
91 22:14:01.025899 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1314-g1ab0ac1d7e2e3/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 22:14:01.025970 saving as /var/lib/lava/dispatcher/tmp/10597232/tftp-deploy-73mp9zex/modules/modules.tar
93 22:14:01.026032 total size: 8543056 (8MB)
94 22:14:01.026092 Using unxz to decompress xz
95 22:14:01.029516 progress 0% (0MB)
96 22:14:01.050816 progress 5% (0MB)
97 22:14:01.075418 progress 10% (0MB)
98 22:14:01.100518 progress 15% (1MB)
99 22:14:01.125053 progress 20% (1MB)
100 22:14:01.147586 progress 25% (2MB)
101 22:14:01.173301 progress 30% (2MB)
102 22:14:01.197618 progress 35% (2MB)
103 22:14:01.221511 progress 40% (3MB)
104 22:14:01.244380 progress 45% (3MB)
105 22:14:01.268196 progress 50% (4MB)
106 22:14:01.290559 progress 55% (4MB)
107 22:14:01.314752 progress 60% (4MB)
108 22:14:01.339365 progress 65% (5MB)
109 22:14:01.363199 progress 70% (5MB)
110 22:14:01.385581 progress 75% (6MB)
111 22:14:01.408711 progress 80% (6MB)
112 22:14:01.433152 progress 85% (6MB)
113 22:14:01.461430 progress 90% (7MB)
114 22:14:01.485775 progress 95% (7MB)
115 22:14:01.509248 progress 100% (8MB)
116 22:14:01.515196 8MB downloaded in 0.49s (16.66MB/s)
117 22:14:01.515473 end: 1.4.1 http-download (duration 00:00:00) [common]
119 22:14:01.515736 end: 1.4 download-retry (duration 00:00:00) [common]
120 22:14:01.515830 start: 1.5 prepare-tftp-overlay (timeout 00:09:56) [common]
121 22:14:01.515926 start: 1.5.1 extract-nfsrootfs (timeout 00:09:56) [common]
122 22:14:01.516008 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 22:14:01.516095 start: 1.5.2 lava-overlay (timeout 00:09:56) [common]
124 22:14:01.516317 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/10597232/lava-overlay-pic6tc_6
125 22:14:01.516446 makedir: /var/lib/lava/dispatcher/tmp/10597232/lava-overlay-pic6tc_6/lava-10597232/bin
126 22:14:01.516548 makedir: /var/lib/lava/dispatcher/tmp/10597232/lava-overlay-pic6tc_6/lava-10597232/tests
127 22:14:01.516644 makedir: /var/lib/lava/dispatcher/tmp/10597232/lava-overlay-pic6tc_6/lava-10597232/results
128 22:14:01.516755 Creating /var/lib/lava/dispatcher/tmp/10597232/lava-overlay-pic6tc_6/lava-10597232/bin/lava-add-keys
129 22:14:01.516939 Creating /var/lib/lava/dispatcher/tmp/10597232/lava-overlay-pic6tc_6/lava-10597232/bin/lava-add-sources
130 22:14:01.517064 Creating /var/lib/lava/dispatcher/tmp/10597232/lava-overlay-pic6tc_6/lava-10597232/bin/lava-background-process-start
131 22:14:01.517212 Creating /var/lib/lava/dispatcher/tmp/10597232/lava-overlay-pic6tc_6/lava-10597232/bin/lava-background-process-stop
132 22:14:01.517335 Creating /var/lib/lava/dispatcher/tmp/10597232/lava-overlay-pic6tc_6/lava-10597232/bin/lava-common-functions
133 22:14:01.517455 Creating /var/lib/lava/dispatcher/tmp/10597232/lava-overlay-pic6tc_6/lava-10597232/bin/lava-echo-ipv4
134 22:14:01.517574 Creating /var/lib/lava/dispatcher/tmp/10597232/lava-overlay-pic6tc_6/lava-10597232/bin/lava-install-packages
135 22:14:01.517694 Creating /var/lib/lava/dispatcher/tmp/10597232/lava-overlay-pic6tc_6/lava-10597232/bin/lava-installed-packages
136 22:14:01.517812 Creating /var/lib/lava/dispatcher/tmp/10597232/lava-overlay-pic6tc_6/lava-10597232/bin/lava-os-build
137 22:14:01.517931 Creating /var/lib/lava/dispatcher/tmp/10597232/lava-overlay-pic6tc_6/lava-10597232/bin/lava-probe-channel
138 22:14:01.518048 Creating /var/lib/lava/dispatcher/tmp/10597232/lava-overlay-pic6tc_6/lava-10597232/bin/lava-probe-ip
139 22:14:01.518165 Creating /var/lib/lava/dispatcher/tmp/10597232/lava-overlay-pic6tc_6/lava-10597232/bin/lava-target-ip
140 22:14:01.518282 Creating /var/lib/lava/dispatcher/tmp/10597232/lava-overlay-pic6tc_6/lava-10597232/bin/lava-target-mac
141 22:14:01.518399 Creating /var/lib/lava/dispatcher/tmp/10597232/lava-overlay-pic6tc_6/lava-10597232/bin/lava-target-storage
142 22:14:01.518524 Creating /var/lib/lava/dispatcher/tmp/10597232/lava-overlay-pic6tc_6/lava-10597232/bin/lava-test-case
143 22:14:01.518643 Creating /var/lib/lava/dispatcher/tmp/10597232/lava-overlay-pic6tc_6/lava-10597232/bin/lava-test-event
144 22:14:01.518762 Creating /var/lib/lava/dispatcher/tmp/10597232/lava-overlay-pic6tc_6/lava-10597232/bin/lava-test-feedback
145 22:14:01.518880 Creating /var/lib/lava/dispatcher/tmp/10597232/lava-overlay-pic6tc_6/lava-10597232/bin/lava-test-raise
146 22:14:01.519000 Creating /var/lib/lava/dispatcher/tmp/10597232/lava-overlay-pic6tc_6/lava-10597232/bin/lava-test-reference
147 22:14:01.519121 Creating /var/lib/lava/dispatcher/tmp/10597232/lava-overlay-pic6tc_6/lava-10597232/bin/lava-test-runner
148 22:14:01.519259 Creating /var/lib/lava/dispatcher/tmp/10597232/lava-overlay-pic6tc_6/lava-10597232/bin/lava-test-set
149 22:14:01.519380 Creating /var/lib/lava/dispatcher/tmp/10597232/lava-overlay-pic6tc_6/lava-10597232/bin/lava-test-shell
150 22:14:01.519504 Updating /var/lib/lava/dispatcher/tmp/10597232/lava-overlay-pic6tc_6/lava-10597232/bin/lava-install-packages (oe)
151 22:14:01.519653 Updating /var/lib/lava/dispatcher/tmp/10597232/lava-overlay-pic6tc_6/lava-10597232/bin/lava-installed-packages (oe)
152 22:14:01.519770 Creating /var/lib/lava/dispatcher/tmp/10597232/lava-overlay-pic6tc_6/lava-10597232/environment
153 22:14:01.519868 LAVA metadata
154 22:14:01.519941 - LAVA_JOB_ID=10597232
155 22:14:01.520006 - LAVA_DISPATCHER_IP=192.168.201.1
156 22:14:01.520106 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:56) [common]
157 22:14:01.520176 skipped lava-vland-overlay
158 22:14:01.520250 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 22:14:01.520331 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:56) [common]
160 22:14:01.520393 skipped lava-multinode-overlay
161 22:14:01.520469 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 22:14:01.520551 start: 1.5.2.3 test-definition (timeout 00:09:56) [common]
163 22:14:01.520626 Loading test definitions
164 22:14:01.520716 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:56) [common]
165 22:14:01.520812 Using /lava-10597232 at stage 0
166 22:14:01.521128 uuid=10597232_1.5.2.3.1 testdef=None
167 22:14:01.521227 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 22:14:01.521312 start: 1.5.2.3.2 test-overlay (timeout 00:09:56) [common]
169 22:14:01.521827 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 22:14:01.522050 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:56) [common]
172 22:14:01.522662 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 22:14:01.522893 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:56) [common]
175 22:14:01.523759 runner path: /var/lib/lava/dispatcher/tmp/10597232/lava-overlay-pic6tc_6/lava-10597232/0/tests/0_dmesg test_uuid 10597232_1.5.2.3.1
176 22:14:01.523911 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 22:14:01.524135 start: 1.5.2.3.5 inline-repo-action (timeout 00:09:56) [common]
179 22:14:01.524206 Using /lava-10597232 at stage 1
180 22:14:01.524492 uuid=10597232_1.5.2.3.5 testdef=None
181 22:14:01.524580 end: 1.5.2.3.5 inline-repo-action (duration 00:00:00) [common]
182 22:14:01.524665 start: 1.5.2.3.6 test-overlay (timeout 00:09:56) [common]
183 22:14:01.525173 end: 1.5.2.3.6 test-overlay (duration 00:00:00) [common]
185 22:14:01.525430 start: 1.5.2.3.7 test-install-overlay (timeout 00:09:56) [common]
186 22:14:01.526489 end: 1.5.2.3.7 test-install-overlay (duration 00:00:00) [common]
188 22:14:01.526716 start: 1.5.2.3.8 test-runscript-overlay (timeout 00:09:56) [common]
189 22:14:01.527341 runner path: /var/lib/lava/dispatcher/tmp/10597232/lava-overlay-pic6tc_6/lava-10597232/1/tests/1_bootrr test_uuid 10597232_1.5.2.3.5
190 22:14:01.527486 end: 1.5.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
192 22:14:01.527692 Creating lava-test-runner.conf files
193 22:14:01.527756 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10597232/lava-overlay-pic6tc_6/lava-10597232/0 for stage 0
194 22:14:01.527843 - 0_dmesg
195 22:14:01.527924 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10597232/lava-overlay-pic6tc_6/lava-10597232/1 for stage 1
196 22:14:01.528012 - 1_bootrr
197 22:14:01.528103 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
198 22:14:01.528187 start: 1.5.2.4 compress-overlay (timeout 00:09:56) [common]
199 22:14:01.535987 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
200 22:14:01.536092 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:56) [common]
201 22:14:01.536180 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
202 22:14:01.536266 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
203 22:14:01.536352 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:56) [common]
204 22:14:01.762824 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:00) [common]
205 22:14:01.763214 start: 1.5.4 extract-modules (timeout 00:09:56) [common]
206 22:14:01.763362 extracting modules file /var/lib/lava/dispatcher/tmp/10597232/tftp-deploy-73mp9zex/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10597232/extract-overlay-ramdisk-b55piubj/ramdisk
207 22:14:01.956887 end: 1.5.4 extract-modules (duration 00:00:00) [common]
208 22:14:01.957062 start: 1.5.5 apply-overlay-tftp (timeout 00:09:56) [common]
209 22:14:01.957159 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10597232/compress-overlay-_31hvzfn/overlay-1.5.2.4.tar.gz to ramdisk
210 22:14:01.957230 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10597232/compress-overlay-_31hvzfn/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/10597232/extract-overlay-ramdisk-b55piubj/ramdisk
211 22:14:01.965017 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
212 22:14:01.965126 start: 1.5.6 configure-preseed-file (timeout 00:09:56) [common]
213 22:14:01.965216 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
214 22:14:01.965299 start: 1.5.7 compress-ramdisk (timeout 00:09:56) [common]
215 22:14:01.965376 Building ramdisk /var/lib/lava/dispatcher/tmp/10597232/extract-overlay-ramdisk-b55piubj/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/10597232/extract-overlay-ramdisk-b55piubj/ramdisk
216 22:14:02.325619 >> 143719 blocks
217 22:14:04.586681 rename /var/lib/lava/dispatcher/tmp/10597232/extract-overlay-ramdisk-b55piubj/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/10597232/tftp-deploy-73mp9zex/ramdisk/ramdisk.cpio.gz
218 22:14:04.587106 end: 1.5.7 compress-ramdisk (duration 00:00:03) [common]
219 22:14:04.587230 start: 1.5.8 prepare-kernel (timeout 00:09:53) [common]
220 22:14:04.587334 start: 1.5.8.1 prepare-fit (timeout 00:09:53) [common]
221 22:14:04.587439 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/10597232/tftp-deploy-73mp9zex/kernel/Image'
222 22:14:15.682656 Returned 0 in 11 seconds
223 22:14:15.783712 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/10597232/tftp-deploy-73mp9zex/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/10597232/tftp-deploy-73mp9zex/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/10597232/tftp-deploy-73mp9zex/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/10597232/tftp-deploy-73mp9zex/kernel/image.itb
224 22:14:16.187172 output: FIT description: Kernel Image image with one or more FDT blobs
225 22:14:16.187524 output: Created: Mon Jun 5 23:14:16 2023
226 22:14:16.187600 output: Image 0 (kernel-1)
227 22:14:16.187662 output: Description:
228 22:14:16.187726 output: Created: Mon Jun 5 23:14:16 2023
229 22:14:16.187788 output: Type: Kernel Image
230 22:14:16.187852 output: Compression: lzma compressed
231 22:14:16.187913 output: Data Size: 10082307 Bytes = 9846.00 KiB = 9.62 MiB
232 22:14:16.187976 output: Architecture: AArch64
233 22:14:16.188035 output: OS: Linux
234 22:14:16.188091 output: Load Address: 0x00000000
235 22:14:16.188148 output: Entry Point: 0x00000000
236 22:14:16.188207 output: Hash algo: crc32
237 22:14:16.188260 output: Hash value: c242daf7
238 22:14:16.188313 output: Image 1 (fdt-1)
239 22:14:16.188365 output: Description: mt8192-asurada-spherion-r0
240 22:14:16.188422 output: Created: Mon Jun 5 23:14:16 2023
241 22:14:16.188525 output: Type: Flat Device Tree
242 22:14:16.188621 output: Compression: uncompressed
243 22:14:16.188675 output: Data Size: 46924 Bytes = 45.82 KiB = 0.04 MiB
244 22:14:16.188729 output: Architecture: AArch64
245 22:14:16.188813 output: Hash algo: crc32
246 22:14:16.188868 output: Hash value: 1df858fa
247 22:14:16.188922 output: Image 2 (ramdisk-1)
248 22:14:16.188974 output: Description: unavailable
249 22:14:16.189027 output: Created: Mon Jun 5 23:14:16 2023
250 22:14:16.189081 output: Type: RAMDisk Image
251 22:14:16.189134 output: Compression: Unknown Compression
252 22:14:16.189187 output: Data Size: 21234464 Bytes = 20736.78 KiB = 20.25 MiB
253 22:14:16.189240 output: Architecture: AArch64
254 22:14:16.189292 output: OS: Linux
255 22:14:16.189344 output: Load Address: unavailable
256 22:14:16.189397 output: Entry Point: unavailable
257 22:14:16.189449 output: Hash algo: crc32
258 22:14:16.189501 output: Hash value: 3430dd00
259 22:14:16.189553 output: Default Configuration: 'conf-1'
260 22:14:16.189606 output: Configuration 0 (conf-1)
261 22:14:16.189658 output: Description: mt8192-asurada-spherion-r0
262 22:14:16.189711 output: Kernel: kernel-1
263 22:14:16.189763 output: Init Ramdisk: ramdisk-1
264 22:14:16.189815 output: FDT: fdt-1
265 22:14:16.189867 output: Loadables: kernel-1
266 22:14:16.189919 output:
267 22:14:16.190097 end: 1.5.8.1 prepare-fit (duration 00:00:12) [common]
268 22:14:16.190191 end: 1.5.8 prepare-kernel (duration 00:00:12) [common]
269 22:14:16.190299 end: 1.5 prepare-tftp-overlay (duration 00:00:15) [common]
270 22:14:16.190400 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:41) [common]
271 22:14:16.190495 No LXC device requested
272 22:14:16.190573 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
273 22:14:16.190657 start: 1.7 deploy-device-env (timeout 00:09:41) [common]
274 22:14:16.190734 end: 1.7 deploy-device-env (duration 00:00:00) [common]
275 22:14:16.190803 Checking files for TFTP limit of 4294967296 bytes.
276 22:14:16.191276 end: 1 tftp-deploy (duration 00:00:19) [common]
277 22:14:16.191382 start: 2 depthcharge-action (timeout 00:05:00) [common]
278 22:14:16.191480 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
279 22:14:16.191602 substitutions:
280 22:14:16.191669 - {DTB}: 10597232/tftp-deploy-73mp9zex/dtb/mt8192-asurada-spherion-r0.dtb
281 22:14:16.191731 - {INITRD}: 10597232/tftp-deploy-73mp9zex/ramdisk/ramdisk.cpio.gz
282 22:14:16.191790 - {KERNEL}: 10597232/tftp-deploy-73mp9zex/kernel/Image
283 22:14:16.191848 - {LAVA_MAC}: None
284 22:14:16.191905 - {PRESEED_CONFIG}: None
285 22:14:16.191960 - {PRESEED_LOCAL}: None
286 22:14:16.192016 - {RAMDISK}: 10597232/tftp-deploy-73mp9zex/ramdisk/ramdisk.cpio.gz
287 22:14:16.192071 - {ROOT_PART}: None
288 22:14:16.192125 - {ROOT}: None
289 22:14:16.192179 - {SERVER_IP}: 192.168.201.1
290 22:14:16.192233 - {TEE}: None
291 22:14:16.192287 Parsed boot commands:
292 22:14:16.192340 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
293 22:14:16.192558 Parsed boot commands: tftpboot 192.168.201.1 10597232/tftp-deploy-73mp9zex/kernel/image.itb 10597232/tftp-deploy-73mp9zex/kernel/cmdline
294 22:14:16.192645 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
295 22:14:16.192730 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
296 22:14:16.192863 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
297 22:14:16.192948 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
298 22:14:16.193022 Not connected, no need to disconnect.
299 22:14:16.193096 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
300 22:14:16.193179 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
301 22:14:16.193244 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost mt8192-asurada-spherion-r0-cbg-1'
302 22:14:16.196900 Setting prompt string to ['lava-test: # ']
303 22:14:16.197415 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
304 22:14:16.197521 end: 2.2.1 reset-connection (duration 00:00:00) [common]
305 22:14:16.197621 start: 2.2.2 reset-device (timeout 00:05:00) [common]
306 22:14:16.197713 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
307 22:14:16.197901 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=reboot'
308 22:14:21.348378 >> Command sent successfully.
309 22:14:21.359367 Returned 0 in 5 seconds
310 22:14:21.460686 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
312 22:14:21.462243 end: 2.2.2 reset-device (duration 00:00:05) [common]
313 22:14:21.462803 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
314 22:14:21.463284 Setting prompt string to 'Starting depthcharge on Spherion...'
315 22:14:21.463689 Changing prompt to 'Starting depthcharge on Spherion...'
316 22:14:21.464096 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
317 22:14:21.465434 [Enter `^Ec?' for help]
318 22:14:21.625418
319 22:14:21.625995
320 22:14:21.626353 F0: 102B 0000
321 22:14:21.626686
322 22:14:21.626999 F3: 1001 0000 [0200]
323 22:14:21.628858
324 22:14:21.629293 F3: 1001 0000
325 22:14:21.629647
326 22:14:21.629971 F7: 102D 0000
327 22:14:21.630288
328 22:14:21.632526 F1: 0000 0000
329 22:14:21.633027
330 22:14:21.633383 V0: 0000 0000 [0001]
331 22:14:21.633717
332 22:14:21.634031 00: 0007 8000
333 22:14:21.634357
334 22:14:21.636679 01: 0000 0000
335 22:14:21.637300
336 22:14:21.637667 BP: 0C00 0209 [0000]
337 22:14:21.638000
338 22:14:21.639723 G0: 1182 0000
339 22:14:21.640165
340 22:14:21.640519 EC: 0000 0021 [4000]
341 22:14:21.640878
342 22:14:21.643476 S7: 0000 0000 [0000]
343 22:14:21.644076
344 22:14:21.644441 CC: 0000 0000 [0001]
345 22:14:21.644800
346 22:14:21.646886 T0: 0000 0040 [010F]
347 22:14:21.647329
348 22:14:21.647682 Jump to BL
349 22:14:21.648021
350 22:14:21.671917
351 22:14:21.672489
352 22:14:21.672901
353 22:14:21.678875 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
354 22:14:21.682385 ARM64: Exception handlers installed.
355 22:14:21.686264 ARM64: Testing exception
356 22:14:21.689274 ARM64: Done test exception
357 22:14:21.696634 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
358 22:14:21.707320 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
359 22:14:21.714313 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
360 22:14:21.724301 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
361 22:14:21.731233 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
362 22:14:21.737405 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
363 22:14:21.748966 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
364 22:14:21.756038 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
365 22:14:21.775896 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
366 22:14:21.778682 WDT: Last reset was cold boot
367 22:14:21.782141 SPI1(PAD0) initialized at 2873684 Hz
368 22:14:21.785681 SPI5(PAD0) initialized at 992727 Hz
369 22:14:21.788806 VBOOT: Loading verstage.
370 22:14:21.795436 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
371 22:14:21.798537 FMAP: Found "FLASH" version 1.1 at 0x20000.
372 22:14:21.801636 FMAP: base = 0x0 size = 0x800000 #areas = 25
373 22:14:21.805456 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
374 22:14:21.812425 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
375 22:14:21.818930 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
376 22:14:21.830364 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
377 22:14:21.830940
378 22:14:21.831326
379 22:14:21.840517 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
380 22:14:21.843572 ARM64: Exception handlers installed.
381 22:14:21.846878 ARM64: Testing exception
382 22:14:21.847383 ARM64: Done test exception
383 22:14:21.854137 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
384 22:14:21.856683 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
385 22:14:21.871086 Probing TPM: . done!
386 22:14:21.871673 TPM ready after 0 ms
387 22:14:21.878226 Connected to device vid:did:rid of 1ae0:0028:00
388 22:14:21.884590 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
389 22:14:21.888642 Initialized TPM device CR50 revision 0
390 22:14:21.955372 tlcl_send_startup: Startup return code is 0
391 22:14:21.955970 TPM: setup succeeded
392 22:14:21.966510 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
393 22:14:21.975636 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
394 22:14:21.985614 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
395 22:14:21.994850 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
396 22:14:21.998301 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
397 22:14:22.004293 in-header: 03 07 00 00 08 00 00 00
398 22:14:22.007574 in-data: aa e4 47 04 13 02 00 00
399 22:14:22.011034 Chrome EC: UHEPI supported
400 22:14:22.017437 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
401 22:14:22.020832 in-header: 03 ad 00 00 08 00 00 00
402 22:14:22.024688 in-data: 00 20 20 08 00 00 00 00
403 22:14:22.025225 Phase 1
404 22:14:22.028493 FMAP: area GBB found @ 3f5000 (12032 bytes)
405 22:14:22.035826 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
406 22:14:22.043359 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
407 22:14:22.046499 Recovery requested (1009000e)
408 22:14:22.054747 TPM: Extending digest for VBOOT: boot mode into PCR 0
409 22:14:22.060397 tlcl_extend: response is 0
410 22:14:22.070501 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
411 22:14:22.076566 tlcl_extend: response is 0
412 22:14:22.083325 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
413 22:14:22.104572 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
414 22:14:22.110264 BS: bootblock times (exec / console): total (unknown) / 148 ms
415 22:14:22.110843
416 22:14:22.111230
417 22:14:22.120344 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
418 22:14:22.123981 ARM64: Exception handlers installed.
419 22:14:22.124574 ARM64: Testing exception
420 22:14:22.127286 ARM64: Done test exception
421 22:14:22.149263 pmic_efuse_setting: Set efuses in 11 msecs
422 22:14:22.152471 pmwrap_interface_init: Select PMIF_VLD_RDY
423 22:14:22.160061 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
424 22:14:22.163286 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
425 22:14:22.166398 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
426 22:14:22.173384 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
427 22:14:22.176454 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
428 22:14:22.183996 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
429 22:14:22.187805 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
430 22:14:22.191115 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
431 22:14:22.194893 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
432 22:14:22.202347 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
433 22:14:22.206196 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
434 22:14:22.209322 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
435 22:14:22.216396 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
436 22:14:22.223271 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
437 22:14:22.225810 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
438 22:14:22.232853 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
439 22:14:22.236957 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
440 22:14:22.243639 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
441 22:14:22.250534 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
442 22:14:22.254097 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
443 22:14:22.261346 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
444 22:14:22.264861 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
445 22:14:22.271472 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
446 22:14:22.278073 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
447 22:14:22.281933 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
448 22:14:22.288133 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
449 22:14:22.294863 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
450 22:14:22.298611 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
451 22:14:22.301492 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
452 22:14:22.307915 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
453 22:14:22.314479 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
454 22:14:22.318232 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
455 22:14:22.324925 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
456 22:14:22.328132 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
457 22:14:22.331272 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
458 22:14:22.337772 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
459 22:14:22.344393 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
460 22:14:22.347349 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
461 22:14:22.350938 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
462 22:14:22.357639 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
463 22:14:22.361204 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
464 22:14:22.364526 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
465 22:14:22.368063 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
466 22:14:22.375867 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
467 22:14:22.378559 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
468 22:14:22.381900 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
469 22:14:22.388639 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
470 22:14:22.392069 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
471 22:14:22.395442 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
472 22:14:22.398505 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
473 22:14:22.405328 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
474 22:14:22.411780 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
475 22:14:22.421670 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
476 22:14:22.425039 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
477 22:14:22.432282 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
478 22:14:22.441686 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
479 22:14:22.445033 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
480 22:14:22.451901 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
481 22:14:22.455002 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
482 22:14:22.462043 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x7
483 22:14:22.468351 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
484 22:14:22.471798 [RTC]rtc_osc_init,62: osc32con val = 0xde70
485 22:14:22.475342 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
486 22:14:22.486215 [RTC]rtc_get_frequency_meter,154: input=15, output=773
487 22:14:22.495747 [RTC]rtc_get_frequency_meter,154: input=23, output=958
488 22:14:22.505051 [RTC]rtc_get_frequency_meter,154: input=19, output=865
489 22:14:22.514532 [RTC]rtc_get_frequency_meter,154: input=17, output=820
490 22:14:22.524005 [RTC]rtc_get_frequency_meter,154: input=16, output=795
491 22:14:22.527368 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
492 22:14:22.534757 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
493 22:14:22.537504 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
494 22:14:22.540636 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
495 22:14:22.544074 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
496 22:14:22.547551 ADC[4]: Raw value=903245 ID=7
497 22:14:22.550703 ADC[3]: Raw value=213179 ID=1
498 22:14:22.554479 RAM Code: 0x71
499 22:14:22.557997 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
500 22:14:22.560862 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
501 22:14:22.570509 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
502 22:14:22.577234 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
503 22:14:22.580497 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
504 22:14:22.583633 in-header: 03 07 00 00 08 00 00 00
505 22:14:22.587298 in-data: aa e4 47 04 13 02 00 00
506 22:14:22.590654 Chrome EC: UHEPI supported
507 22:14:22.597698 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
508 22:14:22.600855 in-header: 03 ed 00 00 08 00 00 00
509 22:14:22.603723 in-data: 80 20 60 08 00 00 00 00
510 22:14:22.607311 MRC: failed to locate region type 0.
511 22:14:22.613829 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
512 22:14:22.617219 DRAM-K: Running full calibration
513 22:14:22.620565 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
514 22:14:22.624103 header.status = 0x0
515 22:14:22.626919 header.version = 0x6 (expected: 0x6)
516 22:14:22.630328 header.size = 0xd00 (expected: 0xd00)
517 22:14:22.633470 header.flags = 0x0
518 22:14:22.636755 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
519 22:14:22.656079 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
520 22:14:22.663257 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
521 22:14:22.665787 dram_init: ddr_geometry: 2
522 22:14:22.669296 [EMI] MDL number = 2
523 22:14:22.669894 [EMI] Get MDL freq = 0
524 22:14:22.672909 dram_init: ddr_type: 0
525 22:14:22.673491 is_discrete_lpddr4: 1
526 22:14:22.675865 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
527 22:14:22.676358
528 22:14:22.676751
529 22:14:22.679177 [Bian_co] ETT version 0.0.0.1
530 22:14:22.683180 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
531 22:14:22.686088
532 22:14:22.690051 dramc_set_vcore_voltage set vcore to 650000
533 22:14:22.690543 Read voltage for 800, 4
534 22:14:22.694100 Vio18 = 0
535 22:14:22.694715 Vcore = 650000
536 22:14:22.695113 Vdram = 0
537 22:14:22.695473 Vddq = 0
538 22:14:22.697641 Vmddr = 0
539 22:14:22.698135 dram_init: config_dvfs: 1
540 22:14:22.705128 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
541 22:14:22.708793 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
542 22:14:22.711849 [SwImpedanceCal] DRVP=10, DRVN=17, ODTN=9
543 22:14:22.715523 freq_region=0, Reg: DRVP=10, DRVN=17, ODTN=9
544 22:14:22.719462 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
545 22:14:22.723147 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
546 22:14:22.726890 MEM_TYPE=3, freq_sel=18
547 22:14:22.730453 sv_algorithm_assistance_LP4_1600
548 22:14:22.734159 ============ PULL DRAM RESETB DOWN ============
549 22:14:22.737671 ========== PULL DRAM RESETB DOWN end =========
550 22:14:22.741100 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
551 22:14:22.744427 ===================================
552 22:14:22.747604 LPDDR4 DRAM CONFIGURATION
553 22:14:22.750916 ===================================
554 22:14:22.754480 EX_ROW_EN[0] = 0x0
555 22:14:22.755068 EX_ROW_EN[1] = 0x0
556 22:14:22.757647 LP4Y_EN = 0x0
557 22:14:22.758261 WORK_FSP = 0x0
558 22:14:22.761372 WL = 0x2
559 22:14:22.761956 RL = 0x2
560 22:14:22.764567 BL = 0x2
561 22:14:22.765188 RPST = 0x0
562 22:14:22.768310 RD_PRE = 0x0
563 22:14:22.768936 WR_PRE = 0x1
564 22:14:22.771141 WR_PST = 0x0
565 22:14:22.771728 DBI_WR = 0x0
566 22:14:22.774470 DBI_RD = 0x0
567 22:14:22.775060 OTF = 0x1
568 22:14:22.777887 ===================================
569 22:14:22.780826 ===================================
570 22:14:22.784597 ANA top config
571 22:14:22.787669 ===================================
572 22:14:22.790894 DLL_ASYNC_EN = 0
573 22:14:22.791480 ALL_SLAVE_EN = 1
574 22:14:22.794251 NEW_RANK_MODE = 1
575 22:14:22.797924 DLL_IDLE_MODE = 1
576 22:14:22.801589 LP45_APHY_COMB_EN = 1
577 22:14:22.802229 TX_ODT_DIS = 1
578 22:14:22.804892 NEW_8X_MODE = 1
579 22:14:22.808222 ===================================
580 22:14:22.812266 ===================================
581 22:14:22.815444 data_rate = 1600
582 22:14:22.819066 CKR = 1
583 22:14:22.819548 DQ_P2S_RATIO = 8
584 22:14:22.823446 ===================================
585 22:14:22.826480 CA_P2S_RATIO = 8
586 22:14:22.829534 DQ_CA_OPEN = 0
587 22:14:22.832916 DQ_SEMI_OPEN = 0
588 22:14:22.833508 CA_SEMI_OPEN = 0
589 22:14:22.836538 CA_FULL_RATE = 0
590 22:14:22.839622 DQ_CKDIV4_EN = 1
591 22:14:22.843157 CA_CKDIV4_EN = 1
592 22:14:22.846198 CA_PREDIV_EN = 0
593 22:14:22.849244 PH8_DLY = 0
594 22:14:22.849725 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
595 22:14:22.852928 DQ_AAMCK_DIV = 4
596 22:14:22.856322 CA_AAMCK_DIV = 4
597 22:14:22.859916 CA_ADMCK_DIV = 4
598 22:14:22.863158 DQ_TRACK_CA_EN = 0
599 22:14:22.866005 CA_PICK = 800
600 22:14:22.869618 CA_MCKIO = 800
601 22:14:22.870201 MCKIO_SEMI = 0
602 22:14:22.872870 PLL_FREQ = 3068
603 22:14:22.876269 DQ_UI_PI_RATIO = 32
604 22:14:22.879822 CA_UI_PI_RATIO = 0
605 22:14:22.882675 ===================================
606 22:14:22.886296 ===================================
607 22:14:22.889330 memory_type:LPDDR4
608 22:14:22.889915 GP_NUM : 10
609 22:14:22.892683 SRAM_EN : 1
610 22:14:22.893347 MD32_EN : 0
611 22:14:22.896038 ===================================
612 22:14:22.899869 [ANA_INIT] >>>>>>>>>>>>>>
613 22:14:22.903281 <<<<<< [CONFIGURE PHASE]: ANA_TX
614 22:14:22.907400 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
615 22:14:22.911129 ===================================
616 22:14:22.911739 data_rate = 1600,PCW = 0X7600
617 22:14:22.914417 ===================================
618 22:14:22.918190 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
619 22:14:22.925483 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
620 22:14:22.928980 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
621 22:14:22.936371 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
622 22:14:22.939919 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
623 22:14:22.943004 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
624 22:14:22.943486 [ANA_INIT] flow start
625 22:14:22.945897 [ANA_INIT] PLL >>>>>>>>
626 22:14:22.949451 [ANA_INIT] PLL <<<<<<<<
627 22:14:22.949933 [ANA_INIT] MIDPI >>>>>>>>
628 22:14:22.952732 [ANA_INIT] MIDPI <<<<<<<<
629 22:14:22.956175 [ANA_INIT] DLL >>>>>>>>
630 22:14:22.956661 [ANA_INIT] flow end
631 22:14:22.962729 ============ LP4 DIFF to SE enter ============
632 22:14:22.966073 ============ LP4 DIFF to SE exit ============
633 22:14:22.966816 [ANA_INIT] <<<<<<<<<<<<<
634 22:14:22.969795 [Flow] Enable top DCM control >>>>>
635 22:14:22.972587 [Flow] Enable top DCM control <<<<<
636 22:14:22.976382 Enable DLL master slave shuffle
637 22:14:22.983272 ==============================================================
638 22:14:22.985843 Gating Mode config
639 22:14:22.989569 ==============================================================
640 22:14:22.993150 Config description:
641 22:14:23.002468 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
642 22:14:23.009337 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
643 22:14:23.012377 SELPH_MODE 0: By rank 1: By Phase
644 22:14:23.019030 ==============================================================
645 22:14:23.022272 GAT_TRACK_EN = 1
646 22:14:23.025601 RX_GATING_MODE = 2
647 22:14:23.029016 RX_GATING_TRACK_MODE = 2
648 22:14:23.029497 SELPH_MODE = 1
649 22:14:23.032524 PICG_EARLY_EN = 1
650 22:14:23.035983 VALID_LAT_VALUE = 1
651 22:14:23.042600 ==============================================================
652 22:14:23.045667 Enter into Gating configuration >>>>
653 22:14:23.048998 Exit from Gating configuration <<<<
654 22:14:23.052650 Enter into DVFS_PRE_config >>>>>
655 22:14:23.063157 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
656 22:14:23.066179 Exit from DVFS_PRE_config <<<<<
657 22:14:23.069395 Enter into PICG configuration >>>>
658 22:14:23.072697 Exit from PICG configuration <<<<
659 22:14:23.075859 [RX_INPUT] configuration >>>>>
660 22:14:23.079205 [RX_INPUT] configuration <<<<<
661 22:14:23.083011 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
662 22:14:23.089337 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
663 22:14:23.095864 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
664 22:14:23.102338 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
665 22:14:23.105812 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
666 22:14:23.112373 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
667 22:14:23.115523 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
668 22:14:23.122782 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
669 22:14:23.125617 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
670 22:14:23.129067 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
671 22:14:23.132563 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
672 22:14:23.139837 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
673 22:14:23.142573 ===================================
674 22:14:23.143162 LPDDR4 DRAM CONFIGURATION
675 22:14:23.146525 ===================================
676 22:14:23.149136 EX_ROW_EN[0] = 0x0
677 22:14:23.152751 EX_ROW_EN[1] = 0x0
678 22:14:23.153368 LP4Y_EN = 0x0
679 22:14:23.156276 WORK_FSP = 0x0
680 22:14:23.156892 WL = 0x2
681 22:14:23.159313 RL = 0x2
682 22:14:23.159817 BL = 0x2
683 22:14:23.162741 RPST = 0x0
684 22:14:23.163345 RD_PRE = 0x0
685 22:14:23.166026 WR_PRE = 0x1
686 22:14:23.166614 WR_PST = 0x0
687 22:14:23.169206 DBI_WR = 0x0
688 22:14:23.169691 DBI_RD = 0x0
689 22:14:23.172667 OTF = 0x1
690 22:14:23.175824 ===================================
691 22:14:23.179439 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
692 22:14:23.183001 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
693 22:14:23.186571 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
694 22:14:23.189958 ===================================
695 22:14:23.194022 LPDDR4 DRAM CONFIGURATION
696 22:14:23.197184 ===================================
697 22:14:23.197673 EX_ROW_EN[0] = 0x10
698 22:14:23.201255 EX_ROW_EN[1] = 0x0
699 22:14:23.201862 LP4Y_EN = 0x0
700 22:14:23.205008 WORK_FSP = 0x0
701 22:14:23.205605 WL = 0x2
702 22:14:23.207960 RL = 0x2
703 22:14:23.208560 BL = 0x2
704 22:14:23.211756 RPST = 0x0
705 22:14:23.212330 RD_PRE = 0x0
706 22:14:23.215247 WR_PRE = 0x1
707 22:14:23.215971 WR_PST = 0x0
708 22:14:23.219026 DBI_WR = 0x0
709 22:14:23.219512 DBI_RD = 0x0
710 22:14:23.223239 OTF = 0x1
711 22:14:23.226305 ===================================
712 22:14:23.229782 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
713 22:14:23.234466 nWR fixed to 40
714 22:14:23.238227 [ModeRegInit_LP4] CH0 RK0
715 22:14:23.238808 [ModeRegInit_LP4] CH0 RK1
716 22:14:23.242001 [ModeRegInit_LP4] CH1 RK0
717 22:14:23.242484 [ModeRegInit_LP4] CH1 RK1
718 22:14:23.245459 match AC timing 13
719 22:14:23.249747 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
720 22:14:23.252910 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
721 22:14:23.259714 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
722 22:14:23.263157 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
723 22:14:23.267395 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
724 22:14:23.271342 [EMI DOE] emi_dcm 0
725 22:14:23.274642 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
726 22:14:23.275232 ==
727 22:14:23.278326 Dram Type= 6, Freq= 0, CH_0, rank 0
728 22:14:23.281588 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
729 22:14:23.282202 ==
730 22:14:23.285975 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
731 22:14:23.292434 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
732 22:14:23.302714 [CA 0] Center 37 (7~68) winsize 62
733 22:14:23.306305 [CA 1] Center 38 (7~69) winsize 63
734 22:14:23.309801 [CA 2] Center 35 (5~66) winsize 62
735 22:14:23.313660 [CA 3] Center 35 (5~66) winsize 62
736 22:14:23.317102 [CA 4] Center 35 (4~66) winsize 63
737 22:14:23.320807 [CA 5] Center 33 (3~64) winsize 62
738 22:14:23.321304
739 22:14:23.324431 [CmdBusTrainingLP45] Vref(ca) range 1: 30
740 22:14:23.324961
741 22:14:23.328147 [CATrainingPosCal] consider 1 rank data
742 22:14:23.328635 u2DelayCellTimex100 = 270/100 ps
743 22:14:23.331752 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
744 22:14:23.335799 CA1 delay=38 (7~69),Diff = 5 PI (36 cell)
745 22:14:23.339811 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
746 22:14:23.343689 CA3 delay=35 (5~66),Diff = 2 PI (14 cell)
747 22:14:23.347122 CA4 delay=35 (4~66),Diff = 2 PI (14 cell)
748 22:14:23.350363 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
749 22:14:23.350853
750 22:14:23.354219 CA PerBit enable=1, Macro0, CA PI delay=33
751 22:14:23.354736
752 22:14:23.358727 [CBTSetCACLKResult] CA Dly = 33
753 22:14:23.361935 CS Dly: 6 (0~37)
754 22:14:23.362544 ==
755 22:14:23.365988 Dram Type= 6, Freq= 0, CH_0, rank 1
756 22:14:23.369401 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
757 22:14:23.369992 ==
758 22:14:23.373431 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
759 22:14:23.379683 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
760 22:14:23.388639 [CA 0] Center 38 (7~69) winsize 63
761 22:14:23.392204 [CA 1] Center 38 (8~69) winsize 62
762 22:14:23.395991 [CA 2] Center 36 (5~67) winsize 63
763 22:14:23.399198 [CA 3] Center 35 (5~66) winsize 62
764 22:14:23.402772 [CA 4] Center 35 (4~66) winsize 63
765 22:14:23.406507 [CA 5] Center 34 (4~65) winsize 62
766 22:14:23.407107
767 22:14:23.410350 [CmdBusTrainingLP45] Vref(ca) range 1: 32
768 22:14:23.410953
769 22:14:23.413981 [CATrainingPosCal] consider 2 rank data
770 22:14:23.417488 u2DelayCellTimex100 = 270/100 ps
771 22:14:23.421066 CA0 delay=37 (7~68),Diff = 3 PI (21 cell)
772 22:14:23.425417 CA1 delay=38 (8~69),Diff = 4 PI (28 cell)
773 22:14:23.428984 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
774 22:14:23.432565 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
775 22:14:23.436231 CA4 delay=35 (4~66),Diff = 1 PI (7 cell)
776 22:14:23.439644 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
777 22:14:23.440243
778 22:14:23.443559 CA PerBit enable=1, Macro0, CA PI delay=34
779 22:14:23.444103
780 22:14:23.444642 [CBTSetCACLKResult] CA Dly = 34
781 22:14:23.447242 CS Dly: 6 (0~38)
782 22:14:23.447737
783 22:14:23.450838 ----->DramcWriteLeveling(PI) begin...
784 22:14:23.451327 ==
785 22:14:23.454560 Dram Type= 6, Freq= 0, CH_0, rank 0
786 22:14:23.458425 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
787 22:14:23.459023 ==
788 22:14:23.462336 Write leveling (Byte 0): 32 => 32
789 22:14:23.465725 Write leveling (Byte 1): 31 => 31
790 22:14:23.466303 DramcWriteLeveling(PI) end<-----
791 22:14:23.466693
792 22:14:23.469457 ==
793 22:14:23.469966 Dram Type= 6, Freq= 0, CH_0, rank 0
794 22:14:23.473562 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
795 22:14:23.477402 ==
796 22:14:23.478019 [Gating] SW mode calibration
797 22:14:23.484452 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
798 22:14:23.491887 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
799 22:14:23.495484 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
800 22:14:23.499387 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
801 22:14:23.502677 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 22:14:23.506969 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 22:14:23.514259 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
804 22:14:23.517127 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 22:14:23.520740 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 22:14:23.523785 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 22:14:23.531040 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 22:14:23.533619 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 22:14:23.537345 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 22:14:23.543629 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 22:14:23.546702 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 22:14:23.550243 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
813 22:14:23.557109 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
814 22:14:23.560143 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
815 22:14:23.563635 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
816 22:14:23.570158 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
817 22:14:23.573672 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
818 22:14:23.576603 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
819 22:14:23.583375 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
820 22:14:23.588028 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
821 22:14:23.590244 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
822 22:14:23.596925 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 22:14:23.599875 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 22:14:23.603177 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 22:14:23.609991 0 9 8 | B1->B0 | 2323 3434 | 1 1 | (1 1) (1 1)
826 22:14:23.613319 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
827 22:14:23.616877 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
828 22:14:23.623564 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
829 22:14:23.626733 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
830 22:14:23.629660 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
831 22:14:23.636482 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
832 22:14:23.639988 0 10 4 | B1->B0 | 3434 2e2e | 1 0 | (1 0) (0 0)
833 22:14:23.643230 0 10 8 | B1->B0 | 3131 2323 | 1 0 | (1 0) (0 0)
834 22:14:23.649699 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
835 22:14:23.653950 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
836 22:14:23.656463 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
837 22:14:23.662900 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
838 22:14:23.666193 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
839 22:14:23.669384 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
840 22:14:23.672681 0 11 4 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
841 22:14:23.679737 0 11 8 | B1->B0 | 2c2c 4646 | 0 0 | (0 0) (0 0)
842 22:14:23.682984 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
843 22:14:23.686311 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
844 22:14:23.692886 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
845 22:14:23.696275 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
846 22:14:23.699452 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
847 22:14:23.707118 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
848 22:14:23.709584 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
849 22:14:23.713074 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
850 22:14:23.719477 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 22:14:23.723014 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
852 22:14:23.726414 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
853 22:14:23.732879 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
854 22:14:23.736681 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
855 22:14:23.739653 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
856 22:14:23.746323 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
857 22:14:23.749136 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
858 22:14:23.753035 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
859 22:14:23.759286 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
860 22:14:23.762797 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
861 22:14:23.766084 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
862 22:14:23.772659 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
863 22:14:23.776058 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
864 22:14:23.779287 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
865 22:14:23.785930 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
866 22:14:23.786526 Total UI for P1: 0, mck2ui 16
867 22:14:23.789056 best dqsien dly found for B0: ( 0, 14, 4)
868 22:14:23.792632 Total UI for P1: 0, mck2ui 16
869 22:14:23.796046 best dqsien dly found for B1: ( 0, 14, 6)
870 22:14:23.799509 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
871 22:14:23.805797 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
872 22:14:23.806395
873 22:14:23.809718 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
874 22:14:23.812557 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
875 22:14:23.815851 [Gating] SW calibration Done
876 22:14:23.816447 ==
877 22:14:23.819397 Dram Type= 6, Freq= 0, CH_0, rank 0
878 22:14:23.822567 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
879 22:14:23.823169 ==
880 22:14:23.823567 RX Vref Scan: 0
881 22:14:23.825681
882 22:14:23.826167 RX Vref 0 -> 0, step: 1
883 22:14:23.826559
884 22:14:23.829586 RX Delay -130 -> 252, step: 16
885 22:14:23.833147 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
886 22:14:23.835828 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
887 22:14:23.842680 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
888 22:14:23.846008 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
889 22:14:23.849149 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
890 22:14:23.852215 iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240
891 22:14:23.855712 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
892 22:14:23.862463 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
893 22:14:23.865881 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
894 22:14:23.868935 iDelay=222, Bit 9, Center 69 (-34 ~ 173) 208
895 22:14:23.872284 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
896 22:14:23.878887 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
897 22:14:23.882412 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
898 22:14:23.885736 iDelay=222, Bit 13, Center 85 (-18 ~ 189) 208
899 22:14:23.888711 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
900 22:14:23.892144 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
901 22:14:23.895724 ==
902 22:14:23.896344 Dram Type= 6, Freq= 0, CH_0, rank 0
903 22:14:23.902235 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
904 22:14:23.902909 ==
905 22:14:23.903312 DQS Delay:
906 22:14:23.905508 DQS0 = 0, DQS1 = 0
907 22:14:23.905999 DQM Delay:
908 22:14:23.908510 DQM0 = 92, DQM1 = 81
909 22:14:23.909028 DQ Delay:
910 22:14:23.912178 DQ0 =93, DQ1 =93, DQ2 =85, DQ3 =85
911 22:14:23.915412 DQ4 =93, DQ5 =85, DQ6 =101, DQ7 =101
912 22:14:23.918747 DQ8 =77, DQ9 =69, DQ10 =77, DQ11 =77
913 22:14:23.922683 DQ12 =77, DQ13 =85, DQ14 =93, DQ15 =93
914 22:14:23.923273
915 22:14:23.923657
916 22:14:23.924015 ==
917 22:14:23.925566 Dram Type= 6, Freq= 0, CH_0, rank 0
918 22:14:23.928498 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
919 22:14:23.929146 ==
920 22:14:23.929535
921 22:14:23.929891
922 22:14:23.932048 TX Vref Scan disable
923 22:14:23.935244 == TX Byte 0 ==
924 22:14:23.939031 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
925 22:14:23.942598 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
926 22:14:23.945124 == TX Byte 1 ==
927 22:14:23.948832 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
928 22:14:23.951857 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
929 22:14:23.952442 ==
930 22:14:23.954785 Dram Type= 6, Freq= 0, CH_0, rank 0
931 22:14:23.961691 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
932 22:14:23.962280 ==
933 22:14:23.973177 TX Vref=22, minBit 11, minWin=26, winSum=438
934 22:14:23.976753 TX Vref=24, minBit 6, minWin=27, winSum=443
935 22:14:23.980178 TX Vref=26, minBit 8, minWin=27, winSum=448
936 22:14:23.983182 TX Vref=28, minBit 8, minWin=27, winSum=451
937 22:14:23.986491 TX Vref=30, minBit 5, minWin=28, winSum=459
938 22:14:23.990270 TX Vref=32, minBit 3, minWin=28, winSum=458
939 22:14:23.996830 [TxChooseVref] Worse bit 5, Min win 28, Win sum 459, Final Vref 30
940 22:14:23.997433
941 22:14:24.000306 Final TX Range 1 Vref 30
942 22:14:24.000946
943 22:14:24.001342 ==
944 22:14:24.003463 Dram Type= 6, Freq= 0, CH_0, rank 0
945 22:14:24.006441 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
946 22:14:24.007037 ==
947 22:14:24.007428
948 22:14:24.010119
949 22:14:24.010713 TX Vref Scan disable
950 22:14:24.013038 == TX Byte 0 ==
951 22:14:24.016473 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
952 22:14:24.023243 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
953 22:14:24.023839 == TX Byte 1 ==
954 22:14:24.026598 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
955 22:14:24.030018 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
956 22:14:24.032984
957 22:14:24.033476 [DATLAT]
958 22:14:24.033866 Freq=800, CH0 RK0
959 22:14:24.034232
960 22:14:24.036350 DATLAT Default: 0xa
961 22:14:24.036863 0, 0xFFFF, sum = 0
962 22:14:24.039798 1, 0xFFFF, sum = 0
963 22:14:24.040292 2, 0xFFFF, sum = 0
964 22:14:24.043332 3, 0xFFFF, sum = 0
965 22:14:24.046986 4, 0xFFFF, sum = 0
966 22:14:24.047589 5, 0xFFFF, sum = 0
967 22:14:24.049669 6, 0xFFFF, sum = 0
968 22:14:24.050165 7, 0xFFFF, sum = 0
969 22:14:24.053205 8, 0xFFFF, sum = 0
970 22:14:24.053699 9, 0x0, sum = 1
971 22:14:24.054096 10, 0x0, sum = 2
972 22:14:24.056527 11, 0x0, sum = 3
973 22:14:24.057168 12, 0x0, sum = 4
974 22:14:24.060193 best_step = 10
975 22:14:24.060817
976 22:14:24.061265 ==
977 22:14:24.063307 Dram Type= 6, Freq= 0, CH_0, rank 0
978 22:14:24.066335 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
979 22:14:24.066926 ==
980 22:14:24.069958 RX Vref Scan: 1
981 22:14:24.070541
982 22:14:24.072947 Set Vref Range= 32 -> 127
983 22:14:24.073539
984 22:14:24.073929 RX Vref 32 -> 127, step: 1
985 22:14:24.074296
986 22:14:24.076274 RX Delay -79 -> 252, step: 8
987 22:14:24.076904
988 22:14:24.079695 Set Vref, RX VrefLevel [Byte0]: 32
989 22:14:24.082916 [Byte1]: 32
990 22:14:24.083510
991 22:14:24.086204 Set Vref, RX VrefLevel [Byte0]: 33
992 22:14:24.089685 [Byte1]: 33
993 22:14:24.093363
994 22:14:24.093939 Set Vref, RX VrefLevel [Byte0]: 34
995 22:14:24.096443 [Byte1]: 34
996 22:14:24.100813
997 22:14:24.101394 Set Vref, RX VrefLevel [Byte0]: 35
998 22:14:24.104142 [Byte1]: 35
999 22:14:24.108336
1000 22:14:24.108940 Set Vref, RX VrefLevel [Byte0]: 36
1001 22:14:24.111772 [Byte1]: 36
1002 22:14:24.115889
1003 22:14:24.116370 Set Vref, RX VrefLevel [Byte0]: 37
1004 22:14:24.119228 [Byte1]: 37
1005 22:14:24.123454
1006 22:14:24.124070 Set Vref, RX VrefLevel [Byte0]: 38
1007 22:14:24.127194 [Byte1]: 38
1008 22:14:24.131186
1009 22:14:24.131672 Set Vref, RX VrefLevel [Byte0]: 39
1010 22:14:24.134923 [Byte1]: 39
1011 22:14:24.138867
1012 22:14:24.139458 Set Vref, RX VrefLevel [Byte0]: 40
1013 22:14:24.142285 [Byte1]: 40
1014 22:14:24.146448
1015 22:14:24.147032 Set Vref, RX VrefLevel [Byte0]: 41
1016 22:14:24.149704 [Byte1]: 41
1017 22:14:24.154081
1018 22:14:24.154564 Set Vref, RX VrefLevel [Byte0]: 42
1019 22:14:24.157299 [Byte1]: 42
1020 22:14:24.161723
1021 22:14:24.162309 Set Vref, RX VrefLevel [Byte0]: 43
1022 22:14:24.165279 [Byte1]: 43
1023 22:14:24.169171
1024 22:14:24.169765 Set Vref, RX VrefLevel [Byte0]: 44
1025 22:14:24.172567 [Byte1]: 44
1026 22:14:24.177096
1027 22:14:24.177699 Set Vref, RX VrefLevel [Byte0]: 45
1028 22:14:24.180582 [Byte1]: 45
1029 22:14:24.184510
1030 22:14:24.185153 Set Vref, RX VrefLevel [Byte0]: 46
1031 22:14:24.187346 [Byte1]: 46
1032 22:14:24.191427
1033 22:14:24.192033 Set Vref, RX VrefLevel [Byte0]: 47
1034 22:14:24.194930 [Byte1]: 47
1035 22:14:24.199384
1036 22:14:24.199962 Set Vref, RX VrefLevel [Byte0]: 48
1037 22:14:24.201991 [Byte1]: 48
1038 22:14:24.206406
1039 22:14:24.206887 Set Vref, RX VrefLevel [Byte0]: 49
1040 22:14:24.210004 [Byte1]: 49
1041 22:14:24.213994
1042 22:14:24.214579 Set Vref, RX VrefLevel [Byte0]: 50
1043 22:14:24.217430 [Byte1]: 50
1044 22:14:24.221606
1045 22:14:24.222084 Set Vref, RX VrefLevel [Byte0]: 51
1046 22:14:24.224902 [Byte1]: 51
1047 22:14:24.229489
1048 22:14:24.230092 Set Vref, RX VrefLevel [Byte0]: 52
1049 22:14:24.232446 [Byte1]: 52
1050 22:14:24.236495
1051 22:14:24.239880 Set Vref, RX VrefLevel [Byte0]: 53
1052 22:14:24.243584 [Byte1]: 53
1053 22:14:24.244168
1054 22:14:24.246455 Set Vref, RX VrefLevel [Byte0]: 54
1055 22:14:24.249745 [Byte1]: 54
1056 22:14:24.250318
1057 22:14:24.253110 Set Vref, RX VrefLevel [Byte0]: 55
1058 22:14:24.256416 [Byte1]: 55
1059 22:14:24.257044
1060 22:14:24.260001 Set Vref, RX VrefLevel [Byte0]: 56
1061 22:14:24.263110 [Byte1]: 56
1062 22:14:24.266948
1063 22:14:24.267532 Set Vref, RX VrefLevel [Byte0]: 57
1064 22:14:24.273368 [Byte1]: 57
1065 22:14:24.273975
1066 22:14:24.276952 Set Vref, RX VrefLevel [Byte0]: 58
1067 22:14:24.279999 [Byte1]: 58
1068 22:14:24.280593
1069 22:14:24.283217 Set Vref, RX VrefLevel [Byte0]: 59
1070 22:14:24.287157 [Byte1]: 59
1071 22:14:24.287742
1072 22:14:24.290169 Set Vref, RX VrefLevel [Byte0]: 60
1073 22:14:24.293548 [Byte1]: 60
1074 22:14:24.297338
1075 22:14:24.297924 Set Vref, RX VrefLevel [Byte0]: 61
1076 22:14:24.300475 [Byte1]: 61
1077 22:14:24.305073
1078 22:14:24.305667 Set Vref, RX VrefLevel [Byte0]: 62
1079 22:14:24.308128 [Byte1]: 62
1080 22:14:24.312150
1081 22:14:24.312739 Set Vref, RX VrefLevel [Byte0]: 63
1082 22:14:24.315699 [Byte1]: 63
1083 22:14:24.319706
1084 22:14:24.320290 Set Vref, RX VrefLevel [Byte0]: 64
1085 22:14:24.323159 [Byte1]: 64
1086 22:14:24.327181
1087 22:14:24.327770 Set Vref, RX VrefLevel [Byte0]: 65
1088 22:14:24.330573 [Byte1]: 65
1089 22:14:24.334780
1090 22:14:24.335359 Set Vref, RX VrefLevel [Byte0]: 66
1091 22:14:24.338103 [Byte1]: 66
1092 22:14:24.342666
1093 22:14:24.343148 Set Vref, RX VrefLevel [Byte0]: 67
1094 22:14:24.345858 [Byte1]: 67
1095 22:14:24.350356
1096 22:14:24.350935 Set Vref, RX VrefLevel [Byte0]: 68
1097 22:14:24.353484 [Byte1]: 68
1098 22:14:24.357569
1099 22:14:24.358149 Set Vref, RX VrefLevel [Byte0]: 69
1100 22:14:24.361152 [Byte1]: 69
1101 22:14:24.365386
1102 22:14:24.365964 Set Vref, RX VrefLevel [Byte0]: 70
1103 22:14:24.368667 [Byte1]: 70
1104 22:14:24.372838
1105 22:14:24.373418 Set Vref, RX VrefLevel [Byte0]: 71
1106 22:14:24.376045 [Byte1]: 71
1107 22:14:24.380255
1108 22:14:24.380875 Set Vref, RX VrefLevel [Byte0]: 72
1109 22:14:24.383779 [Byte1]: 72
1110 22:14:24.387843
1111 22:14:24.388428 Set Vref, RX VrefLevel [Byte0]: 73
1112 22:14:24.391263 [Byte1]: 73
1113 22:14:24.396001
1114 22:14:24.396582 Set Vref, RX VrefLevel [Byte0]: 74
1115 22:14:24.398839 [Byte1]: 74
1116 22:14:24.402837
1117 22:14:24.406146 Set Vref, RX VrefLevel [Byte0]: 75
1118 22:14:24.406733 [Byte1]: 75
1119 22:14:24.410249
1120 22:14:24.410726 Set Vref, RX VrefLevel [Byte0]: 76
1121 22:14:24.413601 [Byte1]: 76
1122 22:14:24.417825
1123 22:14:24.418415 Final RX Vref Byte 0 = 60 to rank0
1124 22:14:24.421058 Final RX Vref Byte 1 = 60 to rank0
1125 22:14:24.424338 Final RX Vref Byte 0 = 60 to rank1
1126 22:14:24.428072 Final RX Vref Byte 1 = 60 to rank1==
1127 22:14:24.431243 Dram Type= 6, Freq= 0, CH_0, rank 0
1128 22:14:24.437935 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1129 22:14:24.438422 ==
1130 22:14:24.438811 DQS Delay:
1131 22:14:24.439162 DQS0 = 0, DQS1 = 0
1132 22:14:24.440889 DQM Delay:
1133 22:14:24.441371 DQM0 = 93, DQM1 = 82
1134 22:14:24.444440 DQ Delay:
1135 22:14:24.448153 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1136 22:14:24.451441 DQ4 =92, DQ5 =80, DQ6 =104, DQ7 =104
1137 22:14:24.452019 DQ8 =72, DQ9 =72, DQ10 =84, DQ11 =80
1138 22:14:24.458524 DQ12 =84, DQ13 =80, DQ14 =92, DQ15 =92
1139 22:14:24.459104
1140 22:14:24.459487
1141 22:14:24.465061 [DQSOSCAuto] RK0, (LSB)MR18= 0x3b36, (MSB)MR19= 0x606, tDQSOscB0 = 396 ps tDQSOscB1 = 394 ps
1142 22:14:24.468340 CH0 RK0: MR19=606, MR18=3B36
1143 22:14:24.474569 CH0_RK0: MR19=0x606, MR18=0x3B36, DQSOSC=394, MR23=63, INC=95, DEC=63
1144 22:14:24.475172
1145 22:14:24.478113 ----->DramcWriteLeveling(PI) begin...
1146 22:14:24.478697 ==
1147 22:14:24.481159 Dram Type= 6, Freq= 0, CH_0, rank 1
1148 22:14:24.484662 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1149 22:14:24.485295 ==
1150 22:14:24.488088 Write leveling (Byte 0): 33 => 33
1151 22:14:24.491362 Write leveling (Byte 1): 28 => 28
1152 22:14:24.494524 DramcWriteLeveling(PI) end<-----
1153 22:14:24.495097
1154 22:14:24.495483 ==
1155 22:14:24.497995 Dram Type= 6, Freq= 0, CH_0, rank 1
1156 22:14:24.501698 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1157 22:14:24.502280 ==
1158 22:14:24.504520 [Gating] SW mode calibration
1159 22:14:24.511317 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1160 22:14:24.517943 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1161 22:14:24.521271 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1162 22:14:24.524050 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1163 22:14:24.531223 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1164 22:14:24.534350 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 22:14:24.537759 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 22:14:24.544421 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 22:14:24.547964 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 22:14:24.550998 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 22:14:24.595637 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 22:14:24.596230 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 22:14:24.596977 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 22:14:24.597368 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 22:14:24.597719 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 22:14:24.598060 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 22:14:24.598389 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 22:14:24.598777 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 22:14:24.599113 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 22:14:24.599437 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1179 22:14:24.639668 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1180 22:14:24.640297 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1181 22:14:24.641021 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1182 22:14:24.641412 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1183 22:14:24.641764 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1184 22:14:24.642097 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1185 22:14:24.642630 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1186 22:14:24.643039 0 9 4 | B1->B0 | 2323 2424 | 0 1 | (0 0) (1 1)
1187 22:14:24.643449 0 9 8 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)
1188 22:14:24.643856 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1189 22:14:24.652650 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1190 22:14:24.653276 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1191 22:14:24.656292 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1192 22:14:24.659582 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1193 22:14:24.663139 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1194 22:14:24.666021 0 10 4 | B1->B0 | 3232 2f2f | 0 1 | (0 0) (1 1)
1195 22:14:24.669345 0 10 8 | B1->B0 | 2e2e 2626 | 0 0 | (1 1) (0 0)
1196 22:14:24.676029 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1197 22:14:24.679594 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1198 22:14:24.683247 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1199 22:14:24.689324 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1200 22:14:24.692840 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1201 22:14:24.696000 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1202 22:14:24.702673 0 11 4 | B1->B0 | 2727 3131 | 0 0 | (0 0) (0 0)
1203 22:14:24.705784 0 11 8 | B1->B0 | 4040 4646 | 1 0 | (0 0) (0 0)
1204 22:14:24.709317 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1205 22:14:24.715890 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1206 22:14:24.719024 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1207 22:14:24.722268 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1208 22:14:24.729465 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1209 22:14:24.733015 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1210 22:14:24.736906 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1211 22:14:24.740401 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1212 22:14:24.743736 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 22:14:24.750555 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 22:14:24.753880 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 22:14:24.757458 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 22:14:24.764664 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 22:14:24.768035 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1218 22:14:24.772000 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1219 22:14:24.774592 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1220 22:14:24.781144 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1221 22:14:24.784528 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1222 22:14:24.787986 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1223 22:14:24.795232 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1224 22:14:24.797873 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1225 22:14:24.801506 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1226 22:14:24.808076 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1227 22:14:24.811327 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1228 22:14:24.814612 Total UI for P1: 0, mck2ui 16
1229 22:14:24.818297 best dqsien dly found for B0: ( 0, 14, 4)
1230 22:14:24.820933 Total UI for P1: 0, mck2ui 16
1231 22:14:24.824201 best dqsien dly found for B1: ( 0, 14, 4)
1232 22:14:24.828187 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1233 22:14:24.831641 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1234 22:14:24.832226
1235 22:14:24.834110 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1236 22:14:24.837828 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1237 22:14:24.841394 [Gating] SW calibration Done
1238 22:14:24.841976 ==
1239 22:14:24.845023 Dram Type= 6, Freq= 0, CH_0, rank 1
1240 22:14:24.847809 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1241 22:14:24.850797 ==
1242 22:14:24.851278 RX Vref Scan: 0
1243 22:14:24.851702
1244 22:14:24.854561 RX Vref 0 -> 0, step: 1
1245 22:14:24.855043
1246 22:14:24.857685 RX Delay -130 -> 252, step: 16
1247 22:14:24.861505 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1248 22:14:24.864116 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1249 22:14:24.867937 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1250 22:14:24.871323 iDelay=222, Bit 3, Center 77 (-34 ~ 189) 224
1251 22:14:24.877868 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1252 22:14:24.881297 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
1253 22:14:24.884087 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1254 22:14:24.887747 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1255 22:14:24.891371 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1256 22:14:24.898195 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
1257 22:14:24.901199 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1258 22:14:24.904528 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1259 22:14:24.907772 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
1260 22:14:24.911028 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1261 22:14:24.917694 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1262 22:14:24.921440 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1263 22:14:24.922025 ==
1264 22:14:24.924625 Dram Type= 6, Freq= 0, CH_0, rank 1
1265 22:14:24.928041 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1266 22:14:24.928629 ==
1267 22:14:24.930798 DQS Delay:
1268 22:14:24.931275 DQS0 = 0, DQS1 = 0
1269 22:14:24.931658 DQM Delay:
1270 22:14:24.934268 DQM0 = 88, DQM1 = 80
1271 22:14:24.934851 DQ Delay:
1272 22:14:24.937382 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =77
1273 22:14:24.941406 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =93
1274 22:14:24.944434 DQ8 =77, DQ9 =61, DQ10 =77, DQ11 =77
1275 22:14:24.947729 DQ12 =77, DQ13 =85, DQ14 =93, DQ15 =93
1276 22:14:24.948211
1277 22:14:24.948598
1278 22:14:24.949012 ==
1279 22:14:24.951539 Dram Type= 6, Freq= 0, CH_0, rank 1
1280 22:14:24.957264 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1281 22:14:24.957745 ==
1282 22:14:24.958129
1283 22:14:24.958484
1284 22:14:24.958821 TX Vref Scan disable
1285 22:14:24.961009 == TX Byte 0 ==
1286 22:14:24.964465 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1287 22:14:24.967617 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1288 22:14:24.971322 == TX Byte 1 ==
1289 22:14:24.974759 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1290 22:14:24.980707 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1291 22:14:24.981321 ==
1292 22:14:24.984308 Dram Type= 6, Freq= 0, CH_0, rank 1
1293 22:14:24.987306 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1294 22:14:24.987888 ==
1295 22:14:25.000938 TX Vref=22, minBit 3, minWin=27, winSum=443
1296 22:14:25.004467 TX Vref=24, minBit 1, minWin=27, winSum=451
1297 22:14:25.007393 TX Vref=26, minBit 8, minWin=27, winSum=454
1298 22:14:25.011152 TX Vref=28, minBit 8, minWin=27, winSum=456
1299 22:14:25.014104 TX Vref=30, minBit 8, minWin=27, winSum=458
1300 22:14:25.020645 TX Vref=32, minBit 8, minWin=28, winSum=459
1301 22:14:25.024090 [TxChooseVref] Worse bit 8, Min win 28, Win sum 459, Final Vref 32
1302 22:14:25.024685
1303 22:14:25.027572 Final TX Range 1 Vref 32
1304 22:14:25.028156
1305 22:14:25.028542 ==
1306 22:14:25.030302 Dram Type= 6, Freq= 0, CH_0, rank 1
1307 22:14:25.034028 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1308 22:14:25.036726 ==
1309 22:14:25.037242
1310 22:14:25.037617
1311 22:14:25.037962 TX Vref Scan disable
1312 22:14:25.040554 == TX Byte 0 ==
1313 22:14:25.044037 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1314 22:14:25.050468 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1315 22:14:25.050964 == TX Byte 1 ==
1316 22:14:25.053530 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1317 22:14:25.060327 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1318 22:14:25.060754
1319 22:14:25.061121 [DATLAT]
1320 22:14:25.061433 Freq=800, CH0 RK1
1321 22:14:25.061741
1322 22:14:25.063501 DATLAT Default: 0xa
1323 22:14:25.063815 0, 0xFFFF, sum = 0
1324 22:14:25.067248 1, 0xFFFF, sum = 0
1325 22:14:25.070686 2, 0xFFFF, sum = 0
1326 22:14:25.071098 3, 0xFFFF, sum = 0
1327 22:14:25.073256 4, 0xFFFF, sum = 0
1328 22:14:25.073571 5, 0xFFFF, sum = 0
1329 22:14:25.076736 6, 0xFFFF, sum = 0
1330 22:14:25.077082 7, 0xFFFF, sum = 0
1331 22:14:25.080228 8, 0xFFFF, sum = 0
1332 22:14:25.080534 9, 0x0, sum = 1
1333 22:14:25.083922 10, 0x0, sum = 2
1334 22:14:25.084330 11, 0x0, sum = 3
1335 22:14:25.084586 12, 0x0, sum = 4
1336 22:14:25.086775 best_step = 10
1337 22:14:25.087180
1338 22:14:25.087433 ==
1339 22:14:25.090127 Dram Type= 6, Freq= 0, CH_0, rank 1
1340 22:14:25.093362 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1341 22:14:25.093668 ==
1342 22:14:25.096833 RX Vref Scan: 0
1343 22:14:25.097251
1344 22:14:25.100263 RX Vref 0 -> 0, step: 1
1345 22:14:25.100566
1346 22:14:25.100842 RX Delay -95 -> 252, step: 8
1347 22:14:25.107221 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1348 22:14:25.110997 iDelay=209, Bit 1, Center 92 (-15 ~ 200) 216
1349 22:14:25.114579 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1350 22:14:25.117527 iDelay=209, Bit 3, Center 84 (-23 ~ 192) 216
1351 22:14:25.120840 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
1352 22:14:25.127230 iDelay=209, Bit 5, Center 84 (-23 ~ 192) 216
1353 22:14:25.130528 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1354 22:14:25.134258 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1355 22:14:25.137959 iDelay=209, Bit 8, Center 72 (-31 ~ 176) 208
1356 22:14:25.140692 iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216
1357 22:14:25.147194 iDelay=209, Bit 10, Center 80 (-23 ~ 184) 208
1358 22:14:25.151284 iDelay=209, Bit 11, Center 80 (-23 ~ 184) 208
1359 22:14:25.154276 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1360 22:14:25.157001 iDelay=209, Bit 13, Center 84 (-23 ~ 192) 216
1361 22:14:25.161052 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1362 22:14:25.167473 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1363 22:14:25.168044 ==
1364 22:14:25.170446 Dram Type= 6, Freq= 0, CH_0, rank 1
1365 22:14:25.173799 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1366 22:14:25.174380 ==
1367 22:14:25.174756 DQS Delay:
1368 22:14:25.177291 DQS0 = 0, DQS1 = 0
1369 22:14:25.177862 DQM Delay:
1370 22:14:25.180952 DQM0 = 91, DQM1 = 81
1371 22:14:25.181529 DQ Delay:
1372 22:14:25.183908 DQ0 =88, DQ1 =92, DQ2 =88, DQ3 =84
1373 22:14:25.187387 DQ4 =92, DQ5 =84, DQ6 =100, DQ7 =100
1374 22:14:25.190528 DQ8 =72, DQ9 =68, DQ10 =80, DQ11 =80
1375 22:14:25.193753 DQ12 =84, DQ13 =84, DQ14 =92, DQ15 =88
1376 22:14:25.194324
1377 22:14:25.194701
1378 22:14:25.203643 [DQSOSCAuto] RK1, (LSB)MR18= 0x401b, (MSB)MR19= 0x606, tDQSOscB0 = 403 ps tDQSOscB1 = 393 ps
1379 22:14:25.204372 CH0 RK1: MR19=606, MR18=401B
1380 22:14:25.210092 CH0_RK1: MR19=0x606, MR18=0x401B, DQSOSC=393, MR23=63, INC=95, DEC=63
1381 22:14:25.213593 [RxdqsGatingPostProcess] freq 800
1382 22:14:25.220661 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1383 22:14:25.223736 Pre-setting of DQS Precalculation
1384 22:14:25.226726 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1385 22:14:25.227212 ==
1386 22:14:25.230185 Dram Type= 6, Freq= 0, CH_1, rank 0
1387 22:14:25.237229 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1388 22:14:25.237819 ==
1389 22:14:25.240324 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1390 22:14:25.247317 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1391 22:14:25.256460 [CA 0] Center 36 (6~67) winsize 62
1392 22:14:25.259476 [CA 1] Center 36 (6~67) winsize 62
1393 22:14:25.262577 [CA 2] Center 35 (5~65) winsize 61
1394 22:14:25.265947 [CA 3] Center 34 (4~65) winsize 62
1395 22:14:25.269692 [CA 4] Center 34 (4~65) winsize 62
1396 22:14:25.272712 [CA 5] Center 34 (3~65) winsize 63
1397 22:14:25.273220
1398 22:14:25.276451 [CmdBusTrainingLP45] Vref(ca) range 1: 28
1399 22:14:25.277063
1400 22:14:25.279635 [CATrainingPosCal] consider 1 rank data
1401 22:14:25.282663 u2DelayCellTimex100 = 270/100 ps
1402 22:14:25.286222 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1403 22:14:25.289600 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1404 22:14:25.295861 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1405 22:14:25.299154 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1406 22:14:25.302598 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1407 22:14:25.306133 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1408 22:14:25.306616
1409 22:14:25.309241 CA PerBit enable=1, Macro0, CA PI delay=34
1410 22:14:25.309719
1411 22:14:25.312567 [CBTSetCACLKResult] CA Dly = 34
1412 22:14:25.313198 CS Dly: 5 (0~36)
1413 22:14:25.313587 ==
1414 22:14:25.315580 Dram Type= 6, Freq= 0, CH_1, rank 1
1415 22:14:25.322582 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1416 22:14:25.323159 ==
1417 22:14:25.325475 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1418 22:14:25.332582 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1419 22:14:25.341963 [CA 0] Center 37 (6~68) winsize 63
1420 22:14:25.345275 [CA 1] Center 37 (6~68) winsize 63
1421 22:14:25.348724 [CA 2] Center 35 (5~66) winsize 62
1422 22:14:25.352018 [CA 3] Center 34 (4~65) winsize 62
1423 22:14:25.355390 [CA 4] Center 34 (4~65) winsize 62
1424 22:14:25.358953 [CA 5] Center 34 (4~65) winsize 62
1425 22:14:25.359532
1426 22:14:25.362285 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1427 22:14:25.362860
1428 22:14:25.365052 [CATrainingPosCal] consider 2 rank data
1429 22:14:25.368702 u2DelayCellTimex100 = 270/100 ps
1430 22:14:25.372473 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1431 22:14:25.378674 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1432 22:14:25.381469 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1433 22:14:25.385256 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1434 22:14:25.388528 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1435 22:14:25.391899 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1436 22:14:25.392474
1437 22:14:25.395270 CA PerBit enable=1, Macro0, CA PI delay=34
1438 22:14:25.395751
1439 22:14:25.398778 [CBTSetCACLKResult] CA Dly = 34
1440 22:14:25.399342 CS Dly: 6 (0~38)
1441 22:14:25.399745
1442 22:14:25.402366 ----->DramcWriteLeveling(PI) begin...
1443 22:14:25.402855 ==
1444 22:14:25.405792 Dram Type= 6, Freq= 0, CH_1, rank 0
1445 22:14:25.409586 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1446 22:14:25.413123 ==
1447 22:14:25.413761 Write leveling (Byte 0): 24 => 24
1448 22:14:25.416365 Write leveling (Byte 1): 28 => 28
1449 22:14:25.420189 DramcWriteLeveling(PI) end<-----
1450 22:14:25.420671
1451 22:14:25.421113 ==
1452 22:14:25.423286 Dram Type= 6, Freq= 0, CH_1, rank 0
1453 22:14:25.427036 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1454 22:14:25.427562 ==
1455 22:14:25.430949 [Gating] SW mode calibration
1456 22:14:25.437746 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1457 22:14:25.444288 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1458 22:14:25.447633 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1459 22:14:25.450755 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 22:14:25.457510 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1461 22:14:25.460737 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 22:14:25.464220 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 22:14:25.470938 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 22:14:25.474106 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 22:14:25.478070 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 22:14:25.484217 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 22:14:25.487582 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 22:14:25.491177 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 22:14:25.497615 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 22:14:25.500655 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 22:14:25.504198 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 22:14:25.510705 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 22:14:25.514349 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 22:14:25.517280 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1475 22:14:25.524032 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1476 22:14:25.527085 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1477 22:14:25.530643 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1478 22:14:25.536748 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1479 22:14:25.540202 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1480 22:14:25.543811 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1481 22:14:25.550233 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1482 22:14:25.553971 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1483 22:14:25.557099 0 9 4 | B1->B0 | 2525 2929 | 0 0 | (0 0) (1 1)
1484 22:14:25.563618 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1485 22:14:25.567226 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1486 22:14:25.570421 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1487 22:14:25.573608 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1488 22:14:25.580173 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1489 22:14:25.584065 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1490 22:14:25.587096 0 10 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
1491 22:14:25.594013 0 10 4 | B1->B0 | 3030 2d2d | 0 0 | (0 1) (0 0)
1492 22:14:25.597071 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1493 22:14:25.600563 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1494 22:14:25.607374 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1495 22:14:25.610734 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1496 22:14:25.613483 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1497 22:14:25.620729 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1498 22:14:25.623789 0 11 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1499 22:14:25.627124 0 11 4 | B1->B0 | 3232 3a3a | 0 0 | (0 0) (0 0)
1500 22:14:25.633796 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1501 22:14:25.637212 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1502 22:14:25.640379 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1503 22:14:25.647603 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1504 22:14:25.650266 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1505 22:14:25.653535 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1506 22:14:25.660270 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1507 22:14:25.663886 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1508 22:14:25.666964 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 22:14:25.670261 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 22:14:25.677315 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 22:14:25.680249 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 22:14:25.683872 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 22:14:25.690360 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 22:14:25.693312 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1515 22:14:25.696550 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1516 22:14:25.703993 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1517 22:14:25.706896 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1518 22:14:25.710928 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1519 22:14:25.716861 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1520 22:14:25.720252 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1521 22:14:25.723558 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1522 22:14:25.730214 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1523 22:14:25.733602 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1524 22:14:25.736423 Total UI for P1: 0, mck2ui 16
1525 22:14:25.740010 best dqsien dly found for B0: ( 0, 14, 2)
1526 22:14:25.743273 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1527 22:14:25.746328 Total UI for P1: 0, mck2ui 16
1528 22:14:25.750311 best dqsien dly found for B1: ( 0, 14, 4)
1529 22:14:25.753376 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1530 22:14:25.756288 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1531 22:14:25.756791
1532 22:14:25.763409 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1533 22:14:25.766657 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1534 22:14:25.767143 [Gating] SW calibration Done
1535 22:14:25.770165 ==
1536 22:14:25.770748 Dram Type= 6, Freq= 0, CH_1, rank 0
1537 22:14:25.776548 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1538 22:14:25.777176 ==
1539 22:14:25.777568 RX Vref Scan: 0
1540 22:14:25.777926
1541 22:14:25.780055 RX Vref 0 -> 0, step: 1
1542 22:14:25.780642
1543 22:14:25.783314 RX Delay -130 -> 252, step: 16
1544 22:14:25.786841 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
1545 22:14:25.790080 iDelay=206, Bit 1, Center 85 (-18 ~ 189) 208
1546 22:14:25.793430 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1547 22:14:25.799905 iDelay=206, Bit 3, Center 93 (-18 ~ 205) 224
1548 22:14:25.803196 iDelay=206, Bit 4, Center 85 (-18 ~ 189) 208
1549 22:14:25.806559 iDelay=206, Bit 5, Center 101 (-2 ~ 205) 208
1550 22:14:25.810811 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1551 22:14:25.813285 iDelay=206, Bit 7, Center 85 (-34 ~ 205) 240
1552 22:14:25.820194 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1553 22:14:25.822956 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1554 22:14:25.826433 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1555 22:14:25.829527 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1556 22:14:25.832984 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1557 22:14:25.839370 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1558 22:14:25.843016 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1559 22:14:25.846317 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1560 22:14:25.846904 ==
1561 22:14:25.849511 Dram Type= 6, Freq= 0, CH_1, rank 0
1562 22:14:25.852518 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1563 22:14:25.856115 ==
1564 22:14:25.856594 DQS Delay:
1565 22:14:25.857010 DQS0 = 0, DQS1 = 0
1566 22:14:25.859407 DQM Delay:
1567 22:14:25.859986 DQM0 = 89, DQM1 = 80
1568 22:14:25.862858 DQ Delay:
1569 22:14:25.866021 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93
1570 22:14:25.866502 DQ4 =85, DQ5 =101, DQ6 =93, DQ7 =85
1571 22:14:25.869141 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =77
1572 22:14:25.876104 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1573 22:14:25.876691
1574 22:14:25.877112
1575 22:14:25.877471 ==
1576 22:14:25.879318 Dram Type= 6, Freq= 0, CH_1, rank 0
1577 22:14:25.882464 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1578 22:14:25.882948 ==
1579 22:14:25.883331
1580 22:14:25.883689
1581 22:14:25.885712 TX Vref Scan disable
1582 22:14:25.886192 == TX Byte 0 ==
1583 22:14:25.892902 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1584 22:14:25.896570 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1585 22:14:25.897196 == TX Byte 1 ==
1586 22:14:25.902835 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1587 22:14:25.906442 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1588 22:14:25.907032 ==
1589 22:14:25.909178 Dram Type= 6, Freq= 0, CH_1, rank 0
1590 22:14:25.912635 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1591 22:14:25.913246 ==
1592 22:14:25.926690 TX Vref=22, minBit 8, minWin=27, winSum=449
1593 22:14:25.930185 TX Vref=24, minBit 15, minWin=27, winSum=454
1594 22:14:25.933038 TX Vref=26, minBit 15, minWin=27, winSum=458
1595 22:14:25.936595 TX Vref=28, minBit 15, minWin=27, winSum=458
1596 22:14:25.939752 TX Vref=30, minBit 15, minWin=27, winSum=458
1597 22:14:25.946461 TX Vref=32, minBit 15, minWin=27, winSum=457
1598 22:14:25.949586 [TxChooseVref] Worse bit 15, Min win 27, Win sum 458, Final Vref 26
1599 22:14:25.950073
1600 22:14:25.953156 Final TX Range 1 Vref 26
1601 22:14:25.953638
1602 22:14:25.954020 ==
1603 22:14:25.956606 Dram Type= 6, Freq= 0, CH_1, rank 0
1604 22:14:25.959784 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1605 22:14:25.963302 ==
1606 22:14:25.963782
1607 22:14:25.964168
1608 22:14:25.964525 TX Vref Scan disable
1609 22:14:25.967306 == TX Byte 0 ==
1610 22:14:25.970168 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1611 22:14:25.977242 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1612 22:14:25.977828 == TX Byte 1 ==
1613 22:14:25.980946 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1614 22:14:25.984213 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1615 22:14:25.984693
1616 22:14:25.987601 [DATLAT]
1617 22:14:25.988080 Freq=800, CH1 RK0
1618 22:14:25.988465
1619 22:14:25.990770 DATLAT Default: 0xa
1620 22:14:25.991352 0, 0xFFFF, sum = 0
1621 22:14:25.994420 1, 0xFFFF, sum = 0
1622 22:14:25.995011 2, 0xFFFF, sum = 0
1623 22:14:25.998060 3, 0xFFFF, sum = 0
1624 22:14:25.998649 4, 0xFFFF, sum = 0
1625 22:14:26.000611 5, 0xFFFF, sum = 0
1626 22:14:26.001129 6, 0xFFFF, sum = 0
1627 22:14:26.004439 7, 0xFFFF, sum = 0
1628 22:14:26.005060 8, 0xFFFF, sum = 0
1629 22:14:26.007695 9, 0x0, sum = 1
1630 22:14:26.008283 10, 0x0, sum = 2
1631 22:14:26.010773 11, 0x0, sum = 3
1632 22:14:26.011364 12, 0x0, sum = 4
1633 22:14:26.014282 best_step = 10
1634 22:14:26.014875
1635 22:14:26.015263 ==
1636 22:14:26.017440 Dram Type= 6, Freq= 0, CH_1, rank 0
1637 22:14:26.021191 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1638 22:14:26.021781 ==
1639 22:14:26.024489 RX Vref Scan: 1
1640 22:14:26.025104
1641 22:14:26.025491 Set Vref Range= 32 -> 127
1642 22:14:26.025850
1643 22:14:26.027287 RX Vref 32 -> 127, step: 1
1644 22:14:26.027821
1645 22:14:26.031037 RX Delay -95 -> 252, step: 8
1646 22:14:26.031519
1647 22:14:26.034438 Set Vref, RX VrefLevel [Byte0]: 32
1648 22:14:26.037891 [Byte1]: 32
1649 22:14:26.038477
1650 22:14:26.040965 Set Vref, RX VrefLevel [Byte0]: 33
1651 22:14:26.044302 [Byte1]: 33
1652 22:14:26.044930
1653 22:14:26.047711 Set Vref, RX VrefLevel [Byte0]: 34
1654 22:14:26.051867 [Byte1]: 34
1655 22:14:26.055304
1656 22:14:26.055783 Set Vref, RX VrefLevel [Byte0]: 35
1657 22:14:26.058168 [Byte1]: 35
1658 22:14:26.062439
1659 22:14:26.063036 Set Vref, RX VrefLevel [Byte0]: 36
1660 22:14:26.066017 [Byte1]: 36
1661 22:14:26.070057
1662 22:14:26.070535 Set Vref, RX VrefLevel [Byte0]: 37
1663 22:14:26.073513 [Byte1]: 37
1664 22:14:26.077572
1665 22:14:26.078161 Set Vref, RX VrefLevel [Byte0]: 38
1666 22:14:26.080998 [Byte1]: 38
1667 22:14:26.085214
1668 22:14:26.085797 Set Vref, RX VrefLevel [Byte0]: 39
1669 22:14:26.088565 [Byte1]: 39
1670 22:14:26.093379
1671 22:14:26.093961 Set Vref, RX VrefLevel [Byte0]: 40
1672 22:14:26.095988 [Byte1]: 40
1673 22:14:26.100812
1674 22:14:26.101401 Set Vref, RX VrefLevel [Byte0]: 41
1675 22:14:26.104030 [Byte1]: 41
1676 22:14:26.108287
1677 22:14:26.108925 Set Vref, RX VrefLevel [Byte0]: 42
1678 22:14:26.114713 [Byte1]: 42
1679 22:14:26.115300
1680 22:14:26.118053 Set Vref, RX VrefLevel [Byte0]: 43
1681 22:14:26.121490 [Byte1]: 43
1682 22:14:26.122077
1683 22:14:26.124938 Set Vref, RX VrefLevel [Byte0]: 44
1684 22:14:26.129029 [Byte1]: 44
1685 22:14:26.129614
1686 22:14:26.131161 Set Vref, RX VrefLevel [Byte0]: 45
1687 22:14:26.134756 [Byte1]: 45
1688 22:14:26.138992
1689 22:14:26.139575 Set Vref, RX VrefLevel [Byte0]: 46
1690 22:14:26.141829 [Byte1]: 46
1691 22:14:26.145968
1692 22:14:26.146446 Set Vref, RX VrefLevel [Byte0]: 47
1693 22:14:26.149528 [Byte1]: 47
1694 22:14:26.153596
1695 22:14:26.154143 Set Vref, RX VrefLevel [Byte0]: 48
1696 22:14:26.156947 [Byte1]: 48
1697 22:14:26.161230
1698 22:14:26.161816 Set Vref, RX VrefLevel [Byte0]: 49
1699 22:14:26.164891 [Byte1]: 49
1700 22:14:26.169388
1701 22:14:26.169974 Set Vref, RX VrefLevel [Byte0]: 50
1702 22:14:26.172412 [Byte1]: 50
1703 22:14:26.176675
1704 22:14:26.177352 Set Vref, RX VrefLevel [Byte0]: 51
1705 22:14:26.179936 [Byte1]: 51
1706 22:14:26.184046
1707 22:14:26.184527 Set Vref, RX VrefLevel [Byte0]: 52
1708 22:14:26.187230 [Byte1]: 52
1709 22:14:26.192469
1710 22:14:26.193108 Set Vref, RX VrefLevel [Byte0]: 53
1711 22:14:26.195791 [Byte1]: 53
1712 22:14:26.199495
1713 22:14:26.200075 Set Vref, RX VrefLevel [Byte0]: 54
1714 22:14:26.203000 [Byte1]: 54
1715 22:14:26.207275
1716 22:14:26.207856 Set Vref, RX VrefLevel [Byte0]: 55
1717 22:14:26.210218 [Byte1]: 55
1718 22:14:26.214629
1719 22:14:26.215215 Set Vref, RX VrefLevel [Byte0]: 56
1720 22:14:26.217866 [Byte1]: 56
1721 22:14:26.222002
1722 22:14:26.222589 Set Vref, RX VrefLevel [Byte0]: 57
1723 22:14:26.225075 [Byte1]: 57
1724 22:14:26.229696
1725 22:14:26.230279 Set Vref, RX VrefLevel [Byte0]: 58
1726 22:14:26.232715 [Byte1]: 58
1727 22:14:26.237216
1728 22:14:26.237828 Set Vref, RX VrefLevel [Byte0]: 59
1729 22:14:26.240539 [Byte1]: 59
1730 22:14:26.245443
1731 22:14:26.246025 Set Vref, RX VrefLevel [Byte0]: 60
1732 22:14:26.248556 [Byte1]: 60
1733 22:14:26.252981
1734 22:14:26.253687 Set Vref, RX VrefLevel [Byte0]: 61
1735 22:14:26.255622 [Byte1]: 61
1736 22:14:26.260102
1737 22:14:26.260689 Set Vref, RX VrefLevel [Byte0]: 62
1738 22:14:26.263825 [Byte1]: 62
1739 22:14:26.268157
1740 22:14:26.268746 Set Vref, RX VrefLevel [Byte0]: 63
1741 22:14:26.271075 [Byte1]: 63
1742 22:14:26.275364
1743 22:14:26.276098 Set Vref, RX VrefLevel [Byte0]: 64
1744 22:14:26.278698 [Byte1]: 64
1745 22:14:26.283048
1746 22:14:26.283831 Set Vref, RX VrefLevel [Byte0]: 65
1747 22:14:26.286094 [Byte1]: 65
1748 22:14:26.290399
1749 22:14:26.290976 Set Vref, RX VrefLevel [Byte0]: 66
1750 22:14:26.294012 [Byte1]: 66
1751 22:14:26.298066
1752 22:14:26.298546 Set Vref, RX VrefLevel [Byte0]: 67
1753 22:14:26.301481 [Byte1]: 67
1754 22:14:26.305840
1755 22:14:26.306422 Set Vref, RX VrefLevel [Byte0]: 68
1756 22:14:26.308650 [Byte1]: 68
1757 22:14:26.314044
1758 22:14:26.314626 Set Vref, RX VrefLevel [Byte0]: 69
1759 22:14:26.316676 [Byte1]: 69
1760 22:14:26.321000
1761 22:14:26.321586 Set Vref, RX VrefLevel [Byte0]: 70
1762 22:14:26.324275 [Byte1]: 70
1763 22:14:26.328801
1764 22:14:26.329395 Set Vref, RX VrefLevel [Byte0]: 71
1765 22:14:26.331545 [Byte1]: 71
1766 22:14:26.336178
1767 22:14:26.336797 Set Vref, RX VrefLevel [Byte0]: 72
1768 22:14:26.339331 [Byte1]: 72
1769 22:14:26.343462
1770 22:14:26.346874 Set Vref, RX VrefLevel [Byte0]: 73
1771 22:14:26.347462 [Byte1]: 73
1772 22:14:26.351395
1773 22:14:26.351973 Set Vref, RX VrefLevel [Byte0]: 74
1774 22:14:26.354256 [Byte1]: 74
1775 22:14:26.358746
1776 22:14:26.359333 Set Vref, RX VrefLevel [Byte0]: 75
1777 22:14:26.362125 [Byte1]: 75
1778 22:14:26.366557
1779 22:14:26.367139 Set Vref, RX VrefLevel [Byte0]: 76
1780 22:14:26.370086 [Byte1]: 76
1781 22:14:26.374250
1782 22:14:26.374835 Set Vref, RX VrefLevel [Byte0]: 77
1783 22:14:26.377361 [Byte1]: 77
1784 22:14:26.381858
1785 22:14:26.382440 Final RX Vref Byte 0 = 52 to rank0
1786 22:14:26.385157 Final RX Vref Byte 1 = 63 to rank0
1787 22:14:26.388442 Final RX Vref Byte 0 = 52 to rank1
1788 22:14:26.391424 Final RX Vref Byte 1 = 63 to rank1==
1789 22:14:26.394819 Dram Type= 6, Freq= 0, CH_1, rank 0
1790 22:14:26.401514 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1791 22:14:26.402107 ==
1792 22:14:26.402496 DQS Delay:
1793 22:14:26.402852 DQS0 = 0, DQS1 = 0
1794 22:14:26.404678 DQM Delay:
1795 22:14:26.405190 DQM0 = 92, DQM1 = 83
1796 22:14:26.408022 DQ Delay:
1797 22:14:26.412576 DQ0 =96, DQ1 =88, DQ2 =84, DQ3 =88
1798 22:14:26.414890 DQ4 =92, DQ5 =104, DQ6 =100, DQ7 =88
1799 22:14:26.418305 DQ8 =72, DQ9 =72, DQ10 =88, DQ11 =80
1800 22:14:26.421388 DQ12 =92, DQ13 =88, DQ14 =88, DQ15 =88
1801 22:14:26.421873
1802 22:14:26.422255
1803 22:14:26.428275 [DQSOSCAuto] RK0, (LSB)MR18= 0x3451, (MSB)MR19= 0x606, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps
1804 22:14:26.431605 CH1 RK0: MR19=606, MR18=3451
1805 22:14:26.438140 CH1_RK0: MR19=0x606, MR18=0x3451, DQSOSC=389, MR23=63, INC=97, DEC=65
1806 22:14:26.438731
1807 22:14:26.441306 ----->DramcWriteLeveling(PI) begin...
1808 22:14:26.441793 ==
1809 22:14:26.444681 Dram Type= 6, Freq= 0, CH_1, rank 1
1810 22:14:26.448227 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1811 22:14:26.448835 ==
1812 22:14:26.451404 Write leveling (Byte 0): 26 => 26
1813 22:14:26.454565 Write leveling (Byte 1): 31 => 31
1814 22:14:26.457831 DramcWriteLeveling(PI) end<-----
1815 22:14:26.458312
1816 22:14:26.458693 ==
1817 22:14:26.461078 Dram Type= 6, Freq= 0, CH_1, rank 1
1818 22:14:26.464728 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1819 22:14:26.465348 ==
1820 22:14:26.468122 [Gating] SW mode calibration
1821 22:14:26.474676 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1822 22:14:26.481482 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1823 22:14:26.484720 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1824 22:14:26.488352 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1825 22:14:26.494614 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 22:14:26.498083 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 22:14:26.501349 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 22:14:26.507812 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 22:14:26.510969 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 22:14:26.514709 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 22:14:26.520894 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 22:14:26.524178 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 22:14:26.527753 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 22:14:26.534596 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 22:14:26.538567 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 22:14:26.540738 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 22:14:26.547674 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 22:14:26.550837 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 22:14:26.553931 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1840 22:14:26.561115 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1841 22:14:26.564535 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1842 22:14:26.567650 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1843 22:14:26.574438 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1844 22:14:26.577683 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1845 22:14:26.580889 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1846 22:14:26.587812 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1847 22:14:26.590610 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1848 22:14:26.593978 0 9 4 | B1->B0 | 2424 2424 | 1 1 | (1 1) (1 1)
1849 22:14:26.600904 0 9 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
1850 22:14:26.603921 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1851 22:14:26.607396 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1852 22:14:26.613851 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1853 22:14:26.617302 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1854 22:14:26.620698 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1855 22:14:26.627218 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1856 22:14:26.630475 0 10 4 | B1->B0 | 2f2f 2f2f | 1 1 | (1 1) (1 1)
1857 22:14:26.633641 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1858 22:14:26.640550 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1859 22:14:26.643665 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1860 22:14:26.646999 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1861 22:14:26.654026 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1862 22:14:26.656908 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1863 22:14:26.660288 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1864 22:14:26.663838 0 11 4 | B1->B0 | 3030 2c2c | 0 0 | (0 0) (0 0)
1865 22:14:26.670206 0 11 8 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
1866 22:14:26.673688 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1867 22:14:26.677390 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1868 22:14:26.683767 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1869 22:14:26.687152 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1870 22:14:26.690435 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1871 22:14:26.697010 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1872 22:14:26.700335 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1873 22:14:26.703857 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1874 22:14:26.710145 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1875 22:14:26.713743 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1876 22:14:26.717301 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1877 22:14:26.723274 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1878 22:14:26.726790 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1879 22:14:26.730424 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1880 22:14:26.736745 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1881 22:14:26.739959 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1882 22:14:26.743361 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1883 22:14:26.750261 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1884 22:14:26.753413 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1885 22:14:26.756599 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1886 22:14:26.763632 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1887 22:14:26.767133 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1888 22:14:26.770509 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1889 22:14:26.776665 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1890 22:14:26.777268 Total UI for P1: 0, mck2ui 16
1891 22:14:26.783507 best dqsien dly found for B0: ( 0, 14, 2)
1892 22:14:26.784086 Total UI for P1: 0, mck2ui 16
1893 22:14:26.786670 best dqsien dly found for B1: ( 0, 14, 4)
1894 22:14:26.793153 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1895 22:14:26.796363 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1896 22:14:26.796983
1897 22:14:26.799743 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1898 22:14:26.803209 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1899 22:14:26.806346 [Gating] SW calibration Done
1900 22:14:26.806919 ==
1901 22:14:26.809703 Dram Type= 6, Freq= 0, CH_1, rank 1
1902 22:14:26.813194 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1903 22:14:26.813769 ==
1904 22:14:26.816161 RX Vref Scan: 0
1905 22:14:26.816797
1906 22:14:26.817198 RX Vref 0 -> 0, step: 1
1907 22:14:26.817549
1908 22:14:26.819381 RX Delay -130 -> 252, step: 16
1909 22:14:26.823038 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
1910 22:14:26.829887 iDelay=206, Bit 1, Center 85 (-18 ~ 189) 208
1911 22:14:26.832895 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1912 22:14:26.836175 iDelay=206, Bit 3, Center 93 (-18 ~ 205) 224
1913 22:14:26.839644 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1914 22:14:26.842616 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1915 22:14:26.849681 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1916 22:14:26.852753 iDelay=206, Bit 7, Center 85 (-18 ~ 189) 208
1917 22:14:26.856108 iDelay=206, Bit 8, Center 61 (-50 ~ 173) 224
1918 22:14:26.859737 iDelay=206, Bit 9, Center 77 (-34 ~ 189) 224
1919 22:14:26.862754 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1920 22:14:26.869569 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1921 22:14:26.872567 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224
1922 22:14:26.876142 iDelay=206, Bit 13, Center 93 (-18 ~ 205) 224
1923 22:14:26.879615 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1924 22:14:26.882638 iDelay=206, Bit 15, Center 93 (-18 ~ 205) 224
1925 22:14:26.886221 ==
1926 22:14:26.886793 Dram Type= 6, Freq= 0, CH_1, rank 1
1927 22:14:26.892526 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1928 22:14:26.893154 ==
1929 22:14:26.893535 DQS Delay:
1930 22:14:26.895835 DQS0 = 0, DQS1 = 0
1931 22:14:26.896410 DQM Delay:
1932 22:14:26.899325 DQM0 = 89, DQM1 = 83
1933 22:14:26.899900 DQ Delay:
1934 22:14:26.902619 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93
1935 22:14:26.905824 DQ4 =93, DQ5 =93, DQ6 =93, DQ7 =85
1936 22:14:26.909373 DQ8 =61, DQ9 =77, DQ10 =85, DQ11 =77
1937 22:14:26.912440 DQ12 =93, DQ13 =93, DQ14 =85, DQ15 =93
1938 22:14:26.913047
1939 22:14:26.913435
1940 22:14:26.913786 ==
1941 22:14:26.915479 Dram Type= 6, Freq= 0, CH_1, rank 1
1942 22:14:26.919201 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1943 22:14:26.919776 ==
1944 22:14:26.920159
1945 22:14:26.920511
1946 22:14:26.922903 TX Vref Scan disable
1947 22:14:26.925666 == TX Byte 0 ==
1948 22:14:26.928982 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1949 22:14:26.932420 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1950 22:14:26.935628 == TX Byte 1 ==
1951 22:14:26.938855 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1952 22:14:26.942131 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1953 22:14:26.942704 ==
1954 22:14:26.945292 Dram Type= 6, Freq= 0, CH_1, rank 1
1955 22:14:26.952199 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1956 22:14:26.952851 ==
1957 22:14:26.964337 TX Vref=22, minBit 13, minWin=27, winSum=455
1958 22:14:26.967579 TX Vref=24, minBit 13, minWin=27, winSum=457
1959 22:14:26.970510 TX Vref=26, minBit 8, minWin=27, winSum=456
1960 22:14:26.973994 TX Vref=28, minBit 15, minWin=27, winSum=459
1961 22:14:26.977598 TX Vref=30, minBit 8, minWin=28, winSum=461
1962 22:14:26.983909 TX Vref=32, minBit 15, minWin=27, winSum=459
1963 22:14:26.987623 [TxChooseVref] Worse bit 8, Min win 28, Win sum 461, Final Vref 30
1964 22:14:26.988198
1965 22:14:26.990472 Final TX Range 1 Vref 30
1966 22:14:26.991047
1967 22:14:26.991428 ==
1968 22:14:26.993988 Dram Type= 6, Freq= 0, CH_1, rank 1
1969 22:14:26.997343 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1970 22:14:27.000461 ==
1971 22:14:27.001070
1972 22:14:27.001452
1973 22:14:27.001798 TX Vref Scan disable
1974 22:14:27.004183 == TX Byte 0 ==
1975 22:14:27.007939 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1976 22:14:27.010953 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1977 22:14:27.014367 == TX Byte 1 ==
1978 22:14:27.018192 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1979 22:14:27.021375 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1980 22:14:27.024379
1981 22:14:27.024882 [DATLAT]
1982 22:14:27.025266 Freq=800, CH1 RK1
1983 22:14:27.025621
1984 22:14:27.027765 DATLAT Default: 0xa
1985 22:14:27.028336 0, 0xFFFF, sum = 0
1986 22:14:27.031393 1, 0xFFFF, sum = 0
1987 22:14:27.031974 2, 0xFFFF, sum = 0
1988 22:14:27.034282 3, 0xFFFF, sum = 0
1989 22:14:27.034765 4, 0xFFFF, sum = 0
1990 22:14:27.037435 5, 0xFFFF, sum = 0
1991 22:14:27.040645 6, 0xFFFF, sum = 0
1992 22:14:27.041209 7, 0xFFFF, sum = 0
1993 22:14:27.044054 8, 0xFFFF, sum = 0
1994 22:14:27.044537 9, 0x0, sum = 1
1995 22:14:27.044964 10, 0x0, sum = 2
1996 22:14:27.047276 11, 0x0, sum = 3
1997 22:14:27.047758 12, 0x0, sum = 4
1998 22:14:27.051023 best_step = 10
1999 22:14:27.051595
2000 22:14:27.051989 ==
2001 22:14:27.053870 Dram Type= 6, Freq= 0, CH_1, rank 1
2002 22:14:27.056965 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2003 22:14:27.057483 ==
2004 22:14:27.060542 RX Vref Scan: 0
2005 22:14:27.061136
2006 22:14:27.061696 RX Vref 0 -> 0, step: 1
2007 22:14:27.063575
2008 22:14:27.064051 RX Delay -95 -> 252, step: 8
2009 22:14:27.070812 iDelay=209, Bit 0, Center 96 (-7 ~ 200) 208
2010 22:14:27.073968 iDelay=209, Bit 1, Center 84 (-15 ~ 184) 200
2011 22:14:27.077623 iDelay=209, Bit 2, Center 80 (-23 ~ 184) 208
2012 22:14:27.080601 iDelay=209, Bit 3, Center 88 (-15 ~ 192) 208
2013 22:14:27.084301 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
2014 22:14:27.090602 iDelay=209, Bit 5, Center 100 (-7 ~ 208) 216
2015 22:14:27.093965 iDelay=209, Bit 6, Center 96 (-7 ~ 200) 208
2016 22:14:27.097691 iDelay=209, Bit 7, Center 88 (-15 ~ 192) 208
2017 22:14:27.100567 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
2018 22:14:27.103928 iDelay=209, Bit 9, Center 76 (-31 ~ 184) 216
2019 22:14:27.110621 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
2020 22:14:27.113815 iDelay=209, Bit 11, Center 80 (-31 ~ 192) 224
2021 22:14:27.117786 iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216
2022 22:14:27.120819 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
2023 22:14:27.127072 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
2024 22:14:27.131259 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
2025 22:14:27.131842 ==
2026 22:14:27.133452 Dram Type= 6, Freq= 0, CH_1, rank 1
2027 22:14:27.137233 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2028 22:14:27.137888 ==
2029 22:14:27.140482 DQS Delay:
2030 22:14:27.141014 DQS0 = 0, DQS1 = 0
2031 22:14:27.141404 DQM Delay:
2032 22:14:27.143799 DQM0 = 90, DQM1 = 83
2033 22:14:27.144360 DQ Delay:
2034 22:14:27.146987 DQ0 =96, DQ1 =84, DQ2 =80, DQ3 =88
2035 22:14:27.150278 DQ4 =92, DQ5 =100, DQ6 =96, DQ7 =88
2036 22:14:27.153228 DQ8 =68, DQ9 =76, DQ10 =84, DQ11 =80
2037 22:14:27.156565 DQ12 =92, DQ13 =88, DQ14 =88, DQ15 =88
2038 22:14:27.157085
2039 22:14:27.157463
2040 22:14:27.166993 [DQSOSCAuto] RK1, (LSB)MR18= 0x390e, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 395 ps
2041 22:14:27.167666 CH1 RK1: MR19=606, MR18=390E
2042 22:14:27.173469 CH1_RK1: MR19=0x606, MR18=0x390E, DQSOSC=395, MR23=63, INC=94, DEC=63
2043 22:14:27.176917 [RxdqsGatingPostProcess] freq 800
2044 22:14:27.183806 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2045 22:14:27.186787 Pre-setting of DQS Precalculation
2046 22:14:27.190343 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2047 22:14:27.197032 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2048 22:14:27.206990 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2049 22:14:27.207572
2050 22:14:27.207956
2051 22:14:27.210057 [Calibration Summary] 1600 Mbps
2052 22:14:27.210532 CH 0, Rank 0
2053 22:14:27.213705 SW Impedance : PASS
2054 22:14:27.214284 DUTY Scan : NO K
2055 22:14:27.216689 ZQ Calibration : PASS
2056 22:14:27.217299 Jitter Meter : NO K
2057 22:14:27.219842 CBT Training : PASS
2058 22:14:27.223670 Write leveling : PASS
2059 22:14:27.224290 RX DQS gating : PASS
2060 22:14:27.227241 RX DQ/DQS(RDDQC) : PASS
2061 22:14:27.230159 TX DQ/DQS : PASS
2062 22:14:27.230752 RX DATLAT : PASS
2063 22:14:27.233695 RX DQ/DQS(Engine): PASS
2064 22:14:27.236829 TX OE : NO K
2065 22:14:27.237485 All Pass.
2066 22:14:27.238047
2067 22:14:27.238441 CH 0, Rank 1
2068 22:14:27.239720 SW Impedance : PASS
2069 22:14:27.243016 DUTY Scan : NO K
2070 22:14:27.243598 ZQ Calibration : PASS
2071 22:14:27.246478 Jitter Meter : NO K
2072 22:14:27.249527 CBT Training : PASS
2073 22:14:27.250008 Write leveling : PASS
2074 22:14:27.253701 RX DQS gating : PASS
2075 22:14:27.256275 RX DQ/DQS(RDDQC) : PASS
2076 22:14:27.256756 TX DQ/DQS : PASS
2077 22:14:27.259854 RX DATLAT : PASS
2078 22:14:27.263311 RX DQ/DQS(Engine): PASS
2079 22:14:27.263895 TX OE : NO K
2080 22:14:27.266475 All Pass.
2081 22:14:27.267041
2082 22:14:27.267431 CH 1, Rank 0
2083 22:14:27.269338 SW Impedance : PASS
2084 22:14:27.269820 DUTY Scan : NO K
2085 22:14:27.272818 ZQ Calibration : PASS
2086 22:14:27.276347 Jitter Meter : NO K
2087 22:14:27.276969 CBT Training : PASS
2088 22:14:27.279435 Write leveling : PASS
2089 22:14:27.282906 RX DQS gating : PASS
2090 22:14:27.283492 RX DQ/DQS(RDDQC) : PASS
2091 22:14:27.285956 TX DQ/DQS : PASS
2092 22:14:27.286439 RX DATLAT : PASS
2093 22:14:27.289622 RX DQ/DQS(Engine): PASS
2094 22:14:27.292881 TX OE : NO K
2095 22:14:27.293468 All Pass.
2096 22:14:27.293857
2097 22:14:27.294213 CH 1, Rank 1
2098 22:14:27.296079 SW Impedance : PASS
2099 22:14:27.300585 DUTY Scan : NO K
2100 22:14:27.301202 ZQ Calibration : PASS
2101 22:14:27.302991 Jitter Meter : NO K
2102 22:14:27.306168 CBT Training : PASS
2103 22:14:27.306754 Write leveling : PASS
2104 22:14:27.309510 RX DQS gating : PASS
2105 22:14:27.313162 RX DQ/DQS(RDDQC) : PASS
2106 22:14:27.313743 TX DQ/DQS : PASS
2107 22:14:27.315991 RX DATLAT : PASS
2108 22:14:27.319250 RX DQ/DQS(Engine): PASS
2109 22:14:27.319728 TX OE : NO K
2110 22:14:27.322889 All Pass.
2111 22:14:27.323467
2112 22:14:27.323855 DramC Write-DBI off
2113 22:14:27.326447 PER_BANK_REFRESH: Hybrid Mode
2114 22:14:27.327048 TX_TRACKING: ON
2115 22:14:27.329349 [GetDramInforAfterCalByMRR] Vendor 6.
2116 22:14:27.336427 [GetDramInforAfterCalByMRR] Revision 606.
2117 22:14:27.339815 [GetDramInforAfterCalByMRR] Revision 2 0.
2118 22:14:27.340301 MR0 0x3b3b
2119 22:14:27.340683 MR8 0x5151
2120 22:14:27.342472 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2121 22:14:27.342954
2122 22:14:27.346312 MR0 0x3b3b
2123 22:14:27.346912 MR8 0x5151
2124 22:14:27.348983 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2125 22:14:27.349481
2126 22:14:27.359369 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2127 22:14:27.362602 [FAST_K] Save calibration result to emmc
2128 22:14:27.366197 [FAST_K] Save calibration result to emmc
2129 22:14:27.369113 dram_init: config_dvfs: 1
2130 22:14:27.372917 dramc_set_vcore_voltage set vcore to 662500
2131 22:14:27.376110 Read voltage for 1200, 2
2132 22:14:27.376697 Vio18 = 0
2133 22:14:27.377123 Vcore = 662500
2134 22:14:27.379030 Vdram = 0
2135 22:14:27.379621 Vddq = 0
2136 22:14:27.380006 Vmddr = 0
2137 22:14:27.385625 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2138 22:14:27.388890 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2139 22:14:27.392090 MEM_TYPE=3, freq_sel=15
2140 22:14:27.395776 sv_algorithm_assistance_LP4_1600
2141 22:14:27.399336 ============ PULL DRAM RESETB DOWN ============
2142 22:14:27.402542 ========== PULL DRAM RESETB DOWN end =========
2143 22:14:27.409208 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2144 22:14:27.412394 ===================================
2145 22:14:27.413016 LPDDR4 DRAM CONFIGURATION
2146 22:14:27.415695 ===================================
2147 22:14:27.419259 EX_ROW_EN[0] = 0x0
2148 22:14:27.422193 EX_ROW_EN[1] = 0x0
2149 22:14:27.422781 LP4Y_EN = 0x0
2150 22:14:27.425469 WORK_FSP = 0x0
2151 22:14:27.425951 WL = 0x4
2152 22:14:27.429128 RL = 0x4
2153 22:14:27.429717 BL = 0x2
2154 22:14:27.433401 RPST = 0x0
2155 22:14:27.433981 RD_PRE = 0x0
2156 22:14:27.435360 WR_PRE = 0x1
2157 22:14:27.435835 WR_PST = 0x0
2158 22:14:27.439436 DBI_WR = 0x0
2159 22:14:27.439907 DBI_RD = 0x0
2160 22:14:27.442277 OTF = 0x1
2161 22:14:27.445647 ===================================
2162 22:14:27.449162 ===================================
2163 22:14:27.449762 ANA top config
2164 22:14:27.452070 ===================================
2165 22:14:27.455461 DLL_ASYNC_EN = 0
2166 22:14:27.458541 ALL_SLAVE_EN = 0
2167 22:14:27.461951 NEW_RANK_MODE = 1
2168 22:14:27.462533 DLL_IDLE_MODE = 1
2169 22:14:27.465876 LP45_APHY_COMB_EN = 1
2170 22:14:27.468972 TX_ODT_DIS = 1
2171 22:14:27.472244 NEW_8X_MODE = 1
2172 22:14:27.475485 ===================================
2173 22:14:27.478612 ===================================
2174 22:14:27.482062 data_rate = 2400
2175 22:14:27.482643 CKR = 1
2176 22:14:27.485448 DQ_P2S_RATIO = 8
2177 22:14:27.488524 ===================================
2178 22:14:27.491739 CA_P2S_RATIO = 8
2179 22:14:27.495415 DQ_CA_OPEN = 0
2180 22:14:27.498560 DQ_SEMI_OPEN = 0
2181 22:14:27.502136 CA_SEMI_OPEN = 0
2182 22:14:27.502714 CA_FULL_RATE = 0
2183 22:14:27.504925 DQ_CKDIV4_EN = 0
2184 22:14:27.508576 CA_CKDIV4_EN = 0
2185 22:14:27.511851 CA_PREDIV_EN = 0
2186 22:14:27.515110 PH8_DLY = 17
2187 22:14:27.518829 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2188 22:14:27.519402 DQ_AAMCK_DIV = 4
2189 22:14:27.521460 CA_AAMCK_DIV = 4
2190 22:14:27.525375 CA_ADMCK_DIV = 4
2191 22:14:27.528568 DQ_TRACK_CA_EN = 0
2192 22:14:27.531707 CA_PICK = 1200
2193 22:14:27.535125 CA_MCKIO = 1200
2194 22:14:27.538178 MCKIO_SEMI = 0
2195 22:14:27.538652 PLL_FREQ = 2366
2196 22:14:27.541709 DQ_UI_PI_RATIO = 32
2197 22:14:27.544965 CA_UI_PI_RATIO = 0
2198 22:14:27.548172 ===================================
2199 22:14:27.551902 ===================================
2200 22:14:27.555031 memory_type:LPDDR4
2201 22:14:27.555606 GP_NUM : 10
2202 22:14:27.558266 SRAM_EN : 1
2203 22:14:27.561894 MD32_EN : 0
2204 22:14:27.565415 ===================================
2205 22:14:27.565989 [ANA_INIT] >>>>>>>>>>>>>>
2206 22:14:27.568475 <<<<<< [CONFIGURE PHASE]: ANA_TX
2207 22:14:27.572000 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2208 22:14:27.575633 ===================================
2209 22:14:27.578246 data_rate = 2400,PCW = 0X5b00
2210 22:14:27.581803 ===================================
2211 22:14:27.585007 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2212 22:14:27.591639 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2213 22:14:27.595163 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2214 22:14:27.601443 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2215 22:14:27.604943 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2216 22:14:27.607780 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2217 22:14:27.611535 [ANA_INIT] flow start
2218 22:14:27.612008 [ANA_INIT] PLL >>>>>>>>
2219 22:14:27.614655 [ANA_INIT] PLL <<<<<<<<
2220 22:14:27.618194 [ANA_INIT] MIDPI >>>>>>>>
2221 22:14:27.618770 [ANA_INIT] MIDPI <<<<<<<<
2222 22:14:27.621198 [ANA_INIT] DLL >>>>>>>>
2223 22:14:27.624650 [ANA_INIT] DLL <<<<<<<<
2224 22:14:27.625341 [ANA_INIT] flow end
2225 22:14:27.628246 ============ LP4 DIFF to SE enter ============
2226 22:14:27.634570 ============ LP4 DIFF to SE exit ============
2227 22:14:27.635146 [ANA_INIT] <<<<<<<<<<<<<
2228 22:14:27.638025 [Flow] Enable top DCM control >>>>>
2229 22:14:27.641157 [Flow] Enable top DCM control <<<<<
2230 22:14:27.644868 Enable DLL master slave shuffle
2231 22:14:27.651255 ==============================================================
2232 22:14:27.654397 Gating Mode config
2233 22:14:27.657427 ==============================================================
2234 22:14:27.660980 Config description:
2235 22:14:27.670977 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2236 22:14:27.677806 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2237 22:14:27.680923 SELPH_MODE 0: By rank 1: By Phase
2238 22:14:27.687598 ==============================================================
2239 22:14:27.691006 GAT_TRACK_EN = 1
2240 22:14:27.694390 RX_GATING_MODE = 2
2241 22:14:27.694968 RX_GATING_TRACK_MODE = 2
2242 22:14:27.697654 SELPH_MODE = 1
2243 22:14:27.700916 PICG_EARLY_EN = 1
2244 22:14:27.704041 VALID_LAT_VALUE = 1
2245 22:14:27.710580 ==============================================================
2246 22:14:27.714594 Enter into Gating configuration >>>>
2247 22:14:27.717273 Exit from Gating configuration <<<<
2248 22:14:27.720739 Enter into DVFS_PRE_config >>>>>
2249 22:14:27.730676 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2250 22:14:27.734087 Exit from DVFS_PRE_config <<<<<
2251 22:14:27.737446 Enter into PICG configuration >>>>
2252 22:14:27.740636 Exit from PICG configuration <<<<
2253 22:14:27.743929 [RX_INPUT] configuration >>>>>
2254 22:14:27.747644 [RX_INPUT] configuration <<<<<
2255 22:14:27.750620 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2256 22:14:27.757274 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2257 22:14:27.763856 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2258 22:14:27.770733 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2259 22:14:27.774211 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2260 22:14:27.780634 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2261 22:14:27.783908 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2262 22:14:27.790717 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2263 22:14:27.794106 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2264 22:14:27.797317 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2265 22:14:27.800588 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2266 22:14:27.806902 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2267 22:14:27.810332 ===================================
2268 22:14:27.813710 LPDDR4 DRAM CONFIGURATION
2269 22:14:27.814287 ===================================
2270 22:14:27.816700 EX_ROW_EN[0] = 0x0
2271 22:14:27.820185 EX_ROW_EN[1] = 0x0
2272 22:14:27.820753 LP4Y_EN = 0x0
2273 22:14:27.824250 WORK_FSP = 0x0
2274 22:14:27.824883 WL = 0x4
2275 22:14:27.826916 RL = 0x4
2276 22:14:27.827387 BL = 0x2
2277 22:14:27.830213 RPST = 0x0
2278 22:14:27.830689 RD_PRE = 0x0
2279 22:14:27.833164 WR_PRE = 0x1
2280 22:14:27.833636 WR_PST = 0x0
2281 22:14:27.836843 DBI_WR = 0x0
2282 22:14:27.837317 DBI_RD = 0x0
2283 22:14:27.839924 OTF = 0x1
2284 22:14:27.843155 ===================================
2285 22:14:27.846586 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2286 22:14:27.850017 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2287 22:14:27.857243 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2288 22:14:27.860035 ===================================
2289 22:14:27.860534 LPDDR4 DRAM CONFIGURATION
2290 22:14:27.863570 ===================================
2291 22:14:27.866654 EX_ROW_EN[0] = 0x10
2292 22:14:27.870178 EX_ROW_EN[1] = 0x0
2293 22:14:27.870782 LP4Y_EN = 0x0
2294 22:14:27.873780 WORK_FSP = 0x0
2295 22:14:27.874361 WL = 0x4
2296 22:14:27.877207 RL = 0x4
2297 22:14:27.877790 BL = 0x2
2298 22:14:27.880028 RPST = 0x0
2299 22:14:27.880609 RD_PRE = 0x0
2300 22:14:27.883727 WR_PRE = 0x1
2301 22:14:27.884306 WR_PST = 0x0
2302 22:14:27.886804 DBI_WR = 0x0
2303 22:14:27.887382 DBI_RD = 0x0
2304 22:14:27.890722 OTF = 0x1
2305 22:14:27.893150 ===================================
2306 22:14:27.900231 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2307 22:14:27.900850 ==
2308 22:14:27.903194 Dram Type= 6, Freq= 0, CH_0, rank 0
2309 22:14:27.906800 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2310 22:14:27.907268 ==
2311 22:14:27.909724 [Duty_Offset_Calibration]
2312 22:14:27.910186 B0:2 B1:0 CA:1
2313 22:14:27.910554
2314 22:14:27.913109 [DutyScan_Calibration_Flow] k_type=0
2315 22:14:27.922500
2316 22:14:27.922961 ==CLK 0==
2317 22:14:27.926092 Final CLK duty delay cell = -4
2318 22:14:27.929204 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2319 22:14:27.932538 [-4] MIN Duty = 4875%(X100), DQS PI = 0
2320 22:14:27.935907 [-4] AVG Duty = 4953%(X100)
2321 22:14:27.936501
2322 22:14:27.939538 CH0 CLK Duty spec in!! Max-Min= 156%
2323 22:14:27.942358 [DutyScan_Calibration_Flow] ====Done====
2324 22:14:27.942832
2325 22:14:27.945693 [DutyScan_Calibration_Flow] k_type=1
2326 22:14:27.961625
2327 22:14:27.962189 ==DQS 0 ==
2328 22:14:27.964702 Final DQS duty delay cell = 0
2329 22:14:27.968390 [0] MAX Duty = 5187%(X100), DQS PI = 30
2330 22:14:27.971436 [0] MIN Duty = 4938%(X100), DQS PI = 0
2331 22:14:27.972010 [0] AVG Duty = 5062%(X100)
2332 22:14:27.975037
2333 22:14:27.975626 ==DQS 1 ==
2334 22:14:27.978404 Final DQS duty delay cell = -4
2335 22:14:27.981580 [-4] MAX Duty = 5124%(X100), DQS PI = 32
2336 22:14:27.985011 [-4] MIN Duty = 4938%(X100), DQS PI = 8
2337 22:14:27.988297 [-4] AVG Duty = 5031%(X100)
2338 22:14:27.988905
2339 22:14:27.991506 CH0 DQS 0 Duty spec in!! Max-Min= 249%
2340 22:14:27.992079
2341 22:14:27.994710 CH0 DQS 1 Duty spec in!! Max-Min= 186%
2342 22:14:27.998406 [DutyScan_Calibration_Flow] ====Done====
2343 22:14:27.998977
2344 22:14:28.001496 [DutyScan_Calibration_Flow] k_type=3
2345 22:14:28.017660
2346 22:14:28.018240 ==DQM 0 ==
2347 22:14:28.021072 Final DQM duty delay cell = 0
2348 22:14:28.024402 [0] MAX Duty = 5062%(X100), DQS PI = 24
2349 22:14:28.028374 [0] MIN Duty = 4875%(X100), DQS PI = 0
2350 22:14:28.028983 [0] AVG Duty = 4968%(X100)
2351 22:14:28.030975
2352 22:14:28.031544 ==DQM 1 ==
2353 22:14:28.034285 Final DQM duty delay cell = -4
2354 22:14:28.037414 [-4] MAX Duty = 5000%(X100), DQS PI = 32
2355 22:14:28.040881 [-4] MIN Duty = 4813%(X100), DQS PI = 10
2356 22:14:28.043849 [-4] AVG Duty = 4906%(X100)
2357 22:14:28.044316
2358 22:14:28.047172 CH0 DQM 0 Duty spec in!! Max-Min= 187%
2359 22:14:28.047638
2360 22:14:28.050735 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2361 22:14:28.054223 [DutyScan_Calibration_Flow] ====Done====
2362 22:14:28.054811
2363 22:14:28.057073 [DutyScan_Calibration_Flow] k_type=2
2364 22:14:28.073678
2365 22:14:28.074257 ==DQ 0 ==
2366 22:14:28.077113 Final DQ duty delay cell = -4
2367 22:14:28.080382 [-4] MAX Duty = 5031%(X100), DQS PI = 34
2368 22:14:28.083809 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2369 22:14:28.087297 [-4] AVG Duty = 4969%(X100)
2370 22:14:28.087888
2371 22:14:28.088277 ==DQ 1 ==
2372 22:14:28.090503 Final DQ duty delay cell = 0
2373 22:14:28.093904 [0] MAX Duty = 4938%(X100), DQS PI = 4
2374 22:14:28.097005 [0] MIN Duty = 4907%(X100), DQS PI = 0
2375 22:14:28.097490 [0] AVG Duty = 4922%(X100)
2376 22:14:28.097877
2377 22:14:28.103931 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2378 22:14:28.104520
2379 22:14:28.106886 CH0 DQ 1 Duty spec in!! Max-Min= 31%
2380 22:14:28.110327 [DutyScan_Calibration_Flow] ====Done====
2381 22:14:28.110916 ==
2382 22:14:28.113475 Dram Type= 6, Freq= 0, CH_1, rank 0
2383 22:14:28.116958 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2384 22:14:28.117545 ==
2385 22:14:28.120382 [Duty_Offset_Calibration]
2386 22:14:28.121007 B0:0 B1:-1 CA:2
2387 22:14:28.121402
2388 22:14:28.123659 [DutyScan_Calibration_Flow] k_type=0
2389 22:14:28.134028
2390 22:14:28.134613 ==CLK 0==
2391 22:14:28.137330 Final CLK duty delay cell = 0
2392 22:14:28.140210 [0] MAX Duty = 5156%(X100), DQS PI = 16
2393 22:14:28.143561 [0] MIN Duty = 4938%(X100), DQS PI = 44
2394 22:14:28.146664 [0] AVG Duty = 5047%(X100)
2395 22:14:28.147143
2396 22:14:28.149955 CH1 CLK Duty spec in!! Max-Min= 218%
2397 22:14:28.153455 [DutyScan_Calibration_Flow] ====Done====
2398 22:14:28.153939
2399 22:14:28.156700 [DutyScan_Calibration_Flow] k_type=1
2400 22:14:28.173237
2401 22:14:28.173837 ==DQS 0 ==
2402 22:14:28.176274 Final DQS duty delay cell = 0
2403 22:14:28.179526 [0] MAX Duty = 5093%(X100), DQS PI = 24
2404 22:14:28.183064 [0] MIN Duty = 4969%(X100), DQS PI = 0
2405 22:14:28.186162 [0] AVG Duty = 5031%(X100)
2406 22:14:28.186739
2407 22:14:28.187131 ==DQS 1 ==
2408 22:14:28.189602 Final DQS duty delay cell = 0
2409 22:14:28.193621 [0] MAX Duty = 5156%(X100), DQS PI = 0
2410 22:14:28.196531 [0] MIN Duty = 4875%(X100), DQS PI = 34
2411 22:14:28.200042 [0] AVG Duty = 5015%(X100)
2412 22:14:28.200617
2413 22:14:28.203247 CH1 DQS 0 Duty spec in!! Max-Min= 124%
2414 22:14:28.203827
2415 22:14:28.206708 CH1 DQS 1 Duty spec in!! Max-Min= 281%
2416 22:14:28.209753 [DutyScan_Calibration_Flow] ====Done====
2417 22:14:28.210329
2418 22:14:28.212702 [DutyScan_Calibration_Flow] k_type=3
2419 22:14:28.229520
2420 22:14:28.230094 ==DQM 0 ==
2421 22:14:28.232876 Final DQM duty delay cell = 4
2422 22:14:28.236257 [4] MAX Duty = 5093%(X100), DQS PI = 4
2423 22:14:28.240199 [4] MIN Duty = 4969%(X100), DQS PI = 28
2424 22:14:28.240818 [4] AVG Duty = 5031%(X100)
2425 22:14:28.243206
2426 22:14:28.243964 ==DQM 1 ==
2427 22:14:28.246343 Final DQM duty delay cell = -4
2428 22:14:28.249577 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2429 22:14:28.252467 [-4] MIN Duty = 4782%(X100), DQS PI = 34
2430 22:14:28.256631 [-4] AVG Duty = 4891%(X100)
2431 22:14:28.257259
2432 22:14:28.259139 CH1 DQM 0 Duty spec in!! Max-Min= 124%
2433 22:14:28.259642
2434 22:14:28.262629 CH1 DQM 1 Duty spec in!! Max-Min= 218%
2435 22:14:28.265926 [DutyScan_Calibration_Flow] ====Done====
2436 22:14:28.266411
2437 22:14:28.269529 [DutyScan_Calibration_Flow] k_type=2
2438 22:14:28.286483
2439 22:14:28.287075 ==DQ 0 ==
2440 22:14:28.290188 Final DQ duty delay cell = 0
2441 22:14:28.293385 [0] MAX Duty = 5062%(X100), DQS PI = 20
2442 22:14:28.296067 [0] MIN Duty = 4938%(X100), DQS PI = 46
2443 22:14:28.296553 [0] AVG Duty = 5000%(X100)
2444 22:14:28.299811
2445 22:14:28.300395 ==DQ 1 ==
2446 22:14:28.303263 Final DQ duty delay cell = 0
2447 22:14:28.306660 [0] MAX Duty = 5031%(X100), DQS PI = 2
2448 22:14:28.309428 [0] MIN Duty = 4813%(X100), DQS PI = 34
2449 22:14:28.309913 [0] AVG Duty = 4922%(X100)
2450 22:14:28.310301
2451 22:14:28.313155 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2452 22:14:28.316591
2453 22:14:28.319480 CH1 DQ 1 Duty spec in!! Max-Min= 218%
2454 22:14:28.322822 [DutyScan_Calibration_Flow] ====Done====
2455 22:14:28.326130 nWR fixed to 30
2456 22:14:28.326729 [ModeRegInit_LP4] CH0 RK0
2457 22:14:28.329629 [ModeRegInit_LP4] CH0 RK1
2458 22:14:28.332843 [ModeRegInit_LP4] CH1 RK0
2459 22:14:28.333432 [ModeRegInit_LP4] CH1 RK1
2460 22:14:28.336442 match AC timing 7
2461 22:14:28.339570 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2462 22:14:28.346112 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2463 22:14:28.349309 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2464 22:14:28.352536 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2465 22:14:28.359445 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2466 22:14:28.359959 ==
2467 22:14:28.362798 Dram Type= 6, Freq= 0, CH_0, rank 0
2468 22:14:28.366011 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2469 22:14:28.366502 ==
2470 22:14:28.372932 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2471 22:14:28.379459 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
2472 22:14:28.386107 [CA 0] Center 38 (8~69) winsize 62
2473 22:14:28.389634 [CA 1] Center 38 (7~69) winsize 63
2474 22:14:28.392804 [CA 2] Center 35 (5~66) winsize 62
2475 22:14:28.396870 [CA 3] Center 35 (5~66) winsize 62
2476 22:14:28.399579 [CA 4] Center 34 (4~65) winsize 62
2477 22:14:28.402962 [CA 5] Center 33 (3~63) winsize 61
2478 22:14:28.403537
2479 22:14:28.406255 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2480 22:14:28.406832
2481 22:14:28.409681 [CATrainingPosCal] consider 1 rank data
2482 22:14:28.413145 u2DelayCellTimex100 = 270/100 ps
2483 22:14:28.416234 CA0 delay=38 (8~69),Diff = 5 PI (24 cell)
2484 22:14:28.419609 CA1 delay=38 (7~69),Diff = 5 PI (24 cell)
2485 22:14:28.426451 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2486 22:14:28.429771 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2487 22:14:28.432841 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2488 22:14:28.436110 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2489 22:14:28.436685
2490 22:14:28.439365 CA PerBit enable=1, Macro0, CA PI delay=33
2491 22:14:28.439941
2492 22:14:28.442618 [CBTSetCACLKResult] CA Dly = 33
2493 22:14:28.443198 CS Dly: 6 (0~37)
2494 22:14:28.445908 ==
2495 22:14:28.449020 Dram Type= 6, Freq= 0, CH_0, rank 1
2496 22:14:28.452741 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2497 22:14:28.453358 ==
2498 22:14:28.456220 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2499 22:14:28.462063 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2500 22:14:28.472033 [CA 0] Center 39 (8~70) winsize 63
2501 22:14:28.475415 [CA 1] Center 38 (8~69) winsize 62
2502 22:14:28.478485 [CA 2] Center 35 (5~66) winsize 62
2503 22:14:28.482099 [CA 3] Center 35 (5~66) winsize 62
2504 22:14:28.485620 [CA 4] Center 34 (4~65) winsize 62
2505 22:14:28.488577 [CA 5] Center 34 (4~64) winsize 61
2506 22:14:28.489206
2507 22:14:28.491774 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2508 22:14:28.492259
2509 22:14:28.495177 [CATrainingPosCal] consider 2 rank data
2510 22:14:28.498731 u2DelayCellTimex100 = 270/100 ps
2511 22:14:28.501885 CA0 delay=38 (8~69),Diff = 5 PI (24 cell)
2512 22:14:28.505175 CA1 delay=38 (8~69),Diff = 5 PI (24 cell)
2513 22:14:28.512009 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2514 22:14:28.515390 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2515 22:14:28.518663 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2516 22:14:28.521712 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
2517 22:14:28.522301
2518 22:14:28.525092 CA PerBit enable=1, Macro0, CA PI delay=33
2519 22:14:28.525679
2520 22:14:28.528543 [CBTSetCACLKResult] CA Dly = 33
2521 22:14:28.529171 CS Dly: 7 (0~39)
2522 22:14:28.529562
2523 22:14:28.531897 ----->DramcWriteLeveling(PI) begin...
2524 22:14:28.535319 ==
2525 22:14:28.538463 Dram Type= 6, Freq= 0, CH_0, rank 0
2526 22:14:28.541697 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2527 22:14:28.542287 ==
2528 22:14:28.545010 Write leveling (Byte 0): 33 => 33
2529 22:14:28.548205 Write leveling (Byte 1): 31 => 31
2530 22:14:28.551794 DramcWriteLeveling(PI) end<-----
2531 22:14:28.552382
2532 22:14:28.552810 ==
2533 22:14:28.554891 Dram Type= 6, Freq= 0, CH_0, rank 0
2534 22:14:28.558212 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2535 22:14:28.558703 ==
2536 22:14:28.561236 [Gating] SW mode calibration
2537 22:14:28.568285 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2538 22:14:28.574690 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2539 22:14:28.577962 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2540 22:14:28.581475 0 15 4 | B1->B0 | 2b2b 3434 | 0 1 | (0 0) (1 1)
2541 22:14:28.587859 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2542 22:14:28.591627 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2543 22:14:28.594590 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2544 22:14:28.601156 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2545 22:14:28.604999 0 15 24 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 0)
2546 22:14:28.608006 0 15 28 | B1->B0 | 3434 2727 | 1 0 | (1 1) (1 0)
2547 22:14:28.611463 1 0 0 | B1->B0 | 2c2c 2323 | 1 0 | (1 0) (0 0)
2548 22:14:28.618356 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2549 22:14:28.621613 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2550 22:14:28.624484 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2551 22:14:28.631523 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2552 22:14:28.634836 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2553 22:14:28.637670 1 0 24 | B1->B0 | 2323 3636 | 0 1 | (0 0) (0 0)
2554 22:14:28.644635 1 0 28 | B1->B0 | 2424 4646 | 0 0 | (0 0) (0 0)
2555 22:14:28.648188 1 1 0 | B1->B0 | 3232 4646 | 1 0 | (0 0) (0 0)
2556 22:14:28.651428 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2557 22:14:28.657390 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2558 22:14:28.661154 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2559 22:14:28.664339 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2560 22:14:28.671425 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2561 22:14:28.674737 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2562 22:14:28.678055 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2563 22:14:28.684507 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2564 22:14:28.687590 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2565 22:14:28.691098 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2566 22:14:28.697616 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2567 22:14:28.701152 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2568 22:14:28.704294 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2569 22:14:28.711027 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2570 22:14:28.713897 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2571 22:14:28.717712 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2572 22:14:28.724469 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2573 22:14:28.727596 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2574 22:14:28.730930 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2575 22:14:28.737700 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2576 22:14:28.740925 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2577 22:14:28.744197 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2578 22:14:28.747244 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2579 22:14:28.754452 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2580 22:14:28.757197 Total UI for P1: 0, mck2ui 16
2581 22:14:28.761455 best dqsien dly found for B0: ( 1, 3, 26)
2582 22:14:28.764268 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2583 22:14:28.767296 Total UI for P1: 0, mck2ui 16
2584 22:14:28.770761 best dqsien dly found for B1: ( 1, 4, 0)
2585 22:14:28.773969 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2586 22:14:28.777612 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2587 22:14:28.778202
2588 22:14:28.780412 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2589 22:14:28.784035 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2590 22:14:28.787072 [Gating] SW calibration Done
2591 22:14:28.787554 ==
2592 22:14:28.791086 Dram Type= 6, Freq= 0, CH_0, rank 0
2593 22:14:28.797117 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2594 22:14:28.797709 ==
2595 22:14:28.798102 RX Vref Scan: 0
2596 22:14:28.798464
2597 22:14:28.801115 RX Vref 0 -> 0, step: 1
2598 22:14:28.801700
2599 22:14:28.803734 RX Delay -40 -> 252, step: 8
2600 22:14:28.807377 iDelay=208, Bit 0, Center 123 (56 ~ 191) 136
2601 22:14:28.810379 iDelay=208, Bit 1, Center 123 (56 ~ 191) 136
2602 22:14:28.813586 iDelay=208, Bit 2, Center 119 (48 ~ 191) 144
2603 22:14:28.817237 iDelay=208, Bit 3, Center 119 (48 ~ 191) 144
2604 22:14:28.824339 iDelay=208, Bit 4, Center 127 (56 ~ 199) 144
2605 22:14:28.827045 iDelay=208, Bit 5, Center 115 (48 ~ 183) 136
2606 22:14:28.830605 iDelay=208, Bit 6, Center 131 (56 ~ 207) 152
2607 22:14:28.833397 iDelay=208, Bit 7, Center 127 (56 ~ 199) 144
2608 22:14:28.837284 iDelay=208, Bit 8, Center 99 (32 ~ 167) 136
2609 22:14:28.843443 iDelay=208, Bit 9, Center 99 (32 ~ 167) 136
2610 22:14:28.846853 iDelay=208, Bit 10, Center 107 (40 ~ 175) 136
2611 22:14:28.850043 iDelay=208, Bit 11, Center 107 (40 ~ 175) 136
2612 22:14:28.853615 iDelay=208, Bit 12, Center 115 (48 ~ 183) 136
2613 22:14:28.857065 iDelay=208, Bit 13, Center 111 (48 ~ 175) 128
2614 22:14:28.863463 iDelay=208, Bit 14, Center 123 (56 ~ 191) 136
2615 22:14:28.866935 iDelay=208, Bit 15, Center 115 (48 ~ 183) 136
2616 22:14:28.867413 ==
2617 22:14:28.870130 Dram Type= 6, Freq= 0, CH_0, rank 0
2618 22:14:28.873450 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2619 22:14:28.874028 ==
2620 22:14:28.876921 DQS Delay:
2621 22:14:28.877493 DQS0 = 0, DQS1 = 0
2622 22:14:28.880340 DQM Delay:
2623 22:14:28.880950 DQM0 = 123, DQM1 = 109
2624 22:14:28.881340 DQ Delay:
2625 22:14:28.883505 DQ0 =123, DQ1 =123, DQ2 =119, DQ3 =119
2626 22:14:28.886826 DQ4 =127, DQ5 =115, DQ6 =131, DQ7 =127
2627 22:14:28.893272 DQ8 =99, DQ9 =99, DQ10 =107, DQ11 =107
2628 22:14:28.896593 DQ12 =115, DQ13 =111, DQ14 =123, DQ15 =115
2629 22:14:28.897206
2630 22:14:28.897594
2631 22:14:28.897948 ==
2632 22:14:28.899979 Dram Type= 6, Freq= 0, CH_0, rank 0
2633 22:14:28.903061 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2634 22:14:28.903542 ==
2635 22:14:28.903924
2636 22:14:28.904277
2637 22:14:28.906460 TX Vref Scan disable
2638 22:14:28.907039 == TX Byte 0 ==
2639 22:14:28.913232 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2640 22:14:28.916448 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2641 22:14:28.920322 == TX Byte 1 ==
2642 22:14:28.923373 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2643 22:14:28.926734 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2644 22:14:28.927322 ==
2645 22:14:28.929397 Dram Type= 6, Freq= 0, CH_0, rank 0
2646 22:14:28.933723 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2647 22:14:28.934302 ==
2648 22:14:28.945993 TX Vref=22, minBit 6, minWin=24, winSum=407
2649 22:14:28.949454 TX Vref=24, minBit 0, minWin=25, winSum=410
2650 22:14:28.952992 TX Vref=26, minBit 0, minWin=25, winSum=415
2651 22:14:28.956587 TX Vref=28, minBit 1, minWin=25, winSum=422
2652 22:14:28.959469 TX Vref=30, minBit 7, minWin=25, winSum=420
2653 22:14:28.962857 TX Vref=32, minBit 1, minWin=24, winSum=414
2654 22:14:28.969526 [TxChooseVref] Worse bit 1, Min win 25, Win sum 422, Final Vref 28
2655 22:14:28.970107
2656 22:14:28.973111 Final TX Range 1 Vref 28
2657 22:14:28.973689
2658 22:14:28.974071 ==
2659 22:14:28.976438 Dram Type= 6, Freq= 0, CH_0, rank 0
2660 22:14:28.979605 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2661 22:14:28.980182 ==
2662 22:14:28.980562
2663 22:14:28.982842
2664 22:14:28.983410 TX Vref Scan disable
2665 22:14:28.986119 == TX Byte 0 ==
2666 22:14:28.989606 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2667 22:14:28.992831 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2668 22:14:28.996160 == TX Byte 1 ==
2669 22:14:28.999353 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2670 22:14:29.002880 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2671 22:14:29.006164
2672 22:14:29.006731 [DATLAT]
2673 22:14:29.007114 Freq=1200, CH0 RK0
2674 22:14:29.007470
2675 22:14:29.009190 DATLAT Default: 0xd
2676 22:14:29.009669 0, 0xFFFF, sum = 0
2677 22:14:29.012393 1, 0xFFFF, sum = 0
2678 22:14:29.013002 2, 0xFFFF, sum = 0
2679 22:14:29.015840 3, 0xFFFF, sum = 0
2680 22:14:29.016444 4, 0xFFFF, sum = 0
2681 22:14:29.019565 5, 0xFFFF, sum = 0
2682 22:14:29.022363 6, 0xFFFF, sum = 0
2683 22:14:29.022864 7, 0xFFFF, sum = 0
2684 22:14:29.025973 8, 0xFFFF, sum = 0
2685 22:14:29.026551 9, 0xFFFF, sum = 0
2686 22:14:29.029100 10, 0xFFFF, sum = 0
2687 22:14:29.029581 11, 0xFFFF, sum = 0
2688 22:14:29.032325 12, 0x0, sum = 1
2689 22:14:29.032938 13, 0x0, sum = 2
2690 22:14:29.035948 14, 0x0, sum = 3
2691 22:14:29.036550 15, 0x0, sum = 4
2692 22:14:29.036983 best_step = 13
2693 22:14:29.038932
2694 22:14:29.039407 ==
2695 22:14:29.042346 Dram Type= 6, Freq= 0, CH_0, rank 0
2696 22:14:29.045874 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2697 22:14:29.046360 ==
2698 22:14:29.046745 RX Vref Scan: 1
2699 22:14:29.047100
2700 22:14:29.049023 Set Vref Range= 32 -> 127
2701 22:14:29.049504
2702 22:14:29.052606 RX Vref 32 -> 127, step: 1
2703 22:14:29.053113
2704 22:14:29.055490 RX Delay -13 -> 252, step: 4
2705 22:14:29.055964
2706 22:14:29.058823 Set Vref, RX VrefLevel [Byte0]: 32
2707 22:14:29.062231 [Byte1]: 32
2708 22:14:29.062729
2709 22:14:29.065806 Set Vref, RX VrefLevel [Byte0]: 33
2710 22:14:29.069285 [Byte1]: 33
2711 22:14:29.072362
2712 22:14:29.072972 Set Vref, RX VrefLevel [Byte0]: 34
2713 22:14:29.075788 [Byte1]: 34
2714 22:14:29.080562
2715 22:14:29.081168 Set Vref, RX VrefLevel [Byte0]: 35
2716 22:14:29.083309 [Byte1]: 35
2717 22:14:29.087999
2718 22:14:29.088574 Set Vref, RX VrefLevel [Byte0]: 36
2719 22:14:29.091767 [Byte1]: 36
2720 22:14:29.095803
2721 22:14:29.096374 Set Vref, RX VrefLevel [Byte0]: 37
2722 22:14:29.099459 [Byte1]: 37
2723 22:14:29.103556
2724 22:14:29.104034 Set Vref, RX VrefLevel [Byte0]: 38
2725 22:14:29.107070 [Byte1]: 38
2726 22:14:29.111420
2727 22:14:29.111895 Set Vref, RX VrefLevel [Byte0]: 39
2728 22:14:29.114647 [Byte1]: 39
2729 22:14:29.119498
2730 22:14:29.120071 Set Vref, RX VrefLevel [Byte0]: 40
2731 22:14:29.122631 [Byte1]: 40
2732 22:14:29.127219
2733 22:14:29.127791 Set Vref, RX VrefLevel [Byte0]: 41
2734 22:14:29.130387 [Byte1]: 41
2735 22:14:29.135320
2736 22:14:29.135890 Set Vref, RX VrefLevel [Byte0]: 42
2737 22:14:29.139253 [Byte1]: 42
2738 22:14:29.143337
2739 22:14:29.143911 Set Vref, RX VrefLevel [Byte0]: 43
2740 22:14:29.146504 [Byte1]: 43
2741 22:14:29.151285
2742 22:14:29.151858 Set Vref, RX VrefLevel [Byte0]: 44
2743 22:14:29.154804 [Byte1]: 44
2744 22:14:29.159066
2745 22:14:29.159650 Set Vref, RX VrefLevel [Byte0]: 45
2746 22:14:29.162217 [Byte1]: 45
2747 22:14:29.167026
2748 22:14:29.167599 Set Vref, RX VrefLevel [Byte0]: 46
2749 22:14:29.170435 [Byte1]: 46
2750 22:14:29.175302
2751 22:14:29.175872 Set Vref, RX VrefLevel [Byte0]: 47
2752 22:14:29.178604 [Byte1]: 47
2753 22:14:29.182926
2754 22:14:29.183502 Set Vref, RX VrefLevel [Byte0]: 48
2755 22:14:29.186103 [Byte1]: 48
2756 22:14:29.190767
2757 22:14:29.191339 Set Vref, RX VrefLevel [Byte0]: 49
2758 22:14:29.193806 [Byte1]: 49
2759 22:14:29.198732
2760 22:14:29.199301 Set Vref, RX VrefLevel [Byte0]: 50
2761 22:14:29.202505 [Byte1]: 50
2762 22:14:29.206758
2763 22:14:29.207328 Set Vref, RX VrefLevel [Byte0]: 51
2764 22:14:29.209761 [Byte1]: 51
2765 22:14:29.214355
2766 22:14:29.214930 Set Vref, RX VrefLevel [Byte0]: 52
2767 22:14:29.217679 [Byte1]: 52
2768 22:14:29.222235
2769 22:14:29.222804 Set Vref, RX VrefLevel [Byte0]: 53
2770 22:14:29.225729 [Byte1]: 53
2771 22:14:29.230207
2772 22:14:29.230779 Set Vref, RX VrefLevel [Byte0]: 54
2773 22:14:29.233458 [Byte1]: 54
2774 22:14:29.237792
2775 22:14:29.238379 Set Vref, RX VrefLevel [Byte0]: 55
2776 22:14:29.241189 [Byte1]: 55
2777 22:14:29.245762
2778 22:14:29.246376 Set Vref, RX VrefLevel [Byte0]: 56
2779 22:14:29.248881 [Byte1]: 56
2780 22:14:29.253482
2781 22:14:29.254122 Set Vref, RX VrefLevel [Byte0]: 57
2782 22:14:29.256617 [Byte1]: 57
2783 22:14:29.261730
2784 22:14:29.262279 Set Vref, RX VrefLevel [Byte0]: 58
2785 22:14:29.265539 [Byte1]: 58
2786 22:14:29.269489
2787 22:14:29.270084 Set Vref, RX VrefLevel [Byte0]: 59
2788 22:14:29.272840 [Byte1]: 59
2789 22:14:29.277665
2790 22:14:29.278239 Set Vref, RX VrefLevel [Byte0]: 60
2791 22:14:29.280612 [Byte1]: 60
2792 22:14:29.285708
2793 22:14:29.286285 Set Vref, RX VrefLevel [Byte0]: 61
2794 22:14:29.288706 [Byte1]: 61
2795 22:14:29.293700
2796 22:14:29.294274 Set Vref, RX VrefLevel [Byte0]: 62
2797 22:14:29.296915 [Byte1]: 62
2798 22:14:29.301195
2799 22:14:29.301771 Set Vref, RX VrefLevel [Byte0]: 63
2800 22:14:29.304556 [Byte1]: 63
2801 22:14:29.309021
2802 22:14:29.309595 Set Vref, RX VrefLevel [Byte0]: 64
2803 22:14:29.312870 [Byte1]: 64
2804 22:14:29.317016
2805 22:14:29.317585 Set Vref, RX VrefLevel [Byte0]: 65
2806 22:14:29.320105 [Byte1]: 65
2807 22:14:29.324695
2808 22:14:29.325311 Set Vref, RX VrefLevel [Byte0]: 66
2809 22:14:29.328380 [Byte1]: 66
2810 22:14:29.332853
2811 22:14:29.333422 Set Vref, RX VrefLevel [Byte0]: 67
2812 22:14:29.335906 [Byte1]: 67
2813 22:14:29.340624
2814 22:14:29.341234 Set Vref, RX VrefLevel [Byte0]: 68
2815 22:14:29.343554 [Byte1]: 68
2816 22:14:29.348422
2817 22:14:29.349051 Set Vref, RX VrefLevel [Byte0]: 69
2818 22:14:29.351935 [Byte1]: 69
2819 22:14:29.356129
2820 22:14:29.356606 Final RX Vref Byte 0 = 58 to rank0
2821 22:14:29.359434 Final RX Vref Byte 1 = 49 to rank0
2822 22:14:29.362738 Final RX Vref Byte 0 = 58 to rank1
2823 22:14:29.366249 Final RX Vref Byte 1 = 49 to rank1==
2824 22:14:29.369713 Dram Type= 6, Freq= 0, CH_0, rank 0
2825 22:14:29.377032 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2826 22:14:29.377613 ==
2827 22:14:29.378000 DQS Delay:
2828 22:14:29.378358 DQS0 = 0, DQS1 = 0
2829 22:14:29.379532 DQM Delay:
2830 22:14:29.380007 DQM0 = 123, DQM1 = 109
2831 22:14:29.383180 DQ Delay:
2832 22:14:29.386419 DQ0 =122, DQ1 =122, DQ2 =120, DQ3 =120
2833 22:14:29.389722 DQ4 =126, DQ5 =116, DQ6 =130, DQ7 =128
2834 22:14:29.393127 DQ8 =100, DQ9 =94, DQ10 =110, DQ11 =104
2835 22:14:29.396408 DQ12 =116, DQ13 =110, DQ14 =122, DQ15 =116
2836 22:14:29.397028
2837 22:14:29.397414
2838 22:14:29.402839 [DQSOSCAuto] RK0, (LSB)MR18= 0x906, (MSB)MR19= 0x404, tDQSOscB0 = 407 ps tDQSOscB1 = 406 ps
2839 22:14:29.406346 CH0 RK0: MR19=404, MR18=906
2840 22:14:29.412859 CH0_RK0: MR19=0x404, MR18=0x906, DQSOSC=406, MR23=63, INC=39, DEC=26
2841 22:14:29.413437
2842 22:14:29.416279 ----->DramcWriteLeveling(PI) begin...
2843 22:14:29.416899 ==
2844 22:14:29.419747 Dram Type= 6, Freq= 0, CH_0, rank 1
2845 22:14:29.422677 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2846 22:14:29.426534 ==
2847 22:14:29.427111 Write leveling (Byte 0): 35 => 35
2848 22:14:29.429200 Write leveling (Byte 1): 29 => 29
2849 22:14:29.432927 DramcWriteLeveling(PI) end<-----
2850 22:14:29.433490
2851 22:14:29.433871 ==
2852 22:14:29.436579 Dram Type= 6, Freq= 0, CH_0, rank 1
2853 22:14:29.442994 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2854 22:14:29.443574 ==
2855 22:14:29.443962 [Gating] SW mode calibration
2856 22:14:29.452671 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2857 22:14:29.455967 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2858 22:14:29.462378 0 15 0 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
2859 22:14:29.466023 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2860 22:14:29.469189 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2861 22:14:29.472557 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2862 22:14:29.479614 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2863 22:14:29.482232 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2864 22:14:29.485846 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2865 22:14:29.492488 0 15 28 | B1->B0 | 3131 2c2c | 1 0 | (1 0) (0 0)
2866 22:14:29.496180 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
2867 22:14:29.502279 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2868 22:14:29.505047 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2869 22:14:29.508505 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2870 22:14:29.511450 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2871 22:14:29.518126 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2872 22:14:29.521695 1 0 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
2873 22:14:29.524770 1 0 28 | B1->B0 | 3939 4545 | 0 0 | (0 0) (0 0)
2874 22:14:29.531314 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2875 22:14:29.535050 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2876 22:14:29.538965 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2877 22:14:29.544708 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2878 22:14:29.548085 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2879 22:14:29.551581 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2880 22:14:29.558051 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2881 22:14:29.561185 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2882 22:14:29.564681 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2883 22:14:29.571272 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2884 22:14:29.575282 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2885 22:14:29.577804 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2886 22:14:29.584712 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2887 22:14:29.588141 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2888 22:14:29.591222 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2889 22:14:29.598027 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2890 22:14:29.601765 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2891 22:14:29.604429 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2892 22:14:29.610988 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2893 22:14:29.614351 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2894 22:14:29.617770 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2895 22:14:29.624269 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2896 22:14:29.627793 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2897 22:14:29.631382 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2898 22:14:29.638149 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2899 22:14:29.638280 Total UI for P1: 0, mck2ui 16
2900 22:14:29.641669 best dqsien dly found for B0: ( 1, 3, 28)
2901 22:14:29.644608 Total UI for P1: 0, mck2ui 16
2902 22:14:29.647785 best dqsien dly found for B1: ( 1, 3, 28)
2903 22:14:29.651063 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2904 22:14:29.657805 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2905 22:14:29.657910
2906 22:14:29.660762 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2907 22:14:29.664363 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2908 22:14:29.667410 [Gating] SW calibration Done
2909 22:14:29.667496 ==
2910 22:14:29.670938 Dram Type= 6, Freq= 0, CH_0, rank 1
2911 22:14:29.674185 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2912 22:14:29.674292 ==
2913 22:14:29.678176 RX Vref Scan: 0
2914 22:14:29.678268
2915 22:14:29.678335 RX Vref 0 -> 0, step: 1
2916 22:14:29.678399
2917 22:14:29.680666 RX Delay -40 -> 252, step: 8
2918 22:14:29.684200 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2919 22:14:29.690773 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2920 22:14:29.694433 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2921 22:14:29.697566 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2922 22:14:29.701215 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2923 22:14:29.703933 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2924 22:14:29.710966 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2925 22:14:29.713968 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2926 22:14:29.717328 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2927 22:14:29.720644 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2928 22:14:29.724002 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2929 22:14:29.730591 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2930 22:14:29.733962 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2931 22:14:29.737296 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2932 22:14:29.740487 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2933 22:14:29.743953 iDelay=200, Bit 15, Center 111 (48 ~ 175) 128
2934 22:14:29.747058 ==
2935 22:14:29.747233 Dram Type= 6, Freq= 0, CH_0, rank 1
2936 22:14:29.753762 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2937 22:14:29.753950 ==
2938 22:14:29.754046 DQS Delay:
2939 22:14:29.757113 DQS0 = 0, DQS1 = 0
2940 22:14:29.757300 DQM Delay:
2941 22:14:29.760508 DQM0 = 120, DQM1 = 108
2942 22:14:29.760699 DQ Delay:
2943 22:14:29.764275 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =115
2944 22:14:29.767043 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2945 22:14:29.770209 DQ8 =99, DQ9 =95, DQ10 =107, DQ11 =107
2946 22:14:29.773708 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =111
2947 22:14:29.773953
2948 22:14:29.774092
2949 22:14:29.774224 ==
2950 22:14:29.776642 Dram Type= 6, Freq= 0, CH_0, rank 1
2951 22:14:29.784014 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2952 22:14:29.784321 ==
2953 22:14:29.784524
2954 22:14:29.784713
2955 22:14:29.784891 TX Vref Scan disable
2956 22:14:29.786738 == TX Byte 0 ==
2957 22:14:29.790446 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
2958 22:14:29.797060 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
2959 22:14:29.797641 == TX Byte 1 ==
2960 22:14:29.800329 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2961 22:14:29.807482 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2962 22:14:29.807965 ==
2963 22:14:29.810575 Dram Type= 6, Freq= 0, CH_0, rank 1
2964 22:14:29.813766 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2965 22:14:29.814344 ==
2966 22:14:29.825925 TX Vref=22, minBit 3, minWin=23, winSum=405
2967 22:14:29.829161 TX Vref=24, minBit 3, minWin=24, winSum=413
2968 22:14:29.832355 TX Vref=26, minBit 2, minWin=24, winSum=415
2969 22:14:29.835824 TX Vref=28, minBit 1, minWin=24, winSum=417
2970 22:14:29.839379 TX Vref=30, minBit 1, minWin=25, winSum=417
2971 22:14:29.845587 TX Vref=32, minBit 0, minWin=25, winSum=416
2972 22:14:29.849207 [TxChooseVref] Worse bit 1, Min win 25, Win sum 417, Final Vref 30
2973 22:14:29.849784
2974 22:14:29.852335 Final TX Range 1 Vref 30
2975 22:14:29.852859
2976 22:14:29.853254 ==
2977 22:14:29.855466 Dram Type= 6, Freq= 0, CH_0, rank 1
2978 22:14:29.859002 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2979 22:14:29.859584 ==
2980 22:14:29.859970
2981 22:14:29.862359
2982 22:14:29.862931 TX Vref Scan disable
2983 22:14:29.865442 == TX Byte 0 ==
2984 22:14:29.869143 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
2985 22:14:29.872576 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
2986 22:14:29.875528 == TX Byte 1 ==
2987 22:14:29.879170 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2988 22:14:29.882196 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2989 22:14:29.886217
2990 22:14:29.886788 [DATLAT]
2991 22:14:29.887173 Freq=1200, CH0 RK1
2992 22:14:29.887531
2993 22:14:29.888990 DATLAT Default: 0xd
2994 22:14:29.889613 0, 0xFFFF, sum = 0
2995 22:14:29.892416 1, 0xFFFF, sum = 0
2996 22:14:29.893007 2, 0xFFFF, sum = 0
2997 22:14:29.895290 3, 0xFFFF, sum = 0
2998 22:14:29.895812 4, 0xFFFF, sum = 0
2999 22:14:29.898616 5, 0xFFFF, sum = 0
3000 22:14:29.902321 6, 0xFFFF, sum = 0
3001 22:14:29.902945 7, 0xFFFF, sum = 0
3002 22:14:29.905333 8, 0xFFFF, sum = 0
3003 22:14:29.905822 9, 0xFFFF, sum = 0
3004 22:14:29.909136 10, 0xFFFF, sum = 0
3005 22:14:29.909719 11, 0xFFFF, sum = 0
3006 22:14:29.912451 12, 0x0, sum = 1
3007 22:14:29.913198 13, 0x0, sum = 2
3008 22:14:29.915187 14, 0x0, sum = 3
3009 22:14:29.915672 15, 0x0, sum = 4
3010 22:14:29.916114 best_step = 13
3011 22:14:29.918929
3012 22:14:29.919500 ==
3013 22:14:29.921997 Dram Type= 6, Freq= 0, CH_0, rank 1
3014 22:14:29.925310 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3015 22:14:29.925889 ==
3016 22:14:29.926275 RX Vref Scan: 0
3017 22:14:29.926636
3018 22:14:29.928695 RX Vref 0 -> 0, step: 1
3019 22:14:29.929198
3020 22:14:29.931821 RX Delay -21 -> 252, step: 4
3021 22:14:29.935302 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
3022 22:14:29.941816 iDelay=195, Bit 1, Center 122 (55 ~ 190) 136
3023 22:14:29.945684 iDelay=195, Bit 2, Center 116 (51 ~ 182) 132
3024 22:14:29.949115 iDelay=195, Bit 3, Center 114 (51 ~ 178) 128
3025 22:14:29.952001 iDelay=195, Bit 4, Center 120 (55 ~ 186) 132
3026 22:14:29.955717 iDelay=195, Bit 5, Center 114 (51 ~ 178) 128
3027 22:14:29.962354 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3028 22:14:29.964877 iDelay=195, Bit 7, Center 126 (59 ~ 194) 136
3029 22:14:29.968503 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3030 22:14:29.971483 iDelay=195, Bit 9, Center 94 (31 ~ 158) 128
3031 22:14:29.975062 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3032 22:14:29.981675 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3033 22:14:29.985638 iDelay=195, Bit 12, Center 112 (47 ~ 178) 132
3034 22:14:29.988217 iDelay=195, Bit 13, Center 110 (47 ~ 174) 128
3035 22:14:29.992000 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3036 22:14:29.995229 iDelay=195, Bit 15, Center 114 (51 ~ 178) 128
3037 22:14:29.998188 ==
3038 22:14:30.001569 Dram Type= 6, Freq= 0, CH_0, rank 1
3039 22:14:30.005110 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3040 22:14:30.005713 ==
3041 22:14:30.006111 DQS Delay:
3042 22:14:30.008361 DQS0 = 0, DQS1 = 0
3043 22:14:30.008880 DQM Delay:
3044 22:14:30.011354 DQM0 = 119, DQM1 = 107
3045 22:14:30.011838 DQ Delay:
3046 22:14:30.014604 DQ0 =118, DQ1 =122, DQ2 =116, DQ3 =114
3047 22:14:30.018353 DQ4 =120, DQ5 =114, DQ6 =126, DQ7 =126
3048 22:14:30.021463 DQ8 =98, DQ9 =94, DQ10 =110, DQ11 =106
3049 22:14:30.024880 DQ12 =112, DQ13 =110, DQ14 =118, DQ15 =114
3050 22:14:30.025365
3051 22:14:30.025744
3052 22:14:30.035234 [DQSOSCAuto] RK1, (LSB)MR18= 0xef5, (MSB)MR19= 0x403, tDQSOscB0 = 414 ps tDQSOscB1 = 404 ps
3053 22:14:30.035819 CH0 RK1: MR19=403, MR18=EF5
3054 22:14:30.041558 CH0_RK1: MR19=0x403, MR18=0xEF5, DQSOSC=404, MR23=63, INC=40, DEC=26
3055 22:14:30.044928 [RxdqsGatingPostProcess] freq 1200
3056 22:14:30.051241 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3057 22:14:30.054775 best DQS0 dly(2T, 0.5T) = (0, 11)
3058 22:14:30.058089 best DQS1 dly(2T, 0.5T) = (0, 12)
3059 22:14:30.061630 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3060 22:14:30.064491 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3061 22:14:30.067828 best DQS0 dly(2T, 0.5T) = (0, 11)
3062 22:14:30.071129 best DQS1 dly(2T, 0.5T) = (0, 11)
3063 22:14:30.074778 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3064 22:14:30.075357 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3065 22:14:30.077621 Pre-setting of DQS Precalculation
3066 22:14:30.085068 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3067 22:14:30.085644 ==
3068 22:14:30.087811 Dram Type= 6, Freq= 0, CH_1, rank 0
3069 22:14:30.091419 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3070 22:14:30.092004 ==
3071 22:14:30.097910 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3072 22:14:30.104397 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=23, u1VrefScanEnd=33
3073 22:14:30.111518 [CA 0] Center 37 (7~68) winsize 62
3074 22:14:30.115290 [CA 1] Center 37 (7~68) winsize 62
3075 22:14:30.118333 [CA 2] Center 35 (5~65) winsize 61
3076 22:14:30.121606 [CA 3] Center 34 (4~65) winsize 62
3077 22:14:30.124817 [CA 4] Center 33 (3~64) winsize 62
3078 22:14:30.128581 [CA 5] Center 33 (3~64) winsize 62
3079 22:14:30.129204
3080 22:14:30.131358 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3081 22:14:30.131839
3082 22:14:30.135103 [CATrainingPosCal] consider 1 rank data
3083 22:14:30.138022 u2DelayCellTimex100 = 270/100 ps
3084 22:14:30.141378 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3085 22:14:30.147813 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3086 22:14:30.151309 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3087 22:14:30.154328 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3088 22:14:30.158161 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3089 22:14:30.160849 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3090 22:14:30.161512
3091 22:14:30.164939 CA PerBit enable=1, Macro0, CA PI delay=33
3092 22:14:30.165518
3093 22:14:30.167798 [CBTSetCACLKResult] CA Dly = 33
3094 22:14:30.168427 CS Dly: 5 (0~36)
3095 22:14:30.171038 ==
3096 22:14:30.174579 Dram Type= 6, Freq= 0, CH_1, rank 1
3097 22:14:30.177561 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3098 22:14:30.178042 ==
3099 22:14:30.181360 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3100 22:14:30.187508 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3101 22:14:30.197382 [CA 0] Center 38 (8~68) winsize 61
3102 22:14:30.200665 [CA 1] Center 38 (7~69) winsize 63
3103 22:14:30.204199 [CA 2] Center 35 (5~66) winsize 62
3104 22:14:30.206850 [CA 3] Center 35 (5~65) winsize 61
3105 22:14:30.210734 [CA 4] Center 35 (5~65) winsize 61
3106 22:14:30.213655 [CA 5] Center 34 (4~64) winsize 61
3107 22:14:30.214139
3108 22:14:30.217132 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3109 22:14:30.217612
3110 22:14:30.220294 [CATrainingPosCal] consider 2 rank data
3111 22:14:30.223954 u2DelayCellTimex100 = 270/100 ps
3112 22:14:30.227405 CA0 delay=38 (8~68),Diff = 4 PI (19 cell)
3113 22:14:30.233659 CA1 delay=37 (7~68),Diff = 3 PI (14 cell)
3114 22:14:30.237333 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3115 22:14:30.240564 CA3 delay=35 (5~65),Diff = 1 PI (4 cell)
3116 22:14:30.243934 CA4 delay=34 (5~64),Diff = 0 PI (0 cell)
3117 22:14:30.247105 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3118 22:14:30.247586
3119 22:14:30.250018 CA PerBit enable=1, Macro0, CA PI delay=34
3120 22:14:30.250503
3121 22:14:30.253563 [CBTSetCACLKResult] CA Dly = 34
3122 22:14:30.254088 CS Dly: 6 (0~39)
3123 22:14:30.254661
3124 22:14:30.260573 ----->DramcWriteLeveling(PI) begin...
3125 22:14:30.261198 ==
3126 22:14:30.263508 Dram Type= 6, Freq= 0, CH_1, rank 0
3127 22:14:30.267187 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3128 22:14:30.267767 ==
3129 22:14:30.270282 Write leveling (Byte 0): 23 => 23
3130 22:14:30.273660 Write leveling (Byte 1): 28 => 28
3131 22:14:30.277309 DramcWriteLeveling(PI) end<-----
3132 22:14:30.277880
3133 22:14:30.278266 ==
3134 22:14:30.280258 Dram Type= 6, Freq= 0, CH_1, rank 0
3135 22:14:30.283466 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3136 22:14:30.283954 ==
3137 22:14:30.287069 [Gating] SW mode calibration
3138 22:14:30.293604 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3139 22:14:30.300468 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3140 22:14:30.303278 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3141 22:14:30.306885 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3142 22:14:30.314379 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3143 22:14:30.316696 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3144 22:14:30.320206 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3145 22:14:30.326401 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3146 22:14:30.329764 0 15 24 | B1->B0 | 2929 2525 | 1 0 | (1 0) (1 0)
3147 22:14:30.333076 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3148 22:14:30.339814 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3149 22:14:30.343638 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3150 22:14:30.346427 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3151 22:14:30.349673 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3152 22:14:30.356406 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3153 22:14:30.359759 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3154 22:14:30.363217 1 0 24 | B1->B0 | 3b3a 4646 | 1 0 | (0 0) (0 0)
3155 22:14:30.370564 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3156 22:14:30.373264 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3157 22:14:30.376920 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3158 22:14:30.383501 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3159 22:14:30.387172 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3160 22:14:30.389958 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3161 22:14:30.396423 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3162 22:14:30.400554 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3163 22:14:30.403536 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3164 22:14:30.410220 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3165 22:14:30.413608 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3166 22:14:30.416536 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3167 22:14:30.423217 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3168 22:14:30.426524 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3169 22:14:30.430608 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3170 22:14:30.436645 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3171 22:14:30.439822 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3172 22:14:30.443724 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3173 22:14:30.446899 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3174 22:14:30.452934 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3175 22:14:30.456716 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3176 22:14:30.459761 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3177 22:14:30.466097 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3178 22:14:30.469521 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3179 22:14:30.472812 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3180 22:14:30.476398 Total UI for P1: 0, mck2ui 16
3181 22:14:30.479835 best dqsien dly found for B0: ( 1, 3, 22)
3182 22:14:30.486502 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3183 22:14:30.489641 Total UI for P1: 0, mck2ui 16
3184 22:14:30.492928 best dqsien dly found for B1: ( 1, 3, 26)
3185 22:14:30.496126 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3186 22:14:30.499558 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3187 22:14:30.500133
3188 22:14:30.502964 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3189 22:14:30.506160 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3190 22:14:30.509749 [Gating] SW calibration Done
3191 22:14:30.510325 ==
3192 22:14:30.512628 Dram Type= 6, Freq= 0, CH_1, rank 0
3193 22:14:30.516407 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3194 22:14:30.517050 ==
3195 22:14:30.519717 RX Vref Scan: 0
3196 22:14:30.520291
3197 22:14:30.522627 RX Vref 0 -> 0, step: 1
3198 22:14:30.523346
3199 22:14:30.523830 RX Delay -40 -> 252, step: 8
3200 22:14:30.529325 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3201 22:14:30.532665 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3202 22:14:30.536104 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3203 22:14:30.539200 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3204 22:14:30.542619 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3205 22:14:30.549560 iDelay=200, Bit 5, Center 127 (64 ~ 191) 128
3206 22:14:30.552518 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3207 22:14:30.555748 iDelay=200, Bit 7, Center 119 (56 ~ 183) 128
3208 22:14:30.559027 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3209 22:14:30.562500 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3210 22:14:30.568720 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3211 22:14:30.572352 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3212 22:14:30.575317 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3213 22:14:30.579426 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3214 22:14:30.585499 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3215 22:14:30.588629 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3216 22:14:30.589228 ==
3217 22:14:30.591999 Dram Type= 6, Freq= 0, CH_1, rank 0
3218 22:14:30.595623 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3219 22:14:30.596111 ==
3220 22:14:30.596496 DQS Delay:
3221 22:14:30.598598 DQS0 = 0, DQS1 = 0
3222 22:14:30.599171 DQM Delay:
3223 22:14:30.602025 DQM0 = 119, DQM1 = 112
3224 22:14:30.602600 DQ Delay:
3225 22:14:30.605477 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3226 22:14:30.608615 DQ4 =115, DQ5 =127, DQ6 =127, DQ7 =119
3227 22:14:30.612026 DQ8 =99, DQ9 =99, DQ10 =115, DQ11 =107
3228 22:14:30.615056 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =119
3229 22:14:30.615621
3230 22:14:30.618240
3231 22:14:30.618719 ==
3232 22:14:30.621540 Dram Type= 6, Freq= 0, CH_1, rank 0
3233 22:14:30.624817 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3234 22:14:30.625009 ==
3235 22:14:30.625088
3236 22:14:30.625161
3237 22:14:30.628450 TX Vref Scan disable
3238 22:14:30.628613 == TX Byte 0 ==
3239 22:14:30.635079 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3240 22:14:30.638197 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3241 22:14:30.638363 == TX Byte 1 ==
3242 22:14:30.645569 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3243 22:14:30.648065 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3244 22:14:30.648246 ==
3245 22:14:30.650975 Dram Type= 6, Freq= 0, CH_1, rank 0
3246 22:14:30.654357 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3247 22:14:30.654550 ==
3248 22:14:30.667097 TX Vref=22, minBit 1, minWin=24, winSum=409
3249 22:14:30.670609 TX Vref=24, minBit 10, minWin=24, winSum=411
3250 22:14:30.673998 TX Vref=26, minBit 8, minWin=25, winSum=420
3251 22:14:30.677836 TX Vref=28, minBit 8, minWin=25, winSum=422
3252 22:14:30.680601 TX Vref=30, minBit 1, minWin=26, winSum=423
3253 22:14:30.686699 TX Vref=32, minBit 9, minWin=25, winSum=420
3254 22:14:30.690362 [TxChooseVref] Worse bit 1, Min win 26, Win sum 423, Final Vref 30
3255 22:14:30.690847
3256 22:14:30.694190 Final TX Range 1 Vref 30
3257 22:14:30.694770
3258 22:14:30.695160 ==
3259 22:14:30.697174 Dram Type= 6, Freq= 0, CH_1, rank 0
3260 22:14:30.700358 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3261 22:14:30.703681 ==
3262 22:14:30.704256
3263 22:14:30.704640
3264 22:14:30.705028 TX Vref Scan disable
3265 22:14:30.707107 == TX Byte 0 ==
3266 22:14:30.710467 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
3267 22:14:30.717144 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
3268 22:14:30.717743 == TX Byte 1 ==
3269 22:14:30.720688 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3270 22:14:30.727778 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3271 22:14:30.728358
3272 22:14:30.728738 [DATLAT]
3273 22:14:30.729144 Freq=1200, CH1 RK0
3274 22:14:30.729492
3275 22:14:30.730414 DATLAT Default: 0xd
3276 22:14:30.730888 0, 0xFFFF, sum = 0
3277 22:14:30.733886 1, 0xFFFF, sum = 0
3278 22:14:30.737368 2, 0xFFFF, sum = 0
3279 22:14:30.737948 3, 0xFFFF, sum = 0
3280 22:14:30.740482 4, 0xFFFF, sum = 0
3281 22:14:30.741098 5, 0xFFFF, sum = 0
3282 22:14:30.744143 6, 0xFFFF, sum = 0
3283 22:14:30.744724 7, 0xFFFF, sum = 0
3284 22:14:30.747065 8, 0xFFFF, sum = 0
3285 22:14:30.747644 9, 0xFFFF, sum = 0
3286 22:14:30.750871 10, 0xFFFF, sum = 0
3287 22:14:30.751453 11, 0xFFFF, sum = 0
3288 22:14:30.753466 12, 0x0, sum = 1
3289 22:14:30.754025 13, 0x0, sum = 2
3290 22:14:30.756947 14, 0x0, sum = 3
3291 22:14:30.757431 15, 0x0, sum = 4
3292 22:14:30.760425 best_step = 13
3293 22:14:30.761035
3294 22:14:30.761458 ==
3295 22:14:30.763843 Dram Type= 6, Freq= 0, CH_1, rank 0
3296 22:14:30.766966 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3297 22:14:30.767569 ==
3298 22:14:30.768113 RX Vref Scan: 1
3299 22:14:30.768492
3300 22:14:30.770481 Set Vref Range= 32 -> 127
3301 22:14:30.770957
3302 22:14:30.773553 RX Vref 32 -> 127, step: 1
3303 22:14:30.774029
3304 22:14:30.776747 RX Delay -13 -> 252, step: 4
3305 22:14:30.777284
3306 22:14:30.780314 Set Vref, RX VrefLevel [Byte0]: 32
3307 22:14:30.783546 [Byte1]: 32
3308 22:14:30.784023
3309 22:14:30.786730 Set Vref, RX VrefLevel [Byte0]: 33
3310 22:14:30.789876 [Byte1]: 33
3311 22:14:30.793429
3312 22:14:30.793890 Set Vref, RX VrefLevel [Byte0]: 34
3313 22:14:30.796820 [Byte1]: 34
3314 22:14:30.801437
3315 22:14:30.801901 Set Vref, RX VrefLevel [Byte0]: 35
3316 22:14:30.804825 [Byte1]: 35
3317 22:14:30.809250
3318 22:14:30.809713 Set Vref, RX VrefLevel [Byte0]: 36
3319 22:14:30.812731 [Byte1]: 36
3320 22:14:30.817471
3321 22:14:30.818031 Set Vref, RX VrefLevel [Byte0]: 37
3322 22:14:30.820295 [Byte1]: 37
3323 22:14:30.825338
3324 22:14:30.825996 Set Vref, RX VrefLevel [Byte0]: 38
3325 22:14:30.828440 [Byte1]: 38
3326 22:14:30.833017
3327 22:14:30.833476 Set Vref, RX VrefLevel [Byte0]: 39
3328 22:14:30.836739 [Byte1]: 39
3329 22:14:30.841280
3330 22:14:30.841746 Set Vref, RX VrefLevel [Byte0]: 40
3331 22:14:30.844303 [Byte1]: 40
3332 22:14:30.848940
3333 22:14:30.849407 Set Vref, RX VrefLevel [Byte0]: 41
3334 22:14:30.852073 [Byte1]: 41
3335 22:14:30.857035
3336 22:14:30.857650 Set Vref, RX VrefLevel [Byte0]: 42
3337 22:14:30.860018 [Byte1]: 42
3338 22:14:30.864950
3339 22:14:30.865509 Set Vref, RX VrefLevel [Byte0]: 43
3340 22:14:30.868733 [Byte1]: 43
3341 22:14:30.872833
3342 22:14:30.873420 Set Vref, RX VrefLevel [Byte0]: 44
3343 22:14:30.875851 [Byte1]: 44
3344 22:14:30.880813
3345 22:14:30.881399 Set Vref, RX VrefLevel [Byte0]: 45
3346 22:14:30.883855 [Byte1]: 45
3347 22:14:30.888404
3348 22:14:30.889005 Set Vref, RX VrefLevel [Byte0]: 46
3349 22:14:30.891859 [Byte1]: 46
3350 22:14:30.896312
3351 22:14:30.896922 Set Vref, RX VrefLevel [Byte0]: 47
3352 22:14:30.899421 [Byte1]: 47
3353 22:14:30.904048
3354 22:14:30.904615 Set Vref, RX VrefLevel [Byte0]: 48
3355 22:14:30.908092 [Byte1]: 48
3356 22:14:30.912139
3357 22:14:30.912710 Set Vref, RX VrefLevel [Byte0]: 49
3358 22:14:30.915378 [Byte1]: 49
3359 22:14:30.920389
3360 22:14:30.921011 Set Vref, RX VrefLevel [Byte0]: 50
3361 22:14:30.923077 [Byte1]: 50
3362 22:14:30.927514
3363 22:14:30.927978 Set Vref, RX VrefLevel [Byte0]: 51
3364 22:14:30.931306 [Byte1]: 51
3365 22:14:30.935692
3366 22:14:30.936265 Set Vref, RX VrefLevel [Byte0]: 52
3367 22:14:30.939122 [Byte1]: 52
3368 22:14:30.943809
3369 22:14:30.944383 Set Vref, RX VrefLevel [Byte0]: 53
3370 22:14:30.946953 [Byte1]: 53
3371 22:14:30.951393
3372 22:14:30.951979 Set Vref, RX VrefLevel [Byte0]: 54
3373 22:14:30.954632 [Byte1]: 54
3374 22:14:30.959342
3375 22:14:30.959921 Set Vref, RX VrefLevel [Byte0]: 55
3376 22:14:30.962609 [Byte1]: 55
3377 22:14:30.967968
3378 22:14:30.968540 Set Vref, RX VrefLevel [Byte0]: 56
3379 22:14:30.970455 [Byte1]: 56
3380 22:14:30.975042
3381 22:14:30.975620 Set Vref, RX VrefLevel [Byte0]: 57
3382 22:14:30.979083 [Byte1]: 57
3383 22:14:30.982786
3384 22:14:30.983353 Set Vref, RX VrefLevel [Byte0]: 58
3385 22:14:30.986045 [Byte1]: 58
3386 22:14:30.990971
3387 22:14:30.991545 Set Vref, RX VrefLevel [Byte0]: 59
3388 22:14:30.994038 [Byte1]: 59
3389 22:14:30.998798
3390 22:14:30.999389 Set Vref, RX VrefLevel [Byte0]: 60
3391 22:14:31.002173 [Byte1]: 60
3392 22:14:31.006584
3393 22:14:31.007160 Set Vref, RX VrefLevel [Byte0]: 61
3394 22:14:31.009542 [Byte1]: 61
3395 22:14:31.014403
3396 22:14:31.014977 Set Vref, RX VrefLevel [Byte0]: 62
3397 22:14:31.017825 [Byte1]: 62
3398 22:14:31.022298
3399 22:14:31.022869 Set Vref, RX VrefLevel [Byte0]: 63
3400 22:14:31.025751 [Byte1]: 63
3401 22:14:31.030807
3402 22:14:31.031378 Set Vref, RX VrefLevel [Byte0]: 64
3403 22:14:31.033277 [Byte1]: 64
3404 22:14:31.038128
3405 22:14:31.038701 Set Vref, RX VrefLevel [Byte0]: 65
3406 22:14:31.041508 [Byte1]: 65
3407 22:14:31.046202
3408 22:14:31.046798 Set Vref, RX VrefLevel [Byte0]: 66
3409 22:14:31.049314 [Byte1]: 66
3410 22:14:31.054001
3411 22:14:31.054594 Set Vref, RX VrefLevel [Byte0]: 67
3412 22:14:31.057031 [Byte1]: 67
3413 22:14:31.061557
3414 22:14:31.062030 Set Vref, RX VrefLevel [Byte0]: 68
3415 22:14:31.065075 [Byte1]: 68
3416 22:14:31.069395
3417 22:14:31.069868 Final RX Vref Byte 0 = 53 to rank0
3418 22:14:31.073030 Final RX Vref Byte 1 = 53 to rank0
3419 22:14:31.076490 Final RX Vref Byte 0 = 53 to rank1
3420 22:14:31.079581 Final RX Vref Byte 1 = 53 to rank1==
3421 22:14:31.082782 Dram Type= 6, Freq= 0, CH_1, rank 0
3422 22:14:31.090538 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3423 22:14:31.091133 ==
3424 22:14:31.091524 DQS Delay:
3425 22:14:31.091883 DQS0 = 0, DQS1 = 0
3426 22:14:31.092963 DQM Delay:
3427 22:14:31.093442 DQM0 = 119, DQM1 = 112
3428 22:14:31.096063 DQ Delay:
3429 22:14:31.099612 DQ0 =120, DQ1 =112, DQ2 =112, DQ3 =118
3430 22:14:31.102865 DQ4 =118, DQ5 =128, DQ6 =130, DQ7 =118
3431 22:14:31.106516 DQ8 =102, DQ9 =100, DQ10 =114, DQ11 =106
3432 22:14:31.109427 DQ12 =122, DQ13 =118, DQ14 =122, DQ15 =118
3433 22:14:31.110032
3434 22:14:31.110426
3435 22:14:31.119440 [DQSOSCAuto] RK0, (LSB)MR18= 0x215, (MSB)MR19= 0x404, tDQSOscB0 = 401 ps tDQSOscB1 = 409 ps
3436 22:14:31.120067 CH1 RK0: MR19=404, MR18=215
3437 22:14:31.126335 CH1_RK0: MR19=0x404, MR18=0x215, DQSOSC=401, MR23=63, INC=40, DEC=27
3438 22:14:31.126928
3439 22:14:31.129638 ----->DramcWriteLeveling(PI) begin...
3440 22:14:31.130222 ==
3441 22:14:31.132959 Dram Type= 6, Freq= 0, CH_1, rank 1
3442 22:14:31.136106 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3443 22:14:31.139528 ==
3444 22:14:31.140122 Write leveling (Byte 0): 24 => 24
3445 22:14:31.142944 Write leveling (Byte 1): 28 => 28
3446 22:14:31.146228 DramcWriteLeveling(PI) end<-----
3447 22:14:31.146809
3448 22:14:31.147194 ==
3449 22:14:31.149222 Dram Type= 6, Freq= 0, CH_1, rank 1
3450 22:14:31.155919 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3451 22:14:31.156512 ==
3452 22:14:31.159208 [Gating] SW mode calibration
3453 22:14:31.166147 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3454 22:14:31.169235 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3455 22:14:31.176073 0 15 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
3456 22:14:31.179133 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3457 22:14:31.182243 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3458 22:14:31.189319 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3459 22:14:31.192744 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3460 22:14:31.195559 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3461 22:14:31.202219 0 15 24 | B1->B0 | 2929 3434 | 0 1 | (0 0) (1 0)
3462 22:14:31.205650 0 15 28 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
3463 22:14:31.209123 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3464 22:14:31.212535 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3465 22:14:31.219143 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3466 22:14:31.222138 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3467 22:14:31.225395 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3468 22:14:31.231858 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3469 22:14:31.235921 1 0 24 | B1->B0 | 3f3f 2524 | 0 1 | (0 0) (0 0)
3470 22:14:31.238526 1 0 28 | B1->B0 | 4646 3f3f | 0 0 | (0 0) (0 0)
3471 22:14:31.245131 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3472 22:14:31.248596 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3473 22:14:31.251761 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3474 22:14:31.258225 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3475 22:14:31.261647 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3476 22:14:31.264905 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3477 22:14:31.271246 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3478 22:14:31.274801 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3479 22:14:31.278607 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3480 22:14:31.284882 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3481 22:14:31.288427 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3482 22:14:31.291088 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3483 22:14:31.297637 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3484 22:14:31.300922 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3485 22:14:31.304443 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3486 22:14:31.311496 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3487 22:14:31.314167 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3488 22:14:31.317596 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3489 22:14:31.324345 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3490 22:14:31.327415 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3491 22:14:31.330682 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3492 22:14:31.337218 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3493 22:14:31.340580 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3494 22:14:31.343970 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3495 22:14:31.347116 Total UI for P1: 0, mck2ui 16
3496 22:14:31.350724 best dqsien dly found for B0: ( 1, 3, 24)
3497 22:14:31.353847 Total UI for P1: 0, mck2ui 16
3498 22:14:31.356947 best dqsien dly found for B1: ( 1, 3, 24)
3499 22:14:31.360297 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3500 22:14:31.363686 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3501 22:14:31.363780
3502 22:14:31.370901 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3503 22:14:31.373764 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3504 22:14:31.376920 [Gating] SW calibration Done
3505 22:14:31.377004 ==
3506 22:14:31.380198 Dram Type= 6, Freq= 0, CH_1, rank 1
3507 22:14:31.383613 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3508 22:14:31.383698 ==
3509 22:14:31.383765 RX Vref Scan: 0
3510 22:14:31.386845
3511 22:14:31.386929 RX Vref 0 -> 0, step: 1
3512 22:14:31.386996
3513 22:14:31.390058 RX Delay -40 -> 252, step: 8
3514 22:14:31.393138 iDelay=200, Bit 0, Center 123 (64 ~ 183) 120
3515 22:14:31.396761 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3516 22:14:31.403164 iDelay=200, Bit 2, Center 111 (48 ~ 175) 128
3517 22:14:31.407075 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3518 22:14:31.409889 iDelay=200, Bit 4, Center 123 (56 ~ 191) 136
3519 22:14:31.413532 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3520 22:14:31.416530 iDelay=200, Bit 6, Center 123 (56 ~ 191) 136
3521 22:14:31.423148 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3522 22:14:31.426595 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3523 22:14:31.429501 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3524 22:14:31.433127 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3525 22:14:31.436257 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3526 22:14:31.442971 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3527 22:14:31.446052 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3528 22:14:31.449488 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3529 22:14:31.452686 iDelay=200, Bit 15, Center 123 (48 ~ 199) 152
3530 22:14:31.452775 ==
3531 22:14:31.456352 Dram Type= 6, Freq= 0, CH_1, rank 1
3532 22:14:31.462796 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3533 22:14:31.462890 ==
3534 22:14:31.462979 DQS Delay:
3535 22:14:31.465894 DQS0 = 0, DQS1 = 0
3536 22:14:31.465982 DQM Delay:
3537 22:14:31.469390 DQM0 = 120, DQM1 = 112
3538 22:14:31.469478 DQ Delay:
3539 22:14:31.472632 DQ0 =123, DQ1 =115, DQ2 =111, DQ3 =119
3540 22:14:31.475970 DQ4 =123, DQ5 =131, DQ6 =123, DQ7 =115
3541 22:14:31.479386 DQ8 =99, DQ9 =99, DQ10 =115, DQ11 =107
3542 22:14:31.483016 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =123
3543 22:14:31.483103
3544 22:14:31.483190
3545 22:14:31.483272 ==
3546 22:14:31.485766 Dram Type= 6, Freq= 0, CH_1, rank 1
3547 22:14:31.492681 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3548 22:14:31.492775 ==
3549 22:14:31.492861
3550 22:14:31.492943
3551 22:14:31.493022 TX Vref Scan disable
3552 22:14:31.495750 == TX Byte 0 ==
3553 22:14:31.499627 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3554 22:14:31.506340 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3555 22:14:31.506428 == TX Byte 1 ==
3556 22:14:31.509284 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3557 22:14:31.515803 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3558 22:14:31.515891 ==
3559 22:14:31.518979 Dram Type= 6, Freq= 0, CH_1, rank 1
3560 22:14:31.522362 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3561 22:14:31.522451 ==
3562 22:14:31.533831 TX Vref=22, minBit 1, minWin=25, winSum=416
3563 22:14:31.537219 TX Vref=24, minBit 1, minWin=25, winSum=422
3564 22:14:31.540722 TX Vref=26, minBit 1, minWin=26, winSum=425
3565 22:14:31.544119 TX Vref=28, minBit 1, minWin=26, winSum=429
3566 22:14:31.547191 TX Vref=30, minBit 1, minWin=26, winSum=425
3567 22:14:31.550672 TX Vref=32, minBit 0, minWin=26, winSum=425
3568 22:14:31.557245 [TxChooseVref] Worse bit 1, Min win 26, Win sum 429, Final Vref 28
3569 22:14:31.557335
3570 22:14:31.561013 Final TX Range 1 Vref 28
3571 22:14:31.561101
3572 22:14:31.561169 ==
3573 22:14:31.563646 Dram Type= 6, Freq= 0, CH_1, rank 1
3574 22:14:31.567087 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3575 22:14:31.567172 ==
3576 22:14:31.567240
3577 22:14:31.570489
3578 22:14:31.570574 TX Vref Scan disable
3579 22:14:31.573495 == TX Byte 0 ==
3580 22:14:31.576883 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3581 22:14:31.583746 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3582 22:14:31.583837 == TX Byte 1 ==
3583 22:14:31.586735 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3584 22:14:31.593252 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3585 22:14:31.593337
3586 22:14:31.593404 [DATLAT]
3587 22:14:31.593465 Freq=1200, CH1 RK1
3588 22:14:31.593525
3589 22:14:31.596784 DATLAT Default: 0xd
3590 22:14:31.596881 0, 0xFFFF, sum = 0
3591 22:14:31.599971 1, 0xFFFF, sum = 0
3592 22:14:31.603563 2, 0xFFFF, sum = 0
3593 22:14:31.603648 3, 0xFFFF, sum = 0
3594 22:14:31.606484 4, 0xFFFF, sum = 0
3595 22:14:31.606569 5, 0xFFFF, sum = 0
3596 22:14:31.609812 6, 0xFFFF, sum = 0
3597 22:14:31.609896 7, 0xFFFF, sum = 0
3598 22:14:31.612958 8, 0xFFFF, sum = 0
3599 22:14:31.613043 9, 0xFFFF, sum = 0
3600 22:14:31.616973 10, 0xFFFF, sum = 0
3601 22:14:31.617058 11, 0xFFFF, sum = 0
3602 22:14:31.619796 12, 0x0, sum = 1
3603 22:14:31.619881 13, 0x0, sum = 2
3604 22:14:31.623475 14, 0x0, sum = 3
3605 22:14:31.623581 15, 0x0, sum = 4
3606 22:14:31.626531 best_step = 13
3607 22:14:31.626614
3608 22:14:31.626680 ==
3609 22:14:31.629422 Dram Type= 6, Freq= 0, CH_1, rank 1
3610 22:14:31.632575 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3611 22:14:31.632661 ==
3612 22:14:31.636266 RX Vref Scan: 0
3613 22:14:31.636349
3614 22:14:31.636416 RX Vref 0 -> 0, step: 1
3615 22:14:31.636475
3616 22:14:31.639331 RX Delay -13 -> 252, step: 4
3617 22:14:31.646418 iDelay=195, Bit 0, Center 122 (63 ~ 182) 120
3618 22:14:31.649117 iDelay=195, Bit 1, Center 114 (55 ~ 174) 120
3619 22:14:31.652532 iDelay=195, Bit 2, Center 108 (51 ~ 166) 116
3620 22:14:31.655629 iDelay=195, Bit 3, Center 118 (59 ~ 178) 120
3621 22:14:31.658933 iDelay=195, Bit 4, Center 122 (63 ~ 182) 120
3622 22:14:31.665785 iDelay=195, Bit 5, Center 130 (67 ~ 194) 128
3623 22:14:31.669052 iDelay=195, Bit 6, Center 126 (67 ~ 186) 120
3624 22:14:31.672114 iDelay=195, Bit 7, Center 116 (55 ~ 178) 124
3625 22:14:31.675711 iDelay=195, Bit 8, Center 100 (39 ~ 162) 124
3626 22:14:31.678948 iDelay=195, Bit 9, Center 102 (39 ~ 166) 128
3627 22:14:31.685628 iDelay=195, Bit 10, Center 114 (51 ~ 178) 128
3628 22:14:31.688647 iDelay=195, Bit 11, Center 110 (47 ~ 174) 128
3629 22:14:31.692179 iDelay=195, Bit 12, Center 122 (59 ~ 186) 128
3630 22:14:31.695739 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3631 22:14:31.702063 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3632 22:14:31.705392 iDelay=195, Bit 15, Center 124 (59 ~ 190) 132
3633 22:14:31.705479 ==
3634 22:14:31.708668 Dram Type= 6, Freq= 0, CH_1, rank 1
3635 22:14:31.711858 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3636 22:14:31.711943 ==
3637 22:14:31.715184 DQS Delay:
3638 22:14:31.715268 DQS0 = 0, DQS1 = 0
3639 22:14:31.715335 DQM Delay:
3640 22:14:31.718322 DQM0 = 119, DQM1 = 114
3641 22:14:31.718406 DQ Delay:
3642 22:14:31.721675 DQ0 =122, DQ1 =114, DQ2 =108, DQ3 =118
3643 22:14:31.724938 DQ4 =122, DQ5 =130, DQ6 =126, DQ7 =116
3644 22:14:31.731555 DQ8 =100, DQ9 =102, DQ10 =114, DQ11 =110
3645 22:14:31.735139 DQ12 =122, DQ13 =118, DQ14 =122, DQ15 =124
3646 22:14:31.735223
3647 22:14:31.735289
3648 22:14:31.741988 [DQSOSCAuto] RK1, (LSB)MR18= 0x8ed, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 406 ps
3649 22:14:31.744639 CH1 RK1: MR19=403, MR18=8ED
3650 22:14:31.751430 CH1_RK1: MR19=0x403, MR18=0x8ED, DQSOSC=406, MR23=63, INC=39, DEC=26
3651 22:14:31.754706 [RxdqsGatingPostProcess] freq 1200
3652 22:14:31.758296 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3653 22:14:31.761235 best DQS0 dly(2T, 0.5T) = (0, 11)
3654 22:14:31.764727 best DQS1 dly(2T, 0.5T) = (0, 11)
3655 22:14:31.767598 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3656 22:14:31.770795 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3657 22:14:31.774475 best DQS0 dly(2T, 0.5T) = (0, 11)
3658 22:14:31.777671 best DQS1 dly(2T, 0.5T) = (0, 11)
3659 22:14:31.781029 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3660 22:14:31.783977 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3661 22:14:31.787388 Pre-setting of DQS Precalculation
3662 22:14:31.793920 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3663 22:14:31.800451 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3664 22:14:31.807227 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3665 22:14:31.807313
3666 22:14:31.807380
3667 22:14:31.810460 [Calibration Summary] 2400 Mbps
3668 22:14:31.810545 CH 0, Rank 0
3669 22:14:31.814150 SW Impedance : PASS
3670 22:14:31.817243 DUTY Scan : NO K
3671 22:14:31.817328 ZQ Calibration : PASS
3672 22:14:31.820490 Jitter Meter : NO K
3673 22:14:31.824415 CBT Training : PASS
3674 22:14:31.824499 Write leveling : PASS
3675 22:14:31.827020 RX DQS gating : PASS
3676 22:14:31.827105 RX DQ/DQS(RDDQC) : PASS
3677 22:14:31.830430 TX DQ/DQS : PASS
3678 22:14:31.833575 RX DATLAT : PASS
3679 22:14:31.833660 RX DQ/DQS(Engine): PASS
3680 22:14:31.837020 TX OE : NO K
3681 22:14:31.837105 All Pass.
3682 22:14:31.837173
3683 22:14:31.840331 CH 0, Rank 1
3684 22:14:31.840416 SW Impedance : PASS
3685 22:14:31.843469 DUTY Scan : NO K
3686 22:14:31.847215 ZQ Calibration : PASS
3687 22:14:31.847301 Jitter Meter : NO K
3688 22:14:31.850365 CBT Training : PASS
3689 22:14:31.853681 Write leveling : PASS
3690 22:14:31.853767 RX DQS gating : PASS
3691 22:14:31.857283 RX DQ/DQS(RDDQC) : PASS
3692 22:14:31.860131 TX DQ/DQS : PASS
3693 22:14:31.860230 RX DATLAT : PASS
3694 22:14:31.863290 RX DQ/DQS(Engine): PASS
3695 22:14:31.866636 TX OE : NO K
3696 22:14:31.866719 All Pass.
3697 22:14:31.866785
3698 22:14:31.866845 CH 1, Rank 0
3699 22:14:31.869958 SW Impedance : PASS
3700 22:14:31.873349 DUTY Scan : NO K
3701 22:14:31.873432 ZQ Calibration : PASS
3702 22:14:31.876723 Jitter Meter : NO K
3703 22:14:31.880075 CBT Training : PASS
3704 22:14:31.880158 Write leveling : PASS
3705 22:14:31.883653 RX DQS gating : PASS
3706 22:14:31.883736 RX DQ/DQS(RDDQC) : PASS
3707 22:14:31.887093 TX DQ/DQS : PASS
3708 22:14:31.890044 RX DATLAT : PASS
3709 22:14:31.890127 RX DQ/DQS(Engine): PASS
3710 22:14:31.893457 TX OE : NO K
3711 22:14:31.893540 All Pass.
3712 22:14:31.893606
3713 22:14:31.896976 CH 1, Rank 1
3714 22:14:31.897059 SW Impedance : PASS
3715 22:14:31.899799 DUTY Scan : NO K
3716 22:14:31.903352 ZQ Calibration : PASS
3717 22:14:31.903435 Jitter Meter : NO K
3718 22:14:31.906651 CBT Training : PASS
3719 22:14:31.909583 Write leveling : PASS
3720 22:14:31.909666 RX DQS gating : PASS
3721 22:14:31.912987 RX DQ/DQS(RDDQC) : PASS
3722 22:14:31.916317 TX DQ/DQS : PASS
3723 22:14:31.916400 RX DATLAT : PASS
3724 22:14:31.919594 RX DQ/DQS(Engine): PASS
3725 22:14:31.923033 TX OE : NO K
3726 22:14:31.923117 All Pass.
3727 22:14:31.923183
3728 22:14:31.926216 DramC Write-DBI off
3729 22:14:31.926299 PER_BANK_REFRESH: Hybrid Mode
3730 22:14:31.929861 TX_TRACKING: ON
3731 22:14:31.936242 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3732 22:14:31.943050 [FAST_K] Save calibration result to emmc
3733 22:14:31.945997 dramc_set_vcore_voltage set vcore to 650000
3734 22:14:31.946094 Read voltage for 600, 5
3735 22:14:31.949268 Vio18 = 0
3736 22:14:31.949351 Vcore = 650000
3737 22:14:31.949417 Vdram = 0
3738 22:14:31.953086 Vddq = 0
3739 22:14:31.953168 Vmddr = 0
3740 22:14:31.956347 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3741 22:14:31.962853 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3742 22:14:31.966342 MEM_TYPE=3, freq_sel=19
3743 22:14:31.969530 sv_algorithm_assistance_LP4_1600
3744 22:14:31.972683 ============ PULL DRAM RESETB DOWN ============
3745 22:14:31.975892 ========== PULL DRAM RESETB DOWN end =========
3746 22:14:31.982367 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3747 22:14:31.985688 ===================================
3748 22:14:31.985773 LPDDR4 DRAM CONFIGURATION
3749 22:14:31.989115 ===================================
3750 22:14:31.992271 EX_ROW_EN[0] = 0x0
3751 22:14:31.992354 EX_ROW_EN[1] = 0x0
3752 22:14:31.995808 LP4Y_EN = 0x0
3753 22:14:31.995892 WORK_FSP = 0x0
3754 22:14:31.999186 WL = 0x2
3755 22:14:32.002393 RL = 0x2
3756 22:14:32.002476 BL = 0x2
3757 22:14:32.005483 RPST = 0x0
3758 22:14:32.005566 RD_PRE = 0x0
3759 22:14:32.008968 WR_PRE = 0x1
3760 22:14:32.009051 WR_PST = 0x0
3761 22:14:32.012421 DBI_WR = 0x0
3762 22:14:32.012504 DBI_RD = 0x0
3763 22:14:32.015754 OTF = 0x1
3764 22:14:32.019141 ===================================
3765 22:14:32.022255 ===================================
3766 22:14:32.022339 ANA top config
3767 22:14:32.025585 ===================================
3768 22:14:32.028691 DLL_ASYNC_EN = 0
3769 22:14:32.031985 ALL_SLAVE_EN = 1
3770 22:14:32.032068 NEW_RANK_MODE = 1
3771 22:14:32.035234 DLL_IDLE_MODE = 1
3772 22:14:32.038736 LP45_APHY_COMB_EN = 1
3773 22:14:32.042112 TX_ODT_DIS = 1
3774 22:14:32.045221 NEW_8X_MODE = 1
3775 22:14:32.048774 ===================================
3776 22:14:32.051768 ===================================
3777 22:14:32.051852 data_rate = 1200
3778 22:14:32.055186 CKR = 1
3779 22:14:32.058466 DQ_P2S_RATIO = 8
3780 22:14:32.062027 ===================================
3781 22:14:32.065110 CA_P2S_RATIO = 8
3782 22:14:32.068669 DQ_CA_OPEN = 0
3783 22:14:32.071430 DQ_SEMI_OPEN = 0
3784 22:14:32.071517 CA_SEMI_OPEN = 0
3785 22:14:32.074762 CA_FULL_RATE = 0
3786 22:14:32.078246 DQ_CKDIV4_EN = 1
3787 22:14:32.081630 CA_CKDIV4_EN = 1
3788 22:14:32.084659 CA_PREDIV_EN = 0
3789 22:14:32.088049 PH8_DLY = 0
3790 22:14:32.091569 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3791 22:14:32.091653 DQ_AAMCK_DIV = 4
3792 22:14:32.094506 CA_AAMCK_DIV = 4
3793 22:14:32.097763 CA_ADMCK_DIV = 4
3794 22:14:32.101197 DQ_TRACK_CA_EN = 0
3795 22:14:32.104448 CA_PICK = 600
3796 22:14:32.107685 CA_MCKIO = 600
3797 22:14:32.107769 MCKIO_SEMI = 0
3798 22:14:32.110961 PLL_FREQ = 2288
3799 22:14:32.114207 DQ_UI_PI_RATIO = 32
3800 22:14:32.117718 CA_UI_PI_RATIO = 0
3801 22:14:32.121263 ===================================
3802 22:14:32.124402 ===================================
3803 22:14:32.127535 memory_type:LPDDR4
3804 22:14:32.127618 GP_NUM : 10
3805 22:14:32.130764 SRAM_EN : 1
3806 22:14:32.133911 MD32_EN : 0
3807 22:14:32.137442 ===================================
3808 22:14:32.137525 [ANA_INIT] >>>>>>>>>>>>>>
3809 22:14:32.140631 <<<<<< [CONFIGURE PHASE]: ANA_TX
3810 22:14:32.143951 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3811 22:14:32.147293 ===================================
3812 22:14:32.150424 data_rate = 1200,PCW = 0X5800
3813 22:14:32.153834 ===================================
3814 22:14:32.156886 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3815 22:14:32.163509 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3816 22:14:32.170671 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3817 22:14:32.173674 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3818 22:14:32.177102 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3819 22:14:32.180365 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3820 22:14:32.183626 [ANA_INIT] flow start
3821 22:14:32.183709 [ANA_INIT] PLL >>>>>>>>
3822 22:14:32.186927 [ANA_INIT] PLL <<<<<<<<
3823 22:14:32.190114 [ANA_INIT] MIDPI >>>>>>>>
3824 22:14:32.190198 [ANA_INIT] MIDPI <<<<<<<<
3825 22:14:32.193535 [ANA_INIT] DLL >>>>>>>>
3826 22:14:32.196697 [ANA_INIT] flow end
3827 22:14:32.199815 ============ LP4 DIFF to SE enter ============
3828 22:14:32.203580 ============ LP4 DIFF to SE exit ============
3829 22:14:32.206691 [ANA_INIT] <<<<<<<<<<<<<
3830 22:14:32.210265 [Flow] Enable top DCM control >>>>>
3831 22:14:32.213666 [Flow] Enable top DCM control <<<<<
3832 22:14:32.217048 Enable DLL master slave shuffle
3833 22:14:32.219915 ==============================================================
3834 22:14:32.223115 Gating Mode config
3835 22:14:32.230156 ==============================================================
3836 22:14:32.230240 Config description:
3837 22:14:32.239712 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3838 22:14:32.246621 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3839 22:14:32.253423 SELPH_MODE 0: By rank 1: By Phase
3840 22:14:32.256526 ==============================================================
3841 22:14:32.259958 GAT_TRACK_EN = 1
3842 22:14:32.262957 RX_GATING_MODE = 2
3843 22:14:32.266319 RX_GATING_TRACK_MODE = 2
3844 22:14:32.269553 SELPH_MODE = 1
3845 22:14:32.272760 PICG_EARLY_EN = 1
3846 22:14:32.276396 VALID_LAT_VALUE = 1
3847 22:14:32.279594 ==============================================================
3848 22:14:32.283047 Enter into Gating configuration >>>>
3849 22:14:32.286153 Exit from Gating configuration <<<<
3850 22:14:32.289445 Enter into DVFS_PRE_config >>>>>
3851 22:14:32.302703 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3852 22:14:32.306090 Exit from DVFS_PRE_config <<<<<
3853 22:14:32.309070 Enter into PICG configuration >>>>
3854 22:14:32.312746 Exit from PICG configuration <<<<
3855 22:14:32.312838 [RX_INPUT] configuration >>>>>
3856 22:14:32.315784 [RX_INPUT] configuration <<<<<
3857 22:14:32.322667 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3858 22:14:32.325847 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3859 22:14:32.332301 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3860 22:14:32.339538 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3861 22:14:32.345895 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3862 22:14:32.352218 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3863 22:14:32.355485 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3864 22:14:32.358556 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3865 22:14:32.365078 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3866 22:14:32.368349 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3867 22:14:32.371575 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3868 22:14:32.378379 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3869 22:14:32.381816 ===================================
3870 22:14:32.381903 LPDDR4 DRAM CONFIGURATION
3871 22:14:32.385139 ===================================
3872 22:14:32.388135 EX_ROW_EN[0] = 0x0
3873 22:14:32.388221 EX_ROW_EN[1] = 0x0
3874 22:14:32.391638 LP4Y_EN = 0x0
3875 22:14:32.391723 WORK_FSP = 0x0
3876 22:14:32.394765 WL = 0x2
3877 22:14:32.397912 RL = 0x2
3878 22:14:32.397996 BL = 0x2
3879 22:14:32.401612 RPST = 0x0
3880 22:14:32.401697 RD_PRE = 0x0
3881 22:14:32.404619 WR_PRE = 0x1
3882 22:14:32.404704 WR_PST = 0x0
3883 22:14:32.408049 DBI_WR = 0x0
3884 22:14:32.408134 DBI_RD = 0x0
3885 22:14:32.411133 OTF = 0x1
3886 22:14:32.414979 ===================================
3887 22:14:32.417863 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3888 22:14:32.421099 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3889 22:14:32.427725 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3890 22:14:32.430844 ===================================
3891 22:14:32.430930 LPDDR4 DRAM CONFIGURATION
3892 22:14:32.434206 ===================================
3893 22:14:32.437543 EX_ROW_EN[0] = 0x10
3894 22:14:32.441879 EX_ROW_EN[1] = 0x0
3895 22:14:32.441964 LP4Y_EN = 0x0
3896 22:14:32.444498 WORK_FSP = 0x0
3897 22:14:32.444582 WL = 0x2
3898 22:14:32.447636 RL = 0x2
3899 22:14:32.447721 BL = 0x2
3900 22:14:32.450637 RPST = 0x0
3901 22:14:32.450722 RD_PRE = 0x0
3902 22:14:32.453989 WR_PRE = 0x1
3903 22:14:32.454074 WR_PST = 0x0
3904 22:14:32.457252 DBI_WR = 0x0
3905 22:14:32.457337 DBI_RD = 0x0
3906 22:14:32.460601 OTF = 0x1
3907 22:14:32.463864 ===================================
3908 22:14:32.470554 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3909 22:14:32.473861 nWR fixed to 30
3910 22:14:32.473947 [ModeRegInit_LP4] CH0 RK0
3911 22:14:32.477096 [ModeRegInit_LP4] CH0 RK1
3912 22:14:32.480348 [ModeRegInit_LP4] CH1 RK0
3913 22:14:32.483744 [ModeRegInit_LP4] CH1 RK1
3914 22:14:32.483830 match AC timing 17
3915 22:14:32.490278 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3916 22:14:32.494020 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3917 22:14:32.497283 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3918 22:14:32.503665 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3919 22:14:32.506794 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3920 22:14:32.506880 ==
3921 22:14:32.510216 Dram Type= 6, Freq= 0, CH_0, rank 0
3922 22:14:32.513771 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3923 22:14:32.513861 ==
3924 22:14:32.520147 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3925 22:14:32.526571 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3926 22:14:32.530445 [CA 0] Center 36 (5~67) winsize 63
3927 22:14:32.533318 [CA 1] Center 36 (6~67) winsize 62
3928 22:14:32.537131 [CA 2] Center 34 (4~65) winsize 62
3929 22:14:32.540011 [CA 3] Center 34 (3~65) winsize 63
3930 22:14:32.543299 [CA 4] Center 34 (3~65) winsize 63
3931 22:14:32.546730 [CA 5] Center 33 (2~64) winsize 63
3932 22:14:32.546815
3933 22:14:32.550219 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3934 22:14:32.550304
3935 22:14:32.552967 [CATrainingPosCal] consider 1 rank data
3936 22:14:32.556795 u2DelayCellTimex100 = 270/100 ps
3937 22:14:32.559924 CA0 delay=36 (5~67),Diff = 3 PI (28 cell)
3938 22:14:32.563271 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3939 22:14:32.566742 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3940 22:14:32.569930 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
3941 22:14:32.573423 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
3942 22:14:32.576465 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
3943 22:14:32.576550
3944 22:14:32.583336 CA PerBit enable=1, Macro0, CA PI delay=33
3945 22:14:32.583421
3946 22:14:32.586378 [CBTSetCACLKResult] CA Dly = 33
3947 22:14:32.586463 CS Dly: 5 (0~36)
3948 22:14:32.586531 ==
3949 22:14:32.589778 Dram Type= 6, Freq= 0, CH_0, rank 1
3950 22:14:32.592951 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3951 22:14:32.593038 ==
3952 22:14:32.599570 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3953 22:14:32.606362 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3954 22:14:32.609941 [CA 0] Center 36 (6~67) winsize 62
3955 22:14:32.612914 [CA 1] Center 36 (6~67) winsize 62
3956 22:14:32.616095 [CA 2] Center 34 (4~65) winsize 62
3957 22:14:32.619274 [CA 3] Center 34 (4~65) winsize 62
3958 22:14:32.622796 [CA 4] Center 34 (3~65) winsize 63
3959 22:14:32.626503 [CA 5] Center 33 (3~64) winsize 62
3960 22:14:32.626588
3961 22:14:32.629423 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3962 22:14:32.629508
3963 22:14:32.632548 [CATrainingPosCal] consider 2 rank data
3964 22:14:32.636242 u2DelayCellTimex100 = 270/100 ps
3965 22:14:32.639619 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3966 22:14:32.642650 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3967 22:14:32.646038 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3968 22:14:32.649202 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3969 22:14:32.655943 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
3970 22:14:32.659494 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3971 22:14:32.659579
3972 22:14:32.662385 CA PerBit enable=1, Macro0, CA PI delay=33
3973 22:14:32.662470
3974 22:14:32.666196 [CBTSetCACLKResult] CA Dly = 33
3975 22:14:32.666281 CS Dly: 5 (0~37)
3976 22:14:32.666348
3977 22:14:32.669021 ----->DramcWriteLeveling(PI) begin...
3978 22:14:32.669108 ==
3979 22:14:32.672619 Dram Type= 6, Freq= 0, CH_0, rank 0
3980 22:14:32.679240 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3981 22:14:32.679327 ==
3982 22:14:32.682219 Write leveling (Byte 0): 33 => 33
3983 22:14:32.685554 Write leveling (Byte 1): 32 => 32
3984 22:14:32.685640 DramcWriteLeveling(PI) end<-----
3985 22:14:32.685707
3986 22:14:32.689178 ==
3987 22:14:32.692226 Dram Type= 6, Freq= 0, CH_0, rank 0
3988 22:14:32.695906 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3989 22:14:32.695993 ==
3990 22:14:32.699053 [Gating] SW mode calibration
3991 22:14:32.705875 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3992 22:14:32.708685 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3993 22:14:32.715108 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3994 22:14:32.718419 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3995 22:14:32.721853 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3996 22:14:32.728749 0 9 12 | B1->B0 | 3434 2c2c | 0 0 | (0 1) (0 0)
3997 22:14:32.732035 0 9 16 | B1->B0 | 2525 2323 | 1 0 | (1 0) (0 0)
3998 22:14:32.735297 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3999 22:14:32.741999 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4000 22:14:32.744974 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4001 22:14:32.748659 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4002 22:14:32.755051 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4003 22:14:32.758036 0 10 8 | B1->B0 | 2323 2423 | 0 1 | (0 0) (1 1)
4004 22:14:32.761208 0 10 12 | B1->B0 | 2c2c 3d3d | 0 0 | (0 0) (0 0)
4005 22:14:32.768030 0 10 16 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
4006 22:14:32.771220 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4007 22:14:32.774728 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4008 22:14:32.781487 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4009 22:14:32.784799 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4010 22:14:32.787951 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4011 22:14:32.794343 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4012 22:14:32.797765 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4013 22:14:32.800793 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4014 22:14:32.807633 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4015 22:14:32.810778 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4016 22:14:32.814711 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4017 22:14:32.820543 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4018 22:14:32.824225 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4019 22:14:32.827639 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4020 22:14:32.834112 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4021 22:14:32.837149 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4022 22:14:32.840360 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4023 22:14:32.847048 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4024 22:14:32.850063 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4025 22:14:32.853545 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4026 22:14:32.860034 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4027 22:14:32.863567 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4028 22:14:32.869718 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4029 22:14:32.873584 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4030 22:14:32.876656 Total UI for P1: 0, mck2ui 16
4031 22:14:32.879860 best dqsien dly found for B0: ( 0, 13, 12)
4032 22:14:32.883305 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4033 22:14:32.886780 Total UI for P1: 0, mck2ui 16
4034 22:14:32.889864 best dqsien dly found for B1: ( 0, 13, 14)
4035 22:14:32.893174 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4036 22:14:32.896109 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4037 22:14:32.896184
4038 22:14:32.899368 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4039 22:14:32.906212 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4040 22:14:32.906294 [Gating] SW calibration Done
4041 22:14:32.906359 ==
4042 22:14:32.909431 Dram Type= 6, Freq= 0, CH_0, rank 0
4043 22:14:32.916153 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4044 22:14:32.916239 ==
4045 22:14:32.916306 RX Vref Scan: 0
4046 22:14:32.916368
4047 22:14:32.919654 RX Vref 0 -> 0, step: 1
4048 22:14:32.919739
4049 22:14:32.922783 RX Delay -230 -> 252, step: 16
4050 22:14:32.925989 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4051 22:14:32.929387 iDelay=218, Bit 1, Center 49 (-118 ~ 217) 336
4052 22:14:32.935965 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4053 22:14:32.939283 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4054 22:14:32.942830 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4055 22:14:32.946520 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4056 22:14:32.949256 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4057 22:14:32.955954 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4058 22:14:32.959206 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4059 22:14:32.962862 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4060 22:14:32.965893 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4061 22:14:32.972540 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4062 22:14:32.975731 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4063 22:14:32.979101 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4064 22:14:32.982535 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4065 22:14:32.989177 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4066 22:14:32.989262 ==
4067 22:14:32.992225 Dram Type= 6, Freq= 0, CH_0, rank 0
4068 22:14:32.995864 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4069 22:14:32.995950 ==
4070 22:14:32.996017 DQS Delay:
4071 22:14:32.998781 DQS0 = 0, DQS1 = 0
4072 22:14:32.998865 DQM Delay:
4073 22:14:33.002326 DQM0 = 50, DQM1 = 39
4074 22:14:33.002410 DQ Delay:
4075 22:14:33.005350 DQ0 =49, DQ1 =49, DQ2 =49, DQ3 =41
4076 22:14:33.008672 DQ4 =57, DQ5 =41, DQ6 =57, DQ7 =57
4077 22:14:33.011951 DQ8 =33, DQ9 =33, DQ10 =41, DQ11 =33
4078 22:14:33.015289 DQ12 =41, DQ13 =41, DQ14 =49, DQ15 =41
4079 22:14:33.015374
4080 22:14:33.015441
4081 22:14:33.015502 ==
4082 22:14:33.018949 Dram Type= 6, Freq= 0, CH_0, rank 0
4083 22:14:33.022019 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4084 22:14:33.022105 ==
4085 22:14:33.025199
4086 22:14:33.025283
4087 22:14:33.025350 TX Vref Scan disable
4088 22:14:33.028324 == TX Byte 0 ==
4089 22:14:33.031610 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4090 22:14:33.034807 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4091 22:14:33.038331 == TX Byte 1 ==
4092 22:14:33.041658 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4093 22:14:33.045151 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4094 22:14:33.048366 ==
4095 22:14:33.052004 Dram Type= 6, Freq= 0, CH_0, rank 0
4096 22:14:33.055190 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4097 22:14:33.055276 ==
4098 22:14:33.055344
4099 22:14:33.055406
4100 22:14:33.058188 TX Vref Scan disable
4101 22:14:33.058273 == TX Byte 0 ==
4102 22:14:33.064681 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4103 22:14:33.067928 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4104 22:14:33.071458 == TX Byte 1 ==
4105 22:14:33.074811 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4106 22:14:33.077899 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4107 22:14:33.077984
4108 22:14:33.078052 [DATLAT]
4109 22:14:33.081370 Freq=600, CH0 RK0
4110 22:14:33.081474
4111 22:14:33.081542 DATLAT Default: 0x9
4112 22:14:33.084780 0, 0xFFFF, sum = 0
4113 22:14:33.088486 1, 0xFFFF, sum = 0
4114 22:14:33.088574 2, 0xFFFF, sum = 0
4115 22:14:33.091445 3, 0xFFFF, sum = 0
4116 22:14:33.091537 4, 0xFFFF, sum = 0
4117 22:14:33.094480 5, 0xFFFF, sum = 0
4118 22:14:33.094595 6, 0xFFFF, sum = 0
4119 22:14:33.097996 7, 0xFFFF, sum = 0
4120 22:14:33.098082 8, 0x0, sum = 1
4121 22:14:33.101191 9, 0x0, sum = 2
4122 22:14:33.101305 10, 0x0, sum = 3
4123 22:14:33.101403 11, 0x0, sum = 4
4124 22:14:33.104722 best_step = 9
4125 22:14:33.104824
4126 22:14:33.104892 ==
4127 22:14:33.108070 Dram Type= 6, Freq= 0, CH_0, rank 0
4128 22:14:33.111099 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4129 22:14:33.111185 ==
4130 22:14:33.114692 RX Vref Scan: 1
4131 22:14:33.114777
4132 22:14:33.114847 RX Vref 0 -> 0, step: 1
4133 22:14:33.114950
4134 22:14:33.117829 RX Delay -163 -> 252, step: 8
4135 22:14:33.117913
4136 22:14:33.121564 Set Vref, RX VrefLevel [Byte0]: 58
4137 22:14:33.124264 [Byte1]: 49
4138 22:14:33.128798
4139 22:14:33.128895 Final RX Vref Byte 0 = 58 to rank0
4140 22:14:33.132195 Final RX Vref Byte 1 = 49 to rank0
4141 22:14:33.135350 Final RX Vref Byte 0 = 58 to rank1
4142 22:14:33.138541 Final RX Vref Byte 1 = 49 to rank1==
4143 22:14:33.141714 Dram Type= 6, Freq= 0, CH_0, rank 0
4144 22:14:33.148549 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4145 22:14:33.148636 ==
4146 22:14:33.148704 DQS Delay:
4147 22:14:33.148774 DQS0 = 0, DQS1 = 0
4148 22:14:33.151682 DQM Delay:
4149 22:14:33.151767 DQM0 = 50, DQM1 = 37
4150 22:14:33.154931 DQ Delay:
4151 22:14:33.158363 DQ0 =48, DQ1 =52, DQ2 =48, DQ3 =44
4152 22:14:33.161788 DQ4 =52, DQ5 =40, DQ6 =60, DQ7 =56
4153 22:14:33.165228 DQ8 =32, DQ9 =24, DQ10 =36, DQ11 =32
4154 22:14:33.168301 DQ12 =40, DQ13 =40, DQ14 =48, DQ15 =48
4155 22:14:33.168386
4156 22:14:33.168453
4157 22:14:33.175173 [DQSOSCAuto] RK0, (LSB)MR18= 0x5852, (MSB)MR19= 0x808, tDQSOscB0 = 394 ps tDQSOscB1 = 393 ps
4158 22:14:33.177949 CH0 RK0: MR19=808, MR18=5852
4159 22:14:33.184654 CH0_RK0: MR19=0x808, MR18=0x5852, DQSOSC=393, MR23=63, INC=169, DEC=113
4160 22:14:33.184771
4161 22:14:33.187953 ----->DramcWriteLeveling(PI) begin...
4162 22:14:33.188039 ==
4163 22:14:33.191171 Dram Type= 6, Freq= 0, CH_0, rank 1
4164 22:14:33.194610 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4165 22:14:33.194695 ==
4166 22:14:33.197741 Write leveling (Byte 0): 33 => 33
4167 22:14:33.201237 Write leveling (Byte 1): 32 => 32
4168 22:14:33.205282 DramcWriteLeveling(PI) end<-----
4169 22:14:33.205366
4170 22:14:33.205433 ==
4171 22:14:33.207806 Dram Type= 6, Freq= 0, CH_0, rank 1
4172 22:14:33.211200 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4173 22:14:33.214680 ==
4174 22:14:33.214791 [Gating] SW mode calibration
4175 22:14:33.224552 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4176 22:14:33.227420 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4177 22:14:33.230796 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4178 22:14:33.237652 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4179 22:14:33.240802 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4180 22:14:33.244285 0 9 12 | B1->B0 | 3333 3232 | 1 1 | (1 0) (1 0)
4181 22:14:33.250617 0 9 16 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
4182 22:14:33.253999 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4183 22:14:33.257376 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4184 22:14:33.263942 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4185 22:14:33.267180 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4186 22:14:33.270733 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4187 22:14:33.277271 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4188 22:14:33.281379 0 10 12 | B1->B0 | 3030 3232 | 0 0 | (0 0) (1 1)
4189 22:14:33.283868 0 10 16 | B1->B0 | 4040 4545 | 1 1 | (0 0) (0 0)
4190 22:14:33.290773 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4191 22:14:33.294273 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4192 22:14:33.297096 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4193 22:14:33.303717 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4194 22:14:33.307154 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4195 22:14:33.310568 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4196 22:14:33.316936 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4197 22:14:33.320465 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4198 22:14:33.323433 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4199 22:14:33.330194 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4200 22:14:33.333377 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4201 22:14:33.336661 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4202 22:14:33.343360 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4203 22:14:33.346632 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4204 22:14:33.350131 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4205 22:14:33.356507 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4206 22:14:33.360279 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4207 22:14:33.363256 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4208 22:14:33.370321 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4209 22:14:33.373390 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4210 22:14:33.377011 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4211 22:14:33.382945 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4212 22:14:33.386324 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4213 22:14:33.389376 Total UI for P1: 0, mck2ui 16
4214 22:14:33.392717 best dqsien dly found for B1: ( 0, 13, 10)
4215 22:14:33.396053 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4216 22:14:33.399197 Total UI for P1: 0, mck2ui 16
4217 22:14:33.402890 best dqsien dly found for B0: ( 0, 13, 12)
4218 22:14:33.405869 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4219 22:14:33.409542 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4220 22:14:33.409627
4221 22:14:33.415880 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4222 22:14:33.419256 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4223 22:14:33.422417 [Gating] SW calibration Done
4224 22:14:33.422502 ==
4225 22:14:33.425559 Dram Type= 6, Freq= 0, CH_0, rank 1
4226 22:14:33.428753 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4227 22:14:33.428876 ==
4228 22:14:33.428944 RX Vref Scan: 0
4229 22:14:33.429007
4230 22:14:33.432598 RX Vref 0 -> 0, step: 1
4231 22:14:33.432683
4232 22:14:33.435527 RX Delay -230 -> 252, step: 16
4233 22:14:33.438939 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4234 22:14:33.445490 iDelay=218, Bit 1, Center 57 (-86 ~ 201) 288
4235 22:14:33.448695 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4236 22:14:33.451900 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4237 22:14:33.455582 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4238 22:14:33.458362 iDelay=218, Bit 5, Center 49 (-102 ~ 201) 304
4239 22:14:33.464713 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4240 22:14:33.468227 iDelay=218, Bit 7, Center 65 (-86 ~ 217) 304
4241 22:14:33.471574 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4242 22:14:33.474834 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4243 22:14:33.481394 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4244 22:14:33.484657 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4245 22:14:33.487907 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4246 22:14:33.491201 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4247 22:14:33.498229 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4248 22:14:33.501368 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4249 22:14:33.501453 ==
4250 22:14:33.504646 Dram Type= 6, Freq= 0, CH_0, rank 1
4251 22:14:33.507555 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4252 22:14:33.507640 ==
4253 22:14:33.511362 DQS Delay:
4254 22:14:33.511449 DQS0 = 0, DQS1 = 0
4255 22:14:33.511517 DQM Delay:
4256 22:14:33.514424 DQM0 = 54, DQM1 = 42
4257 22:14:33.514510 DQ Delay:
4258 22:14:33.517898 DQ0 =49, DQ1 =57, DQ2 =49, DQ3 =49
4259 22:14:33.521491 DQ4 =49, DQ5 =49, DQ6 =65, DQ7 =65
4260 22:14:33.524475 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =41
4261 22:14:33.527502 DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =49
4262 22:14:33.527588
4263 22:14:33.527656
4264 22:14:33.527717 ==
4265 22:14:33.531162 Dram Type= 6, Freq= 0, CH_0, rank 1
4266 22:14:33.537370 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4267 22:14:33.537458 ==
4268 22:14:33.537526
4269 22:14:33.537590
4270 22:14:33.537651 TX Vref Scan disable
4271 22:14:33.541112 == TX Byte 0 ==
4272 22:14:33.544539 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4273 22:14:33.551038 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4274 22:14:33.551123 == TX Byte 1 ==
4275 22:14:33.554236 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4276 22:14:33.560950 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4277 22:14:33.561057 ==
4278 22:14:33.564100 Dram Type= 6, Freq= 0, CH_0, rank 1
4279 22:14:33.567785 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4280 22:14:33.567870 ==
4281 22:14:33.567938
4282 22:14:33.568000
4283 22:14:33.570700 TX Vref Scan disable
4284 22:14:33.574480 == TX Byte 0 ==
4285 22:14:33.577220 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4286 22:14:33.580882 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4287 22:14:33.584142 == TX Byte 1 ==
4288 22:14:33.587371 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4289 22:14:33.590421 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4290 22:14:33.590505
4291 22:14:33.593757 [DATLAT]
4292 22:14:33.593841 Freq=600, CH0 RK1
4293 22:14:33.593909
4294 22:14:33.597497 DATLAT Default: 0x9
4295 22:14:33.597581 0, 0xFFFF, sum = 0
4296 22:14:33.600388 1, 0xFFFF, sum = 0
4297 22:14:33.600472 2, 0xFFFF, sum = 0
4298 22:14:33.604112 3, 0xFFFF, sum = 0
4299 22:14:33.604197 4, 0xFFFF, sum = 0
4300 22:14:33.607245 5, 0xFFFF, sum = 0
4301 22:14:33.607330 6, 0xFFFF, sum = 0
4302 22:14:33.610532 7, 0xFFFF, sum = 0
4303 22:14:33.610616 8, 0x0, sum = 1
4304 22:14:33.613762 9, 0x0, sum = 2
4305 22:14:33.613847 10, 0x0, sum = 3
4306 22:14:33.616979 11, 0x0, sum = 4
4307 22:14:33.617071 best_step = 9
4308 22:14:33.617138
4309 22:14:33.617198 ==
4310 22:14:33.620236 Dram Type= 6, Freq= 0, CH_0, rank 1
4311 22:14:33.623551 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4312 22:14:33.627030 ==
4313 22:14:33.627121 RX Vref Scan: 0
4314 22:14:33.627216
4315 22:14:33.630546 RX Vref 0 -> 0, step: 1
4316 22:14:33.630651
4317 22:14:33.633263 RX Delay -179 -> 252, step: 8
4318 22:14:33.636654 iDelay=205, Bit 0, Center 44 (-107 ~ 196) 304
4319 22:14:33.639834 iDelay=205, Bit 1, Center 48 (-99 ~ 196) 296
4320 22:14:33.646612 iDelay=205, Bit 2, Center 44 (-99 ~ 188) 288
4321 22:14:33.649732 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4322 22:14:33.653014 iDelay=205, Bit 4, Center 48 (-99 ~ 196) 296
4323 22:14:33.656522 iDelay=205, Bit 5, Center 40 (-107 ~ 188) 296
4324 22:14:33.659809 iDelay=205, Bit 6, Center 56 (-91 ~ 204) 296
4325 22:14:33.666323 iDelay=205, Bit 7, Center 56 (-91 ~ 204) 296
4326 22:14:33.669775 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4327 22:14:33.673104 iDelay=205, Bit 9, Center 28 (-115 ~ 172) 288
4328 22:14:33.676741 iDelay=205, Bit 10, Center 40 (-107 ~ 188) 296
4329 22:14:33.683219 iDelay=205, Bit 11, Center 32 (-115 ~ 180) 296
4330 22:14:33.686235 iDelay=205, Bit 12, Center 48 (-99 ~ 196) 296
4331 22:14:33.689423 iDelay=205, Bit 13, Center 44 (-99 ~ 188) 288
4332 22:14:33.692644 iDelay=205, Bit 14, Center 52 (-91 ~ 196) 288
4333 22:14:33.699353 iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288
4334 22:14:33.699436 ==
4335 22:14:33.702859 Dram Type= 6, Freq= 0, CH_0, rank 1
4336 22:14:33.706141 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4337 22:14:33.706224 ==
4338 22:14:33.706290 DQS Delay:
4339 22:14:33.709236 DQS0 = 0, DQS1 = 0
4340 22:14:33.709318 DQM Delay:
4341 22:14:33.712411 DQM0 = 47, DQM1 = 41
4342 22:14:33.712493 DQ Delay:
4343 22:14:33.716424 DQ0 =44, DQ1 =48, DQ2 =44, DQ3 =44
4344 22:14:33.719817 DQ4 =48, DQ5 =40, DQ6 =56, DQ7 =56
4345 22:14:33.722576 DQ8 =32, DQ9 =28, DQ10 =40, DQ11 =32
4346 22:14:33.725562 DQ12 =48, DQ13 =44, DQ14 =52, DQ15 =52
4347 22:14:33.725645
4348 22:14:33.725710
4349 22:14:33.736055 [DQSOSCAuto] RK1, (LSB)MR18= 0x6231, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 391 ps
4350 22:14:33.736139 CH0 RK1: MR19=808, MR18=6231
4351 22:14:33.741979 CH0_RK1: MR19=0x808, MR18=0x6231, DQSOSC=391, MR23=63, INC=171, DEC=114
4352 22:14:33.745644 [RxdqsGatingPostProcess] freq 600
4353 22:14:33.752081 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4354 22:14:33.755526 Pre-setting of DQS Precalculation
4355 22:14:33.758569 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4356 22:14:33.758659 ==
4357 22:14:33.761792 Dram Type= 6, Freq= 0, CH_1, rank 0
4358 22:14:33.765039 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4359 22:14:33.768318 ==
4360 22:14:33.771582 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4361 22:14:33.778470 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4362 22:14:33.781688 [CA 0] Center 35 (5~66) winsize 62
4363 22:14:33.785144 [CA 1] Center 35 (5~66) winsize 62
4364 22:14:33.788373 [CA 2] Center 34 (4~65) winsize 62
4365 22:14:33.791543 [CA 3] Center 33 (3~64) winsize 62
4366 22:14:33.794775 [CA 4] Center 34 (3~65) winsize 63
4367 22:14:33.798107 [CA 5] Center 33 (3~64) winsize 62
4368 22:14:33.798187
4369 22:14:33.801650 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4370 22:14:33.801735
4371 22:14:33.804672 [CATrainingPosCal] consider 1 rank data
4372 22:14:33.808059 u2DelayCellTimex100 = 270/100 ps
4373 22:14:33.811552 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4374 22:14:33.815092 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4375 22:14:33.818435 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4376 22:14:33.824432 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4377 22:14:33.827800 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4378 22:14:33.831201 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4379 22:14:33.831285
4380 22:14:33.835424 CA PerBit enable=1, Macro0, CA PI delay=33
4381 22:14:33.835509
4382 22:14:33.838741 [CBTSetCACLKResult] CA Dly = 33
4383 22:14:33.838826 CS Dly: 4 (0~35)
4384 22:14:33.838894 ==
4385 22:14:33.841219 Dram Type= 6, Freq= 0, CH_1, rank 1
4386 22:14:33.847717 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4387 22:14:33.847803 ==
4388 22:14:33.850961 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4389 22:14:33.857672 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4390 22:14:33.861130 [CA 0] Center 35 (5~66) winsize 62
4391 22:14:33.864671 [CA 1] Center 35 (5~66) winsize 62
4392 22:14:33.867747 [CA 2] Center 34 (4~65) winsize 62
4393 22:14:33.871207 [CA 3] Center 34 (4~64) winsize 61
4394 22:14:33.874689 [CA 4] Center 34 (4~64) winsize 61
4395 22:14:33.877970 [CA 5] Center 33 (3~64) winsize 62
4396 22:14:33.878059
4397 22:14:33.880893 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4398 22:14:33.880982
4399 22:14:33.884879 [CATrainingPosCal] consider 2 rank data
4400 22:14:33.887463 u2DelayCellTimex100 = 270/100 ps
4401 22:14:33.890844 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4402 22:14:33.897281 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4403 22:14:33.900623 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4404 22:14:33.904246 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4405 22:14:33.908004 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4406 22:14:33.910668 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4407 22:14:33.910752
4408 22:14:33.914206 CA PerBit enable=1, Macro0, CA PI delay=33
4409 22:14:33.914289
4410 22:14:33.917130 [CBTSetCACLKResult] CA Dly = 33
4411 22:14:33.921075 CS Dly: 4 (0~36)
4412 22:14:33.921158
4413 22:14:33.924141 ----->DramcWriteLeveling(PI) begin...
4414 22:14:33.924229 ==
4415 22:14:33.927343 Dram Type= 6, Freq= 0, CH_1, rank 0
4416 22:14:33.930504 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4417 22:14:33.930589 ==
4418 22:14:33.933896 Write leveling (Byte 0): 29 => 29
4419 22:14:33.937132 Write leveling (Byte 1): 30 => 30
4420 22:14:33.940285 DramcWriteLeveling(PI) end<-----
4421 22:14:33.940368
4422 22:14:33.940434 ==
4423 22:14:33.943624 Dram Type= 6, Freq= 0, CH_1, rank 0
4424 22:14:33.947455 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4425 22:14:33.947539 ==
4426 22:14:33.950309 [Gating] SW mode calibration
4427 22:14:33.956644 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4428 22:14:33.963377 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4429 22:14:33.967565 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4430 22:14:33.969801 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4431 22:14:33.976556 0 9 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
4432 22:14:33.980143 0 9 12 | B1->B0 | 2d2d 2b2b | 0 0 | (0 1) (0 1)
4433 22:14:33.982928 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4434 22:14:33.990098 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4435 22:14:33.992951 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4436 22:14:33.996167 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4437 22:14:34.002934 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4438 22:14:34.006088 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4439 22:14:34.009691 0 10 8 | B1->B0 | 2525 2828 | 0 0 | (0 0) (0 0)
4440 22:14:34.016213 0 10 12 | B1->B0 | 3939 3b3b | 0 0 | (0 0) (0 0)
4441 22:14:34.019421 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4442 22:14:34.023100 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4443 22:14:34.030016 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4444 22:14:34.032445 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4445 22:14:34.035674 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4446 22:14:34.042634 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4447 22:14:34.045812 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4448 22:14:34.049848 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4449 22:14:34.055735 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4450 22:14:34.058992 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4451 22:14:34.062172 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4452 22:14:34.068975 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4453 22:14:34.072076 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4454 22:14:34.075943 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4455 22:14:34.082250 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4456 22:14:34.085378 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4457 22:14:34.088613 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4458 22:14:34.095239 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4459 22:14:34.099211 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4460 22:14:34.102219 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4461 22:14:34.108549 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4462 22:14:34.111721 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4463 22:14:34.115115 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4464 22:14:34.121848 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4465 22:14:34.125377 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4466 22:14:34.128716 Total UI for P1: 0, mck2ui 16
4467 22:14:34.131819 best dqsien dly found for B0: ( 0, 13, 10)
4468 22:14:34.135439 Total UI for P1: 0, mck2ui 16
4469 22:14:34.138700 best dqsien dly found for B1: ( 0, 13, 12)
4470 22:14:34.141544 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4471 22:14:34.145318 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4472 22:14:34.145403
4473 22:14:34.148408 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4474 22:14:34.151455 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4475 22:14:34.155030 [Gating] SW calibration Done
4476 22:14:34.155116 ==
4477 22:14:34.158024 Dram Type= 6, Freq= 0, CH_1, rank 0
4478 22:14:34.164689 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4479 22:14:34.164837 ==
4480 22:14:34.164937 RX Vref Scan: 0
4481 22:14:34.165036
4482 22:14:34.167993 RX Vref 0 -> 0, step: 1
4483 22:14:34.168079
4484 22:14:34.171640 RX Delay -230 -> 252, step: 16
4485 22:14:34.174545 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4486 22:14:34.177799 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4487 22:14:34.181185 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4488 22:14:34.188235 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4489 22:14:34.191026 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4490 22:14:34.194532 iDelay=218, Bit 5, Center 57 (-86 ~ 201) 288
4491 22:14:34.197611 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4492 22:14:34.201466 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4493 22:14:34.207575 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4494 22:14:34.211089 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4495 22:14:34.214410 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4496 22:14:34.217730 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4497 22:14:34.224218 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4498 22:14:34.227676 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4499 22:14:34.231647 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4500 22:14:34.234087 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4501 22:14:34.237689 ==
4502 22:14:34.237773 Dram Type= 6, Freq= 0, CH_1, rank 0
4503 22:14:34.244074 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4504 22:14:34.244160 ==
4505 22:14:34.244228 DQS Delay:
4506 22:14:34.247265 DQS0 = 0, DQS1 = 0
4507 22:14:34.247349 DQM Delay:
4508 22:14:34.250557 DQM0 = 53, DQM1 = 43
4509 22:14:34.250642 DQ Delay:
4510 22:14:34.253866 DQ0 =57, DQ1 =49, DQ2 =49, DQ3 =49
4511 22:14:34.257653 DQ4 =49, DQ5 =57, DQ6 =65, DQ7 =49
4512 22:14:34.260631 DQ8 =25, DQ9 =25, DQ10 =49, DQ11 =41
4513 22:14:34.263813 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =49
4514 22:14:34.263897
4515 22:14:34.263964
4516 22:14:34.264024 ==
4517 22:14:34.267120 Dram Type= 6, Freq= 0, CH_1, rank 0
4518 22:14:34.270473 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4519 22:14:34.270560 ==
4520 22:14:34.270628
4521 22:14:34.270692
4522 22:14:34.273866 TX Vref Scan disable
4523 22:14:34.277118 == TX Byte 0 ==
4524 22:14:34.280697 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4525 22:14:34.283867 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4526 22:14:34.287395 == TX Byte 1 ==
4527 22:14:34.290582 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4528 22:14:34.294054 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4529 22:14:34.294139 ==
4530 22:14:34.297051 Dram Type= 6, Freq= 0, CH_1, rank 0
4531 22:14:34.303582 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4532 22:14:34.303668 ==
4533 22:14:34.303734
4534 22:14:34.303794
4535 22:14:34.303852 TX Vref Scan disable
4536 22:14:34.307615 == TX Byte 0 ==
4537 22:14:34.311564 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4538 22:14:34.314965 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4539 22:14:34.317632 == TX Byte 1 ==
4540 22:14:34.320713 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4541 22:14:34.327518 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4542 22:14:34.327602
4543 22:14:34.327668 [DATLAT]
4544 22:14:34.327728 Freq=600, CH1 RK0
4545 22:14:34.327788
4546 22:14:34.331200 DATLAT Default: 0x9
4547 22:14:34.331284 0, 0xFFFF, sum = 0
4548 22:14:34.334374 1, 0xFFFF, sum = 0
4549 22:14:34.337494 2, 0xFFFF, sum = 0
4550 22:14:34.337578 3, 0xFFFF, sum = 0
4551 22:14:34.340890 4, 0xFFFF, sum = 0
4552 22:14:34.340974 5, 0xFFFF, sum = 0
4553 22:14:34.344134 6, 0xFFFF, sum = 0
4554 22:14:34.344218 7, 0xFFFF, sum = 0
4555 22:14:34.347422 8, 0x0, sum = 1
4556 22:14:34.347507 9, 0x0, sum = 2
4557 22:14:34.347575 10, 0x0, sum = 3
4558 22:14:34.350653 11, 0x0, sum = 4
4559 22:14:34.350737 best_step = 9
4560 22:14:34.350803
4561 22:14:34.350864 ==
4562 22:14:34.353996 Dram Type= 6, Freq= 0, CH_1, rank 0
4563 22:14:34.360818 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4564 22:14:34.360928 ==
4565 22:14:34.361023 RX Vref Scan: 1
4566 22:14:34.361113
4567 22:14:34.364213 RX Vref 0 -> 0, step: 1
4568 22:14:34.364283
4569 22:14:34.367209 RX Delay -179 -> 252, step: 8
4570 22:14:34.367363
4571 22:14:34.370514 Set Vref, RX VrefLevel [Byte0]: 53
4572 22:14:34.373805 [Byte1]: 53
4573 22:14:34.373888
4574 22:14:34.377386 Final RX Vref Byte 0 = 53 to rank0
4575 22:14:34.380401 Final RX Vref Byte 1 = 53 to rank0
4576 22:14:34.383692 Final RX Vref Byte 0 = 53 to rank1
4577 22:14:34.386882 Final RX Vref Byte 1 = 53 to rank1==
4578 22:14:34.390182 Dram Type= 6, Freq= 0, CH_1, rank 0
4579 22:14:34.393667 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4580 22:14:34.397098 ==
4581 22:14:34.397215 DQS Delay:
4582 22:14:34.397283 DQS0 = 0, DQS1 = 0
4583 22:14:34.400130 DQM Delay:
4584 22:14:34.400213 DQM0 = 49, DQM1 = 42
4585 22:14:34.403367 DQ Delay:
4586 22:14:34.403458 DQ0 =56, DQ1 =44, DQ2 =36, DQ3 =44
4587 22:14:34.406838 DQ4 =52, DQ5 =60, DQ6 =60, DQ7 =44
4588 22:14:34.409993 DQ8 =28, DQ9 =28, DQ10 =48, DQ11 =32
4589 22:14:34.413819 DQ12 =56, DQ13 =48, DQ14 =48, DQ15 =48
4590 22:14:34.416734
4591 22:14:34.416825
4592 22:14:34.422974 [DQSOSCAuto] RK0, (LSB)MR18= 0x4d73, (MSB)MR19= 0x808, tDQSOscB0 = 388 ps tDQSOscB1 = 395 ps
4593 22:14:34.426330 CH1 RK0: MR19=808, MR18=4D73
4594 22:14:34.432807 CH1_RK0: MR19=0x808, MR18=0x4D73, DQSOSC=388, MR23=63, INC=174, DEC=116
4595 22:14:34.432896
4596 22:14:34.436197 ----->DramcWriteLeveling(PI) begin...
4597 22:14:34.436285 ==
4598 22:14:34.439753 Dram Type= 6, Freq= 0, CH_1, rank 1
4599 22:14:34.442946 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4600 22:14:34.443034 ==
4601 22:14:34.446106 Write leveling (Byte 0): 30 => 30
4602 22:14:34.449303 Write leveling (Byte 1): 29 => 29
4603 22:14:34.452940 DramcWriteLeveling(PI) end<-----
4604 22:14:34.453026
4605 22:14:34.453130 ==
4606 22:14:34.455969 Dram Type= 6, Freq= 0, CH_1, rank 1
4607 22:14:34.459796 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4608 22:14:34.459884 ==
4609 22:14:34.463241 [Gating] SW mode calibration
4610 22:14:34.469188 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4611 22:14:34.476937 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4612 22:14:34.479196 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4613 22:14:34.485757 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4614 22:14:34.489402 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
4615 22:14:34.492350 0 9 12 | B1->B0 | 2a2a 3333 | 0 1 | (0 0) (1 0)
4616 22:14:34.499187 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4617 22:14:34.502481 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4618 22:14:34.505723 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4619 22:14:34.512173 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4620 22:14:34.515791 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4621 22:14:34.518911 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4622 22:14:34.525509 0 10 8 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
4623 22:14:34.528907 0 10 12 | B1->B0 | 3939 3030 | 0 0 | (0 0) (1 1)
4624 22:14:34.532093 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4625 22:14:34.535511 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4626 22:14:34.542483 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4627 22:14:34.545526 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4628 22:14:34.548893 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4629 22:14:34.555277 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4630 22:14:34.558888 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4631 22:14:34.562157 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4632 22:14:34.568531 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4633 22:14:34.572389 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4634 22:14:34.575349 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4635 22:14:34.581877 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4636 22:14:34.585078 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4637 22:14:34.588603 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4638 22:14:34.595089 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4639 22:14:34.598537 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4640 22:14:34.601663 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4641 22:14:34.608606 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4642 22:14:34.611751 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4643 22:14:34.614987 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4644 22:14:34.621453 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4645 22:14:34.624655 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4646 22:14:34.628364 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4647 22:14:34.634630 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4648 22:14:34.638193 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4649 22:14:34.641785 Total UI for P1: 0, mck2ui 16
4650 22:14:34.645031 best dqsien dly found for B0: ( 0, 13, 12)
4651 22:14:34.648714 Total UI for P1: 0, mck2ui 16
4652 22:14:34.651173 best dqsien dly found for B1: ( 0, 13, 12)
4653 22:14:34.654497 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4654 22:14:34.658032 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4655 22:14:34.658120
4656 22:14:34.661170 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4657 22:14:34.664572 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4658 22:14:34.667968 [Gating] SW calibration Done
4659 22:14:34.668056 ==
4660 22:14:34.671396 Dram Type= 6, Freq= 0, CH_1, rank 1
4661 22:14:34.677751 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4662 22:14:34.677839 ==
4663 22:14:34.677925 RX Vref Scan: 0
4664 22:14:34.678006
4665 22:14:34.681117 RX Vref 0 -> 0, step: 1
4666 22:14:34.681203
4667 22:14:34.684611 RX Delay -230 -> 252, step: 16
4668 22:14:34.687522 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4669 22:14:34.690937 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4670 22:14:34.694518 iDelay=218, Bit 2, Center 41 (-102 ~ 185) 288
4671 22:14:34.700931 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4672 22:14:34.704183 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4673 22:14:34.707169 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4674 22:14:34.710642 iDelay=218, Bit 6, Center 57 (-86 ~ 201) 288
4675 22:14:34.717273 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4676 22:14:34.720759 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4677 22:14:34.724443 iDelay=218, Bit 9, Center 41 (-102 ~ 185) 288
4678 22:14:34.727052 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4679 22:14:34.730463 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4680 22:14:34.737074 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4681 22:14:34.740684 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4682 22:14:34.743904 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4683 22:14:34.749991 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4684 22:14:34.750106 ==
4685 22:14:34.753637 Dram Type= 6, Freq= 0, CH_1, rank 1
4686 22:14:34.756562 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4687 22:14:34.756650 ==
4688 22:14:34.756747 DQS Delay:
4689 22:14:34.759948 DQS0 = 0, DQS1 = 0
4690 22:14:34.760033 DQM Delay:
4691 22:14:34.763841 DQM0 = 52, DQM1 = 47
4692 22:14:34.763952 DQ Delay:
4693 22:14:34.766619 DQ0 =57, DQ1 =49, DQ2 =41, DQ3 =49
4694 22:14:34.770498 DQ4 =49, DQ5 =65, DQ6 =57, DQ7 =49
4695 22:14:34.773158 DQ8 =33, DQ9 =41, DQ10 =49, DQ11 =41
4696 22:14:34.776560 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57
4697 22:14:34.776662
4698 22:14:34.776757
4699 22:14:34.776832 ==
4700 22:14:34.779676 Dram Type= 6, Freq= 0, CH_1, rank 1
4701 22:14:34.783092 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4702 22:14:34.783177 ==
4703 22:14:34.786180
4704 22:14:34.786264
4705 22:14:34.786330 TX Vref Scan disable
4706 22:14:34.789783 == TX Byte 0 ==
4707 22:14:34.793124 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4708 22:14:34.796379 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4709 22:14:34.799514 == TX Byte 1 ==
4710 22:14:34.803105 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4711 22:14:34.806123 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4712 22:14:34.809360 ==
4713 22:14:34.809448 Dram Type= 6, Freq= 0, CH_1, rank 1
4714 22:14:34.816006 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4715 22:14:34.816092 ==
4716 22:14:34.816159
4717 22:14:34.816221
4718 22:14:34.819478 TX Vref Scan disable
4719 22:14:34.819562 == TX Byte 0 ==
4720 22:14:34.825843 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4721 22:14:34.829309 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4722 22:14:34.829394 == TX Byte 1 ==
4723 22:14:34.835891 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4724 22:14:34.839535 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4725 22:14:34.839620
4726 22:14:34.839687 [DATLAT]
4727 22:14:34.842568 Freq=600, CH1 RK1
4728 22:14:34.842653
4729 22:14:34.842720 DATLAT Default: 0x9
4730 22:14:34.845985 0, 0xFFFF, sum = 0
4731 22:14:34.846071 1, 0xFFFF, sum = 0
4732 22:14:34.849480 2, 0xFFFF, sum = 0
4733 22:14:34.849570 3, 0xFFFF, sum = 0
4734 22:14:34.852313 4, 0xFFFF, sum = 0
4735 22:14:34.855695 5, 0xFFFF, sum = 0
4736 22:14:34.855784 6, 0xFFFF, sum = 0
4737 22:14:34.859180 7, 0xFFFF, sum = 0
4738 22:14:34.859265 8, 0x0, sum = 1
4739 22:14:34.859334 9, 0x0, sum = 2
4740 22:14:34.862365 10, 0x0, sum = 3
4741 22:14:34.862479 11, 0x0, sum = 4
4742 22:14:34.865447 best_step = 9
4743 22:14:34.865558
4744 22:14:34.865654 ==
4745 22:14:34.868707 Dram Type= 6, Freq= 0, CH_1, rank 1
4746 22:14:34.872241 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4747 22:14:34.872356 ==
4748 22:14:34.875583 RX Vref Scan: 0
4749 22:14:34.875667
4750 22:14:34.875734 RX Vref 0 -> 0, step: 1
4751 22:14:34.875797
4752 22:14:34.879075 RX Delay -163 -> 252, step: 8
4753 22:14:34.885966 iDelay=205, Bit 0, Center 56 (-83 ~ 196) 280
4754 22:14:34.889357 iDelay=205, Bit 1, Center 40 (-99 ~ 180) 280
4755 22:14:34.892662 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4756 22:14:34.896407 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4757 22:14:34.902706 iDelay=205, Bit 4, Center 52 (-91 ~ 196) 288
4758 22:14:34.905892 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4759 22:14:34.909878 iDelay=205, Bit 6, Center 56 (-83 ~ 196) 280
4760 22:14:34.913141 iDelay=205, Bit 7, Center 48 (-91 ~ 188) 280
4761 22:14:34.916123 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4762 22:14:34.922408 iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296
4763 22:14:34.925569 iDelay=205, Bit 10, Center 44 (-99 ~ 188) 288
4764 22:14:34.929768 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4765 22:14:34.932542 iDelay=205, Bit 12, Center 48 (-99 ~ 196) 296
4766 22:14:34.939051 iDelay=205, Bit 13, Center 48 (-99 ~ 196) 296
4767 22:14:34.942311 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4768 22:14:34.945871 iDelay=205, Bit 15, Center 56 (-91 ~ 204) 296
4769 22:14:34.945949 ==
4770 22:14:34.948583 Dram Type= 6, Freq= 0, CH_1, rank 1
4771 22:14:34.952157 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4772 22:14:34.952237 ==
4773 22:14:34.955399 DQS Delay:
4774 22:14:34.955477 DQS0 = 0, DQS1 = 0
4775 22:14:34.959113 DQM Delay:
4776 22:14:34.959191 DQM0 = 49, DQM1 = 43
4777 22:14:34.959273 DQ Delay:
4778 22:14:34.962026 DQ0 =56, DQ1 =40, DQ2 =36, DQ3 =44
4779 22:14:34.965412 DQ4 =52, DQ5 =60, DQ6 =56, DQ7 =48
4780 22:14:34.968366 DQ8 =32, DQ9 =32, DQ10 =44, DQ11 =40
4781 22:14:34.971832 DQ12 =48, DQ13 =48, DQ14 =48, DQ15 =56
4782 22:14:34.971917
4783 22:14:34.971985
4784 22:14:34.981798 [DQSOSCAuto] RK1, (LSB)MR18= 0x5b22, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 392 ps
4785 22:14:34.985364 CH1 RK1: MR19=808, MR18=5B22
4786 22:14:34.991532 CH1_RK1: MR19=0x808, MR18=0x5B22, DQSOSC=392, MR23=63, INC=170, DEC=113
4787 22:14:34.994857 [RxdqsGatingPostProcess] freq 600
4788 22:14:34.999121 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4789 22:14:35.001683 Pre-setting of DQS Precalculation
4790 22:14:35.004847 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4791 22:14:35.014865 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4792 22:14:35.021742 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4793 22:14:35.021829
4794 22:14:35.021897
4795 22:14:35.025303 [Calibration Summary] 1200 Mbps
4796 22:14:35.025389 CH 0, Rank 0
4797 22:14:35.028227 SW Impedance : PASS
4798 22:14:35.028312 DUTY Scan : NO K
4799 22:14:35.031715 ZQ Calibration : PASS
4800 22:14:35.034940 Jitter Meter : NO K
4801 22:14:35.035026 CBT Training : PASS
4802 22:14:35.038156 Write leveling : PASS
4803 22:14:35.041357 RX DQS gating : PASS
4804 22:14:35.041443 RX DQ/DQS(RDDQC) : PASS
4805 22:14:35.044743 TX DQ/DQS : PASS
4806 22:14:35.048266 RX DATLAT : PASS
4807 22:14:35.048351 RX DQ/DQS(Engine): PASS
4808 22:14:35.051422 TX OE : NO K
4809 22:14:35.051507 All Pass.
4810 22:14:35.051576
4811 22:14:35.054884 CH 0, Rank 1
4812 22:14:35.054969 SW Impedance : PASS
4813 22:14:35.057895 DUTY Scan : NO K
4814 22:14:35.061469 ZQ Calibration : PASS
4815 22:14:35.061554 Jitter Meter : NO K
4816 22:14:35.064889 CBT Training : PASS
4817 22:14:35.067987 Write leveling : PASS
4818 22:14:35.068073 RX DQS gating : PASS
4819 22:14:35.071492 RX DQ/DQS(RDDQC) : PASS
4820 22:14:35.074790 TX DQ/DQS : PASS
4821 22:14:35.074875 RX DATLAT : PASS
4822 22:14:35.078219 RX DQ/DQS(Engine): PASS
4823 22:14:35.078303 TX OE : NO K
4824 22:14:35.081343 All Pass.
4825 22:14:35.081427
4826 22:14:35.081494 CH 1, Rank 0
4827 22:14:35.084685 SW Impedance : PASS
4828 22:14:35.084774 DUTY Scan : NO K
4829 22:14:35.087926 ZQ Calibration : PASS
4830 22:14:35.091432 Jitter Meter : NO K
4831 22:14:35.091516 CBT Training : PASS
4832 22:14:35.094325 Write leveling : PASS
4833 22:14:35.097580 RX DQS gating : PASS
4834 22:14:35.097664 RX DQ/DQS(RDDQC) : PASS
4835 22:14:35.101114 TX DQ/DQS : PASS
4836 22:14:35.104352 RX DATLAT : PASS
4837 22:14:35.104436 RX DQ/DQS(Engine): PASS
4838 22:14:35.107318 TX OE : NO K
4839 22:14:35.107404 All Pass.
4840 22:14:35.107471
4841 22:14:35.110812 CH 1, Rank 1
4842 22:14:35.110895 SW Impedance : PASS
4843 22:14:35.114514 DUTY Scan : NO K
4844 22:14:35.117335 ZQ Calibration : PASS
4845 22:14:35.117419 Jitter Meter : NO K
4846 22:14:35.120880 CBT Training : PASS
4847 22:14:35.124454 Write leveling : PASS
4848 22:14:35.124537 RX DQS gating : PASS
4849 22:14:35.127321 RX DQ/DQS(RDDQC) : PASS
4850 22:14:35.130629 TX DQ/DQS : PASS
4851 22:14:35.130714 RX DATLAT : PASS
4852 22:14:35.133878 RX DQ/DQS(Engine): PASS
4853 22:14:35.137416 TX OE : NO K
4854 22:14:35.137500 All Pass.
4855 22:14:35.137567
4856 22:14:35.137630 DramC Write-DBI off
4857 22:14:35.140496 PER_BANK_REFRESH: Hybrid Mode
4858 22:14:35.143962 TX_TRACKING: ON
4859 22:14:35.150801 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4860 22:14:35.154013 [FAST_K] Save calibration result to emmc
4861 22:14:35.160579 dramc_set_vcore_voltage set vcore to 662500
4862 22:14:35.160667 Read voltage for 933, 3
4863 22:14:35.164023 Vio18 = 0
4864 22:14:35.164110 Vcore = 662500
4865 22:14:35.164197 Vdram = 0
4866 22:14:35.164279 Vddq = 0
4867 22:14:35.167741 Vmddr = 0
4868 22:14:35.170283 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4869 22:14:35.177004 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4870 22:14:35.180290 MEM_TYPE=3, freq_sel=17
4871 22:14:35.183844 sv_algorithm_assistance_LP4_1600
4872 22:14:35.186774 ============ PULL DRAM RESETB DOWN ============
4873 22:14:35.190568 ========== PULL DRAM RESETB DOWN end =========
4874 22:14:35.193457 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4875 22:14:35.196897 ===================================
4876 22:14:35.200357 LPDDR4 DRAM CONFIGURATION
4877 22:14:35.203797 ===================================
4878 22:14:35.206566 EX_ROW_EN[0] = 0x0
4879 22:14:35.206654 EX_ROW_EN[1] = 0x0
4880 22:14:35.209985 LP4Y_EN = 0x0
4881 22:14:35.210072 WORK_FSP = 0x0
4882 22:14:35.213405 WL = 0x3
4883 22:14:35.213493 RL = 0x3
4884 22:14:35.216703 BL = 0x2
4885 22:14:35.216798 RPST = 0x0
4886 22:14:35.220002 RD_PRE = 0x0
4887 22:14:35.223203 WR_PRE = 0x1
4888 22:14:35.223290 WR_PST = 0x0
4889 22:14:35.226469 DBI_WR = 0x0
4890 22:14:35.226557 DBI_RD = 0x0
4891 22:14:35.229967 OTF = 0x1
4892 22:14:35.233360 ===================================
4893 22:14:35.237021 ===================================
4894 22:14:35.237109 ANA top config
4895 22:14:35.240161 ===================================
4896 22:14:35.243206 DLL_ASYNC_EN = 0
4897 22:14:35.246270 ALL_SLAVE_EN = 1
4898 22:14:35.246358 NEW_RANK_MODE = 1
4899 22:14:35.250192 DLL_IDLE_MODE = 1
4900 22:14:35.253550 LP45_APHY_COMB_EN = 1
4901 22:14:35.256141 TX_ODT_DIS = 1
4902 22:14:35.256229 NEW_8X_MODE = 1
4903 22:14:35.259445 ===================================
4904 22:14:35.262941 ===================================
4905 22:14:35.266239 data_rate = 1866
4906 22:14:35.269921 CKR = 1
4907 22:14:35.273648 DQ_P2S_RATIO = 8
4908 22:14:35.276053 ===================================
4909 22:14:35.279376 CA_P2S_RATIO = 8
4910 22:14:35.282882 DQ_CA_OPEN = 0
4911 22:14:35.282970 DQ_SEMI_OPEN = 0
4912 22:14:35.285860 CA_SEMI_OPEN = 0
4913 22:14:35.289467 CA_FULL_RATE = 0
4914 22:14:35.292588 DQ_CKDIV4_EN = 1
4915 22:14:35.295930 CA_CKDIV4_EN = 1
4916 22:14:35.299992 CA_PREDIV_EN = 0
4917 22:14:35.300079 PH8_DLY = 0
4918 22:14:35.302681 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4919 22:14:35.305830 DQ_AAMCK_DIV = 4
4920 22:14:35.309282 CA_AAMCK_DIV = 4
4921 22:14:35.312520 CA_ADMCK_DIV = 4
4922 22:14:35.316011 DQ_TRACK_CA_EN = 0
4923 22:14:35.319262 CA_PICK = 933
4924 22:14:35.319351 CA_MCKIO = 933
4925 22:14:35.322369 MCKIO_SEMI = 0
4926 22:14:35.326125 PLL_FREQ = 3732
4927 22:14:35.329220 DQ_UI_PI_RATIO = 32
4928 22:14:35.332254 CA_UI_PI_RATIO = 0
4929 22:14:35.335931 ===================================
4930 22:14:35.339360 ===================================
4931 22:14:35.342392 memory_type:LPDDR4
4932 22:14:35.342480 GP_NUM : 10
4933 22:14:35.345703 SRAM_EN : 1
4934 22:14:35.345790 MD32_EN : 0
4935 22:14:35.348915 ===================================
4936 22:14:35.352086 [ANA_INIT] >>>>>>>>>>>>>>
4937 22:14:35.355738 <<<<<< [CONFIGURE PHASE]: ANA_TX
4938 22:14:35.358903 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4939 22:14:35.362099 ===================================
4940 22:14:35.366029 data_rate = 1866,PCW = 0X8f00
4941 22:14:35.368692 ===================================
4942 22:14:35.372100 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4943 22:14:35.378907 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4944 22:14:35.382143 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4945 22:14:35.388786 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4946 22:14:35.391885 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4947 22:14:35.395371 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4948 22:14:35.395459 [ANA_INIT] flow start
4949 22:14:35.398681 [ANA_INIT] PLL >>>>>>>>
4950 22:14:35.401967 [ANA_INIT] PLL <<<<<<<<
4951 22:14:35.402054 [ANA_INIT] MIDPI >>>>>>>>
4952 22:14:35.405161 [ANA_INIT] MIDPI <<<<<<<<
4953 22:14:35.408216 [ANA_INIT] DLL >>>>>>>>
4954 22:14:35.408303 [ANA_INIT] flow end
4955 22:14:35.415088 ============ LP4 DIFF to SE enter ============
4956 22:14:35.418541 ============ LP4 DIFF to SE exit ============
4957 22:14:35.422060 [ANA_INIT] <<<<<<<<<<<<<
4958 22:14:35.424749 [Flow] Enable top DCM control >>>>>
4959 22:14:35.428124 [Flow] Enable top DCM control <<<<<
4960 22:14:35.428212 Enable DLL master slave shuffle
4961 22:14:35.435118 ==============================================================
4962 22:14:35.438685 Gating Mode config
4963 22:14:35.441535 ==============================================================
4964 22:14:35.444718 Config description:
4965 22:14:35.454390 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4966 22:14:35.462041 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4967 22:14:35.464416 SELPH_MODE 0: By rank 1: By Phase
4968 22:14:35.471010 ==============================================================
4969 22:14:35.474465 GAT_TRACK_EN = 1
4970 22:14:35.477857 RX_GATING_MODE = 2
4971 22:14:35.481041 RX_GATING_TRACK_MODE = 2
4972 22:14:35.484906 SELPH_MODE = 1
4973 22:14:35.487902 PICG_EARLY_EN = 1
4974 22:14:35.487987 VALID_LAT_VALUE = 1
4975 22:14:35.494358 ==============================================================
4976 22:14:35.497775 Enter into Gating configuration >>>>
4977 22:14:35.500860 Exit from Gating configuration <<<<
4978 22:14:35.504254 Enter into DVFS_PRE_config >>>>>
4979 22:14:35.513979 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4980 22:14:35.517868 Exit from DVFS_PRE_config <<<<<
4981 22:14:35.520701 Enter into PICG configuration >>>>
4982 22:14:35.524015 Exit from PICG configuration <<<<
4983 22:14:35.527454 [RX_INPUT] configuration >>>>>
4984 22:14:35.530539 [RX_INPUT] configuration <<<<<
4985 22:14:35.537060 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4986 22:14:35.540333 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4987 22:14:35.547168 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4988 22:14:35.553909 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4989 22:14:35.560068 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4990 22:14:35.567143 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4991 22:14:35.570193 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4992 22:14:35.573400 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4993 22:14:35.576750 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4994 22:14:35.583386 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4995 22:14:35.586833 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4996 22:14:35.590440 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4997 22:14:35.594124 ===================================
4998 22:14:35.596567 LPDDR4 DRAM CONFIGURATION
4999 22:14:35.600224 ===================================
5000 22:14:35.603299 EX_ROW_EN[0] = 0x0
5001 22:14:35.603386 EX_ROW_EN[1] = 0x0
5002 22:14:35.606480 LP4Y_EN = 0x0
5003 22:14:35.606565 WORK_FSP = 0x0
5004 22:14:35.610169 WL = 0x3
5005 22:14:35.610255 RL = 0x3
5006 22:14:35.613406 BL = 0x2
5007 22:14:35.613491 RPST = 0x0
5008 22:14:35.616813 RD_PRE = 0x0
5009 22:14:35.616898 WR_PRE = 0x1
5010 22:14:35.619808 WR_PST = 0x0
5011 22:14:35.619894 DBI_WR = 0x0
5012 22:14:35.623134 DBI_RD = 0x0
5013 22:14:35.623219 OTF = 0x1
5014 22:14:35.626441 ===================================
5015 22:14:35.633873 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5016 22:14:35.636251 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5017 22:14:35.639643 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5018 22:14:35.642978 ===================================
5019 22:14:35.646361 LPDDR4 DRAM CONFIGURATION
5020 22:14:35.649726 ===================================
5021 22:14:35.649812 EX_ROW_EN[0] = 0x10
5022 22:14:35.653122 EX_ROW_EN[1] = 0x0
5023 22:14:35.656171 LP4Y_EN = 0x0
5024 22:14:35.656257 WORK_FSP = 0x0
5025 22:14:35.659335 WL = 0x3
5026 22:14:35.659420 RL = 0x3
5027 22:14:35.663377 BL = 0x2
5028 22:14:35.663462 RPST = 0x0
5029 22:14:35.666308 RD_PRE = 0x0
5030 22:14:35.666393 WR_PRE = 0x1
5031 22:14:35.669828 WR_PST = 0x0
5032 22:14:35.669914 DBI_WR = 0x0
5033 22:14:35.672746 DBI_RD = 0x0
5034 22:14:35.672870 OTF = 0x1
5035 22:14:35.676303 ===================================
5036 22:14:35.682654 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5037 22:14:35.687029 nWR fixed to 30
5038 22:14:35.690505 [ModeRegInit_LP4] CH0 RK0
5039 22:14:35.690590 [ModeRegInit_LP4] CH0 RK1
5040 22:14:35.694020 [ModeRegInit_LP4] CH1 RK0
5041 22:14:35.697114 [ModeRegInit_LP4] CH1 RK1
5042 22:14:35.697200 match AC timing 9
5043 22:14:35.703936 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5044 22:14:35.706946 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5045 22:14:35.710365 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5046 22:14:35.716668 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5047 22:14:35.720718 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5048 22:14:35.720843 ==
5049 22:14:35.723320 Dram Type= 6, Freq= 0, CH_0, rank 0
5050 22:14:35.726771 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5051 22:14:35.726858 ==
5052 22:14:35.733334 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5053 22:14:35.739767 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5054 22:14:35.743335 [CA 0] Center 38 (7~69) winsize 63
5055 22:14:35.746610 [CA 1] Center 38 (7~69) winsize 63
5056 22:14:35.749680 [CA 2] Center 35 (5~66) winsize 62
5057 22:14:35.753107 [CA 3] Center 35 (5~65) winsize 61
5058 22:14:35.756646 [CA 4] Center 34 (4~65) winsize 62
5059 22:14:35.759704 [CA 5] Center 33 (3~64) winsize 62
5060 22:14:35.759789
5061 22:14:35.762951 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5062 22:14:35.763036
5063 22:14:35.766283 [CATrainingPosCal] consider 1 rank data
5064 22:14:35.769605 u2DelayCellTimex100 = 270/100 ps
5065 22:14:35.772663 CA0 delay=38 (7~69),Diff = 5 PI (31 cell)
5066 22:14:35.775852 CA1 delay=38 (7~69),Diff = 5 PI (31 cell)
5067 22:14:35.779544 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5068 22:14:35.785933 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5069 22:14:35.789306 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5070 22:14:35.792548 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5071 22:14:35.792633
5072 22:14:35.795771 CA PerBit enable=1, Macro0, CA PI delay=33
5073 22:14:35.795857
5074 22:14:35.799508 [CBTSetCACLKResult] CA Dly = 33
5075 22:14:35.799593 CS Dly: 6 (0~37)
5076 22:14:35.799662 ==
5077 22:14:35.802515 Dram Type= 6, Freq= 0, CH_0, rank 1
5078 22:14:35.809585 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5079 22:14:35.809672 ==
5080 22:14:35.812397 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5081 22:14:35.818828 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5082 22:14:35.822755 [CA 0] Center 38 (7~69) winsize 63
5083 22:14:35.825728 [CA 1] Center 38 (8~69) winsize 62
5084 22:14:35.828800 [CA 2] Center 36 (6~66) winsize 61
5085 22:14:35.832549 [CA 3] Center 35 (5~66) winsize 62
5086 22:14:35.835960 [CA 4] Center 35 (4~66) winsize 63
5087 22:14:35.838766 [CA 5] Center 34 (4~64) winsize 61
5088 22:14:35.838852
5089 22:14:35.842080 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5090 22:14:35.842165
5091 22:14:35.845544 [CATrainingPosCal] consider 2 rank data
5092 22:14:35.848952 u2DelayCellTimex100 = 270/100 ps
5093 22:14:35.852334 CA0 delay=38 (7~69),Diff = 4 PI (24 cell)
5094 22:14:35.858748 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5095 22:14:35.861768 CA2 delay=36 (6~66),Diff = 2 PI (12 cell)
5096 22:14:35.865137 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5097 22:14:35.868913 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5098 22:14:35.871710 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5099 22:14:35.871795
5100 22:14:35.874865 CA PerBit enable=1, Macro0, CA PI delay=34
5101 22:14:35.874950
5102 22:14:35.878375 [CBTSetCACLKResult] CA Dly = 34
5103 22:14:35.881702 CS Dly: 7 (0~39)
5104 22:14:35.881787
5105 22:14:35.885014 ----->DramcWriteLeveling(PI) begin...
5106 22:14:35.885100 ==
5107 22:14:35.888209 Dram Type= 6, Freq= 0, CH_0, rank 0
5108 22:14:35.891760 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5109 22:14:35.891845 ==
5110 22:14:35.894711 Write leveling (Byte 0): 31 => 31
5111 22:14:35.898066 Write leveling (Byte 1): 28 => 28
5112 22:14:35.901691 DramcWriteLeveling(PI) end<-----
5113 22:14:35.901776
5114 22:14:35.901844 ==
5115 22:14:35.904485 Dram Type= 6, Freq= 0, CH_0, rank 0
5116 22:14:35.908187 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5117 22:14:35.908273 ==
5118 22:14:35.911062 [Gating] SW mode calibration
5119 22:14:35.917553 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5120 22:14:35.924540 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5121 22:14:35.927619 0 14 0 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
5122 22:14:35.934263 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5123 22:14:35.938013 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5124 22:14:35.940716 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5125 22:14:35.947339 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5126 22:14:35.950861 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5127 22:14:35.954135 0 14 24 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 1)
5128 22:14:35.960927 0 14 28 | B1->B0 | 3232 2626 | 1 0 | (0 1) (1 0)
5129 22:14:35.964309 0 15 0 | B1->B0 | 2525 2323 | 0 0 | (1 0) (0 0)
5130 22:14:35.967112 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5131 22:14:35.973948 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5132 22:14:35.977194 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5133 22:14:35.980176 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5134 22:14:35.986835 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5135 22:14:35.990131 0 15 24 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
5136 22:14:35.993645 0 15 28 | B1->B0 | 2c2c 4646 | 0 0 | (0 0) (0 0)
5137 22:14:36.000176 1 0 0 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
5138 22:14:36.003519 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5139 22:14:36.006849 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5140 22:14:36.013422 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5141 22:14:36.016937 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5142 22:14:36.020334 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5143 22:14:36.026704 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5144 22:14:36.029790 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5145 22:14:36.033223 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5146 22:14:36.036495 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5147 22:14:36.043375 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5148 22:14:36.046835 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5149 22:14:36.049875 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5150 22:14:36.056581 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5151 22:14:36.060122 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5152 22:14:36.063109 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5153 22:14:36.070109 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5154 22:14:36.073065 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5155 22:14:36.076069 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5156 22:14:36.082791 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5157 22:14:36.086441 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5158 22:14:36.089416 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5159 22:14:36.096106 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5160 22:14:36.099337 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5161 22:14:36.102579 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5162 22:14:36.105927 Total UI for P1: 0, mck2ui 16
5163 22:14:36.109163 best dqsien dly found for B0: ( 1, 2, 26)
5164 22:14:36.112998 Total UI for P1: 0, mck2ui 16
5165 22:14:36.115949 best dqsien dly found for B1: ( 1, 2, 30)
5166 22:14:36.119081 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5167 22:14:36.122748 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5168 22:14:36.126065
5169 22:14:36.129675 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5170 22:14:36.132481 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5171 22:14:36.135794 [Gating] SW calibration Done
5172 22:14:36.135878 ==
5173 22:14:36.139240 Dram Type= 6, Freq= 0, CH_0, rank 0
5174 22:14:36.142178 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5175 22:14:36.142263 ==
5176 22:14:36.142330 RX Vref Scan: 0
5177 22:14:36.145668
5178 22:14:36.145752 RX Vref 0 -> 0, step: 1
5179 22:14:36.145819
5180 22:14:36.149063 RX Delay -80 -> 252, step: 8
5181 22:14:36.152153 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5182 22:14:36.158811 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5183 22:14:36.161920 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5184 22:14:36.165397 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5185 22:14:36.168533 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5186 22:14:36.172216 iDelay=208, Bit 5, Center 91 (0 ~ 183) 184
5187 22:14:36.175485 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5188 22:14:36.181690 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5189 22:14:36.185092 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5190 22:14:36.188290 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5191 22:14:36.191725 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5192 22:14:36.195029 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5193 22:14:36.198313 iDelay=208, Bit 12, Center 91 (0 ~ 183) 184
5194 22:14:36.205142 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5195 22:14:36.208171 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5196 22:14:36.211533 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5197 22:14:36.211617 ==
5198 22:14:36.214663 Dram Type= 6, Freq= 0, CH_0, rank 0
5199 22:14:36.218088 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5200 22:14:36.218174 ==
5201 22:14:36.221363 DQS Delay:
5202 22:14:36.221447 DQS0 = 0, DQS1 = 0
5203 22:14:36.224561 DQM Delay:
5204 22:14:36.224644 DQM0 = 105, DQM1 = 90
5205 22:14:36.224710 DQ Delay:
5206 22:14:36.228552 DQ0 =107, DQ1 =107, DQ2 =99, DQ3 =99
5207 22:14:36.231479 DQ4 =107, DQ5 =91, DQ6 =115, DQ7 =115
5208 22:14:36.234523 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =87
5209 22:14:36.241081 DQ12 =91, DQ13 =91, DQ14 =99, DQ15 =99
5210 22:14:36.241165
5211 22:14:36.241232
5212 22:14:36.241292 ==
5213 22:14:36.244499 Dram Type= 6, Freq= 0, CH_0, rank 0
5214 22:14:36.247710 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5215 22:14:36.247794 ==
5216 22:14:36.247861
5217 22:14:36.247922
5218 22:14:36.251124 TX Vref Scan disable
5219 22:14:36.251208 == TX Byte 0 ==
5220 22:14:36.257622 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5221 22:14:36.260892 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5222 22:14:36.260976 == TX Byte 1 ==
5223 22:14:36.267572 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5224 22:14:36.270603 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5225 22:14:36.270688 ==
5226 22:14:36.273931 Dram Type= 6, Freq= 0, CH_0, rank 0
5227 22:14:36.277578 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5228 22:14:36.277663 ==
5229 22:14:36.277730
5230 22:14:36.280509
5231 22:14:36.280592 TX Vref Scan disable
5232 22:14:36.284087 == TX Byte 0 ==
5233 22:14:36.287334 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5234 22:14:36.290936 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5235 22:14:36.293768 == TX Byte 1 ==
5236 22:14:36.297355 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5237 22:14:36.303627 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5238 22:14:36.303712
5239 22:14:36.303779 [DATLAT]
5240 22:14:36.303839 Freq=933, CH0 RK0
5241 22:14:36.303898
5242 22:14:36.307261 DATLAT Default: 0xd
5243 22:14:36.307344 0, 0xFFFF, sum = 0
5244 22:14:36.310247 1, 0xFFFF, sum = 0
5245 22:14:36.310331 2, 0xFFFF, sum = 0
5246 22:14:36.313676 3, 0xFFFF, sum = 0
5247 22:14:36.317456 4, 0xFFFF, sum = 0
5248 22:14:36.317541 5, 0xFFFF, sum = 0
5249 22:14:36.320728 6, 0xFFFF, sum = 0
5250 22:14:36.320836 7, 0xFFFF, sum = 0
5251 22:14:36.323648 8, 0xFFFF, sum = 0
5252 22:14:36.323732 9, 0xFFFF, sum = 0
5253 22:14:36.326649 10, 0x0, sum = 1
5254 22:14:36.326733 11, 0x0, sum = 2
5255 22:14:36.330132 12, 0x0, sum = 3
5256 22:14:36.330217 13, 0x0, sum = 4
5257 22:14:36.330284 best_step = 11
5258 22:14:36.333331
5259 22:14:36.333414 ==
5260 22:14:36.336696 Dram Type= 6, Freq= 0, CH_0, rank 0
5261 22:14:36.340384 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5262 22:14:36.340468 ==
5263 22:14:36.340534 RX Vref Scan: 1
5264 22:14:36.340594
5265 22:14:36.343125 RX Vref 0 -> 0, step: 1
5266 22:14:36.343209
5267 22:14:36.346587 RX Delay -53 -> 252, step: 4
5268 22:14:36.346671
5269 22:14:36.349748 Set Vref, RX VrefLevel [Byte0]: 58
5270 22:14:36.353275 [Byte1]: 49
5271 22:14:36.356577
5272 22:14:36.356660 Final RX Vref Byte 0 = 58 to rank0
5273 22:14:36.359856 Final RX Vref Byte 1 = 49 to rank0
5274 22:14:36.363237 Final RX Vref Byte 0 = 58 to rank1
5275 22:14:36.366577 Final RX Vref Byte 1 = 49 to rank1==
5276 22:14:36.369703 Dram Type= 6, Freq= 0, CH_0, rank 0
5277 22:14:36.376175 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5278 22:14:36.376262 ==
5279 22:14:36.376329 DQS Delay:
5280 22:14:36.379810 DQS0 = 0, DQS1 = 0
5281 22:14:36.379895 DQM Delay:
5282 22:14:36.379962 DQM0 = 106, DQM1 = 91
5283 22:14:36.382648 DQ Delay:
5284 22:14:36.386118 DQ0 =106, DQ1 =106, DQ2 =104, DQ3 =106
5285 22:14:36.389294 DQ4 =106, DQ5 =98, DQ6 =116, DQ7 =112
5286 22:14:36.392464 DQ8 =88, DQ9 =76, DQ10 =92, DQ11 =90
5287 22:14:36.396199 DQ12 =94, DQ13 =92, DQ14 =102, DQ15 =98
5288 22:14:36.396283
5289 22:14:36.396350
5290 22:14:36.402316 [DQSOSCAuto] RK0, (LSB)MR18= 0x2521, (MSB)MR19= 0x505, tDQSOscB0 = 411 ps tDQSOscB1 = 410 ps
5291 22:14:36.405826 CH0 RK0: MR19=505, MR18=2521
5292 22:14:36.412252 CH0_RK0: MR19=0x505, MR18=0x2521, DQSOSC=410, MR23=63, INC=64, DEC=42
5293 22:14:36.412338
5294 22:14:36.415598 ----->DramcWriteLeveling(PI) begin...
5295 22:14:36.415684 ==
5296 22:14:36.418927 Dram Type= 6, Freq= 0, CH_0, rank 1
5297 22:14:36.422882 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5298 22:14:36.425530 ==
5299 22:14:36.425614 Write leveling (Byte 0): 32 => 32
5300 22:14:36.429224 Write leveling (Byte 1): 31 => 31
5301 22:14:36.432190 DramcWriteLeveling(PI) end<-----
5302 22:14:36.432274
5303 22:14:36.432340 ==
5304 22:14:36.435802 Dram Type= 6, Freq= 0, CH_0, rank 1
5305 22:14:36.442271 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5306 22:14:36.442356 ==
5307 22:14:36.442423 [Gating] SW mode calibration
5308 22:14:36.452082 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5309 22:14:36.455776 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5310 22:14:36.461969 0 14 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5311 22:14:36.465285 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5312 22:14:36.468896 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5313 22:14:36.475196 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5314 22:14:36.478523 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5315 22:14:36.482189 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5316 22:14:36.488340 0 14 24 | B1->B0 | 3434 3232 | 0 1 | (0 0) (1 1)
5317 22:14:36.492011 0 14 28 | B1->B0 | 2e2e 2525 | 0 0 | (0 0) (0 0)
5318 22:14:36.495206 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5319 22:14:36.498393 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5320 22:14:36.504943 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5321 22:14:36.508376 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5322 22:14:36.511963 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5323 22:14:36.518348 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5324 22:14:36.521603 0 15 24 | B1->B0 | 2525 2c2c | 0 0 | (0 0) (0 0)
5325 22:14:36.524955 0 15 28 | B1->B0 | 3939 4242 | 0 1 | (0 0) (0 0)
5326 22:14:36.531943 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5327 22:14:36.534984 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5328 22:14:36.538583 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5329 22:14:36.544723 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5330 22:14:36.548354 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5331 22:14:36.551417 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5332 22:14:36.558384 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5333 22:14:36.561123 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5334 22:14:36.564438 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5335 22:14:36.571400 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5336 22:14:36.574728 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5337 22:14:36.577716 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5338 22:14:36.584626 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5339 22:14:36.588131 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5340 22:14:36.591049 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5341 22:14:36.597858 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5342 22:14:36.600873 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5343 22:14:36.604266 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5344 22:14:36.611131 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5345 22:14:36.614264 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5346 22:14:36.617492 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5347 22:14:36.624211 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5348 22:14:36.627432 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5349 22:14:36.630770 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5350 22:14:36.633971 Total UI for P1: 0, mck2ui 16
5351 22:14:36.637095 best dqsien dly found for B0: ( 1, 2, 24)
5352 22:14:36.640349 Total UI for P1: 0, mck2ui 16
5353 22:14:36.643921 best dqsien dly found for B1: ( 1, 2, 26)
5354 22:14:36.647064 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5355 22:14:36.650391 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5356 22:14:36.650467
5357 22:14:36.657056 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5358 22:14:36.660250 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5359 22:14:36.664365 [Gating] SW calibration Done
5360 22:14:36.664452 ==
5361 22:14:36.667551 Dram Type= 6, Freq= 0, CH_0, rank 1
5362 22:14:36.670294 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5363 22:14:36.670382 ==
5364 22:14:36.670484 RX Vref Scan: 0
5365 22:14:36.670575
5366 22:14:36.673513 RX Vref 0 -> 0, step: 1
5367 22:14:36.673601
5368 22:14:36.676971 RX Delay -80 -> 252, step: 8
5369 22:14:36.680155 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5370 22:14:36.683452 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5371 22:14:36.690445 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5372 22:14:36.693304 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5373 22:14:36.696824 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5374 22:14:36.700083 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5375 22:14:36.703400 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5376 22:14:36.706496 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5377 22:14:36.713187 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5378 22:14:36.716539 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5379 22:14:36.719727 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5380 22:14:36.723370 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5381 22:14:36.726549 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5382 22:14:36.732938 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5383 22:14:36.736552 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5384 22:14:36.740134 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5385 22:14:36.740228 ==
5386 22:14:36.743298 Dram Type= 6, Freq= 0, CH_0, rank 1
5387 22:14:36.746370 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5388 22:14:36.746446 ==
5389 22:14:36.749317 DQS Delay:
5390 22:14:36.749389 DQS0 = 0, DQS1 = 0
5391 22:14:36.749450 DQM Delay:
5392 22:14:36.752637 DQM0 = 104, DQM1 = 90
5393 22:14:36.752737 DQ Delay:
5394 22:14:36.755943 DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =99
5395 22:14:36.759714 DQ4 =107, DQ5 =95, DQ6 =115, DQ7 =111
5396 22:14:36.762787 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =83
5397 22:14:36.766219 DQ12 =95, DQ13 =91, DQ14 =99, DQ15 =99
5398 22:14:36.766303
5399 22:14:36.766369
5400 22:14:36.769587 ==
5401 22:14:36.772614 Dram Type= 6, Freq= 0, CH_0, rank 1
5402 22:14:36.776166 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5403 22:14:36.776251 ==
5404 22:14:36.776318
5405 22:14:36.776378
5406 22:14:36.779332 TX Vref Scan disable
5407 22:14:36.779416 == TX Byte 0 ==
5408 22:14:36.785843 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5409 22:14:36.789259 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5410 22:14:36.789345 == TX Byte 1 ==
5411 22:14:36.795775 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5412 22:14:36.799263 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5413 22:14:36.799348 ==
5414 22:14:36.802515 Dram Type= 6, Freq= 0, CH_0, rank 1
5415 22:14:36.805893 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5416 22:14:36.805979 ==
5417 22:14:36.806046
5418 22:14:36.806106
5419 22:14:36.809201 TX Vref Scan disable
5420 22:14:36.812214 == TX Byte 0 ==
5421 22:14:36.815749 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5422 22:14:36.819170 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5423 22:14:36.822046 == TX Byte 1 ==
5424 22:14:36.825285 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5425 22:14:36.828734 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5426 22:14:36.828832
5427 22:14:36.832385 [DATLAT]
5428 22:14:36.832470 Freq=933, CH0 RK1
5429 22:14:36.832538
5430 22:14:36.835274 DATLAT Default: 0xb
5431 22:14:36.835358 0, 0xFFFF, sum = 0
5432 22:14:36.838762 1, 0xFFFF, sum = 0
5433 22:14:36.838848 2, 0xFFFF, sum = 0
5434 22:14:36.841763 3, 0xFFFF, sum = 0
5435 22:14:36.841849 4, 0xFFFF, sum = 0
5436 22:14:36.845215 5, 0xFFFF, sum = 0
5437 22:14:36.845301 6, 0xFFFF, sum = 0
5438 22:14:36.848634 7, 0xFFFF, sum = 0
5439 22:14:36.848719 8, 0xFFFF, sum = 0
5440 22:14:36.852319 9, 0xFFFF, sum = 0
5441 22:14:36.852404 10, 0x0, sum = 1
5442 22:14:36.855058 11, 0x0, sum = 2
5443 22:14:36.855144 12, 0x0, sum = 3
5444 22:14:36.858366 13, 0x0, sum = 4
5445 22:14:36.858451 best_step = 11
5446 22:14:36.858518
5447 22:14:36.858578 ==
5448 22:14:36.861863 Dram Type= 6, Freq= 0, CH_0, rank 1
5449 22:14:36.868190 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5450 22:14:36.868275 ==
5451 22:14:36.868343 RX Vref Scan: 0
5452 22:14:36.868403
5453 22:14:36.871582 RX Vref 0 -> 0, step: 1
5454 22:14:36.871667
5455 22:14:36.874915 RX Delay -53 -> 252, step: 4
5456 22:14:36.878167 iDelay=199, Bit 0, Center 102 (15 ~ 190) 176
5457 22:14:36.885236 iDelay=199, Bit 1, Center 106 (19 ~ 194) 176
5458 22:14:36.888351 iDelay=199, Bit 2, Center 100 (15 ~ 186) 172
5459 22:14:36.891628 iDelay=199, Bit 3, Center 100 (19 ~ 182) 164
5460 22:14:36.894588 iDelay=199, Bit 4, Center 104 (19 ~ 190) 172
5461 22:14:36.897889 iDelay=199, Bit 5, Center 98 (11 ~ 186) 176
5462 22:14:36.904691 iDelay=199, Bit 6, Center 112 (27 ~ 198) 172
5463 22:14:36.907861 iDelay=199, Bit 7, Center 110 (23 ~ 198) 176
5464 22:14:36.910936 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5465 22:14:36.914803 iDelay=199, Bit 9, Center 80 (-1 ~ 162) 164
5466 22:14:36.917788 iDelay=199, Bit 10, Center 94 (11 ~ 178) 168
5467 22:14:36.924589 iDelay=199, Bit 11, Center 92 (11 ~ 174) 164
5468 22:14:36.927796 iDelay=199, Bit 12, Center 96 (11 ~ 182) 172
5469 22:14:36.931003 iDelay=199, Bit 13, Center 94 (11 ~ 178) 168
5470 22:14:36.934268 iDelay=199, Bit 14, Center 100 (15 ~ 186) 172
5471 22:14:36.937443 iDelay=199, Bit 15, Center 98 (15 ~ 182) 168
5472 22:14:36.937527 ==
5473 22:14:36.940658 Dram Type= 6, Freq= 0, CH_0, rank 1
5474 22:14:36.947290 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5475 22:14:36.947375 ==
5476 22:14:36.947442 DQS Delay:
5477 22:14:36.951161 DQS0 = 0, DQS1 = 0
5478 22:14:36.951245 DQM Delay:
5479 22:14:36.954522 DQM0 = 104, DQM1 = 92
5480 22:14:36.954606 DQ Delay:
5481 22:14:36.957607 DQ0 =102, DQ1 =106, DQ2 =100, DQ3 =100
5482 22:14:36.960960 DQ4 =104, DQ5 =98, DQ6 =112, DQ7 =110
5483 22:14:36.963800 DQ8 =84, DQ9 =80, DQ10 =94, DQ11 =92
5484 22:14:36.967260 DQ12 =96, DQ13 =94, DQ14 =100, DQ15 =98
5485 22:14:36.967371
5486 22:14:36.967448
5487 22:14:36.977076 [DQSOSCAuto] RK1, (LSB)MR18= 0x2708, (MSB)MR19= 0x505, tDQSOscB0 = 419 ps tDQSOscB1 = 409 ps
5488 22:14:36.977164 CH0 RK1: MR19=505, MR18=2708
5489 22:14:36.983660 CH0_RK1: MR19=0x505, MR18=0x2708, DQSOSC=409, MR23=63, INC=64, DEC=43
5490 22:14:36.987535 [RxdqsGatingPostProcess] freq 933
5491 22:14:36.993528 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5492 22:14:36.997062 best DQS0 dly(2T, 0.5T) = (0, 10)
5493 22:14:37.000357 best DQS1 dly(2T, 0.5T) = (0, 10)
5494 22:14:37.003585 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5495 22:14:37.006938 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5496 22:14:37.007024 best DQS0 dly(2T, 0.5T) = (0, 10)
5497 22:14:37.010218 best DQS1 dly(2T, 0.5T) = (0, 10)
5498 22:14:37.013578 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5499 22:14:37.017062 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5500 22:14:37.020215 Pre-setting of DQS Precalculation
5501 22:14:37.026928 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5502 22:14:37.027013 ==
5503 22:14:37.030055 Dram Type= 6, Freq= 0, CH_1, rank 0
5504 22:14:37.033297 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5505 22:14:37.033382 ==
5506 22:14:37.039933 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5507 22:14:37.046785 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5508 22:14:37.049775 [CA 0] Center 37 (7~68) winsize 62
5509 22:14:37.052931 [CA 1] Center 37 (7~68) winsize 62
5510 22:14:37.056176 [CA 2] Center 36 (6~66) winsize 61
5511 22:14:37.060191 [CA 3] Center 34 (4~65) winsize 62
5512 22:14:37.062862 [CA 4] Center 35 (5~66) winsize 62
5513 22:14:37.066547 [CA 5] Center 34 (4~65) winsize 62
5514 22:14:37.066632
5515 22:14:37.069664 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5516 22:14:37.069749
5517 22:14:37.072756 [CATrainingPosCal] consider 1 rank data
5518 22:14:37.075931 u2DelayCellTimex100 = 270/100 ps
5519 22:14:37.079763 CA0 delay=37 (7~68),Diff = 3 PI (18 cell)
5520 22:14:37.082619 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5521 22:14:37.086159 CA2 delay=36 (6~66),Diff = 2 PI (12 cell)
5522 22:14:37.089206 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5523 22:14:37.092695 CA4 delay=35 (5~66),Diff = 1 PI (6 cell)
5524 22:14:37.095963 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
5525 22:14:37.099030
5526 22:14:37.102410 CA PerBit enable=1, Macro0, CA PI delay=34
5527 22:14:37.102496
5528 22:14:37.105913 [CBTSetCACLKResult] CA Dly = 34
5529 22:14:37.105999 CS Dly: 6 (0~37)
5530 22:14:37.106068 ==
5531 22:14:37.109030 Dram Type= 6, Freq= 0, CH_1, rank 1
5532 22:14:37.112446 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5533 22:14:37.112532 ==
5534 22:14:37.118942 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5535 22:14:37.125650 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5536 22:14:37.129594 [CA 0] Center 38 (8~69) winsize 62
5537 22:14:37.132293 [CA 1] Center 38 (8~69) winsize 62
5538 22:14:37.135505 [CA 2] Center 36 (6~66) winsize 61
5539 22:14:37.139005 [CA 3] Center 35 (6~65) winsize 60
5540 22:14:37.142298 [CA 4] Center 35 (6~65) winsize 60
5541 22:14:37.145944 [CA 5] Center 35 (5~65) winsize 61
5542 22:14:37.146030
5543 22:14:37.149169 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5544 22:14:37.149254
5545 22:14:37.152343 [CATrainingPosCal] consider 2 rank data
5546 22:14:37.155692 u2DelayCellTimex100 = 270/100 ps
5547 22:14:37.158675 CA0 delay=38 (8~68),Diff = 3 PI (18 cell)
5548 22:14:37.162156 CA1 delay=38 (8~68),Diff = 3 PI (18 cell)
5549 22:14:37.165421 CA2 delay=36 (6~66),Diff = 1 PI (6 cell)
5550 22:14:37.168711 CA3 delay=35 (6~65),Diff = 0 PI (0 cell)
5551 22:14:37.175390 CA4 delay=35 (6~65),Diff = 0 PI (0 cell)
5552 22:14:37.178475 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
5553 22:14:37.178561
5554 22:14:37.181771 CA PerBit enable=1, Macro0, CA PI delay=35
5555 22:14:37.181856
5556 22:14:37.185206 [CBTSetCACLKResult] CA Dly = 35
5557 22:14:37.185294 CS Dly: 7 (0~39)
5558 22:14:37.185362
5559 22:14:37.188514 ----->DramcWriteLeveling(PI) begin...
5560 22:14:37.188601 ==
5561 22:14:37.191799 Dram Type= 6, Freq= 0, CH_1, rank 0
5562 22:14:37.199037 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5563 22:14:37.199123 ==
5564 22:14:37.202291 Write leveling (Byte 0): 25 => 25
5565 22:14:37.205334 Write leveling (Byte 1): 27 => 27
5566 22:14:37.205420 DramcWriteLeveling(PI) end<-----
5567 22:14:37.205487
5568 22:14:37.208651 ==
5569 22:14:37.211400 Dram Type= 6, Freq= 0, CH_1, rank 0
5570 22:14:37.214787 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5571 22:14:37.214873 ==
5572 22:14:37.218289 [Gating] SW mode calibration
5573 22:14:37.224939 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5574 22:14:37.228228 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5575 22:14:37.234838 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5576 22:14:37.238045 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5577 22:14:37.241373 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5578 22:14:37.247959 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5579 22:14:37.251491 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5580 22:14:37.254495 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5581 22:14:37.261341 0 14 24 | B1->B0 | 3434 3434 | 0 0 | (0 0) (0 1)
5582 22:14:37.264682 0 14 28 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
5583 22:14:37.267826 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5584 22:14:37.274361 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5585 22:14:37.277762 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5586 22:14:37.281643 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5587 22:14:37.287453 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5588 22:14:37.290907 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5589 22:14:37.294367 0 15 24 | B1->B0 | 2d2d 2d2d | 0 1 | (0 0) (0 0)
5590 22:14:37.300719 0 15 28 | B1->B0 | 3f3f 4646 | 1 0 | (0 0) (0 0)
5591 22:14:37.304398 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5592 22:14:37.307209 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5593 22:14:37.313777 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5594 22:14:37.317142 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5595 22:14:37.320716 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5596 22:14:37.327094 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5597 22:14:37.330697 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5598 22:14:37.333601 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5599 22:14:37.340552 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5600 22:14:37.343589 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5601 22:14:37.346978 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5602 22:14:37.353737 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5603 22:14:37.356726 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5604 22:14:37.360189 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5605 22:14:37.366864 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5606 22:14:37.370098 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5607 22:14:37.373549 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5608 22:14:37.380093 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5609 22:14:37.383376 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5610 22:14:37.386538 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5611 22:14:37.393179 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5612 22:14:37.396200 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5613 22:14:37.399561 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5614 22:14:37.406249 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5615 22:14:37.406334 Total UI for P1: 0, mck2ui 16
5616 22:14:37.412921 best dqsien dly found for B0: ( 1, 2, 24)
5617 22:14:37.413006 Total UI for P1: 0, mck2ui 16
5618 22:14:37.419289 best dqsien dly found for B1: ( 1, 2, 26)
5619 22:14:37.422619 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5620 22:14:37.426152 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5621 22:14:37.426236
5622 22:14:37.429807 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5623 22:14:37.432951 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5624 22:14:37.435826 [Gating] SW calibration Done
5625 22:14:37.435910 ==
5626 22:14:37.439622 Dram Type= 6, Freq= 0, CH_1, rank 0
5627 22:14:37.442678 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5628 22:14:37.442763 ==
5629 22:14:37.446475 RX Vref Scan: 0
5630 22:14:37.446559
5631 22:14:37.446626 RX Vref 0 -> 0, step: 1
5632 22:14:37.446686
5633 22:14:37.449566 RX Delay -80 -> 252, step: 8
5634 22:14:37.456545 iDelay=208, Bit 0, Center 111 (24 ~ 199) 176
5635 22:14:37.459666 iDelay=208, Bit 1, Center 99 (16 ~ 183) 168
5636 22:14:37.462287 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5637 22:14:37.466232 iDelay=208, Bit 3, Center 103 (16 ~ 191) 176
5638 22:14:37.468998 iDelay=208, Bit 4, Center 103 (16 ~ 191) 176
5639 22:14:37.472502 iDelay=208, Bit 5, Center 111 (24 ~ 199) 176
5640 22:14:37.479262 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5641 22:14:37.482242 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5642 22:14:37.485940 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5643 22:14:37.489068 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5644 22:14:37.492269 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5645 22:14:37.495746 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5646 22:14:37.502277 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5647 22:14:37.506260 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5648 22:14:37.508921 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5649 22:14:37.512418 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5650 22:14:37.512501 ==
5651 22:14:37.515566 Dram Type= 6, Freq= 0, CH_1, rank 0
5652 22:14:37.522167 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5653 22:14:37.522255 ==
5654 22:14:37.522323 DQS Delay:
5655 22:14:37.522383 DQS0 = 0, DQS1 = 0
5656 22:14:37.526057 DQM Delay:
5657 22:14:37.526140 DQM0 = 104, DQM1 = 95
5658 22:14:37.528715 DQ Delay:
5659 22:14:37.532199 DQ0 =111, DQ1 =99, DQ2 =91, DQ3 =103
5660 22:14:37.535396 DQ4 =103, DQ5 =111, DQ6 =115, DQ7 =99
5661 22:14:37.538635 DQ8 =83, DQ9 =83, DQ10 =99, DQ11 =91
5662 22:14:37.542243 DQ12 =103, DQ13 =103, DQ14 =99, DQ15 =103
5663 22:14:37.542327
5664 22:14:37.542393
5665 22:14:37.542453 ==
5666 22:14:37.545443 Dram Type= 6, Freq= 0, CH_1, rank 0
5667 22:14:37.548728 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5668 22:14:37.548828 ==
5669 22:14:37.548895
5670 22:14:37.548955
5671 22:14:37.551966 TX Vref Scan disable
5672 22:14:37.555467 == TX Byte 0 ==
5673 22:14:37.558620 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5674 22:14:37.562328 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5675 22:14:37.565701 == TX Byte 1 ==
5676 22:14:37.568760 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5677 22:14:37.571874 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5678 22:14:37.571958 ==
5679 22:14:37.575123 Dram Type= 6, Freq= 0, CH_1, rank 0
5680 22:14:37.579037 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5681 22:14:37.581723 ==
5682 22:14:37.581832
5683 22:14:37.581929
5684 22:14:37.582000 TX Vref Scan disable
5685 22:14:37.585533 == TX Byte 0 ==
5686 22:14:37.588660 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5687 22:14:37.595330 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5688 22:14:37.595413 == TX Byte 1 ==
5689 22:14:37.599079 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5690 22:14:37.605343 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5691 22:14:37.605425
5692 22:14:37.605490 [DATLAT]
5693 22:14:37.605550 Freq=933, CH1 RK0
5694 22:14:37.605607
5695 22:14:37.608719 DATLAT Default: 0xd
5696 22:14:37.608833 0, 0xFFFF, sum = 0
5697 22:14:37.611774 1, 0xFFFF, sum = 0
5698 22:14:37.615247 2, 0xFFFF, sum = 0
5699 22:14:37.615330 3, 0xFFFF, sum = 0
5700 22:14:37.618678 4, 0xFFFF, sum = 0
5701 22:14:37.618761 5, 0xFFFF, sum = 0
5702 22:14:37.622124 6, 0xFFFF, sum = 0
5703 22:14:37.622207 7, 0xFFFF, sum = 0
5704 22:14:37.624886 8, 0xFFFF, sum = 0
5705 22:14:37.624969 9, 0xFFFF, sum = 0
5706 22:14:37.628688 10, 0x0, sum = 1
5707 22:14:37.628814 11, 0x0, sum = 2
5708 22:14:37.631835 12, 0x0, sum = 3
5709 22:14:37.631917 13, 0x0, sum = 4
5710 22:14:37.632022 best_step = 11
5711 22:14:37.634919
5712 22:14:37.635000 ==
5713 22:14:37.638393 Dram Type= 6, Freq= 0, CH_1, rank 0
5714 22:14:37.641494 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5715 22:14:37.641577 ==
5716 22:14:37.641699 RX Vref Scan: 1
5717 22:14:37.641775
5718 22:14:37.645433 RX Vref 0 -> 0, step: 1
5719 22:14:37.645514
5720 22:14:37.648346 RX Delay -53 -> 252, step: 4
5721 22:14:37.648428
5722 22:14:37.651412 Set Vref, RX VrefLevel [Byte0]: 53
5723 22:14:37.655414 [Byte1]: 53
5724 22:14:37.655510
5725 22:14:37.658114 Final RX Vref Byte 0 = 53 to rank0
5726 22:14:37.661679 Final RX Vref Byte 1 = 53 to rank0
5727 22:14:37.664889 Final RX Vref Byte 0 = 53 to rank1
5728 22:14:37.668177 Final RX Vref Byte 1 = 53 to rank1==
5729 22:14:37.671329 Dram Type= 6, Freq= 0, CH_1, rank 0
5730 22:14:37.674706 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5731 22:14:37.677892 ==
5732 22:14:37.677974 DQS Delay:
5733 22:14:37.678040 DQS0 = 0, DQS1 = 0
5734 22:14:37.681411 DQM Delay:
5735 22:14:37.681493 DQM0 = 104, DQM1 = 97
5736 22:14:37.684958 DQ Delay:
5737 22:14:37.687898 DQ0 =108, DQ1 =98, DQ2 =96, DQ3 =102
5738 22:14:37.691539 DQ4 =104, DQ5 =112, DQ6 =114, DQ7 =102
5739 22:14:37.694787 DQ8 =86, DQ9 =84, DQ10 =100, DQ11 =92
5740 22:14:37.697848 DQ12 =106, DQ13 =104, DQ14 =104, DQ15 =104
5741 22:14:37.697929
5742 22:14:37.697994
5743 22:14:37.704455 [DQSOSCAuto] RK0, (LSB)MR18= 0x162f, (MSB)MR19= 0x505, tDQSOscB0 = 407 ps tDQSOscB1 = 414 ps
5744 22:14:37.707907 CH1 RK0: MR19=505, MR18=162F
5745 22:14:37.714667 CH1_RK0: MR19=0x505, MR18=0x162F, DQSOSC=407, MR23=63, INC=65, DEC=43
5746 22:14:37.714752
5747 22:14:37.717659 ----->DramcWriteLeveling(PI) begin...
5748 22:14:37.717744 ==
5749 22:14:37.720916 Dram Type= 6, Freq= 0, CH_1, rank 1
5750 22:14:37.724341 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5751 22:14:37.724425 ==
5752 22:14:37.728177 Write leveling (Byte 0): 28 => 28
5753 22:14:37.730918 Write leveling (Byte 1): 28 => 28
5754 22:14:37.734145 DramcWriteLeveling(PI) end<-----
5755 22:14:37.734229
5756 22:14:37.734296 ==
5757 22:14:37.737645 Dram Type= 6, Freq= 0, CH_1, rank 1
5758 22:14:37.744085 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5759 22:14:37.744170 ==
5760 22:14:37.744237 [Gating] SW mode calibration
5761 22:14:37.754143 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5762 22:14:37.757300 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5763 22:14:37.764094 0 14 0 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
5764 22:14:37.767461 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5765 22:14:37.770295 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5766 22:14:37.777632 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5767 22:14:37.780571 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5768 22:14:37.784099 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5769 22:14:37.790580 0 14 24 | B1->B0 | 3030 3434 | 0 0 | (0 0) (0 0)
5770 22:14:37.793407 0 14 28 | B1->B0 | 2323 2828 | 0 0 | (0 0) (1 1)
5771 22:14:37.796841 0 15 0 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
5772 22:14:37.803309 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5773 22:14:37.806802 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5774 22:14:37.809915 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5775 22:14:37.816498 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5776 22:14:37.819989 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5777 22:14:37.823345 0 15 24 | B1->B0 | 2a2a 2626 | 0 0 | (0 0) (0 0)
5778 22:14:37.829692 0 15 28 | B1->B0 | 4141 3b3b | 0 0 | (1 1) (0 0)
5779 22:14:37.833502 1 0 0 | B1->B0 | 4646 4545 | 0 0 | (0 0) (1 1)
5780 22:14:37.836561 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5781 22:14:37.843686 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5782 22:14:37.846646 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5783 22:14:37.849476 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5784 22:14:37.856153 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5785 22:14:37.859480 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5786 22:14:37.862751 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5787 22:14:37.869613 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5788 22:14:37.873329 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5789 22:14:37.876307 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5790 22:14:37.879291 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5791 22:14:37.886217 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5792 22:14:37.889291 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5793 22:14:37.892580 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5794 22:14:37.899483 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5795 22:14:37.902719 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5796 22:14:37.905982 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5797 22:14:37.912484 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5798 22:14:37.915966 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5799 22:14:37.919241 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5800 22:14:37.925843 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5801 22:14:37.929007 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5802 22:14:37.932241 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5803 22:14:37.935504 Total UI for P1: 0, mck2ui 16
5804 22:14:37.938933 best dqsien dly found for B1: ( 1, 2, 24)
5805 22:14:37.945627 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5806 22:14:37.949332 Total UI for P1: 0, mck2ui 16
5807 22:14:37.952202 best dqsien dly found for B0: ( 1, 2, 26)
5808 22:14:37.955634 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5809 22:14:37.958900 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5810 22:14:37.958985
5811 22:14:37.962348 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5812 22:14:37.965420 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5813 22:14:37.968917 [Gating] SW calibration Done
5814 22:14:37.969001 ==
5815 22:14:37.972361 Dram Type= 6, Freq= 0, CH_1, rank 1
5816 22:14:37.975508 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5817 22:14:37.975622 ==
5818 22:14:37.978882 RX Vref Scan: 0
5819 22:14:37.978989
5820 22:14:37.979083 RX Vref 0 -> 0, step: 1
5821 22:14:37.982084
5822 22:14:37.982200 RX Delay -80 -> 252, step: 8
5823 22:14:37.988880 iDelay=200, Bit 0, Center 107 (24 ~ 191) 168
5824 22:14:37.992247 iDelay=200, Bit 1, Center 95 (8 ~ 183) 176
5825 22:14:37.995154 iDelay=200, Bit 2, Center 87 (0 ~ 175) 176
5826 22:14:37.998977 iDelay=200, Bit 3, Center 99 (8 ~ 191) 184
5827 22:14:38.002070 iDelay=200, Bit 4, Center 103 (16 ~ 191) 176
5828 22:14:38.005716 iDelay=200, Bit 5, Center 111 (24 ~ 199) 176
5829 22:14:38.011766 iDelay=200, Bit 6, Center 111 (24 ~ 199) 176
5830 22:14:38.015121 iDelay=200, Bit 7, Center 99 (8 ~ 191) 184
5831 22:14:38.018621 iDelay=200, Bit 8, Center 83 (-8 ~ 175) 184
5832 22:14:38.021981 iDelay=200, Bit 9, Center 87 (0 ~ 175) 176
5833 22:14:38.025175 iDelay=200, Bit 10, Center 95 (0 ~ 191) 192
5834 22:14:38.028433 iDelay=200, Bit 11, Center 87 (-8 ~ 183) 192
5835 22:14:38.035415 iDelay=200, Bit 12, Center 103 (8 ~ 199) 192
5836 22:14:38.038246 iDelay=200, Bit 13, Center 103 (8 ~ 199) 192
5837 22:14:38.041851 iDelay=200, Bit 14, Center 103 (8 ~ 199) 192
5838 22:14:38.045011 iDelay=200, Bit 15, Center 103 (8 ~ 199) 192
5839 22:14:38.045121 ==
5840 22:14:38.048913 Dram Type= 6, Freq= 0, CH_1, rank 1
5841 22:14:38.055494 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5842 22:14:38.055607 ==
5843 22:14:38.055704 DQS Delay:
5844 22:14:38.055797 DQS0 = 0, DQS1 = 0
5845 22:14:38.058331 DQM Delay:
5846 22:14:38.058454 DQM0 = 101, DQM1 = 95
5847 22:14:38.061541 DQ Delay:
5848 22:14:38.064593 DQ0 =107, DQ1 =95, DQ2 =87, DQ3 =99
5849 22:14:38.068038 DQ4 =103, DQ5 =111, DQ6 =111, DQ7 =99
5850 22:14:38.071336 DQ8 =83, DQ9 =87, DQ10 =95, DQ11 =87
5851 22:14:38.074559 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =103
5852 22:14:38.074649
5853 22:14:38.074716
5854 22:14:38.074776 ==
5855 22:14:38.078083 Dram Type= 6, Freq= 0, CH_1, rank 1
5856 22:14:38.081432 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5857 22:14:38.081518 ==
5858 22:14:38.081585
5859 22:14:38.081645
5860 22:14:38.084625 TX Vref Scan disable
5861 22:14:38.087946 == TX Byte 0 ==
5862 22:14:38.091784 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5863 22:14:38.094451 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5864 22:14:38.098072 == TX Byte 1 ==
5865 22:14:38.101131 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5866 22:14:38.104409 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5867 22:14:38.104493 ==
5868 22:14:38.108031 Dram Type= 6, Freq= 0, CH_1, rank 1
5869 22:14:38.114175 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5870 22:14:38.114259 ==
5871 22:14:38.114326
5872 22:14:38.114387
5873 22:14:38.114447 TX Vref Scan disable
5874 22:14:38.118446 == TX Byte 0 ==
5875 22:14:38.121467 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5876 22:14:38.128092 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5877 22:14:38.128175 == TX Byte 1 ==
5878 22:14:38.131491 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5879 22:14:38.138551 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5880 22:14:38.138635
5881 22:14:38.138702 [DATLAT]
5882 22:14:38.138762 Freq=933, CH1 RK1
5883 22:14:38.138822
5884 22:14:38.142024 DATLAT Default: 0xb
5885 22:14:38.142109 0, 0xFFFF, sum = 0
5886 22:14:38.144643 1, 0xFFFF, sum = 0
5887 22:14:38.144744 2, 0xFFFF, sum = 0
5888 22:14:38.148282 3, 0xFFFF, sum = 0
5889 22:14:38.151558 4, 0xFFFF, sum = 0
5890 22:14:38.151642 5, 0xFFFF, sum = 0
5891 22:14:38.154648 6, 0xFFFF, sum = 0
5892 22:14:38.154732 7, 0xFFFF, sum = 0
5893 22:14:38.157839 8, 0xFFFF, sum = 0
5894 22:14:38.157925 9, 0xFFFF, sum = 0
5895 22:14:38.161512 10, 0x0, sum = 1
5896 22:14:38.161604 11, 0x0, sum = 2
5897 22:14:38.164891 12, 0x0, sum = 3
5898 22:14:38.165004 13, 0x0, sum = 4
5899 22:14:38.165101 best_step = 11
5900 22:14:38.165191
5901 22:14:38.167664 ==
5902 22:14:38.171313 Dram Type= 6, Freq= 0, CH_1, rank 1
5903 22:14:38.175009 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5904 22:14:38.175095 ==
5905 22:14:38.175162 RX Vref Scan: 0
5906 22:14:38.175223
5907 22:14:38.177891 RX Vref 0 -> 0, step: 1
5908 22:14:38.177975
5909 22:14:38.181129 RX Delay -53 -> 252, step: 4
5910 22:14:38.187586 iDelay=199, Bit 0, Center 108 (31 ~ 186) 156
5911 22:14:38.190833 iDelay=199, Bit 1, Center 98 (19 ~ 178) 160
5912 22:14:38.194892 iDelay=199, Bit 2, Center 94 (15 ~ 174) 160
5913 22:14:38.197600 iDelay=199, Bit 3, Center 104 (23 ~ 186) 164
5914 22:14:38.200956 iDelay=199, Bit 4, Center 106 (23 ~ 190) 168
5915 22:14:38.204773 iDelay=199, Bit 5, Center 116 (35 ~ 198) 164
5916 22:14:38.210582 iDelay=199, Bit 6, Center 114 (35 ~ 194) 160
5917 22:14:38.214166 iDelay=199, Bit 7, Center 102 (23 ~ 182) 160
5918 22:14:38.217474 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5919 22:14:38.220760 iDelay=199, Bit 9, Center 88 (3 ~ 174) 172
5920 22:14:38.224027 iDelay=199, Bit 10, Center 98 (15 ~ 182) 168
5921 22:14:38.230961 iDelay=199, Bit 11, Center 90 (3 ~ 178) 176
5922 22:14:38.233683 iDelay=199, Bit 12, Center 108 (23 ~ 194) 172
5923 22:14:38.237479 iDelay=199, Bit 13, Center 102 (15 ~ 190) 176
5924 22:14:38.240437 iDelay=199, Bit 14, Center 106 (23 ~ 190) 168
5925 22:14:38.244047 iDelay=199, Bit 15, Center 108 (23 ~ 194) 172
5926 22:14:38.246858 ==
5927 22:14:38.250790 Dram Type= 6, Freq= 0, CH_1, rank 1
5928 22:14:38.253686 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5929 22:14:38.253772 ==
5930 22:14:38.253839 DQS Delay:
5931 22:14:38.257097 DQS0 = 0, DQS1 = 0
5932 22:14:38.257182 DQM Delay:
5933 22:14:38.260541 DQM0 = 105, DQM1 = 98
5934 22:14:38.260624 DQ Delay:
5935 22:14:38.263523 DQ0 =108, DQ1 =98, DQ2 =94, DQ3 =104
5936 22:14:38.266901 DQ4 =106, DQ5 =116, DQ6 =114, DQ7 =102
5937 22:14:38.270750 DQ8 =84, DQ9 =88, DQ10 =98, DQ11 =90
5938 22:14:38.273601 DQ12 =108, DQ13 =102, DQ14 =106, DQ15 =108
5939 22:14:38.273685
5940 22:14:38.273752
5941 22:14:38.283494 [DQSOSCAuto] RK1, (LSB)MR18= 0x2300, (MSB)MR19= 0x505, tDQSOscB0 = 422 ps tDQSOscB1 = 410 ps
5942 22:14:38.283581 CH1 RK1: MR19=505, MR18=2300
5943 22:14:38.290015 CH1_RK1: MR19=0x505, MR18=0x2300, DQSOSC=410, MR23=63, INC=64, DEC=42
5944 22:14:38.293941 [RxdqsGatingPostProcess] freq 933
5945 22:14:38.299966 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5946 22:14:38.303352 best DQS0 dly(2T, 0.5T) = (0, 10)
5947 22:14:38.307035 best DQS1 dly(2T, 0.5T) = (0, 10)
5948 22:14:38.309947 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5949 22:14:38.313291 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5950 22:14:38.317013 best DQS0 dly(2T, 0.5T) = (0, 10)
5951 22:14:38.317099 best DQS1 dly(2T, 0.5T) = (0, 10)
5952 22:14:38.320063 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5953 22:14:38.323427 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5954 22:14:38.326577 Pre-setting of DQS Precalculation
5955 22:14:38.333010 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5956 22:14:38.339559 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5957 22:14:38.346291 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5958 22:14:38.346379
5959 22:14:38.346446
5960 22:14:38.349943 [Calibration Summary] 1866 Mbps
5961 22:14:38.353126 CH 0, Rank 0
5962 22:14:38.353209 SW Impedance : PASS
5963 22:14:38.355965 DUTY Scan : NO K
5964 22:14:38.359584 ZQ Calibration : PASS
5965 22:14:38.359669 Jitter Meter : NO K
5966 22:14:38.362732 CBT Training : PASS
5967 22:14:38.366384 Write leveling : PASS
5968 22:14:38.366468 RX DQS gating : PASS
5969 22:14:38.369167 RX DQ/DQS(RDDQC) : PASS
5970 22:14:38.369251 TX DQ/DQS : PASS
5971 22:14:38.372756 RX DATLAT : PASS
5972 22:14:38.376535 RX DQ/DQS(Engine): PASS
5973 22:14:38.376657 TX OE : NO K
5974 22:14:38.379554 All Pass.
5975 22:14:38.379637
5976 22:14:38.379703 CH 0, Rank 1
5977 22:14:38.382515 SW Impedance : PASS
5978 22:14:38.382604 DUTY Scan : NO K
5979 22:14:38.385783 ZQ Calibration : PASS
5980 22:14:38.389348 Jitter Meter : NO K
5981 22:14:38.389432 CBT Training : PASS
5982 22:14:38.392452 Write leveling : PASS
5983 22:14:38.395720 RX DQS gating : PASS
5984 22:14:38.395804 RX DQ/DQS(RDDQC) : PASS
5985 22:14:38.399191 TX DQ/DQS : PASS
5986 22:14:38.402512 RX DATLAT : PASS
5987 22:14:38.402598 RX DQ/DQS(Engine): PASS
5988 22:14:38.405871 TX OE : NO K
5989 22:14:38.405955 All Pass.
5990 22:14:38.406021
5991 22:14:38.409389 CH 1, Rank 0
5992 22:14:38.409472 SW Impedance : PASS
5993 22:14:38.413100 DUTY Scan : NO K
5994 22:14:38.415795 ZQ Calibration : PASS
5995 22:14:38.415877 Jitter Meter : NO K
5996 22:14:38.419007 CBT Training : PASS
5997 22:14:38.422129 Write leveling : PASS
5998 22:14:38.422213 RX DQS gating : PASS
5999 22:14:38.425700 RX DQ/DQS(RDDQC) : PASS
6000 22:14:38.428733 TX DQ/DQS : PASS
6001 22:14:38.428871 RX DATLAT : PASS
6002 22:14:38.432262 RX DQ/DQS(Engine): PASS
6003 22:14:38.432345 TX OE : NO K
6004 22:14:38.435515 All Pass.
6005 22:14:38.435598
6006 22:14:38.435665 CH 1, Rank 1
6007 22:14:38.439124 SW Impedance : PASS
6008 22:14:38.439208 DUTY Scan : NO K
6009 22:14:38.442093 ZQ Calibration : PASS
6010 22:14:38.445584 Jitter Meter : NO K
6011 22:14:38.445668 CBT Training : PASS
6012 22:14:38.449065 Write leveling : PASS
6013 22:14:38.452166 RX DQS gating : PASS
6014 22:14:38.452251 RX DQ/DQS(RDDQC) : PASS
6015 22:14:38.455609 TX DQ/DQS : PASS
6016 22:14:38.458615 RX DATLAT : PASS
6017 22:14:38.458699 RX DQ/DQS(Engine): PASS
6018 22:14:38.462199 TX OE : NO K
6019 22:14:38.462283 All Pass.
6020 22:14:38.462350
6021 22:14:38.465317 DramC Write-DBI off
6022 22:14:38.468667 PER_BANK_REFRESH: Hybrid Mode
6023 22:14:38.468751 TX_TRACKING: ON
6024 22:14:38.478506 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6025 22:14:38.481893 [FAST_K] Save calibration result to emmc
6026 22:14:38.485495 dramc_set_vcore_voltage set vcore to 650000
6027 22:14:38.488619 Read voltage for 400, 6
6028 22:14:38.488729 Vio18 = 0
6029 22:14:38.488847 Vcore = 650000
6030 22:14:38.491687 Vdram = 0
6031 22:14:38.491771 Vddq = 0
6032 22:14:38.491838 Vmddr = 0
6033 22:14:38.498538 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6034 22:14:38.501659 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6035 22:14:38.504692 MEM_TYPE=3, freq_sel=20
6036 22:14:38.507990 sv_algorithm_assistance_LP4_800
6037 22:14:38.511355 ============ PULL DRAM RESETB DOWN ============
6038 22:14:38.518014 ========== PULL DRAM RESETB DOWN end =========
6039 22:14:38.521251 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6040 22:14:38.524745 ===================================
6041 22:14:38.527760 LPDDR4 DRAM CONFIGURATION
6042 22:14:38.531194 ===================================
6043 22:14:38.531279 EX_ROW_EN[0] = 0x0
6044 22:14:38.534314 EX_ROW_EN[1] = 0x0
6045 22:14:38.534399 LP4Y_EN = 0x0
6046 22:14:38.537715 WORK_FSP = 0x0
6047 22:14:38.537799 WL = 0x2
6048 22:14:38.541104 RL = 0x2
6049 22:14:38.541188 BL = 0x2
6050 22:14:38.544468 RPST = 0x0
6051 22:14:38.547483 RD_PRE = 0x0
6052 22:14:38.547568 WR_PRE = 0x1
6053 22:14:38.550957 WR_PST = 0x0
6054 22:14:38.551041 DBI_WR = 0x0
6055 22:14:38.554395 DBI_RD = 0x0
6056 22:14:38.554479 OTF = 0x1
6057 22:14:38.557729 ===================================
6058 22:14:38.561369 ===================================
6059 22:14:38.564337 ANA top config
6060 22:14:38.567686 ===================================
6061 22:14:38.567771 DLL_ASYNC_EN = 0
6062 22:14:38.570764 ALL_SLAVE_EN = 1
6063 22:14:38.573882 NEW_RANK_MODE = 1
6064 22:14:38.577218 DLL_IDLE_MODE = 1
6065 22:14:38.577304 LP45_APHY_COMB_EN = 1
6066 22:14:38.580856 TX_ODT_DIS = 1
6067 22:14:38.583817 NEW_8X_MODE = 1
6068 22:14:38.587005 ===================================
6069 22:14:38.590830 ===================================
6070 22:14:38.593815 data_rate = 800
6071 22:14:38.597275 CKR = 1
6072 22:14:38.600225 DQ_P2S_RATIO = 4
6073 22:14:38.603526 ===================================
6074 22:14:38.603611 CA_P2S_RATIO = 4
6075 22:14:38.606879 DQ_CA_OPEN = 0
6076 22:14:38.610216 DQ_SEMI_OPEN = 1
6077 22:14:38.613608 CA_SEMI_OPEN = 1
6078 22:14:38.616850 CA_FULL_RATE = 0
6079 22:14:38.619955 DQ_CKDIV4_EN = 0
6080 22:14:38.620039 CA_CKDIV4_EN = 1
6081 22:14:38.623262 CA_PREDIV_EN = 0
6082 22:14:38.626866 PH8_DLY = 0
6083 22:14:38.629916 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6084 22:14:38.633270 DQ_AAMCK_DIV = 0
6085 22:14:38.637049 CA_AAMCK_DIV = 0
6086 22:14:38.637133 CA_ADMCK_DIV = 4
6087 22:14:38.639908 DQ_TRACK_CA_EN = 0
6088 22:14:38.643217 CA_PICK = 800
6089 22:14:38.646562 CA_MCKIO = 400
6090 22:14:38.650399 MCKIO_SEMI = 400
6091 22:14:38.652976 PLL_FREQ = 3016
6092 22:14:38.656510 DQ_UI_PI_RATIO = 32
6093 22:14:38.659422 CA_UI_PI_RATIO = 32
6094 22:14:38.662932 ===================================
6095 22:14:38.666276 ===================================
6096 22:14:38.666361 memory_type:LPDDR4
6097 22:14:38.669733 GP_NUM : 10
6098 22:14:38.672776 SRAM_EN : 1
6099 22:14:38.672903 MD32_EN : 0
6100 22:14:38.676109 ===================================
6101 22:14:38.679278 [ANA_INIT] >>>>>>>>>>>>>>
6102 22:14:38.682637 <<<<<< [CONFIGURE PHASE]: ANA_TX
6103 22:14:38.686153 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6104 22:14:38.689879 ===================================
6105 22:14:38.692641 data_rate = 800,PCW = 0X7400
6106 22:14:38.696096 ===================================
6107 22:14:38.699312 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6108 22:14:38.702732 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6109 22:14:38.715610 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6110 22:14:38.718974 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6111 22:14:38.722521 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6112 22:14:38.726187 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6113 22:14:38.728947 [ANA_INIT] flow start
6114 22:14:38.732655 [ANA_INIT] PLL >>>>>>>>
6115 22:14:38.732741 [ANA_INIT] PLL <<<<<<<<
6116 22:14:38.735634 [ANA_INIT] MIDPI >>>>>>>>
6117 22:14:38.739105 [ANA_INIT] MIDPI <<<<<<<<
6118 22:14:38.739191 [ANA_INIT] DLL >>>>>>>>
6119 22:14:38.743251 [ANA_INIT] flow end
6120 22:14:38.745553 ============ LP4 DIFF to SE enter ============
6121 22:14:38.748714 ============ LP4 DIFF to SE exit ============
6122 22:14:38.752339 [ANA_INIT] <<<<<<<<<<<<<
6123 22:14:38.755293 [Flow] Enable top DCM control >>>>>
6124 22:14:38.758770 [Flow] Enable top DCM control <<<<<
6125 22:14:38.761869 Enable DLL master slave shuffle
6126 22:14:38.769025 ==============================================================
6127 22:14:38.769112 Gating Mode config
6128 22:14:38.775060 ==============================================================
6129 22:14:38.778463 Config description:
6130 22:14:38.785441 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6131 22:14:38.791686 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6132 22:14:38.798400 SELPH_MODE 0: By rank 1: By Phase
6133 22:14:38.805461 ==============================================================
6134 22:14:38.805590 GAT_TRACK_EN = 0
6135 22:14:38.808379 RX_GATING_MODE = 2
6136 22:14:38.811984 RX_GATING_TRACK_MODE = 2
6137 22:14:38.814986 SELPH_MODE = 1
6138 22:14:38.818507 PICG_EARLY_EN = 1
6139 22:14:38.821758 VALID_LAT_VALUE = 1
6140 22:14:38.828481 ==============================================================
6141 22:14:38.831475 Enter into Gating configuration >>>>
6142 22:14:38.834691 Exit from Gating configuration <<<<
6143 22:14:38.838141 Enter into DVFS_PRE_config >>>>>
6144 22:14:38.847904 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6145 22:14:38.851349 Exit from DVFS_PRE_config <<<<<
6146 22:14:38.854970 Enter into PICG configuration >>>>
6147 22:14:38.858027 Exit from PICG configuration <<<<
6148 22:14:38.861170 [RX_INPUT] configuration >>>>>
6149 22:14:38.861276 [RX_INPUT] configuration <<<<<
6150 22:14:38.868050 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6151 22:14:38.874698 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6152 22:14:38.881050 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6153 22:14:38.884186 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6154 22:14:38.890746 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6155 22:14:38.897358 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6156 22:14:38.900692 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6157 22:14:38.907435 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6158 22:14:38.910509 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6159 22:14:38.914244 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6160 22:14:38.917302 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6161 22:14:38.923929 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6162 22:14:38.926996 ===================================
6163 22:14:38.930328 LPDDR4 DRAM CONFIGURATION
6164 22:14:38.933477 ===================================
6165 22:14:38.933581 EX_ROW_EN[0] = 0x0
6166 22:14:38.936978 EX_ROW_EN[1] = 0x0
6167 22:14:38.937063 LP4Y_EN = 0x0
6168 22:14:38.940229 WORK_FSP = 0x0
6169 22:14:38.940314 WL = 0x2
6170 22:14:38.943305 RL = 0x2
6171 22:14:38.943391 BL = 0x2
6172 22:14:38.946668 RPST = 0x0
6173 22:14:38.946753 RD_PRE = 0x0
6174 22:14:38.950225 WR_PRE = 0x1
6175 22:14:38.950310 WR_PST = 0x0
6176 22:14:38.953442 DBI_WR = 0x0
6177 22:14:38.956614 DBI_RD = 0x0
6178 22:14:38.956699 OTF = 0x1
6179 22:14:38.960111 ===================================
6180 22:14:38.963030 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6181 22:14:38.966375 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6182 22:14:38.973022 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6183 22:14:38.976277 ===================================
6184 22:14:38.979775 LPDDR4 DRAM CONFIGURATION
6185 22:14:38.983084 ===================================
6186 22:14:38.983168 EX_ROW_EN[0] = 0x10
6187 22:14:38.986326 EX_ROW_EN[1] = 0x0
6188 22:14:38.986410 LP4Y_EN = 0x0
6189 22:14:38.989840 WORK_FSP = 0x0
6190 22:14:38.989923 WL = 0x2
6191 22:14:38.992716 RL = 0x2
6192 22:14:38.992836 BL = 0x2
6193 22:14:38.996354 RPST = 0x0
6194 22:14:38.996438 RD_PRE = 0x0
6195 22:14:38.999715 WR_PRE = 0x1
6196 22:14:38.999798 WR_PST = 0x0
6197 22:14:39.002755 DBI_WR = 0x0
6198 22:14:39.006321 DBI_RD = 0x0
6199 22:14:39.006404 OTF = 0x1
6200 22:14:39.009832 ===================================
6201 22:14:39.015948 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6202 22:14:39.019333 nWR fixed to 30
6203 22:14:39.022990 [ModeRegInit_LP4] CH0 RK0
6204 22:14:39.023074 [ModeRegInit_LP4] CH0 RK1
6205 22:14:39.026641 [ModeRegInit_LP4] CH1 RK0
6206 22:14:39.029231 [ModeRegInit_LP4] CH1 RK1
6207 22:14:39.029314 match AC timing 19
6208 22:14:39.035836 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6209 22:14:39.039364 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6210 22:14:39.042597 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6211 22:14:39.049192 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6212 22:14:39.052899 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6213 22:14:39.052983 ==
6214 22:14:39.056129 Dram Type= 6, Freq= 0, CH_0, rank 0
6215 22:14:39.059258 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6216 22:14:39.059343 ==
6217 22:14:39.065810 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6218 22:14:39.072555 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6219 22:14:39.075801 [CA 0] Center 36 (8~64) winsize 57
6220 22:14:39.079311 [CA 1] Center 36 (8~64) winsize 57
6221 22:14:39.082530 [CA 2] Center 36 (8~64) winsize 57
6222 22:14:39.085510 [CA 3] Center 36 (8~64) winsize 57
6223 22:14:39.090032 [CA 4] Center 36 (8~64) winsize 57
6224 22:14:39.090117 [CA 5] Center 36 (8~64) winsize 57
6225 22:14:39.092197
6226 22:14:39.095536 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6227 22:14:39.095620
6228 22:14:39.099082 [CATrainingPosCal] consider 1 rank data
6229 22:14:39.102285 u2DelayCellTimex100 = 270/100 ps
6230 22:14:39.105701 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6231 22:14:39.109061 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6232 22:14:39.113104 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6233 22:14:39.115450 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6234 22:14:39.118937 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6235 22:14:39.122609 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6236 22:14:39.122693
6237 22:14:39.125462 CA PerBit enable=1, Macro0, CA PI delay=36
6238 22:14:39.125546
6239 22:14:39.128976 [CBTSetCACLKResult] CA Dly = 36
6240 22:14:39.132194 CS Dly: 1 (0~32)
6241 22:14:39.132277 ==
6242 22:14:39.135585 Dram Type= 6, Freq= 0, CH_0, rank 1
6243 22:14:39.138705 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6244 22:14:39.138789 ==
6245 22:14:39.145568 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6246 22:14:39.152123 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6247 22:14:39.152208 [CA 0] Center 36 (8~64) winsize 57
6248 22:14:39.155481 [CA 1] Center 36 (8~64) winsize 57
6249 22:14:39.158806 [CA 2] Center 36 (8~64) winsize 57
6250 22:14:39.162260 [CA 3] Center 36 (8~64) winsize 57
6251 22:14:39.165417 [CA 4] Center 36 (8~64) winsize 57
6252 22:14:39.168780 [CA 5] Center 36 (8~64) winsize 57
6253 22:14:39.168864
6254 22:14:39.172110 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6255 22:14:39.172193
6256 22:14:39.175833 [CATrainingPosCal] consider 2 rank data
6257 22:14:39.178715 u2DelayCellTimex100 = 270/100 ps
6258 22:14:39.181783 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6259 22:14:39.188628 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6260 22:14:39.191877 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6261 22:14:39.195066 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6262 22:14:39.198289 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6263 22:14:39.201576 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6264 22:14:39.201660
6265 22:14:39.204901 CA PerBit enable=1, Macro0, CA PI delay=36
6266 22:14:39.204985
6267 22:14:39.208082 [CBTSetCACLKResult] CA Dly = 36
6268 22:14:39.211603 CS Dly: 1 (0~32)
6269 22:14:39.211690
6270 22:14:39.214741 ----->DramcWriteLeveling(PI) begin...
6271 22:14:39.214829 ==
6272 22:14:39.218538 Dram Type= 6, Freq= 0, CH_0, rank 0
6273 22:14:39.221321 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6274 22:14:39.221409 ==
6275 22:14:39.225031 Write leveling (Byte 0): 40 => 8
6276 22:14:39.228847 Write leveling (Byte 1): 32 => 0
6277 22:14:39.231427 DramcWriteLeveling(PI) end<-----
6278 22:14:39.231514
6279 22:14:39.231601 ==
6280 22:14:39.235635 Dram Type= 6, Freq= 0, CH_0, rank 0
6281 22:14:39.238163 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6282 22:14:39.238250 ==
6283 22:14:39.241344 [Gating] SW mode calibration
6284 22:14:39.248048 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6285 22:14:39.254575 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6286 22:14:39.258123 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6287 22:14:39.261208 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6288 22:14:39.267976 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6289 22:14:39.271080 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6290 22:14:39.274193 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6291 22:14:39.281005 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6292 22:14:39.284588 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6293 22:14:39.287675 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6294 22:14:39.293984 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6295 22:14:39.294074 Total UI for P1: 0, mck2ui 16
6296 22:14:39.300824 best dqsien dly found for B0: ( 0, 14, 24)
6297 22:14:39.300910 Total UI for P1: 0, mck2ui 16
6298 22:14:39.307322 best dqsien dly found for B1: ( 0, 14, 24)
6299 22:14:39.311161 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6300 22:14:39.314097 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6301 22:14:39.314182
6302 22:14:39.317360 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6303 22:14:39.320962 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6304 22:14:39.323914 [Gating] SW calibration Done
6305 22:14:39.324004 ==
6306 22:14:39.327124 Dram Type= 6, Freq= 0, CH_0, rank 0
6307 22:14:39.330793 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6308 22:14:39.330880 ==
6309 22:14:39.333837 RX Vref Scan: 0
6310 22:14:39.333942
6311 22:14:39.334020 RX Vref 0 -> 0, step: 1
6312 22:14:39.334080
6313 22:14:39.337222 RX Delay -410 -> 252, step: 16
6314 22:14:39.343979 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6315 22:14:39.347224 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6316 22:14:39.350734 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6317 22:14:39.353857 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6318 22:14:39.360572 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6319 22:14:39.363661 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6320 22:14:39.366915 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6321 22:14:39.370219 iDelay=230, Bit 7, Center -11 (-250 ~ 229) 480
6322 22:14:39.376716 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6323 22:14:39.380248 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6324 22:14:39.384190 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6325 22:14:39.387162 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6326 22:14:39.393341 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6327 22:14:39.396719 iDelay=230, Bit 13, Center -27 (-266 ~ 213) 480
6328 22:14:39.399936 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6329 22:14:39.406749 iDelay=230, Bit 15, Center -27 (-266 ~ 213) 480
6330 22:14:39.406834 ==
6331 22:14:39.409924 Dram Type= 6, Freq= 0, CH_0, rank 0
6332 22:14:39.413457 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6333 22:14:39.413541 ==
6334 22:14:39.413607 DQS Delay:
6335 22:14:39.416386 DQS0 = 27, DQS1 = 43
6336 22:14:39.416468 DQM Delay:
6337 22:14:39.420065 DQM0 = 11, DQM1 = 13
6338 22:14:39.420147 DQ Delay:
6339 22:14:39.423463 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6340 22:14:39.426627 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6341 22:14:39.429670 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6342 22:14:39.432983 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6343 22:14:39.433103
6344 22:14:39.433192
6345 22:14:39.433272 ==
6346 22:14:39.436507 Dram Type= 6, Freq= 0, CH_0, rank 0
6347 22:14:39.439547 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6348 22:14:39.439630 ==
6349 22:14:39.439697
6350 22:14:39.439757
6351 22:14:39.442833 TX Vref Scan disable
6352 22:14:39.446022 == TX Byte 0 ==
6353 22:14:39.449260 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6354 22:14:39.452780 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6355 22:14:39.456077 == TX Byte 1 ==
6356 22:14:39.459165 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6357 22:14:39.462778 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6358 22:14:39.462861 ==
6359 22:14:39.466094 Dram Type= 6, Freq= 0, CH_0, rank 0
6360 22:14:39.469256 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6361 22:14:39.469339 ==
6362 22:14:39.472798
6363 22:14:39.472899
6364 22:14:39.472965 TX Vref Scan disable
6365 22:14:39.475766 == TX Byte 0 ==
6366 22:14:39.478993 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6367 22:14:39.482578 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6368 22:14:39.485924 == TX Byte 1 ==
6369 22:14:39.489113 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6370 22:14:39.492331 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6371 22:14:39.492416
6372 22:14:39.495616 [DATLAT]
6373 22:14:39.495701 Freq=400, CH0 RK0
6374 22:14:39.495804
6375 22:14:39.499196 DATLAT Default: 0xf
6376 22:14:39.499280 0, 0xFFFF, sum = 0
6377 22:14:39.502483 1, 0xFFFF, sum = 0
6378 22:14:39.502569 2, 0xFFFF, sum = 0
6379 22:14:39.505971 3, 0xFFFF, sum = 0
6380 22:14:39.506057 4, 0xFFFF, sum = 0
6381 22:14:39.509045 5, 0xFFFF, sum = 0
6382 22:14:39.509134 6, 0xFFFF, sum = 0
6383 22:14:39.512045 7, 0xFFFF, sum = 0
6384 22:14:39.512130 8, 0xFFFF, sum = 0
6385 22:14:39.516726 9, 0xFFFF, sum = 0
6386 22:14:39.516829 10, 0xFFFF, sum = 0
6387 22:14:39.519019 11, 0xFFFF, sum = 0
6388 22:14:39.521949 12, 0xFFFF, sum = 0
6389 22:14:39.522034 13, 0x0, sum = 1
6390 22:14:39.522102 14, 0x0, sum = 2
6391 22:14:39.525197 15, 0x0, sum = 3
6392 22:14:39.525287 16, 0x0, sum = 4
6393 22:14:39.528677 best_step = 14
6394 22:14:39.528796
6395 22:14:39.528888 ==
6396 22:14:39.531752 Dram Type= 6, Freq= 0, CH_0, rank 0
6397 22:14:39.535180 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6398 22:14:39.535266 ==
6399 22:14:39.538436 RX Vref Scan: 1
6400 22:14:39.538520
6401 22:14:39.538586 RX Vref 0 -> 0, step: 1
6402 22:14:39.542348
6403 22:14:39.542432 RX Delay -327 -> 252, step: 8
6404 22:14:39.542500
6405 22:14:39.545073 Set Vref, RX VrefLevel [Byte0]: 58
6406 22:14:39.548244 [Byte1]: 49
6407 22:14:39.553328
6408 22:14:39.553412 Final RX Vref Byte 0 = 58 to rank0
6409 22:14:39.556691 Final RX Vref Byte 1 = 49 to rank0
6410 22:14:39.559998 Final RX Vref Byte 0 = 58 to rank1
6411 22:14:39.563535 Final RX Vref Byte 1 = 49 to rank1==
6412 22:14:39.566865 Dram Type= 6, Freq= 0, CH_0, rank 0
6413 22:14:39.573386 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6414 22:14:39.573473 ==
6415 22:14:39.573541 DQS Delay:
6416 22:14:39.576579 DQS0 = 28, DQS1 = 48
6417 22:14:39.576664 DQM Delay:
6418 22:14:39.576732 DQM0 = 11, DQM1 = 15
6419 22:14:39.579932 DQ Delay:
6420 22:14:39.583037 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =8
6421 22:14:39.583123 DQ4 =8, DQ5 =0, DQ6 =24, DQ7 =20
6422 22:14:39.587024 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6423 22:14:39.589998 DQ12 =20, DQ13 =16, DQ14 =28, DQ15 =24
6424 22:14:39.590083
6425 22:14:39.592875
6426 22:14:39.599681 [DQSOSCAuto] RK0, (LSB)MR18= 0xb3aa, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 387 ps
6427 22:14:39.602845 CH0 RK0: MR19=C0C, MR18=B3AA
6428 22:14:39.609443 CH0_RK0: MR19=0xC0C, MR18=0xB3AA, DQSOSC=387, MR23=63, INC=394, DEC=262
6429 22:14:39.609528 ==
6430 22:14:39.612872 Dram Type= 6, Freq= 0, CH_0, rank 1
6431 22:14:39.616078 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6432 22:14:39.616163 ==
6433 22:14:39.619527 [Gating] SW mode calibration
6434 22:14:39.626183 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6435 22:14:39.633055 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6436 22:14:39.636150 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6437 22:14:39.639250 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6438 22:14:39.645902 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6439 22:14:39.649330 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6440 22:14:39.652652 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6441 22:14:39.659140 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6442 22:14:39.662654 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6443 22:14:39.665947 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6444 22:14:39.672582 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6445 22:14:39.672695 Total UI for P1: 0, mck2ui 16
6446 22:14:39.679036 best dqsien dly found for B0: ( 0, 14, 24)
6447 22:14:39.679124 Total UI for P1: 0, mck2ui 16
6448 22:14:39.682440 best dqsien dly found for B1: ( 0, 14, 24)
6449 22:14:39.689281 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6450 22:14:39.692687 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6451 22:14:39.692805
6452 22:14:39.695610 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6453 22:14:39.699983 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6454 22:14:39.702365 [Gating] SW calibration Done
6455 22:14:39.702450 ==
6456 22:14:39.705343 Dram Type= 6, Freq= 0, CH_0, rank 1
6457 22:14:39.708581 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6458 22:14:39.708697 ==
6459 22:14:39.711804 RX Vref Scan: 0
6460 22:14:39.711894
6461 22:14:39.711994 RX Vref 0 -> 0, step: 1
6462 22:14:39.712080
6463 22:14:39.715436 RX Delay -410 -> 252, step: 16
6464 22:14:39.722098 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6465 22:14:39.725066 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6466 22:14:39.728385 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6467 22:14:39.731594 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6468 22:14:39.738312 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6469 22:14:39.742269 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6470 22:14:39.744738 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6471 22:14:39.748250 iDelay=230, Bit 7, Center -11 (-250 ~ 229) 480
6472 22:14:39.754816 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6473 22:14:39.758077 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6474 22:14:39.761445 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6475 22:14:39.764676 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6476 22:14:39.771084 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6477 22:14:39.774333 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6478 22:14:39.778050 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6479 22:14:39.784690 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6480 22:14:39.784796 ==
6481 22:14:39.787769 Dram Type= 6, Freq= 0, CH_0, rank 1
6482 22:14:39.790954 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6483 22:14:39.791043 ==
6484 22:14:39.791111 DQS Delay:
6485 22:14:39.794540 DQS0 = 27, DQS1 = 43
6486 22:14:39.794654 DQM Delay:
6487 22:14:39.797782 DQM0 = 10, DQM1 = 16
6488 22:14:39.797866 DQ Delay:
6489 22:14:39.801141 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6490 22:14:39.804399 DQ4 =8, DQ5 =0, DQ6 =24, DQ7 =16
6491 22:14:39.807677 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =16
6492 22:14:39.810588 DQ12 =16, DQ13 =24, DQ14 =24, DQ15 =24
6493 22:14:39.810680
6494 22:14:39.810751
6495 22:14:39.810811 ==
6496 22:14:39.813948 Dram Type= 6, Freq= 0, CH_0, rank 1
6497 22:14:39.817183 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6498 22:14:39.817305 ==
6499 22:14:39.817416
6500 22:14:39.817523
6501 22:14:39.820503 TX Vref Scan disable
6502 22:14:39.823942 == TX Byte 0 ==
6503 22:14:39.827472 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6504 22:14:39.830656 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6505 22:14:39.830771 == TX Byte 1 ==
6506 22:14:39.837454 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6507 22:14:39.840380 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6508 22:14:39.840493 ==
6509 22:14:39.843724 Dram Type= 6, Freq= 0, CH_0, rank 1
6510 22:14:39.847343 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6511 22:14:39.847457 ==
6512 22:14:39.847562
6513 22:14:39.850625
6514 22:14:39.850737 TX Vref Scan disable
6515 22:14:39.854025 == TX Byte 0 ==
6516 22:14:39.857178 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6517 22:14:39.860509 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6518 22:14:39.863735 == TX Byte 1 ==
6519 22:14:39.866972 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6520 22:14:39.870200 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6521 22:14:39.870313
6522 22:14:39.870416 [DATLAT]
6523 22:14:39.873733 Freq=400, CH0 RK1
6524 22:14:39.873846
6525 22:14:39.873948 DATLAT Default: 0xe
6526 22:14:39.876723 0, 0xFFFF, sum = 0
6527 22:14:39.880339 1, 0xFFFF, sum = 0
6528 22:14:39.880454 2, 0xFFFF, sum = 0
6529 22:14:39.883644 3, 0xFFFF, sum = 0
6530 22:14:39.883760 4, 0xFFFF, sum = 0
6531 22:14:39.886797 5, 0xFFFF, sum = 0
6532 22:14:39.886910 6, 0xFFFF, sum = 0
6533 22:14:39.890653 7, 0xFFFF, sum = 0
6534 22:14:39.890767 8, 0xFFFF, sum = 0
6535 22:14:39.893490 9, 0xFFFF, sum = 0
6536 22:14:39.893603 10, 0xFFFF, sum = 0
6537 22:14:39.896741 11, 0xFFFF, sum = 0
6538 22:14:39.896904 12, 0xFFFF, sum = 0
6539 22:14:39.900114 13, 0x0, sum = 1
6540 22:14:39.900229 14, 0x0, sum = 2
6541 22:14:39.904330 15, 0x0, sum = 3
6542 22:14:39.904444 16, 0x0, sum = 4
6543 22:14:39.906901 best_step = 14
6544 22:14:39.907011
6545 22:14:39.907112 ==
6546 22:14:39.909941 Dram Type= 6, Freq= 0, CH_0, rank 1
6547 22:14:39.913693 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6548 22:14:39.913804 ==
6549 22:14:39.916735 RX Vref Scan: 0
6550 22:14:39.916851
6551 22:14:39.916954 RX Vref 0 -> 0, step: 1
6552 22:14:39.917055
6553 22:14:39.919810 RX Delay -327 -> 252, step: 8
6554 22:14:39.927419 iDelay=217, Bit 0, Center -20 (-247 ~ 208) 456
6555 22:14:39.930587 iDelay=217, Bit 1, Center -16 (-239 ~ 208) 448
6556 22:14:39.934029 iDelay=217, Bit 2, Center -24 (-247 ~ 200) 448
6557 22:14:39.940511 iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448
6558 22:14:39.943729 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6559 22:14:39.947088 iDelay=217, Bit 5, Center -28 (-255 ~ 200) 456
6560 22:14:39.950655 iDelay=217, Bit 6, Center -12 (-239 ~ 216) 456
6561 22:14:39.953850 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6562 22:14:39.960821 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6563 22:14:39.964207 iDelay=217, Bit 9, Center -44 (-271 ~ 184) 456
6564 22:14:39.967341 iDelay=217, Bit 10, Center -28 (-255 ~ 200) 456
6565 22:14:39.973521 iDelay=217, Bit 11, Center -36 (-263 ~ 192) 456
6566 22:14:39.976505 iDelay=217, Bit 12, Center -24 (-247 ~ 200) 448
6567 22:14:39.979863 iDelay=217, Bit 13, Center -24 (-247 ~ 200) 448
6568 22:14:39.983772 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
6569 22:14:39.989910 iDelay=217, Bit 15, Center -20 (-239 ~ 200) 440
6570 22:14:39.990045 ==
6571 22:14:39.993137 Dram Type= 6, Freq= 0, CH_0, rank 1
6572 22:14:39.997225 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6573 22:14:39.997435 ==
6574 22:14:39.997556 DQS Delay:
6575 22:14:39.999545 DQS0 = 28, DQS1 = 44
6576 22:14:39.999683 DQM Delay:
6577 22:14:40.003348 DQM0 = 9, DQM1 = 15
6578 22:14:40.003460 DQ Delay:
6579 22:14:40.006287 DQ0 =8, DQ1 =12, DQ2 =4, DQ3 =4
6580 22:14:40.010095 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =20
6581 22:14:40.013106 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6582 22:14:40.016382 DQ12 =20, DQ13 =20, DQ14 =28, DQ15 =24
6583 22:14:40.016492
6584 22:14:40.016593
6585 22:14:40.023085 [DQSOSCAuto] RK1, (LSB)MR18= 0xbc6f, (MSB)MR19= 0xc0c, tDQSOscB0 = 395 ps tDQSOscB1 = 386 ps
6586 22:14:40.026507 CH0 RK1: MR19=C0C, MR18=BC6F
6587 22:14:40.032826 CH0_RK1: MR19=0xC0C, MR18=0xBC6F, DQSOSC=386, MR23=63, INC=396, DEC=264
6588 22:14:40.036287 [RxdqsGatingPostProcess] freq 400
6589 22:14:40.042526 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6590 22:14:40.046074 best DQS0 dly(2T, 0.5T) = (0, 10)
6591 22:14:40.049206 best DQS1 dly(2T, 0.5T) = (0, 10)
6592 22:14:40.052416 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6593 22:14:40.055867 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6594 22:14:40.059233 best DQS0 dly(2T, 0.5T) = (0, 10)
6595 22:14:40.059344 best DQS1 dly(2T, 0.5T) = (0, 10)
6596 22:14:40.062442 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6597 22:14:40.066294 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6598 22:14:40.069304 Pre-setting of DQS Precalculation
6599 22:14:40.075657 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6600 22:14:40.075771 ==
6601 22:14:40.079156 Dram Type= 6, Freq= 0, CH_1, rank 0
6602 22:14:40.082529 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6603 22:14:40.082641 ==
6604 22:14:40.088958 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6605 22:14:40.095994 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6606 22:14:40.098857 [CA 0] Center 36 (8~64) winsize 57
6607 22:14:40.101930 [CA 1] Center 36 (8~64) winsize 57
6608 22:14:40.105314 [CA 2] Center 36 (8~64) winsize 57
6609 22:14:40.105423 [CA 3] Center 36 (8~64) winsize 57
6610 22:14:40.108851 [CA 4] Center 36 (8~64) winsize 57
6611 22:14:40.111853 [CA 5] Center 36 (8~64) winsize 57
6612 22:14:40.111964
6613 22:14:40.115376 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6614 22:14:40.118692
6615 22:14:40.121923 [CATrainingPosCal] consider 1 rank data
6616 22:14:40.125060 u2DelayCellTimex100 = 270/100 ps
6617 22:14:40.128674 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6618 22:14:40.131857 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6619 22:14:40.135188 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6620 22:14:40.138921 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6621 22:14:40.141710 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6622 22:14:40.145655 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6623 22:14:40.145766
6624 22:14:40.148533 CA PerBit enable=1, Macro0, CA PI delay=36
6625 22:14:40.148644
6626 22:14:40.151607 [CBTSetCACLKResult] CA Dly = 36
6627 22:14:40.155062 CS Dly: 1 (0~32)
6628 22:14:40.155173 ==
6629 22:14:40.158639 Dram Type= 6, Freq= 0, CH_1, rank 1
6630 22:14:40.161561 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6631 22:14:40.161675 ==
6632 22:14:40.168870 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6633 22:14:40.174751 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6634 22:14:40.174879 [CA 0] Center 36 (8~64) winsize 57
6635 22:14:40.178157 [CA 1] Center 36 (8~64) winsize 57
6636 22:14:40.181584 [CA 2] Center 36 (8~64) winsize 57
6637 22:14:40.184680 [CA 3] Center 36 (8~64) winsize 57
6638 22:14:40.188030 [CA 4] Center 36 (8~64) winsize 57
6639 22:14:40.191178 [CA 5] Center 36 (8~64) winsize 57
6640 22:14:40.191290
6641 22:14:40.194729 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6642 22:14:40.194840
6643 22:14:40.197965 [CATrainingPosCal] consider 2 rank data
6644 22:14:40.201481 u2DelayCellTimex100 = 270/100 ps
6645 22:14:40.204481 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6646 22:14:40.211285 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6647 22:14:40.214505 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6648 22:14:40.218001 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6649 22:14:40.221164 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6650 22:14:40.224346 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6651 22:14:40.224457
6652 22:14:40.227593 CA PerBit enable=1, Macro0, CA PI delay=36
6653 22:14:40.227705
6654 22:14:40.231118 [CBTSetCACLKResult] CA Dly = 36
6655 22:14:40.231228 CS Dly: 1 (0~32)
6656 22:14:40.234642
6657 22:14:40.238087 ----->DramcWriteLeveling(PI) begin...
6658 22:14:40.238199 ==
6659 22:14:40.241410 Dram Type= 6, Freq= 0, CH_1, rank 0
6660 22:14:40.244648 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6661 22:14:40.244760 ==
6662 22:14:40.247577 Write leveling (Byte 0): 40 => 8
6663 22:14:40.250894 Write leveling (Byte 1): 32 => 0
6664 22:14:40.254309 DramcWriteLeveling(PI) end<-----
6665 22:14:40.254419
6666 22:14:40.254521 ==
6667 22:14:40.257849 Dram Type= 6, Freq= 0, CH_1, rank 0
6668 22:14:40.260999 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6669 22:14:40.261110 ==
6670 22:14:40.264374 [Gating] SW mode calibration
6671 22:14:40.270794 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6672 22:14:40.277647 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6673 22:14:40.280747 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6674 22:14:40.284254 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6675 22:14:40.290674 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6676 22:14:40.294568 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6677 22:14:40.297671 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6678 22:14:40.300817 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6679 22:14:40.307408 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6680 22:14:40.310639 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6681 22:14:40.314537 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6682 22:14:40.317350 Total UI for P1: 0, mck2ui 16
6683 22:14:40.320583 best dqsien dly found for B0: ( 0, 14, 24)
6684 22:14:40.323893 Total UI for P1: 0, mck2ui 16
6685 22:14:40.327207 best dqsien dly found for B1: ( 0, 14, 24)
6686 22:14:40.330650 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6687 22:14:40.337118 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6688 22:14:40.337236
6689 22:14:40.340561 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6690 22:14:40.343612 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6691 22:14:40.346956 [Gating] SW calibration Done
6692 22:14:40.347072 ==
6693 22:14:40.350240 Dram Type= 6, Freq= 0, CH_1, rank 0
6694 22:14:40.353826 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6695 22:14:40.353943 ==
6696 22:14:40.357012 RX Vref Scan: 0
6697 22:14:40.357128
6698 22:14:40.357234 RX Vref 0 -> 0, step: 1
6699 22:14:40.357338
6700 22:14:40.360480 RX Delay -410 -> 252, step: 16
6701 22:14:40.363485 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6702 22:14:40.370121 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6703 22:14:40.373447 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6704 22:14:40.376945 iDelay=230, Bit 3, Center -27 (-266 ~ 213) 480
6705 22:14:40.383585 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6706 22:14:40.386722 iDelay=230, Bit 5, Center -11 (-250 ~ 229) 480
6707 22:14:40.389961 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6708 22:14:40.393024 iDelay=230, Bit 7, Center -27 (-266 ~ 213) 480
6709 22:14:40.399824 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6710 22:14:40.402896 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6711 22:14:40.406374 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6712 22:14:40.409552 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6713 22:14:40.416379 iDelay=230, Bit 12, Center -19 (-266 ~ 229) 496
6714 22:14:40.419852 iDelay=230, Bit 13, Center -11 (-250 ~ 229) 480
6715 22:14:40.423249 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6716 22:14:40.426243 iDelay=230, Bit 15, Center -19 (-266 ~ 229) 496
6717 22:14:40.429577 ==
6718 22:14:40.432685 Dram Type= 6, Freq= 0, CH_1, rank 0
6719 22:14:40.435928 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6720 22:14:40.436045 ==
6721 22:14:40.436153 DQS Delay:
6722 22:14:40.439126 DQS0 = 27, DQS1 = 43
6723 22:14:40.439244 DQM Delay:
6724 22:14:40.442791 DQM0 = 5, DQM1 = 16
6725 22:14:40.442907 DQ Delay:
6726 22:14:40.445924 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =0
6727 22:14:40.449794 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6728 22:14:40.452650 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6729 22:14:40.455792 DQ12 =24, DQ13 =32, DQ14 =16, DQ15 =24
6730 22:14:40.455909
6731 22:14:40.456015
6732 22:14:40.456120 ==
6733 22:14:40.459507 Dram Type= 6, Freq= 0, CH_1, rank 0
6734 22:14:40.462789 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6735 22:14:40.462909 ==
6736 22:14:40.463017
6737 22:14:40.463121
6738 22:14:40.466095 TX Vref Scan disable
6739 22:14:40.466211 == TX Byte 0 ==
6740 22:14:40.472336 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6741 22:14:40.476000 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6742 22:14:40.476120 == TX Byte 1 ==
6743 22:14:40.482711 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6744 22:14:40.485647 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6745 22:14:40.485766 ==
6746 22:14:40.489228 Dram Type= 6, Freq= 0, CH_1, rank 0
6747 22:14:40.492232 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6748 22:14:40.492349 ==
6749 22:14:40.492456
6750 22:14:40.492561
6751 22:14:40.495565 TX Vref Scan disable
6752 22:14:40.498797 == TX Byte 0 ==
6753 22:14:40.502004 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6754 22:14:40.505278 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6755 22:14:40.508616 == TX Byte 1 ==
6756 22:14:40.512188 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6757 22:14:40.515254 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6758 22:14:40.515370
6759 22:14:40.515478 [DATLAT]
6760 22:14:40.518678 Freq=400, CH1 RK0
6761 22:14:40.518795
6762 22:14:40.518901 DATLAT Default: 0xf
6763 22:14:40.521879 0, 0xFFFF, sum = 0
6764 22:14:40.525164 1, 0xFFFF, sum = 0
6765 22:14:40.525283 2, 0xFFFF, sum = 0
6766 22:14:40.528599 3, 0xFFFF, sum = 0
6767 22:14:40.528715 4, 0xFFFF, sum = 0
6768 22:14:40.532263 5, 0xFFFF, sum = 0
6769 22:14:40.532378 6, 0xFFFF, sum = 0
6770 22:14:40.534996 7, 0xFFFF, sum = 0
6771 22:14:40.535113 8, 0xFFFF, sum = 0
6772 22:14:40.538747 9, 0xFFFF, sum = 0
6773 22:14:40.538864 10, 0xFFFF, sum = 0
6774 22:14:40.541852 11, 0xFFFF, sum = 0
6775 22:14:40.541969 12, 0xFFFF, sum = 0
6776 22:14:40.545009 13, 0x0, sum = 1
6777 22:14:40.545126 14, 0x0, sum = 2
6778 22:14:40.548626 15, 0x0, sum = 3
6779 22:14:40.548741 16, 0x0, sum = 4
6780 22:14:40.551950 best_step = 14
6781 22:14:40.552065
6782 22:14:40.552171 ==
6783 22:14:40.555053 Dram Type= 6, Freq= 0, CH_1, rank 0
6784 22:14:40.558471 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6785 22:14:40.558589 ==
6786 22:14:40.561935 RX Vref Scan: 1
6787 22:14:40.562050
6788 22:14:40.562156 RX Vref 0 -> 0, step: 1
6789 22:14:40.562260
6790 22:14:40.565174 RX Delay -327 -> 252, step: 8
6791 22:14:40.565290
6792 22:14:40.568347 Set Vref, RX VrefLevel [Byte0]: 53
6793 22:14:40.571635 [Byte1]: 53
6794 22:14:40.576276
6795 22:14:40.576392 Final RX Vref Byte 0 = 53 to rank0
6796 22:14:40.579043 Final RX Vref Byte 1 = 53 to rank0
6797 22:14:40.582343 Final RX Vref Byte 0 = 53 to rank1
6798 22:14:40.586529 Final RX Vref Byte 1 = 53 to rank1==
6799 22:14:40.589208 Dram Type= 6, Freq= 0, CH_1, rank 0
6800 22:14:40.595918 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6801 22:14:40.596036 ==
6802 22:14:40.596142 DQS Delay:
6803 22:14:40.598827 DQS0 = 28, DQS1 = 40
6804 22:14:40.598942 DQM Delay:
6805 22:14:40.599048 DQM0 = 7, DQM1 = 13
6806 22:14:40.602355 DQ Delay:
6807 22:14:40.605511 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =4
6808 22:14:40.605628 DQ4 =4, DQ5 =12, DQ6 =16, DQ7 =4
6809 22:14:40.609001 DQ8 =0, DQ9 =0, DQ10 =20, DQ11 =4
6810 22:14:40.612110 DQ12 =24, DQ13 =20, DQ14 =16, DQ15 =20
6811 22:14:40.612226
6812 22:14:40.615329
6813 22:14:40.622102 [DQSOSCAuto] RK0, (LSB)MR18= 0x98d1, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 390 ps
6814 22:14:40.625686 CH1 RK0: MR19=C0C, MR18=98D1
6815 22:14:40.631932 CH1_RK0: MR19=0xC0C, MR18=0x98D1, DQSOSC=384, MR23=63, INC=400, DEC=267
6816 22:14:40.632048 ==
6817 22:14:40.635126 Dram Type= 6, Freq= 0, CH_1, rank 1
6818 22:14:40.638731 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6819 22:14:40.638850 ==
6820 22:14:40.641952 [Gating] SW mode calibration
6821 22:14:40.648559 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6822 22:14:40.655090 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6823 22:14:40.658313 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6824 22:14:40.661565 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6825 22:14:40.668403 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6826 22:14:40.671381 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6827 22:14:40.674973 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6828 22:14:40.681372 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6829 22:14:40.684628 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6830 22:14:40.688400 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6831 22:14:40.695092 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6832 22:14:40.695210 Total UI for P1: 0, mck2ui 16
6833 22:14:40.701465 best dqsien dly found for B0: ( 0, 14, 24)
6834 22:14:40.701585 Total UI for P1: 0, mck2ui 16
6835 22:14:40.707648 best dqsien dly found for B1: ( 0, 14, 24)
6836 22:14:40.711294 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6837 22:14:40.714334 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6838 22:14:40.714451
6839 22:14:40.717654 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6840 22:14:40.720773 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6841 22:14:40.724239 [Gating] SW calibration Done
6842 22:14:40.724353 ==
6843 22:14:40.727500 Dram Type= 6, Freq= 0, CH_1, rank 1
6844 22:14:40.730872 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6845 22:14:40.730989 ==
6846 22:14:40.733943 RX Vref Scan: 0
6847 22:14:40.734061
6848 22:14:40.737171 RX Vref 0 -> 0, step: 1
6849 22:14:40.737285
6850 22:14:40.737391 RX Delay -410 -> 252, step: 16
6851 22:14:40.743881 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6852 22:14:40.747370 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6853 22:14:40.750439 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6854 22:14:40.753621 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6855 22:14:40.760578 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6856 22:14:40.763686 iDelay=230, Bit 5, Center -11 (-250 ~ 229) 480
6857 22:14:40.767257 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6858 22:14:40.770434 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6859 22:14:40.776962 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6860 22:14:40.780327 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6861 22:14:40.784094 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6862 22:14:40.790051 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6863 22:14:40.793808 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6864 22:14:40.796707 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6865 22:14:40.799902 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6866 22:14:40.806512 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6867 22:14:40.806631 ==
6868 22:14:40.810088 Dram Type= 6, Freq= 0, CH_1, rank 1
6869 22:14:40.813461 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6870 22:14:40.813579 ==
6871 22:14:40.813687 DQS Delay:
6872 22:14:40.816577 DQS0 = 35, DQS1 = 43
6873 22:14:40.816692 DQM Delay:
6874 22:14:40.819891 DQM0 = 16, DQM1 = 19
6875 22:14:40.820005 DQ Delay:
6876 22:14:40.822962 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6877 22:14:40.826455 DQ4 =16, DQ5 =24, DQ6 =24, DQ7 =16
6878 22:14:40.829764 DQ8 =0, DQ9 =8, DQ10 =24, DQ11 =16
6879 22:14:40.832861 DQ12 =32, DQ13 =24, DQ14 =16, DQ15 =32
6880 22:14:40.832977
6881 22:14:40.833082
6882 22:14:40.833186 ==
6883 22:14:40.836056 Dram Type= 6, Freq= 0, CH_1, rank 1
6884 22:14:40.839633 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6885 22:14:40.843130 ==
6886 22:14:40.843246
6887 22:14:40.843353
6888 22:14:40.843457 TX Vref Scan disable
6889 22:14:40.846172 == TX Byte 0 ==
6890 22:14:40.849686 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6891 22:14:40.852724 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6892 22:14:40.856096 == TX Byte 1 ==
6893 22:14:40.859545 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6894 22:14:40.862779 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6895 22:14:40.862894 ==
6896 22:14:40.866134 Dram Type= 6, Freq= 0, CH_1, rank 1
6897 22:14:40.872863 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6898 22:14:40.872981 ==
6899 22:14:40.873089
6900 22:14:40.873193
6901 22:14:40.873294 TX Vref Scan disable
6902 22:14:40.876557 == TX Byte 0 ==
6903 22:14:40.879579 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6904 22:14:40.882331 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6905 22:14:40.885698 == TX Byte 1 ==
6906 22:14:40.889083 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6907 22:14:40.892391 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6908 22:14:40.892507
6909 22:14:40.895727 [DATLAT]
6910 22:14:40.895842 Freq=400, CH1 RK1
6911 22:14:40.895951
6912 22:14:40.898822 DATLAT Default: 0xe
6913 22:14:40.898936 0, 0xFFFF, sum = 0
6914 22:14:40.902443 1, 0xFFFF, sum = 0
6915 22:14:40.902562 2, 0xFFFF, sum = 0
6916 22:14:40.905681 3, 0xFFFF, sum = 0
6917 22:14:40.905800 4, 0xFFFF, sum = 0
6918 22:14:40.908762 5, 0xFFFF, sum = 0
6919 22:14:40.908924 6, 0xFFFF, sum = 0
6920 22:14:40.912148 7, 0xFFFF, sum = 0
6921 22:14:40.912265 8, 0xFFFF, sum = 0
6922 22:14:40.915357 9, 0xFFFF, sum = 0
6923 22:14:40.915475 10, 0xFFFF, sum = 0
6924 22:14:40.919091 11, 0xFFFF, sum = 0
6925 22:14:40.922265 12, 0xFFFF, sum = 0
6926 22:14:40.922384 13, 0x0, sum = 1
6927 22:14:40.922491 14, 0x0, sum = 2
6928 22:14:40.925614 15, 0x0, sum = 3
6929 22:14:40.925732 16, 0x0, sum = 4
6930 22:14:40.928876 best_step = 14
6931 22:14:40.928990
6932 22:14:40.929095 ==
6933 22:14:40.932074 Dram Type= 6, Freq= 0, CH_1, rank 1
6934 22:14:40.935921 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6935 22:14:40.936039 ==
6936 22:14:40.938683 RX Vref Scan: 0
6937 22:14:40.938798
6938 22:14:40.938903 RX Vref 0 -> 0, step: 1
6939 22:14:40.939005
6940 22:14:40.941890 RX Delay -327 -> 252, step: 8
6941 22:14:40.950225 iDelay=217, Bit 0, Center -12 (-231 ~ 208) 440
6942 22:14:40.953799 iDelay=217, Bit 1, Center -24 (-247 ~ 200) 448
6943 22:14:40.957314 iDelay=217, Bit 2, Center -32 (-255 ~ 192) 448
6944 22:14:40.963710 iDelay=217, Bit 3, Center -20 (-247 ~ 208) 456
6945 22:14:40.967182 iDelay=217, Bit 4, Center -20 (-247 ~ 208) 456
6946 22:14:40.970269 iDelay=217, Bit 5, Center -8 (-231 ~ 216) 448
6947 22:14:40.973330 iDelay=217, Bit 6, Center -16 (-239 ~ 208) 448
6948 22:14:40.976971 iDelay=217, Bit 7, Center -24 (-247 ~ 200) 448
6949 22:14:40.983381 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6950 22:14:40.986469 iDelay=217, Bit 9, Center -36 (-263 ~ 192) 456
6951 22:14:40.989984 iDelay=217, Bit 10, Center -24 (-247 ~ 200) 448
6952 22:14:40.996690 iDelay=217, Bit 11, Center -28 (-255 ~ 200) 456
6953 22:14:40.999944 iDelay=217, Bit 12, Center -20 (-247 ~ 208) 456
6954 22:14:41.003271 iDelay=217, Bit 13, Center -20 (-247 ~ 208) 456
6955 22:14:41.006661 iDelay=217, Bit 14, Center -20 (-247 ~ 208) 456
6956 22:14:41.012976 iDelay=217, Bit 15, Center -16 (-247 ~ 216) 464
6957 22:14:41.013094 ==
6958 22:14:41.016389 Dram Type= 6, Freq= 0, CH_1, rank 1
6959 22:14:41.019707 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6960 22:14:41.019824 ==
6961 22:14:41.019931 DQS Delay:
6962 22:14:41.022918 DQS0 = 32, DQS1 = 36
6963 22:14:41.023033 DQM Delay:
6964 22:14:41.026699 DQM0 = 12, DQM1 = 11
6965 22:14:41.026814 DQ Delay:
6966 22:14:41.029801 DQ0 =20, DQ1 =8, DQ2 =0, DQ3 =12
6967 22:14:41.032790 DQ4 =12, DQ5 =24, DQ6 =16, DQ7 =8
6968 22:14:41.036227 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =8
6969 22:14:41.039562 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =20
6970 22:14:41.039677
6971 22:14:41.039784
6972 22:14:41.046233 [DQSOSCAuto] RK1, (LSB)MR18= 0xaa53, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 388 ps
6973 22:14:41.049617 CH1 RK1: MR19=C0C, MR18=AA53
6974 22:14:41.055806 CH1_RK1: MR19=0xC0C, MR18=0xAA53, DQSOSC=388, MR23=63, INC=392, DEC=261
6975 22:14:41.059261 [RxdqsGatingPostProcess] freq 400
6976 22:14:41.065665 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6977 22:14:41.069134 best DQS0 dly(2T, 0.5T) = (0, 10)
6978 22:14:41.072576 best DQS1 dly(2T, 0.5T) = (0, 10)
6979 22:14:41.075718 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6980 22:14:41.079160 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6981 22:14:41.079276 best DQS0 dly(2T, 0.5T) = (0, 10)
6982 22:14:41.082840 best DQS1 dly(2T, 0.5T) = (0, 10)
6983 22:14:41.085718 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6984 22:14:41.089335 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6985 22:14:41.092309 Pre-setting of DQS Precalculation
6986 22:14:41.098842 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6987 22:14:41.105997 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6988 22:14:41.112248 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6989 22:14:41.112366
6990 22:14:41.112473
6991 22:14:41.115658 [Calibration Summary] 800 Mbps
6992 22:14:41.115774 CH 0, Rank 0
6993 22:14:41.118658 SW Impedance : PASS
6994 22:14:41.121978 DUTY Scan : NO K
6995 22:14:41.122093 ZQ Calibration : PASS
6996 22:14:41.125397 Jitter Meter : NO K
6997 22:14:41.128470 CBT Training : PASS
6998 22:14:41.128583 Write leveling : PASS
6999 22:14:41.131863 RX DQS gating : PASS
7000 22:14:41.135261 RX DQ/DQS(RDDQC) : PASS
7001 22:14:41.135376 TX DQ/DQS : PASS
7002 22:14:41.138698 RX DATLAT : PASS
7003 22:14:41.142298 RX DQ/DQS(Engine): PASS
7004 22:14:41.142414 TX OE : NO K
7005 22:14:41.145243 All Pass.
7006 22:14:41.145357
7007 22:14:41.145464 CH 0, Rank 1
7008 22:14:41.148392 SW Impedance : PASS
7009 22:14:41.148505 DUTY Scan : NO K
7010 22:14:41.151714 ZQ Calibration : PASS
7011 22:14:41.154884 Jitter Meter : NO K
7012 22:14:41.155001 CBT Training : PASS
7013 22:14:41.158333 Write leveling : NO K
7014 22:14:41.162124 RX DQS gating : PASS
7015 22:14:41.162241 RX DQ/DQS(RDDQC) : PASS
7016 22:14:41.164709 TX DQ/DQS : PASS
7017 22:14:41.168097 RX DATLAT : PASS
7018 22:14:41.168214 RX DQ/DQS(Engine): PASS
7019 22:14:41.171538 TX OE : NO K
7020 22:14:41.171655 All Pass.
7021 22:14:41.171762
7022 22:14:41.174590 CH 1, Rank 0
7023 22:14:41.174706 SW Impedance : PASS
7024 22:14:41.178160 DUTY Scan : NO K
7025 22:14:41.181262 ZQ Calibration : PASS
7026 22:14:41.181378 Jitter Meter : NO K
7027 22:14:41.184698 CBT Training : PASS
7028 22:14:41.184864 Write leveling : PASS
7029 22:14:41.187988 RX DQS gating : PASS
7030 22:14:41.191114 RX DQ/DQS(RDDQC) : PASS
7031 22:14:41.191228 TX DQ/DQS : PASS
7032 22:14:41.194608 RX DATLAT : PASS
7033 22:14:41.197821 RX DQ/DQS(Engine): PASS
7034 22:14:41.197937 TX OE : NO K
7035 22:14:41.201274 All Pass.
7036 22:14:41.201391
7037 22:14:41.201499 CH 1, Rank 1
7038 22:14:41.204416 SW Impedance : PASS
7039 22:14:41.204534 DUTY Scan : NO K
7040 22:14:41.208007 ZQ Calibration : PASS
7041 22:14:41.211673 Jitter Meter : NO K
7042 22:14:41.211790 CBT Training : PASS
7043 22:14:41.214503 Write leveling : NO K
7044 22:14:41.217895 RX DQS gating : PASS
7045 22:14:41.218013 RX DQ/DQS(RDDQC) : PASS
7046 22:14:41.221267 TX DQ/DQS : PASS
7047 22:14:41.224496 RX DATLAT : PASS
7048 22:14:41.224613 RX DQ/DQS(Engine): PASS
7049 22:14:41.227845 TX OE : NO K
7050 22:14:41.227962 All Pass.
7051 22:14:41.228070
7052 22:14:41.230788 DramC Write-DBI off
7053 22:14:41.234301 PER_BANK_REFRESH: Hybrid Mode
7054 22:14:41.234420 TX_TRACKING: ON
7055 22:14:41.244177 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7056 22:14:41.247791 [FAST_K] Save calibration result to emmc
7057 22:14:41.250638 dramc_set_vcore_voltage set vcore to 725000
7058 22:14:41.254202 Read voltage for 1600, 0
7059 22:14:41.254321 Vio18 = 0
7060 22:14:41.254428 Vcore = 725000
7061 22:14:41.257357 Vdram = 0
7062 22:14:41.257476 Vddq = 0
7063 22:14:41.257584 Vmddr = 0
7064 22:14:41.264234 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7065 22:14:41.267076 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7066 22:14:41.270374 MEM_TYPE=3, freq_sel=13
7067 22:14:41.273837 sv_algorithm_assistance_LP4_3733
7068 22:14:41.276929 ============ PULL DRAM RESETB DOWN ============
7069 22:14:41.280450 ========== PULL DRAM RESETB DOWN end =========
7070 22:14:41.287023 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7071 22:14:41.290387 ===================================
7072 22:14:41.293839 LPDDR4 DRAM CONFIGURATION
7073 22:14:41.296762 ===================================
7074 22:14:41.296916 EX_ROW_EN[0] = 0x0
7075 22:14:41.300711 EX_ROW_EN[1] = 0x0
7076 22:14:41.300878 LP4Y_EN = 0x0
7077 22:14:41.303413 WORK_FSP = 0x1
7078 22:14:41.303529 WL = 0x5
7079 22:14:41.307146 RL = 0x5
7080 22:14:41.307263 BL = 0x2
7081 22:14:41.310005 RPST = 0x0
7082 22:14:41.310120 RD_PRE = 0x0
7083 22:14:41.314168 WR_PRE = 0x1
7084 22:14:41.314285 WR_PST = 0x1
7085 22:14:41.316698 DBI_WR = 0x0
7086 22:14:41.320063 DBI_RD = 0x0
7087 22:14:41.320179 OTF = 0x1
7088 22:14:41.323270 ===================================
7089 22:14:41.326680 ===================================
7090 22:14:41.326794 ANA top config
7091 22:14:41.330159 ===================================
7092 22:14:41.333072 DLL_ASYNC_EN = 0
7093 22:14:41.336270 ALL_SLAVE_EN = 0
7094 22:14:41.339854 NEW_RANK_MODE = 1
7095 22:14:41.343309 DLL_IDLE_MODE = 1
7096 22:14:41.343423 LP45_APHY_COMB_EN = 1
7097 22:14:41.346511 TX_ODT_DIS = 0
7098 22:14:41.349570 NEW_8X_MODE = 1
7099 22:14:41.353009 ===================================
7100 22:14:41.356199 ===================================
7101 22:14:41.359472 data_rate = 3200
7102 22:14:41.363009 CKR = 1
7103 22:14:41.366284 DQ_P2S_RATIO = 8
7104 22:14:41.366400 ===================================
7105 22:14:41.369444 CA_P2S_RATIO = 8
7106 22:14:41.372681 DQ_CA_OPEN = 0
7107 22:14:41.376229 DQ_SEMI_OPEN = 0
7108 22:14:41.379339 CA_SEMI_OPEN = 0
7109 22:14:41.382796 CA_FULL_RATE = 0
7110 22:14:41.385906 DQ_CKDIV4_EN = 0
7111 22:14:41.386023 CA_CKDIV4_EN = 0
7112 22:14:41.389309 CA_PREDIV_EN = 0
7113 22:14:41.392749 PH8_DLY = 12
7114 22:14:41.395980 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7115 22:14:41.399148 DQ_AAMCK_DIV = 4
7116 22:14:41.402516 CA_AAMCK_DIV = 4
7117 22:14:41.402634 CA_ADMCK_DIV = 4
7118 22:14:41.405689 DQ_TRACK_CA_EN = 0
7119 22:14:41.409012 CA_PICK = 1600
7120 22:14:41.412348 CA_MCKIO = 1600
7121 22:14:41.415867 MCKIO_SEMI = 0
7122 22:14:41.419014 PLL_FREQ = 3068
7123 22:14:41.422213 DQ_UI_PI_RATIO = 32
7124 22:14:41.425259 CA_UI_PI_RATIO = 0
7125 22:14:41.428666 ===================================
7126 22:14:41.432097 ===================================
7127 22:14:41.432226 memory_type:LPDDR4
7128 22:14:41.435453 GP_NUM : 10
7129 22:14:41.435583 SRAM_EN : 1
7130 22:14:41.438736 MD32_EN : 0
7131 22:14:41.442240 ===================================
7132 22:14:41.445593 [ANA_INIT] >>>>>>>>>>>>>>
7133 22:14:41.448570 <<<<<< [CONFIGURE PHASE]: ANA_TX
7134 22:14:41.452183 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7135 22:14:41.455626 ===================================
7136 22:14:41.455756 data_rate = 3200,PCW = 0X7600
7137 22:14:41.461825 ===================================
7138 22:14:41.465324 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7139 22:14:41.468402 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7140 22:14:41.474939 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7141 22:14:41.478797 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7142 22:14:41.481814 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7143 22:14:41.485288 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7144 22:14:41.488604 [ANA_INIT] flow start
7145 22:14:41.491758 [ANA_INIT] PLL >>>>>>>>
7146 22:14:41.491890 [ANA_INIT] PLL <<<<<<<<
7147 22:14:41.495078 [ANA_INIT] MIDPI >>>>>>>>
7148 22:14:41.498490 [ANA_INIT] MIDPI <<<<<<<<
7149 22:14:41.498573 [ANA_INIT] DLL >>>>>>>>
7150 22:14:41.501491 [ANA_INIT] DLL <<<<<<<<
7151 22:14:41.504830 [ANA_INIT] flow end
7152 22:14:41.508411 ============ LP4 DIFF to SE enter ============
7153 22:14:41.511856 ============ LP4 DIFF to SE exit ============
7154 22:14:41.515076 [ANA_INIT] <<<<<<<<<<<<<
7155 22:14:41.518221 [Flow] Enable top DCM control >>>>>
7156 22:14:41.521870 [Flow] Enable top DCM control <<<<<
7157 22:14:41.524681 Enable DLL master slave shuffle
7158 22:14:41.531231 ==============================================================
7159 22:14:41.531316 Gating Mode config
7160 22:14:41.537916 ==============================================================
7161 22:14:41.538003 Config description:
7162 22:14:41.547960 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7163 22:14:41.554324 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7164 22:14:41.561243 SELPH_MODE 0: By rank 1: By Phase
7165 22:14:41.564166 ==============================================================
7166 22:14:41.567236 GAT_TRACK_EN = 1
7167 22:14:41.570674 RX_GATING_MODE = 2
7168 22:14:41.574257 RX_GATING_TRACK_MODE = 2
7169 22:14:41.577464 SELPH_MODE = 1
7170 22:14:41.580605 PICG_EARLY_EN = 1
7171 22:14:41.583794 VALID_LAT_VALUE = 1
7172 22:14:41.590293 ==============================================================
7173 22:14:41.593856 Enter into Gating configuration >>>>
7174 22:14:41.597245 Exit from Gating configuration <<<<
7175 22:14:41.600337 Enter into DVFS_PRE_config >>>>>
7176 22:14:41.610196 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7177 22:14:41.613715 Exit from DVFS_PRE_config <<<<<
7178 22:14:41.617189 Enter into PICG configuration >>>>
7179 22:14:41.620270 Exit from PICG configuration <<<<
7180 22:14:41.623564 [RX_INPUT] configuration >>>>>
7181 22:14:41.623648 [RX_INPUT] configuration <<<<<
7182 22:14:41.630235 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7183 22:14:41.636745 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7184 22:14:41.643101 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7185 22:14:41.646385 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7186 22:14:41.653155 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7187 22:14:41.659814 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7188 22:14:41.663026 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7189 22:14:41.666367 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7190 22:14:41.672949 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7191 22:14:41.676075 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7192 22:14:41.679631 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7193 22:14:41.686091 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7194 22:14:41.689285 ===================================
7195 22:14:41.689370 LPDDR4 DRAM CONFIGURATION
7196 22:14:41.692492 ===================================
7197 22:14:41.695951 EX_ROW_EN[0] = 0x0
7198 22:14:41.699739 EX_ROW_EN[1] = 0x0
7199 22:14:41.699821 LP4Y_EN = 0x0
7200 22:14:41.702995 WORK_FSP = 0x1
7201 22:14:41.703078 WL = 0x5
7202 22:14:41.706250 RL = 0x5
7203 22:14:41.706333 BL = 0x2
7204 22:14:41.709184 RPST = 0x0
7205 22:14:41.709267 RD_PRE = 0x0
7206 22:14:41.712318 WR_PRE = 0x1
7207 22:14:41.712400 WR_PST = 0x1
7208 22:14:41.715704 DBI_WR = 0x0
7209 22:14:41.715818 DBI_RD = 0x0
7210 22:14:41.719092 OTF = 0x1
7211 22:14:41.722560 ===================================
7212 22:14:41.725568 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7213 22:14:41.729016 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7214 22:14:41.736548 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7215 22:14:41.738653 ===================================
7216 22:14:41.738751 LPDDR4 DRAM CONFIGURATION
7217 22:14:41.742400 ===================================
7218 22:14:41.746055 EX_ROW_EN[0] = 0x10
7219 22:14:41.748742 EX_ROW_EN[1] = 0x0
7220 22:14:41.748880 LP4Y_EN = 0x0
7221 22:14:41.752191 WORK_FSP = 0x1
7222 22:14:41.752273 WL = 0x5
7223 22:14:41.755377 RL = 0x5
7224 22:14:41.755459 BL = 0x2
7225 22:14:41.758778 RPST = 0x0
7226 22:14:41.758861 RD_PRE = 0x0
7227 22:14:41.762222 WR_PRE = 0x1
7228 22:14:41.762303 WR_PST = 0x1
7229 22:14:41.765553 DBI_WR = 0x0
7230 22:14:41.765636 DBI_RD = 0x0
7231 22:14:41.769151 OTF = 0x1
7232 22:14:41.772076 ===================================
7233 22:14:41.778825 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7234 22:14:41.778910 ==
7235 22:14:41.782433 Dram Type= 6, Freq= 0, CH_0, rank 0
7236 22:14:41.785064 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7237 22:14:41.785147 ==
7238 22:14:41.788350 [Duty_Offset_Calibration]
7239 22:14:41.788432 B0:2 B1:0 CA:1
7240 22:14:41.788497
7241 22:14:41.791859 [DutyScan_Calibration_Flow] k_type=0
7242 22:14:41.801862
7243 22:14:41.801946 ==CLK 0==
7244 22:14:41.804965 Final CLK duty delay cell = -4
7245 22:14:41.808363 [-4] MAX Duty = 5031%(X100), DQS PI = 28
7246 22:14:41.811800 [-4] MIN Duty = 4813%(X100), DQS PI = 0
7247 22:14:41.814835 [-4] AVG Duty = 4922%(X100)
7248 22:14:41.814918
7249 22:14:41.818311 CH0 CLK Duty spec in!! Max-Min= 218%
7250 22:14:41.821539 [DutyScan_Calibration_Flow] ====Done====
7251 22:14:41.821622
7252 22:14:41.824781 [DutyScan_Calibration_Flow] k_type=1
7253 22:14:41.841122
7254 22:14:41.841210 ==DQS 0 ==
7255 22:14:41.844313 Final DQS duty delay cell = 0
7256 22:14:41.847713 [0] MAX Duty = 5249%(X100), DQS PI = 32
7257 22:14:41.851121 [0] MIN Duty = 4969%(X100), DQS PI = 0
7258 22:14:41.851205 [0] AVG Duty = 5109%(X100)
7259 22:14:41.854736
7260 22:14:41.854819 ==DQS 1 ==
7261 22:14:41.858008 Final DQS duty delay cell = -4
7262 22:14:41.861413 [-4] MAX Duty = 5125%(X100), DQS PI = 46
7263 22:14:41.864281 [-4] MIN Duty = 4875%(X100), DQS PI = 4
7264 22:14:41.867515 [-4] AVG Duty = 5000%(X100)
7265 22:14:41.867603
7266 22:14:41.871150 CH0 DQS 0 Duty spec in!! Max-Min= 280%
7267 22:14:41.871234
7268 22:14:41.874305 CH0 DQS 1 Duty spec in!! Max-Min= 250%
7269 22:14:41.877644 [DutyScan_Calibration_Flow] ====Done====
7270 22:14:41.877738
7271 22:14:41.880749 [DutyScan_Calibration_Flow] k_type=3
7272 22:14:41.897547
7273 22:14:41.897644 ==DQM 0 ==
7274 22:14:41.900991 Final DQM duty delay cell = 0
7275 22:14:41.904503 [0] MAX Duty = 5124%(X100), DQS PI = 26
7276 22:14:41.907591 [0] MIN Duty = 4844%(X100), DQS PI = 0
7277 22:14:41.910900 [0] AVG Duty = 4984%(X100)
7278 22:14:41.910985
7279 22:14:41.911051 ==DQM 1 ==
7280 22:14:41.914106 Final DQM duty delay cell = -4
7281 22:14:41.917994 [-4] MAX Duty = 5031%(X100), DQS PI = 46
7282 22:14:41.920695 [-4] MIN Duty = 4751%(X100), DQS PI = 10
7283 22:14:41.924033 [-4] AVG Duty = 4891%(X100)
7284 22:14:41.924117
7285 22:14:41.927351 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7286 22:14:41.927434
7287 22:14:41.930584 CH0 DQM 1 Duty spec in!! Max-Min= 280%
7288 22:14:41.933857 [DutyScan_Calibration_Flow] ====Done====
7289 22:14:41.933940
7290 22:14:41.937212 [DutyScan_Calibration_Flow] k_type=2
7291 22:14:41.955090
7292 22:14:41.955278 ==DQ 0 ==
7293 22:14:41.958502 Final DQ duty delay cell = 0
7294 22:14:41.961713 [0] MAX Duty = 5124%(X100), DQS PI = 32
7295 22:14:41.965219 [0] MIN Duty = 5000%(X100), DQS PI = 0
7296 22:14:41.965302 [0] AVG Duty = 5062%(X100)
7297 22:14:41.968584
7298 22:14:41.968665 ==DQ 1 ==
7299 22:14:41.971581 Final DQ duty delay cell = 0
7300 22:14:41.974847 [0] MAX Duty = 4969%(X100), DQS PI = 44
7301 22:14:41.978168 [0] MIN Duty = 4875%(X100), DQS PI = 12
7302 22:14:41.978268 [0] AVG Duty = 4922%(X100)
7303 22:14:41.981902
7304 22:14:41.985172 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7305 22:14:41.985255
7306 22:14:41.988238 CH0 DQ 1 Duty spec in!! Max-Min= 94%
7307 22:14:41.992092 [DutyScan_Calibration_Flow] ====Done====
7308 22:14:41.992175 ==
7309 22:14:41.994840 Dram Type= 6, Freq= 0, CH_1, rank 0
7310 22:14:41.998367 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7311 22:14:41.998448 ==
7312 22:14:42.001942 [Duty_Offset_Calibration]
7313 22:14:42.002022 B0:0 B1:-1 CA:2
7314 22:14:42.002085
7315 22:14:42.004666 [DutyScan_Calibration_Flow] k_type=0
7316 22:14:42.015245
7317 22:14:42.015325 ==CLK 0==
7318 22:14:42.018761 Final CLK duty delay cell = 0
7319 22:14:42.022008 [0] MAX Duty = 5156%(X100), DQS PI = 10
7320 22:14:42.025305 [0] MIN Duty = 4906%(X100), DQS PI = 46
7321 22:14:42.028562 [0] AVG Duty = 5031%(X100)
7322 22:14:42.028667
7323 22:14:42.032164 CH1 CLK Duty spec in!! Max-Min= 250%
7324 22:14:42.035171 [DutyScan_Calibration_Flow] ====Done====
7325 22:14:42.035252
7326 22:14:42.038524 [DutyScan_Calibration_Flow] k_type=1
7327 22:14:42.055131
7328 22:14:42.055216 ==DQS 0 ==
7329 22:14:42.059336 Final DQS duty delay cell = 0
7330 22:14:42.061505 [0] MAX Duty = 5124%(X100), DQS PI = 26
7331 22:14:42.064985 [0] MIN Duty = 4969%(X100), DQS PI = 2
7332 22:14:42.068388 [0] AVG Duty = 5046%(X100)
7333 22:14:42.068468
7334 22:14:42.068531 ==DQS 1 ==
7335 22:14:42.071671 Final DQS duty delay cell = 0
7336 22:14:42.074883 [0] MAX Duty = 5187%(X100), DQS PI = 0
7337 22:14:42.078200 [0] MIN Duty = 4844%(X100), DQS PI = 34
7338 22:14:42.081497 [0] AVG Duty = 5015%(X100)
7339 22:14:42.081579
7340 22:14:42.084735 CH1 DQS 0 Duty spec in!! Max-Min= 155%
7341 22:14:42.084878
7342 22:14:42.088153 CH1 DQS 1 Duty spec in!! Max-Min= 343%
7343 22:14:42.091594 [DutyScan_Calibration_Flow] ====Done====
7344 22:14:42.091678
7345 22:14:42.094601 [DutyScan_Calibration_Flow] k_type=3
7346 22:14:42.113030
7347 22:14:42.113115 ==DQM 0 ==
7348 22:14:42.116104 Final DQM duty delay cell = 4
7349 22:14:42.119291 [4] MAX Duty = 5125%(X100), DQS PI = 6
7350 22:14:42.122636 [4] MIN Duty = 4969%(X100), DQS PI = 48
7351 22:14:42.122720 [4] AVG Duty = 5047%(X100)
7352 22:14:42.126309
7353 22:14:42.126393 ==DQM 1 ==
7354 22:14:42.129196 Final DQM duty delay cell = 0
7355 22:14:42.132490 [0] MAX Duty = 5281%(X100), DQS PI = 58
7356 22:14:42.136004 [0] MIN Duty = 4876%(X100), DQS PI = 34
7357 22:14:42.139023 [0] AVG Duty = 5078%(X100)
7358 22:14:42.139106
7359 22:14:42.142323 CH1 DQM 0 Duty spec in!! Max-Min= 156%
7360 22:14:42.142408
7361 22:14:42.145881 CH1 DQM 1 Duty spec in!! Max-Min= 405%
7362 22:14:42.149140 [DutyScan_Calibration_Flow] ====Done====
7363 22:14:42.149224
7364 22:14:42.152344 [DutyScan_Calibration_Flow] k_type=2
7365 22:14:42.169919
7366 22:14:42.170012 ==DQ 0 ==
7367 22:14:42.173479 Final DQ duty delay cell = 0
7368 22:14:42.176181 [0] MAX Duty = 5093%(X100), DQS PI = 20
7369 22:14:42.179609 [0] MIN Duty = 4969%(X100), DQS PI = 48
7370 22:14:42.182800 [0] AVG Duty = 5031%(X100)
7371 22:14:42.182890
7372 22:14:42.182957 ==DQ 1 ==
7373 22:14:42.186131 Final DQ duty delay cell = 0
7374 22:14:42.189320 [0] MAX Duty = 5062%(X100), DQS PI = 0
7375 22:14:42.192659 [0] MIN Duty = 4813%(X100), DQS PI = 34
7376 22:14:42.196180 [0] AVG Duty = 4937%(X100)
7377 22:14:42.196285
7378 22:14:42.199451 CH1 DQ 0 Duty spec in!! Max-Min= 124%
7379 22:14:42.199536
7380 22:14:42.202488 CH1 DQ 1 Duty spec in!! Max-Min= 249%
7381 22:14:42.205602 [DutyScan_Calibration_Flow] ====Done====
7382 22:14:42.209067 nWR fixed to 30
7383 22:14:42.209152 [ModeRegInit_LP4] CH0 RK0
7384 22:14:42.212702 [ModeRegInit_LP4] CH0 RK1
7385 22:14:42.215622 [ModeRegInit_LP4] CH1 RK0
7386 22:14:42.218603 [ModeRegInit_LP4] CH1 RK1
7387 22:14:42.218688 match AC timing 5
7388 22:14:42.226179 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7389 22:14:42.228680 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7390 22:14:42.231866 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7391 22:14:42.238608 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7392 22:14:42.241650 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7393 22:14:42.241737 [MiockJmeterHQA]
7394 22:14:42.241803
7395 22:14:42.244989 [DramcMiockJmeter] u1RxGatingPI = 0
7396 22:14:42.248367 0 : 4255, 4027
7397 22:14:42.248452 4 : 4363, 4137
7398 22:14:42.251452 8 : 4253, 4026
7399 22:14:42.251537 12 : 4363, 4138
7400 22:14:42.255027 16 : 4253, 4026
7401 22:14:42.255113 20 : 4252, 4026
7402 22:14:42.257990 24 : 4252, 4027
7403 22:14:42.258075 28 : 4363, 4137
7404 22:14:42.258143 32 : 4363, 4138
7405 22:14:42.261406 36 : 4252, 4027
7406 22:14:42.261495 40 : 4255, 4030
7407 22:14:42.265202 44 : 4253, 4027
7408 22:14:42.265288 48 : 4365, 4140
7409 22:14:42.268396 52 : 4252, 4027
7410 22:14:42.268481 56 : 4363, 4137
7411 22:14:42.271285 60 : 4249, 4027
7412 22:14:42.271370 64 : 4253, 4027
7413 22:14:42.271437 68 : 4250, 4027
7414 22:14:42.274736 72 : 4250, 4027
7415 22:14:42.274822 76 : 4250, 4027
7416 22:14:42.278310 80 : 4360, 4138
7417 22:14:42.278426 84 : 4360, 4138
7418 22:14:42.281285 88 : 4250, 3359
7419 22:14:42.281371 92 : 4250, 0
7420 22:14:42.281439 96 : 4360, 0
7421 22:14:42.285113 100 : 4255, 0
7422 22:14:42.285201 104 : 4250, 0
7423 22:14:42.288055 108 : 4252, 0
7424 22:14:42.288140 112 : 4250, 0
7425 22:14:42.288207 116 : 4250, 0
7426 22:14:42.291549 120 : 4252, 0
7427 22:14:42.291634 124 : 4360, 0
7428 22:14:42.291701 128 : 4361, 0
7429 22:14:42.294320 132 : 4360, 0
7430 22:14:42.294417 136 : 4250, 0
7431 22:14:42.298127 140 : 4250, 0
7432 22:14:42.298213 144 : 4363, 0
7433 22:14:42.298280 148 : 4250, 0
7434 22:14:42.301317 152 : 4249, 0
7435 22:14:42.301403 156 : 4250, 0
7436 22:14:42.304547 160 : 4253, 0
7437 22:14:42.304631 164 : 4249, 0
7438 22:14:42.304698 168 : 4250, 0
7439 22:14:42.307988 172 : 4253, 0
7440 22:14:42.308072 176 : 4360, 0
7441 22:14:42.311085 180 : 4250, 0
7442 22:14:42.311169 184 : 4360, 0
7443 22:14:42.311236 188 : 4252, 0
7444 22:14:42.314590 192 : 4250, 0
7445 22:14:42.314674 196 : 4250, 0
7446 22:14:42.314742 200 : 4249, 8
7447 22:14:42.317590 204 : 4250, 2513
7448 22:14:42.317674 208 : 4250, 4027
7449 22:14:42.321289 212 : 4252, 4030
7450 22:14:42.321373 216 : 4250, 4027
7451 22:14:42.324397 220 : 4250, 4027
7452 22:14:42.324481 224 : 4360, 4138
7453 22:14:42.327614 228 : 4250, 4027
7454 22:14:42.327699 232 : 4250, 4026
7455 22:14:42.331034 236 : 4361, 4137
7456 22:14:42.331122 240 : 4250, 4027
7457 22:14:42.334175 244 : 4249, 4027
7458 22:14:42.334259 248 : 4360, 4137
7459 22:14:42.337678 252 : 4250, 4027
7460 22:14:42.337762 256 : 4250, 4027
7461 22:14:42.340989 260 : 4250, 4027
7462 22:14:42.341073 264 : 4250, 4027
7463 22:14:42.341140 268 : 4250, 4026
7464 22:14:42.344378 272 : 4250, 4027
7465 22:14:42.344477 276 : 4360, 4138
7466 22:14:42.347616 280 : 4250, 4027
7467 22:14:42.347701 284 : 4250, 4026
7468 22:14:42.350875 288 : 4361, 4137
7469 22:14:42.351009 292 : 4250, 4027
7470 22:14:42.353939 296 : 4250, 4027
7471 22:14:42.354023 300 : 4360, 4137
7472 22:14:42.357691 304 : 4250, 4027
7473 22:14:42.357776 308 : 4250, 4027
7474 22:14:42.360705 312 : 4250, 3805
7475 22:14:42.360836 316 : 4250, 1858
7476 22:14:42.360904
7477 22:14:42.363974 MIOCK jitter meter ch=0
7478 22:14:42.364057
7479 22:14:42.367390 1T = (316-92) = 224 dly cells
7480 22:14:42.370558 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 290/100 ps
7481 22:14:42.374132 ==
7482 22:14:42.374215 Dram Type= 6, Freq= 0, CH_0, rank 0
7483 22:14:42.380691 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7484 22:14:42.380832 ==
7485 22:14:42.383808 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7486 22:14:42.390715 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7487 22:14:42.393692 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7488 22:14:42.400383 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7489 22:14:42.408223 [CA 0] Center 42 (12~72) winsize 61
7490 22:14:42.411711 [CA 1] Center 42 (12~72) winsize 61
7491 22:14:42.414892 [CA 2] Center 37 (7~67) winsize 61
7492 22:14:42.418122 [CA 3] Center 37 (7~67) winsize 61
7493 22:14:42.421410 [CA 4] Center 36 (6~66) winsize 61
7494 22:14:42.424748 [CA 5] Center 35 (5~65) winsize 61
7495 22:14:42.424842
7496 22:14:42.428213 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7497 22:14:42.428298
7498 22:14:42.434752 [CATrainingPosCal] consider 1 rank data
7499 22:14:42.434839 u2DelayCellTimex100 = 290/100 ps
7500 22:14:42.441398 CA0 delay=42 (12~72),Diff = 7 PI (23 cell)
7501 22:14:42.444550 CA1 delay=42 (12~72),Diff = 7 PI (23 cell)
7502 22:14:42.448529 CA2 delay=37 (7~67),Diff = 2 PI (6 cell)
7503 22:14:42.451194 CA3 delay=37 (7~67),Diff = 2 PI (6 cell)
7504 22:14:42.454656 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7505 22:14:42.457941 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
7506 22:14:42.458026
7507 22:14:42.461037 CA PerBit enable=1, Macro0, CA PI delay=35
7508 22:14:42.461134
7509 22:14:42.464484 [CBTSetCACLKResult] CA Dly = 35
7510 22:14:42.467699 CS Dly: 9 (0~40)
7511 22:14:42.471198 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7512 22:14:42.474490 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7513 22:14:42.474574 ==
7514 22:14:42.477908 Dram Type= 6, Freq= 0, CH_0, rank 1
7515 22:14:42.484159 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7516 22:14:42.484249 ==
7517 22:14:42.487664 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7518 22:14:42.491012 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7519 22:14:42.497560 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7520 22:14:42.504239 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7521 22:14:42.511664 [CA 0] Center 43 (13~73) winsize 61
7522 22:14:42.515320 [CA 1] Center 43 (13~73) winsize 61
7523 22:14:42.518371 [CA 2] Center 38 (8~68) winsize 61
7524 22:14:42.521563 [CA 3] Center 38 (8~68) winsize 61
7525 22:14:42.525101 [CA 4] Center 36 (6~66) winsize 61
7526 22:14:42.527997 [CA 5] Center 36 (6~66) winsize 61
7527 22:14:42.528081
7528 22:14:42.531151 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7529 22:14:42.531235
7530 22:14:42.538114 [CATrainingPosCal] consider 2 rank data
7531 22:14:42.538198 u2DelayCellTimex100 = 290/100 ps
7532 22:14:42.544416 CA0 delay=42 (13~72),Diff = 7 PI (23 cell)
7533 22:14:42.547675 CA1 delay=42 (13~72),Diff = 7 PI (23 cell)
7534 22:14:42.551246 CA2 delay=37 (8~67),Diff = 2 PI (6 cell)
7535 22:14:42.554988 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7536 22:14:42.558258 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7537 22:14:42.561147 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7538 22:14:42.561275
7539 22:14:42.564267 CA PerBit enable=1, Macro0, CA PI delay=35
7540 22:14:42.564352
7541 22:14:42.567532 [CBTSetCACLKResult] CA Dly = 35
7542 22:14:42.570903 CS Dly: 10 (0~43)
7543 22:14:42.574286 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7544 22:14:42.577588 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7545 22:14:42.577728
7546 22:14:42.580895 ----->DramcWriteLeveling(PI) begin...
7547 22:14:42.580988 ==
7548 22:14:42.584185 Dram Type= 6, Freq= 0, CH_0, rank 0
7549 22:14:42.591537 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7550 22:14:42.591671 ==
7551 22:14:42.594141 Write leveling (Byte 0): 37 => 37
7552 22:14:42.597625 Write leveling (Byte 1): 29 => 29
7553 22:14:42.597723 DramcWriteLeveling(PI) end<-----
7554 22:14:42.597794
7555 22:14:42.600746 ==
7556 22:14:42.604062 Dram Type= 6, Freq= 0, CH_0, rank 0
7557 22:14:42.607333 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7558 22:14:42.607421 ==
7559 22:14:42.610568 [Gating] SW mode calibration
7560 22:14:42.617444 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7561 22:14:42.620524 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7562 22:14:42.627320 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7563 22:14:42.630740 1 4 4 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
7564 22:14:42.633796 1 4 8 | B1->B0 | 2323 2b2b | 0 1 | (0 0) (0 0)
7565 22:14:42.640230 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7566 22:14:42.643496 1 4 16 | B1->B0 | 2322 3434 | 1 1 | (0 0) (1 1)
7567 22:14:42.646740 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7568 22:14:42.653984 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7569 22:14:42.656769 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7570 22:14:42.660072 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7571 22:14:42.667411 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7572 22:14:42.670032 1 5 8 | B1->B0 | 3434 3131 | 1 1 | (1 1) (0 0)
7573 22:14:42.673349 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
7574 22:14:42.679772 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
7575 22:14:42.683239 1 5 20 | B1->B0 | 2b2b 2323 | 0 0 | (1 0) (0 0)
7576 22:14:42.686515 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7577 22:14:42.693183 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7578 22:14:42.696337 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7579 22:14:42.699850 1 6 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7580 22:14:42.706464 1 6 8 | B1->B0 | 2323 3e3e | 0 0 | (0 0) (0 0)
7581 22:14:42.710055 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7582 22:14:42.712722 1 6 16 | B1->B0 | 2a2a 4646 | 0 0 | (0 0) (0 0)
7583 22:14:42.719569 1 6 20 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
7584 22:14:42.722928 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7585 22:14:42.726319 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7586 22:14:42.733754 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7587 22:14:42.736218 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7588 22:14:42.739303 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7589 22:14:42.745787 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7590 22:14:42.749375 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7591 22:14:42.752745 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7592 22:14:42.759196 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7593 22:14:42.762381 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7594 22:14:42.765750 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7595 22:14:42.772309 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7596 22:14:42.775582 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7597 22:14:42.778757 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7598 22:14:42.785833 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7599 22:14:42.788993 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7600 22:14:42.791989 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7601 22:14:42.798631 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7602 22:14:42.802474 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7603 22:14:42.805485 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7604 22:14:42.811731 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7605 22:14:42.815075 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7606 22:14:42.818308 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7607 22:14:42.821907 Total UI for P1: 0, mck2ui 16
7608 22:14:42.825184 best dqsien dly found for B0: ( 1, 9, 10)
7609 22:14:42.831874 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7610 22:14:42.835283 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7611 22:14:42.838269 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7612 22:14:42.841470 Total UI for P1: 0, mck2ui 16
7613 22:14:42.844830 best dqsien dly found for B1: ( 1, 9, 20)
7614 22:14:42.848133 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7615 22:14:42.851343 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7616 22:14:42.851438
7617 22:14:42.858352 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7618 22:14:42.861323 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7619 22:14:42.864634 [Gating] SW calibration Done
7620 22:14:42.864758 ==
7621 22:14:42.868071 Dram Type= 6, Freq= 0, CH_0, rank 0
7622 22:14:42.871417 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7623 22:14:42.871507 ==
7624 22:14:42.871576 RX Vref Scan: 0
7625 22:14:42.874549
7626 22:14:42.874636 RX Vref 0 -> 0, step: 1
7627 22:14:42.874705
7628 22:14:42.877948 RX Delay 0 -> 252, step: 8
7629 22:14:42.881221 iDelay=200, Bit 0, Center 135 (88 ~ 183) 96
7630 22:14:42.884547 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7631 22:14:42.891056 iDelay=200, Bit 2, Center 135 (88 ~ 183) 96
7632 22:14:42.894342 iDelay=200, Bit 3, Center 135 (88 ~ 183) 96
7633 22:14:42.898028 iDelay=200, Bit 4, Center 143 (96 ~ 191) 96
7634 22:14:42.901046 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
7635 22:14:42.904269 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7636 22:14:42.907659 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7637 22:14:42.914166 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
7638 22:14:42.917477 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7639 22:14:42.920931 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
7640 22:14:42.924290 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
7641 22:14:42.931417 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7642 22:14:42.933922 iDelay=200, Bit 13, Center 131 (88 ~ 175) 88
7643 22:14:42.937540 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7644 22:14:42.941011 iDelay=200, Bit 15, Center 135 (88 ~ 183) 96
7645 22:14:42.941096 ==
7646 22:14:42.943910 Dram Type= 6, Freq= 0, CH_0, rank 0
7647 22:14:42.947280 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7648 22:14:42.950554 ==
7649 22:14:42.950639 DQS Delay:
7650 22:14:42.950706 DQS0 = 0, DQS1 = 0
7651 22:14:42.954320 DQM Delay:
7652 22:14:42.954405 DQM0 = 138, DQM1 = 127
7653 22:14:42.957652 DQ Delay:
7654 22:14:42.960614 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
7655 22:14:42.963698 DQ4 =143, DQ5 =127, DQ6 =147, DQ7 =147
7656 22:14:42.967020 DQ8 =119, DQ9 =115, DQ10 =123, DQ11 =123
7657 22:14:42.970393 DQ12 =131, DQ13 =131, DQ14 =139, DQ15 =135
7658 22:14:42.970477
7659 22:14:42.970545
7660 22:14:42.970605 ==
7661 22:14:42.973820 Dram Type= 6, Freq= 0, CH_0, rank 0
7662 22:14:42.977181 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7663 22:14:42.977267 ==
7664 22:14:42.980293
7665 22:14:42.980378
7666 22:14:42.980446 TX Vref Scan disable
7667 22:14:42.983707 == TX Byte 0 ==
7668 22:14:42.987374 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7669 22:14:42.990205 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7670 22:14:42.993803 == TX Byte 1 ==
7671 22:14:42.997217 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7672 22:14:43.000365 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7673 22:14:43.003338 ==
7674 22:14:43.003436 Dram Type= 6, Freq= 0, CH_0, rank 0
7675 22:14:43.010398 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7676 22:14:43.010525 ==
7677 22:14:43.022736
7678 22:14:43.026174 TX Vref early break, caculate TX vref
7679 22:14:43.029390 TX Vref=16, minBit 1, minWin=23, winSum=378
7680 22:14:43.032678 TX Vref=18, minBit 12, minWin=22, winSum=388
7681 22:14:43.036462 TX Vref=20, minBit 12, minWin=23, winSum=399
7682 22:14:43.039292 TX Vref=22, minBit 1, minWin=25, winSum=407
7683 22:14:43.042558 TX Vref=24, minBit 2, minWin=25, winSum=415
7684 22:14:43.049492 TX Vref=26, minBit 2, minWin=25, winSum=423
7685 22:14:43.052576 TX Vref=28, minBit 1, minWin=26, winSum=428
7686 22:14:43.055805 TX Vref=30, minBit 4, minWin=25, winSum=426
7687 22:14:43.059453 TX Vref=32, minBit 0, minWin=25, winSum=416
7688 22:14:43.062474 TX Vref=34, minBit 7, minWin=24, winSum=405
7689 22:14:43.068969 [TxChooseVref] Worse bit 1, Min win 26, Win sum 428, Final Vref 28
7690 22:14:43.069054
7691 22:14:43.072466 Final TX Range 0 Vref 28
7692 22:14:43.072551
7693 22:14:43.072617 ==
7694 22:14:43.075489 Dram Type= 6, Freq= 0, CH_0, rank 0
7695 22:14:43.078680 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7696 22:14:43.078785 ==
7697 22:14:43.078866
7698 22:14:43.078927
7699 22:14:43.082530 TX Vref Scan disable
7700 22:14:43.088809 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
7701 22:14:43.088915 == TX Byte 0 ==
7702 22:14:43.092258 u2DelayCellOfst[0]=10 cells (3 PI)
7703 22:14:43.095240 u2DelayCellOfst[1]=16 cells (5 PI)
7704 22:14:43.098620 u2DelayCellOfst[2]=10 cells (3 PI)
7705 22:14:43.102307 u2DelayCellOfst[3]=10 cells (3 PI)
7706 22:14:43.105409 u2DelayCellOfst[4]=6 cells (2 PI)
7707 22:14:43.108909 u2DelayCellOfst[5]=0 cells (0 PI)
7708 22:14:43.112129 u2DelayCellOfst[6]=16 cells (5 PI)
7709 22:14:43.115609 u2DelayCellOfst[7]=16 cells (5 PI)
7710 22:14:43.118497 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7711 22:14:43.121971 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7712 22:14:43.125445 == TX Byte 1 ==
7713 22:14:43.128627 u2DelayCellOfst[8]=0 cells (0 PI)
7714 22:14:43.131769 u2DelayCellOfst[9]=0 cells (0 PI)
7715 22:14:43.131858 u2DelayCellOfst[10]=6 cells (2 PI)
7716 22:14:43.135079 u2DelayCellOfst[11]=3 cells (1 PI)
7717 22:14:43.138831 u2DelayCellOfst[12]=13 cells (4 PI)
7718 22:14:43.142112 u2DelayCellOfst[13]=13 cells (4 PI)
7719 22:14:43.145318 u2DelayCellOfst[14]=13 cells (4 PI)
7720 22:14:43.149030 u2DelayCellOfst[15]=10 cells (3 PI)
7721 22:14:43.155181 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7722 22:14:43.158684 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7723 22:14:43.158854 DramC Write-DBI on
7724 22:14:43.158938 ==
7725 22:14:43.161705 Dram Type= 6, Freq= 0, CH_0, rank 0
7726 22:14:43.168685 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7727 22:14:43.168883 ==
7728 22:14:43.168985
7729 22:14:43.169072
7730 22:14:43.169154 TX Vref Scan disable
7731 22:14:43.172597 == TX Byte 0 ==
7732 22:14:43.175854 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
7733 22:14:43.179391 == TX Byte 1 ==
7734 22:14:43.182594 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
7735 22:14:43.185689 DramC Write-DBI off
7736 22:14:43.185888
7737 22:14:43.186019 [DATLAT]
7738 22:14:43.186133 Freq=1600, CH0 RK0
7739 22:14:43.186244
7740 22:14:43.189139 DATLAT Default: 0xf
7741 22:14:43.192564 0, 0xFFFF, sum = 0
7742 22:14:43.192864 1, 0xFFFF, sum = 0
7743 22:14:43.196212 2, 0xFFFF, sum = 0
7744 22:14:43.196479 3, 0xFFFF, sum = 0
7745 22:14:43.199163 4, 0xFFFF, sum = 0
7746 22:14:43.199461 5, 0xFFFF, sum = 0
7747 22:14:43.202479 6, 0xFFFF, sum = 0
7748 22:14:43.202810 7, 0xFFFF, sum = 0
7749 22:14:43.205476 8, 0xFFFF, sum = 0
7750 22:14:43.205735 9, 0xFFFF, sum = 0
7751 22:14:43.209958 10, 0xFFFF, sum = 0
7752 22:14:43.210363 11, 0xFFFF, sum = 0
7753 22:14:43.212188 12, 0xFFFF, sum = 0
7754 22:14:43.212504 13, 0xFFFF, sum = 0
7755 22:14:43.215613 14, 0x0, sum = 1
7756 22:14:43.216117 15, 0x0, sum = 2
7757 22:14:43.218774 16, 0x0, sum = 3
7758 22:14:43.219183 17, 0x0, sum = 4
7759 22:14:43.222392 best_step = 15
7760 22:14:43.222895
7761 22:14:43.223222 ==
7762 22:14:43.225590 Dram Type= 6, Freq= 0, CH_0, rank 0
7763 22:14:43.229231 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7764 22:14:43.229733 ==
7765 22:14:43.232381 RX Vref Scan: 1
7766 22:14:43.232815
7767 22:14:43.233147 Set Vref Range= 24 -> 127
7768 22:14:43.233452
7769 22:14:43.235553 RX Vref 24 -> 127, step: 1
7770 22:14:43.235954
7771 22:14:43.238657 RX Delay 19 -> 252, step: 4
7772 22:14:43.239049
7773 22:14:43.242308 Set Vref, RX VrefLevel [Byte0]: 24
7774 22:14:43.245567 [Byte1]: 24
7775 22:14:43.246050
7776 22:14:43.248905 Set Vref, RX VrefLevel [Byte0]: 25
7777 22:14:43.251832 [Byte1]: 25
7778 22:14:43.256204
7779 22:14:43.256700 Set Vref, RX VrefLevel [Byte0]: 26
7780 22:14:43.258882 [Byte1]: 26
7781 22:14:43.263552
7782 22:14:43.264052 Set Vref, RX VrefLevel [Byte0]: 27
7783 22:14:43.266743 [Byte1]: 27
7784 22:14:43.271191
7785 22:14:43.271691 Set Vref, RX VrefLevel [Byte0]: 28
7786 22:14:43.274611 [Byte1]: 28
7787 22:14:43.278496
7788 22:14:43.278956 Set Vref, RX VrefLevel [Byte0]: 29
7789 22:14:43.281414 [Byte1]: 29
7790 22:14:43.286747
7791 22:14:43.287243 Set Vref, RX VrefLevel [Byte0]: 30
7792 22:14:43.288923 [Byte1]: 30
7793 22:14:43.293616
7794 22:14:43.294115 Set Vref, RX VrefLevel [Byte0]: 31
7795 22:14:43.297291 [Byte1]: 31
7796 22:14:43.301564
7797 22:14:43.302068 Set Vref, RX VrefLevel [Byte0]: 32
7798 22:14:43.304279 [Byte1]: 32
7799 22:14:43.309062
7800 22:14:43.309566 Set Vref, RX VrefLevel [Byte0]: 33
7801 22:14:43.311853 [Byte1]: 33
7802 22:14:43.316008
7803 22:14:43.316505 Set Vref, RX VrefLevel [Byte0]: 34
7804 22:14:43.319421 [Byte1]: 34
7805 22:14:43.323650
7806 22:14:43.324148 Set Vref, RX VrefLevel [Byte0]: 35
7807 22:14:43.327068 [Byte1]: 35
7808 22:14:43.331324
7809 22:14:43.331730 Set Vref, RX VrefLevel [Byte0]: 36
7810 22:14:43.335102 [Byte1]: 36
7811 22:14:43.338822
7812 22:14:43.339319 Set Vref, RX VrefLevel [Byte0]: 37
7813 22:14:43.342640 [Byte1]: 37
7814 22:14:43.346537
7815 22:14:43.347031 Set Vref, RX VrefLevel [Byte0]: 38
7816 22:14:43.349735 [Byte1]: 38
7817 22:14:43.354346
7818 22:14:43.354841 Set Vref, RX VrefLevel [Byte0]: 39
7819 22:14:43.357576 [Byte1]: 39
7820 22:14:43.361625
7821 22:14:43.362125 Set Vref, RX VrefLevel [Byte0]: 40
7822 22:14:43.364969 [Byte1]: 40
7823 22:14:43.369338
7824 22:14:43.369867 Set Vref, RX VrefLevel [Byte0]: 41
7825 22:14:43.372781 [Byte1]: 41
7826 22:14:43.377579
7827 22:14:43.378085 Set Vref, RX VrefLevel [Byte0]: 42
7828 22:14:43.379756 [Byte1]: 42
7829 22:14:43.384612
7830 22:14:43.385168 Set Vref, RX VrefLevel [Byte0]: 43
7831 22:14:43.387816 [Byte1]: 43
7832 22:14:43.392134
7833 22:14:43.392668 Set Vref, RX VrefLevel [Byte0]: 44
7834 22:14:43.395159 [Byte1]: 44
7835 22:14:43.399571
7836 22:14:43.400107 Set Vref, RX VrefLevel [Byte0]: 45
7837 22:14:43.403040 [Byte1]: 45
7838 22:14:43.407257
7839 22:14:43.407791 Set Vref, RX VrefLevel [Byte0]: 46
7840 22:14:43.411023 [Byte1]: 46
7841 22:14:43.414645
7842 22:14:43.415172 Set Vref, RX VrefLevel [Byte0]: 47
7843 22:14:43.418040 [Byte1]: 47
7844 22:14:43.422250
7845 22:14:43.422780 Set Vref, RX VrefLevel [Byte0]: 48
7846 22:14:43.425619 [Byte1]: 48
7847 22:14:43.430348
7848 22:14:43.430883 Set Vref, RX VrefLevel [Byte0]: 49
7849 22:14:43.433332 [Byte1]: 49
7850 22:14:43.437284
7851 22:14:43.437720 Set Vref, RX VrefLevel [Byte0]: 50
7852 22:14:43.440871 [Byte1]: 50
7853 22:14:43.444830
7854 22:14:43.445390 Set Vref, RX VrefLevel [Byte0]: 51
7855 22:14:43.448013 [Byte1]: 51
7856 22:14:43.452179
7857 22:14:43.452673 Set Vref, RX VrefLevel [Byte0]: 52
7858 22:14:43.455845 [Byte1]: 52
7859 22:14:43.460249
7860 22:14:43.460751 Set Vref, RX VrefLevel [Byte0]: 53
7861 22:14:43.463344 [Byte1]: 53
7862 22:14:43.467509
7863 22:14:43.468004 Set Vref, RX VrefLevel [Byte0]: 54
7864 22:14:43.471017 [Byte1]: 54
7865 22:14:43.475167
7866 22:14:43.478448 Set Vref, RX VrefLevel [Byte0]: 55
7867 22:14:43.481778 [Byte1]: 55
7868 22:14:43.482213
7869 22:14:43.484999 Set Vref, RX VrefLevel [Byte0]: 56
7870 22:14:43.488324 [Byte1]: 56
7871 22:14:43.488910
7872 22:14:43.491488 Set Vref, RX VrefLevel [Byte0]: 57
7873 22:14:43.495037 [Byte1]: 57
7874 22:14:43.495577
7875 22:14:43.498434 Set Vref, RX VrefLevel [Byte0]: 58
7876 22:14:43.501385 [Byte1]: 58
7877 22:14:43.505996
7878 22:14:43.506528 Set Vref, RX VrefLevel [Byte0]: 59
7879 22:14:43.508866 [Byte1]: 59
7880 22:14:43.513735
7881 22:14:43.514268 Set Vref, RX VrefLevel [Byte0]: 60
7882 22:14:43.516553 [Byte1]: 60
7883 22:14:43.521034
7884 22:14:43.521572 Set Vref, RX VrefLevel [Byte0]: 61
7885 22:14:43.524150 [Byte1]: 61
7886 22:14:43.528078
7887 22:14:43.528641 Set Vref, RX VrefLevel [Byte0]: 62
7888 22:14:43.531921 [Byte1]: 62
7889 22:14:43.535759
7890 22:14:43.536316 Set Vref, RX VrefLevel [Byte0]: 63
7891 22:14:43.539404 [Byte1]: 63
7892 22:14:43.543289
7893 22:14:43.543826 Set Vref, RX VrefLevel [Byte0]: 64
7894 22:14:43.546689 [Byte1]: 64
7895 22:14:43.550845
7896 22:14:43.551379 Set Vref, RX VrefLevel [Byte0]: 65
7897 22:14:43.554184 [Byte1]: 65
7898 22:14:43.558597
7899 22:14:43.559157 Set Vref, RX VrefLevel [Byte0]: 66
7900 22:14:43.561540 [Byte1]: 66
7901 22:14:43.566198
7902 22:14:43.566626 Set Vref, RX VrefLevel [Byte0]: 67
7903 22:14:43.569184 [Byte1]: 67
7904 22:14:43.573655
7905 22:14:43.574230 Set Vref, RX VrefLevel [Byte0]: 68
7906 22:14:43.577050 [Byte1]: 68
7907 22:14:43.581017
7908 22:14:43.581452 Set Vref, RX VrefLevel [Byte0]: 69
7909 22:14:43.584163 [Byte1]: 69
7910 22:14:43.589004
7911 22:14:43.589540 Set Vref, RX VrefLevel [Byte0]: 70
7912 22:14:43.591888 [Byte1]: 70
7913 22:14:43.596504
7914 22:14:43.597083 Set Vref, RX VrefLevel [Byte0]: 71
7915 22:14:43.599748 [Byte1]: 71
7916 22:14:43.604041
7917 22:14:43.604576 Set Vref, RX VrefLevel [Byte0]: 72
7918 22:14:43.607573 [Byte1]: 72
7919 22:14:43.612168
7920 22:14:43.612704 Set Vref, RX VrefLevel [Byte0]: 73
7921 22:14:43.614876 [Byte1]: 73
7922 22:14:43.619502
7923 22:14:43.619934 Set Vref, RX VrefLevel [Byte0]: 74
7924 22:14:43.622458 [Byte1]: 74
7925 22:14:43.626818
7926 22:14:43.627357 Set Vref, RX VrefLevel [Byte0]: 75
7927 22:14:43.629751 [Byte1]: 75
7928 22:14:43.634287
7929 22:14:43.634718 Set Vref, RX VrefLevel [Byte0]: 76
7930 22:14:43.637835 [Byte1]: 76
7931 22:14:43.641485
7932 22:14:43.641916 Set Vref, RX VrefLevel [Byte0]: 77
7933 22:14:43.644932 [Byte1]: 77
7934 22:14:43.649644
7935 22:14:43.650074 Set Vref, RX VrefLevel [Byte0]: 78
7936 22:14:43.652350 [Byte1]: 78
7937 22:14:43.657366
7938 22:14:43.657905 Set Vref, RX VrefLevel [Byte0]: 79
7939 22:14:43.659909 [Byte1]: 79
7940 22:14:43.664347
7941 22:14:43.664814 Set Vref, RX VrefLevel [Byte0]: 80
7942 22:14:43.667723 [Byte1]: 80
7943 22:14:43.671928
7944 22:14:43.672358 Set Vref, RX VrefLevel [Byte0]: 81
7945 22:14:43.674970 [Byte1]: 81
7946 22:14:43.680175
7947 22:14:43.680480 Final RX Vref Byte 0 = 61 to rank0
7948 22:14:43.682846 Final RX Vref Byte 1 = 60 to rank0
7949 22:14:43.685824 Final RX Vref Byte 0 = 61 to rank1
7950 22:14:43.689628 Final RX Vref Byte 1 = 60 to rank1==
7951 22:14:43.692622 Dram Type= 6, Freq= 0, CH_0, rank 0
7952 22:14:43.699283 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7953 22:14:43.699424 ==
7954 22:14:43.699532 DQS Delay:
7955 22:14:43.702389 DQS0 = 0, DQS1 = 0
7956 22:14:43.702524 DQM Delay:
7957 22:14:43.702632 DQM0 = 135, DQM1 = 124
7958 22:14:43.705635 DQ Delay:
7959 22:14:43.709221 DQ0 =136, DQ1 =138, DQ2 =132, DQ3 =132
7960 22:14:43.712090 DQ4 =138, DQ5 =124, DQ6 =142, DQ7 =144
7961 22:14:43.715779 DQ8 =116, DQ9 =110, DQ10 =126, DQ11 =118
7962 22:14:43.718975 DQ12 =130, DQ13 =128, DQ14 =136, DQ15 =134
7963 22:14:43.719069
7964 22:14:43.719142
7965 22:14:43.719211
7966 22:14:43.722002 [DramC_TX_OE_Calibration] TA2
7967 22:14:43.725806 Original DQ_B0 (3 6) =30, OEN = 27
7968 22:14:43.728973 Original DQ_B1 (3 6) =30, OEN = 27
7969 22:14:43.732379 24, 0x0, End_B0=24 End_B1=24
7970 22:14:43.732810 25, 0x0, End_B0=25 End_B1=25
7971 22:14:43.735576 26, 0x0, End_B0=26 End_B1=26
7972 22:14:43.739423 27, 0x0, End_B0=27 End_B1=27
7973 22:14:43.742112 28, 0x0, End_B0=28 End_B1=28
7974 22:14:43.745450 29, 0x0, End_B0=29 End_B1=29
7975 22:14:43.745854 30, 0x0, End_B0=30 End_B1=30
7976 22:14:43.749088 31, 0x4141, End_B0=30 End_B1=30
7977 22:14:43.752337 Byte0 end_step=30 best_step=27
7978 22:14:43.755362 Byte1 end_step=30 best_step=27
7979 22:14:43.758615 Byte0 TX OE(2T, 0.5T) = (3, 3)
7980 22:14:43.761962 Byte1 TX OE(2T, 0.5T) = (3, 3)
7981 22:14:43.762357
7982 22:14:43.762685
7983 22:14:43.768631 [DQSOSCAuto] RK0, (LSB)MR18= 0x201e, (MSB)MR19= 0x303, tDQSOscB0 = 394 ps tDQSOscB1 = 393 ps
7984 22:14:43.771885 CH0 RK0: MR19=303, MR18=201E
7985 22:14:43.778420 CH0_RK0: MR19=0x303, MR18=0x201E, DQSOSC=393, MR23=63, INC=23, DEC=15
7986 22:14:43.778571
7987 22:14:43.781582 ----->DramcWriteLeveling(PI) begin...
7988 22:14:43.781734 ==
7989 22:14:43.784856 Dram Type= 6, Freq= 0, CH_0, rank 1
7990 22:14:43.788567 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7991 22:14:43.788682 ==
7992 22:14:43.791726 Write leveling (Byte 0): 38 => 38
7993 22:14:43.794996 Write leveling (Byte 1): 30 => 30
7994 22:14:43.798179 DramcWriteLeveling(PI) end<-----
7995 22:14:43.798273
7996 22:14:43.798346 ==
7997 22:14:43.801765 Dram Type= 6, Freq= 0, CH_0, rank 1
7998 22:14:43.805088 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7999 22:14:43.805425 ==
8000 22:14:43.808626 [Gating] SW mode calibration
8001 22:14:43.814742 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8002 22:14:43.822042 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8003 22:14:43.824689 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8004 22:14:43.831747 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8005 22:14:43.834857 1 4 8 | B1->B0 | 2323 2524 | 0 1 | (0 0) (0 0)
8006 22:14:43.837902 1 4 12 | B1->B0 | 2423 3333 | 1 1 | (0 0) (1 1)
8007 22:14:43.844441 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8008 22:14:43.847824 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8009 22:14:43.851435 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8010 22:14:43.857668 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8011 22:14:43.861061 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8012 22:14:43.864357 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8013 22:14:43.871125 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8014 22:14:43.874439 1 5 12 | B1->B0 | 3434 2a2a | 0 0 | (1 0) (0 0)
8015 22:14:43.877858 1 5 16 | B1->B0 | 2d2d 2323 | 0 0 | (0 0) (0 0)
8016 22:14:43.884853 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8017 22:14:43.887805 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8018 22:14:43.891675 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8019 22:14:43.897515 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8020 22:14:43.900869 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8021 22:14:43.904121 1 6 8 | B1->B0 | 2323 3030 | 0 1 | (0 0) (0 0)
8022 22:14:43.910601 1 6 12 | B1->B0 | 3434 4646 | 1 0 | (0 0) (0 0)
8023 22:14:43.913732 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8024 22:14:43.917411 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8025 22:14:43.924051 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8026 22:14:43.927356 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8027 22:14:43.930622 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8028 22:14:43.937362 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8029 22:14:43.940865 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8030 22:14:43.943625 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8031 22:14:43.950300 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8032 22:14:43.953648 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8033 22:14:43.957085 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8034 22:14:43.963304 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8035 22:14:43.966750 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8036 22:14:43.970321 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8037 22:14:43.976806 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8038 22:14:43.980193 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8039 22:14:43.983378 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8040 22:14:43.986780 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8041 22:14:43.993563 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8042 22:14:43.997108 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8043 22:14:43.999891 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8044 22:14:44.006720 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8045 22:14:44.009806 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8046 22:14:44.013121 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8047 22:14:44.019632 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8048 22:14:44.023234 Total UI for P1: 0, mck2ui 16
8049 22:14:44.026770 best dqsien dly found for B0: ( 1, 9, 10)
8050 22:14:44.030127 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8051 22:14:44.033342 Total UI for P1: 0, mck2ui 16
8052 22:14:44.036384 best dqsien dly found for B1: ( 1, 9, 14)
8053 22:14:44.039914 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8054 22:14:44.043096 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8055 22:14:44.043529
8056 22:14:44.046646 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8057 22:14:44.053314 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8058 22:14:44.053546 [Gating] SW calibration Done
8059 22:14:44.053732 ==
8060 22:14:44.056223 Dram Type= 6, Freq= 0, CH_0, rank 1
8061 22:14:44.062879 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8062 22:14:44.063036 ==
8063 22:14:44.063160 RX Vref Scan: 0
8064 22:14:44.063275
8065 22:14:44.066046 RX Vref 0 -> 0, step: 1
8066 22:14:44.066202
8067 22:14:44.069466 RX Delay 0 -> 252, step: 8
8068 22:14:44.072642 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8069 22:14:44.076225 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8070 22:14:44.079008 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8071 22:14:44.085982 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
8072 22:14:44.089110 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8073 22:14:44.092676 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8074 22:14:44.095598 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8075 22:14:44.099160 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8076 22:14:44.105689 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8077 22:14:44.108885 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8078 22:14:44.112315 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
8079 22:14:44.115562 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8080 22:14:44.119431 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8081 22:14:44.125799 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
8082 22:14:44.129185 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8083 22:14:44.132573 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8084 22:14:44.133039 ==
8085 22:14:44.136145 Dram Type= 6, Freq= 0, CH_0, rank 1
8086 22:14:44.138958 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8087 22:14:44.139286 ==
8088 22:14:44.142122 DQS Delay:
8089 22:14:44.142429 DQS0 = 0, DQS1 = 0
8090 22:14:44.145656 DQM Delay:
8091 22:14:44.145888 DQM0 = 135, DQM1 = 125
8092 22:14:44.148986 DQ Delay:
8093 22:14:44.152346 DQ0 =135, DQ1 =135, DQ2 =135, DQ3 =131
8094 22:14:44.156008 DQ4 =135, DQ5 =127, DQ6 =143, DQ7 =143
8095 22:14:44.158644 DQ8 =119, DQ9 =111, DQ10 =123, DQ11 =123
8096 22:14:44.161874 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =135
8097 22:14:44.162008
8098 22:14:44.162113
8099 22:14:44.162212 ==
8100 22:14:44.165160 Dram Type= 6, Freq= 0, CH_0, rank 1
8101 22:14:44.168578 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8102 22:14:44.168747 ==
8103 22:14:44.168846
8104 22:14:44.168926
8105 22:14:44.172298 TX Vref Scan disable
8106 22:14:44.175260 == TX Byte 0 ==
8107 22:14:44.178823 Update DQ dly =994 (3 ,6, 34) DQ OEN =(3 ,3)
8108 22:14:44.181943 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
8109 22:14:44.185112 == TX Byte 1 ==
8110 22:14:44.188719 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8111 22:14:44.192562 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8112 22:14:44.192647 ==
8113 22:14:44.195180 Dram Type= 6, Freq= 0, CH_0, rank 1
8114 22:14:44.201561 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8115 22:14:44.201678 ==
8116 22:14:44.214471
8117 22:14:44.217352 TX Vref early break, caculate TX vref
8118 22:14:44.220483 TX Vref=16, minBit 0, minWin=23, winSum=390
8119 22:14:44.223893 TX Vref=18, minBit 0, minWin=24, winSum=400
8120 22:14:44.227222 TX Vref=20, minBit 3, minWin=24, winSum=407
8121 22:14:44.230990 TX Vref=22, minBit 0, minWin=25, winSum=417
8122 22:14:44.234182 TX Vref=24, minBit 1, minWin=25, winSum=423
8123 22:14:44.240385 TX Vref=26, minBit 3, minWin=26, winSum=433
8124 22:14:44.243730 TX Vref=28, minBit 2, minWin=26, winSum=431
8125 22:14:44.247290 TX Vref=30, minBit 2, minWin=26, winSum=427
8126 22:14:44.250424 TX Vref=32, minBit 13, minWin=25, winSum=419
8127 22:14:44.253984 TX Vref=34, minBit 2, minWin=24, winSum=407
8128 22:14:44.260042 [TxChooseVref] Worse bit 3, Min win 26, Win sum 433, Final Vref 26
8129 22:14:44.260133
8130 22:14:44.263529 Final TX Range 0 Vref 26
8131 22:14:44.263632
8132 22:14:44.263712 ==
8133 22:14:44.266655 Dram Type= 6, Freq= 0, CH_0, rank 1
8134 22:14:44.270098 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8135 22:14:44.270203 ==
8136 22:14:44.270288
8137 22:14:44.273149
8138 22:14:44.273286 TX Vref Scan disable
8139 22:14:44.279796 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8140 22:14:44.279960 == TX Byte 0 ==
8141 22:14:44.283286 u2DelayCellOfst[0]=13 cells (4 PI)
8142 22:14:44.286505 u2DelayCellOfst[1]=20 cells (6 PI)
8143 22:14:44.289848 u2DelayCellOfst[2]=13 cells (4 PI)
8144 22:14:44.293033 u2DelayCellOfst[3]=13 cells (4 PI)
8145 22:14:44.296380 u2DelayCellOfst[4]=10 cells (3 PI)
8146 22:14:44.299819 u2DelayCellOfst[5]=0 cells (0 PI)
8147 22:14:44.303433 u2DelayCellOfst[6]=20 cells (6 PI)
8148 22:14:44.306281 u2DelayCellOfst[7]=20 cells (6 PI)
8149 22:14:44.309849 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8150 22:14:44.312796 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
8151 22:14:44.316130 == TX Byte 1 ==
8152 22:14:44.319515 u2DelayCellOfst[8]=0 cells (0 PI)
8153 22:14:44.322800 u2DelayCellOfst[9]=0 cells (0 PI)
8154 22:14:44.325925 u2DelayCellOfst[10]=6 cells (2 PI)
8155 22:14:44.329757 u2DelayCellOfst[11]=3 cells (1 PI)
8156 22:14:44.332638 u2DelayCellOfst[12]=13 cells (4 PI)
8157 22:14:44.336411 u2DelayCellOfst[13]=13 cells (4 PI)
8158 22:14:44.336500 u2DelayCellOfst[14]=16 cells (5 PI)
8159 22:14:44.339164 u2DelayCellOfst[15]=10 cells (3 PI)
8160 22:14:44.345964 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8161 22:14:44.348971 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8162 22:14:44.352173 DramC Write-DBI on
8163 22:14:44.352258 ==
8164 22:14:44.355605 Dram Type= 6, Freq= 0, CH_0, rank 1
8165 22:14:44.358933 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8166 22:14:44.359018 ==
8167 22:14:44.359085
8168 22:14:44.359148
8169 22:14:44.362414 TX Vref Scan disable
8170 22:14:44.362498 == TX Byte 0 ==
8171 22:14:44.368961 Update DQM dly =737 (2 ,6, 33) DQM OEN =(3 ,3)
8172 22:14:44.369046 == TX Byte 1 ==
8173 22:14:44.372224 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8174 22:14:44.375854 DramC Write-DBI off
8175 22:14:44.375938
8176 22:14:44.376005 [DATLAT]
8177 22:14:44.378996 Freq=1600, CH0 RK1
8178 22:14:44.379079
8179 22:14:44.379147 DATLAT Default: 0xf
8180 22:14:44.382036 0, 0xFFFF, sum = 0
8181 22:14:44.382122 1, 0xFFFF, sum = 0
8182 22:14:44.385175 2, 0xFFFF, sum = 0
8183 22:14:44.388596 3, 0xFFFF, sum = 0
8184 22:14:44.388717 4, 0xFFFF, sum = 0
8185 22:14:44.391942 5, 0xFFFF, sum = 0
8186 22:14:44.392027 6, 0xFFFF, sum = 0
8187 22:14:44.395373 7, 0xFFFF, sum = 0
8188 22:14:44.395468 8, 0xFFFF, sum = 0
8189 22:14:44.398703 9, 0xFFFF, sum = 0
8190 22:14:44.398790 10, 0xFFFF, sum = 0
8191 22:14:44.401792 11, 0xFFFF, sum = 0
8192 22:14:44.401878 12, 0xFFFF, sum = 0
8193 22:14:44.405405 13, 0xFFFF, sum = 0
8194 22:14:44.405490 14, 0x0, sum = 1
8195 22:14:44.408541 15, 0x0, sum = 2
8196 22:14:44.408626 16, 0x0, sum = 3
8197 22:14:44.411930 17, 0x0, sum = 4
8198 22:14:44.412016 best_step = 15
8199 22:14:44.412083
8200 22:14:44.412145 ==
8201 22:14:44.414985 Dram Type= 6, Freq= 0, CH_0, rank 1
8202 22:14:44.422070 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8203 22:14:44.422155 ==
8204 22:14:44.422223 RX Vref Scan: 0
8205 22:14:44.422283
8206 22:14:44.425188 RX Vref 0 -> 0, step: 1
8207 22:14:44.425272
8208 22:14:44.427947 RX Delay 11 -> 252, step: 4
8209 22:14:44.431600 iDelay=191, Bit 0, Center 132 (83 ~ 182) 100
8210 22:14:44.436145 iDelay=191, Bit 1, Center 136 (87 ~ 186) 100
8211 22:14:44.438612 iDelay=191, Bit 2, Center 130 (79 ~ 182) 104
8212 22:14:44.445529 iDelay=191, Bit 3, Center 130 (83 ~ 178) 96
8213 22:14:44.448195 iDelay=191, Bit 4, Center 134 (83 ~ 186) 104
8214 22:14:44.451652 iDelay=191, Bit 5, Center 124 (75 ~ 174) 100
8215 22:14:44.455449 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8216 22:14:44.458814 iDelay=191, Bit 7, Center 138 (87 ~ 190) 104
8217 22:14:44.464545 iDelay=191, Bit 8, Center 116 (67 ~ 166) 100
8218 22:14:44.467823 iDelay=191, Bit 9, Center 112 (59 ~ 166) 108
8219 22:14:44.471280 iDelay=191, Bit 10, Center 124 (75 ~ 174) 100
8220 22:14:44.474564 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8221 22:14:44.480942 iDelay=191, Bit 12, Center 128 (75 ~ 182) 108
8222 22:14:44.484314 iDelay=191, Bit 13, Center 128 (79 ~ 178) 100
8223 22:14:44.487596 iDelay=191, Bit 14, Center 132 (79 ~ 186) 108
8224 22:14:44.490840 iDelay=191, Bit 15, Center 130 (79 ~ 182) 104
8225 22:14:44.490942 ==
8226 22:14:44.494188 Dram Type= 6, Freq= 0, CH_0, rank 1
8227 22:14:44.501178 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8228 22:14:44.501745 ==
8229 22:14:44.501844 DQS Delay:
8230 22:14:44.501940 DQS0 = 0, DQS1 = 0
8231 22:14:44.503994 DQM Delay:
8232 22:14:44.504077 DQM0 = 133, DQM1 = 123
8233 22:14:44.507253 DQ Delay:
8234 22:14:44.510700 DQ0 =132, DQ1 =136, DQ2 =130, DQ3 =130
8235 22:14:44.514828 DQ4 =134, DQ5 =124, DQ6 =140, DQ7 =138
8236 22:14:44.517317 DQ8 =116, DQ9 =112, DQ10 =124, DQ11 =118
8237 22:14:44.520653 DQ12 =128, DQ13 =128, DQ14 =132, DQ15 =130
8238 22:14:44.520790
8239 22:14:44.520908
8240 22:14:44.521006
8241 22:14:44.523923 [DramC_TX_OE_Calibration] TA2
8242 22:14:44.527506 Original DQ_B0 (3 6) =30, OEN = 27
8243 22:14:44.531056 Original DQ_B1 (3 6) =30, OEN = 27
8244 22:14:44.533937 24, 0x0, End_B0=24 End_B1=24
8245 22:14:44.534516 25, 0x0, End_B0=25 End_B1=25
8246 22:14:44.537473 26, 0x0, End_B0=26 End_B1=26
8247 22:14:44.540644 27, 0x0, End_B0=27 End_B1=27
8248 22:14:44.543916 28, 0x0, End_B0=28 End_B1=28
8249 22:14:44.547222 29, 0x0, End_B0=29 End_B1=29
8250 22:14:44.547782 30, 0x0, End_B0=30 End_B1=30
8251 22:14:44.550877 31, 0x4141, End_B0=30 End_B1=30
8252 22:14:44.553616 Byte0 end_step=30 best_step=27
8253 22:14:44.557089 Byte1 end_step=30 best_step=27
8254 22:14:44.560612 Byte0 TX OE(2T, 0.5T) = (3, 3)
8255 22:14:44.563431 Byte1 TX OE(2T, 0.5T) = (3, 3)
8256 22:14:44.563673
8257 22:14:44.563889
8258 22:14:44.570313 [DQSOSCAuto] RK1, (LSB)MR18= 0x200d, (MSB)MR19= 0x303, tDQSOscB0 = 403 ps tDQSOscB1 = 393 ps
8259 22:14:44.573248 CH0 RK1: MR19=303, MR18=200D
8260 22:14:44.580308 CH0_RK1: MR19=0x303, MR18=0x200D, DQSOSC=393, MR23=63, INC=23, DEC=15
8261 22:14:44.583371 [RxdqsGatingPostProcess] freq 1600
8262 22:14:44.586696 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8263 22:14:44.590249 best DQS0 dly(2T, 0.5T) = (1, 1)
8264 22:14:44.593138 best DQS1 dly(2T, 0.5T) = (1, 1)
8265 22:14:44.596725 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8266 22:14:44.600156 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8267 22:14:44.603519 best DQS0 dly(2T, 0.5T) = (1, 1)
8268 22:14:44.606446 best DQS1 dly(2T, 0.5T) = (1, 1)
8269 22:14:44.609779 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8270 22:14:44.613116 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8271 22:14:44.616924 Pre-setting of DQS Precalculation
8272 22:14:44.619787 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8273 22:14:44.620365 ==
8274 22:14:44.623340 Dram Type= 6, Freq= 0, CH_1, rank 0
8275 22:14:44.629824 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8276 22:14:44.630238 ==
8277 22:14:44.633003 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8278 22:14:44.636343 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8279 22:14:44.643044 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8280 22:14:44.649587 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8281 22:14:44.656967 [CA 0] Center 42 (12~72) winsize 61
8282 22:14:44.660309 [CA 1] Center 42 (12~72) winsize 61
8283 22:14:44.663506 [CA 2] Center 38 (9~68) winsize 60
8284 22:14:44.666823 [CA 3] Center 37 (8~67) winsize 60
8285 22:14:44.670428 [CA 4] Center 37 (8~67) winsize 60
8286 22:14:44.673878 [CA 5] Center 37 (7~67) winsize 61
8287 22:14:44.674006
8288 22:14:44.676737 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8289 22:14:44.676839
8290 22:14:44.680183 [CATrainingPosCal] consider 1 rank data
8291 22:14:44.683556 u2DelayCellTimex100 = 290/100 ps
8292 22:14:44.686915 CA0 delay=42 (12~72),Diff = 5 PI (16 cell)
8293 22:14:44.693169 CA1 delay=42 (12~72),Diff = 5 PI (16 cell)
8294 22:14:44.696699 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8295 22:14:44.700059 CA3 delay=37 (8~67),Diff = 0 PI (0 cell)
8296 22:14:44.703359 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
8297 22:14:44.706622 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
8298 22:14:44.706719
8299 22:14:44.709920 CA PerBit enable=1, Macro0, CA PI delay=37
8300 22:14:44.710005
8301 22:14:44.713687 [CBTSetCACLKResult] CA Dly = 37
8302 22:14:44.716526 CS Dly: 8 (0~39)
8303 22:14:44.720312 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8304 22:14:44.723705 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8305 22:14:44.723799 ==
8306 22:14:44.727033 Dram Type= 6, Freq= 0, CH_1, rank 1
8307 22:14:44.730807 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8308 22:14:44.731240 ==
8309 22:14:44.736630 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8310 22:14:44.739975 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8311 22:14:44.747148 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8312 22:14:44.749535 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8313 22:14:44.760089 [CA 0] Center 42 (13~72) winsize 60
8314 22:14:44.763426 [CA 1] Center 42 (12~72) winsize 61
8315 22:14:44.766575 [CA 2] Center 38 (9~68) winsize 60
8316 22:14:44.769750 [CA 3] Center 37 (8~67) winsize 60
8317 22:14:44.773147 [CA 4] Center 38 (9~67) winsize 59
8318 22:14:44.776540 [CA 5] Center 37 (8~67) winsize 60
8319 22:14:44.776622
8320 22:14:44.779562 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8321 22:14:44.779672
8322 22:14:44.782934 [CATrainingPosCal] consider 2 rank data
8323 22:14:44.786435 u2DelayCellTimex100 = 290/100 ps
8324 22:14:44.793025 CA0 delay=42 (13~72),Diff = 5 PI (16 cell)
8325 22:14:44.796255 CA1 delay=42 (12~72),Diff = 5 PI (16 cell)
8326 22:14:44.799580 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8327 22:14:44.802961 CA3 delay=37 (8~67),Diff = 0 PI (0 cell)
8328 22:14:44.806532 CA4 delay=38 (9~67),Diff = 1 PI (3 cell)
8329 22:14:44.809917 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8330 22:14:44.809998
8331 22:14:44.813017 CA PerBit enable=1, Macro0, CA PI delay=37
8332 22:14:44.813116
8333 22:14:44.816244 [CBTSetCACLKResult] CA Dly = 37
8334 22:14:44.819571 CS Dly: 9 (0~41)
8335 22:14:44.822709 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8336 22:14:44.825985 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8337 22:14:44.826066
8338 22:14:44.829196 ----->DramcWriteLeveling(PI) begin...
8339 22:14:44.829278 ==
8340 22:14:44.832636 Dram Type= 6, Freq= 0, CH_1, rank 0
8341 22:14:44.839320 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8342 22:14:44.839408 ==
8343 22:14:44.842802 Write leveling (Byte 0): 26 => 26
8344 22:14:44.842897 Write leveling (Byte 1): 28 => 28
8345 22:14:44.846017 DramcWriteLeveling(PI) end<-----
8346 22:14:44.846110
8347 22:14:44.846185 ==
8348 22:14:44.849448 Dram Type= 6, Freq= 0, CH_1, rank 0
8349 22:14:44.855957 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8350 22:14:44.856051 ==
8351 22:14:44.858953 [Gating] SW mode calibration
8352 22:14:44.865637 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8353 22:14:44.868952 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8354 22:14:44.875478 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8355 22:14:44.879001 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8356 22:14:44.882516 1 4 8 | B1->B0 | 2525 3030 | 0 0 | (0 0) (0 0)
8357 22:14:44.888625 1 4 12 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
8358 22:14:44.892229 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8359 22:14:44.895816 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8360 22:14:44.902194 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8361 22:14:44.905469 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8362 22:14:44.909085 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8363 22:14:44.915625 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8364 22:14:44.918760 1 5 8 | B1->B0 | 2f2f 2929 | 0 0 | (0 0) (1 0)
8365 22:14:44.921832 1 5 12 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
8366 22:14:44.929173 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8367 22:14:44.932088 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8368 22:14:44.935142 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8369 22:14:44.941579 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8370 22:14:44.944747 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8371 22:14:44.948140 1 6 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
8372 22:14:44.954881 1 6 8 | B1->B0 | 2727 3f3f | 0 0 | (0 0) (0 0)
8373 22:14:44.958166 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8374 22:14:44.961752 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8375 22:14:44.968283 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8376 22:14:44.971373 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8377 22:14:44.974582 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8378 22:14:44.981106 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8379 22:14:44.984554 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8380 22:14:44.987887 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8381 22:14:44.994462 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8382 22:14:44.997978 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8383 22:14:45.001248 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8384 22:14:45.007768 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8385 22:14:45.011164 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8386 22:14:45.014314 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8387 22:14:45.020753 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8388 22:14:45.024153 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8389 22:14:45.027489 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8390 22:14:45.033912 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8391 22:14:45.037095 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8392 22:14:45.041093 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8393 22:14:45.047141 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8394 22:14:45.050661 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8395 22:14:45.054195 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8396 22:14:45.060345 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8397 22:14:45.063893 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8398 22:14:45.066904 Total UI for P1: 0, mck2ui 16
8399 22:14:45.070188 best dqsien dly found for B0: ( 1, 9, 8)
8400 22:14:45.073533 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8401 22:14:45.080367 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8402 22:14:45.080457 Total UI for P1: 0, mck2ui 16
8403 22:14:45.086733 best dqsien dly found for B1: ( 1, 9, 12)
8404 22:14:45.090017 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8405 22:14:45.093444 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8406 22:14:45.093541
8407 22:14:45.096907 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8408 22:14:45.100235 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8409 22:14:45.103433 [Gating] SW calibration Done
8410 22:14:45.103863 ==
8411 22:14:45.106557 Dram Type= 6, Freq= 0, CH_1, rank 0
8412 22:14:45.110075 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8413 22:14:45.110505 ==
8414 22:14:45.113463 RX Vref Scan: 0
8415 22:14:45.113890
8416 22:14:45.114231 RX Vref 0 -> 0, step: 1
8417 22:14:45.114549
8418 22:14:45.116539 RX Delay 0 -> 252, step: 8
8419 22:14:45.119796 iDelay=200, Bit 0, Center 139 (96 ~ 183) 88
8420 22:14:45.126476 iDelay=200, Bit 1, Center 135 (88 ~ 183) 96
8421 22:14:45.129699 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8422 22:14:45.133148 iDelay=200, Bit 3, Center 139 (88 ~ 191) 104
8423 22:14:45.136312 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8424 22:14:45.140479 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8425 22:14:45.146415 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8426 22:14:45.149337 iDelay=200, Bit 7, Center 135 (88 ~ 183) 96
8427 22:14:45.152732 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8428 22:14:45.156389 iDelay=200, Bit 9, Center 119 (72 ~ 167) 96
8429 22:14:45.159643 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8430 22:14:45.166491 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8431 22:14:45.169260 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8432 22:14:45.172621 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8433 22:14:45.176256 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8434 22:14:45.182425 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8435 22:14:45.182510 ==
8436 22:14:45.185668 Dram Type= 6, Freq= 0, CH_1, rank 0
8437 22:14:45.188963 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8438 22:14:45.189050 ==
8439 22:14:45.189116 DQS Delay:
8440 22:14:45.192322 DQS0 = 0, DQS1 = 0
8441 22:14:45.192406 DQM Delay:
8442 22:14:45.195807 DQM0 = 137, DQM1 = 129
8443 22:14:45.195891 DQ Delay:
8444 22:14:45.199031 DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =139
8445 22:14:45.202392 DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =135
8446 22:14:45.205740 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
8447 22:14:45.208945 DQ12 =139, DQ13 =135, DQ14 =135, DQ15 =135
8448 22:14:45.209029
8449 22:14:45.209095
8450 22:14:45.212221 ==
8451 22:14:45.212305 Dram Type= 6, Freq= 0, CH_1, rank 0
8452 22:14:45.219146 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8453 22:14:45.219231 ==
8454 22:14:45.219298
8455 22:14:45.219361
8456 22:14:45.221940 TX Vref Scan disable
8457 22:14:45.222024 == TX Byte 0 ==
8458 22:14:45.225457 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8459 22:14:45.232063 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8460 22:14:45.232148 == TX Byte 1 ==
8461 22:14:45.235625 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8462 22:14:45.242289 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8463 22:14:45.242374 ==
8464 22:14:45.245593 Dram Type= 6, Freq= 0, CH_1, rank 0
8465 22:14:45.248343 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8466 22:14:45.248435 ==
8467 22:14:45.261183
8468 22:14:45.264757 TX Vref early break, caculate TX vref
8469 22:14:45.268138 TX Vref=16, minBit 15, minWin=22, winSum=377
8470 22:14:45.271188 TX Vref=18, minBit 12, minWin=23, winSum=387
8471 22:14:45.274493 TX Vref=20, minBit 15, minWin=23, winSum=394
8472 22:14:45.278251 TX Vref=22, minBit 15, minWin=24, winSum=408
8473 22:14:45.284205 TX Vref=24, minBit 15, minWin=24, winSum=416
8474 22:14:45.287857 TX Vref=26, minBit 15, minWin=25, winSum=421
8475 22:14:45.291132 TX Vref=28, minBit 0, minWin=26, winSum=426
8476 22:14:45.294150 TX Vref=30, minBit 10, minWin=24, winSum=421
8477 22:14:45.297936 TX Vref=32, minBit 10, minWin=24, winSum=413
8478 22:14:45.304908 TX Vref=34, minBit 5, minWin=24, winSum=403
8479 22:14:45.307939 [TxChooseVref] Worse bit 0, Min win 26, Win sum 426, Final Vref 28
8480 22:14:45.308423
8481 22:14:45.311261 Final TX Range 0 Vref 28
8482 22:14:45.311757
8483 22:14:45.312205 ==
8484 22:14:45.314289 Dram Type= 6, Freq= 0, CH_1, rank 0
8485 22:14:45.317861 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8486 22:14:45.320838 ==
8487 22:14:45.321330
8488 22:14:45.321806
8489 22:14:45.322257 TX Vref Scan disable
8490 22:14:45.327755 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8491 22:14:45.328096 == TX Byte 0 ==
8492 22:14:45.330760 u2DelayCellOfst[0]=13 cells (4 PI)
8493 22:14:45.333972 u2DelayCellOfst[1]=10 cells (3 PI)
8494 22:14:45.337042 u2DelayCellOfst[2]=0 cells (0 PI)
8495 22:14:45.340245 u2DelayCellOfst[3]=3 cells (1 PI)
8496 22:14:45.343883 u2DelayCellOfst[4]=6 cells (2 PI)
8497 22:14:45.347036 u2DelayCellOfst[5]=16 cells (5 PI)
8498 22:14:45.350221 u2DelayCellOfst[6]=16 cells (5 PI)
8499 22:14:45.353500 u2DelayCellOfst[7]=3 cells (1 PI)
8500 22:14:45.356661 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8501 22:14:45.360685 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8502 22:14:45.363198 == TX Byte 1 ==
8503 22:14:45.366432 u2DelayCellOfst[8]=0 cells (0 PI)
8504 22:14:45.369684 u2DelayCellOfst[9]=0 cells (0 PI)
8505 22:14:45.373113 u2DelayCellOfst[10]=10 cells (3 PI)
8506 22:14:45.376323 u2DelayCellOfst[11]=3 cells (1 PI)
8507 22:14:45.379694 u2DelayCellOfst[12]=13 cells (4 PI)
8508 22:14:45.383201 u2DelayCellOfst[13]=13 cells (4 PI)
8509 22:14:45.386626 u2DelayCellOfst[14]=13 cells (4 PI)
8510 22:14:45.390046 u2DelayCellOfst[15]=10 cells (3 PI)
8511 22:14:45.392721 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8512 22:14:45.396055 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8513 22:14:45.399779 DramC Write-DBI on
8514 22:14:45.399897 ==
8515 22:14:45.403066 Dram Type= 6, Freq= 0, CH_1, rank 0
8516 22:14:45.406175 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8517 22:14:45.406294 ==
8518 22:14:45.406388
8519 22:14:45.406475
8520 22:14:45.409536 TX Vref Scan disable
8521 22:14:45.409653 == TX Byte 0 ==
8522 22:14:45.416032 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8523 22:14:45.416151 == TX Byte 1 ==
8524 22:14:45.422799 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8525 22:14:45.422918 DramC Write-DBI off
8526 22:14:45.423011
8527 22:14:45.423098 [DATLAT]
8528 22:14:45.426804 Freq=1600, CH1 RK0
8529 22:14:45.426923
8530 22:14:45.429083 DATLAT Default: 0xf
8531 22:14:45.429201 0, 0xFFFF, sum = 0
8532 22:14:45.433210 1, 0xFFFF, sum = 0
8533 22:14:45.433329 2, 0xFFFF, sum = 0
8534 22:14:45.435949 3, 0xFFFF, sum = 0
8535 22:14:45.436069 4, 0xFFFF, sum = 0
8536 22:14:45.439175 5, 0xFFFF, sum = 0
8537 22:14:45.439295 6, 0xFFFF, sum = 0
8538 22:14:45.442613 7, 0xFFFF, sum = 0
8539 22:14:45.442733 8, 0xFFFF, sum = 0
8540 22:14:45.445635 9, 0xFFFF, sum = 0
8541 22:14:45.445720 10, 0xFFFF, sum = 0
8542 22:14:45.448883 11, 0xFFFF, sum = 0
8543 22:14:45.448968 12, 0xFFFF, sum = 0
8544 22:14:45.452357 13, 0xFFFF, sum = 0
8545 22:14:45.452442 14, 0x0, sum = 1
8546 22:14:45.455494 15, 0x0, sum = 2
8547 22:14:45.455579 16, 0x0, sum = 3
8548 22:14:45.458766 17, 0x0, sum = 4
8549 22:14:45.458850 best_step = 15
8550 22:14:45.458916
8551 22:14:45.458975 ==
8552 22:14:45.462095 Dram Type= 6, Freq= 0, CH_1, rank 0
8553 22:14:45.468553 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8554 22:14:45.468638 ==
8555 22:14:45.468704 RX Vref Scan: 1
8556 22:14:45.468771
8557 22:14:45.472028 Set Vref Range= 24 -> 127
8558 22:14:45.472111
8559 22:14:45.475500 RX Vref 24 -> 127, step: 1
8560 22:14:45.475584
8561 22:14:45.478459 RX Delay 19 -> 252, step: 4
8562 22:14:45.478543
8563 22:14:45.481830 Set Vref, RX VrefLevel [Byte0]: 24
8564 22:14:45.485140 [Byte1]: 24
8565 22:14:45.485223
8566 22:14:45.489074 Set Vref, RX VrefLevel [Byte0]: 25
8567 22:14:45.491978 [Byte1]: 25
8568 22:14:45.492062
8569 22:14:45.495329 Set Vref, RX VrefLevel [Byte0]: 26
8570 22:14:45.498554 [Byte1]: 26
8571 22:14:45.498638
8572 22:14:45.501895 Set Vref, RX VrefLevel [Byte0]: 27
8573 22:14:45.505785 [Byte1]: 27
8574 22:14:45.509135
8575 22:14:45.509292 Set Vref, RX VrefLevel [Byte0]: 28
8576 22:14:45.512820 [Byte1]: 28
8577 22:14:45.516352
8578 22:14:45.516482 Set Vref, RX VrefLevel [Byte0]: 29
8579 22:14:45.519864 [Byte1]: 29
8580 22:14:45.525017
8581 22:14:45.525159 Set Vref, RX VrefLevel [Byte0]: 30
8582 22:14:45.527433 [Byte1]: 30
8583 22:14:45.531564
8584 22:14:45.531709 Set Vref, RX VrefLevel [Byte0]: 31
8585 22:14:45.534975 [Byte1]: 31
8586 22:14:45.539061
8587 22:14:45.539184 Set Vref, RX VrefLevel [Byte0]: 32
8588 22:14:45.542633 [Byte1]: 32
8589 22:14:45.546756
8590 22:14:45.546880 Set Vref, RX VrefLevel [Byte0]: 33
8591 22:14:45.549859 [Byte1]: 33
8592 22:14:45.554242
8593 22:14:45.554373 Set Vref, RX VrefLevel [Byte0]: 34
8594 22:14:45.557423 [Byte1]: 34
8595 22:14:45.561963
8596 22:14:45.562050 Set Vref, RX VrefLevel [Byte0]: 35
8597 22:14:45.565369 [Byte1]: 35
8598 22:14:45.569733
8599 22:14:45.569818 Set Vref, RX VrefLevel [Byte0]: 36
8600 22:14:45.573050 [Byte1]: 36
8601 22:14:45.577320
8602 22:14:45.577404 Set Vref, RX VrefLevel [Byte0]: 37
8603 22:14:45.580555 [Byte1]: 37
8604 22:14:45.584732
8605 22:14:45.584855 Set Vref, RX VrefLevel [Byte0]: 38
8606 22:14:45.588161 [Byte1]: 38
8607 22:14:45.592821
8608 22:14:45.592906 Set Vref, RX VrefLevel [Byte0]: 39
8609 22:14:45.595552 [Byte1]: 39
8610 22:14:45.599965
8611 22:14:45.600053 Set Vref, RX VrefLevel [Byte0]: 40
8612 22:14:45.603108 [Byte1]: 40
8613 22:14:45.607432
8614 22:14:45.607516 Set Vref, RX VrefLevel [Byte0]: 41
8615 22:14:45.611026 [Byte1]: 41
8616 22:14:45.614943
8617 22:14:45.615027 Set Vref, RX VrefLevel [Byte0]: 42
8618 22:14:45.618495 [Byte1]: 42
8619 22:14:45.622602
8620 22:14:45.622685 Set Vref, RX VrefLevel [Byte0]: 43
8621 22:14:45.625699 [Byte1]: 43
8622 22:14:45.630434
8623 22:14:45.630519 Set Vref, RX VrefLevel [Byte0]: 44
8624 22:14:45.633299 [Byte1]: 44
8625 22:14:45.637747
8626 22:14:45.637829 Set Vref, RX VrefLevel [Byte0]: 45
8627 22:14:45.641062 [Byte1]: 45
8628 22:14:45.645355
8629 22:14:45.645439 Set Vref, RX VrefLevel [Byte0]: 46
8630 22:14:45.648501 [Byte1]: 46
8631 22:14:45.652999
8632 22:14:45.653083 Set Vref, RX VrefLevel [Byte0]: 47
8633 22:14:45.656564 [Byte1]: 47
8634 22:14:45.660461
8635 22:14:45.660543 Set Vref, RX VrefLevel [Byte0]: 48
8636 22:14:45.663949 [Byte1]: 48
8637 22:14:45.668431
8638 22:14:45.668515 Set Vref, RX VrefLevel [Byte0]: 49
8639 22:14:45.671221 [Byte1]: 49
8640 22:14:45.675551
8641 22:14:45.675633 Set Vref, RX VrefLevel [Byte0]: 50
8642 22:14:45.679026 [Byte1]: 50
8643 22:14:45.683347
8644 22:14:45.683431 Set Vref, RX VrefLevel [Byte0]: 51
8645 22:14:45.686537 [Byte1]: 51
8646 22:14:45.690557
8647 22:14:45.690649 Set Vref, RX VrefLevel [Byte0]: 52
8648 22:14:45.693935 [Byte1]: 52
8649 22:14:45.698326
8650 22:14:45.698411 Set Vref, RX VrefLevel [Byte0]: 53
8651 22:14:45.701700 [Byte1]: 53
8652 22:14:45.705983
8653 22:14:45.706066 Set Vref, RX VrefLevel [Byte0]: 54
8654 22:14:45.709402 [Byte1]: 54
8655 22:14:45.713227
8656 22:14:45.713337 Set Vref, RX VrefLevel [Byte0]: 55
8657 22:14:45.716557 [Byte1]: 55
8658 22:14:45.721035
8659 22:14:45.721122 Set Vref, RX VrefLevel [Byte0]: 56
8660 22:14:45.724319 [Byte1]: 56
8661 22:14:45.729308
8662 22:14:45.729391 Set Vref, RX VrefLevel [Byte0]: 57
8663 22:14:45.731928 [Byte1]: 57
8664 22:14:45.736422
8665 22:14:45.736505 Set Vref, RX VrefLevel [Byte0]: 58
8666 22:14:45.740020 [Byte1]: 58
8667 22:14:45.743950
8668 22:14:45.744040 Set Vref, RX VrefLevel [Byte0]: 59
8669 22:14:45.747031 [Byte1]: 59
8670 22:14:45.751517
8671 22:14:45.751601 Set Vref, RX VrefLevel [Byte0]: 60
8672 22:14:45.754467 [Byte1]: 60
8673 22:14:45.759122
8674 22:14:45.759206 Set Vref, RX VrefLevel [Byte0]: 61
8675 22:14:45.762160 [Byte1]: 61
8676 22:14:45.766473
8677 22:14:45.766558 Set Vref, RX VrefLevel [Byte0]: 62
8678 22:14:45.769990 [Byte1]: 62
8679 22:14:45.774046
8680 22:14:45.774138 Set Vref, RX VrefLevel [Byte0]: 63
8681 22:14:45.777373 [Byte1]: 63
8682 22:14:45.781683
8683 22:14:45.781808 Set Vref, RX VrefLevel [Byte0]: 64
8684 22:14:45.785303 [Byte1]: 64
8685 22:14:45.789337
8686 22:14:45.792388 Set Vref, RX VrefLevel [Byte0]: 65
8687 22:14:45.795395 [Byte1]: 65
8688 22:14:45.795483
8689 22:14:45.799017 Set Vref, RX VrefLevel [Byte0]: 66
8690 22:14:45.802131 [Byte1]: 66
8691 22:14:45.802217
8692 22:14:45.805309 Set Vref, RX VrefLevel [Byte0]: 67
8693 22:14:45.808698 [Byte1]: 67
8694 22:14:45.808819
8695 22:14:45.811888 Set Vref, RX VrefLevel [Byte0]: 68
8696 22:14:45.815301 [Byte1]: 68
8697 22:14:45.819581
8698 22:14:45.819666 Set Vref, RX VrefLevel [Byte0]: 69
8699 22:14:45.823139 [Byte1]: 69
8700 22:14:45.827005
8701 22:14:45.827090 Set Vref, RX VrefLevel [Byte0]: 70
8702 22:14:45.830218 [Byte1]: 70
8703 22:14:45.834641
8704 22:14:45.834723 Set Vref, RX VrefLevel [Byte0]: 71
8705 22:14:45.838049 [Byte1]: 71
8706 22:14:45.842269
8707 22:14:45.842351 Set Vref, RX VrefLevel [Byte0]: 72
8708 22:14:45.846126 [Byte1]: 72
8709 22:14:45.849994
8710 22:14:45.850076 Set Vref, RX VrefLevel [Byte0]: 73
8711 22:14:45.853206 [Byte1]: 73
8712 22:14:45.857442
8713 22:14:45.857525 Set Vref, RX VrefLevel [Byte0]: 74
8714 22:14:45.860761 [Byte1]: 74
8715 22:14:45.864731
8716 22:14:45.864868 Set Vref, RX VrefLevel [Byte0]: 75
8717 22:14:45.868198 [Byte1]: 75
8718 22:14:45.872450
8719 22:14:45.872532 Set Vref, RX VrefLevel [Byte0]: 76
8720 22:14:45.875758 [Byte1]: 76
8721 22:14:45.880634
8722 22:14:45.880732 Set Vref, RX VrefLevel [Byte0]: 77
8723 22:14:45.883620 [Byte1]: 77
8724 22:14:45.887861
8725 22:14:45.887959 Final RX Vref Byte 0 = 53 to rank0
8726 22:14:45.890868 Final RX Vref Byte 1 = 63 to rank0
8727 22:14:45.894254 Final RX Vref Byte 0 = 53 to rank1
8728 22:14:45.897602 Final RX Vref Byte 1 = 63 to rank1==
8729 22:14:45.900817 Dram Type= 6, Freq= 0, CH_1, rank 0
8730 22:14:45.907253 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8731 22:14:45.907337 ==
8732 22:14:45.907405 DQS Delay:
8733 22:14:45.910703 DQS0 = 0, DQS1 = 0
8734 22:14:45.910787 DQM Delay:
8735 22:14:45.910854 DQM0 = 133, DQM1 = 129
8736 22:14:45.914067 DQ Delay:
8737 22:14:45.917724 DQ0 =136, DQ1 =130, DQ2 =122, DQ3 =132
8738 22:14:45.920579 DQ4 =132, DQ5 =144, DQ6 =144, DQ7 =130
8739 22:14:45.924002 DQ8 =116, DQ9 =118, DQ10 =134, DQ11 =122
8740 22:14:45.927195 DQ12 =138, DQ13 =134, DQ14 =136, DQ15 =134
8741 22:14:45.927279
8742 22:14:45.927345
8743 22:14:45.927405
8744 22:14:45.930894 [DramC_TX_OE_Calibration] TA2
8745 22:14:45.933696 Original DQ_B0 (3 6) =30, OEN = 27
8746 22:14:45.937153 Original DQ_B1 (3 6) =30, OEN = 27
8747 22:14:45.940333 24, 0x0, End_B0=24 End_B1=24
8748 22:14:45.940418 25, 0x0, End_B0=25 End_B1=25
8749 22:14:45.943679 26, 0x0, End_B0=26 End_B1=26
8750 22:14:45.947204 27, 0x0, End_B0=27 End_B1=27
8751 22:14:45.950387 28, 0x0, End_B0=28 End_B1=28
8752 22:14:45.953624 29, 0x0, End_B0=29 End_B1=29
8753 22:14:45.953709 30, 0x0, End_B0=30 End_B1=30
8754 22:14:45.956987 31, 0x4141, End_B0=30 End_B1=30
8755 22:14:45.960538 Byte0 end_step=30 best_step=27
8756 22:14:45.963364 Byte1 end_step=30 best_step=27
8757 22:14:45.966691 Byte0 TX OE(2T, 0.5T) = (3, 3)
8758 22:14:45.970087 Byte1 TX OE(2T, 0.5T) = (3, 3)
8759 22:14:45.970216
8760 22:14:45.970312
8761 22:14:45.977127 [DQSOSCAuto] RK0, (LSB)MR18= 0x1a28, (MSB)MR19= 0x303, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps
8762 22:14:45.979836 CH1 RK0: MR19=303, MR18=1A28
8763 22:14:45.986775 CH1_RK0: MR19=0x303, MR18=0x1A28, DQSOSC=389, MR23=63, INC=24, DEC=16
8764 22:14:45.986860
8765 22:14:45.989897 ----->DramcWriteLeveling(PI) begin...
8766 22:14:45.989982 ==
8767 22:14:45.993434 Dram Type= 6, Freq= 0, CH_1, rank 1
8768 22:14:45.996521 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8769 22:14:45.996605 ==
8770 22:14:45.999590 Write leveling (Byte 0): 23 => 23
8771 22:14:46.003248 Write leveling (Byte 1): 28 => 28
8772 22:14:46.006349 DramcWriteLeveling(PI) end<-----
8773 22:14:46.006452
8774 22:14:46.006521 ==
8775 22:14:46.009744 Dram Type= 6, Freq= 0, CH_1, rank 1
8776 22:14:46.012883 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8777 22:14:46.016117 ==
8778 22:14:46.016201 [Gating] SW mode calibration
8779 22:14:46.026120 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8780 22:14:46.029433 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8781 22:14:46.032656 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8782 22:14:46.039252 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8783 22:14:46.042655 1 4 8 | B1->B0 | 2b2b 2323 | 0 0 | (0 0) (0 0)
8784 22:14:46.046281 1 4 12 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 0)
8785 22:14:46.052724 1 4 16 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
8786 22:14:46.055972 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8787 22:14:46.059223 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8788 22:14:46.065621 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8789 22:14:46.068975 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8790 22:14:46.072322 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8791 22:14:46.079187 1 5 8 | B1->B0 | 3030 3434 | 1 1 | (1 0) (1 0)
8792 22:14:46.082314 1 5 12 | B1->B0 | 2323 3030 | 0 0 | (1 0) (0 0)
8793 22:14:46.085536 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8794 22:14:46.092790 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8795 22:14:46.095498 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8796 22:14:46.098856 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8797 22:14:46.105523 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8798 22:14:46.108836 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8799 22:14:46.112164 1 6 8 | B1->B0 | 3939 2323 | 0 0 | (0 0) (0 0)
8800 22:14:46.118790 1 6 12 | B1->B0 | 4646 3232 | 0 0 | (0 0) (0 0)
8801 22:14:46.121838 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8802 22:14:46.125318 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8803 22:14:46.131851 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8804 22:14:46.135051 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8805 22:14:46.138296 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8806 22:14:46.145058 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8807 22:14:46.148505 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8808 22:14:46.151931 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8809 22:14:46.158725 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8810 22:14:46.161813 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8811 22:14:46.164749 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8812 22:14:46.171513 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8813 22:14:46.174743 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8814 22:14:46.178451 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8815 22:14:46.185074 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8816 22:14:46.188094 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8817 22:14:46.191320 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8818 22:14:46.197790 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8819 22:14:46.201116 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8820 22:14:46.204591 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8821 22:14:46.211343 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8822 22:14:46.214494 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8823 22:14:46.217655 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8824 22:14:46.224487 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8825 22:14:46.224571 Total UI for P1: 0, mck2ui 16
8826 22:14:46.230963 best dqsien dly found for B1: ( 1, 9, 8)
8827 22:14:46.234184 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8828 22:14:46.237418 Total UI for P1: 0, mck2ui 16
8829 22:14:46.240700 best dqsien dly found for B0: ( 1, 9, 10)
8830 22:14:46.244224 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8831 22:14:46.247312 best DQS1 dly(MCK, UI, PI) = (1, 9, 8)
8832 22:14:46.247395
8833 22:14:46.250576 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8834 22:14:46.254187 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 8)
8835 22:14:46.257455 [Gating] SW calibration Done
8836 22:14:46.257538 ==
8837 22:14:46.260693 Dram Type= 6, Freq= 0, CH_1, rank 1
8838 22:14:46.264056 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8839 22:14:46.267780 ==
8840 22:14:46.267862 RX Vref Scan: 0
8841 22:14:46.267928
8842 22:14:46.270742 RX Vref 0 -> 0, step: 1
8843 22:14:46.270824
8844 22:14:46.274584 RX Delay 0 -> 252, step: 8
8845 22:14:46.277447 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8846 22:14:46.280358 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8847 22:14:46.283561 iDelay=200, Bit 2, Center 127 (80 ~ 175) 96
8848 22:14:46.286910 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8849 22:14:46.290293 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8850 22:14:46.297035 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8851 22:14:46.300067 iDelay=200, Bit 6, Center 143 (96 ~ 191) 96
8852 22:14:46.303493 iDelay=200, Bit 7, Center 139 (88 ~ 191) 104
8853 22:14:46.307525 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8854 22:14:46.310369 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8855 22:14:46.316956 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8856 22:14:46.320168 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8857 22:14:46.323300 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8858 22:14:46.326519 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8859 22:14:46.333264 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8860 22:14:46.336620 iDelay=200, Bit 15, Center 143 (88 ~ 199) 112
8861 22:14:46.336703 ==
8862 22:14:46.340574 Dram Type= 6, Freq= 0, CH_1, rank 1
8863 22:14:46.343156 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8864 22:14:46.343239 ==
8865 22:14:46.346461 DQS Delay:
8866 22:14:46.346543 DQS0 = 0, DQS1 = 0
8867 22:14:46.346610 DQM Delay:
8868 22:14:46.349745 DQM0 = 138, DQM1 = 131
8869 22:14:46.349828 DQ Delay:
8870 22:14:46.353220 DQ0 =143, DQ1 =131, DQ2 =127, DQ3 =135
8871 22:14:46.356244 DQ4 =139, DQ5 =147, DQ6 =143, DQ7 =139
8872 22:14:46.362910 DQ8 =115, DQ9 =119, DQ10 =131, DQ11 =127
8873 22:14:46.366067 DQ12 =135, DQ13 =143, DQ14 =139, DQ15 =143
8874 22:14:46.366150
8875 22:14:46.366215
8876 22:14:46.366275 ==
8877 22:14:46.369677 Dram Type= 6, Freq= 0, CH_1, rank 1
8878 22:14:46.372777 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8879 22:14:46.372872 ==
8880 22:14:46.372938
8881 22:14:46.372997
8882 22:14:46.376072 TX Vref Scan disable
8883 22:14:46.376155 == TX Byte 0 ==
8884 22:14:46.382633 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8885 22:14:46.386384 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8886 22:14:46.389461 == TX Byte 1 ==
8887 22:14:46.392492 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8888 22:14:46.395921 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8889 22:14:46.396004 ==
8890 22:14:46.399155 Dram Type= 6, Freq= 0, CH_1, rank 1
8891 22:14:46.402630 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8892 22:14:46.405865 ==
8893 22:14:46.417132
8894 22:14:46.420707 TX Vref early break, caculate TX vref
8895 22:14:46.423527 TX Vref=16, minBit 13, minWin=22, winSum=385
8896 22:14:46.427060 TX Vref=18, minBit 15, minWin=23, winSum=392
8897 22:14:46.430739 TX Vref=20, minBit 13, minWin=24, winSum=407
8898 22:14:46.433521 TX Vref=22, minBit 9, minWin=25, winSum=418
8899 22:14:46.439987 TX Vref=24, minBit 9, minWin=25, winSum=420
8900 22:14:46.443272 TX Vref=26, minBit 13, minWin=25, winSum=429
8901 22:14:46.446575 TX Vref=28, minBit 0, minWin=26, winSum=427
8902 22:14:46.449849 TX Vref=30, minBit 0, minWin=26, winSum=420
8903 22:14:46.453501 TX Vref=32, minBit 0, minWin=25, winSum=415
8904 22:14:46.456581 TX Vref=34, minBit 10, minWin=24, winSum=405
8905 22:14:46.463057 [TxChooseVref] Worse bit 0, Min win 26, Win sum 427, Final Vref 28
8906 22:14:46.463140
8907 22:14:46.466421 Final TX Range 0 Vref 28
8908 22:14:46.466504
8909 22:14:46.466569 ==
8910 22:14:46.470119 Dram Type= 6, Freq= 0, CH_1, rank 1
8911 22:14:46.472996 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8912 22:14:46.473079 ==
8913 22:14:46.473145
8914 22:14:46.473204
8915 22:14:46.476488 TX Vref Scan disable
8916 22:14:46.482936 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8917 22:14:46.483018 == TX Byte 0 ==
8918 22:14:46.486308 u2DelayCellOfst[0]=16 cells (5 PI)
8919 22:14:46.490178 u2DelayCellOfst[1]=10 cells (3 PI)
8920 22:14:46.493070 u2DelayCellOfst[2]=0 cells (0 PI)
8921 22:14:46.496087 u2DelayCellOfst[3]=3 cells (1 PI)
8922 22:14:46.499476 u2DelayCellOfst[4]=6 cells (2 PI)
8923 22:14:46.502892 u2DelayCellOfst[5]=16 cells (5 PI)
8924 22:14:46.506366 u2DelayCellOfst[6]=16 cells (5 PI)
8925 22:14:46.509479 u2DelayCellOfst[7]=3 cells (1 PI)
8926 22:14:46.512968 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8927 22:14:46.516245 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8928 22:14:46.519409 == TX Byte 1 ==
8929 22:14:46.522887 u2DelayCellOfst[8]=0 cells (0 PI)
8930 22:14:46.526303 u2DelayCellOfst[9]=3 cells (1 PI)
8931 22:14:46.526385 u2DelayCellOfst[10]=6 cells (2 PI)
8932 22:14:46.529359 u2DelayCellOfst[11]=3 cells (1 PI)
8933 22:14:46.532406 u2DelayCellOfst[12]=13 cells (4 PI)
8934 22:14:46.535954 u2DelayCellOfst[13]=13 cells (4 PI)
8935 22:14:46.539445 u2DelayCellOfst[14]=16 cells (5 PI)
8936 22:14:46.542344 u2DelayCellOfst[15]=13 cells (4 PI)
8937 22:14:46.549145 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8938 22:14:46.552988 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8939 22:14:46.553087 DramC Write-DBI on
8940 22:14:46.553155 ==
8941 22:14:46.555536 Dram Type= 6, Freq= 0, CH_1, rank 1
8942 22:14:46.562025 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8943 22:14:46.562108 ==
8944 22:14:46.562173
8945 22:14:46.562235
8946 22:14:46.565382 TX Vref Scan disable
8947 22:14:46.565465 == TX Byte 0 ==
8948 22:14:46.572079 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
8949 22:14:46.572162 == TX Byte 1 ==
8950 22:14:46.575305 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8951 22:14:46.578864 DramC Write-DBI off
8952 22:14:46.578946
8953 22:14:46.579012 [DATLAT]
8954 22:14:46.581992 Freq=1600, CH1 RK1
8955 22:14:46.582075
8956 22:14:46.582140 DATLAT Default: 0xf
8957 22:14:46.585032 0, 0xFFFF, sum = 0
8958 22:14:46.585116 1, 0xFFFF, sum = 0
8959 22:14:46.588252 2, 0xFFFF, sum = 0
8960 22:14:46.588336 3, 0xFFFF, sum = 0
8961 22:14:46.592051 4, 0xFFFF, sum = 0
8962 22:14:46.592135 5, 0xFFFF, sum = 0
8963 22:14:46.595655 6, 0xFFFF, sum = 0
8964 22:14:46.595739 7, 0xFFFF, sum = 0
8965 22:14:46.598439 8, 0xFFFF, sum = 0
8966 22:14:46.602210 9, 0xFFFF, sum = 0
8967 22:14:46.602294 10, 0xFFFF, sum = 0
8968 22:14:46.605497 11, 0xFFFF, sum = 0
8969 22:14:46.605606 12, 0xFFFF, sum = 0
8970 22:14:46.608381 13, 0xFFFF, sum = 0
8971 22:14:46.608465 14, 0x0, sum = 1
8972 22:14:46.612649 15, 0x0, sum = 2
8973 22:14:46.612735 16, 0x0, sum = 3
8974 22:14:46.614922 17, 0x0, sum = 4
8975 22:14:46.615006 best_step = 15
8976 22:14:46.615071
8977 22:14:46.615155 ==
8978 22:14:46.618070 Dram Type= 6, Freq= 0, CH_1, rank 1
8979 22:14:46.621544 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8980 22:14:46.624740 ==
8981 22:14:46.624843 RX Vref Scan: 0
8982 22:14:46.624910
8983 22:14:46.627839 RX Vref 0 -> 0, step: 1
8984 22:14:46.627922
8985 22:14:46.627987 RX Delay 19 -> 252, step: 4
8986 22:14:46.635397 iDelay=195, Bit 0, Center 138 (95 ~ 182) 88
8987 22:14:46.638814 iDelay=195, Bit 1, Center 130 (83 ~ 178) 96
8988 22:14:46.641882 iDelay=195, Bit 2, Center 122 (75 ~ 170) 96
8989 22:14:46.645132 iDelay=195, Bit 3, Center 130 (83 ~ 178) 96
8990 22:14:46.648673 iDelay=195, Bit 4, Center 134 (87 ~ 182) 96
8991 22:14:46.654996 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
8992 22:14:46.658406 iDelay=195, Bit 6, Center 142 (95 ~ 190) 96
8993 22:14:46.661879 iDelay=195, Bit 7, Center 130 (83 ~ 178) 96
8994 22:14:46.664942 iDelay=195, Bit 8, Center 112 (63 ~ 162) 100
8995 22:14:46.668459 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8996 22:14:46.674825 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
8997 22:14:46.678575 iDelay=195, Bit 11, Center 124 (71 ~ 178) 108
8998 22:14:46.681335 iDelay=195, Bit 12, Center 138 (87 ~ 190) 104
8999 22:14:46.684804 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
9000 22:14:46.688160 iDelay=195, Bit 14, Center 138 (91 ~ 186) 96
9001 22:14:46.694651 iDelay=195, Bit 15, Center 140 (87 ~ 194) 108
9002 22:14:46.694734 ==
9003 22:14:46.698181 Dram Type= 6, Freq= 0, CH_1, rank 1
9004 22:14:46.701715 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9005 22:14:46.701799 ==
9006 22:14:46.701865 DQS Delay:
9007 22:14:46.704522 DQS0 = 0, DQS1 = 0
9008 22:14:46.704624 DQM Delay:
9009 22:14:46.708022 DQM0 = 134, DQM1 = 129
9010 22:14:46.708106 DQ Delay:
9011 22:14:46.711603 DQ0 =138, DQ1 =130, DQ2 =122, DQ3 =130
9012 22:14:46.714544 DQ4 =134, DQ5 =146, DQ6 =142, DQ7 =130
9013 22:14:46.717804 DQ8 =112, DQ9 =118, DQ10 =128, DQ11 =124
9014 22:14:46.721258 DQ12 =138, DQ13 =138, DQ14 =138, DQ15 =140
9015 22:14:46.724609
9016 22:14:46.724692
9017 22:14:46.724758
9018 22:14:46.724859 [DramC_TX_OE_Calibration] TA2
9019 22:14:46.727845 Original DQ_B0 (3 6) =30, OEN = 27
9020 22:14:46.730930 Original DQ_B1 (3 6) =30, OEN = 27
9021 22:14:46.734407 24, 0x0, End_B0=24 End_B1=24
9022 22:14:46.737735 25, 0x0, End_B0=25 End_B1=25
9023 22:14:46.741060 26, 0x0, End_B0=26 End_B1=26
9024 22:14:46.741146 27, 0x0, End_B0=27 End_B1=27
9025 22:14:46.745014 28, 0x0, End_B0=28 End_B1=28
9026 22:14:46.747525 29, 0x0, End_B0=29 End_B1=29
9027 22:14:46.751376 30, 0x0, End_B0=30 End_B1=30
9028 22:14:46.754226 31, 0x4141, End_B0=30 End_B1=30
9029 22:14:46.757839 Byte0 end_step=30 best_step=27
9030 22:14:46.757923 Byte1 end_step=30 best_step=27
9031 22:14:46.760696 Byte0 TX OE(2T, 0.5T) = (3, 3)
9032 22:14:46.764972 Byte1 TX OE(2T, 0.5T) = (3, 3)
9033 22:14:46.765056
9034 22:14:46.765122
9035 22:14:46.773886 [DQSOSCAuto] RK1, (LSB)MR18= 0x1b07, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 396 ps
9036 22:14:46.773972 CH1 RK1: MR19=303, MR18=1B07
9037 22:14:46.780347 CH1_RK1: MR19=0x303, MR18=0x1B07, DQSOSC=396, MR23=63, INC=23, DEC=15
9038 22:14:46.783732 [RxdqsGatingPostProcess] freq 1600
9039 22:14:46.790382 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9040 22:14:46.793550 best DQS0 dly(2T, 0.5T) = (1, 1)
9041 22:14:46.796925 best DQS1 dly(2T, 0.5T) = (1, 1)
9042 22:14:46.800439 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9043 22:14:46.803583 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9044 22:14:46.806899 best DQS0 dly(2T, 0.5T) = (1, 1)
9045 22:14:46.806982 best DQS1 dly(2T, 0.5T) = (1, 1)
9046 22:14:46.809775 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9047 22:14:46.813141 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9048 22:14:46.816442 Pre-setting of DQS Precalculation
9049 22:14:46.823087 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9050 22:14:46.830553 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9051 22:14:46.836374 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9052 22:14:46.836458
9053 22:14:46.836524
9054 22:14:46.839839 [Calibration Summary] 3200 Mbps
9055 22:14:46.839922 CH 0, Rank 0
9056 22:14:46.843112 SW Impedance : PASS
9057 22:14:46.846288 DUTY Scan : NO K
9058 22:14:46.846372 ZQ Calibration : PASS
9059 22:14:46.849634 Jitter Meter : NO K
9060 22:14:46.853044 CBT Training : PASS
9061 22:14:46.853128 Write leveling : PASS
9062 22:14:46.856383 RX DQS gating : PASS
9063 22:14:46.859579 RX DQ/DQS(RDDQC) : PASS
9064 22:14:46.859662 TX DQ/DQS : PASS
9065 22:14:46.862651 RX DATLAT : PASS
9066 22:14:46.865944 RX DQ/DQS(Engine): PASS
9067 22:14:46.866027 TX OE : PASS
9068 22:14:46.869345 All Pass.
9069 22:14:46.869469
9070 22:14:46.869553 CH 0, Rank 1
9071 22:14:46.872692 SW Impedance : PASS
9072 22:14:46.872783 DUTY Scan : NO K
9073 22:14:46.876123 ZQ Calibration : PASS
9074 22:14:46.879238 Jitter Meter : NO K
9075 22:14:46.879322 CBT Training : PASS
9076 22:14:46.882543 Write leveling : PASS
9077 22:14:46.885977 RX DQS gating : PASS
9078 22:14:46.886061 RX DQ/DQS(RDDQC) : PASS
9079 22:14:46.889135 TX DQ/DQS : PASS
9080 22:14:46.892740 RX DATLAT : PASS
9081 22:14:46.892876 RX DQ/DQS(Engine): PASS
9082 22:14:46.895910 TX OE : PASS
9083 22:14:46.895995 All Pass.
9084 22:14:46.896061
9085 22:14:46.899993 CH 1, Rank 0
9086 22:14:46.900076 SW Impedance : PASS
9087 22:14:46.902542 DUTY Scan : NO K
9088 22:14:46.902625 ZQ Calibration : PASS
9089 22:14:46.906421 Jitter Meter : NO K
9090 22:14:46.909361 CBT Training : PASS
9091 22:14:46.909444 Write leveling : PASS
9092 22:14:46.912398 RX DQS gating : PASS
9093 22:14:46.915905 RX DQ/DQS(RDDQC) : PASS
9094 22:14:46.915989 TX DQ/DQS : PASS
9095 22:14:46.918958 RX DATLAT : PASS
9096 22:14:46.922672 RX DQ/DQS(Engine): PASS
9097 22:14:46.922755 TX OE : PASS
9098 22:14:46.925532 All Pass.
9099 22:14:46.925616
9100 22:14:46.925682 CH 1, Rank 1
9101 22:14:46.929194 SW Impedance : PASS
9102 22:14:46.929277 DUTY Scan : NO K
9103 22:14:46.932454 ZQ Calibration : PASS
9104 22:14:46.935744 Jitter Meter : NO K
9105 22:14:46.935828 CBT Training : PASS
9106 22:14:46.938873 Write leveling : PASS
9107 22:14:46.942650 RX DQS gating : PASS
9108 22:14:46.942734 RX DQ/DQS(RDDQC) : PASS
9109 22:14:46.945425 TX DQ/DQS : PASS
9110 22:14:46.949164 RX DATLAT : PASS
9111 22:14:46.949247 RX DQ/DQS(Engine): PASS
9112 22:14:46.952217 TX OE : PASS
9113 22:14:46.952301 All Pass.
9114 22:14:46.952367
9115 22:14:46.955571 DramC Write-DBI on
9116 22:14:46.958929 PER_BANK_REFRESH: Hybrid Mode
9117 22:14:46.959013 TX_TRACKING: ON
9118 22:14:46.968531 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9119 22:14:46.975437 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9120 22:14:46.981614 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9121 22:14:46.985047 [FAST_K] Save calibration result to emmc
9122 22:14:46.988370 sync common calibartion params.
9123 22:14:46.991408 sync cbt_mode0:1, 1:1
9124 22:14:46.994823 dram_init: ddr_geometry: 2
9125 22:14:46.994907 dram_init: ddr_geometry: 2
9126 22:14:46.998384 dram_init: ddr_geometry: 2
9127 22:14:47.001504 0:dram_rank_size:100000000
9128 22:14:47.005043 1:dram_rank_size:100000000
9129 22:14:47.008651 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9130 22:14:47.011489 DFS_SHUFFLE_HW_MODE: ON
9131 22:14:47.014874 dramc_set_vcore_voltage set vcore to 725000
9132 22:14:47.018116 Read voltage for 1600, 0
9133 22:14:47.018199 Vio18 = 0
9134 22:14:47.018264 Vcore = 725000
9135 22:14:47.021641 Vdram = 0
9136 22:14:47.021724 Vddq = 0
9137 22:14:47.021791 Vmddr = 0
9138 22:14:47.024736 switch to 3200 Mbps bootup
9139 22:14:47.028100 [DramcRunTimeConfig]
9140 22:14:47.028184 PHYPLL
9141 22:14:47.028251 DPM_CONTROL_AFTERK: ON
9142 22:14:47.031359 PER_BANK_REFRESH: ON
9143 22:14:47.034468 REFRESH_OVERHEAD_REDUCTION: ON
9144 22:14:47.034551 CMD_PICG_NEW_MODE: OFF
9145 22:14:47.038333 XRTWTW_NEW_MODE: ON
9146 22:14:47.041207 XRTRTR_NEW_MODE: ON
9147 22:14:47.041290 TX_TRACKING: ON
9148 22:14:47.044933 RDSEL_TRACKING: OFF
9149 22:14:47.045016 DQS Precalculation for DVFS: ON
9150 22:14:47.047743 RX_TRACKING: OFF
9151 22:14:47.047826 HW_GATING DBG: ON
9152 22:14:47.051355 ZQCS_ENABLE_LP4: ON
9153 22:14:47.051438 RX_PICG_NEW_MODE: ON
9154 22:14:47.054393 TX_PICG_NEW_MODE: ON
9155 22:14:47.057754 ENABLE_RX_DCM_DPHY: ON
9156 22:14:47.061098 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9157 22:14:47.061182 DUMMY_READ_FOR_TRACKING: OFF
9158 22:14:47.064500 !!! SPM_CONTROL_AFTERK: OFF
9159 22:14:47.067978 !!! SPM could not control APHY
9160 22:14:47.072210 IMPEDANCE_TRACKING: ON
9161 22:14:47.072294 TEMP_SENSOR: ON
9162 22:14:47.074413 HW_SAVE_FOR_SR: OFF
9163 22:14:47.074498 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9164 22:14:47.080983 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9165 22:14:47.081068 Read ODT Tracking: ON
9166 22:14:47.084257 Refresh Rate DeBounce: ON
9167 22:14:47.087483 DFS_NO_QUEUE_FLUSH: ON
9168 22:14:47.090962 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9169 22:14:47.091046 ENABLE_DFS_RUNTIME_MRW: OFF
9170 22:14:47.094502 DDR_RESERVE_NEW_MODE: ON
9171 22:14:47.097344 MR_CBT_SWITCH_FREQ: ON
9172 22:14:47.097428 =========================
9173 22:14:47.117580 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9174 22:14:47.121202 dram_init: ddr_geometry: 2
9175 22:14:47.138599 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9176 22:14:47.142324 dram_init: dram init end (result: 0)
9177 22:14:47.148895 DRAM-K: Full calibration passed in 24521 msecs
9178 22:14:47.152184 MRC: failed to locate region type 0.
9179 22:14:47.152269 DRAM rank0 size:0x100000000,
9180 22:14:47.155096 DRAM rank1 size=0x100000000
9181 22:14:47.165423 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9182 22:14:47.171602 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9183 22:14:47.178212 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9184 22:14:47.184997 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9185 22:14:47.188403 DRAM rank0 size:0x100000000,
9186 22:14:47.191546 DRAM rank1 size=0x100000000
9187 22:14:47.191630 CBMEM:
9188 22:14:47.195075 IMD: root @ 0xfffff000 254 entries.
9189 22:14:47.198245 IMD: root @ 0xffffec00 62 entries.
9190 22:14:47.201950 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9191 22:14:47.208145 WARNING: RO_VPD is uninitialized or empty.
9192 22:14:47.211315 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9193 22:14:47.218938 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9194 22:14:47.231566 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9195 22:14:47.243108 BS: romstage times (exec / console): total (unknown) / 24019 ms
9196 22:14:47.243193
9197 22:14:47.243277
9198 22:14:47.252896 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9199 22:14:47.256080 ARM64: Exception handlers installed.
9200 22:14:47.259553 ARM64: Testing exception
9201 22:14:47.262593 ARM64: Done test exception
9202 22:14:47.262678 Enumerating buses...
9203 22:14:47.266197 Show all devs... Before device enumeration.
9204 22:14:47.269156 Root Device: enabled 1
9205 22:14:47.272406 CPU_CLUSTER: 0: enabled 1
9206 22:14:47.272491 CPU: 00: enabled 1
9207 22:14:47.276157 Compare with tree...
9208 22:14:47.276255 Root Device: enabled 1
9209 22:14:47.278999 CPU_CLUSTER: 0: enabled 1
9210 22:14:47.282398 CPU: 00: enabled 1
9211 22:14:47.282483 Root Device scanning...
9212 22:14:47.285702 scan_static_bus for Root Device
9213 22:14:47.289542 CPU_CLUSTER: 0 enabled
9214 22:14:47.292364 scan_static_bus for Root Device done
9215 22:14:47.295414 scan_bus: bus Root Device finished in 8 msecs
9216 22:14:47.295500 done
9217 22:14:47.301985 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9218 22:14:47.305424 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9219 22:14:47.312293 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9220 22:14:47.318817 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9221 22:14:47.318902 Allocating resources...
9222 22:14:47.321816 Reading resources...
9223 22:14:47.325226 Root Device read_resources bus 0 link: 0
9224 22:14:47.328576 DRAM rank0 size:0x100000000,
9225 22:14:47.328660 DRAM rank1 size=0x100000000
9226 22:14:47.335142 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9227 22:14:47.335228 CPU: 00 missing read_resources
9228 22:14:47.341851 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9229 22:14:47.344982 Root Device read_resources bus 0 link: 0 done
9230 22:14:47.348629 Done reading resources.
9231 22:14:47.351560 Show resources in subtree (Root Device)...After reading.
9232 22:14:47.354871 Root Device child on link 0 CPU_CLUSTER: 0
9233 22:14:47.358228 CPU_CLUSTER: 0 child on link 0 CPU: 00
9234 22:14:47.368273 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9235 22:14:47.368359 CPU: 00
9236 22:14:47.374648 Root Device assign_resources, bus 0 link: 0
9237 22:14:47.378139 CPU_CLUSTER: 0 missing set_resources
9238 22:14:47.381340 Root Device assign_resources, bus 0 link: 0 done
9239 22:14:47.381425 Done setting resources.
9240 22:14:47.387931 Show resources in subtree (Root Device)...After assigning values.
9241 22:14:47.391261 Root Device child on link 0 CPU_CLUSTER: 0
9242 22:14:47.394597 CPU_CLUSTER: 0 child on link 0 CPU: 00
9243 22:14:47.404425 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9244 22:14:47.404508 CPU: 00
9245 22:14:47.408054 Done allocating resources.
9246 22:14:47.414425 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9247 22:14:47.414507 Enabling resources...
9248 22:14:47.417658 done.
9249 22:14:47.421138 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9250 22:14:47.424473 Initializing devices...
9251 22:14:47.424554 Root Device init
9252 22:14:47.427945 init hardware done!
9253 22:14:47.428051 0x00000018: ctrlr->caps
9254 22:14:47.430807 52.000 MHz: ctrlr->f_max
9255 22:14:47.434145 0.400 MHz: ctrlr->f_min
9256 22:14:47.434228 0x40ff8080: ctrlr->voltages
9257 22:14:47.437625 sclk: 390625
9258 22:14:47.437707 Bus Width = 1
9259 22:14:47.440743 sclk: 390625
9260 22:14:47.440858 Bus Width = 1
9261 22:14:47.444431 Early init status = 3
9262 22:14:47.447185 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9263 22:14:47.450536 in-header: 03 fc 00 00 01 00 00 00
9264 22:14:47.453981 in-data: 00
9265 22:14:47.457148 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9266 22:14:47.462138 in-header: 03 fd 00 00 00 00 00 00
9267 22:14:47.465769 in-data:
9268 22:14:47.468525 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9269 22:14:47.473012 in-header: 03 fc 00 00 01 00 00 00
9270 22:14:47.476661 in-data: 00
9271 22:14:47.479478 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9272 22:14:47.485068 in-header: 03 fd 00 00 00 00 00 00
9273 22:14:47.488570 in-data:
9274 22:14:47.491963 [SSUSB] Setting up USB HOST controller...
9275 22:14:47.495398 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9276 22:14:47.498418 [SSUSB] phy power-on done.
9277 22:14:47.501886 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9278 22:14:47.508272 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9279 22:14:47.511615 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9280 22:14:47.518245 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9281 22:14:47.524802 read SPI 0x50eb0 0x2ad3: 1175 us, 9330 KB/s, 74.640 Mbps
9282 22:14:47.531831 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9283 22:14:47.538381 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9284 22:14:47.544722 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9285 22:14:47.548108 SPM: binary array size = 0x9dc
9286 22:14:47.551159 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9287 22:14:47.557843 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9288 22:14:47.564679 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9289 22:14:47.571383 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9290 22:14:47.574072 configure_display: Starting display init
9291 22:14:47.608563 anx7625_power_on_init: Init interface.
9292 22:14:47.612120 anx7625_disable_pd_protocol: Disabled PD feature.
9293 22:14:47.615120 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9294 22:14:47.642821 anx7625_start_dp_work: Secure OCM version=00
9295 22:14:47.645954 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9296 22:14:47.661198 sp_tx_get_edid_block: EDID Block = 1
9297 22:14:47.763191 Extracted contents:
9298 22:14:47.767228 header: 00 ff ff ff ff ff ff 00
9299 22:14:47.769866 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9300 22:14:47.773516 version: 01 04
9301 22:14:47.776612 basic params: 95 1f 11 78 0a
9302 22:14:47.780018 chroma info: 76 90 94 55 54 90 27 21 50 54
9303 22:14:47.783066 established: 00 00 00
9304 22:14:47.789839 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9305 22:14:47.792976 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9306 22:14:47.799760 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9307 22:14:47.806210 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9308 22:14:47.813187 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9309 22:14:47.816271 extensions: 00
9310 22:14:47.816351 checksum: fb
9311 22:14:47.816414
9312 22:14:47.819505 Manufacturer: IVO Model 57d Serial Number 0
9313 22:14:47.822942 Made week 0 of 2020
9314 22:14:47.826572 EDID version: 1.4
9315 22:14:47.826653 Digital display
9316 22:14:47.829512 6 bits per primary color channel
9317 22:14:47.829596 DisplayPort interface
9318 22:14:47.832852 Maximum image size: 31 cm x 17 cm
9319 22:14:47.836128 Gamma: 220%
9320 22:14:47.836208 Check DPMS levels
9321 22:14:47.839506 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9322 22:14:47.846473 First detailed timing is preferred timing
9323 22:14:47.846554 Established timings supported:
9324 22:14:47.849353 Standard timings supported:
9325 22:14:47.852367 Detailed timings
9326 22:14:47.855833 Hex of detail: 383680a07038204018303c0035ae10000019
9327 22:14:47.862694 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9328 22:14:47.865662 0780 0798 07c8 0820 hborder 0
9329 22:14:47.869545 0438 043b 0447 0458 vborder 0
9330 22:14:47.873020 -hsync -vsync
9331 22:14:47.873101 Did detailed timing
9332 22:14:47.879513 Hex of detail: 000000000000000000000000000000000000
9333 22:14:47.882544 Manufacturer-specified data, tag 0
9334 22:14:47.886369 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9335 22:14:47.888963 ASCII string: InfoVision
9336 22:14:47.892519 Hex of detail: 000000fe00523134304e574635205248200a
9337 22:14:47.895948 ASCII string: R140NWF5 RH
9338 22:14:47.896029 Checksum
9339 22:14:47.899174 Checksum: 0xfb (valid)
9340 22:14:47.902558 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9341 22:14:47.905452 DSI data_rate: 832800000 bps
9342 22:14:47.912465 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9343 22:14:47.915559 anx7625_parse_edid: pixelclock(138800).
9344 22:14:47.918595 hactive(1920), hsync(48), hfp(24), hbp(88)
9345 22:14:47.922176 vactive(1080), vsync(12), vfp(3), vbp(17)
9346 22:14:47.925498 anx7625_dsi_config: config dsi.
9347 22:14:47.931935 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9348 22:14:47.945422 anx7625_dsi_config: success to config DSI
9349 22:14:47.948893 anx7625_dp_start: MIPI phy setup OK.
9350 22:14:47.952128 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9351 22:14:47.955884 mtk_ddp_mode_set invalid vrefresh 60
9352 22:14:47.958436 main_disp_path_setup
9353 22:14:47.958518 ovl_layer_smi_id_en
9354 22:14:47.961705 ovl_layer_smi_id_en
9355 22:14:47.961788 ccorr_config
9356 22:14:47.961855 aal_config
9357 22:14:47.965245 gamma_config
9358 22:14:47.965327 postmask_config
9359 22:14:47.968266 dither_config
9360 22:14:47.971738 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9361 22:14:47.978436 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9362 22:14:47.981438 Root Device init finished in 553 msecs
9363 22:14:47.984774 CPU_CLUSTER: 0 init
9364 22:14:47.991790 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9365 22:14:47.998192 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9366 22:14:47.998275 APU_MBOX 0x190000b0 = 0x10001
9367 22:14:48.002004 APU_MBOX 0x190001b0 = 0x10001
9368 22:14:48.004655 APU_MBOX 0x190005b0 = 0x10001
9369 22:14:48.008132 APU_MBOX 0x190006b0 = 0x10001
9370 22:14:48.014746 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9371 22:14:48.024340 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9372 22:14:48.036713 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9373 22:14:48.043304 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9374 22:14:48.055333 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9375 22:14:48.064459 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9376 22:14:48.067428 CPU_CLUSTER: 0 init finished in 81 msecs
9377 22:14:48.070873 Devices initialized
9378 22:14:48.074165 Show all devs... After init.
9379 22:14:48.074248 Root Device: enabled 1
9380 22:14:48.077226 CPU_CLUSTER: 0: enabled 1
9381 22:14:48.080677 CPU: 00: enabled 1
9382 22:14:48.084223 BS: BS_DEV_INIT run times (exec / console): 211 / 447 ms
9383 22:14:48.087309 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9384 22:14:48.090407 ELOG: NV offset 0x57f000 size 0x1000
9385 22:14:48.097417 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9386 22:14:48.104929 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9387 22:14:48.107385 ELOG: Event(17) added with size 13 at 2023-06-05 22:14:50 UTC
9388 22:14:48.114076 out: cmd=0x121: 03 db 21 01 00 00 00 00
9389 22:14:48.117105 in-header: 03 1d 00 00 2c 00 00 00
9390 22:14:48.126989 in-data: 42 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9391 22:14:48.133909 ELOG: Event(A1) added with size 10 at 2023-06-05 22:14:50 UTC
9392 22:14:48.140076 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9393 22:14:48.146920 ELOG: Event(A0) added with size 9 at 2023-06-05 22:14:50 UTC
9394 22:14:48.150049 elog_add_boot_reason: Logged dev mode boot
9395 22:14:48.156612 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9396 22:14:48.156721 Finalize devices...
9397 22:14:48.160033 Devices finalized
9398 22:14:48.163216 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9399 22:14:48.166641 Writing coreboot table at 0xffe64000
9400 22:14:48.170610 0. 000000000010a000-0000000000113fff: RAMSTAGE
9401 22:14:48.176382 1. 0000000040000000-00000000400fffff: RAM
9402 22:14:48.179996 2. 0000000040100000-000000004032afff: RAMSTAGE
9403 22:14:48.182975 3. 000000004032b000-00000000545fffff: RAM
9404 22:14:48.186280 4. 0000000054600000-000000005465ffff: BL31
9405 22:14:48.189877 5. 0000000054660000-00000000ffe63fff: RAM
9406 22:14:48.196269 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9407 22:14:48.199959 7. 0000000100000000-000000023fffffff: RAM
9408 22:14:48.202995 Passing 5 GPIOs to payload:
9409 22:14:48.206318 NAME | PORT | POLARITY | VALUE
9410 22:14:48.213246 EC in RW | 0x000000aa | low | undefined
9411 22:14:48.216273 EC interrupt | 0x00000005 | low | undefined
9412 22:14:48.219515 TPM interrupt | 0x000000ab | high | undefined
9413 22:14:48.226201 SD card detect | 0x00000011 | high | undefined
9414 22:14:48.229370 speaker enable | 0x00000093 | high | undefined
9415 22:14:48.232727 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9416 22:14:48.236043 in-header: 03 f9 00 00 02 00 00 00
9417 22:14:48.239451 in-data: 02 00
9418 22:14:48.242724 ADC[4]: Raw value=901401 ID=7
9419 22:14:48.242807 ADC[3]: Raw value=213179 ID=1
9420 22:14:48.246233 RAM Code: 0x71
9421 22:14:48.249619 ADC[6]: Raw value=74502 ID=0
9422 22:14:48.249701 ADC[5]: Raw value=212072 ID=1
9423 22:14:48.252673 SKU Code: 0x1
9424 22:14:48.259143 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 4ba3
9425 22:14:48.259226 coreboot table: 964 bytes.
9426 22:14:48.262452 IMD ROOT 0. 0xfffff000 0x00001000
9427 22:14:48.265747 IMD SMALL 1. 0xffffe000 0x00001000
9428 22:14:48.269790 RO MCACHE 2. 0xffffc000 0x00001104
9429 22:14:48.272707 CONSOLE 3. 0xfff7c000 0x00080000
9430 22:14:48.276148 FMAP 4. 0xfff7b000 0x00000452
9431 22:14:48.279170 TIME STAMP 5. 0xfff7a000 0x00000910
9432 22:14:48.282470 VBOOT WORK 6. 0xfff66000 0x00014000
9433 22:14:48.285656 RAMOOPS 7. 0xffe66000 0x00100000
9434 22:14:48.288976 COREBOOT 8. 0xffe64000 0x00002000
9435 22:14:48.292539 IMD small region:
9436 22:14:48.295677 IMD ROOT 0. 0xffffec00 0x00000400
9437 22:14:48.298884 VPD 1. 0xffffeba0 0x0000004c
9438 22:14:48.302223 MMC STATUS 2. 0xffffeb80 0x00000004
9439 22:14:48.305610 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9440 22:14:48.308610 Probing TPM: done!
9441 22:14:48.312286 Connected to device vid:did:rid of 1ae0:0028:00
9442 22:14:48.323431 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
9443 22:14:48.326566 Initialized TPM device CR50 revision 0
9444 22:14:48.329859 Checking cr50 for pending updates
9445 22:14:48.333568 Reading cr50 TPM mode
9446 22:14:48.342751 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9447 22:14:48.349062 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9448 22:14:48.389560 read SPI 0x3990ec 0x4f1b0: 34845 us, 9298 KB/s, 74.384 Mbps
9449 22:14:48.392989 Checking segment from ROM address 0x40100000
9450 22:14:48.395915 Checking segment from ROM address 0x4010001c
9451 22:14:48.402715 Loading segment from ROM address 0x40100000
9452 22:14:48.402797 code (compression=0)
9453 22:14:48.409432 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9454 22:14:48.419405 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9455 22:14:48.419488 it's not compressed!
9456 22:14:48.425852 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9457 22:14:48.429296 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9458 22:14:48.449480 Loading segment from ROM address 0x4010001c
9459 22:14:48.449563 Entry Point 0x80000000
9460 22:14:48.452692 Loaded segments
9461 22:14:48.455956 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9462 22:14:48.462726 Jumping to boot code at 0x80000000(0xffe64000)
9463 22:14:48.469112 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9464 22:14:48.475862 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9465 22:14:48.483870 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9466 22:14:48.487811 Checking segment from ROM address 0x40100000
9467 22:14:48.490729 Checking segment from ROM address 0x4010001c
9468 22:14:48.497131 Loading segment from ROM address 0x40100000
9469 22:14:48.497214 code (compression=1)
9470 22:14:48.503826 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9471 22:14:48.513647 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9472 22:14:48.513731 using LZMA
9473 22:14:48.522395 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9474 22:14:48.529121 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9475 22:14:48.532183 Loading segment from ROM address 0x4010001c
9476 22:14:48.532266 Entry Point 0x54601000
9477 22:14:48.535710 Loaded segments
9478 22:14:48.539278 NOTICE: MT8192 bl31_setup
9479 22:14:48.546216 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9480 22:14:48.549874 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9481 22:14:48.552902 WARNING: region 0:
9482 22:14:48.555832 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9483 22:14:48.555915 WARNING: region 1:
9484 22:14:48.562689 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9485 22:14:48.565700 WARNING: region 2:
9486 22:14:48.569456 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9487 22:14:48.572634 WARNING: region 3:
9488 22:14:48.575983 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9489 22:14:48.579336 WARNING: region 4:
9490 22:14:48.585988 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9491 22:14:48.586071 WARNING: region 5:
9492 22:14:48.589774 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9493 22:14:48.592650 WARNING: region 6:
9494 22:14:48.596030 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9495 22:14:48.599202 WARNING: region 7:
9496 22:14:48.603162 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9497 22:14:48.609048 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9498 22:14:48.612452 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9499 22:14:48.616017 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9500 22:14:48.622393 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9501 22:14:48.625619 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9502 22:14:48.628976 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9503 22:14:48.635731 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9504 22:14:48.638866 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9505 22:14:48.645599 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9506 22:14:48.649039 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9507 22:14:48.652717 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9508 22:14:48.658767 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9509 22:14:48.662580 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9510 22:14:48.665703 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9511 22:14:48.672089 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9512 22:14:48.676039 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9513 22:14:48.682421 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9514 22:14:48.685389 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9515 22:14:48.688999 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9516 22:14:48.695495 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9517 22:14:48.698911 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9518 22:14:48.702072 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9519 22:14:48.709024 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9520 22:14:48.712147 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9521 22:14:48.718684 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9522 22:14:48.722932 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9523 22:14:48.729163 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9524 22:14:48.731978 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9525 22:14:48.735609 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9526 22:14:48.742452 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9527 22:14:48.745247 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9528 22:14:48.748672 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9529 22:14:48.756151 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9530 22:14:48.758924 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9531 22:14:48.762041 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9532 22:14:48.765327 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9533 22:14:48.771853 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9534 22:14:48.775207 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9535 22:14:48.778397 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9536 22:14:48.782125 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9537 22:14:48.788382 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9538 22:14:48.792082 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9539 22:14:48.795549 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9540 22:14:48.798978 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9541 22:14:48.805295 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9542 22:14:48.808641 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9543 22:14:48.811905 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9544 22:14:48.818814 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9545 22:14:48.821895 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9546 22:14:48.825331 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9547 22:14:48.832027 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9548 22:14:48.835166 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9549 22:14:48.841692 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9550 22:14:48.845047 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9551 22:14:48.851817 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9552 22:14:48.855365 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9553 22:14:48.858479 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9554 22:14:48.865391 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9555 22:14:48.868282 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9556 22:14:48.875146 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9557 22:14:48.878058 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9558 22:14:48.885115 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9559 22:14:48.888719 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9560 22:14:48.894987 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9561 22:14:48.898079 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9562 22:14:48.901721 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9563 22:14:48.908049 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9564 22:14:48.911408 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9565 22:14:48.918185 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9566 22:14:48.921571 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9567 22:14:48.928318 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9568 22:14:48.931420 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9569 22:14:48.934959 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9570 22:14:48.941361 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9571 22:14:48.944905 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9572 22:14:48.951762 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9573 22:14:48.954886 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9574 22:14:48.961518 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9575 22:14:48.964825 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9576 22:14:48.968489 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9577 22:14:48.974665 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9578 22:14:48.977979 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9579 22:14:48.984773 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9580 22:14:48.988131 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9581 22:14:48.994799 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9582 22:14:48.998993 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9583 22:14:49.001586 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9584 22:14:49.008032 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9585 22:14:49.011262 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9586 22:14:49.017785 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9587 22:14:49.021422 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9588 22:14:49.027928 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9589 22:14:49.031090 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9590 22:14:49.037827 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9591 22:14:49.041252 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9592 22:14:49.044399 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9593 22:14:49.051036 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9594 22:14:49.054436 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9595 22:14:49.058254 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9596 22:14:49.061278 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9597 22:14:49.067841 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9598 22:14:49.071061 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9599 22:14:49.077860 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9600 22:14:49.081544 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9601 22:14:49.084285 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9602 22:14:49.090920 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9603 22:14:49.094313 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9604 22:14:49.100979 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9605 22:14:49.104296 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9606 22:14:49.107552 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9607 22:14:49.114604 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9608 22:14:49.118054 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9609 22:14:49.124075 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9610 22:14:49.127291 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9611 22:14:49.131130 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9612 22:14:49.137328 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9613 22:14:49.140680 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9614 22:14:49.144439 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9615 22:14:49.150635 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9616 22:14:49.154039 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9617 22:14:49.157233 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9618 22:14:49.161131 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9619 22:14:49.167260 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9620 22:14:49.170516 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9621 22:14:49.174237 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9622 22:14:49.180520 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9623 22:14:49.183760 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9624 22:14:49.187678 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9625 22:14:49.193658 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9626 22:14:49.197291 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9627 22:14:49.203686 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9628 22:14:49.206956 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9629 22:14:49.210359 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9630 22:14:49.217106 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9631 22:14:49.220025 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9632 22:14:49.227141 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9633 22:14:49.230488 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9634 22:14:49.233878 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9635 22:14:49.240149 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9636 22:14:49.243580 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9637 22:14:49.250494 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9638 22:14:49.253783 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9639 22:14:49.257038 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9640 22:14:49.263546 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9641 22:14:49.266598 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9642 22:14:49.273270 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9643 22:14:49.277516 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9644 22:14:49.280547 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9645 22:14:49.286780 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9646 22:14:49.290075 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9647 22:14:49.296582 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9648 22:14:49.300047 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9649 22:14:49.303220 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9650 22:14:49.310012 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9651 22:14:49.313532 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9652 22:14:49.316453 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9653 22:14:49.323126 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9654 22:14:49.326435 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9655 22:14:49.333099 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9656 22:14:49.336348 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9657 22:14:49.339859 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9658 22:14:49.346194 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9659 22:14:49.349490 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9660 22:14:49.356511 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9661 22:14:49.359521 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9662 22:14:49.362807 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9663 22:14:49.369622 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9664 22:14:49.372980 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9665 22:14:49.379854 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9666 22:14:49.382750 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9667 22:14:49.385805 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9668 22:14:49.393351 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9669 22:14:49.395750 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9670 22:14:49.402519 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9671 22:14:49.405858 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9672 22:14:49.409163 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9673 22:14:49.416022 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9674 22:14:49.419000 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9675 22:14:49.425681 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9676 22:14:49.429498 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9677 22:14:49.432291 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9678 22:14:49.438965 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9679 22:14:49.442159 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9680 22:14:49.449078 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9681 22:14:49.452152 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9682 22:14:49.455589 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9683 22:14:49.462178 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9684 22:14:49.465608 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9685 22:14:49.469139 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9686 22:14:49.475137 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9687 22:14:49.478733 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9688 22:14:49.485829 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9689 22:14:49.488547 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9690 22:14:49.495249 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9691 22:14:49.498939 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9692 22:14:49.502167 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9693 22:14:49.508718 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9694 22:14:49.512049 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9695 22:14:49.518501 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9696 22:14:49.521672 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9697 22:14:49.528252 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9698 22:14:49.531609 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9699 22:14:49.535443 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9700 22:14:49.541827 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9701 22:14:49.545326 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9702 22:14:49.551826 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9703 22:14:49.554838 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9704 22:14:49.558156 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9705 22:14:49.564561 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9706 22:14:49.567939 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9707 22:14:49.574866 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9708 22:14:49.577902 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9709 22:14:49.584633 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9710 22:14:49.588993 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9711 22:14:49.591299 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9712 22:14:49.597704 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9713 22:14:49.601010 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9714 22:14:49.608208 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9715 22:14:49.610850 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9716 22:14:49.617412 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9717 22:14:49.620799 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9718 22:14:49.624492 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9719 22:14:49.630531 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9720 22:14:49.634452 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9721 22:14:49.640401 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9722 22:14:49.644656 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9723 22:14:49.650527 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9724 22:14:49.653915 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9725 22:14:49.657260 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9726 22:14:49.663806 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9727 22:14:49.667025 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9728 22:14:49.670493 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9729 22:14:49.673553 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9730 22:14:49.680123 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9731 22:14:49.683301 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9732 22:14:49.686738 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9733 22:14:49.693808 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9734 22:14:49.696553 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9735 22:14:49.700041 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9736 22:14:49.706735 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9737 22:14:49.709936 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9738 22:14:49.716291 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9739 22:14:49.719963 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9740 22:14:49.723267 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9741 22:14:49.730212 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9742 22:14:49.733184 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9743 22:14:49.739814 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9744 22:14:49.743178 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9745 22:14:49.745988 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9746 22:14:49.753331 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9747 22:14:49.756346 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9748 22:14:49.759405 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9749 22:14:49.765861 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9750 22:14:49.769660 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9751 22:14:49.772733 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9752 22:14:49.779235 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9753 22:14:49.782564 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9754 22:14:49.789154 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9755 22:14:49.792595 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9756 22:14:49.796041 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9757 22:14:49.802466 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9758 22:14:49.805645 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9759 22:14:49.809211 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9760 22:14:49.815668 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9761 22:14:49.819179 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9762 22:14:49.822422 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9763 22:14:49.828737 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9764 22:14:49.832266 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9765 22:14:49.838640 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9766 22:14:49.842374 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9767 22:14:49.845705 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9768 22:14:49.848493 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9769 22:14:49.852170 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9770 22:14:49.858428 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9771 22:14:49.861992 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9772 22:14:49.865292 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9773 22:14:49.868357 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9774 22:14:49.874942 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9775 22:14:49.878765 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9776 22:14:49.881760 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9777 22:14:49.888520 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9778 22:14:49.891749 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9779 22:14:49.894946 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9780 22:14:49.901450 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9781 22:14:49.904660 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9782 22:14:49.911565 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9783 22:14:49.914947 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9784 22:14:49.918283 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9785 22:14:49.924490 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9786 22:14:49.927932 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9787 22:14:49.934417 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9788 22:14:49.937846 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9789 22:14:49.941027 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9790 22:14:49.948101 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9791 22:14:49.951008 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9792 22:14:49.958238 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9793 22:14:49.960692 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9794 22:14:49.967495 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9795 22:14:49.970630 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9796 22:14:49.974375 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9797 22:14:49.981001 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9798 22:14:49.983888 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9799 22:14:49.990476 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9800 22:14:49.993956 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9801 22:14:50.000510 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9802 22:14:50.004043 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9803 22:14:50.007197 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9804 22:14:50.014013 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9805 22:14:50.017051 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9806 22:14:50.024044 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9807 22:14:50.027062 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9808 22:14:50.030622 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9809 22:14:50.037170 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9810 22:14:50.040300 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9811 22:14:50.046581 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9812 22:14:50.050012 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9813 22:14:50.053109 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9814 22:14:50.060095 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9815 22:14:50.063273 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9816 22:14:50.069995 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9817 22:14:50.073068 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9818 22:14:50.079838 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9819 22:14:50.083079 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9820 22:14:50.086296 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9821 22:14:50.092802 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9822 22:14:50.096279 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9823 22:14:50.102798 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9824 22:14:50.106286 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9825 22:14:50.112749 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9826 22:14:50.116022 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9827 22:14:50.119330 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9828 22:14:50.125967 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9829 22:14:50.129515 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9830 22:14:50.135703 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9831 22:14:50.139740 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9832 22:14:50.142403 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9833 22:14:50.149021 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9834 22:14:50.152241 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9835 22:14:50.159042 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9836 22:14:50.162292 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9837 22:14:50.165631 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9838 22:14:50.172183 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9839 22:14:50.175555 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9840 22:14:50.181903 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9841 22:14:50.185379 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9842 22:14:50.192102 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9843 22:14:50.194978 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9844 22:14:50.198491 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9845 22:14:50.205126 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9846 22:14:50.208554 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9847 22:14:50.215381 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9848 22:14:50.218325 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9849 22:14:50.224870 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9850 22:14:50.228024 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9851 22:14:50.231492 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9852 22:14:50.238248 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9853 22:14:50.241386 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9854 22:14:50.248011 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9855 22:14:50.251195 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9856 22:14:50.257854 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9857 22:14:50.261323 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9858 22:14:50.264469 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9859 22:14:50.271225 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9860 22:14:50.274368 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9861 22:14:50.281661 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9862 22:14:50.284318 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9863 22:14:50.290894 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9864 22:14:50.294183 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9865 22:14:50.300641 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9866 22:14:50.304248 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9867 22:14:50.307369 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9868 22:14:50.314064 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9869 22:14:50.317266 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9870 22:14:50.324269 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9871 22:14:50.327287 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9872 22:14:50.333692 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9873 22:14:50.337028 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9874 22:14:50.340509 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9875 22:14:50.346816 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9876 22:14:50.350149 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9877 22:14:50.357002 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9878 22:14:50.359890 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9879 22:14:50.366791 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9880 22:14:50.370318 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9881 22:14:50.376686 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9882 22:14:50.380061 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9883 22:14:50.383140 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9884 22:14:50.389793 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9885 22:14:50.393073 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9886 22:14:50.399739 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9887 22:14:50.403012 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9888 22:14:50.409783 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9889 22:14:50.412759 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9890 22:14:50.419494 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9891 22:14:50.423065 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9892 22:14:50.426038 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9893 22:14:50.432823 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9894 22:14:50.436005 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9895 22:14:50.442458 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9896 22:14:50.445723 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9897 22:14:50.452423 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9898 22:14:50.455744 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9899 22:14:50.459477 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9900 22:14:50.465805 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9901 22:14:50.469246 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9902 22:14:50.475817 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9903 22:14:50.479083 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9904 22:14:50.485575 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9905 22:14:50.489215 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9906 22:14:50.495916 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9907 22:14:50.498599 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9908 22:14:50.505277 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9909 22:14:50.508491 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9910 22:14:50.515251 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9911 22:14:50.518396 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9912 22:14:50.525457 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9913 22:14:50.528917 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9914 22:14:50.535150 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9915 22:14:50.538514 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9916 22:14:50.545037 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9917 22:14:50.548387 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9918 22:14:50.555119 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9919 22:14:50.558355 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9920 22:14:50.565096 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9921 22:14:50.568138 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9922 22:14:50.575096 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9923 22:14:50.577992 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9924 22:14:50.584520 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9925 22:14:50.588209 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9926 22:14:50.594443 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9927 22:14:50.598054 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9928 22:14:50.604510 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9929 22:14:50.607852 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9930 22:14:50.614660 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9931 22:14:50.617807 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9932 22:14:50.620969 INFO: [APUAPC] vio 0
9933 22:14:50.624521 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9934 22:14:50.630832 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9935 22:14:50.634471 INFO: [APUAPC] D0_APC_0: 0x400510
9936 22:14:50.634554 INFO: [APUAPC] D0_APC_1: 0x0
9937 22:14:50.637517 INFO: [APUAPC] D0_APC_2: 0x1540
9938 22:14:50.640915 INFO: [APUAPC] D0_APC_3: 0x0
9939 22:14:50.644205 INFO: [APUAPC] D1_APC_0: 0xffffffff
9940 22:14:50.647828 INFO: [APUAPC] D1_APC_1: 0xffffffff
9941 22:14:50.650833 INFO: [APUAPC] D1_APC_2: 0x3fffff
9942 22:14:50.654107 INFO: [APUAPC] D1_APC_3: 0x0
9943 22:14:50.657755 INFO: [APUAPC] D2_APC_0: 0xffffffff
9944 22:14:50.660534 INFO: [APUAPC] D2_APC_1: 0xffffffff
9945 22:14:50.664076 INFO: [APUAPC] D2_APC_2: 0x3fffff
9946 22:14:50.667738 INFO: [APUAPC] D2_APC_3: 0x0
9947 22:14:50.671000 INFO: [APUAPC] D3_APC_0: 0xffffffff
9948 22:14:50.674145 INFO: [APUAPC] D3_APC_1: 0xffffffff
9949 22:14:50.677200 INFO: [APUAPC] D3_APC_2: 0x3fffff
9950 22:14:50.680544 INFO: [APUAPC] D3_APC_3: 0x0
9951 22:14:50.683909 INFO: [APUAPC] D4_APC_0: 0xffffffff
9952 22:14:50.687506 INFO: [APUAPC] D4_APC_1: 0xffffffff
9953 22:14:50.690320 INFO: [APUAPC] D4_APC_2: 0x3fffff
9954 22:14:50.693763 INFO: [APUAPC] D4_APC_3: 0x0
9955 22:14:50.697427 INFO: [APUAPC] D5_APC_0: 0xffffffff
9956 22:14:50.700318 INFO: [APUAPC] D5_APC_1: 0xffffffff
9957 22:14:50.703555 INFO: [APUAPC] D5_APC_2: 0x3fffff
9958 22:14:50.707001 INFO: [APUAPC] D5_APC_3: 0x0
9959 22:14:50.710226 INFO: [APUAPC] D6_APC_0: 0xffffffff
9960 22:14:50.713471 INFO: [APUAPC] D6_APC_1: 0xffffffff
9961 22:14:50.716970 INFO: [APUAPC] D6_APC_2: 0x3fffff
9962 22:14:50.720261 INFO: [APUAPC] D6_APC_3: 0x0
9963 22:14:50.723534 INFO: [APUAPC] D7_APC_0: 0xffffffff
9964 22:14:50.726894 INFO: [APUAPC] D7_APC_1: 0xffffffff
9965 22:14:50.729893 INFO: [APUAPC] D7_APC_2: 0x3fffff
9966 22:14:50.733216 INFO: [APUAPC] D7_APC_3: 0x0
9967 22:14:50.736886 INFO: [APUAPC] D8_APC_0: 0xffffffff
9968 22:14:50.740139 INFO: [APUAPC] D8_APC_1: 0xffffffff
9969 22:14:50.743170 INFO: [APUAPC] D8_APC_2: 0x3fffff
9970 22:14:50.746441 INFO: [APUAPC] D8_APC_3: 0x0
9971 22:14:50.750283 INFO: [APUAPC] D9_APC_0: 0xffffffff
9972 22:14:50.753278 INFO: [APUAPC] D9_APC_1: 0xffffffff
9973 22:14:50.756599 INFO: [APUAPC] D9_APC_2: 0x3fffff
9974 22:14:50.759799 INFO: [APUAPC] D9_APC_3: 0x0
9975 22:14:50.762875 INFO: [APUAPC] D10_APC_0: 0xffffffff
9976 22:14:50.766535 INFO: [APUAPC] D10_APC_1: 0xffffffff
9977 22:14:50.769887 INFO: [APUAPC] D10_APC_2: 0x3fffff
9978 22:14:50.773104 INFO: [APUAPC] D10_APC_3: 0x0
9979 22:14:50.777195 INFO: [APUAPC] D11_APC_0: 0xffffffff
9980 22:14:50.780019 INFO: [APUAPC] D11_APC_1: 0xffffffff
9981 22:14:50.783232 INFO: [APUAPC] D11_APC_2: 0x3fffff
9982 22:14:50.786780 INFO: [APUAPC] D11_APC_3: 0x0
9983 22:14:50.789922 INFO: [APUAPC] D12_APC_0: 0xffffffff
9984 22:14:50.793023 INFO: [APUAPC] D12_APC_1: 0xffffffff
9985 22:14:50.796526 INFO: [APUAPC] D12_APC_2: 0x3fffff
9986 22:14:50.799916 INFO: [APUAPC] D12_APC_3: 0x0
9987 22:14:50.803116 INFO: [APUAPC] D13_APC_0: 0xffffffff
9988 22:14:50.806082 INFO: [APUAPC] D13_APC_1: 0xffffffff
9989 22:14:50.809499 INFO: [APUAPC] D13_APC_2: 0x3fffff
9990 22:14:50.812932 INFO: [APUAPC] D13_APC_3: 0x0
9991 22:14:50.816975 INFO: [APUAPC] D14_APC_0: 0xffffffff
9992 22:14:50.819442 INFO: [APUAPC] D14_APC_1: 0xffffffff
9993 22:14:50.822729 INFO: [APUAPC] D14_APC_2: 0x3fffff
9994 22:14:50.826257 INFO: [APUAPC] D14_APC_3: 0x0
9995 22:14:50.829191 INFO: [APUAPC] D15_APC_0: 0xffffffff
9996 22:14:50.832714 INFO: [APUAPC] D15_APC_1: 0xffffffff
9997 22:14:50.836264 INFO: [APUAPC] D15_APC_2: 0x3fffff
9998 22:14:50.839428 INFO: [APUAPC] D15_APC_3: 0x0
9999 22:14:50.842498 INFO: [APUAPC] APC_CON: 0x4
10000 22:14:50.846013 INFO: [NOCDAPC] D0_APC_0: 0x0
10001 22:14:50.846095 INFO: [NOCDAPC] D0_APC_1: 0x0
10002 22:14:50.849462 INFO: [NOCDAPC] D1_APC_0: 0x0
10003 22:14:50.852624 INFO: [NOCDAPC] D1_APC_1: 0xfff
10004 22:14:50.856036 INFO: [NOCDAPC] D2_APC_0: 0x0
10005 22:14:50.859820 INFO: [NOCDAPC] D2_APC_1: 0xfff
10006 22:14:50.862681 INFO: [NOCDAPC] D3_APC_0: 0x0
10007 22:14:50.866156 INFO: [NOCDAPC] D3_APC_1: 0xfff
10008 22:14:50.869232 INFO: [NOCDAPC] D4_APC_0: 0x0
10009 22:14:50.872779 INFO: [NOCDAPC] D4_APC_1: 0xfff
10010 22:14:50.875856 INFO: [NOCDAPC] D5_APC_0: 0x0
10011 22:14:50.875939 INFO: [NOCDAPC] D5_APC_1: 0xfff
10012 22:14:50.879236 INFO: [NOCDAPC] D6_APC_0: 0x0
10013 22:14:50.882905 INFO: [NOCDAPC] D6_APC_1: 0xfff
10014 22:14:50.886113 INFO: [NOCDAPC] D7_APC_0: 0x0
10015 22:14:50.889499 INFO: [NOCDAPC] D7_APC_1: 0xfff
10016 22:14:50.892696 INFO: [NOCDAPC] D8_APC_0: 0x0
10017 22:14:50.895820 INFO: [NOCDAPC] D8_APC_1: 0xfff
10018 22:14:50.898798 INFO: [NOCDAPC] D9_APC_0: 0x0
10019 22:14:50.902156 INFO: [NOCDAPC] D9_APC_1: 0xfff
10020 22:14:50.905646 INFO: [NOCDAPC] D10_APC_0: 0x0
10021 22:14:50.909019 INFO: [NOCDAPC] D10_APC_1: 0xfff
10022 22:14:50.912095 INFO: [NOCDAPC] D11_APC_0: 0x0
10023 22:14:50.915676 INFO: [NOCDAPC] D11_APC_1: 0xfff
10024 22:14:50.915763 INFO: [NOCDAPC] D12_APC_0: 0x0
10025 22:14:50.919219 INFO: [NOCDAPC] D12_APC_1: 0xfff
10026 22:14:50.922166 INFO: [NOCDAPC] D13_APC_0: 0x0
10027 22:14:50.925574 INFO: [NOCDAPC] D13_APC_1: 0xfff
10028 22:14:50.928848 INFO: [NOCDAPC] D14_APC_0: 0x0
10029 22:14:50.932022 INFO: [NOCDAPC] D14_APC_1: 0xfff
10030 22:14:50.935402 INFO: [NOCDAPC] D15_APC_0: 0x0
10031 22:14:50.938702 INFO: [NOCDAPC] D15_APC_1: 0xfff
10032 22:14:50.942053 INFO: [NOCDAPC] APC_CON: 0x4
10033 22:14:50.945320 INFO: [APUAPC] set_apusys_apc done
10034 22:14:50.948671 INFO: [DEVAPC] devapc_init done
10035 22:14:50.951818 INFO: GICv3 without legacy support detected.
10036 22:14:50.955325 INFO: ARM GICv3 driver initialized in EL3
10037 22:14:50.958375 INFO: Maximum SPI INTID supported: 639
10038 22:14:50.965402 INFO: BL31: Initializing runtime services
10039 22:14:50.968699 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10040 22:14:50.971937 INFO: SPM: enable CPC mode
10041 22:14:50.978613 INFO: mcdi ready for mcusys-off-idle and system suspend
10042 22:14:50.981741 INFO: BL31: Preparing for EL3 exit to normal world
10043 22:14:50.985382 INFO: Entry point address = 0x80000000
10044 22:14:50.988238 INFO: SPSR = 0x8
10045 22:14:50.993848
10046 22:14:50.993930
10047 22:14:50.993995
10048 22:14:50.997182 Starting depthcharge on Spherion...
10049 22:14:50.997265
10050 22:14:50.997331 Wipe memory regions:
10051 22:14:50.997391
10052 22:14:50.998015 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10053 22:14:50.998116 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10054 22:14:50.998200 Setting prompt string to ['asurada:']
10055 22:14:50.998278 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10056 22:14:51.000500 [0x00000040000000, 0x00000054600000)
10057 22:14:51.122707
10058 22:14:51.122807 [0x00000054660000, 0x00000080000000)
10059 22:14:51.383349
10060 22:14:51.383507 [0x000000821a7280, 0x000000ffe64000)
10061 22:14:52.128474
10062 22:14:52.128623 [0x00000100000000, 0x00000240000000)
10063 22:14:54.018746
10064 22:14:54.022591 Initializing XHCI USB controller at 0x11200000.
10065 22:14:55.059520
10066 22:14:55.062778 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10067 22:14:55.062872
10068 22:14:55.062938
10069 22:14:55.063000
10070 22:14:55.063277 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10072 22:14:55.163641 asurada: tftpboot 192.168.201.1 10597232/tftp-deploy-73mp9zex/kernel/image.itb 10597232/tftp-deploy-73mp9zex/kernel/cmdline
10073 22:14:55.163754 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10074 22:14:55.163922 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10075 22:14:55.168393 tftpboot 192.168.201.1 10597232/tftp-deploy-73mp9zex/kernel/image.itp-deploy-73mp9zex/kernel/cmdline
10076 22:14:55.168478
10077 22:14:55.168544 Waiting for link
10078 22:14:55.326983
10079 22:14:55.327120 R8152: Initializing
10080 22:14:55.327193
10081 22:14:55.329635 Version 9 (ocp_data = 6010)
10082 22:14:55.329720
10083 22:14:55.332723 R8152: Done initializing
10084 22:14:55.332832
10085 22:14:55.332899 Adding net device
10086 22:14:57.207383
10087 22:14:57.207544 done.
10088 22:14:57.207613
10089 22:14:57.207676 MAC: 00:e0:4c:72:2d:d6
10090 22:14:57.207737
10091 22:14:57.210768 Sending DHCP discover... done.
10092 22:14:57.210858
10093 22:14:57.213898 Waiting for reply... done.
10094 22:14:57.214010
10095 22:14:57.217708 Sending DHCP request... done.
10096 22:14:57.217795
10097 22:14:57.217862 Waiting for reply... done.
10098 22:14:57.217925
10099 22:14:57.220601 My ip is 192.168.201.21
10100 22:14:57.220686
10101 22:14:57.223917 The DHCP server ip is 192.168.201.1
10102 22:14:57.224003
10103 22:14:57.227567 TFTP server IP predefined by user: 192.168.201.1
10104 22:14:57.227653
10105 22:14:57.233837 Bootfile predefined by user: 10597232/tftp-deploy-73mp9zex/kernel/image.itb
10106 22:14:57.233926
10107 22:14:57.237035 Sending tftp read request... done.
10108 22:14:57.237119
10109 22:14:57.240587 Waiting for the transfer...
10110 22:14:57.240675
10111 22:14:57.517940 00000000 ################################################################
10112 22:14:57.518095
10113 22:14:57.772511 00080000 ################################################################
10114 22:14:57.772666
10115 22:14:58.041469 00100000 ################################################################
10116 22:14:58.041628
10117 22:14:58.307254 00180000 ################################################################
10118 22:14:58.307411
10119 22:14:58.569281 00200000 ################################################################
10120 22:14:58.569439
10121 22:14:58.840560 00280000 ################################################################
10122 22:14:58.840717
10123 22:14:59.114769 00300000 ################################################################
10124 22:14:59.114925
10125 22:14:59.390886 00380000 ################################################################
10126 22:14:59.391042
10127 22:14:59.652750 00400000 ################################################################
10128 22:14:59.652910
10129 22:14:59.922642 00480000 ################################################################
10130 22:14:59.922797
10131 22:15:00.222179 00500000 ################################################################
10132 22:15:00.222339
10133 22:15:00.493270 00580000 ################################################################
10134 22:15:00.493429
10135 22:15:00.778456 00600000 ################################################################
10136 22:15:00.778615
10137 22:15:01.079638 00680000 ################################################################
10138 22:15:01.079795
10139 22:15:01.355968 00700000 ################################################################
10140 22:15:01.356149
10141 22:15:01.625078 00780000 ################################################################
10142 22:15:01.625235
10143 22:15:01.901501 00800000 ################################################################
10144 22:15:01.901653
10145 22:15:02.159810 00880000 ################################################################
10146 22:15:02.159964
10147 22:15:02.427823 00900000 ################################################################
10148 22:15:02.427982
10149 22:15:02.713708 00980000 ################################################################
10150 22:15:02.713865
10151 22:15:02.969611 00a00000 ################################################################
10152 22:15:02.969770
10153 22:15:03.262774 00a80000 ################################################################
10154 22:15:03.262933
10155 22:15:03.527728 00b00000 ################################################################
10156 22:15:03.527880
10157 22:15:03.782945 00b80000 ################################################################
10158 22:15:03.783103
10159 22:15:04.040554 00c00000 ################################################################
10160 22:15:04.040708
10161 22:15:04.308025 00c80000 ################################################################
10162 22:15:04.308175
10163 22:15:04.579346 00d00000 ################################################################
10164 22:15:04.579501
10165 22:15:04.835784 00d80000 ################################################################
10166 22:15:04.835939
10167 22:15:05.095179 00e00000 ################################################################
10168 22:15:05.095335
10169 22:15:05.372968 00e80000 ################################################################
10170 22:15:05.373127
10171 22:15:05.623445 00f00000 ################################################################
10172 22:15:05.623603
10173 22:15:05.868499 00f80000 ################################################################
10174 22:15:05.868682
10175 22:15:06.133879 01000000 ################################################################
10176 22:15:06.134030
10177 22:15:06.422212 01080000 ################################################################
10178 22:15:06.422366
10179 22:15:06.718704 01100000 ################################################################
10180 22:15:06.718881
10181 22:15:07.015156 01180000 ################################################################
10182 22:15:07.015331
10183 22:15:07.313501 01200000 ################################################################
10184 22:15:07.313657
10185 22:15:07.610011 01280000 ################################################################
10186 22:15:07.610195
10187 22:15:07.907633 01300000 ################################################################
10188 22:15:07.907816
10189 22:15:08.205098 01380000 ################################################################
10190 22:15:08.205252
10191 22:15:08.502927 01400000 ################################################################
10192 22:15:08.503080
10193 22:15:08.799531 01480000 ################################################################
10194 22:15:08.799717
10195 22:15:09.081888 01500000 ################################################################
10196 22:15:09.082048
10197 22:15:09.347696 01580000 ################################################################
10198 22:15:09.347851
10199 22:15:09.674323 01600000 ################################################################
10200 22:15:09.674474
10201 22:15:09.972186 01680000 ################################################################
10202 22:15:09.972317
10203 22:15:10.242273 01700000 ################################################################
10204 22:15:10.242403
10205 22:15:10.491518 01780000 ################################################################
10206 22:15:10.491643
10207 22:15:10.741306 01800000 ################################################################
10208 22:15:10.741432
10209 22:15:10.992050 01880000 ################################################################
10210 22:15:10.992199
10211 22:15:11.238475 01900000 ################################################################
10212 22:15:11.238628
10213 22:15:11.488031 01980000 ################################################################
10214 22:15:11.488159
10215 22:15:11.738294 01a00000 ################################################################
10216 22:15:11.738427
10217 22:15:11.987830 01a80000 ################################################################
10218 22:15:11.987955
10219 22:15:12.237867 01b00000 ################################################################
10220 22:15:12.237995
10221 22:15:12.487604 01b80000 ################################################################
10222 22:15:12.487735
10223 22:15:12.757888 01c00000 ################################################################
10224 22:15:12.758020
10225 22:15:13.058671 01c80000 ################################################################
10226 22:15:13.058804
10227 22:15:13.359868 01d00000 ################################################################
10228 22:15:13.360002
10229 22:15:13.643065 01d80000 ##################################################### done.
10230 22:15:13.643580
10231 22:15:13.646319 The bootfile was 31365726 bytes long.
10232 22:15:13.646770
10233 22:15:13.649805 Sending tftp read request... done.
10234 22:15:13.650285
10235 22:15:13.650735 Waiting for the transfer...
10236 22:15:13.651159
10237 22:15:13.653456 00000000 # done.
10238 22:15:13.653914
10239 22:15:13.659650 Command line loaded dynamically from TFTP file: 10597232/tftp-deploy-73mp9zex/kernel/cmdline
10240 22:15:13.660206
10241 22:15:13.673643 The command line is: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10242 22:15:13.674199
10243 22:15:13.674727 Loading FIT.
10244 22:15:13.675159
10245 22:15:13.676303 Image ramdisk-1 has 21234464 bytes.
10246 22:15:13.676685
10247 22:15:13.680083 Image fdt-1 has 46924 bytes.
10248 22:15:13.680630
10249 22:15:13.682914 Image kernel-1 has 10082307 bytes.
10250 22:15:13.683462
10251 22:15:13.692954 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10252 22:15:13.693528
10253 22:15:13.709246 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10254 22:15:13.709806
10255 22:15:13.712522 Choosing best match conf-1 for compat google,spherion-rev2.
10256 22:15:13.715630
10257 22:15:13.719273 Connected to device vid:did:rid of 1ae0:0028:00
10258 22:15:13.729947
10259 22:15:13.732645 tpm_get_response: command 0x17b, return code 0x0
10260 22:15:13.733302
10261 22:15:13.735830 ec_init: CrosEC protocol v3 supported (256, 248)
10262 22:15:13.740156
10263 22:15:13.743746 tpm_cleanup: add release locality here.
10264 22:15:13.744451
10265 22:15:13.745002 Shutting down all USB controllers.
10266 22:15:13.746864
10267 22:15:13.747316 Removing current net device
10268 22:15:13.747761
10269 22:15:13.753321 Exiting depthcharge with code 4 at timestamp: 52077779
10270 22:15:13.753859
10271 22:15:13.756926 LZMA decompressing kernel-1 to 0x821a6718
10272 22:15:13.757468
10273 22:15:13.760123 LZMA decompressing kernel-1 to 0x40000000
10274 22:15:15.027150
10275 22:15:15.027693 jumping to kernel
10276 22:15:15.029206 end: 2.2.4 bootloader-commands (duration 00:00:24) [common]
10277 22:15:15.029783 start: 2.2.5 auto-login-action (timeout 00:04:01) [common]
10278 22:15:15.030206 Setting prompt string to ['Linux version [0-9]']
10279 22:15:15.030587 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10280 22:15:15.031006 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10281 22:15:15.108153
10282 22:15:15.111689 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10283 22:15:15.115258 start: 2.2.5.1 login-action (timeout 00:04:01) [common]
10284 22:15:15.115360 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10285 22:15:15.115454 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10286 22:15:15.115537 Using line separator: #'\n'#
10287 22:15:15.115603 No login prompt set.
10288 22:15:15.115674 Parsing kernel messages
10289 22:15:15.115735 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10290 22:15:15.115849 [login-action] Waiting for messages, (timeout 00:04:01)
10291 22:15:15.134731 [ 0.000000] Linux version 6.1.31 (KernelCI@build-j1612341-arm64-gcc-10-defconfig-arm64-chromebook-n674v) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Mon Jun 5 22:04:07 UTC 2023
10292 22:15:15.137652 [ 0.000000] random: crng init done
10293 22:15:15.144658 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10294 22:15:15.144850 [ 0.000000] efi: UEFI not found.
10295 22:15:15.154829 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10296 22:15:15.161273 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10297 22:15:15.171168 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10298 22:15:15.181469 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10299 22:15:15.187580 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10300 22:15:15.194404 [ 0.000000] printk: bootconsole [mtk8250] enabled
10301 22:15:15.201250 [ 0.000000] NUMA: No NUMA configuration found
10302 22:15:15.207668 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10303 22:15:15.211311 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcda00-0x23efcffff]
10304 22:15:15.214460 [ 0.000000] Zone ranges:
10305 22:15:15.220884 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10306 22:15:15.224196 [ 0.000000] DMA32 empty
10307 22:15:15.230838 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10308 22:15:15.234013 [ 0.000000] Movable zone start for each node
10309 22:15:15.237348 [ 0.000000] Early memory node ranges
10310 22:15:15.244123 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10311 22:15:15.250919 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10312 22:15:15.257540 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10313 22:15:15.264328 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10314 22:15:15.267229 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10315 22:15:15.277229 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10316 22:15:15.332382 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10317 22:15:15.339446 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10318 22:15:15.345625 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10319 22:15:15.348843 [ 0.000000] psci: probing for conduit method from DT.
10320 22:15:15.355402 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10321 22:15:15.358764 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10322 22:15:15.365583 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10323 22:15:15.368932 [ 0.000000] psci: SMC Calling Convention v1.2
10324 22:15:15.375051 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10325 22:15:15.378648 [ 0.000000] Detected VIPT I-cache on CPU0
10326 22:15:15.384973 [ 0.000000] CPU features: detected: GIC system register CPU interface
10327 22:15:15.391863 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10328 22:15:15.398231 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10329 22:15:15.404946 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10330 22:15:15.412122 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10331 22:15:15.421571 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10332 22:15:15.425446 [ 0.000000] alternatives: applying boot alternatives
10333 22:15:15.432005 [ 0.000000] Fallback order for Node 0: 0
10334 22:15:15.437908 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10335 22:15:15.441280 [ 0.000000] Policy zone: Normal
10336 22:15:15.451420 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10337 22:15:15.465086 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10338 22:15:15.474959 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10339 22:15:15.484750 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10340 22:15:15.491694 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10341 22:15:15.494300 <6>[ 0.000000] software IO TLB: area num 8.
10342 22:15:15.551001 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10343 22:15:15.699359 <6>[ 0.000000] Memory: 7952204K/8385536K available (17984K kernel code, 4098K rwdata, 14068K rodata, 8384K init, 615K bss, 400564K reserved, 32768K cma-reserved)
10344 22:15:15.706062 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10345 22:15:15.712951 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10346 22:15:15.715820 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10347 22:15:15.722568 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10348 22:15:15.729273 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10349 22:15:15.732606 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10350 22:15:15.742372 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10351 22:15:15.749095 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10352 22:15:15.755654 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10353 22:15:15.762205 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10354 22:15:15.765735 <6>[ 0.000000] GICv3: 608 SPIs implemented
10355 22:15:15.769047 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10356 22:15:15.775794 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10357 22:15:15.779273 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10358 22:15:15.785509 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10359 22:15:15.798382 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10360 22:15:15.811985 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10361 22:15:15.818477 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10362 22:15:15.825742 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10363 22:15:15.839215 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10364 22:15:15.846108 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10365 22:15:15.852526 <6>[ 0.009174] Console: colour dummy device 80x25
10366 22:15:15.862364 <6>[ 0.013901] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10367 22:15:15.868987 <6>[ 0.024344] pid_max: default: 32768 minimum: 301
10368 22:15:15.872155 <6>[ 0.029217] LSM: Security Framework initializing
10369 22:15:15.878870 <6>[ 0.034155] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10370 22:15:15.888741 <6>[ 0.042016] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10371 22:15:15.898383 <6>[ 0.051495] cblist_init_generic: Setting adjustable number of callback queues.
10372 22:15:15.901615 <6>[ 0.058949] cblist_init_generic: Setting shift to 3 and lim to 1.
10373 22:15:15.908564 <6>[ 0.065327] cblist_init_generic: Setting shift to 3 and lim to 1.
10374 22:15:15.915479 <6>[ 0.071773] rcu: Hierarchical SRCU implementation.
10375 22:15:15.921623 <6>[ 0.076787] rcu: Max phase no-delay instances is 1000.
10376 22:15:15.928162 <6>[ 0.083812] EFI services will not be available.
10377 22:15:15.931600 <6>[ 0.088780] smp: Bringing up secondary CPUs ...
10378 22:15:15.939229 <6>[ 0.093835] Detected VIPT I-cache on CPU1
10379 22:15:15.946137 <6>[ 0.093908] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10380 22:15:15.952443 <6>[ 0.093940] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10381 22:15:15.955955 <6>[ 0.094269] Detected VIPT I-cache on CPU2
10382 22:15:15.962741 <6>[ 0.094317] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10383 22:15:15.972837 <6>[ 0.094331] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10384 22:15:15.976009 <6>[ 0.094588] Detected VIPT I-cache on CPU3
10385 22:15:15.982742 <6>[ 0.094634] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10386 22:15:15.989538 <6>[ 0.094648] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10387 22:15:15.993158 <6>[ 0.094954] CPU features: detected: Spectre-v4
10388 22:15:15.999554 <6>[ 0.094960] CPU features: detected: Spectre-BHB
10389 22:15:16.002862 <6>[ 0.094966] Detected PIPT I-cache on CPU4
10390 22:15:16.009303 <6>[ 0.095024] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10391 22:15:16.016320 <6>[ 0.095041] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10392 22:15:16.022319 <6>[ 0.095339] Detected PIPT I-cache on CPU5
10393 22:15:16.029381 <6>[ 0.095401] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10394 22:15:16.036102 <6>[ 0.095417] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10395 22:15:16.039134 <6>[ 0.095700] Detected PIPT I-cache on CPU6
10396 22:15:16.045884 <6>[ 0.095764] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10397 22:15:16.052478 <6>[ 0.095779] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10398 22:15:16.059117 <6>[ 0.096075] Detected PIPT I-cache on CPU7
10399 22:15:16.065885 <6>[ 0.096139] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10400 22:15:16.072587 <6>[ 0.096155] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10401 22:15:16.075423 <6>[ 0.096202] smp: Brought up 1 node, 8 CPUs
10402 22:15:16.082213 <6>[ 0.237477] SMP: Total of 8 processors activated.
10403 22:15:16.085317 <6>[ 0.242429] CPU features: detected: 32-bit EL0 Support
10404 22:15:16.094874 <6>[ 0.247823] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10405 22:15:16.101395 <6>[ 0.256619] CPU features: detected: Common not Private translations
10406 22:15:16.108510 <6>[ 0.263098] CPU features: detected: CRC32 instructions
10407 22:15:16.114586 <6>[ 0.268484] CPU features: detected: RCpc load-acquire (LDAPR)
10408 22:15:16.118122 <6>[ 0.274443] CPU features: detected: LSE atomic instructions
10409 22:15:16.124756 <6>[ 0.280260] CPU features: detected: Privileged Access Never
10410 22:15:16.131214 <6>[ 0.286047] CPU features: detected: RAS Extension Support
10411 22:15:16.138449 <6>[ 0.291692] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10412 22:15:16.141155 <6>[ 0.298912] CPU: All CPU(s) started at EL2
10413 22:15:16.148061 <6>[ 0.303229] alternatives: applying system-wide alternatives
10414 22:15:16.157553 <6>[ 0.313937] devtmpfs: initialized
10415 22:15:16.170048 <6>[ 0.322858] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10416 22:15:16.180176 <6>[ 0.332819] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10417 22:15:16.186512 <6>[ 0.340962] pinctrl core: initialized pinctrl subsystem
10418 22:15:16.189652 <6>[ 0.347603] DMI not present or invalid.
10419 22:15:16.196228 <6>[ 0.352013] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10420 22:15:16.206107 <6>[ 0.358886] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10421 22:15:16.212608 <6>[ 0.366466] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10422 22:15:16.222404 <6>[ 0.374688] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10423 22:15:16.226201 <6>[ 0.382931] audit: initializing netlink subsys (disabled)
10424 22:15:16.235286 <5>[ 0.388626] audit: type=2000 audit(0.276:1): state=initialized audit_enabled=0 res=1
10425 22:15:16.241935 <6>[ 0.389323] thermal_sys: Registered thermal governor 'step_wise'
10426 22:15:16.248616 <6>[ 0.396591] thermal_sys: Registered thermal governor 'power_allocator'
10427 22:15:16.252100 <6>[ 0.402848] cpuidle: using governor menu
10428 22:15:16.258400 <6>[ 0.413805] NET: Registered PF_QIPCRTR protocol family
10429 22:15:16.265144 <6>[ 0.419281] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10430 22:15:16.271641 <6>[ 0.426381] ASID allocator initialised with 32768 entries
10431 22:15:16.274779 <6>[ 0.432945] Serial: AMBA PL011 UART driver
10432 22:15:16.284633 <4>[ 0.441559] Trying to register duplicate clock ID: 134
10433 22:15:16.340427 <6>[ 0.500810] KASLR enabled
10434 22:15:16.355000 <6>[ 0.508524] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10435 22:15:16.361468 <6>[ 0.515535] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10436 22:15:16.368147 <6>[ 0.522025] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10437 22:15:16.374581 <6>[ 0.529030] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10438 22:15:16.381184 <6>[ 0.535516] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10439 22:15:16.387849 <6>[ 0.542517] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10440 22:15:16.394895 <6>[ 0.549004] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10441 22:15:16.401436 <6>[ 0.556009] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10442 22:15:16.404187 <6>[ 0.563496] ACPI: Interpreter disabled.
10443 22:15:16.413094 <6>[ 0.569879] iommu: Default domain type: Translated
10444 22:15:16.419821 <6>[ 0.575042] iommu: DMA domain TLB invalidation policy: strict mode
10445 22:15:16.422838 <5>[ 0.581695] SCSI subsystem initialized
10446 22:15:16.429255 <6>[ 0.585934] usbcore: registered new interface driver usbfs
10447 22:15:16.435812 <6>[ 0.591667] usbcore: registered new interface driver hub
10448 22:15:16.439131 <6>[ 0.597218] usbcore: registered new device driver usb
10449 22:15:16.446562 <6>[ 0.603325] pps_core: LinuxPPS API ver. 1 registered
10450 22:15:16.456194 <6>[ 0.608518] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10451 22:15:16.459451 <6>[ 0.617860] PTP clock support registered
10452 22:15:16.462804 <6>[ 0.622101] EDAC MC: Ver: 3.0.0
10453 22:15:16.470363 <6>[ 0.627263] FPGA manager framework
10454 22:15:16.476843 <6>[ 0.630940] Advanced Linux Sound Architecture Driver Initialized.
10455 22:15:16.480191 <6>[ 0.637709] vgaarb: loaded
10456 22:15:16.487174 <6>[ 0.640869] clocksource: Switched to clocksource arch_sys_counter
10457 22:15:16.490018 <5>[ 0.647320] VFS: Disk quotas dquot_6.6.0
10458 22:15:16.496706 <6>[ 0.651504] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10459 22:15:16.499959 <6>[ 0.658697] pnp: PnP ACPI: disabled
10460 22:15:16.508266 <6>[ 0.665372] NET: Registered PF_INET protocol family
10461 22:15:16.518318 <6>[ 0.670949] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10462 22:15:16.529551 <6>[ 0.683250] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10463 22:15:16.539508 <6>[ 0.692065] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10464 22:15:16.546365 <6>[ 0.700037] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10465 22:15:16.555983 <6>[ 0.708736] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10466 22:15:16.562563 <6>[ 0.718473] TCP: Hash tables configured (established 65536 bind 65536)
10467 22:15:16.569237 <6>[ 0.725333] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10468 22:15:16.579057 <6>[ 0.732529] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10469 22:15:16.585658 <6>[ 0.740231] NET: Registered PF_UNIX/PF_LOCAL protocol family
10470 22:15:16.592224 <6>[ 0.746389] RPC: Registered named UNIX socket transport module.
10471 22:15:16.595621 <6>[ 0.752542] RPC: Registered udp transport module.
10472 22:15:16.602589 <6>[ 0.757476] RPC: Registered tcp transport module.
10473 22:15:16.608608 <6>[ 0.762406] RPC: Registered tcp NFSv4.1 backchannel transport module.
10474 22:15:16.612013 <6>[ 0.769076] PCI: CLS 0 bytes, default 64
10475 22:15:16.615457 <6>[ 0.773420] Unpacking initramfs...
10476 22:15:16.635634 <6>[ 0.789363] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10477 22:15:16.645836 <6>[ 0.798019] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10478 22:15:16.649165 <6>[ 0.806862] kvm [1]: IPA Size Limit: 40 bits
10479 22:15:16.656011 <6>[ 0.811385] kvm [1]: GICv3: no GICV resource entry
10480 22:15:16.659363 <6>[ 0.816405] kvm [1]: disabling GICv2 emulation
10481 22:15:16.666043 <6>[ 0.821093] kvm [1]: GIC system register CPU interface enabled
10482 22:15:16.669299 <6>[ 0.827252] kvm [1]: vgic interrupt IRQ18
10483 22:15:16.676390 <6>[ 0.831613] kvm [1]: VHE mode initialized successfully
10484 22:15:16.681990 <5>[ 0.838009] Initialise system trusted keyrings
10485 22:15:16.688571 <6>[ 0.842822] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10486 22:15:16.695961 <6>[ 0.852845] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10487 22:15:16.702751 <5>[ 0.859233] NFS: Registering the id_resolver key type
10488 22:15:16.706017 <5>[ 0.864537] Key type id_resolver registered
10489 22:15:16.712332 <5>[ 0.868953] Key type id_legacy registered
10490 22:15:16.718772 <6>[ 0.873231] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10491 22:15:16.725329 <6>[ 0.880150] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10492 22:15:16.732275 <6>[ 0.887881] 9p: Installing v9fs 9p2000 file system support
10493 22:15:16.769046 <5>[ 0.925887] Key type asymmetric registered
10494 22:15:16.772551 <5>[ 0.930216] Asymmetric key parser 'x509' registered
10495 22:15:16.782088 <6>[ 0.935362] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10496 22:15:16.785739 <6>[ 0.942975] io scheduler mq-deadline registered
10497 22:15:16.788596 <6>[ 0.947755] io scheduler kyber registered
10498 22:15:16.808168 <6>[ 0.964743] EINJ: ACPI disabled.
10499 22:15:16.840326 <4>[ 0.990122] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10500 22:15:16.850681 <4>[ 1.000764] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10501 22:15:16.865419 <6>[ 1.021541] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10502 22:15:16.873672 <6>[ 1.029569] printk: console [ttyS0] disabled
10503 22:15:16.901025 <6>[ 1.054217] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10504 22:15:16.908320 <6>[ 1.063695] printk: console [ttyS0] enabled
10505 22:15:16.911276 <6>[ 1.063695] printk: console [ttyS0] enabled
10506 22:15:16.918167 <6>[ 1.072590] printk: bootconsole [mtk8250] disabled
10507 22:15:16.920986 <6>[ 1.072590] printk: bootconsole [mtk8250] disabled
10508 22:15:16.927592 <6>[ 1.083903] SuperH (H)SCI(F) driver initialized
10509 22:15:16.930700 <6>[ 1.089185] msm_serial: driver initialized
10510 22:15:16.944700 <6>[ 1.098105] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10511 22:15:16.955533 <6>[ 1.106652] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10512 22:15:16.961787 <6>[ 1.115197] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10513 22:15:16.971588 <6>[ 1.123825] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10514 22:15:16.981675 <6>[ 1.132533] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10515 22:15:16.988684 <6>[ 1.141247] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10516 22:15:16.998150 <6>[ 1.149787] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10517 22:15:17.004881 <6>[ 1.158600] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10518 22:15:17.014519 <6>[ 1.167144] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10519 22:15:17.026223 <6>[ 1.182746] loop: module loaded
10520 22:15:17.032982 <6>[ 1.188792] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10521 22:15:17.055804 <4>[ 1.212137] mtk-pmic-keys: Failed to locate of_node [id: -1]
10522 22:15:17.062631 <6>[ 1.218847] megasas: 07.719.03.00-rc1
10523 22:15:17.072370 <6>[ 1.228359] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10524 22:15:17.084207 <6>[ 1.240268] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10525 22:15:17.100933 <6>[ 1.256970] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10526 22:15:17.161675 <6>[ 1.311149] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10527 22:15:17.538717 <6>[ 1.695404] Freeing initrd memory: 20732K
10528 22:15:17.554689 <6>[ 1.710983] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10529 22:15:17.565628 <6>[ 1.721873] tun: Universal TUN/TAP device driver, 1.6
10530 22:15:17.568943 <6>[ 1.727915] thunder_xcv, ver 1.0
10531 22:15:17.572094 <6>[ 1.731421] thunder_bgx, ver 1.0
10532 22:15:17.575308 <6>[ 1.734921] nicpf, ver 1.0
10533 22:15:17.586130 <6>[ 1.738923] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10534 22:15:17.589080 <6>[ 1.746398] hns3: Copyright (c) 2017 Huawei Corporation.
10535 22:15:17.595611 <6>[ 1.751985] hclge is initializing
10536 22:15:17.599144 <6>[ 1.755564] e1000: Intel(R) PRO/1000 Network Driver
10537 22:15:17.605597 <6>[ 1.760693] e1000: Copyright (c) 1999-2006 Intel Corporation.
10538 22:15:17.608989 <6>[ 1.766706] e1000e: Intel(R) PRO/1000 Network Driver
10539 22:15:17.615987 <6>[ 1.771921] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10540 22:15:17.622133 <6>[ 1.778106] igb: Intel(R) Gigabit Ethernet Network Driver
10541 22:15:17.629022 <6>[ 1.783756] igb: Copyright (c) 2007-2014 Intel Corporation.
10542 22:15:17.635678 <6>[ 1.789595] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10543 22:15:17.642324 <6>[ 1.796112] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10544 22:15:17.645597 <6>[ 1.802567] sky2: driver version 1.30
10545 22:15:17.651850 <6>[ 1.807547] VFIO - User Level meta-driver version: 0.3
10546 22:15:17.659929 <6>[ 1.815723] usbcore: registered new interface driver usb-storage
10547 22:15:17.666042 <6>[ 1.822175] usbcore: registered new device driver onboard-usb-hub
10548 22:15:17.675021 <6>[ 1.831246] mt6397-rtc mt6359-rtc: registered as rtc0
10549 22:15:17.684869 <6>[ 1.836724] mt6397-rtc mt6359-rtc: setting system clock to 2023-06-05T22:15:19 UTC (1686003319)
10550 22:15:17.688302 <6>[ 1.846336] i2c_dev: i2c /dev entries driver
10551 22:15:17.704701 <6>[ 1.858005] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10552 22:15:17.711947 <6>[ 1.868190] sdhci: Secure Digital Host Controller Interface driver
10553 22:15:17.718447 <6>[ 1.874651] sdhci: Copyright(c) Pierre Ossman
10554 22:15:17.725129 <6>[ 1.880053] Synopsys Designware Multimedia Card Interface Driver
10555 22:15:17.728389 <6>[ 1.886671] mmc0: CQHCI version 5.10
10556 22:15:17.735374 <6>[ 1.887208] sdhci-pltfm: SDHCI platform and OF driver helper
10557 22:15:17.743135 <6>[ 1.898812] ledtrig-cpu: registered to indicate activity on CPUs
10558 22:15:17.753124 <6>[ 1.906212] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10559 22:15:17.756440 <6>[ 1.913613] usbcore: registered new interface driver usbhid
10560 22:15:17.763206 <6>[ 1.919447] usbhid: USB HID core driver
10561 22:15:17.769565 <6>[ 1.923701] spi_master spi0: will run message pump with realtime priority
10562 22:15:17.817955 <6>[ 1.968123] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10563 22:15:17.838430 <6>[ 1.984325] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10564 22:15:17.841444 <6>[ 1.997890] mmc0: Command Queue Engine enabled
10565 22:15:17.848687 <6>[ 2.000402] cros-ec-spi spi0.0: Chrome EC device registered
10566 22:15:17.855486 <6>[ 2.002631] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10567 22:15:17.859083 <6>[ 2.015812] mmcblk0: mmc0:0001 DA4128 116 GiB
10568 22:15:17.874080 <6>[ 2.026512] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10569 22:15:17.880545 <6>[ 2.027984] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10570 22:15:17.886681 <6>[ 2.038006] NET: Registered PF_PACKET protocol family
10571 22:15:17.890025 <6>[ 2.043040] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10572 22:15:17.896507 <6>[ 2.047168] 9pnet: Installing 9P2000 support
10573 22:15:17.899940 <6>[ 2.052907] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10574 22:15:17.906779 <5>[ 2.056842] Key type dns_resolver registered
10575 22:15:17.913032 <6>[ 2.062646] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10576 22:15:17.916423 <6>[ 2.067160] registered taskstats version 1
10577 22:15:17.920245 <5>[ 2.077440] Loading compiled-in X.509 certificates
10578 22:15:17.955755 <4>[ 2.105339] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10579 22:15:17.965575 <4>[ 2.116043] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10580 22:15:17.975649 <3>[ 2.128787] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10581 22:15:17.987864 <6>[ 2.144225] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10582 22:15:17.994820 <6>[ 2.151111] xhci-mtk 11200000.usb: xHCI Host Controller
10583 22:15:18.001413 <6>[ 2.156610] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10584 22:15:18.011459 <6>[ 2.164462] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10585 22:15:18.018199 <6>[ 2.173887] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10586 22:15:18.024724 <6>[ 2.179957] xhci-mtk 11200000.usb: xHCI Host Controller
10587 22:15:18.031623 <6>[ 2.185440] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10588 22:15:18.037831 <6>[ 2.193102] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10589 22:15:18.045040 <6>[ 2.200822] hub 1-0:1.0: USB hub found
10590 22:15:18.047988 <6>[ 2.204842] hub 1-0:1.0: 1 port detected
10591 22:15:18.057630 <6>[ 2.209183] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10592 22:15:18.060739 <6>[ 2.217773] hub 2-0:1.0: USB hub found
10593 22:15:18.064625 <6>[ 2.221788] hub 2-0:1.0: 1 port detected
10594 22:15:18.072503 <6>[ 2.228841] mtk-msdc 11f70000.mmc: Got CD GPIO
10595 22:15:18.089661 <6>[ 2.242853] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10596 22:15:18.096338 <6>[ 2.250886] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10597 22:15:18.106622 <4>[ 2.258867] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10598 22:15:18.116637 <6>[ 2.268529] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10599 22:15:18.123141 <6>[ 2.276613] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10600 22:15:18.129339 <6>[ 2.284653] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10601 22:15:18.139617 <6>[ 2.292568] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10602 22:15:18.145805 <6>[ 2.300388] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10603 22:15:18.156075 <6>[ 2.308212] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10604 22:15:18.166234 <6>[ 2.318994] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10605 22:15:18.172490 <6>[ 2.327361] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10606 22:15:18.182544 <6>[ 2.335722] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10607 22:15:18.192821 <6>[ 2.344065] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10608 22:15:18.199550 <6>[ 2.352409] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10609 22:15:18.208883 <6>[ 2.360752] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10610 22:15:18.215871 <6>[ 2.369096] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10611 22:15:18.225440 <6>[ 2.377439] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10612 22:15:18.232225 <6>[ 2.385783] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10613 22:15:18.242145 <6>[ 2.394126] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10614 22:15:18.248508 <6>[ 2.402469] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10615 22:15:18.258290 <6>[ 2.410812] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10616 22:15:18.264997 <6>[ 2.419155] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10617 22:15:18.275298 <6>[ 2.427499] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10618 22:15:18.281716 <6>[ 2.435844] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10619 22:15:18.288266 <6>[ 2.444772] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10620 22:15:18.295585 <6>[ 2.452257] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10621 22:15:18.302891 <6>[ 2.459346] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10622 22:15:18.313193 <6>[ 2.466524] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10623 22:15:18.319962 <6>[ 2.473852] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10624 22:15:18.329688 <6>[ 2.480758] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10625 22:15:18.336438 <6>[ 2.489916] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10626 22:15:18.346499 <6>[ 2.499043] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10627 22:15:18.356061 <6>[ 2.508347] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10628 22:15:18.366425 <6>[ 2.517821] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10629 22:15:18.376213 <6>[ 2.527295] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10630 22:15:18.386383 <6>[ 2.536423] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10631 22:15:18.392655 <6>[ 2.545899] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10632 22:15:18.402287 <6>[ 2.555026] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10633 22:15:18.412242 <6>[ 2.564327] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10634 22:15:18.422479 <6>[ 2.574493] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10635 22:15:18.432918 <6>[ 2.585940] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10636 22:15:18.475945 <6>[ 2.629118] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10637 22:15:18.628285 <6>[ 2.785030] hub 1-1:1.0: USB hub found
10638 22:15:18.631700 <6>[ 2.789383] hub 1-1:1.0: 4 ports detected
10639 22:15:18.756153 <6>[ 2.909482] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10640 22:15:18.782523 <6>[ 2.939426] hub 2-1:1.0: USB hub found
10641 22:15:18.785817 <6>[ 2.943948] hub 2-1:1.0: 3 ports detected
10642 22:15:18.951285 <6>[ 3.105141] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10643 22:15:19.084151 <6>[ 3.241130] hub 1-1.4:1.0: USB hub found
10644 22:15:19.087181 <6>[ 3.245777] hub 1-1.4:1.0: 2 ports detected
10645 22:15:19.163569 <6>[ 3.317396] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10646 22:15:19.382996 <6>[ 3.537143] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10647 22:15:19.575161 <6>[ 3.729141] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10648 22:15:30.704081 <6>[ 14.865769] ALSA device list:
10649 22:15:30.710330 <6>[ 14.869018] No soundcards found.
10650 22:15:30.723057 <6>[ 14.881410] Freeing unused kernel memory: 8384K
10651 22:15:30.726218 <6>[ 14.886341] Run /init as init process
10652 22:15:30.752698 Starting syslogd: OK
10653 22:15:30.756973 Starting klogd: OK
10654 22:15:30.766307 Running sysctl: OK
10655 22:15:30.772920 Populating /dev using udev: <30>[ 14.932771] udevd[186]: starting version 3.2.9
10656 22:15:30.782342 <27>[ 14.940713] udevd[186]: specified user 'tss' unknown
10657 22:15:30.788926 <27>[ 14.946104] udevd[186]: specified group 'tss' unknown
10658 22:15:30.792436 <30>[ 14.952461] udevd[187]: starting eudev-3.2.9
10659 22:15:30.822197 <27>[ 14.980448] udevd[187]: specified user 'tss' unknown
10660 22:15:30.828259 <27>[ 14.985833] udevd[187]: specified group 'tss' unknown
10661 22:15:31.018962 <6>[ 15.174268] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10662 22:15:31.029069 <6>[ 15.182274] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10663 22:15:31.048114 <6>[ 15.203038] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10664 22:15:31.068911 <6>[ 15.223939] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10665 22:15:31.075225 <3>[ 15.225739] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10666 22:15:31.081824 <6>[ 15.237452] remoteproc remoteproc0: scp is available
10667 22:15:31.088610 <3>[ 15.239408] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10668 22:15:31.098579 <4>[ 15.244877] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10669 22:15:31.108335 <3>[ 15.252746] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10670 22:15:31.115115 <6>[ 15.255306] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10671 22:15:31.121436 <6>[ 15.259356] usbcore: registered new interface driver r8152
10672 22:15:31.124734 <6>[ 15.262756] remoteproc remoteproc0: powering up scp
10673 22:15:31.134974 <3>[ 15.270844] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10674 22:15:31.141979 <4>[ 15.278767] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10675 22:15:31.145307 <6>[ 15.278842] mc: Linux media interface: v0.10
10676 22:15:31.155117 <3>[ 15.284063] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10677 22:15:31.161936 <3>[ 15.284072] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10678 22:15:31.171950 <4>[ 15.288786] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10679 22:15:31.175455 <4>[ 15.288786] Fallback method does not support PEC.
10680 22:15:31.182092 <4>[ 15.289347] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10681 22:15:31.191704 <3>[ 15.297329] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10682 22:15:31.198534 <3>[ 15.304185] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10683 22:15:31.208679 <4>[ 15.304664] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10684 22:15:31.218251 <3>[ 15.309141] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10685 22:15:31.224730 <3>[ 15.309320] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10686 22:15:31.231505 <3>[ 15.317373] remoteproc remoteproc0: request_firmware failed: -2
10687 22:15:31.241361 <3>[ 15.325525] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10688 22:15:31.248210 <3>[ 15.327633] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10689 22:15:31.254910 <6>[ 15.330281] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10690 22:15:31.261327 <6>[ 15.330290] pci_bus 0000:00: root bus resource [bus 00-ff]
10691 22:15:31.267736 <6>[ 15.330299] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10692 22:15:31.277674 <6>[ 15.330305] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10693 22:15:31.284487 <6>[ 15.330349] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10694 22:15:31.290978 <6>[ 15.330385] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10695 22:15:31.297445 <6>[ 15.330460] pci 0000:00:00.0: supports D1 D2
10696 22:15:31.304573 <6>[ 15.330463] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10697 22:15:31.310693 <6>[ 15.332287] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10698 22:15:31.317372 <6>[ 15.332398] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10699 22:15:31.324362 <6>[ 15.332428] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10700 22:15:31.333775 <6>[ 15.332448] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10701 22:15:31.340663 <6>[ 15.332465] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10702 22:15:31.343696 <6>[ 15.332577] pci 0000:01:00.0: supports D1 D2
10703 22:15:31.350349 <6>[ 15.332581] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10704 22:15:31.360434 <6>[ 15.341223] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10705 22:15:31.370158 <6>[ 15.341398] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10706 22:15:31.376577 <6>[ 15.345112] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10707 22:15:31.383421 <6>[ 15.345417] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10708 22:15:31.393253 <6>[ 15.345461] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10709 22:15:31.399894 <6>[ 15.345469] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10710 22:15:31.410080 <6>[ 15.345483] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10711 22:15:31.416408 <6>[ 15.345500] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10712 22:15:31.426354 <6>[ 15.345518] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10713 22:15:31.430015 <6>[ 15.345533] pci 0000:00:00.0: PCI bridge to [bus 01]
10714 22:15:31.439434 <6>[ 15.345540] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10715 22:15:31.442691 <6>[ 15.345739] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10716 22:15:31.452652 <3>[ 15.346375] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10717 22:15:31.459293 <3>[ 15.346382] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10718 22:15:31.466168 <6>[ 15.346649] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10719 22:15:31.472897 <6>[ 15.349215] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10720 22:15:31.478999 <6>[ 15.373868] videodev: Linux video capture interface: v2.00
10721 22:15:31.485634 <4>[ 15.375954] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10722 22:15:31.495541 <4>[ 15.375967] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10723 22:15:31.502319 <3>[ 15.381222] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10724 22:15:31.509061 <3>[ 15.409188] elants_i2c 4-0010: invalid 'hello' packet: ff ff ff ff
10725 22:15:31.518895 <3>[ 15.412263] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10726 22:15:31.522048 <6>[ 15.437129] r8152 2-1.3:1.0 eth0: v1.12.13
10727 22:15:31.532021 <3>[ 15.441899] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10728 22:15:31.535314 <3>[ 15.525147] elants_i2c 4-0010: invalid 'hello' packet: ff ff ff ff
10729 22:15:31.545159 <3>[ 15.532521] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10730 22:15:31.551897 <3>[ 15.649137] elants_i2c 4-0010: invalid 'hello' packet: ff ff ff ff
10731 22:15:31.558435 <3>[ 15.650921] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10732 22:15:31.564911 <3>[ 15.659330] elants_i2c 4-0010: (read fw id) unexpected response: ff ff
10733 22:15:31.575152 <3>[ 15.667108] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10734 22:15:31.584925 <6>[ 15.738332] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10735 22:15:31.599159 <6>[ 15.757926] usbcore: registered new interface driver cdc_ether
10736 22:15:31.613173 <6>[ 15.771952] Bluetooth: Core ver 2.22
10737 22:15:31.620610 <6>[ 15.771969] usbcore: registered new interface driver r8153_ecm
10738 22:15:31.623548 <6>[ 15.772138] NET: Registered PF_BLUETOOTH protocol family
10739 22:15:31.633340 <5>[ 15.784180] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10740 22:15:31.640008 <6>[ 15.787578] Bluetooth: HCI device and connection manager initialized
10741 22:15:31.646484 <6>[ 15.788769] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10742 22:15:31.659721 <6>[ 15.790194] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10743 22:15:31.663332 <6>[ 15.790337] usbcore: registered new interface driver uvcvideo
10744 22:15:31.669440 <6>[ 15.810134] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10745 22:15:31.676062 <5>[ 15.819509] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10746 22:15:31.686087 <4>[ 15.819583] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10747 22:15:31.692526 <6>[ 15.819592] cfg80211: failed to load regulatory.db
10748 22:15:31.695928 <6>[ 15.821758] Bluetooth: HCI socket layer initialized
10749 22:15:31.702807 <6>[ 15.834743] remoteproc remoteproc0: powering up scp
10750 22:15:31.706158 <6>[ 15.840969] Bluetooth: L2CAP socket layer initialized
10751 22:15:31.712435 <6>[ 15.841007] Bluetooth: SCO socket layer initialized
10752 22:15:31.722328 <4>[ 15.849925] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10753 22:15:31.729083 <3>[ 15.885541] remoteproc remoteproc0: request_firmware failed: -2
10754 22:15:31.735490 <3>[ 15.891850] fops_vcodec_open(),166: [MTK_V4L2][ERROR] vpu_load_firmware failed!
10755 22:15:31.742837 <6>[ 15.901373] usbcore: registered new interface driver btusb
10756 22:15:31.755954 <4>[ 15.907887] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10757 22:15:31.762558 <3>[ 15.918547] Bluetooth: hci0: Failed to load firmware file (-2)
10758 22:15:31.768952 <6>[ 15.920744] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10759 22:15:31.776157 <3>[ 15.924673] Bluetooth: hci0: Failed to set up firmware (-2)
10760 22:15:31.779722 <6>[ 15.932142] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10761 22:15:31.791974 <4>[ 15.937888] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10762 22:15:31.802430 <6>[ 15.961108] mt7921e 0000:01:00.0: ASIC revision: 79610010
10763 22:15:31.909202 <4>[ 16.061397] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10764 22:15:31.921328 done
10765 22:15:31.933453 Saving random seed: OK
10766 22:15:31.947138 Starting network: OK
10767 22:15:31.984829 Starting dropbear sshd: <6>[ 16.143227] NET: Registered PF_INET6 protocol family
10768 22:15:31.991523 <6>[ 16.150427] Segment Routing with IPv6
10769 22:15:31.995079 <6>[ 16.154381] In-situ OAM (IOAM) with IPv6
10770 22:15:31.998608 OK
10771 22:15:32.009802 /bin/sh: can't access tty; job control turned off
10772 22:15:32.010109 Matched prompt #10: / #
10774 22:15:32.010322 Setting prompt string to ['/ #']
10775 22:15:32.010418 end: 2.2.5.1 login-action (duration 00:00:17) [common]
10777 22:15:32.010613 end: 2.2.5 auto-login-action (duration 00:00:17) [common]
10778 22:15:32.010701 start: 2.2.6 expect-shell-connection (timeout 00:03:44) [common]
10779 22:15:32.010774 Setting prompt string to ['/ #']
10780 22:15:32.010838 Forcing a shell prompt, looking for ['/ #']
10782 22:15:32.061049 / #
10783 22:15:32.061151 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10784 22:15:32.061229 Waiting using forced prompt support (timeout 00:02:30)
10785 22:15:32.061329 <4>[ 16.179817] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10786 22:15:32.066085
10787 22:15:32.066357 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10788 22:15:32.066454 start: 2.2.7 export-device-env (timeout 00:03:44) [common]
10789 22:15:32.066551 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10790 22:15:32.066640 end: 2.2 depthcharge-retry (duration 00:01:16) [common]
10791 22:15:32.066726 end: 2 depthcharge-action (duration 00:01:16) [common]
10792 22:15:32.066814 start: 3 lava-test-retry (timeout 00:01:00) [common]
10793 22:15:32.066905 start: 3.1 lava-test-shell (timeout 00:01:00) [common]
10794 22:15:32.066983 Using namespace: common
10796 22:15:32.167305 / # #
10797 22:15:32.167435 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
10798 22:15:32.167558 #<4>[ 16.299053] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10799 22:15:32.172035
10800 22:15:32.172297 Using /lava-10597232
10802 22:15:32.272626 / # export SHELL=/bin/sh
10803 22:15:32.272768 export SHELL=/bin/sh<4>[ 16.419181] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10804 22:15:32.277934
10806 22:15:32.378466 / # . /lava-10597232/environment
10807 22:15:32.424919 . /lava-10597232/environment<4>[ 16.539383] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10808 22:15:32.425012
10810 22:15:32.525522 / # /lava-10597232/bin/lava-test-runner /lava-10597232/0
10811 22:15:32.525632 Test shell timeout: 10s (minimum of the action and connection timeout)
10812 22:15:32.525982 /lava-10597232/bin/lava-test-runner /lava-10597232/0<4>[ 16.659310] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10813 22:15:32.530788
10814 22:15:32.572926 + export 'TESTRUN_ID=0_dmesg'
10815 22:15:32.573021 +<8>[ 16.711910] <LAVA_SIGNAL_STARTRUN 0_dmesg 10597232_1.5.2.3.1>
10816 22:15:32.573093 cd /lava-10597232/0/tests/0_dmesg
10817 22:15:32.573158 + cat uuid
10818 22:15:32.573399 Received signal: <STARTRUN> 0_dmesg 10597232_1.5.2.3.1
10819 22:15:32.573474 Starting test lava.0_dmesg (10597232_1.5.2.3.1)
10820 22:15:32.573558 Skipping test definition patterns.
10821 22:15:32.573659 + UUID=10597232_1.5.2.3.1
10822 22:15:32.573726 + set +x
10823 22:15:32.573788 + KERNELCI_LAVA=y /bin/sh /opt/kernelci/dmesg.sh
10824 22:15:32.578047 <8>[ 16.732528] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0>
10825 22:15:32.578303 Received signal: <TESTCASE> TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0
10827 22:15:32.597955 <8>[ 16.753309] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0>
10828 22:15:32.598212 Received signal: <TESTCASE> TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0
10830 22:15:32.630152 <4>[ 16.782042] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10831 22:15:32.636613 <8>[ 16.783950] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0>
10832 22:15:32.636869 Received signal: <TESTCASE> TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0
10834 22:15:32.641640 + set +x
10835 22:15:32.645587 Received signal: <ENDRUN> 0_dmesg 10597232_1.5.2.3.1
10836 22:15:32.645685 Ending use of test pattern.
10837 22:15:32.645753 Ending test lava.0_dmesg (10597232_1.5.2.3.1), duration 0.07
10839 22:15:32.648402 <8>[ 16.803973] <LAVA_SIGNAL_ENDRUN 0_dmesg 10597232_1.5.2.3.1>
10840 22:15:32.651560 <LAVA_TEST_RUNNER EXIT>
10841 22:15:32.651813 ok: lava_test_shell seems to have completed
10842 22:15:32.651920 alert: pass
crit: pass
emerg: pass
10843 22:15:32.652008 end: 3.1 lava-test-shell (duration 00:00:01) [common]
10844 22:15:32.652092 end: 3 lava-test-retry (duration 00:00:01) [common]
10845 22:15:32.652178 start: 4 lava-test-retry (timeout 00:01:00) [common]
10846 22:15:32.652267 start: 4.1 lava-test-shell (timeout 00:01:00) [common]
10847 22:15:32.652348 Using namespace: common
10849 22:15:32.752676 / # #
10850 22:15:32.752846 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
10851 22:15:32.752970 Using /lava-10597232
10853 22:15:32.853301 export SHELL=/bin/sh
10854 22:15:32.853446 #<4>[ 16.911621] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10855 22:15:32.853539
10857 22:15:32.954033 / # export SHELL=/bin/sh. /lava-10597232/environment
10858 22:15:32.954185
10859 22:15:32.954274 / # <4>[ 17.031711] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10861 22:15:33.054789 . /lava-10597232/environment/lava-10597232/bin/lava-test-runner /lava-10597232/1
10862 22:15:33.054895 Test shell timeout: 10s (minimum of the action and connection timeout)
10863 22:15:33.055013
10864 22:15:33.055086 / # <4>[ 17.150981] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10865 22:15:33.059857 /lava-10597232/bin/lava-test-runner /lava-10597232/1
10866 22:15:33.100950 + export 'TESTRUN_ID=1_bootrr'
10867 22:15:33.101040 <8>[ 17.242382] <LAVA_SIGNAL_STARTRUN 1_bootrr 10597232_1.5.2.3.5>
10868 22:15:33.101111 + cd /lava-10597232/1/tests/1_bootrr
10869 22:15:33.101176 + cat uuid
10870 22:15:33.101237 + UUID=10597232_1.5.2.3.5
10871 22:15:33.101299 + set +x
10872 22:15:33.101532 Received signal: <STARTRUN> 1_bootrr 10597232_1.5.2.3.5
10873 22:15:33.101597 Starting test lava.1_bootrr (10597232_1.5.2.3.5)
10874 22:15:33.101677 Skipping test definition patterns.
10875 22:15:33.101774 + export 'PATH=/opt/bootrr/libexec/bootrr/helpers:/lava-10597232/1/../bin:/sbin:/usr/sbin:/bin:/usr/bin'
10876 22:15:33.105313 + cd /opt/bootrr/libexec/bootrr
10877 22:15:33.108097 + sh helpers/bootrr-auto
10878 22:15:33.114946 /lav<3>[ 17.271243] mt7921e 0000:01:00.0: hardware init failed
10879 22:15:33.121034 a-10597232/1/../<8>[ 17.274556] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=deferred-probe-empty RESULT=pass>
10880 22:15:33.121291 Received signal: <TESTCASE> TEST_CASE_ID=deferred-probe-empty RESULT=pass
10882 22:15:33.124559 bin/lava-test-case
10883 22:15:33.134861 /lava-10597232/1/../bin/lava-test-case
10884 22:15:33.141572 <8>[ 17.296758] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=all-cpus-are-online RESULT=pass>
10885 22:15:33.141838 Received signal: <TESTCASE> TEST_CASE_ID=all-cpus-are-online RESULT=pass
10887 22:15:33.145850 /usr/bin/tpm2_getcap
10888 22:15:33.182617 /lava-10597232/1/../bin/lava-test-case
10889 22:15:33.188776 <8>[ 17.344772] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm-chip-is-online RESULT=pass>
10890 22:15:33.189040 Received signal: <TESTCASE> TEST_CASE_ID=tpm-chip-is-online RESULT=pass
10892 22:15:33.206488 /lava-10597232/1/../bin/lava-test-case
10893 22:15:33.213168 <8>[ 17.368623] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-driver-present RESULT=pass>
10894 22:15:33.213425 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-driver-present RESULT=pass
10896 22:15:33.224820 /lava-10597232/1/../bin/lava-test-case
10897 22:15:33.231516 <8>[ 17.386723] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-topckgen-probed RESULT=pass>
10898 22:15:33.231898 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-topckgen-probed RESULT=pass
10900 22:15:33.243316 /lava-10597232/1/../bin/lava-test-case
10901 22:15:33.249996 <8>[ 17.405456] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-infracfg-probed RESULT=pass>
10902 22:15:33.250464 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-infracfg-probed RESULT=pass
10904 22:15:33.261275 /lava-10597232/1/../bin/lava-test-case
10905 22:15:33.268274 <8>[ 17.423752] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-pericfg-probed RESULT=pass>
10906 22:15:33.268916 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-pericfg-probed RESULT=pass
10908 22:15:33.279707 /lava-10597232/1/../bin/lava-test-case
10909 22:15:33.286581 <8>[ 17.441773] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-apmixedsys-probed RESULT=pass>
10910 22:15:33.287438 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-apmixedsys-probed RESULT=pass
10912 22:15:33.296381 /lava-10597232/1/../bin/lava-test-case
10913 22:15:33.303096 <8>[ 17.457676] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-aud-driver-present RESULT=pass>
10914 22:15:33.303959 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-aud-driver-present RESULT=pass
10916 22:15:33.314622 /lava-10597232/1/../bin/lava-test-case
10917 22:15:33.321149 <8>[ 17.476288] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-aud-probed RESULT=pass>
10918 22:15:33.321904 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-aud-probed RESULT=pass
10920 22:15:33.330831 /lava-10597232/1/../bin/lava-test-case
10921 22:15:33.336932 <8>[ 17.492100] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap-driver-present RESULT=pass>
10922 22:15:33.337790 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap-driver-present RESULT=pass
10924 22:15:33.349242 /lava-10597232/1/../bin/lava-test-case
10925 22:15:33.355905 <8>[ 17.510991] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_n-probed RESULT=pass>
10926 22:15:33.356796 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_n-probed RESULT=pass
10928 22:15:33.369034 /lava-10597232/1/../bin/lava-test-case
10929 22:15:33.375540 <8>[ 17.529983] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_ws-probed RESULT=pass>
10930 22:15:33.376393 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_ws-probed RESULT=pass
10932 22:15:33.386527 /lava-10597232/1/../bin/lava-test-case
10933 22:15:33.393207 <8>[ 17.548572] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_e-probed RESULT=pass>
10934 22:15:33.394057 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_e-probed RESULT=pass
10936 22:15:33.405638 /lava-10597232/1/../bin/lava-test-case
10937 22:15:33.412053 <8>[ 17.567481] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_s-probed RESULT=pass>
10938 22:15:33.412900 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_s-probed RESULT=pass
10940 22:15:33.423470 /lava-10597232/1/../bin/lava-test-case
10941 22:15:33.429369 <8>[ 17.584246] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mfg-driver-present RESULT=pass>
10942 22:15:33.430247 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mfg-driver-present RESULT=pass
10944 22:15:33.440707 /lava-10597232/1/../bin/lava-test-case
10945 22:15:33.447297 <8>[ 17.602906] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mfg-probed RESULT=pass>
10946 22:15:33.448147 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mfg-probed RESULT=pass
10948 22:15:33.457389 /lava-10597232/1/../bin/lava-test-case
10949 22:15:33.463931 <8>[ 17.619025] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mm-driver-present RESULT=pass>
10950 22:15:33.464901 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mm-driver-present RESULT=pass
10952 22:15:33.476059 /lava-10597232/1/../bin/lava-test-case
10953 22:15:33.482586 <8>[ 17.637963] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mm-probed RESULT=pass>
10954 22:15:33.483436 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mm-probed RESULT=pass
10956 22:15:33.492155 /lava-10597232/1/../bin/lava-test-case
10957 22:15:33.498783 <8>[ 17.653754] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-mmsys-driver-present RESULT=pass>
10958 22:15:33.499633 Received signal: <TESTCASE> TEST_CASE_ID=mtk-mmsys-driver-present RESULT=pass
10960 22:15:33.510215 /lava-10597232/1/../bin/lava-test-case
10961 22:15:33.516306 <8>[ 17.671823] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-mmsys-probed RESULT=pass>
10962 22:15:33.517196 Received signal: <TESTCASE> TEST_CASE_ID=mtk-mmsys-probed RESULT=pass
10964 22:15:33.525282 /lava-10597232/1/../bin/lava-test-case
10965 22:15:33.531715 <8>[ 17.686608] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-msdc-driver-present RESULT=pass>
10966 22:15:33.532567 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-msdc-driver-present RESULT=pass
10968 22:15:33.544024 /lava-10597232/1/../bin/lava-test-case
10969 22:15:33.550159 <8>[ 17.706058] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-msdc-probed RESULT=pass>
10970 22:15:33.550907 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-msdc-probed RESULT=pass
10972 22:15:33.560563 /lava-10597232/1/../bin/lava-test-case
10973 22:15:33.566906 <8>[ 17.721783] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec-driver-present RESULT=pass>
10974 22:15:33.567767 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec-driver-present RESULT=pass
10976 22:15:33.578878 /lava-10597232/1/../bin/lava-test-case
10977 22:15:33.585187 <8>[ 17.740493] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec_soc-probed RESULT=pass>
10978 22:15:33.586044 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec_soc-probed RESULT=pass
10980 22:15:33.597202 /lava-10597232/1/../bin/lava-test-case
10981 22:15:33.603458 <8>[ 17.758894] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec-probed RESULT=pass>
10982 22:15:33.604310 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec-probed RESULT=pass
10984 22:15:33.613285 /lava-10597232/1/../bin/lava-test-case
10985 22:15:33.619322 <8>[ 17.775074] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-venc-driver-present RESULT=pass>
10986 22:15:33.620187 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-venc-driver-present RESULT=pass
10988 22:15:33.632117 /lava-10597232/1/../bin/lava-test-case
10989 22:15:33.638873 <8>[ 17.793458] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-venc-probed RESULT=pass>
10990 22:15:33.639732 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-venc-probed RESULT=pass
10992 22:15:33.647457 /lava-10597232/1/../bin/lava-test-case
10993 22:15:33.655335 <8>[ 17.809022] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam-driver-present RESULT=pass>
10994 22:15:33.656213 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam-driver-present RESULT=pass
10996 22:15:33.665477 /lava-10597232/1/../bin/lava-test-case
10997 22:15:33.672294 <8>[ 17.827286] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam-probed RESULT=pass>
10998 22:15:33.673206 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam-probed RESULT=pass
11000 22:15:33.684019 /lava-10597232/1/../bin/lava-test-case
11001 22:15:33.690285 <8>[ 17.845921] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawa-probed RESULT=pass>
11002 22:15:33.691175 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawa-probed RESULT=pass
11004 22:15:33.702573 /lava-10597232/1/../bin/lava-test-case
11005 22:15:33.708728 <8>[ 17.863609] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawb-probed RESULT=pass>
11006 22:15:33.709527 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawb-probed RESULT=pass
11008 22:15:33.720556 /lava-10597232/1/../bin/lava-test-case
11009 22:15:33.727075 <8>[ 17.882626] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawc-probed RESULT=pass>
11010 22:15:33.727976 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawc-probed RESULT=pass
11012 22:15:33.737281 /lava-10597232/1/../bin/lava-test-case
11013 22:15:33.743948 <8>[ 17.899099] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img-driver-present RESULT=pass>
11014 22:15:33.744873 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img-driver-present RESULT=pass
11016 22:15:33.756284 /lava-10597232/1/../bin/lava-test-case
11017 22:15:33.762544 <8>[ 17.917700] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img-probed RESULT=pass>
11018 22:15:33.763406 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img-probed RESULT=pass
11020 22:15:33.774047 /lava-10597232/1/../bin/lava-test-case
11021 22:15:33.780210 <8>[ 17.935842] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img2-probed RESULT=pass>
11022 22:15:33.781119 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img2-probed RESULT=pass
11024 22:15:33.790134 /lava-10597232/1/../bin/lava-test-case
11025 22:15:33.796648 <8>[ 17.951603] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-ipe-driver-present RESULT=pass>
11026 22:15:33.797566 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-ipe-driver-present RESULT=pass
11028 22:15:33.808427 /lava-10597232/1/../bin/lava-test-case
11029 22:15:33.815093 <8>[ 17.969906] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-ipe-probed RESULT=pass>
11030 22:15:33.815985 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-ipe-probed RESULT=pass
11032 22:15:33.824011 /lava-10597232/1/../bin/lava-test-case
11033 22:15:33.830526 <8>[ 17.985365] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mdp-driver-present RESULT=pass>
11034 22:15:33.831409 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mdp-driver-present RESULT=pass
11036 22:15:33.842968 /lava-10597232/1/../bin/lava-test-case
11037 22:15:33.849449 <8>[ 18.004599] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mdp-probed RESULT=pass>
11038 22:15:33.850219 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mdp-probed RESULT=pass
11040 22:15:33.858864 /lava-10597232/1/../bin/lava-test-case
11041 22:15:33.865334 <8>[ 18.020155] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-pinctrl-driver-present RESULT=pass>
11042 22:15:33.866198 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-pinctrl-driver-present RESULT=pass
11044 22:15:33.877653 /lava-10597232/1/../bin/lava-test-case
11045 22:15:33.884309 <8>[ 18.039765] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-pinctrl-probed RESULT=pass>
11046 22:15:33.885105 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-pinctrl-probed RESULT=pass
11048 22:15:33.893550 /lava-10597232/1/../bin/lava-test-case
11049 22:15:33.900115 <8>[ 18.055463] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-power-controller-driver-present RESULT=pass>
11050 22:15:33.901004 Received signal: <TESTCASE> TEST_CASE_ID=mtk-power-controller-driver-present RESULT=pass
11052 22:15:33.913264 /lava-10597232/1/../bin/lava-test-case
11053 22:15:33.919657 <8>[ 18.074707] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-power-controller-probed RESULT=pass>
11054 22:15:33.920546 Received signal: <TESTCASE> TEST_CASE_ID=mtk-power-controller-probed RESULT=pass
11056 22:15:33.929128 /lava-10597232/1/../bin/lava-test-case
11057 22:15:33.935674 <8>[ 18.091111] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt-pmic-pwrap-driver-present RESULT=pass>
11058 22:15:33.936564 Received signal: <TESTCASE> TEST_CASE_ID=mt-pmic-pwrap-driver-present RESULT=pass
11060 22:15:33.947648 /lava-10597232/1/../bin/lava-test-case
11061 22:15:33.954179 <8>[ 18.108914] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt-pmic-pwrap-probed RESULT=pass>
11062 22:15:33.954944 Received signal: <TESTCASE> TEST_CASE_ID=mt-pmic-pwrap-probed RESULT=pass
11064 22:15:33.963616 /lava-10597232/1/../bin/lava-test-case
11065 22:15:33.970018 <8>[ 18.125446] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=spmi-mtk-driver-present RESULT=pass>
11066 22:15:33.970898 Received signal: <TESTCASE> TEST_CASE_ID=spmi-mtk-driver-present RESULT=pass
11068 22:15:33.981538 /lava-10597232/1/../bin/lava-test-case
11069 22:15:33.988058 <8>[ 18.142983] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=spmi-mtk-probed RESULT=pass>
11070 22:15:33.988934 Received signal: <TESTCASE> TEST_CASE_ID=spmi-mtk-probed RESULT=pass
11072 22:15:33.996833 /lava-10597232/1/../bin/lava-test-case
11073 22:15:34.003483 <8>[ 18.158487] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator-driver-present RESULT=pass>
11074 22:15:34.004366 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator-driver-present RESULT=pass
11076 22:15:34.015905 /lava-10597232/1/../bin/lava-test-case
11077 22:15:34.022346 <8>[ 18.177418] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator6-probed RESULT=pass>
11078 22:15:34.023224 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator6-probed RESULT=pass
11080 22:15:34.034563 /lava-10597232/1/../bin/lava-test-case
11081 22:15:34.040989 <8>[ 18.195965] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator7-probed RESULT=pass>
11082 22:15:34.041857 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator7-probed RESULT=pass
11084 22:15:35.052277 /lava-10597232/1/../bin/lava-test-case
11085 22:15:35.059006 <8>[ 19.215405] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-rpmsg-driver-present RESULT=fail>
11086 22:15:35.059823 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-rpmsg-driver-present RESULT=fail
11088 22:15:36.071517 /lava-10597232/1/../bin/lava-test-case
11089 22:15:36.077888 <8>[ 20.234081] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-rpmsg-probed RESULT=blocked>
11090 22:15:36.078159 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-rpmsg-probed RESULT=blocked
11091 22:15:36.078247 Bad test result: blocked
11092 22:15:36.088390 /lava-10597232/1/../bin/lava-test-case
11093 22:15:36.094331 <8>[ 20.250967] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c-mt65xx-driver-present RESULT=pass>
11094 22:15:36.094621 Received signal: <TESTCASE> TEST_CASE_ID=i2c-mt65xx-driver-present RESULT=pass
11096 22:15:36.106393 /lava-10597232/1/../bin/lava-test-case
11097 22:15:36.112799 <8>[ 20.269134] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c0-mt65xx-probed RESULT=pass>
11098 22:15:36.113059 Received signal: <TESTCASE> TEST_CASE_ID=i2c0-mt65xx-probed RESULT=pass
11100 22:15:36.123943 /lava-10597232/1/../bin/lava-test-case
11101 22:15:36.130236 <8>[ 20.286726] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c1-mt65xx-probed RESULT=pass>
11102 22:15:36.130508 Received signal: <TESTCASE> TEST_CASE_ID=i2c1-mt65xx-probed RESULT=pass
11104 22:15:36.141584 /lava-10597232/1/../bin/lava-test-case
11105 22:15:36.148331 <8>[ 20.304016] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c2-mt65xx-probed RESULT=pass>
11106 22:15:36.149186 Received signal: <TESTCASE> TEST_CASE_ID=i2c2-mt65xx-probed RESULT=pass
11108 22:15:36.158904 /lava-10597232/1/../bin/lava-test-case
11109 22:15:36.165432 <8>[ 20.321250] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c3-mt65xx-probed RESULT=pass>
11110 22:15:36.166278 Received signal: <TESTCASE> TEST_CASE_ID=i2c3-mt65xx-probed RESULT=pass
11112 22:15:36.176093 /lava-10597232/1/../bin/lava-test-case
11113 22:15:36.182879 <8>[ 20.339006] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c7-mt65xx-probed RESULT=pass>
11114 22:15:36.183575 Received signal: <TESTCASE> TEST_CASE_ID=i2c7-mt65xx-probed RESULT=pass
11116 22:15:36.192108 /lava-10597232/1/../bin/lava-test-case
11117 22:15:36.199086 <8>[ 20.354763] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-driver-present RESULT=pass>
11118 22:15:36.199726 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-driver-present RESULT=pass
11120 22:15:36.210090 /lava-10597232/1/../bin/lava-test-case
11121 22:15:36.216409 <8>[ 20.372222] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi1-probed RESULT=pass>
11122 22:15:36.216814 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi1-probed RESULT=pass
11124 22:15:36.226644 /lava-10597232/1/../bin/lava-test-case
11125 22:15:36.233315 <8>[ 20.389311] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi5-probed RESULT=pass>
11126 22:15:36.233617 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi5-probed RESULT=pass
11128 22:15:36.242026 /lava-10597232/1/../bin/lava-test-case
11129 22:15:36.248692 <8>[ 20.404769] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6577-uart-driver-present RESULT=pass>
11130 22:15:36.248996 Received signal: <TESTCASE> TEST_CASE_ID=mt6577-uart-driver-present RESULT=pass
11132 22:15:36.260581 /lava-10597232/1/../bin/lava-test-case
11133 22:15:36.266964 <8>[ 20.423309] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6577-uart-probed RESULT=pass>
11134 22:15:36.267217 Received signal: <TESTCASE> TEST_CASE_ID=mt6577-uart-probed RESULT=pass
11136 22:15:36.276179 /lava-10597232/1/../bin/lava-test-case
11137 22:15:36.283377 <8>[ 20.439045] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-common-driver-present RESULT=pass>
11138 22:15:36.283631 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-common-driver-present RESULT=pass
11140 22:15:36.295163 /lava-10597232/1/../bin/lava-test-case
11141 22:15:36.302207 <8>[ 20.457664] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-common-probed RESULT=pass>
11142 22:15:36.302524 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-common-probed RESULT=pass
11144 22:15:36.311351 /lava-10597232/1/../bin/lava-test-case
11145 22:15:36.318429 <8>[ 20.473851] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb-driver-present RESULT=pass>
11146 22:15:36.318709 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb-driver-present RESULT=pass
11148 22:15:36.330440 /lava-10597232/1/../bin/lava-test-case
11149 22:15:36.336655 <8>[ 20.493104] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb0-probed RESULT=pass>
11150 22:15:36.336909 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb0-probed RESULT=pass
11152 22:15:36.348668 /lava-10597232/1/../bin/lava-test-case
11153 22:15:36.355142 <8>[ 20.510516] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb5-probed RESULT=pass>
11154 22:15:36.355887 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb5-probed RESULT=pass
11156 22:15:36.367315 /lava-10597232/1/../bin/lava-test-case
11157 22:15:36.373241 <8>[ 20.528776] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb14-probed RESULT=pass>
11158 22:15:36.374076 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb14-probed RESULT=pass
11160 22:15:36.385073 /lava-10597232/1/../bin/lava-test-case
11161 22:15:36.391330 <8>[ 20.546816] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb20-probed RESULT=pass>
11162 22:15:36.392091 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb20-probed RESULT=pass
11164 22:15:36.402798 /lava-10597232/1/../bin/lava-test-case
11165 22:15:36.409089 <8>[ 20.565571] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb1-probed RESULT=pass>
11166 22:15:36.409347 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb1-probed RESULT=pass
11168 22:15:36.420903 /lava-10597232/1/../bin/lava-test-case
11169 22:15:36.427343 <8>[ 20.583361] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb4-probed RESULT=pass>
11170 22:15:36.427597 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb4-probed RESULT=pass
11172 22:15:36.439000 /lava-10597232/1/../bin/lava-test-case
11173 22:15:36.445200 <8>[ 20.601443] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb16-probed RESULT=pass>
11174 22:15:36.445535 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb16-probed RESULT=pass
11176 22:15:36.457274 /lava-10597232/1/../bin/lava-test-case
11177 22:15:36.463910 <8>[ 20.619536] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb19-probed RESULT=pass>
11178 22:15:36.464759 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb19-probed RESULT=pass
11180 22:15:36.475139 /lava-10597232/1/../bin/lava-test-case
11181 22:15:36.482064 <8>[ 20.637178] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb9-probed RESULT=pass>
11182 22:15:36.482927 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb9-probed RESULT=pass
11184 22:15:36.493391 /lava-10597232/1/../bin/lava-test-case
11185 22:15:36.499806 <8>[ 20.655439] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb7-probed RESULT=pass>
11186 22:15:36.500592 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb7-probed RESULT=pass
11188 22:15:36.511439 /lava-10597232/1/../bin/lava-test-case
11189 22:15:36.518186 <8>[ 20.673741] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb17-probed RESULT=pass>
11190 22:15:36.519001 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb17-probed RESULT=pass
11192 22:15:36.529514 /lava-10597232/1/../bin/lava-test-case
11193 22:15:36.536161 <8>[ 20.691914] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb2-probed RESULT=pass>
11194 22:15:36.536898 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb2-probed RESULT=pass
11196 22:15:36.547521 /lava-10597232/1/../bin/lava-test-case
11197 22:15:36.554230 <8>[ 20.710085] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb11-probed RESULT=pass>
11198 22:15:36.555206 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb11-probed RESULT=pass
11200 22:15:36.566125 /lava-10597232/1/../bin/lava-test-case
11201 22:15:36.572634 <8>[ 20.728814] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb13-probed RESULT=pass>
11202 22:15:36.573424 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb13-probed RESULT=pass
11204 22:15:36.584449 /lava-10597232/1/../bin/lava-test-case
11205 22:15:36.591230 <8>[ 20.747142] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb18-probed RESULT=pass>
11206 22:15:36.591921 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb18-probed RESULT=pass
11208 22:15:36.601014 /lava-10597232/1/../bin/lava-test-case
11209 22:15:36.607699 <8>[ 20.763163] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-iommu-driver-present RESULT=pass>
11210 22:15:36.608444 Received signal: <TESTCASE> TEST_CASE_ID=mtk-iommu-driver-present RESULT=pass
11212 22:15:36.619548 /lava-10597232/1/../bin/lava-test-case
11213 22:15:36.626063 <8>[ 20.781738] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-iommu-probed RESULT=pass>
11214 22:15:36.626807 Received signal: <TESTCASE> TEST_CASE_ID=mtk-iommu-probed RESULT=pass
11216 22:15:36.635393 /lava-10597232/1/../bin/lava-test-case
11217 22:15:36.642420 <8>[ 20.797269] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-spi-driver-present RESULT=pass>
11218 22:15:36.643278 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-spi-driver-present RESULT=pass
11220 22:15:36.653116 /lava-10597232/1/../bin/lava-test-case
11221 22:15:36.659770 <8>[ 20.815700] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-spi-probed RESULT=pass>
11222 22:15:36.660652 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-spi-probed RESULT=pass
11224 22:15:36.669577 /lava-10597232/1/../bin/lava-test-case
11225 22:15:36.676402 <8>[ 20.831781] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-i2c-tunnel-driver-present RESULT=pass>
11226 22:15:36.677302 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-i2c-tunnel-driver-present RESULT=pass
11228 22:15:36.688991 /lava-10597232/1/../bin/lava-test-case
11229 22:15:36.695358 <8>[ 20.850966] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-i2c-tunnel-probed RESULT=pass>
11230 22:15:36.696216 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-i2c-tunnel-probed RESULT=pass
11232 22:15:36.705138 /lava-10597232/1/../bin/lava-test-case
11233 22:15:36.711666 <8>[ 20.866921] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-typec-driver-present RESULT=pass>
11234 22:15:36.712518 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-typec-driver-present RESULT=pass
11236 22:15:36.723751 /lava-10597232/1/../bin/lava-test-case
11237 22:15:36.730682 <8>[ 20.885935] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-typec-probed RESULT=pass>
11238 22:15:36.731535 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-typec-probed RESULT=pass
11240 22:15:36.740501 /lava-10597232/1/../bin/lava-test-case
11241 22:15:36.747044 <8>[ 20.902039] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-pwm-driver-present RESULT=pass>
11242 22:15:36.747897 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-pwm-driver-present RESULT=pass
11244 22:15:36.758787 /lava-10597232/1/../bin/lava-test-case
11245 22:15:36.765771 <8>[ 20.920550] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-pwm-probed RESULT=pass>
11246 22:15:36.766593 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-pwm-probed RESULT=pass
11248 22:15:36.774437 /lava-10597232/1/../bin/lava-test-case
11249 22:15:36.781070 <8>[ 20.936826] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator-driver-present RESULT=pass>
11250 22:15:36.781926 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator-driver-present RESULT=pass
11252 22:15:36.793594 /lava-10597232/1/../bin/lava-test-case
11253 22:15:36.799979 <8>[ 20.955507] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator0-probed RESULT=pass>
11254 22:15:36.800858 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator0-probed RESULT=pass
11256 22:15:36.812243 /lava-10597232/1/../bin/lava-test-case
11257 22:15:36.818497 <8>[ 20.973913] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator1-probed RESULT=pass>
11258 22:15:36.819376 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator1-probed RESULT=pass
11260 22:15:36.827529 /lava-10597232/1/../bin/lava-test-case
11261 22:15:36.834381 <8>[ 20.989914] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-keyb-driver-present RESULT=pass>
11262 22:15:36.835237 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-keyb-driver-present RESULT=pass
11264 22:15:36.846275 /lava-10597232/1/../bin/lava-test-case
11265 22:15:36.852681 <8>[ 21.008782] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-keyb-probed RESULT=pass>
11266 22:15:36.853515 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-keyb-probed RESULT=pass
11268 22:15:36.862472 /lava-10597232/1/../bin/lava-test-case
11269 22:15:36.868230 <8>[ 21.024343] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=leds_pwm-driver-present RESULT=pass>
11270 22:15:36.869149 Received signal: <TESTCASE> TEST_CASE_ID=leds_pwm-driver-present RESULT=pass
11272 22:15:36.880196 /lava-10597232/1/../bin/lava-test-case
11273 22:15:36.886362 <8>[ 21.042461] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=leds_pwm-probed RESULT=pass>
11274 22:15:36.887106 Received signal: <TESTCASE> TEST_CASE_ID=leds_pwm-probed RESULT=pass
11276 22:15:36.895668 /lava-10597232/1/../bin/lava-test-case
11277 22:15:36.902049 <8>[ 21.058249] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elan_i2c-driver-present RESULT=pass>
11278 22:15:36.902827 Received signal: <TESTCASE> TEST_CASE_ID=elan_i2c-driver-present RESULT=pass
11280 22:15:37.914540 /lava-10597232/1/../bin/lava-test-case
11281 22:15:37.921234 <8>[ 22.078358] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elan_i2c-probed RESULT=fail>
11282 22:15:37.921498 Received signal: <TESTCASE> TEST_CASE_ID=elan_i2c-probed RESULT=fail
11284 22:15:37.931669 /lava-10597232/1/../bin/lava-test-case
11285 22:15:37.937576 <8>[ 22.094136] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elants_i2c-driver-present RESULT=pass>
11286 22:15:37.937860 Received signal: <TESTCASE> TEST_CASE_ID=elants_i2c-driver-present RESULT=pass
11288 22:15:38.952107 /lava-10597232/1/../bin/lava-test-case
11289 22:15:38.958259 <8>[ 23.115070] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elants_i2c-probed RESULT=fail>
11290 22:15:38.959002 Received signal: <TESTCASE> TEST_CASE_ID=elants_i2c-probed RESULT=fail
11292 22:15:38.967922 /lava-10597232/1/../bin/lava-test-case
11293 22:15:38.974558 <8>[ 23.130487] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mipi-tx-driver-present RESULT=pass>
11294 22:15:38.975418 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mipi-tx-driver-present RESULT=pass
11296 22:15:39.988940 /lava-10597232/1/../bin/lava-test-case
11297 22:15:39.995554 <8>[ 24.151772] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mipi-tx-probed RESULT=fail>
11298 22:15:39.996410 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mipi-tx-probed RESULT=fail
11300 22:15:40.005309 /lava-10597232/1/../bin/lava-test-case
11301 22:15:40.012118 <8>[ 24.168066] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-dsi-driver-present RESULT=pass>
11302 22:15:40.012966 Received signal: <TESTCASE> TEST_CASE_ID=mtk-dsi-driver-present RESULT=pass
11304 22:15:41.025106 /lava-10597232/1/../bin/lava-test-case
11305 22:15:41.031692 <8>[ 25.188782] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-dsi-probed RESULT=fail>
11306 22:15:41.032627 Received signal: <TESTCASE> TEST_CASE_ID=mtk-dsi-probed RESULT=fail
11308 22:15:41.041430 /lava-10597232/1/../bin/lava-test-case
11309 22:15:41.047757 <8>[ 25.204268] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-driver-present RESULT=pass>
11310 22:15:41.048673 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-driver-present RESULT=pass
11312 22:15:42.061416 /lava-10597232/1/../bin/lava-test-case
11313 22:15:42.067862 <8>[ 26.224755] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-3-probed RESULT=fail>
11314 22:15:42.068117 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-3-probed RESULT=fail
11316 22:15:42.077052 /lava-10597232/1/../bin/lava-test-case
11317 22:15:42.083426 <8>[ 26.240031] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-pwm-driver-present RESULT=pass>
11318 22:15:42.083794 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-pwm-driver-present RESULT=pass
11320 22:15:43.097860 /lava-10597232/1/../bin/lava-test-case
11321 22:15:43.104444 <8>[ 27.261251] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-pwm-probed RESULT=fail>
11322 22:15:43.105358 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-pwm-probed RESULT=fail
11324 22:15:43.114350 /lava-10597232/1/../bin/lava-test-case
11325 22:15:43.121154 <8>[ 27.276741] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pwm-backlight-driver-present RESULT=pass>
11326 22:15:43.121996 Received signal: <TESTCASE> TEST_CASE_ID=pwm-backlight-driver-present RESULT=pass
11328 22:15:44.134833 /lava-10597232/1/../bin/lava-test-case
11329 22:15:44.141437 <8>[ 28.299250] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pwm-backlight-probed RESULT=fail>
11330 22:15:44.142204 Received signal: <TESTCASE> TEST_CASE_ID=pwm-backlight-probed RESULT=fail
11332 22:15:44.152075 /lava-10597232/1/../bin/lava-test-case
11333 22:15:44.158558 <8>[ 28.315386] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-edp-driver-present RESULT=pass>
11334 22:15:44.159429 Received signal: <TESTCASE> TEST_CASE_ID=panel-edp-driver-present RESULT=pass
11336 22:15:44.168749 /lava-10597232/1/../bin/lava-test-case
11337 22:15:44.175807 <8>[ 28.331724] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-simple-dp-aux-driver-present RESULT=pass>
11338 22:15:44.176689 Received signal: <TESTCASE> TEST_CASE_ID=panel-simple-dp-aux-driver-present RESULT=pass
11340 22:15:45.189519 /lava-10597232/1/../bin/lava-test-case
11341 22:15:45.195926 <8>[ 29.352794] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-simple-dp-aux-probed RESULT=fail>
11342 22:15:45.196838 Received signal: <TESTCASE> TEST_CASE_ID=panel-simple-dp-aux-probed RESULT=fail
11344 22:15:45.205526 /lava-10597232/1/../bin/lava-test-case
11345 22:15:45.212393 <8>[ 29.369375] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mutex-driver-present RESULT=pass>
11346 22:15:45.213297 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mutex-driver-present RESULT=pass
11348 22:15:45.224875 /lava-10597232/1/../bin/lava-test-case
11349 22:15:45.231215 <8>[ 29.388134] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mutex-probed RESULT=pass>
11350 22:15:45.232075 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mutex-probed RESULT=pass
11352 22:15:45.241174 /lava-10597232/1/../bin/lava-test-case
11353 22:15:45.247423 <8>[ 29.403792] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl-driver-present RESULT=pass>
11354 22:15:45.248291 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl-driver-present RESULT=pass
11356 22:15:45.260098 /lava-10597232/1/../bin/lava-test-case
11357 22:15:45.266413 <8>[ 29.422967] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl0-probed RESULT=pass>
11358 22:15:45.267280 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl0-probed RESULT=pass
11360 22:15:45.278622 /lava-10597232/1/../bin/lava-test-case
11361 22:15:45.284690 <8>[ 29.441520] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl2l0-probed RESULT=pass>
11362 22:15:45.285590 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl2l0-probed RESULT=pass
11364 22:15:45.297688 /lava-10597232/1/../bin/lava-test-case
11365 22:15:45.304421 <8>[ 29.460560] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl2l2-probed RESULT=pass>
11366 22:15:45.305317 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl2l2-probed RESULT=pass
11368 22:15:45.314708 /lava-10597232/1/../bin/lava-test-case
11369 22:15:45.320884 <8>[ 29.477680] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma-driver-present RESULT=pass>
11370 22:15:45.321725 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma-driver-present RESULT=pass
11372 22:15:45.334192 /lava-10597232/1/../bin/lava-test-case
11373 22:15:45.340670 <8>[ 29.497407] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma0-probed RESULT=pass>
11374 22:15:45.341582 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma0-probed RESULT=pass
11376 22:15:45.352992 /lava-10597232/1/../bin/lava-test-case
11377 22:15:45.359541 <8>[ 29.516111] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma4-probed RESULT=pass>
11378 22:15:45.360408 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma4-probed RESULT=pass
11380 22:15:45.369341 /lava-10597232/1/../bin/lava-test-case
11381 22:15:45.376218 <8>[ 29.532636] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-aal-driver-present RESULT=pass>
11382 22:15:45.377107 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-aal-driver-present RESULT=pass
11384 22:15:45.388625 /lava-10597232/1/../bin/lava-test-case
11385 22:15:45.394629 <8>[ 29.551417] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-aal-probed RESULT=pass>
11386 22:15:45.395485 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-aal-probed RESULT=pass
11388 22:15:45.404466 /lava-10597232/1/../bin/lava-test-case
11389 22:15:45.411174 <8>[ 29.567859] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ccorr-driver-present RESULT=pass>
11390 22:15:45.412041 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ccorr-driver-present RESULT=pass
11392 22:15:45.424169 /lava-10597232/1/../bin/lava-test-case
11393 22:15:45.430689 <8>[ 29.587366] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ccorr-probed RESULT=pass>
11394 22:15:45.431439 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ccorr-probed RESULT=pass
11396 22:15:45.440581 /lava-10597232/1/../bin/lava-test-case
11397 22:15:45.447199 <8>[ 29.603500] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-color-driver-present RESULT=pass>
11398 22:15:45.448197 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-color-driver-present RESULT=pass
11400 22:15:45.459671 /lava-10597232/1/../bin/lava-test-case
11401 22:15:45.466225 <8>[ 29.623191] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-color-probed RESULT=pass>
11402 22:15:45.467087 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-color-probed RESULT=pass
11404 22:15:45.476409 /lava-10597232/1/../bin/lava-test-case
11405 22:15:45.483121 <8>[ 29.639845] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-gamma-driver-present RESULT=pass>
11406 22:15:45.483972 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-gamma-driver-present RESULT=pass
11408 22:15:45.496394 /lava-10597232/1/../bin/lava-test-case
11409 22:15:45.502687 <8>[ 29.659255] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-gamma-probed RESULT=pass>
11410 22:15:45.503527 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-gamma-probed RESULT=pass
11412 22:15:45.512804 /lava-10597232/1/../bin/lava-test-case
11413 22:15:45.518791 <8>[ 29.675855] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-drm-driver-present RESULT=pass>
11414 22:15:45.519545 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-drm-driver-present RESULT=pass
11416 22:15:45.531063 /lava-10597232/1/../bin/lava-test-case
11417 22:15:45.538011 <8>[ 29.694543] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-drm-probed RESULT=pass>
11418 22:15:45.538866 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-drm-probed RESULT=pass
11420 22:15:45.547632 /lava-10597232/1/../bin/lava-test-case
11421 22:15:45.554512 <8>[ 29.711046] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-dpi-driver-present RESULT=pass>
11422 22:15:45.555373 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-dpi-driver-present RESULT=pass
11424 22:15:46.568592 /lava-10597232/1/../bin/lava-test-case
11425 22:15:46.575197 <8>[ 30.732185] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-dpi-probed RESULT=fail>
11426 22:15:46.576043 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-dpi-probed RESULT=fail
11428 22:15:47.587850 /lava-10597232/1/../bin/lava-test-case
11429 22:15:47.594191 <8>[ 31.751528] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-7-probed RESULT=fail>
11430 22:15:47.594449 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-7-probed RESULT=fail
11432 22:15:47.603029 /lava-10597232/1/../bin/lava-test-case
11433 22:15:47.609338 <8>[ 31.767072] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=sbs-battery-driver-present RESULT=pass>
11434 22:15:47.609704 Received signal: <TESTCASE> TEST_CASE_ID=sbs-battery-driver-present RESULT=pass
11436 22:15:47.621704 /lava-10597232/1/../bin/lava-test-case
11437 22:15:47.628086 <8>[ 31.785350] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=sbs-battery-probed RESULT=pass>
11438 22:15:47.628493 Received signal: <TESTCASE> TEST_CASE_ID=sbs-battery-probed RESULT=pass
11440 22:15:47.637169 /lava-10597232/1/../bin/lava-test-case
11441 22:15:47.643812 <8>[ 31.800828] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-pcie-gen3-driver-present RESULT=pass>
11442 22:15:47.644333 Received signal: <TESTCASE> TEST_CASE_ID=mtk-pcie-gen3-driver-present RESULT=pass
11444 22:15:47.656256 /lava-10597232/1/../bin/lava-test-case
11445 22:15:47.662426 <8>[ 31.819568] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-pcie-gen3-probed RESULT=pass>
11446 22:15:47.663279 Received signal: <TESTCASE> TEST_CASE_ID=mtk-pcie-gen3-probed RESULT=pass
11448 22:15:47.672007 /lava-10597232/1/../bin/lava-test-case
11449 22:15:47.678783 <8>[ 31.835219] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt7921e-driver-present RESULT=pass>
11450 22:15:47.679626 Received signal: <TESTCASE> TEST_CASE_ID=mt7921e-driver-present RESULT=pass
11452 22:15:47.689908 /lava-10597232/1/../bin/lava-test-case
11453 22:15:47.696510 <8>[ 31.853437] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt7921e-probed RESULT=pass>
11454 22:15:47.697409 Received signal: <TESTCASE> TEST_CASE_ID=mt7921e-probed RESULT=pass
11456 22:15:47.705596 /lava-10597232/1/../bin/lava-test-case
11457 22:15:47.711965 <8>[ 31.868910] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm_tis_spi-driver-present RESULT=pass>
11458 22:15:47.712826 Received signal: <TESTCASE> TEST_CASE_ID=tpm_tis_spi-driver-present RESULT=pass
11460 22:15:47.723923 /lava-10597232/1/../bin/lava-test-case
11461 22:15:47.730600 <8>[ 31.887616] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm_tis_spi-probed RESULT=pass>
11462 22:15:47.731440 Received signal: <TESTCASE> TEST_CASE_ID=tpm_tis_spi-probed RESULT=pass
11464 22:15:47.739673 /lava-10597232/1/../bin/lava-test-case
11465 22:15:47.745970 <8>[ 31.903227] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-msdc-driver-present RESULT=pass>
11466 22:15:47.746813 Received signal: <TESTCASE> TEST_CASE_ID=mtk-msdc-driver-present RESULT=pass
11468 22:15:47.758005 /lava-10597232/1/../bin/lava-test-case
11469 22:15:47.764756 <8>[ 31.921617] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-msdc-probed RESULT=pass>
11470 22:15:47.765556 Received signal: <TESTCASE> TEST_CASE_ID=mtk-msdc-probed RESULT=pass
11472 22:15:47.773478 /lava-10597232/1/../bin/lava-test-case
11473 22:15:47.780551 <8>[ 31.937363] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-nor-driver-present RESULT=pass>
11474 22:15:47.781526 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-nor-driver-present RESULT=pass
11476 22:15:47.792275 /lava-10597232/1/../bin/lava-test-case
11477 22:15:47.798828 <8>[ 31.955695] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-nor-probed RESULT=pass>
11478 22:15:47.799664 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-nor-probed RESULT=pass
11480 22:15:47.808320 /lava-10597232/1/../bin/lava-test-case
11481 22:15:47.815101 <8>[ 31.971812] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-tphy-driver-present RESULT=pass>
11482 22:15:47.815946 Received signal: <TESTCASE> TEST_CASE_ID=mtk-tphy-driver-present RESULT=pass
11484 22:15:47.826743 /lava-10597232/1/../bin/lava-test-case
11485 22:15:47.833284 <8>[ 31.990039] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-tphy-probed RESULT=pass>
11486 22:15:47.834166 Received signal: <TESTCASE> TEST_CASE_ID=mtk-tphy-probed RESULT=pass
11488 22:15:47.842309 /lava-10597232/1/../bin/lava-test-case
11489 22:15:47.848740 <8>[ 32.005574] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=xhci-mtk-driver-present RESULT=pass>
11490 22:15:47.849627 Received signal: <TESTCASE> TEST_CASE_ID=xhci-mtk-driver-present RESULT=pass
11492 22:15:47.860151 /lava-10597232/1/../bin/lava-test-case
11493 22:15:47.866480 <8>[ 32.023882] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=xhci-mtk-probed RESULT=pass>
11494 22:15:47.867331 Received signal: <TESTCASE> TEST_CASE_ID=xhci-mtk-probed RESULT=pass
11496 22:15:47.875203 /lava-10597232/1/../bin/lava-test-case
11497 22:15:47.881933 <8>[ 32.039203] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-scp-driver-present RESULT=pass>
11498 22:15:47.882680 Received signal: <TESTCASE> TEST_CASE_ID=mtk-scp-driver-present RESULT=pass
11500 22:15:47.893291 /lava-10597232/1/../bin/lava-test-case
11501 22:15:47.900660 <8>[ 32.057000] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-scp-probed RESULT=pass>
11502 22:15:47.901570 Received signal: <TESTCASE> TEST_CASE_ID=mtk-scp-probed RESULT=pass
11504 22:15:47.908636 /lava-10597232/1/../bin/lava-test-case
11505 22:15:47.914785 <8>[ 32.071437] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-enc-driver-present RESULT=pass>
11506 22:15:47.915614 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-enc-driver-present RESULT=pass
11508 22:15:47.927016 /lava-10597232/1/../bin/lava-test-case
11509 22:15:47.933621 <8>[ 32.090593] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-enc-probed RESULT=pass>
11510 22:15:47.934476 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-enc-probed RESULT=pass
11512 22:15:48.944810 /lava-10597232/1/../bin/lava-test-case
11513 22:15:48.951326 <8>[ 33.108643] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-dec-driver-present RESULT=fail>
11514 22:15:48.952181 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-dec-driver-present RESULT=fail
11516 22:15:49.963980 /lava-10597232/1/../bin/lava-test-case
11517 22:15:49.970364 <8>[ 34.128503] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-dec-probed RESULT=blocked>
11518 22:15:49.971219 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-dec-probed RESULT=blocked
11519 22:15:49.971666 Bad test result: blocked
11520 22:15:49.981113 /lava-10597232/1/../bin/lava-test-case
11521 22:15:49.987844 <8>[ 34.144454] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panfrost-driver-present RESULT=pass>
11522 22:15:49.988705 Received signal: <TESTCASE> TEST_CASE_ID=panfrost-driver-present RESULT=pass
11524 22:15:51.001796 /lava-10597232/1/../bin/lava-test-case
11525 22:15:51.007627 <8>[ 35.165006] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panfrost-probed RESULT=fail>
11526 22:15:51.008479 Received signal: <TESTCASE> TEST_CASE_ID=panfrost-probed RESULT=fail
11528 22:15:51.016575 /lava-10597232/1/../bin/lava-test-case
11529 22:15:51.023153 <8>[ 35.180499] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo-driver-present RESULT=pass>
11530 22:15:51.024045 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo-driver-present RESULT=pass
11532 22:15:51.034735 /lava-10597232/1/../bin/lava-test-case
11533 22:15:51.041606 <8>[ 35.198470] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo0-probed RESULT=pass>
11534 22:15:51.042461 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo0-probed RESULT=pass
11536 22:15:51.052237 /lava-10597232/1/../bin/lava-test-case
11537 22:15:51.058671 <8>[ 35.215757] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo1-probed RESULT=pass>
11538 22:15:51.059529 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo1-probed RESULT=pass
11540 22:15:51.067628 /lava-10597232/1/../bin/lava-test-case
11541 22:15:51.074051 <8>[ 35.231207] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-audio-driver-present RESULT=pass>
11542 22:15:51.074906 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-audio-driver-present RESULT=pass
11544 22:15:51.085930 /lava-10597232/1/../bin/lava-test-case
11545 22:15:51.092631 <8>[ 35.249608] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-audio-probed RESULT=pass>
11546 22:15:51.093575 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-audio-probed RESULT=pass
11548 22:15:51.101667 /lava-10597232/1/../bin/lava-test-case
11549 22:15:51.108110 <8>[ 35.265184] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dmic-codec-driver-present RESULT=pass>
11550 22:15:51.108956 Received signal: <TESTCASE> TEST_CASE_ID=dmic-codec-driver-present RESULT=pass
11552 22:15:52.121814 /lava-10597232/1/../bin/lava-test-case
11553 22:15:52.128391 <8>[ 36.286991] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dmic-codec-probed RESULT=fail>
11554 22:15:52.129300 Received signal: <TESTCASE> TEST_CASE_ID=dmic-codec-probed RESULT=fail
11556 22:15:52.138237 /lava-10597232/1/../bin/lava-test-case
11557 22:15:52.145131 <8>[ 36.303064] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt5682-driver-present RESULT=pass>
11558 22:15:52.145880 Received signal: <TESTCASE> TEST_CASE_ID=rt5682-driver-present RESULT=pass
11560 22:15:53.159241 /lava-10597232/1/../bin/lava-test-case
11561 22:15:53.165243 <8>[ 37.324092] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt5682-probed RESULT=fail>
11562 22:15:53.165975 Received signal: <TESTCASE> TEST_CASE_ID=rt5682-probed RESULT=fail
11564 22:15:53.175340 /lava-10597232/1/../bin/lava-test-case
11565 22:15:53.181586 <8>[ 37.338838] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt1015p-driver-present RESULT=pass>
11566 22:15:53.182422 Received signal: <TESTCASE> TEST_CASE_ID=rt1015p-driver-present RESULT=pass
11568 22:15:54.195580 /lava-10597232/1/../bin/lava-test-case
11569 22:15:54.202003 <8>[ 38.359618] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt1015p-probed RESULT=fail>
11570 22:15:54.202843 Received signal: <TESTCASE> TEST_CASE_ID=rt1015p-probed RESULT=fail
11572 22:15:54.210722 /lava-10597232/1/../bin/lava-test-case
11573 22:15:54.217745 <8>[ 38.374598] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192_mt6359-driver-present RESULT=pass>
11574 22:15:54.218662 Received signal: <TESTCASE> TEST_CASE_ID=mt8192_mt6359-driver-present RESULT=pass
11576 22:15:55.230498 /lava-10597232/1/../bin/lava-test-case
11577 22:15:55.237119 <8>[ 39.395812] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192_mt6359-probed RESULT=fail>
11578 22:15:55.237813 Received signal: <TESTCASE> TEST_CASE_ID=mt8192_mt6359-probed RESULT=fail
11580 22:15:55.246884 /lava-10597232/1/../bin/lava-test-case
11581 22:15:55.253422 <8>[ 39.411668] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb-driver-present RESULT=pass>
11582 22:15:55.254094 Received signal: <TESTCASE> TEST_CASE_ID=btusb-driver-present RESULT=pass
11584 22:15:55.264887 /lava-10597232/1/../bin/lava-test-case
11585 22:15:55.271224 <8>[ 39.428796] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb0-probed RESULT=pass>
11586 22:15:55.271899 Received signal: <TESTCASE> TEST_CASE_ID=btusb0-probed RESULT=pass
11588 22:15:55.281183 /lava-10597232/1/../bin/lava-test-case
11589 22:15:55.288256 <8>[ 39.445560] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb1-probed RESULT=pass>
11590 22:15:55.288932 Received signal: <TESTCASE> TEST_CASE_ID=btusb1-probed RESULT=pass
11592 22:15:55.296892 /lava-10597232/1/../bin/lava-test-case
11593 22:15:55.303442 <8>[ 39.460925] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-wdt-driver-present RESULT=pass>
11594 22:15:55.304124 Received signal: <TESTCASE> TEST_CASE_ID=mtk-wdt-driver-present RESULT=pass
11596 22:15:55.314693 /lava-10597232/1/../bin/lava-test-case
11597 22:15:55.321110 <8>[ 39.479374] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-wdt-probed RESULT=pass>
11598 22:15:55.321785 Received signal: <TESTCASE> TEST_CASE_ID=mtk-wdt-probed RESULT=pass
11600 22:15:55.330562 /lava-10597232/1/../bin/lava-test-case
11601 22:15:55.336858 <8>[ 39.494888] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek,efuse-driver-present RESULT=pass>
11602 22:15:55.337531 Received signal: <TESTCASE> TEST_CASE_ID=mediatek,efuse-driver-present RESULT=pass
11604 22:15:55.348611 /lava-10597232/1/../bin/lava-test-case
11605 22:15:55.355411 <8>[ 39.513333] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek,efuse-probed RESULT=pass>
11606 22:15:55.356150 Received signal: <TESTCASE> TEST_CASE_ID=mediatek,efuse-probed RESULT=pass
11608 22:15:55.365256 /lava-10597232/1/../bin/lava-test-case
11609 22:15:55.371937 <8>[ 39.529607] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-cpufreq-hw-driver-present RESULT=pass>
11610 22:15:55.372613 Received signal: <TESTCASE> TEST_CASE_ID=mtk-cpufreq-hw-driver-present RESULT=pass
11612 22:15:56.386413 /lava-10597232/1/../bin/lava-test-case
11613 22:15:56.393017 <8>[ 40.552127] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-cpufreq-hw-probed RESULT=fail>
11614 22:15:56.393805 Received signal: <TESTCASE> TEST_CASE_ID=mtk-cpufreq-hw-probed RESULT=fail
11616 22:15:56.397721 + set +x
11617 22:15:56.401374 Received signal: <ENDRUN> 1_bootrr 10597232_1.5.2.3.5
11618 22:15:56.401874 Ending use of test pattern.
11619 22:15:56.402262 Ending test lava.1_bootrr (10597232_1.5.2.3.5), duration 23.30
11621 22:15:56.404211 <8>[ 40.562407] <LAVA_SIGNAL_ENDRUN 1_bootrr 10597232_1.5.2.3.5>
11622 22:15:56.404889 ok: lava_test_shell seems to have completed
11623 22:15:56.410669 all-cpus-are-online: pass
anx7625-3-probed: fail
anx7625-7-probed: fail
anx7625-driver-present: pass
btusb-driver-present: pass
btusb0-probed: pass
btusb1-probed: pass
clk-mt8192-apmixedsys-probed: pass
clk-mt8192-aud-driver-present: pass
clk-mt8192-aud-probed: pass
clk-mt8192-cam-driver-present: pass
clk-mt8192-cam-probed: pass
clk-mt8192-cam_rawa-probed: pass
clk-mt8192-cam_rawb-probed: pass
clk-mt8192-cam_rawc-probed: pass
clk-mt8192-driver-present: pass
clk-mt8192-img-driver-present: pass
clk-mt8192-img-probed: pass
clk-mt8192-img2-probed: pass
clk-mt8192-imp_iic_wrap-driver-present: pass
clk-mt8192-imp_iic_wrap_e-probed: pass
clk-mt8192-imp_iic_wrap_n-probed: pass
clk-mt8192-imp_iic_wrap_s-probed: pass
clk-mt8192-imp_iic_wrap_ws-probed: pass
clk-mt8192-infracfg-probed: pass
clk-mt8192-ipe-driver-present: pass
clk-mt8192-ipe-probed: pass
clk-mt8192-mdp-driver-present: pass
clk-mt8192-mdp-probed: pass
clk-mt8192-mfg-driver-present: pass
clk-mt8192-mfg-probed: pass
clk-mt8192-mm-driver-present: pass
clk-mt8192-mm-probed: pass
clk-mt8192-msdc-driver-present: pass
clk-mt8192-msdc-probed: pass
clk-mt8192-pericfg-probed: pass
clk-mt8192-topckgen-probed: pass
clk-mt8192-vdec-driver-present: pass
clk-mt8192-vdec-probed: pass
clk-mt8192-vdec_soc-probed: pass
clk-mt8192-venc-driver-present: pass
clk-mt8192-venc-probed: pass
cros-ec-i2c-tunnel-driver-present: pass
cros-ec-i2c-tunnel-probed: pass
cros-ec-keyb-driver-present: pass
cros-ec-keyb-probed: pass
cros-ec-pwm-driver-present: pass
cros-ec-pwm-probed: pass
cros-ec-regulator-driver-present: pass
cros-ec-regulator0-probed: pass
cros-ec-regulator1-probed: pass
cros-ec-rpmsg-driver-present: fail
cros-ec-spi-driver-present: pass
cros-ec-spi-probed: pass
cros-ec-typec-driver-present: pass
cros-ec-typec-probed: pass
deferred-probe-empty: pass
dmic-codec-driver-present: pass
dmic-codec-probed: fail
elan_i2c-driver-present: pass
elan_i2c-probed: fail
elants_i2c-driver-present: pass
elants_i2c-probed: fail
i2c-mt65xx-driver-present: pass
i2c0-mt65xx-probed: pass
i2c1-mt65xx-probed: pass
i2c2-mt65xx-probed: pass
i2c3-mt65xx-probed: pass
i2c7-mt65xx-probed: pass
leds_pwm-driver-present: pass
leds_pwm-probed: pass
mediatek,efuse-driver-present: pass
mediatek,efuse-probed: pass
mediatek-disp-aal-driver-present: pass
mediatek-disp-aal-probed: pass
mediatek-disp-ccorr-driver-present: pass
mediatek-disp-ccorr-probed: pass
mediatek-disp-color-driver-present: pass
mediatek-disp-color-probed: pass
mediatek-disp-gamma-driver-present: pass
mediatek-disp-gamma-probed: pass
mediatek-disp-ovl-driver-present: pass
mediatek-disp-ovl0-probed: pass
mediatek-disp-ovl2l0-probed: pass
mediatek-disp-ovl2l2-probed: pass
mediatek-disp-pwm-driver-present: pass
mediatek-disp-pwm-probed: fail
mediatek-disp-rdma-driver-present: pass
mediatek-disp-rdma0-probed: pass
mediatek-disp-rdma4-probed: pass
mediatek-dpi-driver-present: pass
mediatek-dpi-probed: fail
mediatek-drm-driver-present: pass
mediatek-drm-probed: pass
mediatek-mipi-tx-driver-present: pass
mediatek-mipi-tx-probed: fail
mediatek-mutex-driver-present: pass
mediatek-mutex-probed: pass
mt-pmic-pwrap-driver-present: pass
mt-pmic-pwrap-probed: pass
mt6315-regulator-driver-present: pass
mt6315-regulator6-probed: pass
mt6315-regulator7-probed: pass
mt6577-uart-driver-present: pass
mt6577-uart-probed: pass
mt7921e-driver-present: pass
mt7921e-probed: pass
mt8192-audio-driver-present: pass
mt8192-audio-probed: pass
mt8192-pinctrl-driver-present: pass
mt8192-pinctrl-probed: pass
mt8192_mt6359-driver-present: pass
mt8192_mt6359-probed: fail
mtk-cpufreq-hw-driver-present: pass
mtk-cpufreq-hw-probed: fail
mtk-dsi-driver-present: pass
mtk-dsi-probed: fail
mtk-iommu-driver-present: pass
mtk-iommu-probed: pass
mtk-mmsys-driver-present: pass
mtk-mmsys-probed: pass
mtk-msdc-driver-present: pass
mtk-msdc-probed: pass
mtk-pcie-gen3-driver-present: pass
mtk-pcie-gen3-probed: pass
mtk-power-controller-driver-present: pass
mtk-power-controller-probed: pass
mtk-scp-driver-present: pass
mtk-scp-probed: pass
mtk-smi-common-driver-present: pass
mtk-smi-common-probed: pass
mtk-smi-larb-driver-present: pass
mtk-smi-larb0-probed: pass
mtk-smi-larb1-probed: pass
mtk-smi-larb11-probed: pass
mtk-smi-larb13-probed: pass
mtk-smi-larb14-probed: pass
mtk-smi-larb16-probed: pass
mtk-smi-larb17-probed: pass
mtk-smi-larb18-probed: pass
mtk-smi-larb19-probed: pass
mtk-smi-larb2-probed: pass
mtk-smi-larb20-probed: pass
mtk-smi-larb4-probed: pass
mtk-smi-larb5-probed: pass
mtk-smi-larb7-probed: pass
mtk-smi-larb9-probed: pass
mtk-spi-driver-present: pass
mtk-spi-nor-driver-present: pass
mtk-spi-nor-probed: pass
mtk-spi1-probed: pass
mtk-spi5-probed: pass
mtk-tphy-driver-present: pass
mtk-tphy-probed: pass
mtk-vcodec-dec-driver-present: fail
mtk-vcodec-enc-driver-present: pass
mtk-vcodec-enc-probed: pass
mtk-wdt-driver-present: pass
mtk-wdt-probed: pass
panel-edp-driver-present: pass
panel-simple-dp-aux-driver-present: pass
panel-simple-dp-aux-probed: fail
panfrost-driver-present: pass
panfrost-probed: fail
pwm-backlight-driver-present: pass
pwm-backlight-probed: fail
rt1015p-driver-present: pass
rt1015p-probed: fail
rt5682-driver-present: pass
rt5682-probed: fail
sbs-battery-driver-present: pass
sbs-battery-probed: pass
spmi-mtk-driver-present: pass
spmi-mtk-probed: pass
tpm-chip-is-online: pass
tpm_tis_spi-driver-present: pass
tpm_tis_spi-probed: pass
uvcvideo-driver-present: pass
uvcvideo0-probed: pass
uvcvideo1-probed: pass
xhci-mtk-driver-present: pass
xhci-mtk-probed: pass
11624 22:15:56.411484 end: 4.1 lava-test-shell (duration 00:00:24) [common]
11625 22:15:56.411982 end: 4 lava-test-retry (duration 00:00:24) [common]
11626 22:15:56.412441 start: 5 finalize (timeout 00:08:01) [common]
11627 22:15:56.413004 start: 5.1 power-off (timeout 00:00:30) [common]
11628 22:15:56.413851 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=off'
11629 22:15:56.531078 >> Command sent successfully.
11630 22:15:56.534660 Returned 0 in 0 seconds
11631 22:15:56.635520 end: 5.1 power-off (duration 00:00:00) [common]
11633 22:15:56.637184 start: 5.2 read-feedback (timeout 00:08:01) [common]
11635 22:15:56.639326 Listened to connection for namespace 'common' for up to 1s
11636 22:15:57.639042 Finalising connection for namespace 'common'
11637 22:15:57.639641 Disconnecting from shell: Finalise
11638 22:15:57.640016 / #
11639 22:15:57.741118 end: 5.2 read-feedback (duration 00:00:01) [common]
11640 22:15:57.741868 end: 5 finalize (duration 00:00:01) [common]
11641 22:15:57.742475 Cleaning after the job
11642 22:15:57.743034 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10597232/tftp-deploy-73mp9zex/ramdisk
11643 22:15:57.754908 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10597232/tftp-deploy-73mp9zex/kernel
11644 22:15:57.776662 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10597232/tftp-deploy-73mp9zex/dtb
11645 22:15:57.777122 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10597232/tftp-deploy-73mp9zex/modules
11646 22:15:57.782898 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/10597232
11647 22:15:57.820287 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/10597232
11648 22:15:57.820454 Job finished correctly