Boot log: mt8192-asurada-spherion-r0
- Errors: 2
- Kernel Errors: 40
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 33
1 22:13:43.912872 lava-dispatcher, installed at version: 2023.05.1
2 22:13:43.913069 start: 0 validate
3 22:13:43.913192 Start time: 2023-06-05 22:13:43.913185+00:00 (UTC)
4 22:13:43.913314 Using caching service: 'http://localhost/cache/?uri=%s'
5 22:13:43.913438 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye%2F20230527.0%2Farm64%2Finitrd.cpio.gz exists
6 22:13:44.230557 Using caching service: 'http://localhost/cache/?uri=%s'
7 22:13:44.231361 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1314-g1ab0ac1d7e2e3%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 22:13:44.521554 Using caching service: 'http://localhost/cache/?uri=%s'
9 22:13:44.521777 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1314-g1ab0ac1d7e2e3%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 22:13:44.814665 Using caching service: 'http://localhost/cache/?uri=%s'
11 22:13:44.814900 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye%2F20230527.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 22:13:45.105556 Using caching service: 'http://localhost/cache/?uri=%s'
13 22:13:45.105760 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1314-g1ab0ac1d7e2e3%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 22:13:45.108824 validate duration: 1.20
16 22:13:45.109126 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 22:13:45.109299 start: 1.1 download-retry (timeout 00:10:00) [common]
18 22:13:45.109423 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 22:13:45.109588 Not decompressing ramdisk as can be used compressed.
20 22:13:45.109705 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye/20230527.0/arm64/initrd.cpio.gz
21 22:13:45.109799 saving as /var/lib/lava/dispatcher/tmp/10597297/tftp-deploy-7relhzi_/ramdisk/initrd.cpio.gz
22 22:13:45.109897 total size: 4665395 (4MB)
23 22:13:45.111168 progress 0% (0MB)
24 22:13:45.113401 progress 5% (0MB)
25 22:13:45.115372 progress 10% (0MB)
26 22:13:45.117376 progress 15% (0MB)
27 22:13:45.119341 progress 20% (0MB)
28 22:13:45.121319 progress 25% (1MB)
29 22:13:45.123255 progress 30% (1MB)
30 22:13:45.125229 progress 35% (1MB)
31 22:13:45.127161 progress 40% (1MB)
32 22:13:45.129408 progress 45% (2MB)
33 22:13:45.131346 progress 50% (2MB)
34 22:13:45.133335 progress 55% (2MB)
35 22:13:45.135271 progress 60% (2MB)
36 22:13:45.137258 progress 65% (2MB)
37 22:13:45.139230 progress 70% (3MB)
38 22:13:45.141204 progress 75% (3MB)
39 22:13:45.143142 progress 80% (3MB)
40 22:13:45.145377 progress 85% (3MB)
41 22:13:45.147316 progress 90% (4MB)
42 22:13:45.149321 progress 95% (4MB)
43 22:13:45.151281 progress 100% (4MB)
44 22:13:45.151506 4MB downloaded in 0.04s (106.94MB/s)
45 22:13:45.151709 end: 1.1.1 http-download (duration 00:00:00) [common]
47 22:13:45.152067 end: 1.1 download-retry (duration 00:00:00) [common]
48 22:13:45.152190 start: 1.2 download-retry (timeout 00:10:00) [common]
49 22:13:45.152309 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 22:13:45.152483 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1314-g1ab0ac1d7e2e3/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 22:13:45.152624 saving as /var/lib/lava/dispatcher/tmp/10597297/tftp-deploy-7relhzi_/kernel/Image
52 22:13:45.152715 total size: 45746688 (43MB)
53 22:13:45.152804 No compression specified
54 22:13:45.154341 progress 0% (0MB)
55 22:13:45.166833 progress 5% (2MB)
56 22:13:45.178608 progress 10% (4MB)
57 22:13:45.190310 progress 15% (6MB)
58 22:13:45.201813 progress 20% (8MB)
59 22:13:45.213362 progress 25% (10MB)
60 22:13:45.224731 progress 30% (13MB)
61 22:13:45.236261 progress 35% (15MB)
62 22:13:45.247969 progress 40% (17MB)
63 22:13:45.259715 progress 45% (19MB)
64 22:13:45.271360 progress 50% (21MB)
65 22:13:45.282862 progress 55% (24MB)
66 22:13:45.294667 progress 60% (26MB)
67 22:13:45.306310 progress 65% (28MB)
68 22:13:45.317896 progress 70% (30MB)
69 22:13:45.329552 progress 75% (32MB)
70 22:13:45.341137 progress 80% (34MB)
71 22:13:45.352689 progress 85% (37MB)
72 22:13:45.364306 progress 90% (39MB)
73 22:13:45.375810 progress 95% (41MB)
74 22:13:45.387333 progress 100% (43MB)
75 22:13:45.387494 43MB downloaded in 0.23s (185.83MB/s)
76 22:13:45.387648 end: 1.2.1 http-download (duration 00:00:00) [common]
78 22:13:45.387880 end: 1.2 download-retry (duration 00:00:00) [common]
79 22:13:45.387968 start: 1.3 download-retry (timeout 00:10:00) [common]
80 22:13:45.388056 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 22:13:45.388198 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1314-g1ab0ac1d7e2e3/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 22:13:45.388272 saving as /var/lib/lava/dispatcher/tmp/10597297/tftp-deploy-7relhzi_/dtb/mt8192-asurada-spherion-r0.dtb
83 22:13:45.388336 total size: 46924 (0MB)
84 22:13:45.388395 No compression specified
85 22:13:45.389530 progress 69% (0MB)
86 22:13:45.389801 progress 100% (0MB)
87 22:13:45.389983 0MB downloaded in 0.00s (27.20MB/s)
88 22:13:45.390104 end: 1.3.1 http-download (duration 00:00:00) [common]
90 22:13:45.390368 end: 1.3 download-retry (duration 00:00:00) [common]
91 22:13:45.390456 start: 1.4 download-retry (timeout 00:10:00) [common]
92 22:13:45.390538 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 22:13:45.390652 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye/20230527.0/arm64/full.rootfs.tar.xz
94 22:13:45.390720 saving as /var/lib/lava/dispatcher/tmp/10597297/tftp-deploy-7relhzi_/nfsrootfs/full.rootfs.tar
95 22:13:45.390782 total size: 125267308 (119MB)
96 22:13:45.390841 Using unxz to decompress xz
97 22:13:45.394430 progress 0% (0MB)
98 22:13:45.713492 progress 5% (6MB)
99 22:13:46.041789 progress 10% (11MB)
100 22:13:46.365659 progress 15% (17MB)
101 22:13:46.553863 progress 20% (23MB)
102 22:13:46.735031 progress 25% (29MB)
103 22:13:47.085831 progress 30% (35MB)
104 22:13:47.434270 progress 35% (41MB)
105 22:13:47.812593 progress 40% (47MB)
106 22:13:48.180604 progress 45% (53MB)
107 22:13:48.556029 progress 50% (59MB)
108 22:13:48.907750 progress 55% (65MB)
109 22:13:49.262806 progress 60% (71MB)
110 22:13:49.599237 progress 65% (77MB)
111 22:13:49.958023 progress 70% (83MB)
112 22:13:50.333256 progress 75% (89MB)
113 22:13:50.745443 progress 80% (95MB)
114 22:13:51.156824 progress 85% (101MB)
115 22:13:51.392058 progress 90% (107MB)
116 22:13:51.718876 progress 95% (113MB)
117 22:13:52.081006 progress 100% (119MB)
118 22:13:52.087128 119MB downloaded in 6.70s (17.84MB/s)
119 22:13:52.087406 end: 1.4.1 http-download (duration 00:00:07) [common]
121 22:13:52.087668 end: 1.4 download-retry (duration 00:00:07) [common]
122 22:13:52.087757 start: 1.5 download-retry (timeout 00:09:53) [common]
123 22:13:52.087844 start: 1.5.1 http-download (timeout 00:09:53) [common]
124 22:13:52.087993 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1314-g1ab0ac1d7e2e3/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 22:13:52.088064 saving as /var/lib/lava/dispatcher/tmp/10597297/tftp-deploy-7relhzi_/modules/modules.tar
126 22:13:52.088125 total size: 8543056 (8MB)
127 22:13:52.088186 Using unxz to decompress xz
128 22:13:52.091787 progress 0% (0MB)
129 22:13:52.112974 progress 5% (0MB)
130 22:13:52.138325 progress 10% (0MB)
131 22:13:52.163976 progress 15% (1MB)
132 22:13:52.188694 progress 20% (1MB)
133 22:13:52.211651 progress 25% (2MB)
134 22:13:52.238061 progress 30% (2MB)
135 22:13:52.263111 progress 35% (2MB)
136 22:13:52.287014 progress 40% (3MB)
137 22:13:52.310473 progress 45% (3MB)
138 22:13:52.334934 progress 50% (4MB)
139 22:13:52.358454 progress 55% (4MB)
140 22:13:52.382727 progress 60% (4MB)
141 22:13:52.407474 progress 65% (5MB)
142 22:13:52.431765 progress 70% (5MB)
143 22:13:52.455163 progress 75% (6MB)
144 22:13:52.479729 progress 80% (6MB)
145 22:13:52.504386 progress 85% (6MB)
146 22:13:52.533263 progress 90% (7MB)
147 22:13:52.558717 progress 95% (7MB)
148 22:13:52.582902 progress 100% (8MB)
149 22:13:52.588764 8MB downloaded in 0.50s (16.27MB/s)
150 22:13:52.589052 end: 1.5.1 http-download (duration 00:00:01) [common]
152 22:13:52.589315 end: 1.5 download-retry (duration 00:00:01) [common]
153 22:13:52.589408 start: 1.6 prepare-tftp-overlay (timeout 00:09:53) [common]
154 22:13:52.589500 start: 1.6.1 extract-nfsrootfs (timeout 00:09:53) [common]
155 22:13:54.551371 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/10597297/extract-nfsrootfs-iuuo3m7a
156 22:13:54.551580 end: 1.6.1 extract-nfsrootfs (duration 00:00:02) [common]
157 22:13:54.551683 start: 1.6.2 lava-overlay (timeout 00:09:51) [common]
158 22:13:54.551852 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/10597297/lava-overlay-okhwrnmm
159 22:13:54.551978 makedir: /var/lib/lava/dispatcher/tmp/10597297/lava-overlay-okhwrnmm/lava-10597297/bin
160 22:13:54.552078 makedir: /var/lib/lava/dispatcher/tmp/10597297/lava-overlay-okhwrnmm/lava-10597297/tests
161 22:13:54.552172 makedir: /var/lib/lava/dispatcher/tmp/10597297/lava-overlay-okhwrnmm/lava-10597297/results
162 22:13:54.552271 Creating /var/lib/lava/dispatcher/tmp/10597297/lava-overlay-okhwrnmm/lava-10597297/bin/lava-add-keys
163 22:13:54.552409 Creating /var/lib/lava/dispatcher/tmp/10597297/lava-overlay-okhwrnmm/lava-10597297/bin/lava-add-sources
164 22:13:54.552554 Creating /var/lib/lava/dispatcher/tmp/10597297/lava-overlay-okhwrnmm/lava-10597297/bin/lava-background-process-start
165 22:13:54.552687 Creating /var/lib/lava/dispatcher/tmp/10597297/lava-overlay-okhwrnmm/lava-10597297/bin/lava-background-process-stop
166 22:13:54.552804 Creating /var/lib/lava/dispatcher/tmp/10597297/lava-overlay-okhwrnmm/lava-10597297/bin/lava-common-functions
167 22:13:54.552918 Creating /var/lib/lava/dispatcher/tmp/10597297/lava-overlay-okhwrnmm/lava-10597297/bin/lava-echo-ipv4
168 22:13:54.553033 Creating /var/lib/lava/dispatcher/tmp/10597297/lava-overlay-okhwrnmm/lava-10597297/bin/lava-install-packages
169 22:13:54.553146 Creating /var/lib/lava/dispatcher/tmp/10597297/lava-overlay-okhwrnmm/lava-10597297/bin/lava-installed-packages
170 22:13:54.553258 Creating /var/lib/lava/dispatcher/tmp/10597297/lava-overlay-okhwrnmm/lava-10597297/bin/lava-os-build
171 22:13:54.553373 Creating /var/lib/lava/dispatcher/tmp/10597297/lava-overlay-okhwrnmm/lava-10597297/bin/lava-probe-channel
172 22:13:54.553486 Creating /var/lib/lava/dispatcher/tmp/10597297/lava-overlay-okhwrnmm/lava-10597297/bin/lava-probe-ip
173 22:13:54.553599 Creating /var/lib/lava/dispatcher/tmp/10597297/lava-overlay-okhwrnmm/lava-10597297/bin/lava-target-ip
174 22:13:54.553711 Creating /var/lib/lava/dispatcher/tmp/10597297/lava-overlay-okhwrnmm/lava-10597297/bin/lava-target-mac
175 22:13:54.553824 Creating /var/lib/lava/dispatcher/tmp/10597297/lava-overlay-okhwrnmm/lava-10597297/bin/lava-target-storage
176 22:13:54.553939 Creating /var/lib/lava/dispatcher/tmp/10597297/lava-overlay-okhwrnmm/lava-10597297/bin/lava-test-case
177 22:13:54.554054 Creating /var/lib/lava/dispatcher/tmp/10597297/lava-overlay-okhwrnmm/lava-10597297/bin/lava-test-event
178 22:13:54.554168 Creating /var/lib/lava/dispatcher/tmp/10597297/lava-overlay-okhwrnmm/lava-10597297/bin/lava-test-feedback
179 22:13:54.554283 Creating /var/lib/lava/dispatcher/tmp/10597297/lava-overlay-okhwrnmm/lava-10597297/bin/lava-test-raise
180 22:13:54.554396 Creating /var/lib/lava/dispatcher/tmp/10597297/lava-overlay-okhwrnmm/lava-10597297/bin/lava-test-reference
181 22:13:54.554511 Creating /var/lib/lava/dispatcher/tmp/10597297/lava-overlay-okhwrnmm/lava-10597297/bin/lava-test-runner
182 22:13:54.554625 Creating /var/lib/lava/dispatcher/tmp/10597297/lava-overlay-okhwrnmm/lava-10597297/bin/lava-test-set
183 22:13:54.554738 Creating /var/lib/lava/dispatcher/tmp/10597297/lava-overlay-okhwrnmm/lava-10597297/bin/lava-test-shell
184 22:13:54.554853 Updating /var/lib/lava/dispatcher/tmp/10597297/lava-overlay-okhwrnmm/lava-10597297/bin/lava-install-packages (oe)
185 22:13:54.554996 Updating /var/lib/lava/dispatcher/tmp/10597297/lava-overlay-okhwrnmm/lava-10597297/bin/lava-installed-packages (oe)
186 22:13:54.555110 Creating /var/lib/lava/dispatcher/tmp/10597297/lava-overlay-okhwrnmm/lava-10597297/environment
187 22:13:54.555200 LAVA metadata
188 22:13:54.555276 - LAVA_JOB_ID=10597297
189 22:13:54.555336 - LAVA_DISPATCHER_IP=192.168.201.1
190 22:13:54.555434 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:51) [common]
191 22:13:54.555496 skipped lava-vland-overlay
192 22:13:54.555567 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
193 22:13:54.555645 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:51) [common]
194 22:13:54.555703 skipped lava-multinode-overlay
195 22:13:54.555772 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
196 22:13:54.555846 start: 1.6.2.3 test-definition (timeout 00:09:51) [common]
197 22:13:54.555916 Loading test definitions
198 22:13:54.556003 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:51) [common]
199 22:13:54.556071 Using /lava-10597297 at stage 0
200 22:13:54.556367 uuid=10597297_1.6.2.3.1 testdef=None
201 22:13:54.556473 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
202 22:13:54.556622 start: 1.6.2.3.2 test-overlay (timeout 00:09:51) [common]
203 22:13:54.557125 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
205 22:13:54.557343 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:51) [common]
206 22:13:54.557957 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
208 22:13:54.558177 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:51) [common]
209 22:13:54.558779 runner path: /var/lib/lava/dispatcher/tmp/10597297/lava-overlay-okhwrnmm/lava-10597297/0/tests/0_dmesg test_uuid 10597297_1.6.2.3.1
210 22:13:54.558925 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
212 22:13:54.559140 start: 1.6.2.3.5 inline-repo-action (timeout 00:09:51) [common]
213 22:13:54.559207 Using /lava-10597297 at stage 1
214 22:13:54.559488 uuid=10597297_1.6.2.3.5 testdef=None
215 22:13:54.559572 end: 1.6.2.3.5 inline-repo-action (duration 00:00:00) [common]
216 22:13:54.559652 start: 1.6.2.3.6 test-overlay (timeout 00:09:51) [common]
217 22:13:54.560095 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
219 22:13:54.560301 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:51) [common]
220 22:13:54.560961 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
222 22:13:54.561180 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:51) [common]
223 22:13:54.561782 runner path: /var/lib/lava/dispatcher/tmp/10597297/lava-overlay-okhwrnmm/lava-10597297/1/tests/1_bootrr test_uuid 10597297_1.6.2.3.5
224 22:13:54.561925 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
226 22:13:54.562119 Creating lava-test-runner.conf files
227 22:13:54.562179 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10597297/lava-overlay-okhwrnmm/lava-10597297/0 for stage 0
228 22:13:54.562262 - 0_dmesg
229 22:13:54.562336 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10597297/lava-overlay-okhwrnmm/lava-10597297/1 for stage 1
230 22:13:54.562420 - 1_bootrr
231 22:13:54.562514 end: 1.6.2.3 test-definition (duration 00:00:00) [common]
232 22:13:54.562598 start: 1.6.2.4 compress-overlay (timeout 00:09:51) [common]
233 22:13:54.569847 end: 1.6.2.4 compress-overlay (duration 00:00:00) [common]
234 22:13:54.569972 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:51) [common]
235 22:13:54.570057 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
236 22:13:54.570140 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
237 22:13:54.570221 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:51) [common]
238 22:13:54.685783 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
239 22:13:54.686165 start: 1.6.4 extract-modules (timeout 00:09:50) [common]
240 22:13:54.686288 extracting modules file /var/lib/lava/dispatcher/tmp/10597297/tftp-deploy-7relhzi_/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10597297/extract-nfsrootfs-iuuo3m7a
241 22:13:54.887523 extracting modules file /var/lib/lava/dispatcher/tmp/10597297/tftp-deploy-7relhzi_/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10597297/extract-overlay-ramdisk-2msk16_w/ramdisk
242 22:13:55.094988 end: 1.6.4 extract-modules (duration 00:00:00) [common]
243 22:13:55.095164 start: 1.6.5 apply-overlay-tftp (timeout 00:09:50) [common]
244 22:13:55.095260 [common] Applying overlay to NFS
245 22:13:55.095329 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10597297/compress-overlay-29g2eb98/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/10597297/extract-nfsrootfs-iuuo3m7a
246 22:13:55.103043 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
247 22:13:55.103182 start: 1.6.6 configure-preseed-file (timeout 00:09:50) [common]
248 22:13:55.103312 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
249 22:13:55.103400 start: 1.6.7 compress-ramdisk (timeout 00:09:50) [common]
250 22:13:55.103481 Building ramdisk /var/lib/lava/dispatcher/tmp/10597297/extract-overlay-ramdisk-2msk16_w/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/10597297/extract-overlay-ramdisk-2msk16_w/ramdisk
251 22:13:55.376171 >> 117807 blocks
252 22:13:57.285654 rename /var/lib/lava/dispatcher/tmp/10597297/extract-overlay-ramdisk-2msk16_w/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/10597297/tftp-deploy-7relhzi_/ramdisk/ramdisk.cpio.gz
253 22:13:57.286097 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
254 22:13:57.286222 start: 1.6.8 prepare-kernel (timeout 00:09:48) [common]
255 22:13:57.286318 start: 1.6.8.1 prepare-fit (timeout 00:09:48) [common]
256 22:13:57.286426 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/10597297/tftp-deploy-7relhzi_/kernel/Image'
257 22:14:09.403389 Returned 0 in 12 seconds
258 22:14:09.504018 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/10597297/tftp-deploy-7relhzi_/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/10597297/tftp-deploy-7relhzi_/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/10597297/tftp-deploy-7relhzi_/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/10597297/tftp-deploy-7relhzi_/kernel/image.itb
259 22:14:09.830761 output: FIT description: Kernel Image image with one or more FDT blobs
260 22:14:09.831129 output: Created: Mon Jun 5 23:14:09 2023
261 22:14:09.831208 output: Image 0 (kernel-1)
262 22:14:09.831276 output: Description:
263 22:14:09.831340 output: Created: Mon Jun 5 23:14:09 2023
264 22:14:09.831400 output: Type: Kernel Image
265 22:14:09.831461 output: Compression: lzma compressed
266 22:14:09.831522 output: Data Size: 10082307 Bytes = 9846.00 KiB = 9.62 MiB
267 22:14:09.831580 output: Architecture: AArch64
268 22:14:09.831646 output: OS: Linux
269 22:14:09.831704 output: Load Address: 0x00000000
270 22:14:09.831763 output: Entry Point: 0x00000000
271 22:14:09.831819 output: Hash algo: crc32
272 22:14:09.831873 output: Hash value: c242daf7
273 22:14:09.831926 output: Image 1 (fdt-1)
274 22:14:09.831979 output: Description: mt8192-asurada-spherion-r0
275 22:14:09.832033 output: Created: Mon Jun 5 23:14:09 2023
276 22:14:09.832086 output: Type: Flat Device Tree
277 22:14:09.832140 output: Compression: uncompressed
278 22:14:09.832193 output: Data Size: 46924 Bytes = 45.82 KiB = 0.04 MiB
279 22:14:09.832247 output: Architecture: AArch64
280 22:14:09.832299 output: Hash algo: crc32
281 22:14:09.832352 output: Hash value: 1df858fa
282 22:14:09.832406 output: Image 2 (ramdisk-1)
283 22:14:09.832458 output: Description: unavailable
284 22:14:09.832511 output: Created: Mon Jun 5 23:14:09 2023
285 22:14:09.832611 output: Type: RAMDisk Image
286 22:14:09.832665 output: Compression: Unknown Compression
287 22:14:09.832718 output: Data Size: 17645513 Bytes = 17231.95 KiB = 16.83 MiB
288 22:14:09.832771 output: Architecture: AArch64
289 22:14:09.832824 output: OS: Linux
290 22:14:09.832877 output: Load Address: unavailable
291 22:14:09.832931 output: Entry Point: unavailable
292 22:14:09.832983 output: Hash algo: crc32
293 22:14:09.833036 output: Hash value: 4366e44a
294 22:14:09.833089 output: Default Configuration: 'conf-1'
295 22:14:09.833142 output: Configuration 0 (conf-1)
296 22:14:09.833198 output: Description: mt8192-asurada-spherion-r0
297 22:14:09.833251 output: Kernel: kernel-1
298 22:14:09.833304 output: Init Ramdisk: ramdisk-1
299 22:14:09.833357 output: FDT: fdt-1
300 22:14:09.833410 output: Loadables: kernel-1
301 22:14:09.833463 output:
302 22:14:09.833670 end: 1.6.8.1 prepare-fit (duration 00:00:13) [common]
303 22:14:09.833803 end: 1.6.8 prepare-kernel (duration 00:00:13) [common]
304 22:14:09.833914 end: 1.6 prepare-tftp-overlay (duration 00:00:17) [common]
305 22:14:09.834019 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:35) [common]
306 22:14:09.834106 No LXC device requested
307 22:14:09.834186 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
308 22:14:09.834271 start: 1.8 deploy-device-env (timeout 00:09:35) [common]
309 22:14:09.834348 end: 1.8 deploy-device-env (duration 00:00:00) [common]
310 22:14:09.834414 Checking files for TFTP limit of 4294967296 bytes.
311 22:14:09.834912 end: 1 tftp-deploy (duration 00:00:25) [common]
312 22:14:09.835014 start: 2 depthcharge-action (timeout 00:05:00) [common]
313 22:14:09.835110 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
314 22:14:09.835232 substitutions:
315 22:14:09.835300 - {DTB}: 10597297/tftp-deploy-7relhzi_/dtb/mt8192-asurada-spherion-r0.dtb
316 22:14:09.835364 - {INITRD}: 10597297/tftp-deploy-7relhzi_/ramdisk/ramdisk.cpio.gz
317 22:14:09.835423 - {KERNEL}: 10597297/tftp-deploy-7relhzi_/kernel/Image
318 22:14:09.835480 - {LAVA_MAC}: None
319 22:14:09.835537 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/10597297/extract-nfsrootfs-iuuo3m7a
320 22:14:09.835593 - {NFS_SERVER_IP}: 192.168.201.1
321 22:14:09.835648 - {PRESEED_CONFIG}: None
322 22:14:09.835704 - {PRESEED_LOCAL}: None
323 22:14:09.835758 - {RAMDISK}: 10597297/tftp-deploy-7relhzi_/ramdisk/ramdisk.cpio.gz
324 22:14:09.835812 - {ROOT_PART}: None
325 22:14:09.835867 - {ROOT}: None
326 22:14:09.835921 - {SERVER_IP}: 192.168.201.1
327 22:14:09.835974 - {TEE}: None
328 22:14:09.836028 Parsed boot commands:
329 22:14:09.836081 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
330 22:14:09.836253 Parsed boot commands: tftpboot 192.168.201.1 10597297/tftp-deploy-7relhzi_/kernel/image.itb 10597297/tftp-deploy-7relhzi_/kernel/cmdline
331 22:14:09.836342 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
332 22:14:09.836426 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
333 22:14:09.836524 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
334 22:14:09.836658 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
335 22:14:09.836729 Not connected, no need to disconnect.
336 22:14:09.836805 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
337 22:14:09.836886 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
338 22:14:09.836955 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost mt8192-asurada-spherion-r0-cbg-9'
339 22:14:09.840272 Setting prompt string to ['lava-test: # ']
340 22:14:09.840701 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
341 22:14:09.840841 end: 2.2.1 reset-connection (duration 00:00:00) [common]
342 22:14:09.841008 start: 2.2.2 reset-device (timeout 00:05:00) [common]
343 22:14:09.841128 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
344 22:14:09.841456 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-9' '--port=1' '--command=reboot'
345 22:14:14.980171 >> Command sent successfully.
346 22:14:14.985716 Returned 0 in 5 seconds
347 22:14:15.086439 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
349 22:14:15.087506 end: 2.2.2 reset-device (duration 00:00:05) [common]
350 22:14:15.087933 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
351 22:14:15.088238 Setting prompt string to 'Starting depthcharge on Spherion...'
352 22:14:15.088496 Changing prompt to 'Starting depthcharge on Spherion...'
353 22:14:15.088823 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
354 22:14:15.089761 [Enter `^Ec?' for help]
355 22:14:15.256329
356 22:14:15.256964
357 22:14:15.257363 F0: 102B 0000
358 22:14:15.257717
359 22:14:15.258058 F3: 1001 0000 [0200]
360 22:14:15.258397
361 22:14:15.260078 F3: 1001 0000
362 22:14:15.260600
363 22:14:15.261047 F7: 102D 0000
364 22:14:15.261408
365 22:14:15.261749 F1: 0000 0000
366 22:14:15.263904
367 22:14:15.264471 V0: 0000 0000 [0001]
368 22:14:15.264905
369 22:14:15.265259 00: 0007 8000
370 22:14:15.266609
371 22:14:15.267083 01: 0000 0000
372 22:14:15.267473
373 22:14:15.267826 BP: 0C00 0209 [0000]
374 22:14:15.268163
375 22:14:15.269804 G0: 1182 0000
376 22:14:15.270279
377 22:14:15.270749 EC: 0000 0021 [4000]
378 22:14:15.271119
379 22:14:15.273180 S7: 0000 0000 [0000]
380 22:14:15.273656
381 22:14:15.274033 CC: 0000 0000 [0001]
382 22:14:15.276499
383 22:14:15.277010 T0: 0000 0040 [010F]
384 22:14:15.277412
385 22:14:15.277767 Jump to BL
386 22:14:15.278109
387 22:14:15.303372
388 22:14:15.303949
389 22:14:15.304330
390 22:14:15.310703 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
391 22:14:15.314108 ARM64: Exception handlers installed.
392 22:14:15.317930 ARM64: Testing exception
393 22:14:15.321077 ARM64: Done test exception
394 22:14:15.328639 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
395 22:14:15.338637 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
396 22:14:15.345229 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
397 22:14:15.355131 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
398 22:14:15.361831 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
399 22:14:15.368498 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
400 22:14:15.379760 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
401 22:14:15.386424 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
402 22:14:15.406234 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
403 22:14:15.409552 WDT: Last reset was cold boot
404 22:14:15.412952 SPI1(PAD0) initialized at 2873684 Hz
405 22:14:15.415854 SPI5(PAD0) initialized at 992727 Hz
406 22:14:15.419086 VBOOT: Loading verstage.
407 22:14:15.425903 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
408 22:14:15.429328 FMAP: Found "FLASH" version 1.1 at 0x20000.
409 22:14:15.432295 FMAP: base = 0x0 size = 0x800000 #areas = 25
410 22:14:15.435706 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
411 22:14:15.444075 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
412 22:14:15.450219 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
413 22:14:15.461132 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
414 22:14:15.461722
415 22:14:15.462203
416 22:14:15.470984 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
417 22:14:15.474332 ARM64: Exception handlers installed.
418 22:14:15.477914 ARM64: Testing exception
419 22:14:15.478483 ARM64: Done test exception
420 22:14:15.484406 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
421 22:14:15.487315 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 22:14:15.502021 Probing TPM: . done!
423 22:14:15.502612 TPM ready after 0 ms
424 22:14:15.509263 Connected to device vid:did:rid of 1ae0:0028:00
425 22:14:15.518280 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
426 22:14:15.556663 Initialized TPM device CR50 revision 0
427 22:14:15.569229 tlcl_send_startup: Startup return code is 0
428 22:14:15.569796 TPM: setup succeeded
429 22:14:15.581641 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
430 22:14:15.589514 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
431 22:14:15.600635 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
432 22:14:15.610023 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
433 22:14:15.613103 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
434 22:14:15.616554 in-header: 03 07 00 00 08 00 00 00
435 22:14:15.619787 in-data: aa e4 47 04 13 02 00 00
436 22:14:15.622916 Chrome EC: UHEPI supported
437 22:14:15.629668 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
438 22:14:15.632812 in-header: 03 ad 00 00 08 00 00 00
439 22:14:15.636794 in-data: 00 20 20 08 00 00 00 00
440 22:14:15.637265 Phase 1
441 22:14:15.639918 FMAP: area GBB found @ 3f5000 (12032 bytes)
442 22:14:15.646230 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
443 22:14:15.653610 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
444 22:14:15.655755 Recovery requested (1009000e)
445 22:14:15.660179 TPM: Extending digest for VBOOT: boot mode into PCR 0
446 22:14:15.668850 tlcl_extend: response is 0
447 22:14:15.677163 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
448 22:14:15.682736 tlcl_extend: response is 0
449 22:14:15.688705 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
450 22:14:15.709698 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
451 22:14:15.716006 BS: bootblock times (exec / console): total (unknown) / 148 ms
452 22:14:15.716673
453 22:14:15.717231
454 22:14:15.726706 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
455 22:14:15.730298 ARM64: Exception handlers installed.
456 22:14:15.730807 ARM64: Testing exception
457 22:14:15.733036 ARM64: Done test exception
458 22:14:15.754944 pmic_efuse_setting: Set efuses in 11 msecs
459 22:14:15.758508 pmwrap_interface_init: Select PMIF_VLD_RDY
460 22:14:15.766258 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
461 22:14:15.768823 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
462 22:14:15.772252 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
463 22:14:15.779153 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
464 22:14:15.782146 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
465 22:14:15.788600 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
466 22:14:15.792287 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
467 22:14:15.798507 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
468 22:14:15.802204 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
469 22:14:15.805163 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
470 22:14:15.811288 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
471 22:14:15.814704 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
472 22:14:15.821351 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
473 22:14:15.828413 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
474 22:14:15.831558 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
475 22:14:15.837862 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
476 22:14:15.844780 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
477 22:14:15.847994 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
478 22:14:15.854825 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
479 22:14:15.861299 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
480 22:14:15.864846 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
481 22:14:15.872037 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
482 22:14:15.879228 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
483 22:14:15.882828 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
484 22:14:15.889426 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
485 22:14:15.892689 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
486 22:14:15.900472 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
487 22:14:15.903285 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
488 22:14:15.907515 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
489 22:14:15.913930 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
490 22:14:15.917439 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
491 22:14:15.923983 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
492 22:14:15.927802 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
493 22:14:15.934107 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
494 22:14:15.937609 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
495 22:14:15.944129 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
496 22:14:15.947847 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
497 22:14:15.955232 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
498 22:14:15.959007 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
499 22:14:15.962281 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
500 22:14:15.965742 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
501 22:14:15.972131 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
502 22:14:15.975823 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
503 22:14:15.978653 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
504 22:14:15.985825 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
505 22:14:15.988557 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
506 22:14:15.991933 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
507 22:14:15.995444 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
508 22:14:16.001956 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
509 22:14:16.005422 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
510 22:14:16.008475 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
511 22:14:16.018579 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
512 22:14:16.025253 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
513 22:14:16.031859 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
514 22:14:16.038316 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
515 22:14:16.048638 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
516 22:14:16.051575 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
517 22:14:16.054762 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
518 22:14:16.061343 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
519 22:14:16.068805 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6c, sec=0x2e
520 22:14:16.071747 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
521 22:14:16.078734 [RTC]rtc_osc_init,62: osc32con val = 0xde6c
522 22:14:16.082201 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
523 22:14:16.091733 [RTC]rtc_get_frequency_meter,154: input=15, output=835
524 22:14:16.101356 [RTC]rtc_get_frequency_meter,154: input=7, output=708
525 22:14:16.110256 [RTC]rtc_get_frequency_meter,154: input=11, output=772
526 22:14:16.120019 [RTC]rtc_get_frequency_meter,154: input=13, output=804
527 22:14:16.129956 [RTC]rtc_get_frequency_meter,154: input=12, output=788
528 22:14:16.139392 [RTC]rtc_get_frequency_meter,154: input=12, output=788
529 22:14:16.148696 [RTC]rtc_get_frequency_meter,154: input=13, output=804
530 22:14:16.152048 [RTC]rtc_eosc_cali,47: left: 12, middle: 12, right: 13
531 22:14:16.158742 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6c
532 22:14:16.162229 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
533 22:14:16.165582 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
534 22:14:16.172131 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
535 22:14:16.175995 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
536 22:14:16.178671 ADC[4]: Raw value=904509 ID=7
537 22:14:16.178765 ADC[3]: Raw value=213282 ID=1
538 22:14:16.182178 RAM Code: 0x71
539 22:14:16.185791 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
540 22:14:16.191915 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
541 22:14:16.198488 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
542 22:14:16.205284 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
543 22:14:16.208452 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
544 22:14:16.211819 in-header: 03 07 00 00 08 00 00 00
545 22:14:16.215332 in-data: aa e4 47 04 13 02 00 00
546 22:14:16.219068 Chrome EC: UHEPI supported
547 22:14:16.225033 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
548 22:14:16.228487 in-header: 03 dd 00 00 08 00 00 00
549 22:14:16.232167 in-data: 90 20 60 08 00 00 00 00
550 22:14:16.235369 MRC: failed to locate region type 0.
551 22:14:16.242068 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
552 22:14:16.245258 DRAM-K: Running full calibration
553 22:14:16.251498 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
554 22:14:16.251576 header.status = 0x0
555 22:14:16.255168 header.version = 0x6 (expected: 0x6)
556 22:14:16.258312 header.size = 0xd00 (expected: 0xd00)
557 22:14:16.261606 header.flags = 0x0
558 22:14:16.268356 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
559 22:14:16.284812 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
560 22:14:16.291783 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
561 22:14:16.294932 dram_init: ddr_geometry: 2
562 22:14:16.298134 [EMI] MDL number = 2
563 22:14:16.298214 [EMI] Get MDL freq = 0
564 22:14:16.301665 dram_init: ddr_type: 0
565 22:14:16.301734 is_discrete_lpddr4: 1
566 22:14:16.304743 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
567 22:14:16.304827
568 22:14:16.304918
569 22:14:16.308394 [Bian_co] ETT version 0.0.0.1
570 22:14:16.315005 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
571 22:14:16.315112
572 22:14:16.318086 dramc_set_vcore_voltage set vcore to 650000
573 22:14:16.321466 Read voltage for 800, 4
574 22:14:16.321566 Vio18 = 0
575 22:14:16.321659 Vcore = 650000
576 22:14:16.325159 Vdram = 0
577 22:14:16.325236 Vddq = 0
578 22:14:16.325327 Vmddr = 0
579 22:14:16.328855 dram_init: config_dvfs: 1
580 22:14:16.331858 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
581 22:14:16.338263 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
582 22:14:16.341521 [SwImpedanceCal] DRVP=8, DRVN=16, ODTN=9
583 22:14:16.345166 freq_region=0, Reg: DRVP=8, DRVN=16, ODTN=9
584 22:14:16.348354 [SwImpedanceCal] DRVP=14, DRVN=24, ODTN=9
585 22:14:16.351343 freq_region=1, Reg: DRVP=14, DRVN=24, ODTN=9
586 22:14:16.354667 MEM_TYPE=3, freq_sel=18
587 22:14:16.357965 sv_algorithm_assistance_LP4_1600
588 22:14:16.361471 ============ PULL DRAM RESETB DOWN ============
589 22:14:16.368086 ========== PULL DRAM RESETB DOWN end =========
590 22:14:16.371717 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
591 22:14:16.374753 ===================================
592 22:14:16.378014 LPDDR4 DRAM CONFIGURATION
593 22:14:16.381241 ===================================
594 22:14:16.381315 EX_ROW_EN[0] = 0x0
595 22:14:16.384850 EX_ROW_EN[1] = 0x0
596 22:14:16.384925 LP4Y_EN = 0x0
597 22:14:16.388033 WORK_FSP = 0x0
598 22:14:16.388101 WL = 0x2
599 22:14:16.391107 RL = 0x2
600 22:14:16.391205 BL = 0x2
601 22:14:16.394781 RPST = 0x0
602 22:14:16.394875 RD_PRE = 0x0
603 22:14:16.397810 WR_PRE = 0x1
604 22:14:16.401247 WR_PST = 0x0
605 22:14:16.401315 DBI_WR = 0x0
606 22:14:16.404376 DBI_RD = 0x0
607 22:14:16.404470 OTF = 0x1
608 22:14:16.408052 ===================================
609 22:14:16.410911 ===================================
610 22:14:16.411010 ANA top config
611 22:14:16.414741 ===================================
612 22:14:16.417802 DLL_ASYNC_EN = 0
613 22:14:16.421014 ALL_SLAVE_EN = 1
614 22:14:16.424434 NEW_RANK_MODE = 1
615 22:14:16.427712 DLL_IDLE_MODE = 1
616 22:14:16.427781 LP45_APHY_COMB_EN = 1
617 22:14:16.431011 TX_ODT_DIS = 1
618 22:14:16.434987 NEW_8X_MODE = 1
619 22:14:16.438009 ===================================
620 22:14:16.440947 ===================================
621 22:14:16.444330 data_rate = 1600
622 22:14:16.447532 CKR = 1
623 22:14:16.447617 DQ_P2S_RATIO = 8
624 22:14:16.450897 ===================================
625 22:14:16.454157 CA_P2S_RATIO = 8
626 22:14:16.457915 DQ_CA_OPEN = 0
627 22:14:16.461165 DQ_SEMI_OPEN = 0
628 22:14:16.464371 CA_SEMI_OPEN = 0
629 22:14:16.467545 CA_FULL_RATE = 0
630 22:14:16.467628 DQ_CKDIV4_EN = 1
631 22:14:16.470761 CA_CKDIV4_EN = 1
632 22:14:16.474107 CA_PREDIV_EN = 0
633 22:14:16.479079 PH8_DLY = 0
634 22:14:16.481230 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
635 22:14:16.484772 DQ_AAMCK_DIV = 4
636 22:14:16.484847 CA_AAMCK_DIV = 4
637 22:14:16.487709 CA_ADMCK_DIV = 4
638 22:14:16.490810 DQ_TRACK_CA_EN = 0
639 22:14:16.494396 CA_PICK = 800
640 22:14:16.498145 CA_MCKIO = 800
641 22:14:16.501250 MCKIO_SEMI = 0
642 22:14:16.504462 PLL_FREQ = 3068
643 22:14:16.504542 DQ_UI_PI_RATIO = 32
644 22:14:16.507541 CA_UI_PI_RATIO = 0
645 22:14:16.510693 ===================================
646 22:14:16.514098 ===================================
647 22:14:16.517751 memory_type:LPDDR4
648 22:14:16.520943 GP_NUM : 10
649 22:14:16.521025 SRAM_EN : 1
650 22:14:16.524470 MD32_EN : 0
651 22:14:16.527334 ===================================
652 22:14:16.527417 [ANA_INIT] >>>>>>>>>>>>>>
653 22:14:16.530581 <<<<<< [CONFIGURE PHASE]: ANA_TX
654 22:14:16.534081 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
655 22:14:16.537658 ===================================
656 22:14:16.541567 data_rate = 1600,PCW = 0X7600
657 22:14:16.544393 ===================================
658 22:14:16.547721 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
659 22:14:16.554221 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
660 22:14:16.557782 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
661 22:14:16.564227 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
662 22:14:16.567496 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
663 22:14:16.570581 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
664 22:14:16.574237 [ANA_INIT] flow start
665 22:14:16.574320 [ANA_INIT] PLL >>>>>>>>
666 22:14:16.577256 [ANA_INIT] PLL <<<<<<<<
667 22:14:16.580578 [ANA_INIT] MIDPI >>>>>>>>
668 22:14:16.580673 [ANA_INIT] MIDPI <<<<<<<<
669 22:14:16.584154 [ANA_INIT] DLL >>>>>>>>
670 22:14:16.587232 [ANA_INIT] flow end
671 22:14:16.590548 ============ LP4 DIFF to SE enter ============
672 22:14:16.594038 ============ LP4 DIFF to SE exit ============
673 22:14:16.597550 [ANA_INIT] <<<<<<<<<<<<<
674 22:14:16.600716 [Flow] Enable top DCM control >>>>>
675 22:14:16.604062 [Flow] Enable top DCM control <<<<<
676 22:14:16.607411 Enable DLL master slave shuffle
677 22:14:16.611110 ==============================================================
678 22:14:16.614044 Gating Mode config
679 22:14:16.620992 ==============================================================
680 22:14:16.621076 Config description:
681 22:14:16.630536 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
682 22:14:16.637107 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
683 22:14:16.640713 SELPH_MODE 0: By rank 1: By Phase
684 22:14:16.646940 ==============================================================
685 22:14:16.650273 GAT_TRACK_EN = 1
686 22:14:16.653832 RX_GATING_MODE = 2
687 22:14:16.657239 RX_GATING_TRACK_MODE = 2
688 22:14:16.660260 SELPH_MODE = 1
689 22:14:16.663611 PICG_EARLY_EN = 1
690 22:14:16.666932 VALID_LAT_VALUE = 1
691 22:14:16.670462 ==============================================================
692 22:14:16.673558 Enter into Gating configuration >>>>
693 22:14:16.676963 Exit from Gating configuration <<<<
694 22:14:16.680093 Enter into DVFS_PRE_config >>>>>
695 22:14:16.690636 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
696 22:14:16.693873 Exit from DVFS_PRE_config <<<<<
697 22:14:16.697309 Enter into PICG configuration >>>>
698 22:14:16.700388 Exit from PICG configuration <<<<
699 22:14:16.703850 [RX_INPUT] configuration >>>>>
700 22:14:16.706956 [RX_INPUT] configuration <<<<<
701 22:14:16.714079 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
702 22:14:16.717724 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
703 22:14:16.724221 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
704 22:14:16.728668 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
705 22:14:16.735789 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
706 22:14:16.742875 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
707 22:14:16.746377 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
708 22:14:16.750157 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
709 22:14:16.753223 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
710 22:14:16.760613 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
711 22:14:16.763888 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
712 22:14:16.767325 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
713 22:14:16.770853 ===================================
714 22:14:16.774381 LPDDR4 DRAM CONFIGURATION
715 22:14:16.777800 ===================================
716 22:14:16.777885 EX_ROW_EN[0] = 0x0
717 22:14:16.781119 EX_ROW_EN[1] = 0x0
718 22:14:16.781208 LP4Y_EN = 0x0
719 22:14:16.784659 WORK_FSP = 0x0
720 22:14:16.784744 WL = 0x2
721 22:14:16.788259 RL = 0x2
722 22:14:16.788343 BL = 0x2
723 22:14:16.792019 RPST = 0x0
724 22:14:16.792103 RD_PRE = 0x0
725 22:14:16.795622 WR_PRE = 0x1
726 22:14:16.795741 WR_PST = 0x0
727 22:14:16.795842 DBI_WR = 0x0
728 22:14:16.799386 DBI_RD = 0x0
729 22:14:16.799469 OTF = 0x1
730 22:14:16.803377 ===================================
731 22:14:16.806934 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
732 22:14:16.811030 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
733 22:14:16.818281 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
734 22:14:16.821811 ===================================
735 22:14:16.821904 LPDDR4 DRAM CONFIGURATION
736 22:14:16.825911 ===================================
737 22:14:16.829074 EX_ROW_EN[0] = 0x10
738 22:14:16.829158 EX_ROW_EN[1] = 0x0
739 22:14:16.832974 LP4Y_EN = 0x0
740 22:14:16.833056 WORK_FSP = 0x0
741 22:14:16.836706 WL = 0x2
742 22:14:16.836787 RL = 0x2
743 22:14:16.836852 BL = 0x2
744 22:14:16.841074 RPST = 0x0
745 22:14:16.841157 RD_PRE = 0x0
746 22:14:16.844414 WR_PRE = 0x1
747 22:14:16.844544 WR_PST = 0x0
748 22:14:16.848077 DBI_WR = 0x0
749 22:14:16.848166 DBI_RD = 0x0
750 22:14:16.851516 OTF = 0x1
751 22:14:16.854839 ===================================
752 22:14:16.858701 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
753 22:14:16.863844 nWR fixed to 40
754 22:14:16.867517 [ModeRegInit_LP4] CH0 RK0
755 22:14:16.867600 [ModeRegInit_LP4] CH0 RK1
756 22:14:16.870728 [ModeRegInit_LP4] CH1 RK0
757 22:14:16.874288 [ModeRegInit_LP4] CH1 RK1
758 22:14:16.874370 match AC timing 13
759 22:14:16.878316 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
760 22:14:16.881064 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
761 22:14:16.888174 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
762 22:14:16.891624 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
763 22:14:16.894763 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
764 22:14:16.898395 [EMI DOE] emi_dcm 0
765 22:14:16.901794 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
766 22:14:16.901880 ==
767 22:14:16.904947 Dram Type= 6, Freq= 0, CH_0, rank 0
768 22:14:16.911622 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
769 22:14:16.911707 ==
770 22:14:16.914959 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
771 22:14:16.921868 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
772 22:14:16.931468 [CA 0] Center 37 (6~68) winsize 63
773 22:14:16.934166 [CA 1] Center 37 (6~68) winsize 63
774 22:14:16.937901 [CA 2] Center 34 (4~65) winsize 62
775 22:14:16.941275 [CA 3] Center 34 (4~65) winsize 62
776 22:14:16.944651 [CA 4] Center 33 (3~64) winsize 62
777 22:14:16.948027 [CA 5] Center 33 (3~64) winsize 62
778 22:14:16.948110
779 22:14:16.951248 [CmdBusTrainingLP45] Vref(ca) range 1: 34
780 22:14:16.951332
781 22:14:16.954895 [CATrainingPosCal] consider 1 rank data
782 22:14:16.957847 u2DelayCellTimex100 = 270/100 ps
783 22:14:16.960856 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
784 22:14:16.964451 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
785 22:14:16.971016 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
786 22:14:16.974172 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
787 22:14:16.977638 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
788 22:14:16.980955 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
789 22:14:16.981038
790 22:14:16.984061 CA PerBit enable=1, Macro0, CA PI delay=33
791 22:14:16.984144
792 22:14:16.987742 [CBTSetCACLKResult] CA Dly = 33
793 22:14:16.987825 CS Dly: 6 (0~37)
794 22:14:16.987890 ==
795 22:14:16.990722 Dram Type= 6, Freq= 0, CH_0, rank 1
796 22:14:16.997526 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
797 22:14:16.997637 ==
798 22:14:17.000648 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
799 22:14:17.007807 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
800 22:14:17.017874 [CA 0] Center 37 (6~68) winsize 63
801 22:14:17.020553 [CA 1] Center 37 (7~68) winsize 62
802 22:14:17.023833 [CA 2] Center 34 (4~65) winsize 62
803 22:14:17.027117 [CA 3] Center 34 (4~65) winsize 62
804 22:14:17.030480 [CA 4] Center 33 (3~64) winsize 62
805 22:14:17.033662 [CA 5] Center 33 (2~64) winsize 63
806 22:14:17.033745
807 22:14:17.037320 [CmdBusTrainingLP45] Vref(ca) range 1: 34
808 22:14:17.037403
809 22:14:17.040511 [CATrainingPosCal] consider 2 rank data
810 22:14:17.043822 u2DelayCellTimex100 = 270/100 ps
811 22:14:17.047157 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
812 22:14:17.050669 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
813 22:14:17.057507 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
814 22:14:17.060781 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
815 22:14:17.064755 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
816 22:14:17.068848 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
817 22:14:17.068957
818 22:14:17.071879 CA PerBit enable=1, Macro0, CA PI delay=33
819 22:14:17.071963
820 22:14:17.072029 [CBTSetCACLKResult] CA Dly = 33
821 22:14:17.075710 CS Dly: 6 (0~38)
822 22:14:17.075792
823 22:14:17.079293 ----->DramcWriteLeveling(PI) begin...
824 22:14:17.079377 ==
825 22:14:17.082992 Dram Type= 6, Freq= 0, CH_0, rank 0
826 22:14:17.086907 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
827 22:14:17.087003 ==
828 22:14:17.090257 Write leveling (Byte 0): 31 => 31
829 22:14:17.093626 Write leveling (Byte 1): 31 => 31
830 22:14:17.096722 DramcWriteLeveling(PI) end<-----
831 22:14:17.096801
832 22:14:17.096885 ==
833 22:14:17.100285 Dram Type= 6, Freq= 0, CH_0, rank 0
834 22:14:17.103942 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
835 22:14:17.104020 ==
836 22:14:17.107036 [Gating] SW mode calibration
837 22:14:17.113135 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
838 22:14:17.119899 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
839 22:14:17.124367 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
840 22:14:17.126898 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
841 22:14:17.133502 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
842 22:14:17.136605 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
843 22:14:17.139770 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
844 22:14:17.143421 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
845 22:14:17.150021 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
846 22:14:17.153243 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
847 22:14:17.156825 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
848 22:14:17.163364 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
849 22:14:17.166732 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
850 22:14:17.169883 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
851 22:14:17.176061 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
852 22:14:17.179720 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
853 22:14:17.183093 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
854 22:14:17.189396 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
855 22:14:17.193066 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 22:14:17.196204 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
857 22:14:17.202634 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
858 22:14:17.206258 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
859 22:14:17.209323 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 22:14:17.216187 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 22:14:17.219195 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 22:14:17.222955 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 22:14:17.229305 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 22:14:17.232598 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 22:14:17.236062 0 9 8 | B1->B0 | 2323 2a2a | 0 1 | (0 0) (1 1)
866 22:14:17.242380 0 9 12 | B1->B0 | 2d2d 3434 | 1 1 | (1 1) (1 1)
867 22:14:17.245915 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
868 22:14:17.249536 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
869 22:14:17.255779 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
870 22:14:17.259146 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
871 22:14:17.262659 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
872 22:14:17.269200 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
873 22:14:17.273146 0 10 8 | B1->B0 | 3232 2f2f | 1 0 | (1 0) (1 1)
874 22:14:17.276352 0 10 12 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
875 22:14:17.282234 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 22:14:17.285849 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
877 22:14:17.289556 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
878 22:14:17.295772 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
879 22:14:17.298748 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
880 22:14:17.302304 0 11 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
881 22:14:17.308994 0 11 8 | B1->B0 | 2323 3939 | 0 1 | (0 0) (0 0)
882 22:14:17.312752 0 11 12 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
883 22:14:17.315476 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
884 22:14:17.321853 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
885 22:14:17.325458 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
886 22:14:17.328781 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
887 22:14:17.335465 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
888 22:14:17.338632 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
889 22:14:17.342091 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
890 22:14:17.345523 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
891 22:14:17.352286 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
892 22:14:17.355234 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
893 22:14:17.358796 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
894 22:14:17.364970 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
895 22:14:17.368839 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
896 22:14:17.371720 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
897 22:14:17.378686 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
898 22:14:17.381536 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
899 22:14:17.385156 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
900 22:14:17.391863 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
901 22:14:17.395073 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
902 22:14:17.398652 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
903 22:14:17.405321 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
904 22:14:17.408523 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 22:14:17.411814 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
906 22:14:17.414752 Total UI for P1: 0, mck2ui 16
907 22:14:17.418347 best dqsien dly found for B0: ( 0, 14, 6)
908 22:14:17.425178 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
909 22:14:17.425258 Total UI for P1: 0, mck2ui 16
910 22:14:17.432187 best dqsien dly found for B1: ( 0, 14, 8)
911 22:14:17.435195 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
912 22:14:17.438546 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
913 22:14:17.438623
914 22:14:17.441276 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
915 22:14:17.444993 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
916 22:14:17.449148 [Gating] SW calibration Done
917 22:14:17.449231 ==
918 22:14:17.453202 Dram Type= 6, Freq= 0, CH_0, rank 0
919 22:14:17.455718 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
920 22:14:17.455820 ==
921 22:14:17.455904 RX Vref Scan: 0
922 22:14:17.456003
923 22:14:17.459330 RX Vref 0 -> 0, step: 1
924 22:14:17.459405
925 22:14:17.462215 RX Delay -130 -> 252, step: 16
926 22:14:17.466106 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
927 22:14:17.468951 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
928 22:14:17.475847 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
929 22:14:17.478707 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
930 22:14:17.482116 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
931 22:14:17.485546 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
932 22:14:17.488902 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
933 22:14:17.495411 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
934 22:14:17.498901 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
935 22:14:17.502130 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
936 22:14:17.505125 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
937 22:14:17.508491 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
938 22:14:17.514872 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
939 22:14:17.518240 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
940 22:14:17.521599 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
941 22:14:17.524903 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
942 22:14:17.524981 ==
943 22:14:17.528545 Dram Type= 6, Freq= 0, CH_0, rank 0
944 22:14:17.534819 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
945 22:14:17.534901 ==
946 22:14:17.534983 DQS Delay:
947 22:14:17.538342 DQS0 = 0, DQS1 = 0
948 22:14:17.538422 DQM Delay:
949 22:14:17.541350 DQM0 = 86, DQM1 = 74
950 22:14:17.541428 DQ Delay:
951 22:14:17.544774 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
952 22:14:17.548039 DQ4 =85, DQ5 =77, DQ6 =93, DQ7 =93
953 22:14:17.551571 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =69
954 22:14:17.554658 DQ12 =77, DQ13 =85, DQ14 =85, DQ15 =85
955 22:14:17.554738
956 22:14:17.554819
957 22:14:17.554901 ==
958 22:14:17.558204 Dram Type= 6, Freq= 0, CH_0, rank 0
959 22:14:17.561219 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
960 22:14:17.561303 ==
961 22:14:17.561385
962 22:14:17.561462
963 22:14:17.564579 TX Vref Scan disable
964 22:14:17.564656 == TX Byte 0 ==
965 22:14:17.571432 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
966 22:14:17.574752 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
967 22:14:17.578037 == TX Byte 1 ==
968 22:14:17.581072 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
969 22:14:17.584930 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
970 22:14:17.585017 ==
971 22:14:17.588373 Dram Type= 6, Freq= 0, CH_0, rank 0
972 22:14:17.591725 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
973 22:14:17.591810 ==
974 22:14:17.606284 TX Vref=22, minBit 8, minWin=27, winSum=442
975 22:14:17.609465 TX Vref=24, minBit 14, minWin=27, winSum=447
976 22:14:17.612969 TX Vref=26, minBit 5, minWin=27, winSum=447
977 22:14:17.616690 TX Vref=28, minBit 10, minWin=27, winSum=446
978 22:14:17.621008 TX Vref=30, minBit 10, minWin=27, winSum=447
979 22:14:17.624192 TX Vref=32, minBit 4, minWin=27, winSum=443
980 22:14:17.631854 [TxChooseVref] Worse bit 14, Min win 27, Win sum 447, Final Vref 24
981 22:14:17.631944
982 22:14:17.632010 Final TX Range 1 Vref 24
983 22:14:17.632072
984 22:14:17.632132 ==
985 22:14:17.635470 Dram Type= 6, Freq= 0, CH_0, rank 0
986 22:14:17.639544 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
987 22:14:17.639628 ==
988 22:14:17.639694
989 22:14:17.639755
990 22:14:17.642646 TX Vref Scan disable
991 22:14:17.646362 == TX Byte 0 ==
992 22:14:17.649805 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
993 22:14:17.652775 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
994 22:14:17.656845 == TX Byte 1 ==
995 22:14:17.659762 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
996 22:14:17.662991 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
997 22:14:17.663076
998 22:14:17.666345 [DATLAT]
999 22:14:17.666428 Freq=800, CH0 RK0
1000 22:14:17.666495
1001 22:14:17.669291 DATLAT Default: 0xa
1002 22:14:17.669373 0, 0xFFFF, sum = 0
1003 22:14:17.672948 1, 0xFFFF, sum = 0
1004 22:14:17.673032 2, 0xFFFF, sum = 0
1005 22:14:17.676318 3, 0xFFFF, sum = 0
1006 22:14:17.676402 4, 0xFFFF, sum = 0
1007 22:14:17.679664 5, 0xFFFF, sum = 0
1008 22:14:17.679748 6, 0xFFFF, sum = 0
1009 22:14:17.682854 7, 0xFFFF, sum = 0
1010 22:14:17.682943 8, 0xFFFF, sum = 0
1011 22:14:17.686221 9, 0x0, sum = 1
1012 22:14:17.686304 10, 0x0, sum = 2
1013 22:14:17.689857 11, 0x0, sum = 3
1014 22:14:17.689941 12, 0x0, sum = 4
1015 22:14:17.692707 best_step = 10
1016 22:14:17.692790
1017 22:14:17.692855 ==
1018 22:14:17.695969 Dram Type= 6, Freq= 0, CH_0, rank 0
1019 22:14:17.699660 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1020 22:14:17.699743 ==
1021 22:14:17.699808 RX Vref Scan: 1
1022 22:14:17.703182
1023 22:14:17.703266 Set Vref Range= 32 -> 127
1024 22:14:17.703333
1025 22:14:17.706676 RX Vref 32 -> 127, step: 1
1026 22:14:17.706748
1027 22:14:17.710307 RX Delay -111 -> 252, step: 8
1028 22:14:17.710385
1029 22:14:17.714783 Set Vref, RX VrefLevel [Byte0]: 32
1030 22:14:17.714883 [Byte1]: 32
1031 22:14:17.718786
1032 22:14:17.718862 Set Vref, RX VrefLevel [Byte0]: 33
1033 22:14:17.721789 [Byte1]: 33
1034 22:14:17.726229
1035 22:14:17.726335 Set Vref, RX VrefLevel [Byte0]: 34
1036 22:14:17.729375 [Byte1]: 34
1037 22:14:17.733430
1038 22:14:17.733504 Set Vref, RX VrefLevel [Byte0]: 35
1039 22:14:17.737601 [Byte1]: 35
1040 22:14:17.741120
1041 22:14:17.741195 Set Vref, RX VrefLevel [Byte0]: 36
1042 22:14:17.744895 [Byte1]: 36
1043 22:14:17.749596
1044 22:14:17.749670 Set Vref, RX VrefLevel [Byte0]: 37
1045 22:14:17.753085 [Byte1]: 37
1046 22:14:17.756595
1047 22:14:17.756669 Set Vref, RX VrefLevel [Byte0]: 38
1048 22:14:17.759898 [Byte1]: 38
1049 22:14:17.764259
1050 22:14:17.764330 Set Vref, RX VrefLevel [Byte0]: 39
1051 22:14:17.767852 [Byte1]: 39
1052 22:14:17.772137
1053 22:14:17.772234 Set Vref, RX VrefLevel [Byte0]: 40
1054 22:14:17.775523 [Byte1]: 40
1055 22:14:17.779694
1056 22:14:17.779765 Set Vref, RX VrefLevel [Byte0]: 41
1057 22:14:17.783401 [Byte1]: 41
1058 22:14:17.787307
1059 22:14:17.787376 Set Vref, RX VrefLevel [Byte0]: 42
1060 22:14:17.790935 [Byte1]: 42
1061 22:14:17.795193
1062 22:14:17.795293 Set Vref, RX VrefLevel [Byte0]: 43
1063 22:14:17.798145 [Byte1]: 43
1064 22:14:17.802291
1065 22:14:17.802374 Set Vref, RX VrefLevel [Byte0]: 44
1066 22:14:17.805691 [Byte1]: 44
1067 22:14:17.810300
1068 22:14:17.810371 Set Vref, RX VrefLevel [Byte0]: 45
1069 22:14:17.813496 [Byte1]: 45
1070 22:14:17.817634
1071 22:14:17.817706 Set Vref, RX VrefLevel [Byte0]: 46
1072 22:14:17.821306 [Byte1]: 46
1073 22:14:17.825530
1074 22:14:17.825605 Set Vref, RX VrefLevel [Byte0]: 47
1075 22:14:17.828481 [Byte1]: 47
1076 22:14:17.833558
1077 22:14:17.833638 Set Vref, RX VrefLevel [Byte0]: 48
1078 22:14:17.837131 [Byte1]: 48
1079 22:14:17.841336
1080 22:14:17.841416 Set Vref, RX VrefLevel [Byte0]: 49
1081 22:14:17.844251 [Byte1]: 49
1082 22:14:17.848402
1083 22:14:17.848509 Set Vref, RX VrefLevel [Byte0]: 50
1084 22:14:17.851890 [Byte1]: 50
1085 22:14:17.856295
1086 22:14:17.856401 Set Vref, RX VrefLevel [Byte0]: 51
1087 22:14:17.859155 [Byte1]: 51
1088 22:14:17.863489
1089 22:14:17.863570 Set Vref, RX VrefLevel [Byte0]: 52
1090 22:14:17.866898 [Byte1]: 52
1091 22:14:17.871213
1092 22:14:17.871294 Set Vref, RX VrefLevel [Byte0]: 53
1093 22:14:17.874526 [Byte1]: 53
1094 22:14:17.878791
1095 22:14:17.878885 Set Vref, RX VrefLevel [Byte0]: 54
1096 22:14:17.882149 [Byte1]: 54
1097 22:14:17.886685
1098 22:14:17.886766 Set Vref, RX VrefLevel [Byte0]: 55
1099 22:14:17.889802 [Byte1]: 55
1100 22:14:17.894256
1101 22:14:17.894337 Set Vref, RX VrefLevel [Byte0]: 56
1102 22:14:17.897640 [Byte1]: 56
1103 22:14:17.902375
1104 22:14:17.902455 Set Vref, RX VrefLevel [Byte0]: 57
1105 22:14:17.905186 [Byte1]: 57
1106 22:14:17.910037
1107 22:14:17.910117 Set Vref, RX VrefLevel [Byte0]: 58
1108 22:14:17.912704 [Byte1]: 58
1109 22:14:17.917036
1110 22:14:17.917117 Set Vref, RX VrefLevel [Byte0]: 59
1111 22:14:17.920406 [Byte1]: 59
1112 22:14:17.925178
1113 22:14:17.925259 Set Vref, RX VrefLevel [Byte0]: 60
1114 22:14:17.928144 [Byte1]: 60
1115 22:14:17.932430
1116 22:14:17.932511 Set Vref, RX VrefLevel [Byte0]: 61
1117 22:14:17.935792 [Byte1]: 61
1118 22:14:17.940300
1119 22:14:17.940380 Set Vref, RX VrefLevel [Byte0]: 62
1120 22:14:17.947018 [Byte1]: 62
1121 22:14:17.947099
1122 22:14:17.950575 Set Vref, RX VrefLevel [Byte0]: 63
1123 22:14:17.953390 [Byte1]: 63
1124 22:14:17.953471
1125 22:14:17.957265 Set Vref, RX VrefLevel [Byte0]: 64
1126 22:14:17.959891 [Byte1]: 64
1127 22:14:17.963016
1128 22:14:17.963097 Set Vref, RX VrefLevel [Byte0]: 65
1129 22:14:17.966757 [Byte1]: 65
1130 22:14:17.970781
1131 22:14:17.970860 Set Vref, RX VrefLevel [Byte0]: 66
1132 22:14:17.973974 [Byte1]: 66
1133 22:14:17.979054
1134 22:14:17.979135 Set Vref, RX VrefLevel [Byte0]: 67
1135 22:14:17.982346 [Byte1]: 67
1136 22:14:17.985750
1137 22:14:17.985830 Set Vref, RX VrefLevel [Byte0]: 68
1138 22:14:17.989475 [Byte1]: 68
1139 22:14:17.993656
1140 22:14:17.993736 Set Vref, RX VrefLevel [Byte0]: 69
1141 22:14:17.996740 [Byte1]: 69
1142 22:14:18.001441
1143 22:14:18.001521 Set Vref, RX VrefLevel [Byte0]: 70
1144 22:14:18.004705 [Byte1]: 70
1145 22:14:18.009025
1146 22:14:18.009105 Set Vref, RX VrefLevel [Byte0]: 71
1147 22:14:18.012357 [Byte1]: 71
1148 22:14:18.016658
1149 22:14:18.016737 Set Vref, RX VrefLevel [Byte0]: 72
1150 22:14:18.019900 [Byte1]: 72
1151 22:14:18.024111
1152 22:14:18.024192 Set Vref, RX VrefLevel [Byte0]: 73
1153 22:14:18.027746 [Byte1]: 73
1154 22:14:18.031914
1155 22:14:18.031994 Set Vref, RX VrefLevel [Byte0]: 74
1156 22:14:18.034902 [Byte1]: 74
1157 22:14:18.039488
1158 22:14:18.039569 Set Vref, RX VrefLevel [Byte0]: 75
1159 22:14:18.043413 [Byte1]: 75
1160 22:14:18.047332
1161 22:14:18.047413 Set Vref, RX VrefLevel [Byte0]: 76
1162 22:14:18.050427 [Byte1]: 76
1163 22:14:18.054799
1164 22:14:18.054879 Set Vref, RX VrefLevel [Byte0]: 77
1165 22:14:18.058311 [Byte1]: 77
1166 22:14:18.062905
1167 22:14:18.062985 Set Vref, RX VrefLevel [Byte0]: 78
1168 22:14:18.065962 [Byte1]: 78
1169 22:14:18.069849
1170 22:14:18.069930 Set Vref, RX VrefLevel [Byte0]: 79
1171 22:14:18.073504 [Byte1]: 79
1172 22:14:18.077975
1173 22:14:18.078055 Set Vref, RX VrefLevel [Byte0]: 80
1174 22:14:18.080721 [Byte1]: 80
1175 22:14:18.085558
1176 22:14:18.085638 Final RX Vref Byte 0 = 61 to rank0
1177 22:14:18.088843 Final RX Vref Byte 1 = 57 to rank0
1178 22:14:18.091733 Final RX Vref Byte 0 = 61 to rank1
1179 22:14:18.095611 Final RX Vref Byte 1 = 57 to rank1==
1180 22:14:18.098609 Dram Type= 6, Freq= 0, CH_0, rank 0
1181 22:14:18.105871 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1182 22:14:18.105959 ==
1183 22:14:18.106027 DQS Delay:
1184 22:14:18.106089 DQS0 = 0, DQS1 = 0
1185 22:14:18.108711 DQM Delay:
1186 22:14:18.108808 DQM0 = 87, DQM1 = 75
1187 22:14:18.112065 DQ Delay:
1188 22:14:18.115271 DQ0 =84, DQ1 =88, DQ2 =84, DQ3 =84
1189 22:14:18.118856 DQ4 =92, DQ5 =76, DQ6 =92, DQ7 =96
1190 22:14:18.118932 DQ8 =68, DQ9 =64, DQ10 =76, DQ11 =68
1191 22:14:18.125246 DQ12 =80, DQ13 =76, DQ14 =88, DQ15 =84
1192 22:14:18.125328
1193 22:14:18.125392
1194 22:14:18.131855 [DQSOSCAuto] RK0, (LSB)MR18= 0x4425, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 392 ps
1195 22:14:18.135412 CH0 RK0: MR19=606, MR18=4425
1196 22:14:18.141404 CH0_RK0: MR19=0x606, MR18=0x4425, DQSOSC=392, MR23=63, INC=96, DEC=64
1197 22:14:18.141486
1198 22:14:18.144988 ----->DramcWriteLeveling(PI) begin...
1199 22:14:18.145070 ==
1200 22:14:18.148426 Dram Type= 6, Freq= 0, CH_0, rank 1
1201 22:14:18.151662 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1202 22:14:18.151743 ==
1203 22:14:18.155330 Write leveling (Byte 0): 31 => 31
1204 22:14:18.158953 Write leveling (Byte 1): 30 => 30
1205 22:14:18.162342 DramcWriteLeveling(PI) end<-----
1206 22:14:18.162423
1207 22:14:18.162486 ==
1208 22:14:18.166763 Dram Type= 6, Freq= 0, CH_0, rank 1
1209 22:14:18.168968 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1210 22:14:18.169049 ==
1211 22:14:18.172802 [Gating] SW mode calibration
1212 22:14:18.179547 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1213 22:14:18.223491 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1214 22:14:18.223899 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1215 22:14:18.224523 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1216 22:14:18.224626 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1217 22:14:18.224863 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1218 22:14:18.225353 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1219 22:14:18.226171 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1220 22:14:18.226414 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1221 22:14:18.226477 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1222 22:14:18.227024 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1223 22:14:18.268122 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1224 22:14:18.268389 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 22:14:18.269431 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 22:14:18.269512 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 22:14:18.269755 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 22:14:18.270220 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 22:14:18.270922 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 22:14:18.271229 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 22:14:18.271310 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1232 22:14:18.271942 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1233 22:14:18.311634 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1234 22:14:18.311899 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1235 22:14:18.312162 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1236 22:14:18.312243 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1237 22:14:18.312525 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1238 22:14:18.312785 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1239 22:14:18.313028 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1240 22:14:18.313591 0 9 8 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
1241 22:14:18.313672 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1242 22:14:18.314160 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1243 22:14:18.343809 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1244 22:14:18.344078 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1245 22:14:18.344645 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1246 22:14:18.344726 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1247 22:14:18.345436 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1248 22:14:18.346429 0 10 8 | B1->B0 | 3131 2525 | 0 0 | (0 0) (0 0)
1249 22:14:18.346885 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1250 22:14:18.348856 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1251 22:14:18.352462 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1252 22:14:18.356060 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1253 22:14:18.359449 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1254 22:14:18.363342 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1255 22:14:18.370814 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1256 22:14:18.373897 0 11 8 | B1->B0 | 2e2e 3b3b | 0 0 | (0 0) (0 0)
1257 22:14:18.377905 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1258 22:14:18.381109 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1259 22:14:18.388748 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1260 22:14:18.392448 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1261 22:14:18.395528 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1262 22:14:18.399455 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1263 22:14:18.402954 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1264 22:14:18.406983 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1265 22:14:18.414126 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1266 22:14:18.417539 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1267 22:14:18.421252 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1268 22:14:18.424865 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1269 22:14:18.428503 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1270 22:14:18.436158 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1271 22:14:18.439541 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1272 22:14:18.443459 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1273 22:14:18.446902 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1274 22:14:18.453562 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1275 22:14:18.457788 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1276 22:14:18.461233 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1277 22:14:18.464974 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1278 22:14:18.468885 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1279 22:14:18.475971 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1280 22:14:18.479550 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1281 22:14:18.483160 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1282 22:14:18.486750 Total UI for P1: 0, mck2ui 16
1283 22:14:18.490503 best dqsien dly found for B0: ( 0, 14, 6)
1284 22:14:18.494297 Total UI for P1: 0, mck2ui 16
1285 22:14:18.498003 best dqsien dly found for B1: ( 0, 14, 10)
1286 22:14:18.501675 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1287 22:14:18.505267 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
1288 22:14:18.505336
1289 22:14:18.508954 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1290 22:14:18.512615 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
1291 22:14:18.512695 [Gating] SW calibration Done
1292 22:14:18.512759 ==
1293 22:14:18.516036 Dram Type= 6, Freq= 0, CH_0, rank 1
1294 22:14:18.519675 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1295 22:14:18.523067 ==
1296 22:14:18.523168 RX Vref Scan: 0
1297 22:14:18.523266
1298 22:14:18.526649 RX Vref 0 -> 0, step: 1
1299 22:14:18.526745
1300 22:14:18.526833 RX Delay -130 -> 252, step: 16
1301 22:14:18.534219 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1302 22:14:18.537993 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1303 22:14:18.541522 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
1304 22:14:18.545462 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1305 22:14:18.548867 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1306 22:14:18.552799 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1307 22:14:18.556406 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1308 22:14:18.559874 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1309 22:14:18.563391 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1310 22:14:18.567365 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1311 22:14:18.570938 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1312 22:14:18.578291 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1313 22:14:18.581637 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1314 22:14:18.585460 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1315 22:14:18.588724 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1316 22:14:18.592634 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1317 22:14:18.592726 ==
1318 22:14:18.595857 Dram Type= 6, Freq= 0, CH_0, rank 1
1319 22:14:18.599504 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1320 22:14:18.599630 ==
1321 22:14:18.603174 DQS Delay:
1322 22:14:18.603278 DQS0 = 0, DQS1 = 0
1323 22:14:18.603367 DQM Delay:
1324 22:14:18.607287 DQM0 = 83, DQM1 = 74
1325 22:14:18.607357 DQ Delay:
1326 22:14:18.611100 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =77
1327 22:14:18.614683 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
1328 22:14:18.618075 DQ8 =69, DQ9 =61, DQ10 =77, DQ11 =69
1329 22:14:18.621494 DQ12 =77, DQ13 =77, DQ14 =85, DQ15 =77
1330 22:14:18.621575
1331 22:14:18.621638
1332 22:14:18.621695 ==
1333 22:14:18.625277 Dram Type= 6, Freq= 0, CH_0, rank 1
1334 22:14:18.628794 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1335 22:14:18.628893 ==
1336 22:14:18.628988
1337 22:14:18.629074
1338 22:14:18.629157 TX Vref Scan disable
1339 22:14:18.633088 == TX Byte 0 ==
1340 22:14:18.635970 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1341 22:14:18.639602 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1342 22:14:18.643499 == TX Byte 1 ==
1343 22:14:18.646908 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1344 22:14:18.650113 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1345 22:14:18.650195 ==
1346 22:14:18.653440 Dram Type= 6, Freq= 0, CH_0, rank 1
1347 22:14:18.660321 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1348 22:14:18.660403 ==
1349 22:14:18.671497 TX Vref=22, minBit 8, minWin=27, winSum=446
1350 22:14:18.675073 TX Vref=24, minBit 9, minWin=27, winSum=447
1351 22:14:18.678680 TX Vref=26, minBit 9, minWin=27, winSum=449
1352 22:14:18.681540 TX Vref=28, minBit 9, minWin=27, winSum=449
1353 22:14:18.685142 TX Vref=30, minBit 8, minWin=27, winSum=446
1354 22:14:18.688159 TX Vref=32, minBit 8, minWin=27, winSum=443
1355 22:14:18.695067 [TxChooseVref] Worse bit 9, Min win 27, Win sum 449, Final Vref 26
1356 22:14:18.695144
1357 22:14:18.699007 Final TX Range 1 Vref 26
1358 22:14:18.699082
1359 22:14:18.699145 ==
1360 22:14:18.702357 Dram Type= 6, Freq= 0, CH_0, rank 1
1361 22:14:18.705010 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1362 22:14:18.705084 ==
1363 22:14:18.705143
1364 22:14:18.708078
1365 22:14:18.708149 TX Vref Scan disable
1366 22:14:18.711777 == TX Byte 0 ==
1367 22:14:18.714932 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1368 22:14:18.721903 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1369 22:14:18.721978 == TX Byte 1 ==
1370 22:14:18.725048 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1371 22:14:18.731339 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1372 22:14:18.731434
1373 22:14:18.731497 [DATLAT]
1374 22:14:18.731559 Freq=800, CH0 RK1
1375 22:14:18.731617
1376 22:14:18.734633 DATLAT Default: 0xa
1377 22:14:18.734701 0, 0xFFFF, sum = 0
1378 22:14:18.738198 1, 0xFFFF, sum = 0
1379 22:14:18.741591 2, 0xFFFF, sum = 0
1380 22:14:18.741671 3, 0xFFFF, sum = 0
1381 22:14:18.744430 4, 0xFFFF, sum = 0
1382 22:14:18.744508 5, 0xFFFF, sum = 0
1383 22:14:18.748339 6, 0xFFFF, sum = 0
1384 22:14:18.748414 7, 0xFFFF, sum = 0
1385 22:14:18.751547 8, 0xFFFF, sum = 0
1386 22:14:18.751626 9, 0x0, sum = 1
1387 22:14:18.754608 10, 0x0, sum = 2
1388 22:14:18.754680 11, 0x0, sum = 3
1389 22:14:18.754747 12, 0x0, sum = 4
1390 22:14:18.757964 best_step = 10
1391 22:14:18.758038
1392 22:14:18.758099 ==
1393 22:14:18.761128 Dram Type= 6, Freq= 0, CH_0, rank 1
1394 22:14:18.764353 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1395 22:14:18.764428 ==
1396 22:14:18.768364 RX Vref Scan: 0
1397 22:14:18.768431
1398 22:14:18.768489 RX Vref 0 -> 0, step: 1
1399 22:14:18.771071
1400 22:14:18.771139 RX Delay -111 -> 252, step: 8
1401 22:14:18.778646 iDelay=209, Bit 0, Center 80 (-31 ~ 192) 224
1402 22:14:18.781957 iDelay=209, Bit 1, Center 92 (-23 ~ 208) 232
1403 22:14:18.785047 iDelay=209, Bit 2, Center 80 (-31 ~ 192) 224
1404 22:14:18.788665 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
1405 22:14:18.791738 iDelay=209, Bit 4, Center 84 (-31 ~ 200) 232
1406 22:14:18.798315 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1407 22:14:18.802127 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
1408 22:14:18.805301 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1409 22:14:18.808291 iDelay=209, Bit 8, Center 68 (-47 ~ 184) 232
1410 22:14:18.811528 iDelay=209, Bit 9, Center 60 (-55 ~ 176) 232
1411 22:14:18.818439 iDelay=209, Bit 10, Center 76 (-39 ~ 192) 232
1412 22:14:18.821363 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
1413 22:14:18.824976 iDelay=209, Bit 12, Center 84 (-31 ~ 200) 232
1414 22:14:18.828078 iDelay=209, Bit 13, Center 84 (-31 ~ 200) 232
1415 22:14:18.835257 iDelay=209, Bit 14, Center 84 (-31 ~ 200) 232
1416 22:14:18.837943 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
1417 22:14:18.838022 ==
1418 22:14:18.841594 Dram Type= 6, Freq= 0, CH_0, rank 1
1419 22:14:18.844941 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1420 22:14:18.845023 ==
1421 22:14:18.845088 DQS Delay:
1422 22:14:18.848047 DQS0 = 0, DQS1 = 0
1423 22:14:18.848122 DQM Delay:
1424 22:14:18.851804 DQM0 = 85, DQM1 = 76
1425 22:14:18.851880 DQ Delay:
1426 22:14:18.854701 DQ0 =80, DQ1 =92, DQ2 =80, DQ3 =84
1427 22:14:18.857823 DQ4 =84, DQ5 =76, DQ6 =92, DQ7 =96
1428 22:14:18.861219 DQ8 =68, DQ9 =60, DQ10 =76, DQ11 =68
1429 22:14:18.864909 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =84
1430 22:14:18.865007
1431 22:14:18.865098
1432 22:14:18.874509 [DQSOSCAuto] RK1, (LSB)MR18= 0x4007, (MSB)MR19= 0x606, tDQSOscB0 = 408 ps tDQSOscB1 = 393 ps
1433 22:14:18.874591 CH0 RK1: MR19=606, MR18=4007
1434 22:14:18.881087 CH0_RK1: MR19=0x606, MR18=0x4007, DQSOSC=393, MR23=63, INC=95, DEC=63
1435 22:14:18.884741 [RxdqsGatingPostProcess] freq 800
1436 22:14:18.891444 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1437 22:14:18.894792 Pre-setting of DQS Precalculation
1438 22:14:18.897922 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1439 22:14:18.898007 ==
1440 22:14:18.901326 Dram Type= 6, Freq= 0, CH_1, rank 0
1441 22:14:18.905105 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1442 22:14:18.908162 ==
1443 22:14:18.911287 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1444 22:14:18.918051 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1445 22:14:18.926744 [CA 0] Center 36 (6~67) winsize 62
1446 22:14:18.930209 [CA 1] Center 36 (6~67) winsize 62
1447 22:14:18.933763 [CA 2] Center 34 (4~65) winsize 62
1448 22:14:18.937016 [CA 3] Center 34 (3~65) winsize 63
1449 22:14:18.940177 [CA 4] Center 34 (4~65) winsize 62
1450 22:14:18.943530 [CA 5] Center 34 (3~65) winsize 63
1451 22:14:18.943605
1452 22:14:18.946849 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1453 22:14:18.946924
1454 22:14:18.950166 [CATrainingPosCal] consider 1 rank data
1455 22:14:18.953515 u2DelayCellTimex100 = 270/100 ps
1456 22:14:18.956873 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1457 22:14:18.960154 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1458 22:14:18.967164 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1459 22:14:18.970017 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
1460 22:14:18.973149 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1461 22:14:18.976644 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1462 22:14:18.976720
1463 22:14:18.979743 CA PerBit enable=1, Macro0, CA PI delay=34
1464 22:14:18.979819
1465 22:14:18.983234 [CBTSetCACLKResult] CA Dly = 34
1466 22:14:18.983308 CS Dly: 5 (0~36)
1467 22:14:18.986290 ==
1468 22:14:18.989337 Dram Type= 6, Freq= 0, CH_1, rank 1
1469 22:14:18.993229 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1470 22:14:18.993305 ==
1471 22:14:18.995962 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1472 22:14:19.002894 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1473 22:14:19.012891 [CA 0] Center 36 (6~67) winsize 62
1474 22:14:19.016598 [CA 1] Center 36 (6~67) winsize 62
1475 22:14:19.019717 [CA 2] Center 34 (4~65) winsize 62
1476 22:14:19.022880 [CA 3] Center 34 (3~65) winsize 63
1477 22:14:19.026134 [CA 4] Center 34 (4~65) winsize 62
1478 22:14:19.029583 [CA 5] Center 34 (3~65) winsize 63
1479 22:14:19.029660
1480 22:14:19.032658 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1481 22:14:19.032748
1482 22:14:19.036098 [CATrainingPosCal] consider 2 rank data
1483 22:14:19.040071 u2DelayCellTimex100 = 270/100 ps
1484 22:14:19.042539 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1485 22:14:19.046035 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1486 22:14:19.052581 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1487 22:14:19.056312 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
1488 22:14:19.059366 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1489 22:14:19.063020 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1490 22:14:19.063095
1491 22:14:19.065870 CA PerBit enable=1, Macro0, CA PI delay=34
1492 22:14:19.065947
1493 22:14:19.069333 [CBTSetCACLKResult] CA Dly = 34
1494 22:14:19.069407 CS Dly: 6 (0~38)
1495 22:14:19.069468
1496 22:14:19.072811 ----->DramcWriteLeveling(PI) begin...
1497 22:14:19.075865 ==
1498 22:14:19.079309 Dram Type= 6, Freq= 0, CH_1, rank 0
1499 22:14:19.082757 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1500 22:14:19.082832 ==
1501 22:14:19.086277 Write leveling (Byte 0): 25 => 25
1502 22:14:19.089351 Write leveling (Byte 1): 29 => 29
1503 22:14:19.092415 DramcWriteLeveling(PI) end<-----
1504 22:14:19.092506
1505 22:14:19.092609 ==
1506 22:14:19.096028 Dram Type= 6, Freq= 0, CH_1, rank 0
1507 22:14:19.099252 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1508 22:14:19.099331 ==
1509 22:14:19.102617 [Gating] SW mode calibration
1510 22:14:19.109077 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1511 22:14:19.116086 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1512 22:14:19.118842 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1513 22:14:19.122405 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1514 22:14:19.125885 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1515 22:14:19.132242 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1516 22:14:19.135826 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1517 22:14:19.138946 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1518 22:14:19.145558 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1519 22:14:19.148930 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1520 22:14:19.152089 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1521 22:14:19.158893 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1522 22:14:19.162104 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 22:14:19.165785 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 22:14:19.172153 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 22:14:19.175946 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 22:14:19.178611 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 22:14:19.185389 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 22:14:19.188303 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1529 22:14:19.191873 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1530 22:14:19.198454 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1531 22:14:19.201680 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1532 22:14:19.205057 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 22:14:19.211955 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1534 22:14:19.214917 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1535 22:14:19.218699 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1536 22:14:19.225476 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1537 22:14:19.228459 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1538 22:14:19.232271 0 9 8 | B1->B0 | 2e2e 2f2f | 0 0 | (0 0) (1 1)
1539 22:14:19.238602 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1540 22:14:19.242211 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1541 22:14:19.245270 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1542 22:14:19.251924 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1543 22:14:19.255428 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1544 22:14:19.258448 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1545 22:14:19.265672 0 10 4 | B1->B0 | 3434 3333 | 1 1 | (1 0) (1 0)
1546 22:14:19.268733 0 10 8 | B1->B0 | 2c2c 2424 | 0 0 | (0 0) (0 0)
1547 22:14:19.272012 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1548 22:14:19.278652 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1549 22:14:19.281833 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1550 22:14:19.285604 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1551 22:14:19.291417 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1552 22:14:19.294710 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1553 22:14:19.298309 0 11 4 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
1554 22:14:19.304694 0 11 8 | B1->B0 | 3838 4141 | 0 1 | (0 0) (0 0)
1555 22:14:19.308327 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1556 22:14:19.311134 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1557 22:14:19.314846 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1558 22:14:19.321427 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1559 22:14:19.324740 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1560 22:14:19.328002 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1561 22:14:19.334594 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
1562 22:14:19.338002 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1563 22:14:19.341052 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1564 22:14:19.347812 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1565 22:14:19.351107 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1566 22:14:19.354495 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1567 22:14:19.361438 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1568 22:14:19.364486 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1569 22:14:19.367728 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1570 22:14:19.374275 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1571 22:14:19.377624 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1572 22:14:19.381344 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1573 22:14:19.387863 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1574 22:14:19.391351 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1575 22:14:19.394647 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1576 22:14:19.401325 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1577 22:14:19.404217 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1578 22:14:19.407734 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1579 22:14:19.410838 Total UI for P1: 0, mck2ui 16
1580 22:14:19.414353 best dqsien dly found for B0: ( 0, 14, 4)
1581 22:14:19.417492 Total UI for P1: 0, mck2ui 16
1582 22:14:19.420907 best dqsien dly found for B1: ( 0, 14, 6)
1583 22:14:19.424248 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1584 22:14:19.427599 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1585 22:14:19.427680
1586 22:14:19.430613 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1587 22:14:19.437654 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1588 22:14:19.437737 [Gating] SW calibration Done
1589 22:14:19.437802 ==
1590 22:14:19.440848 Dram Type= 6, Freq= 0, CH_1, rank 0
1591 22:14:19.447237 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1592 22:14:19.447317 ==
1593 22:14:19.447381 RX Vref Scan: 0
1594 22:14:19.447439
1595 22:14:19.450675 RX Vref 0 -> 0, step: 1
1596 22:14:19.450756
1597 22:14:19.453914 RX Delay -130 -> 252, step: 16
1598 22:14:19.457968 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1599 22:14:19.460678 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1600 22:14:19.464015 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1601 22:14:19.470843 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1602 22:14:19.473993 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1603 22:14:19.477137 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1604 22:14:19.481038 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1605 22:14:19.487030 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1606 22:14:19.490144 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1607 22:14:19.494142 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1608 22:14:19.496895 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1609 22:14:19.500812 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1610 22:14:19.506805 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1611 22:14:19.510368 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1612 22:14:19.513462 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1613 22:14:19.517196 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1614 22:14:19.517278 ==
1615 22:14:19.520458 Dram Type= 6, Freq= 0, CH_1, rank 0
1616 22:14:19.526683 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1617 22:14:19.526766 ==
1618 22:14:19.526831 DQS Delay:
1619 22:14:19.529902 DQS0 = 0, DQS1 = 0
1620 22:14:19.529983 DQM Delay:
1621 22:14:19.530047 DQM0 = 89, DQM1 = 80
1622 22:14:19.533505 DQ Delay:
1623 22:14:19.536750 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =85
1624 22:14:19.540169 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1625 22:14:19.543185 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1626 22:14:19.546702 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =93
1627 22:14:19.546784
1628 22:14:19.546848
1629 22:14:19.546906 ==
1630 22:14:19.549894 Dram Type= 6, Freq= 0, CH_1, rank 0
1631 22:14:19.553559 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1632 22:14:19.553641 ==
1633 22:14:19.553705
1634 22:14:19.553763
1635 22:14:19.556629 TX Vref Scan disable
1636 22:14:19.559689 == TX Byte 0 ==
1637 22:14:19.563202 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1638 22:14:19.566544 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1639 22:14:19.569745 == TX Byte 1 ==
1640 22:14:19.573655 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1641 22:14:19.576233 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1642 22:14:19.576314 ==
1643 22:14:19.580018 Dram Type= 6, Freq= 0, CH_1, rank 0
1644 22:14:19.583162 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1645 22:14:19.583244 ==
1646 22:14:19.597432 TX Vref=22, minBit 10, minWin=26, winSum=441
1647 22:14:19.601406 TX Vref=24, minBit 8, minWin=26, winSum=440
1648 22:14:19.604351 TX Vref=26, minBit 9, minWin=27, winSum=445
1649 22:14:19.608160 TX Vref=28, minBit 0, minWin=27, winSum=447
1650 22:14:19.610967 TX Vref=30, minBit 13, minWin=27, winSum=447
1651 22:14:19.617660 TX Vref=32, minBit 0, minWin=27, winSum=443
1652 22:14:19.621093 [TxChooseVref] Worse bit 0, Min win 27, Win sum 447, Final Vref 28
1653 22:14:19.621176
1654 22:14:19.624238 Final TX Range 1 Vref 28
1655 22:14:19.624319
1656 22:14:19.624383 ==
1657 22:14:19.627202 Dram Type= 6, Freq= 0, CH_1, rank 0
1658 22:14:19.630499 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1659 22:14:19.634134 ==
1660 22:14:19.634232
1661 22:14:19.634321
1662 22:14:19.634411 TX Vref Scan disable
1663 22:14:19.637902 == TX Byte 0 ==
1664 22:14:19.640966 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1665 22:14:19.647632 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1666 22:14:19.647707 == TX Byte 1 ==
1667 22:14:19.650988 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1668 22:14:19.657499 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1669 22:14:19.657574
1670 22:14:19.657636 [DATLAT]
1671 22:14:19.657697 Freq=800, CH1 RK0
1672 22:14:19.657754
1673 22:14:19.660902 DATLAT Default: 0xa
1674 22:14:19.660995 0, 0xFFFF, sum = 0
1675 22:14:19.665056 1, 0xFFFF, sum = 0
1676 22:14:19.667676 2, 0xFFFF, sum = 0
1677 22:14:19.667750 3, 0xFFFF, sum = 0
1678 22:14:19.670624 4, 0xFFFF, sum = 0
1679 22:14:19.670721 5, 0xFFFF, sum = 0
1680 22:14:19.674274 6, 0xFFFF, sum = 0
1681 22:14:19.674345 7, 0xFFFF, sum = 0
1682 22:14:19.677276 8, 0xFFFF, sum = 0
1683 22:14:19.677345 9, 0x0, sum = 1
1684 22:14:19.680799 10, 0x0, sum = 2
1685 22:14:19.680873 11, 0x0, sum = 3
1686 22:14:19.680935 12, 0x0, sum = 4
1687 22:14:19.684237 best_step = 10
1688 22:14:19.684304
1689 22:14:19.684366 ==
1690 22:14:19.687368 Dram Type= 6, Freq= 0, CH_1, rank 0
1691 22:14:19.690632 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1692 22:14:19.690702 ==
1693 22:14:19.694339 RX Vref Scan: 1
1694 22:14:19.694409
1695 22:14:19.697599 Set Vref Range= 32 -> 127
1696 22:14:19.697667
1697 22:14:19.697725 RX Vref 32 -> 127, step: 1
1698 22:14:19.697783
1699 22:14:19.700831 RX Delay -95 -> 252, step: 8
1700 22:14:19.700897
1701 22:14:19.704040 Set Vref, RX VrefLevel [Byte0]: 32
1702 22:14:19.707851 [Byte1]: 32
1703 22:14:19.707947
1704 22:14:19.710817 Set Vref, RX VrefLevel [Byte0]: 33
1705 22:14:19.714140 [Byte1]: 33
1706 22:14:19.717816
1707 22:14:19.717901 Set Vref, RX VrefLevel [Byte0]: 34
1708 22:14:19.721128 [Byte1]: 34
1709 22:14:19.725649
1710 22:14:19.725723 Set Vref, RX VrefLevel [Byte0]: 35
1711 22:14:19.728675 [Byte1]: 35
1712 22:14:19.733124
1713 22:14:19.733200 Set Vref, RX VrefLevel [Byte0]: 36
1714 22:14:19.736271 [Byte1]: 36
1715 22:14:19.741051
1716 22:14:19.741120 Set Vref, RX VrefLevel [Byte0]: 37
1717 22:14:19.744114 [Byte1]: 37
1718 22:14:19.748351
1719 22:14:19.748448 Set Vref, RX VrefLevel [Byte0]: 38
1720 22:14:19.751436 [Byte1]: 38
1721 22:14:19.755764
1722 22:14:19.755861 Set Vref, RX VrefLevel [Byte0]: 39
1723 22:14:19.759036 [Byte1]: 39
1724 22:14:19.763596
1725 22:14:19.763692 Set Vref, RX VrefLevel [Byte0]: 40
1726 22:14:19.766751 [Byte1]: 40
1727 22:14:19.771311
1728 22:14:19.771381 Set Vref, RX VrefLevel [Byte0]: 41
1729 22:14:19.774502 [Byte1]: 41
1730 22:14:19.778944
1731 22:14:19.779040 Set Vref, RX VrefLevel [Byte0]: 42
1732 22:14:19.781861 [Byte1]: 42
1733 22:14:19.786265
1734 22:14:19.786337 Set Vref, RX VrefLevel [Byte0]: 43
1735 22:14:19.789528 [Byte1]: 43
1736 22:14:19.793755
1737 22:14:19.793827 Set Vref, RX VrefLevel [Byte0]: 44
1738 22:14:19.797338 [Byte1]: 44
1739 22:14:19.801292
1740 22:14:19.801364 Set Vref, RX VrefLevel [Byte0]: 45
1741 22:14:19.807747 [Byte1]: 45
1742 22:14:19.807843
1743 22:14:19.811301 Set Vref, RX VrefLevel [Byte0]: 46
1744 22:14:19.814724 [Byte1]: 46
1745 22:14:19.814821
1746 22:14:19.818091 Set Vref, RX VrefLevel [Byte0]: 47
1747 22:14:19.821304 [Byte1]: 47
1748 22:14:19.821400
1749 22:14:19.824720 Set Vref, RX VrefLevel [Byte0]: 48
1750 22:14:19.827729 [Byte1]: 48
1751 22:14:19.832010
1752 22:14:19.832108 Set Vref, RX VrefLevel [Byte0]: 49
1753 22:14:19.835343 [Byte1]: 49
1754 22:14:19.839676
1755 22:14:19.839744 Set Vref, RX VrefLevel [Byte0]: 50
1756 22:14:19.842711 [Byte1]: 50
1757 22:14:19.846866
1758 22:14:19.846964 Set Vref, RX VrefLevel [Byte0]: 51
1759 22:14:19.850814 [Byte1]: 51
1760 22:14:19.855174
1761 22:14:19.855270 Set Vref, RX VrefLevel [Byte0]: 52
1762 22:14:19.857779 [Byte1]: 52
1763 22:14:19.862176
1764 22:14:19.862308 Set Vref, RX VrefLevel [Byte0]: 53
1765 22:14:19.865552 [Byte1]: 53
1766 22:14:19.869979
1767 22:14:19.870082 Set Vref, RX VrefLevel [Byte0]: 54
1768 22:14:19.873294 [Byte1]: 54
1769 22:14:19.877483
1770 22:14:19.877555 Set Vref, RX VrefLevel [Byte0]: 55
1771 22:14:19.881008 [Byte1]: 55
1772 22:14:19.885147
1773 22:14:19.885232 Set Vref, RX VrefLevel [Byte0]: 56
1774 22:14:19.888412 [Byte1]: 56
1775 22:14:19.892746
1776 22:14:19.892820 Set Vref, RX VrefLevel [Byte0]: 57
1777 22:14:19.896421 [Byte1]: 57
1778 22:14:19.900315
1779 22:14:19.900414 Set Vref, RX VrefLevel [Byte0]: 58
1780 22:14:19.903636 [Byte1]: 58
1781 22:14:19.908394
1782 22:14:19.908490 Set Vref, RX VrefLevel [Byte0]: 59
1783 22:14:19.911554 [Byte1]: 59
1784 22:14:19.915260
1785 22:14:19.915357 Set Vref, RX VrefLevel [Byte0]: 60
1786 22:14:19.919480 [Byte1]: 60
1787 22:14:19.923132
1788 22:14:19.923228 Set Vref, RX VrefLevel [Byte0]: 61
1789 22:14:19.926643 [Byte1]: 61
1790 22:14:19.931003
1791 22:14:19.931105 Set Vref, RX VrefLevel [Byte0]: 62
1792 22:14:19.934103 [Byte1]: 62
1793 22:14:19.938345
1794 22:14:19.938443 Set Vref, RX VrefLevel [Byte0]: 63
1795 22:14:19.941709 [Byte1]: 63
1796 22:14:19.946064
1797 22:14:19.946163 Set Vref, RX VrefLevel [Byte0]: 64
1798 22:14:19.949352 [Byte1]: 64
1799 22:14:19.953347
1800 22:14:19.953444 Set Vref, RX VrefLevel [Byte0]: 65
1801 22:14:19.957029 [Byte1]: 65
1802 22:14:19.961324
1803 22:14:19.961399 Set Vref, RX VrefLevel [Byte0]: 66
1804 22:14:19.964899 [Byte1]: 66
1805 22:14:19.968468
1806 22:14:19.968560 Set Vref, RX VrefLevel [Byte0]: 67
1807 22:14:19.972483 [Byte1]: 67
1808 22:14:19.976524
1809 22:14:19.976636 Set Vref, RX VrefLevel [Byte0]: 68
1810 22:14:19.979442 [Byte1]: 68
1811 22:14:19.983976
1812 22:14:19.984074 Set Vref, RX VrefLevel [Byte0]: 69
1813 22:14:19.987061 [Byte1]: 69
1814 22:14:19.991355
1815 22:14:19.991425 Set Vref, RX VrefLevel [Byte0]: 70
1816 22:14:19.995034 [Byte1]: 70
1817 22:14:19.999372
1818 22:14:19.999468 Set Vref, RX VrefLevel [Byte0]: 71
1819 22:14:20.002411 [Byte1]: 71
1820 22:14:20.006548
1821 22:14:20.006643 Set Vref, RX VrefLevel [Byte0]: 72
1822 22:14:20.009668 [Byte1]: 72
1823 22:14:20.014012
1824 22:14:20.014112 Set Vref, RX VrefLevel [Byte0]: 73
1825 22:14:20.018099 [Byte1]: 73
1826 22:14:20.021725
1827 22:14:20.021820 Set Vref, RX VrefLevel [Byte0]: 74
1828 22:14:20.025017 [Byte1]: 74
1829 22:14:20.029595
1830 22:14:20.029697 Set Vref, RX VrefLevel [Byte0]: 75
1831 22:14:20.032921 [Byte1]: 75
1832 22:14:20.037015
1833 22:14:20.037111 Final RX Vref Byte 0 = 55 to rank0
1834 22:14:20.040586 Final RX Vref Byte 1 = 63 to rank0
1835 22:14:20.043457 Final RX Vref Byte 0 = 55 to rank1
1836 22:14:20.046834 Final RX Vref Byte 1 = 63 to rank1==
1837 22:14:20.050387 Dram Type= 6, Freq= 0, CH_1, rank 0
1838 22:14:20.057133 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1839 22:14:20.057213 ==
1840 22:14:20.057277 DQS Delay:
1841 22:14:20.057335 DQS0 = 0, DQS1 = 0
1842 22:14:20.060311 DQM Delay:
1843 22:14:20.060408 DQM0 = 86, DQM1 = 79
1844 22:14:20.063401 DQ Delay:
1845 22:14:20.066885 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
1846 22:14:20.070409 DQ4 =84, DQ5 =96, DQ6 =100, DQ7 =80
1847 22:14:20.073583 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =72
1848 22:14:20.077040 DQ12 =88, DQ13 =84, DQ14 =88, DQ15 =88
1849 22:14:20.077112
1850 22:14:20.077175
1851 22:14:20.083523 [DQSOSCAuto] RK0, (LSB)MR18= 0x2d1a, (MSB)MR19= 0x606, tDQSOscB0 = 403 ps tDQSOscB1 = 398 ps
1852 22:14:20.086411 CH1 RK0: MR19=606, MR18=2D1A
1853 22:14:20.093501 CH1_RK0: MR19=0x606, MR18=0x2D1A, DQSOSC=398, MR23=63, INC=93, DEC=62
1854 22:14:20.093589
1855 22:14:20.096595 ----->DramcWriteLeveling(PI) begin...
1856 22:14:20.096667 ==
1857 22:14:20.099988 Dram Type= 6, Freq= 0, CH_1, rank 1
1858 22:14:20.103356 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1859 22:14:20.103454 ==
1860 22:14:20.106634 Write leveling (Byte 0): 28 => 28
1861 22:14:20.109863 Write leveling (Byte 1): 29 => 29
1862 22:14:20.113494 DramcWriteLeveling(PI) end<-----
1863 22:14:20.113595
1864 22:14:20.113683 ==
1865 22:14:20.116276 Dram Type= 6, Freq= 0, CH_1, rank 1
1866 22:14:20.120395 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1867 22:14:20.120491 ==
1868 22:14:20.123158 [Gating] SW mode calibration
1869 22:14:20.130113 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1870 22:14:20.136511 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1871 22:14:20.139511 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1872 22:14:20.146469 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1873 22:14:20.149489 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1874 22:14:20.152678 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1875 22:14:20.159626 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1876 22:14:20.162898 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1877 22:14:20.166065 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1878 22:14:20.172975 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1879 22:14:20.176046 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1880 22:14:20.179426 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1881 22:14:20.182834 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 22:14:20.189732 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 22:14:20.192737 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1884 22:14:20.196311 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1885 22:14:20.202488 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1886 22:14:20.206135 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1887 22:14:20.209150 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1888 22:14:20.215720 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 1)
1889 22:14:20.219099 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1890 22:14:20.223391 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1891 22:14:20.229251 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1892 22:14:20.232715 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1893 22:14:20.236053 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1894 22:14:20.242466 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1895 22:14:20.245957 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1896 22:14:20.249244 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1897 22:14:20.255999 0 9 8 | B1->B0 | 302f 2727 | 1 0 | (1 1) (0 0)
1898 22:14:20.259467 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1899 22:14:20.262560 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1900 22:14:20.269594 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1901 22:14:20.272639 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1902 22:14:20.276322 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1903 22:14:20.282221 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1904 22:14:20.285607 0 10 4 | B1->B0 | 3434 3434 | 0 1 | (0 1) (1 1)
1905 22:14:20.288992 0 10 8 | B1->B0 | 2828 2f2f | 0 1 | (0 0) (1 1)
1906 22:14:20.295975 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1907 22:14:20.299003 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1908 22:14:20.302520 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1909 22:14:20.306670 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1910 22:14:20.312248 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1911 22:14:20.315904 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1912 22:14:20.319442 0 11 4 | B1->B0 | 2f2e 2323 | 1 0 | (0 0) (0 0)
1913 22:14:20.326045 0 11 8 | B1->B0 | 4242 3a3a | 0 0 | (0 0) (0 0)
1914 22:14:20.329268 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1915 22:14:20.332424 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1916 22:14:20.339385 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1917 22:14:20.342405 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1918 22:14:20.345757 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1919 22:14:20.352636 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1920 22:14:20.355546 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1921 22:14:20.359105 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1922 22:14:20.365420 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1923 22:14:20.368649 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1924 22:14:20.371966 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1925 22:14:20.378665 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1926 22:14:20.381728 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1927 22:14:20.385514 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1928 22:14:20.391849 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1929 22:14:20.395040 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1930 22:14:20.398749 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1931 22:14:20.405010 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1932 22:14:20.408358 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1933 22:14:20.411713 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1934 22:14:20.418843 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1935 22:14:20.421630 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1936 22:14:20.425146 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1937 22:14:20.431607 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1938 22:14:20.431692 Total UI for P1: 0, mck2ui 16
1939 22:14:20.438459 best dqsien dly found for B1: ( 0, 14, 6)
1940 22:14:20.441794 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1941 22:14:20.444916 Total UI for P1: 0, mck2ui 16
1942 22:14:20.448129 best dqsien dly found for B0: ( 0, 14, 6)
1943 22:14:20.451644 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1944 22:14:20.454788 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1945 22:14:20.454860
1946 22:14:20.458910 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1947 22:14:20.461609 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1948 22:14:20.465030 [Gating] SW calibration Done
1949 22:14:20.465111 ==
1950 22:14:20.468230 Dram Type= 6, Freq= 0, CH_1, rank 1
1951 22:14:20.471119 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1952 22:14:20.474388 ==
1953 22:14:20.474473 RX Vref Scan: 0
1954 22:14:20.474537
1955 22:14:20.477695 RX Vref 0 -> 0, step: 1
1956 22:14:20.477776
1957 22:14:20.481247 RX Delay -130 -> 252, step: 16
1958 22:14:20.484551 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1959 22:14:20.487883 iDelay=222, Bit 1, Center 77 (-34 ~ 189) 224
1960 22:14:20.490833 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1961 22:14:20.494347 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1962 22:14:20.501424 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1963 22:14:20.504290 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1964 22:14:20.507916 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1965 22:14:20.510983 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1966 22:14:20.514174 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1967 22:14:20.520695 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1968 22:14:20.524279 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1969 22:14:20.527554 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1970 22:14:20.530911 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1971 22:14:20.537459 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1972 22:14:20.540841 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1973 22:14:20.543984 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1974 22:14:20.544066 ==
1975 22:14:20.547725 Dram Type= 6, Freq= 0, CH_1, rank 1
1976 22:14:20.550902 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1977 22:14:20.550986 ==
1978 22:14:20.553813 DQS Delay:
1979 22:14:20.553896 DQS0 = 0, DQS1 = 0
1980 22:14:20.557331 DQM Delay:
1981 22:14:20.557414 DQM0 = 87, DQM1 = 78
1982 22:14:20.557478 DQ Delay:
1983 22:14:20.560436 DQ0 =85, DQ1 =77, DQ2 =77, DQ3 =85
1984 22:14:20.564040 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1985 22:14:20.567618 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1986 22:14:20.570640 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1987 22:14:20.570745
1988 22:14:20.570837
1989 22:14:20.573973 ==
1990 22:14:20.577077 Dram Type= 6, Freq= 0, CH_1, rank 1
1991 22:14:20.580379 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1992 22:14:20.580507 ==
1993 22:14:20.580642
1994 22:14:20.580730
1995 22:14:20.584340 TX Vref Scan disable
1996 22:14:20.584441 == TX Byte 0 ==
1997 22:14:20.590177 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1998 22:14:20.593944 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1999 22:14:20.594077 == TX Byte 1 ==
2000 22:14:20.600090 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2001 22:14:20.603370 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2002 22:14:20.603471 ==
2003 22:14:20.607202 Dram Type= 6, Freq= 0, CH_1, rank 1
2004 22:14:20.610187 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2005 22:14:20.610312 ==
2006 22:14:20.624110 TX Vref=22, minBit 8, minWin=26, winSum=446
2007 22:14:20.627212 TX Vref=24, minBit 8, minWin=27, winSum=446
2008 22:14:20.631161 TX Vref=26, minBit 13, minWin=27, winSum=450
2009 22:14:20.633562 TX Vref=28, minBit 15, minWin=27, winSum=453
2010 22:14:20.637515 TX Vref=30, minBit 13, minWin=27, winSum=450
2011 22:14:20.643778 TX Vref=32, minBit 8, minWin=27, winSum=450
2012 22:14:20.646760 [TxChooseVref] Worse bit 15, Min win 27, Win sum 453, Final Vref 28
2013 22:14:20.646869
2014 22:14:20.650042 Final TX Range 1 Vref 28
2015 22:14:20.650151
2016 22:14:20.650243 ==
2017 22:14:20.653828 Dram Type= 6, Freq= 0, CH_1, rank 1
2018 22:14:20.656831 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2019 22:14:20.659995 ==
2020 22:14:20.660122
2021 22:14:20.660237
2022 22:14:20.660349 TX Vref Scan disable
2023 22:14:20.664254 == TX Byte 0 ==
2024 22:14:20.667505 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
2025 22:14:20.670876 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
2026 22:14:20.673910 == TX Byte 1 ==
2027 22:14:20.677443 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2028 22:14:20.683948 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2029 22:14:20.684088
2030 22:14:20.684206 [DATLAT]
2031 22:14:20.684306 Freq=800, CH1 RK1
2032 22:14:20.684398
2033 22:14:20.687250 DATLAT Default: 0xa
2034 22:14:20.687345 0, 0xFFFF, sum = 0
2035 22:14:20.690751 1, 0xFFFF, sum = 0
2036 22:14:20.690875 2, 0xFFFF, sum = 0
2037 22:14:20.693779 3, 0xFFFF, sum = 0
2038 22:14:20.693889 4, 0xFFFF, sum = 0
2039 22:14:20.697110 5, 0xFFFF, sum = 0
2040 22:14:20.700719 6, 0xFFFF, sum = 0
2041 22:14:20.700830 7, 0xFFFF, sum = 0
2042 22:14:20.703930 8, 0xFFFF, sum = 0
2043 22:14:20.704037 9, 0x0, sum = 1
2044 22:14:20.704134 10, 0x0, sum = 2
2045 22:14:20.707132 11, 0x0, sum = 3
2046 22:14:20.707232 12, 0x0, sum = 4
2047 22:14:20.710257 best_step = 10
2048 22:14:20.710356
2049 22:14:20.710446 ==
2050 22:14:20.714078 Dram Type= 6, Freq= 0, CH_1, rank 1
2051 22:14:20.717491 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2052 22:14:20.717601 ==
2053 22:14:20.720606 RX Vref Scan: 0
2054 22:14:20.720704
2055 22:14:20.720793 RX Vref 0 -> 0, step: 1
2056 22:14:20.720879
2057 22:14:20.724007 RX Delay -95 -> 252, step: 8
2058 22:14:20.730462 iDelay=217, Bit 0, Center 92 (-23 ~ 208) 232
2059 22:14:20.734023 iDelay=217, Bit 1, Center 80 (-31 ~ 192) 224
2060 22:14:20.737810 iDelay=217, Bit 2, Center 76 (-39 ~ 192) 232
2061 22:14:20.740463 iDelay=217, Bit 3, Center 84 (-23 ~ 192) 216
2062 22:14:20.744085 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
2063 22:14:20.750698 iDelay=217, Bit 5, Center 96 (-15 ~ 208) 224
2064 22:14:20.753778 iDelay=217, Bit 6, Center 100 (-15 ~ 216) 232
2065 22:14:20.757401 iDelay=217, Bit 7, Center 84 (-31 ~ 200) 232
2066 22:14:20.760446 iDelay=217, Bit 8, Center 68 (-47 ~ 184) 232
2067 22:14:20.763628 iDelay=217, Bit 9, Center 72 (-39 ~ 184) 224
2068 22:14:20.770885 iDelay=217, Bit 10, Center 80 (-39 ~ 200) 240
2069 22:14:20.773838 iDelay=217, Bit 11, Center 68 (-47 ~ 184) 232
2070 22:14:20.776914 iDelay=217, Bit 12, Center 84 (-31 ~ 200) 232
2071 22:14:20.780467 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
2072 22:14:20.786961 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
2073 22:14:20.790353 iDelay=217, Bit 15, Center 88 (-31 ~ 208) 240
2074 22:14:20.790457 ==
2075 22:14:20.793764 Dram Type= 6, Freq= 0, CH_1, rank 1
2076 22:14:20.796763 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2077 22:14:20.796907 ==
2078 22:14:20.800224 DQS Delay:
2079 22:14:20.800327 DQS0 = 0, DQS1 = 0
2080 22:14:20.800418 DQM Delay:
2081 22:14:20.803626 DQM0 = 87, DQM1 = 78
2082 22:14:20.803723 DQ Delay:
2083 22:14:20.806864 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
2084 22:14:20.810270 DQ4 =84, DQ5 =96, DQ6 =100, DQ7 =84
2085 22:14:20.813411 DQ8 =68, DQ9 =72, DQ10 =80, DQ11 =68
2086 22:14:20.816888 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =88
2087 22:14:20.816999
2088 22:14:20.817092
2089 22:14:20.826767 [DQSOSCAuto] RK1, (LSB)MR18= 0x170f, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 404 ps
2090 22:14:20.826920 CH1 RK1: MR19=606, MR18=170F
2091 22:14:20.833207 CH1_RK1: MR19=0x606, MR18=0x170F, DQSOSC=404, MR23=63, INC=90, DEC=60
2092 22:14:20.836787 [RxdqsGatingPostProcess] freq 800
2093 22:14:20.843682 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2094 22:14:20.846753 Pre-setting of DQS Precalculation
2095 22:14:20.850558 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2096 22:14:20.856677 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2097 22:14:20.866421 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2098 22:14:20.866511
2099 22:14:20.866575
2100 22:14:20.869826 [Calibration Summary] 1600 Mbps
2101 22:14:20.869909 CH 0, Rank 0
2102 22:14:20.873017 SW Impedance : PASS
2103 22:14:20.873099 DUTY Scan : NO K
2104 22:14:20.876762 ZQ Calibration : PASS
2105 22:14:20.879967 Jitter Meter : NO K
2106 22:14:20.880050 CBT Training : PASS
2107 22:14:20.883434 Write leveling : PASS
2108 22:14:20.883516 RX DQS gating : PASS
2109 22:14:20.886599 RX DQ/DQS(RDDQC) : PASS
2110 22:14:20.890042 TX DQ/DQS : PASS
2111 22:14:20.890124 RX DATLAT : PASS
2112 22:14:20.893133 RX DQ/DQS(Engine): PASS
2113 22:14:20.896451 TX OE : NO K
2114 22:14:20.896575 All Pass.
2115 22:14:20.896641
2116 22:14:20.896701 CH 0, Rank 1
2117 22:14:20.899733 SW Impedance : PASS
2118 22:14:20.902949 DUTY Scan : NO K
2119 22:14:20.903031 ZQ Calibration : PASS
2120 22:14:20.906484 Jitter Meter : NO K
2121 22:14:20.909718 CBT Training : PASS
2122 22:14:20.909799 Write leveling : PASS
2123 22:14:20.913289 RX DQS gating : PASS
2124 22:14:20.916874 RX DQ/DQS(RDDQC) : PASS
2125 22:14:20.916956 TX DQ/DQS : PASS
2126 22:14:20.919633 RX DATLAT : PASS
2127 22:14:20.923034 RX DQ/DQS(Engine): PASS
2128 22:14:20.923116 TX OE : NO K
2129 22:14:20.926185 All Pass.
2130 22:14:20.926267
2131 22:14:20.926331 CH 1, Rank 0
2132 22:14:20.929597 SW Impedance : PASS
2133 22:14:20.929679 DUTY Scan : NO K
2134 22:14:20.933527 ZQ Calibration : PASS
2135 22:14:20.936358 Jitter Meter : NO K
2136 22:14:20.936439 CBT Training : PASS
2137 22:14:20.940094 Write leveling : PASS
2138 22:14:20.940177 RX DQS gating : PASS
2139 22:14:20.942977 RX DQ/DQS(RDDQC) : PASS
2140 22:14:20.946551 TX DQ/DQS : PASS
2141 22:14:20.946632 RX DATLAT : PASS
2142 22:14:20.949638 RX DQ/DQS(Engine): PASS
2143 22:14:20.953209 TX OE : NO K
2144 22:14:20.953291 All Pass.
2145 22:14:20.953355
2146 22:14:20.953414 CH 1, Rank 1
2147 22:14:20.956460 SW Impedance : PASS
2148 22:14:20.959680 DUTY Scan : NO K
2149 22:14:20.959761 ZQ Calibration : PASS
2150 22:14:20.963191 Jitter Meter : NO K
2151 22:14:20.966538 CBT Training : PASS
2152 22:14:20.966619 Write leveling : PASS
2153 22:14:20.969925 RX DQS gating : PASS
2154 22:14:20.973019 RX DQ/DQS(RDDQC) : PASS
2155 22:14:20.973091 TX DQ/DQS : PASS
2156 22:14:20.976479 RX DATLAT : PASS
2157 22:14:20.979689 RX DQ/DQS(Engine): PASS
2158 22:14:20.979764 TX OE : NO K
2159 22:14:20.979840 All Pass.
2160 22:14:20.983592
2161 22:14:20.983663 DramC Write-DBI off
2162 22:14:20.986123 PER_BANK_REFRESH: Hybrid Mode
2163 22:14:20.986198 TX_TRACKING: ON
2164 22:14:20.989222 [GetDramInforAfterCalByMRR] Vendor 6.
2165 22:14:20.992769 [GetDramInforAfterCalByMRR] Revision 606.
2166 22:14:20.999854 [GetDramInforAfterCalByMRR] Revision 2 0.
2167 22:14:20.999935 MR0 0x3b3b
2168 22:14:20.999999 MR8 0x5151
2169 22:14:21.002535 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2170 22:14:21.002605
2171 22:14:21.005800 MR0 0x3b3b
2172 22:14:21.005872 MR8 0x5151
2173 22:14:21.009138 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2174 22:14:21.009213
2175 22:14:21.019494 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2176 22:14:21.022618 [FAST_K] Save calibration result to emmc
2177 22:14:21.025762 [FAST_K] Save calibration result to emmc
2178 22:14:21.028907 dram_init: config_dvfs: 1
2179 22:14:21.032900 dramc_set_vcore_voltage set vcore to 662500
2180 22:14:21.036087 Read voltage for 1200, 2
2181 22:14:21.036163 Vio18 = 0
2182 22:14:21.036226 Vcore = 662500
2183 22:14:21.038920 Vdram = 0
2184 22:14:21.038997 Vddq = 0
2185 22:14:21.039060 Vmddr = 0
2186 22:14:21.045445 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2187 22:14:21.048894 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2188 22:14:21.052619 MEM_TYPE=3, freq_sel=15
2189 22:14:21.055901 sv_algorithm_assistance_LP4_1600
2190 22:14:21.059069 ============ PULL DRAM RESETB DOWN ============
2191 22:14:21.062251 ========== PULL DRAM RESETB DOWN end =========
2192 22:14:21.068914 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2193 22:14:21.072335 ===================================
2194 22:14:21.072409 LPDDR4 DRAM CONFIGURATION
2195 22:14:21.075316 ===================================
2196 22:14:21.078833 EX_ROW_EN[0] = 0x0
2197 22:14:21.082711 EX_ROW_EN[1] = 0x0
2198 22:14:21.082781 LP4Y_EN = 0x0
2199 22:14:21.085153 WORK_FSP = 0x0
2200 22:14:21.085222 WL = 0x4
2201 22:14:21.088982 RL = 0x4
2202 22:14:21.089055 BL = 0x2
2203 22:14:21.091743 RPST = 0x0
2204 22:14:21.091811 RD_PRE = 0x0
2205 22:14:21.095210 WR_PRE = 0x1
2206 22:14:21.095279 WR_PST = 0x0
2207 22:14:21.098448 DBI_WR = 0x0
2208 22:14:21.098522 DBI_RD = 0x0
2209 22:14:21.101898 OTF = 0x1
2210 22:14:21.105314 ===================================
2211 22:14:21.108494 ===================================
2212 22:14:21.108585 ANA top config
2213 22:14:21.112424 ===================================
2214 22:14:21.114883 DLL_ASYNC_EN = 0
2215 22:14:21.118274 ALL_SLAVE_EN = 0
2216 22:14:21.121729 NEW_RANK_MODE = 1
2217 22:14:21.121805 DLL_IDLE_MODE = 1
2218 22:14:21.125013 LP45_APHY_COMB_EN = 1
2219 22:14:21.128216 TX_ODT_DIS = 1
2220 22:14:21.131517 NEW_8X_MODE = 1
2221 22:14:21.135070 ===================================
2222 22:14:21.138624 ===================================
2223 22:14:21.141864 data_rate = 2400
2224 22:14:21.141938 CKR = 1
2225 22:14:21.145240 DQ_P2S_RATIO = 8
2226 22:14:21.148351 ===================================
2227 22:14:21.151844 CA_P2S_RATIO = 8
2228 22:14:21.155089 DQ_CA_OPEN = 0
2229 22:14:21.158355 DQ_SEMI_OPEN = 0
2230 22:14:21.162010 CA_SEMI_OPEN = 0
2231 22:14:21.162080 CA_FULL_RATE = 0
2232 22:14:21.165016 DQ_CKDIV4_EN = 0
2233 22:14:21.168227 CA_CKDIV4_EN = 0
2234 22:14:21.171531 CA_PREDIV_EN = 0
2235 22:14:21.174909 PH8_DLY = 17
2236 22:14:21.177939 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2237 22:14:21.178007 DQ_AAMCK_DIV = 4
2238 22:14:21.181676 CA_AAMCK_DIV = 4
2239 22:14:21.186094 CA_ADMCK_DIV = 4
2240 22:14:21.188432 DQ_TRACK_CA_EN = 0
2241 22:14:21.191260 CA_PICK = 1200
2242 22:14:21.194527 CA_MCKIO = 1200
2243 22:14:21.198240 MCKIO_SEMI = 0
2244 22:14:21.198308 PLL_FREQ = 2366
2245 22:14:21.201901 DQ_UI_PI_RATIO = 32
2246 22:14:21.204873 CA_UI_PI_RATIO = 0
2247 22:14:21.207993 ===================================
2248 22:14:21.211621 ===================================
2249 22:14:21.214780 memory_type:LPDDR4
2250 22:14:21.217787 GP_NUM : 10
2251 22:14:21.217856 SRAM_EN : 1
2252 22:14:21.221492 MD32_EN : 0
2253 22:14:21.224426 ===================================
2254 22:14:21.224492 [ANA_INIT] >>>>>>>>>>>>>>
2255 22:14:21.228031 <<<<<< [CONFIGURE PHASE]: ANA_TX
2256 22:14:21.231131 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2257 22:14:21.234489 ===================================
2258 22:14:21.237828 data_rate = 2400,PCW = 0X5b00
2259 22:14:21.240939 ===================================
2260 22:14:21.244205 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2261 22:14:21.251191 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2262 22:14:21.258094 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2263 22:14:21.261326 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2264 22:14:21.264726 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2265 22:14:21.267648 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2266 22:14:21.270775 [ANA_INIT] flow start
2267 22:14:21.270850 [ANA_INIT] PLL >>>>>>>>
2268 22:14:21.274420 [ANA_INIT] PLL <<<<<<<<
2269 22:14:21.277832 [ANA_INIT] MIDPI >>>>>>>>
2270 22:14:21.277903 [ANA_INIT] MIDPI <<<<<<<<
2271 22:14:21.280962 [ANA_INIT] DLL >>>>>>>>
2272 22:14:21.284146 [ANA_INIT] DLL <<<<<<<<
2273 22:14:21.284244 [ANA_INIT] flow end
2274 22:14:21.291528 ============ LP4 DIFF to SE enter ============
2275 22:14:21.293967 ============ LP4 DIFF to SE exit ============
2276 22:14:21.297859 [ANA_INIT] <<<<<<<<<<<<<
2277 22:14:21.300914 [Flow] Enable top DCM control >>>>>
2278 22:14:21.304187 [Flow] Enable top DCM control <<<<<
2279 22:14:21.304269 Enable DLL master slave shuffle
2280 22:14:21.310453 ==============================================================
2281 22:14:21.313909 Gating Mode config
2282 22:14:21.317373 ==============================================================
2283 22:14:21.320463 Config description:
2284 22:14:21.330338 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2285 22:14:21.337305 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2286 22:14:21.340315 SELPH_MODE 0: By rank 1: By Phase
2287 22:14:21.347031 ==============================================================
2288 22:14:21.350283 GAT_TRACK_EN = 1
2289 22:14:21.353943 RX_GATING_MODE = 2
2290 22:14:21.357932 RX_GATING_TRACK_MODE = 2
2291 22:14:21.360207 SELPH_MODE = 1
2292 22:14:21.360290 PICG_EARLY_EN = 1
2293 22:14:21.363461 VALID_LAT_VALUE = 1
2294 22:14:21.370328 ==============================================================
2295 22:14:21.373777 Enter into Gating configuration >>>>
2296 22:14:21.376822 Exit from Gating configuration <<<<
2297 22:14:21.380204 Enter into DVFS_PRE_config >>>>>
2298 22:14:21.390055 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2299 22:14:21.393336 Exit from DVFS_PRE_config <<<<<
2300 22:14:21.397133 Enter into PICG configuration >>>>
2301 22:14:21.399878 Exit from PICG configuration <<<<
2302 22:14:21.403271 [RX_INPUT] configuration >>>>>
2303 22:14:21.406796 [RX_INPUT] configuration <<<<<
2304 22:14:21.410080 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2305 22:14:21.416635 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2306 22:14:21.422934 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2307 22:14:21.430090 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2308 22:14:21.436521 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2309 22:14:21.442931 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2310 22:14:21.446469 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2311 22:14:21.450145 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2312 22:14:21.453100 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2313 22:14:21.459452 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2314 22:14:21.462679 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2315 22:14:21.466127 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2316 22:14:21.469367 ===================================
2317 22:14:21.472824 LPDDR4 DRAM CONFIGURATION
2318 22:14:21.476450 ===================================
2319 22:14:21.476595 EX_ROW_EN[0] = 0x0
2320 22:14:21.479795 EX_ROW_EN[1] = 0x0
2321 22:14:21.479877 LP4Y_EN = 0x0
2322 22:14:21.482894 WORK_FSP = 0x0
2323 22:14:21.482975 WL = 0x4
2324 22:14:21.485981 RL = 0x4
2325 22:14:21.489200 BL = 0x2
2326 22:14:21.489283 RPST = 0x0
2327 22:14:21.493153 RD_PRE = 0x0
2328 22:14:21.493236 WR_PRE = 0x1
2329 22:14:21.496219 WR_PST = 0x0
2330 22:14:21.496327 DBI_WR = 0x0
2331 22:14:21.499241 DBI_RD = 0x0
2332 22:14:21.499323 OTF = 0x1
2333 22:14:21.502459 ===================================
2334 22:14:21.505959 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2335 22:14:21.512415 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2336 22:14:21.515805 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2337 22:14:21.518868 ===================================
2338 22:14:21.522531 LPDDR4 DRAM CONFIGURATION
2339 22:14:21.525874 ===================================
2340 22:14:21.525957 EX_ROW_EN[0] = 0x10
2341 22:14:21.528711 EX_ROW_EN[1] = 0x0
2342 22:14:21.528816 LP4Y_EN = 0x0
2343 22:14:21.532633 WORK_FSP = 0x0
2344 22:14:21.535785 WL = 0x4
2345 22:14:21.535867 RL = 0x4
2346 22:14:21.538739 BL = 0x2
2347 22:14:21.538819 RPST = 0x0
2348 22:14:21.542144 RD_PRE = 0x0
2349 22:14:21.542224 WR_PRE = 0x1
2350 22:14:21.545726 WR_PST = 0x0
2351 22:14:21.545806 DBI_WR = 0x0
2352 22:14:21.549238 DBI_RD = 0x0
2353 22:14:21.549317 OTF = 0x1
2354 22:14:21.552183 ===================================
2355 22:14:21.558848 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2356 22:14:21.558928 ==
2357 22:14:21.562896 Dram Type= 6, Freq= 0, CH_0, rank 0
2358 22:14:21.566240 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2359 22:14:21.566322 ==
2360 22:14:21.568750 [Duty_Offset_Calibration]
2361 22:14:21.572005 B0:1 B1:-1 CA:0
2362 22:14:21.572084
2363 22:14:21.575643 [DutyScan_Calibration_Flow] k_type=0
2364 22:14:21.583607
2365 22:14:21.583686 ==CLK 0==
2366 22:14:21.587711 Final CLK duty delay cell = 0
2367 22:14:21.590211 [0] MAX Duty = 5125%(X100), DQS PI = 24
2368 22:14:21.593326 [0] MIN Duty = 4907%(X100), DQS PI = 6
2369 22:14:21.593404 [0] AVG Duty = 5016%(X100)
2370 22:14:21.596586
2371 22:14:21.600169 CH0 CLK Duty spec in!! Max-Min= 218%
2372 22:14:21.603427 [DutyScan_Calibration_Flow] ====Done====
2373 22:14:21.603516
2374 22:14:21.606487 [DutyScan_Calibration_Flow] k_type=1
2375 22:14:21.621304
2376 22:14:21.621383 ==DQS 0 ==
2377 22:14:21.624547 Final DQS duty delay cell = -4
2378 22:14:21.627982 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2379 22:14:21.631283 [-4] MIN Duty = 4875%(X100), DQS PI = 56
2380 22:14:21.634363 [-4] AVG Duty = 4968%(X100)
2381 22:14:21.634442
2382 22:14:21.634505 ==DQS 1 ==
2383 22:14:21.637735 Final DQS duty delay cell = -4
2384 22:14:21.641440 [-4] MAX Duty = 5000%(X100), DQS PI = 6
2385 22:14:21.644564 [-4] MIN Duty = 4876%(X100), DQS PI = 24
2386 22:14:21.647956 [-4] AVG Duty = 4938%(X100)
2387 22:14:21.648035
2388 22:14:21.651046 CH0 DQS 0 Duty spec in!! Max-Min= 187%
2389 22:14:21.651126
2390 22:14:21.654316 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2391 22:14:21.658068 [DutyScan_Calibration_Flow] ====Done====
2392 22:14:21.658147
2393 22:14:21.660921 [DutyScan_Calibration_Flow] k_type=3
2394 22:14:21.679333
2395 22:14:21.679417 ==DQM 0 ==
2396 22:14:21.682458 Final DQM duty delay cell = 0
2397 22:14:21.686238 [0] MAX Duty = 5062%(X100), DQS PI = 22
2398 22:14:21.689105 [0] MIN Duty = 4875%(X100), DQS PI = 8
2399 22:14:21.689189 [0] AVG Duty = 4968%(X100)
2400 22:14:21.692413
2401 22:14:21.692510 ==DQM 1 ==
2402 22:14:21.695823 Final DQM duty delay cell = 4
2403 22:14:21.699017 [4] MAX Duty = 5187%(X100), DQS PI = 14
2404 22:14:21.702616 [4] MIN Duty = 5000%(X100), DQS PI = 24
2405 22:14:21.706592 [4] AVG Duty = 5093%(X100)
2406 22:14:21.706677
2407 22:14:21.709012 CH0 DQM 0 Duty spec in!! Max-Min= 187%
2408 22:14:21.709096
2409 22:14:21.712632 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2410 22:14:21.715648 [DutyScan_Calibration_Flow] ====Done====
2411 22:14:21.715731
2412 22:14:21.719266 [DutyScan_Calibration_Flow] k_type=2
2413 22:14:21.734487
2414 22:14:21.734571 ==DQ 0 ==
2415 22:14:21.737820 Final DQ duty delay cell = -4
2416 22:14:21.741107 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2417 22:14:21.744111 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2418 22:14:21.747784 [-4] AVG Duty = 4969%(X100)
2419 22:14:21.747868
2420 22:14:21.747950 ==DQ 1 ==
2421 22:14:21.750769 Final DQ duty delay cell = -4
2422 22:14:21.753915 [-4] MAX Duty = 5000%(X100), DQS PI = 56
2423 22:14:21.757301 [-4] MIN Duty = 4876%(X100), DQS PI = 16
2424 22:14:21.760721 [-4] AVG Duty = 4938%(X100)
2425 22:14:21.760804
2426 22:14:21.763831 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2427 22:14:21.763915
2428 22:14:21.766989 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2429 22:14:21.770758 [DutyScan_Calibration_Flow] ====Done====
2430 22:14:21.770842 ==
2431 22:14:21.773854 Dram Type= 6, Freq= 0, CH_1, rank 0
2432 22:14:21.777169 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2433 22:14:21.777253 ==
2434 22:14:21.780325 [Duty_Offset_Calibration]
2435 22:14:21.783768 B0:-1 B1:1 CA:1
2436 22:14:21.783852
2437 22:14:21.786583 [DutyScan_Calibration_Flow] k_type=0
2438 22:14:21.794609
2439 22:14:21.794691 ==CLK 0==
2440 22:14:21.797949 Final CLK duty delay cell = 0
2441 22:14:21.801345 [0] MAX Duty = 5156%(X100), DQS PI = 20
2442 22:14:21.804841 [0] MIN Duty = 4969%(X100), DQS PI = 62
2443 22:14:21.804924 [0] AVG Duty = 5062%(X100)
2444 22:14:21.808373
2445 22:14:21.811653 CH1 CLK Duty spec in!! Max-Min= 187%
2446 22:14:21.814886 [DutyScan_Calibration_Flow] ====Done====
2447 22:14:21.814970
2448 22:14:21.817965 [DutyScan_Calibration_Flow] k_type=1
2449 22:14:21.834020
2450 22:14:21.834104 ==DQS 0 ==
2451 22:14:21.837901 Final DQS duty delay cell = 0
2452 22:14:21.841028 [0] MAX Duty = 5125%(X100), DQS PI = 48
2453 22:14:21.844663 [0] MIN Duty = 4907%(X100), DQS PI = 8
2454 22:14:21.847284 [0] AVG Duty = 5016%(X100)
2455 22:14:21.847367
2456 22:14:21.847450 ==DQS 1 ==
2457 22:14:21.850592 Final DQS duty delay cell = 0
2458 22:14:21.854048 [0] MAX Duty = 5094%(X100), DQS PI = 10
2459 22:14:21.857176 [0] MIN Duty = 4969%(X100), DQS PI = 58
2460 22:14:21.860656 [0] AVG Duty = 5031%(X100)
2461 22:14:21.860739
2462 22:14:21.864220 CH1 DQS 0 Duty spec in!! Max-Min= 218%
2463 22:14:21.864304
2464 22:14:21.867074 CH1 DQS 1 Duty spec in!! Max-Min= 125%
2465 22:14:21.870578 [DutyScan_Calibration_Flow] ====Done====
2466 22:14:21.870660
2467 22:14:21.874191 [DutyScan_Calibration_Flow] k_type=3
2468 22:14:21.890035
2469 22:14:21.890116 ==DQM 0 ==
2470 22:14:21.893143 Final DQM duty delay cell = -4
2471 22:14:21.896361 [-4] MAX Duty = 5062%(X100), DQS PI = 34
2472 22:14:21.900007 [-4] MIN Duty = 4876%(X100), DQS PI = 6
2473 22:14:21.902955 [-4] AVG Duty = 4969%(X100)
2474 22:14:21.903037
2475 22:14:21.903100 ==DQM 1 ==
2476 22:14:21.906083 Final DQM duty delay cell = 0
2477 22:14:21.909716 [0] MAX Duty = 5187%(X100), DQS PI = 6
2478 22:14:21.913031 [0] MIN Duty = 5000%(X100), DQS PI = 28
2479 22:14:21.916171 [0] AVG Duty = 5093%(X100)
2480 22:14:21.916252
2481 22:14:21.919796 CH1 DQM 0 Duty spec in!! Max-Min= 186%
2482 22:14:21.919877
2483 22:14:21.923197 CH1 DQM 1 Duty spec in!! Max-Min= 187%
2484 22:14:21.926217 [DutyScan_Calibration_Flow] ====Done====
2485 22:14:21.926298
2486 22:14:21.929388 [DutyScan_Calibration_Flow] k_type=2
2487 22:14:21.946991
2488 22:14:21.947073 ==DQ 0 ==
2489 22:14:21.950013 Final DQ duty delay cell = 0
2490 22:14:21.953510 [0] MAX Duty = 5156%(X100), DQS PI = 28
2491 22:14:21.956275 [0] MIN Duty = 4907%(X100), DQS PI = 6
2492 22:14:21.956356 [0] AVG Duty = 5031%(X100)
2493 22:14:21.956420
2494 22:14:21.960288 ==DQ 1 ==
2495 22:14:21.962879 Final DQ duty delay cell = 0
2496 22:14:21.966534 [0] MAX Duty = 5124%(X100), DQS PI = 10
2497 22:14:21.969881 [0] MIN Duty = 4969%(X100), DQS PI = 0
2498 22:14:21.969963 [0] AVG Duty = 5046%(X100)
2499 22:14:21.970027
2500 22:14:21.973179 CH1 DQ 0 Duty spec in!! Max-Min= 249%
2501 22:14:21.976391
2502 22:14:21.980032 CH1 DQ 1 Duty spec in!! Max-Min= 155%
2503 22:14:21.982843 [DutyScan_Calibration_Flow] ====Done====
2504 22:14:21.986485 nWR fixed to 30
2505 22:14:21.986567 [ModeRegInit_LP4] CH0 RK0
2506 22:14:21.989538 [ModeRegInit_LP4] CH0 RK1
2507 22:14:21.993420 [ModeRegInit_LP4] CH1 RK0
2508 22:14:21.993502 [ModeRegInit_LP4] CH1 RK1
2509 22:14:21.996087 match AC timing 7
2510 22:14:21.999572 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2511 22:14:22.005983 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2512 22:14:22.009457 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2513 22:14:22.012669 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2514 22:14:22.019789 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2515 22:14:22.019903 ==
2516 22:14:22.022542 Dram Type= 6, Freq= 0, CH_0, rank 0
2517 22:14:22.026186 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2518 22:14:22.026283 ==
2519 22:14:22.032928 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2520 22:14:22.039488 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2521 22:14:22.046244 [CA 0] Center 39 (9~70) winsize 62
2522 22:14:22.049573 [CA 1] Center 39 (9~69) winsize 61
2523 22:14:22.052882 [CA 2] Center 35 (5~66) winsize 62
2524 22:14:22.056365 [CA 3] Center 35 (5~66) winsize 62
2525 22:14:22.059696 [CA 4] Center 33 (4~63) winsize 60
2526 22:14:22.063183 [CA 5] Center 33 (3~63) winsize 61
2527 22:14:22.063283
2528 22:14:22.066760 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2529 22:14:22.066860
2530 22:14:22.069395 [CATrainingPosCal] consider 1 rank data
2531 22:14:22.073189 u2DelayCellTimex100 = 270/100 ps
2532 22:14:22.076313 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2533 22:14:22.079500 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2534 22:14:22.086325 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2535 22:14:22.089724 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2536 22:14:22.093192 CA4 delay=33 (4~63),Diff = 0 PI (0 cell)
2537 22:14:22.096233 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2538 22:14:22.096332
2539 22:14:22.099202 CA PerBit enable=1, Macro0, CA PI delay=33
2540 22:14:22.099300
2541 22:14:22.102665 [CBTSetCACLKResult] CA Dly = 33
2542 22:14:22.102764 CS Dly: 8 (0~39)
2543 22:14:22.106370 ==
2544 22:14:22.109510 Dram Type= 6, Freq= 0, CH_0, rank 1
2545 22:14:22.112797 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2546 22:14:22.112897 ==
2547 22:14:22.116018 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2548 22:14:22.122368 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2549 22:14:22.132100 [CA 0] Center 39 (9~70) winsize 62
2550 22:14:22.135099 [CA 1] Center 39 (9~70) winsize 62
2551 22:14:22.138823 [CA 2] Center 35 (5~66) winsize 62
2552 22:14:22.142377 [CA 3] Center 34 (4~65) winsize 62
2553 22:14:22.145274 [CA 4] Center 33 (3~64) winsize 62
2554 22:14:22.148385 [CA 5] Center 33 (3~63) winsize 61
2555 22:14:22.148484
2556 22:14:22.152152 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2557 22:14:22.152259
2558 22:14:22.155524 [CATrainingPosCal] consider 2 rank data
2559 22:14:22.158564 u2DelayCellTimex100 = 270/100 ps
2560 22:14:22.161890 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2561 22:14:22.165271 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2562 22:14:22.171905 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2563 22:14:22.175106 CA3 delay=35 (5~65),Diff = 2 PI (9 cell)
2564 22:14:22.178574 CA4 delay=33 (4~63),Diff = 0 PI (0 cell)
2565 22:14:22.181608 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2566 22:14:22.181707
2567 22:14:22.185076 CA PerBit enable=1, Macro0, CA PI delay=33
2568 22:14:22.185152
2569 22:14:22.188334 [CBTSetCACLKResult] CA Dly = 33
2570 22:14:22.188427 CS Dly: 9 (0~41)
2571 22:14:22.191946
2572 22:14:22.195307 ----->DramcWriteLeveling(PI) begin...
2573 22:14:22.195407 ==
2574 22:14:22.198556 Dram Type= 6, Freq= 0, CH_0, rank 0
2575 22:14:22.201759 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2576 22:14:22.201859 ==
2577 22:14:22.205299 Write leveling (Byte 0): 34 => 34
2578 22:14:22.208513 Write leveling (Byte 1): 27 => 27
2579 22:14:22.211721 DramcWriteLeveling(PI) end<-----
2580 22:14:22.211819
2581 22:14:22.211910 ==
2582 22:14:22.214786 Dram Type= 6, Freq= 0, CH_0, rank 0
2583 22:14:22.218168 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2584 22:14:22.218268 ==
2585 22:14:22.221407 [Gating] SW mode calibration
2586 22:14:22.228651 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2587 22:14:22.234699 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2588 22:14:22.237978 0 15 0 | B1->B0 | 2323 3232 | 0 1 | (0 0) (1 1)
2589 22:14:22.241228 0 15 4 | B1->B0 | 2626 3434 | 0 1 | (0 0) (1 1)
2590 22:14:22.247798 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2591 22:14:22.251259 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2592 22:14:22.254953 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2593 22:14:22.261449 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2594 22:14:22.264359 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2595 22:14:22.267640 0 15 28 | B1->B0 | 3434 2d2d | 1 1 | (1 1) (0 0)
2596 22:14:22.274972 1 0 0 | B1->B0 | 2f2f 2323 | 0 0 | (0 1) (0 0)
2597 22:14:22.277684 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2598 22:14:22.281574 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2599 22:14:22.288014 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2600 22:14:22.290908 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2601 22:14:22.294952 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2602 22:14:22.301047 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2603 22:14:22.304339 1 0 28 | B1->B0 | 2323 3d3d | 0 0 | (0 0) (0 0)
2604 22:14:22.308427 1 1 0 | B1->B0 | 2727 4545 | 1 0 | (0 0) (0 0)
2605 22:14:22.311183 1 1 4 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
2606 22:14:22.317394 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2607 22:14:22.320905 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2608 22:14:22.324488 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2609 22:14:22.330776 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2610 22:14:22.334186 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2611 22:14:22.337322 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2612 22:14:22.344165 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2613 22:14:22.347401 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2614 22:14:22.350690 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2615 22:14:22.357512 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2616 22:14:22.360721 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2617 22:14:22.364440 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2618 22:14:22.370496 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2619 22:14:22.373859 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2620 22:14:22.377716 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2621 22:14:22.384074 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2622 22:14:22.387320 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2623 22:14:22.390770 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2624 22:14:22.397127 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2625 22:14:22.400281 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2626 22:14:22.403590 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2627 22:14:22.410580 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2628 22:14:22.413968 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2629 22:14:22.417270 Total UI for P1: 0, mck2ui 16
2630 22:14:22.420392 best dqsien dly found for B0: ( 1, 3, 28)
2631 22:14:22.423799 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2632 22:14:22.426853 Total UI for P1: 0, mck2ui 16
2633 22:14:22.430332 best dqsien dly found for B1: ( 1, 4, 0)
2634 22:14:22.433696 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2635 22:14:22.436867 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2636 22:14:22.436949
2637 22:14:22.443514 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2638 22:14:22.447088 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2639 22:14:22.447170 [Gating] SW calibration Done
2640 22:14:22.450232 ==
2641 22:14:22.450316 Dram Type= 6, Freq= 0, CH_0, rank 0
2642 22:14:22.456693 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2643 22:14:22.456776 ==
2644 22:14:22.456840 RX Vref Scan: 0
2645 22:14:22.456900
2646 22:14:22.460350 RX Vref 0 -> 0, step: 1
2647 22:14:22.460432
2648 22:14:22.463363 RX Delay -40 -> 252, step: 8
2649 22:14:22.466652 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2650 22:14:22.470238 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2651 22:14:22.473588 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2652 22:14:22.479768 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2653 22:14:22.483318 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2654 22:14:22.486535 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2655 22:14:22.490171 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2656 22:14:22.493137 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2657 22:14:22.499666 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2658 22:14:22.503571 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2659 22:14:22.506366 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152
2660 22:14:22.509575 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2661 22:14:22.513167 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2662 22:14:22.519837 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2663 22:14:22.523270 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2664 22:14:22.526173 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2665 22:14:22.526255 ==
2666 22:14:22.529785 Dram Type= 6, Freq= 0, CH_0, rank 0
2667 22:14:22.533346 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2668 22:14:22.536520 ==
2669 22:14:22.536603 DQS Delay:
2670 22:14:22.536668 DQS0 = 0, DQS1 = 0
2671 22:14:22.539491 DQM Delay:
2672 22:14:22.539573 DQM0 = 119, DQM1 = 106
2673 22:14:22.542980 DQ Delay:
2674 22:14:22.546431 DQ0 =119, DQ1 =119, DQ2 =115, DQ3 =115
2675 22:14:22.549655 DQ4 =123, DQ5 =111, DQ6 =127, DQ7 =127
2676 22:14:22.552765 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2677 22:14:22.556006 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
2678 22:14:22.556104
2679 22:14:22.556179
2680 22:14:22.556241 ==
2681 22:14:22.559439 Dram Type= 6, Freq= 0, CH_0, rank 0
2682 22:14:22.562940 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2683 22:14:22.563022 ==
2684 22:14:22.563086
2685 22:14:22.563146
2686 22:14:22.565955 TX Vref Scan disable
2687 22:14:22.569193 == TX Byte 0 ==
2688 22:14:22.573030 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2689 22:14:22.576061 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2690 22:14:22.579345 == TX Byte 1 ==
2691 22:14:22.582876 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2692 22:14:22.586018 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2693 22:14:22.586101 ==
2694 22:14:22.589234 Dram Type= 6, Freq= 0, CH_0, rank 0
2695 22:14:22.596054 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2696 22:14:22.596137 ==
2697 22:14:22.606887 TX Vref=22, minBit 10, minWin=25, winSum=419
2698 22:14:22.610109 TX Vref=24, minBit 8, minWin=26, winSum=428
2699 22:14:22.613580 TX Vref=26, minBit 8, minWin=25, winSum=428
2700 22:14:22.617066 TX Vref=28, minBit 5, minWin=26, winSum=433
2701 22:14:22.620636 TX Vref=30, minBit 8, minWin=26, winSum=431
2702 22:14:22.627043 TX Vref=32, minBit 5, minWin=26, winSum=431
2703 22:14:22.630132 [TxChooseVref] Worse bit 5, Min win 26, Win sum 433, Final Vref 28
2704 22:14:22.630215
2705 22:14:22.633543 Final TX Range 1 Vref 28
2706 22:14:22.633625
2707 22:14:22.633690 ==
2708 22:14:22.636706 Dram Type= 6, Freq= 0, CH_0, rank 0
2709 22:14:22.640599 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2710 22:14:22.640681 ==
2711 22:14:22.643248
2712 22:14:22.643329
2713 22:14:22.643392 TX Vref Scan disable
2714 22:14:22.646816 == TX Byte 0 ==
2715 22:14:22.650246 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2716 22:14:22.656509 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2717 22:14:22.656628 == TX Byte 1 ==
2718 22:14:22.659867 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
2719 22:14:22.666610 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
2720 22:14:22.666691
2721 22:14:22.666755 [DATLAT]
2722 22:14:22.666815 Freq=1200, CH0 RK0
2723 22:14:22.666873
2724 22:14:22.669925 DATLAT Default: 0xd
2725 22:14:22.673042 0, 0xFFFF, sum = 0
2726 22:14:22.673125 1, 0xFFFF, sum = 0
2727 22:14:22.676651 2, 0xFFFF, sum = 0
2728 22:14:22.676734 3, 0xFFFF, sum = 0
2729 22:14:22.679850 4, 0xFFFF, sum = 0
2730 22:14:22.679932 5, 0xFFFF, sum = 0
2731 22:14:22.683459 6, 0xFFFF, sum = 0
2732 22:14:22.683541 7, 0xFFFF, sum = 0
2733 22:14:22.686217 8, 0xFFFF, sum = 0
2734 22:14:22.686300 9, 0xFFFF, sum = 0
2735 22:14:22.689956 10, 0xFFFF, sum = 0
2736 22:14:22.690038 11, 0xFFFF, sum = 0
2737 22:14:22.693036 12, 0x0, sum = 1
2738 22:14:22.693119 13, 0x0, sum = 2
2739 22:14:22.696547 14, 0x0, sum = 3
2740 22:14:22.696643 15, 0x0, sum = 4
2741 22:14:22.699859 best_step = 13
2742 22:14:22.699940
2743 22:14:22.700004 ==
2744 22:14:22.702816 Dram Type= 6, Freq= 0, CH_0, rank 0
2745 22:14:22.706207 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2746 22:14:22.706288 ==
2747 22:14:22.709260 RX Vref Scan: 1
2748 22:14:22.709341
2749 22:14:22.709405 Set Vref Range= 32 -> 127
2750 22:14:22.709465
2751 22:14:22.712636 RX Vref 32 -> 127, step: 1
2752 22:14:22.712717
2753 22:14:22.716084 RX Delay -21 -> 252, step: 4
2754 22:14:22.716166
2755 22:14:22.719830 Set Vref, RX VrefLevel [Byte0]: 32
2756 22:14:22.722699 [Byte1]: 32
2757 22:14:22.722785
2758 22:14:22.726701 Set Vref, RX VrefLevel [Byte0]: 33
2759 22:14:22.729664 [Byte1]: 33
2760 22:14:22.733041
2761 22:14:22.733122 Set Vref, RX VrefLevel [Byte0]: 34
2762 22:14:22.736501 [Byte1]: 34
2763 22:14:22.741057
2764 22:14:22.741138 Set Vref, RX VrefLevel [Byte0]: 35
2765 22:14:22.745481 [Byte1]: 35
2766 22:14:22.749140
2767 22:14:22.749220 Set Vref, RX VrefLevel [Byte0]: 36
2768 22:14:22.752482 [Byte1]: 36
2769 22:14:22.757268
2770 22:14:22.757348 Set Vref, RX VrefLevel [Byte0]: 37
2771 22:14:22.760159 [Byte1]: 37
2772 22:14:22.764928
2773 22:14:22.765009 Set Vref, RX VrefLevel [Byte0]: 38
2774 22:14:22.768175 [Byte1]: 38
2775 22:14:22.772688
2776 22:14:22.772770 Set Vref, RX VrefLevel [Byte0]: 39
2777 22:14:22.775995 [Byte1]: 39
2778 22:14:22.780608
2779 22:14:22.780689 Set Vref, RX VrefLevel [Byte0]: 40
2780 22:14:22.784151 [Byte1]: 40
2781 22:14:22.788688
2782 22:14:22.788769 Set Vref, RX VrefLevel [Byte0]: 41
2783 22:14:22.792319 [Byte1]: 41
2784 22:14:22.797153
2785 22:14:22.797234 Set Vref, RX VrefLevel [Byte0]: 42
2786 22:14:22.799989 [Byte1]: 42
2787 22:14:22.805121
2788 22:14:22.805202 Set Vref, RX VrefLevel [Byte0]: 43
2789 22:14:22.807909 [Byte1]: 43
2790 22:14:22.812480
2791 22:14:22.812570 Set Vref, RX VrefLevel [Byte0]: 44
2792 22:14:22.815755 [Byte1]: 44
2793 22:14:22.820389
2794 22:14:22.820470 Set Vref, RX VrefLevel [Byte0]: 45
2795 22:14:22.824193 [Byte1]: 45
2796 22:14:22.828352
2797 22:14:22.828433 Set Vref, RX VrefLevel [Byte0]: 46
2798 22:14:22.831573 [Byte1]: 46
2799 22:14:22.836483
2800 22:14:22.836605 Set Vref, RX VrefLevel [Byte0]: 47
2801 22:14:22.839491 [Byte1]: 47
2802 22:14:22.844202
2803 22:14:22.844283 Set Vref, RX VrefLevel [Byte0]: 48
2804 22:14:22.847329 [Byte1]: 48
2805 22:14:22.852030
2806 22:14:22.852111 Set Vref, RX VrefLevel [Byte0]: 49
2807 22:14:22.855924 [Byte1]: 49
2808 22:14:22.860432
2809 22:14:22.860521 Set Vref, RX VrefLevel [Byte0]: 50
2810 22:14:22.863163 [Byte1]: 50
2811 22:14:22.868525
2812 22:14:22.868606 Set Vref, RX VrefLevel [Byte0]: 51
2813 22:14:22.871110 [Byte1]: 51
2814 22:14:22.875904
2815 22:14:22.876011 Set Vref, RX VrefLevel [Byte0]: 52
2816 22:14:22.879751 [Byte1]: 52
2817 22:14:22.884052
2818 22:14:22.884133 Set Vref, RX VrefLevel [Byte0]: 53
2819 22:14:22.887164 [Byte1]: 53
2820 22:14:22.891717
2821 22:14:22.891798 Set Vref, RX VrefLevel [Byte0]: 54
2822 22:14:22.894846 [Byte1]: 54
2823 22:14:22.899800
2824 22:14:22.899882 Set Vref, RX VrefLevel [Byte0]: 55
2825 22:14:22.902794 [Byte1]: 55
2826 22:14:22.907521
2827 22:14:22.907602 Set Vref, RX VrefLevel [Byte0]: 56
2828 22:14:22.910899 [Byte1]: 56
2829 22:14:22.915803
2830 22:14:22.915884 Set Vref, RX VrefLevel [Byte0]: 57
2831 22:14:22.919045 [Byte1]: 57
2832 22:14:22.923413
2833 22:14:22.923494 Set Vref, RX VrefLevel [Byte0]: 58
2834 22:14:22.926770 [Byte1]: 58
2835 22:14:22.931655
2836 22:14:22.931736 Set Vref, RX VrefLevel [Byte0]: 59
2837 22:14:22.934558 [Byte1]: 59
2838 22:14:22.939497
2839 22:14:22.939577 Set Vref, RX VrefLevel [Byte0]: 60
2840 22:14:22.942602 [Byte1]: 60
2841 22:14:22.947382
2842 22:14:22.947463 Set Vref, RX VrefLevel [Byte0]: 61
2843 22:14:22.950616 [Byte1]: 61
2844 22:14:22.955049
2845 22:14:22.955129 Set Vref, RX VrefLevel [Byte0]: 62
2846 22:14:22.959290 [Byte1]: 62
2847 22:14:22.963331
2848 22:14:22.963427 Set Vref, RX VrefLevel [Byte0]: 63
2849 22:14:22.966793 [Byte1]: 63
2850 22:14:22.970899
2851 22:14:22.970980 Set Vref, RX VrefLevel [Byte0]: 64
2852 22:14:22.974330 [Byte1]: 64
2853 22:14:22.979374
2854 22:14:22.979454 Set Vref, RX VrefLevel [Byte0]: 65
2855 22:14:22.982044 [Byte1]: 65
2856 22:14:22.987162
2857 22:14:22.987243 Set Vref, RX VrefLevel [Byte0]: 66
2858 22:14:22.990085 [Byte1]: 66
2859 22:14:22.994956
2860 22:14:22.995037 Set Vref, RX VrefLevel [Byte0]: 67
2861 22:14:22.998163 [Byte1]: 67
2862 22:14:23.003016
2863 22:14:23.003097 Set Vref, RX VrefLevel [Byte0]: 68
2864 22:14:23.005996 [Byte1]: 68
2865 22:14:23.010620
2866 22:14:23.010702 Set Vref, RX VrefLevel [Byte0]: 69
2867 22:14:23.013939 [Byte1]: 69
2868 22:14:23.018884
2869 22:14:23.018978 Set Vref, RX VrefLevel [Byte0]: 70
2870 22:14:23.021763 [Byte1]: 70
2871 22:14:23.026712
2872 22:14:23.026793 Set Vref, RX VrefLevel [Byte0]: 71
2873 22:14:23.029819 [Byte1]: 71
2874 22:14:23.035008
2875 22:14:23.035105 Set Vref, RX VrefLevel [Byte0]: 72
2876 22:14:23.037583 [Byte1]: 72
2877 22:14:23.042467
2878 22:14:23.042548 Set Vref, RX VrefLevel [Byte0]: 73
2879 22:14:23.045568 [Byte1]: 73
2880 22:14:23.050189
2881 22:14:23.050270 Set Vref, RX VrefLevel [Byte0]: 74
2882 22:14:23.053699 [Byte1]: 74
2883 22:14:23.058256
2884 22:14:23.058337 Set Vref, RX VrefLevel [Byte0]: 75
2885 22:14:23.062618 [Byte1]: 75
2886 22:14:23.066525
2887 22:14:23.066606 Set Vref, RX VrefLevel [Byte0]: 76
2888 22:14:23.069965 [Byte1]: 76
2889 22:14:23.074042
2890 22:14:23.074123 Set Vref, RX VrefLevel [Byte0]: 77
2891 22:14:23.077598 [Byte1]: 77
2892 22:14:23.082220
2893 22:14:23.082301 Set Vref, RX VrefLevel [Byte0]: 78
2894 22:14:23.085592 [Byte1]: 78
2895 22:14:23.089863
2896 22:14:23.089944 Set Vref, RX VrefLevel [Byte0]: 79
2897 22:14:23.093340 [Byte1]: 79
2898 22:14:23.097859
2899 22:14:23.097941 Final RX Vref Byte 0 = 59 to rank0
2900 22:14:23.101208 Final RX Vref Byte 1 = 49 to rank0
2901 22:14:23.104335 Final RX Vref Byte 0 = 59 to rank1
2902 22:14:23.108445 Final RX Vref Byte 1 = 49 to rank1==
2903 22:14:23.111626 Dram Type= 6, Freq= 0, CH_0, rank 0
2904 22:14:23.118462 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2905 22:14:23.118544 ==
2906 22:14:23.118609 DQS Delay:
2907 22:14:23.118669 DQS0 = 0, DQS1 = 0
2908 22:14:23.120972 DQM Delay:
2909 22:14:23.121109 DQM0 = 119, DQM1 = 106
2910 22:14:23.124652 DQ Delay:
2911 22:14:23.127607 DQ0 =116, DQ1 =120, DQ2 =116, DQ3 =116
2912 22:14:23.131161 DQ4 =120, DQ5 =114, DQ6 =126, DQ7 =128
2913 22:14:23.134396 DQ8 =96, DQ9 =92, DQ10 =110, DQ11 =100
2914 22:14:23.137626 DQ12 =110, DQ13 =110, DQ14 =118, DQ15 =116
2915 22:14:23.137707
2916 22:14:23.137771
2917 22:14:23.144103 [DQSOSCAuto] RK0, (LSB)MR18= 0xefa, (MSB)MR19= 0x403, tDQSOscB0 = 412 ps tDQSOscB1 = 404 ps
2918 22:14:23.147628 CH0 RK0: MR19=403, MR18=EFA
2919 22:14:23.154251 CH0_RK0: MR19=0x403, MR18=0xEFA, DQSOSC=404, MR23=63, INC=40, DEC=26
2920 22:14:23.154333
2921 22:14:23.157902 ----->DramcWriteLeveling(PI) begin...
2922 22:14:23.157985 ==
2923 22:14:23.161070 Dram Type= 6, Freq= 0, CH_0, rank 1
2924 22:14:23.164735 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2925 22:14:23.167326 ==
2926 22:14:23.167407 Write leveling (Byte 0): 32 => 32
2927 22:14:23.171059 Write leveling (Byte 1): 31 => 31
2928 22:14:23.174166 DramcWriteLeveling(PI) end<-----
2929 22:14:23.174247
2930 22:14:23.174310 ==
2931 22:14:23.177382 Dram Type= 6, Freq= 0, CH_0, rank 1
2932 22:14:23.184210 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2933 22:14:23.184291 ==
2934 22:14:23.184356 [Gating] SW mode calibration
2935 22:14:23.194105 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2936 22:14:23.197202 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2937 22:14:23.204040 0 15 0 | B1->B0 | 2727 3434 | 0 0 | (0 0) (0 0)
2938 22:14:23.207254 0 15 4 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 1)
2939 22:14:23.210783 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2940 22:14:23.216997 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2941 22:14:23.220387 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2942 22:14:23.223620 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2943 22:14:23.227127 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2944 22:14:23.233743 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2945 22:14:23.237011 1 0 0 | B1->B0 | 2e2e 2323 | 0 0 | (1 0) (0 0)
2946 22:14:23.240681 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2947 22:14:23.247102 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2948 22:14:23.250381 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2949 22:14:23.253534 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2950 22:14:23.260513 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2951 22:14:23.263926 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2952 22:14:23.266917 1 0 28 | B1->B0 | 2323 3b3b | 0 0 | (0 0) (0 0)
2953 22:14:23.273667 1 1 0 | B1->B0 | 3636 4646 | 0 0 | (0 0) (0 0)
2954 22:14:23.277068 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2955 22:14:23.280338 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2956 22:14:23.287056 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2957 22:14:23.290644 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2958 22:14:23.293525 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2959 22:14:23.300316 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2960 22:14:23.303598 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2961 22:14:23.307377 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2962 22:14:23.313550 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2963 22:14:23.316657 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2964 22:14:23.319901 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2965 22:14:23.326822 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2966 22:14:23.330214 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2967 22:14:23.333355 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2968 22:14:23.339815 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2969 22:14:23.343264 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2970 22:14:23.346414 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2971 22:14:23.352906 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2972 22:14:23.356206 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2973 22:14:23.359741 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2974 22:14:23.366186 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2975 22:14:23.369538 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2976 22:14:23.372890 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2977 22:14:23.379558 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2978 22:14:23.382859 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2979 22:14:23.386444 Total UI for P1: 0, mck2ui 16
2980 22:14:23.389910 best dqsien dly found for B0: ( 1, 3, 30)
2981 22:14:23.393314 Total UI for P1: 0, mck2ui 16
2982 22:14:23.396504 best dqsien dly found for B1: ( 1, 4, 0)
2983 22:14:23.399795 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2984 22:14:23.403258 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2985 22:14:23.403350
2986 22:14:23.406365 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2987 22:14:23.409767 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2988 22:14:23.412740 [Gating] SW calibration Done
2989 22:14:23.412822 ==
2990 22:14:23.416253 Dram Type= 6, Freq= 0, CH_0, rank 1
2991 22:14:23.419699 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2992 22:14:23.419781 ==
2993 22:14:23.423467 RX Vref Scan: 0
2994 22:14:23.423547
2995 22:14:23.426883 RX Vref 0 -> 0, step: 1
2996 22:14:23.426964
2997 22:14:23.427028 RX Delay -40 -> 252, step: 8
2998 22:14:23.432902 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2999 22:14:23.436392 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
3000 22:14:23.439662 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
3001 22:14:23.442738 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3002 22:14:23.446465 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3003 22:14:23.452458 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
3004 22:14:23.456246 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3005 22:14:23.459419 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
3006 22:14:23.462597 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3007 22:14:23.465804 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3008 22:14:23.472366 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3009 22:14:23.475997 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3010 22:14:23.479345 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
3011 22:14:23.482312 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3012 22:14:23.485910 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3013 22:14:23.492299 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3014 22:14:23.492381 ==
3015 22:14:23.495535 Dram Type= 6, Freq= 0, CH_0, rank 1
3016 22:14:23.498713 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3017 22:14:23.498795 ==
3018 22:14:23.498860 DQS Delay:
3019 22:14:23.502075 DQS0 = 0, DQS1 = 0
3020 22:14:23.502157 DQM Delay:
3021 22:14:23.505688 DQM0 = 117, DQM1 = 108
3022 22:14:23.505769 DQ Delay:
3023 22:14:23.509216 DQ0 =111, DQ1 =119, DQ2 =111, DQ3 =115
3024 22:14:23.512391 DQ4 =115, DQ5 =111, DQ6 =127, DQ7 =127
3025 22:14:23.515753 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =103
3026 22:14:23.519258 DQ12 =111, DQ13 =119, DQ14 =119, DQ15 =111
3027 22:14:23.519340
3028 22:14:23.522240
3029 22:14:23.522321 ==
3030 22:14:23.525371 Dram Type= 6, Freq= 0, CH_0, rank 1
3031 22:14:23.528725 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3032 22:14:23.528807 ==
3033 22:14:23.528870
3034 22:14:23.528929
3035 22:14:23.532377 TX Vref Scan disable
3036 22:14:23.532459 == TX Byte 0 ==
3037 22:14:23.535820 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
3038 22:14:23.542563 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
3039 22:14:23.542645 == TX Byte 1 ==
3040 22:14:23.548502 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
3041 22:14:23.551884 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
3042 22:14:23.551966 ==
3043 22:14:23.555126 Dram Type= 6, Freq= 0, CH_0, rank 1
3044 22:14:23.558515 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3045 22:14:23.558597 ==
3046 22:14:23.570850 TX Vref=22, minBit 6, minWin=25, winSum=421
3047 22:14:23.574577 TX Vref=24, minBit 0, minWin=26, winSum=422
3048 22:14:23.577547 TX Vref=26, minBit 1, minWin=26, winSum=431
3049 22:14:23.580673 TX Vref=28, minBit 10, minWin=26, winSum=433
3050 22:14:23.584755 TX Vref=30, minBit 1, minWin=26, winSum=432
3051 22:14:23.590651 TX Vref=32, minBit 12, minWin=26, winSum=434
3052 22:14:23.594445 [TxChooseVref] Worse bit 12, Min win 26, Win sum 434, Final Vref 32
3053 22:14:23.594527
3054 22:14:23.597517 Final TX Range 1 Vref 32
3055 22:14:23.597599
3056 22:14:23.597664 ==
3057 22:14:23.601374 Dram Type= 6, Freq= 0, CH_0, rank 1
3058 22:14:23.603943 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3059 22:14:23.607132 ==
3060 22:14:23.607213
3061 22:14:23.607276
3062 22:14:23.607335 TX Vref Scan disable
3063 22:14:23.611140 == TX Byte 0 ==
3064 22:14:23.614075 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
3065 22:14:23.620452 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
3066 22:14:23.620556 == TX Byte 1 ==
3067 22:14:23.624358 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
3068 22:14:23.630535 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
3069 22:14:23.630617
3070 22:14:23.630681 [DATLAT]
3071 22:14:23.630741 Freq=1200, CH0 RK1
3072 22:14:23.630799
3073 22:14:23.633994 DATLAT Default: 0xd
3074 22:14:23.634078 0, 0xFFFF, sum = 0
3075 22:14:23.637634 1, 0xFFFF, sum = 0
3076 22:14:23.640685 2, 0xFFFF, sum = 0
3077 22:14:23.640767 3, 0xFFFF, sum = 0
3078 22:14:23.643756 4, 0xFFFF, sum = 0
3079 22:14:23.643839 5, 0xFFFF, sum = 0
3080 22:14:23.647011 6, 0xFFFF, sum = 0
3081 22:14:23.647093 7, 0xFFFF, sum = 0
3082 22:14:23.650469 8, 0xFFFF, sum = 0
3083 22:14:23.650552 9, 0xFFFF, sum = 0
3084 22:14:23.653789 10, 0xFFFF, sum = 0
3085 22:14:23.653871 11, 0xFFFF, sum = 0
3086 22:14:23.656900 12, 0x0, sum = 1
3087 22:14:23.656983 13, 0x0, sum = 2
3088 22:14:23.661117 14, 0x0, sum = 3
3089 22:14:23.661199 15, 0x0, sum = 4
3090 22:14:23.663465 best_step = 13
3091 22:14:23.663546
3092 22:14:23.663609 ==
3093 22:14:23.666823 Dram Type= 6, Freq= 0, CH_0, rank 1
3094 22:14:23.670478 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3095 22:14:23.670562 ==
3096 22:14:23.670629 RX Vref Scan: 0
3097 22:14:23.673667
3098 22:14:23.673751 RX Vref 0 -> 0, step: 1
3099 22:14:23.673816
3100 22:14:23.676800 RX Delay -21 -> 252, step: 4
3101 22:14:23.683831 iDelay=199, Bit 0, Center 114 (47 ~ 182) 136
3102 22:14:23.686967 iDelay=199, Bit 1, Center 118 (47 ~ 190) 144
3103 22:14:23.690502 iDelay=199, Bit 2, Center 110 (43 ~ 178) 136
3104 22:14:23.693612 iDelay=199, Bit 3, Center 114 (43 ~ 186) 144
3105 22:14:23.696904 iDelay=199, Bit 4, Center 116 (47 ~ 186) 140
3106 22:14:23.700623 iDelay=199, Bit 5, Center 110 (43 ~ 178) 136
3107 22:14:23.707301 iDelay=199, Bit 6, Center 126 (55 ~ 198) 144
3108 22:14:23.710014 iDelay=199, Bit 7, Center 124 (55 ~ 194) 140
3109 22:14:23.713685 iDelay=199, Bit 8, Center 96 (27 ~ 166) 140
3110 22:14:23.716987 iDelay=199, Bit 9, Center 94 (27 ~ 162) 136
3111 22:14:23.719947 iDelay=199, Bit 10, Center 110 (43 ~ 178) 136
3112 22:14:23.727595 iDelay=199, Bit 11, Center 100 (35 ~ 166) 132
3113 22:14:23.730273 iDelay=199, Bit 12, Center 112 (47 ~ 178) 132
3114 22:14:23.733430 iDelay=199, Bit 13, Center 114 (47 ~ 182) 136
3115 22:14:23.736402 iDelay=199, Bit 14, Center 118 (55 ~ 182) 128
3116 22:14:23.743252 iDelay=199, Bit 15, Center 116 (51 ~ 182) 132
3117 22:14:23.743335 ==
3118 22:14:23.746611 Dram Type= 6, Freq= 0, CH_0, rank 1
3119 22:14:23.749798 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3120 22:14:23.749881 ==
3121 22:14:23.749946 DQS Delay:
3122 22:14:23.753081 DQS0 = 0, DQS1 = 0
3123 22:14:23.753163 DQM Delay:
3124 22:14:23.756560 DQM0 = 116, DQM1 = 107
3125 22:14:23.756642 DQ Delay:
3126 22:14:23.759983 DQ0 =114, DQ1 =118, DQ2 =110, DQ3 =114
3127 22:14:23.763160 DQ4 =116, DQ5 =110, DQ6 =126, DQ7 =124
3128 22:14:23.766629 DQ8 =96, DQ9 =94, DQ10 =110, DQ11 =100
3129 22:14:23.769877 DQ12 =112, DQ13 =114, DQ14 =118, DQ15 =116
3130 22:14:23.769959
3131 22:14:23.770024
3132 22:14:23.779883 [DQSOSCAuto] RK1, (LSB)MR18= 0xfea, (MSB)MR19= 0x403, tDQSOscB0 = 419 ps tDQSOscB1 = 404 ps
3133 22:14:23.783245 CH0 RK1: MR19=403, MR18=FEA
3134 22:14:23.786408 CH0_RK1: MR19=0x403, MR18=0xFEA, DQSOSC=404, MR23=63, INC=40, DEC=26
3135 22:14:23.790033 [RxdqsGatingPostProcess] freq 1200
3136 22:14:23.796702 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3137 22:14:23.799981 best DQS0 dly(2T, 0.5T) = (0, 11)
3138 22:14:23.803036 best DQS1 dly(2T, 0.5T) = (0, 12)
3139 22:14:23.806165 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3140 22:14:23.809531 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3141 22:14:23.813317 best DQS0 dly(2T, 0.5T) = (0, 11)
3142 22:14:23.815996 best DQS1 dly(2T, 0.5T) = (0, 12)
3143 22:14:23.819222 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3144 22:14:23.822971 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3145 22:14:23.825772 Pre-setting of DQS Precalculation
3146 22:14:23.829147 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3147 22:14:23.829230 ==
3148 22:14:23.833136 Dram Type= 6, Freq= 0, CH_1, rank 0
3149 22:14:23.835828 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3150 22:14:23.835935 ==
3151 22:14:23.842663 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3152 22:14:23.849423 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3153 22:14:23.856730 [CA 0] Center 37 (8~67) winsize 60
3154 22:14:23.860237 [CA 1] Center 37 (7~68) winsize 62
3155 22:14:23.863897 [CA 2] Center 34 (4~65) winsize 62
3156 22:14:23.867304 [CA 3] Center 33 (3~64) winsize 62
3157 22:14:23.870356 [CA 4] Center 34 (4~64) winsize 61
3158 22:14:23.873724 [CA 5] Center 33 (3~64) winsize 62
3159 22:14:23.873805
3160 22:14:23.876786 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3161 22:14:23.876868
3162 22:14:23.879865 [CATrainingPosCal] consider 1 rank data
3163 22:14:23.883820 u2DelayCellTimex100 = 270/100 ps
3164 22:14:23.886748 CA0 delay=37 (8~67),Diff = 4 PI (19 cell)
3165 22:14:23.893162 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3166 22:14:23.896445 CA2 delay=34 (4~65),Diff = 1 PI (4 cell)
3167 22:14:23.900163 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3168 22:14:23.903504 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3169 22:14:23.906538 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3170 22:14:23.906653
3171 22:14:23.909979 CA PerBit enable=1, Macro0, CA PI delay=33
3172 22:14:23.910053
3173 22:14:23.912954 [CBTSetCACLKResult] CA Dly = 33
3174 22:14:23.913060 CS Dly: 6 (0~37)
3175 22:14:23.916796 ==
3176 22:14:23.919620 Dram Type= 6, Freq= 0, CH_1, rank 1
3177 22:14:23.923010 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3178 22:14:23.923113 ==
3179 22:14:23.926500 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3180 22:14:23.932959 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3181 22:14:23.942380 [CA 0] Center 37 (7~68) winsize 62
3182 22:14:23.945744 [CA 1] Center 37 (7~68) winsize 62
3183 22:14:23.949134 [CA 2] Center 34 (4~65) winsize 62
3184 22:14:23.952326 [CA 3] Center 33 (3~64) winsize 62
3185 22:14:23.955552 [CA 4] Center 34 (4~65) winsize 62
3186 22:14:23.959083 [CA 5] Center 33 (3~64) winsize 62
3187 22:14:23.959154
3188 22:14:23.962527 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3189 22:14:23.962622
3190 22:14:23.965692 [CATrainingPosCal] consider 2 rank data
3191 22:14:23.968987 u2DelayCellTimex100 = 270/100 ps
3192 22:14:23.971887 CA0 delay=37 (8~67),Diff = 4 PI (19 cell)
3193 22:14:23.978934 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3194 22:14:23.981848 CA2 delay=34 (4~65),Diff = 1 PI (4 cell)
3195 22:14:23.985221 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3196 22:14:23.988946 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3197 22:14:23.992059 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3198 22:14:23.992142
3199 22:14:23.995212 CA PerBit enable=1, Macro0, CA PI delay=33
3200 22:14:23.995294
3201 22:14:23.999098 [CBTSetCACLKResult] CA Dly = 33
3202 22:14:23.999180 CS Dly: 7 (0~40)
3203 22:14:24.002017
3204 22:14:24.005264 ----->DramcWriteLeveling(PI) begin...
3205 22:14:24.005347 ==
3206 22:14:24.008438 Dram Type= 6, Freq= 0, CH_1, rank 0
3207 22:14:24.011772 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3208 22:14:24.011854 ==
3209 22:14:24.015281 Write leveling (Byte 0): 23 => 23
3210 22:14:24.018699 Write leveling (Byte 1): 26 => 26
3211 22:14:24.022081 DramcWriteLeveling(PI) end<-----
3212 22:14:24.022162
3213 22:14:24.022225 ==
3214 22:14:24.024958 Dram Type= 6, Freq= 0, CH_1, rank 0
3215 22:14:24.028128 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3216 22:14:24.028210 ==
3217 22:14:24.031683 [Gating] SW mode calibration
3218 22:14:24.038406 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3219 22:14:24.044902 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3220 22:14:24.048673 0 15 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
3221 22:14:24.051765 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3222 22:14:24.058269 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3223 22:14:24.061697 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3224 22:14:24.064629 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3225 22:14:24.071784 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3226 22:14:24.074632 0 15 24 | B1->B0 | 3434 2b2b | 0 1 | (0 0) (1 0)
3227 22:14:24.077924 0 15 28 | B1->B0 | 2929 2323 | 0 0 | (0 0) (1 0)
3228 22:14:24.084881 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3229 22:14:24.087799 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3230 22:14:24.091437 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3231 22:14:24.097758 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3232 22:14:24.101113 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3233 22:14:24.104468 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3234 22:14:24.111114 1 0 24 | B1->B0 | 2625 3333 | 1 0 | (0 0) (0 0)
3235 22:14:24.114351 1 0 28 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
3236 22:14:24.117863 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3237 22:14:24.124299 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3238 22:14:24.128143 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3239 22:14:24.131189 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3240 22:14:24.137663 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3241 22:14:24.141200 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3242 22:14:24.143927 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3243 22:14:24.150619 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3244 22:14:24.154560 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3245 22:14:24.157441 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3246 22:14:24.164685 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3247 22:14:24.167549 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3248 22:14:24.170711 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3249 22:14:24.173940 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3250 22:14:24.180811 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3251 22:14:24.183950 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3252 22:14:24.187496 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3253 22:14:24.194406 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3254 22:14:24.197203 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3255 22:14:24.200469 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3256 22:14:24.207357 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3257 22:14:24.210694 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3258 22:14:24.213891 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3259 22:14:24.220928 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3260 22:14:24.224201 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3261 22:14:24.226931 Total UI for P1: 0, mck2ui 16
3262 22:14:24.230420 best dqsien dly found for B0: ( 1, 3, 26)
3263 22:14:24.233501 Total UI for P1: 0, mck2ui 16
3264 22:14:24.237048 best dqsien dly found for B1: ( 1, 3, 26)
3265 22:14:24.240006 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3266 22:14:24.243749 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3267 22:14:24.243832
3268 22:14:24.247117 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3269 22:14:24.250413 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3270 22:14:24.253566 [Gating] SW calibration Done
3271 22:14:24.253639 ==
3272 22:14:24.256824 Dram Type= 6, Freq= 0, CH_1, rank 0
3273 22:14:24.263891 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3274 22:14:24.263962 ==
3275 22:14:24.264023 RX Vref Scan: 0
3276 22:14:24.264080
3277 22:14:24.266674 RX Vref 0 -> 0, step: 1
3278 22:14:24.266748
3279 22:14:24.269815 RX Delay -40 -> 252, step: 8
3280 22:14:24.273807 iDelay=208, Bit 0, Center 123 (48 ~ 199) 152
3281 22:14:24.277068 iDelay=208, Bit 1, Center 111 (40 ~ 183) 144
3282 22:14:24.280057 iDelay=208, Bit 2, Center 111 (40 ~ 183) 144
3283 22:14:24.286645 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3284 22:14:24.289951 iDelay=208, Bit 4, Center 111 (40 ~ 183) 144
3285 22:14:24.293036 iDelay=208, Bit 5, Center 131 (56 ~ 207) 152
3286 22:14:24.296601 iDelay=208, Bit 6, Center 123 (48 ~ 199) 152
3287 22:14:24.300071 iDelay=208, Bit 7, Center 115 (48 ~ 183) 136
3288 22:14:24.303665 iDelay=208, Bit 8, Center 95 (24 ~ 167) 144
3289 22:14:24.309641 iDelay=208, Bit 9, Center 99 (24 ~ 175) 152
3290 22:14:24.312956 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3291 22:14:24.316347 iDelay=208, Bit 11, Center 95 (24 ~ 167) 144
3292 22:14:24.320091 iDelay=208, Bit 12, Center 119 (48 ~ 191) 144
3293 22:14:24.323021 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3294 22:14:24.329950 iDelay=208, Bit 14, Center 115 (40 ~ 191) 152
3295 22:14:24.333208 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3296 22:14:24.333284 ==
3297 22:14:24.336292 Dram Type= 6, Freq= 0, CH_1, rank 0
3298 22:14:24.339760 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3299 22:14:24.339829 ==
3300 22:14:24.343273 DQS Delay:
3301 22:14:24.343375 DQS0 = 0, DQS1 = 0
3302 22:14:24.346103 DQM Delay:
3303 22:14:24.346170 DQM0 = 117, DQM1 = 109
3304 22:14:24.346235 DQ Delay:
3305 22:14:24.349459 DQ0 =123, DQ1 =111, DQ2 =111, DQ3 =115
3306 22:14:24.355978 DQ4 =111, DQ5 =131, DQ6 =123, DQ7 =115
3307 22:14:24.359697 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =95
3308 22:14:24.362952 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119
3309 22:14:24.363022
3310 22:14:24.363088
3311 22:14:24.363145 ==
3312 22:14:24.367414 Dram Type= 6, Freq= 0, CH_1, rank 0
3313 22:14:24.369370 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3314 22:14:24.369443 ==
3315 22:14:24.369502
3316 22:14:24.369558
3317 22:14:24.373067 TX Vref Scan disable
3318 22:14:24.373132 == TX Byte 0 ==
3319 22:14:24.379385 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
3320 22:14:24.382778 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
3321 22:14:24.382858 == TX Byte 1 ==
3322 22:14:24.389171 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3323 22:14:24.393030 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3324 22:14:24.393100 ==
3325 22:14:24.396325 Dram Type= 6, Freq= 0, CH_1, rank 0
3326 22:14:24.399373 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3327 22:14:24.399475 ==
3328 22:14:24.412163 TX Vref=22, minBit 10, minWin=25, winSum=419
3329 22:14:24.415458 TX Vref=24, minBit 2, minWin=26, winSum=425
3330 22:14:24.419062 TX Vref=26, minBit 10, minWin=26, winSum=436
3331 22:14:24.422111 TX Vref=28, minBit 11, minWin=26, winSum=437
3332 22:14:24.425442 TX Vref=30, minBit 9, minWin=26, winSum=435
3333 22:14:24.432540 TX Vref=32, minBit 10, minWin=26, winSum=432
3334 22:14:24.435979 [TxChooseVref] Worse bit 11, Min win 26, Win sum 437, Final Vref 28
3335 22:14:24.436057
3336 22:14:24.438797 Final TX Range 1 Vref 28
3337 22:14:24.438870
3338 22:14:24.438937 ==
3339 22:14:24.442761 Dram Type= 6, Freq= 0, CH_1, rank 0
3340 22:14:24.448979 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3341 22:14:24.449054 ==
3342 22:14:24.449121
3343 22:14:24.449178
3344 22:14:24.449233 TX Vref Scan disable
3345 22:14:24.452464 == TX Byte 0 ==
3346 22:14:24.455524 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
3347 22:14:24.462339 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
3348 22:14:24.462414 == TX Byte 1 ==
3349 22:14:24.465852 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3350 22:14:24.472217 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3351 22:14:24.472318
3352 22:14:24.472410 [DATLAT]
3353 22:14:24.472497 Freq=1200, CH1 RK0
3354 22:14:24.472606
3355 22:14:24.476643 DATLAT Default: 0xd
3356 22:14:24.476716 0, 0xFFFF, sum = 0
3357 22:14:24.479123 1, 0xFFFF, sum = 0
3358 22:14:24.482451 2, 0xFFFF, sum = 0
3359 22:14:24.482521 3, 0xFFFF, sum = 0
3360 22:14:24.485894 4, 0xFFFF, sum = 0
3361 22:14:24.485962 5, 0xFFFF, sum = 0
3362 22:14:24.488805 6, 0xFFFF, sum = 0
3363 22:14:24.488874 7, 0xFFFF, sum = 0
3364 22:14:24.492170 8, 0xFFFF, sum = 0
3365 22:14:24.492264 9, 0xFFFF, sum = 0
3366 22:14:24.495302 10, 0xFFFF, sum = 0
3367 22:14:24.495369 11, 0xFFFF, sum = 0
3368 22:14:24.498967 12, 0x0, sum = 1
3369 22:14:24.499037 13, 0x0, sum = 2
3370 22:14:24.502095 14, 0x0, sum = 3
3371 22:14:24.502169 15, 0x0, sum = 4
3372 22:14:24.505189 best_step = 13
3373 22:14:24.505254
3374 22:14:24.505310 ==
3375 22:14:24.508914 Dram Type= 6, Freq= 0, CH_1, rank 0
3376 22:14:24.512119 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3377 22:14:24.512216 ==
3378 22:14:24.515160 RX Vref Scan: 1
3379 22:14:24.515227
3380 22:14:24.515291 Set Vref Range= 32 -> 127
3381 22:14:24.515347
3382 22:14:24.518404 RX Vref 32 -> 127, step: 1
3383 22:14:24.518480
3384 22:14:24.521997 RX Delay -21 -> 252, step: 4
3385 22:14:24.522062
3386 22:14:24.525457 Set Vref, RX VrefLevel [Byte0]: 32
3387 22:14:24.528298 [Byte1]: 32
3388 22:14:24.528390
3389 22:14:24.532048 Set Vref, RX VrefLevel [Byte0]: 33
3390 22:14:24.534849 [Byte1]: 33
3391 22:14:24.538970
3392 22:14:24.539045 Set Vref, RX VrefLevel [Byte0]: 34
3393 22:14:24.542658 [Byte1]: 34
3394 22:14:24.547046
3395 22:14:24.547153 Set Vref, RX VrefLevel [Byte0]: 35
3396 22:14:24.550089 [Byte1]: 35
3397 22:14:24.555025
3398 22:14:24.555093 Set Vref, RX VrefLevel [Byte0]: 36
3399 22:14:24.558444 [Byte1]: 36
3400 22:14:24.562494
3401 22:14:24.562564 Set Vref, RX VrefLevel [Byte0]: 37
3402 22:14:24.566318 [Byte1]: 37
3403 22:14:24.570837
3404 22:14:24.570905 Set Vref, RX VrefLevel [Byte0]: 38
3405 22:14:24.573871 [Byte1]: 38
3406 22:14:24.578500
3407 22:14:24.578572 Set Vref, RX VrefLevel [Byte0]: 39
3408 22:14:24.581757 [Byte1]: 39
3409 22:14:24.586374
3410 22:14:24.586440 Set Vref, RX VrefLevel [Byte0]: 40
3411 22:14:24.589911 [Byte1]: 40
3412 22:14:24.595104
3413 22:14:24.595174 Set Vref, RX VrefLevel [Byte0]: 41
3414 22:14:24.597590 [Byte1]: 41
3415 22:14:24.602426
3416 22:14:24.602495 Set Vref, RX VrefLevel [Byte0]: 42
3417 22:14:24.605771 [Byte1]: 42
3418 22:14:24.610325
3419 22:14:24.610397 Set Vref, RX VrefLevel [Byte0]: 43
3420 22:14:24.613472 [Byte1]: 43
3421 22:14:24.618017
3422 22:14:24.618090 Set Vref, RX VrefLevel [Byte0]: 44
3423 22:14:24.621224 [Byte1]: 44
3424 22:14:24.626109
3425 22:14:24.626176 Set Vref, RX VrefLevel [Byte0]: 45
3426 22:14:24.632611 [Byte1]: 45
3427 22:14:24.632694
3428 22:14:24.635671 Set Vref, RX VrefLevel [Byte0]: 46
3429 22:14:24.638983 [Byte1]: 46
3430 22:14:24.639056
3431 22:14:24.642340 Set Vref, RX VrefLevel [Byte0]: 47
3432 22:14:24.645882 [Byte1]: 47
3433 22:14:24.649854
3434 22:14:24.649922 Set Vref, RX VrefLevel [Byte0]: 48
3435 22:14:24.653142 [Byte1]: 48
3436 22:14:24.657573
3437 22:14:24.657642 Set Vref, RX VrefLevel [Byte0]: 49
3438 22:14:24.660970 [Byte1]: 49
3439 22:14:24.665481
3440 22:14:24.665554 Set Vref, RX VrefLevel [Byte0]: 50
3441 22:14:24.669309 [Byte1]: 50
3442 22:14:24.673437
3443 22:14:24.673508 Set Vref, RX VrefLevel [Byte0]: 51
3444 22:14:24.677034 [Byte1]: 51
3445 22:14:24.681619
3446 22:14:24.681685 Set Vref, RX VrefLevel [Byte0]: 52
3447 22:14:24.684814 [Byte1]: 52
3448 22:14:24.689293
3449 22:14:24.689366 Set Vref, RX VrefLevel [Byte0]: 53
3450 22:14:24.692505 [Byte1]: 53
3451 22:14:24.697197
3452 22:14:24.697264 Set Vref, RX VrefLevel [Byte0]: 54
3453 22:14:24.700436 [Byte1]: 54
3454 22:14:24.705454
3455 22:14:24.705553 Set Vref, RX VrefLevel [Byte0]: 55
3456 22:14:24.708537 [Byte1]: 55
3457 22:14:24.713016
3458 22:14:24.713085 Set Vref, RX VrefLevel [Byte0]: 56
3459 22:14:24.716870 [Byte1]: 56
3460 22:14:24.721432
3461 22:14:24.721500 Set Vref, RX VrefLevel [Byte0]: 57
3462 22:14:24.724368 [Byte1]: 57
3463 22:14:24.728806
3464 22:14:24.728918 Set Vref, RX VrefLevel [Byte0]: 58
3465 22:14:24.732507 [Byte1]: 58
3466 22:14:24.737075
3467 22:14:24.737176 Set Vref, RX VrefLevel [Byte0]: 59
3468 22:14:24.740494 [Byte1]: 59
3469 22:14:24.744697
3470 22:14:24.744767 Set Vref, RX VrefLevel [Byte0]: 60
3471 22:14:24.748397 [Byte1]: 60
3472 22:14:24.752878
3473 22:14:24.752982 Set Vref, RX VrefLevel [Byte0]: 61
3474 22:14:24.756116 [Byte1]: 61
3475 22:14:24.760923
3476 22:14:24.761029 Set Vref, RX VrefLevel [Byte0]: 62
3477 22:14:24.764124 [Byte1]: 62
3478 22:14:24.768676
3479 22:14:24.768773 Set Vref, RX VrefLevel [Byte0]: 63
3480 22:14:24.771846 [Byte1]: 63
3481 22:14:24.776423
3482 22:14:24.776527 Set Vref, RX VrefLevel [Byte0]: 64
3483 22:14:24.780166 [Byte1]: 64
3484 22:14:24.784435
3485 22:14:24.784536 Set Vref, RX VrefLevel [Byte0]: 65
3486 22:14:24.787647 [Byte1]: 65
3487 22:14:24.792052
3488 22:14:24.792146 Set Vref, RX VrefLevel [Byte0]: 66
3489 22:14:24.795549 [Byte1]: 66
3490 22:14:24.800243
3491 22:14:24.800349 Set Vref, RX VrefLevel [Byte0]: 67
3492 22:14:24.803643 [Byte1]: 67
3493 22:14:24.808431
3494 22:14:24.808533 Set Vref, RX VrefLevel [Byte0]: 68
3495 22:14:24.811371 [Byte1]: 68
3496 22:14:24.816028
3497 22:14:24.816122 Set Vref, RX VrefLevel [Byte0]: 69
3498 22:14:24.819610 [Byte1]: 69
3499 22:14:24.824402
3500 22:14:24.824473 Set Vref, RX VrefLevel [Byte0]: 70
3501 22:14:24.827221 [Byte1]: 70
3502 22:14:24.831992
3503 22:14:24.832069 Set Vref, RX VrefLevel [Byte0]: 71
3504 22:14:24.835687 [Byte1]: 71
3505 22:14:24.839996
3506 22:14:24.840079 Final RX Vref Byte 0 = 48 to rank0
3507 22:14:24.843029 Final RX Vref Byte 1 = 58 to rank0
3508 22:14:24.846915 Final RX Vref Byte 0 = 48 to rank1
3509 22:14:24.849748 Final RX Vref Byte 1 = 58 to rank1==
3510 22:14:24.853263 Dram Type= 6, Freq= 0, CH_1, rank 0
3511 22:14:24.859683 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3512 22:14:24.859764 ==
3513 22:14:24.859829 DQS Delay:
3514 22:14:24.859890 DQS0 = 0, DQS1 = 0
3515 22:14:24.862811 DQM Delay:
3516 22:14:24.862892 DQM0 = 116, DQM1 = 112
3517 22:14:24.866436 DQ Delay:
3518 22:14:24.869778 DQ0 =120, DQ1 =112, DQ2 =106, DQ3 =112
3519 22:14:24.872754 DQ4 =114, DQ5 =126, DQ6 =126, DQ7 =114
3520 22:14:24.876172 DQ8 =100, DQ9 =100, DQ10 =116, DQ11 =100
3521 22:14:24.879551 DQ12 =118, DQ13 =120, DQ14 =122, DQ15 =120
3522 22:14:24.879631
3523 22:14:24.879695
3524 22:14:24.886667 [DQSOSCAuto] RK0, (LSB)MR18= 0x2f6, (MSB)MR19= 0x403, tDQSOscB0 = 414 ps tDQSOscB1 = 409 ps
3525 22:14:24.890045 CH1 RK0: MR19=403, MR18=2F6
3526 22:14:24.896693 CH1_RK0: MR19=0x403, MR18=0x2F6, DQSOSC=409, MR23=63, INC=39, DEC=26
3527 22:14:24.896774
3528 22:14:24.900071 ----->DramcWriteLeveling(PI) begin...
3529 22:14:24.900153 ==
3530 22:14:24.903325 Dram Type= 6, Freq= 0, CH_1, rank 1
3531 22:14:24.906452 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3532 22:14:24.909498 ==
3533 22:14:24.909578 Write leveling (Byte 0): 26 => 26
3534 22:14:24.912860 Write leveling (Byte 1): 27 => 27
3535 22:14:24.916144 DramcWriteLeveling(PI) end<-----
3536 22:14:24.916225
3537 22:14:24.916288 ==
3538 22:14:24.919609 Dram Type= 6, Freq= 0, CH_1, rank 1
3539 22:14:24.926015 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3540 22:14:24.926096 ==
3541 22:14:24.929146 [Gating] SW mode calibration
3542 22:14:24.935749 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3543 22:14:24.939117 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3544 22:14:24.945739 0 15 0 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
3545 22:14:24.949085 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3546 22:14:24.952731 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3547 22:14:24.959143 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3548 22:14:24.962401 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3549 22:14:24.965738 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3550 22:14:24.972143 0 15 24 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 0)
3551 22:14:24.976131 0 15 28 | B1->B0 | 2323 2424 | 0 0 | (1 0) (1 0)
3552 22:14:24.978815 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3553 22:14:24.985626 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3554 22:14:24.988697 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3555 22:14:24.992250 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3556 22:14:24.998682 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3557 22:14:25.001976 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3558 22:14:25.005408 1 0 24 | B1->B0 | 3f3f 2e2d | 1 1 | (0 0) (0 0)
3559 22:14:25.011770 1 0 28 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
3560 22:14:25.015006 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3561 22:14:25.018356 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3562 22:14:25.025190 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3563 22:14:25.028076 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3564 22:14:25.031616 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3565 22:14:25.037993 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3566 22:14:25.042194 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3567 22:14:25.044982 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3568 22:14:25.051677 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3569 22:14:25.054625 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3570 22:14:25.057868 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3571 22:14:25.064590 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3572 22:14:25.068131 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3573 22:14:25.071192 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3574 22:14:25.078147 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3575 22:14:25.081103 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3576 22:14:25.084315 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3577 22:14:25.091070 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3578 22:14:25.094532 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3579 22:14:25.098145 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3580 22:14:25.104259 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3581 22:14:25.107821 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3582 22:14:25.110781 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3583 22:14:25.117371 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3584 22:14:25.117458 Total UI for P1: 0, mck2ui 16
3585 22:14:25.120925 best dqsien dly found for B1: ( 1, 3, 24)
3586 22:14:25.127537 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3587 22:14:25.130874 Total UI for P1: 0, mck2ui 16
3588 22:14:25.134023 best dqsien dly found for B0: ( 1, 3, 26)
3589 22:14:25.137451 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3590 22:14:25.140799 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3591 22:14:25.140880
3592 22:14:25.144142 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3593 22:14:25.147068 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3594 22:14:25.150742 [Gating] SW calibration Done
3595 22:14:25.150824 ==
3596 22:14:25.154490 Dram Type= 6, Freq= 0, CH_1, rank 1
3597 22:14:25.158227 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3598 22:14:25.158309 ==
3599 22:14:25.160932 RX Vref Scan: 0
3600 22:14:25.161013
3601 22:14:25.164350 RX Vref 0 -> 0, step: 1
3602 22:14:25.164458
3603 22:14:25.164584 RX Delay -40 -> 252, step: 8
3604 22:14:25.170950 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3605 22:14:25.173756 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3606 22:14:25.177062 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3607 22:14:25.180240 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3608 22:14:25.183733 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3609 22:14:25.190360 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3610 22:14:25.193400 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3611 22:14:25.197109 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3612 22:14:25.200148 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3613 22:14:25.203527 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3614 22:14:25.209923 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3615 22:14:25.213343 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3616 22:14:25.216779 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3617 22:14:25.220375 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3618 22:14:25.226587 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
3619 22:14:25.229956 iDelay=200, Bit 15, Center 115 (40 ~ 191) 152
3620 22:14:25.230037 ==
3621 22:14:25.233354 Dram Type= 6, Freq= 0, CH_1, rank 1
3622 22:14:25.236590 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3623 22:14:25.236673 ==
3624 22:14:25.239538 DQS Delay:
3625 22:14:25.239619 DQS0 = 0, DQS1 = 0
3626 22:14:25.239683 DQM Delay:
3627 22:14:25.242955 DQM0 = 116, DQM1 = 109
3628 22:14:25.243036 DQ Delay:
3629 22:14:25.246306 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =111
3630 22:14:25.249682 DQ4 =115, DQ5 =127, DQ6 =127, DQ7 =115
3631 22:14:25.253138 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =103
3632 22:14:25.259336 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =115
3633 22:14:25.259418
3634 22:14:25.259483
3635 22:14:25.259543 ==
3636 22:14:25.262778 Dram Type= 6, Freq= 0, CH_1, rank 1
3637 22:14:25.266012 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3638 22:14:25.266094 ==
3639 22:14:25.266157
3640 22:14:25.266216
3641 22:14:25.269468 TX Vref Scan disable
3642 22:14:25.269549 == TX Byte 0 ==
3643 22:14:25.275892 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3644 22:14:25.279293 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3645 22:14:25.279374 == TX Byte 1 ==
3646 22:14:25.285870 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3647 22:14:25.289126 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3648 22:14:25.289208 ==
3649 22:14:25.292626 Dram Type= 6, Freq= 0, CH_1, rank 1
3650 22:14:25.295723 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3651 22:14:25.295804 ==
3652 22:14:25.308547 TX Vref=22, minBit 1, minWin=26, winSum=426
3653 22:14:25.311740 TX Vref=24, minBit 9, minWin=26, winSum=431
3654 22:14:25.315392 TX Vref=26, minBit 9, minWin=26, winSum=431
3655 22:14:25.318557 TX Vref=28, minBit 10, minWin=26, winSum=432
3656 22:14:25.322160 TX Vref=30, minBit 9, minWin=26, winSum=432
3657 22:14:25.328558 TX Vref=32, minBit 8, minWin=26, winSum=429
3658 22:14:25.331911 [TxChooseVref] Worse bit 10, Min win 26, Win sum 432, Final Vref 28
3659 22:14:25.331992
3660 22:14:25.335168 Final TX Range 1 Vref 28
3661 22:14:25.335250
3662 22:14:25.335314 ==
3663 22:14:25.338283 Dram Type= 6, Freq= 0, CH_1, rank 1
3664 22:14:25.342824 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3665 22:14:25.345273 ==
3666 22:14:25.345354
3667 22:14:25.345418
3668 22:14:25.345476 TX Vref Scan disable
3669 22:14:25.348866 == TX Byte 0 ==
3670 22:14:25.351892 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3671 22:14:25.358592 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3672 22:14:25.358690 == TX Byte 1 ==
3673 22:14:25.361618 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3674 22:14:25.368133 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3675 22:14:25.368259
3676 22:14:25.368341 [DATLAT]
3677 22:14:25.368401 Freq=1200, CH1 RK1
3678 22:14:25.368460
3679 22:14:25.371583 DATLAT Default: 0xd
3680 22:14:25.374734 0, 0xFFFF, sum = 0
3681 22:14:25.374821 1, 0xFFFF, sum = 0
3682 22:14:25.378310 2, 0xFFFF, sum = 0
3683 22:14:25.378391 3, 0xFFFF, sum = 0
3684 22:14:25.381536 4, 0xFFFF, sum = 0
3685 22:14:25.381619 5, 0xFFFF, sum = 0
3686 22:14:25.385013 6, 0xFFFF, sum = 0
3687 22:14:25.385096 7, 0xFFFF, sum = 0
3688 22:14:25.387822 8, 0xFFFF, sum = 0
3689 22:14:25.387904 9, 0xFFFF, sum = 0
3690 22:14:25.391258 10, 0xFFFF, sum = 0
3691 22:14:25.391340 11, 0xFFFF, sum = 0
3692 22:14:25.394673 12, 0x0, sum = 1
3693 22:14:25.394755 13, 0x0, sum = 2
3694 22:14:25.398327 14, 0x0, sum = 3
3695 22:14:25.398409 15, 0x0, sum = 4
3696 22:14:25.401283 best_step = 13
3697 22:14:25.401364
3698 22:14:25.401455 ==
3699 22:14:25.404510 Dram Type= 6, Freq= 0, CH_1, rank 1
3700 22:14:25.407884 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3701 22:14:25.407966 ==
3702 22:14:25.411078 RX Vref Scan: 0
3703 22:14:25.411159
3704 22:14:25.411222 RX Vref 0 -> 0, step: 1
3705 22:14:25.411283
3706 22:14:25.414225 RX Delay -21 -> 252, step: 4
3707 22:14:25.421163 iDelay=199, Bit 0, Center 118 (51 ~ 186) 136
3708 22:14:25.424127 iDelay=199, Bit 1, Center 110 (43 ~ 178) 136
3709 22:14:25.427465 iDelay=199, Bit 2, Center 106 (43 ~ 170) 128
3710 22:14:25.430934 iDelay=199, Bit 3, Center 112 (47 ~ 178) 132
3711 22:14:25.434209 iDelay=199, Bit 4, Center 114 (47 ~ 182) 136
3712 22:14:25.440939 iDelay=199, Bit 5, Center 126 (59 ~ 194) 136
3713 22:14:25.444294 iDelay=199, Bit 6, Center 130 (63 ~ 198) 136
3714 22:14:25.447415 iDelay=199, Bit 7, Center 116 (51 ~ 182) 132
3715 22:14:25.450574 iDelay=199, Bit 8, Center 98 (31 ~ 166) 136
3716 22:14:25.453827 iDelay=199, Bit 9, Center 100 (35 ~ 166) 132
3717 22:14:25.460776 iDelay=199, Bit 10, Center 112 (47 ~ 178) 132
3718 22:14:25.464197 iDelay=199, Bit 11, Center 102 (35 ~ 170) 136
3719 22:14:25.467600 iDelay=199, Bit 12, Center 118 (51 ~ 186) 136
3720 22:14:25.470432 iDelay=199, Bit 13, Center 118 (51 ~ 186) 136
3721 22:14:25.477057 iDelay=199, Bit 14, Center 118 (51 ~ 186) 136
3722 22:14:25.480503 iDelay=199, Bit 15, Center 120 (51 ~ 190) 140
3723 22:14:25.480607 ==
3724 22:14:25.483752 Dram Type= 6, Freq= 0, CH_1, rank 1
3725 22:14:25.486937 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3726 22:14:25.487016 ==
3727 22:14:25.490538 DQS Delay:
3728 22:14:25.490638 DQS0 = 0, DQS1 = 0
3729 22:14:25.490727 DQM Delay:
3730 22:14:25.493885 DQM0 = 116, DQM1 = 110
3731 22:14:25.493959 DQ Delay:
3732 22:14:25.496936 DQ0 =118, DQ1 =110, DQ2 =106, DQ3 =112
3733 22:14:25.500772 DQ4 =114, DQ5 =126, DQ6 =130, DQ7 =116
3734 22:14:25.503428 DQ8 =98, DQ9 =100, DQ10 =112, DQ11 =102
3735 22:14:25.509921 DQ12 =118, DQ13 =118, DQ14 =118, DQ15 =120
3736 22:14:25.509997
3737 22:14:25.510060
3738 22:14:25.517125 [DQSOSCAuto] RK1, (LSB)MR18= 0xf2ed, (MSB)MR19= 0x303, tDQSOscB0 = 417 ps tDQSOscB1 = 415 ps
3739 22:14:25.520191 CH1 RK1: MR19=303, MR18=F2ED
3740 22:14:25.526647 CH1_RK1: MR19=0x303, MR18=0xF2ED, DQSOSC=415, MR23=63, INC=38, DEC=25
3741 22:14:25.529896 [RxdqsGatingPostProcess] freq 1200
3742 22:14:25.533523 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3743 22:14:25.536875 best DQS0 dly(2T, 0.5T) = (0, 11)
3744 22:14:25.540196 best DQS1 dly(2T, 0.5T) = (0, 11)
3745 22:14:25.543591 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3746 22:14:25.546452 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3747 22:14:25.550197 best DQS0 dly(2T, 0.5T) = (0, 11)
3748 22:14:25.553239 best DQS1 dly(2T, 0.5T) = (0, 11)
3749 22:14:25.556152 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3750 22:14:25.559474 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3751 22:14:25.562945 Pre-setting of DQS Precalculation
3752 22:14:25.566183 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3753 22:14:25.576388 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3754 22:14:25.582490 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3755 22:14:25.582565
3756 22:14:25.582665
3757 22:14:25.585832 [Calibration Summary] 2400 Mbps
3758 22:14:25.585905 CH 0, Rank 0
3759 22:14:25.588981 SW Impedance : PASS
3760 22:14:25.592395 DUTY Scan : NO K
3761 22:14:25.592492 ZQ Calibration : PASS
3762 22:14:25.595600 Jitter Meter : NO K
3763 22:14:25.595674 CBT Training : PASS
3764 22:14:25.598918 Write leveling : PASS
3765 22:14:25.602446 RX DQS gating : PASS
3766 22:14:25.602546 RX DQ/DQS(RDDQC) : PASS
3767 22:14:25.605789 TX DQ/DQS : PASS
3768 22:14:25.609120 RX DATLAT : PASS
3769 22:14:25.609218 RX DQ/DQS(Engine): PASS
3770 22:14:25.612438 TX OE : NO K
3771 22:14:25.612540 All Pass.
3772 22:14:25.612604
3773 22:14:25.615533 CH 0, Rank 1
3774 22:14:25.615602 SW Impedance : PASS
3775 22:14:25.619142 DUTY Scan : NO K
3776 22:14:25.622174 ZQ Calibration : PASS
3777 22:14:25.622248 Jitter Meter : NO K
3778 22:14:25.625469 CBT Training : PASS
3779 22:14:25.628588 Write leveling : PASS
3780 22:14:25.628697 RX DQS gating : PASS
3781 22:14:25.632431 RX DQ/DQS(RDDQC) : PASS
3782 22:14:25.635339 TX DQ/DQS : PASS
3783 22:14:25.635440 RX DATLAT : PASS
3784 22:14:25.638500 RX DQ/DQS(Engine): PASS
3785 22:14:25.642078 TX OE : NO K
3786 22:14:25.642176 All Pass.
3787 22:14:25.642267
3788 22:14:25.642353 CH 1, Rank 0
3789 22:14:25.645133 SW Impedance : PASS
3790 22:14:25.648898 DUTY Scan : NO K
3791 22:14:25.648972 ZQ Calibration : PASS
3792 22:14:25.652150 Jitter Meter : NO K
3793 22:14:25.655195 CBT Training : PASS
3794 22:14:25.655292 Write leveling : PASS
3795 22:14:25.658143 RX DQS gating : PASS
3796 22:14:25.661585 RX DQ/DQS(RDDQC) : PASS
3797 22:14:25.661659 TX DQ/DQS : PASS
3798 22:14:25.665197 RX DATLAT : PASS
3799 22:14:25.665293 RX DQ/DQS(Engine): PASS
3800 22:14:25.668235 TX OE : NO K
3801 22:14:25.668332 All Pass.
3802 22:14:25.668420
3803 22:14:25.672155 CH 1, Rank 1
3804 22:14:25.675143 SW Impedance : PASS
3805 22:14:25.675214 DUTY Scan : NO K
3806 22:14:25.678171 ZQ Calibration : PASS
3807 22:14:25.678241 Jitter Meter : NO K
3808 22:14:25.681347 CBT Training : PASS
3809 22:14:25.685130 Write leveling : PASS
3810 22:14:25.685206 RX DQS gating : PASS
3811 22:14:25.688280 RX DQ/DQS(RDDQC) : PASS
3812 22:14:25.692078 TX DQ/DQS : PASS
3813 22:14:25.692176 RX DATLAT : PASS
3814 22:14:25.694990 RX DQ/DQS(Engine): PASS
3815 22:14:25.698140 TX OE : NO K
3816 22:14:25.698241 All Pass.
3817 22:14:25.698333
3818 22:14:25.702005 DramC Write-DBI off
3819 22:14:25.702103 PER_BANK_REFRESH: Hybrid Mode
3820 22:14:25.705362 TX_TRACKING: ON
3821 22:14:25.711260 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3822 22:14:25.718021 [FAST_K] Save calibration result to emmc
3823 22:14:25.721676 dramc_set_vcore_voltage set vcore to 650000
3824 22:14:25.721751 Read voltage for 600, 5
3825 22:14:25.724793 Vio18 = 0
3826 22:14:25.724862 Vcore = 650000
3827 22:14:25.724926 Vdram = 0
3828 22:14:25.728073 Vddq = 0
3829 22:14:25.728169 Vmddr = 0
3830 22:14:25.731035 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3831 22:14:25.737977 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3832 22:14:25.741611 MEM_TYPE=3, freq_sel=19
3833 22:14:25.744908 sv_algorithm_assistance_LP4_1600
3834 22:14:25.747739 ============ PULL DRAM RESETB DOWN ============
3835 22:14:25.751104 ========== PULL DRAM RESETB DOWN end =========
3836 22:14:25.757519 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3837 22:14:25.761271 ===================================
3838 22:14:25.761348 LPDDR4 DRAM CONFIGURATION
3839 22:14:25.764064 ===================================
3840 22:14:25.767653 EX_ROW_EN[0] = 0x0
3841 22:14:25.767752 EX_ROW_EN[1] = 0x0
3842 22:14:25.770744 LP4Y_EN = 0x0
3843 22:14:25.774384 WORK_FSP = 0x0
3844 22:14:25.774458 WL = 0x2
3845 22:14:25.777764 RL = 0x2
3846 22:14:25.777834 BL = 0x2
3847 22:14:25.780686 RPST = 0x0
3848 22:14:25.780753 RD_PRE = 0x0
3849 22:14:25.783974 WR_PRE = 0x1
3850 22:14:25.784044 WR_PST = 0x0
3851 22:14:25.787540 DBI_WR = 0x0
3852 22:14:25.787607 DBI_RD = 0x0
3853 22:14:25.790993 OTF = 0x1
3854 22:14:25.794114 ===================================
3855 22:14:25.797248 ===================================
3856 22:14:25.797319 ANA top config
3857 22:14:25.800366 ===================================
3858 22:14:25.803886 DLL_ASYNC_EN = 0
3859 22:14:25.806899 ALL_SLAVE_EN = 1
3860 22:14:25.806999 NEW_RANK_MODE = 1
3861 22:14:25.810331 DLL_IDLE_MODE = 1
3862 22:14:25.813807 LP45_APHY_COMB_EN = 1
3863 22:14:25.816878 TX_ODT_DIS = 1
3864 22:14:25.820669 NEW_8X_MODE = 1
3865 22:14:25.823745 ===================================
3866 22:14:25.826815 ===================================
3867 22:14:25.831009 data_rate = 1200
3868 22:14:25.831107 CKR = 1
3869 22:14:25.833910 DQ_P2S_RATIO = 8
3870 22:14:25.836941 ===================================
3871 22:14:25.840079 CA_P2S_RATIO = 8
3872 22:14:25.843326 DQ_CA_OPEN = 0
3873 22:14:25.846601 DQ_SEMI_OPEN = 0
3874 22:14:25.850234 CA_SEMI_OPEN = 0
3875 22:14:25.850332 CA_FULL_RATE = 0
3876 22:14:25.853442 DQ_CKDIV4_EN = 1
3877 22:14:25.857100 CA_CKDIV4_EN = 1
3878 22:14:25.860020 CA_PREDIV_EN = 0
3879 22:14:25.863063 PH8_DLY = 0
3880 22:14:25.866729 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3881 22:14:25.866830 DQ_AAMCK_DIV = 4
3882 22:14:25.869641 CA_AAMCK_DIV = 4
3883 22:14:25.873333 CA_ADMCK_DIV = 4
3884 22:14:25.876967 DQ_TRACK_CA_EN = 0
3885 22:14:25.879809 CA_PICK = 600
3886 22:14:25.883240 CA_MCKIO = 600
3887 22:14:25.883340 MCKIO_SEMI = 0
3888 22:14:25.886445 PLL_FREQ = 2288
3889 22:14:25.889747 DQ_UI_PI_RATIO = 32
3890 22:14:25.892785 CA_UI_PI_RATIO = 0
3891 22:14:25.896461 ===================================
3892 22:14:25.899386 ===================================
3893 22:14:25.902818 memory_type:LPDDR4
3894 22:14:25.902922 GP_NUM : 10
3895 22:14:25.906520 SRAM_EN : 1
3896 22:14:25.909482 MD32_EN : 0
3897 22:14:25.912709 ===================================
3898 22:14:25.912783 [ANA_INIT] >>>>>>>>>>>>>>
3899 22:14:25.916112 <<<<<< [CONFIGURE PHASE]: ANA_TX
3900 22:14:25.919180 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3901 22:14:25.922327 ===================================
3902 22:14:25.925957 data_rate = 1200,PCW = 0X5800
3903 22:14:25.929074 ===================================
3904 22:14:25.932794 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3905 22:14:25.939081 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3906 22:14:25.945518 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3907 22:14:25.948967 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3908 22:14:25.952600 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3909 22:14:25.955582 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3910 22:14:25.958788 [ANA_INIT] flow start
3911 22:14:25.958884 [ANA_INIT] PLL >>>>>>>>
3912 22:14:25.962392 [ANA_INIT] PLL <<<<<<<<
3913 22:14:25.965574 [ANA_INIT] MIDPI >>>>>>>>
3914 22:14:25.965645 [ANA_INIT] MIDPI <<<<<<<<
3915 22:14:25.969060 [ANA_INIT] DLL >>>>>>>>
3916 22:14:25.972428 [ANA_INIT] flow end
3917 22:14:25.975322 ============ LP4 DIFF to SE enter ============
3918 22:14:25.979230 ============ LP4 DIFF to SE exit ============
3919 22:14:25.981795 [ANA_INIT] <<<<<<<<<<<<<
3920 22:14:25.985150 [Flow] Enable top DCM control >>>>>
3921 22:14:25.988396 [Flow] Enable top DCM control <<<<<
3922 22:14:25.992032 Enable DLL master slave shuffle
3923 22:14:25.995365 ==============================================================
3924 22:14:25.998575 Gating Mode config
3925 22:14:26.005048 ==============================================================
3926 22:14:26.005150 Config description:
3927 22:14:26.014869 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3928 22:14:26.021384 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3929 22:14:26.028265 SELPH_MODE 0: By rank 1: By Phase
3930 22:14:26.031333 ==============================================================
3931 22:14:26.035304 GAT_TRACK_EN = 1
3932 22:14:26.038317 RX_GATING_MODE = 2
3933 22:14:26.041727 RX_GATING_TRACK_MODE = 2
3934 22:14:26.044455 SELPH_MODE = 1
3935 22:14:26.048071 PICG_EARLY_EN = 1
3936 22:14:26.051256 VALID_LAT_VALUE = 1
3937 22:14:26.054678 ==============================================================
3938 22:14:26.058136 Enter into Gating configuration >>>>
3939 22:14:26.061250 Exit from Gating configuration <<<<
3940 22:14:26.064711 Enter into DVFS_PRE_config >>>>>
3941 22:14:26.077921 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3942 22:14:26.081251 Exit from DVFS_PRE_config <<<<<
3943 22:14:26.084906 Enter into PICG configuration >>>>
3944 22:14:26.087903 Exit from PICG configuration <<<<
3945 22:14:26.088003 [RX_INPUT] configuration >>>>>
3946 22:14:26.090921 [RX_INPUT] configuration <<<<<
3947 22:14:26.098205 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3948 22:14:26.101235 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3949 22:14:26.107329 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3950 22:14:26.114054 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3951 22:14:26.120672 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3952 22:14:26.127136 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3953 22:14:26.130577 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3954 22:14:26.134021 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3955 22:14:26.140534 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3956 22:14:26.143526 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3957 22:14:26.147229 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3958 22:14:26.153782 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3959 22:14:26.156930 ===================================
3960 22:14:26.157027 LPDDR4 DRAM CONFIGURATION
3961 22:14:26.160714 ===================================
3962 22:14:26.163613 EX_ROW_EN[0] = 0x0
3963 22:14:26.163712 EX_ROW_EN[1] = 0x0
3964 22:14:26.167200 LP4Y_EN = 0x0
3965 22:14:26.167285 WORK_FSP = 0x0
3966 22:14:26.170092 WL = 0x2
3967 22:14:26.170192 RL = 0x2
3968 22:14:26.173865 BL = 0x2
3969 22:14:26.177058 RPST = 0x0
3970 22:14:26.177145 RD_PRE = 0x0
3971 22:14:26.179914 WR_PRE = 0x1
3972 22:14:26.180025 WR_PST = 0x0
3973 22:14:26.183265 DBI_WR = 0x0
3974 22:14:26.183350 DBI_RD = 0x0
3975 22:14:26.186846 OTF = 0x1
3976 22:14:26.190844 ===================================
3977 22:14:26.193483 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3978 22:14:26.196989 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3979 22:14:26.200404 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3980 22:14:26.203076 ===================================
3981 22:14:26.206538 LPDDR4 DRAM CONFIGURATION
3982 22:14:26.209997 ===================================
3983 22:14:26.213123 EX_ROW_EN[0] = 0x10
3984 22:14:26.213211 EX_ROW_EN[1] = 0x0
3985 22:14:26.216431 LP4Y_EN = 0x0
3986 22:14:26.216593 WORK_FSP = 0x0
3987 22:14:26.220076 WL = 0x2
3988 22:14:26.222985 RL = 0x2
3989 22:14:26.223126 BL = 0x2
3990 22:14:26.226145 RPST = 0x0
3991 22:14:26.226255 RD_PRE = 0x0
3992 22:14:26.230098 WR_PRE = 0x1
3993 22:14:26.230206 WR_PST = 0x0
3994 22:14:26.233507 DBI_WR = 0x0
3995 22:14:26.233645 DBI_RD = 0x0
3996 22:14:26.236238 OTF = 0x1
3997 22:14:26.239711 ===================================
3998 22:14:26.246126 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3999 22:14:26.249368 nWR fixed to 30
4000 22:14:26.249457 [ModeRegInit_LP4] CH0 RK0
4001 22:14:26.252704 [ModeRegInit_LP4] CH0 RK1
4002 22:14:26.256068 [ModeRegInit_LP4] CH1 RK0
4003 22:14:26.256148 [ModeRegInit_LP4] CH1 RK1
4004 22:14:26.259206 match AC timing 17
4005 22:14:26.263027 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
4006 22:14:26.269616 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
4007 22:14:26.273400 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
4008 22:14:26.275860 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
4009 22:14:26.282277 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
4010 22:14:26.282359 ==
4011 22:14:26.285845 Dram Type= 6, Freq= 0, CH_0, rank 0
4012 22:14:26.288969 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4013 22:14:26.289056 ==
4014 22:14:26.295582 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4015 22:14:26.302280 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4016 22:14:26.305584 [CA 0] Center 36 (6~66) winsize 61
4017 22:14:26.308764 [CA 1] Center 36 (6~66) winsize 61
4018 22:14:26.311905 [CA 2] Center 34 (4~65) winsize 62
4019 22:14:26.315353 [CA 3] Center 34 (4~65) winsize 62
4020 22:14:26.319155 [CA 4] Center 33 (3~64) winsize 62
4021 22:14:26.322616 [CA 5] Center 33 (3~64) winsize 62
4022 22:14:26.322700
4023 22:14:26.325275 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4024 22:14:26.325365
4025 22:14:26.328885 [CATrainingPosCal] consider 1 rank data
4026 22:14:26.331884 u2DelayCellTimex100 = 270/100 ps
4027 22:14:26.335310 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4028 22:14:26.338405 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4029 22:14:26.342010 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4030 22:14:26.345635 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4031 22:14:26.348694 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4032 22:14:26.351878 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4033 22:14:26.351998
4034 22:14:26.358302 CA PerBit enable=1, Macro0, CA PI delay=33
4035 22:14:26.358409
4036 22:14:26.361827 [CBTSetCACLKResult] CA Dly = 33
4037 22:14:26.361927 CS Dly: 5 (0~36)
4038 22:14:26.362016 ==
4039 22:14:26.364870 Dram Type= 6, Freq= 0, CH_0, rank 1
4040 22:14:26.368472 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4041 22:14:26.368580 ==
4042 22:14:26.374739 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4043 22:14:26.381534 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4044 22:14:26.384799 [CA 0] Center 35 (5~66) winsize 62
4045 22:14:26.388362 [CA 1] Center 36 (6~66) winsize 61
4046 22:14:26.391555 [CA 2] Center 33 (3~64) winsize 62
4047 22:14:26.394957 [CA 3] Center 33 (3~64) winsize 62
4048 22:14:26.398415 [CA 4] Center 33 (3~64) winsize 62
4049 22:14:26.401890 [CA 5] Center 33 (2~64) winsize 63
4050 22:14:26.401972
4051 22:14:26.404650 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4052 22:14:26.404751
4053 22:14:26.408053 [CATrainingPosCal] consider 2 rank data
4054 22:14:26.411146 u2DelayCellTimex100 = 270/100 ps
4055 22:14:26.414706 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4056 22:14:26.417679 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4057 22:14:26.421099 CA2 delay=34 (4~64),Diff = 1 PI (9 cell)
4058 22:14:26.424776 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4059 22:14:26.431332 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4060 22:14:26.434664 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4061 22:14:26.434770
4062 22:14:26.437491 CA PerBit enable=1, Macro0, CA PI delay=33
4063 22:14:26.437574
4064 22:14:26.440818 [CBTSetCACLKResult] CA Dly = 33
4065 22:14:26.440901 CS Dly: 5 (0~37)
4066 22:14:26.440966
4067 22:14:26.444433 ----->DramcWriteLeveling(PI) begin...
4068 22:14:26.444571 ==
4069 22:14:26.447925 Dram Type= 6, Freq= 0, CH_0, rank 0
4070 22:14:26.453939 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4071 22:14:26.454047 ==
4072 22:14:26.457369 Write leveling (Byte 0): 32 => 32
4073 22:14:26.460814 Write leveling (Byte 1): 28 => 28
4074 22:14:26.460922 DramcWriteLeveling(PI) end<-----
4075 22:14:26.461050
4076 22:14:26.464010 ==
4077 22:14:26.467379 Dram Type= 6, Freq= 0, CH_0, rank 0
4078 22:14:26.471002 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4079 22:14:26.471157 ==
4080 22:14:26.474410 [Gating] SW mode calibration
4081 22:14:26.480435 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4082 22:14:26.483556 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4083 22:14:26.490455 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4084 22:14:26.493558 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4085 22:14:26.496848 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4086 22:14:26.503679 0 9 12 | B1->B0 | 3434 3333 | 0 0 | (0 1) (0 0)
4087 22:14:26.507199 0 9 16 | B1->B0 | 3030 2323 | 1 0 | (1 1) (0 0)
4088 22:14:26.509985 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4089 22:14:26.516739 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4090 22:14:26.520361 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4091 22:14:26.523148 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4092 22:14:26.530079 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4093 22:14:26.532930 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4094 22:14:26.536262 0 10 12 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
4095 22:14:26.543030 0 10 16 | B1->B0 | 3131 4646 | 1 0 | (0 0) (0 0)
4096 22:14:26.546126 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4097 22:14:26.549690 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4098 22:14:26.556005 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4099 22:14:26.559961 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4100 22:14:26.562735 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4101 22:14:26.569404 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4102 22:14:26.572696 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4103 22:14:26.575972 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4104 22:14:26.583025 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4105 22:14:26.585990 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4106 22:14:26.589217 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4107 22:14:26.595791 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4108 22:14:26.599810 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4109 22:14:26.602758 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4110 22:14:26.609317 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4111 22:14:26.612263 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4112 22:14:26.615451 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4113 22:14:26.622583 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4114 22:14:26.625733 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4115 22:14:26.629558 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4116 22:14:26.635299 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4117 22:14:26.638722 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4118 22:14:26.642309 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4119 22:14:26.648493 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4120 22:14:26.652054 Total UI for P1: 0, mck2ui 16
4121 22:14:26.655386 best dqsien dly found for B0: ( 0, 13, 12)
4122 22:14:26.658559 Total UI for P1: 0, mck2ui 16
4123 22:14:26.662348 best dqsien dly found for B1: ( 0, 13, 12)
4124 22:14:26.665477 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4125 22:14:26.668552 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4126 22:14:26.668640
4127 22:14:26.672156 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4128 22:14:26.675043 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4129 22:14:26.678631 [Gating] SW calibration Done
4130 22:14:26.678703 ==
4131 22:14:26.681573 Dram Type= 6, Freq= 0, CH_0, rank 0
4132 22:14:26.685285 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4133 22:14:26.685388 ==
4134 22:14:26.688304 RX Vref Scan: 0
4135 22:14:26.688378
4136 22:14:26.691747 RX Vref 0 -> 0, step: 1
4137 22:14:26.691825
4138 22:14:26.691887 RX Delay -230 -> 252, step: 16
4139 22:14:26.698180 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4140 22:14:26.701482 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4141 22:14:26.705128 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4142 22:14:26.708313 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4143 22:14:26.714684 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4144 22:14:26.717850 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4145 22:14:26.721220 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4146 22:14:26.724820 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4147 22:14:26.731761 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4148 22:14:26.734990 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4149 22:14:26.737876 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4150 22:14:26.741336 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4151 22:14:26.747476 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4152 22:14:26.751130 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4153 22:14:26.754854 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4154 22:14:26.757768 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4155 22:14:26.757856 ==
4156 22:14:26.761034 Dram Type= 6, Freq= 0, CH_0, rank 0
4157 22:14:26.767967 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4158 22:14:26.768089 ==
4159 22:14:26.768183 DQS Delay:
4160 22:14:26.768245 DQS0 = 0, DQS1 = 0
4161 22:14:26.770849 DQM Delay:
4162 22:14:26.770933 DQM0 = 43, DQM1 = 29
4163 22:14:26.774253 DQ Delay:
4164 22:14:26.777307 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4165 22:14:26.780761 DQ4 =41, DQ5 =33, DQ6 =57, DQ7 =49
4166 22:14:26.784046 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4167 22:14:26.787172 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =33
4168 22:14:26.787278
4169 22:14:26.787358
4170 22:14:26.787419 ==
4171 22:14:26.790492 Dram Type= 6, Freq= 0, CH_0, rank 0
4172 22:14:26.794000 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4173 22:14:26.794084 ==
4174 22:14:26.794150
4175 22:14:26.794210
4176 22:14:26.798078 TX Vref Scan disable
4177 22:14:26.800830 == TX Byte 0 ==
4178 22:14:26.803987 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4179 22:14:26.807575 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4180 22:14:26.810785 == TX Byte 1 ==
4181 22:14:26.813717 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4182 22:14:26.817400 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4183 22:14:26.817529 ==
4184 22:14:26.820260 Dram Type= 6, Freq= 0, CH_0, rank 0
4185 22:14:26.823880 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4186 22:14:26.823962 ==
4187 22:14:26.827379
4188 22:14:26.827451
4189 22:14:26.827516 TX Vref Scan disable
4190 22:14:26.830903 == TX Byte 0 ==
4191 22:14:26.833870 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4192 22:14:26.840834 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4193 22:14:26.840920 == TX Byte 1 ==
4194 22:14:26.843659 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4195 22:14:26.850666 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4196 22:14:26.850746
4197 22:14:26.850807 [DATLAT]
4198 22:14:26.850864 Freq=600, CH0 RK0
4199 22:14:26.850926
4200 22:14:26.853833 DATLAT Default: 0x9
4201 22:14:26.856904 0, 0xFFFF, sum = 0
4202 22:14:26.856974 1, 0xFFFF, sum = 0
4203 22:14:26.860380 2, 0xFFFF, sum = 0
4204 22:14:26.860449 3, 0xFFFF, sum = 0
4205 22:14:26.863554 4, 0xFFFF, sum = 0
4206 22:14:26.863632 5, 0xFFFF, sum = 0
4207 22:14:26.866755 6, 0xFFFF, sum = 0
4208 22:14:26.866833 7, 0xFFFF, sum = 0
4209 22:14:26.870320 8, 0x0, sum = 1
4210 22:14:26.870393 9, 0x0, sum = 2
4211 22:14:26.873573 10, 0x0, sum = 3
4212 22:14:26.873650 11, 0x0, sum = 4
4213 22:14:26.873711 best_step = 9
4214 22:14:26.873767
4215 22:14:26.876750 ==
4216 22:14:26.880204 Dram Type= 6, Freq= 0, CH_0, rank 0
4217 22:14:26.883550 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4218 22:14:26.883627 ==
4219 22:14:26.883688 RX Vref Scan: 1
4220 22:14:26.883753
4221 22:14:26.886792 RX Vref 0 -> 0, step: 1
4222 22:14:26.886896
4223 22:14:26.889907 RX Delay -195 -> 252, step: 8
4224 22:14:26.889981
4225 22:14:26.893585 Set Vref, RX VrefLevel [Byte0]: 59
4226 22:14:26.897038 [Byte1]: 49
4227 22:14:26.897116
4228 22:14:26.900111 Final RX Vref Byte 0 = 59 to rank0
4229 22:14:26.903218 Final RX Vref Byte 1 = 49 to rank0
4230 22:14:26.906718 Final RX Vref Byte 0 = 59 to rank1
4231 22:14:26.909687 Final RX Vref Byte 1 = 49 to rank1==
4232 22:14:26.913047 Dram Type= 6, Freq= 0, CH_0, rank 0
4233 22:14:26.919683 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4234 22:14:26.919760 ==
4235 22:14:26.919822 DQS Delay:
4236 22:14:26.919888 DQS0 = 0, DQS1 = 0
4237 22:14:26.923108 DQM Delay:
4238 22:14:26.923180 DQM0 = 43, DQM1 = 32
4239 22:14:26.926791 DQ Delay:
4240 22:14:26.929928 DQ0 =44, DQ1 =44, DQ2 =40, DQ3 =40
4241 22:14:26.933239 DQ4 =44, DQ5 =32, DQ6 =52, DQ7 =48
4242 22:14:26.935922 DQ8 =24, DQ9 =20, DQ10 =32, DQ11 =24
4243 22:14:26.939699 DQ12 =36, DQ13 =36, DQ14 =44, DQ15 =40
4244 22:14:26.939772
4245 22:14:26.939832
4246 22:14:26.945921 [DQSOSCAuto] RK0, (LSB)MR18= 0x6940, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 390 ps
4247 22:14:26.949217 CH0 RK0: MR19=808, MR18=6940
4248 22:14:26.955630 CH0_RK0: MR19=0x808, MR18=0x6940, DQSOSC=390, MR23=63, INC=172, DEC=114
4249 22:14:26.955728
4250 22:14:26.959289 ----->DramcWriteLeveling(PI) begin...
4251 22:14:26.959360 ==
4252 22:14:26.962397 Dram Type= 6, Freq= 0, CH_0, rank 1
4253 22:14:26.965800 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4254 22:14:26.965885 ==
4255 22:14:26.969093 Write leveling (Byte 0): 34 => 34
4256 22:14:26.972174 Write leveling (Byte 1): 31 => 31
4257 22:14:26.975785 DramcWriteLeveling(PI) end<-----
4258 22:14:26.975865
4259 22:14:26.975928 ==
4260 22:14:26.978929 Dram Type= 6, Freq= 0, CH_0, rank 1
4261 22:14:26.982422 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4262 22:14:26.985828 ==
4263 22:14:26.985908 [Gating] SW mode calibration
4264 22:14:26.995270 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4265 22:14:26.998699 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4266 22:14:27.001793 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4267 22:14:27.008588 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4268 22:14:27.011705 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4269 22:14:27.015138 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
4270 22:14:27.021505 0 9 16 | B1->B0 | 2f2f 2525 | 0 0 | (1 1) (0 0)
4271 22:14:27.025612 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4272 22:14:27.028151 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4273 22:14:27.034556 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4274 22:14:27.038012 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4275 22:14:27.041335 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4276 22:14:27.047908 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4277 22:14:27.051321 0 10 12 | B1->B0 | 2e2e 2c2b | 0 1 | (0 0) (0 0)
4278 22:14:27.054687 0 10 16 | B1->B0 | 3a3a 4646 | 1 0 | (0 0) (0 0)
4279 22:14:27.061530 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4280 22:14:27.064831 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4281 22:14:27.068146 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4282 22:14:27.074734 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4283 22:14:27.078277 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4284 22:14:27.080974 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4285 22:14:27.087685 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4286 22:14:27.090647 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4287 22:14:27.094090 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4288 22:14:27.100539 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4289 22:14:27.104228 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4290 22:14:27.107120 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4291 22:14:27.113884 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4292 22:14:27.117346 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4293 22:14:27.120301 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4294 22:14:27.127343 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4295 22:14:27.130686 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4296 22:14:27.133610 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4297 22:14:27.140455 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4298 22:14:27.143766 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4299 22:14:27.146658 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4300 22:14:27.153602 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4301 22:14:27.156533 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4302 22:14:27.159990 Total UI for P1: 0, mck2ui 16
4303 22:14:27.163549 best dqsien dly found for B0: ( 0, 13, 10)
4304 22:14:27.166590 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4305 22:14:27.173672 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4306 22:14:27.176397 Total UI for P1: 0, mck2ui 16
4307 22:14:27.179517 best dqsien dly found for B1: ( 0, 13, 14)
4308 22:14:27.183086 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4309 22:14:27.185998 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4310 22:14:27.186083
4311 22:14:27.189917 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4312 22:14:27.192625 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4313 22:14:27.196278 [Gating] SW calibration Done
4314 22:14:27.196362 ==
4315 22:14:27.199450 Dram Type= 6, Freq= 0, CH_0, rank 1
4316 22:14:27.202477 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4317 22:14:27.202562 ==
4318 22:14:27.206008 RX Vref Scan: 0
4319 22:14:27.206092
4320 22:14:27.209312 RX Vref 0 -> 0, step: 1
4321 22:14:27.209394
4322 22:14:27.212322 RX Delay -230 -> 252, step: 16
4323 22:14:27.216013 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4324 22:14:27.218899 iDelay=218, Bit 1, Center 49 (-118 ~ 217) 336
4325 22:14:27.222613 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4326 22:14:27.228877 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4327 22:14:27.232162 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4328 22:14:27.235631 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4329 22:14:27.239371 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4330 22:14:27.242260 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4331 22:14:27.249143 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4332 22:14:27.251929 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4333 22:14:27.255239 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4334 22:14:27.258548 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4335 22:14:27.265389 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4336 22:14:27.268416 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4337 22:14:27.272234 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4338 22:14:27.275751 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4339 22:14:27.275833 ==
4340 22:14:27.278737 Dram Type= 6, Freq= 0, CH_0, rank 1
4341 22:14:27.285045 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4342 22:14:27.285128 ==
4343 22:14:27.285192 DQS Delay:
4344 22:14:27.288824 DQS0 = 0, DQS1 = 0
4345 22:14:27.288905 DQM Delay:
4346 22:14:27.291536 DQM0 = 42, DQM1 = 34
4347 22:14:27.291616 DQ Delay:
4348 22:14:27.294913 DQ0 =41, DQ1 =49, DQ2 =41, DQ3 =33
4349 22:14:27.298603 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4350 22:14:27.301741 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =25
4351 22:14:27.305087 DQ12 =33, DQ13 =49, DQ14 =49, DQ15 =33
4352 22:14:27.305167
4353 22:14:27.305232
4354 22:14:27.305291 ==
4355 22:14:27.308599 Dram Type= 6, Freq= 0, CH_0, rank 1
4356 22:14:27.311336 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4357 22:14:27.311417 ==
4358 22:14:27.311480
4359 22:14:27.311539
4360 22:14:27.315109 TX Vref Scan disable
4361 22:14:27.317852 == TX Byte 0 ==
4362 22:14:27.321881 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4363 22:14:27.324865 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4364 22:14:27.328160 == TX Byte 1 ==
4365 22:14:27.331469 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4366 22:14:27.334556 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4367 22:14:27.334637 ==
4368 22:14:27.338284 Dram Type= 6, Freq= 0, CH_0, rank 1
4369 22:14:27.344367 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4370 22:14:27.344449 ==
4371 22:14:27.344511
4372 22:14:27.344614
4373 22:14:27.344670 TX Vref Scan disable
4374 22:14:27.348734 == TX Byte 0 ==
4375 22:14:27.352526 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4376 22:14:27.355380 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4377 22:14:27.359125 == TX Byte 1 ==
4378 22:14:27.361905 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4379 22:14:27.368916 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4380 22:14:27.369001
4381 22:14:27.369064 [DATLAT]
4382 22:14:27.369124 Freq=600, CH0 RK1
4383 22:14:27.369180
4384 22:14:27.371652 DATLAT Default: 0x9
4385 22:14:27.371731 0, 0xFFFF, sum = 0
4386 22:14:27.375216 1, 0xFFFF, sum = 0
4387 22:14:27.378717 2, 0xFFFF, sum = 0
4388 22:14:27.378798 3, 0xFFFF, sum = 0
4389 22:14:27.381989 4, 0xFFFF, sum = 0
4390 22:14:27.382070 5, 0xFFFF, sum = 0
4391 22:14:27.385168 6, 0xFFFF, sum = 0
4392 22:14:27.385249 7, 0xFFFF, sum = 0
4393 22:14:27.388452 8, 0x0, sum = 1
4394 22:14:27.388541 9, 0x0, sum = 2
4395 22:14:27.391736 10, 0x0, sum = 3
4396 22:14:27.391817 11, 0x0, sum = 4
4397 22:14:27.391881 best_step = 9
4398 22:14:27.391940
4399 22:14:27.395057 ==
4400 22:14:27.395137 Dram Type= 6, Freq= 0, CH_0, rank 1
4401 22:14:27.401717 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4402 22:14:27.401798 ==
4403 22:14:27.401861 RX Vref Scan: 0
4404 22:14:27.401920
4405 22:14:27.404905 RX Vref 0 -> 0, step: 1
4406 22:14:27.404986
4407 22:14:27.407999 RX Delay -179 -> 252, step: 8
4408 22:14:27.414579 iDelay=205, Bit 0, Center 36 (-115 ~ 188) 304
4409 22:14:27.418178 iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304
4410 22:14:27.422007 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4411 22:14:27.424738 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4412 22:14:27.427869 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4413 22:14:27.434584 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4414 22:14:27.437887 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4415 22:14:27.442017 iDelay=205, Bit 7, Center 52 (-99 ~ 204) 304
4416 22:14:27.444115 iDelay=205, Bit 8, Center 28 (-123 ~ 180) 304
4417 22:14:27.450744 iDelay=205, Bit 9, Center 24 (-123 ~ 172) 296
4418 22:14:27.454420 iDelay=205, Bit 10, Center 40 (-115 ~ 196) 312
4419 22:14:27.457520 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4420 22:14:27.460809 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4421 22:14:27.467233 iDelay=205, Bit 13, Center 44 (-107 ~ 196) 304
4422 22:14:27.470688 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4423 22:14:27.474150 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4424 22:14:27.474232 ==
4425 22:14:27.477184 Dram Type= 6, Freq= 0, CH_0, rank 1
4426 22:14:27.480678 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4427 22:14:27.483786 ==
4428 22:14:27.483868 DQS Delay:
4429 22:14:27.483932 DQS0 = 0, DQS1 = 0
4430 22:14:27.487383 DQM Delay:
4431 22:14:27.487466 DQM0 = 41, DQM1 = 37
4432 22:14:27.490309 DQ Delay:
4433 22:14:27.490391 DQ0 =36, DQ1 =44, DQ2 =36, DQ3 =40
4434 22:14:27.493852 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =52
4435 22:14:27.497456 DQ8 =28, DQ9 =24, DQ10 =40, DQ11 =28
4436 22:14:27.500863 DQ12 =44, DQ13 =44, DQ14 =48, DQ15 =44
4437 22:14:27.500946
4438 22:14:27.503592
4439 22:14:27.510424 [DQSOSCAuto] RK1, (LSB)MR18= 0x5d10, (MSB)MR19= 0x808, tDQSOscB0 = 406 ps tDQSOscB1 = 392 ps
4440 22:14:27.513852 CH0 RK1: MR19=808, MR18=5D10
4441 22:14:27.520282 CH0_RK1: MR19=0x808, MR18=0x5D10, DQSOSC=392, MR23=63, INC=170, DEC=113
4442 22:14:27.524281 [RxdqsGatingPostProcess] freq 600
4443 22:14:27.527026 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4444 22:14:27.530709 Pre-setting of DQS Precalculation
4445 22:14:27.536960 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4446 22:14:27.537044 ==
4447 22:14:27.540002 Dram Type= 6, Freq= 0, CH_1, rank 0
4448 22:14:27.543672 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4449 22:14:27.543754 ==
4450 22:14:27.550027 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4451 22:14:27.553656 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4452 22:14:27.557702 [CA 0] Center 35 (5~66) winsize 62
4453 22:14:27.561087 [CA 1] Center 35 (5~66) winsize 62
4454 22:14:27.564067 [CA 2] Center 34 (3~65) winsize 63
4455 22:14:27.567855 [CA 3] Center 33 (3~64) winsize 62
4456 22:14:27.570898 [CA 4] Center 34 (4~64) winsize 61
4457 22:14:27.574081 [CA 5] Center 33 (3~64) winsize 62
4458 22:14:27.574187
4459 22:14:27.577633 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4460 22:14:27.577738
4461 22:14:27.581308 [CATrainingPosCal] consider 1 rank data
4462 22:14:27.584126 u2DelayCellTimex100 = 270/100 ps
4463 22:14:27.587642 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4464 22:14:27.593820 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4465 22:14:27.597209 CA2 delay=34 (3~65),Diff = 1 PI (9 cell)
4466 22:14:27.600978 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4467 22:14:27.603743 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4468 22:14:27.607358 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4469 22:14:27.607455
4470 22:14:27.610429 CA PerBit enable=1, Macro0, CA PI delay=33
4471 22:14:27.610525
4472 22:14:27.613636 [CBTSetCACLKResult] CA Dly = 33
4473 22:14:27.617239 CS Dly: 4 (0~35)
4474 22:14:27.617348 ==
4475 22:14:27.620726 Dram Type= 6, Freq= 0, CH_1, rank 1
4476 22:14:27.623886 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4477 22:14:27.623959 ==
4478 22:14:27.630792 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4479 22:14:27.633352 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4480 22:14:27.637860 [CA 0] Center 35 (5~66) winsize 62
4481 22:14:27.641383 [CA 1] Center 36 (6~66) winsize 61
4482 22:14:27.644289 [CA 2] Center 34 (4~65) winsize 62
4483 22:14:27.647544 [CA 3] Center 34 (3~65) winsize 63
4484 22:14:27.650992 [CA 4] Center 34 (3~65) winsize 63
4485 22:14:27.654260 [CA 5] Center 34 (3~65) winsize 63
4486 22:14:27.654333
4487 22:14:27.657315 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4488 22:14:27.657388
4489 22:14:27.661148 [CATrainingPosCal] consider 2 rank data
4490 22:14:27.663860 u2DelayCellTimex100 = 270/100 ps
4491 22:14:27.667429 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4492 22:14:27.673840 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4493 22:14:27.677378 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4494 22:14:27.680338 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4495 22:14:27.683842 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4496 22:14:27.687098 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4497 22:14:27.687180
4498 22:14:27.690472 CA PerBit enable=1, Macro0, CA PI delay=33
4499 22:14:27.690554
4500 22:14:27.694163 [CBTSetCACLKResult] CA Dly = 33
4501 22:14:27.696885 CS Dly: 4 (0~36)
4502 22:14:27.696966
4503 22:14:27.700218 ----->DramcWriteLeveling(PI) begin...
4504 22:14:27.700300 ==
4505 22:14:27.703875 Dram Type= 6, Freq= 0, CH_1, rank 0
4506 22:14:27.707105 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4507 22:14:27.707188 ==
4508 22:14:27.710638 Write leveling (Byte 0): 29 => 29
4509 22:14:27.713633 Write leveling (Byte 1): 31 => 31
4510 22:14:27.717007 DramcWriteLeveling(PI) end<-----
4511 22:14:27.717088
4512 22:14:27.717152 ==
4513 22:14:27.720285 Dram Type= 6, Freq= 0, CH_1, rank 0
4514 22:14:27.723533 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4515 22:14:27.723615 ==
4516 22:14:27.726952 [Gating] SW mode calibration
4517 22:14:27.733343 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4518 22:14:27.740232 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4519 22:14:27.743254 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4520 22:14:27.746288 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4521 22:14:27.753488 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
4522 22:14:27.756377 0 9 12 | B1->B0 | 3232 2e2e | 1 1 | (1 1) (1 1)
4523 22:14:27.759543 0 9 16 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
4524 22:14:27.766257 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4525 22:14:27.769086 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4526 22:14:27.775861 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4527 22:14:27.779349 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4528 22:14:27.782264 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4529 22:14:27.788873 0 10 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
4530 22:14:27.792099 0 10 12 | B1->B0 | 2525 3a3a | 0 0 | (0 0) (0 0)
4531 22:14:27.795987 0 10 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
4532 22:14:27.801796 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4533 22:14:27.805521 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4534 22:14:27.808568 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4535 22:14:27.815378 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4536 22:14:27.818822 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4537 22:14:27.822016 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4538 22:14:27.828197 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4539 22:14:27.831760 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4540 22:14:27.834996 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4541 22:14:27.841507 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4542 22:14:27.844432 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4543 22:14:27.848699 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4544 22:14:27.854340 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4545 22:14:27.857852 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4546 22:14:27.861274 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4547 22:14:27.867669 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4548 22:14:27.870862 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4549 22:14:27.874126 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4550 22:14:27.881035 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4551 22:14:27.884082 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4552 22:14:27.887226 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4553 22:14:27.894251 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4554 22:14:27.897182 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4555 22:14:27.900866 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4556 22:14:27.904175 Total UI for P1: 0, mck2ui 16
4557 22:14:27.907224 best dqsien dly found for B0: ( 0, 13, 12)
4558 22:14:27.910634 Total UI for P1: 0, mck2ui 16
4559 22:14:27.913944 best dqsien dly found for B1: ( 0, 13, 14)
4560 22:14:27.917262 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4561 22:14:27.920723 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4562 22:14:27.920804
4563 22:14:27.926952 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4564 22:14:27.930307 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4565 22:14:27.933972 [Gating] SW calibration Done
4566 22:14:27.934044 ==
4567 22:14:27.937005 Dram Type= 6, Freq= 0, CH_1, rank 0
4568 22:14:27.940090 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4569 22:14:27.940170 ==
4570 22:14:27.940234 RX Vref Scan: 0
4571 22:14:27.940293
4572 22:14:27.943519 RX Vref 0 -> 0, step: 1
4573 22:14:27.943598
4574 22:14:27.946832 RX Delay -230 -> 252, step: 16
4575 22:14:27.950181 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4576 22:14:27.956422 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4577 22:14:27.959835 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4578 22:14:27.963283 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4579 22:14:27.966772 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4580 22:14:27.970169 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4581 22:14:27.976922 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4582 22:14:27.979653 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4583 22:14:27.982980 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4584 22:14:27.985989 iDelay=218, Bit 9, Center 33 (-134 ~ 201) 336
4585 22:14:27.992733 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4586 22:14:27.996301 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4587 22:14:27.999323 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4588 22:14:28.002732 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4589 22:14:28.009398 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4590 22:14:28.012496 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4591 22:14:28.012575 ==
4592 22:14:28.015743 Dram Type= 6, Freq= 0, CH_1, rank 0
4593 22:14:28.019179 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4594 22:14:28.019247 ==
4595 22:14:28.022576 DQS Delay:
4596 22:14:28.022644 DQS0 = 0, DQS1 = 0
4597 22:14:28.022703 DQM Delay:
4598 22:14:28.025963 DQM0 = 46, DQM1 = 39
4599 22:14:28.026034 DQ Delay:
4600 22:14:28.028926 DQ0 =49, DQ1 =41, DQ2 =41, DQ3 =41
4601 22:14:28.033161 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4602 22:14:28.035763 DQ8 =25, DQ9 =33, DQ10 =33, DQ11 =25
4603 22:14:28.039296 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4604 22:14:28.039374
4605 22:14:28.039437
4606 22:14:28.039495 ==
4607 22:14:28.042485 Dram Type= 6, Freq= 0, CH_1, rank 0
4608 22:14:28.048768 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4609 22:14:28.048844 ==
4610 22:14:28.048910
4611 22:14:28.048969
4612 22:14:28.052192 TX Vref Scan disable
4613 22:14:28.052260 == TX Byte 0 ==
4614 22:14:28.055942 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4615 22:14:28.062100 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4616 22:14:28.062175 == TX Byte 1 ==
4617 22:14:28.065792 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4618 22:14:28.072166 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4619 22:14:28.072245 ==
4620 22:14:28.075432 Dram Type= 6, Freq= 0, CH_1, rank 0
4621 22:14:28.078505 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4622 22:14:28.078578 ==
4623 22:14:28.078638
4624 22:14:28.078695
4625 22:14:28.081907 TX Vref Scan disable
4626 22:14:28.085272 == TX Byte 0 ==
4627 22:14:28.088442 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4628 22:14:28.091788 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4629 22:14:28.095386 == TX Byte 1 ==
4630 22:14:28.098335 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4631 22:14:28.101709 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4632 22:14:28.101791
4633 22:14:28.105416 [DATLAT]
4634 22:14:28.105498 Freq=600, CH1 RK0
4635 22:14:28.105563
4636 22:14:28.108415 DATLAT Default: 0x9
4637 22:14:28.108497 0, 0xFFFF, sum = 0
4638 22:14:28.111914 1, 0xFFFF, sum = 0
4639 22:14:28.111997 2, 0xFFFF, sum = 0
4640 22:14:28.115039 3, 0xFFFF, sum = 0
4641 22:14:28.115122 4, 0xFFFF, sum = 0
4642 22:14:28.118799 5, 0xFFFF, sum = 0
4643 22:14:28.118882 6, 0xFFFF, sum = 0
4644 22:14:28.121542 7, 0xFFFF, sum = 0
4645 22:14:28.121625 8, 0x0, sum = 1
4646 22:14:28.125475 9, 0x0, sum = 2
4647 22:14:28.125558 10, 0x0, sum = 3
4648 22:14:28.128317 11, 0x0, sum = 4
4649 22:14:28.128399 best_step = 9
4650 22:14:28.128464
4651 22:14:28.128532 ==
4652 22:14:28.131317 Dram Type= 6, Freq= 0, CH_1, rank 0
4653 22:14:28.138320 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4654 22:14:28.138402 ==
4655 22:14:28.138467 RX Vref Scan: 1
4656 22:14:28.138527
4657 22:14:28.141591 RX Vref 0 -> 0, step: 1
4658 22:14:28.141674
4659 22:14:28.144922 RX Delay -179 -> 252, step: 8
4660 22:14:28.145004
4661 22:14:28.147884 Set Vref, RX VrefLevel [Byte0]: 48
4662 22:14:28.151601 [Byte1]: 58
4663 22:14:28.151683
4664 22:14:28.154664 Final RX Vref Byte 0 = 48 to rank0
4665 22:14:28.158224 Final RX Vref Byte 1 = 58 to rank0
4666 22:14:28.161429 Final RX Vref Byte 0 = 48 to rank1
4667 22:14:28.164747 Final RX Vref Byte 1 = 58 to rank1==
4668 22:14:28.167922 Dram Type= 6, Freq= 0, CH_1, rank 0
4669 22:14:28.171305 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4670 22:14:28.171388 ==
4671 22:14:28.174550 DQS Delay:
4672 22:14:28.174631 DQS0 = 0, DQS1 = 0
4673 22:14:28.174696 DQM Delay:
4674 22:14:28.177945 DQM0 = 48, DQM1 = 37
4675 22:14:28.178027 DQ Delay:
4676 22:14:28.181067 DQ0 =56, DQ1 =44, DQ2 =40, DQ3 =44
4677 22:14:28.185303 DQ4 =44, DQ5 =56, DQ6 =60, DQ7 =44
4678 22:14:28.188066 DQ8 =24, DQ9 =24, DQ10 =40, DQ11 =28
4679 22:14:28.191112 DQ12 =44, DQ13 =44, DQ14 =44, DQ15 =48
4680 22:14:28.191194
4681 22:14:28.191288
4682 22:14:28.201164 [DQSOSCAuto] RK0, (LSB)MR18= 0x5136, (MSB)MR19= 0x808, tDQSOscB0 = 399 ps tDQSOscB1 = 394 ps
4683 22:14:28.204157 CH1 RK0: MR19=808, MR18=5136
4684 22:14:28.207940 CH1_RK0: MR19=0x808, MR18=0x5136, DQSOSC=394, MR23=63, INC=168, DEC=112
4685 22:14:28.210573
4686 22:14:28.214238 ----->DramcWriteLeveling(PI) begin...
4687 22:14:28.214321 ==
4688 22:14:28.217448 Dram Type= 6, Freq= 0, CH_1, rank 1
4689 22:14:28.220628 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4690 22:14:28.220710 ==
4691 22:14:28.223937 Write leveling (Byte 0): 30 => 30
4692 22:14:28.227174 Write leveling (Byte 1): 30 => 30
4693 22:14:28.231037 DramcWriteLeveling(PI) end<-----
4694 22:14:28.231119
4695 22:14:28.231183 ==
4696 22:14:28.233848 Dram Type= 6, Freq= 0, CH_1, rank 1
4697 22:14:28.237112 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4698 22:14:28.237196 ==
4699 22:14:28.240390 [Gating] SW mode calibration
4700 22:14:28.247301 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4701 22:14:28.253718 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4702 22:14:28.257648 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4703 22:14:28.260609 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4704 22:14:28.267147 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4705 22:14:28.269967 0 9 12 | B1->B0 | 2f2f 3131 | 0 0 | (0 1) (0 1)
4706 22:14:28.273519 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4707 22:14:28.280481 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4708 22:14:28.283572 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4709 22:14:28.286601 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4710 22:14:28.293631 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4711 22:14:28.296728 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4712 22:14:28.299881 0 10 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4713 22:14:28.306602 0 10 12 | B1->B0 | 3838 2f2f | 0 0 | (0 0) (0 0)
4714 22:14:28.310206 0 10 16 | B1->B0 | 4646 3f3f | 0 0 | (0 0) (0 0)
4715 22:14:28.313281 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4716 22:14:28.319745 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4717 22:14:28.323277 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4718 22:14:28.326508 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4719 22:14:28.332799 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4720 22:14:28.336285 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4721 22:14:28.339732 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4722 22:14:28.345888 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4723 22:14:28.349351 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4724 22:14:28.352859 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4725 22:14:28.359688 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4726 22:14:28.362482 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4727 22:14:28.365795 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4728 22:14:28.372569 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4729 22:14:28.376060 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4730 22:14:28.379172 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4731 22:14:28.385801 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4732 22:14:28.389186 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4733 22:14:28.393174 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4734 22:14:28.399310 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4735 22:14:28.402228 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4736 22:14:28.405564 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4737 22:14:28.412419 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4738 22:14:28.415381 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4739 22:14:28.418794 Total UI for P1: 0, mck2ui 16
4740 22:14:28.422268 best dqsien dly found for B1: ( 0, 13, 12)
4741 22:14:28.425671 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4742 22:14:28.428960 Total UI for P1: 0, mck2ui 16
4743 22:14:28.432474 best dqsien dly found for B0: ( 0, 13, 16)
4744 22:14:28.435348 best DQS0 dly(MCK, UI, PI) = (0, 13, 16)
4745 22:14:28.438710 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4746 22:14:28.438790
4747 22:14:28.444870 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 16)
4748 22:14:28.448550 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4749 22:14:28.448644 [Gating] SW calibration Done
4750 22:14:28.452048 ==
4751 22:14:28.455343 Dram Type= 6, Freq= 0, CH_1, rank 1
4752 22:14:28.458648 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4753 22:14:28.458729 ==
4754 22:14:28.458792 RX Vref Scan: 0
4755 22:14:28.458851
4756 22:14:28.461570 RX Vref 0 -> 0, step: 1
4757 22:14:28.461650
4758 22:14:28.465285 RX Delay -230 -> 252, step: 16
4759 22:14:28.468469 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4760 22:14:28.471798 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4761 22:14:28.478104 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4762 22:14:28.482310 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4763 22:14:28.484789 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4764 22:14:28.488646 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4765 22:14:28.492126 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4766 22:14:28.498225 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4767 22:14:28.501601 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4768 22:14:28.504897 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4769 22:14:28.508428 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4770 22:14:28.514625 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4771 22:14:28.518149 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4772 22:14:28.521590 iDelay=218, Bit 13, Center 41 (-134 ~ 217) 352
4773 22:14:28.524716 iDelay=218, Bit 14, Center 41 (-134 ~ 217) 352
4774 22:14:28.531189 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4775 22:14:28.531271 ==
4776 22:14:28.534413 Dram Type= 6, Freq= 0, CH_1, rank 1
4777 22:14:28.538278 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4778 22:14:28.538394 ==
4779 22:14:28.538459 DQS Delay:
4780 22:14:28.541666 DQS0 = 0, DQS1 = 0
4781 22:14:28.541747 DQM Delay:
4782 22:14:28.544587 DQM0 = 43, DQM1 = 36
4783 22:14:28.544668 DQ Delay:
4784 22:14:28.547607 DQ0 =49, DQ1 =41, DQ2 =25, DQ3 =41
4785 22:14:28.551192 DQ4 =33, DQ5 =57, DQ6 =57, DQ7 =41
4786 22:14:28.554363 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =33
4787 22:14:28.557649 DQ12 =49, DQ13 =41, DQ14 =41, DQ15 =49
4788 22:14:28.557730
4789 22:14:28.557794
4790 22:14:28.557854 ==
4791 22:14:28.561288 Dram Type= 6, Freq= 0, CH_1, rank 1
4792 22:14:28.564389 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4793 22:14:28.567623 ==
4794 22:14:28.567730
4795 22:14:28.567822
4796 22:14:28.567897 TX Vref Scan disable
4797 22:14:28.571177 == TX Byte 0 ==
4798 22:14:28.574163 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4799 22:14:28.577506 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4800 22:14:28.580767 == TX Byte 1 ==
4801 22:14:28.584253 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4802 22:14:28.591029 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4803 22:14:28.591110 ==
4804 22:14:28.593851 Dram Type= 6, Freq= 0, CH_1, rank 1
4805 22:14:28.597122 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4806 22:14:28.597204 ==
4807 22:14:28.597268
4808 22:14:28.597329
4809 22:14:28.600882 TX Vref Scan disable
4810 22:14:28.604683 == TX Byte 0 ==
4811 22:14:28.607373 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4812 22:14:28.610732 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4813 22:14:28.613719 == TX Byte 1 ==
4814 22:14:28.617114 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4815 22:14:28.620505 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4816 22:14:28.620624
4817 22:14:28.620688 [DATLAT]
4818 22:14:28.623643 Freq=600, CH1 RK1
4819 22:14:28.623724
4820 22:14:28.627223 DATLAT Default: 0x9
4821 22:14:28.627308 0, 0xFFFF, sum = 0
4822 22:14:28.630217 1, 0xFFFF, sum = 0
4823 22:14:28.630299 2, 0xFFFF, sum = 0
4824 22:14:28.633826 3, 0xFFFF, sum = 0
4825 22:14:28.633913 4, 0xFFFF, sum = 0
4826 22:14:28.637197 5, 0xFFFF, sum = 0
4827 22:14:28.637326 6, 0xFFFF, sum = 0
4828 22:14:28.640238 7, 0xFFFF, sum = 0
4829 22:14:28.640349 8, 0x0, sum = 1
4830 22:14:28.643259 9, 0x0, sum = 2
4831 22:14:28.643342 10, 0x0, sum = 3
4832 22:14:28.646738 11, 0x0, sum = 4
4833 22:14:28.646820 best_step = 9
4834 22:14:28.646884
4835 22:14:28.646943 ==
4836 22:14:28.649858 Dram Type= 6, Freq= 0, CH_1, rank 1
4837 22:14:28.653317 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4838 22:14:28.653399 ==
4839 22:14:28.656903 RX Vref Scan: 0
4840 22:14:28.656984
4841 22:14:28.660034 RX Vref 0 -> 0, step: 1
4842 22:14:28.660115
4843 22:14:28.660179 RX Delay -195 -> 252, step: 8
4844 22:14:28.667905 iDelay=213, Bit 0, Center 48 (-99 ~ 196) 296
4845 22:14:28.671155 iDelay=213, Bit 1, Center 40 (-107 ~ 188) 296
4846 22:14:28.674519 iDelay=213, Bit 2, Center 32 (-115 ~ 180) 296
4847 22:14:28.678030 iDelay=213, Bit 3, Center 40 (-107 ~ 188) 296
4848 22:14:28.684427 iDelay=213, Bit 4, Center 44 (-107 ~ 196) 304
4849 22:14:28.687631 iDelay=213, Bit 5, Center 56 (-91 ~ 204) 296
4850 22:14:28.691026 iDelay=213, Bit 6, Center 60 (-91 ~ 212) 304
4851 22:14:28.694576 iDelay=213, Bit 7, Center 44 (-107 ~ 196) 304
4852 22:14:28.697536 iDelay=213, Bit 8, Center 24 (-131 ~ 180) 312
4853 22:14:28.704546 iDelay=213, Bit 9, Center 24 (-131 ~ 180) 312
4854 22:14:28.707456 iDelay=213, Bit 10, Center 36 (-123 ~ 196) 320
4855 22:14:28.710652 iDelay=213, Bit 11, Center 24 (-131 ~ 180) 312
4856 22:14:28.714099 iDelay=213, Bit 12, Center 48 (-107 ~ 204) 312
4857 22:14:28.720607 iDelay=213, Bit 13, Center 48 (-107 ~ 204) 312
4858 22:14:28.724239 iDelay=213, Bit 14, Center 44 (-107 ~ 196) 304
4859 22:14:28.727364 iDelay=213, Bit 15, Center 48 (-107 ~ 204) 312
4860 22:14:28.727440 ==
4861 22:14:28.730883 Dram Type= 6, Freq= 0, CH_1, rank 1
4862 22:14:28.733989 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4863 22:14:28.737186 ==
4864 22:14:28.737287 DQS Delay:
4865 22:14:28.737377 DQS0 = 0, DQS1 = 0
4866 22:14:28.740503 DQM Delay:
4867 22:14:28.740641 DQM0 = 45, DQM1 = 37
4868 22:14:28.743935 DQ Delay:
4869 22:14:28.747400 DQ0 =48, DQ1 =40, DQ2 =32, DQ3 =40
4870 22:14:28.750329 DQ4 =44, DQ5 =56, DQ6 =60, DQ7 =44
4871 22:14:28.753820 DQ8 =24, DQ9 =24, DQ10 =36, DQ11 =24
4872 22:14:28.757382 DQ12 =48, DQ13 =48, DQ14 =44, DQ15 =48
4873 22:14:28.757455
4874 22:14:28.757516
4875 22:14:28.763935 [DQSOSCAuto] RK1, (LSB)MR18= 0x2a1f, (MSB)MR19= 0x808, tDQSOscB0 = 404 ps tDQSOscB1 = 401 ps
4876 22:14:28.766703 CH1 RK1: MR19=808, MR18=2A1F
4877 22:14:28.773946 CH1_RK1: MR19=0x808, MR18=0x2A1F, DQSOSC=401, MR23=63, INC=163, DEC=108
4878 22:14:28.776923 [RxdqsGatingPostProcess] freq 600
4879 22:14:28.780629 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4880 22:14:28.783381 Pre-setting of DQS Precalculation
4881 22:14:28.790430 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4882 22:14:28.796919 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4883 22:14:28.803485 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4884 22:14:28.803585
4885 22:14:28.803674
4886 22:14:28.806314 [Calibration Summary] 1200 Mbps
4887 22:14:28.806406 CH 0, Rank 0
4888 22:14:28.809974 SW Impedance : PASS
4889 22:14:28.812848 DUTY Scan : NO K
4890 22:14:28.812978 ZQ Calibration : PASS
4891 22:14:28.816383 Jitter Meter : NO K
4892 22:14:28.820410 CBT Training : PASS
4893 22:14:28.820535 Write leveling : PASS
4894 22:14:28.823055 RX DQS gating : PASS
4895 22:14:28.826290 RX DQ/DQS(RDDQC) : PASS
4896 22:14:28.826391 TX DQ/DQS : PASS
4897 22:14:28.829551 RX DATLAT : PASS
4898 22:14:28.833404 RX DQ/DQS(Engine): PASS
4899 22:14:28.833481 TX OE : NO K
4900 22:14:28.836534 All Pass.
4901 22:14:28.836647
4902 22:14:28.836739 CH 0, Rank 1
4903 22:14:28.840096 SW Impedance : PASS
4904 22:14:28.840198 DUTY Scan : NO K
4905 22:14:28.843138 ZQ Calibration : PASS
4906 22:14:28.846321 Jitter Meter : NO K
4907 22:14:28.846404 CBT Training : PASS
4908 22:14:28.849575 Write leveling : PASS
4909 22:14:28.849656 RX DQS gating : PASS
4910 22:14:28.852770 RX DQ/DQS(RDDQC) : PASS
4911 22:14:28.856336 TX DQ/DQS : PASS
4912 22:14:28.856416 RX DATLAT : PASS
4913 22:14:28.859987 RX DQ/DQS(Engine): PASS
4914 22:14:28.862549 TX OE : NO K
4915 22:14:28.862649 All Pass.
4916 22:14:28.862738
4917 22:14:28.862833 CH 1, Rank 0
4918 22:14:28.866104 SW Impedance : PASS
4919 22:14:28.869546 DUTY Scan : NO K
4920 22:14:28.869644 ZQ Calibration : PASS
4921 22:14:28.873040 Jitter Meter : NO K
4922 22:14:28.876205 CBT Training : PASS
4923 22:14:28.876286 Write leveling : PASS
4924 22:14:28.879313 RX DQS gating : PASS
4925 22:14:28.882738 RX DQ/DQS(RDDQC) : PASS
4926 22:14:28.882817 TX DQ/DQS : PASS
4927 22:14:28.886018 RX DATLAT : PASS
4928 22:14:28.888993 RX DQ/DQS(Engine): PASS
4929 22:14:28.889074 TX OE : NO K
4930 22:14:28.892741 All Pass.
4931 22:14:28.892822
4932 22:14:28.892888 CH 1, Rank 1
4933 22:14:28.895515 SW Impedance : PASS
4934 22:14:28.895588 DUTY Scan : NO K
4935 22:14:28.899436 ZQ Calibration : PASS
4936 22:14:28.902312 Jitter Meter : NO K
4937 22:14:28.902397 CBT Training : PASS
4938 22:14:28.905514 Write leveling : PASS
4939 22:14:28.909240 RX DQS gating : PASS
4940 22:14:28.909360 RX DQ/DQS(RDDQC) : PASS
4941 22:14:28.912260 TX DQ/DQS : PASS
4942 22:14:28.912338 RX DATLAT : PASS
4943 22:14:28.915729 RX DQ/DQS(Engine): PASS
4944 22:14:28.919173 TX OE : NO K
4945 22:14:28.919249 All Pass.
4946 22:14:28.919331
4947 22:14:28.922160 DramC Write-DBI off
4948 22:14:28.922234 PER_BANK_REFRESH: Hybrid Mode
4949 22:14:28.926775 TX_TRACKING: ON
4950 22:14:28.935155 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4951 22:14:28.938764 [FAST_K] Save calibration result to emmc
4952 22:14:28.941781 dramc_set_vcore_voltage set vcore to 662500
4953 22:14:28.945376 Read voltage for 933, 3
4954 22:14:28.945453 Vio18 = 0
4955 22:14:28.945532 Vcore = 662500
4956 22:14:28.948403 Vdram = 0
4957 22:14:28.948479 Vddq = 0
4958 22:14:28.948589 Vmddr = 0
4959 22:14:28.954850 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4960 22:14:28.958261 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4961 22:14:28.961604 MEM_TYPE=3, freq_sel=17
4962 22:14:28.965058 sv_algorithm_assistance_LP4_1600
4963 22:14:28.968005 ============ PULL DRAM RESETB DOWN ============
4964 22:14:28.972248 ========== PULL DRAM RESETB DOWN end =========
4965 22:14:28.978650 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4966 22:14:28.981449 ===================================
4967 22:14:28.981528 LPDDR4 DRAM CONFIGURATION
4968 22:14:28.985291 ===================================
4969 22:14:28.988176 EX_ROW_EN[0] = 0x0
4970 22:14:28.991354 EX_ROW_EN[1] = 0x0
4971 22:14:28.991432 LP4Y_EN = 0x0
4972 22:14:28.994710 WORK_FSP = 0x0
4973 22:14:28.994802 WL = 0x3
4974 22:14:28.998349 RL = 0x3
4975 22:14:28.998432 BL = 0x2
4976 22:14:29.001634 RPST = 0x0
4977 22:14:29.001715 RD_PRE = 0x0
4978 22:14:29.004463 WR_PRE = 0x1
4979 22:14:29.004597 WR_PST = 0x0
4980 22:14:29.007676 DBI_WR = 0x0
4981 22:14:29.007758 DBI_RD = 0x0
4982 22:14:29.011259 OTF = 0x1
4983 22:14:29.014517 ===================================
4984 22:14:29.017760 ===================================
4985 22:14:29.017842 ANA top config
4986 22:14:29.021299 ===================================
4987 22:14:29.024780 DLL_ASYNC_EN = 0
4988 22:14:29.028037 ALL_SLAVE_EN = 1
4989 22:14:29.031142 NEW_RANK_MODE = 1
4990 22:14:29.031223 DLL_IDLE_MODE = 1
4991 22:14:29.034220 LP45_APHY_COMB_EN = 1
4992 22:14:29.037604 TX_ODT_DIS = 1
4993 22:14:29.041154 NEW_8X_MODE = 1
4994 22:14:29.044463 ===================================
4995 22:14:29.047688 ===================================
4996 22:14:29.050851 data_rate = 1866
4997 22:14:29.050932 CKR = 1
4998 22:14:29.054454 DQ_P2S_RATIO = 8
4999 22:14:29.057775 ===================================
5000 22:14:29.060970 CA_P2S_RATIO = 8
5001 22:14:29.064403 DQ_CA_OPEN = 0
5002 22:14:29.067683 DQ_SEMI_OPEN = 0
5003 22:14:29.071163 CA_SEMI_OPEN = 0
5004 22:14:29.071245 CA_FULL_RATE = 0
5005 22:14:29.074058 DQ_CKDIV4_EN = 1
5006 22:14:29.077433 CA_CKDIV4_EN = 1
5007 22:14:29.080477 CA_PREDIV_EN = 0
5008 22:14:29.084101 PH8_DLY = 0
5009 22:14:29.086951 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
5010 22:14:29.087027 DQ_AAMCK_DIV = 4
5011 22:14:29.090658 CA_AAMCK_DIV = 4
5012 22:14:29.093879 CA_ADMCK_DIV = 4
5013 22:14:29.097058 DQ_TRACK_CA_EN = 0
5014 22:14:29.100687 CA_PICK = 933
5015 22:14:29.104176 CA_MCKIO = 933
5016 22:14:29.107433 MCKIO_SEMI = 0
5017 22:14:29.110423 PLL_FREQ = 3732
5018 22:14:29.110517 DQ_UI_PI_RATIO = 32
5019 22:14:29.113682 CA_UI_PI_RATIO = 0
5020 22:14:29.116944 ===================================
5021 22:14:29.120417 ===================================
5022 22:14:29.123682 memory_type:LPDDR4
5023 22:14:29.126910 GP_NUM : 10
5024 22:14:29.126998 SRAM_EN : 1
5025 22:14:29.129978 MD32_EN : 0
5026 22:14:29.133954 ===================================
5027 22:14:29.136981 [ANA_INIT] >>>>>>>>>>>>>>
5028 22:14:29.137063 <<<<<< [CONFIGURE PHASE]: ANA_TX
5029 22:14:29.140452 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5030 22:14:29.143654 ===================================
5031 22:14:29.147038 data_rate = 1866,PCW = 0X8f00
5032 22:14:29.149937 ===================================
5033 22:14:29.153362 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5034 22:14:29.159834 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5035 22:14:29.166399 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5036 22:14:29.169532 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5037 22:14:29.172749 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5038 22:14:29.176793 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5039 22:14:29.179639 [ANA_INIT] flow start
5040 22:14:29.179742 [ANA_INIT] PLL >>>>>>>>
5041 22:14:29.182590 [ANA_INIT] PLL <<<<<<<<
5042 22:14:29.185880 [ANA_INIT] MIDPI >>>>>>>>
5043 22:14:29.189489 [ANA_INIT] MIDPI <<<<<<<<
5044 22:14:29.189559 [ANA_INIT] DLL >>>>>>>>
5045 22:14:29.192689 [ANA_INIT] flow end
5046 22:14:29.196046 ============ LP4 DIFF to SE enter ============
5047 22:14:29.199816 ============ LP4 DIFF to SE exit ============
5048 22:14:29.202294 [ANA_INIT] <<<<<<<<<<<<<
5049 22:14:29.205819 [Flow] Enable top DCM control >>>>>
5050 22:14:29.209326 [Flow] Enable top DCM control <<<<<
5051 22:14:29.212357 Enable DLL master slave shuffle
5052 22:14:29.219015 ==============================================================
5053 22:14:29.219115 Gating Mode config
5054 22:14:29.225641 ==============================================================
5055 22:14:29.225743 Config description:
5056 22:14:29.235592 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5057 22:14:29.242024 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5058 22:14:29.248894 SELPH_MODE 0: By rank 1: By Phase
5059 22:14:29.252429 ==============================================================
5060 22:14:29.255557 GAT_TRACK_EN = 1
5061 22:14:29.258567 RX_GATING_MODE = 2
5062 22:14:29.262239 RX_GATING_TRACK_MODE = 2
5063 22:14:29.265159 SELPH_MODE = 1
5064 22:14:29.268712 PICG_EARLY_EN = 1
5065 22:14:29.272012 VALID_LAT_VALUE = 1
5066 22:14:29.278881 ==============================================================
5067 22:14:29.281607 Enter into Gating configuration >>>>
5068 22:14:29.285399 Exit from Gating configuration <<<<
5069 22:14:29.288203 Enter into DVFS_PRE_config >>>>>
5070 22:14:29.298201 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5071 22:14:29.301303 Exit from DVFS_PRE_config <<<<<
5072 22:14:29.305115 Enter into PICG configuration >>>>
5073 22:14:29.308538 Exit from PICG configuration <<<<
5074 22:14:29.311408 [RX_INPUT] configuration >>>>>
5075 22:14:29.314779 [RX_INPUT] configuration <<<<<
5076 22:14:29.317976 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5077 22:14:29.324779 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5078 22:14:29.330863 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5079 22:14:29.334247 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5080 22:14:29.341399 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5081 22:14:29.347640 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5082 22:14:29.350807 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5083 22:14:29.357872 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5084 22:14:29.361223 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5085 22:14:29.364006 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5086 22:14:29.367500 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5087 22:14:29.374033 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5088 22:14:29.377250 ===================================
5089 22:14:29.377332 LPDDR4 DRAM CONFIGURATION
5090 22:14:29.380352 ===================================
5091 22:14:29.383845 EX_ROW_EN[0] = 0x0
5092 22:14:29.386618 EX_ROW_EN[1] = 0x0
5093 22:14:29.386699 LP4Y_EN = 0x0
5094 22:14:29.390194 WORK_FSP = 0x0
5095 22:14:29.390276 WL = 0x3
5096 22:14:29.393404 RL = 0x3
5097 22:14:29.393510 BL = 0x2
5098 22:14:29.396796 RPST = 0x0
5099 22:14:29.396877 RD_PRE = 0x0
5100 22:14:29.399868 WR_PRE = 0x1
5101 22:14:29.399979 WR_PST = 0x0
5102 22:14:29.404082 DBI_WR = 0x0
5103 22:14:29.404163 DBI_RD = 0x0
5104 22:14:29.407016 OTF = 0x1
5105 22:14:29.410255 ===================================
5106 22:14:29.413239 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5107 22:14:29.416446 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5108 22:14:29.423322 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5109 22:14:29.426667 ===================================
5110 22:14:29.429625 LPDDR4 DRAM CONFIGURATION
5111 22:14:29.433037 ===================================
5112 22:14:29.433118 EX_ROW_EN[0] = 0x10
5113 22:14:29.436475 EX_ROW_EN[1] = 0x0
5114 22:14:29.436589 LP4Y_EN = 0x0
5115 22:14:29.439979 WORK_FSP = 0x0
5116 22:14:29.440061 WL = 0x3
5117 22:14:29.442925 RL = 0x3
5118 22:14:29.443007 BL = 0x2
5119 22:14:29.447425 RPST = 0x0
5120 22:14:29.447506 RD_PRE = 0x0
5121 22:14:29.449527 WR_PRE = 0x1
5122 22:14:29.449609 WR_PST = 0x0
5123 22:14:29.452974 DBI_WR = 0x0
5124 22:14:29.453055 DBI_RD = 0x0
5125 22:14:29.456721 OTF = 0x1
5126 22:14:29.459638 ===================================
5127 22:14:29.466245 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5128 22:14:29.469759 nWR fixed to 30
5129 22:14:29.472876 [ModeRegInit_LP4] CH0 RK0
5130 22:14:29.472978 [ModeRegInit_LP4] CH0 RK1
5131 22:14:29.476615 [ModeRegInit_LP4] CH1 RK0
5132 22:14:29.479489 [ModeRegInit_LP4] CH1 RK1
5133 22:14:29.479570 match AC timing 9
5134 22:14:29.486532 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5135 22:14:29.489452 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5136 22:14:29.493028 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5137 22:14:29.499483 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5138 22:14:29.502573 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5139 22:14:29.502654 ==
5140 22:14:29.505595 Dram Type= 6, Freq= 0, CH_0, rank 0
5141 22:14:29.509226 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5142 22:14:29.509321 ==
5143 22:14:29.515799 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5144 22:14:29.522498 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5145 22:14:29.525840 [CA 0] Center 37 (7~68) winsize 62
5146 22:14:29.528866 [CA 1] Center 37 (7~68) winsize 62
5147 22:14:29.532428 [CA 2] Center 34 (4~65) winsize 62
5148 22:14:29.535802 [CA 3] Center 34 (4~65) winsize 62
5149 22:14:29.539351 [CA 4] Center 33 (3~64) winsize 62
5150 22:14:29.542614 [CA 5] Center 33 (3~63) winsize 61
5151 22:14:29.542695
5152 22:14:29.545295 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5153 22:14:29.545377
5154 22:14:29.549043 [CATrainingPosCal] consider 1 rank data
5155 22:14:29.551945 u2DelayCellTimex100 = 270/100 ps
5156 22:14:29.555120 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5157 22:14:29.558545 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5158 22:14:29.562034 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5159 22:14:29.565048 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5160 22:14:29.571712 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5161 22:14:29.575556 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5162 22:14:29.575638
5163 22:14:29.578699 CA PerBit enable=1, Macro0, CA PI delay=33
5164 22:14:29.578780
5165 22:14:29.581604 [CBTSetCACLKResult] CA Dly = 33
5166 22:14:29.581713 CS Dly: 7 (0~38)
5167 22:14:29.581810 ==
5168 22:14:29.584790 Dram Type= 6, Freq= 0, CH_0, rank 1
5169 22:14:29.591183 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5170 22:14:29.591270 ==
5171 22:14:29.595220 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5172 22:14:29.601213 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5173 22:14:29.604740 [CA 0] Center 37 (7~68) winsize 62
5174 22:14:29.608382 [CA 1] Center 37 (7~68) winsize 62
5175 22:14:29.611847 [CA 2] Center 34 (4~65) winsize 62
5176 22:14:29.614492 [CA 3] Center 34 (4~65) winsize 62
5177 22:14:29.617813 [CA 4] Center 33 (3~64) winsize 62
5178 22:14:29.620959 [CA 5] Center 33 (3~63) winsize 61
5179 22:14:29.621044
5180 22:14:29.624391 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5181 22:14:29.624498
5182 22:14:29.627897 [CATrainingPosCal] consider 2 rank data
5183 22:14:29.630891 u2DelayCellTimex100 = 270/100 ps
5184 22:14:29.634498 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5185 22:14:29.641258 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5186 22:14:29.644295 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5187 22:14:29.647660 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5188 22:14:29.650590 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5189 22:14:29.654375 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5190 22:14:29.654457
5191 22:14:29.657727 CA PerBit enable=1, Macro0, CA PI delay=33
5192 22:14:29.657809
5193 22:14:29.660486 [CBTSetCACLKResult] CA Dly = 33
5194 22:14:29.664350 CS Dly: 7 (0~39)
5195 22:14:29.664431
5196 22:14:29.667506 ----->DramcWriteLeveling(PI) begin...
5197 22:14:29.667588 ==
5198 22:14:29.670968 Dram Type= 6, Freq= 0, CH_0, rank 0
5199 22:14:29.673685 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5200 22:14:29.673784 ==
5201 22:14:29.677806 Write leveling (Byte 0): 33 => 33
5202 22:14:29.680616 Write leveling (Byte 1): 32 => 32
5203 22:14:29.683847 DramcWriteLeveling(PI) end<-----
5204 22:14:29.683928
5205 22:14:29.683992 ==
5206 22:14:29.687482 Dram Type= 6, Freq= 0, CH_0, rank 0
5207 22:14:29.690321 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5208 22:14:29.690403 ==
5209 22:14:29.694055 [Gating] SW mode calibration
5210 22:14:29.700265 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5211 22:14:29.706839 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5212 22:14:29.710241 0 14 0 | B1->B0 | 2323 3232 | 0 0 | (1 1) (0 0)
5213 22:14:29.713296 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5214 22:14:29.719973 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5215 22:14:29.723147 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5216 22:14:29.726349 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5217 22:14:29.733485 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5218 22:14:29.736884 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5219 22:14:29.739527 0 14 28 | B1->B0 | 3333 2e2e | 1 1 | (1 1) (1 0)
5220 22:14:29.746446 0 15 0 | B1->B0 | 3232 2323 | 1 0 | (1 0) (0 0)
5221 22:14:29.749686 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5222 22:14:29.752953 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5223 22:14:29.759711 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5224 22:14:29.762652 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5225 22:14:29.766603 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5226 22:14:29.772432 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5227 22:14:29.776092 0 15 28 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
5228 22:14:29.779076 1 0 0 | B1->B0 | 2f2e 4040 | 1 0 | (0 0) (0 0)
5229 22:14:29.786071 1 0 4 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
5230 22:14:29.789125 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5231 22:14:29.792703 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5232 22:14:29.798996 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5233 22:14:29.802453 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5234 22:14:29.805611 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5235 22:14:29.812230 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5236 22:14:29.815586 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5237 22:14:29.818822 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5238 22:14:29.825669 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5239 22:14:29.828850 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5240 22:14:29.832472 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5241 22:14:29.838938 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5242 22:14:29.842723 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5243 22:14:29.845724 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5244 22:14:29.851938 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5245 22:14:29.855294 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5246 22:14:29.858507 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5247 22:14:29.865532 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5248 22:14:29.868687 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5249 22:14:29.871930 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5250 22:14:29.878457 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5251 22:14:29.881672 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5252 22:14:29.885282 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5253 22:14:29.888405 Total UI for P1: 0, mck2ui 16
5254 22:14:29.891481 best dqsien dly found for B0: ( 1, 2, 28)
5255 22:14:29.898321 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5256 22:14:29.898406 Total UI for P1: 0, mck2ui 16
5257 22:14:29.904899 best dqsien dly found for B1: ( 1, 2, 30)
5258 22:14:29.907895 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5259 22:14:29.911443 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5260 22:14:29.911526
5261 22:14:29.914698 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5262 22:14:29.917952 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5263 22:14:29.921139 [Gating] SW calibration Done
5264 22:14:29.921220 ==
5265 22:14:29.924527 Dram Type= 6, Freq= 0, CH_0, rank 0
5266 22:14:29.927793 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5267 22:14:29.927874 ==
5268 22:14:29.931231 RX Vref Scan: 0
5269 22:14:29.931312
5270 22:14:29.934903 RX Vref 0 -> 0, step: 1
5271 22:14:29.934985
5272 22:14:29.935049 RX Delay -80 -> 252, step: 8
5273 22:14:29.941551 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5274 22:14:29.944047 iDelay=208, Bit 1, Center 103 (8 ~ 199) 192
5275 22:14:29.947633 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5276 22:14:29.951065 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5277 22:14:29.954119 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5278 22:14:29.957569 iDelay=208, Bit 5, Center 87 (-16 ~ 191) 208
5279 22:14:29.964006 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5280 22:14:29.967785 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5281 22:14:29.970455 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5282 22:14:29.973826 iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184
5283 22:14:29.976949 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5284 22:14:29.983648 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5285 22:14:29.986872 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5286 22:14:29.990173 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5287 22:14:29.993511 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5288 22:14:29.996758 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5289 22:14:29.996828 ==
5290 22:14:30.000855 Dram Type= 6, Freq= 0, CH_0, rank 0
5291 22:14:30.006581 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5292 22:14:30.006664 ==
5293 22:14:30.006728 DQS Delay:
5294 22:14:30.010466 DQS0 = 0, DQS1 = 0
5295 22:14:30.010547 DQM Delay:
5296 22:14:30.013678 DQM0 = 98, DQM1 = 87
5297 22:14:30.013795 DQ Delay:
5298 22:14:30.016851 DQ0 =99, DQ1 =103, DQ2 =91, DQ3 =95
5299 22:14:30.020337 DQ4 =99, DQ5 =87, DQ6 =107, DQ7 =107
5300 22:14:30.023813 DQ8 =79, DQ9 =75, DQ10 =87, DQ11 =79
5301 22:14:30.026794 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5302 22:14:30.026875
5303 22:14:30.026976
5304 22:14:30.027034 ==
5305 22:14:30.029986 Dram Type= 6, Freq= 0, CH_0, rank 0
5306 22:14:30.033530 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5307 22:14:30.033612 ==
5308 22:14:30.033676
5309 22:14:30.033758
5310 22:14:30.036805 TX Vref Scan disable
5311 22:14:30.040362 == TX Byte 0 ==
5312 22:14:30.043618 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5313 22:14:30.046328 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5314 22:14:30.050014 == TX Byte 1 ==
5315 22:14:30.052973 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5316 22:14:30.056179 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5317 22:14:30.056261 ==
5318 22:14:30.059983 Dram Type= 6, Freq= 0, CH_0, rank 0
5319 22:14:30.066309 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5320 22:14:30.066391 ==
5321 22:14:30.066455
5322 22:14:30.066514
5323 22:14:30.066570 TX Vref Scan disable
5324 22:14:30.069952 == TX Byte 0 ==
5325 22:14:30.073634 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5326 22:14:30.080036 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5327 22:14:30.080118 == TX Byte 1 ==
5328 22:14:30.083224 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5329 22:14:30.090761 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5330 22:14:30.090870
5331 22:14:30.090935 [DATLAT]
5332 22:14:30.090994 Freq=933, CH0 RK0
5333 22:14:30.091053
5334 22:14:30.093357 DATLAT Default: 0xd
5335 22:14:30.093438 0, 0xFFFF, sum = 0
5336 22:14:30.096500 1, 0xFFFF, sum = 0
5337 22:14:30.099857 2, 0xFFFF, sum = 0
5338 22:14:30.099940 3, 0xFFFF, sum = 0
5339 22:14:30.103797 4, 0xFFFF, sum = 0
5340 22:14:30.103880 5, 0xFFFF, sum = 0
5341 22:14:30.106611 6, 0xFFFF, sum = 0
5342 22:14:30.106708 7, 0xFFFF, sum = 0
5343 22:14:30.109575 8, 0xFFFF, sum = 0
5344 22:14:30.109658 9, 0xFFFF, sum = 0
5345 22:14:30.112837 10, 0x0, sum = 1
5346 22:14:30.112933 11, 0x0, sum = 2
5347 22:14:30.116184 12, 0x0, sum = 3
5348 22:14:30.116265 13, 0x0, sum = 4
5349 22:14:30.116329 best_step = 11
5350 22:14:30.120031
5351 22:14:30.120110 ==
5352 22:14:30.122860 Dram Type= 6, Freq= 0, CH_0, rank 0
5353 22:14:30.125951 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5354 22:14:30.126046 ==
5355 22:14:30.126110 RX Vref Scan: 1
5356 22:14:30.126169
5357 22:14:30.129408 RX Vref 0 -> 0, step: 1
5358 22:14:30.129488
5359 22:14:30.132791 RX Delay -61 -> 252, step: 4
5360 22:14:30.132870
5361 22:14:30.136007 Set Vref, RX VrefLevel [Byte0]: 59
5362 22:14:30.139300 [Byte1]: 49
5363 22:14:30.142402
5364 22:14:30.146139 Final RX Vref Byte 0 = 59 to rank0
5365 22:14:30.146220 Final RX Vref Byte 1 = 49 to rank0
5366 22:14:30.149147 Final RX Vref Byte 0 = 59 to rank1
5367 22:14:30.152955 Final RX Vref Byte 1 = 49 to rank1==
5368 22:14:30.155597 Dram Type= 6, Freq= 0, CH_0, rank 0
5369 22:14:30.162614 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5370 22:14:30.162693 ==
5371 22:14:30.162756 DQS Delay:
5372 22:14:30.165440 DQS0 = 0, DQS1 = 0
5373 22:14:30.165520 DQM Delay:
5374 22:14:30.165610 DQM0 = 97, DQM1 = 85
5375 22:14:30.168808 DQ Delay:
5376 22:14:30.172308 DQ0 =96, DQ1 =98, DQ2 =94, DQ3 =94
5377 22:14:30.175539 DQ4 =98, DQ5 =88, DQ6 =106, DQ7 =106
5378 22:14:30.178769 DQ8 =76, DQ9 =74, DQ10 =84, DQ11 =78
5379 22:14:30.182071 DQ12 =90, DQ13 =88, DQ14 =96, DQ15 =94
5380 22:14:30.182151
5381 22:14:30.182212
5382 22:14:30.188861 [DQSOSCAuto] RK0, (LSB)MR18= 0x2c12, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 408 ps
5383 22:14:30.191685 CH0 RK0: MR19=505, MR18=2C12
5384 22:14:30.198844 CH0_RK0: MR19=0x505, MR18=0x2C12, DQSOSC=408, MR23=63, INC=65, DEC=43
5385 22:14:30.198924
5386 22:14:30.201871 ----->DramcWriteLeveling(PI) begin...
5387 22:14:30.201951 ==
5388 22:14:30.205912 Dram Type= 6, Freq= 0, CH_0, rank 1
5389 22:14:30.208627 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5390 22:14:30.208707 ==
5391 22:14:30.211506 Write leveling (Byte 0): 34 => 34
5392 22:14:30.214851 Write leveling (Byte 1): 29 => 29
5393 22:14:30.218177 DramcWriteLeveling(PI) end<-----
5394 22:14:30.218256
5395 22:14:30.218317 ==
5396 22:14:30.221497 Dram Type= 6, Freq= 0, CH_0, rank 1
5397 22:14:30.228377 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5398 22:14:30.228457 ==
5399 22:14:30.228541 [Gating] SW mode calibration
5400 22:14:30.238368 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5401 22:14:30.241766 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5402 22:14:30.244695 0 14 0 | B1->B0 | 2828 2f2f | 0 0 | (0 0) (0 0)
5403 22:14:30.251147 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5404 22:14:30.254582 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5405 22:14:30.258042 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5406 22:14:30.264680 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5407 22:14:30.268178 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5408 22:14:30.271371 0 14 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5409 22:14:30.277774 0 14 28 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 1)
5410 22:14:30.281068 0 15 0 | B1->B0 | 2b2b 2323 | 0 0 | (1 1) (0 0)
5411 22:14:30.284122 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5412 22:14:30.291264 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5413 22:14:30.294117 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5414 22:14:30.297529 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5415 22:14:30.304387 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5416 22:14:30.307284 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5417 22:14:30.311023 0 15 28 | B1->B0 | 2626 3332 | 0 1 | (0 0) (0 0)
5418 22:14:30.317678 1 0 0 | B1->B0 | 3c3c 4444 | 0 0 | (0 0) (0 0)
5419 22:14:30.320966 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5420 22:14:30.324146 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5421 22:14:30.330854 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5422 22:14:30.333720 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5423 22:14:30.337184 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5424 22:14:30.343923 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5425 22:14:30.347760 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5426 22:14:30.350568 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5427 22:14:30.357082 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5428 22:14:30.360407 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5429 22:14:30.363596 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5430 22:14:30.370011 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5431 22:14:30.373246 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5432 22:14:30.376453 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5433 22:14:30.383305 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5434 22:14:30.386848 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5435 22:14:30.390012 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5436 22:14:30.396622 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5437 22:14:30.399700 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5438 22:14:30.402997 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5439 22:14:30.409611 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5440 22:14:30.413052 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5441 22:14:30.416443 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5442 22:14:30.422940 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5443 22:14:30.426313 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5444 22:14:30.430394 Total UI for P1: 0, mck2ui 16
5445 22:14:30.432705 best dqsien dly found for B0: ( 1, 2, 30)
5446 22:14:30.436624 Total UI for P1: 0, mck2ui 16
5447 22:14:30.439702 best dqsien dly found for B1: ( 1, 3, 2)
5448 22:14:30.442926 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5449 22:14:30.445772 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5450 22:14:30.445870
5451 22:14:30.449081 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5452 22:14:30.452971 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5453 22:14:30.455919 [Gating] SW calibration Done
5454 22:14:30.456002 ==
5455 22:14:30.459110 Dram Type= 6, Freq= 0, CH_0, rank 1
5456 22:14:30.465755 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5457 22:14:30.465839 ==
5458 22:14:30.465905 RX Vref Scan: 0
5459 22:14:30.465965
5460 22:14:30.468737 RX Vref 0 -> 0, step: 1
5461 22:14:30.468820
5462 22:14:30.472615 RX Delay -80 -> 252, step: 8
5463 22:14:30.475507 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5464 22:14:30.478882 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5465 22:14:30.482406 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5466 22:14:30.485683 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5467 22:14:30.492026 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5468 22:14:30.495876 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5469 22:14:30.498761 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5470 22:14:30.501880 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5471 22:14:30.505331 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5472 22:14:30.508461 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5473 22:14:30.514955 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5474 22:14:30.518499 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5475 22:14:30.521723 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5476 22:14:30.525176 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5477 22:14:30.528426 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5478 22:14:30.535091 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5479 22:14:30.535173 ==
5480 22:14:30.538270 Dram Type= 6, Freq= 0, CH_0, rank 1
5481 22:14:30.541619 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5482 22:14:30.541702 ==
5483 22:14:30.541767 DQS Delay:
5484 22:14:30.544660 DQS0 = 0, DQS1 = 0
5485 22:14:30.544763 DQM Delay:
5486 22:14:30.548360 DQM0 = 97, DQM1 = 87
5487 22:14:30.548473 DQ Delay:
5488 22:14:30.551799 DQ0 =95, DQ1 =99, DQ2 =91, DQ3 =91
5489 22:14:30.554848 DQ4 =99, DQ5 =87, DQ6 =107, DQ7 =107
5490 22:14:30.558290 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =83
5491 22:14:30.561565 DQ12 =91, DQ13 =91, DQ14 =95, DQ15 =91
5492 22:14:30.561645
5493 22:14:30.561708
5494 22:14:30.561766 ==
5495 22:14:30.564978 Dram Type= 6, Freq= 0, CH_0, rank 1
5496 22:14:30.568011 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5497 22:14:30.571521 ==
5498 22:14:30.571605
5499 22:14:30.571668
5500 22:14:30.571726 TX Vref Scan disable
5501 22:14:30.574570 == TX Byte 0 ==
5502 22:14:30.578323 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5503 22:14:30.584452 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5504 22:14:30.584591 == TX Byte 1 ==
5505 22:14:30.587982 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5506 22:14:30.594506 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5507 22:14:30.594589 ==
5508 22:14:30.597840 Dram Type= 6, Freq= 0, CH_0, rank 1
5509 22:14:30.601192 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5510 22:14:30.601272 ==
5511 22:14:30.601336
5512 22:14:30.601393
5513 22:14:30.604806 TX Vref Scan disable
5514 22:14:30.604887 == TX Byte 0 ==
5515 22:14:30.611165 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5516 22:14:30.614364 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5517 22:14:30.614445 == TX Byte 1 ==
5518 22:14:30.621330 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5519 22:14:30.624320 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5520 22:14:30.624419
5521 22:14:30.624511 [DATLAT]
5522 22:14:30.627336 Freq=933, CH0 RK1
5523 22:14:30.627416
5524 22:14:30.627479 DATLAT Default: 0xb
5525 22:14:30.630811 0, 0xFFFF, sum = 0
5526 22:14:30.634214 1, 0xFFFF, sum = 0
5527 22:14:30.634312 2, 0xFFFF, sum = 0
5528 22:14:30.637636 3, 0xFFFF, sum = 0
5529 22:14:30.637718 4, 0xFFFF, sum = 0
5530 22:14:30.640647 5, 0xFFFF, sum = 0
5531 22:14:30.640765 6, 0xFFFF, sum = 0
5532 22:14:30.643863 7, 0xFFFF, sum = 0
5533 22:14:30.643944 8, 0xFFFF, sum = 0
5534 22:14:30.647120 9, 0xFFFF, sum = 0
5535 22:14:30.647228 10, 0x0, sum = 1
5536 22:14:30.650766 11, 0x0, sum = 2
5537 22:14:30.650848 12, 0x0, sum = 3
5538 22:14:30.653643 13, 0x0, sum = 4
5539 22:14:30.653724 best_step = 11
5540 22:14:30.653787
5541 22:14:30.653877 ==
5542 22:14:30.656910 Dram Type= 6, Freq= 0, CH_0, rank 1
5543 22:14:30.660225 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5544 22:14:30.663502 ==
5545 22:14:30.663583 RX Vref Scan: 0
5546 22:14:30.663647
5547 22:14:30.666904 RX Vref 0 -> 0, step: 1
5548 22:14:30.666985
5549 22:14:30.670387 RX Delay -61 -> 252, step: 4
5550 22:14:30.673389 iDelay=203, Bit 0, Center 92 (-1 ~ 186) 188
5551 22:14:30.676406 iDelay=203, Bit 1, Center 96 (-1 ~ 194) 196
5552 22:14:30.680162 iDelay=203, Bit 2, Center 90 (-1 ~ 182) 184
5553 22:14:30.687712 iDelay=203, Bit 3, Center 92 (-5 ~ 190) 196
5554 22:14:30.689941 iDelay=203, Bit 4, Center 96 (3 ~ 190) 188
5555 22:14:30.693477 iDelay=203, Bit 5, Center 86 (-9 ~ 182) 192
5556 22:14:30.696781 iDelay=203, Bit 6, Center 104 (7 ~ 202) 196
5557 22:14:30.699822 iDelay=203, Bit 7, Center 104 (11 ~ 198) 188
5558 22:14:30.706312 iDelay=203, Bit 8, Center 78 (-13 ~ 170) 184
5559 22:14:30.709596 iDelay=203, Bit 9, Center 74 (-17 ~ 166) 184
5560 22:14:30.713206 iDelay=203, Bit 10, Center 88 (-5 ~ 182) 188
5561 22:14:30.716425 iDelay=203, Bit 11, Center 78 (-13 ~ 170) 184
5562 22:14:30.720370 iDelay=203, Bit 12, Center 92 (-1 ~ 186) 188
5563 22:14:30.726119 iDelay=203, Bit 13, Center 90 (-5 ~ 186) 192
5564 22:14:30.729495 iDelay=203, Bit 14, Center 96 (7 ~ 186) 180
5565 22:14:30.732921 iDelay=203, Bit 15, Center 92 (-1 ~ 186) 188
5566 22:14:30.733002 ==
5567 22:14:30.736075 Dram Type= 6, Freq= 0, CH_0, rank 1
5568 22:14:30.739418 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5569 22:14:30.739500 ==
5570 22:14:30.742645 DQS Delay:
5571 22:14:30.742731 DQS0 = 0, DQS1 = 0
5572 22:14:30.746202 DQM Delay:
5573 22:14:30.746289 DQM0 = 95, DQM1 = 86
5574 22:14:30.746354 DQ Delay:
5575 22:14:30.749175 DQ0 =92, DQ1 =96, DQ2 =90, DQ3 =92
5576 22:14:30.753050 DQ4 =96, DQ5 =86, DQ6 =104, DQ7 =104
5577 22:14:30.756467 DQ8 =78, DQ9 =74, DQ10 =88, DQ11 =78
5578 22:14:30.759290 DQ12 =92, DQ13 =90, DQ14 =96, DQ15 =92
5579 22:14:30.759366
5580 22:14:30.759434
5581 22:14:30.769218 [DQSOSCAuto] RK1, (LSB)MR18= 0x2bfb, (MSB)MR19= 0x504, tDQSOscB0 = 423 ps tDQSOscB1 = 408 ps
5582 22:14:30.772249 CH0 RK1: MR19=504, MR18=2BFB
5583 22:14:30.778985 CH0_RK1: MR19=0x504, MR18=0x2BFB, DQSOSC=408, MR23=63, INC=65, DEC=43
5584 22:14:30.779064 [RxdqsGatingPostProcess] freq 933
5585 22:14:30.785617 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5586 22:14:30.789275 best DQS0 dly(2T, 0.5T) = (0, 10)
5587 22:14:30.792752 best DQS1 dly(2T, 0.5T) = (0, 10)
5588 22:14:30.795487 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5589 22:14:30.798821 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5590 22:14:30.802203 best DQS0 dly(2T, 0.5T) = (0, 10)
5591 22:14:30.805447 best DQS1 dly(2T, 0.5T) = (0, 11)
5592 22:14:30.808669 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5593 22:14:30.811749 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5594 22:14:30.815183 Pre-setting of DQS Precalculation
5595 22:14:30.818554 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5596 22:14:30.818630 ==
5597 22:14:30.821987 Dram Type= 6, Freq= 0, CH_1, rank 0
5598 22:14:30.828489 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5599 22:14:30.828615 ==
5600 22:14:30.831368 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5601 22:14:30.838706 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5602 22:14:30.841378 [CA 0] Center 37 (7~67) winsize 61
5603 22:14:30.844915 [CA 1] Center 37 (7~68) winsize 62
5604 22:14:30.848256 [CA 2] Center 34 (4~65) winsize 62
5605 22:14:30.851798 [CA 3] Center 33 (3~64) winsize 62
5606 22:14:30.854910 [CA 4] Center 34 (5~64) winsize 60
5607 22:14:30.858171 [CA 5] Center 34 (4~64) winsize 61
5608 22:14:30.858248
5609 22:14:30.861230 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5610 22:14:30.861310
5611 22:14:30.864944 [CATrainingPosCal] consider 1 rank data
5612 22:14:30.867943 u2DelayCellTimex100 = 270/100 ps
5613 22:14:30.871009 CA0 delay=37 (7~67),Diff = 4 PI (24 cell)
5614 22:14:30.874787 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5615 22:14:30.881307 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5616 22:14:30.884389 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5617 22:14:30.887535 CA4 delay=34 (5~64),Diff = 1 PI (6 cell)
5618 22:14:30.891106 CA5 delay=34 (4~64),Diff = 1 PI (6 cell)
5619 22:14:30.891190
5620 22:14:30.894270 CA PerBit enable=1, Macro0, CA PI delay=33
5621 22:14:30.894346
5622 22:14:30.897563 [CBTSetCACLKResult] CA Dly = 33
5623 22:14:30.897636 CS Dly: 6 (0~37)
5624 22:14:30.900882 ==
5625 22:14:30.904773 Dram Type= 6, Freq= 0, CH_1, rank 1
5626 22:14:30.908118 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5627 22:14:30.908191 ==
5628 22:14:30.913979 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5629 22:14:30.917337 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5630 22:14:30.921200 [CA 0] Center 36 (6~67) winsize 62
5631 22:14:30.924333 [CA 1] Center 37 (7~67) winsize 61
5632 22:14:30.927518 [CA 2] Center 34 (4~65) winsize 62
5633 22:14:30.931232 [CA 3] Center 34 (4~65) winsize 62
5634 22:14:30.934265 [CA 4] Center 34 (4~65) winsize 62
5635 22:14:30.938351 [CA 5] Center 33 (3~64) winsize 62
5636 22:14:30.938430
5637 22:14:30.940822 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5638 22:14:30.940930
5639 22:14:30.944131 [CATrainingPosCal] consider 2 rank data
5640 22:14:30.947600 u2DelayCellTimex100 = 270/100 ps
5641 22:14:30.950955 CA0 delay=37 (7~67),Diff = 3 PI (18 cell)
5642 22:14:30.957611 CA1 delay=37 (7~67),Diff = 3 PI (18 cell)
5643 22:14:30.960668 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
5644 22:14:30.963979 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
5645 22:14:30.967572 CA4 delay=34 (5~64),Diff = 0 PI (0 cell)
5646 22:14:30.970933 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5647 22:14:30.971007
5648 22:14:30.974248 CA PerBit enable=1, Macro0, CA PI delay=34
5649 22:14:30.974326
5650 22:14:30.977492 [CBTSetCACLKResult] CA Dly = 34
5651 22:14:30.980605 CS Dly: 7 (0~39)
5652 22:14:30.980683
5653 22:14:30.983740 ----->DramcWriteLeveling(PI) begin...
5654 22:14:30.983814 ==
5655 22:14:30.987414 Dram Type= 6, Freq= 0, CH_1, rank 0
5656 22:14:30.990529 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5657 22:14:30.990605 ==
5658 22:14:30.994207 Write leveling (Byte 0): 26 => 26
5659 22:14:30.997062 Write leveling (Byte 1): 27 => 27
5660 22:14:31.000634 DramcWriteLeveling(PI) end<-----
5661 22:14:31.000710
5662 22:14:31.000771 ==
5663 22:14:31.003527 Dram Type= 6, Freq= 0, CH_1, rank 0
5664 22:14:31.006984 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5665 22:14:31.007055 ==
5666 22:14:31.010171 [Gating] SW mode calibration
5667 22:14:31.016985 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5668 22:14:31.024011 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5669 22:14:31.026940 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5670 22:14:31.029989 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5671 22:14:31.036442 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5672 22:14:31.040149 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5673 22:14:31.043294 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5674 22:14:31.050352 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5675 22:14:31.052974 0 14 24 | B1->B0 | 3434 3333 | 0 1 | (0 0) (1 0)
5676 22:14:31.056217 0 14 28 | B1->B0 | 2a2a 2828 | 0 1 | (1 0) (1 0)
5677 22:14:31.063145 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5678 22:14:31.066285 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5679 22:14:31.069468 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5680 22:14:31.076527 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5681 22:14:31.079683 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5682 22:14:31.082614 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5683 22:14:31.089439 0 15 24 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
5684 22:14:31.092670 0 15 28 | B1->B0 | 3939 3e3e | 0 0 | (0 0) (0 0)
5685 22:14:31.096042 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5686 22:14:31.102615 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5687 22:14:31.106451 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5688 22:14:31.109520 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5689 22:14:31.115958 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5690 22:14:31.118950 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5691 22:14:31.122502 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5692 22:14:31.129566 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5693 22:14:31.132568 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5694 22:14:31.135897 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5695 22:14:31.142641 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5696 22:14:31.146063 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5697 22:14:31.149369 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5698 22:14:31.155591 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5699 22:14:31.158921 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5700 22:14:31.162388 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5701 22:14:31.168782 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5702 22:14:31.172372 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5703 22:14:31.175444 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5704 22:14:31.182616 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5705 22:14:31.185244 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5706 22:14:31.188897 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5707 22:14:31.195430 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5708 22:14:31.198805 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5709 22:14:31.202297 Total UI for P1: 0, mck2ui 16
5710 22:14:31.205147 best dqsien dly found for B0: ( 1, 2, 24)
5711 22:14:31.208698 Total UI for P1: 0, mck2ui 16
5712 22:14:31.212012 best dqsien dly found for B1: ( 1, 2, 24)
5713 22:14:31.215073 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5714 22:14:31.218441 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5715 22:14:31.218513
5716 22:14:31.222131 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5717 22:14:31.224806 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5718 22:14:31.228189 [Gating] SW calibration Done
5719 22:14:31.228264 ==
5720 22:14:31.231693 Dram Type= 6, Freq= 0, CH_1, rank 0
5721 22:14:31.238344 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5722 22:14:31.238444 ==
5723 22:14:31.238552 RX Vref Scan: 0
5724 22:14:31.238613
5725 22:14:31.241712 RX Vref 0 -> 0, step: 1
5726 22:14:31.241794
5727 22:14:31.244792 RX Delay -80 -> 252, step: 8
5728 22:14:31.247860 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5729 22:14:31.251664 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5730 22:14:31.254720 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5731 22:14:31.258089 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5732 22:14:31.264253 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5733 22:14:31.267503 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5734 22:14:31.271080 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5735 22:14:31.274110 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5736 22:14:31.277324 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5737 22:14:31.280976 iDelay=208, Bit 9, Center 83 (-16 ~ 183) 200
5738 22:14:31.287685 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5739 22:14:31.291020 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5740 22:14:31.294011 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5741 22:14:31.297371 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5742 22:14:31.300469 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5743 22:14:31.307407 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5744 22:14:31.307506 ==
5745 22:14:31.310429 Dram Type= 6, Freq= 0, CH_1, rank 0
5746 22:14:31.313760 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5747 22:14:31.313842 ==
5748 22:14:31.313908 DQS Delay:
5749 22:14:31.317389 DQS0 = 0, DQS1 = 0
5750 22:14:31.317470 DQM Delay:
5751 22:14:31.320431 DQM0 = 101, DQM1 = 91
5752 22:14:31.320519 DQ Delay:
5753 22:14:31.323480 DQ0 =107, DQ1 =95, DQ2 =95, DQ3 =99
5754 22:14:31.327012 DQ4 =95, DQ5 =111, DQ6 =111, DQ7 =99
5755 22:14:31.330407 DQ8 =79, DQ9 =83, DQ10 =91, DQ11 =79
5756 22:14:31.333578 DQ12 =99, DQ13 =99, DQ14 =99, DQ15 =99
5757 22:14:31.333696
5758 22:14:31.333788
5759 22:14:31.333875 ==
5760 22:14:31.337335 Dram Type= 6, Freq= 0, CH_1, rank 0
5761 22:14:31.343386 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5762 22:14:31.343468 ==
5763 22:14:31.343533
5764 22:14:31.343593
5765 22:14:31.343650 TX Vref Scan disable
5766 22:14:31.346971 == TX Byte 0 ==
5767 22:14:31.349773 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5768 22:14:31.356422 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5769 22:14:31.356578 == TX Byte 1 ==
5770 22:14:31.359999 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5771 22:14:31.366118 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5772 22:14:31.366230 ==
5773 22:14:31.369700 Dram Type= 6, Freq= 0, CH_1, rank 0
5774 22:14:31.373057 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5775 22:14:31.373165 ==
5776 22:14:31.373261
5777 22:14:31.373351
5778 22:14:31.376491 TX Vref Scan disable
5779 22:14:31.379352 == TX Byte 0 ==
5780 22:14:31.383029 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5781 22:14:31.386490 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5782 22:14:31.389426 == TX Byte 1 ==
5783 22:14:31.392816 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5784 22:14:31.396116 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5785 22:14:31.396219
5786 22:14:31.396320 [DATLAT]
5787 22:14:31.399507 Freq=933, CH1 RK0
5788 22:14:31.399611
5789 22:14:31.402830 DATLAT Default: 0xd
5790 22:14:31.402931 0, 0xFFFF, sum = 0
5791 22:14:31.406002 1, 0xFFFF, sum = 0
5792 22:14:31.406112 2, 0xFFFF, sum = 0
5793 22:14:31.409329 3, 0xFFFF, sum = 0
5794 22:14:31.409440 4, 0xFFFF, sum = 0
5795 22:14:31.412512 5, 0xFFFF, sum = 0
5796 22:14:31.412616 6, 0xFFFF, sum = 0
5797 22:14:31.415854 7, 0xFFFF, sum = 0
5798 22:14:31.415932 8, 0xFFFF, sum = 0
5799 22:14:31.419265 9, 0xFFFF, sum = 0
5800 22:14:31.419337 10, 0x0, sum = 1
5801 22:14:31.422395 11, 0x0, sum = 2
5802 22:14:31.422469 12, 0x0, sum = 3
5803 22:14:31.425768 13, 0x0, sum = 4
5804 22:14:31.425846 best_step = 11
5805 22:14:31.425908
5806 22:14:31.425971 ==
5807 22:14:31.428971 Dram Type= 6, Freq= 0, CH_1, rank 0
5808 22:14:31.432754 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5809 22:14:31.435831 ==
5810 22:14:31.435905 RX Vref Scan: 1
5811 22:14:31.435969
5812 22:14:31.439094 RX Vref 0 -> 0, step: 1
5813 22:14:31.439178
5814 22:14:31.439270 RX Delay -61 -> 252, step: 4
5815 22:14:31.442352
5816 22:14:31.442466 Set Vref, RX VrefLevel [Byte0]: 48
5817 22:14:31.445746 [Byte1]: 58
5818 22:14:31.450457
5819 22:14:31.450551 Final RX Vref Byte 0 = 48 to rank0
5820 22:14:31.454025 Final RX Vref Byte 1 = 58 to rank0
5821 22:14:31.456997 Final RX Vref Byte 0 = 48 to rank1
5822 22:14:31.460415 Final RX Vref Byte 1 = 58 to rank1==
5823 22:14:31.463718 Dram Type= 6, Freq= 0, CH_1, rank 0
5824 22:14:31.470595 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5825 22:14:31.470671 ==
5826 22:14:31.470735 DQS Delay:
5827 22:14:31.473507 DQS0 = 0, DQS1 = 0
5828 22:14:31.473581 DQM Delay:
5829 22:14:31.473656 DQM0 = 101, DQM1 = 95
5830 22:14:31.476601 DQ Delay:
5831 22:14:31.480144 DQ0 =106, DQ1 =96, DQ2 =94, DQ3 =98
5832 22:14:31.483332 DQ4 =100, DQ5 =112, DQ6 =110, DQ7 =98
5833 22:14:31.486468 DQ8 =84, DQ9 =86, DQ10 =98, DQ11 =84
5834 22:14:31.489948 DQ12 =102, DQ13 =102, DQ14 =102, DQ15 =102
5835 22:14:31.490022
5836 22:14:31.490087
5837 22:14:31.496592 [DQSOSCAuto] RK0, (LSB)MR18= 0x1a0a, (MSB)MR19= 0x505, tDQSOscB0 = 418 ps tDQSOscB1 = 413 ps
5838 22:14:31.499815 CH1 RK0: MR19=505, MR18=1A0A
5839 22:14:31.506333 CH1_RK0: MR19=0x505, MR18=0x1A0A, DQSOSC=413, MR23=63, INC=63, DEC=42
5840 22:14:31.506412
5841 22:14:31.509612 ----->DramcWriteLeveling(PI) begin...
5842 22:14:31.509709 ==
5843 22:14:31.513120 Dram Type= 6, Freq= 0, CH_1, rank 1
5844 22:14:31.519806 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5845 22:14:31.519904 ==
5846 22:14:31.523160 Write leveling (Byte 0): 28 => 28
5847 22:14:31.523237 Write leveling (Byte 1): 29 => 29
5848 22:14:31.526246 DramcWriteLeveling(PI) end<-----
5849 22:14:31.526314
5850 22:14:31.526374 ==
5851 22:14:31.530110 Dram Type= 6, Freq= 0, CH_1, rank 1
5852 22:14:31.536527 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5853 22:14:31.536614 ==
5854 22:14:31.539661 [Gating] SW mode calibration
5855 22:14:31.546046 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5856 22:14:31.549535 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5857 22:14:31.556219 0 14 0 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 1)
5858 22:14:31.559311 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5859 22:14:31.562964 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5860 22:14:31.569396 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5861 22:14:31.572536 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5862 22:14:31.575977 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5863 22:14:31.582370 0 14 24 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 0)
5864 22:14:31.585307 0 14 28 | B1->B0 | 2e2e 2f2f | 0 0 | (0 0) (0 0)
5865 22:14:31.589183 0 15 0 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
5866 22:14:31.595616 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5867 22:14:31.598722 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5868 22:14:31.601648 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5869 22:14:31.608470 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5870 22:14:31.612031 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5871 22:14:31.615428 0 15 24 | B1->B0 | 2b2b 2323 | 0 0 | (0 0) (0 0)
5872 22:14:31.621456 0 15 28 | B1->B0 | 3f3f 2f2f | 1 0 | (0 0) (0 0)
5873 22:14:31.625495 1 0 0 | B1->B0 | 4646 4141 | 0 0 | (0 0) (0 0)
5874 22:14:31.628488 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5875 22:14:31.635088 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5876 22:14:31.638012 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5877 22:14:31.641315 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5878 22:14:31.648057 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5879 22:14:31.651925 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5880 22:14:31.654795 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5881 22:14:31.660948 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5882 22:14:31.664321 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5883 22:14:31.667523 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5884 22:14:31.674622 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5885 22:14:31.678084 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5886 22:14:31.680952 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5887 22:14:31.687508 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5888 22:14:31.690663 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5889 22:14:31.693989 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5890 22:14:31.701109 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5891 22:14:31.704313 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5892 22:14:31.707525 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5893 22:14:31.713739 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5894 22:14:31.717398 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5895 22:14:31.720522 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5896 22:14:31.727161 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5897 22:14:31.730831 Total UI for P1: 0, mck2ui 16
5898 22:14:31.734171 best dqsien dly found for B1: ( 1, 2, 24)
5899 22:14:31.736886 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5900 22:14:31.740844 Total UI for P1: 0, mck2ui 16
5901 22:14:31.743612 best dqsien dly found for B0: ( 1, 2, 28)
5902 22:14:31.746890 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5903 22:14:31.750333 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5904 22:14:31.750436
5905 22:14:31.753793 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5906 22:14:31.756789 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5907 22:14:31.760277 [Gating] SW calibration Done
5908 22:14:31.760377 ==
5909 22:14:31.763513 Dram Type= 6, Freq= 0, CH_1, rank 1
5910 22:14:31.770122 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5911 22:14:31.770228 ==
5912 22:14:31.770318 RX Vref Scan: 0
5913 22:14:31.770410
5914 22:14:31.773239 RX Vref 0 -> 0, step: 1
5915 22:14:31.773311
5916 22:14:31.776575 RX Delay -80 -> 252, step: 8
5917 22:14:31.780036 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5918 22:14:31.783089 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5919 22:14:31.786715 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5920 22:14:31.789739 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5921 22:14:31.793583 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5922 22:14:31.799812 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5923 22:14:31.803269 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5924 22:14:31.806530 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5925 22:14:31.809575 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5926 22:14:31.812979 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5927 22:14:31.819522 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5928 22:14:31.822762 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5929 22:14:31.826405 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5930 22:14:31.830479 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5931 22:14:31.833453 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5932 22:14:31.839199 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5933 22:14:31.839272 ==
5934 22:14:31.842784 Dram Type= 6, Freq= 0, CH_1, rank 1
5935 22:14:31.846168 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5936 22:14:31.846271 ==
5937 22:14:31.846362 DQS Delay:
5938 22:14:31.849078 DQS0 = 0, DQS1 = 0
5939 22:14:31.849151 DQM Delay:
5940 22:14:31.852652 DQM0 = 102, DQM1 = 92
5941 22:14:31.852723 DQ Delay:
5942 22:14:31.856057 DQ0 =107, DQ1 =99, DQ2 =91, DQ3 =99
5943 22:14:31.859095 DQ4 =95, DQ5 =115, DQ6 =111, DQ7 =99
5944 22:14:31.862565 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =83
5945 22:14:31.865583 DQ12 =103, DQ13 =103, DQ14 =99, DQ15 =103
5946 22:14:31.865652
5947 22:14:31.865712
5948 22:14:31.865771 ==
5949 22:14:31.868759 Dram Type= 6, Freq= 0, CH_1, rank 1
5950 22:14:31.875810 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5951 22:14:31.875886 ==
5952 22:14:31.875953
5953 22:14:31.876012
5954 22:14:31.876069 TX Vref Scan disable
5955 22:14:31.879427 == TX Byte 0 ==
5956 22:14:31.883053 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5957 22:14:31.889084 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5958 22:14:31.889157 == TX Byte 1 ==
5959 22:14:31.892673 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5960 22:14:31.898901 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5961 22:14:31.898978 ==
5962 22:14:31.902567 Dram Type= 6, Freq= 0, CH_1, rank 1
5963 22:14:31.905808 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5964 22:14:31.905880 ==
5965 22:14:31.905944
5966 22:14:31.906003
5967 22:14:31.909204 TX Vref Scan disable
5968 22:14:31.909273 == TX Byte 0 ==
5969 22:14:31.915476 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5970 22:14:31.918831 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5971 22:14:31.918930 == TX Byte 1 ==
5972 22:14:31.925773 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5973 22:14:31.929218 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5974 22:14:31.929291
5975 22:14:31.929354 [DATLAT]
5976 22:14:31.932572 Freq=933, CH1 RK1
5977 22:14:31.932670
5978 22:14:31.932759 DATLAT Default: 0xb
5979 22:14:31.935892 0, 0xFFFF, sum = 0
5980 22:14:31.935997 1, 0xFFFF, sum = 0
5981 22:14:31.938539 2, 0xFFFF, sum = 0
5982 22:14:31.941919 3, 0xFFFF, sum = 0
5983 22:14:31.941995 4, 0xFFFF, sum = 0
5984 22:14:31.945141 5, 0xFFFF, sum = 0
5985 22:14:31.945222 6, 0xFFFF, sum = 0
5986 22:14:31.949064 7, 0xFFFF, sum = 0
5987 22:14:31.949138 8, 0xFFFF, sum = 0
5988 22:14:31.951857 9, 0xFFFF, sum = 0
5989 22:14:31.951942 10, 0x0, sum = 1
5990 22:14:31.955478 11, 0x0, sum = 2
5991 22:14:31.955560 12, 0x0, sum = 3
5992 22:14:31.959327 13, 0x0, sum = 4
5993 22:14:31.959448 best_step = 11
5994 22:14:31.959513
5995 22:14:31.959573 ==
5996 22:14:31.961996 Dram Type= 6, Freq= 0, CH_1, rank 1
5997 22:14:31.965418 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5998 22:14:31.965500 ==
5999 22:14:31.968868 RX Vref Scan: 0
6000 22:14:31.968949
6001 22:14:31.971797 RX Vref 0 -> 0, step: 1
6002 22:14:31.971878
6003 22:14:31.971958 RX Delay -61 -> 252, step: 4
6004 22:14:31.979429 iDelay=207, Bit 0, Center 104 (15 ~ 194) 180
6005 22:14:31.983357 iDelay=207, Bit 1, Center 96 (11 ~ 182) 172
6006 22:14:31.986596 iDelay=207, Bit 2, Center 90 (3 ~ 178) 176
6007 22:14:31.989692 iDelay=207, Bit 3, Center 98 (15 ~ 182) 168
6008 22:14:31.992914 iDelay=207, Bit 4, Center 100 (11 ~ 190) 180
6009 22:14:31.999771 iDelay=207, Bit 5, Center 112 (27 ~ 198) 172
6010 22:14:32.002902 iDelay=207, Bit 6, Center 118 (31 ~ 206) 176
6011 22:14:32.006368 iDelay=207, Bit 7, Center 98 (7 ~ 190) 184
6012 22:14:32.009244 iDelay=207, Bit 8, Center 84 (-5 ~ 174) 180
6013 22:14:32.013079 iDelay=207, Bit 9, Center 84 (-5 ~ 174) 180
6014 22:14:32.016151 iDelay=207, Bit 10, Center 94 (3 ~ 186) 184
6015 22:14:32.022621 iDelay=207, Bit 11, Center 84 (-5 ~ 174) 180
6016 22:14:32.026149 iDelay=207, Bit 12, Center 102 (11 ~ 194) 184
6017 22:14:32.029185 iDelay=207, Bit 13, Center 102 (11 ~ 194) 184
6018 22:14:32.032822 iDelay=207, Bit 14, Center 102 (11 ~ 194) 184
6019 22:14:32.039308 iDelay=207, Bit 15, Center 102 (11 ~ 194) 184
6020 22:14:32.039404 ==
6021 22:14:32.042670 Dram Type= 6, Freq= 0, CH_1, rank 1
6022 22:14:32.045670 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
6023 22:14:32.045751 ==
6024 22:14:32.045845 DQS Delay:
6025 22:14:32.049466 DQS0 = 0, DQS1 = 0
6026 22:14:32.049536 DQM Delay:
6027 22:14:32.052477 DQM0 = 102, DQM1 = 94
6028 22:14:32.052579 DQ Delay:
6029 22:14:32.056252 DQ0 =104, DQ1 =96, DQ2 =90, DQ3 =98
6030 22:14:32.059075 DQ4 =100, DQ5 =112, DQ6 =118, DQ7 =98
6031 22:14:32.062307 DQ8 =84, DQ9 =84, DQ10 =94, DQ11 =84
6032 22:14:32.065928 DQ12 =102, DQ13 =102, DQ14 =102, DQ15 =102
6033 22:14:32.066040
6034 22:14:32.066103
6035 22:14:32.075536 [DQSOSCAuto] RK1, (LSB)MR18= 0xc05, (MSB)MR19= 0x505, tDQSOscB0 = 420 ps tDQSOscB1 = 418 ps
6036 22:14:32.075622 CH1 RK1: MR19=505, MR18=C05
6037 22:14:32.082348 CH1_RK1: MR19=0x505, MR18=0xC05, DQSOSC=418, MR23=63, INC=62, DEC=41
6038 22:14:32.085658 [RxdqsGatingPostProcess] freq 933
6039 22:14:32.092009 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
6040 22:14:32.095357 best DQS0 dly(2T, 0.5T) = (0, 10)
6041 22:14:32.098867 best DQS1 dly(2T, 0.5T) = (0, 10)
6042 22:14:32.102298 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6043 22:14:32.105271 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6044 22:14:32.108443 best DQS0 dly(2T, 0.5T) = (0, 10)
6045 22:14:32.108533 best DQS1 dly(2T, 0.5T) = (0, 10)
6046 22:14:32.112228 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6047 22:14:32.115257 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6048 22:14:32.118665 Pre-setting of DQS Precalculation
6049 22:14:32.125465 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6050 22:14:32.131825 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6051 22:14:32.138611 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6052 22:14:32.138693
6053 22:14:32.138756
6054 22:14:32.141627 [Calibration Summary] 1866 Mbps
6055 22:14:32.145190 CH 0, Rank 0
6056 22:14:32.145292 SW Impedance : PASS
6057 22:14:32.148442 DUTY Scan : NO K
6058 22:14:32.151781 ZQ Calibration : PASS
6059 22:14:32.151862 Jitter Meter : NO K
6060 22:14:32.155018 CBT Training : PASS
6061 22:14:32.155099 Write leveling : PASS
6062 22:14:32.157999 RX DQS gating : PASS
6063 22:14:32.161371 RX DQ/DQS(RDDQC) : PASS
6064 22:14:32.161453 TX DQ/DQS : PASS
6065 22:14:32.165304 RX DATLAT : PASS
6066 22:14:32.167900 RX DQ/DQS(Engine): PASS
6067 22:14:32.167981 TX OE : NO K
6068 22:14:32.171409 All Pass.
6069 22:14:32.171490
6070 22:14:32.171555 CH 0, Rank 1
6071 22:14:32.174529 SW Impedance : PASS
6072 22:14:32.174611 DUTY Scan : NO K
6073 22:14:32.178541 ZQ Calibration : PASS
6074 22:14:32.181687 Jitter Meter : NO K
6075 22:14:32.181768 CBT Training : PASS
6076 22:14:32.184717 Write leveling : PASS
6077 22:14:32.188653 RX DQS gating : PASS
6078 22:14:32.188734 RX DQ/DQS(RDDQC) : PASS
6079 22:14:32.191352 TX DQ/DQS : PASS
6080 22:14:32.194792 RX DATLAT : PASS
6081 22:14:32.194873 RX DQ/DQS(Engine): PASS
6082 22:14:32.197923 TX OE : NO K
6083 22:14:32.198005 All Pass.
6084 22:14:32.198085
6085 22:14:32.201132 CH 1, Rank 0
6086 22:14:32.201214 SW Impedance : PASS
6087 22:14:32.204252 DUTY Scan : NO K
6088 22:14:32.207412 ZQ Calibration : PASS
6089 22:14:32.207493 Jitter Meter : NO K
6090 22:14:32.211380 CBT Training : PASS
6091 22:14:32.213996 Write leveling : PASS
6092 22:14:32.214078 RX DQS gating : PASS
6093 22:14:32.217448 RX DQ/DQS(RDDQC) : PASS
6094 22:14:32.220679 TX DQ/DQS : PASS
6095 22:14:32.220761 RX DATLAT : PASS
6096 22:14:32.224193 RX DQ/DQS(Engine): PASS
6097 22:14:32.227436 TX OE : NO K
6098 22:14:32.227519 All Pass.
6099 22:14:32.227583
6100 22:14:32.227641 CH 1, Rank 1
6101 22:14:32.230363 SW Impedance : PASS
6102 22:14:32.233637 DUTY Scan : NO K
6103 22:14:32.233733 ZQ Calibration : PASS
6104 22:14:32.237139 Jitter Meter : NO K
6105 22:14:32.237220 CBT Training : PASS
6106 22:14:32.240500 Write leveling : PASS
6107 22:14:32.244088 RX DQS gating : PASS
6108 22:14:32.244169 RX DQ/DQS(RDDQC) : PASS
6109 22:14:32.247098 TX DQ/DQS : PASS
6110 22:14:32.250451 RX DATLAT : PASS
6111 22:14:32.250532 RX DQ/DQS(Engine): PASS
6112 22:14:32.253650 TX OE : NO K
6113 22:14:32.253732 All Pass.
6114 22:14:32.253796
6115 22:14:32.257302 DramC Write-DBI off
6116 22:14:32.260204 PER_BANK_REFRESH: Hybrid Mode
6117 22:14:32.260286 TX_TRACKING: ON
6118 22:14:32.270017 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6119 22:14:32.273723 [FAST_K] Save calibration result to emmc
6120 22:14:32.277331 dramc_set_vcore_voltage set vcore to 650000
6121 22:14:32.280125 Read voltage for 400, 6
6122 22:14:32.280206 Vio18 = 0
6123 22:14:32.280269 Vcore = 650000
6124 22:14:32.283657 Vdram = 0
6125 22:14:32.283738 Vddq = 0
6126 22:14:32.283803 Vmddr = 0
6127 22:14:32.290027 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6128 22:14:32.293654 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6129 22:14:32.296942 MEM_TYPE=3, freq_sel=20
6130 22:14:32.300175 sv_algorithm_assistance_LP4_800
6131 22:14:32.303225 ============ PULL DRAM RESETB DOWN ============
6132 22:14:32.307144 ========== PULL DRAM RESETB DOWN end =========
6133 22:14:32.313400 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6134 22:14:32.316617 ===================================
6135 22:14:32.319812 LPDDR4 DRAM CONFIGURATION
6136 22:14:32.323671 ===================================
6137 22:14:32.323753 EX_ROW_EN[0] = 0x0
6138 22:14:32.326716 EX_ROW_EN[1] = 0x0
6139 22:14:32.326797 LP4Y_EN = 0x0
6140 22:14:32.330137 WORK_FSP = 0x0
6141 22:14:32.330258 WL = 0x2
6142 22:14:32.333560 RL = 0x2
6143 22:14:32.333641 BL = 0x2
6144 22:14:32.336688 RPST = 0x0
6145 22:14:32.336818 RD_PRE = 0x0
6146 22:14:32.339913 WR_PRE = 0x1
6147 22:14:32.339994 WR_PST = 0x0
6148 22:14:32.343304 DBI_WR = 0x0
6149 22:14:32.343385 DBI_RD = 0x0
6150 22:14:32.346756 OTF = 0x1
6151 22:14:32.350201 ===================================
6152 22:14:32.353175 ===================================
6153 22:14:32.353257 ANA top config
6154 22:14:32.356528 ===================================
6155 22:14:32.359892 DLL_ASYNC_EN = 0
6156 22:14:32.363960 ALL_SLAVE_EN = 1
6157 22:14:32.366769 NEW_RANK_MODE = 1
6158 22:14:32.366852 DLL_IDLE_MODE = 1
6159 22:14:32.370135 LP45_APHY_COMB_EN = 1
6160 22:14:32.373717 TX_ODT_DIS = 1
6161 22:14:32.376505 NEW_8X_MODE = 1
6162 22:14:32.379818 ===================================
6163 22:14:32.383444 ===================================
6164 22:14:32.386828 data_rate = 800
6165 22:14:32.386910 CKR = 1
6166 22:14:32.389812 DQ_P2S_RATIO = 4
6167 22:14:32.393057 ===================================
6168 22:14:32.396577 CA_P2S_RATIO = 4
6169 22:14:32.399826 DQ_CA_OPEN = 0
6170 22:14:32.403345 DQ_SEMI_OPEN = 1
6171 22:14:32.406720 CA_SEMI_OPEN = 1
6172 22:14:32.406801 CA_FULL_RATE = 0
6173 22:14:32.409547 DQ_CKDIV4_EN = 0
6174 22:14:32.412994 CA_CKDIV4_EN = 1
6175 22:14:32.416541 CA_PREDIV_EN = 0
6176 22:14:32.419866 PH8_DLY = 0
6177 22:14:32.423191 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6178 22:14:32.423273 DQ_AAMCK_DIV = 0
6179 22:14:32.426445 CA_AAMCK_DIV = 0
6180 22:14:32.429557 CA_ADMCK_DIV = 4
6181 22:14:32.432773 DQ_TRACK_CA_EN = 0
6182 22:14:32.436102 CA_PICK = 800
6183 22:14:32.439302 CA_MCKIO = 400
6184 22:14:32.442430 MCKIO_SEMI = 400
6185 22:14:32.446120 PLL_FREQ = 3016
6186 22:14:32.446202 DQ_UI_PI_RATIO = 32
6187 22:14:32.449697 CA_UI_PI_RATIO = 32
6188 22:14:32.452773 ===================================
6189 22:14:32.455915 ===================================
6190 22:14:32.459251 memory_type:LPDDR4
6191 22:14:32.462458 GP_NUM : 10
6192 22:14:32.462540 SRAM_EN : 1
6193 22:14:32.466058 MD32_EN : 0
6194 22:14:32.469317 ===================================
6195 22:14:32.472448 [ANA_INIT] >>>>>>>>>>>>>>
6196 22:14:32.475476 <<<<<< [CONFIGURE PHASE]: ANA_TX
6197 22:14:32.478955 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6198 22:14:32.482102 ===================================
6199 22:14:32.482183 data_rate = 800,PCW = 0X7400
6200 22:14:32.485397 ===================================
6201 22:14:32.488924 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6202 22:14:32.495174 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6203 22:14:32.508732 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6204 22:14:32.511721 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6205 22:14:32.515229 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6206 22:14:32.518831 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6207 22:14:32.522301 [ANA_INIT] flow start
6208 22:14:32.522378 [ANA_INIT] PLL >>>>>>>>
6209 22:14:32.525495 [ANA_INIT] PLL <<<<<<<<
6210 22:14:32.528200 [ANA_INIT] MIDPI >>>>>>>>
6211 22:14:32.528271 [ANA_INIT] MIDPI <<<<<<<<
6212 22:14:32.531831 [ANA_INIT] DLL >>>>>>>>
6213 22:14:32.535724 [ANA_INIT] flow end
6214 22:14:32.538540 ============ LP4 DIFF to SE enter ============
6215 22:14:32.541576 ============ LP4 DIFF to SE exit ============
6216 22:14:32.545032 [ANA_INIT] <<<<<<<<<<<<<
6217 22:14:32.548308 [Flow] Enable top DCM control >>>>>
6218 22:14:32.551683 [Flow] Enable top DCM control <<<<<
6219 22:14:32.554755 Enable DLL master slave shuffle
6220 22:14:32.558196 ==============================================================
6221 22:14:32.562242 Gating Mode config
6222 22:14:32.567943 ==============================================================
6223 22:14:32.568021 Config description:
6224 22:14:32.577898 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6225 22:14:32.584716 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6226 22:14:32.590931 SELPH_MODE 0: By rank 1: By Phase
6227 22:14:32.594371 ==============================================================
6228 22:14:32.597545 GAT_TRACK_EN = 0
6229 22:14:32.600810 RX_GATING_MODE = 2
6230 22:14:32.604609 RX_GATING_TRACK_MODE = 2
6231 22:14:32.607618 SELPH_MODE = 1
6232 22:14:32.610825 PICG_EARLY_EN = 1
6233 22:14:32.613754 VALID_LAT_VALUE = 1
6234 22:14:32.620573 ==============================================================
6235 22:14:32.623802 Enter into Gating configuration >>>>
6236 22:14:32.626993 Exit from Gating configuration <<<<
6237 22:14:32.630816 Enter into DVFS_PRE_config >>>>>
6238 22:14:32.640639 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6239 22:14:32.643869 Exit from DVFS_PRE_config <<<<<
6240 22:14:32.646927 Enter into PICG configuration >>>>
6241 22:14:32.650487 Exit from PICG configuration <<<<
6242 22:14:32.653557 [RX_INPUT] configuration >>>>>
6243 22:14:32.653638 [RX_INPUT] configuration <<<<<
6244 22:14:32.660070 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6245 22:14:32.666923 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6246 22:14:32.669992 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6247 22:14:32.676668 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6248 22:14:32.683395 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6249 22:14:32.690018 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6250 22:14:32.693121 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6251 22:14:32.696932 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6252 22:14:32.702766 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6253 22:14:32.706375 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6254 22:14:32.709350 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6255 22:14:32.715912 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6256 22:14:32.719696 ===================================
6257 22:14:32.719804 LPDDR4 DRAM CONFIGURATION
6258 22:14:32.722488 ===================================
6259 22:14:32.726508 EX_ROW_EN[0] = 0x0
6260 22:14:32.729577 EX_ROW_EN[1] = 0x0
6261 22:14:32.729658 LP4Y_EN = 0x0
6262 22:14:32.732875 WORK_FSP = 0x0
6263 22:14:32.732960 WL = 0x2
6264 22:14:32.735871 RL = 0x2
6265 22:14:32.735952 BL = 0x2
6266 22:14:32.739022 RPST = 0x0
6267 22:14:32.739104 RD_PRE = 0x0
6268 22:14:32.742727 WR_PRE = 0x1
6269 22:14:32.742823 WR_PST = 0x0
6270 22:14:32.745921 DBI_WR = 0x0
6271 22:14:32.746002 DBI_RD = 0x0
6272 22:14:32.749383 OTF = 0x1
6273 22:14:32.752279 ===================================
6274 22:14:32.755648 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6275 22:14:32.759441 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6276 22:14:32.765684 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6277 22:14:32.769485 ===================================
6278 22:14:32.769567 LPDDR4 DRAM CONFIGURATION
6279 22:14:32.772624 ===================================
6280 22:14:32.776158 EX_ROW_EN[0] = 0x10
6281 22:14:32.776239 EX_ROW_EN[1] = 0x0
6282 22:14:32.779000 LP4Y_EN = 0x0
6283 22:14:32.782219 WORK_FSP = 0x0
6284 22:14:32.782300 WL = 0x2
6285 22:14:32.785591 RL = 0x2
6286 22:14:32.785672 BL = 0x2
6287 22:14:32.789180 RPST = 0x0
6288 22:14:32.789261 RD_PRE = 0x0
6289 22:14:32.792405 WR_PRE = 0x1
6290 22:14:32.792512 WR_PST = 0x0
6291 22:14:32.795360 DBI_WR = 0x0
6292 22:14:32.795441 DBI_RD = 0x0
6293 22:14:32.798906 OTF = 0x1
6294 22:14:32.802183 ===================================
6295 22:14:32.808441 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6296 22:14:32.811912 nWR fixed to 30
6297 22:14:32.811995 [ModeRegInit_LP4] CH0 RK0
6298 22:14:32.814943 [ModeRegInit_LP4] CH0 RK1
6299 22:14:32.818656 [ModeRegInit_LP4] CH1 RK0
6300 22:14:32.821523 [ModeRegInit_LP4] CH1 RK1
6301 22:14:32.821604 match AC timing 19
6302 22:14:32.828468 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6303 22:14:32.831414 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6304 22:14:32.834973 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6305 22:14:32.841405 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6306 22:14:32.844682 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6307 22:14:32.844786 ==
6308 22:14:32.848144 Dram Type= 6, Freq= 0, CH_0, rank 0
6309 22:14:32.851362 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6310 22:14:32.851459 ==
6311 22:14:32.857799 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6312 22:14:32.864450 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6313 22:14:32.867882 [CA 0] Center 36 (8~64) winsize 57
6314 22:14:32.871516 [CA 1] Center 36 (8~64) winsize 57
6315 22:14:32.874380 [CA 2] Center 36 (8~64) winsize 57
6316 22:14:32.877674 [CA 3] Center 36 (8~64) winsize 57
6317 22:14:32.877749 [CA 4] Center 36 (8~64) winsize 57
6318 22:14:32.880700 [CA 5] Center 36 (8~64) winsize 57
6319 22:14:32.880786
6320 22:14:32.887258 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6321 22:14:32.887355
6322 22:14:32.890810 [CATrainingPosCal] consider 1 rank data
6323 22:14:32.893906 u2DelayCellTimex100 = 270/100 ps
6324 22:14:32.897159 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6325 22:14:32.900414 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6326 22:14:32.903588 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6327 22:14:32.906959 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6328 22:14:32.910618 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6329 22:14:32.913685 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6330 22:14:32.913769
6331 22:14:32.916812 CA PerBit enable=1, Macro0, CA PI delay=36
6332 22:14:32.920394
6333 22:14:32.920478 [CBTSetCACLKResult] CA Dly = 36
6334 22:14:32.923826 CS Dly: 1 (0~32)
6335 22:14:32.923909 ==
6336 22:14:32.927074 Dram Type= 6, Freq= 0, CH_0, rank 1
6337 22:14:32.930161 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6338 22:14:32.930246 ==
6339 22:14:32.936494 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6340 22:14:32.943244 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6341 22:14:32.946999 [CA 0] Center 36 (8~64) winsize 57
6342 22:14:32.949804 [CA 1] Center 36 (8~64) winsize 57
6343 22:14:32.953466 [CA 2] Center 36 (8~64) winsize 57
6344 22:14:32.953584 [CA 3] Center 36 (8~64) winsize 57
6345 22:14:32.956452 [CA 4] Center 36 (8~64) winsize 57
6346 22:14:32.959535 [CA 5] Center 36 (8~64) winsize 57
6347 22:14:32.959632
6348 22:14:32.966479 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6349 22:14:32.966557
6350 22:14:32.969871 [CATrainingPosCal] consider 2 rank data
6351 22:14:32.973189 u2DelayCellTimex100 = 270/100 ps
6352 22:14:32.976696 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6353 22:14:32.979500 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6354 22:14:32.982758 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6355 22:14:32.985788 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6356 22:14:32.989761 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6357 22:14:32.992652 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6358 22:14:32.992725
6359 22:14:32.995648 CA PerBit enable=1, Macro0, CA PI delay=36
6360 22:14:32.995747
6361 22:14:32.999531 [CBTSetCACLKResult] CA Dly = 36
6362 22:14:33.002678 CS Dly: 1 (0~32)
6363 22:14:33.002774
6364 22:14:33.005902 ----->DramcWriteLeveling(PI) begin...
6365 22:14:33.005975 ==
6366 22:14:33.009334 Dram Type= 6, Freq= 0, CH_0, rank 0
6367 22:14:33.012201 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6368 22:14:33.012302 ==
6369 22:14:33.015969 Write leveling (Byte 0): 40 => 8
6370 22:14:33.019151 Write leveling (Byte 1): 32 => 0
6371 22:14:33.022414 DramcWriteLeveling(PI) end<-----
6372 22:14:33.022516
6373 22:14:33.022607 ==
6374 22:14:33.025416 Dram Type= 6, Freq= 0, CH_0, rank 0
6375 22:14:33.028834 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6376 22:14:33.028933 ==
6377 22:14:33.031855 [Gating] SW mode calibration
6378 22:14:33.038780 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6379 22:14:33.045170 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6380 22:14:33.048645 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6381 22:14:33.055281 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6382 22:14:33.058376 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6383 22:14:33.062304 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6384 22:14:33.068452 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6385 22:14:33.071624 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6386 22:14:33.074913 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6387 22:14:33.081389 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6388 22:14:33.084923 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6389 22:14:33.087883 Total UI for P1: 0, mck2ui 16
6390 22:14:33.091545 best dqsien dly found for B0: ( 0, 14, 24)
6391 22:14:33.094480 Total UI for P1: 0, mck2ui 16
6392 22:14:33.097917 best dqsien dly found for B1: ( 0, 14, 24)
6393 22:14:33.101407 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6394 22:14:33.104634 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6395 22:14:33.104710
6396 22:14:33.107949 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6397 22:14:33.110895 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6398 22:14:33.114599 [Gating] SW calibration Done
6399 22:14:33.114703 ==
6400 22:14:33.117734 Dram Type= 6, Freq= 0, CH_0, rank 0
6401 22:14:33.124630 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6402 22:14:33.124708 ==
6403 22:14:33.124772 RX Vref Scan: 0
6404 22:14:33.124835
6405 22:14:33.127397 RX Vref 0 -> 0, step: 1
6406 22:14:33.127498
6407 22:14:33.130884 RX Delay -410 -> 252, step: 16
6408 22:14:33.134102 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6409 22:14:33.137385 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6410 22:14:33.143913 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6411 22:14:33.147283 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6412 22:14:33.150531 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6413 22:14:33.154386 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6414 22:14:33.160748 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6415 22:14:33.164218 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6416 22:14:33.167218 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6417 22:14:33.170279 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6418 22:14:33.177088 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6419 22:14:33.180465 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6420 22:14:33.183497 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6421 22:14:33.187133 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6422 22:14:33.193819 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6423 22:14:33.196732 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6424 22:14:33.196814 ==
6425 22:14:33.200302 Dram Type= 6, Freq= 0, CH_0, rank 0
6426 22:14:33.203358 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6427 22:14:33.203462 ==
6428 22:14:33.206757 DQS Delay:
6429 22:14:33.206859 DQS0 = 43, DQS1 = 59
6430 22:14:33.210461 DQM Delay:
6431 22:14:33.210561 DQM0 = 10, DQM1 = 12
6432 22:14:33.213210 DQ Delay:
6433 22:14:33.213339 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6434 22:14:33.216679 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6435 22:14:33.220080 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6436 22:14:33.223030 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6437 22:14:33.223128
6438 22:14:33.223221
6439 22:14:33.223308 ==
6440 22:14:33.226793 Dram Type= 6, Freq= 0, CH_0, rank 0
6441 22:14:33.233257 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6442 22:14:33.233363 ==
6443 22:14:33.233454
6444 22:14:33.233544
6445 22:14:33.233632 TX Vref Scan disable
6446 22:14:33.236433 == TX Byte 0 ==
6447 22:14:33.239591 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6448 22:14:33.243469 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6449 22:14:33.246408 == TX Byte 1 ==
6450 22:14:33.249498 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6451 22:14:33.256255 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6452 22:14:33.256361 ==
6453 22:14:33.259413 Dram Type= 6, Freq= 0, CH_0, rank 0
6454 22:14:33.262729 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6455 22:14:33.262831 ==
6456 22:14:33.262922
6457 22:14:33.262985
6458 22:14:33.265986 TX Vref Scan disable
6459 22:14:33.266083 == TX Byte 0 ==
6460 22:14:33.269475 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6461 22:14:33.276166 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6462 22:14:33.276257 == TX Byte 1 ==
6463 22:14:33.279250 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6464 22:14:33.285634 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6465 22:14:33.285715
6466 22:14:33.285780 [DATLAT]
6467 22:14:33.289737 Freq=400, CH0 RK0
6468 22:14:33.289833
6469 22:14:33.289897 DATLAT Default: 0xf
6470 22:14:33.292690 0, 0xFFFF, sum = 0
6471 22:14:33.292816 1, 0xFFFF, sum = 0
6472 22:14:33.296130 2, 0xFFFF, sum = 0
6473 22:14:33.296207 3, 0xFFFF, sum = 0
6474 22:14:33.298974 4, 0xFFFF, sum = 0
6475 22:14:33.299050 5, 0xFFFF, sum = 0
6476 22:14:33.302289 6, 0xFFFF, sum = 0
6477 22:14:33.302365 7, 0xFFFF, sum = 0
6478 22:14:33.305988 8, 0xFFFF, sum = 0
6479 22:14:33.306066 9, 0xFFFF, sum = 0
6480 22:14:33.309475 10, 0xFFFF, sum = 0
6481 22:14:33.309554 11, 0xFFFF, sum = 0
6482 22:14:33.312450 12, 0xFFFF, sum = 0
6483 22:14:33.312583 13, 0x0, sum = 1
6484 22:14:33.315915 14, 0x0, sum = 2
6485 22:14:33.316014 15, 0x0, sum = 3
6486 22:14:33.319054 16, 0x0, sum = 4
6487 22:14:33.319138 best_step = 14
6488 22:14:33.319232
6489 22:14:33.319320 ==
6490 22:14:33.322505 Dram Type= 6, Freq= 0, CH_0, rank 0
6491 22:14:33.328673 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6492 22:14:33.328748 ==
6493 22:14:33.328822 RX Vref Scan: 1
6494 22:14:33.328882
6495 22:14:33.332041 RX Vref 0 -> 0, step: 1
6496 22:14:33.332160
6497 22:14:33.335397 RX Delay -359 -> 252, step: 8
6498 22:14:33.335497
6499 22:14:33.338521 Set Vref, RX VrefLevel [Byte0]: 59
6500 22:14:33.342432 [Byte1]: 49
6501 22:14:33.345587
6502 22:14:33.345701 Final RX Vref Byte 0 = 59 to rank0
6503 22:14:33.348926 Final RX Vref Byte 1 = 49 to rank0
6504 22:14:33.351769 Final RX Vref Byte 0 = 59 to rank1
6505 22:14:33.355122 Final RX Vref Byte 1 = 49 to rank1==
6506 22:14:33.358426 Dram Type= 6, Freq= 0, CH_0, rank 0
6507 22:14:33.365091 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6508 22:14:33.365189 ==
6509 22:14:33.365254 DQS Delay:
6510 22:14:33.368199 DQS0 = 48, DQS1 = 60
6511 22:14:33.368279 DQM Delay:
6512 22:14:33.368343 DQM0 = 12, DQM1 = 12
6513 22:14:33.371855 DQ Delay:
6514 22:14:33.375233 DQ0 =12, DQ1 =16, DQ2 =8, DQ3 =8
6515 22:14:33.378134 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6516 22:14:33.378242 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =4
6517 22:14:33.384735 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6518 22:14:33.384817
6519 22:14:33.384880
6520 22:14:33.391431 [DQSOSCAuto] RK0, (LSB)MR18= 0xbf81, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 386 ps
6521 22:14:33.395138 CH0 RK0: MR19=C0C, MR18=BF81
6522 22:14:33.401832 CH0_RK0: MR19=0xC0C, MR18=0xBF81, DQSOSC=386, MR23=63, INC=396, DEC=264
6523 22:14:33.401914 ==
6524 22:14:33.404991 Dram Type= 6, Freq= 0, CH_0, rank 1
6525 22:14:33.408263 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6526 22:14:33.408345 ==
6527 22:14:33.412132 [Gating] SW mode calibration
6528 22:14:33.418355 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6529 22:14:33.424562 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6530 22:14:33.427801 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6531 22:14:33.431355 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6532 22:14:33.438171 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6533 22:14:33.441457 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6534 22:14:33.444632 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6535 22:14:33.451397 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6536 22:14:33.454340 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6537 22:14:33.457956 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6538 22:14:33.464562 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6539 22:14:33.464645 Total UI for P1: 0, mck2ui 16
6540 22:14:33.470906 best dqsien dly found for B0: ( 0, 14, 24)
6541 22:14:33.470983 Total UI for P1: 0, mck2ui 16
6542 22:14:33.477863 best dqsien dly found for B1: ( 0, 14, 24)
6543 22:14:33.480474 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6544 22:14:33.484201 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6545 22:14:33.484284
6546 22:14:33.487503 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6547 22:14:33.490477 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6548 22:14:33.494178 [Gating] SW calibration Done
6549 22:14:33.494259 ==
6550 22:14:33.497045 Dram Type= 6, Freq= 0, CH_0, rank 1
6551 22:14:33.500423 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6552 22:14:33.500573 ==
6553 22:14:33.504111 RX Vref Scan: 0
6554 22:14:33.504246
6555 22:14:33.504342 RX Vref 0 -> 0, step: 1
6556 22:14:33.507388
6557 22:14:33.507469 RX Delay -410 -> 252, step: 16
6558 22:14:33.513706 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6559 22:14:33.517045 iDelay=230, Bit 1, Center -27 (-282 ~ 229) 512
6560 22:14:33.520359 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6561 22:14:33.523823 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6562 22:14:33.530425 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6563 22:14:33.533536 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6564 22:14:33.537177 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6565 22:14:33.540014 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6566 22:14:33.547194 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6567 22:14:33.550132 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6568 22:14:33.553396 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6569 22:14:33.559782 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6570 22:14:33.563102 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6571 22:14:33.566483 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6572 22:14:33.569934 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6573 22:14:33.576144 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6574 22:14:33.576226 ==
6575 22:14:33.580000 Dram Type= 6, Freq= 0, CH_0, rank 1
6576 22:14:33.582735 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6577 22:14:33.582817 ==
6578 22:14:33.582881 DQS Delay:
6579 22:14:33.585974 DQS0 = 43, DQS1 = 59
6580 22:14:33.586056 DQM Delay:
6581 22:14:33.589348 DQM0 = 10, DQM1 = 16
6582 22:14:33.589430 DQ Delay:
6583 22:14:33.592886 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6584 22:14:33.596147 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6585 22:14:33.599878 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6586 22:14:33.603241 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6587 22:14:33.603342
6588 22:14:33.603409
6589 22:14:33.603468 ==
6590 22:14:33.606233 Dram Type= 6, Freq= 0, CH_0, rank 1
6591 22:14:33.609558 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6592 22:14:33.609640 ==
6593 22:14:33.609704
6594 22:14:33.609763
6595 22:14:33.612760 TX Vref Scan disable
6596 22:14:33.616045 == TX Byte 0 ==
6597 22:14:33.619652 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6598 22:14:33.622966 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6599 22:14:33.626266 == TX Byte 1 ==
6600 22:14:33.629139 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6601 22:14:33.632811 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6602 22:14:33.632893 ==
6603 22:14:33.636046 Dram Type= 6, Freq= 0, CH_0, rank 1
6604 22:14:33.639301 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6605 22:14:33.639382 ==
6606 22:14:33.642349
6607 22:14:33.642430
6608 22:14:33.642494 TX Vref Scan disable
6609 22:14:33.646031 == TX Byte 0 ==
6610 22:14:33.648996 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6611 22:14:33.652412 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6612 22:14:33.655976 == TX Byte 1 ==
6613 22:14:33.658997 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6614 22:14:33.662534 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6615 22:14:33.662615
6616 22:14:33.662679 [DATLAT]
6617 22:14:33.665914 Freq=400, CH0 RK1
6618 22:14:33.665996
6619 22:14:33.668760 DATLAT Default: 0xe
6620 22:14:33.668841 0, 0xFFFF, sum = 0
6621 22:14:33.672102 1, 0xFFFF, sum = 0
6622 22:14:33.672243 2, 0xFFFF, sum = 0
6623 22:14:33.675650 3, 0xFFFF, sum = 0
6624 22:14:33.675733 4, 0xFFFF, sum = 0
6625 22:14:33.678560 5, 0xFFFF, sum = 0
6626 22:14:33.678643 6, 0xFFFF, sum = 0
6627 22:14:33.681829 7, 0xFFFF, sum = 0
6628 22:14:33.681911 8, 0xFFFF, sum = 0
6629 22:14:33.685561 9, 0xFFFF, sum = 0
6630 22:14:33.685644 10, 0xFFFF, sum = 0
6631 22:14:33.688615 11, 0xFFFF, sum = 0
6632 22:14:33.688697 12, 0xFFFF, sum = 0
6633 22:14:33.691876 13, 0x0, sum = 1
6634 22:14:33.691958 14, 0x0, sum = 2
6635 22:14:33.695207 15, 0x0, sum = 3
6636 22:14:33.695289 16, 0x0, sum = 4
6637 22:14:33.698862 best_step = 14
6638 22:14:33.698943
6639 22:14:33.699007 ==
6640 22:14:33.702251 Dram Type= 6, Freq= 0, CH_0, rank 1
6641 22:14:33.706009 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6642 22:14:33.706090 ==
6643 22:14:33.708287 RX Vref Scan: 0
6644 22:14:33.708368
6645 22:14:33.708432 RX Vref 0 -> 0, step: 1
6646 22:14:33.708492
6647 22:14:33.711810 RX Delay -359 -> 252, step: 8
6648 22:14:33.719930 iDelay=217, Bit 0, Center -40 (-279 ~ 200) 480
6649 22:14:33.722972 iDelay=217, Bit 1, Center -36 (-279 ~ 208) 488
6650 22:14:33.726356 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6651 22:14:33.729576 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6652 22:14:33.736118 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6653 22:14:33.740025 iDelay=217, Bit 5, Center -44 (-287 ~ 200) 488
6654 22:14:33.742928 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6655 22:14:33.749302 iDelay=217, Bit 7, Center -28 (-271 ~ 216) 488
6656 22:14:33.752459 iDelay=217, Bit 8, Center -52 (-295 ~ 192) 488
6657 22:14:33.755636 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6658 22:14:33.759274 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6659 22:14:33.765858 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6660 22:14:33.769262 iDelay=217, Bit 12, Center -36 (-279 ~ 208) 488
6661 22:14:33.772551 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6662 22:14:33.775840 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6663 22:14:33.782476 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6664 22:14:33.782557 ==
6665 22:14:33.785952 Dram Type= 6, Freq= 0, CH_0, rank 1
6666 22:14:33.788885 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6667 22:14:33.788968 ==
6668 22:14:33.789034 DQS Delay:
6669 22:14:33.792351 DQS0 = 44, DQS1 = 60
6670 22:14:33.792433 DQM Delay:
6671 22:14:33.795639 DQM0 = 8, DQM1 = 15
6672 22:14:33.795720 DQ Delay:
6673 22:14:33.799224 DQ0 =4, DQ1 =8, DQ2 =4, DQ3 =8
6674 22:14:33.802009 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6675 22:14:33.805750 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6676 22:14:33.808474 DQ12 =24, DQ13 =20, DQ14 =24, DQ15 =24
6677 22:14:33.808582
6678 22:14:33.808648
6679 22:14:33.815399 [DQSOSCAuto] RK1, (LSB)MR18= 0xb43f, (MSB)MR19= 0xc0c, tDQSOscB0 = 401 ps tDQSOscB1 = 387 ps
6680 22:14:33.818637 CH0 RK1: MR19=C0C, MR18=B43F
6681 22:14:33.825236 CH0_RK1: MR19=0xC0C, MR18=0xB43F, DQSOSC=387, MR23=63, INC=394, DEC=262
6682 22:14:33.828314 [RxdqsGatingPostProcess] freq 400
6683 22:14:33.834840 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6684 22:14:33.838140 best DQS0 dly(2T, 0.5T) = (0, 10)
6685 22:14:33.841554 best DQS1 dly(2T, 0.5T) = (0, 10)
6686 22:14:33.845027 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6687 22:14:33.848329 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6688 22:14:33.848411 best DQS0 dly(2T, 0.5T) = (0, 10)
6689 22:14:33.851662 best DQS1 dly(2T, 0.5T) = (0, 10)
6690 22:14:33.854952 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6691 22:14:33.858000 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6692 22:14:33.861780 Pre-setting of DQS Precalculation
6693 22:14:33.868384 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6694 22:14:33.868467 ==
6695 22:14:33.871223 Dram Type= 6, Freq= 0, CH_1, rank 0
6696 22:14:33.874716 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6697 22:14:33.874798 ==
6698 22:14:33.881248 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6699 22:14:33.887515 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6700 22:14:33.890804 [CA 0] Center 36 (8~64) winsize 57
6701 22:14:33.894272 [CA 1] Center 36 (8~64) winsize 57
6702 22:14:33.894348 [CA 2] Center 36 (8~64) winsize 57
6703 22:14:33.897549 [CA 3] Center 36 (8~64) winsize 57
6704 22:14:33.900890 [CA 4] Center 36 (8~64) winsize 57
6705 22:14:33.904232 [CA 5] Center 36 (8~64) winsize 57
6706 22:14:33.904326
6707 22:14:33.910472 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6708 22:14:33.910550
6709 22:14:33.914346 [CATrainingPosCal] consider 1 rank data
6710 22:14:33.917319 u2DelayCellTimex100 = 270/100 ps
6711 22:14:33.920832 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6712 22:14:33.924582 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6713 22:14:33.927585 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6714 22:14:33.930413 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6715 22:14:33.934269 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6716 22:14:33.937331 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6717 22:14:33.937426
6718 22:14:33.940403 CA PerBit enable=1, Macro0, CA PI delay=36
6719 22:14:33.940485
6720 22:14:33.943727 [CBTSetCACLKResult] CA Dly = 36
6721 22:14:33.947367 CS Dly: 1 (0~32)
6722 22:14:33.947447 ==
6723 22:14:33.950323 Dram Type= 6, Freq= 0, CH_1, rank 1
6724 22:14:33.953724 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6725 22:14:33.953821 ==
6726 22:14:33.960631 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6727 22:14:33.966847 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6728 22:14:33.966958 [CA 0] Center 36 (8~64) winsize 57
6729 22:14:33.970051 [CA 1] Center 36 (8~64) winsize 57
6730 22:14:33.973525 [CA 2] Center 36 (8~64) winsize 57
6731 22:14:33.977208 [CA 3] Center 36 (8~64) winsize 57
6732 22:14:33.980558 [CA 4] Center 36 (8~64) winsize 57
6733 22:14:33.983355 [CA 5] Center 36 (8~64) winsize 57
6734 22:14:33.983435
6735 22:14:33.986792 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6736 22:14:33.986872
6737 22:14:33.990330 [CATrainingPosCal] consider 2 rank data
6738 22:14:33.993404 u2DelayCellTimex100 = 270/100 ps
6739 22:14:33.996852 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6740 22:14:34.003051 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6741 22:14:34.006765 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6742 22:14:34.009864 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6743 22:14:34.013192 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6744 22:14:34.016456 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6745 22:14:34.016561
6746 22:14:34.019380 CA PerBit enable=1, Macro0, CA PI delay=36
6747 22:14:34.019462
6748 22:14:34.022971 [CBTSetCACLKResult] CA Dly = 36
6749 22:14:34.026120 CS Dly: 1 (0~32)
6750 22:14:34.026200
6751 22:14:34.029287 ----->DramcWriteLeveling(PI) begin...
6752 22:14:34.029382 ==
6753 22:14:34.033036 Dram Type= 6, Freq= 0, CH_1, rank 0
6754 22:14:34.036211 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6755 22:14:34.036293 ==
6756 22:14:34.039440 Write leveling (Byte 0): 40 => 8
6757 22:14:34.042892 Write leveling (Byte 1): 40 => 8
6758 22:14:34.045613 DramcWriteLeveling(PI) end<-----
6759 22:14:34.045699
6760 22:14:34.045764 ==
6761 22:14:34.049358 Dram Type= 6, Freq= 0, CH_1, rank 0
6762 22:14:34.052273 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6763 22:14:34.052353 ==
6764 22:14:34.055691 [Gating] SW mode calibration
6765 22:14:34.062503 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6766 22:14:34.069043 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6767 22:14:34.071936 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6768 22:14:34.075467 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6769 22:14:34.082017 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6770 22:14:34.085224 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6771 22:14:34.088375 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6772 22:14:34.095115 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6773 22:14:34.098737 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6774 22:14:34.101813 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6775 22:14:34.108222 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6776 22:14:34.111777 Total UI for P1: 0, mck2ui 16
6777 22:14:34.115150 best dqsien dly found for B0: ( 0, 14, 24)
6778 22:14:34.118590 Total UI for P1: 0, mck2ui 16
6779 22:14:34.121942 best dqsien dly found for B1: ( 0, 14, 24)
6780 22:14:34.125178 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6781 22:14:34.127954 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6782 22:14:34.128034
6783 22:14:34.131913 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6784 22:14:34.134514 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6785 22:14:34.138111 [Gating] SW calibration Done
6786 22:14:34.138191 ==
6787 22:14:34.141415 Dram Type= 6, Freq= 0, CH_1, rank 0
6788 22:14:34.144634 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6789 22:14:34.144717 ==
6790 22:14:34.147736 RX Vref Scan: 0
6791 22:14:34.147816
6792 22:14:34.151672 RX Vref 0 -> 0, step: 1
6793 22:14:34.151752
6794 22:14:34.154222 RX Delay -410 -> 252, step: 16
6795 22:14:34.157602 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6796 22:14:34.160932 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6797 22:14:34.164167 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6798 22:14:34.170993 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6799 22:14:34.174290 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6800 22:14:34.177569 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6801 22:14:34.181213 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6802 22:14:34.187425 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6803 22:14:34.190655 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6804 22:14:34.193806 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6805 22:14:34.197553 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6806 22:14:34.204113 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6807 22:14:34.206958 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6808 22:14:34.210488 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6809 22:14:34.217264 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6810 22:14:34.220588 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6811 22:14:34.220668 ==
6812 22:14:34.223428 Dram Type= 6, Freq= 0, CH_1, rank 0
6813 22:14:34.227107 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6814 22:14:34.227203 ==
6815 22:14:34.230210 DQS Delay:
6816 22:14:34.230295 DQS0 = 43, DQS1 = 51
6817 22:14:34.233471 DQM Delay:
6818 22:14:34.233552 DQM0 = 12, DQM1 = 14
6819 22:14:34.233616 DQ Delay:
6820 22:14:34.236698 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6821 22:14:34.239843 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6822 22:14:34.243170 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =0
6823 22:14:34.246656 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6824 22:14:34.246739
6825 22:14:34.246815
6826 22:14:34.246873 ==
6827 22:14:34.249747 Dram Type= 6, Freq= 0, CH_1, rank 0
6828 22:14:34.256809 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6829 22:14:34.256889 ==
6830 22:14:34.256953
6831 22:14:34.257011
6832 22:14:34.257067 TX Vref Scan disable
6833 22:14:34.260246 == TX Byte 0 ==
6834 22:14:34.262947 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6835 22:14:34.266066 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6836 22:14:34.269761 == TX Byte 1 ==
6837 22:14:34.272973 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6838 22:14:34.276659 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6839 22:14:34.276739 ==
6840 22:14:34.279356 Dram Type= 6, Freq= 0, CH_1, rank 0
6841 22:14:34.286330 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6842 22:14:34.286411 ==
6843 22:14:34.286475
6844 22:14:34.286534
6845 22:14:34.286590 TX Vref Scan disable
6846 22:14:34.289800 == TX Byte 0 ==
6847 22:14:34.292930 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6848 22:14:34.296079 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6849 22:14:34.299635 == TX Byte 1 ==
6850 22:14:34.302816 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6851 22:14:34.306305 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6852 22:14:34.306386
6853 22:14:34.309551 [DATLAT]
6854 22:14:34.309631 Freq=400, CH1 RK0
6855 22:14:34.309695
6856 22:14:34.312871 DATLAT Default: 0xf
6857 22:14:34.312951 0, 0xFFFF, sum = 0
6858 22:14:34.315785 1, 0xFFFF, sum = 0
6859 22:14:34.315867 2, 0xFFFF, sum = 0
6860 22:14:34.319807 3, 0xFFFF, sum = 0
6861 22:14:34.319933 4, 0xFFFF, sum = 0
6862 22:14:34.322499 5, 0xFFFF, sum = 0
6863 22:14:34.322580 6, 0xFFFF, sum = 0
6864 22:14:34.325727 7, 0xFFFF, sum = 0
6865 22:14:34.329296 8, 0xFFFF, sum = 0
6866 22:14:34.329378 9, 0xFFFF, sum = 0
6867 22:14:34.332713 10, 0xFFFF, sum = 0
6868 22:14:34.332795 11, 0xFFFF, sum = 0
6869 22:14:34.335614 12, 0xFFFF, sum = 0
6870 22:14:34.335695 13, 0x0, sum = 1
6871 22:14:34.339722 14, 0x0, sum = 2
6872 22:14:34.339804 15, 0x0, sum = 3
6873 22:14:34.342302 16, 0x0, sum = 4
6874 22:14:34.342383 best_step = 14
6875 22:14:34.342482
6876 22:14:34.342541 ==
6877 22:14:34.345608 Dram Type= 6, Freq= 0, CH_1, rank 0
6878 22:14:34.348661 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6879 22:14:34.348742 ==
6880 22:14:34.351913 RX Vref Scan: 1
6881 22:14:34.351993
6882 22:14:34.355255 RX Vref 0 -> 0, step: 1
6883 22:14:34.355335
6884 22:14:34.355430 RX Delay -343 -> 252, step: 8
6885 22:14:34.358624
6886 22:14:34.358736 Set Vref, RX VrefLevel [Byte0]: 48
6887 22:14:34.362176 [Byte1]: 58
6888 22:14:34.367430
6889 22:14:34.367509 Final RX Vref Byte 0 = 48 to rank0
6890 22:14:34.371035 Final RX Vref Byte 1 = 58 to rank0
6891 22:14:34.374252 Final RX Vref Byte 0 = 48 to rank1
6892 22:14:34.377638 Final RX Vref Byte 1 = 58 to rank1==
6893 22:14:34.380726 Dram Type= 6, Freq= 0, CH_1, rank 0
6894 22:14:34.387251 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6895 22:14:34.387327 ==
6896 22:14:34.387403 DQS Delay:
6897 22:14:34.390719 DQS0 = 44, DQS1 = 52
6898 22:14:34.390788 DQM Delay:
6899 22:14:34.390848 DQM0 = 8, DQM1 = 10
6900 22:14:34.393843 DQ Delay:
6901 22:14:34.397764 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =4
6902 22:14:34.397845 DQ4 =8, DQ5 =20, DQ6 =16, DQ7 =4
6903 22:14:34.400811 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6904 22:14:34.404086 DQ12 =20, DQ13 =12, DQ14 =20, DQ15 =20
6905 22:14:34.404170
6906 22:14:34.407245
6907 22:14:34.413707 [DQSOSCAuto] RK0, (LSB)MR18= 0x986e, (MSB)MR19= 0xc0c, tDQSOscB0 = 395 ps tDQSOscB1 = 390 ps
6908 22:14:34.417210 CH1 RK0: MR19=C0C, MR18=986E
6909 22:14:34.423848 CH1_RK0: MR19=0xC0C, MR18=0x986E, DQSOSC=390, MR23=63, INC=388, DEC=258
6910 22:14:34.423929 ==
6911 22:14:34.426914 Dram Type= 6, Freq= 0, CH_1, rank 1
6912 22:14:34.430059 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6913 22:14:34.430140 ==
6914 22:14:34.433591 [Gating] SW mode calibration
6915 22:14:34.440251 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6916 22:14:34.446612 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6917 22:14:34.450277 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6918 22:14:34.453132 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6919 22:14:34.460141 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6920 22:14:34.463443 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6921 22:14:34.466377 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6922 22:14:34.473274 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6923 22:14:34.476396 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6924 22:14:34.479850 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6925 22:14:34.486417 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6926 22:14:34.486526 Total UI for P1: 0, mck2ui 16
6927 22:14:34.492801 best dqsien dly found for B0: ( 0, 14, 24)
6928 22:14:34.492906 Total UI for P1: 0, mck2ui 16
6929 22:14:34.499590 best dqsien dly found for B1: ( 0, 14, 24)
6930 22:14:34.502949 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6931 22:14:34.505996 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6932 22:14:34.506098
6933 22:14:34.509578 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6934 22:14:34.513091 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6935 22:14:34.516347 [Gating] SW calibration Done
6936 22:14:34.516450 ==
6937 22:14:34.519654 Dram Type= 6, Freq= 0, CH_1, rank 1
6938 22:14:34.522607 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6939 22:14:34.522701 ==
6940 22:14:34.525919 RX Vref Scan: 0
6941 22:14:34.525996
6942 22:14:34.526059 RX Vref 0 -> 0, step: 1
6943 22:14:34.526118
6944 22:14:34.529954 RX Delay -410 -> 252, step: 16
6945 22:14:34.535986 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6946 22:14:34.539830 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6947 22:14:34.543134 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6948 22:14:34.546044 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6949 22:14:34.552542 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6950 22:14:34.556211 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6951 22:14:34.559488 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6952 22:14:34.562607 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6953 22:14:34.569493 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6954 22:14:34.572660 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6955 22:14:34.575702 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6956 22:14:34.579008 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6957 22:14:34.585533 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6958 22:14:34.589126 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6959 22:14:34.592229 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6960 22:14:34.599070 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6961 22:14:34.599181 ==
6962 22:14:34.602114 Dram Type= 6, Freq= 0, CH_1, rank 1
6963 22:14:34.605620 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6964 22:14:34.605721 ==
6965 22:14:34.605817 DQS Delay:
6966 22:14:34.608597 DQS0 = 51, DQS1 = 59
6967 22:14:34.608700 DQM Delay:
6968 22:14:34.612117 DQM0 = 19, DQM1 = 22
6969 22:14:34.612226 DQ Delay:
6970 22:14:34.615064 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6971 22:14:34.618597 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6972 22:14:34.621856 DQ8 =0, DQ9 =16, DQ10 =16, DQ11 =16
6973 22:14:34.625069 DQ12 =32, DQ13 =32, DQ14 =32, DQ15 =32
6974 22:14:34.625169
6975 22:14:34.625263
6976 22:14:34.625357 ==
6977 22:14:34.628553 Dram Type= 6, Freq= 0, CH_1, rank 1
6978 22:14:34.631894 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6979 22:14:34.631999 ==
6980 22:14:34.632091
6981 22:14:34.635403
6982 22:14:34.635504 TX Vref Scan disable
6983 22:14:34.638615 == TX Byte 0 ==
6984 22:14:34.641674 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6985 22:14:34.645205 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6986 22:14:34.648724 == TX Byte 1 ==
6987 22:14:34.651772 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6988 22:14:34.654864 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6989 22:14:34.654961 ==
6990 22:14:34.658061 Dram Type= 6, Freq= 0, CH_1, rank 1
6991 22:14:34.661611 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6992 22:14:34.665038 ==
6993 22:14:34.665116
6994 22:14:34.665179
6995 22:14:34.665237 TX Vref Scan disable
6996 22:14:34.668282 == TX Byte 0 ==
6997 22:14:34.671909 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6998 22:14:34.674979 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6999 22:14:34.677953 == TX Byte 1 ==
7000 22:14:34.681026 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
7001 22:14:34.684394 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
7002 22:14:34.684494
7003 22:14:34.688068 [DATLAT]
7004 22:14:34.688167 Freq=400, CH1 RK1
7005 22:14:34.688256
7006 22:14:34.691019 DATLAT Default: 0xe
7007 22:14:34.691122 0, 0xFFFF, sum = 0
7008 22:14:34.694258 1, 0xFFFF, sum = 0
7009 22:14:34.694368 2, 0xFFFF, sum = 0
7010 22:14:34.698429 3, 0xFFFF, sum = 0
7011 22:14:34.698508 4, 0xFFFF, sum = 0
7012 22:14:34.701143 5, 0xFFFF, sum = 0
7013 22:14:34.701221 6, 0xFFFF, sum = 0
7014 22:14:34.704255 7, 0xFFFF, sum = 0
7015 22:14:34.704357 8, 0xFFFF, sum = 0
7016 22:14:34.707680 9, 0xFFFF, sum = 0
7017 22:14:34.707787 10, 0xFFFF, sum = 0
7018 22:14:34.711171 11, 0xFFFF, sum = 0
7019 22:14:34.711273 12, 0xFFFF, sum = 0
7020 22:14:34.714474 13, 0x0, sum = 1
7021 22:14:34.714581 14, 0x0, sum = 2
7022 22:14:34.717661 15, 0x0, sum = 3
7023 22:14:34.717761 16, 0x0, sum = 4
7024 22:14:34.720825 best_step = 14
7025 22:14:34.720900
7026 22:14:34.720963 ==
7027 22:14:34.724428 Dram Type= 6, Freq= 0, CH_1, rank 1
7028 22:14:34.727297 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7029 22:14:34.727399 ==
7030 22:14:34.731015 RX Vref Scan: 0
7031 22:14:34.731116
7032 22:14:34.731205 RX Vref 0 -> 0, step: 1
7033 22:14:34.731295
7034 22:14:34.733797 RX Delay -359 -> 252, step: 8
7035 22:14:34.742297 iDelay=225, Bit 0, Center -32 (-271 ~ 208) 480
7036 22:14:34.745815 iDelay=225, Bit 1, Center -40 (-279 ~ 200) 480
7037 22:14:34.749026 iDelay=225, Bit 2, Center -48 (-287 ~ 192) 480
7038 22:14:34.755828 iDelay=225, Bit 3, Center -40 (-279 ~ 200) 480
7039 22:14:34.758713 iDelay=225, Bit 4, Center -36 (-279 ~ 208) 488
7040 22:14:34.762231 iDelay=225, Bit 5, Center -28 (-271 ~ 216) 488
7041 22:14:34.765220 iDelay=225, Bit 6, Center -20 (-263 ~ 224) 488
7042 22:14:34.771992 iDelay=225, Bit 7, Center -36 (-279 ~ 208) 488
7043 22:14:34.775358 iDelay=225, Bit 8, Center -56 (-303 ~ 192) 496
7044 22:14:34.778668 iDelay=225, Bit 9, Center -56 (-303 ~ 192) 496
7045 22:14:34.781818 iDelay=225, Bit 10, Center -44 (-295 ~ 208) 504
7046 22:14:34.788628 iDelay=225, Bit 11, Center -52 (-295 ~ 192) 488
7047 22:14:34.791850 iDelay=225, Bit 12, Center -36 (-287 ~ 216) 504
7048 22:14:34.794959 iDelay=225, Bit 13, Center -40 (-287 ~ 208) 496
7049 22:14:34.798549 iDelay=225, Bit 14, Center -40 (-287 ~ 208) 496
7050 22:14:34.805191 iDelay=225, Bit 15, Center -32 (-279 ~ 216) 496
7051 22:14:34.805273 ==
7052 22:14:34.808244 Dram Type= 6, Freq= 0, CH_1, rank 1
7053 22:14:34.811498 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7054 22:14:34.811600 ==
7055 22:14:34.811696 DQS Delay:
7056 22:14:34.814898 DQS0 = 48, DQS1 = 56
7057 22:14:34.814995 DQM Delay:
7058 22:14:34.818062 DQM0 = 13, DQM1 = 11
7059 22:14:34.818163 DQ Delay:
7060 22:14:34.821978 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
7061 22:14:34.825015 DQ4 =12, DQ5 =20, DQ6 =28, DQ7 =12
7062 22:14:34.827973 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
7063 22:14:34.831312 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =24
7064 22:14:34.831408
7065 22:14:34.831498
7066 22:14:34.841263 [DQSOSCAuto] RK1, (LSB)MR18= 0x6c5a, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 396 ps
7067 22:14:34.841377 CH1 RK1: MR19=C0C, MR18=6C5A
7068 22:14:34.847866 CH1_RK1: MR19=0xC0C, MR18=0x6C5A, DQSOSC=396, MR23=63, INC=376, DEC=251
7069 22:14:34.851177 [RxdqsGatingPostProcess] freq 400
7070 22:14:34.858263 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7071 22:14:34.860893 best DQS0 dly(2T, 0.5T) = (0, 10)
7072 22:14:34.864683 best DQS1 dly(2T, 0.5T) = (0, 10)
7073 22:14:34.867839 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7074 22:14:34.871550 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7075 22:14:34.874662 best DQS0 dly(2T, 0.5T) = (0, 10)
7076 22:14:34.874760 best DQS1 dly(2T, 0.5T) = (0, 10)
7077 22:14:34.877824 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7078 22:14:34.880937 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7079 22:14:34.884866 Pre-setting of DQS Precalculation
7080 22:14:34.891054 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7081 22:14:34.897283 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7082 22:14:34.904049 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7083 22:14:34.904151
7084 22:14:34.904241
7085 22:14:34.907399 [Calibration Summary] 800 Mbps
7086 22:14:34.907523 CH 0, Rank 0
7087 22:14:34.910523 SW Impedance : PASS
7088 22:14:34.914551 DUTY Scan : NO K
7089 22:14:34.914650 ZQ Calibration : PASS
7090 22:14:34.917229 Jitter Meter : NO K
7091 22:14:34.920675 CBT Training : PASS
7092 22:14:34.920773 Write leveling : PASS
7093 22:14:34.923896 RX DQS gating : PASS
7094 22:14:34.927635 RX DQ/DQS(RDDQC) : PASS
7095 22:14:34.927733 TX DQ/DQS : PASS
7096 22:14:34.930403 RX DATLAT : PASS
7097 22:14:34.933886 RX DQ/DQS(Engine): PASS
7098 22:14:34.933986 TX OE : NO K
7099 22:14:34.937357 All Pass.
7100 22:14:34.937455
7101 22:14:34.937547 CH 0, Rank 1
7102 22:14:34.940676 SW Impedance : PASS
7103 22:14:34.940775 DUTY Scan : NO K
7104 22:14:34.943608 ZQ Calibration : PASS
7105 22:14:34.946781 Jitter Meter : NO K
7106 22:14:34.946879 CBT Training : PASS
7107 22:14:34.950107 Write leveling : NO K
7108 22:14:34.953462 RX DQS gating : PASS
7109 22:14:34.953535 RX DQ/DQS(RDDQC) : PASS
7110 22:14:34.957263 TX DQ/DQS : PASS
7111 22:14:34.960268 RX DATLAT : PASS
7112 22:14:34.960376 RX DQ/DQS(Engine): PASS
7113 22:14:34.963754 TX OE : NO K
7114 22:14:34.963828 All Pass.
7115 22:14:34.963890
7116 22:14:34.966586 CH 1, Rank 0
7117 22:14:34.966684 SW Impedance : PASS
7118 22:14:34.970271 DUTY Scan : NO K
7119 22:14:34.973267 ZQ Calibration : PASS
7120 22:14:34.973377 Jitter Meter : NO K
7121 22:14:34.976687 CBT Training : PASS
7122 22:14:34.976787 Write leveling : PASS
7123 22:14:34.980054 RX DQS gating : PASS
7124 22:14:34.983278 RX DQ/DQS(RDDQC) : PASS
7125 22:14:34.983382 TX DQ/DQS : PASS
7126 22:14:34.986488 RX DATLAT : PASS
7127 22:14:34.990478 RX DQ/DQS(Engine): PASS
7128 22:14:34.990575 TX OE : NO K
7129 22:14:34.993366 All Pass.
7130 22:14:34.993446
7131 22:14:34.993512 CH 1, Rank 1
7132 22:14:34.996643 SW Impedance : PASS
7133 22:14:34.996712 DUTY Scan : NO K
7134 22:14:34.999630 ZQ Calibration : PASS
7135 22:14:35.002990 Jitter Meter : NO K
7136 22:14:35.003087 CBT Training : PASS
7137 22:14:35.006195 Write leveling : NO K
7138 22:14:35.009643 RX DQS gating : PASS
7139 22:14:35.009713 RX DQ/DQS(RDDQC) : PASS
7140 22:14:35.012885 TX DQ/DQS : PASS
7141 22:14:35.016592 RX DATLAT : PASS
7142 22:14:35.016698 RX DQ/DQS(Engine): PASS
7143 22:14:35.019313 TX OE : NO K
7144 22:14:35.019417 All Pass.
7145 22:14:35.019508
7146 22:14:35.022916 DramC Write-DBI off
7147 22:14:35.026466 PER_BANK_REFRESH: Hybrid Mode
7148 22:14:35.026566 TX_TRACKING: ON
7149 22:14:35.036134 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7150 22:14:35.039689 [FAST_K] Save calibration result to emmc
7151 22:14:35.042512 dramc_set_vcore_voltage set vcore to 725000
7152 22:14:35.046156 Read voltage for 1600, 0
7153 22:14:35.046258 Vio18 = 0
7154 22:14:35.046356 Vcore = 725000
7155 22:14:35.049335 Vdram = 0
7156 22:14:35.049443 Vddq = 0
7157 22:14:35.049532 Vmddr = 0
7158 22:14:35.055779 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7159 22:14:35.059990 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7160 22:14:35.062621 MEM_TYPE=3, freq_sel=13
7161 22:14:35.065814 sv_algorithm_assistance_LP4_3733
7162 22:14:35.069985 ============ PULL DRAM RESETB DOWN ============
7163 22:14:35.073013 ========== PULL DRAM RESETB DOWN end =========
7164 22:14:35.079061 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7165 22:14:35.082588 ===================================
7166 22:14:35.085812 LPDDR4 DRAM CONFIGURATION
7167 22:14:35.088983 ===================================
7168 22:14:35.089057 EX_ROW_EN[0] = 0x0
7169 22:14:35.092647 EX_ROW_EN[1] = 0x0
7170 22:14:35.092724 LP4Y_EN = 0x0
7171 22:14:35.095589 WORK_FSP = 0x1
7172 22:14:35.095655 WL = 0x5
7173 22:14:35.098906 RL = 0x5
7174 22:14:35.098979 BL = 0x2
7175 22:14:35.102316 RPST = 0x0
7176 22:14:35.102388 RD_PRE = 0x0
7177 22:14:35.105904 WR_PRE = 0x1
7178 22:14:35.105981 WR_PST = 0x1
7179 22:14:35.109148 DBI_WR = 0x0
7180 22:14:35.109223 DBI_RD = 0x0
7181 22:14:35.112477 OTF = 0x1
7182 22:14:35.116067 ===================================
7183 22:14:35.119027 ===================================
7184 22:14:35.119103 ANA top config
7185 22:14:35.122049 ===================================
7186 22:14:35.125379 DLL_ASYNC_EN = 0
7187 22:14:35.128608 ALL_SLAVE_EN = 0
7188 22:14:35.132419 NEW_RANK_MODE = 1
7189 22:14:35.135363 DLL_IDLE_MODE = 1
7190 22:14:35.135470 LP45_APHY_COMB_EN = 1
7191 22:14:35.138635 TX_ODT_DIS = 0
7192 22:14:35.141682 NEW_8X_MODE = 1
7193 22:14:35.145135 ===================================
7194 22:14:35.148522 ===================================
7195 22:14:35.152142 data_rate = 3200
7196 22:14:35.155309 CKR = 1
7197 22:14:35.155410 DQ_P2S_RATIO = 8
7198 22:14:35.158335 ===================================
7199 22:14:35.161812 CA_P2S_RATIO = 8
7200 22:14:35.165438 DQ_CA_OPEN = 0
7201 22:14:35.168294 DQ_SEMI_OPEN = 0
7202 22:14:35.171702 CA_SEMI_OPEN = 0
7203 22:14:35.174808 CA_FULL_RATE = 0
7204 22:14:35.174910 DQ_CKDIV4_EN = 0
7205 22:14:35.178183 CA_CKDIV4_EN = 0
7206 22:14:35.181309 CA_PREDIV_EN = 0
7207 22:14:35.185092 PH8_DLY = 12
7208 22:14:35.187878 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7209 22:14:35.191394 DQ_AAMCK_DIV = 4
7210 22:14:35.194747 CA_AAMCK_DIV = 4
7211 22:14:35.194835 CA_ADMCK_DIV = 4
7212 22:14:35.197876 DQ_TRACK_CA_EN = 0
7213 22:14:35.201013 CA_PICK = 1600
7214 22:14:35.204464 CA_MCKIO = 1600
7215 22:14:35.207645 MCKIO_SEMI = 0
7216 22:14:35.211164 PLL_FREQ = 3068
7217 22:14:35.214476 DQ_UI_PI_RATIO = 32
7218 22:14:35.214558 CA_UI_PI_RATIO = 0
7219 22:14:35.217889 ===================================
7220 22:14:35.220786 ===================================
7221 22:14:35.224512 memory_type:LPDDR4
7222 22:14:35.227383 GP_NUM : 10
7223 22:14:35.227465 SRAM_EN : 1
7224 22:14:35.230750 MD32_EN : 0
7225 22:14:35.234755 ===================================
7226 22:14:35.237458 [ANA_INIT] >>>>>>>>>>>>>>
7227 22:14:35.240580 <<<<<< [CONFIGURE PHASE]: ANA_TX
7228 22:14:35.243779 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7229 22:14:35.247544 ===================================
7230 22:14:35.250661 data_rate = 3200,PCW = 0X7600
7231 22:14:35.253619 ===================================
7232 22:14:35.257377 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7233 22:14:35.260217 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7234 22:14:35.266938 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7235 22:14:35.270468 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7236 22:14:35.273510 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7237 22:14:35.277072 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7238 22:14:35.280494 [ANA_INIT] flow start
7239 22:14:35.283361 [ANA_INIT] PLL >>>>>>>>
7240 22:14:35.283442 [ANA_INIT] PLL <<<<<<<<
7241 22:14:35.286933 [ANA_INIT] MIDPI >>>>>>>>
7242 22:14:35.290311 [ANA_INIT] MIDPI <<<<<<<<
7243 22:14:35.293740 [ANA_INIT] DLL >>>>>>>>
7244 22:14:35.293860 [ANA_INIT] DLL <<<<<<<<
7245 22:14:35.296721 [ANA_INIT] flow end
7246 22:14:35.300149 ============ LP4 DIFF to SE enter ============
7247 22:14:35.303017 ============ LP4 DIFF to SE exit ============
7248 22:14:35.306390 [ANA_INIT] <<<<<<<<<<<<<
7249 22:14:35.309743 [Flow] Enable top DCM control >>>>>
7250 22:14:35.313081 [Flow] Enable top DCM control <<<<<
7251 22:14:35.316632 Enable DLL master slave shuffle
7252 22:14:35.323418 ==============================================================
7253 22:14:35.323499 Gating Mode config
7254 22:14:35.329808 ==============================================================
7255 22:14:35.329889 Config description:
7256 22:14:35.339462 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7257 22:14:35.346206 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7258 22:14:35.353083 SELPH_MODE 0: By rank 1: By Phase
7259 22:14:35.356315 ==============================================================
7260 22:14:35.359194 GAT_TRACK_EN = 1
7261 22:14:35.362494 RX_GATING_MODE = 2
7262 22:14:35.366042 RX_GATING_TRACK_MODE = 2
7263 22:14:35.369432 SELPH_MODE = 1
7264 22:14:35.372965 PICG_EARLY_EN = 1
7265 22:14:35.376121 VALID_LAT_VALUE = 1
7266 22:14:35.382454 ==============================================================
7267 22:14:35.385725 Enter into Gating configuration >>>>
7268 22:14:35.389450 Exit from Gating configuration <<<<
7269 22:14:35.392615 Enter into DVFS_PRE_config >>>>>
7270 22:14:35.402145 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7271 22:14:35.405510 Exit from DVFS_PRE_config <<<<<
7272 22:14:35.409175 Enter into PICG configuration >>>>
7273 22:14:35.412451 Exit from PICG configuration <<<<
7274 22:14:35.415362 [RX_INPUT] configuration >>>>>
7275 22:14:35.415468 [RX_INPUT] configuration <<<<<
7276 22:14:35.421880 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7277 22:14:35.428401 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7278 22:14:35.435108 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7279 22:14:35.438515 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7280 22:14:35.445314 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7281 22:14:35.451599 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7282 22:14:35.455380 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7283 22:14:35.458751 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7284 22:14:35.464942 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7285 22:14:35.468266 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7286 22:14:35.471402 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7287 22:14:35.478101 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7288 22:14:35.481921 ===================================
7289 22:14:35.482004 LPDDR4 DRAM CONFIGURATION
7290 22:14:35.484550 ===================================
7291 22:14:35.488017 EX_ROW_EN[0] = 0x0
7292 22:14:35.491269 EX_ROW_EN[1] = 0x0
7293 22:14:35.491349 LP4Y_EN = 0x0
7294 22:14:35.494624 WORK_FSP = 0x1
7295 22:14:35.494705 WL = 0x5
7296 22:14:35.497817 RL = 0x5
7297 22:14:35.497897 BL = 0x2
7298 22:14:35.500964 RPST = 0x0
7299 22:14:35.501046 RD_PRE = 0x0
7300 22:14:35.504450 WR_PRE = 0x1
7301 22:14:35.504537 WR_PST = 0x1
7302 22:14:35.507958 DBI_WR = 0x0
7303 22:14:35.508039 DBI_RD = 0x0
7304 22:14:35.511251 OTF = 0x1
7305 22:14:35.514283 ===================================
7306 22:14:35.518079 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7307 22:14:35.520798 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7308 22:14:35.527491 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7309 22:14:35.530705 ===================================
7310 22:14:35.530786 LPDDR4 DRAM CONFIGURATION
7311 22:14:35.534096 ===================================
7312 22:14:35.537299 EX_ROW_EN[0] = 0x10
7313 22:14:35.540535 EX_ROW_EN[1] = 0x0
7314 22:14:35.540617 LP4Y_EN = 0x0
7315 22:14:35.543726 WORK_FSP = 0x1
7316 22:14:35.543807 WL = 0x5
7317 22:14:35.547357 RL = 0x5
7318 22:14:35.547438 BL = 0x2
7319 22:14:35.550304 RPST = 0x0
7320 22:14:35.550386 RD_PRE = 0x0
7321 22:14:35.553942 WR_PRE = 0x1
7322 22:14:35.554024 WR_PST = 0x1
7323 22:14:35.557340 DBI_WR = 0x0
7324 22:14:35.557421 DBI_RD = 0x0
7325 22:14:35.560352 OTF = 0x1
7326 22:14:35.563863 ===================================
7327 22:14:35.570345 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7328 22:14:35.570427 ==
7329 22:14:35.573534 Dram Type= 6, Freq= 0, CH_0, rank 0
7330 22:14:35.577328 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7331 22:14:35.577410 ==
7332 22:14:35.580348 [Duty_Offset_Calibration]
7333 22:14:35.580432 B0:1 B1:-1 CA:0
7334 22:14:35.580497
7335 22:14:35.583352 [DutyScan_Calibration_Flow] k_type=0
7336 22:14:35.595429
7337 22:14:35.595515 ==CLK 0==
7338 22:14:35.597935 Final CLK duty delay cell = 0
7339 22:14:35.601179 [0] MAX Duty = 5125%(X100), DQS PI = 24
7340 22:14:35.604267 [0] MIN Duty = 4907%(X100), DQS PI = 6
7341 22:14:35.608064 [0] AVG Duty = 5016%(X100)
7342 22:14:35.608174
7343 22:14:35.611023 CH0 CLK Duty spec in!! Max-Min= 218%
7344 22:14:35.614857 [DutyScan_Calibration_Flow] ====Done====
7345 22:14:35.614943
7346 22:14:35.618257 [DutyScan_Calibration_Flow] k_type=1
7347 22:14:35.634005
7348 22:14:35.634088 ==DQS 0 ==
7349 22:14:35.636806 Final DQS duty delay cell = -4
7350 22:14:35.640289 [-4] MAX Duty = 5000%(X100), DQS PI = 18
7351 22:14:35.643564 [-4] MIN Duty = 4844%(X100), DQS PI = 56
7352 22:14:35.647096 [-4] AVG Duty = 4922%(X100)
7353 22:14:35.647167
7354 22:14:35.647228 ==DQS 1 ==
7355 22:14:35.650243 Final DQS duty delay cell = 0
7356 22:14:35.653481 [0] MAX Duty = 5156%(X100), DQS PI = 0
7357 22:14:35.657107 [0] MIN Duty = 5031%(X100), DQS PI = 22
7358 22:14:35.660453 [0] AVG Duty = 5093%(X100)
7359 22:14:35.660588
7360 22:14:35.663677 CH0 DQS 0 Duty spec in!! Max-Min= 156%
7361 22:14:35.663750
7362 22:14:35.666586 CH0 DQS 1 Duty spec in!! Max-Min= 125%
7363 22:14:35.669787 [DutyScan_Calibration_Flow] ====Done====
7364 22:14:35.669864
7365 22:14:35.673455 [DutyScan_Calibration_Flow] k_type=3
7366 22:14:35.691266
7367 22:14:35.691347 ==DQM 0 ==
7368 22:14:35.694994 Final DQM duty delay cell = 0
7369 22:14:35.697997 [0] MAX Duty = 5124%(X100), DQS PI = 22
7370 22:14:35.701592 [0] MIN Duty = 4876%(X100), DQS PI = 10
7371 22:14:35.704598 [0] AVG Duty = 5000%(X100)
7372 22:14:35.704670
7373 22:14:35.704730 ==DQM 1 ==
7374 22:14:35.708182 Final DQM duty delay cell = 0
7375 22:14:35.710752 [0] MAX Duty = 5000%(X100), DQS PI = 6
7376 22:14:35.714481 [0] MIN Duty = 4813%(X100), DQS PI = 20
7377 22:14:35.717467 [0] AVG Duty = 4906%(X100)
7378 22:14:35.717542
7379 22:14:35.721081 CH0 DQM 0 Duty spec in!! Max-Min= 248%
7380 22:14:35.721151
7381 22:14:35.723866 CH0 DQM 1 Duty spec in!! Max-Min= 187%
7382 22:14:35.727207 [DutyScan_Calibration_Flow] ====Done====
7383 22:14:35.727277
7384 22:14:35.730834 [DutyScan_Calibration_Flow] k_type=2
7385 22:14:35.747817
7386 22:14:35.747894 ==DQ 0 ==
7387 22:14:35.750664 Final DQ duty delay cell = -4
7388 22:14:35.754100 [-4] MAX Duty = 5031%(X100), DQS PI = 24
7389 22:14:35.757285 [-4] MIN Duty = 4876%(X100), DQS PI = 54
7390 22:14:35.761067 [-4] AVG Duty = 4953%(X100)
7391 22:14:35.761138
7392 22:14:35.761199 ==DQ 1 ==
7393 22:14:35.763877 Final DQ duty delay cell = 0
7394 22:14:35.767508 [0] MAX Duty = 5125%(X100), DQS PI = 0
7395 22:14:35.770397 [0] MIN Duty = 5000%(X100), DQS PI = 36
7396 22:14:35.774081 [0] AVG Duty = 5062%(X100)
7397 22:14:35.774173
7398 22:14:35.777168 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7399 22:14:35.777241
7400 22:14:35.780367 CH0 DQ 1 Duty spec in!! Max-Min= 125%
7401 22:14:35.784112 [DutyScan_Calibration_Flow] ====Done====
7402 22:14:35.784181 ==
7403 22:14:35.786885 Dram Type= 6, Freq= 0, CH_1, rank 0
7404 22:14:35.790260 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7405 22:14:35.790335 ==
7406 22:14:35.793967 [Duty_Offset_Calibration]
7407 22:14:35.794039 B0:-1 B1:1 CA:2
7408 22:14:35.794100
7409 22:14:35.796967 [DutyScan_Calibration_Flow] k_type=0
7410 22:14:35.808568
7411 22:14:35.808645 ==CLK 0==
7412 22:14:35.811381 Final CLK duty delay cell = 0
7413 22:14:35.815010 [0] MAX Duty = 5187%(X100), DQS PI = 24
7414 22:14:35.818222 [0] MIN Duty = 4969%(X100), DQS PI = 0
7415 22:14:35.821607 [0] AVG Duty = 5078%(X100)
7416 22:14:35.821684
7417 22:14:35.824874 CH1 CLK Duty spec in!! Max-Min= 218%
7418 22:14:35.827617 [DutyScan_Calibration_Flow] ====Done====
7419 22:14:35.827684
7420 22:14:35.831272 [DutyScan_Calibration_Flow] k_type=1
7421 22:14:35.848264
7422 22:14:35.848342 ==DQS 0 ==
7423 22:14:35.851895 Final DQS duty delay cell = 0
7424 22:14:35.854351 [0] MAX Duty = 5156%(X100), DQS PI = 18
7425 22:14:35.857462 [0] MIN Duty = 4907%(X100), DQS PI = 10
7426 22:14:35.861074 [0] AVG Duty = 5031%(X100)
7427 22:14:35.861150
7428 22:14:35.861212 ==DQS 1 ==
7429 22:14:35.864348 Final DQS duty delay cell = 0
7430 22:14:35.867591 [0] MAX Duty = 5093%(X100), DQS PI = 24
7431 22:14:35.870879 [0] MIN Duty = 4969%(X100), DQS PI = 54
7432 22:14:35.874263 [0] AVG Duty = 5031%(X100)
7433 22:14:35.874340
7434 22:14:35.877227 CH1 DQS 0 Duty spec in!! Max-Min= 249%
7435 22:14:35.877301
7436 22:14:35.880764 CH1 DQS 1 Duty spec in!! Max-Min= 124%
7437 22:14:35.883863 [DutyScan_Calibration_Flow] ====Done====
7438 22:14:35.883936
7439 22:14:35.887393 [DutyScan_Calibration_Flow] k_type=3
7440 22:14:35.905053
7441 22:14:35.905133 ==DQM 0 ==
7442 22:14:35.908786 Final DQM duty delay cell = 0
7443 22:14:35.911207 [0] MAX Duty = 5218%(X100), DQS PI = 34
7444 22:14:35.915251 [0] MIN Duty = 5031%(X100), DQS PI = 6
7445 22:14:35.918006 [0] AVG Duty = 5124%(X100)
7446 22:14:35.918083
7447 22:14:35.918145 ==DQM 1 ==
7448 22:14:35.921326 Final DQM duty delay cell = 0
7449 22:14:35.924463 [0] MAX Duty = 5156%(X100), DQS PI = 2
7450 22:14:35.927963 [0] MIN Duty = 5000%(X100), DQS PI = 28
7451 22:14:35.931068 [0] AVG Duty = 5078%(X100)
7452 22:14:35.931153
7453 22:14:35.934772 CH1 DQM 0 Duty spec in!! Max-Min= 187%
7454 22:14:35.934863
7455 22:14:35.937736 CH1 DQM 1 Duty spec in!! Max-Min= 156%
7456 22:14:35.940988 [DutyScan_Calibration_Flow] ====Done====
7457 22:14:35.941072
7458 22:14:35.944183 [DutyScan_Calibration_Flow] k_type=2
7459 22:14:35.961301
7460 22:14:35.961404 ==DQ 0 ==
7461 22:14:35.965272 Final DQ duty delay cell = 0
7462 22:14:35.968376 [0] MAX Duty = 5156%(X100), DQS PI = 30
7463 22:14:35.971593 [0] MIN Duty = 4906%(X100), DQS PI = 8
7464 22:14:35.971681 [0] AVG Duty = 5031%(X100)
7465 22:14:35.971745
7466 22:14:35.975029 ==DQ 1 ==
7467 22:14:35.978517 Final DQ duty delay cell = 0
7468 22:14:35.981198 [0] MAX Duty = 5156%(X100), DQS PI = 8
7469 22:14:35.985346 [0] MIN Duty = 4969%(X100), DQS PI = 56
7470 22:14:35.985436 [0] AVG Duty = 5062%(X100)
7471 22:14:35.985500
7472 22:14:35.987963 CH1 DQ 0 Duty spec in!! Max-Min= 250%
7473 22:14:35.991240
7474 22:14:35.994460 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7475 22:14:35.997916 [DutyScan_Calibration_Flow] ====Done====
7476 22:14:36.001023 nWR fixed to 30
7477 22:14:36.001111 [ModeRegInit_LP4] CH0 RK0
7478 22:14:36.004302 [ModeRegInit_LP4] CH0 RK1
7479 22:14:36.007965 [ModeRegInit_LP4] CH1 RK0
7480 22:14:36.011152 [ModeRegInit_LP4] CH1 RK1
7481 22:14:36.011234 match AC timing 5
7482 22:14:36.017785 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7483 22:14:36.021168 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7484 22:14:36.024438 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7485 22:14:36.030864 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7486 22:14:36.034109 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7487 22:14:36.034183 [MiockJmeterHQA]
7488 22:14:36.034253
7489 22:14:36.037675 [DramcMiockJmeter] u1RxGatingPI = 0
7490 22:14:36.040471 0 : 4258, 4029
7491 22:14:36.040577 4 : 4252, 4027
7492 22:14:36.044155 8 : 4365, 4140
7493 22:14:36.044262 12 : 4258, 4029
7494 22:14:36.046981 16 : 4368, 4140
7495 22:14:36.047087 20 : 4253, 4026
7496 22:14:36.047181 24 : 4363, 4137
7497 22:14:36.050629 28 : 4252, 4026
7498 22:14:36.050707 32 : 4252, 4027
7499 22:14:36.053622 36 : 4250, 4027
7500 22:14:36.053694 40 : 4360, 4137
7501 22:14:36.057001 44 : 4361, 4137
7502 22:14:36.057072 48 : 4250, 4026
7503 22:14:36.060164 52 : 4250, 4027
7504 22:14:36.060261 56 : 4250, 4027
7505 22:14:36.060350 60 : 4250, 4026
7506 22:14:36.063785 64 : 4250, 4027
7507 22:14:36.063856 68 : 4360, 4137
7508 22:14:36.067147 72 : 4252, 4027
7509 22:14:36.067257 76 : 4250, 4027
7510 22:14:36.070304 80 : 4250, 4026
7511 22:14:36.070381 84 : 4250, 4027
7512 22:14:36.070442 88 : 4250, 4027
7513 22:14:36.073558 92 : 4363, 230
7514 22:14:36.073662 96 : 4250, 0
7515 22:14:36.076912 100 : 4361, 0
7516 22:14:36.077009 104 : 4360, 0
7517 22:14:36.077106 108 : 4361, 0
7518 22:14:36.080579 112 : 4361, 0
7519 22:14:36.080687 116 : 4252, 0
7520 22:14:36.083414 120 : 4250, 0
7521 22:14:36.083492 124 : 4250, 0
7522 22:14:36.083554 128 : 4252, 0
7523 22:14:36.087117 132 : 4250, 0
7524 22:14:36.087193 136 : 4250, 0
7525 22:14:36.090286 140 : 4252, 0
7526 22:14:36.090356 144 : 4363, 0
7527 22:14:36.090417 148 : 4250, 0
7528 22:14:36.093440 152 : 4361, 0
7529 22:14:36.093536 156 : 4250, 0
7530 22:14:36.093630 160 : 4250, 0
7531 22:14:36.097085 164 : 4363, 0
7532 22:14:36.097162 168 : 4250, 0
7533 22:14:36.100181 172 : 4250, 0
7534 22:14:36.100250 176 : 4250, 0
7535 22:14:36.100309 180 : 4252, 0
7536 22:14:36.103524 184 : 4250, 0
7537 22:14:36.103594 188 : 4250, 0
7538 22:14:36.106940 192 : 4252, 0
7539 22:14:36.107010 196 : 4361, 0
7540 22:14:36.107069 200 : 4250, 0
7541 22:14:36.110392 204 : 4249, 0
7542 22:14:36.110467 208 : 4252, 0
7543 22:14:36.113584 212 : 4361, 0
7544 22:14:36.113653 216 : 4250, 0
7545 22:14:36.113713 220 : 4249, 0
7546 22:14:36.117063 224 : 4250, 398
7547 22:14:36.117132 228 : 4250, 3515
7548 22:14:36.120027 232 : 4361, 4137
7549 22:14:36.120101 236 : 4361, 4138
7550 22:14:36.123310 240 : 4250, 4027
7551 22:14:36.123388 244 : 4250, 4027
7552 22:14:36.126402 248 : 4361, 4138
7553 22:14:36.126477 252 : 4250, 4027
7554 22:14:36.130379 256 : 4250, 4026
7555 22:14:36.130452 260 : 4250, 4027
7556 22:14:36.133322 264 : 4250, 4027
7557 22:14:36.133392 268 : 4250, 4027
7558 22:14:36.133453 272 : 4250, 4026
7559 22:14:36.136638 276 : 4361, 4138
7560 22:14:36.136707 280 : 4250, 4027
7561 22:14:36.139454 284 : 4249, 4027
7562 22:14:36.139523 288 : 4360, 4137
7563 22:14:36.143046 292 : 4250, 4026
7564 22:14:36.143116 296 : 4250, 4027
7565 22:14:36.146489 300 : 4361, 4138
7566 22:14:36.146584 304 : 4250, 4027
7567 22:14:36.149889 308 : 4250, 4026
7568 22:14:36.149967 312 : 4250, 4027
7569 22:14:36.152970 316 : 4250, 4027
7570 22:14:36.153043 320 : 4250, 4027
7571 22:14:36.156171 324 : 4250, 4026
7572 22:14:36.156247 328 : 4361, 4137
7573 22:14:36.159399 332 : 4250, 4027
7574 22:14:36.159472 336 : 4250, 3380
7575 22:14:36.159539 340 : 4360, 1205
7576 22:14:36.163240
7577 22:14:36.163309 MIOCK jitter meter ch=0
7578 22:14:36.163368
7579 22:14:36.166024 1T = (340-92) = 248 dly cells
7580 22:14:36.172523 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 262/100 ps
7581 22:14:36.172611 ==
7582 22:14:36.176269 Dram Type= 6, Freq= 0, CH_0, rank 0
7583 22:14:36.179091 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7584 22:14:36.179174 ==
7585 22:14:36.185846 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7586 22:14:36.189278 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7587 22:14:36.192800 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7588 22:14:36.198984 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7589 22:14:36.208940 [CA 0] Center 43 (13~74) winsize 62
7590 22:14:36.211760 [CA 1] Center 43 (13~74) winsize 62
7591 22:14:36.215416 [CA 2] Center 39 (10~69) winsize 60
7592 22:14:36.218912 [CA 3] Center 39 (9~69) winsize 61
7593 22:14:36.221493 [CA 4] Center 37 (8~66) winsize 59
7594 22:14:36.225063 [CA 5] Center 36 (7~66) winsize 60
7595 22:14:36.225132
7596 22:14:36.228289 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7597 22:14:36.228390
7598 22:14:36.234789 [CATrainingPosCal] consider 1 rank data
7599 22:14:36.234862 u2DelayCellTimex100 = 262/100 ps
7600 22:14:36.241422 CA0 delay=43 (13~74),Diff = 7 PI (26 cell)
7601 22:14:36.244661 CA1 delay=43 (13~74),Diff = 7 PI (26 cell)
7602 22:14:36.248773 CA2 delay=39 (10~69),Diff = 3 PI (11 cell)
7603 22:14:36.251324 CA3 delay=39 (9~69),Diff = 3 PI (11 cell)
7604 22:14:36.254745 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
7605 22:14:36.257816 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7606 22:14:36.257898
7607 22:14:36.261344 CA PerBit enable=1, Macro0, CA PI delay=36
7608 22:14:36.261426
7609 22:14:36.264638 [CBTSetCACLKResult] CA Dly = 36
7610 22:14:36.268143 CS Dly: 12 (0~43)
7611 22:14:36.271078 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7612 22:14:36.274317 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7613 22:14:36.274398 ==
7614 22:14:36.277589 Dram Type= 6, Freq= 0, CH_0, rank 1
7615 22:14:36.284109 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7616 22:14:36.284192 ==
7617 22:14:36.287631 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7618 22:14:36.294026 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7619 22:14:36.297305 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7620 22:14:36.303935 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7621 22:14:36.312455 [CA 0] Center 43 (13~74) winsize 62
7622 22:14:36.316092 [CA 1] Center 44 (14~74) winsize 61
7623 22:14:36.319660 [CA 2] Center 38 (9~68) winsize 60
7624 22:14:36.322167 [CA 3] Center 38 (9~68) winsize 60
7625 22:14:36.325972 [CA 4] Center 36 (7~66) winsize 60
7626 22:14:36.328830 [CA 5] Center 36 (7~66) winsize 60
7627 22:14:36.328936
7628 22:14:36.332232 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7629 22:14:36.332313
7630 22:14:36.335238 [CATrainingPosCal] consider 2 rank data
7631 22:14:36.338332 u2DelayCellTimex100 = 262/100 ps
7632 22:14:36.345249 CA0 delay=43 (13~74),Diff = 7 PI (26 cell)
7633 22:14:36.348542 CA1 delay=44 (14~74),Diff = 8 PI (29 cell)
7634 22:14:36.352026 CA2 delay=39 (10~68),Diff = 3 PI (11 cell)
7635 22:14:36.355155 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7636 22:14:36.358200 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
7637 22:14:36.362320 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7638 22:14:36.362401
7639 22:14:36.364888 CA PerBit enable=1, Macro0, CA PI delay=36
7640 22:14:36.364970
7641 22:14:36.368472 [CBTSetCACLKResult] CA Dly = 36
7642 22:14:36.371659 CS Dly: 12 (0~44)
7643 22:14:36.375031 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7644 22:14:36.378113 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7645 22:14:36.378194
7646 22:14:36.381803 ----->DramcWriteLeveling(PI) begin...
7647 22:14:36.381885 ==
7648 22:14:36.385191 Dram Type= 6, Freq= 0, CH_0, rank 0
7649 22:14:36.391214 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7650 22:14:36.391319 ==
7651 22:14:36.394958 Write leveling (Byte 0): 35 => 35
7652 22:14:36.398045 Write leveling (Byte 1): 26 => 26
7653 22:14:36.401943 DramcWriteLeveling(PI) end<-----
7654 22:14:36.402020
7655 22:14:36.402082 ==
7656 22:14:36.405028 Dram Type= 6, Freq= 0, CH_0, rank 0
7657 22:14:36.407787 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7658 22:14:36.407887 ==
7659 22:14:36.411015 [Gating] SW mode calibration
7660 22:14:36.417651 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7661 22:14:36.424821 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7662 22:14:36.427967 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7663 22:14:36.430918 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7664 22:14:36.437580 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7665 22:14:36.440674 1 4 12 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
7666 22:14:36.444695 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7667 22:14:36.447753 1 4 20 | B1->B0 | 2626 3434 | 0 1 | (0 0) (1 1)
7668 22:14:36.453875 1 4 24 | B1->B0 | 2f2f 3434 | 1 1 | (1 1) (1 1)
7669 22:14:36.457343 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7670 22:14:36.463973 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7671 22:14:36.467139 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7672 22:14:36.470410 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7673 22:14:36.477030 1 5 12 | B1->B0 | 3434 2c2c | 1 0 | (1 1) (0 0)
7674 22:14:36.480433 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
7675 22:14:36.483820 1 5 20 | B1->B0 | 3333 2323 | 0 0 | (1 0) (0 0)
7676 22:14:36.490340 1 5 24 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
7677 22:14:36.493734 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7678 22:14:36.496734 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7679 22:14:36.503120 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7680 22:14:36.506439 1 6 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7681 22:14:36.510121 1 6 12 | B1->B0 | 2323 3c3c | 0 1 | (0 0) (0 0)
7682 22:14:36.516731 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7683 22:14:36.520252 1 6 20 | B1->B0 | 2d2c 4646 | 1 0 | (0 0) (0 0)
7684 22:14:36.523261 1 6 24 | B1->B0 | 4141 4646 | 1 0 | (0 0) (0 0)
7685 22:14:36.529900 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7686 22:14:36.532959 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7687 22:14:36.536184 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7688 22:14:36.542746 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7689 22:14:36.546026 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7690 22:14:36.549223 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7691 22:14:36.555943 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7692 22:14:36.559264 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7693 22:14:36.562662 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7694 22:14:36.569333 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7695 22:14:36.572720 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7696 22:14:36.575968 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7697 22:14:36.582782 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7698 22:14:36.585869 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7699 22:14:36.589337 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7700 22:14:36.595973 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7701 22:14:36.598995 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7702 22:14:36.602843 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7703 22:14:36.608938 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7704 22:14:36.611963 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7705 22:14:36.615917 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7706 22:14:36.622098 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7707 22:14:36.622196 Total UI for P1: 0, mck2ui 16
7708 22:14:36.625630 best dqsien dly found for B0: ( 1, 9, 10)
7709 22:14:36.632585 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7710 22:14:36.635602 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7711 22:14:36.638778 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7712 22:14:36.642136 Total UI for P1: 0, mck2ui 16
7713 22:14:36.645156 best dqsien dly found for B1: ( 1, 9, 22)
7714 22:14:36.648348 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7715 22:14:36.655400 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7716 22:14:36.655504
7717 22:14:36.658386 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7718 22:14:36.661730 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7719 22:14:36.665206 [Gating] SW calibration Done
7720 22:14:36.665303 ==
7721 22:14:36.668486 Dram Type= 6, Freq= 0, CH_0, rank 0
7722 22:14:36.672093 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7723 22:14:36.672190 ==
7724 22:14:36.674795 RX Vref Scan: 0
7725 22:14:36.674902
7726 22:14:36.674995 RX Vref 0 -> 0, step: 1
7727 22:14:36.675083
7728 22:14:36.678648 RX Delay 0 -> 252, step: 8
7729 22:14:36.682162 iDelay=200, Bit 0, Center 135 (88 ~ 183) 96
7730 22:14:36.684751 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7731 22:14:36.691673 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
7732 22:14:36.694762 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7733 22:14:36.698317 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7734 22:14:36.701555 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7735 22:14:36.704699 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
7736 22:14:36.711437 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7737 22:14:36.714815 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
7738 22:14:36.718354 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7739 22:14:36.721419 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
7740 22:14:36.724943 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7741 22:14:36.731530 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7742 22:14:36.734585 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
7743 22:14:36.738227 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7744 22:14:36.741385 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7745 22:14:36.741483 ==
7746 22:14:36.744599 Dram Type= 6, Freq= 0, CH_0, rank 0
7747 22:14:36.751219 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7748 22:14:36.751323 ==
7749 22:14:36.751422 DQS Delay:
7750 22:14:36.754488 DQS0 = 0, DQS1 = 0
7751 22:14:36.754593 DQM Delay:
7752 22:14:36.757570 DQM0 = 135, DQM1 = 126
7753 22:14:36.757676 DQ Delay:
7754 22:14:36.761124 DQ0 =135, DQ1 =139, DQ2 =131, DQ3 =131
7755 22:14:36.764520 DQ4 =135, DQ5 =123, DQ6 =139, DQ7 =147
7756 22:14:36.767434 DQ8 =119, DQ9 =115, DQ10 =127, DQ11 =119
7757 22:14:36.771048 DQ12 =131, DQ13 =131, DQ14 =139, DQ15 =131
7758 22:14:36.771160
7759 22:14:36.771254
7760 22:14:36.771349 ==
7761 22:14:36.774012 Dram Type= 6, Freq= 0, CH_0, rank 0
7762 22:14:36.780616 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7763 22:14:36.780768 ==
7764 22:14:36.780866
7765 22:14:36.780959
7766 22:14:36.781055 TX Vref Scan disable
7767 22:14:36.784285 == TX Byte 0 ==
7768 22:14:36.787514 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7769 22:14:36.794256 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7770 22:14:36.794362 == TX Byte 1 ==
7771 22:14:36.797412 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7772 22:14:36.804208 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7773 22:14:36.804312 ==
7774 22:14:36.807455 Dram Type= 6, Freq= 0, CH_0, rank 0
7775 22:14:36.810873 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7776 22:14:36.810983 ==
7777 22:14:36.823796
7778 22:14:36.827230 TX Vref early break, caculate TX vref
7779 22:14:36.830705 TX Vref=16, minBit 4, minWin=22, winSum=370
7780 22:14:36.834549 TX Vref=18, minBit 1, minWin=23, winSum=380
7781 22:14:36.837708 TX Vref=20, minBit 1, minWin=23, winSum=388
7782 22:14:36.840896 TX Vref=22, minBit 1, minWin=24, winSum=395
7783 22:14:36.844730 TX Vref=24, minBit 1, minWin=25, winSum=411
7784 22:14:36.850176 TX Vref=26, minBit 0, minWin=24, winSum=412
7785 22:14:36.854043 TX Vref=28, minBit 4, minWin=25, winSum=416
7786 22:14:36.857150 TX Vref=30, minBit 0, minWin=24, winSum=409
7787 22:14:36.860754 TX Vref=32, minBit 0, minWin=24, winSum=398
7788 22:14:36.863551 TX Vref=34, minBit 4, minWin=22, winSum=391
7789 22:14:36.870491 [TxChooseVref] Worse bit 4, Min win 25, Win sum 416, Final Vref 28
7790 22:14:36.870573
7791 22:14:36.873467 Final TX Range 0 Vref 28
7792 22:14:36.873549
7793 22:14:36.873613 ==
7794 22:14:36.876802 Dram Type= 6, Freq= 0, CH_0, rank 0
7795 22:14:36.880270 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7796 22:14:36.880352 ==
7797 22:14:36.880417
7798 22:14:36.880477
7799 22:14:36.883386 TX Vref Scan disable
7800 22:14:36.889945 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
7801 22:14:36.890030 == TX Byte 0 ==
7802 22:14:36.893378 u2DelayCellOfst[0]=14 cells (4 PI)
7803 22:14:36.896762 u2DelayCellOfst[1]=18 cells (5 PI)
7804 22:14:36.900178 u2DelayCellOfst[2]=14 cells (4 PI)
7805 22:14:36.903552 u2DelayCellOfst[3]=14 cells (4 PI)
7806 22:14:36.906746 u2DelayCellOfst[4]=11 cells (3 PI)
7807 22:14:36.909992 u2DelayCellOfst[5]=0 cells (0 PI)
7808 22:14:36.913728 u2DelayCellOfst[6]=18 cells (5 PI)
7809 22:14:36.916892 u2DelayCellOfst[7]=22 cells (6 PI)
7810 22:14:36.919983 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
7811 22:14:36.923604 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7812 22:14:36.926693 == TX Byte 1 ==
7813 22:14:36.930177 u2DelayCellOfst[8]=0 cells (0 PI)
7814 22:14:36.933367 u2DelayCellOfst[9]=0 cells (0 PI)
7815 22:14:36.933448 u2DelayCellOfst[10]=3 cells (1 PI)
7816 22:14:36.936109 u2DelayCellOfst[11]=0 cells (0 PI)
7817 22:14:36.939516 u2DelayCellOfst[12]=11 cells (3 PI)
7818 22:14:36.943154 u2DelayCellOfst[13]=11 cells (3 PI)
7819 22:14:36.946320 u2DelayCellOfst[14]=14 cells (4 PI)
7820 22:14:36.949702 u2DelayCellOfst[15]=7 cells (2 PI)
7821 22:14:36.956432 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7822 22:14:36.960199 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7823 22:14:36.960280 DramC Write-DBI on
7824 22:14:36.960344 ==
7825 22:14:36.962832 Dram Type= 6, Freq= 0, CH_0, rank 0
7826 22:14:36.969817 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7827 22:14:36.969899 ==
7828 22:14:36.969963
7829 22:14:36.970022
7830 22:14:36.970078 TX Vref Scan disable
7831 22:14:36.973656 == TX Byte 0 ==
7832 22:14:36.977022 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
7833 22:14:36.980271 == TX Byte 1 ==
7834 22:14:36.983521 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
7835 22:14:36.986870 DramC Write-DBI off
7836 22:14:36.986946
7837 22:14:36.987009 [DATLAT]
7838 22:14:36.987069 Freq=1600, CH0 RK0
7839 22:14:36.987127
7840 22:14:36.989977 DATLAT Default: 0xf
7841 22:14:36.990045 0, 0xFFFF, sum = 0
7842 22:14:36.993529 1, 0xFFFF, sum = 0
7843 22:14:36.996986 2, 0xFFFF, sum = 0
7844 22:14:36.997060 3, 0xFFFF, sum = 0
7845 22:14:37.000709 4, 0xFFFF, sum = 0
7846 22:14:37.000781 5, 0xFFFF, sum = 0
7847 22:14:37.003151 6, 0xFFFF, sum = 0
7848 22:14:37.003223 7, 0xFFFF, sum = 0
7849 22:14:37.006929 8, 0xFFFF, sum = 0
7850 22:14:37.007001 9, 0xFFFF, sum = 0
7851 22:14:37.009915 10, 0xFFFF, sum = 0
7852 22:14:37.009986 11, 0xFFFF, sum = 0
7853 22:14:37.013723 12, 0xFFFF, sum = 0
7854 22:14:37.013796 13, 0xFFFF, sum = 0
7855 22:14:37.016533 14, 0x0, sum = 1
7856 22:14:37.016628 15, 0x0, sum = 2
7857 22:14:37.019895 16, 0x0, sum = 3
7858 22:14:37.019966 17, 0x0, sum = 4
7859 22:14:37.023140 best_step = 15
7860 22:14:37.023217
7861 22:14:37.023276 ==
7862 22:14:37.026821 Dram Type= 6, Freq= 0, CH_0, rank 0
7863 22:14:37.030285 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7864 22:14:37.030358 ==
7865 22:14:37.034225 RX Vref Scan: 1
7866 22:14:37.034297
7867 22:14:37.034357 Set Vref Range= 24 -> 127
7868 22:14:37.034414
7869 22:14:37.036230 RX Vref 24 -> 127, step: 1
7870 22:14:37.036312
7871 22:14:37.039715 RX Delay 19 -> 252, step: 4
7872 22:14:37.039790
7873 22:14:37.042937 Set Vref, RX VrefLevel [Byte0]: 24
7874 22:14:37.046480 [Byte1]: 24
7875 22:14:37.046562
7876 22:14:37.049825 Set Vref, RX VrefLevel [Byte0]: 25
7877 22:14:37.052692 [Byte1]: 25
7878 22:14:37.056129
7879 22:14:37.056210 Set Vref, RX VrefLevel [Byte0]: 26
7880 22:14:37.059790 [Byte1]: 26
7881 22:14:37.063945
7882 22:14:37.064026 Set Vref, RX VrefLevel [Byte0]: 27
7883 22:14:37.067367 [Byte1]: 27
7884 22:14:37.071288
7885 22:14:37.071368 Set Vref, RX VrefLevel [Byte0]: 28
7886 22:14:37.074820 [Byte1]: 28
7887 22:14:37.079478
7888 22:14:37.079576 Set Vref, RX VrefLevel [Byte0]: 29
7889 22:14:37.082343 [Byte1]: 29
7890 22:14:37.086687
7891 22:14:37.086784 Set Vref, RX VrefLevel [Byte0]: 30
7892 22:14:37.089878 [Byte1]: 30
7893 22:14:37.094140
7894 22:14:37.094244 Set Vref, RX VrefLevel [Byte0]: 31
7895 22:14:37.097821 [Byte1]: 31
7896 22:14:37.101743
7897 22:14:37.101825 Set Vref, RX VrefLevel [Byte0]: 32
7898 22:14:37.104813 [Byte1]: 32
7899 22:14:37.109381
7900 22:14:37.109462 Set Vref, RX VrefLevel [Byte0]: 33
7901 22:14:37.112558 [Byte1]: 33
7902 22:14:37.117084
7903 22:14:37.117189 Set Vref, RX VrefLevel [Byte0]: 34
7904 22:14:37.120104 [Byte1]: 34
7905 22:14:37.124465
7906 22:14:37.124598 Set Vref, RX VrefLevel [Byte0]: 35
7907 22:14:37.127565 [Byte1]: 35
7908 22:14:37.131754
7909 22:14:37.131835 Set Vref, RX VrefLevel [Byte0]: 36
7910 22:14:37.135565 [Byte1]: 36
7911 22:14:37.139986
7912 22:14:37.140067 Set Vref, RX VrefLevel [Byte0]: 37
7913 22:14:37.145963 [Byte1]: 37
7914 22:14:37.146045
7915 22:14:37.149192 Set Vref, RX VrefLevel [Byte0]: 38
7916 22:14:37.152508 [Byte1]: 38
7917 22:14:37.152636
7918 22:14:37.155890 Set Vref, RX VrefLevel [Byte0]: 39
7919 22:14:37.159852 [Byte1]: 39
7920 22:14:37.162265
7921 22:14:37.162374 Set Vref, RX VrefLevel [Byte0]: 40
7922 22:14:37.165928 [Byte1]: 40
7923 22:14:37.170034
7924 22:14:37.170116 Set Vref, RX VrefLevel [Byte0]: 41
7925 22:14:37.173379 [Byte1]: 41
7926 22:14:37.177689
7927 22:14:37.177770 Set Vref, RX VrefLevel [Byte0]: 42
7928 22:14:37.181226 [Byte1]: 42
7929 22:14:37.184933
7930 22:14:37.185014 Set Vref, RX VrefLevel [Byte0]: 43
7931 22:14:37.188637 [Byte1]: 43
7932 22:14:37.192661
7933 22:14:37.192772 Set Vref, RX VrefLevel [Byte0]: 44
7934 22:14:37.195922 [Byte1]: 44
7935 22:14:37.200348
7936 22:14:37.200439 Set Vref, RX VrefLevel [Byte0]: 45
7937 22:14:37.203249 [Byte1]: 45
7938 22:14:37.207629
7939 22:14:37.207710 Set Vref, RX VrefLevel [Byte0]: 46
7940 22:14:37.211046 [Byte1]: 46
7941 22:14:37.215469
7942 22:14:37.215551 Set Vref, RX VrefLevel [Byte0]: 47
7943 22:14:37.218603 [Byte1]: 47
7944 22:14:37.222793
7945 22:14:37.222898 Set Vref, RX VrefLevel [Byte0]: 48
7946 22:14:37.226104 [Byte1]: 48
7947 22:14:37.230526
7948 22:14:37.230607 Set Vref, RX VrefLevel [Byte0]: 49
7949 22:14:37.233571 [Byte1]: 49
7950 22:14:37.237885
7951 22:14:37.237967 Set Vref, RX VrefLevel [Byte0]: 50
7952 22:14:37.241566 [Byte1]: 50
7953 22:14:37.245545
7954 22:14:37.245626 Set Vref, RX VrefLevel [Byte0]: 51
7955 22:14:37.248722 [Byte1]: 51
7956 22:14:37.253217
7957 22:14:37.253299 Set Vref, RX VrefLevel [Byte0]: 52
7958 22:14:37.256413 [Byte1]: 52
7959 22:14:37.260673
7960 22:14:37.260745 Set Vref, RX VrefLevel [Byte0]: 53
7961 22:14:37.264061 [Byte1]: 53
7962 22:14:37.268468
7963 22:14:37.268590 Set Vref, RX VrefLevel [Byte0]: 54
7964 22:14:37.271779 [Byte1]: 54
7965 22:14:37.275916
7966 22:14:37.275995 Set Vref, RX VrefLevel [Byte0]: 55
7967 22:14:37.279065 [Byte1]: 55
7968 22:14:37.283664
7969 22:14:37.283737 Set Vref, RX VrefLevel [Byte0]: 56
7970 22:14:37.286472 [Byte1]: 56
7971 22:14:37.290999
7972 22:14:37.291072 Set Vref, RX VrefLevel [Byte0]: 57
7973 22:14:37.294304 [Byte1]: 57
7974 22:14:37.298719
7975 22:14:37.298785 Set Vref, RX VrefLevel [Byte0]: 58
7976 22:14:37.301900 [Byte1]: 58
7977 22:14:37.306111
7978 22:14:37.306184 Set Vref, RX VrefLevel [Byte0]: 59
7979 22:14:37.309627 [Byte1]: 59
7980 22:14:37.313990
7981 22:14:37.314071 Set Vref, RX VrefLevel [Byte0]: 60
7982 22:14:37.316908 [Byte1]: 60
7983 22:14:37.321106
7984 22:14:37.321219 Set Vref, RX VrefLevel [Byte0]: 61
7985 22:14:37.325115 [Byte1]: 61
7986 22:14:37.329097
7987 22:14:37.329180 Set Vref, RX VrefLevel [Byte0]: 62
7988 22:14:37.332556 [Byte1]: 62
7989 22:14:37.336689
7990 22:14:37.336765 Set Vref, RX VrefLevel [Byte0]: 63
7991 22:14:37.339866 [Byte1]: 63
7992 22:14:37.344046
7993 22:14:37.344147 Set Vref, RX VrefLevel [Byte0]: 64
7994 22:14:37.347213 [Byte1]: 64
7995 22:14:37.351651
7996 22:14:37.351759 Set Vref, RX VrefLevel [Byte0]: 65
7997 22:14:37.355292 [Byte1]: 65
7998 22:14:37.359087
7999 22:14:37.359201 Set Vref, RX VrefLevel [Byte0]: 66
8000 22:14:37.363027 [Byte1]: 66
8001 22:14:37.366974
8002 22:14:37.367080 Set Vref, RX VrefLevel [Byte0]: 67
8003 22:14:37.370416 [Byte1]: 67
8004 22:14:37.374357
8005 22:14:37.374456 Set Vref, RX VrefLevel [Byte0]: 68
8006 22:14:37.378232 [Byte1]: 68
8007 22:14:37.382245
8008 22:14:37.382321 Set Vref, RX VrefLevel [Byte0]: 69
8009 22:14:37.385318 [Byte1]: 69
8010 22:14:37.389257
8011 22:14:37.389350 Set Vref, RX VrefLevel [Byte0]: 70
8012 22:14:37.392758 [Byte1]: 70
8013 22:14:37.397017
8014 22:14:37.397121 Set Vref, RX VrefLevel [Byte0]: 71
8015 22:14:37.400658 [Byte1]: 71
8016 22:14:37.404560
8017 22:14:37.404659 Set Vref, RX VrefLevel [Byte0]: 72
8018 22:14:37.407890 [Byte1]: 72
8019 22:14:37.412401
8020 22:14:37.412511 Set Vref, RX VrefLevel [Byte0]: 73
8021 22:14:37.415177 [Byte1]: 73
8022 22:14:37.419553
8023 22:14:37.419680 Set Vref, RX VrefLevel [Byte0]: 74
8024 22:14:37.422941 [Byte1]: 74
8025 22:14:37.427753
8026 22:14:37.427853 Set Vref, RX VrefLevel [Byte0]: 75
8027 22:14:37.430693 [Byte1]: 75
8028 22:14:37.435015
8029 22:14:37.435114 Set Vref, RX VrefLevel [Byte0]: 76
8030 22:14:37.438761 [Byte1]: 76
8031 22:14:37.442677
8032 22:14:37.442776 Set Vref, RX VrefLevel [Byte0]: 77
8033 22:14:37.445902 [Byte1]: 77
8034 22:14:37.449782
8035 22:14:37.449878 Final RX Vref Byte 0 = 69 to rank0
8036 22:14:37.453741 Final RX Vref Byte 1 = 56 to rank0
8037 22:14:37.456735 Final RX Vref Byte 0 = 69 to rank1
8038 22:14:37.459857 Final RX Vref Byte 1 = 56 to rank1==
8039 22:14:37.463258 Dram Type= 6, Freq= 0, CH_0, rank 0
8040 22:14:37.469869 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8041 22:14:37.469967 ==
8042 22:14:37.470046 DQS Delay:
8043 22:14:37.470106 DQS0 = 0, DQS1 = 0
8044 22:14:37.473334 DQM Delay:
8045 22:14:37.473415 DQM0 = 133, DQM1 = 123
8046 22:14:37.476526 DQ Delay:
8047 22:14:37.480170 DQ0 =132, DQ1 =136, DQ2 =130, DQ3 =132
8048 22:14:37.483321 DQ4 =134, DQ5 =122, DQ6 =142, DQ7 =142
8049 22:14:37.487036 DQ8 =114, DQ9 =110, DQ10 =122, DQ11 =118
8050 22:14:37.489904 DQ12 =130, DQ13 =128, DQ14 =136, DQ15 =128
8051 22:14:37.489985
8052 22:14:37.490049
8053 22:14:37.490107
8054 22:14:37.493082 [DramC_TX_OE_Calibration] TA2
8055 22:14:37.496807 Original DQ_B0 (3 6) =30, OEN = 27
8056 22:14:37.499820 Original DQ_B1 (3 6) =30, OEN = 27
8057 22:14:37.503034 24, 0x0, End_B0=24 End_B1=24
8058 22:14:37.503117 25, 0x0, End_B0=25 End_B1=25
8059 22:14:37.506598 26, 0x0, End_B0=26 End_B1=26
8060 22:14:37.509980 27, 0x0, End_B0=27 End_B1=27
8061 22:14:37.513004 28, 0x0, End_B0=28 End_B1=28
8062 22:14:37.516660 29, 0x0, End_B0=29 End_B1=29
8063 22:14:37.516743 30, 0x0, End_B0=30 End_B1=30
8064 22:14:37.519590 31, 0x4141, End_B0=30 End_B1=30
8065 22:14:37.522964 Byte0 end_step=30 best_step=27
8066 22:14:37.526054 Byte1 end_step=30 best_step=27
8067 22:14:37.529480 Byte0 TX OE(2T, 0.5T) = (3, 3)
8068 22:14:37.532942 Byte1 TX OE(2T, 0.5T) = (3, 3)
8069 22:14:37.533052
8070 22:14:37.533145
8071 22:14:37.539271 [DQSOSCAuto] RK0, (LSB)MR18= 0x2011, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 393 ps
8072 22:14:37.543446 CH0 RK0: MR19=303, MR18=2011
8073 22:14:37.549625 CH0_RK0: MR19=0x303, MR18=0x2011, DQSOSC=393, MR23=63, INC=23, DEC=15
8074 22:14:37.549707
8075 22:14:37.552655 ----->DramcWriteLeveling(PI) begin...
8076 22:14:37.552738 ==
8077 22:14:37.556027 Dram Type= 6, Freq= 0, CH_0, rank 1
8078 22:14:37.559319 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8079 22:14:37.559401 ==
8080 22:14:37.562638 Write leveling (Byte 0): 35 => 35
8081 22:14:37.565766 Write leveling (Byte 1): 29 => 29
8082 22:14:37.569288 DramcWriteLeveling(PI) end<-----
8083 22:14:37.569369
8084 22:14:37.569434 ==
8085 22:14:37.573275 Dram Type= 6, Freq= 0, CH_0, rank 1
8086 22:14:37.576094 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8087 22:14:37.576176 ==
8088 22:14:37.579380 [Gating] SW mode calibration
8089 22:14:37.586002 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8090 22:14:37.592326 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8091 22:14:37.595540 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8092 22:14:37.602230 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8093 22:14:37.605376 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8094 22:14:37.609155 1 4 12 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8095 22:14:37.615581 1 4 16 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
8096 22:14:37.619193 1 4 20 | B1->B0 | 2d2c 3434 | 1 1 | (0 0) (1 1)
8097 22:14:37.622167 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8098 22:14:37.629034 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8099 22:14:37.632000 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8100 22:14:37.635790 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8101 22:14:37.642150 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8102 22:14:37.645082 1 5 12 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
8103 22:14:37.648425 1 5 16 | B1->B0 | 3434 2727 | 1 0 | (1 0) (0 0)
8104 22:14:37.655335 1 5 20 | B1->B0 | 2d2d 2323 | 0 0 | (1 0) (0 0)
8105 22:14:37.658330 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8106 22:14:37.661506 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8107 22:14:37.668390 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8108 22:14:37.671730 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8109 22:14:37.675346 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8110 22:14:37.681949 1 6 12 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
8111 22:14:37.684659 1 6 16 | B1->B0 | 2323 4545 | 0 0 | (0 0) (0 0)
8112 22:14:37.688149 1 6 20 | B1->B0 | 3535 4646 | 0 0 | (0 0) (0 0)
8113 22:14:37.694786 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8114 22:14:37.697755 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8115 22:14:37.701121 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8116 22:14:37.707882 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8117 22:14:37.711428 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8118 22:14:37.714236 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8119 22:14:37.720842 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8120 22:14:37.724186 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8121 22:14:37.727656 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8122 22:14:37.734722 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8123 22:14:37.737517 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8124 22:14:37.740654 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8125 22:14:37.747535 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8126 22:14:37.750715 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8127 22:14:37.754284 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8128 22:14:37.760487 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8129 22:14:37.764139 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8130 22:14:37.767441 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8131 22:14:37.773878 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8132 22:14:37.776945 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8133 22:14:37.780556 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8134 22:14:37.787031 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8135 22:14:37.790277 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8136 22:14:37.794049 Total UI for P1: 0, mck2ui 16
8137 22:14:37.797098 best dqsien dly found for B0: ( 1, 9, 10)
8138 22:14:37.800238 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8139 22:14:37.803883 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8140 22:14:37.810293 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8141 22:14:37.813962 Total UI for P1: 0, mck2ui 16
8142 22:14:37.817041 best dqsien dly found for B1: ( 1, 9, 18)
8143 22:14:37.819865 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8144 22:14:37.823168 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8145 22:14:37.823270
8146 22:14:37.826669 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8147 22:14:37.830157 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8148 22:14:37.833254 [Gating] SW calibration Done
8149 22:14:37.833349 ==
8150 22:14:37.836390 Dram Type= 6, Freq= 0, CH_0, rank 1
8151 22:14:37.839847 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8152 22:14:37.842990 ==
8153 22:14:37.843086 RX Vref Scan: 0
8154 22:14:37.843148
8155 22:14:37.846219 RX Vref 0 -> 0, step: 1
8156 22:14:37.846297
8157 22:14:37.846362 RX Delay 0 -> 252, step: 8
8158 22:14:37.853356 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8159 22:14:37.856372 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8160 22:14:37.859593 iDelay=200, Bit 2, Center 131 (72 ~ 191) 120
8161 22:14:37.862918 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8162 22:14:37.866203 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8163 22:14:37.873368 iDelay=200, Bit 5, Center 123 (64 ~ 183) 120
8164 22:14:37.876085 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8165 22:14:37.879406 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8166 22:14:37.883144 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8167 22:14:37.889196 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8168 22:14:37.892737 iDelay=200, Bit 10, Center 127 (64 ~ 191) 128
8169 22:14:37.896241 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8170 22:14:37.899269 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8171 22:14:37.902690 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8172 22:14:37.909095 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8173 22:14:37.912620 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8174 22:14:37.912699 ==
8175 22:14:37.915749 Dram Type= 6, Freq= 0, CH_0, rank 1
8176 22:14:37.919106 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8177 22:14:37.919189 ==
8178 22:14:37.922293 DQS Delay:
8179 22:14:37.922369 DQS0 = 0, DQS1 = 0
8180 22:14:37.922440 DQM Delay:
8181 22:14:37.925578 DQM0 = 133, DQM1 = 127
8182 22:14:37.925655 DQ Delay:
8183 22:14:37.928988 DQ0 =135, DQ1 =135, DQ2 =131, DQ3 =127
8184 22:14:37.932011 DQ4 =135, DQ5 =123, DQ6 =139, DQ7 =143
8185 22:14:37.938981 DQ8 =115, DQ9 =115, DQ10 =127, DQ11 =123
8186 22:14:37.942117 DQ12 =131, DQ13 =135, DQ14 =135, DQ15 =135
8187 22:14:37.942193
8188 22:14:37.942274
8189 22:14:37.942371 ==
8190 22:14:37.946024 Dram Type= 6, Freq= 0, CH_0, rank 1
8191 22:14:37.949195 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8192 22:14:37.949275 ==
8193 22:14:37.949338
8194 22:14:37.949395
8195 22:14:37.952214 TX Vref Scan disable
8196 22:14:37.955411 == TX Byte 0 ==
8197 22:14:37.958619 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8198 22:14:37.962323 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8199 22:14:37.965510 == TX Byte 1 ==
8200 22:14:37.968907 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
8201 22:14:37.972035 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8202 22:14:37.972112 ==
8203 22:14:37.975127 Dram Type= 6, Freq= 0, CH_0, rank 1
8204 22:14:37.978718 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8205 22:14:37.981751 ==
8206 22:14:37.993451
8207 22:14:37.996873 TX Vref early break, caculate TX vref
8208 22:14:38.000033 TX Vref=16, minBit 2, minWin=22, winSum=378
8209 22:14:38.003136 TX Vref=18, minBit 0, minWin=23, winSum=390
8210 22:14:38.006419 TX Vref=20, minBit 0, minWin=24, winSum=401
8211 22:14:38.009634 TX Vref=22, minBit 3, minWin=23, winSum=406
8212 22:14:38.013025 TX Vref=24, minBit 1, minWin=24, winSum=408
8213 22:14:38.019650 TX Vref=26, minBit 0, minWin=24, winSum=417
8214 22:14:38.023139 TX Vref=28, minBit 1, minWin=24, winSum=417
8215 22:14:38.026418 TX Vref=30, minBit 1, minWin=24, winSum=408
8216 22:14:38.029374 TX Vref=32, minBit 0, minWin=24, winSum=400
8217 22:14:38.032708 TX Vref=34, minBit 1, minWin=22, winSum=389
8218 22:14:38.039700 [TxChooseVref] Worse bit 0, Min win 24, Win sum 417, Final Vref 26
8219 22:14:38.039780
8220 22:14:38.043401 Final TX Range 0 Vref 26
8221 22:14:38.043480
8222 22:14:38.043542 ==
8223 22:14:38.046129 Dram Type= 6, Freq= 0, CH_0, rank 1
8224 22:14:38.049216 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8225 22:14:38.049295 ==
8226 22:14:38.049360
8227 22:14:38.049418
8228 22:14:38.052723 TX Vref Scan disable
8229 22:14:38.059459 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8230 22:14:38.059538 == TX Byte 0 ==
8231 22:14:38.062657 u2DelayCellOfst[0]=14 cells (4 PI)
8232 22:14:38.065594 u2DelayCellOfst[1]=18 cells (5 PI)
8233 22:14:38.069032 u2DelayCellOfst[2]=14 cells (4 PI)
8234 22:14:38.072120 u2DelayCellOfst[3]=14 cells (4 PI)
8235 22:14:38.075585 u2DelayCellOfst[4]=11 cells (3 PI)
8236 22:14:38.079101 u2DelayCellOfst[5]=0 cells (0 PI)
8237 22:14:38.081915 u2DelayCellOfst[6]=22 cells (6 PI)
8238 22:14:38.085823 u2DelayCellOfst[7]=22 cells (6 PI)
8239 22:14:38.088812 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
8240 22:14:38.092209 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8241 22:14:38.095939 == TX Byte 1 ==
8242 22:14:38.098724 u2DelayCellOfst[8]=0 cells (0 PI)
8243 22:14:38.101696 u2DelayCellOfst[9]=3 cells (1 PI)
8244 22:14:38.104995 u2DelayCellOfst[10]=7 cells (2 PI)
8245 22:14:38.108309 u2DelayCellOfst[11]=3 cells (1 PI)
8246 22:14:38.111972 u2DelayCellOfst[12]=14 cells (4 PI)
8247 22:14:38.112054 u2DelayCellOfst[13]=14 cells (4 PI)
8248 22:14:38.115312 u2DelayCellOfst[14]=18 cells (5 PI)
8249 22:14:38.118089 u2DelayCellOfst[15]=11 cells (3 PI)
8250 22:14:38.124818 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8251 22:14:38.128029 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8252 22:14:38.131578 DramC Write-DBI on
8253 22:14:38.131659 ==
8254 22:14:38.134848 Dram Type= 6, Freq= 0, CH_0, rank 1
8255 22:14:38.138297 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8256 22:14:38.138395 ==
8257 22:14:38.138505
8258 22:14:38.138583
8259 22:14:38.141439 TX Vref Scan disable
8260 22:14:38.141521 == TX Byte 0 ==
8261 22:14:38.148343 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
8262 22:14:38.148441 == TX Byte 1 ==
8263 22:14:38.151354 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
8264 22:14:38.154756 DramC Write-DBI off
8265 22:14:38.154838
8266 22:14:38.154902 [DATLAT]
8267 22:14:38.158108 Freq=1600, CH0 RK1
8268 22:14:38.158189
8269 22:14:38.158253 DATLAT Default: 0xf
8270 22:14:38.161455 0, 0xFFFF, sum = 0
8271 22:14:38.161538 1, 0xFFFF, sum = 0
8272 22:14:38.164368 2, 0xFFFF, sum = 0
8273 22:14:38.164451 3, 0xFFFF, sum = 0
8274 22:14:38.168233 4, 0xFFFF, sum = 0
8275 22:14:38.171047 5, 0xFFFF, sum = 0
8276 22:14:38.171130 6, 0xFFFF, sum = 0
8277 22:14:38.174283 7, 0xFFFF, sum = 0
8278 22:14:38.174366 8, 0xFFFF, sum = 0
8279 22:14:38.177560 9, 0xFFFF, sum = 0
8280 22:14:38.177643 10, 0xFFFF, sum = 0
8281 22:14:38.181132 11, 0xFFFF, sum = 0
8282 22:14:38.181215 12, 0xFFFF, sum = 0
8283 22:14:38.184250 13, 0xFFFF, sum = 0
8284 22:14:38.184333 14, 0x0, sum = 1
8285 22:14:38.188091 15, 0x0, sum = 2
8286 22:14:38.188174 16, 0x0, sum = 3
8287 22:14:38.191141 17, 0x0, sum = 4
8288 22:14:38.191224 best_step = 15
8289 22:14:38.191288
8290 22:14:38.191348 ==
8291 22:14:38.194190 Dram Type= 6, Freq= 0, CH_0, rank 1
8292 22:14:38.197684 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8293 22:14:38.201436 ==
8294 22:14:38.201532 RX Vref Scan: 0
8295 22:14:38.201597
8296 22:14:38.204457 RX Vref 0 -> 0, step: 1
8297 22:14:38.204562
8298 22:14:38.207389 RX Delay 11 -> 252, step: 4
8299 22:14:38.210748 iDelay=195, Bit 0, Center 130 (79 ~ 182) 104
8300 22:14:38.214145 iDelay=195, Bit 1, Center 132 (79 ~ 186) 108
8301 22:14:38.217419 iDelay=195, Bit 2, Center 124 (71 ~ 178) 108
8302 22:14:38.223976 iDelay=195, Bit 3, Center 128 (79 ~ 178) 100
8303 22:14:38.227206 iDelay=195, Bit 4, Center 132 (79 ~ 186) 108
8304 22:14:38.230492 iDelay=195, Bit 5, Center 120 (67 ~ 174) 108
8305 22:14:38.233886 iDelay=195, Bit 6, Center 138 (87 ~ 190) 104
8306 22:14:38.236957 iDelay=195, Bit 7, Center 140 (87 ~ 194) 108
8307 22:14:38.243770 iDelay=195, Bit 8, Center 114 (59 ~ 170) 112
8308 22:14:38.247032 iDelay=195, Bit 9, Center 112 (55 ~ 170) 116
8309 22:14:38.250277 iDelay=195, Bit 10, Center 126 (71 ~ 182) 112
8310 22:14:38.253798 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8311 22:14:38.257028 iDelay=195, Bit 12, Center 132 (79 ~ 186) 108
8312 22:14:38.263834 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8313 22:14:38.266542 iDelay=195, Bit 14, Center 136 (83 ~ 190) 108
8314 22:14:38.270218 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8315 22:14:38.270313 ==
8316 22:14:38.273801 Dram Type= 6, Freq= 0, CH_0, rank 1
8317 22:14:38.279923 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8318 22:14:38.280006 ==
8319 22:14:38.280074 DQS Delay:
8320 22:14:38.280135 DQS0 = 0, DQS1 = 0
8321 22:14:38.283201 DQM Delay:
8322 22:14:38.283282 DQM0 = 130, DQM1 = 125
8323 22:14:38.286263 DQ Delay:
8324 22:14:38.289516 DQ0 =130, DQ1 =132, DQ2 =124, DQ3 =128
8325 22:14:38.293151 DQ4 =132, DQ5 =120, DQ6 =138, DQ7 =140
8326 22:14:38.296775 DQ8 =114, DQ9 =112, DQ10 =126, DQ11 =120
8327 22:14:38.299377 DQ12 =132, DQ13 =132, DQ14 =136, DQ15 =132
8328 22:14:38.299458
8329 22:14:38.299521
8330 22:14:38.299581
8331 22:14:38.303455 [DramC_TX_OE_Calibration] TA2
8332 22:14:38.306573 Original DQ_B0 (3 6) =30, OEN = 27
8333 22:14:38.309530 Original DQ_B1 (3 6) =30, OEN = 27
8334 22:14:38.313012 24, 0x0, End_B0=24 End_B1=24
8335 22:14:38.313096 25, 0x0, End_B0=25 End_B1=25
8336 22:14:38.315967 26, 0x0, End_B0=26 End_B1=26
8337 22:14:38.319777 27, 0x0, End_B0=27 End_B1=27
8338 22:14:38.322738 28, 0x0, End_B0=28 End_B1=28
8339 22:14:38.325892 29, 0x0, End_B0=29 End_B1=29
8340 22:14:38.325975 30, 0x0, End_B0=30 End_B1=30
8341 22:14:38.329432 31, 0x4141, End_B0=30 End_B1=30
8342 22:14:38.332690 Byte0 end_step=30 best_step=27
8343 22:14:38.335732 Byte1 end_step=30 best_step=27
8344 22:14:38.339357 Byte0 TX OE(2T, 0.5T) = (3, 3)
8345 22:14:38.342615 Byte1 TX OE(2T, 0.5T) = (3, 3)
8346 22:14:38.342708
8347 22:14:38.342770
8348 22:14:38.349399 [DQSOSCAuto] RK1, (LSB)MR18= 0x2104, (MSB)MR19= 0x303, tDQSOscB0 = 408 ps tDQSOscB1 = 393 ps
8349 22:14:38.352460 CH0 RK1: MR19=303, MR18=2104
8350 22:14:38.359015 CH0_RK1: MR19=0x303, MR18=0x2104, DQSOSC=393, MR23=63, INC=23, DEC=15
8351 22:14:38.362453 [RxdqsGatingPostProcess] freq 1600
8352 22:14:38.368810 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8353 22:14:38.368889 best DQS0 dly(2T, 0.5T) = (1, 1)
8354 22:14:38.372151 best DQS1 dly(2T, 0.5T) = (1, 1)
8355 22:14:38.375714 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8356 22:14:38.378603 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8357 22:14:38.382184 best DQS0 dly(2T, 0.5T) = (1, 1)
8358 22:14:38.385079 best DQS1 dly(2T, 0.5T) = (1, 1)
8359 22:14:38.388543 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8360 22:14:38.391984 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8361 22:14:38.395091 Pre-setting of DQS Precalculation
8362 22:14:38.398495 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8363 22:14:38.398575 ==
8364 22:14:38.401826 Dram Type= 6, Freq= 0, CH_1, rank 0
8365 22:14:38.408284 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8366 22:14:38.408365 ==
8367 22:14:38.411765 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8368 22:14:38.418540 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8369 22:14:38.421944 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8370 22:14:38.428134 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8371 22:14:38.435847 [CA 0] Center 42 (12~72) winsize 61
8372 22:14:38.439685 [CA 1] Center 42 (13~72) winsize 60
8373 22:14:38.442388 [CA 2] Center 38 (9~67) winsize 59
8374 22:14:38.446074 [CA 3] Center 37 (8~66) winsize 59
8375 22:14:38.449438 [CA 4] Center 37 (8~67) winsize 60
8376 22:14:38.452401 [CA 5] Center 37 (8~67) winsize 60
8377 22:14:38.452481
8378 22:14:38.455670 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8379 22:14:38.455749
8380 22:14:38.462388 [CATrainingPosCal] consider 1 rank data
8381 22:14:38.462494 u2DelayCellTimex100 = 262/100 ps
8382 22:14:38.468656 CA0 delay=42 (12~72),Diff = 5 PI (18 cell)
8383 22:14:38.472257 CA1 delay=42 (13~72),Diff = 5 PI (18 cell)
8384 22:14:38.475943 CA2 delay=38 (9~67),Diff = 1 PI (3 cell)
8385 22:14:38.478560 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8386 22:14:38.482615 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
8387 22:14:38.485591 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8388 22:14:38.485662
8389 22:14:38.489096 CA PerBit enable=1, Macro0, CA PI delay=37
8390 22:14:38.489166
8391 22:14:38.492275 [CBTSetCACLKResult] CA Dly = 37
8392 22:14:38.495263 CS Dly: 9 (0~40)
8393 22:14:38.498705 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8394 22:14:38.502049 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8395 22:14:38.502147 ==
8396 22:14:38.505268 Dram Type= 6, Freq= 0, CH_1, rank 1
8397 22:14:38.512203 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8398 22:14:38.512307 ==
8399 22:14:38.515395 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8400 22:14:38.521609 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8401 22:14:38.525295 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8402 22:14:38.531635 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8403 22:14:38.538956 [CA 0] Center 42 (13~72) winsize 60
8404 22:14:38.542693 [CA 1] Center 42 (13~72) winsize 60
8405 22:14:38.546145 [CA 2] Center 37 (8~67) winsize 60
8406 22:14:38.549219 [CA 3] Center 37 (8~67) winsize 60
8407 22:14:38.552558 [CA 4] Center 37 (8~67) winsize 60
8408 22:14:38.555797 [CA 5] Center 37 (7~67) winsize 61
8409 22:14:38.555880
8410 22:14:38.559013 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8411 22:14:38.559095
8412 22:14:38.562098 [CATrainingPosCal] consider 2 rank data
8413 22:14:38.565450 u2DelayCellTimex100 = 262/100 ps
8414 22:14:38.571956 CA0 delay=42 (13~72),Diff = 5 PI (18 cell)
8415 22:14:38.575374 CA1 delay=42 (13~72),Diff = 5 PI (18 cell)
8416 22:14:38.578840 CA2 delay=38 (9~67),Diff = 1 PI (3 cell)
8417 22:14:38.582699 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8418 22:14:38.585295 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
8419 22:14:38.588787 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8420 22:14:38.588865
8421 22:14:38.591831 CA PerBit enable=1, Macro0, CA PI delay=37
8422 22:14:38.591905
8423 22:14:38.594979 [CBTSetCACLKResult] CA Dly = 37
8424 22:14:38.598633 CS Dly: 10 (0~43)
8425 22:14:38.601462 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8426 22:14:38.604777 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8427 22:14:38.604859
8428 22:14:38.608056 ----->DramcWriteLeveling(PI) begin...
8429 22:14:38.608138 ==
8430 22:14:38.611260 Dram Type= 6, Freq= 0, CH_1, rank 0
8431 22:14:38.618105 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8432 22:14:38.618187 ==
8433 22:14:38.621573 Write leveling (Byte 0): 25 => 25
8434 22:14:38.624422 Write leveling (Byte 1): 26 => 26
8435 22:14:38.628109 DramcWriteLeveling(PI) end<-----
8436 22:14:38.628222
8437 22:14:38.628314 ==
8438 22:14:38.631396 Dram Type= 6, Freq= 0, CH_1, rank 0
8439 22:14:38.634347 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8440 22:14:38.634418 ==
8441 22:14:38.638284 [Gating] SW mode calibration
8442 22:14:38.644703 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8443 22:14:38.651096 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8444 22:14:38.654475 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8445 22:14:38.657442 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8446 22:14:38.664119 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8447 22:14:38.667967 1 4 12 | B1->B0 | 2b2a 3232 | 1 0 | (1 1) (0 0)
8448 22:14:38.671278 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8449 22:14:38.674478 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8450 22:14:38.680882 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8451 22:14:38.684229 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8452 22:14:38.687791 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8453 22:14:38.694411 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8454 22:14:38.697177 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8455 22:14:38.700718 1 5 12 | B1->B0 | 2828 2424 | 0 0 | (0 0) (1 0)
8456 22:14:38.707171 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8457 22:14:38.710331 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8458 22:14:38.716997 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8459 22:14:38.720437 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8460 22:14:38.723403 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8461 22:14:38.730177 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8462 22:14:38.733783 1 6 8 | B1->B0 | 2323 3434 | 0 0 | (0 0) (1 1)
8463 22:14:38.736689 1 6 12 | B1->B0 | 4242 4646 | 1 0 | (0 0) (0 0)
8464 22:14:38.743386 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8465 22:14:38.746488 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8466 22:14:38.749766 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8467 22:14:38.756731 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8468 22:14:38.759817 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8469 22:14:38.763046 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8470 22:14:38.769530 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8471 22:14:38.772713 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8472 22:14:38.776206 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8473 22:14:38.783012 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8474 22:14:38.785889 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8475 22:14:38.789756 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8476 22:14:38.796272 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8477 22:14:38.799579 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8478 22:14:38.802847 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8479 22:14:38.809414 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8480 22:14:38.812277 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8481 22:14:38.816250 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8482 22:14:38.821990 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8483 22:14:38.825469 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8484 22:14:38.829014 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8485 22:14:38.835665 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8486 22:14:38.838912 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8487 22:14:38.842003 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8488 22:14:38.845385 Total UI for P1: 0, mck2ui 16
8489 22:14:38.848505 best dqsien dly found for B0: ( 1, 9, 8)
8490 22:14:38.855014 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8491 22:14:38.858728 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8492 22:14:38.861994 Total UI for P1: 0, mck2ui 16
8493 22:14:38.865298 best dqsien dly found for B1: ( 1, 9, 12)
8494 22:14:38.868336 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8495 22:14:38.871677 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8496 22:14:38.871759
8497 22:14:38.875037 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8498 22:14:38.878332 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8499 22:14:38.881542 [Gating] SW calibration Done
8500 22:14:38.881656 ==
8501 22:14:38.885084 Dram Type= 6, Freq= 0, CH_1, rank 0
8502 22:14:38.887918 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8503 22:14:38.891450 ==
8504 22:14:38.891531 RX Vref Scan: 0
8505 22:14:38.891595
8506 22:14:38.894839 RX Vref 0 -> 0, step: 1
8507 22:14:38.894921
8508 22:14:38.894985 RX Delay 0 -> 252, step: 8
8509 22:14:38.901413 iDelay=208, Bit 0, Center 143 (88 ~ 199) 112
8510 22:14:38.904959 iDelay=208, Bit 1, Center 131 (80 ~ 183) 104
8511 22:14:38.907810 iDelay=208, Bit 2, Center 127 (72 ~ 183) 112
8512 22:14:38.911615 iDelay=208, Bit 3, Center 139 (88 ~ 191) 104
8513 22:14:38.917861 iDelay=208, Bit 4, Center 135 (80 ~ 191) 112
8514 22:14:38.921152 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8515 22:14:38.924320 iDelay=208, Bit 6, Center 147 (96 ~ 199) 104
8516 22:14:38.927545 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8517 22:14:38.930782 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8518 22:14:38.937448 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8519 22:14:38.940990 iDelay=208, Bit 10, Center 131 (80 ~ 183) 104
8520 22:14:38.944626 iDelay=208, Bit 11, Center 123 (72 ~ 175) 104
8521 22:14:38.947334 iDelay=208, Bit 12, Center 139 (88 ~ 191) 104
8522 22:14:38.950707 iDelay=208, Bit 13, Center 143 (88 ~ 199) 112
8523 22:14:38.957254 iDelay=208, Bit 14, Center 135 (80 ~ 191) 112
8524 22:14:38.960728 iDelay=208, Bit 15, Center 139 (88 ~ 191) 104
8525 22:14:38.960810 ==
8526 22:14:38.963649 Dram Type= 6, Freq= 0, CH_1, rank 0
8527 22:14:38.967114 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8528 22:14:38.967191 ==
8529 22:14:38.970801 DQS Delay:
8530 22:14:38.970876 DQS0 = 0, DQS1 = 0
8531 22:14:38.973856 DQM Delay:
8532 22:14:38.973933 DQM0 = 138, DQM1 = 130
8533 22:14:38.974014 DQ Delay:
8534 22:14:38.977276 DQ0 =143, DQ1 =131, DQ2 =127, DQ3 =139
8535 22:14:38.984099 DQ4 =135, DQ5 =151, DQ6 =147, DQ7 =135
8536 22:14:38.986917 DQ8 =119, DQ9 =115, DQ10 =131, DQ11 =123
8537 22:14:38.990884 DQ12 =139, DQ13 =143, DQ14 =135, DQ15 =139
8538 22:14:38.990961
8539 22:14:38.991046
8540 22:14:38.991121 ==
8541 22:14:38.993881 Dram Type= 6, Freq= 0, CH_1, rank 0
8542 22:14:38.997122 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8543 22:14:38.997198 ==
8544 22:14:38.997276
8545 22:14:38.997351
8546 22:14:39.000320 TX Vref Scan disable
8547 22:14:39.003612 == TX Byte 0 ==
8548 22:14:39.007020 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8549 22:14:39.010320 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8550 22:14:39.013740 == TX Byte 1 ==
8551 22:14:39.016920 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8552 22:14:39.019915 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8553 22:14:39.019993 ==
8554 22:14:39.023434 Dram Type= 6, Freq= 0, CH_1, rank 0
8555 22:14:39.030020 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8556 22:14:39.030101 ==
8557 22:14:39.041186
8558 22:14:39.044704 TX Vref early break, caculate TX vref
8559 22:14:39.047449 TX Vref=16, minBit 10, minWin=22, winSum=384
8560 22:14:39.050716 TX Vref=18, minBit 0, minWin=23, winSum=387
8561 22:14:39.054286 TX Vref=20, minBit 5, minWin=23, winSum=397
8562 22:14:39.057168 TX Vref=22, minBit 10, minWin=24, winSum=411
8563 22:14:39.064202 TX Vref=24, minBit 0, minWin=25, winSum=419
8564 22:14:39.067103 TX Vref=26, minBit 0, minWin=25, winSum=419
8565 22:14:39.070713 TX Vref=28, minBit 0, minWin=26, winSum=429
8566 22:14:39.073647 TX Vref=30, minBit 1, minWin=25, winSum=417
8567 22:14:39.077083 TX Vref=32, minBit 5, minWin=24, winSum=407
8568 22:14:39.080096 TX Vref=34, minBit 0, minWin=23, winSum=397
8569 22:14:39.087118 [TxChooseVref] Worse bit 0, Min win 26, Win sum 429, Final Vref 28
8570 22:14:39.087198
8571 22:14:39.090156 Final TX Range 0 Vref 28
8572 22:14:39.090232
8573 22:14:39.090316 ==
8574 22:14:39.093798 Dram Type= 6, Freq= 0, CH_1, rank 0
8575 22:14:39.097036 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8576 22:14:39.097110 ==
8577 22:14:39.097190
8578 22:14:39.100223
8579 22:14:39.100298 TX Vref Scan disable
8580 22:14:39.107001 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8581 22:14:39.107080 == TX Byte 0 ==
8582 22:14:39.110686 u2DelayCellOfst[0]=18 cells (5 PI)
8583 22:14:39.113552 u2DelayCellOfst[1]=11 cells (3 PI)
8584 22:14:39.116990 u2DelayCellOfst[2]=0 cells (0 PI)
8585 22:14:39.119634 u2DelayCellOfst[3]=7 cells (2 PI)
8586 22:14:39.123058 u2DelayCellOfst[4]=11 cells (3 PI)
8587 22:14:39.126285 u2DelayCellOfst[5]=22 cells (6 PI)
8588 22:14:39.129560 u2DelayCellOfst[6]=22 cells (6 PI)
8589 22:14:39.132966 u2DelayCellOfst[7]=3 cells (1 PI)
8590 22:14:39.135911 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8591 22:14:39.139747 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8592 22:14:39.143350 == TX Byte 1 ==
8593 22:14:39.145872 u2DelayCellOfst[8]=0 cells (0 PI)
8594 22:14:39.149244 u2DelayCellOfst[9]=3 cells (1 PI)
8595 22:14:39.152448 u2DelayCellOfst[10]=11 cells (3 PI)
8596 22:14:39.155859 u2DelayCellOfst[11]=7 cells (2 PI)
8597 22:14:39.159179 u2DelayCellOfst[12]=18 cells (5 PI)
8598 22:14:39.162498 u2DelayCellOfst[13]=18 cells (5 PI)
8599 22:14:39.165476 u2DelayCellOfst[14]=18 cells (5 PI)
8600 22:14:39.169197 u2DelayCellOfst[15]=18 cells (5 PI)
8601 22:14:39.172309 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8602 22:14:39.175563 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8603 22:14:39.179054 DramC Write-DBI on
8604 22:14:39.179133 ==
8605 22:14:39.182252 Dram Type= 6, Freq= 0, CH_1, rank 0
8606 22:14:39.185310 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8607 22:14:39.185388 ==
8608 22:14:39.185469
8609 22:14:39.185548
8610 22:14:39.188693 TX Vref Scan disable
8611 22:14:39.188767 == TX Byte 0 ==
8612 22:14:39.195323 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8613 22:14:39.195393 == TX Byte 1 ==
8614 22:14:39.201806 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8615 22:14:39.201876 DramC Write-DBI off
8616 22:14:39.201937
8617 22:14:39.201994 [DATLAT]
8618 22:14:39.205022 Freq=1600, CH1 RK0
8619 22:14:39.205094
8620 22:14:39.208397 DATLAT Default: 0xf
8621 22:14:39.208492 0, 0xFFFF, sum = 0
8622 22:14:39.211539 1, 0xFFFF, sum = 0
8623 22:14:39.211611 2, 0xFFFF, sum = 0
8624 22:14:39.215020 3, 0xFFFF, sum = 0
8625 22:14:39.215088 4, 0xFFFF, sum = 0
8626 22:14:39.218299 5, 0xFFFF, sum = 0
8627 22:14:39.218367 6, 0xFFFF, sum = 0
8628 22:14:39.221691 7, 0xFFFF, sum = 0
8629 22:14:39.221792 8, 0xFFFF, sum = 0
8630 22:14:39.225227 9, 0xFFFF, sum = 0
8631 22:14:39.225300 10, 0xFFFF, sum = 0
8632 22:14:39.228338 11, 0xFFFF, sum = 0
8633 22:14:39.228406 12, 0xFFFF, sum = 0
8634 22:14:39.231510 13, 0xFFFF, sum = 0
8635 22:14:39.231586 14, 0x0, sum = 1
8636 22:14:39.234971 15, 0x0, sum = 2
8637 22:14:39.235042 16, 0x0, sum = 3
8638 22:14:39.238085 17, 0x0, sum = 4
8639 22:14:39.238159 best_step = 15
8640 22:14:39.238220
8641 22:14:39.238277 ==
8642 22:14:39.241692 Dram Type= 6, Freq= 0, CH_1, rank 0
8643 22:14:39.248350 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8644 22:14:39.248448 ==
8645 22:14:39.248573 RX Vref Scan: 1
8646 22:14:39.248634
8647 22:14:39.251362 Set Vref Range= 24 -> 127
8648 22:14:39.251430
8649 22:14:39.255412 RX Vref 24 -> 127, step: 1
8650 22:14:39.255484
8651 22:14:39.255543 RX Delay 11 -> 252, step: 4
8652 22:14:39.258301
8653 22:14:39.258376 Set Vref, RX VrefLevel [Byte0]: 24
8654 22:14:39.261415 [Byte1]: 24
8655 22:14:39.265678
8656 22:14:39.265778 Set Vref, RX VrefLevel [Byte0]: 25
8657 22:14:39.268951 [Byte1]: 25
8658 22:14:39.273368
8659 22:14:39.273435 Set Vref, RX VrefLevel [Byte0]: 26
8660 22:14:39.276612 [Byte1]: 26
8661 22:14:39.280724
8662 22:14:39.280796 Set Vref, RX VrefLevel [Byte0]: 27
8663 22:14:39.284029 [Byte1]: 27
8664 22:14:39.288180
8665 22:14:39.291432 Set Vref, RX VrefLevel [Byte0]: 28
8666 22:14:39.294933 [Byte1]: 28
8667 22:14:39.295003
8668 22:14:39.298026 Set Vref, RX VrefLevel [Byte0]: 29
8669 22:14:39.301777 [Byte1]: 29
8670 22:14:39.301848
8671 22:14:39.304634 Set Vref, RX VrefLevel [Byte0]: 30
8672 22:14:39.308268 [Byte1]: 30
8673 22:14:39.308338
8674 22:14:39.311711 Set Vref, RX VrefLevel [Byte0]: 31
8675 22:14:39.314746 [Byte1]: 31
8676 22:14:39.318786
8677 22:14:39.318853 Set Vref, RX VrefLevel [Byte0]: 32
8678 22:14:39.322125 [Byte1]: 32
8679 22:14:39.326466
8680 22:14:39.326545 Set Vref, RX VrefLevel [Byte0]: 33
8681 22:14:39.329733 [Byte1]: 33
8682 22:14:39.334049
8683 22:14:39.334117 Set Vref, RX VrefLevel [Byte0]: 34
8684 22:14:39.337517 [Byte1]: 34
8685 22:14:39.341656
8686 22:14:39.341739 Set Vref, RX VrefLevel [Byte0]: 35
8687 22:14:39.345413 [Byte1]: 35
8688 22:14:39.349306
8689 22:14:39.349387 Set Vref, RX VrefLevel [Byte0]: 36
8690 22:14:39.352656 [Byte1]: 36
8691 22:14:39.356917
8692 22:14:39.356998 Set Vref, RX VrefLevel [Byte0]: 37
8693 22:14:39.360354 [Byte1]: 37
8694 22:14:39.364601
8695 22:14:39.364681 Set Vref, RX VrefLevel [Byte0]: 38
8696 22:14:39.368249 [Byte1]: 38
8697 22:14:39.372325
8698 22:14:39.372406 Set Vref, RX VrefLevel [Byte0]: 39
8699 22:14:39.375263 [Byte1]: 39
8700 22:14:39.379733
8701 22:14:39.379815 Set Vref, RX VrefLevel [Byte0]: 40
8702 22:14:39.382916 [Byte1]: 40
8703 22:14:39.387244
8704 22:14:39.387325 Set Vref, RX VrefLevel [Byte0]: 41
8705 22:14:39.390624 [Byte1]: 41
8706 22:14:39.394776
8707 22:14:39.394857 Set Vref, RX VrefLevel [Byte0]: 42
8708 22:14:39.398073 [Byte1]: 42
8709 22:14:39.402825
8710 22:14:39.402906 Set Vref, RX VrefLevel [Byte0]: 43
8711 22:14:39.406043 [Byte1]: 43
8712 22:14:39.410264
8713 22:14:39.410345 Set Vref, RX VrefLevel [Byte0]: 44
8714 22:14:39.413453 [Byte1]: 44
8715 22:14:39.417762
8716 22:14:39.417843 Set Vref, RX VrefLevel [Byte0]: 45
8717 22:14:39.421325 [Byte1]: 45
8718 22:14:39.425686
8719 22:14:39.425767 Set Vref, RX VrefLevel [Byte0]: 46
8720 22:14:39.428985 [Byte1]: 46
8721 22:14:39.433139
8722 22:14:39.433251 Set Vref, RX VrefLevel [Byte0]: 47
8723 22:14:39.436425 [Byte1]: 47
8724 22:14:39.440879
8725 22:14:39.440985 Set Vref, RX VrefLevel [Byte0]: 48
8726 22:14:39.443974 [Byte1]: 48
8727 22:14:39.448618
8728 22:14:39.448699 Set Vref, RX VrefLevel [Byte0]: 49
8729 22:14:39.451562 [Byte1]: 49
8730 22:14:39.456028
8731 22:14:39.456131 Set Vref, RX VrefLevel [Byte0]: 50
8732 22:14:39.458993 [Byte1]: 50
8733 22:14:39.463611
8734 22:14:39.463714 Set Vref, RX VrefLevel [Byte0]: 51
8735 22:14:39.467286 [Byte1]: 51
8736 22:14:39.471207
8737 22:14:39.471333 Set Vref, RX VrefLevel [Byte0]: 52
8738 22:14:39.474597 [Byte1]: 52
8739 22:14:39.478999
8740 22:14:39.479099 Set Vref, RX VrefLevel [Byte0]: 53
8741 22:14:39.481809 [Byte1]: 53
8742 22:14:39.486830
8743 22:14:39.486925 Set Vref, RX VrefLevel [Byte0]: 54
8744 22:14:39.489397 [Byte1]: 54
8745 22:14:39.493725
8746 22:14:39.493822 Set Vref, RX VrefLevel [Byte0]: 55
8747 22:14:39.497491 [Byte1]: 55
8748 22:14:39.501357
8749 22:14:39.501465 Set Vref, RX VrefLevel [Byte0]: 56
8750 22:14:39.504695 [Byte1]: 56
8751 22:14:39.509492
8752 22:14:39.509572 Set Vref, RX VrefLevel [Byte0]: 57
8753 22:14:39.512435 [Byte1]: 57
8754 22:14:39.517317
8755 22:14:39.517397 Set Vref, RX VrefLevel [Byte0]: 58
8756 22:14:39.520699 [Byte1]: 58
8757 22:14:39.524206
8758 22:14:39.524287 Set Vref, RX VrefLevel [Byte0]: 59
8759 22:14:39.527802 [Byte1]: 59
8760 22:14:39.532130
8761 22:14:39.532211 Set Vref, RX VrefLevel [Byte0]: 60
8762 22:14:39.535762 [Byte1]: 60
8763 22:14:39.539615
8764 22:14:39.539696 Set Vref, RX VrefLevel [Byte0]: 61
8765 22:14:39.543266 [Byte1]: 61
8766 22:14:39.547570
8767 22:14:39.547651 Set Vref, RX VrefLevel [Byte0]: 62
8768 22:14:39.550394 [Byte1]: 62
8769 22:14:39.555212
8770 22:14:39.555292 Set Vref, RX VrefLevel [Byte0]: 63
8771 22:14:39.558167 [Byte1]: 63
8772 22:14:39.562405
8773 22:14:39.562486 Set Vref, RX VrefLevel [Byte0]: 64
8774 22:14:39.566325 [Byte1]: 64
8775 22:14:39.570296
8776 22:14:39.570423 Set Vref, RX VrefLevel [Byte0]: 65
8777 22:14:39.573247 [Byte1]: 65
8778 22:14:39.577505
8779 22:14:39.577585 Set Vref, RX VrefLevel [Byte0]: 66
8780 22:14:39.580977 [Byte1]: 66
8781 22:14:39.585483
8782 22:14:39.588195 Set Vref, RX VrefLevel [Byte0]: 67
8783 22:14:39.591580 [Byte1]: 67
8784 22:14:39.591661
8785 22:14:39.595149 Set Vref, RX VrefLevel [Byte0]: 68
8786 22:14:39.598997 [Byte1]: 68
8787 22:14:39.599078
8788 22:14:39.601529 Set Vref, RX VrefLevel [Byte0]: 69
8789 22:14:39.604765 [Byte1]: 69
8790 22:14:39.607917
8791 22:14:39.607998 Set Vref, RX VrefLevel [Byte0]: 70
8792 22:14:39.611356 [Byte1]: 70
8793 22:14:39.616080
8794 22:14:39.616182 Set Vref, RX VrefLevel [Byte0]: 71
8795 22:14:39.619736 [Byte1]: 71
8796 22:14:39.623732
8797 22:14:39.623813 Set Vref, RX VrefLevel [Byte0]: 72
8798 22:14:39.626604 [Byte1]: 72
8799 22:14:39.630870
8800 22:14:39.630951 Set Vref, RX VrefLevel [Byte0]: 73
8801 22:14:39.634782 [Byte1]: 73
8802 22:14:39.638894
8803 22:14:39.638975 Set Vref, RX VrefLevel [Byte0]: 74
8804 22:14:39.642169 [Byte1]: 74
8805 22:14:39.646332
8806 22:14:39.646413 Set Vref, RX VrefLevel [Byte0]: 75
8807 22:14:39.649503 [Byte1]: 75
8808 22:14:39.653877
8809 22:14:39.653958 Set Vref, RX VrefLevel [Byte0]: 76
8810 22:14:39.657116 [Byte1]: 76
8811 22:14:39.661546
8812 22:14:39.661627 Final RX Vref Byte 0 = 55 to rank0
8813 22:14:39.664758 Final RX Vref Byte 1 = 59 to rank0
8814 22:14:39.668134 Final RX Vref Byte 0 = 55 to rank1
8815 22:14:39.671283 Final RX Vref Byte 1 = 59 to rank1==
8816 22:14:39.674948 Dram Type= 6, Freq= 0, CH_1, rank 0
8817 22:14:39.681993 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8818 22:14:39.682124 ==
8819 22:14:39.682269 DQS Delay:
8820 22:14:39.684833 DQS0 = 0, DQS1 = 0
8821 22:14:39.684906 DQM Delay:
8822 22:14:39.684967 DQM0 = 134, DQM1 = 129
8823 22:14:39.688314 DQ Delay:
8824 22:14:39.691112 DQ0 =142, DQ1 =128, DQ2 =124, DQ3 =132
8825 22:14:39.694583 DQ4 =132, DQ5 =148, DQ6 =144, DQ7 =128
8826 22:14:39.697725 DQ8 =116, DQ9 =118, DQ10 =132, DQ11 =118
8827 22:14:39.701029 DQ12 =138, DQ13 =138, DQ14 =138, DQ15 =138
8828 22:14:39.701107
8829 22:14:39.701169
8830 22:14:39.701226
8831 22:14:39.704603 [DramC_TX_OE_Calibration] TA2
8832 22:14:39.707986 Original DQ_B0 (3 6) =30, OEN = 27
8833 22:14:39.711241 Original DQ_B1 (3 6) =30, OEN = 27
8834 22:14:39.714256 24, 0x0, End_B0=24 End_B1=24
8835 22:14:39.714332 25, 0x0, End_B0=25 End_B1=25
8836 22:14:39.717729 26, 0x0, End_B0=26 End_B1=26
8837 22:14:39.720740 27, 0x0, End_B0=27 End_B1=27
8838 22:14:39.723966 28, 0x0, End_B0=28 End_B1=28
8839 22:14:39.727577 29, 0x0, End_B0=29 End_B1=29
8840 22:14:39.727661 30, 0x0, End_B0=30 End_B1=30
8841 22:14:39.730956 31, 0x4545, End_B0=30 End_B1=30
8842 22:14:39.733891 Byte0 end_step=30 best_step=27
8843 22:14:39.737311 Byte1 end_step=30 best_step=27
8844 22:14:39.740761 Byte0 TX OE(2T, 0.5T) = (3, 3)
8845 22:14:39.743866 Byte1 TX OE(2T, 0.5T) = (3, 3)
8846 22:14:39.743948
8847 22:14:39.744011
8848 22:14:39.750487 [DQSOSCAuto] RK0, (LSB)MR18= 0x1a10, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 396 ps
8849 22:14:39.753843 CH1 RK0: MR19=303, MR18=1A10
8850 22:14:39.760391 CH1_RK0: MR19=0x303, MR18=0x1A10, DQSOSC=396, MR23=63, INC=23, DEC=15
8851 22:14:39.760473
8852 22:14:39.763734 ----->DramcWriteLeveling(PI) begin...
8853 22:14:39.763816 ==
8854 22:14:39.767040 Dram Type= 6, Freq= 0, CH_1, rank 1
8855 22:14:39.770187 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8856 22:14:39.770269 ==
8857 22:14:39.773507 Write leveling (Byte 0): 25 => 25
8858 22:14:39.776875 Write leveling (Byte 1): 27 => 27
8859 22:14:39.779963 DramcWriteLeveling(PI) end<-----
8860 22:14:39.780043
8861 22:14:39.780107 ==
8862 22:14:39.784158 Dram Type= 6, Freq= 0, CH_1, rank 1
8863 22:14:39.787253 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8864 22:14:39.790626 ==
8865 22:14:39.790708 [Gating] SW mode calibration
8866 22:14:39.800622 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8867 22:14:39.803442 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8868 22:14:39.806623 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8869 22:14:39.813121 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8870 22:14:39.816483 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8871 22:14:39.819750 1 4 12 | B1->B0 | 3434 2423 | 1 1 | (1 1) (0 0)
8872 22:14:39.826073 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8873 22:14:39.829863 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8874 22:14:39.832859 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8875 22:14:39.839170 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8876 22:14:39.842634 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8877 22:14:39.846295 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8878 22:14:39.852357 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8879 22:14:39.856071 1 5 12 | B1->B0 | 2626 3434 | 0 1 | (0 0) (1 0)
8880 22:14:39.859032 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8881 22:14:39.866221 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8882 22:14:39.869348 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8883 22:14:39.872494 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8884 22:14:39.879073 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8885 22:14:39.882411 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8886 22:14:39.885730 1 6 8 | B1->B0 | 3232 2323 | 0 0 | (1 1) (0 0)
8887 22:14:39.892369 1 6 12 | B1->B0 | 4646 2e2e | 0 0 | (0 0) (0 0)
8888 22:14:39.895386 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8889 22:14:39.899125 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8890 22:14:39.905939 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8891 22:14:39.908765 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8892 22:14:39.912031 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8893 22:14:39.918788 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8894 22:14:39.921947 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8895 22:14:39.925555 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8896 22:14:39.931931 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8897 22:14:39.935203 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8898 22:14:39.938563 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8899 22:14:39.945443 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8900 22:14:39.948392 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8901 22:14:39.951709 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8902 22:14:39.958765 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8903 22:14:39.961878 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8904 22:14:39.965026 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8905 22:14:39.972219 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8906 22:14:39.975242 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8907 22:14:39.978588 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8908 22:14:39.984964 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8909 22:14:39.988209 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8910 22:14:39.991617 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8911 22:14:39.997928 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8912 22:14:40.001622 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8913 22:14:40.004910 Total UI for P1: 0, mck2ui 16
8914 22:14:40.007925 best dqsien dly found for B0: ( 1, 9, 10)
8915 22:14:40.011616 Total UI for P1: 0, mck2ui 16
8916 22:14:40.014945 best dqsien dly found for B1: ( 1, 9, 10)
8917 22:14:40.018190 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8918 22:14:40.021529 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8919 22:14:40.021611
8920 22:14:40.024589 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8921 22:14:40.027910 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8922 22:14:40.030958 [Gating] SW calibration Done
8923 22:14:40.031040 ==
8924 22:14:40.034202 Dram Type= 6, Freq= 0, CH_1, rank 1
8925 22:14:40.040817 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8926 22:14:40.040899 ==
8927 22:14:40.040964 RX Vref Scan: 0
8928 22:14:40.041025
8929 22:14:40.044467 RX Vref 0 -> 0, step: 1
8930 22:14:40.044558
8931 22:14:40.047649 RX Delay 0 -> 252, step: 8
8932 22:14:40.050964 iDelay=208, Bit 0, Center 139 (80 ~ 199) 120
8933 22:14:40.053928 iDelay=208, Bit 1, Center 131 (72 ~ 191) 120
8934 22:14:40.057687 iDelay=208, Bit 2, Center 123 (64 ~ 183) 120
8935 22:14:40.060903 iDelay=208, Bit 3, Center 135 (80 ~ 191) 112
8936 22:14:40.067135 iDelay=208, Bit 4, Center 135 (72 ~ 199) 128
8937 22:14:40.070465 iDelay=208, Bit 5, Center 147 (88 ~ 207) 120
8938 22:14:40.073540 iDelay=208, Bit 6, Center 147 (88 ~ 207) 120
8939 22:14:40.077149 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8940 22:14:40.080343 iDelay=208, Bit 8, Center 115 (56 ~ 175) 120
8941 22:14:40.086787 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8942 22:14:40.090522 iDelay=208, Bit 10, Center 131 (72 ~ 191) 120
8943 22:14:40.093705 iDelay=208, Bit 11, Center 123 (64 ~ 183) 120
8944 22:14:40.096785 iDelay=208, Bit 12, Center 139 (80 ~ 199) 120
8945 22:14:40.103329 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8946 22:14:40.107032 iDelay=208, Bit 14, Center 135 (80 ~ 191) 112
8947 22:14:40.110145 iDelay=208, Bit 15, Center 139 (80 ~ 199) 120
8948 22:14:40.110247 ==
8949 22:14:40.113399 Dram Type= 6, Freq= 0, CH_1, rank 1
8950 22:14:40.116807 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8951 22:14:40.116913 ==
8952 22:14:40.119946 DQS Delay:
8953 22:14:40.120071 DQS0 = 0, DQS1 = 0
8954 22:14:40.123441 DQM Delay:
8955 22:14:40.123545 DQM0 = 136, DQM1 = 129
8956 22:14:40.127015 DQ Delay:
8957 22:14:40.129794 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8958 22:14:40.133382 DQ4 =135, DQ5 =147, DQ6 =147, DQ7 =135
8959 22:14:40.136437 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =123
8960 22:14:40.139625 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =139
8961 22:14:40.139724
8962 22:14:40.139819
8963 22:14:40.139908 ==
8964 22:14:40.143282 Dram Type= 6, Freq= 0, CH_1, rank 1
8965 22:14:40.146558 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8966 22:14:40.146678 ==
8967 22:14:40.146791
8968 22:14:40.149910
8969 22:14:40.150010 TX Vref Scan disable
8970 22:14:40.153125 == TX Byte 0 ==
8971 22:14:40.156115 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8972 22:14:40.159627 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8973 22:14:40.162650 == TX Byte 1 ==
8974 22:14:40.166268 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8975 22:14:40.169436 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8976 22:14:40.169539 ==
8977 22:14:40.173139 Dram Type= 6, Freq= 0, CH_1, rank 1
8978 22:14:40.179644 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8979 22:14:40.179746 ==
8980 22:14:40.191119
8981 22:14:40.194346 TX Vref early break, caculate TX vref
8982 22:14:40.197612 TX Vref=16, minBit 0, minWin=22, winSum=384
8983 22:14:40.201031 TX Vref=18, minBit 0, minWin=23, winSum=394
8984 22:14:40.204309 TX Vref=20, minBit 3, minWin=24, winSum=405
8985 22:14:40.207824 TX Vref=22, minBit 9, minWin=24, winSum=412
8986 22:14:40.210892 TX Vref=24, minBit 1, minWin=25, winSum=422
8987 22:14:40.218147 TX Vref=26, minBit 0, minWin=25, winSum=426
8988 22:14:40.221137 TX Vref=28, minBit 1, minWin=25, winSum=425
8989 22:14:40.224236 TX Vref=30, minBit 0, minWin=25, winSum=420
8990 22:14:40.227769 TX Vref=32, minBit 0, minWin=25, winSum=410
8991 22:14:40.230820 TX Vref=34, minBit 0, minWin=24, winSum=399
8992 22:14:40.236902 [TxChooseVref] Worse bit 0, Min win 25, Win sum 426, Final Vref 26
8993 22:14:40.237005
8994 22:14:40.240450 Final TX Range 0 Vref 26
8995 22:14:40.240593
8996 22:14:40.240662 ==
8997 22:14:40.243521 Dram Type= 6, Freq= 0, CH_1, rank 1
8998 22:14:40.247080 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8999 22:14:40.247184 ==
9000 22:14:40.247276
9001 22:14:40.247365
9002 22:14:40.250225 TX Vref Scan disable
9003 22:14:40.256691 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
9004 22:14:40.256770 == TX Byte 0 ==
9005 22:14:40.259991 u2DelayCellOfst[0]=18 cells (5 PI)
9006 22:14:40.263833 u2DelayCellOfst[1]=14 cells (4 PI)
9007 22:14:40.266598 u2DelayCellOfst[2]=0 cells (0 PI)
9008 22:14:40.270113 u2DelayCellOfst[3]=11 cells (3 PI)
9009 22:14:40.273459 u2DelayCellOfst[4]=7 cells (2 PI)
9010 22:14:40.276777 u2DelayCellOfst[5]=22 cells (6 PI)
9011 22:14:40.279863 u2DelayCellOfst[6]=22 cells (6 PI)
9012 22:14:40.283346 u2DelayCellOfst[7]=7 cells (2 PI)
9013 22:14:40.286802 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
9014 22:14:40.289746 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
9015 22:14:40.293376 == TX Byte 1 ==
9016 22:14:40.296211 u2DelayCellOfst[8]=0 cells (0 PI)
9017 22:14:40.299672 u2DelayCellOfst[9]=3 cells (1 PI)
9018 22:14:40.303381 u2DelayCellOfst[10]=14 cells (4 PI)
9019 22:14:40.303478 u2DelayCellOfst[11]=7 cells (2 PI)
9020 22:14:40.306570 u2DelayCellOfst[12]=14 cells (4 PI)
9021 22:14:40.309724 u2DelayCellOfst[13]=18 cells (5 PI)
9022 22:14:40.312953 u2DelayCellOfst[14]=18 cells (5 PI)
9023 22:14:40.316232 u2DelayCellOfst[15]=18 cells (5 PI)
9024 22:14:40.323138 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
9025 22:14:40.326206 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
9026 22:14:40.326283 DramC Write-DBI on
9027 22:14:40.329644 ==
9028 22:14:40.329719 Dram Type= 6, Freq= 0, CH_1, rank 1
9029 22:14:40.335938 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9030 22:14:40.336020 ==
9031 22:14:40.336083
9032 22:14:40.336142
9033 22:14:40.339435 TX Vref Scan disable
9034 22:14:40.339530 == TX Byte 0 ==
9035 22:14:40.346318 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
9036 22:14:40.346392 == TX Byte 1 ==
9037 22:14:40.349261 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
9038 22:14:40.352604 DramC Write-DBI off
9039 22:14:40.352701
9040 22:14:40.352799 [DATLAT]
9041 22:14:40.356184 Freq=1600, CH1 RK1
9042 22:14:40.356292
9043 22:14:40.356381 DATLAT Default: 0xf
9044 22:14:40.359648 0, 0xFFFF, sum = 0
9045 22:14:40.359745 1, 0xFFFF, sum = 0
9046 22:14:40.362608 2, 0xFFFF, sum = 0
9047 22:14:40.362711 3, 0xFFFF, sum = 0
9048 22:14:40.365883 4, 0xFFFF, sum = 0
9049 22:14:40.365981 5, 0xFFFF, sum = 0
9050 22:14:40.368718 6, 0xFFFF, sum = 0
9051 22:14:40.372085 7, 0xFFFF, sum = 0
9052 22:14:40.372182 8, 0xFFFF, sum = 0
9053 22:14:40.375586 9, 0xFFFF, sum = 0
9054 22:14:40.375689 10, 0xFFFF, sum = 0
9055 22:14:40.378775 11, 0xFFFF, sum = 0
9056 22:14:40.378872 12, 0xFFFF, sum = 0
9057 22:14:40.382251 13, 0xFFFF, sum = 0
9058 22:14:40.382355 14, 0x0, sum = 1
9059 22:14:40.385501 15, 0x0, sum = 2
9060 22:14:40.385578 16, 0x0, sum = 3
9061 22:14:40.388813 17, 0x0, sum = 4
9062 22:14:40.388911 best_step = 15
9063 22:14:40.389007
9064 22:14:40.389093 ==
9065 22:14:40.392005 Dram Type= 6, Freq= 0, CH_1, rank 1
9066 22:14:40.395420 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9067 22:14:40.398752 ==
9068 22:14:40.398846 RX Vref Scan: 0
9069 22:14:40.398942
9070 22:14:40.402461 RX Vref 0 -> 0, step: 1
9071 22:14:40.402556
9072 22:14:40.402644 RX Delay 11 -> 252, step: 4
9073 22:14:40.409129 iDelay=203, Bit 0, Center 140 (87 ~ 194) 108
9074 22:14:40.412439 iDelay=203, Bit 1, Center 128 (75 ~ 182) 108
9075 22:14:40.415953 iDelay=203, Bit 2, Center 122 (67 ~ 178) 112
9076 22:14:40.419615 iDelay=203, Bit 3, Center 130 (79 ~ 182) 104
9077 22:14:40.423165 iDelay=203, Bit 4, Center 134 (79 ~ 190) 112
9078 22:14:40.429099 iDelay=203, Bit 5, Center 144 (91 ~ 198) 108
9079 22:14:40.432841 iDelay=203, Bit 6, Center 148 (95 ~ 202) 108
9080 22:14:40.435970 iDelay=203, Bit 7, Center 130 (79 ~ 182) 104
9081 22:14:40.438956 iDelay=203, Bit 8, Center 112 (55 ~ 170) 116
9082 22:14:40.445748 iDelay=203, Bit 9, Center 116 (63 ~ 170) 108
9083 22:14:40.449071 iDelay=203, Bit 10, Center 128 (75 ~ 182) 108
9084 22:14:40.452609 iDelay=203, Bit 11, Center 118 (67 ~ 170) 104
9085 22:14:40.455701 iDelay=203, Bit 12, Center 136 (83 ~ 190) 108
9086 22:14:40.458849 iDelay=203, Bit 13, Center 136 (83 ~ 190) 108
9087 22:14:40.465452 iDelay=203, Bit 14, Center 134 (79 ~ 190) 112
9088 22:14:40.468640 iDelay=203, Bit 15, Center 138 (83 ~ 194) 112
9089 22:14:40.468715 ==
9090 22:14:40.472313 Dram Type= 6, Freq= 0, CH_1, rank 1
9091 22:14:40.475346 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9092 22:14:40.475447 ==
9093 22:14:40.478936 DQS Delay:
9094 22:14:40.479032 DQS0 = 0, DQS1 = 0
9095 22:14:40.479137 DQM Delay:
9096 22:14:40.481938 DQM0 = 134, DQM1 = 127
9097 22:14:40.482034 DQ Delay:
9098 22:14:40.485142 DQ0 =140, DQ1 =128, DQ2 =122, DQ3 =130
9099 22:14:40.488674 DQ4 =134, DQ5 =144, DQ6 =148, DQ7 =130
9100 22:14:40.494918 DQ8 =112, DQ9 =116, DQ10 =128, DQ11 =118
9101 22:14:40.498757 DQ12 =136, DQ13 =136, DQ14 =134, DQ15 =138
9102 22:14:40.498844
9103 22:14:40.498907
9104 22:14:40.498963
9105 22:14:40.501522 [DramC_TX_OE_Calibration] TA2
9106 22:14:40.505318 Original DQ_B0 (3 6) =30, OEN = 27
9107 22:14:40.508399 Original DQ_B1 (3 6) =30, OEN = 27
9108 22:14:40.508497 24, 0x0, End_B0=24 End_B1=24
9109 22:14:40.511864 25, 0x0, End_B0=25 End_B1=25
9110 22:14:40.514941 26, 0x0, End_B0=26 End_B1=26
9111 22:14:40.518727 27, 0x0, End_B0=27 End_B1=27
9112 22:14:40.518826 28, 0x0, End_B0=28 End_B1=28
9113 22:14:40.521232 29, 0x0, End_B0=29 End_B1=29
9114 22:14:40.525135 30, 0x0, End_B0=30 End_B1=30
9115 22:14:40.528367 31, 0x4141, End_B0=30 End_B1=30
9116 22:14:40.531762 Byte0 end_step=30 best_step=27
9117 22:14:40.534832 Byte1 end_step=30 best_step=27
9118 22:14:40.534905 Byte0 TX OE(2T, 0.5T) = (3, 3)
9119 22:14:40.538095 Byte1 TX OE(2T, 0.5T) = (3, 3)
9120 22:14:40.538179
9121 22:14:40.538243
9122 22:14:40.548252 [DQSOSCAuto] RK1, (LSB)MR18= 0xb07, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 404 ps
9123 22:14:40.551316 CH1 RK1: MR19=303, MR18=B07
9124 22:14:40.554372 CH1_RK1: MR19=0x303, MR18=0xB07, DQSOSC=404, MR23=63, INC=22, DEC=15
9125 22:14:40.557557 [RxdqsGatingPostProcess] freq 1600
9126 22:14:40.564411 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9127 22:14:40.567792 best DQS0 dly(2T, 0.5T) = (1, 1)
9128 22:14:40.570759 best DQS1 dly(2T, 0.5T) = (1, 1)
9129 22:14:40.574295 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9130 22:14:40.577564 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9131 22:14:40.581012 best DQS0 dly(2T, 0.5T) = (1, 1)
9132 22:14:40.584679 best DQS1 dly(2T, 0.5T) = (1, 1)
9133 22:14:40.584760 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9134 22:14:40.587445 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9135 22:14:40.590645 Pre-setting of DQS Precalculation
9136 22:14:40.597854 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9137 22:14:40.603847 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9138 22:14:40.610081 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9139 22:14:40.610163
9140 22:14:40.610227
9141 22:14:40.613906 [Calibration Summary] 3200 Mbps
9142 22:14:40.616950 CH 0, Rank 0
9143 22:14:40.617031 SW Impedance : PASS
9144 22:14:40.620152 DUTY Scan : NO K
9145 22:14:40.623926 ZQ Calibration : PASS
9146 22:14:40.624008 Jitter Meter : NO K
9147 22:14:40.627060 CBT Training : PASS
9148 22:14:40.630292 Write leveling : PASS
9149 22:14:40.630374 RX DQS gating : PASS
9150 22:14:40.633794 RX DQ/DQS(RDDQC) : PASS
9151 22:14:40.636562 TX DQ/DQS : PASS
9152 22:14:40.636683 RX DATLAT : PASS
9153 22:14:40.639972 RX DQ/DQS(Engine): PASS
9154 22:14:40.640054 TX OE : PASS
9155 22:14:40.643277 All Pass.
9156 22:14:40.643375
9157 22:14:40.643470 CH 0, Rank 1
9158 22:14:40.647199 SW Impedance : PASS
9159 22:14:40.649897 DUTY Scan : NO K
9160 22:14:40.649994 ZQ Calibration : PASS
9161 22:14:40.653066 Jitter Meter : NO K
9162 22:14:40.653209 CBT Training : PASS
9163 22:14:40.656587 Write leveling : PASS
9164 22:14:40.659774 RX DQS gating : PASS
9165 22:14:40.659856 RX DQ/DQS(RDDQC) : PASS
9166 22:14:40.663516 TX DQ/DQS : PASS
9167 22:14:40.666825 RX DATLAT : PASS
9168 22:14:40.666937 RX DQ/DQS(Engine): PASS
9169 22:14:40.669873 TX OE : PASS
9170 22:14:40.669968 All Pass.
9171 22:14:40.670063
9172 22:14:40.673068 CH 1, Rank 0
9173 22:14:40.673162 SW Impedance : PASS
9174 22:14:40.676687 DUTY Scan : NO K
9175 22:14:40.679528 ZQ Calibration : PASS
9176 22:14:40.679624 Jitter Meter : NO K
9177 22:14:40.682964 CBT Training : PASS
9178 22:14:40.686357 Write leveling : PASS
9179 22:14:40.686452 RX DQS gating : PASS
9180 22:14:40.689879 RX DQ/DQS(RDDQC) : PASS
9181 22:14:40.693012 TX DQ/DQS : PASS
9182 22:14:40.693122 RX DATLAT : PASS
9183 22:14:40.695960 RX DQ/DQS(Engine): PASS
9184 22:14:40.699563 TX OE : PASS
9185 22:14:40.699675 All Pass.
9186 22:14:40.699768
9187 22:14:40.699842 CH 1, Rank 1
9188 22:14:40.702873 SW Impedance : PASS
9189 22:14:40.705832 DUTY Scan : NO K
9190 22:14:40.705916 ZQ Calibration : PASS
9191 22:14:40.709324 Jitter Meter : NO K
9192 22:14:40.712288 CBT Training : PASS
9193 22:14:40.712369 Write leveling : PASS
9194 22:14:40.716181 RX DQS gating : PASS
9195 22:14:40.719064 RX DQ/DQS(RDDQC) : PASS
9196 22:14:40.719146 TX DQ/DQS : PASS
9197 22:14:40.722285 RX DATLAT : PASS
9198 22:14:40.725643 RX DQ/DQS(Engine): PASS
9199 22:14:40.725724 TX OE : PASS
9200 22:14:40.725789 All Pass.
9201 22:14:40.725849
9202 22:14:40.729428 DramC Write-DBI on
9203 22:14:40.732688 PER_BANK_REFRESH: Hybrid Mode
9204 22:14:40.732799 TX_TRACKING: ON
9205 22:14:40.742121 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9206 22:14:40.749018 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9207 22:14:40.758532 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9208 22:14:40.761963 [FAST_K] Save calibration result to emmc
9209 22:14:40.765159 sync common calibartion params.
9210 22:14:40.765242 sync cbt_mode0:1, 1:1
9211 22:14:40.768425 dram_init: ddr_geometry: 2
9212 22:14:40.771696 dram_init: ddr_geometry: 2
9213 22:14:40.771780 dram_init: ddr_geometry: 2
9214 22:14:40.775350 0:dram_rank_size:100000000
9215 22:14:40.778218 1:dram_rank_size:100000000
9216 22:14:40.784925 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9217 22:14:40.785010 DFS_SHUFFLE_HW_MODE: ON
9218 22:14:40.788534 dramc_set_vcore_voltage set vcore to 725000
9219 22:14:40.791933 Read voltage for 1600, 0
9220 22:14:40.792016 Vio18 = 0
9221 22:14:40.794790 Vcore = 725000
9222 22:14:40.794873 Vdram = 0
9223 22:14:40.794939 Vddq = 0
9224 22:14:40.798385 Vmddr = 0
9225 22:14:40.798468 switch to 3200 Mbps bootup
9226 22:14:40.801743 [DramcRunTimeConfig]
9227 22:14:40.801827 PHYPLL
9228 22:14:40.805197 DPM_CONTROL_AFTERK: ON
9229 22:14:40.805279 PER_BANK_REFRESH: ON
9230 22:14:40.808695 REFRESH_OVERHEAD_REDUCTION: ON
9231 22:14:40.811210 CMD_PICG_NEW_MODE: OFF
9232 22:14:40.811293 XRTWTW_NEW_MODE: ON
9233 22:14:40.814843 XRTRTR_NEW_MODE: ON
9234 22:14:40.814927 TX_TRACKING: ON
9235 22:14:40.818035 RDSEL_TRACKING: OFF
9236 22:14:40.821630 DQS Precalculation for DVFS: ON
9237 22:14:40.821714 RX_TRACKING: OFF
9238 22:14:40.824748 HW_GATING DBG: ON
9239 22:14:40.824830 ZQCS_ENABLE_LP4: ON
9240 22:14:40.828139 RX_PICG_NEW_MODE: ON
9241 22:14:40.828221 TX_PICG_NEW_MODE: ON
9242 22:14:40.831208 ENABLE_RX_DCM_DPHY: ON
9243 22:14:40.834170 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9244 22:14:40.837783 DUMMY_READ_FOR_TRACKING: OFF
9245 22:14:40.840810 !!! SPM_CONTROL_AFTERK: OFF
9246 22:14:40.840902 !!! SPM could not control APHY
9247 22:14:40.844742 IMPEDANCE_TRACKING: ON
9248 22:14:40.844825 TEMP_SENSOR: ON
9249 22:14:40.848305 HW_SAVE_FOR_SR: OFF
9250 22:14:40.850812 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9251 22:14:40.854237 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9252 22:14:40.857402 Read ODT Tracking: ON
9253 22:14:40.857490 Refresh Rate DeBounce: ON
9254 22:14:40.861193 DFS_NO_QUEUE_FLUSH: ON
9255 22:14:40.864390 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9256 22:14:40.867272 ENABLE_DFS_RUNTIME_MRW: OFF
9257 22:14:40.867353 DDR_RESERVE_NEW_MODE: ON
9258 22:14:40.870765 MR_CBT_SWITCH_FREQ: ON
9259 22:14:40.873992 =========================
9260 22:14:40.892192 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9261 22:14:40.894927 dram_init: ddr_geometry: 2
9262 22:14:40.913248 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9263 22:14:40.916493 dram_init: dram init end (result: 0)
9264 22:14:40.923537 DRAM-K: Full calibration passed in 24666 msecs
9265 22:14:40.926743 MRC: failed to locate region type 0.
9266 22:14:40.926825 DRAM rank0 size:0x100000000,
9267 22:14:40.930327 DRAM rank1 size=0x100000000
9268 22:14:40.939840 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9269 22:14:40.946300 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9270 22:14:40.952635 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9271 22:14:40.962957 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9272 22:14:40.963042 DRAM rank0 size:0x100000000,
9273 22:14:40.965854 DRAM rank1 size=0x100000000
9274 22:14:40.965927 CBMEM:
9275 22:14:40.969396 IMD: root @ 0xfffff000 254 entries.
9276 22:14:40.972802 IMD: root @ 0xffffec00 62 entries.
9277 22:14:40.976052 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9278 22:14:40.982373 WARNING: RO_VPD is uninitialized or empty.
9279 22:14:40.985717 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9280 22:14:40.993467 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9281 22:14:41.006199 read SPI 0x42894 0xe01e: 6223 us, 9219 KB/s, 73.752 Mbps
9282 22:14:41.017384 BS: romstage times (exec / console): total (unknown) / 24153 ms
9283 22:14:41.017467
9284 22:14:41.017531
9285 22:14:41.027510 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9286 22:14:41.031212 ARM64: Exception handlers installed.
9287 22:14:41.033842 ARM64: Testing exception
9288 22:14:41.037428 ARM64: Done test exception
9289 22:14:41.037537 Enumerating buses...
9290 22:14:41.040793 Show all devs... Before device enumeration.
9291 22:14:41.043749 Root Device: enabled 1
9292 22:14:41.046929 CPU_CLUSTER: 0: enabled 1
9293 22:14:41.047031 CPU: 00: enabled 1
9294 22:14:41.050467 Compare with tree...
9295 22:14:41.050569 Root Device: enabled 1
9296 22:14:41.053785 CPU_CLUSTER: 0: enabled 1
9297 22:14:41.057112 CPU: 00: enabled 1
9298 22:14:41.057218 Root Device scanning...
9299 22:14:41.060154 scan_static_bus for Root Device
9300 22:14:41.063748 CPU_CLUSTER: 0 enabled
9301 22:14:41.067350 scan_static_bus for Root Device done
9302 22:14:41.070537 scan_bus: bus Root Device finished in 8 msecs
9303 22:14:41.070638 done
9304 22:14:41.076709 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9305 22:14:41.079836 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9306 22:14:41.086735 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9307 22:14:41.092956 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9308 22:14:41.093036 Allocating resources...
9309 22:14:41.096187 Reading resources...
9310 22:14:41.099593 Root Device read_resources bus 0 link: 0
9311 22:14:41.102883 DRAM rank0 size:0x100000000,
9312 22:14:41.102988 DRAM rank1 size=0x100000000
9313 22:14:41.109545 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9314 22:14:41.109651 CPU: 00 missing read_resources
9315 22:14:41.116473 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9316 22:14:41.119469 Root Device read_resources bus 0 link: 0 done
9317 22:14:41.123008 Done reading resources.
9318 22:14:41.126112 Show resources in subtree (Root Device)...After reading.
9319 22:14:41.129961 Root Device child on link 0 CPU_CLUSTER: 0
9320 22:14:41.132748 CPU_CLUSTER: 0 child on link 0 CPU: 00
9321 22:14:41.143477 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9322 22:14:41.143583 CPU: 00
9323 22:14:41.146098 Root Device assign_resources, bus 0 link: 0
9324 22:14:41.149338 CPU_CLUSTER: 0 missing set_resources
9325 22:14:41.155859 Root Device assign_resources, bus 0 link: 0 done
9326 22:14:41.155966 Done setting resources.
9327 22:14:41.162812 Show resources in subtree (Root Device)...After assigning values.
9328 22:14:41.166274 Root Device child on link 0 CPU_CLUSTER: 0
9329 22:14:41.168975 CPU_CLUSTER: 0 child on link 0 CPU: 00
9330 22:14:41.179296 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9331 22:14:41.179409 CPU: 00
9332 22:14:41.182380 Done allocating resources.
9333 22:14:41.188920 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9334 22:14:41.189011 Enabling resources...
9335 22:14:41.192273 done.
9336 22:14:41.195529 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9337 22:14:41.199017 Initializing devices...
9338 22:14:41.199115 Root Device init
9339 22:14:41.202078 init hardware done!
9340 22:14:41.202152 0x00000018: ctrlr->caps
9341 22:14:41.205668 52.000 MHz: ctrlr->f_max
9342 22:14:41.209113 0.400 MHz: ctrlr->f_min
9343 22:14:41.209196 0x40ff8080: ctrlr->voltages
9344 22:14:41.211982 sclk: 390625
9345 22:14:41.212062 Bus Width = 1
9346 22:14:41.215064 sclk: 390625
9347 22:14:41.215139 Bus Width = 1
9348 22:14:41.218657 Early init status = 3
9349 22:14:41.221802 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9350 22:14:41.225152 in-header: 03 fc 00 00 01 00 00 00
9351 22:14:41.228410 in-data: 00
9352 22:14:41.231625 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9353 22:14:41.237024 in-header: 03 fd 00 00 00 00 00 00
9354 22:14:41.240857 in-data:
9355 22:14:41.243852 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9356 22:14:41.247162 in-header: 03 fc 00 00 01 00 00 00
9357 22:14:41.250833 in-data: 00
9358 22:14:41.254208 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9359 22:14:41.258880 in-header: 03 fd 00 00 00 00 00 00
9360 22:14:41.262012 in-data:
9361 22:14:41.264997 [SSUSB] Setting up USB HOST controller...
9362 22:14:41.268435 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9363 22:14:41.272101 [SSUSB] phy power-on done.
9364 22:14:41.275972 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9365 22:14:41.281638 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9366 22:14:41.284796 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9367 22:14:41.291827 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9368 22:14:41.298513 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9369 22:14:41.304790 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9370 22:14:41.311239 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9371 22:14:41.318020 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9372 22:14:41.321467 SPM: binary array size = 0x9dc
9373 22:14:41.324779 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9374 22:14:41.330952 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9375 22:14:41.337975 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9376 22:14:41.344037 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9377 22:14:41.347534 configure_display: Starting display init
9378 22:14:41.382391 anx7625_power_on_init: Init interface.
9379 22:14:41.385113 anx7625_disable_pd_protocol: Disabled PD feature.
9380 22:14:41.388333 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9381 22:14:41.416631 anx7625_start_dp_work: Secure OCM version=00
9382 22:14:41.419908 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9383 22:14:41.437191 sp_tx_get_edid_block: EDID Block = 1
9384 22:14:41.537408 Extracted contents:
9385 22:14:41.540071 header: 00 ff ff ff ff ff ff 00
9386 22:14:41.543645 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9387 22:14:41.546593 version: 01 04
9388 22:14:41.550218 basic params: 95 1f 11 78 0a
9389 22:14:41.553471 chroma info: 76 90 94 55 54 90 27 21 50 54
9390 22:14:41.556348 established: 00 00 00
9391 22:14:41.563400 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9392 22:14:41.569879 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9393 22:14:41.572681 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9394 22:14:41.579204 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9395 22:14:41.585966 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9396 22:14:41.589782 extensions: 00
9397 22:14:41.589854 checksum: fb
9398 22:14:41.589924
9399 22:14:41.595796 Manufacturer: IVO Model 57d Serial Number 0
9400 22:14:41.595873 Made week 0 of 2020
9401 22:14:41.599306 EDID version: 1.4
9402 22:14:41.599392 Digital display
9403 22:14:41.602465 6 bits per primary color channel
9404 22:14:41.605390 DisplayPort interface
9405 22:14:41.608934 Maximum image size: 31 cm x 17 cm
9406 22:14:41.609004 Gamma: 220%
9407 22:14:41.609068 Check DPMS levels
9408 22:14:41.615723 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9409 22:14:41.618747 First detailed timing is preferred timing
9410 22:14:41.622333 Established timings supported:
9411 22:14:41.622408 Standard timings supported:
9412 22:14:41.625348 Detailed timings
9413 22:14:41.628715 Hex of detail: 383680a07038204018303c0035ae10000019
9414 22:14:41.635736 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9415 22:14:41.638820 0780 0798 07c8 0820 hborder 0
9416 22:14:41.642102 0438 043b 0447 0458 vborder 0
9417 22:14:41.645373 -hsync -vsync
9418 22:14:41.645449 Did detailed timing
9419 22:14:41.651722 Hex of detail: 000000000000000000000000000000000000
9420 22:14:41.655164 Manufacturer-specified data, tag 0
9421 22:14:41.658194 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9422 22:14:41.661950 ASCII string: InfoVision
9423 22:14:41.665579 Hex of detail: 000000fe00523134304e574635205248200a
9424 22:14:41.668347 ASCII string: R140NWF5 RH
9425 22:14:41.668450 Checksum
9426 22:14:41.671915 Checksum: 0xfb (valid)
9427 22:14:41.675200 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9428 22:14:41.678199 DSI data_rate: 832800000 bps
9429 22:14:41.684789 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9430 22:14:41.688114 anx7625_parse_edid: pixelclock(138800).
9431 22:14:41.691491 hactive(1920), hsync(48), hfp(24), hbp(88)
9432 22:14:41.695208 vactive(1080), vsync(12), vfp(3), vbp(17)
9433 22:14:41.697953 anx7625_dsi_config: config dsi.
9434 22:14:41.704662 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9435 22:14:41.718924 anx7625_dsi_config: success to config DSI
9436 22:14:41.722070 anx7625_dp_start: MIPI phy setup OK.
9437 22:14:41.725554 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9438 22:14:41.728455 mtk_ddp_mode_set invalid vrefresh 60
9439 22:14:41.731935 main_disp_path_setup
9440 22:14:41.732026 ovl_layer_smi_id_en
9441 22:14:41.735077 ovl_layer_smi_id_en
9442 22:14:41.735175 ccorr_config
9443 22:14:41.735264 aal_config
9444 22:14:41.738379 gamma_config
9445 22:14:41.738453 postmask_config
9446 22:14:41.741835 dither_config
9447 22:14:41.745110 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9448 22:14:41.752036 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9449 22:14:41.755454 Root Device init finished in 552 msecs
9450 22:14:41.758762 CPU_CLUSTER: 0 init
9451 22:14:41.765197 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9452 22:14:41.771902 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9453 22:14:41.771975 APU_MBOX 0x190000b0 = 0x10001
9454 22:14:41.774950 APU_MBOX 0x190001b0 = 0x10001
9455 22:14:41.778039 APU_MBOX 0x190005b0 = 0x10001
9456 22:14:41.781859 APU_MBOX 0x190006b0 = 0x10001
9457 22:14:41.788110 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9458 22:14:41.797748 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9459 22:14:41.810236 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9460 22:14:41.816845 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9461 22:14:41.828290 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9462 22:14:41.837850 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9463 22:14:41.840698 CPU_CLUSTER: 0 init finished in 81 msecs
9464 22:14:41.844660 Devices initialized
9465 22:14:41.847527 Show all devs... After init.
9466 22:14:41.847599 Root Device: enabled 1
9467 22:14:41.850855 CPU_CLUSTER: 0: enabled 1
9468 22:14:41.854479 CPU: 00: enabled 1
9469 22:14:41.858266 BS: BS_DEV_INIT run times (exec / console): 210 / 447 ms
9470 22:14:41.860687 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9471 22:14:41.863951 ELOG: NV offset 0x57f000 size 0x1000
9472 22:14:41.870903 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9473 22:14:41.877176 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9474 22:14:41.880920 ELOG: Event(17) added with size 13 at 2023-06-05 22:14:46 UTC
9475 22:14:41.887180 out: cmd=0x121: 03 db 21 01 00 00 00 00
9476 22:14:41.890527 in-header: 03 94 00 00 2c 00 00 00
9477 22:14:41.903883 in-data: cb 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9478 22:14:41.910480 ELOG: Event(A1) added with size 10 at 2023-06-05 22:14:46 UTC
9479 22:14:41.917188 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9480 22:14:41.923554 ELOG: Event(A0) added with size 9 at 2023-06-05 22:14:46 UTC
9481 22:14:41.926768 elog_add_boot_reason: Logged dev mode boot
9482 22:14:41.930328 BS: BS_POST_DEVICE entry times (exec / console): 4 / 64 ms
9483 22:14:41.933095 Finalize devices...
9484 22:14:41.933168 Devices finalized
9485 22:14:41.939861 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9486 22:14:41.943063 Writing coreboot table at 0xffe64000
9487 22:14:41.946352 0. 000000000010a000-0000000000113fff: RAMSTAGE
9488 22:14:41.949499 1. 0000000040000000-00000000400fffff: RAM
9489 22:14:41.956376 2. 0000000040100000-000000004032afff: RAMSTAGE
9490 22:14:41.959743 3. 000000004032b000-00000000545fffff: RAM
9491 22:14:41.962694 4. 0000000054600000-000000005465ffff: BL31
9492 22:14:41.965803 5. 0000000054660000-00000000ffe63fff: RAM
9493 22:14:41.972792 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9494 22:14:41.976267 7. 0000000100000000-000000023fffffff: RAM
9495 22:14:41.979383 Passing 5 GPIOs to payload:
9496 22:14:41.982575 NAME | PORT | POLARITY | VALUE
9497 22:14:41.985511 EC in RW | 0x000000aa | low | undefined
9498 22:14:41.992619 EC interrupt | 0x00000005 | low | undefined
9499 22:14:41.995629 TPM interrupt | 0x000000ab | high | undefined
9500 22:14:42.002737 SD card detect | 0x00000011 | high | undefined
9501 22:14:42.005677 speaker enable | 0x00000093 | high | undefined
9502 22:14:42.008961 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9503 22:14:42.012513 in-header: 03 f9 00 00 02 00 00 00
9504 22:14:42.016350 in-data: 02 00
9505 22:14:42.016443 ADC[4]: Raw value=901552 ID=7
9506 22:14:42.018683 ADC[3]: Raw value=213652 ID=1
9507 22:14:42.021900 RAM Code: 0x71
9508 22:14:42.021998 ADC[6]: Raw value=75036 ID=0
9509 22:14:42.025538 ADC[5]: Raw value=212912 ID=1
9510 22:14:42.028383 SKU Code: 0x1
9511 22:14:42.031888 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum a129
9512 22:14:42.035383 coreboot table: 964 bytes.
9513 22:14:42.038646 IMD ROOT 0. 0xfffff000 0x00001000
9514 22:14:42.042147 IMD SMALL 1. 0xffffe000 0x00001000
9515 22:14:42.045571 RO MCACHE 2. 0xffffc000 0x00001104
9516 22:14:42.048472 CONSOLE 3. 0xfff7c000 0x00080000
9517 22:14:42.052034 FMAP 4. 0xfff7b000 0x00000452
9518 22:14:42.054853 TIME STAMP 5. 0xfff7a000 0x00000910
9519 22:14:42.058292 VBOOT WORK 6. 0xfff66000 0x00014000
9520 22:14:42.061385 RAMOOPS 7. 0xffe66000 0x00100000
9521 22:14:42.064585 COREBOOT 8. 0xffe64000 0x00002000
9522 22:14:42.068279 IMD small region:
9523 22:14:42.071610 IMD ROOT 0. 0xffffec00 0x00000400
9524 22:14:42.074735 VPD 1. 0xffffeba0 0x0000004c
9525 22:14:42.077712 MMC STATUS 2. 0xffffeb80 0x00000004
9526 22:14:42.080874 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9527 22:14:42.084612 Probing TPM: done!
9528 22:14:42.088118 Connected to device vid:did:rid of 1ae0:0028:00
9529 22:14:42.098758 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
9530 22:14:42.102502 Initialized TPM device CR50 revision 0
9531 22:14:42.105444 Checking cr50 for pending updates
9532 22:14:42.109509 Reading cr50 TPM mode
9533 22:14:42.118523 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9534 22:14:42.124574 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9535 22:14:42.165123 read SPI 0x3990ec 0x4f1b0: 34847 us, 9298 KB/s, 74.384 Mbps
9536 22:14:42.168334 Checking segment from ROM address 0x40100000
9537 22:14:42.171712 Checking segment from ROM address 0x4010001c
9538 22:14:42.178020 Loading segment from ROM address 0x40100000
9539 22:14:42.178103 code (compression=0)
9540 22:14:42.188250 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9541 22:14:42.194855 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9542 22:14:42.194938 it's not compressed!
9543 22:14:42.201530 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9544 22:14:42.207706 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9545 22:14:42.225293 Loading segment from ROM address 0x4010001c
9546 22:14:42.225379 Entry Point 0x80000000
9547 22:14:42.228931 Loaded segments
9548 22:14:42.231979 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9549 22:14:42.238555 Jumping to boot code at 0x80000000(0xffe64000)
9550 22:14:42.245042 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9551 22:14:42.251475 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9552 22:14:42.259374 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9553 22:14:42.262616 Checking segment from ROM address 0x40100000
9554 22:14:42.266252 Checking segment from ROM address 0x4010001c
9555 22:14:42.272684 Loading segment from ROM address 0x40100000
9556 22:14:42.272767 code (compression=1)
9557 22:14:42.279371 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9558 22:14:42.289198 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9559 22:14:42.289285 using LZMA
9560 22:14:42.297981 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9561 22:14:42.305151 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9562 22:14:42.307955 Loading segment from ROM address 0x4010001c
9563 22:14:42.308038 Entry Point 0x54601000
9564 22:14:42.311043 Loaded segments
9565 22:14:42.314246 NOTICE: MT8192 bl31_setup
9566 22:14:42.321662 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9567 22:14:42.324744 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9568 22:14:42.328122 WARNING: region 0:
9569 22:14:42.331565 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9570 22:14:42.331648 WARNING: region 1:
9571 22:14:42.338273 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9572 22:14:42.341770 WARNING: region 2:
9573 22:14:42.345642 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9574 22:14:42.348740 WARNING: region 3:
9575 22:14:42.351931 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9576 22:14:42.354866 WARNING: region 4:
9577 22:14:42.361321 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9578 22:14:42.361421 WARNING: region 5:
9579 22:14:42.364638 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9580 22:14:42.367793 WARNING: region 6:
9581 22:14:42.371165 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9582 22:14:42.374933 WARNING: region 7:
9583 22:14:42.377849 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9584 22:14:42.384556 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9585 22:14:42.387913 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9586 22:14:42.391118 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9587 22:14:42.397821 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9588 22:14:42.400916 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9589 22:14:42.407929 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9590 22:14:42.410895 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9591 22:14:42.414412 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9592 22:14:42.421296 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9593 22:14:42.424226 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9594 22:14:42.427531 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9595 22:14:42.434117 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9596 22:14:42.437727 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9597 22:14:42.443946 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9598 22:14:42.447389 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9599 22:14:42.451081 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9600 22:14:42.457806 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9601 22:14:42.461125 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9602 22:14:42.463798 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9603 22:14:42.470591 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9604 22:14:42.473892 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9605 22:14:42.480843 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9606 22:14:42.484244 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9607 22:14:42.487723 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9608 22:14:42.493872 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9609 22:14:42.497065 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9610 22:14:42.504479 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9611 22:14:42.507069 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9612 22:14:42.510981 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9613 22:14:42.516912 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9614 22:14:42.521048 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9615 22:14:42.527460 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9616 22:14:42.530751 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9617 22:14:42.534188 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9618 22:14:42.536968 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9619 22:14:42.544054 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9620 22:14:42.547670 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9621 22:14:42.550698 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9622 22:14:42.553792 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9623 22:14:42.560248 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9624 22:14:42.563743 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9625 22:14:42.566733 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9626 22:14:42.570178 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9627 22:14:42.576980 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9628 22:14:42.580001 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9629 22:14:42.583539 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9630 22:14:42.586556 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9631 22:14:42.593537 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9632 22:14:42.597083 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9633 22:14:42.603295 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9634 22:14:42.606724 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9635 22:14:42.610075 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9636 22:14:42.616454 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9637 22:14:42.619783 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9638 22:14:42.627331 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9639 22:14:42.629970 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9640 22:14:42.636663 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9641 22:14:42.639961 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9642 22:14:42.643708 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9643 22:14:42.650832 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9644 22:14:42.654008 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9645 22:14:42.659864 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9646 22:14:42.662986 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9647 22:14:42.669650 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9648 22:14:42.673090 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9649 22:14:42.680123 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9650 22:14:42.683021 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9651 22:14:42.686819 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9652 22:14:42.692940 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9653 22:14:42.696435 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9654 22:14:42.703437 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9655 22:14:42.706675 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9656 22:14:42.713249 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9657 22:14:42.716598 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9658 22:14:42.719477 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9659 22:14:42.726451 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9660 22:14:42.729560 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9661 22:14:42.736429 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9662 22:14:42.739388 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9663 22:14:42.746085 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9664 22:14:42.749161 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9665 22:14:42.756319 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9666 22:14:42.759477 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9667 22:14:42.762631 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9668 22:14:42.769224 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9669 22:14:42.772698 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9670 22:14:42.779483 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9671 22:14:42.782686 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9672 22:14:42.789353 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9673 22:14:42.792345 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9674 22:14:42.799381 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9675 22:14:42.802256 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9676 22:14:42.806249 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9677 22:14:42.812520 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9678 22:14:42.815738 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9679 22:14:42.822160 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9680 22:14:42.825379 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9681 22:14:42.829107 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9682 22:14:42.835556 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9683 22:14:42.839284 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9684 22:14:42.842242 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9685 22:14:42.845242 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9686 22:14:42.852329 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9687 22:14:42.855489 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9688 22:14:42.862492 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9689 22:14:42.866304 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9690 22:14:42.868727 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9691 22:14:42.875637 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9692 22:14:42.878587 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9693 22:14:42.885040 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9694 22:14:42.888320 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9695 22:14:42.894962 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9696 22:14:42.898673 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9697 22:14:42.901733 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9698 22:14:42.908428 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9699 22:14:42.911609 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9700 22:14:42.915120 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9701 22:14:42.921882 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9702 22:14:42.924760 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9703 22:14:42.927991 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9704 22:14:42.935055 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9705 22:14:42.938152 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9706 22:14:42.941819 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9707 22:14:42.944668 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9708 22:14:42.951837 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9709 22:14:42.954955 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9710 22:14:42.961139 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9711 22:14:42.964422 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9712 22:14:42.967712 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9713 22:14:42.974327 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9714 22:14:42.977653 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9715 22:14:42.981004 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9716 22:14:42.987835 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9717 22:14:42.990967 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9718 22:14:42.997604 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9719 22:14:43.001191 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9720 22:14:43.004441 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9721 22:14:43.010723 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9722 22:14:43.014401 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9723 22:14:43.020753 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9724 22:14:43.024304 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9725 22:14:43.027711 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9726 22:14:43.034348 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9727 22:14:43.037702 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9728 22:14:43.044323 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9729 22:14:43.047171 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9730 22:14:43.050545 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9731 22:14:43.057419 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9732 22:14:43.060907 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9733 22:14:43.067117 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9734 22:14:43.070288 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9735 22:14:43.073989 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9736 22:14:43.080472 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9737 22:14:43.083592 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9738 22:14:43.090239 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9739 22:14:43.093685 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9740 22:14:43.097054 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9741 22:14:43.103668 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9742 22:14:43.106875 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9743 22:14:43.110112 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9744 22:14:43.117005 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9745 22:14:43.120719 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9746 22:14:43.126698 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9747 22:14:43.130298 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9748 22:14:43.136731 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9749 22:14:43.139904 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9750 22:14:43.143420 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9751 22:14:43.150224 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9752 22:14:43.153594 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9753 22:14:43.156624 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9754 22:14:43.163056 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9755 22:14:43.166597 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9756 22:14:43.173580 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9757 22:14:43.176627 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9758 22:14:43.179518 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9759 22:14:43.186395 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9760 22:14:43.189571 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9761 22:14:43.196129 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9762 22:14:43.199386 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9763 22:14:43.203312 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9764 22:14:43.209404 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9765 22:14:43.212766 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9766 22:14:43.219563 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9767 22:14:43.222765 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9768 22:14:43.225764 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9769 22:14:43.232407 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9770 22:14:43.235734 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9771 22:14:43.242617 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9772 22:14:43.245849 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9773 22:14:43.252305 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9774 22:14:43.255941 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9775 22:14:43.258697 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9776 22:14:43.265188 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9777 22:14:43.268885 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9778 22:14:43.275474 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9779 22:14:43.279029 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9780 22:14:43.285389 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9781 22:14:43.288484 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9782 22:14:43.292020 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9783 22:14:43.298262 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9784 22:14:43.301489 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9785 22:14:43.308078 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9786 22:14:43.311362 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9787 22:14:43.315137 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9788 22:14:43.321303 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9789 22:14:43.324645 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9790 22:14:43.331256 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9791 22:14:43.335056 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9792 22:14:43.340987 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9793 22:14:43.344662 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9794 22:14:43.347739 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9795 22:14:43.354709 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9796 22:14:43.358102 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9797 22:14:43.364105 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9798 22:14:43.367670 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9799 22:14:43.373894 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9800 22:14:43.377372 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9801 22:14:43.383797 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9802 22:14:43.387413 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9803 22:14:43.390432 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9804 22:14:43.397041 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9805 22:14:43.400878 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9806 22:14:43.406958 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9807 22:14:43.410366 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9808 22:14:43.416777 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9809 22:14:43.420176 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9810 22:14:43.424055 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9811 22:14:43.430394 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9812 22:14:43.433716 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9813 22:14:43.436993 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9814 22:14:43.443358 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9815 22:14:43.446635 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9816 22:14:43.449889 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9817 22:14:43.453282 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9818 22:14:43.460014 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9819 22:14:43.463353 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9820 22:14:43.470024 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9821 22:14:43.473197 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9822 22:14:43.476727 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9823 22:14:43.482988 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9824 22:14:43.486173 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9825 22:14:43.489786 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9826 22:14:43.496272 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9827 22:14:43.500154 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9828 22:14:43.502967 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9829 22:14:43.509269 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9830 22:14:43.512434 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9831 22:14:43.519396 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9832 22:14:43.522573 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9833 22:14:43.525871 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9834 22:14:43.532119 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9835 22:14:43.535462 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9836 22:14:43.542157 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9837 22:14:43.545288 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9838 22:14:43.548700 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9839 22:14:43.555345 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9840 22:14:43.558476 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9841 22:14:43.561933 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9842 22:14:43.568833 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9843 22:14:43.571952 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9844 22:14:43.575246 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9845 22:14:43.581922 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9846 22:14:43.585062 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9847 22:14:43.588666 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9848 22:14:43.595327 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9849 22:14:43.598440 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9850 22:14:43.604958 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9851 22:14:43.608403 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9852 22:14:43.611908 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9853 22:14:43.618449 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9854 22:14:43.621742 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9855 22:14:43.625300 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9856 22:14:43.628376 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9857 22:14:43.631421 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9858 22:14:43.638414 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9859 22:14:43.641552 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9860 22:14:43.645083 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9861 22:14:43.651806 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9862 22:14:43.654458 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9863 22:14:43.658027 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9864 22:14:43.661097 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9865 22:14:43.667729 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9866 22:14:43.671099 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9867 22:14:43.677592 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9868 22:14:43.681157 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9869 22:14:43.684603 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9870 22:14:43.690979 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9871 22:14:43.694377 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9872 22:14:43.701084 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9873 22:14:43.704088 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9874 22:14:43.707429 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9875 22:14:43.714096 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9876 22:14:43.717681 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9877 22:14:43.723730 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9878 22:14:43.726999 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9879 22:14:43.734207 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9880 22:14:43.736995 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9881 22:14:43.740796 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9882 22:14:43.747253 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9883 22:14:43.750209 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9884 22:14:43.756924 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9885 22:14:43.760390 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9886 22:14:43.763325 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9887 22:14:43.769976 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9888 22:14:43.773230 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9889 22:14:43.780178 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9890 22:14:43.783144 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9891 22:14:43.790230 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9892 22:14:43.793560 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9893 22:14:43.796672 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9894 22:14:43.803062 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9895 22:14:43.806430 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9896 22:14:43.812995 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9897 22:14:43.816434 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9898 22:14:43.819909 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9899 22:14:43.826441 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9900 22:14:43.829622 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9901 22:14:43.836307 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9902 22:14:43.839684 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9903 22:14:43.846612 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9904 22:14:43.849659 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9905 22:14:43.852671 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9906 22:14:43.859330 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9907 22:14:43.862515 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9908 22:14:43.869442 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9909 22:14:43.872714 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9910 22:14:43.875896 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9911 22:14:43.882448 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9912 22:14:43.885588 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9913 22:14:43.892590 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9914 22:14:43.895502 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9915 22:14:43.899357 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9916 22:14:43.905833 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9917 22:14:43.908844 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9918 22:14:43.915485 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9919 22:14:43.918725 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9920 22:14:43.925793 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9921 22:14:43.928916 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9922 22:14:43.931784 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9923 22:14:43.938650 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9924 22:14:43.941648 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9925 22:14:43.948561 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9926 22:14:43.952020 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9927 22:14:43.958655 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9928 22:14:43.961889 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9929 22:14:43.964900 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9930 22:14:43.971344 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9931 22:14:43.975061 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9932 22:14:43.981380 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9933 22:14:43.984551 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9934 22:14:43.987705 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9935 22:14:43.994804 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9936 22:14:43.997619 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9937 22:14:44.004546 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9938 22:14:44.007735 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9939 22:14:44.014735 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9940 22:14:44.017934 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9941 22:14:44.024197 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9942 22:14:44.027741 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9943 22:14:44.030937 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9944 22:14:44.037712 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9945 22:14:44.041095 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9946 22:14:44.047187 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9947 22:14:44.050369 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9948 22:14:44.057184 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9949 22:14:44.060359 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9950 22:14:44.067065 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9951 22:14:44.070453 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9952 22:14:44.073944 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9953 22:14:44.080201 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9954 22:14:44.083700 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9955 22:14:44.089912 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9956 22:14:44.093304 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9957 22:14:44.100051 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9958 22:14:44.103345 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9959 22:14:44.109949 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9960 22:14:44.112987 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9961 22:14:44.116856 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9962 22:14:44.123401 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9963 22:14:44.126205 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9964 22:14:44.132748 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9965 22:14:44.136663 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9966 22:14:44.142641 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9967 22:14:44.146076 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9968 22:14:44.152649 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9969 22:14:44.156309 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9970 22:14:44.159412 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9971 22:14:44.165615 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9972 22:14:44.169218 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9973 22:14:44.175690 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9974 22:14:44.179031 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9975 22:14:44.185494 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9976 22:14:44.188560 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9977 22:14:44.192032 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9978 22:14:44.198679 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9979 22:14:44.201931 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9980 22:14:44.208808 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9981 22:14:44.211977 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9982 22:14:44.218868 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9983 22:14:44.222050 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9984 22:14:44.228469 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9985 22:14:44.232063 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9986 22:14:44.234809 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9987 22:14:44.241657 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9988 22:14:44.245163 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9989 22:14:44.251369 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9990 22:14:44.254749 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9991 22:14:44.261292 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9992 22:14:44.265155 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9993 22:14:44.271277 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9994 22:14:44.275037 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9995 22:14:44.281195 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9996 22:14:44.284850 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9997 22:14:44.291158 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9998 22:14:44.294418 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9999 22:14:44.301191 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
10000 22:14:44.304576 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
10001 22:14:44.310782 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
10002 22:14:44.314355 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
10003 22:14:44.321115 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
10004 22:14:44.324420 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
10005 22:14:44.327465 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
10006 22:14:44.334730 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
10007 22:14:44.341364 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
10008 22:14:44.344392 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
10009 22:14:44.350699 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
10010 22:14:44.353913 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
10011 22:14:44.360752 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
10012 22:14:44.363833 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
10013 22:14:44.370310 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
10014 22:14:44.373559 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
10015 22:14:44.380377 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
10016 22:14:44.383367 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
10017 22:14:44.390083 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
10018 22:14:44.393583 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
10019 22:14:44.396767 INFO: [APUAPC] vio 0
10020 22:14:44.400149 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
10021 22:14:44.406461 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
10022 22:14:44.409716 INFO: [APUAPC] D0_APC_0: 0x400510
10023 22:14:44.409823 INFO: [APUAPC] D0_APC_1: 0x0
10024 22:14:44.413290 INFO: [APUAPC] D0_APC_2: 0x1540
10025 22:14:44.416476 INFO: [APUAPC] D0_APC_3: 0x0
10026 22:14:44.419817 INFO: [APUAPC] D1_APC_0: 0xffffffff
10027 22:14:44.423462 INFO: [APUAPC] D1_APC_1: 0xffffffff
10028 22:14:44.426514 INFO: [APUAPC] D1_APC_2: 0x3fffff
10029 22:14:44.429983 INFO: [APUAPC] D1_APC_3: 0x0
10030 22:14:44.433164 INFO: [APUAPC] D2_APC_0: 0xffffffff
10031 22:14:44.436256 INFO: [APUAPC] D2_APC_1: 0xffffffff
10032 22:14:44.439833 INFO: [APUAPC] D2_APC_2: 0x3fffff
10033 22:14:44.443071 INFO: [APUAPC] D2_APC_3: 0x0
10034 22:14:44.446695 INFO: [APUAPC] D3_APC_0: 0xffffffff
10035 22:14:44.449842 INFO: [APUAPC] D3_APC_1: 0xffffffff
10036 22:14:44.453090 INFO: [APUAPC] D3_APC_2: 0x3fffff
10037 22:14:44.456171 INFO: [APUAPC] D3_APC_3: 0x0
10038 22:14:44.459230 INFO: [APUAPC] D4_APC_0: 0xffffffff
10039 22:14:44.462750 INFO: [APUAPC] D4_APC_1: 0xffffffff
10040 22:14:44.466188 INFO: [APUAPC] D4_APC_2: 0x3fffff
10041 22:14:44.469816 INFO: [APUAPC] D4_APC_3: 0x0
10042 22:14:44.473092 INFO: [APUAPC] D5_APC_0: 0xffffffff
10043 22:14:44.475914 INFO: [APUAPC] D5_APC_1: 0xffffffff
10044 22:14:44.479394 INFO: [APUAPC] D5_APC_2: 0x3fffff
10045 22:14:44.482684 INFO: [APUAPC] D5_APC_3: 0x0
10046 22:14:44.486137 INFO: [APUAPC] D6_APC_0: 0xffffffff
10047 22:14:44.489213 INFO: [APUAPC] D6_APC_1: 0xffffffff
10048 22:14:44.492809 INFO: [APUAPC] D6_APC_2: 0x3fffff
10049 22:14:44.495898 INFO: [APUAPC] D6_APC_3: 0x0
10050 22:14:44.499338 INFO: [APUAPC] D7_APC_0: 0xffffffff
10051 22:14:44.502703 INFO: [APUAPC] D7_APC_1: 0xffffffff
10052 22:14:44.505595 INFO: [APUAPC] D7_APC_2: 0x3fffff
10053 22:14:44.509257 INFO: [APUAPC] D7_APC_3: 0x0
10054 22:14:44.512555 INFO: [APUAPC] D8_APC_0: 0xffffffff
10055 22:14:44.515867 INFO: [APUAPC] D8_APC_1: 0xffffffff
10056 22:14:44.519811 INFO: [APUAPC] D8_APC_2: 0x3fffff
10057 22:14:44.522565 INFO: [APUAPC] D8_APC_3: 0x0
10058 22:14:44.525940 INFO: [APUAPC] D9_APC_0: 0xffffffff
10059 22:14:44.529148 INFO: [APUAPC] D9_APC_1: 0xffffffff
10060 22:14:44.533003 INFO: [APUAPC] D9_APC_2: 0x3fffff
10061 22:14:44.535852 INFO: [APUAPC] D9_APC_3: 0x0
10062 22:14:44.539109 INFO: [APUAPC] D10_APC_0: 0xffffffff
10063 22:14:44.542747 INFO: [APUAPC] D10_APC_1: 0xffffffff
10064 22:14:44.546234 INFO: [APUAPC] D10_APC_2: 0x3fffff
10065 22:14:44.549167 INFO: [APUAPC] D10_APC_3: 0x0
10066 22:14:44.552117 INFO: [APUAPC] D11_APC_0: 0xffffffff
10067 22:14:44.555771 INFO: [APUAPC] D11_APC_1: 0xffffffff
10068 22:14:44.559350 INFO: [APUAPC] D11_APC_2: 0x3fffff
10069 22:14:44.562106 INFO: [APUAPC] D11_APC_3: 0x0
10070 22:14:44.565566 INFO: [APUAPC] D12_APC_0: 0xffffffff
10071 22:14:44.568693 INFO: [APUAPC] D12_APC_1: 0xffffffff
10072 22:14:44.572412 INFO: [APUAPC] D12_APC_2: 0x3fffff
10073 22:14:44.575932 INFO: [APUAPC] D12_APC_3: 0x0
10074 22:14:44.579167 INFO: [APUAPC] D13_APC_0: 0xffffffff
10075 22:14:44.582283 INFO: [APUAPC] D13_APC_1: 0xffffffff
10076 22:14:44.585458 INFO: [APUAPC] D13_APC_2: 0x3fffff
10077 22:14:44.588728 INFO: [APUAPC] D13_APC_3: 0x0
10078 22:14:44.592000 INFO: [APUAPC] D14_APC_0: 0xffffffff
10079 22:14:44.595620 INFO: [APUAPC] D14_APC_1: 0xffffffff
10080 22:14:44.598680 INFO: [APUAPC] D14_APC_2: 0x3fffff
10081 22:14:44.601917 INFO: [APUAPC] D14_APC_3: 0x0
10082 22:14:44.605422 INFO: [APUAPC] D15_APC_0: 0xffffffff
10083 22:14:44.608418 INFO: [APUAPC] D15_APC_1: 0xffffffff
10084 22:14:44.611970 INFO: [APUAPC] D15_APC_2: 0x3fffff
10085 22:14:44.614965 INFO: [APUAPC] D15_APC_3: 0x0
10086 22:14:44.618588 INFO: [APUAPC] APC_CON: 0x4
10087 22:14:44.621992 INFO: [NOCDAPC] D0_APC_0: 0x0
10088 22:14:44.624979 INFO: [NOCDAPC] D0_APC_1: 0x0
10089 22:14:44.625440 INFO: [NOCDAPC] D1_APC_0: 0x0
10090 22:14:44.628250 INFO: [NOCDAPC] D1_APC_1: 0xfff
10091 22:14:44.632057 INFO: [NOCDAPC] D2_APC_0: 0x0
10092 22:14:44.635109 INFO: [NOCDAPC] D2_APC_1: 0xfff
10093 22:14:44.638604 INFO: [NOCDAPC] D3_APC_0: 0x0
10094 22:14:44.641526 INFO: [NOCDAPC] D3_APC_1: 0xfff
10095 22:14:44.644825 INFO: [NOCDAPC] D4_APC_0: 0x0
10096 22:14:44.647896 INFO: [NOCDAPC] D4_APC_1: 0xfff
10097 22:14:44.651372 INFO: [NOCDAPC] D5_APC_0: 0x0
10098 22:14:44.654810 INFO: [NOCDAPC] D5_APC_1: 0xfff
10099 22:14:44.657788 INFO: [NOCDAPC] D6_APC_0: 0x0
10100 22:14:44.661121 INFO: [NOCDAPC] D6_APC_1: 0xfff
10101 22:14:44.661682 INFO: [NOCDAPC] D7_APC_0: 0x0
10102 22:14:44.664338 INFO: [NOCDAPC] D7_APC_1: 0xfff
10103 22:14:44.667810 INFO: [NOCDAPC] D8_APC_0: 0x0
10104 22:14:44.671015 INFO: [NOCDAPC] D8_APC_1: 0xfff
10105 22:14:44.674096 INFO: [NOCDAPC] D9_APC_0: 0x0
10106 22:14:44.677732 INFO: [NOCDAPC] D9_APC_1: 0xfff
10107 22:14:44.681280 INFO: [NOCDAPC] D10_APC_0: 0x0
10108 22:14:44.684202 INFO: [NOCDAPC] D10_APC_1: 0xfff
10109 22:14:44.687753 INFO: [NOCDAPC] D11_APC_0: 0x0
10110 22:14:44.690729 INFO: [NOCDAPC] D11_APC_1: 0xfff
10111 22:14:44.694236 INFO: [NOCDAPC] D12_APC_0: 0x0
10112 22:14:44.697276 INFO: [NOCDAPC] D12_APC_1: 0xfff
10113 22:14:44.701325 INFO: [NOCDAPC] D13_APC_0: 0x0
10114 22:14:44.704272 INFO: [NOCDAPC] D13_APC_1: 0xfff
10115 22:14:44.704857 INFO: [NOCDAPC] D14_APC_0: 0x0
10116 22:14:44.707773 INFO: [NOCDAPC] D14_APC_1: 0xfff
10117 22:14:44.710438 INFO: [NOCDAPC] D15_APC_0: 0x0
10118 22:14:44.714126 INFO: [NOCDAPC] D15_APC_1: 0xfff
10119 22:14:44.717281 INFO: [NOCDAPC] APC_CON: 0x4
10120 22:14:44.720948 INFO: [APUAPC] set_apusys_apc done
10121 22:14:44.723842 INFO: [DEVAPC] devapc_init done
10122 22:14:44.727170 INFO: GICv3 without legacy support detected.
10123 22:14:44.734179 INFO: ARM GICv3 driver initialized in EL3
10124 22:14:44.737772 INFO: Maximum SPI INTID supported: 639
10125 22:14:44.740340 INFO: BL31: Initializing runtime services
10126 22:14:44.747399 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10127 22:14:44.747927 INFO: SPM: enable CPC mode
10128 22:14:44.753846 INFO: mcdi ready for mcusys-off-idle and system suspend
10129 22:14:44.760080 INFO: BL31: Preparing for EL3 exit to normal world
10130 22:14:44.763944 INFO: Entry point address = 0x80000000
10131 22:14:44.764625 INFO: SPSR = 0x8
10132 22:14:44.769998
10133 22:14:44.770453
10134 22:14:44.770813
10135 22:14:44.773314 Starting depthcharge on Spherion...
10136 22:14:44.773771
10137 22:14:44.774132 Wipe memory regions:
10138 22:14:44.774471
10139 22:14:44.777031 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10140 22:14:44.777566 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10141 22:14:44.778030 Setting prompt string to ['asurada:']
10142 22:14:44.779518 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10143 22:14:44.780247 [0x00000040000000, 0x00000054600000)
10144 22:14:44.898805
10145 22:14:44.899351 [0x00000054660000, 0x00000080000000)
10146 22:14:45.159524
10147 22:14:45.160143 [0x000000821a7280, 0x000000ffe64000)
10148 22:14:45.904205
10149 22:14:45.904806 [0x00000100000000, 0x00000240000000)
10150 22:14:47.794685
10151 22:14:47.797413 Initializing XHCI USB controller at 0x11200000.
10152 22:14:48.779040
10153 22:14:48.779604 R8152: Initializing
10154 22:14:48.779975
10155 22:14:48.782131 Version 9 (ocp_data = 6010)
10156 22:14:48.782800
10157 22:14:48.785516 R8152: Done initializing
10158 22:14:48.785978
10159 22:14:48.786343 Adding net device
10160 22:14:49.307350
10161 22:14:49.310690 [firmware-asurada-13885.B-collabora] Dec 14 2021 15:21:43
10162 22:14:49.310797
10163 22:14:49.310873
10164 22:14:49.310944
10165 22:14:49.311236 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10167 22:14:49.411662 asurada: tftpboot 192.168.201.1 10597297/tftp-deploy-7relhzi_/kernel/image.itb 10597297/tftp-deploy-7relhzi_/kernel/cmdline
10168 22:14:49.411789 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10169 22:14:49.411874 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:20)
10170 22:14:49.415937 tftpboot 192.168.201.1 10597297/tftp-deploy-7relhzi_/kernel/image.itp-deploy-7relhzi_/kernel/cmdline
10171 22:14:49.416019
10172 22:14:49.416084 Waiting for link
10173 22:14:49.619378
10174 22:14:49.620183 done.
10175 22:14:49.620992
10176 22:14:49.621672 MAC: f4:f5:e8:50:de:0a
10177 22:14:49.622044
10178 22:14:49.622695 Sending DHCP discover... done.
10179 22:14:49.623059
10180 22:14:49.625181 Waiting for reply... done.
10181 22:14:49.625725
10182 22:14:49.628585 Sending DHCP request... done.
10183 22:14:49.629051
10184 22:14:49.629419 Waiting for reply... done.
10185 22:14:49.629766
10186 22:14:49.631910 My ip is 192.168.201.14
10187 22:14:49.632377
10188 22:14:49.635911 The DHCP server ip is 192.168.201.1
10189 22:14:49.636479
10190 22:14:49.638736 TFTP server IP predefined by user: 192.168.201.1
10191 22:14:49.639207
10192 22:14:49.644902 Bootfile predefined by user: 10597297/tftp-deploy-7relhzi_/kernel/image.itb
10193 22:14:49.645462
10194 22:14:49.648468 Sending tftp read request... done.
10195 22:14:49.649023
10196 22:14:49.657081 Waiting for the transfer...
10197 22:14:49.657644
10198 22:14:49.957323 00000000 ################################################################
10199 22:14:49.957455
10200 22:14:50.198283 00080000 ################################################################
10201 22:14:50.198417
10202 22:14:50.432633 00100000 ################################################################
10203 22:14:50.432800
10204 22:14:50.679276 00180000 ################################################################
10205 22:14:50.679408
10206 22:14:50.933755 00200000 ################################################################
10207 22:14:50.933887
10208 22:14:51.163447 00280000 ################################################################
10209 22:14:51.163585
10210 22:14:51.424525 00300000 ################################################################
10211 22:14:51.424680
10212 22:14:51.668317 00380000 ################################################################
10213 22:14:51.668487
10214 22:14:51.909289 00400000 ################################################################
10215 22:14:51.909418
10216 22:14:52.146018 00480000 ################################################################
10217 22:14:52.146148
10218 22:14:52.374566 00500000 ################################################################
10219 22:14:52.374705
10220 22:14:52.604929 00580000 ################################################################
10221 22:14:52.605066
10222 22:14:52.851139 00600000 ################################################################
10223 22:14:52.851271
10224 22:14:53.097033 00680000 ################################################################
10225 22:14:53.097173
10226 22:14:53.346318 00700000 ################################################################
10227 22:14:53.346455
10228 22:14:53.583894 00780000 ################################################################
10229 22:14:53.584030
10230 22:14:53.823109 00800000 ################################################################
10231 22:14:53.823246
10232 22:14:54.061322 00880000 ################################################################
10233 22:14:54.061457
10234 22:14:54.297333 00900000 ################################################################
10235 22:14:54.297466
10236 22:14:54.523263 00980000 ################################################################
10237 22:14:54.523396
10238 22:14:54.765616 00a00000 ################################################################
10239 22:14:54.765750
10240 22:14:54.991329 00a80000 ################################################################
10241 22:14:54.991463
10242 22:14:55.217152 00b00000 ################################################################
10243 22:14:55.217282
10244 22:14:55.455285 00b80000 ################################################################
10245 22:14:55.455422
10246 22:14:55.692252 00c00000 ################################################################
10247 22:14:55.692387
10248 22:14:55.921580 00c80000 ################################################################
10249 22:14:55.921717
10250 22:14:56.155030 00d00000 ################################################################
10251 22:14:56.155170
10252 22:14:56.388951 00d80000 ################################################################
10253 22:14:56.389086
10254 22:14:56.617053 00e00000 ################################################################
10255 22:14:56.617187
10256 22:14:56.877687 00e80000 ################################################################
10257 22:14:56.877827
10258 22:14:57.122337 00f00000 ################################################################
10259 22:14:57.122497
10260 22:14:57.358171 00f80000 ################################################################
10261 22:14:57.358340
10262 22:14:57.596065 01000000 ################################################################
10263 22:14:57.596232
10264 22:14:57.821779 01080000 ################################################################
10265 22:14:57.821915
10266 22:14:58.048121 01100000 ################################################################
10267 22:14:58.048282
10268 22:14:58.278762 01180000 ################################################################
10269 22:14:58.278922
10270 22:14:58.506611 01200000 ################################################################
10271 22:14:58.506774
10272 22:14:58.736119 01280000 ################################################################
10273 22:14:58.736255
10274 22:14:58.974633 01300000 ################################################################
10275 22:14:58.974768
10276 22:14:59.204344 01380000 ################################################################
10277 22:14:59.204510
10278 22:14:59.433308 01400000 ################################################################
10279 22:14:59.433437
10280 22:14:59.659322 01480000 ################################################################
10281 22:14:59.659461
10282 22:14:59.888100 01500000 ################################################################
10283 22:14:59.888233
10284 22:15:00.116097 01580000 ################################################################
10285 22:15:00.116232
10286 22:15:00.346323 01600000 ################################################################
10287 22:15:00.346462
10288 22:15:00.590516 01680000 ################################################################
10289 22:15:00.590645
10290 22:15:00.820715 01700000 ################################################################
10291 22:15:00.820850
10292 22:15:01.061328 01780000 ################################################################
10293 22:15:01.061464
10294 22:15:01.293972 01800000 ################################################################
10295 22:15:01.294107
10296 22:15:01.519663 01880000 ################################################################
10297 22:15:01.519810
10298 22:15:01.764346 01900000 ################################################################
10299 22:15:01.764477
10300 22:15:01.996166 01980000 ################################################################
10301 22:15:01.996327
10302 22:15:02.218861 01a00000 ############################################################### done.
10303 22:15:02.218997
10304 22:15:02.222155 The bootfile was 27776778 bytes long.
10305 22:15:02.222240
10306 22:15:02.225292 Sending tftp read request... done.
10307 22:15:02.225387
10308 22:15:02.228769 Waiting for the transfer...
10309 22:15:02.228864
10310 22:15:02.232014 00000000 # done.
10311 22:15:02.232186
10312 22:15:02.238927 Command line loaded dynamically from TFTP file: 10597297/tftp-deploy-7relhzi_/kernel/cmdline
10313 22:15:02.239110
10314 22:15:02.259235 The command line is: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/10597297/extract-nfsrootfs-iuuo3m7a,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10315 22:15:02.259497
10316 22:15:02.259649 Loading FIT.
10317 22:15:02.259786
10318 22:15:02.261840 Image ramdisk-1 has 17645513 bytes.
10319 22:15:02.262085
10320 22:15:02.265390 Image fdt-1 has 46924 bytes.
10321 22:15:02.265679
10322 22:15:02.268904 Image kernel-1 has 10082307 bytes.
10323 22:15:02.269153
10324 22:15:02.279164 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10325 22:15:02.279662
10326 22:15:02.295510 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10327 22:15:02.296100
10328 22:15:02.301947 Choosing best match conf-1 for compat google,spherion-rev2.
10329 22:15:02.302529
10330 22:15:02.309203 Connected to device vid:did:rid of 1ae0:0028:00
10331 22:15:02.316334
10332 22:15:02.319997 tpm_get_response: command 0x17b, return code 0x0
10333 22:15:02.320469
10334 22:15:02.322952 ec_init: CrosEC protocol v3 supported (256, 248)
10335 22:15:02.327165
10336 22:15:02.331114 tpm_cleanup: add release locality here.
10337 22:15:02.331712
10338 22:15:02.332091 Shutting down all USB controllers.
10339 22:15:02.333750
10340 22:15:02.334311 Removing current net device
10341 22:15:02.334691
10342 22:15:02.341378 Exiting depthcharge with code 4 at timestamp: 47033911
10343 22:15:02.341940
10344 22:15:02.343744 LZMA decompressing kernel-1 to 0x821a6718
10345 22:15:02.344215
10346 22:15:02.347469 LZMA decompressing kernel-1 to 0x40000000
10347 22:15:03.614428
10348 22:15:03.614958 jumping to kernel
10349 22:15:03.616307 end: 2.2.4 bootloader-commands (duration 00:00:19) [common]
10350 22:15:03.616853 start: 2.2.5 auto-login-action (timeout 00:04:06) [common]
10351 22:15:03.617269 Setting prompt string to ['Linux version [0-9]']
10352 22:15:03.617674 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10353 22:15:03.618088 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10354 22:15:03.697240
10355 22:15:03.700413 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10356 22:15:03.704177 start: 2.2.5.1 login-action (timeout 00:04:06) [common]
10357 22:15:03.704664 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10358 22:15:03.705084 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10359 22:15:03.705452 Using line separator: #'\n'#
10360 22:15:03.705762 No login prompt set.
10361 22:15:03.706077 Parsing kernel messages
10362 22:15:03.706361 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10363 22:15:03.706884 [login-action] Waiting for messages, (timeout 00:04:06)
10364 22:15:03.723175 [ 0.000000] Linux version 6.1.31 (KernelCI@build-j1612341-arm64-gcc-10-defconfig-arm64-chromebook-n674v) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Mon Jun 5 22:04:07 UTC 2023
10365 22:15:03.726913 [ 0.000000] random: crng init done
10366 22:15:03.732774 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10367 22:15:03.736470 [ 0.000000] efi: UEFI not found.
10368 22:15:03.743043 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10369 22:15:03.749266 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10370 22:15:03.759630 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10371 22:15:03.769351 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10372 22:15:03.775527 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10373 22:15:03.782552 [ 0.000000] printk: bootconsole [mtk8250] enabled
10374 22:15:03.789321 [ 0.000000] NUMA: No NUMA configuration found
10375 22:15:03.795474 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10376 22:15:03.798722 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcda00-0x23efcffff]
10377 22:15:03.802056 [ 0.000000] Zone ranges:
10378 22:15:03.809119 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10379 22:15:03.811707 [ 0.000000] DMA32 empty
10380 22:15:03.818243 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10381 22:15:03.821472 [ 0.000000] Movable zone start for each node
10382 22:15:03.825131 [ 0.000000] Early memory node ranges
10383 22:15:03.831883 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10384 22:15:03.838239 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10385 22:15:03.844523 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10386 22:15:03.851178 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10387 22:15:03.858339 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10388 22:15:03.864894 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10389 22:15:03.920706 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10390 22:15:03.927308 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10391 22:15:03.934332 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10392 22:15:03.937402 [ 0.000000] psci: probing for conduit method from DT.
10393 22:15:03.943657 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10394 22:15:03.947334 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10395 22:15:03.953618 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10396 22:15:03.957368 [ 0.000000] psci: SMC Calling Convention v1.2
10397 22:15:03.963703 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10398 22:15:03.967017 [ 0.000000] Detected VIPT I-cache on CPU0
10399 22:15:03.973548 [ 0.000000] CPU features: detected: GIC system register CPU interface
10400 22:15:03.980508 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10401 22:15:03.986894 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10402 22:15:03.993890 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10403 22:15:04.002946 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10404 22:15:04.009805 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10405 22:15:04.013002 [ 0.000000] alternatives: applying boot alternatives
10406 22:15:04.019709 [ 0.000000] Fallback order for Node 0: 0
10407 22:15:04.026429 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10408 22:15:04.029732 [ 0.000000] Policy zone: Normal
10409 22:15:04.049813 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/10597297/extract-nfsrootfs-iuuo3m7a,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10410 22:15:04.059097 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10411 22:15:04.071330 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10412 22:15:04.080927 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10413 22:15:04.087323 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10414 22:15:04.090990 <6>[ 0.000000] software IO TLB: area num 8.
10415 22:15:04.147959 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10416 22:15:04.296918 <6>[ 0.000000] Memory: 7955712K/8385536K available (17984K kernel code, 4098K rwdata, 14068K rodata, 8384K init, 615K bss, 397056K reserved, 32768K cma-reserved)
10417 22:15:04.303787 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10418 22:15:04.310424 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10419 22:15:04.313517 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10420 22:15:04.320734 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10421 22:15:04.327163 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10422 22:15:04.330357 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10423 22:15:04.339940 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10424 22:15:04.346522 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10425 22:15:04.353157 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10426 22:15:04.360020 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10427 22:15:04.363272 <6>[ 0.000000] GICv3: 608 SPIs implemented
10428 22:15:04.366673 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10429 22:15:04.373081 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10430 22:15:04.376603 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10431 22:15:04.383026 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10432 22:15:04.396207 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10433 22:15:04.409589 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10434 22:15:04.416682 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10435 22:15:04.423962 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10436 22:15:04.437175 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10437 22:15:04.444263 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10438 22:15:04.450354 <6>[ 0.009176] Console: colour dummy device 80x25
10439 22:15:04.460254 <6>[ 0.013904] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10440 22:15:04.466854 <6>[ 0.024411] pid_max: default: 32768 minimum: 301
10441 22:15:04.470426 <6>[ 0.029284] LSM: Security Framework initializing
10442 22:15:04.476296 <6>[ 0.034223] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10443 22:15:04.486158 <6>[ 0.042085] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10444 22:15:04.495902 <6>[ 0.051464] cblist_init_generic: Setting adjustable number of callback queues.
10445 22:15:04.502765 <6>[ 0.058918] cblist_init_generic: Setting shift to 3 and lim to 1.
10446 22:15:04.506278 <6>[ 0.065257] cblist_init_generic: Setting shift to 3 and lim to 1.
10447 22:15:04.512276 <6>[ 0.071665] rcu: Hierarchical SRCU implementation.
10448 22:15:04.519014 <6>[ 0.076680] rcu: Max phase no-delay instances is 1000.
10449 22:15:04.525689 <6>[ 0.083701] EFI services will not be available.
10450 22:15:04.528490 <6>[ 0.088671] smp: Bringing up secondary CPUs ...
10451 22:15:04.536716 <6>[ 0.093728] Detected VIPT I-cache on CPU1
10452 22:15:04.543694 <6>[ 0.093799] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10453 22:15:04.549632 <6>[ 0.093830] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10454 22:15:04.553332 <6>[ 0.094167] Detected VIPT I-cache on CPU2
10455 22:15:04.562840 <6>[ 0.094222] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10456 22:15:04.570005 <6>[ 0.094240] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10457 22:15:04.572980 <6>[ 0.094498] Detected VIPT I-cache on CPU3
10458 22:15:04.579942 <6>[ 0.094544] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10459 22:15:04.586112 <6>[ 0.094558] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10460 22:15:04.593121 <6>[ 0.094864] CPU features: detected: Spectre-v4
10461 22:15:04.597436 <6>[ 0.094870] CPU features: detected: Spectre-BHB
10462 22:15:04.599496 <6>[ 0.094876] Detected PIPT I-cache on CPU4
10463 22:15:04.606243 <6>[ 0.094932] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10464 22:15:04.616311 <6>[ 0.094949] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10465 22:15:04.619358 <6>[ 0.095248] Detected PIPT I-cache on CPU5
10466 22:15:04.626068 <6>[ 0.095310] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10467 22:15:04.632406 <6>[ 0.095326] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10468 22:15:04.635703 <6>[ 0.095609] Detected PIPT I-cache on CPU6
10469 22:15:04.645279 <6>[ 0.095674] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10470 22:15:04.651762 <6>[ 0.095690] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10471 22:15:04.655486 <6>[ 0.095991] Detected PIPT I-cache on CPU7
10472 22:15:04.661907 <6>[ 0.096055] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10473 22:15:04.668498 <6>[ 0.096071] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10474 22:15:04.674751 <6>[ 0.096118] smp: Brought up 1 node, 8 CPUs
10475 22:15:04.678242 <6>[ 0.237377] SMP: Total of 8 processors activated.
10476 22:15:04.684371 <6>[ 0.242297] CPU features: detected: 32-bit EL0 Support
10477 22:15:04.691399 <6>[ 0.247694] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10478 22:15:04.697772 <6>[ 0.256493] CPU features: detected: Common not Private translations
10479 22:15:04.705418 <6>[ 0.262969] CPU features: detected: CRC32 instructions
10480 22:15:04.710929 <6>[ 0.268353] CPU features: detected: RCpc load-acquire (LDAPR)
10481 22:15:04.717834 <6>[ 0.274350] CPU features: detected: LSE atomic instructions
10482 22:15:04.721086 <6>[ 0.280132] CPU features: detected: Privileged Access Never
10483 22:15:04.727986 <6>[ 0.285911] CPU features: detected: RAS Extension Support
10484 22:15:04.734113 <6>[ 0.291520] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10485 22:15:04.737425 <6>[ 0.298785] CPU: All CPU(s) started at EL2
10486 22:15:04.744269 <6>[ 0.303101] alternatives: applying system-wide alternatives
10487 22:15:04.755136 <6>[ 0.313794] devtmpfs: initialized
10488 22:15:04.769968 <6>[ 0.322593] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10489 22:15:04.777157 <6>[ 0.332554] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10490 22:15:04.782971 <6>[ 0.340734] pinctrl core: initialized pinctrl subsystem
10491 22:15:04.786771 <6>[ 0.347366] DMI not present or invalid.
10492 22:15:04.793430 <6>[ 0.351714] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10493 22:15:04.802896 <6>[ 0.358583] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10494 22:15:04.809647 <6>[ 0.366166] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10495 22:15:04.820015 <6>[ 0.374389] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10496 22:15:04.822974 <6>[ 0.382633] audit: initializing netlink subsys (disabled)
10497 22:15:04.832504 <5>[ 0.388325] audit: type=2000 audit(0.276:1): state=initialized audit_enabled=0 res=1
10498 22:15:04.839345 <6>[ 0.389017] thermal_sys: Registered thermal governor 'step_wise'
10499 22:15:04.846040 <6>[ 0.396295] thermal_sys: Registered thermal governor 'power_allocator'
10500 22:15:04.848878 <6>[ 0.402548] cpuidle: using governor menu
10501 22:15:04.855656 <6>[ 0.413513] NET: Registered PF_QIPCRTR protocol family
10502 22:15:04.861975 <6>[ 0.418974] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10503 22:15:04.869036 <6>[ 0.426077] ASID allocator initialised with 32768 entries
10504 22:15:04.871977 <6>[ 0.432627] Serial: AMBA PL011 UART driver
10505 22:15:04.882249 <4>[ 0.441230] Trying to register duplicate clock ID: 134
10506 22:15:04.936291 <6>[ 0.498506] KASLR enabled
10507 22:15:04.950611 <6>[ 0.506233] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10508 22:15:04.957147 <6>[ 0.513243] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10509 22:15:04.963461 <6>[ 0.519733] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10510 22:15:04.970433 <6>[ 0.526740] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10511 22:15:04.976993 <6>[ 0.533223] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10512 22:15:04.983529 <6>[ 0.540226] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10513 22:15:04.990521 <6>[ 0.546710] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10514 22:15:04.996654 <6>[ 0.553714] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10515 22:15:04.999876 <6>[ 0.561218] ACPI: Interpreter disabled.
10516 22:15:05.008941 <6>[ 0.567601] iommu: Default domain type: Translated
10517 22:15:05.014930 <6>[ 0.572709] iommu: DMA domain TLB invalidation policy: strict mode
10518 22:15:05.018913 <5>[ 0.579362] SCSI subsystem initialized
10519 22:15:05.025033 <6>[ 0.583529] usbcore: registered new interface driver usbfs
10520 22:15:05.031338 <6>[ 0.589261] usbcore: registered new interface driver hub
10521 22:15:05.034702 <6>[ 0.594810] usbcore: registered new device driver usb
10522 22:15:05.041616 <6>[ 0.600889] pps_core: LinuxPPS API ver. 1 registered
10523 22:15:05.051976 <6>[ 0.606081] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10524 22:15:05.055039 <6>[ 0.615428] PTP clock support registered
10525 22:15:05.057853 <6>[ 0.619671] EDAC MC: Ver: 3.0.0
10526 22:15:05.066055 <6>[ 0.624811] FPGA manager framework
10527 22:15:05.072290 <6>[ 0.628492] Advanced Linux Sound Architecture Driver Initialized.
10528 22:15:05.075320 <6>[ 0.635255] vgaarb: loaded
10529 22:15:05.082614 <6>[ 0.638428] clocksource: Switched to clocksource arch_sys_counter
10530 22:15:05.085124 <5>[ 0.644866] VFS: Disk quotas dquot_6.6.0
10531 22:15:05.092147 <6>[ 0.649050] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10532 22:15:05.095214 <6>[ 0.656238] pnp: PnP ACPI: disabled
10533 22:15:05.103905 <6>[ 0.662954] NET: Registered PF_INET protocol family
10534 22:15:05.113973 <6>[ 0.668550] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10535 22:15:05.124901 <6>[ 0.680900] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10536 22:15:05.135562 <6>[ 0.689717] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10537 22:15:05.141433 <6>[ 0.697688] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10538 22:15:05.151291 <6>[ 0.706388] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10539 22:15:05.157895 <6>[ 0.716129] TCP: Hash tables configured (established 65536 bind 65536)
10540 22:15:05.164512 <6>[ 0.722988] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10541 22:15:05.174511 <6>[ 0.730189] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10542 22:15:05.181010 <6>[ 0.737883] NET: Registered PF_UNIX/PF_LOCAL protocol family
10543 22:15:05.188102 <6>[ 0.744042] RPC: Registered named UNIX socket transport module.
10544 22:15:05.191129 <6>[ 0.750199] RPC: Registered udp transport module.
10545 22:15:05.197616 <6>[ 0.755130] RPC: Registered tcp transport module.
10546 22:15:05.204030 <6>[ 0.760062] RPC: Registered tcp NFSv4.1 backchannel transport module.
10547 22:15:05.207362 <6>[ 0.766728] PCI: CLS 0 bytes, default 64
10548 22:15:05.210838 <6>[ 0.770983] Unpacking initramfs...
10549 22:15:05.227252 <6>[ 0.783029] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10550 22:15:05.237460 <6>[ 0.791689] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10551 22:15:05.240471 <6>[ 0.800528] kvm [1]: IPA Size Limit: 40 bits
10552 22:15:05.247161 <6>[ 0.805055] kvm [1]: GICv3: no GICV resource entry
10553 22:15:05.250675 <6>[ 0.810076] kvm [1]: disabling GICv2 emulation
10554 22:15:05.256617 <6>[ 0.814765] kvm [1]: GIC system register CPU interface enabled
10555 22:15:05.260031 <6>[ 0.820923] kvm [1]: vgic interrupt IRQ18
10556 22:15:05.266732 <6>[ 0.825280] kvm [1]: VHE mode initialized successfully
10557 22:15:05.274360 <5>[ 0.831700] Initialise system trusted keyrings
10558 22:15:05.279734 <6>[ 0.836515] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10559 22:15:05.287743 <6>[ 0.846536] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10560 22:15:05.294137 <5>[ 0.852937] NFS: Registering the id_resolver key type
10561 22:15:05.297524 <5>[ 0.858234] Key type id_resolver registered
10562 22:15:05.304141 <5>[ 0.862650] Key type id_legacy registered
10563 22:15:05.310312 <6>[ 0.866927] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10564 22:15:05.317052 <6>[ 0.873850] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10565 22:15:05.323433 <6>[ 0.881576] 9p: Installing v9fs 9p2000 file system support
10566 22:15:05.360676 <5>[ 0.920039] Key type asymmetric registered
10567 22:15:05.364382 <5>[ 0.924370] Asymmetric key parser 'x509' registered
10568 22:15:05.374025 <6>[ 0.929528] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10569 22:15:05.377100 <6>[ 0.937142] io scheduler mq-deadline registered
10570 22:15:05.380612 <6>[ 0.941904] io scheduler kyber registered
10571 22:15:05.400240 <6>[ 0.958842] EINJ: ACPI disabled.
10572 22:15:05.432707 <4>[ 0.984225] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10573 22:15:05.441416 <4>[ 0.994854] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10574 22:15:05.456450 <6>[ 1.015413] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10575 22:15:05.464098 <6>[ 1.023290] printk: console [ttyS0] disabled
10576 22:15:05.492213 <6>[ 1.047939] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10577 22:15:05.499170 <6>[ 1.057416] printk: console [ttyS0] enabled
10578 22:15:05.502095 <6>[ 1.057416] printk: console [ttyS0] enabled
10579 22:15:05.508756 <6>[ 1.066316] printk: bootconsole [mtk8250] disabled
10580 22:15:05.512106 <6>[ 1.066316] printk: bootconsole [mtk8250] disabled
10581 22:15:05.518362 <6>[ 1.077521] SuperH (H)SCI(F) driver initialized
10582 22:15:05.521611 <6>[ 1.082805] msm_serial: driver initialized
10583 22:15:05.536170 <6>[ 1.091744] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10584 22:15:05.545818 <6>[ 1.100293] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10585 22:15:05.552507 <6>[ 1.108835] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10586 22:15:05.562785 <6>[ 1.117463] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10587 22:15:05.572026 <6>[ 1.126169] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10588 22:15:05.578804 <6>[ 1.134882] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10589 22:15:05.589084 <6>[ 1.143422] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10590 22:15:05.594933 <6>[ 1.152233] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10591 22:15:05.607831 <6>[ 1.160776] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10592 22:15:05.617350 <6>[ 1.176406] loop: module loaded
10593 22:15:05.623594 <6>[ 1.182394] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10594 22:15:05.646490 <4>[ 1.205723] mtk-pmic-keys: Failed to locate of_node [id: -1]
10595 22:15:05.653551 <6>[ 1.212538] megasas: 07.719.03.00-rc1
10596 22:15:05.663111 <6>[ 1.222131] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10597 22:15:05.671194 <6>[ 1.229813] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10598 22:15:05.686722 <6>[ 1.245689] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10599 22:15:05.746804 <6>[ 1.298951] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10600 22:15:05.945436 <6>[ 1.504742] Freeing initrd memory: 17228K
10601 22:15:05.955634 <6>[ 1.515154] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10602 22:15:05.966516 <6>[ 1.525800] tun: Universal TUN/TAP device driver, 1.6
10603 22:15:05.970094 <6>[ 1.531853] thunder_xcv, ver 1.0
10604 22:15:05.973230 <6>[ 1.535358] thunder_bgx, ver 1.0
10605 22:15:05.976566 <6>[ 1.538852] nicpf, ver 1.0
10606 22:15:05.987082 <6>[ 1.542854] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10607 22:15:05.990048 <6>[ 1.550328] hns3: Copyright (c) 2017 Huawei Corporation.
10608 22:15:05.997207 <6>[ 1.555914] hclge is initializing
10609 22:15:06.000076 <6>[ 1.559493] e1000: Intel(R) PRO/1000 Network Driver
10610 22:15:06.007059 <6>[ 1.564622] e1000: Copyright (c) 1999-2006 Intel Corporation.
10611 22:15:06.009931 <6>[ 1.570634] e1000e: Intel(R) PRO/1000 Network Driver
10612 22:15:06.016820 <6>[ 1.575850] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10613 22:15:06.023204 <6>[ 1.582038] igb: Intel(R) Gigabit Ethernet Network Driver
10614 22:15:06.029631 <6>[ 1.587688] igb: Copyright (c) 2007-2014 Intel Corporation.
10615 22:15:06.036415 <6>[ 1.593524] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10616 22:15:06.043165 <6>[ 1.600042] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10617 22:15:06.046422 <6>[ 1.606512] sky2: driver version 1.30
10618 22:15:06.053231 <6>[ 1.611491] VFIO - User Level meta-driver version: 0.3
10619 22:15:06.060614 <6>[ 1.619724] usbcore: registered new interface driver usb-storage
10620 22:15:06.067265 <6>[ 1.626165] usbcore: registered new device driver onboard-usb-hub
10621 22:15:06.076026 <6>[ 1.635253] mt6397-rtc mt6359-rtc: registered as rtc0
10622 22:15:06.086010 <6>[ 1.640732] mt6397-rtc mt6359-rtc: setting system clock to 2023-06-05T22:15:10 UTC (1686003310)
10623 22:15:06.089276 <6>[ 1.650323] i2c_dev: i2c /dev entries driver
10624 22:15:06.106041 <6>[ 1.661897] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10625 22:15:06.112705 <6>[ 1.672095] sdhci: Secure Digital Host Controller Interface driver
10626 22:15:06.119567 <6>[ 1.678533] sdhci: Copyright(c) Pierre Ossman
10627 22:15:06.125919 <6>[ 1.683928] Synopsys Designware Multimedia Card Interface Driver
10628 22:15:06.129247 <6>[ 1.690539] mmc0: CQHCI version 5.10
10629 22:15:06.135970 <6>[ 1.691090] sdhci-pltfm: SDHCI platform and OF driver helper
10630 22:15:06.143204 <6>[ 1.702689] ledtrig-cpu: registered to indicate activity on CPUs
10631 22:15:06.154146 <6>[ 1.709912] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10632 22:15:06.157685 <6>[ 1.717310] usbcore: registered new interface driver usbhid
10633 22:15:06.164168 <6>[ 1.723143] usbhid: USB HID core driver
10634 22:15:06.170926 <6>[ 1.727398] spi_master spi0: will run message pump with realtime priority
10635 22:15:06.216959 <6>[ 1.769308] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10636 22:15:06.235565 <6>[ 1.784305] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10637 22:15:06.238818 <6>[ 1.797878] mmc0: Command Queue Engine enabled
10638 22:15:06.245895 <6>[ 1.799244] cros-ec-spi spi0.0: Chrome EC device registered
10639 22:15:06.249704 <6>[ 1.802611] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10640 22:15:06.256390 <6>[ 1.815712] mmcblk0: mmc0:0001 DA4128 116 GiB
10641 22:15:06.268768 <6>[ 1.823985] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10642 22:15:06.274804 <6>[ 1.826464] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10643 22:15:06.281471 <6>[ 1.835381] NET: Registered PF_PACKET protocol family
10644 22:15:06.285521 <6>[ 1.840672] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10645 22:15:06.291414 <6>[ 1.844639] 9pnet: Installing 9P2000 support
10646 22:15:06.295013 <6>[ 1.850368] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10647 22:15:06.301564 <5>[ 1.854333] Key type dns_resolver registered
10648 22:15:06.308245 <6>[ 1.860160] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10649 22:15:06.311153 <6>[ 1.864567] registered taskstats version 1
10650 22:15:06.315025 <5>[ 1.874939] Loading compiled-in X.509 certificates
10651 22:15:06.350029 <4>[ 1.902186] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10652 22:15:06.359579 <4>[ 1.912876] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10653 22:15:06.369943 <3>[ 1.925630] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10654 22:15:06.381856 <6>[ 1.941147] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10655 22:15:06.389120 <6>[ 1.948050] xhci-mtk 11200000.usb: xHCI Host Controller
10656 22:15:06.395883 <6>[ 1.953565] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10657 22:15:06.405368 <6>[ 1.961418] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10658 22:15:06.412712 <6>[ 1.970861] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10659 22:15:06.418700 <6>[ 1.976958] xhci-mtk 11200000.usb: xHCI Host Controller
10660 22:15:06.425437 <6>[ 1.982440] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10661 22:15:06.432611 <6>[ 1.990089] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10662 22:15:06.438784 <6>[ 1.997794] hub 1-0:1.0: USB hub found
10663 22:15:06.442226 <6>[ 2.001817] hub 1-0:1.0: 1 port detected
10664 22:15:06.452684 <6>[ 2.006167] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10665 22:15:06.454965 <6>[ 2.014910] hub 2-0:1.0: USB hub found
10666 22:15:06.458519 <6>[ 2.018947] hub 2-0:1.0: 1 port detected
10667 22:15:06.466659 <6>[ 2.026052] mtk-msdc 11f70000.mmc: Got CD GPIO
10668 22:15:06.484923 <6>[ 2.040389] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10669 22:15:06.491192 <6>[ 2.048426] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10670 22:15:06.501313 <4>[ 2.056399] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10671 22:15:06.511311 <6>[ 2.066063] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10672 22:15:06.517782 <6>[ 2.074148] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10673 22:15:06.524246 <6>[ 2.082186] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10674 22:15:06.534976 <6>[ 2.090102] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10675 22:15:06.540971 <6>[ 2.097924] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10676 22:15:06.550867 <6>[ 2.105745] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10677 22:15:06.560495 <6>[ 2.116501] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10678 22:15:06.570411 <6>[ 2.124869] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10679 22:15:06.577439 <6>[ 2.133221] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10680 22:15:06.586928 <6>[ 2.141569] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10681 22:15:06.593884 <6>[ 2.149913] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10682 22:15:06.603388 <6>[ 2.158255] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10683 22:15:06.610214 <6>[ 2.166599] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10684 22:15:06.619838 <6>[ 2.174942] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10685 22:15:06.626827 <6>[ 2.183285] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10686 22:15:06.636992 <6>[ 2.191629] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10687 22:15:06.643034 <6>[ 2.199972] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10688 22:15:06.653329 <6>[ 2.208315] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10689 22:15:06.659878 <6>[ 2.216663] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10690 22:15:06.669825 <6>[ 2.225007] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10691 22:15:06.676584 <6>[ 2.233353] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10692 22:15:06.683022 <6>[ 2.242255] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10693 22:15:06.691012 <6>[ 2.249750] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10694 22:15:06.697843 <6>[ 2.256818] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10695 22:15:06.708231 <6>[ 2.263962] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10696 22:15:06.715219 <6>[ 2.271273] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10697 22:15:06.724441 <6>[ 2.278179] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10698 22:15:06.731133 <6>[ 2.287319] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10699 22:15:06.741237 <6>[ 2.296446] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10700 22:15:06.751126 <6>[ 2.305749] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10701 22:15:06.760412 <6>[ 2.315224] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10702 22:15:06.770720 <6>[ 2.324697] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10703 22:15:06.776980 <6>[ 2.333823] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10704 22:15:06.786967 <6>[ 2.343298] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10705 22:15:06.796622 <6>[ 2.352428] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10706 22:15:06.806662 <6>[ 2.361730] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10707 22:15:06.816820 <6>[ 2.371898] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10708 22:15:06.827370 <6>[ 2.383739] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10709 22:15:06.834098 <6>[ 2.393674] Trying to probe devices needed for running init ...
10710 22:15:06.866462 <6>[ 2.422675] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10711 22:15:07.018504 <6>[ 2.578432] hub 1-1:1.0: USB hub found
10712 22:15:07.022413 <6>[ 2.582773] hub 1-1:1.0: 4 ports detected
10713 22:15:07.146137 <6>[ 2.702796] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10714 22:15:07.173037 <6>[ 2.732677] hub 2-1:1.0: USB hub found
10715 22:15:07.176218 <6>[ 2.737182] hub 2-1:1.0: 3 ports detected
10716 22:15:07.341932 <6>[ 2.898703] usb 1-1.1: new high-speed USB device number 3 using xhci-mtk
10717 22:15:07.473693 <6>[ 3.032580] hub 1-1.1:1.0: USB hub found
10718 22:15:07.476598 <6>[ 3.036865] hub 1-1.1:1.0: 4 ports detected
10719 22:15:07.589906 <6>[ 3.146478] usb 1-1.4: new high-speed USB device number 4 using xhci-mtk
10720 22:15:07.722956 <6>[ 3.282773] hub 1-1.4:1.0: USB hub found
10721 22:15:07.726423 <6>[ 3.287424] hub 1-1.4:1.0: 2 ports detected
10722 22:15:07.802001 <6>[ 3.358703] usb 1-1.1.1: new high-speed USB device number 5 using xhci-mtk
10723 22:15:07.990180 <6>[ 3.546703] usb 1-1.1.4: new full-speed USB device number 6 using xhci-mtk
10724 22:15:08.074896 <3>[ 3.634908] usb 1-1.1.4: device descriptor read/64, error -32
10725 22:15:08.267457 <3>[ 3.826918] usb 1-1.1.4: device descriptor read/64, error -32
10726 22:15:08.462892 <6>[ 4.018704] usb 1-1.4.1: new high-speed USB device number 7 using xhci-mtk
10727 22:15:08.650176 <6>[ 4.206666] usb 1-1.1.4: new full-speed USB device number 8 using xhci-mtk
10728 22:15:08.735483 <3>[ 4.294912] usb 1-1.1.4: device descriptor read/64, error -32
10729 22:15:08.927510 <3>[ 4.486925] usb 1-1.1.4: device descriptor read/64, error -32
10730 22:15:09.039190 <6>[ 4.599274] usb 1-1.1-port4: attempt power cycle
10731 22:15:09.126112 <6>[ 4.682705] usb 1-1.4.2: new high-speed USB device number 9 using xhci-mtk
10732 22:15:09.650231 <6>[ 5.206704] usb 1-1.1.4: new full-speed USB device number 10 using xhci-mtk
10733 22:15:09.656594 <4>[ 5.214156] usb 1-1.1.4: Device not responding to setup address.
10734 22:15:09.866893 <4>[ 5.427049] usb 1-1.1.4: Device not responding to setup address.
10735 22:15:10.078747 <3>[ 5.638692] usb 1-1.1.4: device not accepting address 10, error -71
10736 22:15:10.170660 <6>[ 5.726642] usb 1-1.1.4: new full-speed USB device number 11 using xhci-mtk
10737 22:15:10.177184 <4>[ 5.734137] usb 1-1.1.4: Device not responding to setup address.
10738 22:15:10.386816 <4>[ 5.946990] usb 1-1.1.4: Device not responding to setup address.
10739 22:15:10.598961 <3>[ 6.158557] usb 1-1.1.4: device not accepting address 11, error -71
10740 22:15:10.605750 <3>[ 6.165617] usb 1-1.1-port4: unable to enumerate USB device
10741 22:15:19.135782 <6>[ 14.699259] ALSA device list:
10742 22:15:19.142065 <6>[ 14.702514] No soundcards found.
10743 22:15:19.154595 <6>[ 14.714907] Freeing unused kernel memory: 8384K
10744 22:15:19.157604 <6>[ 14.719842] Run /init as init process
10745 22:15:19.168149 Loading, please wait...
10746 22:15:19.188504 Starting version 247.3-7+deb11u2
10747 22:15:19.508698 <6>[ 15.065620] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10748 22:15:19.522375 <6>[ 15.082874] remoteproc remoteproc0: scp is available
10749 22:15:19.532394 <4>[ 15.088386] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10750 22:15:19.538989 <6>[ 15.098235] remoteproc remoteproc0: powering up scp
10751 22:15:19.548431 <4>[ 15.104146] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10752 22:15:19.555354 <3>[ 15.104870] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10753 22:15:19.562060 <3>[ 15.113982] remoteproc remoteproc0: request_firmware failed: -2
10754 22:15:19.572205 <3>[ 15.128276] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10755 22:15:19.578441 <3>[ 15.136399] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10756 22:15:19.600234 <6>[ 15.157242] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10757 22:15:19.606539 <3>[ 15.158815] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10758 22:15:19.616283 <6>[ 15.166634] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10759 22:15:19.623137 <3>[ 15.173050] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10760 22:15:19.629522 <3>[ 15.173062] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10761 22:15:19.639278 <3>[ 15.173072] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10762 22:15:19.649330 <6>[ 15.180751] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10763 22:15:19.656039 <3>[ 15.188732] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10764 22:15:19.665969 <3>[ 15.188814] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10765 22:15:19.669478 <6>[ 15.191632] mc: Linux media interface: v0.10
10766 22:15:19.675943 <6>[ 15.197125] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10767 22:15:19.686387 <4>[ 15.209062] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10768 22:15:19.692865 <3>[ 15.209133] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10769 22:15:19.702357 <3>[ 15.209148] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10770 22:15:19.709087 <3>[ 15.209155] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10771 22:15:19.718896 <3>[ 15.216391] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10772 22:15:19.725731 <4>[ 15.222783] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10773 22:15:19.732320 <4>[ 15.222987] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10774 22:15:19.738817 <4>[ 15.222987] Fallback method does not support PEC.
10775 22:15:19.745182 <3>[ 15.229883] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10776 22:15:19.752151 <6>[ 15.230914] usbcore: registered new interface driver r8152
10777 22:15:19.758643 <6>[ 15.235670] videodev: Linux video capture interface: v2.00
10778 22:15:19.764974 <3>[ 15.243203] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10779 22:15:19.775454 <3>[ 15.243230] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10780 22:15:19.781291 <3>[ 15.243239] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10781 22:15:19.791490 <3>[ 15.243344] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10782 22:15:19.798086 <3>[ 15.252000] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10783 22:15:19.807721 <6>[ 15.318166] usb 1-1.1.1: reset high-speed USB device number 5 using xhci-mtk
10784 22:15:19.817486 <6>[ 15.326465] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10785 22:15:19.824397 <6>[ 15.335843] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10786 22:15:19.834614 <6>[ 15.340427] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10787 22:15:19.837388 <6>[ 15.348413] pci_bus 0000:00: root bus resource [bus 00-ff]
10788 22:15:19.848112 <6>[ 15.360395] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10789 22:15:19.854842 <6>[ 15.365021] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10790 22:15:19.864741 <6>[ 15.365028] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10791 22:15:19.871052 <6>[ 15.365075] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10792 22:15:19.878144 <6>[ 15.404621] usbcore: registered new interface driver cdc_ether
10793 22:15:19.888222 <3>[ 15.412542] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10794 22:15:19.894323 <6>[ 15.413471] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10795 22:15:19.897322 <6>[ 15.414497] Bluetooth: Core ver 2.22
10796 22:15:19.903685 <6>[ 15.414571] NET: Registered PF_BLUETOOTH protocol family
10797 22:15:19.910790 <6>[ 15.414574] Bluetooth: HCI device and connection manager initialized
10798 22:15:19.914237 <6>[ 15.414592] Bluetooth: HCI socket layer initialized
10799 22:15:19.920581 <6>[ 15.414598] Bluetooth: L2CAP socket layer initialized
10800 22:15:19.924170 <6>[ 15.414606] Bluetooth: SCO socket layer initialized
10801 22:15:19.930763 <6>[ 15.430818] usbcore: registered new interface driver r8153_ecm
10802 22:15:19.937419 <6>[ 15.436848] pci 0000:00:00.0: supports D1 D2
10803 22:15:19.943702 <4>[ 15.449707] r8152 1-1.1.1:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10804 22:15:19.950110 <6>[ 15.451671] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10805 22:15:19.960004 <6>[ 15.453098] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10806 22:15:19.969806 <6>[ 15.454564] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10807 22:15:19.976407 <6>[ 15.454830] usbcore: registered new interface driver uvcvideo
10808 22:15:19.986294 <4>[ 15.459159] r8152 1-1.1.1:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10809 22:15:19.989737 <6>[ 15.460684] usbcore: registered new interface driver btusb
10810 22:15:20.002985 <4>[ 15.461136] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10811 22:15:20.010062 <3>[ 15.461147] Bluetooth: hci0: Failed to load firmware file (-2)
10812 22:15:20.012563 <3>[ 15.461151] Bluetooth: hci0: Failed to set up firmware (-2)
10813 22:15:20.023319 <4>[ 15.461154] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10814 22:15:20.033084 <6>[ 15.464896] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10815 22:15:20.038992 <6>[ 15.465139] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10816 22:15:20.042542 <6>[ 15.518542] r8152 1-1.1.1:1.0 eth0: v1.12.13
10817 22:15:20.049353 <6>[ 15.524559] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10818 22:15:20.056295 <6>[ 15.546449] r8152 1-1.1.1:1.0 enxf4f5e850de0a: renamed from eth0
10819 22:15:20.062239 <6>[ 15.551140] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10820 22:15:20.071939 <6>[ 15.628980] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10821 22:15:20.078322 <6>[ 15.636468] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10822 22:15:20.081740 <6>[ 15.644054] pci 0000:01:00.0: supports D1 D2
10823 22:15:20.088434 <6>[ 15.648579] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10824 22:15:20.113445 <6>[ 15.670696] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10825 22:15:20.120199 <6>[ 15.677609] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10826 22:15:20.126813 <6>[ 15.685700] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10827 22:15:20.137385 <6>[ 15.693705] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10828 22:15:20.143116 <6>[ 15.701713] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10829 22:15:20.153200 <6>[ 15.709719] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10830 22:15:20.156487 <6>[ 15.717727] pci 0000:00:00.0: PCI bridge to [bus 01]
10831 22:15:20.166444 <6>[ 15.722948] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10832 22:15:20.173084 <6>[ 15.731107] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10833 22:15:20.179746 <6>[ 15.738321] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10834 22:15:20.185847 <6>[ 15.744806] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10835 22:15:20.204835 <5>[ 15.761983] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10836 22:15:20.225084 <5>[ 15.781703] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10837 22:15:20.231162 <4>[ 15.788602] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10838 22:15:20.237805 <6>[ 15.797503] cfg80211: failed to load regulatory.db
10839 22:15:20.287596 <6>[ 15.845238] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10840 22:15:20.294527 <6>[ 15.852830] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10841 22:15:20.319254 <6>[ 15.879535] mt7921e 0000:01:00.0: ASIC revision: 79610010
10842 22:15:20.424056 <4>[ 15.978017] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10843 22:15:20.441692 Begin: Loading essential drivers ... done.
10844 22:15:20.445154 Begin: Running /scripts/init-premount ... done.
10845 22:15:20.451470 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10846 22:15:20.461131 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10847 22:15:20.464666 Device /sys/class/net/enxf4f5e850de0a found
10848 22:15:20.465228 done.
10849 22:15:20.542807 <4>[ 16.096780] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10850 22:15:20.549196 IP-Config: enxf4f5e850de0a hardware address f4:f5:e8:50:de:0a mtu 1500 DHCP
10851 22:15:20.662130 <4>[ 16.216352] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10852 22:15:20.777882 <4>[ 16.332281] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10853 22:15:20.894136 <4>[ 16.448207] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10854 22:15:21.009955 <4>[ 16.564114] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10855 22:15:21.126362 <4>[ 16.680062] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10856 22:15:21.242092 <4>[ 16.796029] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10857 22:15:21.358577 <4>[ 16.912004] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10858 22:15:21.473575 <4>[ 17.027956] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10859 22:15:21.583471 IP-Config: no re<3>[ 17.142036] mt7921e 0000:01:00.0: hardware init failed
10860 22:15:21.584050 sponse after 2 secs - giving up
10861 22:15:21.616953 IP-Config: enxf4f5e850de0a hardware address f4:f5:e8:50:de:0a mtu 1500 DHCP
10862 22:15:21.642225 <6>[ 17.203100] r8152 1-1.1.1:1.0 enxf4f5e850de0a: carrier on
10863 22:15:22.721798 IP-Config: enxf4f5e850de0a complete (dhcp from 192.168.201.1):
10864 22:15:22.728469 address: 192.168.201.14 broadcast: 192.168.201.255 netmask: 255.255.255.0
10865 22:15:22.735080 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10866 22:15:22.741112 host : mt8192-asurada-spherion-r0-cbg-9
10867 22:15:22.747703 domain : lava-rack
10868 22:15:22.754460 rootserver: 192.168.201.1 rootpath:
10869 22:15:22.754543 filename :
10870 22:15:22.767069 done.
10871 22:15:22.773696 Begin: Running /scripts/nfs-bottom ... done.
10872 22:15:22.791880 Begin: Running /scripts/init-bottom ... done.
10873 22:15:23.930744 <6>[ 19.491476] NET: Registered PF_INET6 protocol family
10874 22:15:23.937318 <6>[ 19.498027] Segment Routing with IPv6
10875 22:15:23.940621 <6>[ 19.502020] In-situ OAM (IOAM) with IPv6
10876 22:15:24.056942 <30>[ 19.598680] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10877 22:15:24.060713 <30>[ 19.622433] systemd[1]: Detected architecture arm64.
10878 22:15:24.082047
10879 22:15:24.085670 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10880 22:15:24.086138
10881 22:15:24.108158 <30>[ 19.669362] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10882 22:15:24.679798 <30>[ 20.238117] systemd[1]: Queued start job for default target Graphical Interface.
10883 22:15:24.702552 <30>[ 20.263856] systemd[1]: Created slice system-getty.slice.
10884 22:15:24.708995 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10885 22:15:24.726445 <30>[ 20.287478] systemd[1]: Created slice system-modprobe.slice.
10886 22:15:24.733105 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10887 22:15:24.750375 <30>[ 20.311307] systemd[1]: Created slice system-serial\x2dgetty.slice.
10888 22:15:24.760728 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10889 22:15:24.774518 <30>[ 20.335249] systemd[1]: Created slice User and Session Slice.
10890 22:15:24.780991 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10891 22:15:24.801440 <30>[ 20.358915] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10892 22:15:24.810923 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10893 22:15:24.824823 <30>[ 20.382832] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10894 22:15:24.832212 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10895 22:15:24.852673 <30>[ 20.406743] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10896 22:15:24.858529 <30>[ 20.418752] systemd[1]: Reached target Local Encrypted Volumes.
10897 22:15:24.865514 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10898 22:15:24.882153 <30>[ 20.443070] systemd[1]: Reached target Paths.
10899 22:15:24.885294 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10900 22:15:24.901979 <30>[ 20.462751] systemd[1]: Reached target Remote File Systems.
10901 22:15:24.907908 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10902 22:15:24.922038 <30>[ 20.482730] systemd[1]: Reached target Slices.
10903 22:15:24.925209 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10904 22:15:24.941612 <30>[ 20.502746] systemd[1]: Reached target Swap.
10905 22:15:24.944868 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10906 22:15:24.965478 <30>[ 20.522980] systemd[1]: Listening on initctl Compatibility Named Pipe.
10907 22:15:24.971775 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10908 22:15:24.978095 <30>[ 20.538474] systemd[1]: Listening on Journal Audit Socket.
10909 22:15:24.985780 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10910 22:15:24.998503 <30>[ 20.559987] systemd[1]: Listening on Journal Socket (/dev/log).
10911 22:15:25.005359 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10912 22:15:25.022712 <30>[ 20.583537] systemd[1]: Listening on Journal Socket.
10913 22:15:25.029185 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10914 22:15:25.047069 <30>[ 20.604281] systemd[1]: Listening on Network Service Netlink Socket.
10915 22:15:25.052978 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10916 22:15:25.068768 <30>[ 20.629859] systemd[1]: Listening on udev Control Socket.
10917 22:15:25.075447 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10918 22:15:25.090124 <30>[ 20.650961] systemd[1]: Listening on udev Kernel Socket.
10919 22:15:25.096088 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10920 22:15:25.126164 <30>[ 20.687112] systemd[1]: Mounting Huge Pages File System...
10921 22:15:25.132142 Mounting [0;1;39mHuge Pages File System[0m...
10922 22:15:25.147973 <30>[ 20.709228] systemd[1]: Mounting POSIX Message Queue File System...
10923 22:15:25.154687 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10924 22:15:25.171806 <30>[ 20.733255] systemd[1]: Mounting Kernel Debug File System...
10925 22:15:25.178506 Mounting [0;1;39mKernel Debug File System[0m...
10926 22:15:25.197221 <30>[ 20.755045] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10927 22:15:25.233660 <30>[ 20.791101] systemd[1]: Starting Create list of static device nodes for the current kernel...
10928 22:15:25.239951 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10929 22:15:25.260090 <30>[ 20.821280] systemd[1]: Starting Load Kernel Module configfs...
10930 22:15:25.266494 Starting [0;1;39mLoad Kernel Module configfs[0m...
10931 22:15:25.283977 <30>[ 20.845355] systemd[1]: Starting Load Kernel Module drm...
10932 22:15:25.290606 Starting [0;1;39mLoad Kernel Module drm[0m...
10933 22:15:25.308045 <30>[ 20.869302] systemd[1]: Starting Load Kernel Module fuse...
10934 22:15:25.314744 Starting [0;1;39mLoad Kernel Module fuse[0m...
10935 22:15:25.345238 <6>[ 20.906710] fuse: init (API version 7.37)
10936 22:15:25.355350 <30>[ 20.912173] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10937 22:15:25.378132 <30>[ 20.939209] systemd[1]: Starting Journal Service...
10938 22:15:25.381329 Starting [0;1;39mJournal Service[0m...
10939 22:15:25.405948 <30>[ 20.967289] systemd[1]: Starting Load Kernel Modules...
10940 22:15:25.412551 Starting [0;1;39mLoad Kernel Modules[0m...
10941 22:15:25.430993 <30>[ 20.989141] systemd[1]: Starting Remount Root and Kernel File Systems...
10942 22:15:25.437680 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10943 22:15:25.452819 <30>[ 21.014351] systemd[1]: Starting Coldplug All udev Devices...
10944 22:15:25.459556 Starting [0;1;39mColdplug All udev Devices[0m...
10945 22:15:25.476193 <30>[ 21.037718] systemd[1]: Mounted Huge Pages File System.
10946 22:15:25.482730 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10947 22:15:25.497787 <30>[ 21.059114] systemd[1]: Mounted POSIX Message Queue File System.
10948 22:15:25.504450 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10949 22:15:25.522162 <30>[ 21.083188] systemd[1]: Mounted Kernel Debug File System.
10950 22:15:25.535837 [[0;32m OK [0m] Mounted [0;1;39mKernel Debu<3>[ 21.091823] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10951 22:15:25.539760 g File System[0m.
10952 22:15:25.558248 <30>[ 21.115621] systemd[1]: Finished Create list of static device nodes for the current kernel.
10953 22:15:25.568115 <3>[ 21.124080] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10954 22:15:25.575152 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10955 22:15:25.590267 <30>[ 21.151711] systemd[1]: modprobe@configfs.service: Succeeded.
10956 22:15:25.597630 <30>[ 21.158658] systemd[1]: Finished Load Kernel Module configfs.
10957 22:15:25.611218 [[0;32m OK [0m] Finished [0;1;39mLoad Kerne<3>[ 21.169004] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10958 22:15:25.614126 l Module configfs[0m.
10959 22:15:25.631440 <30>[ 21.191871] systemd[1]: modprobe@drm.service: Succeeded.
10960 22:15:25.637768 <30>[ 21.198087] systemd[1]: Finished Load Kernel Module drm.
10961 22:15:25.647836 <3>[ 21.200435] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10962 22:15:25.650992 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10963 22:15:25.671047 <30>[ 21.231939] systemd[1]: modprobe@fuse.service: Succeeded.
10964 22:15:25.681248 <3>[ 21.234519] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10965 22:15:25.686978 <30>[ 21.238238] systemd[1]: Finished Load Kernel Module fuse.
10966 22:15:25.690374 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module fuse[0m.
10967 22:15:25.708026 <30>[ 21.268035] systemd[1]: Finished Load Kernel Modules.
10968 22:15:25.717067 <3>[ 21.271636] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10969 22:15:25.724175 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10970 22:15:25.740266 <30>[ 21.300030] systemd[1]: Finished Remount Root and Kernel File Systems.
10971 22:15:25.752226 [[0;32m OK [<3>[ 21.307511] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10972 22:15:25.755758 0m] Finished [0;1;39mRemount Root and Kernel File Systems[0m.
10973 22:15:25.783779 <3>[ 21.341620] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10974 22:15:25.797203 <30>[ 21.358605] systemd[1]: Mounting FUSE Control File System...
10975 22:15:25.803838 Mounting [0;1;39mFUSE Control File System[0m...
10976 22:15:25.820165 <3>[ 21.378218] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10977 22:15:25.832597 <30>[ 21.390224] systemd[1]: Mounting Kernel Configuration File System...
10978 22:15:25.835315 Mounting [0;1;39mKernel Configuration File System[0m...
10979 22:15:25.853819 <3>[ 21.412020] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10980 22:15:25.871151 <30>[ 21.429091] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped.
10981 22:15:25.881237 <30>[ 21.438106] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped.
10982 22:15:25.918149 <30>[ 21.479273] systemd[1]: Starting Load/Save Random Seed...
10983 22:15:25.924813 Starting [0;1;39mLoad/Save Random Seed[0m...
10984 22:15:25.940129 <30>[ 21.501381] systemd[1]: Starting Apply Kernel Variables...
10985 22:15:25.946951 Starting [0;1;39mApply Kernel Variables[0m...
10986 22:15:25.964991 <30>[ 21.526688] systemd[1]: Starting Create System Users...
10987 22:15:25.972189 Starting [0;1;39mCreate System Users[0m...
10988 22:15:25.987263 <30>[ 21.548283] systemd[1]: Started Journal Service.
10989 22:15:26.003657 [[0;32m OK [<4>[ 21.553952] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10990 22:15:26.013891 0m] Started [0;<3>[ 21.570646] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10991 22:15:26.017217 1;39mJournal Service[0m.
10992 22:15:26.036452 [[0;32m OK [0m] Mounted [0;1;39mFUSE Control File System[0m.
10993 22:15:26.062910 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10994 22:15:26.077453 See 'systemctl status systemd-udev-trigger.service' for details.
10995 22:15:26.094075 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10996 22:15:26.110441 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10997 22:15:26.126571 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10998 22:15:26.142751 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10999 22:15:26.206524 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
11000 22:15:26.223496 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
11001 22:15:26.262714 <46>[ 21.821036] systemd-journald[292]: Received client request to flush runtime journal.
11002 22:15:26.292795 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
11003 22:15:26.305557 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
11004 22:15:26.320953 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
11005 22:15:26.360553 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
11006 22:15:27.646739 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
11007 22:15:27.693328 Starting [0;1;39mCreate Volatile Files and Directories[0m...
11008 22:15:27.713622 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
11009 22:15:27.736591 Starting [0;1;39mNetwork Service[0m...
11010 22:15:28.079384 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
11011 22:15:28.096923 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
11012 22:15:28.133911 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
11013 22:15:28.322208 <6>[ 23.884543] remoteproc remoteproc0: powering up scp
11014 22:15:28.348398 <4>[ 23.907127] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
11015 22:15:28.355092 <3>[ 23.917032] remoteproc remoteproc0: request_firmware failed: -2
11016 22:15:28.364878 <3>[ 23.923224] fops_vcodec_open(),166: [MTK_V4L2][ERROR] vpu_load_firmware failed!
11017 22:15:28.448306 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
11018 22:15:28.461368 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
11019 22:15:28.493835 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
11020 22:15:28.515005 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
11021 22:15:28.532948 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
11022 22:15:28.577507 Starting [0;1;39mNetwork Name Resolution[0m...
11023 22:15:28.602578 Starting [0;1;39mNetwork Time Synchronization[0m...
11024 22:15:28.619763 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
11025 22:15:28.641642 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
11026 22:15:28.671142 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
11027 22:15:28.713514 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
11028 22:15:28.849870 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
11029 22:15:28.869208 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
11030 22:15:28.893327 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
11031 22:15:28.909146 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
11032 22:15:28.928996 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
11033 22:15:29.056073 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
11034 22:15:29.095511 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
11035 22:15:29.114675 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
11036 22:15:29.664890 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
11037 22:15:29.676486 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
11038 22:15:29.844415 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
11039 22:15:29.856908 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
11040 22:15:29.873504 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
11041 22:15:29.917156 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
11042 22:15:30.200707 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
11043 22:15:30.290238 Starting [0;1;39mUser Login Management[0m...
11044 22:15:30.306066 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
11045 22:15:30.322096 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
11046 22:15:30.339975 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
11047 22:15:30.385399 Starting [0;1;39mPermit User Sessions[0m...
11048 22:15:30.455224 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
11049 22:15:30.497774 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
11050 22:15:30.537498 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
11051 22:15:30.561822 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
11052 22:15:30.577171 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
11053 22:15:30.599126 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
11054 22:15:30.618297 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
11055 22:15:30.637393 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
11056 22:15:30.678097 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
11057 22:15:30.719817 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
11058 22:15:30.811442
11059 22:15:30.812087
11060 22:15:30.814645 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
11061 22:15:30.815218
11062 22:15:30.817753 debian-bullseye-arm64 login: root (automatic login)
11063 22:15:30.818271
11064 22:15:30.818770
11065 22:15:31.063759 Linux debian-bullseye-arm64 6.1.31 #1 SMP PREEMPT Mon Jun 5 22:04:07 UTC 2023 aarch64
11066 22:15:31.064138
11067 22:15:31.070428 The programs included with the Debian GNU/Linux system are free software;
11068 22:15:31.076984 the exact distribution terms for each program are described in the
11069 22:15:31.080911 individual files in /usr/share/doc/*/copyright.
11070 22:15:31.081515
11071 22:15:31.087037 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11072 22:15:31.090356 permitted by applicable law.
11073 22:15:31.142205 Matched prompt #10: / #
11075 22:15:31.143283 Setting prompt string to ['/ #']
11076 22:15:31.143722 end: 2.2.5.1 login-action (duration 00:00:27) [common]
11078 22:15:31.144740 end: 2.2.5 auto-login-action (duration 00:00:28) [common]
11079 22:15:31.145184 start: 2.2.6 expect-shell-connection (timeout 00:03:39) [common]
11080 22:15:31.145553 Setting prompt string to ['/ #']
11081 22:15:31.145863 Forcing a shell prompt, looking for ['/ #']
11083 22:15:31.196708 / #
11084 22:15:31.197362 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11085 22:15:31.197818 Waiting using forced prompt support (timeout 00:02:30)
11086 22:15:31.203364
11087 22:15:31.204297 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11088 22:15:31.204858 start: 2.2.7 export-device-env (timeout 00:03:39) [common]
11090 22:15:31.306225 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/10597297/extract-nfsrootfs-iuuo3m7a'
11091 22:15:31.312616 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/10597297/extract-nfsrootfs-iuuo3m7a'
11093 22:15:31.414351 / # export NFS_SERVER_IP='192.168.201.1'
11094 22:15:31.420931 export NFS_SERVER_IP='192.168.201.1'
11095 22:15:31.422093 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11096 22:15:31.422840 end: 2.2 depthcharge-retry (duration 00:01:22) [common]
11097 22:15:31.423454 end: 2 depthcharge-action (duration 00:01:22) [common]
11098 22:15:31.423978 start: 3 lava-test-retry (timeout 00:01:00) [common]
11099 22:15:31.424469 start: 3.1 lava-test-shell (timeout 00:01:00) [common]
11100 22:15:31.424925 Using namespace: common
11102 22:15:31.526192 / # #
11103 22:15:31.526850 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
11104 22:15:31.532873 #
11105 22:15:31.533750 Using /lava-10597297
11107 22:15:31.634937 / # export SHELL=/bin/sh
11108 22:15:31.641965 export SHELL=/bin/sh
11110 22:15:31.743740 / # . /lava-10597297/environment
11111 22:15:31.750462 . /lava-10597297/environment
11113 22:15:31.856775 / # /lava-10597297/bin/lava-test-runner /lava-10597297/0
11114 22:15:31.857406 Test shell timeout: 10s (minimum of the action and connection timeout)
11115 22:15:31.863690 /lava-10597297/bin/lava-test-runner /lava-10597297/0
11116 22:15:32.084356 + export TESTRUN_ID=0_dmesg
11117 22:15:32.087327 + cd /lava-10597297/0/tests/0_dmesg
11118 22:15:32.090730 + cat uuid
11119 22:15:32.102381 + UUID=10597297_1.<8>[ 27.661030] <LAVA_SIGNAL_STARTRUN 0_dmesg 10597297_1.6.2.3.1>
11120 22:15:32.102925 6.2.3.1
11121 22:15:32.103349 + set +x
11122 22:15:32.104090 Received signal: <STARTRUN> 0_dmesg 10597297_1.6.2.3.1
11123 22:15:32.104724 Starting test lava.0_dmesg (10597297_1.6.2.3.1)
11124 22:15:32.105348 Skipping test definition patterns.
11125 22:15:32.109044 + KERNELCI_LAVA=y /bin/sh /opt/kernelci/dmesg.sh
11126 22:15:32.198945 <8>[ 27.757857] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0>
11127 22:15:32.199764 Received signal: <TESTCASE> TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0
11129 22:15:32.284764 <8>[ 27.842353] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0>
11130 22:15:32.285620 Received signal: <TESTCASE> TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0
11132 22:15:32.361005 <8>[ 27.919589] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0>
11133 22:15:32.361704 Received signal: <TESTCASE> TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0
11135 22:15:32.364773 + set +x
11136 22:15:32.366961 <8>[ 27.928954] <LAVA_SIGNAL_ENDRUN 0_dmesg 10597297_1.6.2.3.1>
11137 22:15:32.367769 Received signal: <ENDRUN> 0_dmesg 10597297_1.6.2.3.1
11138 22:15:32.368340 Ending use of test pattern.
11139 22:15:32.368819 Ending test lava.0_dmesg (10597297_1.6.2.3.1), duration 0.26
11141 22:15:32.374367 <LAVA_TEST_RUNNER EXIT>
11142 22:15:32.375041 ok: lava_test_shell seems to have completed
11143 22:15:32.375583 alert: pass
crit: pass
emerg: pass
11144 22:15:32.375993 end: 3.1 lava-test-shell (duration 00:00:01) [common]
11145 22:15:32.376407 end: 3 lava-test-retry (duration 00:00:01) [common]
11146 22:15:32.376872 start: 4 lava-test-retry (timeout 00:01:00) [common]
11147 22:15:32.377284 start: 4.1 lava-test-shell (timeout 00:01:00) [common]
11148 22:15:32.377613 Using namespace: common
11150 22:15:32.478817 / # #
11151 22:15:32.479476 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
11152 22:15:32.480112 Using /lava-10597297
11154 22:15:32.581506 export SHELL=/bin/sh
11155 22:15:32.582313 #
11157 22:15:32.683891 / # export SHELL=/bin/sh. /lava-10597297/environment
11158 22:15:32.684752
11160 22:15:32.786359 / # . /lava-10597297/environment/lava-10597297/bin/lava-test-runner /lava-10597297/1
11161 22:15:32.786987 Test shell timeout: 10s (minimum of the action and connection timeout)
11162 22:15:32.787598
11163 22:15:32.792855 / # /lava-10597297/bin/lava-test-runner /lava-10597297/1
11164 22:15:32.907624 + export TESTRUN_ID=1_bootrr
11165 22:15:32.910520 + cd /lava-10597297/1/tests/1_bootrr
11166 22:15:32.914079 + cat uuid
11167 22:15:32.927478 + UUID=10597297_1.<8>[ 28.486250] <LAVA_SIGNAL_STARTRUN 1_bootrr 10597297_1.6.2.3.5>
11168 22:15:32.928114 6.2.3.5
11169 22:15:32.928709 + set +x
11170 22:15:32.929499 Received signal: <STARTRUN> 1_bootrr 10597297_1.6.2.3.5
11171 22:15:32.929995 Starting test lava.1_bootrr (10597297_1.6.2.3.5)
11172 22:15:32.930572 Skipping test definition patterns.
11173 22:15:32.940582 + export PATH=/opt/bootrr/libexec/bootrr/helpers:/lava-10597297/1/../bin:/usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin
11174 22:15:32.943344 + cd /opt/bootrr/libexec/bootrr
11175 22:15:32.943930 + sh helpers/bootrr-auto
11176 22:15:32.999215 /lava-10597297/1/../bin/lava-test-case
11177 22:15:33.024917 <8>[ 28.584397] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=deferred-probe-empty RESULT=pass>
11178 22:15:33.025316 Received signal: <TESTCASE> TEST_CASE_ID=deferred-probe-empty RESULT=pass
11180 22:15:33.060309 /lava-10597297/1/../bin/lava-test-case
11181 22:15:33.078710 <8>[ 28.637781] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=all-cpus-are-online RESULT=pass>
11182 22:15:33.079515 Received signal: <TESTCASE> TEST_CASE_ID=all-cpus-are-online RESULT=pass
11184 22:15:33.102924 /lava-10597297/1/../bin/lava-test-case
11185 22:15:33.127136 <8>[ 28.686158] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm-chip-is-online RESULT=skip>
11186 22:15:33.127902 Received signal: <TESTCASE> TEST_CASE_ID=tpm-chip-is-online RESULT=skip
11188 22:15:33.183636 /lava-10597297/1/../bin/lava-test-case
11189 22:15:33.208144 <8>[ 28.766478] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-driver-present RESULT=pass>
11190 22:15:33.208995 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-driver-present RESULT=pass
11192 22:15:33.246402 /lava-10597297/1/../bin/lava-test-case
11193 22:15:33.276664 <8>[ 28.835275] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-topckgen-probed RESULT=pass>
11194 22:15:33.277466 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-topckgen-probed RESULT=pass
11196 22:15:33.309790 /lava-10597297/1/../bin/lava-test-case
11197 22:15:33.337835 <8>[ 28.895886] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-infracfg-probed RESULT=pass>
11198 22:15:33.338776 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-infracfg-probed RESULT=pass
11200 22:15:33.369846 /lava-10597297/1/../bin/lava-test-case
11201 22:15:33.396905 <8>[ 28.955751] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-pericfg-probed RESULT=pass>
11202 22:15:33.397850 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-pericfg-probed RESULT=pass
11204 22:15:33.428158 /lava-10597297/1/../bin/lava-test-case
11205 22:15:33.460047 <8>[ 29.018194] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-apmixedsys-probed RESULT=pass>
11206 22:15:33.461058 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-apmixedsys-probed RESULT=pass
11208 22:15:33.481026 /lava-10597297/1/../bin/lava-test-case
11209 22:15:33.508561 <8>[ 29.067657] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-aud-driver-present RESULT=pass>
11210 22:15:33.508907 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-aud-driver-present RESULT=pass
11212 22:15:33.536491 /lava-10597297/1/../bin/lava-test-case
11213 22:15:33.556397 <8>[ 29.115296] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-aud-probed RESULT=pass>
11214 22:15:33.557069 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-aud-probed RESULT=pass
11216 22:15:33.581411 /lava-10597297/1/../bin/lava-test-case
11217 22:15:33.604675 <8>[ 29.163504] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap-driver-present RESULT=pass>
11218 22:15:33.605481 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap-driver-present RESULT=pass
11220 22:15:33.640458 /lava-10597297/1/../bin/lava-test-case
11221 22:15:33.670988 <8>[ 29.229993] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_n-probed RESULT=pass>
11222 22:15:33.671782 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_n-probed RESULT=pass
11224 22:15:33.701137 /lava-10597297/1/../bin/lava-test-case
11225 22:15:33.726023 <8>[ 29.285645] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_ws-probed RESULT=pass>
11226 22:15:33.726398 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_ws-probed RESULT=pass
11228 22:15:33.755197 /lava-10597297/1/../bin/lava-test-case
11229 22:15:33.777981 <8>[ 29.335778] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_e-probed RESULT=pass>
11230 22:15:33.778775 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_e-probed RESULT=pass
11232 22:15:33.815059 /lava-10597297/1/../bin/lava-test-case
11233 22:15:33.842712 <8>[ 29.401210] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_s-probed RESULT=pass>
11234 22:15:33.843448 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_s-probed RESULT=pass
11236 22:15:33.865231 /lava-10597297/1/../bin/lava-test-case
11237 22:15:33.889315 <8>[ 29.448339] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mfg-driver-present RESULT=pass>
11238 22:15:33.889709 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mfg-driver-present RESULT=pass
11240 22:15:33.929273 /lava-10597297/1/../bin/lava-test-case
11241 22:15:33.960341 <8>[ 29.519752] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mfg-probed RESULT=pass>
11242 22:15:33.960627 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mfg-probed RESULT=pass
11244 22:15:33.979545 /lava-10597297/1/../bin/lava-test-case
11245 22:15:34.002107 <8>[ 29.560984] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mm-driver-present RESULT=pass>
11246 22:15:34.002958 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mm-driver-present RESULT=pass
11248 22:15:34.034911 /lava-10597297/1/../bin/lava-test-case
11249 22:15:34.059004 <8>[ 29.618323] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mm-probed RESULT=pass>
11250 22:15:34.059875 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mm-probed RESULT=pass
11252 22:15:34.081612 /lava-10597297/1/../bin/lava-test-case
11253 22:15:34.109206 <8>[ 29.668392] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-mmsys-driver-present RESULT=pass>
11254 22:15:34.109562 Received signal: <TESTCASE> TEST_CASE_ID=mtk-mmsys-driver-present RESULT=pass
11256 22:15:34.135180 /lava-10597297/1/../bin/lava-test-case
11257 22:15:34.156484 <8>[ 29.716054] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-mmsys-probed RESULT=pass>
11258 22:15:34.156854 Received signal: <TESTCASE> TEST_CASE_ID=mtk-mmsys-probed RESULT=pass
11260 22:15:34.173921 /lava-10597297/1/../bin/lava-test-case
11261 22:15:34.199792 <8>[ 29.758617] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-msdc-driver-present RESULT=pass>
11262 22:15:34.200244 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-msdc-driver-present RESULT=pass
11264 22:15:34.231133 /lava-10597297/1/../bin/lava-test-case
11265 22:15:34.256885 <8>[ 29.815671] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-msdc-probed RESULT=pass>
11266 22:15:34.257712 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-msdc-probed RESULT=pass
11268 22:15:34.284078 /lava-10597297/1/../bin/lava-test-case
11269 22:15:34.307113 <8>[ 29.865828] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec-driver-present RESULT=pass>
11270 22:15:34.307949 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec-driver-present RESULT=pass
11272 22:15:34.337681 /lava-10597297/1/../bin/lava-test-case
11273 22:15:34.362150 <8>[ 29.921076] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec_soc-probed RESULT=pass>
11274 22:15:34.363019 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec_soc-probed RESULT=pass
11276 22:15:34.390753 /lava-10597297/1/../bin/lava-test-case
11277 22:15:34.416817 <8>[ 29.975896] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec-probed RESULT=pass>
11278 22:15:34.417525 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec-probed RESULT=pass
11280 22:15:34.438136 /lava-10597297/1/../bin/lava-test-case
11281 22:15:34.463742 <8>[ 30.022768] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-venc-driver-present RESULT=pass>
11282 22:15:34.464617 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-venc-driver-present RESULT=pass
11284 22:15:34.497620 /lava-10597297/1/../bin/lava-test-case
11285 22:15:34.521053 <8>[ 30.080232] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-venc-probed RESULT=pass>
11286 22:15:34.521752 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-venc-probed RESULT=pass
11288 22:15:34.543409 /lava-10597297/1/../bin/lava-test-case
11289 22:15:34.567909 <8>[ 30.127160] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam-driver-present RESULT=pass>
11290 22:15:34.568728 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam-driver-present RESULT=pass
11292 22:15:34.606717 /lava-10597297/1/../bin/lava-test-case
11293 22:15:34.631789 <8>[ 30.190892] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam-probed RESULT=pass>
11294 22:15:34.632510 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam-probed RESULT=pass
11296 22:15:34.661446 /lava-10597297/1/../bin/lava-test-case
11297 22:15:34.687631 <8>[ 30.246406] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawa-probed RESULT=pass>
11298 22:15:34.688502 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawa-probed RESULT=pass
11300 22:15:34.715265 /lava-10597297/1/../bin/lava-test-case
11301 22:15:34.738218 <8>[ 30.297146] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawb-probed RESULT=pass>
11302 22:15:34.738498 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawb-probed RESULT=pass
11304 22:15:34.765924 /lava-10597297/1/../bin/lava-test-case
11305 22:15:34.788751 <8>[ 30.347473] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawc-probed RESULT=pass>
11306 22:15:34.789528 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawc-probed RESULT=pass
11308 22:15:34.808264 /lava-10597297/1/../bin/lava-test-case
11309 22:15:34.834382 <8>[ 30.393200] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img-driver-present RESULT=pass>
11310 22:15:34.835224 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img-driver-present RESULT=pass
11312 22:15:34.869636 /lava-10597297/1/../bin/lava-test-case
11313 22:15:34.899372 <8>[ 30.458413] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img-probed RESULT=pass>
11314 22:15:34.900145 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img-probed RESULT=pass
11316 22:15:34.933996 /lava-10597297/1/../bin/lava-test-case
11317 22:15:34.961191 <8>[ 30.520568] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img2-probed RESULT=pass>
11318 22:15:34.961960 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img2-probed RESULT=pass
11320 22:15:34.982706 /lava-10597297/1/../bin/lava-test-case
11321 22:15:35.011513 <8>[ 30.570333] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-ipe-driver-present RESULT=pass>
11322 22:15:35.012309 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-ipe-driver-present RESULT=pass
11324 22:15:35.046245 /lava-10597297/1/../bin/lava-test-case
11325 22:15:35.074525 <8>[ 30.633636] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-ipe-probed RESULT=pass>
11326 22:15:35.075340 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-ipe-probed RESULT=pass
11328 22:15:35.095771 /lava-10597297/1/../bin/lava-test-case
11329 22:15:35.124114 <8>[ 30.682952] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mdp-driver-present RESULT=pass>
11330 22:15:35.124818 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mdp-driver-present RESULT=pass
11332 22:15:35.154873 /lava-10597297/1/../bin/lava-test-case
11333 22:15:35.182065 <8>[ 30.741513] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mdp-probed RESULT=pass>
11334 22:15:35.182849 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mdp-probed RESULT=pass
11336 22:15:35.203827 /lava-10597297/1/../bin/lava-test-case
11337 22:15:35.228163 <8>[ 30.787177] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-pinctrl-driver-present RESULT=pass>
11338 22:15:35.229000 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-pinctrl-driver-present RESULT=pass
11340 22:15:35.266106 /lava-10597297/1/../bin/lava-test-case
11341 22:15:35.296398 <8>[ 30.855394] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-pinctrl-probed RESULT=pass>
11342 22:15:35.297211 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-pinctrl-probed RESULT=pass
11344 22:15:35.316030 /lava-10597297/1/../bin/lava-test-case
11345 22:15:35.339891 <8>[ 30.898989] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-power-controller-driver-present RESULT=pass>
11346 22:15:35.340648 Received signal: <TESTCASE> TEST_CASE_ID=mtk-power-controller-driver-present RESULT=pass
11348 22:15:35.373535 /lava-10597297/1/../bin/lava-test-case
11349 22:15:35.402716 <8>[ 30.961974] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-power-controller-probed RESULT=pass>
11350 22:15:35.403395 Received signal: <TESTCASE> TEST_CASE_ID=mtk-power-controller-probed RESULT=pass
11352 22:15:35.422775 /lava-10597297/1/../bin/lava-test-case
11353 22:15:35.453534 <8>[ 31.012244] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt-pmic-pwrap-driver-present RESULT=pass>
11354 22:15:35.454315 Received signal: <TESTCASE> TEST_CASE_ID=mt-pmic-pwrap-driver-present RESULT=pass
11356 22:15:35.485966 /lava-10597297/1/../bin/lava-test-case
11357 22:15:35.510169 <8>[ 31.069120] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt-pmic-pwrap-probed RESULT=pass>
11358 22:15:35.510943 Received signal: <TESTCASE> TEST_CASE_ID=mt-pmic-pwrap-probed RESULT=pass
11360 22:15:35.530455 /lava-10597297/1/../bin/lava-test-case
11361 22:15:35.558445 <8>[ 31.117440] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=spmi-mtk-driver-present RESULT=pass>
11362 22:15:35.559231 Received signal: <TESTCASE> TEST_CASE_ID=spmi-mtk-driver-present RESULT=pass
11364 22:15:35.594816 /lava-10597297/1/../bin/lava-test-case
11365 22:15:35.623451 <8>[ 31.182761] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=spmi-mtk-probed RESULT=pass>
11366 22:15:35.624132 Received signal: <TESTCASE> TEST_CASE_ID=spmi-mtk-probed RESULT=pass
11368 22:15:35.645595 /lava-10597297/1/../bin/lava-test-case
11369 22:15:35.672644 <8>[ 31.232129] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator-driver-present RESULT=pass>
11370 22:15:35.673440 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator-driver-present RESULT=pass
11372 22:15:35.708986 /lava-10597297/1/../bin/lava-test-case
11373 22:15:35.735109 <8>[ 31.294329] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator6-probed RESULT=pass>
11374 22:15:35.735907 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator6-probed RESULT=pass
11376 22:15:35.764309 /lava-10597297/1/../bin/lava-test-case
11377 22:15:35.789295 <8>[ 31.347717] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator7-probed RESULT=pass>
11378 22:15:35.790098 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator7-probed RESULT=pass
11380 22:15:36.824509 /lava-10597297/1/../bin/lava-test-case
11381 22:15:36.850013 <8>[ 32.409191] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-rpmsg-driver-present RESULT=fail>
11382 22:15:36.850866 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-rpmsg-driver-present RESULT=fail
11384 22:15:37.880133 /lava-10597297/1/../bin/lava-test-case
11385 22:15:37.906808 <8>[ 33.466405] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-rpmsg-probed RESULT=blocked>
11386 22:15:37.907605 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-rpmsg-probed RESULT=blocked
11387 22:15:37.908114 Bad test result: blocked
11388 22:15:37.930170 /lava-10597297/1/../bin/lava-test-case
11389 22:15:37.954791 <8>[ 33.514504] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c-mt65xx-driver-present RESULT=pass>
11390 22:15:37.955146 Received signal: <TESTCASE> TEST_CASE_ID=i2c-mt65xx-driver-present RESULT=pass
11392 22:15:37.982416 /lava-10597297/1/../bin/lava-test-case
11393 22:15:38.004964 <8>[ 33.565261] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c0-mt65xx-probed RESULT=pass>
11394 22:15:38.005229 Received signal: <TESTCASE> TEST_CASE_ID=i2c0-mt65xx-probed RESULT=pass
11396 22:15:38.039496 /lava-10597297/1/../bin/lava-test-case
11397 22:15:38.066683 <8>[ 33.626545] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c1-mt65xx-probed RESULT=pass>
11398 22:15:38.066961 Received signal: <TESTCASE> TEST_CASE_ID=i2c1-mt65xx-probed RESULT=pass
11400 22:15:38.092895 /lava-10597297/1/../bin/lava-test-case
11401 22:15:38.115325 <8>[ 33.674613] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c2-mt65xx-probed RESULT=pass>
11402 22:15:38.115683 Received signal: <TESTCASE> TEST_CASE_ID=i2c2-mt65xx-probed RESULT=pass
11404 22:15:38.143856 /lava-10597297/1/../bin/lava-test-case
11405 22:15:38.170059 <8>[ 33.729604] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c3-mt65xx-probed RESULT=pass>
11406 22:15:38.170812 Received signal: <TESTCASE> TEST_CASE_ID=i2c3-mt65xx-probed RESULT=pass
11408 22:15:38.206494 /lava-10597297/1/../bin/lava-test-case
11409 22:15:38.232352 <8>[ 33.791928] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c7-mt65xx-probed RESULT=pass>
11410 22:15:38.233201 Received signal: <TESTCASE> TEST_CASE_ID=i2c7-mt65xx-probed RESULT=pass
11412 22:15:38.253469 /lava-10597297/1/../bin/lava-test-case
11413 22:15:38.279279 <8>[ 33.839074] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-driver-present RESULT=pass>
11414 22:15:38.280093 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-driver-present RESULT=pass
11416 22:15:38.313268 /lava-10597297/1/../bin/lava-test-case
11417 22:15:38.341169 <8>[ 33.900042] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi1-probed RESULT=pass>
11418 22:15:38.341849 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi1-probed RESULT=pass
11420 22:15:38.372450 /lava-10597297/1/../bin/lava-test-case
11421 22:15:38.400159 <8>[ 33.959808] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi5-probed RESULT=pass>
11422 22:15:38.400990 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi5-probed RESULT=pass
11424 22:15:38.422766 /lava-10597297/1/../bin/lava-test-case
11425 22:15:38.451767 <8>[ 34.011204] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6577-uart-driver-present RESULT=pass>
11426 22:15:38.452440 Received signal: <TESTCASE> TEST_CASE_ID=mt6577-uart-driver-present RESULT=pass
11428 22:15:38.485487 /lava-10597297/1/../bin/lava-test-case
11429 22:15:38.511437 <8>[ 34.070895] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6577-uart-probed RESULT=pass>
11430 22:15:38.512215 Received signal: <TESTCASE> TEST_CASE_ID=mt6577-uart-probed RESULT=pass
11432 22:15:38.536278 /lava-10597297/1/../bin/lava-test-case
11433 22:15:38.557651 <8>[ 34.117083] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-common-driver-present RESULT=pass>
11434 22:15:38.558422 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-common-driver-present RESULT=pass
11436 22:15:38.591912 /lava-10597297/1/../bin/lava-test-case
11437 22:15:38.617326 <8>[ 34.176751] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-common-probed RESULT=pass>
11438 22:15:38.618157 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-common-probed RESULT=pass
11440 22:15:38.638025 /lava-10597297/1/../bin/lava-test-case
11441 22:15:38.661508 <8>[ 34.221126] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb-driver-present RESULT=pass>
11442 22:15:38.662326 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb-driver-present RESULT=pass
11444 22:15:38.690419 /lava-10597297/1/../bin/lava-test-case
11445 22:15:38.720980 <8>[ 34.280685] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb0-probed RESULT=pass>
11446 22:15:38.721834 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb0-probed RESULT=pass
11448 22:15:38.753264 /lava-10597297/1/../bin/lava-test-case
11449 22:15:38.777568 <8>[ 34.337039] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb5-probed RESULT=pass>
11450 22:15:38.778399 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb5-probed RESULT=pass
11452 22:15:38.814733 /lava-10597297/1/../bin/lava-test-case
11453 22:15:38.840969 <8>[ 34.400661] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb14-probed RESULT=pass>
11454 22:15:38.841911 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb14-probed RESULT=pass
11456 22:15:38.879317 /lava-10597297/1/../bin/lava-test-case
11457 22:15:38.909672 <8>[ 34.468860] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb20-probed RESULT=pass>
11458 22:15:38.910521 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb20-probed RESULT=pass
11460 22:15:38.942587 /lava-10597297/1/../bin/lava-test-case
11461 22:15:38.968956 <8>[ 34.528458] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb1-probed RESULT=pass>
11462 22:15:38.969762 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb1-probed RESULT=pass
11464 22:15:39.005529 /lava-10597297/1/../bin/lava-test-case
11465 22:15:39.037533 <8>[ 34.596584] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb4-probed RESULT=pass>
11466 22:15:39.038211 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb4-probed RESULT=pass
11468 22:15:39.070263 /lava-10597297/1/../bin/lava-test-case
11469 22:15:39.094865 <8>[ 34.654499] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb16-probed RESULT=pass>
11470 22:15:39.095594 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb16-probed RESULT=pass
11472 22:15:39.128749 /lava-10597297/1/../bin/lava-test-case
11473 22:15:39.158687 <8>[ 34.717883] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb19-probed RESULT=pass>
11474 22:15:39.159498 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb19-probed RESULT=pass
11476 22:15:39.191936 /lava-10597297/1/../bin/lava-test-case
11477 22:15:39.216130 <8>[ 34.775523] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb9-probed RESULT=pass>
11478 22:15:39.216985 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb9-probed RESULT=pass
11480 22:15:39.253694 /lava-10597297/1/../bin/lava-test-case
11481 22:15:39.276804 <8>[ 34.836326] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb7-probed RESULT=pass>
11482 22:15:39.277597 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb7-probed RESULT=pass
11484 22:15:39.311419 /lava-10597297/1/../bin/lava-test-case
11485 22:15:39.341085 <8>[ 34.900806] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb17-probed RESULT=pass>
11486 22:15:39.341927 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb17-probed RESULT=pass
11488 22:15:39.373636 /lava-10597297/1/../bin/lava-test-case
11489 22:15:39.399827 <8>[ 34.959530] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb2-probed RESULT=pass>
11490 22:15:39.400699 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb2-probed RESULT=pass
11492 22:15:39.430882 /lava-10597297/1/../bin/lava-test-case
11493 22:15:39.457612 <8>[ 35.017384] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb11-probed RESULT=pass>
11494 22:15:39.458428 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb11-probed RESULT=pass
11496 22:15:39.486763 /lava-10597297/1/../bin/lava-test-case
11497 22:15:39.514334 <8>[ 35.073900] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb13-probed RESULT=pass>
11498 22:15:39.515157 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb13-probed RESULT=pass
11500 22:15:39.542193 /lava-10597297/1/../bin/lava-test-case
11501 22:15:39.570230 <8>[ 35.130172] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb18-probed RESULT=pass>
11502 22:15:39.571076 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb18-probed RESULT=pass
11504 22:15:39.596776 /lava-10597297/1/../bin/lava-test-case
11505 22:15:39.622811 <8>[ 35.181899] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-iommu-driver-present RESULT=pass>
11506 22:15:39.623601 Received signal: <TESTCASE> TEST_CASE_ID=mtk-iommu-driver-present RESULT=pass
11508 22:15:39.654148 /lava-10597297/1/../bin/lava-test-case
11509 22:15:39.676309 <8>[ 35.236395] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-iommu-probed RESULT=pass>
11510 22:15:39.676541 Received signal: <TESTCASE> TEST_CASE_ID=mtk-iommu-probed RESULT=pass
11512 22:15:39.698246 /lava-10597297/1/../bin/lava-test-case
11513 22:15:39.724263 <8>[ 35.283218] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-spi-driver-present RESULT=pass>
11514 22:15:39.725015 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-spi-driver-present RESULT=pass
11516 22:15:39.755424 /lava-10597297/1/../bin/lava-test-case
11517 22:15:39.782816 <8>[ 35.342136] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-spi-probed RESULT=pass>
11518 22:15:39.783590 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-spi-probed RESULT=pass
11520 22:15:39.803754 /lava-10597297/1/../bin/lava-test-case
11521 22:15:39.835708 <8>[ 35.395085] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-i2c-tunnel-driver-present RESULT=pass>
11522 22:15:39.836555 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-i2c-tunnel-driver-present RESULT=pass
11524 22:15:39.868039 /lava-10597297/1/../bin/lava-test-case
11525 22:15:39.893187 <8>[ 35.453135] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-i2c-tunnel-probed RESULT=pass>
11526 22:15:39.894001 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-i2c-tunnel-probed RESULT=pass
11528 22:15:39.925462 /lava-10597297/1/../bin/lava-test-case
11529 22:15:39.950348 <8>[ 35.510211] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-typec-driver-present RESULT=pass>
11530 22:15:39.951115 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-typec-driver-present RESULT=pass
11532 22:15:39.983204 /lava-10597297/1/../bin/lava-test-case
11533 22:15:40.011189 <8>[ 35.570768] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-typec-probed RESULT=pass>
11534 22:15:40.011873 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-typec-probed RESULT=pass
11536 22:15:40.034783 /lava-10597297/1/../bin/lava-test-case
11537 22:15:40.067007 <8>[ 35.626823] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-pwm-driver-present RESULT=pass>
11538 22:15:40.067883 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-pwm-driver-present RESULT=pass
11540 22:15:40.097650 /lava-10597297/1/../bin/lava-test-case
11541 22:15:40.123285 <8>[ 35.683031] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-pwm-probed RESULT=pass>
11542 22:15:40.124133 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-pwm-probed RESULT=pass
11544 22:15:40.146039 /lava-10597297/1/../bin/lava-test-case
11545 22:15:40.177033 <8>[ 35.736805] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator-driver-present RESULT=pass>
11546 22:15:40.177828 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator-driver-present RESULT=pass
11548 22:15:40.209571 /lava-10597297/1/../bin/lava-test-case
11549 22:15:40.234668 <8>[ 35.793849] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator0-probed RESULT=pass>
11550 22:15:40.235501 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator0-probed RESULT=pass
11552 22:15:40.272282 /lava-10597297/1/../bin/lava-test-case
11553 22:15:40.295716 <8>[ 35.855618] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator1-probed RESULT=pass>
11554 22:15:40.296400 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator1-probed RESULT=pass
11556 22:15:40.320431 /lava-10597297/1/../bin/lava-test-case
11557 22:15:40.348424 <8>[ 35.908345] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-keyb-driver-present RESULT=pass>
11558 22:15:40.349180 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-keyb-driver-present RESULT=pass
11560 22:15:40.379555 /lava-10597297/1/../bin/lava-test-case
11561 22:15:40.403069 <8>[ 35.962684] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-keyb-probed RESULT=pass>
11562 22:15:40.403760 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-keyb-probed RESULT=pass
11564 22:15:40.424971 /lava-10597297/1/../bin/lava-test-case
11565 22:15:40.454143 <8>[ 36.013750] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=leds_pwm-driver-present RESULT=pass>
11566 22:15:40.454968 Received signal: <TESTCASE> TEST_CASE_ID=leds_pwm-driver-present RESULT=pass
11568 22:15:40.484367 /lava-10597297/1/../bin/lava-test-case
11569 22:15:40.508618 <8>[ 36.067938] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=leds_pwm-probed RESULT=pass>
11570 22:15:40.509388 Received signal: <TESTCASE> TEST_CASE_ID=leds_pwm-probed RESULT=pass
11572 22:15:40.531473 /lava-10597297/1/../bin/lava-test-case
11573 22:15:40.559288 <8>[ 36.117973] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elan_i2c-driver-present RESULT=pass>
11574 22:15:40.560057 Received signal: <TESTCASE> TEST_CASE_ID=elan_i2c-driver-present RESULT=pass
11576 22:15:41.609687 /lava-10597297/1/../bin/lava-test-case
11577 22:15:41.643425 <8>[ 37.203065] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elan_i2c-probed RESULT=fail>
11578 22:15:41.643814 Received signal: <TESTCASE> TEST_CASE_ID=elan_i2c-probed RESULT=fail
11580 22:15:41.661141 /lava-10597297/1/../bin/lava-test-case
11581 22:15:41.684001 <8>[ 37.244172] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elants_i2c-driver-present RESULT=pass>
11582 22:15:41.684694 Received signal: <TESTCASE> TEST_CASE_ID=elants_i2c-driver-present RESULT=pass
11584 22:15:42.726243 /lava-10597297/1/../bin/lava-test-case
11585 22:15:42.756437 <8>[ 38.316257] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elants_i2c-probed RESULT=fail>
11586 22:15:42.757223 Received signal: <TESTCASE> TEST_CASE_ID=elants_i2c-probed RESULT=fail
11588 22:15:42.780505 /lava-10597297/1/../bin/lava-test-case
11589 22:15:42.810722 <8>[ 38.370231] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mipi-tx-driver-present RESULT=pass>
11590 22:15:42.811528 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mipi-tx-driver-present RESULT=pass
11592 22:15:43.854181 /lava-10597297/1/../bin/lava-test-case
11593 22:15:43.881821 <8>[ 39.442622] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mipi-tx-probed RESULT=fail>
11594 22:15:43.882140 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mipi-tx-probed RESULT=fail
11596 22:15:43.902412 /lava-10597297/1/../bin/lava-test-case
11597 22:15:43.921810 <8>[ 39.482083] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-dsi-driver-present RESULT=pass>
11598 22:15:43.922162 Received signal: <TESTCASE> TEST_CASE_ID=mtk-dsi-driver-present RESULT=pass
11600 22:15:44.959185 /lava-10597297/1/../bin/lava-test-case
11601 22:15:44.989619 <8>[ 40.550107] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-dsi-probed RESULT=fail>
11602 22:15:44.990366 Received signal: <TESTCASE> TEST_CASE_ID=mtk-dsi-probed RESULT=fail
11604 22:15:45.014047 /lava-10597297/1/../bin/lava-test-case
11605 22:15:45.045894 <8>[ 40.606295] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-driver-present RESULT=pass>
11606 22:15:45.046724 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-driver-present RESULT=pass
11608 22:15:46.090027 /lava-10597297/1/../bin/lava-test-case
11609 22:15:46.117245 <8>[ 41.677863] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-3-probed RESULT=fail>
11610 22:15:46.117569 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-3-probed RESULT=fail
11612 22:15:46.135134 /lava-10597297/1/../bin/lava-test-case
11613 22:15:46.153623 <8>[ 41.714306] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-pwm-driver-present RESULT=pass>
11614 22:15:46.153927 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-pwm-driver-present RESULT=pass
11616 22:15:47.185347 /lava-10597297/1/../bin/lava-test-case
11617 22:15:47.207506 <8>[ 42.768633] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-pwm-probed RESULT=fail>
11618 22:15:47.207822 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-pwm-probed RESULT=fail
11620 22:15:47.224820 /lava-10597297/1/../bin/lava-test-case
11621 22:15:47.243165 <8>[ 42.804346] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pwm-backlight-driver-present RESULT=pass>
11622 22:15:47.243482 Received signal: <TESTCASE> TEST_CASE_ID=pwm-backlight-driver-present RESULT=pass
11624 22:15:48.277331 /lava-10597297/1/../bin/lava-test-case
11625 22:15:48.300666 <8>[ 43.861946] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pwm-backlight-probed RESULT=fail>
11626 22:15:48.300979 Received signal: <TESTCASE> TEST_CASE_ID=pwm-backlight-probed RESULT=fail
11628 22:15:48.316941 /lava-10597297/1/../bin/lava-test-case
11629 22:15:48.335860 <8>[ 43.896876] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-edp-driver-present RESULT=pass>
11630 22:15:48.336161 Received signal: <TESTCASE> TEST_CASE_ID=panel-edp-driver-present RESULT=pass
11632 22:15:48.352066 /lava-10597297/1/../bin/lava-test-case
11633 22:15:48.372762 <8>[ 43.933990] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-simple-dp-aux-driver-present RESULT=pass>
11634 22:15:48.373058 Received signal: <TESTCASE> TEST_CASE_ID=panel-simple-dp-aux-driver-present RESULT=pass
11636 22:15:49.404081 /lava-10597297/1/../bin/lava-test-case
11637 22:15:49.429555 <8>[ 44.990312] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-simple-dp-aux-probed RESULT=fail>
11638 22:15:49.429870 Received signal: <TESTCASE> TEST_CASE_ID=panel-simple-dp-aux-probed RESULT=fail
11640 22:15:49.448316 /lava-10597297/1/../bin/lava-test-case
11641 22:15:49.471903 <8>[ 45.033327] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mutex-driver-present RESULT=pass>
11642 22:15:49.472198 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mutex-driver-present RESULT=pass
11644 22:15:49.503332 /lava-10597297/1/../bin/lava-test-case
11645 22:15:49.528836 <8>[ 45.089896] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mutex-probed RESULT=pass>
11646 22:15:49.529155 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mutex-probed RESULT=pass
11648 22:15:49.549496 /lava-10597297/1/../bin/lava-test-case
11649 22:15:49.573337 <8>[ 45.134325] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl-driver-present RESULT=pass>
11650 22:15:49.573645 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl-driver-present RESULT=pass
11652 22:15:49.604659 /lava-10597297/1/../bin/lava-test-case
11653 22:15:49.628052 <8>[ 45.189360] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl0-probed RESULT=pass>
11654 22:15:49.628372 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl0-probed RESULT=pass
11656 22:15:49.655103 /lava-10597297/1/../bin/lava-test-case
11657 22:15:49.673652 <8>[ 45.234913] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl2l0-probed RESULT=pass>
11658 22:15:49.673954 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl2l0-probed RESULT=pass
11660 22:15:49.701347 /lava-10597297/1/../bin/lava-test-case
11661 22:15:49.724108 <8>[ 45.284976] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl2l2-probed RESULT=pass>
11662 22:15:49.724432 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl2l2-probed RESULT=pass
11664 22:15:49.749171 /lava-10597297/1/../bin/lava-test-case
11665 22:15:49.766256 <8>[ 45.326699] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma-driver-present RESULT=pass>
11666 22:15:49.766554 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma-driver-present RESULT=pass
11668 22:15:49.788869 /lava-10597297/1/../bin/lava-test-case
11669 22:15:49.804992 <8>[ 45.366216] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma0-probed RESULT=pass>
11670 22:15:49.805309 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma0-probed RESULT=pass
11672 22:15:49.828683 /lava-10597297/1/../bin/lava-test-case
11673 22:15:49.845184 <8>[ 45.406443] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma4-probed RESULT=pass>
11674 22:15:49.845496 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma4-probed RESULT=pass
11676 22:15:49.863481 /lava-10597297/1/../bin/lava-test-case
11677 22:15:49.885660 <8>[ 45.446801] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-aal-driver-present RESULT=pass>
11678 22:15:49.885962 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-aal-driver-present RESULT=pass
11680 22:15:49.909990 /lava-10597297/1/../bin/lava-test-case
11681 22:15:49.929569 <8>[ 45.491063] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-aal-probed RESULT=pass>
11682 22:15:49.929891 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-aal-probed RESULT=pass
11684 22:15:49.945379 /lava-10597297/1/../bin/lava-test-case
11685 22:15:49.964307 <8>[ 45.525473] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ccorr-driver-present RESULT=pass>
11686 22:15:49.964641 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ccorr-driver-present RESULT=pass
11688 22:15:49.989826 /lava-10597297/1/../bin/lava-test-case
11689 22:15:50.008953 <8>[ 45.570319] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ccorr-probed RESULT=pass>
11690 22:15:50.009272 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ccorr-probed RESULT=pass
11692 22:15:50.033043 /lava-10597297/1/../bin/lava-test-case
11693 22:15:50.052388 <8>[ 45.613331] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-color-driver-present RESULT=pass>
11694 22:15:50.052760 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-color-driver-present RESULT=pass
11696 22:15:50.079636 /lava-10597297/1/../bin/lava-test-case
11697 22:15:50.097874 <8>[ 45.658924] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-color-probed RESULT=pass>
11698 22:15:50.098235 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-color-probed RESULT=pass
11700 22:15:50.114926 /lava-10597297/1/../bin/lava-test-case
11701 22:15:50.137518 <8>[ 45.697526] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-gamma-driver-present RESULT=pass>
11702 22:15:50.137820 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-gamma-driver-present RESULT=pass
11704 22:15:50.160526 /lava-10597297/1/../bin/lava-test-case
11705 22:15:50.181978 <8>[ 45.742189] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-gamma-probed RESULT=pass>
11706 22:15:50.182293 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-gamma-probed RESULT=pass
11708 22:15:50.200415 /lava-10597297/1/../bin/lava-test-case
11709 22:15:50.222235 <8>[ 45.783127] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-drm-driver-present RESULT=pass>
11710 22:15:50.222553 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-drm-driver-present RESULT=pass
11712 22:15:50.246549 /lava-10597297/1/../bin/lava-test-case
11713 22:15:50.267696 <8>[ 45.828889] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-drm-probed RESULT=pass>
11714 22:15:50.268016 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-drm-probed RESULT=pass
11716 22:15:50.287251 /lava-10597297/1/../bin/lava-test-case
11717 22:15:50.309094 <8>[ 45.870080] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-dpi-driver-present RESULT=pass>
11718 22:15:50.309409 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-dpi-driver-present RESULT=pass
11720 22:15:50.587631 <6>[ 46.154773] vpu: disabling
11721 22:15:50.590357 <6>[ 46.157835] vproc2: disabling
11722 22:15:50.593198 <6>[ 46.161114] vproc1: disabling
11723 22:15:50.596782 <6>[ 46.164376] vaud18: disabling
11724 22:15:50.603358 <6>[ 46.167779] vsram_others: disabling
11725 22:15:50.606723 <6>[ 46.171653] va09: disabling
11726 22:15:50.609978 <6>[ 46.174758] vsram_md: disabling
11727 22:15:50.612685 <6>[ 46.178242] Vgpu: disabling
11728 22:15:51.347233 /lava-10597297/1/../bin/lava-test-case
11729 22:15:51.372203 <8>[ 46.933797] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-dpi-probed RESULT=fail>
11730 22:15:51.372560 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-dpi-probed RESULT=fail
11732 22:15:52.408316 /lava-10597297/1/../bin/lava-test-case
11733 22:15:52.430756 <8>[ 47.992079] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-7-probed RESULT=fail>
11734 22:15:52.431079 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-7-probed RESULT=fail
11736 22:15:52.448079 /lava-10597297/1/../bin/lava-test-case
11737 22:15:52.471391 <8>[ 48.032462] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=sbs-battery-driver-present RESULT=pass>
11738 22:15:52.471764 Received signal: <TESTCASE> TEST_CASE_ID=sbs-battery-driver-present RESULT=pass
11740 22:15:52.497716 /lava-10597297/1/../bin/lava-test-case
11741 22:15:52.517495 <8>[ 48.078595] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=sbs-battery-probed RESULT=pass>
11742 22:15:52.517855 Received signal: <TESTCASE> TEST_CASE_ID=sbs-battery-probed RESULT=pass
11744 22:15:52.534113 /lava-10597297/1/../bin/lava-test-case
11745 22:15:52.554816 <8>[ 48.116576] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-pcie-gen3-driver-present RESULT=pass>
11746 22:15:52.555174 Received signal: <TESTCASE> TEST_CASE_ID=mtk-pcie-gen3-driver-present RESULT=pass
11748 22:15:52.579932 /lava-10597297/1/../bin/lava-test-case
11749 22:15:52.599950 <8>[ 48.161794] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-pcie-gen3-probed RESULT=pass>
11750 22:15:52.600265 Received signal: <TESTCASE> TEST_CASE_ID=mtk-pcie-gen3-probed RESULT=pass
11752 22:15:52.617366 /lava-10597297/1/../bin/lava-test-case
11753 22:15:52.638379 <8>[ 48.200406] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt7921e-driver-present RESULT=pass>
11754 22:15:52.638691 Received signal: <TESTCASE> TEST_CASE_ID=mt7921e-driver-present RESULT=pass
11756 22:15:52.663530 /lava-10597297/1/../bin/lava-test-case
11757 22:15:52.681844 <8>[ 48.243390] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt7921e-probed RESULT=pass>
11758 22:15:52.682201 Received signal: <TESTCASE> TEST_CASE_ID=mt7921e-probed RESULT=pass
11760 22:15:52.704656 /lava-10597297/1/../bin/lava-test-case
11761 22:15:52.722607 <8>[ 48.284253] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm_tis_spi-driver-present RESULT=pass>
11762 22:15:52.723008 Received signal: <TESTCASE> TEST_CASE_ID=tpm_tis_spi-driver-present RESULT=pass
11764 22:15:52.747918 /lava-10597297/1/../bin/lava-test-case
11765 22:15:52.768346 <8>[ 48.329731] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm_tis_spi-probed RESULT=pass>
11766 22:15:52.768661 Received signal: <TESTCASE> TEST_CASE_ID=tpm_tis_spi-probed RESULT=pass
11768 22:15:52.784046 /lava-10597297/1/../bin/lava-test-case
11769 22:15:52.805964 <8>[ 48.367297] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-msdc-driver-present RESULT=pass>
11770 22:15:52.806303 Received signal: <TESTCASE> TEST_CASE_ID=mtk-msdc-driver-present RESULT=pass
11772 22:15:52.832371 /lava-10597297/1/../bin/lava-test-case
11773 22:15:52.850880 <8>[ 48.412444] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-msdc-probed RESULT=pass>
11774 22:15:52.851193 Received signal: <TESTCASE> TEST_CASE_ID=mtk-msdc-probed RESULT=pass
11776 22:15:52.869781 /lava-10597297/1/../bin/lava-test-case
11777 22:15:52.890948 <8>[ 48.452862] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-nor-driver-present RESULT=pass>
11778 22:15:52.891256 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-nor-driver-present RESULT=pass
11780 22:15:52.916872 /lava-10597297/1/../bin/lava-test-case
11781 22:15:52.936076 <8>[ 48.497366] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-nor-probed RESULT=pass>
11782 22:15:52.936409 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-nor-probed RESULT=pass
11784 22:15:52.955592 /lava-10597297/1/../bin/lava-test-case
11785 22:15:52.979947 <8>[ 48.540901] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-tphy-driver-present RESULT=pass>
11786 22:15:52.980262 Received signal: <TESTCASE> TEST_CASE_ID=mtk-tphy-driver-present RESULT=pass
11788 22:15:53.012792 /lava-10597297/1/../bin/lava-test-case
11789 22:15:53.031221 <8>[ 48.592906] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-tphy-probed RESULT=pass>
11790 22:15:53.031523 Received signal: <TESTCASE> TEST_CASE_ID=mtk-tphy-probed RESULT=pass
11792 22:15:53.049552 /lava-10597297/1/../bin/lava-test-case
11793 22:15:53.070002 <8>[ 48.631713] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=xhci-mtk-driver-present RESULT=pass>
11794 22:15:53.070323 Received signal: <TESTCASE> TEST_CASE_ID=xhci-mtk-driver-present RESULT=pass
11796 22:15:53.099218 /lava-10597297/1/../bin/lava-test-case
11797 22:15:53.125367 <8>[ 48.687011] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=xhci-mtk-probed RESULT=pass>
11798 22:15:53.125687 Received signal: <TESTCASE> TEST_CASE_ID=xhci-mtk-probed RESULT=pass
11800 22:15:53.142895 /lava-10597297/1/../bin/lava-test-case
11801 22:15:53.164430 <8>[ 48.726135] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-scp-driver-present RESULT=pass>
11802 22:15:53.164802 Received signal: <TESTCASE> TEST_CASE_ID=mtk-scp-driver-present RESULT=pass
11804 22:15:53.195290 /lava-10597297/1/../bin/lava-test-case
11805 22:15:53.219443 <8>[ 48.781133] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-scp-probed RESULT=pass>
11806 22:15:53.219761 Received signal: <TESTCASE> TEST_CASE_ID=mtk-scp-probed RESULT=pass
11808 22:15:53.237885 /lava-10597297/1/../bin/lava-test-case
11809 22:15:53.259399 <8>[ 48.820640] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-enc-driver-present RESULT=pass>
11810 22:15:53.259713 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-enc-driver-present RESULT=pass
11812 22:15:53.287869 /lava-10597297/1/../bin/lava-test-case
11813 22:15:53.312411 <8>[ 48.873861] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-enc-probed RESULT=pass>
11814 22:15:53.312784 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-enc-probed RESULT=pass
11816 22:15:54.344445 /lava-10597297/1/../bin/lava-test-case
11817 22:15:54.367091 <8>[ 49.928912] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-dec-driver-present RESULT=fail>
11818 22:15:54.367419 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-dec-driver-present RESULT=fail
11820 22:15:55.397430 /lava-10597297/1/../bin/lava-test-case
11821 22:15:55.421802 <8>[ 50.983962] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-dec-probed RESULT=blocked>
11822 22:15:55.422150 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-dec-probed RESULT=blocked
11823 22:15:55.422250 Bad test result: blocked
11824 22:15:55.441145 /lava-10597297/1/../bin/lava-test-case
11825 22:15:55.460878 <8>[ 51.023055] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panfrost-driver-present RESULT=pass>
11826 22:15:55.461196 Received signal: <TESTCASE> TEST_CASE_ID=panfrost-driver-present RESULT=pass
11828 22:15:56.494036 /lava-10597297/1/../bin/lava-test-case
11829 22:15:56.524945 <8>[ 52.086935] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panfrost-probed RESULT=fail>
11830 22:15:56.525257 Received signal: <TESTCASE> TEST_CASE_ID=panfrost-probed RESULT=fail
11832 22:15:56.542062 /lava-10597297/1/../bin/lava-test-case
11833 22:15:56.560352 <8>[ 52.122280] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo-driver-present RESULT=pass>
11834 22:15:56.560659 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo-driver-present RESULT=pass
11836 22:15:56.587303 /lava-10597297/1/../bin/lava-test-case
11837 22:15:56.609832 <8>[ 52.172086] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo0-probed RESULT=pass>
11838 22:15:56.610166 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo0-probed RESULT=pass
11840 22:15:56.634930 /lava-10597297/1/../bin/lava-test-case
11841 22:15:56.654840 <8>[ 52.216618] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo1-probed RESULT=pass>
11842 22:15:56.655187 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo1-probed RESULT=pass
11844 22:15:56.671124 /lava-10597297/1/../bin/lava-test-case
11845 22:15:56.695385 <8>[ 52.257547] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-audio-driver-present RESULT=pass>
11846 22:15:56.695705 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-audio-driver-present RESULT=pass
11848 22:15:56.719850 /lava-10597297/1/../bin/lava-test-case
11849 22:15:56.737760 <8>[ 52.299882] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-audio-probed RESULT=pass>
11850 22:15:56.738072 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-audio-probed RESULT=pass
11852 22:15:56.753142 /lava-10597297/1/../bin/lava-test-case
11853 22:15:56.775459 <8>[ 52.337134] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dmic-codec-driver-present RESULT=pass>
11854 22:15:56.775780 Received signal: <TESTCASE> TEST_CASE_ID=dmic-codec-driver-present RESULT=pass
11856 22:15:57.813197 /lava-10597297/1/../bin/lava-test-case
11857 22:15:57.837940 <8>[ 53.400191] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dmic-codec-probed RESULT=fail>
11858 22:15:57.838621 Received signal: <TESTCASE> TEST_CASE_ID=dmic-codec-probed RESULT=fail
11860 22:15:57.854840 /lava-10597297/1/../bin/lava-test-case
11861 22:15:57.880629 <8>[ 53.442978] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt5682-driver-present RESULT=pass>
11862 22:15:57.880901 Received signal: <TESTCASE> TEST_CASE_ID=rt5682-driver-present RESULT=pass
11864 22:15:58.916299 /lava-10597297/1/../bin/lava-test-case
11865 22:15:58.938955 <8>[ 54.501230] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt5682-probed RESULT=fail>
11866 22:15:58.939238 Received signal: <TESTCASE> TEST_CASE_ID=rt5682-probed RESULT=fail
11868 22:15:58.957428 /lava-10597297/1/../bin/lava-test-case
11869 22:15:58.977395 <8>[ 54.539524] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt1015p-driver-present RESULT=pass>
11870 22:15:58.978019 Received signal: <TESTCASE> TEST_CASE_ID=rt1015p-driver-present RESULT=pass
11872 22:16:00.017850 /lava-10597297/1/../bin/lava-test-case
11873 22:16:00.046382 <8>[ 55.608302] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt1015p-probed RESULT=fail>
11874 22:16:00.046958 Received signal: <TESTCASE> TEST_CASE_ID=rt1015p-probed RESULT=fail
11876 22:16:00.062732 /lava-10597297/1/../bin/lava-test-case
11877 22:16:00.087035 <8>[ 55.649393] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192_mt6359-driver-present RESULT=pass>
11878 22:16:00.087746 Received signal: <TESTCASE> TEST_CASE_ID=mt8192_mt6359-driver-present RESULT=pass
11880 22:16:01.125072 /lava-10597297/1/../bin/lava-test-case
11881 22:16:01.153936 <8>[ 56.716317] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192_mt6359-probed RESULT=fail>
11882 22:16:01.154490 Received signal: <TESTCASE> TEST_CASE_ID=mt8192_mt6359-probed RESULT=fail
11884 22:16:01.172084 /lava-10597297/1/../bin/lava-test-case
11885 22:16:01.196411 <8>[ 56.758859] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb-driver-present RESULT=pass>
11886 22:16:01.196970 Received signal: <TESTCASE> TEST_CASE_ID=btusb-driver-present RESULT=pass
11888 22:16:01.223605 /lava-10597297/1/../bin/lava-test-case
11889 22:16:01.243931 <8>[ 56.806022] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb0-probed RESULT=pass>
11890 22:16:01.244475 Received signal: <TESTCASE> TEST_CASE_ID=btusb0-probed RESULT=pass
11892 22:16:01.269869 /lava-10597297/1/../bin/lava-test-case
11893 22:16:01.290622 <8>[ 56.852766] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb1-probed RESULT=pass>
11894 22:16:01.291349 Received signal: <TESTCASE> TEST_CASE_ID=btusb1-probed RESULT=pass
11896 22:16:01.310634 /lava-10597297/1/../bin/lava-test-case
11897 22:16:01.333136 <8>[ 56.895626] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-wdt-driver-present RESULT=pass>
11898 22:16:01.333848 Received signal: <TESTCASE> TEST_CASE_ID=mtk-wdt-driver-present RESULT=pass
11900 22:16:01.363610 /lava-10597297/1/../bin/lava-test-case
11901 22:16:01.392348 <8>[ 56.954942] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-wdt-probed RESULT=pass>
11902 22:16:01.393372 Received signal: <TESTCASE> TEST_CASE_ID=mtk-wdt-probed RESULT=pass
11904 22:16:01.411692 /lava-10597297/1/../bin/lava-test-case
11905 22:16:01.435365 <8>[ 56.997705] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek,efuse-driver-present RESULT=pass>
11906 22:16:01.435928 Received signal: <TESTCASE> TEST_CASE_ID=mediatek,efuse-driver-present RESULT=pass
11908 22:16:01.472804 /lava-10597297/1/../bin/lava-test-case
11909 22:16:01.491933 <8>[ 57.054665] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek,efuse-probed RESULT=pass>
11910 22:16:01.492626 Received signal: <TESTCASE> TEST_CASE_ID=mediatek,efuse-probed RESULT=pass
11912 22:16:01.510619 /lava-10597297/1/../bin/lava-test-case
11913 22:16:01.531214 <8>[ 57.093836] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-cpufreq-hw-driver-present RESULT=pass>
11914 22:16:01.531946 Received signal: <TESTCASE> TEST_CASE_ID=mtk-cpufreq-hw-driver-present RESULT=pass
11916 22:16:02.568029 /lava-10597297/1/../bin/lava-test-case
11917 22:16:02.587312 <8>[ 58.150318] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-cpufreq-hw-probed RESULT=fail>
11918 22:16:02.587628 Received signal: <TESTCASE> TEST_CASE_ID=mtk-cpufreq-hw-probed RESULT=fail
11920 22:16:02.593076 + set +x
11921 22:16:02.596202 Received signal: <ENDRUN> 1_bootrr 10597297_1.6.2.3.5
11922 22:16:02.596300 Ending use of test pattern.
11923 22:16:02.596367 Ending test lava.1_bootrr (10597297_1.6.2.3.5), duration 29.67
11925 22:16:02.599094 <8>[ 58.162047] <LAVA_SIGNAL_ENDRUN 1_bootrr 10597297_1.6.2.3.5>
11926 22:16:02.602393 <LAVA_TEST_RUNNER EXIT>
11927 22:16:02.602648 ok: lava_test_shell seems to have completed
11928 22:16:02.603613 all-cpus-are-online: pass
anx7625-3-probed: fail
anx7625-7-probed: fail
anx7625-driver-present: pass
btusb-driver-present: pass
btusb0-probed: pass
btusb1-probed: pass
clk-mt8192-apmixedsys-probed: pass
clk-mt8192-aud-driver-present: pass
clk-mt8192-aud-probed: pass
clk-mt8192-cam-driver-present: pass
clk-mt8192-cam-probed: pass
clk-mt8192-cam_rawa-probed: pass
clk-mt8192-cam_rawb-probed: pass
clk-mt8192-cam_rawc-probed: pass
clk-mt8192-driver-present: pass
clk-mt8192-img-driver-present: pass
clk-mt8192-img-probed: pass
clk-mt8192-img2-probed: pass
clk-mt8192-imp_iic_wrap-driver-present: pass
clk-mt8192-imp_iic_wrap_e-probed: pass
clk-mt8192-imp_iic_wrap_n-probed: pass
clk-mt8192-imp_iic_wrap_s-probed: pass
clk-mt8192-imp_iic_wrap_ws-probed: pass
clk-mt8192-infracfg-probed: pass
clk-mt8192-ipe-driver-present: pass
clk-mt8192-ipe-probed: pass
clk-mt8192-mdp-driver-present: pass
clk-mt8192-mdp-probed: pass
clk-mt8192-mfg-driver-present: pass
clk-mt8192-mfg-probed: pass
clk-mt8192-mm-driver-present: pass
clk-mt8192-mm-probed: pass
clk-mt8192-msdc-driver-present: pass
clk-mt8192-msdc-probed: pass
clk-mt8192-pericfg-probed: pass
clk-mt8192-topckgen-probed: pass
clk-mt8192-vdec-driver-present: pass
clk-mt8192-vdec-probed: pass
clk-mt8192-vdec_soc-probed: pass
clk-mt8192-venc-driver-present: pass
clk-mt8192-venc-probed: pass
cros-ec-i2c-tunnel-driver-present: pass
cros-ec-i2c-tunnel-probed: pass
cros-ec-keyb-driver-present: pass
cros-ec-keyb-probed: pass
cros-ec-pwm-driver-present: pass
cros-ec-pwm-probed: pass
cros-ec-regulator-driver-present: pass
cros-ec-regulator0-probed: pass
cros-ec-regulator1-probed: pass
cros-ec-rpmsg-driver-present: fail
cros-ec-spi-driver-present: pass
cros-ec-spi-probed: pass
cros-ec-typec-driver-present: pass
cros-ec-typec-probed: pass
deferred-probe-empty: pass
dmic-codec-driver-present: pass
dmic-codec-probed: fail
elan_i2c-driver-present: pass
elan_i2c-probed: fail
elants_i2c-driver-present: pass
elants_i2c-probed: fail
i2c-mt65xx-driver-present: pass
i2c0-mt65xx-probed: pass
i2c1-mt65xx-probed: pass
i2c2-mt65xx-probed: pass
i2c3-mt65xx-probed: pass
i2c7-mt65xx-probed: pass
leds_pwm-driver-present: pass
leds_pwm-probed: pass
mediatek,efuse-driver-present: pass
mediatek,efuse-probed: pass
mediatek-disp-aal-driver-present: pass
mediatek-disp-aal-probed: pass
mediatek-disp-ccorr-driver-present: pass
mediatek-disp-ccorr-probed: pass
mediatek-disp-color-driver-present: pass
mediatek-disp-color-probed: pass
mediatek-disp-gamma-driver-present: pass
mediatek-disp-gamma-probed: pass
mediatek-disp-ovl-driver-present: pass
mediatek-disp-ovl0-probed: pass
mediatek-disp-ovl2l0-probed: pass
mediatek-disp-ovl2l2-probed: pass
mediatek-disp-pwm-driver-present: pass
mediatek-disp-pwm-probed: fail
mediatek-disp-rdma-driver-present: pass
mediatek-disp-rdma0-probed: pass
mediatek-disp-rdma4-probed: pass
mediatek-dpi-driver-present: pass
mediatek-dpi-probed: fail
mediatek-drm-driver-present: pass
mediatek-drm-probed: pass
mediatek-mipi-tx-driver-present: pass
mediatek-mipi-tx-probed: fail
mediatek-mutex-driver-present: pass
mediatek-mutex-probed: pass
mt-pmic-pwrap-driver-present: pass
mt-pmic-pwrap-probed: pass
mt6315-regulator-driver-present: pass
mt6315-regulator6-probed: pass
mt6315-regulator7-probed: pass
mt6577-uart-driver-present: pass
mt6577-uart-probed: pass
mt7921e-driver-present: pass
mt7921e-probed: pass
mt8192-audio-driver-present: pass
mt8192-audio-probed: pass
mt8192-pinctrl-driver-present: pass
mt8192-pinctrl-probed: pass
mt8192_mt6359-driver-present: pass
mt8192_mt6359-probed: fail
mtk-cpufreq-hw-driver-present: pass
mtk-cpufreq-hw-probed: fail
mtk-dsi-driver-present: pass
mtk-dsi-probed: fail
mtk-iommu-driver-present: pass
mtk-iommu-probed: pass
mtk-mmsys-driver-present: pass
mtk-mmsys-probed: pass
mtk-msdc-driver-present: pass
mtk-msdc-probed: pass
mtk-pcie-gen3-driver-present: pass
mtk-pcie-gen3-probed: pass
mtk-power-controller-driver-present: pass
mtk-power-controller-probed: pass
mtk-scp-driver-present: pass
mtk-scp-probed: pass
mtk-smi-common-driver-present: pass
mtk-smi-common-probed: pass
mtk-smi-larb-driver-present: pass
mtk-smi-larb0-probed: pass
mtk-smi-larb1-probed: pass
mtk-smi-larb11-probed: pass
mtk-smi-larb13-probed: pass
mtk-smi-larb14-probed: pass
mtk-smi-larb16-probed: pass
mtk-smi-larb17-probed: pass
mtk-smi-larb18-probed: pass
mtk-smi-larb19-probed: pass
mtk-smi-larb2-probed: pass
mtk-smi-larb20-probed: pass
mtk-smi-larb4-probed: pass
mtk-smi-larb5-probed: pass
mtk-smi-larb7-probed: pass
mtk-smi-larb9-probed: pass
mtk-spi-driver-present: pass
mtk-spi-nor-driver-present: pass
mtk-spi-nor-probed: pass
mtk-spi1-probed: pass
mtk-spi5-probed: pass
mtk-tphy-driver-present: pass
mtk-tphy-probed: pass
mtk-vcodec-dec-driver-present: fail
mtk-vcodec-enc-driver-present: pass
mtk-vcodec-enc-probed: pass
mtk-wdt-driver-present: pass
mtk-wdt-probed: pass
panel-edp-driver-present: pass
panel-simple-dp-aux-driver-present: pass
panel-simple-dp-aux-probed: fail
panfrost-driver-present: pass
panfrost-probed: fail
pwm-backlight-driver-present: pass
pwm-backlight-probed: fail
rt1015p-driver-present: pass
rt1015p-probed: fail
rt5682-driver-present: pass
rt5682-probed: fail
sbs-battery-driver-present: pass
sbs-battery-probed: pass
spmi-mtk-driver-present: pass
spmi-mtk-probed: pass
tpm-chip-is-online: skip
tpm_tis_spi-driver-present: pass
tpm_tis_spi-probed: pass
uvcvideo-driver-present: pass
uvcvideo0-probed: pass
uvcvideo1-probed: pass
xhci-mtk-driver-present: pass
xhci-mtk-probed: pass
11929 22:16:02.603758 end: 4.1 lava-test-shell (duration 00:00:30) [common]
11930 22:16:02.603845 end: 4 lava-test-retry (duration 00:00:30) [common]
11931 22:16:02.603932 start: 5 finalize (timeout 00:07:43) [common]
11932 22:16:02.604025 start: 5.1 power-off (timeout 00:00:30) [common]
11933 22:16:02.604178 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-9' '--port=1' '--command=off'
11934 22:16:02.680298 >> Command sent successfully.
11935 22:16:02.682835 Returned 0 in 0 seconds
11936 22:16:02.783274 end: 5.1 power-off (duration 00:00:00) [common]
11938 22:16:02.783625 start: 5.2 read-feedback (timeout 00:07:42) [common]
11939 22:16:02.783884 Listened to connection for namespace 'common' for up to 1s
11940 22:16:03.784635 Finalising connection for namespace 'common'
11941 22:16:03.784818 Disconnecting from shell: Finalise
11942 22:16:03.784899 / #
11943 22:16:03.885230 end: 5.2 read-feedback (duration 00:00:01) [common]
11944 22:16:03.885400 end: 5 finalize (duration 00:00:01) [common]
11945 22:16:03.885510 Cleaning after the job
11946 22:16:03.885605 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10597297/tftp-deploy-7relhzi_/ramdisk
11947 22:16:03.887595 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10597297/tftp-deploy-7relhzi_/kernel
11948 22:16:03.896210 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10597297/tftp-deploy-7relhzi_/dtb
11949 22:16:03.896367 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10597297/tftp-deploy-7relhzi_/nfsrootfs
11950 22:16:03.950103 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10597297/tftp-deploy-7relhzi_/modules
11951 22:16:03.955420 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/10597297
11952 22:16:04.262331 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/10597297
11953 22:16:04.262514 Job finished correctly