Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 31
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 23
1 22:13:26.043785 lava-dispatcher, installed at version: 2023.05.1
2 22:13:26.044003 start: 0 validate
3 22:13:26.044144 Start time: 2023-06-05 22:13:26.044137+00:00 (UTC)
4 22:13:26.044276 Using caching service: 'http://localhost/cache/?uri=%s'
5 22:13:26.044407 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-cros-ec%2F20230527.0%2Farm64%2Frootfs.cpio.gz exists
6 22:13:26.363597 Using caching service: 'http://localhost/cache/?uri=%s'
7 22:13:26.364434 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1314-g1ab0ac1d7e2e3%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 22:13:56.883834 Using caching service: 'http://localhost/cache/?uri=%s'
9 22:13:56.884623 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1314-g1ab0ac1d7e2e3%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 22:13:57.180320 Using caching service: 'http://localhost/cache/?uri=%s'
11 22:13:57.181067 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1314-g1ab0ac1d7e2e3%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 22:14:08.980320 validate duration: 42.94
14 22:14:08.980630 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 22:14:08.980749 start: 1.1 download-retry (timeout 00:10:00) [common]
16 22:14:08.980853 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 22:14:08.980996 Not decompressing ramdisk as can be used compressed.
18 22:14:08.981098 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-cros-ec/20230527.0/arm64/rootfs.cpio.gz
19 22:14:08.981174 saving as /var/lib/lava/dispatcher/tmp/10597227/tftp-deploy-x8cwzr0n/ramdisk/rootfs.cpio.gz
20 22:14:08.981263 total size: 34405874 (32MB)
21 22:14:09.275700 progress 0% (0MB)
22 22:14:09.285423 progress 5% (1MB)
23 22:14:09.294861 progress 10% (3MB)
24 22:14:09.304351 progress 15% (4MB)
25 22:14:09.313804 progress 20% (6MB)
26 22:14:09.323448 progress 25% (8MB)
27 22:14:09.332739 progress 30% (9MB)
28 22:14:09.342129 progress 35% (11MB)
29 22:14:09.351265 progress 40% (13MB)
30 22:14:09.360491 progress 45% (14MB)
31 22:14:09.369677 progress 50% (16MB)
32 22:14:09.378563 progress 55% (18MB)
33 22:14:09.387348 progress 60% (19MB)
34 22:14:09.396236 progress 65% (21MB)
35 22:14:09.404894 progress 70% (22MB)
36 22:14:09.413751 progress 75% (24MB)
37 22:14:09.422538 progress 80% (26MB)
38 22:14:09.431354 progress 85% (27MB)
39 22:14:09.440030 progress 90% (29MB)
40 22:14:09.448580 progress 95% (31MB)
41 22:14:09.456945 progress 100% (32MB)
42 22:14:09.457206 32MB downloaded in 0.48s (68.94MB/s)
43 22:14:09.457359 end: 1.1.1 http-download (duration 00:00:00) [common]
45 22:14:09.457600 end: 1.1 download-retry (duration 00:00:00) [common]
46 22:14:09.457686 start: 1.2 download-retry (timeout 00:10:00) [common]
47 22:14:09.457768 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 22:14:09.457902 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1314-g1ab0ac1d7e2e3/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 22:14:09.457973 saving as /var/lib/lava/dispatcher/tmp/10597227/tftp-deploy-x8cwzr0n/kernel/Image
50 22:14:09.458034 total size: 45746688 (43MB)
51 22:14:09.458093 No compression specified
52 22:14:09.459234 progress 0% (0MB)
53 22:14:09.470582 progress 5% (2MB)
54 22:14:09.482020 progress 10% (4MB)
55 22:14:09.493695 progress 15% (6MB)
56 22:14:09.505265 progress 20% (8MB)
57 22:14:09.516836 progress 25% (10MB)
58 22:14:09.528434 progress 30% (13MB)
59 22:14:09.539932 progress 35% (15MB)
60 22:14:09.551376 progress 40% (17MB)
61 22:14:09.562812 progress 45% (19MB)
62 22:14:09.574325 progress 50% (21MB)
63 22:14:09.585610 progress 55% (24MB)
64 22:14:09.597273 progress 60% (26MB)
65 22:14:09.608981 progress 65% (28MB)
66 22:14:09.620629 progress 70% (30MB)
67 22:14:09.632234 progress 75% (32MB)
68 22:14:09.643715 progress 80% (34MB)
69 22:14:09.655230 progress 85% (37MB)
70 22:14:09.666754 progress 90% (39MB)
71 22:14:09.678058 progress 95% (41MB)
72 22:14:09.689308 progress 100% (43MB)
73 22:14:09.689448 43MB downloaded in 0.23s (188.53MB/s)
74 22:14:09.689599 end: 1.2.1 http-download (duration 00:00:00) [common]
76 22:14:09.689827 end: 1.2 download-retry (duration 00:00:00) [common]
77 22:14:09.689913 start: 1.3 download-retry (timeout 00:09:59) [common]
78 22:14:09.689998 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 22:14:09.690138 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1314-g1ab0ac1d7e2e3/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 22:14:09.690216 saving as /var/lib/lava/dispatcher/tmp/10597227/tftp-deploy-x8cwzr0n/dtb/mt8192-asurada-spherion-r0.dtb
81 22:14:09.690279 total size: 46924 (0MB)
82 22:14:09.690338 No compression specified
83 22:14:09.990567 progress 69% (0MB)
84 22:14:09.990975 progress 100% (0MB)
85 22:14:09.991207 0MB downloaded in 0.30s (0.15MB/s)
86 22:14:09.991355 end: 1.3.1 http-download (duration 00:00:00) [common]
88 22:14:09.991585 end: 1.3 download-retry (duration 00:00:00) [common]
89 22:14:09.991671 start: 1.4 download-retry (timeout 00:09:59) [common]
90 22:14:09.991755 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 22:14:09.991881 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1314-g1ab0ac1d7e2e3/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 22:14:09.991954 saving as /var/lib/lava/dispatcher/tmp/10597227/tftp-deploy-x8cwzr0n/modules/modules.tar
93 22:14:09.992015 total size: 8543056 (8MB)
94 22:14:09.992077 Using unxz to decompress xz
95 22:14:09.995763 progress 0% (0MB)
96 22:14:10.017682 progress 5% (0MB)
97 22:14:10.043431 progress 10% (0MB)
98 22:14:10.069476 progress 15% (1MB)
99 22:14:10.094536 progress 20% (1MB)
100 22:14:10.117802 progress 25% (2MB)
101 22:14:10.144826 progress 30% (2MB)
102 22:14:10.170337 progress 35% (2MB)
103 22:14:10.194940 progress 40% (3MB)
104 22:14:10.218931 progress 45% (3MB)
105 22:14:10.244089 progress 50% (4MB)
106 22:14:10.267793 progress 55% (4MB)
107 22:14:10.292530 progress 60% (4MB)
108 22:14:10.317786 progress 65% (5MB)
109 22:14:10.342430 progress 70% (5MB)
110 22:14:10.365892 progress 75% (6MB)
111 22:14:10.390036 progress 80% (6MB)
112 22:14:10.414763 progress 85% (6MB)
113 22:14:10.443855 progress 90% (7MB)
114 22:14:10.469203 progress 95% (7MB)
115 22:14:10.493546 progress 100% (8MB)
116 22:14:10.499403 8MB downloaded in 0.51s (16.06MB/s)
117 22:14:10.499696 end: 1.4.1 http-download (duration 00:00:01) [common]
119 22:14:10.499954 end: 1.4 download-retry (duration 00:00:01) [common]
120 22:14:10.500049 start: 1.5 prepare-tftp-overlay (timeout 00:09:58) [common]
121 22:14:10.500144 start: 1.5.1 extract-nfsrootfs (timeout 00:09:58) [common]
122 22:14:10.500224 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 22:14:10.500305 start: 1.5.2 lava-overlay (timeout 00:09:58) [common]
124 22:14:10.500523 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/10597227/lava-overlay-msri9rw_
125 22:14:10.500649 makedir: /var/lib/lava/dispatcher/tmp/10597227/lava-overlay-msri9rw_/lava-10597227/bin
126 22:14:10.500749 makedir: /var/lib/lava/dispatcher/tmp/10597227/lava-overlay-msri9rw_/lava-10597227/tests
127 22:14:10.500842 makedir: /var/lib/lava/dispatcher/tmp/10597227/lava-overlay-msri9rw_/lava-10597227/results
128 22:14:10.500976 Creating /var/lib/lava/dispatcher/tmp/10597227/lava-overlay-msri9rw_/lava-10597227/bin/lava-add-keys
129 22:14:10.501146 Creating /var/lib/lava/dispatcher/tmp/10597227/lava-overlay-msri9rw_/lava-10597227/bin/lava-add-sources
130 22:14:10.501274 Creating /var/lib/lava/dispatcher/tmp/10597227/lava-overlay-msri9rw_/lava-10597227/bin/lava-background-process-start
131 22:14:10.501399 Creating /var/lib/lava/dispatcher/tmp/10597227/lava-overlay-msri9rw_/lava-10597227/bin/lava-background-process-stop
132 22:14:10.501519 Creating /var/lib/lava/dispatcher/tmp/10597227/lava-overlay-msri9rw_/lava-10597227/bin/lava-common-functions
133 22:14:10.501638 Creating /var/lib/lava/dispatcher/tmp/10597227/lava-overlay-msri9rw_/lava-10597227/bin/lava-echo-ipv4
134 22:14:10.501757 Creating /var/lib/lava/dispatcher/tmp/10597227/lava-overlay-msri9rw_/lava-10597227/bin/lava-install-packages
135 22:14:10.501876 Creating /var/lib/lava/dispatcher/tmp/10597227/lava-overlay-msri9rw_/lava-10597227/bin/lava-installed-packages
136 22:14:10.501995 Creating /var/lib/lava/dispatcher/tmp/10597227/lava-overlay-msri9rw_/lava-10597227/bin/lava-os-build
137 22:14:10.502114 Creating /var/lib/lava/dispatcher/tmp/10597227/lava-overlay-msri9rw_/lava-10597227/bin/lava-probe-channel
138 22:14:10.502234 Creating /var/lib/lava/dispatcher/tmp/10597227/lava-overlay-msri9rw_/lava-10597227/bin/lava-probe-ip
139 22:14:10.502353 Creating /var/lib/lava/dispatcher/tmp/10597227/lava-overlay-msri9rw_/lava-10597227/bin/lava-target-ip
140 22:14:10.502471 Creating /var/lib/lava/dispatcher/tmp/10597227/lava-overlay-msri9rw_/lava-10597227/bin/lava-target-mac
141 22:14:10.502589 Creating /var/lib/lava/dispatcher/tmp/10597227/lava-overlay-msri9rw_/lava-10597227/bin/lava-target-storage
142 22:14:10.502711 Creating /var/lib/lava/dispatcher/tmp/10597227/lava-overlay-msri9rw_/lava-10597227/bin/lava-test-case
143 22:14:10.502840 Creating /var/lib/lava/dispatcher/tmp/10597227/lava-overlay-msri9rw_/lava-10597227/bin/lava-test-event
144 22:14:10.502990 Creating /var/lib/lava/dispatcher/tmp/10597227/lava-overlay-msri9rw_/lava-10597227/bin/lava-test-feedback
145 22:14:10.503109 Creating /var/lib/lava/dispatcher/tmp/10597227/lava-overlay-msri9rw_/lava-10597227/bin/lava-test-raise
146 22:14:10.503229 Creating /var/lib/lava/dispatcher/tmp/10597227/lava-overlay-msri9rw_/lava-10597227/bin/lava-test-reference
147 22:14:10.503347 Creating /var/lib/lava/dispatcher/tmp/10597227/lava-overlay-msri9rw_/lava-10597227/bin/lava-test-runner
148 22:14:10.503465 Creating /var/lib/lava/dispatcher/tmp/10597227/lava-overlay-msri9rw_/lava-10597227/bin/lava-test-set
149 22:14:10.503585 Creating /var/lib/lava/dispatcher/tmp/10597227/lava-overlay-msri9rw_/lava-10597227/bin/lava-test-shell
150 22:14:10.503707 Updating /var/lib/lava/dispatcher/tmp/10597227/lava-overlay-msri9rw_/lava-10597227/bin/lava-install-packages (oe)
151 22:14:10.503861 Updating /var/lib/lava/dispatcher/tmp/10597227/lava-overlay-msri9rw_/lava-10597227/bin/lava-installed-packages (oe)
152 22:14:10.503980 Creating /var/lib/lava/dispatcher/tmp/10597227/lava-overlay-msri9rw_/lava-10597227/environment
153 22:14:10.504081 LAVA metadata
154 22:14:10.504152 - LAVA_JOB_ID=10597227
155 22:14:10.504215 - LAVA_DISPATCHER_IP=192.168.201.1
156 22:14:10.504314 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:58) [common]
157 22:14:10.504378 skipped lava-vland-overlay
158 22:14:10.504450 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 22:14:10.504526 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:58) [common]
160 22:14:10.504586 skipped lava-multinode-overlay
161 22:14:10.504658 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 22:14:10.504738 start: 1.5.2.3 test-definition (timeout 00:09:58) [common]
163 22:14:10.504809 Loading test definitions
164 22:14:10.504896 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:58) [common]
165 22:14:10.504968 Using /lava-10597227 at stage 0
166 22:14:10.505249 uuid=10597227_1.5.2.3.1 testdef=None
167 22:14:10.505335 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 22:14:10.505418 start: 1.5.2.3.2 test-overlay (timeout 00:09:58) [common]
169 22:14:10.505908 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 22:14:10.506123 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:58) [common]
172 22:14:10.506700 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 22:14:10.506965 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:58) [common]
175 22:14:10.507537 runner path: /var/lib/lava/dispatcher/tmp/10597227/lava-overlay-msri9rw_/lava-10597227/0/tests/0_cros-ec test_uuid 10597227_1.5.2.3.1
176 22:14:10.507686 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 22:14:10.507889 Creating lava-test-runner.conf files
179 22:14:10.507951 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10597227/lava-overlay-msri9rw_/lava-10597227/0 for stage 0
180 22:14:10.508036 - 0_cros-ec
181 22:14:10.508128 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 22:14:10.508212 start: 1.5.2.4 compress-overlay (timeout 00:09:58) [common]
183 22:14:10.514656 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 22:14:10.514762 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:58) [common]
185 22:14:10.514868 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 22:14:10.514965 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 22:14:10.515054 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:58) [common]
188 22:14:11.460738 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 22:14:11.461117 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 22:14:11.461229 extracting modules file /var/lib/lava/dispatcher/tmp/10597227/tftp-deploy-x8cwzr0n/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10597227/extract-overlay-ramdisk-q4a6m5hi/ramdisk
191 22:14:11.671555 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 22:14:11.671723 start: 1.5.5 apply-overlay-tftp (timeout 00:09:57) [common]
193 22:14:11.671820 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10597227/compress-overlay-7geku0p0/overlay-1.5.2.4.tar.gz to ramdisk
194 22:14:11.671895 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10597227/compress-overlay-7geku0p0/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/10597227/extract-overlay-ramdisk-q4a6m5hi/ramdisk
195 22:14:11.678255 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 22:14:11.678371 start: 1.5.6 configure-preseed-file (timeout 00:09:57) [common]
197 22:14:11.678462 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 22:14:11.678554 start: 1.5.7 compress-ramdisk (timeout 00:09:57) [common]
199 22:14:11.678633 Building ramdisk /var/lib/lava/dispatcher/tmp/10597227/extract-overlay-ramdisk-q4a6m5hi/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/10597227/extract-overlay-ramdisk-q4a6m5hi/ramdisk
200 22:14:12.318421 >> 269476 blocks
201 22:14:17.025201 rename /var/lib/lava/dispatcher/tmp/10597227/extract-overlay-ramdisk-q4a6m5hi/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/10597227/tftp-deploy-x8cwzr0n/ramdisk/ramdisk.cpio.gz
202 22:14:17.025629 end: 1.5.7 compress-ramdisk (duration 00:00:05) [common]
203 22:14:17.025751 start: 1.5.8 prepare-kernel (timeout 00:09:52) [common]
204 22:14:17.025849 start: 1.5.8.1 prepare-fit (timeout 00:09:52) [common]
205 22:14:17.025956 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/10597227/tftp-deploy-x8cwzr0n/kernel/Image'
206 22:14:29.150445 Returned 0 in 12 seconds
207 22:14:29.251205 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/10597227/tftp-deploy-x8cwzr0n/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/10597227/tftp-deploy-x8cwzr0n/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/10597227/tftp-deploy-x8cwzr0n/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/10597227/tftp-deploy-x8cwzr0n/kernel/image.itb
208 22:14:29.919370 output: FIT description: Kernel Image image with one or more FDT blobs
209 22:14:29.919730 output: Created: Mon Jun 5 23:14:29 2023
210 22:14:29.919804 output: Image 0 (kernel-1)
211 22:14:29.919870 output: Description:
212 22:14:29.919933 output: Created: Mon Jun 5 23:14:29 2023
213 22:14:29.919995 output: Type: Kernel Image
214 22:14:29.920055 output: Compression: lzma compressed
215 22:14:29.920110 output: Data Size: 10082307 Bytes = 9846.00 KiB = 9.62 MiB
216 22:14:29.920168 output: Architecture: AArch64
217 22:14:29.920223 output: OS: Linux
218 22:14:29.920276 output: Load Address: 0x00000000
219 22:14:29.920329 output: Entry Point: 0x00000000
220 22:14:29.920384 output: Hash algo: crc32
221 22:14:29.920437 output: Hash value: c242daf7
222 22:14:29.920488 output: Image 1 (fdt-1)
223 22:14:29.920539 output: Description: mt8192-asurada-spherion-r0
224 22:14:29.920590 output: Created: Mon Jun 5 23:14:29 2023
225 22:14:29.920641 output: Type: Flat Device Tree
226 22:14:29.920692 output: Compression: uncompressed
227 22:14:29.920743 output: Data Size: 46924 Bytes = 45.82 KiB = 0.04 MiB
228 22:14:29.920795 output: Architecture: AArch64
229 22:14:29.920846 output: Hash algo: crc32
230 22:14:29.920897 output: Hash value: 1df858fa
231 22:14:29.920947 output: Image 2 (ramdisk-1)
232 22:14:29.920998 output: Description: unavailable
233 22:14:29.921048 output: Created: Mon Jun 5 23:14:29 2023
234 22:14:29.921099 output: Type: RAMDisk Image
235 22:14:29.921149 output: Compression: Unknown Compression
236 22:14:29.921200 output: Data Size: 47372346 Bytes = 46262.06 KiB = 45.18 MiB
237 22:14:29.921251 output: Architecture: AArch64
238 22:14:29.921301 output: OS: Linux
239 22:14:29.921351 output: Load Address: unavailable
240 22:14:29.921402 output: Entry Point: unavailable
241 22:14:29.921452 output: Hash algo: crc32
242 22:14:29.921503 output: Hash value: 364613ae
243 22:14:29.921553 output: Default Configuration: 'conf-1'
244 22:14:29.921603 output: Configuration 0 (conf-1)
245 22:14:29.921653 output: Description: mt8192-asurada-spherion-r0
246 22:14:29.921704 output: Kernel: kernel-1
247 22:14:29.921754 output: Init Ramdisk: ramdisk-1
248 22:14:29.921804 output: FDT: fdt-1
249 22:14:29.921854 output: Loadables: kernel-1
250 22:14:29.921905 output:
251 22:14:29.922099 end: 1.5.8.1 prepare-fit (duration 00:00:13) [common]
252 22:14:29.922196 end: 1.5.8 prepare-kernel (duration 00:00:13) [common]
253 22:14:29.922305 end: 1.5 prepare-tftp-overlay (duration 00:00:19) [common]
254 22:14:29.922398 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:39) [common]
255 22:14:29.922471 No LXC device requested
256 22:14:29.922546 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 22:14:29.922629 start: 1.7 deploy-device-env (timeout 00:09:39) [common]
258 22:14:29.922707 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 22:14:29.922771 Checking files for TFTP limit of 4294967296 bytes.
260 22:14:29.923324 end: 1 tftp-deploy (duration 00:00:21) [common]
261 22:14:29.923423 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 22:14:29.923509 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 22:14:29.923632 substitutions:
264 22:14:29.923696 - {DTB}: 10597227/tftp-deploy-x8cwzr0n/dtb/mt8192-asurada-spherion-r0.dtb
265 22:14:29.923757 - {INITRD}: 10597227/tftp-deploy-x8cwzr0n/ramdisk/ramdisk.cpio.gz
266 22:14:29.923814 - {KERNEL}: 10597227/tftp-deploy-x8cwzr0n/kernel/Image
267 22:14:29.923870 - {LAVA_MAC}: None
268 22:14:29.923924 - {PRESEED_CONFIG}: None
269 22:14:29.923977 - {PRESEED_LOCAL}: None
270 22:14:29.924030 - {RAMDISK}: 10597227/tftp-deploy-x8cwzr0n/ramdisk/ramdisk.cpio.gz
271 22:14:29.924084 - {ROOT_PART}: None
272 22:14:29.924136 - {ROOT}: None
273 22:14:29.924188 - {SERVER_IP}: 192.168.201.1
274 22:14:29.924240 - {TEE}: None
275 22:14:29.924293 Parsed boot commands:
276 22:14:29.924345 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 22:14:29.924510 Parsed boot commands: tftpboot 192.168.201.1 10597227/tftp-deploy-x8cwzr0n/kernel/image.itb 10597227/tftp-deploy-x8cwzr0n/kernel/cmdline
278 22:14:29.924595 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 22:14:29.924677 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 22:14:29.924768 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 22:14:29.924852 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 22:14:29.924924 Not connected, no need to disconnect.
283 22:14:29.924997 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 22:14:29.925075 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 22:14:29.925141 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost mt8192-asurada-spherion-r0-cbg-8'
286 22:14:29.928503 Setting prompt string to ['lava-test: # ']
287 22:14:29.928830 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 22:14:29.928935 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 22:14:29.929029 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 22:14:29.929121 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 22:14:29.929367 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=reboot'
292 22:14:35.063506 >> Command sent successfully.
293 22:14:35.066361 Returned 0 in 5 seconds
294 22:14:35.166754 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 22:14:35.167371 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 22:14:35.167476 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 22:14:35.167562 Setting prompt string to 'Starting depthcharge on Spherion...'
299 22:14:35.167629 Changing prompt to 'Starting depthcharge on Spherion...'
300 22:14:35.167701 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 22:14:35.167945 [Enter `^Ec?' for help]
302 22:14:35.339084
303 22:14:35.339251
304 22:14:35.339348 F0: 102B 0000
305 22:14:35.339439
306 22:14:35.339528 F3: 1001 0000 [0200]
307 22:14:35.339621
308 22:14:35.342697 F3: 1001 0000
309 22:14:35.342808
310 22:14:35.342917 F7: 102D 0000
311 22:14:35.342982
312 22:14:35.343043 F1: 0000 0000
313 22:14:35.343117
314 22:14:35.346307 V0: 0000 0000 [0001]
315 22:14:35.346391
316 22:14:35.346457 00: 0007 8000
317 22:14:35.346522
318 22:14:35.349941 01: 0000 0000
319 22:14:35.350027
320 22:14:35.350093 BP: 0C00 0209 [0000]
321 22:14:35.350154
322 22:14:35.353698 G0: 1182 0000
323 22:14:35.353806
324 22:14:35.353875 EC: 0000 0021 [4000]
325 22:14:35.353951
326 22:14:35.357784 S7: 0000 0000 [0000]
327 22:14:35.357886
328 22:14:35.357967 CC: 0000 0000 [0001]
329 22:14:35.358028
330 22:14:35.360890 T0: 0000 0040 [010F]
331 22:14:35.360976
332 22:14:35.361042 Jump to BL
333 22:14:35.361103
334 22:14:35.385590
335 22:14:35.385701
336 22:14:35.385771
337 22:14:35.392460 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 22:14:35.396543 ARM64: Exception handlers installed.
339 22:14:35.400072 ARM64: Testing exception
340 22:14:35.403464 ARM64: Done test exception
341 22:14:35.410858 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 22:14:35.421995 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 22:14:35.425972 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 22:14:35.436087 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 22:14:35.443074 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 22:14:35.453388 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 22:14:35.463049 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 22:14:35.469979 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 22:14:35.488311 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 22:14:35.491544 WDT: Last reset was cold boot
351 22:14:35.495082 SPI1(PAD0) initialized at 2873684 Hz
352 22:14:35.498586 SPI5(PAD0) initialized at 992727 Hz
353 22:14:35.501960 VBOOT: Loading verstage.
354 22:14:35.508268 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 22:14:35.511565 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 22:14:35.515347 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 22:14:35.518156 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 22:14:35.526075 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 22:14:35.532232 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 22:14:35.543042 read SPI 0x96554 0xa1eb: 4594 us, 9022 KB/s, 72.176 Mbps
361 22:14:35.543130
362 22:14:35.543217
363 22:14:35.553419 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 22:14:35.556514 ARM64: Exception handlers installed.
365 22:14:35.559815 ARM64: Testing exception
366 22:14:35.559927 ARM64: Done test exception
367 22:14:35.566631 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 22:14:35.570236 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 22:14:35.584542 Probing TPM: . done!
370 22:14:35.584653 TPM ready after 0 ms
371 22:14:35.590757 Connected to device vid:did:rid of 1ae0:0028:00
372 22:14:35.640005 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
373 22:14:35.640097 Initialized TPM device CR50 revision 0
374 22:14:35.651275 tlcl_send_startup: Startup return code is 0
375 22:14:35.651361 TPM: setup succeeded
376 22:14:35.662071 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 22:14:35.671455 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 22:14:35.682436 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 22:14:35.692692 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 22:14:35.695951 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 22:14:35.699899 in-header: 03 07 00 00 08 00 00 00
382 22:14:35.703305 in-data: aa e4 47 04 13 02 00 00
383 22:14:35.706709 Chrome EC: UHEPI supported
384 22:14:35.713926 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 22:14:35.717362 in-header: 03 9d 00 00 08 00 00 00
386 22:14:35.720767 in-data: 10 20 20 08 00 00 00 00
387 22:14:35.720837 Phase 1
388 22:14:35.727951 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 22:14:35.731729 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 22:14:35.739282 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 22:14:35.742496 Recovery requested (1009000e)
392 22:14:35.748335 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 22:14:35.753441 tlcl_extend: response is 0
394 22:14:35.761805 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 22:14:35.767058 tlcl_extend: response is 0
396 22:14:35.773672 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 22:14:35.795142 read SPI 0x210d4 0x2173b: 15146 us, 9046 KB/s, 72.368 Mbps
398 22:14:35.802382 BS: bootblock times (exec / console): total (unknown) / 149 ms
399 22:14:35.802487
400 22:14:35.802553
401 22:14:35.812770 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 22:14:35.816158 ARM64: Exception handlers installed.
403 22:14:35.816242 ARM64: Testing exception
404 22:14:35.819525 ARM64: Done test exception
405 22:14:35.840276 pmic_efuse_setting: Set efuses in 11 msecs
406 22:14:35.843743 pmwrap_interface_init: Select PMIF_VLD_RDY
407 22:14:35.850760 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 22:14:35.854600 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 22:14:35.858229 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 22:14:35.862100 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 22:14:35.868986 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 22:14:35.872693 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 22:14:35.879968 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 22:14:35.883197 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 22:14:35.886525 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 22:14:35.893370 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 22:14:35.897005 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 22:14:35.899944 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 22:14:35.907049 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 22:14:35.913524 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 22:14:35.916828 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 22:14:35.923136 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 22:14:35.930052 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 22:14:35.933237 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 22:14:35.940093 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 22:14:35.947011 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 22:14:35.950741 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 22:14:35.958225 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 22:14:35.961523 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 22:14:35.968541 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 22:14:35.972007 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 22:14:35.978410 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 22:14:35.985135 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 22:14:35.988319 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 22:14:35.994685 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 22:14:35.998676 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 22:14:36.005875 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 22:14:36.009462 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 22:14:36.013120 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 22:14:36.020570 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 22:14:36.024029 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 22:14:36.027934 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 22:14:36.035203 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 22:14:36.038625 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 22:14:36.041348 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 22:14:36.048200 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 22:14:36.051488 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 22:14:36.054832 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 22:14:36.061558 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 22:14:36.065028 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 22:14:36.068006 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 22:14:36.074747 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 22:14:36.078218 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 22:14:36.081401 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 22:14:36.088633 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 22:14:36.091184 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 22:14:36.094806 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 22:14:36.101471 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 22:14:36.111889 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 22:14:36.115008 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 22:14:36.124759 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 22:14:36.131292 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 22:14:36.137996 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 22:14:36.140926 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 22:14:36.144197 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 22:14:36.152752 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x0
467 22:14:36.159303 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 22:14:36.162695 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
469 22:14:36.165792 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 22:14:36.177288 [RTC]rtc_get_frequency_meter,154: input=15, output=794
471 22:14:36.180235 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
472 22:14:36.187113 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
473 22:14:36.190242 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
474 22:14:36.193435 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
475 22:14:36.197005 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
476 22:14:36.200671 ADC[4]: Raw value=897780 ID=7
477 22:14:36.203856 ADC[3]: Raw value=213070 ID=1
478 22:14:36.206968 RAM Code: 0x71
479 22:14:36.210608 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
480 22:14:36.213861 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
481 22:14:36.223674 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
482 22:14:36.230729 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
483 22:14:36.234049 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
484 22:14:36.237716 in-header: 03 07 00 00 08 00 00 00
485 22:14:36.240752 in-data: aa e4 47 04 13 02 00 00
486 22:14:36.244279 Chrome EC: UHEPI supported
487 22:14:36.251047 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
488 22:14:36.254882 in-header: 03 d5 00 00 08 00 00 00
489 22:14:36.254979 in-data: 98 20 60 08 00 00 00 00
490 22:14:36.258546 MRC: failed to locate region type 0.
491 22:14:36.265973 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
492 22:14:36.269613 DRAM-K: Running full calibration
493 22:14:36.275852 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
494 22:14:36.275937 header.status = 0x0
495 22:14:36.279157 header.version = 0x6 (expected: 0x6)
496 22:14:36.282901 header.size = 0xd00 (expected: 0xd00)
497 22:14:36.286760 header.flags = 0x0
498 22:14:36.292837 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
499 22:14:36.309388 read SPI 0x72590 0x1c583: 12502 us, 9286 KB/s, 74.288 Mbps
500 22:14:36.316183 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
501 22:14:36.319596 dram_init: ddr_geometry: 2
502 22:14:36.322703 [EMI] MDL number = 2
503 22:14:36.322787 [EMI] Get MDL freq = 0
504 22:14:36.326012 dram_init: ddr_type: 0
505 22:14:36.326096 is_discrete_lpddr4: 1
506 22:14:36.329226 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
507 22:14:36.329308
508 22:14:36.329374
509 22:14:36.332342 [Bian_co] ETT version 0.0.0.1
510 22:14:36.338951 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
511 22:14:36.339035
512 22:14:36.342563 dramc_set_vcore_voltage set vcore to 650000
513 22:14:36.345821 Read voltage for 800, 4
514 22:14:36.345905 Vio18 = 0
515 22:14:36.345971 Vcore = 650000
516 22:14:36.348866 Vdram = 0
517 22:14:36.348949 Vddq = 0
518 22:14:36.349015 Vmddr = 0
519 22:14:36.352167 dram_init: config_dvfs: 1
520 22:14:36.355505 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
521 22:14:36.362426 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
522 22:14:36.365363 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=9
523 22:14:36.368756 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=9
524 22:14:36.372158 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
525 22:14:36.378990 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
526 22:14:36.379074 MEM_TYPE=3, freq_sel=18
527 22:14:36.382216 sv_algorithm_assistance_LP4_1600
528 22:14:36.385497 ============ PULL DRAM RESETB DOWN ============
529 22:14:36.392192 ========== PULL DRAM RESETB DOWN end =========
530 22:14:36.395309 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
531 22:14:36.398623 ===================================
532 22:14:36.401698 LPDDR4 DRAM CONFIGURATION
533 22:14:36.405468 ===================================
534 22:14:36.405551 EX_ROW_EN[0] = 0x0
535 22:14:36.408668 EX_ROW_EN[1] = 0x0
536 22:14:36.408752 LP4Y_EN = 0x0
537 22:14:36.411628 WORK_FSP = 0x0
538 22:14:36.411711 WL = 0x2
539 22:14:36.415216 RL = 0x2
540 22:14:36.418224 BL = 0x2
541 22:14:36.418328 RPST = 0x0
542 22:14:36.422215 RD_PRE = 0x0
543 22:14:36.422299 WR_PRE = 0x1
544 22:14:36.425134 WR_PST = 0x0
545 22:14:36.425248 DBI_WR = 0x0
546 22:14:36.428247 DBI_RD = 0x0
547 22:14:36.428330 OTF = 0x1
548 22:14:36.432221 ===================================
549 22:14:36.435068 ===================================
550 22:14:36.438370 ANA top config
551 22:14:36.441954 ===================================
552 22:14:36.442038 DLL_ASYNC_EN = 0
553 22:14:36.445326 ALL_SLAVE_EN = 1
554 22:14:36.448713 NEW_RANK_MODE = 1
555 22:14:36.451663 DLL_IDLE_MODE = 1
556 22:14:36.451746 LP45_APHY_COMB_EN = 1
557 22:14:36.455109 TX_ODT_DIS = 1
558 22:14:36.458693 NEW_8X_MODE = 1
559 22:14:36.461774 ===================================
560 22:14:36.465013 ===================================
561 22:14:36.468279 data_rate = 1600
562 22:14:36.471710 CKR = 1
563 22:14:36.475096 DQ_P2S_RATIO = 8
564 22:14:36.475179 ===================================
565 22:14:36.478295 CA_P2S_RATIO = 8
566 22:14:36.481667 DQ_CA_OPEN = 0
567 22:14:36.485105 DQ_SEMI_OPEN = 0
568 22:14:36.488811 CA_SEMI_OPEN = 0
569 22:14:36.491790 CA_FULL_RATE = 0
570 22:14:36.491874 DQ_CKDIV4_EN = 1
571 22:14:36.495046 CA_CKDIV4_EN = 1
572 22:14:36.498167 CA_PREDIV_EN = 0
573 22:14:36.501931 PH8_DLY = 0
574 22:14:36.505023 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
575 22:14:36.508244 DQ_AAMCK_DIV = 4
576 22:14:36.508327 CA_AAMCK_DIV = 4
577 22:14:36.511970 CA_ADMCK_DIV = 4
578 22:14:36.515130 DQ_TRACK_CA_EN = 0
579 22:14:36.518809 CA_PICK = 800
580 22:14:36.523163 CA_MCKIO = 800
581 22:14:36.523247 MCKIO_SEMI = 0
582 22:14:36.526574 PLL_FREQ = 3068
583 22:14:36.530233 DQ_UI_PI_RATIO = 32
584 22:14:36.533812 CA_UI_PI_RATIO = 0
585 22:14:36.537289 ===================================
586 22:14:36.541480 ===================================
587 22:14:36.541566 memory_type:LPDDR4
588 22:14:36.544513 GP_NUM : 10
589 22:14:36.544597 SRAM_EN : 1
590 22:14:36.548449 MD32_EN : 0
591 22:14:36.551874 ===================================
592 22:14:36.551958 [ANA_INIT] >>>>>>>>>>>>>>
593 22:14:36.555992 <<<<<< [CONFIGURE PHASE]: ANA_TX
594 22:14:36.559886 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
595 22:14:36.563357 ===================================
596 22:14:36.567197 data_rate = 1600,PCW = 0X7600
597 22:14:36.570478 ===================================
598 22:14:36.570562 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
599 22:14:36.578312 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
600 22:14:36.581558 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
601 22:14:36.589096 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
602 22:14:36.593010 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
603 22:14:36.597066 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
604 22:14:36.597150 [ANA_INIT] flow start
605 22:14:36.599982 [ANA_INIT] PLL >>>>>>>>
606 22:14:36.600123 [ANA_INIT] PLL <<<<<<<<
607 22:14:36.603830 [ANA_INIT] MIDPI >>>>>>>>
608 22:14:36.607424 [ANA_INIT] MIDPI <<<<<<<<
609 22:14:36.607507 [ANA_INIT] DLL >>>>>>>>
610 22:14:36.610559 [ANA_INIT] flow end
611 22:14:36.614304 ============ LP4 DIFF to SE enter ============
612 22:14:36.617821 ============ LP4 DIFF to SE exit ============
613 22:14:36.621319 [ANA_INIT] <<<<<<<<<<<<<
614 22:14:36.624545 [Flow] Enable top DCM control >>>>>
615 22:14:36.628354 [Flow] Enable top DCM control <<<<<
616 22:14:36.632111 Enable DLL master slave shuffle
617 22:14:36.635692 ==============================================================
618 22:14:36.639294 Gating Mode config
619 22:14:36.642755 ==============================================================
620 22:14:36.645632 Config description:
621 22:14:36.655898 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
622 22:14:36.662076 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
623 22:14:36.665481 SELPH_MODE 0: By rank 1: By Phase
624 22:14:36.672134 ==============================================================
625 22:14:36.675367 GAT_TRACK_EN = 1
626 22:14:36.678744 RX_GATING_MODE = 2
627 22:14:36.682114 RX_GATING_TRACK_MODE = 2
628 22:14:36.682198 SELPH_MODE = 1
629 22:14:36.685398 PICG_EARLY_EN = 1
630 22:14:36.688600 VALID_LAT_VALUE = 1
631 22:14:36.695504 ==============================================================
632 22:14:36.698726 Enter into Gating configuration >>>>
633 22:14:36.701992 Exit from Gating configuration <<<<
634 22:14:36.705386 Enter into DVFS_PRE_config >>>>>
635 22:14:36.715642 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
636 22:14:36.718648 Exit from DVFS_PRE_config <<<<<
637 22:14:36.722017 Enter into PICG configuration >>>>
638 22:14:36.725249 Exit from PICG configuration <<<<
639 22:14:36.728751 [RX_INPUT] configuration >>>>>
640 22:14:36.732166 [RX_INPUT] configuration <<<<<
641 22:14:36.735548 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
642 22:14:36.742272 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
643 22:14:36.748503 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
644 22:14:36.755433 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
645 22:14:36.758613 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
646 22:14:36.765483 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
647 22:14:36.768747 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
648 22:14:36.775807 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
649 22:14:36.778833 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
650 22:14:36.781593 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
651 22:14:36.785163 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
652 22:14:36.792075 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
653 22:14:36.795096 ===================================
654 22:14:36.798372 LPDDR4 DRAM CONFIGURATION
655 22:14:36.801739 ===================================
656 22:14:36.801823 EX_ROW_EN[0] = 0x0
657 22:14:36.805209 EX_ROW_EN[1] = 0x0
658 22:14:36.805292 LP4Y_EN = 0x0
659 22:14:36.808650 WORK_FSP = 0x0
660 22:14:36.808734 WL = 0x2
661 22:14:36.812011 RL = 0x2
662 22:14:36.812095 BL = 0x2
663 22:14:36.815459 RPST = 0x0
664 22:14:36.815542 RD_PRE = 0x0
665 22:14:36.819300 WR_PRE = 0x1
666 22:14:36.819384 WR_PST = 0x0
667 22:14:36.822614 DBI_WR = 0x0
668 22:14:36.822697 DBI_RD = 0x0
669 22:14:36.826011 OTF = 0x1
670 22:14:36.829995 ===================================
671 22:14:36.833519 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
672 22:14:36.837192 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
673 22:14:36.841022 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
674 22:14:36.844600 ===================================
675 22:14:36.848062 LPDDR4 DRAM CONFIGURATION
676 22:14:36.848146 ===================================
677 22:14:36.851654 EX_ROW_EN[0] = 0x10
678 22:14:36.855797 EX_ROW_EN[1] = 0x0
679 22:14:36.855881 LP4Y_EN = 0x0
680 22:14:36.859784 WORK_FSP = 0x0
681 22:14:36.859893 WL = 0x2
682 22:14:36.859987 RL = 0x2
683 22:14:36.862322 BL = 0x2
684 22:14:36.862444 RPST = 0x0
685 22:14:36.866548 RD_PRE = 0x0
686 22:14:36.866657 WR_PRE = 0x1
687 22:14:36.869752 WR_PST = 0x0
688 22:14:36.869835 DBI_WR = 0x0
689 22:14:36.873235 DBI_RD = 0x0
690 22:14:36.873319 OTF = 0x1
691 22:14:36.877250 ===================================
692 22:14:36.883748 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
693 22:14:36.887763 nWR fixed to 40
694 22:14:36.891553 [ModeRegInit_LP4] CH0 RK0
695 22:14:36.891636 [ModeRegInit_LP4] CH0 RK1
696 22:14:36.895365 [ModeRegInit_LP4] CH1 RK0
697 22:14:36.895449 [ModeRegInit_LP4] CH1 RK1
698 22:14:36.899307 match AC timing 13
699 22:14:36.902480 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
700 22:14:36.905945 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
701 22:14:36.913274 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
702 22:14:36.916646 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
703 22:14:36.920450 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
704 22:14:36.924031 [EMI DOE] emi_dcm 0
705 22:14:36.927759 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
706 22:14:36.927843 ==
707 22:14:36.931528 Dram Type= 6, Freq= 0, CH_0, rank 0
708 22:14:36.935202 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
709 22:14:36.935286 ==
710 22:14:36.938594 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
711 22:14:36.945553 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
712 22:14:36.955663 [CA 0] Center 38 (7~69) winsize 63
713 22:14:36.959471 [CA 1] Center 37 (7~68) winsize 62
714 22:14:36.962806 [CA 2] Center 35 (5~66) winsize 62
715 22:14:36.966626 [CA 3] Center 35 (5~66) winsize 62
716 22:14:36.970501 [CA 4] Center 34 (4~65) winsize 62
717 22:14:36.973498 [CA 5] Center 34 (3~65) winsize 63
718 22:14:36.973582
719 22:14:36.977259 [CmdBusTrainingLP45] Vref(ca) range 1: 34
720 22:14:36.977343
721 22:14:36.981247 [CATrainingPosCal] consider 1 rank data
722 22:14:36.981330 u2DelayCellTimex100 = 270/100 ps
723 22:14:36.984494 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
724 22:14:36.988251 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
725 22:14:36.992111 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
726 22:14:36.995536 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
727 22:14:36.999773 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
728 22:14:37.003169 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
729 22:14:37.003253
730 22:14:37.006587 CA PerBit enable=1, Macro0, CA PI delay=34
731 22:14:37.010554
732 22:14:37.010638 [CBTSetCACLKResult] CA Dly = 34
733 22:14:37.014046 CS Dly: 6 (0~37)
734 22:14:37.014130 ==
735 22:14:37.017451 Dram Type= 6, Freq= 0, CH_0, rank 1
736 22:14:37.021274 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
737 22:14:37.021384 ==
738 22:14:37.025232 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
739 22:14:37.032003 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
740 22:14:37.041905 [CA 0] Center 38 (7~69) winsize 63
741 22:14:37.045472 [CA 1] Center 38 (7~69) winsize 63
742 22:14:37.049219 [CA 2] Center 35 (5~66) winsize 62
743 22:14:37.052671 [CA 3] Center 35 (5~66) winsize 62
744 22:14:37.056186 [CA 4] Center 34 (4~65) winsize 62
745 22:14:37.059846 [CA 5] Center 34 (4~65) winsize 62
746 22:14:37.059955
747 22:14:37.063171 [CmdBusTrainingLP45] Vref(ca) range 1: 34
748 22:14:37.063255
749 22:14:37.066435 [CATrainingPosCal] consider 2 rank data
750 22:14:37.069907 u2DelayCellTimex100 = 270/100 ps
751 22:14:37.073656 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
752 22:14:37.077638 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
753 22:14:37.081330 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
754 22:14:37.085196 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
755 22:14:37.088602 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
756 22:14:37.092469 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
757 22:14:37.092552
758 22:14:37.095850 CA PerBit enable=1, Macro0, CA PI delay=34
759 22:14:37.095933
760 22:14:37.099189 [CBTSetCACLKResult] CA Dly = 34
761 22:14:37.099273 CS Dly: 6 (0~38)
762 22:14:37.099339
763 22:14:37.102306 ----->DramcWriteLeveling(PI) begin...
764 22:14:37.102390 ==
765 22:14:37.105699 Dram Type= 6, Freq= 0, CH_0, rank 0
766 22:14:37.109053 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
767 22:14:37.112343 ==
768 22:14:37.112426 Write leveling (Byte 0): 32 => 32
769 22:14:37.115709 Write leveling (Byte 1): 31 => 31
770 22:14:37.119186 DramcWriteLeveling(PI) end<-----
771 22:14:37.119269
772 22:14:37.119335 ==
773 22:14:37.122472 Dram Type= 6, Freq= 0, CH_0, rank 0
774 22:14:37.129258 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
775 22:14:37.129342 ==
776 22:14:37.129408 [Gating] SW mode calibration
777 22:14:37.139032 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
778 22:14:37.142219 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
779 22:14:37.145968 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
780 22:14:37.152517 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
781 22:14:37.155805 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
782 22:14:37.159149 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
783 22:14:37.166026 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
784 22:14:37.169154 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
785 22:14:37.172375 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
786 22:14:37.179126 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
787 22:14:37.182726 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
788 22:14:37.185924 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
789 22:14:37.189790 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 22:14:37.197032 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 22:14:37.200438 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 22:14:37.203782 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 22:14:37.210462 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 22:14:37.214056 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 22:14:37.217211 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 22:14:37.220566 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 22:14:37.227389 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
798 22:14:37.230711 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
799 22:14:37.234159 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 22:14:37.240876 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 22:14:37.243977 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 22:14:37.247351 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 22:14:37.253590 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
804 22:14:37.257233 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 22:14:37.260505 0 9 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
806 22:14:37.266732 0 9 12 | B1->B0 | 2929 3333 | 0 0 | (0 0) (0 0)
807 22:14:37.270366 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
808 22:14:37.273823 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
809 22:14:37.280202 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
810 22:14:37.283657 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
811 22:14:37.287038 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
812 22:14:37.293854 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
813 22:14:37.296737 0 10 8 | B1->B0 | 3333 2f2f | 1 1 | (1 1) (1 1)
814 22:14:37.300174 0 10 12 | B1->B0 | 2e2e 2323 | 1 0 | (1 0) (1 0)
815 22:14:37.307169 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
816 22:14:37.310292 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
817 22:14:37.313645 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
818 22:14:37.317029 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
819 22:14:37.323649 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
820 22:14:37.327084 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
821 22:14:37.330060 0 11 8 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
822 22:14:37.336906 0 11 12 | B1->B0 | 3636 3e3e | 0 0 | (0 0) (0 0)
823 22:14:37.340589 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
824 22:14:37.343623 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
825 22:14:37.350082 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
826 22:14:37.353474 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
827 22:14:37.356677 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
828 22:14:37.363552 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
829 22:14:37.366632 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
830 22:14:37.370224 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
831 22:14:37.376815 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
832 22:14:37.380055 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
833 22:14:37.383125 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
834 22:14:37.390068 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
835 22:14:37.393491 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
836 22:14:37.396548 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
837 22:14:37.403152 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 22:14:37.406182 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 22:14:37.409867 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 22:14:37.416570 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 22:14:37.420083 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 22:14:37.422671 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 22:14:37.429502 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 22:14:37.432689 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 22:14:37.436211 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
846 22:14:37.442980 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
847 22:14:37.443065 Total UI for P1: 0, mck2ui 16
848 22:14:37.449587 best dqsien dly found for B0: ( 0, 14, 8)
849 22:14:37.452808 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
850 22:14:37.456151 Total UI for P1: 0, mck2ui 16
851 22:14:37.459604 best dqsien dly found for B1: ( 0, 14, 10)
852 22:14:37.462544 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
853 22:14:37.466259 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
854 22:14:37.466343
855 22:14:37.469447 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
856 22:14:37.472668 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
857 22:14:37.475772 [Gating] SW calibration Done
858 22:14:37.475856 ==
859 22:14:37.479117 Dram Type= 6, Freq= 0, CH_0, rank 0
860 22:14:37.482689 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
861 22:14:37.485889 ==
862 22:14:37.485973 RX Vref Scan: 0
863 22:14:37.486039
864 22:14:37.489510 RX Vref 0 -> 0, step: 1
865 22:14:37.489593
866 22:14:37.492798 RX Delay -130 -> 252, step: 16
867 22:14:37.496215 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
868 22:14:37.499378 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
869 22:14:37.502420 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
870 22:14:37.506462 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
871 22:14:37.512500 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
872 22:14:37.515615 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
873 22:14:37.519138 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
874 22:14:37.522257 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
875 22:14:37.525478 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
876 22:14:37.532132 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
877 22:14:37.535612 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
878 22:14:37.539001 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
879 22:14:37.541903 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
880 22:14:37.545812 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
881 22:14:37.552085 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
882 22:14:37.555547 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
883 22:14:37.555649 ==
884 22:14:37.558944 Dram Type= 6, Freq= 0, CH_0, rank 0
885 22:14:37.561997 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
886 22:14:37.562089 ==
887 22:14:37.565564 DQS Delay:
888 22:14:37.565675 DQS0 = 0, DQS1 = 0
889 22:14:37.565755 DQM Delay:
890 22:14:37.568742 DQM0 = 81, DQM1 = 69
891 22:14:37.568853 DQ Delay:
892 22:14:37.571935 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =77
893 22:14:37.575189 DQ4 =85, DQ5 =69, DQ6 =85, DQ7 =93
894 22:14:37.578819 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =61
895 22:14:37.581869 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
896 22:14:37.581951
897 22:14:37.582017
898 22:14:37.582078 ==
899 22:14:37.585682 Dram Type= 6, Freq= 0, CH_0, rank 0
900 22:14:37.589407 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
901 22:14:37.592557 ==
902 22:14:37.592640
903 22:14:37.592704
904 22:14:37.592764 TX Vref Scan disable
905 22:14:37.596009 == TX Byte 0 ==
906 22:14:37.598966 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
907 22:14:37.602371 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
908 22:14:37.605835 == TX Byte 1 ==
909 22:14:37.609168 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
910 22:14:37.612917 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
911 22:14:37.615901 ==
912 22:14:37.616025 Dram Type= 6, Freq= 0, CH_0, rank 0
913 22:14:37.622398 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
914 22:14:37.622481 ==
915 22:14:37.634429 TX Vref=22, minBit 9, minWin=26, winSum=429
916 22:14:37.637835 TX Vref=24, minBit 1, minWin=27, winSum=437
917 22:14:37.641281 TX Vref=26, minBit 1, minWin=27, winSum=440
918 22:14:37.644699 TX Vref=28, minBit 10, minWin=26, winSum=440
919 22:14:37.647544 TX Vref=30, minBit 11, minWin=27, winSum=443
920 22:14:37.654292 TX Vref=32, minBit 1, minWin=27, winSum=439
921 22:14:37.657498 [TxChooseVref] Worse bit 11, Min win 27, Win sum 443, Final Vref 30
922 22:14:37.657581
923 22:14:37.660913 Final TX Range 1 Vref 30
924 22:14:37.661021
925 22:14:37.661121 ==
926 22:14:37.664185 Dram Type= 6, Freq= 0, CH_0, rank 0
927 22:14:37.667393 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
928 22:14:37.670619 ==
929 22:14:37.670729
930 22:14:37.670822
931 22:14:37.670925 TX Vref Scan disable
932 22:14:37.674700 == TX Byte 0 ==
933 22:14:37.677865 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
934 22:14:37.684659 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
935 22:14:37.684743 == TX Byte 1 ==
936 22:14:37.687792 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
937 22:14:37.694598 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
938 22:14:37.694681
939 22:14:37.694762 [DATLAT]
940 22:14:37.694825 Freq=800, CH0 RK0
941 22:14:37.694908
942 22:14:37.698104 DATLAT Default: 0xa
943 22:14:37.698188 0, 0xFFFF, sum = 0
944 22:14:37.701167 1, 0xFFFF, sum = 0
945 22:14:37.701254 2, 0xFFFF, sum = 0
946 22:14:37.704833 3, 0xFFFF, sum = 0
947 22:14:37.707627 4, 0xFFFF, sum = 0
948 22:14:37.707711 5, 0xFFFF, sum = 0
949 22:14:37.711003 6, 0xFFFF, sum = 0
950 22:14:37.711121 7, 0xFFFF, sum = 0
951 22:14:37.714365 8, 0xFFFF, sum = 0
952 22:14:37.714450 9, 0x0, sum = 1
953 22:14:37.717787 10, 0x0, sum = 2
954 22:14:37.717871 11, 0x0, sum = 3
955 22:14:37.717969 12, 0x0, sum = 4
956 22:14:37.720984 best_step = 10
957 22:14:37.721066
958 22:14:37.721131 ==
959 22:14:37.724750 Dram Type= 6, Freq= 0, CH_0, rank 0
960 22:14:37.727769 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
961 22:14:37.727853 ==
962 22:14:37.730981 RX Vref Scan: 1
963 22:14:37.731063
964 22:14:37.734365 Set Vref Range= 32 -> 127
965 22:14:37.734447
966 22:14:37.734514 RX Vref 32 -> 127, step: 1
967 22:14:37.734576
968 22:14:37.737501 RX Delay -111 -> 252, step: 8
969 22:14:37.737588
970 22:14:37.741229 Set Vref, RX VrefLevel [Byte0]: 32
971 22:14:37.744490 [Byte1]: 32
972 22:14:37.744576
973 22:14:37.747472 Set Vref, RX VrefLevel [Byte0]: 33
974 22:14:37.750812 [Byte1]: 33
975 22:14:37.755037
976 22:14:37.755147 Set Vref, RX VrefLevel [Byte0]: 34
977 22:14:37.758359 [Byte1]: 34
978 22:14:37.762950
979 22:14:37.763034 Set Vref, RX VrefLevel [Byte0]: 35
980 22:14:37.766225 [Byte1]: 35
981 22:14:37.770218
982 22:14:37.770301 Set Vref, RX VrefLevel [Byte0]: 36
983 22:14:37.773527 [Byte1]: 36
984 22:14:37.778199
985 22:14:37.778282 Set Vref, RX VrefLevel [Byte0]: 37
986 22:14:37.781362 [Byte1]: 37
987 22:14:37.785640
988 22:14:37.785723 Set Vref, RX VrefLevel [Byte0]: 38
989 22:14:37.788775 [Byte1]: 38
990 22:14:37.793497
991 22:14:37.793580 Set Vref, RX VrefLevel [Byte0]: 39
992 22:14:37.796540 [Byte1]: 39
993 22:14:37.801115
994 22:14:37.801197 Set Vref, RX VrefLevel [Byte0]: 40
995 22:14:37.804523 [Byte1]: 40
996 22:14:37.808750
997 22:14:37.808833 Set Vref, RX VrefLevel [Byte0]: 41
998 22:14:37.812192 [Byte1]: 41
999 22:14:37.816039
1000 22:14:37.816122 Set Vref, RX VrefLevel [Byte0]: 42
1001 22:14:37.819500 [Byte1]: 42
1002 22:14:37.824035
1003 22:14:37.824143 Set Vref, RX VrefLevel [Byte0]: 43
1004 22:14:37.827117 [Byte1]: 43
1005 22:14:37.831840
1006 22:14:37.831923 Set Vref, RX VrefLevel [Byte0]: 44
1007 22:14:37.835248 [Byte1]: 44
1008 22:14:37.838967
1009 22:14:37.839050 Set Vref, RX VrefLevel [Byte0]: 45
1010 22:14:37.843034 [Byte1]: 45
1011 22:14:37.847282
1012 22:14:37.847383 Set Vref, RX VrefLevel [Byte0]: 46
1013 22:14:37.850730 [Byte1]: 46
1014 22:14:37.854855
1015 22:14:37.854951 Set Vref, RX VrefLevel [Byte0]: 47
1016 22:14:37.858099 [Byte1]: 47
1017 22:14:37.862427
1018 22:14:37.862544 Set Vref, RX VrefLevel [Byte0]: 48
1019 22:14:37.865354 [Byte1]: 48
1020 22:14:37.869856
1021 22:14:37.873353 Set Vref, RX VrefLevel [Byte0]: 49
1022 22:14:37.873436 [Byte1]: 49
1023 22:14:37.877655
1024 22:14:37.877737 Set Vref, RX VrefLevel [Byte0]: 50
1025 22:14:37.880898 [Byte1]: 50
1026 22:14:37.885269
1027 22:14:37.885350 Set Vref, RX VrefLevel [Byte0]: 51
1028 22:14:37.888439 [Byte1]: 51
1029 22:14:37.892768
1030 22:14:37.892849 Set Vref, RX VrefLevel [Byte0]: 52
1031 22:14:37.895833 [Byte1]: 52
1032 22:14:37.900599
1033 22:14:37.900680 Set Vref, RX VrefLevel [Byte0]: 53
1034 22:14:37.903871 [Byte1]: 53
1035 22:14:37.908162
1036 22:14:37.908243 Set Vref, RX VrefLevel [Byte0]: 54
1037 22:14:37.911387 [Byte1]: 54
1038 22:14:37.915596
1039 22:14:37.915698 Set Vref, RX VrefLevel [Byte0]: 55
1040 22:14:37.918743 [Byte1]: 55
1041 22:14:37.923192
1042 22:14:37.923273 Set Vref, RX VrefLevel [Byte0]: 56
1043 22:14:37.926683 [Byte1]: 56
1044 22:14:37.930960
1045 22:14:37.931046 Set Vref, RX VrefLevel [Byte0]: 57
1046 22:14:37.935115 [Byte1]: 57
1047 22:14:37.938455
1048 22:14:37.938556 Set Vref, RX VrefLevel [Byte0]: 58
1049 22:14:37.941919 [Byte1]: 58
1050 22:14:37.946720
1051 22:14:37.946831 Set Vref, RX VrefLevel [Byte0]: 59
1052 22:14:37.949782 [Byte1]: 59
1053 22:14:37.953780
1054 22:14:37.953861 Set Vref, RX VrefLevel [Byte0]: 60
1055 22:14:37.957097 [Byte1]: 60
1056 22:14:37.961603
1057 22:14:37.961686 Set Vref, RX VrefLevel [Byte0]: 61
1058 22:14:37.964986 [Byte1]: 61
1059 22:14:37.969287
1060 22:14:37.969367 Set Vref, RX VrefLevel [Byte0]: 62
1061 22:14:37.972203 [Byte1]: 62
1062 22:14:37.976734
1063 22:14:37.976816 Set Vref, RX VrefLevel [Byte0]: 63
1064 22:14:37.980004 [Byte1]: 63
1065 22:14:37.984583
1066 22:14:37.984664 Set Vref, RX VrefLevel [Byte0]: 64
1067 22:14:37.987832 [Byte1]: 64
1068 22:14:37.992239
1069 22:14:37.992319 Set Vref, RX VrefLevel [Byte0]: 65
1070 22:14:37.995437 [Byte1]: 65
1071 22:14:37.999541
1072 22:14:37.999622 Set Vref, RX VrefLevel [Byte0]: 66
1073 22:14:38.003213 [Byte1]: 66
1074 22:14:38.007482
1075 22:14:38.007563 Set Vref, RX VrefLevel [Byte0]: 67
1076 22:14:38.010549 [Byte1]: 67
1077 22:14:38.015510
1078 22:14:38.015591 Set Vref, RX VrefLevel [Byte0]: 68
1079 22:14:38.018143 [Byte1]: 68
1080 22:14:38.022977
1081 22:14:38.023057 Set Vref, RX VrefLevel [Byte0]: 69
1082 22:14:38.025867 [Byte1]: 69
1083 22:14:38.030406
1084 22:14:38.030487 Set Vref, RX VrefLevel [Byte0]: 70
1085 22:14:38.033889 [Byte1]: 70
1086 22:14:38.037749
1087 22:14:38.037831 Set Vref, RX VrefLevel [Byte0]: 71
1088 22:14:38.041165 [Byte1]: 71
1089 22:14:38.045572
1090 22:14:38.045653 Set Vref, RX VrefLevel [Byte0]: 72
1091 22:14:38.048704 [Byte1]: 72
1092 22:14:38.053108
1093 22:14:38.053211 Set Vref, RX VrefLevel [Byte0]: 73
1094 22:14:38.056933 [Byte1]: 73
1095 22:14:38.061074
1096 22:14:38.061157 Set Vref, RX VrefLevel [Byte0]: 74
1097 22:14:38.063985 [Byte1]: 74
1098 22:14:38.068288
1099 22:14:38.068391 Set Vref, RX VrefLevel [Byte0]: 75
1100 22:14:38.071731 [Byte1]: 75
1101 22:14:38.076709
1102 22:14:38.076816 Set Vref, RX VrefLevel [Byte0]: 76
1103 22:14:38.079566 [Byte1]: 76
1104 22:14:38.084036
1105 22:14:38.084112 Set Vref, RX VrefLevel [Byte0]: 77
1106 22:14:38.086914 [Byte1]: 77
1107 22:14:38.092086
1108 22:14:38.092183 Set Vref, RX VrefLevel [Byte0]: 78
1109 22:14:38.094740 [Byte1]: 78
1110 22:14:38.099551
1111 22:14:38.099625 Set Vref, RX VrefLevel [Byte0]: 79
1112 22:14:38.102609 [Byte1]: 79
1113 22:14:38.106844
1114 22:14:38.106929 Set Vref, RX VrefLevel [Byte0]: 80
1115 22:14:38.109982 [Byte1]: 80
1116 22:14:38.114152
1117 22:14:38.114242 Final RX Vref Byte 0 = 60 to rank0
1118 22:14:38.117980 Final RX Vref Byte 1 = 58 to rank0
1119 22:14:38.121067 Final RX Vref Byte 0 = 60 to rank1
1120 22:14:38.124626 Final RX Vref Byte 1 = 58 to rank1==
1121 22:14:38.127687 Dram Type= 6, Freq= 0, CH_0, rank 0
1122 22:14:38.134708 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1123 22:14:38.134808 ==
1124 22:14:38.134930 DQS Delay:
1125 22:14:38.135023 DQS0 = 0, DQS1 = 0
1126 22:14:38.137592 DQM Delay:
1127 22:14:38.137701 DQM0 = 81, DQM1 = 68
1128 22:14:38.140968 DQ Delay:
1129 22:14:38.144231 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1130 22:14:38.144328 DQ4 =80, DQ5 =68, DQ6 =88, DQ7 =92
1131 22:14:38.147641 DQ8 =60, DQ9 =56, DQ10 =68, DQ11 =60
1132 22:14:38.154504 DQ12 =72, DQ13 =76, DQ14 =80, DQ15 =76
1133 22:14:38.154602
1134 22:14:38.154702
1135 22:14:38.161125 [DQSOSCAuto] RK0, (LSB)MR18= 0x2726, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 400 ps
1136 22:14:38.164251 CH0 RK0: MR19=606, MR18=2726
1137 22:14:38.171442 CH0_RK0: MR19=0x606, MR18=0x2726, DQSOSC=400, MR23=63, INC=92, DEC=61
1138 22:14:38.171566
1139 22:14:38.174640 ----->DramcWriteLeveling(PI) begin...
1140 22:14:38.174740 ==
1141 22:14:38.177572 Dram Type= 6, Freq= 0, CH_0, rank 1
1142 22:14:38.180929 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1143 22:14:38.181032 ==
1144 22:14:38.184532 Write leveling (Byte 0): 31 => 31
1145 22:14:38.187808 Write leveling (Byte 1): 30 => 30
1146 22:14:38.191248 DramcWriteLeveling(PI) end<-----
1147 22:14:38.191362
1148 22:14:38.191453 ==
1149 22:14:38.194495 Dram Type= 6, Freq= 0, CH_0, rank 1
1150 22:14:38.197666 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1151 22:14:38.197766 ==
1152 22:14:38.201075 [Gating] SW mode calibration
1153 22:14:38.207412 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1154 22:14:38.214409 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1155 22:14:38.217522 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1156 22:14:38.220712 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1157 22:14:38.227286 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1158 22:14:38.230667 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 22:14:38.233927 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 22:14:38.240939 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 22:14:38.243769 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 22:14:38.247031 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 22:14:38.253699 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 22:14:38.257347 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 22:14:38.260466 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 22:14:38.307971 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 22:14:38.308100 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 22:14:38.308379 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 22:14:38.308491 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 22:14:38.309001 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 22:14:38.309403 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 22:14:38.309499 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1173 22:14:38.309989 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1174 22:14:38.310287 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1175 22:14:38.311146 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 22:14:38.351987 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 22:14:38.352096 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 22:14:38.352392 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 22:14:38.352551 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 22:14:38.352979 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1181 22:14:38.353255 0 9 8 | B1->B0 | 2323 3030 | 0 1 | (0 0) (1 1)
1182 22:14:38.353349 0 9 12 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 1)
1183 22:14:38.353464 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1184 22:14:38.353738 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1185 22:14:38.354392 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1186 22:14:38.366140 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1187 22:14:38.366255 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1188 22:14:38.366833 0 10 4 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
1189 22:14:38.369475 0 10 8 | B1->B0 | 2f2f 2a2a | 0 0 | (0 1) (0 0)
1190 22:14:38.372641 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1191 22:14:38.376184 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 22:14:38.379760 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 22:14:38.386226 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1194 22:14:38.389609 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1195 22:14:38.393048 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1196 22:14:38.399368 0 11 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
1197 22:14:38.402371 0 11 8 | B1->B0 | 2f2f 3c3c | 0 0 | (0 0) (0 0)
1198 22:14:38.405803 0 11 12 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
1199 22:14:38.412531 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1200 22:14:38.415842 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1201 22:14:38.419486 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1202 22:14:38.425928 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1203 22:14:38.429510 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1204 22:14:38.432735 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1205 22:14:38.436384 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1206 22:14:38.443362 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 22:14:38.446487 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 22:14:38.450120 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 22:14:38.453392 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 22:14:38.460214 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 22:14:38.463594 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 22:14:38.466561 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 22:14:38.473561 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 22:14:38.476622 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 22:14:38.479916 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 22:14:38.486924 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 22:14:38.489829 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1218 22:14:38.493205 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1219 22:14:38.499676 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1220 22:14:38.502984 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1221 22:14:38.506414 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1222 22:14:38.509580 Total UI for P1: 0, mck2ui 16
1223 22:14:38.513153 best dqsien dly found for B0: ( 0, 14, 4)
1224 22:14:38.519588 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1225 22:14:38.519690 Total UI for P1: 0, mck2ui 16
1226 22:14:38.526159 best dqsien dly found for B1: ( 0, 14, 8)
1227 22:14:38.529917 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1228 22:14:38.532959 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1229 22:14:38.533057
1230 22:14:38.536132 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1231 22:14:38.539641 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1232 22:14:38.542677 [Gating] SW calibration Done
1233 22:14:38.542775 ==
1234 22:14:38.546428 Dram Type= 6, Freq= 0, CH_0, rank 1
1235 22:14:38.549712 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1236 22:14:38.549814 ==
1237 22:14:38.552825 RX Vref Scan: 0
1238 22:14:38.552927
1239 22:14:38.553014 RX Vref 0 -> 0, step: 1
1240 22:14:38.553109
1241 22:14:38.555879 RX Delay -130 -> 252, step: 16
1242 22:14:38.559675 iDelay=206, Bit 0, Center 77 (-50 ~ 205) 256
1243 22:14:38.565877 iDelay=206, Bit 1, Center 77 (-50 ~ 205) 256
1244 22:14:38.569366 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1245 22:14:38.572559 iDelay=206, Bit 3, Center 77 (-50 ~ 205) 256
1246 22:14:38.575985 iDelay=206, Bit 4, Center 77 (-50 ~ 205) 256
1247 22:14:38.582521 iDelay=206, Bit 5, Center 61 (-66 ~ 189) 256
1248 22:14:38.585817 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
1249 22:14:38.589384 iDelay=206, Bit 7, Center 85 (-34 ~ 205) 240
1250 22:14:38.592514 iDelay=206, Bit 8, Center 61 (-66 ~ 189) 256
1251 22:14:38.595918 iDelay=206, Bit 9, Center 53 (-66 ~ 173) 240
1252 22:14:38.602160 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1253 22:14:38.605140 iDelay=206, Bit 11, Center 61 (-66 ~ 189) 256
1254 22:14:38.608558 iDelay=206, Bit 12, Center 77 (-50 ~ 205) 256
1255 22:14:38.611862 iDelay=206, Bit 13, Center 77 (-50 ~ 205) 256
1256 22:14:38.615582 iDelay=206, Bit 14, Center 77 (-50 ~ 205) 256
1257 22:14:38.622321 iDelay=206, Bit 15, Center 77 (-50 ~ 205) 256
1258 22:14:38.622406 ==
1259 22:14:38.625493 Dram Type= 6, Freq= 0, CH_0, rank 1
1260 22:14:38.628946 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1261 22:14:38.629028 ==
1262 22:14:38.629093 DQS Delay:
1263 22:14:38.632291 DQS0 = 0, DQS1 = 0
1264 22:14:38.632372 DQM Delay:
1265 22:14:38.635476 DQM0 = 76, DQM1 = 69
1266 22:14:38.635558 DQ Delay:
1267 22:14:38.638645 DQ0 =77, DQ1 =77, DQ2 =69, DQ3 =77
1268 22:14:38.641911 DQ4 =77, DQ5 =61, DQ6 =85, DQ7 =85
1269 22:14:38.645273 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =61
1270 22:14:38.648781 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1271 22:14:38.648863
1272 22:14:38.648927
1273 22:14:38.648985 ==
1274 22:14:38.651917 Dram Type= 6, Freq= 0, CH_0, rank 1
1275 22:14:38.655555 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1276 22:14:38.659041 ==
1277 22:14:38.659122
1278 22:14:38.659185
1279 22:14:38.659243 TX Vref Scan disable
1280 22:14:38.662156 == TX Byte 0 ==
1281 22:14:38.665079 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1282 22:14:38.668590 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1283 22:14:38.672001 == TX Byte 1 ==
1284 22:14:38.675447 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1285 22:14:38.678905 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1286 22:14:38.681909 ==
1287 22:14:38.681989 Dram Type= 6, Freq= 0, CH_0, rank 1
1288 22:14:38.688246 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1289 22:14:38.688327 ==
1290 22:14:38.700664 TX Vref=22, minBit 0, minWin=27, winSum=435
1291 22:14:38.704046 TX Vref=24, minBit 0, minWin=27, winSum=440
1292 22:14:38.707527 TX Vref=26, minBit 11, minWin=26, winSum=441
1293 22:14:38.710298 TX Vref=28, minBit 2, minWin=27, winSum=442
1294 22:14:38.713747 TX Vref=30, minBit 1, minWin=27, winSum=442
1295 22:14:38.720808 TX Vref=32, minBit 1, minWin=27, winSum=444
1296 22:14:38.724201 [TxChooseVref] Worse bit 1, Min win 27, Win sum 444, Final Vref 32
1297 22:14:38.724281
1298 22:14:38.727089 Final TX Range 1 Vref 32
1299 22:14:38.727195
1300 22:14:38.727289 ==
1301 22:14:38.730518 Dram Type= 6, Freq= 0, CH_0, rank 1
1302 22:14:38.733731 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1303 22:14:38.733811 ==
1304 22:14:38.737000
1305 22:14:38.737079
1306 22:14:38.737140 TX Vref Scan disable
1307 22:14:38.740826 == TX Byte 0 ==
1308 22:14:38.743660 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1309 22:14:38.750660 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1310 22:14:38.750740 == TX Byte 1 ==
1311 22:14:38.753704 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1312 22:14:38.760223 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1313 22:14:38.760304
1314 22:14:38.760366 [DATLAT]
1315 22:14:38.760424 Freq=800, CH0 RK1
1316 22:14:38.760480
1317 22:14:38.763747 DATLAT Default: 0xa
1318 22:14:38.763841 0, 0xFFFF, sum = 0
1319 22:14:38.767031 1, 0xFFFF, sum = 0
1320 22:14:38.767111 2, 0xFFFF, sum = 0
1321 22:14:38.770512 3, 0xFFFF, sum = 0
1322 22:14:38.773479 4, 0xFFFF, sum = 0
1323 22:14:38.773559 5, 0xFFFF, sum = 0
1324 22:14:38.776977 6, 0xFFFF, sum = 0
1325 22:14:38.777057 7, 0xFFFF, sum = 0
1326 22:14:38.780074 8, 0x0, sum = 1
1327 22:14:38.780155 9, 0x0, sum = 2
1328 22:14:38.780218 10, 0x0, sum = 3
1329 22:14:38.783742 11, 0x0, sum = 4
1330 22:14:38.783834 best_step = 9
1331 22:14:38.783897
1332 22:14:38.783954 ==
1333 22:14:38.787172 Dram Type= 6, Freq= 0, CH_0, rank 1
1334 22:14:38.793769 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1335 22:14:38.793849 ==
1336 22:14:38.793913 RX Vref Scan: 0
1337 22:14:38.793971
1338 22:14:38.796937 RX Vref 0 -> 0, step: 1
1339 22:14:38.797018
1340 22:14:38.800098 RX Delay -111 -> 252, step: 8
1341 22:14:38.803341 iDelay=209, Bit 0, Center 76 (-39 ~ 192) 232
1342 22:14:38.806626 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
1343 22:14:38.813277 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
1344 22:14:38.816567 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
1345 22:14:38.820303 iDelay=209, Bit 4, Center 80 (-39 ~ 200) 240
1346 22:14:38.823091 iDelay=209, Bit 5, Center 64 (-55 ~ 184) 240
1347 22:14:38.826557 iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240
1348 22:14:38.833282 iDelay=209, Bit 7, Center 92 (-23 ~ 208) 232
1349 22:14:38.836600 iDelay=209, Bit 8, Center 64 (-55 ~ 184) 240
1350 22:14:38.840074 iDelay=209, Bit 9, Center 56 (-63 ~ 176) 240
1351 22:14:38.843284 iDelay=209, Bit 10, Center 72 (-47 ~ 192) 240
1352 22:14:38.849543 iDelay=209, Bit 11, Center 64 (-55 ~ 184) 240
1353 22:14:38.852908 iDelay=209, Bit 12, Center 80 (-39 ~ 200) 240
1354 22:14:38.856193 iDelay=209, Bit 13, Center 76 (-39 ~ 192) 232
1355 22:14:38.860301 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
1356 22:14:38.862925 iDelay=209, Bit 15, Center 76 (-39 ~ 192) 232
1357 22:14:38.863010 ==
1358 22:14:38.866519 Dram Type= 6, Freq= 0, CH_0, rank 1
1359 22:14:38.873650 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1360 22:14:38.873732 ==
1361 22:14:38.873795 DQS Delay:
1362 22:14:38.876519 DQS0 = 0, DQS1 = 0
1363 22:14:38.876599 DQM Delay:
1364 22:14:38.879578 DQM0 = 79, DQM1 = 71
1365 22:14:38.879659 DQ Delay:
1366 22:14:38.882747 DQ0 =76, DQ1 =84, DQ2 =76, DQ3 =72
1367 22:14:38.886164 DQ4 =80, DQ5 =64, DQ6 =88, DQ7 =92
1368 22:14:38.889790 DQ8 =64, DQ9 =56, DQ10 =72, DQ11 =64
1369 22:14:38.892679 DQ12 =80, DQ13 =76, DQ14 =80, DQ15 =76
1370 22:14:38.892777
1371 22:14:38.892841
1372 22:14:38.899935 [DQSOSCAuto] RK1, (LSB)MR18= 0x451f, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 392 ps
1373 22:14:38.903153 CH0 RK1: MR19=606, MR18=451F
1374 22:14:38.909712 CH0_RK1: MR19=0x606, MR18=0x451F, DQSOSC=392, MR23=63, INC=96, DEC=64
1375 22:14:38.912964 [RxdqsGatingPostProcess] freq 800
1376 22:14:38.916245 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1377 22:14:38.919597 Pre-setting of DQS Precalculation
1378 22:14:38.926219 [DualRankRxdatlatCal] RK0: 10, RK1: 9, Final_Datlat 10
1379 22:14:38.926300 ==
1380 22:14:38.929626 Dram Type= 6, Freq= 0, CH_1, rank 0
1381 22:14:38.932993 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1382 22:14:38.933075 ==
1383 22:14:38.939649 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1384 22:14:38.945606 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1385 22:14:38.953520 [CA 0] Center 36 (6~66) winsize 61
1386 22:14:38.956717 [CA 1] Center 36 (6~67) winsize 62
1387 22:14:38.960064 [CA 2] Center 34 (5~64) winsize 60
1388 22:14:38.963380 [CA 3] Center 34 (4~64) winsize 61
1389 22:14:38.966725 [CA 4] Center 34 (4~64) winsize 61
1390 22:14:38.970266 [CA 5] Center 33 (3~64) winsize 62
1391 22:14:38.970344
1392 22:14:38.973609 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1393 22:14:38.973689
1394 22:14:38.976492 [CATrainingPosCal] consider 1 rank data
1395 22:14:38.980059 u2DelayCellTimex100 = 270/100 ps
1396 22:14:38.983467 CA0 delay=36 (6~66),Diff = 3 PI (21 cell)
1397 22:14:38.989880 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1398 22:14:38.993064 CA2 delay=34 (5~64),Diff = 1 PI (7 cell)
1399 22:14:38.996709 CA3 delay=34 (4~64),Diff = 1 PI (7 cell)
1400 22:14:38.999766 CA4 delay=34 (4~64),Diff = 1 PI (7 cell)
1401 22:14:39.003458 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1402 22:14:39.003539
1403 22:14:39.006411 CA PerBit enable=1, Macro0, CA PI delay=33
1404 22:14:39.006491
1405 22:14:39.009807 [CBTSetCACLKResult] CA Dly = 33
1406 22:14:39.012742 CS Dly: 5 (0~36)
1407 22:14:39.012823 ==
1408 22:14:39.016009 Dram Type= 6, Freq= 0, CH_1, rank 1
1409 22:14:39.019711 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1410 22:14:39.019792 ==
1411 22:14:39.025967 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1412 22:14:39.029127 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1413 22:14:39.039890 [CA 0] Center 36 (6~67) winsize 62
1414 22:14:39.043244 [CA 1] Center 36 (6~67) winsize 62
1415 22:14:39.046812 [CA 2] Center 34 (4~65) winsize 62
1416 22:14:39.049946 [CA 3] Center 33 (3~64) winsize 62
1417 22:14:39.053248 [CA 4] Center 34 (4~65) winsize 62
1418 22:14:39.056122 [CA 5] Center 33 (3~64) winsize 62
1419 22:14:39.056203
1420 22:14:39.059465 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1421 22:14:39.059545
1422 22:14:39.063226 [CATrainingPosCal] consider 2 rank data
1423 22:14:39.065964 u2DelayCellTimex100 = 270/100 ps
1424 22:14:39.069339 CA0 delay=36 (6~66),Diff = 3 PI (21 cell)
1425 22:14:39.076198 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1426 22:14:39.079486 CA2 delay=34 (5~64),Diff = 1 PI (7 cell)
1427 22:14:39.083153 CA3 delay=34 (4~64),Diff = 1 PI (7 cell)
1428 22:14:39.086918 CA4 delay=34 (4~64),Diff = 1 PI (7 cell)
1429 22:14:39.090874 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1430 22:14:39.090969
1431 22:14:39.094393 CA PerBit enable=1, Macro0, CA PI delay=33
1432 22:14:39.094504
1433 22:14:39.097859 [CBTSetCACLKResult] CA Dly = 33
1434 22:14:39.097971 CS Dly: 6 (0~38)
1435 22:14:39.098034
1436 22:14:39.101443 ----->DramcWriteLeveling(PI) begin...
1437 22:14:39.101524 ==
1438 22:14:39.105261 Dram Type= 6, Freq= 0, CH_1, rank 0
1439 22:14:39.108737 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1440 22:14:39.108829 ==
1441 22:14:39.112601 Write leveling (Byte 0): 26 => 26
1442 22:14:39.116317 Write leveling (Byte 1): 33 => 33
1443 22:14:39.119904 DramcWriteLeveling(PI) end<-----
1444 22:14:39.120046
1445 22:14:39.120109 ==
1446 22:14:39.123132 Dram Type= 6, Freq= 0, CH_1, rank 0
1447 22:14:39.126359 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1448 22:14:39.126460 ==
1449 22:14:39.129754 [Gating] SW mode calibration
1450 22:14:39.136155 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1451 22:14:39.139728 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1452 22:14:39.146235 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1453 22:14:39.149520 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1454 22:14:39.152787 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1455 22:14:39.159543 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 22:14:39.162987 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 22:14:39.166145 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 22:14:39.172377 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 22:14:39.175749 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 22:14:39.179026 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 22:14:39.186089 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 22:14:39.189264 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 22:14:39.192630 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 22:14:39.199053 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 22:14:39.202527 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 22:14:39.205715 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 22:14:39.212623 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 22:14:39.215804 0 8 0 | B1->B0 | 2323 2323 | 0 1 | (0 0) (0 0)
1469 22:14:39.219037 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1470 22:14:39.226014 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1471 22:14:39.229216 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 22:14:39.232465 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 22:14:39.239125 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 22:14:39.242043 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 22:14:39.245431 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 22:14:39.252138 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 22:14:39.255547 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1478 22:14:39.258944 0 9 8 | B1->B0 | 2c2c 2828 | 0 0 | (0 0) (0 0)
1479 22:14:39.265607 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1480 22:14:39.268839 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1481 22:14:39.272178 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1482 22:14:39.278955 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1483 22:14:39.282226 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1484 22:14:39.285248 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1485 22:14:39.291926 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1486 22:14:39.295176 0 10 8 | B1->B0 | 2c2c 2e2e | 0 0 | (0 0) (1 0)
1487 22:14:39.298596 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 22:14:39.305290 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 22:14:39.308703 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 22:14:39.311769 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 22:14:39.314995 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1492 22:14:39.321942 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1493 22:14:39.325530 0 11 4 | B1->B0 | 2626 2424 | 0 0 | (0 0) (0 0)
1494 22:14:39.328725 0 11 8 | B1->B0 | 4343 3e3e | 0 0 | (0 0) (0 0)
1495 22:14:39.335851 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1496 22:14:39.338695 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1497 22:14:39.341991 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1498 22:14:39.348669 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1499 22:14:39.352061 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1500 22:14:39.354881 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1501 22:14:39.361466 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1502 22:14:39.365231 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1503 22:14:39.368331 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 22:14:39.375191 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 22:14:39.378577 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 22:14:39.381760 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 22:14:39.388543 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 22:14:39.391430 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 22:14:39.394715 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 22:14:39.401708 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 22:14:39.404892 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 22:14:39.408470 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 22:14:39.414775 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 22:14:39.417963 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1515 22:14:39.421605 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1516 22:14:39.428353 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1517 22:14:39.431430 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1518 22:14:39.434605 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1519 22:14:39.437897 Total UI for P1: 0, mck2ui 16
1520 22:14:39.441484 best dqsien dly found for B1: ( 0, 14, 4)
1521 22:14:39.448357 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1522 22:14:39.448439 Total UI for P1: 0, mck2ui 16
1523 22:14:39.451252 best dqsien dly found for B0: ( 0, 14, 8)
1524 22:14:39.458104 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1525 22:14:39.461463 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1526 22:14:39.461544
1527 22:14:39.464804 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1528 22:14:39.468102 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1529 22:14:39.471509 [Gating] SW calibration Done
1530 22:14:39.471590 ==
1531 22:14:39.474707 Dram Type= 6, Freq= 0, CH_1, rank 0
1532 22:14:39.478034 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1533 22:14:39.478116 ==
1534 22:14:39.481086 RX Vref Scan: 0
1535 22:14:39.481168
1536 22:14:39.481231 RX Vref 0 -> 0, step: 1
1537 22:14:39.481290
1538 22:14:39.484334 RX Delay -130 -> 252, step: 16
1539 22:14:39.487887 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
1540 22:14:39.494308 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1541 22:14:39.497488 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1542 22:14:39.501288 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1543 22:14:39.504287 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1544 22:14:39.507521 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1545 22:14:39.514308 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1546 22:14:39.517615 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1547 22:14:39.521051 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1548 22:14:39.524208 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1549 22:14:39.527875 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1550 22:14:39.534572 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1551 22:14:39.537710 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1552 22:14:39.541169 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1553 22:14:39.544140 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1554 22:14:39.547685 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1555 22:14:39.550629 ==
1556 22:14:39.554175 Dram Type= 6, Freq= 0, CH_1, rank 0
1557 22:14:39.557563 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1558 22:14:39.557645 ==
1559 22:14:39.557709 DQS Delay:
1560 22:14:39.560941 DQS0 = 0, DQS1 = 0
1561 22:14:39.561022 DQM Delay:
1562 22:14:39.563702 DQM0 = 80, DQM1 = 72
1563 22:14:39.563808 DQ Delay:
1564 22:14:39.567108 DQ0 =77, DQ1 =77, DQ2 =69, DQ3 =77
1565 22:14:39.570408 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1566 22:14:39.573755 DQ8 =61, DQ9 =69, DQ10 =69, DQ11 =69
1567 22:14:39.577108 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1568 22:14:39.577190
1569 22:14:39.577255
1570 22:14:39.577314 ==
1571 22:14:39.580395 Dram Type= 6, Freq= 0, CH_1, rank 0
1572 22:14:39.583683 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1573 22:14:39.583765 ==
1574 22:14:39.583830
1575 22:14:39.583889
1576 22:14:39.587126 TX Vref Scan disable
1577 22:14:39.590592 == TX Byte 0 ==
1578 22:14:39.593873 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1579 22:14:39.597250 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1580 22:14:39.600665 == TX Byte 1 ==
1581 22:14:39.603709 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1582 22:14:39.607272 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1583 22:14:39.607347 ==
1584 22:14:39.610574 Dram Type= 6, Freq= 0, CH_1, rank 0
1585 22:14:39.613698 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1586 22:14:39.617529 ==
1587 22:14:39.629174 TX Vref=22, minBit 11, minWin=26, winSum=443
1588 22:14:39.632854 TX Vref=24, minBit 11, minWin=27, winSum=452
1589 22:14:39.635856 TX Vref=26, minBit 13, minWin=27, winSum=452
1590 22:14:39.639279 TX Vref=28, minBit 13, minWin=27, winSum=456
1591 22:14:39.642399 TX Vref=30, minBit 8, minWin=27, winSum=455
1592 22:14:39.648989 TX Vref=32, minBit 13, minWin=27, winSum=453
1593 22:14:39.652259 [TxChooseVref] Worse bit 13, Min win 27, Win sum 456, Final Vref 28
1594 22:14:39.652362
1595 22:14:39.655546 Final TX Range 1 Vref 28
1596 22:14:39.655642
1597 22:14:39.655732 ==
1598 22:14:39.659170 Dram Type= 6, Freq= 0, CH_1, rank 0
1599 22:14:39.665992 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1600 22:14:39.666106 ==
1601 22:14:39.666196
1602 22:14:39.666301
1603 22:14:39.666390 TX Vref Scan disable
1604 22:14:39.669490 == TX Byte 0 ==
1605 22:14:39.672855 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1606 22:14:39.679388 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1607 22:14:39.679466 == TX Byte 1 ==
1608 22:14:39.682684 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1609 22:14:39.689257 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1610 22:14:39.689362
1611 22:14:39.689452 [DATLAT]
1612 22:14:39.689553 Freq=800, CH1 RK0
1613 22:14:39.689640
1614 22:14:39.692602 DATLAT Default: 0xa
1615 22:14:39.692697 0, 0xFFFF, sum = 0
1616 22:14:39.696489 1, 0xFFFF, sum = 0
1617 22:14:39.699555 2, 0xFFFF, sum = 0
1618 22:14:39.699661 3, 0xFFFF, sum = 0
1619 22:14:39.702719 4, 0xFFFF, sum = 0
1620 22:14:39.702817 5, 0xFFFF, sum = 0
1621 22:14:39.706085 6, 0xFFFF, sum = 0
1622 22:14:39.706156 7, 0xFFFF, sum = 0
1623 22:14:39.709464 8, 0xFFFF, sum = 0
1624 22:14:39.709571 9, 0x0, sum = 1
1625 22:14:39.712682 10, 0x0, sum = 2
1626 22:14:39.712790 11, 0x0, sum = 3
1627 22:14:39.712881 12, 0x0, sum = 4
1628 22:14:39.716032 best_step = 10
1629 22:14:39.716129
1630 22:14:39.716218 ==
1631 22:14:39.719302 Dram Type= 6, Freq= 0, CH_1, rank 0
1632 22:14:39.722504 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1633 22:14:39.722602 ==
1634 22:14:39.726050 RX Vref Scan: 1
1635 22:14:39.726149
1636 22:14:39.729368 Set Vref Range= 32 -> 127
1637 22:14:39.729467
1638 22:14:39.729558 RX Vref 32 -> 127, step: 1
1639 22:14:39.729647
1640 22:14:39.732415 RX Delay -111 -> 252, step: 8
1641 22:14:39.732508
1642 22:14:39.736056 Set Vref, RX VrefLevel [Byte0]: 32
1643 22:14:39.739100 [Byte1]: 32
1644 22:14:39.742374
1645 22:14:39.742471 Set Vref, RX VrefLevel [Byte0]: 33
1646 22:14:39.745593 [Byte1]: 33
1647 22:14:39.750279
1648 22:14:39.750381 Set Vref, RX VrefLevel [Byte0]: 34
1649 22:14:39.753294 [Byte1]: 34
1650 22:14:39.757963
1651 22:14:39.758043 Set Vref, RX VrefLevel [Byte0]: 35
1652 22:14:39.761279 [Byte1]: 35
1653 22:14:39.765532
1654 22:14:39.765637 Set Vref, RX VrefLevel [Byte0]: 36
1655 22:14:39.769187 [Byte1]: 36
1656 22:14:39.773501
1657 22:14:39.773608 Set Vref, RX VrefLevel [Byte0]: 37
1658 22:14:39.776359 [Byte1]: 37
1659 22:14:39.780795
1660 22:14:39.780898 Set Vref, RX VrefLevel [Byte0]: 38
1661 22:14:39.784065 [Byte1]: 38
1662 22:14:39.788659
1663 22:14:39.788763 Set Vref, RX VrefLevel [Byte0]: 39
1664 22:14:39.791825 [Byte1]: 39
1665 22:14:39.796137
1666 22:14:39.796237 Set Vref, RX VrefLevel [Byte0]: 40
1667 22:14:39.799576 [Byte1]: 40
1668 22:14:39.803495
1669 22:14:39.803569 Set Vref, RX VrefLevel [Byte0]: 41
1670 22:14:39.806945 [Byte1]: 41
1671 22:14:39.811369
1672 22:14:39.811439 Set Vref, RX VrefLevel [Byte0]: 42
1673 22:14:39.814825 [Byte1]: 42
1674 22:14:39.818943
1675 22:14:39.819024 Set Vref, RX VrefLevel [Byte0]: 43
1676 22:14:39.822164 [Byte1]: 43
1677 22:14:39.826372
1678 22:14:39.826469 Set Vref, RX VrefLevel [Byte0]: 44
1679 22:14:39.830105 [Byte1]: 44
1680 22:14:39.834518
1681 22:14:39.834616 Set Vref, RX VrefLevel [Byte0]: 45
1682 22:14:39.837580 [Byte1]: 45
1683 22:14:39.842168
1684 22:14:39.842276 Set Vref, RX VrefLevel [Byte0]: 46
1685 22:14:39.845167 [Byte1]: 46
1686 22:14:39.849526
1687 22:14:39.849620 Set Vref, RX VrefLevel [Byte0]: 47
1688 22:14:39.852661 [Byte1]: 47
1689 22:14:39.857072
1690 22:14:39.857170 Set Vref, RX VrefLevel [Byte0]: 48
1691 22:14:39.860491 [Byte1]: 48
1692 22:14:39.864995
1693 22:14:39.865097 Set Vref, RX VrefLevel [Byte0]: 49
1694 22:14:39.868049 [Byte1]: 49
1695 22:14:39.872454
1696 22:14:39.872530 Set Vref, RX VrefLevel [Byte0]: 50
1697 22:14:39.875993 [Byte1]: 50
1698 22:14:39.880139
1699 22:14:39.880244 Set Vref, RX VrefLevel [Byte0]: 51
1700 22:14:39.883516 [Byte1]: 51
1701 22:14:39.887710
1702 22:14:39.887797 Set Vref, RX VrefLevel [Byte0]: 52
1703 22:14:39.891118 [Byte1]: 52
1704 22:14:39.895461
1705 22:14:39.895539 Set Vref, RX VrefLevel [Byte0]: 53
1706 22:14:39.898709 [Byte1]: 53
1707 22:14:39.903149
1708 22:14:39.903225 Set Vref, RX VrefLevel [Byte0]: 54
1709 22:14:39.906528 [Byte1]: 54
1710 22:14:39.911287
1711 22:14:39.911365 Set Vref, RX VrefLevel [Byte0]: 55
1712 22:14:39.913842 [Byte1]: 55
1713 22:14:39.918340
1714 22:14:39.918440 Set Vref, RX VrefLevel [Byte0]: 56
1715 22:14:39.921641 [Byte1]: 56
1716 22:14:39.926247
1717 22:14:39.926346 Set Vref, RX VrefLevel [Byte0]: 57
1718 22:14:39.929273 [Byte1]: 57
1719 22:14:39.933921
1720 22:14:39.934021 Set Vref, RX VrefLevel [Byte0]: 58
1721 22:14:39.937251 [Byte1]: 58
1722 22:14:39.941326
1723 22:14:39.941436 Set Vref, RX VrefLevel [Byte0]: 59
1724 22:14:39.944393 [Byte1]: 59
1725 22:14:39.949109
1726 22:14:39.949210 Set Vref, RX VrefLevel [Byte0]: 60
1727 22:14:39.952301 [Byte1]: 60
1728 22:14:39.956513
1729 22:14:39.956615 Set Vref, RX VrefLevel [Byte0]: 61
1730 22:14:39.959732 [Byte1]: 61
1731 22:14:39.964134
1732 22:14:39.964238 Set Vref, RX VrefLevel [Byte0]: 62
1733 22:14:39.968062 [Byte1]: 62
1734 22:14:39.971885
1735 22:14:39.971983 Set Vref, RX VrefLevel [Byte0]: 63
1736 22:14:39.975192 [Byte1]: 63
1737 22:14:39.979495
1738 22:14:39.979576 Set Vref, RX VrefLevel [Byte0]: 64
1739 22:14:39.982626 [Byte1]: 64
1740 22:14:39.987501
1741 22:14:39.987593 Set Vref, RX VrefLevel [Byte0]: 65
1742 22:14:39.990583 [Byte1]: 65
1743 22:14:39.994678
1744 22:14:39.994759 Set Vref, RX VrefLevel [Byte0]: 66
1745 22:14:39.998076 [Byte1]: 66
1746 22:14:40.002460
1747 22:14:40.002541 Set Vref, RX VrefLevel [Byte0]: 67
1748 22:14:40.005763 [Byte1]: 67
1749 22:14:40.010402
1750 22:14:40.010483 Set Vref, RX VrefLevel [Byte0]: 68
1751 22:14:40.013521 [Byte1]: 68
1752 22:14:40.017746
1753 22:14:40.017827 Set Vref, RX VrefLevel [Byte0]: 69
1754 22:14:40.024062 [Byte1]: 69
1755 22:14:40.024143
1756 22:14:40.028082 Set Vref, RX VrefLevel [Byte0]: 70
1757 22:14:40.031116 [Byte1]: 70
1758 22:14:40.031198
1759 22:14:40.034634 Set Vref, RX VrefLevel [Byte0]: 71
1760 22:14:40.037639 [Byte1]: 71
1761 22:14:40.040717
1762 22:14:40.040798 Set Vref, RX VrefLevel [Byte0]: 72
1763 22:14:40.044297 [Byte1]: 72
1764 22:14:40.048625
1765 22:14:40.048705 Set Vref, RX VrefLevel [Byte0]: 73
1766 22:14:40.051708 [Byte1]: 73
1767 22:14:40.055896
1768 22:14:40.055978 Set Vref, RX VrefLevel [Byte0]: 74
1769 22:14:40.059097 [Byte1]: 74
1770 22:14:40.063804
1771 22:14:40.063885 Set Vref, RX VrefLevel [Byte0]: 75
1772 22:14:40.067201 [Byte1]: 75
1773 22:14:40.071258
1774 22:14:40.071340 Final RX Vref Byte 0 = 54 to rank0
1775 22:14:40.075062 Final RX Vref Byte 1 = 57 to rank0
1776 22:14:40.077962 Final RX Vref Byte 0 = 54 to rank1
1777 22:14:40.081181 Final RX Vref Byte 1 = 57 to rank1==
1778 22:14:40.084877 Dram Type= 6, Freq= 0, CH_1, rank 0
1779 22:14:40.091542 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1780 22:14:40.091625 ==
1781 22:14:40.091689 DQS Delay:
1782 22:14:40.091749 DQS0 = 0, DQS1 = 0
1783 22:14:40.094492 DQM Delay:
1784 22:14:40.094573 DQM0 = 80, DQM1 = 70
1785 22:14:40.097800 DQ Delay:
1786 22:14:40.100924 DQ0 =84, DQ1 =76, DQ2 =68, DQ3 =76
1787 22:14:40.104218 DQ4 =76, DQ5 =92, DQ6 =92, DQ7 =76
1788 22:14:40.107608 DQ8 =56, DQ9 =64, DQ10 =72, DQ11 =64
1789 22:14:40.110923 DQ12 =76, DQ13 =76, DQ14 =76, DQ15 =76
1790 22:14:40.111005
1791 22:14:40.111069
1792 22:14:40.117831 [DQSOSCAuto] RK0, (LSB)MR18= 0xd17, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 406 ps
1793 22:14:40.121299 CH1 RK0: MR19=606, MR18=D17
1794 22:14:40.127485 CH1_RK0: MR19=0x606, MR18=0xD17, DQSOSC=404, MR23=63, INC=90, DEC=60
1795 22:14:40.127567
1796 22:14:40.130856 ----->DramcWriteLeveling(PI) begin...
1797 22:14:40.130939 ==
1798 22:14:40.134644 Dram Type= 6, Freq= 0, CH_1, rank 1
1799 22:14:40.137797 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1800 22:14:40.137879 ==
1801 22:14:40.140967 Write leveling (Byte 0): 28 => 28
1802 22:14:40.144135 Write leveling (Byte 1): 32 => 32
1803 22:14:40.147671 DramcWriteLeveling(PI) end<-----
1804 22:14:40.147753
1805 22:14:40.147816 ==
1806 22:14:40.151062 Dram Type= 6, Freq= 0, CH_1, rank 1
1807 22:14:40.154295 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1808 22:14:40.154377 ==
1809 22:14:40.157671 [Gating] SW mode calibration
1810 22:14:40.163853 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1811 22:14:40.170716 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1812 22:14:40.173983 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1813 22:14:40.177455 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1814 22:14:40.184682 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1815 22:14:40.187189 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 22:14:40.190539 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 22:14:40.196706 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 22:14:40.200135 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 22:14:40.203577 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 22:14:40.210098 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 22:14:40.213597 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 22:14:40.217092 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 22:14:40.223504 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 22:14:40.226870 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 22:14:40.230265 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 22:14:40.236623 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 22:14:40.240480 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 22:14:40.243364 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 22:14:40.250060 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1830 22:14:40.253204 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 22:14:40.256484 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 22:14:40.263368 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 22:14:40.266696 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 22:14:40.269894 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 22:14:40.276668 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 22:14:40.280047 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 22:14:40.283404 0 9 4 | B1->B0 | 2323 2f2e | 0 1 | (0 0) (0 0)
1838 22:14:40.289914 0 9 8 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
1839 22:14:40.293319 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1840 22:14:40.296628 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1841 22:14:40.303168 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1842 22:14:40.306495 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1843 22:14:40.310123 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1844 22:14:40.316157 0 10 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
1845 22:14:40.320056 0 10 4 | B1->B0 | 2f2f 2c2c | 0 0 | (0 0) (0 1)
1846 22:14:40.322751 0 10 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1847 22:14:40.329610 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1848 22:14:40.332982 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1849 22:14:40.336669 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1850 22:14:40.343158 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1851 22:14:40.345954 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1852 22:14:40.349901 0 11 0 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
1853 22:14:40.355905 0 11 4 | B1->B0 | 2e2e 3b3b | 1 0 | (0 0) (0 0)
1854 22:14:40.359361 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1855 22:14:40.362571 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1856 22:14:40.369420 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1857 22:14:40.372331 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1858 22:14:40.375717 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1859 22:14:40.382361 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1860 22:14:40.386013 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1861 22:14:40.389090 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1862 22:14:40.392776 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1863 22:14:40.399541 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1864 22:14:40.402338 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1865 22:14:40.405689 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1866 22:14:40.412367 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1867 22:14:40.415695 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1868 22:14:40.419277 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1869 22:14:40.425652 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1870 22:14:40.429243 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1871 22:14:40.432480 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1872 22:14:40.438583 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1873 22:14:40.441981 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1874 22:14:40.445357 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1875 22:14:40.452526 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1876 22:14:40.455402 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1877 22:14:40.458649 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1878 22:14:40.465378 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1879 22:14:40.468487 Total UI for P1: 0, mck2ui 16
1880 22:14:40.472143 best dqsien dly found for B0: ( 0, 14, 4)
1881 22:14:40.475343 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1882 22:14:40.478707 Total UI for P1: 0, mck2ui 16
1883 22:14:40.481979 best dqsien dly found for B1: ( 0, 14, 8)
1884 22:14:40.485459 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1885 22:14:40.488377 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1886 22:14:40.488459
1887 22:14:40.491745 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1888 22:14:40.494958 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1889 22:14:40.498252 [Gating] SW calibration Done
1890 22:14:40.498334 ==
1891 22:14:40.501811 Dram Type= 6, Freq= 0, CH_1, rank 1
1892 22:14:40.508327 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1893 22:14:40.508409 ==
1894 22:14:40.508474 RX Vref Scan: 0
1895 22:14:40.508533
1896 22:14:40.511514 RX Vref 0 -> 0, step: 1
1897 22:14:40.511595
1898 22:14:40.515229 RX Delay -130 -> 252, step: 16
1899 22:14:40.518504 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1900 22:14:40.521647 iDelay=222, Bit 1, Center 69 (-50 ~ 189) 240
1901 22:14:40.525023 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1902 22:14:40.528058 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1903 22:14:40.534696 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1904 22:14:40.538065 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1905 22:14:40.541320 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1906 22:14:40.544816 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1907 22:14:40.548211 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1908 22:14:40.555007 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1909 22:14:40.558240 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1910 22:14:40.561795 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1911 22:14:40.564855 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1912 22:14:40.568141 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1913 22:14:40.574748 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1914 22:14:40.578057 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1915 22:14:40.578139 ==
1916 22:14:40.581709 Dram Type= 6, Freq= 0, CH_1, rank 1
1917 22:14:40.585015 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1918 22:14:40.585097 ==
1919 22:14:40.588205 DQS Delay:
1920 22:14:40.588286 DQS0 = 0, DQS1 = 0
1921 22:14:40.588349 DQM Delay:
1922 22:14:40.591361 DQM0 = 79, DQM1 = 74
1923 22:14:40.591442 DQ Delay:
1924 22:14:40.594654 DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =77
1925 22:14:40.598007 DQ4 =77, DQ5 =93, DQ6 =85, DQ7 =77
1926 22:14:40.601410 DQ8 =61, DQ9 =61, DQ10 =77, DQ11 =69
1927 22:14:40.604761 DQ12 =85, DQ13 =85, DQ14 =77, DQ15 =77
1928 22:14:40.604843
1929 22:14:40.604907
1930 22:14:40.604966 ==
1931 22:14:40.607682 Dram Type= 6, Freq= 0, CH_1, rank 1
1932 22:14:40.614430 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1933 22:14:40.614512 ==
1934 22:14:40.614576
1935 22:14:40.614635
1936 22:14:40.614691 TX Vref Scan disable
1937 22:14:40.618243 == TX Byte 0 ==
1938 22:14:40.621774 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1939 22:14:40.628534 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1940 22:14:40.628617 == TX Byte 1 ==
1941 22:14:40.631486 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1942 22:14:40.637929 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1943 22:14:40.638011 ==
1944 22:14:40.641433 Dram Type= 6, Freq= 0, CH_1, rank 1
1945 22:14:40.644858 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1946 22:14:40.644940 ==
1947 22:14:40.657791 TX Vref=22, minBit 11, minWin=27, winSum=450
1948 22:14:40.661193 TX Vref=24, minBit 0, minWin=28, winSum=452
1949 22:14:40.664009 TX Vref=26, minBit 0, minWin=28, winSum=456
1950 22:14:40.667287 TX Vref=28, minBit 3, minWin=28, winSum=457
1951 22:14:40.671270 TX Vref=30, minBit 4, minWin=28, winSum=457
1952 22:14:40.677659 TX Vref=32, minBit 8, minWin=28, winSum=460
1953 22:14:40.680786 [TxChooseVref] Worse bit 8, Min win 28, Win sum 460, Final Vref 32
1954 22:14:40.680906
1955 22:14:40.684125 Final TX Range 1 Vref 32
1956 22:14:40.684207
1957 22:14:40.684270 ==
1958 22:14:40.687131 Dram Type= 6, Freq= 0, CH_1, rank 1
1959 22:14:40.690950 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1960 22:14:40.693966 ==
1961 22:14:40.694047
1962 22:14:40.694110
1963 22:14:40.694169 TX Vref Scan disable
1964 22:14:40.697692 == TX Byte 0 ==
1965 22:14:40.700922 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1966 22:14:40.704560 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1967 22:14:40.707476 == TX Byte 1 ==
1968 22:14:40.711448 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1969 22:14:40.714228 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1970 22:14:40.717541
1971 22:14:40.717647 [DATLAT]
1972 22:14:40.717740 Freq=800, CH1 RK1
1973 22:14:40.717809
1974 22:14:40.720849 DATLAT Default: 0xa
1975 22:14:40.720930 0, 0xFFFF, sum = 0
1976 22:14:40.724220 1, 0xFFFF, sum = 0
1977 22:14:40.724302 2, 0xFFFF, sum = 0
1978 22:14:40.727391 3, 0xFFFF, sum = 0
1979 22:14:40.731334 4, 0xFFFF, sum = 0
1980 22:14:40.731445 5, 0xFFFF, sum = 0
1981 22:14:40.733926 6, 0xFFFF, sum = 0
1982 22:14:40.734008 7, 0xFFFF, sum = 0
1983 22:14:40.737533 8, 0xFFFF, sum = 0
1984 22:14:40.737616 9, 0x0, sum = 1
1985 22:14:40.737681 10, 0x0, sum = 2
1986 22:14:40.740709 11, 0x0, sum = 3
1987 22:14:40.740792 12, 0x0, sum = 4
1988 22:14:40.744073 best_step = 10
1989 22:14:40.744154
1990 22:14:40.744217 ==
1991 22:14:40.747581 Dram Type= 6, Freq= 0, CH_1, rank 1
1992 22:14:40.750942 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1993 22:14:40.751024 ==
1994 22:14:40.754198 RX Vref Scan: 0
1995 22:14:40.754279
1996 22:14:40.754342 RX Vref 0 -> 0, step: 1
1997 22:14:40.757204
1998 22:14:40.757285 RX Delay -111 -> 252, step: 8
1999 22:14:40.764278 iDelay=209, Bit 0, Center 80 (-39 ~ 200) 240
2000 22:14:40.767677 iDelay=209, Bit 1, Center 72 (-47 ~ 192) 240
2001 22:14:40.771078 iDelay=209, Bit 2, Center 64 (-55 ~ 184) 240
2002 22:14:40.774329 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
2003 22:14:40.777950 iDelay=209, Bit 4, Center 76 (-47 ~ 200) 248
2004 22:14:40.784127 iDelay=209, Bit 5, Center 88 (-31 ~ 208) 240
2005 22:14:40.787185 iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240
2006 22:14:40.790811 iDelay=209, Bit 7, Center 76 (-47 ~ 200) 248
2007 22:14:40.794010 iDelay=209, Bit 8, Center 60 (-63 ~ 184) 248
2008 22:14:40.800942 iDelay=209, Bit 9, Center 64 (-55 ~ 184) 240
2009 22:14:40.803931 iDelay=209, Bit 10, Center 76 (-47 ~ 200) 248
2010 22:14:40.807574 iDelay=209, Bit 11, Center 68 (-55 ~ 192) 248
2011 22:14:40.810823 iDelay=209, Bit 12, Center 80 (-39 ~ 200) 240
2012 22:14:40.813742 iDelay=209, Bit 13, Center 80 (-39 ~ 200) 240
2013 22:14:40.820529 iDelay=209, Bit 14, Center 76 (-47 ~ 200) 248
2014 22:14:40.824208 iDelay=209, Bit 15, Center 76 (-47 ~ 200) 248
2015 22:14:40.824290 ==
2016 22:14:40.827005 Dram Type= 6, Freq= 0, CH_1, rank 1
2017 22:14:40.830714 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2018 22:14:40.830821 ==
2019 22:14:40.834084 DQS Delay:
2020 22:14:40.834165 DQS0 = 0, DQS1 = 0
2021 22:14:40.834229 DQM Delay:
2022 22:14:40.837408 DQM0 = 77, DQM1 = 72
2023 22:14:40.837489 DQ Delay:
2024 22:14:40.840748 DQ0 =80, DQ1 =72, DQ2 =64, DQ3 =72
2025 22:14:40.843551 DQ4 =76, DQ5 =88, DQ6 =88, DQ7 =76
2026 22:14:40.847119 DQ8 =60, DQ9 =64, DQ10 =76, DQ11 =68
2027 22:14:40.850598 DQ12 =80, DQ13 =80, DQ14 =76, DQ15 =76
2028 22:14:40.850679
2029 22:14:40.850742
2030 22:14:40.860572 [DQSOSCAuto] RK1, (LSB)MR18= 0x2139, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 401 ps
2031 22:14:40.860692 CH1 RK1: MR19=606, MR18=2139
2032 22:14:40.867055 CH1_RK1: MR19=0x606, MR18=0x2139, DQSOSC=395, MR23=63, INC=94, DEC=63
2033 22:14:40.870452 [RxdqsGatingPostProcess] freq 800
2034 22:14:40.877116 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2035 22:14:40.880514 Pre-setting of DQS Precalculation
2036 22:14:40.883573 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2037 22:14:40.893554 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2038 22:14:40.899937 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2039 22:14:40.900019
2040 22:14:40.900082
2041 22:14:40.903171 [Calibration Summary] 1600 Mbps
2042 22:14:40.903247 CH 0, Rank 0
2043 22:14:40.906435 SW Impedance : PASS
2044 22:14:40.906513 DUTY Scan : NO K
2045 22:14:40.909876 ZQ Calibration : PASS
2046 22:14:40.913089 Jitter Meter : NO K
2047 22:14:40.913200 CBT Training : PASS
2048 22:14:40.916400 Write leveling : PASS
2049 22:14:40.919886 RX DQS gating : PASS
2050 22:14:40.919986 RX DQ/DQS(RDDQC) : PASS
2051 22:14:40.923262 TX DQ/DQS : PASS
2052 22:14:40.926524 RX DATLAT : PASS
2053 22:14:40.926623 RX DQ/DQS(Engine): PASS
2054 22:14:40.929798 TX OE : NO K
2055 22:14:40.929894 All Pass.
2056 22:14:40.929980
2057 22:14:40.933159 CH 0, Rank 1
2058 22:14:40.933266 SW Impedance : PASS
2059 22:14:40.936452 DUTY Scan : NO K
2060 22:14:40.936534 ZQ Calibration : PASS
2061 22:14:40.939789 Jitter Meter : NO K
2062 22:14:40.943209 CBT Training : PASS
2063 22:14:40.943289 Write leveling : PASS
2064 22:14:40.946416 RX DQS gating : PASS
2065 22:14:40.949690 RX DQ/DQS(RDDQC) : PASS
2066 22:14:40.949794 TX DQ/DQS : PASS
2067 22:14:40.952949 RX DATLAT : PASS
2068 22:14:40.956866 RX DQ/DQS(Engine): PASS
2069 22:14:40.956947 TX OE : NO K
2070 22:14:40.959538 All Pass.
2071 22:14:40.959618
2072 22:14:40.959681 CH 1, Rank 0
2073 22:14:40.962854 SW Impedance : PASS
2074 22:14:40.962948 DUTY Scan : NO K
2075 22:14:40.966090 ZQ Calibration : PASS
2076 22:14:40.969456 Jitter Meter : NO K
2077 22:14:40.969554 CBT Training : PASS
2078 22:14:40.972845 Write leveling : PASS
2079 22:14:40.976233 RX DQS gating : PASS
2080 22:14:40.976315 RX DQ/DQS(RDDQC) : PASS
2081 22:14:40.979639 TX DQ/DQS : PASS
2082 22:14:40.979721 RX DATLAT : PASS
2083 22:14:40.983213 RX DQ/DQS(Engine): PASS
2084 22:14:40.986011 TX OE : NO K
2085 22:14:40.986084 All Pass.
2086 22:14:40.986147
2087 22:14:40.986212 CH 1, Rank 1
2088 22:14:40.990024 SW Impedance : PASS
2089 22:14:40.992849 DUTY Scan : NO K
2090 22:14:40.992930 ZQ Calibration : PASS
2091 22:14:40.996131 Jitter Meter : NO K
2092 22:14:40.999919 CBT Training : PASS
2093 22:14:41.000007 Write leveling : PASS
2094 22:14:41.002972 RX DQS gating : PASS
2095 22:14:41.006000 RX DQ/DQS(RDDQC) : PASS
2096 22:14:41.006075 TX DQ/DQS : PASS
2097 22:14:41.010071 RX DATLAT : PASS
2098 22:14:41.012624 RX DQ/DQS(Engine): PASS
2099 22:14:41.012704 TX OE : NO K
2100 22:14:41.015819 All Pass.
2101 22:14:41.015891
2102 22:14:41.015958 DramC Write-DBI off
2103 22:14:41.019388 PER_BANK_REFRESH: Hybrid Mode
2104 22:14:41.019472 TX_TRACKING: ON
2105 22:14:41.022815 [GetDramInforAfterCalByMRR] Vendor 6.
2106 22:14:41.029634 [GetDramInforAfterCalByMRR] Revision 606.
2107 22:14:41.032463 [GetDramInforAfterCalByMRR] Revision 2 0.
2108 22:14:41.032543 MR0 0x3b3b
2109 22:14:41.032606 MR8 0x5151
2110 22:14:41.035812 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2111 22:14:41.035885
2112 22:14:41.039163 MR0 0x3b3b
2113 22:14:41.039243 MR8 0x5151
2114 22:14:41.042550 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2115 22:14:41.042621
2116 22:14:41.052646 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2117 22:14:41.055919 [FAST_K] Save calibration result to emmc
2118 22:14:41.059640 [FAST_K] Save calibration result to emmc
2119 22:14:41.062324 dram_init: config_dvfs: 1
2120 22:14:41.065786 dramc_set_vcore_voltage set vcore to 662500
2121 22:14:41.069342 Read voltage for 1200, 2
2122 22:14:41.069426 Vio18 = 0
2123 22:14:41.069495 Vcore = 662500
2124 22:14:41.072420 Vdram = 0
2125 22:14:41.072494 Vddq = 0
2126 22:14:41.072555 Vmddr = 0
2127 22:14:41.079271 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2128 22:14:41.082095 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2129 22:14:41.085543 MEM_TYPE=3, freq_sel=15
2130 22:14:41.088984 sv_algorithm_assistance_LP4_1600
2131 22:14:41.092261 ============ PULL DRAM RESETB DOWN ============
2132 22:14:41.095531 ========== PULL DRAM RESETB DOWN end =========
2133 22:14:41.102466 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2134 22:14:41.105485 ===================================
2135 22:14:41.108661 LPDDR4 DRAM CONFIGURATION
2136 22:14:41.112218 ===================================
2137 22:14:41.112299 EX_ROW_EN[0] = 0x0
2138 22:14:41.115784 EX_ROW_EN[1] = 0x0
2139 22:14:41.115864 LP4Y_EN = 0x0
2140 22:14:41.119033 WORK_FSP = 0x0
2141 22:14:41.119112 WL = 0x4
2142 22:14:41.122128 RL = 0x4
2143 22:14:41.122208 BL = 0x2
2144 22:14:41.125350 RPST = 0x0
2145 22:14:41.125430 RD_PRE = 0x0
2146 22:14:41.128722 WR_PRE = 0x1
2147 22:14:41.128801 WR_PST = 0x0
2148 22:14:41.132160 DBI_WR = 0x0
2149 22:14:41.132240 DBI_RD = 0x0
2150 22:14:41.135419 OTF = 0x1
2151 22:14:41.138762 ===================================
2152 22:14:41.142223 ===================================
2153 22:14:41.142303 ANA top config
2154 22:14:41.145373 ===================================
2155 22:14:41.148807 DLL_ASYNC_EN = 0
2156 22:14:41.152159 ALL_SLAVE_EN = 0
2157 22:14:41.155069 NEW_RANK_MODE = 1
2158 22:14:41.155176 DLL_IDLE_MODE = 1
2159 22:14:41.158656 LP45_APHY_COMB_EN = 1
2160 22:14:41.161972 TX_ODT_DIS = 1
2161 22:14:41.165676 NEW_8X_MODE = 1
2162 22:14:41.168634 ===================================
2163 22:14:41.171807 ===================================
2164 22:14:41.175523 data_rate = 2400
2165 22:14:41.175610 CKR = 1
2166 22:14:41.178253 DQ_P2S_RATIO = 8
2167 22:14:41.181712 ===================================
2168 22:14:41.185141 CA_P2S_RATIO = 8
2169 22:14:41.188544 DQ_CA_OPEN = 0
2170 22:14:41.192078 DQ_SEMI_OPEN = 0
2171 22:14:41.194869 CA_SEMI_OPEN = 0
2172 22:14:41.194964 CA_FULL_RATE = 0
2173 22:14:41.198203 DQ_CKDIV4_EN = 0
2174 22:14:41.201924 CA_CKDIV4_EN = 0
2175 22:14:41.204823 CA_PREDIV_EN = 0
2176 22:14:41.208370 PH8_DLY = 17
2177 22:14:41.211457 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2178 22:14:41.211538 DQ_AAMCK_DIV = 4
2179 22:14:41.215098 CA_AAMCK_DIV = 4
2180 22:14:41.218315 CA_ADMCK_DIV = 4
2181 22:14:41.221943 DQ_TRACK_CA_EN = 0
2182 22:14:41.225053 CA_PICK = 1200
2183 22:14:41.228171 CA_MCKIO = 1200
2184 22:14:41.231718 MCKIO_SEMI = 0
2185 22:14:41.235076 PLL_FREQ = 2366
2186 22:14:41.235157 DQ_UI_PI_RATIO = 32
2187 22:14:41.237889 CA_UI_PI_RATIO = 0
2188 22:14:41.241563 ===================================
2189 22:14:41.244509 ===================================
2190 22:14:41.248737 memory_type:LPDDR4
2191 22:14:41.251658 GP_NUM : 10
2192 22:14:41.251739 SRAM_EN : 1
2193 22:14:41.254524 MD32_EN : 0
2194 22:14:41.257905 ===================================
2195 22:14:41.261220 [ANA_INIT] >>>>>>>>>>>>>>
2196 22:14:41.261355 <<<<<< [CONFIGURE PHASE]: ANA_TX
2197 22:14:41.264415 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2198 22:14:41.267802 ===================================
2199 22:14:41.271607 data_rate = 2400,PCW = 0X5b00
2200 22:14:41.274787 ===================================
2201 22:14:41.277964 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2202 22:14:41.284870 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2203 22:14:41.291155 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2204 22:14:41.294453 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2205 22:14:41.297919 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2206 22:14:41.301279 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2207 22:14:41.304955 [ANA_INIT] flow start
2208 22:14:41.305037 [ANA_INIT] PLL >>>>>>>>
2209 22:14:41.307807 [ANA_INIT] PLL <<<<<<<<
2210 22:14:41.311344 [ANA_INIT] MIDPI >>>>>>>>
2211 22:14:41.311426 [ANA_INIT] MIDPI <<<<<<<<
2212 22:14:41.314645 [ANA_INIT] DLL >>>>>>>>
2213 22:14:41.317982 [ANA_INIT] DLL <<<<<<<<
2214 22:14:41.318064 [ANA_INIT] flow end
2215 22:14:41.324419 ============ LP4 DIFF to SE enter ============
2216 22:14:41.327558 ============ LP4 DIFF to SE exit ============
2217 22:14:41.331248 [ANA_INIT] <<<<<<<<<<<<<
2218 22:14:41.334431 [Flow] Enable top DCM control >>>>>
2219 22:14:41.337966 [Flow] Enable top DCM control <<<<<
2220 22:14:41.338053 Enable DLL master slave shuffle
2221 22:14:41.344391 ==============================================================
2222 22:14:41.347816 Gating Mode config
2223 22:14:41.351081 ==============================================================
2224 22:14:41.354290 Config description:
2225 22:14:41.364289 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2226 22:14:41.370820 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2227 22:14:41.374535 SELPH_MODE 0: By rank 1: By Phase
2228 22:14:41.380901 ==============================================================
2229 22:14:41.384155 GAT_TRACK_EN = 1
2230 22:14:41.387553 RX_GATING_MODE = 2
2231 22:14:41.390626 RX_GATING_TRACK_MODE = 2
2232 22:14:41.394029 SELPH_MODE = 1
2233 22:14:41.394106 PICG_EARLY_EN = 1
2234 22:14:41.397395 VALID_LAT_VALUE = 1
2235 22:14:41.403977 ==============================================================
2236 22:14:41.407375 Enter into Gating configuration >>>>
2237 22:14:41.410729 Exit from Gating configuration <<<<
2238 22:14:41.414113 Enter into DVFS_PRE_config >>>>>
2239 22:14:41.423926 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2240 22:14:41.427444 Exit from DVFS_PRE_config <<<<<
2241 22:14:41.430747 Enter into PICG configuration >>>>
2242 22:14:41.433981 Exit from PICG configuration <<<<
2243 22:14:41.437241 [RX_INPUT] configuration >>>>>
2244 22:14:41.440468 [RX_INPUT] configuration <<<<<
2245 22:14:41.443876 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2246 22:14:41.450572 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2247 22:14:41.457254 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2248 22:14:41.463463 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2249 22:14:41.470685 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2250 22:14:41.473923 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2251 22:14:41.480189 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2252 22:14:41.483543 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2253 22:14:41.487168 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2254 22:14:41.490475 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2255 22:14:41.497029 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2256 22:14:41.500314 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2257 22:14:41.503702 ===================================
2258 22:14:41.506618 LPDDR4 DRAM CONFIGURATION
2259 22:14:41.510040 ===================================
2260 22:14:41.510127 EX_ROW_EN[0] = 0x0
2261 22:14:41.513394 EX_ROW_EN[1] = 0x0
2262 22:14:41.513475 LP4Y_EN = 0x0
2263 22:14:41.516652 WORK_FSP = 0x0
2264 22:14:41.516734 WL = 0x4
2265 22:14:41.520159 RL = 0x4
2266 22:14:41.520242 BL = 0x2
2267 22:14:41.523577 RPST = 0x0
2268 22:14:41.523660 RD_PRE = 0x0
2269 22:14:41.526922 WR_PRE = 0x1
2270 22:14:41.529903 WR_PST = 0x0
2271 22:14:41.529989 DBI_WR = 0x0
2272 22:14:41.533865 DBI_RD = 0x0
2273 22:14:41.533950 OTF = 0x1
2274 22:14:41.537040 ===================================
2275 22:14:41.540129 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2276 22:14:41.543245 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2277 22:14:41.549959 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2278 22:14:41.552895 ===================================
2279 22:14:41.556496 LPDDR4 DRAM CONFIGURATION
2280 22:14:41.559842 ===================================
2281 22:14:41.559994 EX_ROW_EN[0] = 0x10
2282 22:14:41.563143 EX_ROW_EN[1] = 0x0
2283 22:14:41.563267 LP4Y_EN = 0x0
2284 22:14:41.566015 WORK_FSP = 0x0
2285 22:14:41.566128 WL = 0x4
2286 22:14:41.569928 RL = 0x4
2287 22:14:41.570012 BL = 0x2
2288 22:14:41.572628 RPST = 0x0
2289 22:14:41.572718 RD_PRE = 0x0
2290 22:14:41.576296 WR_PRE = 0x1
2291 22:14:41.579389 WR_PST = 0x0
2292 22:14:41.579486 DBI_WR = 0x0
2293 22:14:41.582661 DBI_RD = 0x0
2294 22:14:41.582755 OTF = 0x1
2295 22:14:41.585910 ===================================
2296 22:14:41.592948 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2297 22:14:41.593025 ==
2298 22:14:41.595812 Dram Type= 6, Freq= 0, CH_0, rank 0
2299 22:14:41.599349 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2300 22:14:41.599420 ==
2301 22:14:41.602511 [Duty_Offset_Calibration]
2302 22:14:41.602583 B0:2 B1:0 CA:3
2303 22:14:41.605816
2304 22:14:41.609315 [DutyScan_Calibration_Flow] k_type=0
2305 22:14:41.616981
2306 22:14:41.617070 ==CLK 0==
2307 22:14:41.620526 Final CLK duty delay cell = 0
2308 22:14:41.623412 [0] MAX Duty = 5031%(X100), DQS PI = 12
2309 22:14:41.626630 [0] MIN Duty = 4875%(X100), DQS PI = 58
2310 22:14:41.630049 [0] AVG Duty = 4953%(X100)
2311 22:14:41.630119
2312 22:14:41.633631 CH0 CLK Duty spec in!! Max-Min= 156%
2313 22:14:41.636913 [DutyScan_Calibration_Flow] ====Done====
2314 22:14:41.636997
2315 22:14:41.639818 [DutyScan_Calibration_Flow] k_type=1
2316 22:14:41.655403
2317 22:14:41.655475 ==DQS 0 ==
2318 22:14:41.658584 Final DQS duty delay cell = 0
2319 22:14:41.662115 [0] MAX Duty = 5062%(X100), DQS PI = 12
2320 22:14:41.665369 [0] MIN Duty = 4907%(X100), DQS PI = 2
2321 22:14:41.668482 [0] AVG Duty = 4984%(X100)
2322 22:14:41.668565
2323 22:14:41.668633 ==DQS 1 ==
2324 22:14:41.671944 Final DQS duty delay cell = -4
2325 22:14:41.675364 [-4] MAX Duty = 4969%(X100), DQS PI = 22
2326 22:14:41.678677 [-4] MIN Duty = 4875%(X100), DQS PI = 0
2327 22:14:41.681916 [-4] AVG Duty = 4922%(X100)
2328 22:14:41.681988
2329 22:14:41.685439 CH0 DQS 0 Duty spec in!! Max-Min= 155%
2330 22:14:41.685510
2331 22:14:41.688745 CH0 DQS 1 Duty spec in!! Max-Min= 94%
2332 22:14:41.692033 [DutyScan_Calibration_Flow] ====Done====
2333 22:14:41.692114
2334 22:14:41.694882 [DutyScan_Calibration_Flow] k_type=3
2335 22:14:41.712394
2336 22:14:41.712470 ==DQM 0 ==
2337 22:14:41.715230 Final DQM duty delay cell = 0
2338 22:14:41.718719 [0] MAX Duty = 5124%(X100), DQS PI = 28
2339 22:14:41.722100 [0] MIN Duty = 4876%(X100), DQS PI = 0
2340 22:14:41.722180 [0] AVG Duty = 5000%(X100)
2341 22:14:41.725445
2342 22:14:41.725518 ==DQM 1 ==
2343 22:14:41.728889 Final DQM duty delay cell = 0
2344 22:14:41.732206 [0] MAX Duty = 4938%(X100), DQS PI = 0
2345 22:14:41.735621 [0] MIN Duty = 4876%(X100), DQS PI = 6
2346 22:14:41.735693 [0] AVG Duty = 4907%(X100)
2347 22:14:41.738538
2348 22:14:41.741883 CH0 DQM 0 Duty spec in!! Max-Min= 248%
2349 22:14:41.741957
2350 22:14:41.745559 CH0 DQM 1 Duty spec in!! Max-Min= 62%
2351 22:14:41.748665 [DutyScan_Calibration_Flow] ====Done====
2352 22:14:41.748738
2353 22:14:41.751734 [DutyScan_Calibration_Flow] k_type=2
2354 22:14:41.767023
2355 22:14:41.767108 ==DQ 0 ==
2356 22:14:41.769982 Final DQ duty delay cell = -4
2357 22:14:41.773520 [-4] MAX Duty = 5031%(X100), DQS PI = 20
2358 22:14:41.776573 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2359 22:14:41.780013 [-4] AVG Duty = 4969%(X100)
2360 22:14:41.780088
2361 22:14:41.780171 ==DQ 1 ==
2362 22:14:41.783517 Final DQ duty delay cell = -4
2363 22:14:41.786532 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2364 22:14:41.789876 [-4] MIN Duty = 4876%(X100), DQS PI = 20
2365 22:14:41.793333 [-4] AVG Duty = 4938%(X100)
2366 22:14:41.793407
2367 22:14:41.796696 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2368 22:14:41.796775
2369 22:14:41.799998 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2370 22:14:41.803360 [DutyScan_Calibration_Flow] ====Done====
2371 22:14:41.803432 ==
2372 22:14:41.806767 Dram Type= 6, Freq= 0, CH_1, rank 0
2373 22:14:41.810068 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2374 22:14:41.810142 ==
2375 22:14:41.813183 [Duty_Offset_Calibration]
2376 22:14:41.813257 B0:1 B1:-2 CA:0
2377 22:14:41.813335
2378 22:14:41.816254 [DutyScan_Calibration_Flow] k_type=0
2379 22:14:41.827023
2380 22:14:41.827103 ==CLK 0==
2381 22:14:41.830471 Final CLK duty delay cell = 0
2382 22:14:41.833813 [0] MAX Duty = 5031%(X100), DQS PI = 16
2383 22:14:41.837009 [0] MIN Duty = 4875%(X100), DQS PI = 60
2384 22:14:41.840470 [0] AVG Duty = 4953%(X100)
2385 22:14:41.840545
2386 22:14:41.844395 CH1 CLK Duty spec in!! Max-Min= 156%
2387 22:14:41.847121 [DutyScan_Calibration_Flow] ====Done====
2388 22:14:41.847194
2389 22:14:41.851257 [DutyScan_Calibration_Flow] k_type=1
2390 22:14:41.865655
2391 22:14:41.865734 ==DQS 0 ==
2392 22:14:41.869474 Final DQS duty delay cell = -4
2393 22:14:41.872043 [-4] MAX Duty = 5031%(X100), DQS PI = 24
2394 22:14:41.875769 [-4] MIN Duty = 4907%(X100), DQS PI = 2
2395 22:14:41.879061 [-4] AVG Duty = 4969%(X100)
2396 22:14:41.879136
2397 22:14:41.879214 ==DQS 1 ==
2398 22:14:41.882227 Final DQS duty delay cell = 0
2399 22:14:41.885535 [0] MAX Duty = 5093%(X100), DQS PI = 0
2400 22:14:41.888590 [0] MIN Duty = 4875%(X100), DQS PI = 26
2401 22:14:41.892328 [0] AVG Duty = 4984%(X100)
2402 22:14:41.892404
2403 22:14:41.895688 CH1 DQS 0 Duty spec in!! Max-Min= 124%
2404 22:14:41.895766
2405 22:14:41.899100 CH1 DQS 1 Duty spec in!! Max-Min= 218%
2406 22:14:41.901840 [DutyScan_Calibration_Flow] ====Done====
2407 22:14:41.901911
2408 22:14:41.905559 [DutyScan_Calibration_Flow] k_type=3
2409 22:14:41.922341
2410 22:14:41.922422 ==DQM 0 ==
2411 22:14:41.925797 Final DQM duty delay cell = 0
2412 22:14:41.929228 [0] MAX Duty = 5031%(X100), DQS PI = 24
2413 22:14:41.932580 [0] MIN Duty = 4844%(X100), DQS PI = 56
2414 22:14:41.935980 [0] AVG Duty = 4937%(X100)
2415 22:14:41.936059
2416 22:14:41.936139 ==DQM 1 ==
2417 22:14:41.939129 Final DQM duty delay cell = 0
2418 22:14:41.942410 [0] MAX Duty = 5031%(X100), DQS PI = 36
2419 22:14:41.945676 [0] MIN Duty = 4907%(X100), DQS PI = 0
2420 22:14:41.949148 [0] AVG Duty = 4969%(X100)
2421 22:14:41.949220
2422 22:14:41.952591 CH1 DQM 0 Duty spec in!! Max-Min= 187%
2423 22:14:41.952663
2424 22:14:41.955492 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2425 22:14:41.959055 [DutyScan_Calibration_Flow] ====Done====
2426 22:14:41.959129
2427 22:14:41.962330 [DutyScan_Calibration_Flow] k_type=2
2428 22:14:41.978908
2429 22:14:41.978993 ==DQ 0 ==
2430 22:14:41.982447 Final DQ duty delay cell = 0
2431 22:14:41.985544 [0] MAX Duty = 5093%(X100), DQS PI = 20
2432 22:14:41.989154 [0] MIN Duty = 4938%(X100), DQS PI = 56
2433 22:14:41.989230 [0] AVG Duty = 5015%(X100)
2434 22:14:41.992134
2435 22:14:41.992207 ==DQ 1 ==
2436 22:14:41.995833 Final DQ duty delay cell = 0
2437 22:14:41.998970 [0] MAX Duty = 5125%(X100), DQS PI = 36
2438 22:14:42.002300 [0] MIN Duty = 4969%(X100), DQS PI = 26
2439 22:14:42.002374 [0] AVG Duty = 5047%(X100)
2440 22:14:42.002452
2441 22:14:42.006039 CH1 DQ 0 Duty spec in!! Max-Min= 155%
2442 22:14:42.008569
2443 22:14:42.012404 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2444 22:14:42.015192 [DutyScan_Calibration_Flow] ====Done====
2445 22:14:42.018769 nWR fixed to 30
2446 22:14:42.018881 [ModeRegInit_LP4] CH0 RK0
2447 22:14:42.022035 [ModeRegInit_LP4] CH0 RK1
2448 22:14:42.025820 [ModeRegInit_LP4] CH1 RK0
2449 22:14:42.028802 [ModeRegInit_LP4] CH1 RK1
2450 22:14:42.028880 match AC timing 7
2451 22:14:42.032071 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2452 22:14:42.038922 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2453 22:14:42.041689 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2454 22:14:42.048723 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2455 22:14:42.052015 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2456 22:14:42.052088 ==
2457 22:14:42.055546 Dram Type= 6, Freq= 0, CH_0, rank 0
2458 22:14:42.058914 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2459 22:14:42.058987 ==
2460 22:14:42.065028 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2461 22:14:42.071940 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2462 22:14:42.078721 [CA 0] Center 40 (10~71) winsize 62
2463 22:14:42.082022 [CA 1] Center 39 (9~70) winsize 62
2464 22:14:42.085700 [CA 2] Center 36 (6~66) winsize 61
2465 22:14:42.088783 [CA 3] Center 35 (5~66) winsize 62
2466 22:14:42.092002 [CA 4] Center 34 (4~65) winsize 62
2467 22:14:42.095311 [CA 5] Center 33 (3~64) winsize 62
2468 22:14:42.095392
2469 22:14:42.098752 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2470 22:14:42.098861
2471 22:14:42.101915 [CATrainingPosCal] consider 1 rank data
2472 22:14:42.105479 u2DelayCellTimex100 = 270/100 ps
2473 22:14:42.109102 CA0 delay=40 (10~71),Diff = 7 PI (33 cell)
2474 22:14:42.115665 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2475 22:14:42.118920 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2476 22:14:42.122252 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2477 22:14:42.125229 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2478 22:14:42.128351 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2479 22:14:42.128433
2480 22:14:42.131736 CA PerBit enable=1, Macro0, CA PI delay=33
2481 22:14:42.131821
2482 22:14:42.135465 [CBTSetCACLKResult] CA Dly = 33
2483 22:14:42.138357 CS Dly: 7 (0~38)
2484 22:14:42.138439 ==
2485 22:14:42.142094 Dram Type= 6, Freq= 0, CH_0, rank 1
2486 22:14:42.144867 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2487 22:14:42.144950 ==
2488 22:14:42.151893 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2489 22:14:42.155091 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2490 22:14:42.164781 [CA 0] Center 40 (10~70) winsize 61
2491 22:14:42.168451 [CA 1] Center 39 (9~70) winsize 62
2492 22:14:42.172096 [CA 2] Center 35 (5~66) winsize 62
2493 22:14:42.175184 [CA 3] Center 35 (5~66) winsize 62
2494 22:14:42.178570 [CA 4] Center 34 (4~65) winsize 62
2495 22:14:42.181777 [CA 5] Center 33 (3~64) winsize 62
2496 22:14:42.181858
2497 22:14:42.184956 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2498 22:14:42.185038
2499 22:14:42.188475 [CATrainingPosCal] consider 2 rank data
2500 22:14:42.191548 u2DelayCellTimex100 = 270/100 ps
2501 22:14:42.194834 CA0 delay=40 (10~70),Diff = 7 PI (33 cell)
2502 22:14:42.201514 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2503 22:14:42.204492 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2504 22:14:42.208206 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2505 22:14:42.211452 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2506 22:14:42.214969 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2507 22:14:42.215051
2508 22:14:42.218251 CA PerBit enable=1, Macro0, CA PI delay=33
2509 22:14:42.218334
2510 22:14:42.221680 [CBTSetCACLKResult] CA Dly = 33
2511 22:14:42.225022 CS Dly: 8 (0~40)
2512 22:14:42.225103
2513 22:14:42.227824 ----->DramcWriteLeveling(PI) begin...
2514 22:14:42.227907 ==
2515 22:14:42.231254 Dram Type= 6, Freq= 0, CH_0, rank 0
2516 22:14:42.234428 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2517 22:14:42.234525 ==
2518 22:14:42.237745 Write leveling (Byte 0): 32 => 32
2519 22:14:42.241217 Write leveling (Byte 1): 31 => 31
2520 22:14:42.244631 DramcWriteLeveling(PI) end<-----
2521 22:14:42.244705
2522 22:14:42.244767 ==
2523 22:14:42.247935 Dram Type= 6, Freq= 0, CH_0, rank 0
2524 22:14:42.251499 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2525 22:14:42.251579 ==
2526 22:14:42.254427 [Gating] SW mode calibration
2527 22:14:42.260848 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2528 22:14:42.267634 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2529 22:14:42.270901 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2530 22:14:42.274252 0 15 4 | B1->B0 | 2424 3434 | 1 0 | (1 1) (0 0)
2531 22:14:42.280852 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2532 22:14:42.283665 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2533 22:14:42.287115 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2534 22:14:42.293974 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2535 22:14:42.297031 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2536 22:14:42.300648 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2537 22:14:42.307051 1 0 0 | B1->B0 | 3434 2e2e | 0 0 | (0 0) (0 1)
2538 22:14:42.310150 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2539 22:14:42.313694 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2540 22:14:42.320070 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2541 22:14:42.323264 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2542 22:14:42.326529 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2543 22:14:42.333538 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2544 22:14:42.336361 1 0 28 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
2545 22:14:42.339908 1 1 0 | B1->B0 | 2929 3838 | 0 1 | (0 0) (1 1)
2546 22:14:42.346534 1 1 4 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
2547 22:14:42.349988 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2548 22:14:42.353229 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2549 22:14:42.359587 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2550 22:14:42.362955 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2551 22:14:42.366243 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2552 22:14:42.372446 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2553 22:14:42.376124 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2554 22:14:42.382729 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2555 22:14:42.386103 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2556 22:14:42.389408 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2557 22:14:42.395576 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2558 22:14:42.399163 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2559 22:14:42.402253 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2560 22:14:42.405641 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2561 22:14:42.412690 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2562 22:14:42.415475 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2563 22:14:42.419070 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2564 22:14:42.425635 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2565 22:14:42.428834 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2566 22:14:42.432548 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2567 22:14:42.438753 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2568 22:14:42.441997 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2569 22:14:42.446028 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2570 22:14:42.448840 Total UI for P1: 0, mck2ui 16
2571 22:14:42.452206 best dqsien dly found for B0: ( 1, 3, 28)
2572 22:14:42.458548 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2573 22:14:42.458632 Total UI for P1: 0, mck2ui 16
2574 22:14:42.465932 best dqsien dly found for B1: ( 1, 4, 0)
2575 22:14:42.468389 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2576 22:14:42.471770 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2577 22:14:42.471852
2578 22:14:42.475615 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2579 22:14:42.478392 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2580 22:14:42.481744 [Gating] SW calibration Done
2581 22:14:42.481825 ==
2582 22:14:42.485145 Dram Type= 6, Freq= 0, CH_0, rank 0
2583 22:14:42.488353 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2584 22:14:42.488436 ==
2585 22:14:42.491719 RX Vref Scan: 0
2586 22:14:42.491801
2587 22:14:42.491865 RX Vref 0 -> 0, step: 1
2588 22:14:42.491925
2589 22:14:42.495089 RX Delay -40 -> 252, step: 8
2590 22:14:42.501806 iDelay=200, Bit 0, Center 111 (32 ~ 191) 160
2591 22:14:42.505082 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
2592 22:14:42.508599 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2593 22:14:42.511786 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2594 22:14:42.514972 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2595 22:14:42.518192 iDelay=200, Bit 5, Center 99 (24 ~ 175) 152
2596 22:14:42.524958 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
2597 22:14:42.528464 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2598 22:14:42.531661 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2599 22:14:42.534956 iDelay=200, Bit 9, Center 87 (8 ~ 167) 160
2600 22:14:42.538039 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2601 22:14:42.544797 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
2602 22:14:42.548290 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2603 22:14:42.551764 iDelay=200, Bit 13, Center 107 (32 ~ 183) 152
2604 22:14:42.554588 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
2605 22:14:42.558502 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2606 22:14:42.561466 ==
2607 22:14:42.564740 Dram Type= 6, Freq= 0, CH_0, rank 0
2608 22:14:42.568019 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2609 22:14:42.568102 ==
2610 22:14:42.568166 DQS Delay:
2611 22:14:42.571336 DQS0 = 0, DQS1 = 0
2612 22:14:42.571418 DQM Delay:
2613 22:14:42.574715 DQM0 = 112, DQM1 = 103
2614 22:14:42.574799 DQ Delay:
2615 22:14:42.578024 DQ0 =111, DQ1 =111, DQ2 =115, DQ3 =107
2616 22:14:42.581418 DQ4 =115, DQ5 =99, DQ6 =119, DQ7 =123
2617 22:14:42.584851 DQ8 =95, DQ9 =87, DQ10 =103, DQ11 =95
2618 22:14:42.587890 DQ12 =111, DQ13 =107, DQ14 =115, DQ15 =111
2619 22:14:42.587971
2620 22:14:42.588035
2621 22:14:42.588094 ==
2622 22:14:42.591475 Dram Type= 6, Freq= 0, CH_0, rank 0
2623 22:14:42.597622 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2624 22:14:42.597705 ==
2625 22:14:42.597769
2626 22:14:42.597828
2627 22:14:42.597884 TX Vref Scan disable
2628 22:14:42.601088 == TX Byte 0 ==
2629 22:14:42.604569 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2630 22:14:42.611416 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2631 22:14:42.611497 == TX Byte 1 ==
2632 22:14:42.614553 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2633 22:14:42.621110 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2634 22:14:42.621192 ==
2635 22:14:42.624233 Dram Type= 6, Freq= 0, CH_0, rank 0
2636 22:14:42.627398 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2637 22:14:42.627480 ==
2638 22:14:42.639045 TX Vref=22, minBit 5, minWin=25, winSum=416
2639 22:14:42.642685 TX Vref=24, minBit 1, minWin=26, winSum=424
2640 22:14:42.645877 TX Vref=26, minBit 4, minWin=26, winSum=431
2641 22:14:42.649307 TX Vref=28, minBit 4, minWin=26, winSum=433
2642 22:14:42.652163 TX Vref=30, minBit 10, minWin=26, winSum=431
2643 22:14:42.658920 TX Vref=32, minBit 10, minWin=26, winSum=431
2644 22:14:42.662385 [TxChooseVref] Worse bit 4, Min win 26, Win sum 433, Final Vref 28
2645 22:14:42.662468
2646 22:14:42.665444 Final TX Range 1 Vref 28
2647 22:14:42.665599
2648 22:14:42.665662 ==
2649 22:14:42.668696 Dram Type= 6, Freq= 0, CH_0, rank 0
2650 22:14:42.672617 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2651 22:14:42.675398 ==
2652 22:14:42.675478
2653 22:14:42.675540
2654 22:14:42.675599 TX Vref Scan disable
2655 22:14:42.679227 == TX Byte 0 ==
2656 22:14:42.682628 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2657 22:14:42.685503 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2658 22:14:42.688914 == TX Byte 1 ==
2659 22:14:42.692174 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2660 22:14:42.695904 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2661 22:14:42.698651
2662 22:14:42.698759 [DATLAT]
2663 22:14:42.698871 Freq=1200, CH0 RK0
2664 22:14:42.698947
2665 22:14:42.702193 DATLAT Default: 0xd
2666 22:14:42.702273 0, 0xFFFF, sum = 0
2667 22:14:42.705643 1, 0xFFFF, sum = 0
2668 22:14:42.705724 2, 0xFFFF, sum = 0
2669 22:14:42.708995 3, 0xFFFF, sum = 0
2670 22:14:42.712333 4, 0xFFFF, sum = 0
2671 22:14:42.712415 5, 0xFFFF, sum = 0
2672 22:14:42.716046 6, 0xFFFF, sum = 0
2673 22:14:42.716127 7, 0xFFFF, sum = 0
2674 22:14:42.718707 8, 0xFFFF, sum = 0
2675 22:14:42.718790 9, 0xFFFF, sum = 0
2676 22:14:42.722266 10, 0xFFFF, sum = 0
2677 22:14:42.722348 11, 0xFFFF, sum = 0
2678 22:14:42.725558 12, 0x0, sum = 1
2679 22:14:42.725647 13, 0x0, sum = 2
2680 22:14:42.728635 14, 0x0, sum = 3
2681 22:14:42.728713 15, 0x0, sum = 4
2682 22:14:42.731809 best_step = 13
2683 22:14:42.731891
2684 22:14:42.731954 ==
2685 22:14:42.735745 Dram Type= 6, Freq= 0, CH_0, rank 0
2686 22:14:42.738767 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2687 22:14:42.738860 ==
2688 22:14:42.738923 RX Vref Scan: 1
2689 22:14:42.738983
2690 22:14:42.741911 Set Vref Range= 32 -> 127
2691 22:14:42.741981
2692 22:14:42.745167 RX Vref 32 -> 127, step: 1
2693 22:14:42.745239
2694 22:14:42.748760 RX Delay -37 -> 252, step: 4
2695 22:14:42.748847
2696 22:14:42.752100 Set Vref, RX VrefLevel [Byte0]: 32
2697 22:14:42.755547 [Byte1]: 32
2698 22:14:42.755628
2699 22:14:42.758960 Set Vref, RX VrefLevel [Byte0]: 33
2700 22:14:42.761800 [Byte1]: 33
2701 22:14:42.765611
2702 22:14:42.765687 Set Vref, RX VrefLevel [Byte0]: 34
2703 22:14:42.769201 [Byte1]: 34
2704 22:14:42.773591
2705 22:14:42.773676 Set Vref, RX VrefLevel [Byte0]: 35
2706 22:14:42.776665 [Byte1]: 35
2707 22:14:42.781831
2708 22:14:42.781909 Set Vref, RX VrefLevel [Byte0]: 36
2709 22:14:42.784636 [Byte1]: 36
2710 22:14:42.789681
2711 22:14:42.789766 Set Vref, RX VrefLevel [Byte0]: 37
2712 22:14:42.792975 [Byte1]: 37
2713 22:14:42.797438
2714 22:14:42.797510 Set Vref, RX VrefLevel [Byte0]: 38
2715 22:14:42.800704 [Byte1]: 38
2716 22:14:42.805787
2717 22:14:42.805859 Set Vref, RX VrefLevel [Byte0]: 39
2718 22:14:42.808930 [Byte1]: 39
2719 22:14:42.813769
2720 22:14:42.813837 Set Vref, RX VrefLevel [Byte0]: 40
2721 22:14:42.817032 [Byte1]: 40
2722 22:14:42.821685
2723 22:14:42.821766 Set Vref, RX VrefLevel [Byte0]: 41
2724 22:14:42.824877 [Byte1]: 41
2725 22:14:42.829485
2726 22:14:42.829559 Set Vref, RX VrefLevel [Byte0]: 42
2727 22:14:42.835950 [Byte1]: 42
2728 22:14:42.836033
2729 22:14:42.839648 Set Vref, RX VrefLevel [Byte0]: 43
2730 22:14:42.842924 [Byte1]: 43
2731 22:14:42.843000
2732 22:14:42.845876 Set Vref, RX VrefLevel [Byte0]: 44
2733 22:14:42.849520 [Byte1]: 44
2734 22:14:42.853830
2735 22:14:42.853912 Set Vref, RX VrefLevel [Byte0]: 45
2736 22:14:42.856893 [Byte1]: 45
2737 22:14:42.861480
2738 22:14:42.861560 Set Vref, RX VrefLevel [Byte0]: 46
2739 22:14:42.864821 [Byte1]: 46
2740 22:14:42.870510
2741 22:14:42.870591 Set Vref, RX VrefLevel [Byte0]: 47
2742 22:14:42.873185 [Byte1]: 47
2743 22:14:42.877574
2744 22:14:42.877654 Set Vref, RX VrefLevel [Byte0]: 48
2745 22:14:42.880914 [Byte1]: 48
2746 22:14:42.885895
2747 22:14:42.885976 Set Vref, RX VrefLevel [Byte0]: 49
2748 22:14:42.888712 [Byte1]: 49
2749 22:14:42.893663
2750 22:14:42.893758 Set Vref, RX VrefLevel [Byte0]: 50
2751 22:14:42.896863 [Byte1]: 50
2752 22:14:42.901859
2753 22:14:42.901940 Set Vref, RX VrefLevel [Byte0]: 51
2754 22:14:42.905318 [Byte1]: 51
2755 22:14:42.909890
2756 22:14:42.909974 Set Vref, RX VrefLevel [Byte0]: 52
2757 22:14:42.913136 [Byte1]: 52
2758 22:14:42.917896
2759 22:14:42.917977 Set Vref, RX VrefLevel [Byte0]: 53
2760 22:14:42.920672 [Byte1]: 53
2761 22:14:42.925856
2762 22:14:42.925937 Set Vref, RX VrefLevel [Byte0]: 54
2763 22:14:42.929260 [Byte1]: 54
2764 22:14:42.933466
2765 22:14:42.933547 Set Vref, RX VrefLevel [Byte0]: 55
2766 22:14:42.936848 [Byte1]: 55
2767 22:14:42.941965
2768 22:14:42.942047 Set Vref, RX VrefLevel [Byte0]: 56
2769 22:14:42.945251 [Byte1]: 56
2770 22:14:42.949418
2771 22:14:42.949499 Set Vref, RX VrefLevel [Byte0]: 57
2772 22:14:42.952973 [Byte1]: 57
2773 22:14:42.957766
2774 22:14:42.957848 Set Vref, RX VrefLevel [Byte0]: 58
2775 22:14:42.960803 [Byte1]: 58
2776 22:14:42.965891
2777 22:14:42.965971 Set Vref, RX VrefLevel [Byte0]: 59
2778 22:14:42.969596 [Byte1]: 59
2779 22:14:42.973803
2780 22:14:42.973884 Set Vref, RX VrefLevel [Byte0]: 60
2781 22:14:42.977235 [Byte1]: 60
2782 22:14:42.981606
2783 22:14:42.981687 Set Vref, RX VrefLevel [Byte0]: 61
2784 22:14:42.984752 [Byte1]: 61
2785 22:14:42.989645
2786 22:14:42.989725 Set Vref, RX VrefLevel [Byte0]: 62
2787 22:14:42.992711 [Byte1]: 62
2788 22:14:42.997820
2789 22:14:42.997892 Set Vref, RX VrefLevel [Byte0]: 63
2790 22:14:43.001091 [Byte1]: 63
2791 22:14:43.005532
2792 22:14:43.005601 Set Vref, RX VrefLevel [Byte0]: 64
2793 22:14:43.008744 [Byte1]: 64
2794 22:14:43.013808
2795 22:14:43.013902 Set Vref, RX VrefLevel [Byte0]: 65
2796 22:14:43.016609 [Byte1]: 65
2797 22:14:43.021735
2798 22:14:43.021812 Set Vref, RX VrefLevel [Byte0]: 66
2799 22:14:43.025024 [Byte1]: 66
2800 22:14:43.029784
2801 22:14:43.029851 Set Vref, RX VrefLevel [Byte0]: 67
2802 22:14:43.032909 [Byte1]: 67
2803 22:14:43.037345
2804 22:14:43.037443 Set Vref, RX VrefLevel [Byte0]: 68
2805 22:14:43.041026 [Byte1]: 68
2806 22:14:43.045760
2807 22:14:43.045860 Set Vref, RX VrefLevel [Byte0]: 69
2808 22:14:43.048870 [Byte1]: 69
2809 22:14:43.053661
2810 22:14:43.053764 Set Vref, RX VrefLevel [Byte0]: 70
2811 22:14:43.056840 [Byte1]: 70
2812 22:14:43.061548
2813 22:14:43.061652 Set Vref, RX VrefLevel [Byte0]: 71
2814 22:14:43.064657 [Byte1]: 71
2815 22:14:43.069585
2816 22:14:43.069693 Set Vref, RX VrefLevel [Byte0]: 72
2817 22:14:43.073076 [Byte1]: 72
2818 22:14:43.077851
2819 22:14:43.077929 Set Vref, RX VrefLevel [Byte0]: 73
2820 22:14:43.080947 [Byte1]: 73
2821 22:14:43.085708
2822 22:14:43.085804 Set Vref, RX VrefLevel [Byte0]: 74
2823 22:14:43.088962 [Byte1]: 74
2824 22:14:43.093383
2825 22:14:43.093456 Set Vref, RX VrefLevel [Byte0]: 75
2826 22:14:43.097117 [Byte1]: 75
2827 22:14:43.101481
2828 22:14:43.101557 Final RX Vref Byte 0 = 64 to rank0
2829 22:14:43.104758 Final RX Vref Byte 1 = 58 to rank0
2830 22:14:43.108091 Final RX Vref Byte 0 = 64 to rank1
2831 22:14:43.111369 Final RX Vref Byte 1 = 58 to rank1==
2832 22:14:43.114854 Dram Type= 6, Freq= 0, CH_0, rank 0
2833 22:14:43.121582 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2834 22:14:43.121663 ==
2835 22:14:43.121729 DQS Delay:
2836 22:14:43.121788 DQS0 = 0, DQS1 = 0
2837 22:14:43.124982 DQM Delay:
2838 22:14:43.125048 DQM0 = 112, DQM1 = 102
2839 22:14:43.128271 DQ Delay:
2840 22:14:43.131178 DQ0 =110, DQ1 =112, DQ2 =114, DQ3 =108
2841 22:14:43.134560 DQ4 =112, DQ5 =104, DQ6 =120, DQ7 =120
2842 22:14:43.137836 DQ8 =94, DQ9 =86, DQ10 =104, DQ11 =94
2843 22:14:43.141112 DQ12 =108, DQ13 =108, DQ14 =116, DQ15 =108
2844 22:14:43.141181
2845 22:14:43.141239
2846 22:14:43.151063 [DQSOSCAuto] RK0, (LSB)MR18= 0xfdfd, (MSB)MR19= 0x303, tDQSOscB0 = 411 ps tDQSOscB1 = 411 ps
2847 22:14:43.151144 CH0 RK0: MR19=303, MR18=FDFD
2848 22:14:43.158032 CH0_RK0: MR19=0x303, MR18=0xFDFD, DQSOSC=411, MR23=63, INC=38, DEC=25
2849 22:14:43.158138
2850 22:14:43.161194 ----->DramcWriteLeveling(PI) begin...
2851 22:14:43.161290 ==
2852 22:14:43.164419 Dram Type= 6, Freq= 0, CH_0, rank 1
2853 22:14:43.171330 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2854 22:14:43.171434 ==
2855 22:14:43.174376 Write leveling (Byte 0): 32 => 32
2856 22:14:43.174451 Write leveling (Byte 1): 31 => 31
2857 22:14:43.178048 DramcWriteLeveling(PI) end<-----
2858 22:14:43.178125
2859 22:14:43.178186 ==
2860 22:14:43.181445 Dram Type= 6, Freq= 0, CH_0, rank 1
2861 22:14:43.187889 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2862 22:14:43.187987 ==
2863 22:14:43.191311 [Gating] SW mode calibration
2864 22:14:43.197943 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2865 22:14:43.201118 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2866 22:14:43.207496 0 15 0 | B1->B0 | 2323 3333 | 1 1 | (0 0) (1 1)
2867 22:14:43.210741 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2868 22:14:43.214153 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2869 22:14:43.220764 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2870 22:14:43.224153 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2871 22:14:43.227490 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2872 22:14:43.234214 0 15 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
2873 22:14:43.237479 0 15 28 | B1->B0 | 3434 2626 | 1 0 | (1 0) (0 0)
2874 22:14:43.240844 1 0 0 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
2875 22:14:43.247737 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2876 22:14:43.250537 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2877 22:14:43.254301 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2878 22:14:43.260602 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2879 22:14:43.264206 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2880 22:14:43.267467 1 0 24 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
2881 22:14:43.273941 1 0 28 | B1->B0 | 2828 4646 | 0 0 | (0 0) (0 0)
2882 22:14:43.277165 1 1 0 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
2883 22:14:43.280364 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2884 22:14:43.287152 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2885 22:14:43.290575 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2886 22:14:43.293720 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2887 22:14:43.300227 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2888 22:14:43.303881 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2889 22:14:43.307126 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2890 22:14:43.313381 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2891 22:14:43.316536 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2892 22:14:43.320397 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2893 22:14:43.326528 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2894 22:14:43.329742 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2895 22:14:43.333177 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2896 22:14:43.340022 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2897 22:14:43.342969 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2898 22:14:43.346318 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2899 22:14:43.349678 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2900 22:14:43.356252 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2901 22:14:43.359588 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2902 22:14:43.362666 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2903 22:14:43.369418 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2904 22:14:43.373038 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2905 22:14:43.376180 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2906 22:14:43.382936 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2907 22:14:43.386187 Total UI for P1: 0, mck2ui 16
2908 22:14:43.389620 best dqsien dly found for B0: ( 1, 3, 28)
2909 22:14:43.392668 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2910 22:14:43.396017 Total UI for P1: 0, mck2ui 16
2911 22:14:43.399669 best dqsien dly found for B1: ( 1, 4, 0)
2912 22:14:43.403289 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2913 22:14:43.405895 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2914 22:14:43.405977
2915 22:14:43.409282 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2916 22:14:43.412645 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2917 22:14:43.416277 [Gating] SW calibration Done
2918 22:14:43.416378 ==
2919 22:14:43.419637 Dram Type= 6, Freq= 0, CH_0, rank 1
2920 22:14:43.426097 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2921 22:14:43.426179 ==
2922 22:14:43.426244 RX Vref Scan: 0
2923 22:14:43.426304
2924 22:14:43.429171 RX Vref 0 -> 0, step: 1
2925 22:14:43.429252
2926 22:14:43.432447 RX Delay -40 -> 252, step: 8
2927 22:14:43.435820 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2928 22:14:43.439196 iDelay=200, Bit 1, Center 111 (32 ~ 191) 160
2929 22:14:43.442432 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2930 22:14:43.445790 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2931 22:14:43.452435 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2932 22:14:43.455976 iDelay=200, Bit 5, Center 99 (32 ~ 167) 136
2933 22:14:43.459383 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
2934 22:14:43.462768 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2935 22:14:43.465894 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
2936 22:14:43.469192 iDelay=200, Bit 9, Center 83 (8 ~ 159) 152
2937 22:14:43.475596 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2938 22:14:43.478931 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
2939 22:14:43.482465 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2940 22:14:43.485575 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2941 22:14:43.492130 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
2942 22:14:43.495685 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2943 22:14:43.495767 ==
2944 22:14:43.498745 Dram Type= 6, Freq= 0, CH_0, rank 1
2945 22:14:43.501984 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2946 22:14:43.502067 ==
2947 22:14:43.505353 DQS Delay:
2948 22:14:43.505435 DQS0 = 0, DQS1 = 0
2949 22:14:43.505499 DQM Delay:
2950 22:14:43.508718 DQM0 = 112, DQM1 = 102
2951 22:14:43.508822 DQ Delay:
2952 22:14:43.511772 DQ0 =111, DQ1 =111, DQ2 =111, DQ3 =107
2953 22:14:43.515165 DQ4 =115, DQ5 =99, DQ6 =119, DQ7 =123
2954 22:14:43.518588 DQ8 =91, DQ9 =83, DQ10 =103, DQ11 =95
2955 22:14:43.525388 DQ12 =111, DQ13 =111, DQ14 =111, DQ15 =111
2956 22:14:43.525469
2957 22:14:43.525532
2958 22:14:43.525591 ==
2959 22:14:43.528188 Dram Type= 6, Freq= 0, CH_0, rank 1
2960 22:14:43.531611 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2961 22:14:43.531694 ==
2962 22:14:43.531757
2963 22:14:43.531816
2964 22:14:43.535223 TX Vref Scan disable
2965 22:14:43.535304 == TX Byte 0 ==
2966 22:14:43.542039 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2967 22:14:43.545378 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2968 22:14:43.545460 == TX Byte 1 ==
2969 22:14:43.551576 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2970 22:14:43.554971 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2971 22:14:43.555053 ==
2972 22:14:43.558841 Dram Type= 6, Freq= 0, CH_0, rank 1
2973 22:14:43.561359 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2974 22:14:43.561468 ==
2975 22:14:43.574648 TX Vref=22, minBit 1, minWin=26, winSum=425
2976 22:14:43.577492 TX Vref=24, minBit 8, minWin=26, winSum=432
2977 22:14:43.581486 TX Vref=26, minBit 12, minWin=26, winSum=439
2978 22:14:43.584325 TX Vref=28, minBit 1, minWin=27, winSum=444
2979 22:14:43.588098 TX Vref=30, minBit 8, minWin=26, winSum=440
2980 22:14:43.591149 TX Vref=32, minBit 3, minWin=27, winSum=439
2981 22:14:43.597895 [TxChooseVref] Worse bit 1, Min win 27, Win sum 444, Final Vref 28
2982 22:14:43.597978
2983 22:14:43.601406 Final TX Range 1 Vref 28
2984 22:14:43.601489
2985 22:14:43.601551 ==
2986 22:14:43.604323 Dram Type= 6, Freq= 0, CH_0, rank 1
2987 22:14:43.608009 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2988 22:14:43.608091 ==
2989 22:14:43.608155
2990 22:14:43.611342
2991 22:14:43.611423 TX Vref Scan disable
2992 22:14:43.614814 == TX Byte 0 ==
2993 22:14:43.617976 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2994 22:14:43.621485 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2995 22:14:43.624184 == TX Byte 1 ==
2996 22:14:43.627658 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2997 22:14:43.630982 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2998 22:14:43.634539
2999 22:14:43.634625 [DATLAT]
3000 22:14:43.634690 Freq=1200, CH0 RK1
3001 22:14:43.634750
3002 22:14:43.637834 DATLAT Default: 0xd
3003 22:14:43.637915 0, 0xFFFF, sum = 0
3004 22:14:43.640834 1, 0xFFFF, sum = 0
3005 22:14:43.640916 2, 0xFFFF, sum = 0
3006 22:14:43.644236 3, 0xFFFF, sum = 0
3007 22:14:43.644319 4, 0xFFFF, sum = 0
3008 22:14:43.647665 5, 0xFFFF, sum = 0
3009 22:14:43.651286 6, 0xFFFF, sum = 0
3010 22:14:43.651369 7, 0xFFFF, sum = 0
3011 22:14:43.654420 8, 0xFFFF, sum = 0
3012 22:14:43.654502 9, 0xFFFF, sum = 0
3013 22:14:43.657731 10, 0xFFFF, sum = 0
3014 22:14:43.657813 11, 0xFFFF, sum = 0
3015 22:14:43.661040 12, 0x0, sum = 1
3016 22:14:43.661122 13, 0x0, sum = 2
3017 22:14:43.664099 14, 0x0, sum = 3
3018 22:14:43.664194 15, 0x0, sum = 4
3019 22:14:43.664259 best_step = 13
3020 22:14:43.667326
3021 22:14:43.667407 ==
3022 22:14:43.670673 Dram Type= 6, Freq= 0, CH_0, rank 1
3023 22:14:43.673872 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3024 22:14:43.673955 ==
3025 22:14:43.674019 RX Vref Scan: 0
3026 22:14:43.674078
3027 22:14:43.677302 RX Vref 0 -> 0, step: 1
3028 22:14:43.677383
3029 22:14:43.680617 RX Delay -37 -> 252, step: 4
3030 22:14:43.684086 iDelay=195, Bit 0, Center 108 (39 ~ 178) 140
3031 22:14:43.690383 iDelay=195, Bit 1, Center 112 (43 ~ 182) 140
3032 22:14:43.694169 iDelay=195, Bit 2, Center 108 (43 ~ 174) 132
3033 22:14:43.697375 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3034 22:14:43.700458 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3035 22:14:43.704052 iDelay=195, Bit 5, Center 100 (35 ~ 166) 132
3036 22:14:43.710596 iDelay=195, Bit 6, Center 120 (47 ~ 194) 148
3037 22:14:43.713686 iDelay=195, Bit 7, Center 120 (47 ~ 194) 148
3038 22:14:43.717304 iDelay=195, Bit 8, Center 90 (19 ~ 162) 144
3039 22:14:43.721036 iDelay=195, Bit 9, Center 84 (15 ~ 154) 140
3040 22:14:43.723691 iDelay=195, Bit 10, Center 102 (35 ~ 170) 136
3041 22:14:43.730711 iDelay=195, Bit 11, Center 94 (27 ~ 162) 136
3042 22:14:43.733753 iDelay=195, Bit 12, Center 110 (43 ~ 178) 136
3043 22:14:43.736895 iDelay=195, Bit 13, Center 108 (39 ~ 178) 140
3044 22:14:43.740139 iDelay=195, Bit 14, Center 116 (51 ~ 182) 132
3045 22:14:43.743832 iDelay=195, Bit 15, Center 110 (43 ~ 178) 136
3046 22:14:43.747170 ==
3047 22:14:43.750465 Dram Type= 6, Freq= 0, CH_0, rank 1
3048 22:14:43.753903 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3049 22:14:43.753985 ==
3050 22:14:43.754049 DQS Delay:
3051 22:14:43.757285 DQS0 = 0, DQS1 = 0
3052 22:14:43.757366 DQM Delay:
3053 22:14:43.760740 DQM0 = 111, DQM1 = 101
3054 22:14:43.760821 DQ Delay:
3055 22:14:43.764001 DQ0 =108, DQ1 =112, DQ2 =108, DQ3 =108
3056 22:14:43.767253 DQ4 =112, DQ5 =100, DQ6 =120, DQ7 =120
3057 22:14:43.770579 DQ8 =90, DQ9 =84, DQ10 =102, DQ11 =94
3058 22:14:43.773679 DQ12 =110, DQ13 =108, DQ14 =116, DQ15 =110
3059 22:14:43.773760
3060 22:14:43.773823
3061 22:14:43.783593 [DQSOSCAuto] RK1, (LSB)MR18= 0x15fd, (MSB)MR19= 0x403, tDQSOscB0 = 411 ps tDQSOscB1 = 401 ps
3062 22:14:43.783675 CH0 RK1: MR19=403, MR18=15FD
3063 22:14:43.790412 CH0_RK1: MR19=0x403, MR18=0x15FD, DQSOSC=401, MR23=63, INC=40, DEC=27
3064 22:14:43.793590 [RxdqsGatingPostProcess] freq 1200
3065 22:14:43.800510 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3066 22:14:43.803589 best DQS0 dly(2T, 0.5T) = (0, 11)
3067 22:14:43.807324 best DQS1 dly(2T, 0.5T) = (0, 12)
3068 22:14:43.810400 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3069 22:14:43.813480 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3070 22:14:43.817090 best DQS0 dly(2T, 0.5T) = (0, 11)
3071 22:14:43.817201 best DQS1 dly(2T, 0.5T) = (0, 12)
3072 22:14:43.820285 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3073 22:14:43.823422 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3074 22:14:43.826670 Pre-setting of DQS Precalculation
3075 22:14:43.833572 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3076 22:14:43.833668 ==
3077 22:14:43.836677 Dram Type= 6, Freq= 0, CH_1, rank 0
3078 22:14:43.839668 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3079 22:14:43.839743 ==
3080 22:14:43.846419 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3081 22:14:43.853000 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3082 22:14:43.860402 [CA 0] Center 37 (7~67) winsize 61
3083 22:14:43.863877 [CA 1] Center 37 (7~68) winsize 62
3084 22:14:43.867256 [CA 2] Center 34 (4~64) winsize 61
3085 22:14:43.870698 [CA 3] Center 34 (4~64) winsize 61
3086 22:14:43.873493 [CA 4] Center 34 (4~64) winsize 61
3087 22:14:43.876947 [CA 5] Center 33 (3~63) winsize 61
3088 22:14:43.877035
3089 22:14:43.880279 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3090 22:14:43.880355
3091 22:14:43.883603 [CATrainingPosCal] consider 1 rank data
3092 22:14:43.887071 u2DelayCellTimex100 = 270/100 ps
3093 22:14:43.890463 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3094 22:14:43.893917 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3095 22:14:43.900501 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3096 22:14:43.903607 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3097 22:14:43.907239 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3098 22:14:43.910334 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3099 22:14:43.910403
3100 22:14:43.914029 CA PerBit enable=1, Macro0, CA PI delay=33
3101 22:14:43.914106
3102 22:14:43.917186 [CBTSetCACLKResult] CA Dly = 33
3103 22:14:43.917254 CS Dly: 5 (0~36)
3104 22:14:43.920267 ==
3105 22:14:43.920336 Dram Type= 6, Freq= 0, CH_1, rank 1
3106 22:14:43.927086 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3107 22:14:43.927161 ==
3108 22:14:43.930208 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3109 22:14:43.936836 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3110 22:14:43.945976 [CA 0] Center 37 (8~67) winsize 60
3111 22:14:43.949439 [CA 1] Center 37 (7~68) winsize 62
3112 22:14:43.952789 [CA 2] Center 34 (4~65) winsize 62
3113 22:14:43.956049 [CA 3] Center 33 (3~64) winsize 62
3114 22:14:43.959397 [CA 4] Center 34 (4~65) winsize 62
3115 22:14:43.962542 [CA 5] Center 32 (2~63) winsize 62
3116 22:14:43.962639
3117 22:14:43.966106 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3118 22:14:43.966180
3119 22:14:43.968951 [CATrainingPosCal] consider 2 rank data
3120 22:14:43.972467 u2DelayCellTimex100 = 270/100 ps
3121 22:14:43.975873 CA0 delay=37 (8~67),Diff = 4 PI (19 cell)
3122 22:14:43.979412 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3123 22:14:43.986109 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3124 22:14:43.989476 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3125 22:14:43.992927 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3126 22:14:43.995615 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3127 22:14:43.995696
3128 22:14:43.999101 CA PerBit enable=1, Macro0, CA PI delay=33
3129 22:14:43.999182
3130 22:14:44.002563 [CBTSetCACLKResult] CA Dly = 33
3131 22:14:44.002644 CS Dly: 6 (0~39)
3132 22:14:44.002709
3133 22:14:44.009329 ----->DramcWriteLeveling(PI) begin...
3134 22:14:44.009413 ==
3135 22:14:44.012299 Dram Type= 6, Freq= 0, CH_1, rank 0
3136 22:14:44.015495 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3137 22:14:44.015576 ==
3138 22:14:44.019071 Write leveling (Byte 0): 27 => 27
3139 22:14:44.022497 Write leveling (Byte 1): 31 => 31
3140 22:14:44.025519 DramcWriteLeveling(PI) end<-----
3141 22:14:44.025616
3142 22:14:44.025694 ==
3143 22:14:44.029112 Dram Type= 6, Freq= 0, CH_1, rank 0
3144 22:14:44.032195 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3145 22:14:44.032277 ==
3146 22:14:44.035708 [Gating] SW mode calibration
3147 22:14:44.042435 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3148 22:14:44.049255 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3149 22:14:44.052251 0 15 0 | B1->B0 | 2c2c 2727 | 0 0 | (0 0) (0 0)
3150 22:14:44.055714 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3151 22:14:44.062469 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3152 22:14:44.065648 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3153 22:14:44.068702 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3154 22:14:44.075439 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3155 22:14:44.079093 0 15 24 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
3156 22:14:44.081917 0 15 28 | B1->B0 | 2e2e 3232 | 1 1 | (1 0) (1 0)
3157 22:14:44.085364 1 0 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3158 22:14:44.091924 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3159 22:14:44.095281 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3160 22:14:44.098628 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3161 22:14:44.105723 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3162 22:14:44.108668 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3163 22:14:44.112173 1 0 24 | B1->B0 | 2626 2323 | 1 0 | (0 0) (0 0)
3164 22:14:44.118808 1 0 28 | B1->B0 | 4343 4040 | 0 0 | (0 0) (1 1)
3165 22:14:44.122271 1 1 0 | B1->B0 | 4646 4040 | 0 0 | (0 0) (0 0)
3166 22:14:44.125290 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3167 22:14:44.132151 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3168 22:14:44.135172 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3169 22:14:44.138852 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3170 22:14:44.145178 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3171 22:14:44.148230 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3172 22:14:44.151919 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3173 22:14:44.158378 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3174 22:14:44.161768 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3175 22:14:44.165506 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3176 22:14:44.172346 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3177 22:14:44.175231 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3178 22:14:44.178443 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3179 22:14:44.184797 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3180 22:14:44.188168 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3181 22:14:44.191652 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3182 22:14:44.198256 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3183 22:14:44.201637 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3184 22:14:44.205083 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3185 22:14:44.211287 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3186 22:14:44.214729 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3187 22:14:44.218114 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3188 22:14:44.221378 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3189 22:14:44.228179 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3190 22:14:44.231464 Total UI for P1: 0, mck2ui 16
3191 22:14:44.234667 best dqsien dly found for B0: ( 1, 3, 28)
3192 22:14:44.237895 Total UI for P1: 0, mck2ui 16
3193 22:14:44.241589 best dqsien dly found for B1: ( 1, 3, 28)
3194 22:14:44.245161 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3195 22:14:44.247830 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3196 22:14:44.247902
3197 22:14:44.251608 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3198 22:14:44.254756 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3199 22:14:44.257761 [Gating] SW calibration Done
3200 22:14:44.257834 ==
3201 22:14:44.261263 Dram Type= 6, Freq= 0, CH_1, rank 0
3202 22:14:44.264494 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3203 22:14:44.264629 ==
3204 22:14:44.267872 RX Vref Scan: 0
3205 22:14:44.267967
3206 22:14:44.271138 RX Vref 0 -> 0, step: 1
3207 22:14:44.271212
3208 22:14:44.271273 RX Delay -40 -> 252, step: 8
3209 22:14:44.277869 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3210 22:14:44.281718 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3211 22:14:44.284662 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3212 22:14:44.287759 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3213 22:14:44.291126 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3214 22:14:44.297386 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3215 22:14:44.301127 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3216 22:14:44.304471 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3217 22:14:44.307379 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3218 22:14:44.310824 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3219 22:14:44.317642 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
3220 22:14:44.321051 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
3221 22:14:44.324894 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
3222 22:14:44.327724 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
3223 22:14:44.330859 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3224 22:14:44.337303 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3225 22:14:44.337412 ==
3226 22:14:44.340974 Dram Type= 6, Freq= 0, CH_1, rank 0
3227 22:14:44.344069 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3228 22:14:44.344172 ==
3229 22:14:44.344261 DQS Delay:
3230 22:14:44.347591 DQS0 = 0, DQS1 = 0
3231 22:14:44.347688 DQM Delay:
3232 22:14:44.350689 DQM0 = 114, DQM1 = 104
3233 22:14:44.350790 DQ Delay:
3234 22:14:44.353795 DQ0 =119, DQ1 =107, DQ2 =103, DQ3 =115
3235 22:14:44.357494 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =115
3236 22:14:44.360715 DQ8 =95, DQ9 =95, DQ10 =103, DQ11 =99
3237 22:14:44.364035 DQ12 =111, DQ13 =111, DQ14 =111, DQ15 =111
3238 22:14:44.364144
3239 22:14:44.364233
3240 22:14:44.367386 ==
3241 22:14:44.370484 Dram Type= 6, Freq= 0, CH_1, rank 0
3242 22:14:44.373938 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3243 22:14:44.374020 ==
3244 22:14:44.374084
3245 22:14:44.374149
3246 22:14:44.377311 TX Vref Scan disable
3247 22:14:44.377408 == TX Byte 0 ==
3248 22:14:44.383582 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3249 22:14:44.386984 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3250 22:14:44.387058 == TX Byte 1 ==
3251 22:14:44.390450 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
3252 22:14:44.397138 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
3253 22:14:44.397245 ==
3254 22:14:44.400606 Dram Type= 6, Freq= 0, CH_1, rank 0
3255 22:14:44.403601 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3256 22:14:44.403712 ==
3257 22:14:44.416314 TX Vref=22, minBit 3, minWin=25, winSum=416
3258 22:14:44.419120 TX Vref=24, minBit 8, minWin=25, winSum=423
3259 22:14:44.422470 TX Vref=26, minBit 1, minWin=26, winSum=429
3260 22:14:44.425888 TX Vref=28, minBit 1, minWin=26, winSum=428
3261 22:14:44.429224 TX Vref=30, minBit 1, minWin=26, winSum=430
3262 22:14:44.435722 TX Vref=32, minBit 1, minWin=26, winSum=428
3263 22:14:44.439474 [TxChooseVref] Worse bit 1, Min win 26, Win sum 430, Final Vref 30
3264 22:14:44.439548
3265 22:14:44.442770 Final TX Range 1 Vref 30
3266 22:14:44.442868
3267 22:14:44.442929 ==
3268 22:14:44.445738 Dram Type= 6, Freq= 0, CH_1, rank 0
3269 22:14:44.448945 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3270 22:14:44.449016 ==
3271 22:14:44.452669
3272 22:14:44.452738
3273 22:14:44.452798 TX Vref Scan disable
3274 22:14:44.455726 == TX Byte 0 ==
3275 22:14:44.458972 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3276 22:14:44.462740 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3277 22:14:44.465630 == TX Byte 1 ==
3278 22:14:44.469034 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
3279 22:14:44.475807 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
3280 22:14:44.475920
3281 22:14:44.476012 [DATLAT]
3282 22:14:44.476117 Freq=1200, CH1 RK0
3283 22:14:44.476205
3284 22:14:44.478918 DATLAT Default: 0xd
3285 22:14:44.479016 0, 0xFFFF, sum = 0
3286 22:14:44.482250 1, 0xFFFF, sum = 0
3287 22:14:44.485719 2, 0xFFFF, sum = 0
3288 22:14:44.485818 3, 0xFFFF, sum = 0
3289 22:14:44.488829 4, 0xFFFF, sum = 0
3290 22:14:44.488935 5, 0xFFFF, sum = 0
3291 22:14:44.492251 6, 0xFFFF, sum = 0
3292 22:14:44.492352 7, 0xFFFF, sum = 0
3293 22:14:44.495615 8, 0xFFFF, sum = 0
3294 22:14:44.495715 9, 0xFFFF, sum = 0
3295 22:14:44.499299 10, 0xFFFF, sum = 0
3296 22:14:44.499396 11, 0xFFFF, sum = 0
3297 22:14:44.502111 12, 0x0, sum = 1
3298 22:14:44.502208 13, 0x0, sum = 2
3299 22:14:44.505743 14, 0x0, sum = 3
3300 22:14:44.505853 15, 0x0, sum = 4
3301 22:14:44.508660 best_step = 13
3302 22:14:44.508755
3303 22:14:44.508857 ==
3304 22:14:44.512172 Dram Type= 6, Freq= 0, CH_1, rank 0
3305 22:14:44.515361 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3306 22:14:44.515457 ==
3307 22:14:44.515551 RX Vref Scan: 1
3308 22:14:44.515645
3309 22:14:44.518689 Set Vref Range= 32 -> 127
3310 22:14:44.518789
3311 22:14:44.522269 RX Vref 32 -> 127, step: 1
3312 22:14:44.522364
3313 22:14:44.525478 RX Delay -21 -> 252, step: 4
3314 22:14:44.525572
3315 22:14:44.528372 Set Vref, RX VrefLevel [Byte0]: 32
3316 22:14:44.532149 [Byte1]: 32
3317 22:14:44.532244
3318 22:14:44.535399 Set Vref, RX VrefLevel [Byte0]: 33
3319 22:14:44.538660 [Byte1]: 33
3320 22:14:44.542041
3321 22:14:44.542135 Set Vref, RX VrefLevel [Byte0]: 34
3322 22:14:44.545614 [Byte1]: 34
3323 22:14:44.550191
3324 22:14:44.550290 Set Vref, RX VrefLevel [Byte0]: 35
3325 22:14:44.556647 [Byte1]: 35
3326 22:14:44.556743
3327 22:14:44.559758 Set Vref, RX VrefLevel [Byte0]: 36
3328 22:14:44.563375 [Byte1]: 36
3329 22:14:44.563474
3330 22:14:44.566902 Set Vref, RX VrefLevel [Byte0]: 37
3331 22:14:44.570038 [Byte1]: 37
3332 22:14:44.573675
3333 22:14:44.573779 Set Vref, RX VrefLevel [Byte0]: 38
3334 22:14:44.577406 [Byte1]: 38
3335 22:14:44.581763
3336 22:14:44.581854 Set Vref, RX VrefLevel [Byte0]: 39
3337 22:14:44.585321 [Byte1]: 39
3338 22:14:44.589658
3339 22:14:44.589750 Set Vref, RX VrefLevel [Byte0]: 40
3340 22:14:44.593042 [Byte1]: 40
3341 22:14:44.597529
3342 22:14:44.597622 Set Vref, RX VrefLevel [Byte0]: 41
3343 22:14:44.600949 [Byte1]: 41
3344 22:14:44.605630
3345 22:14:44.605722 Set Vref, RX VrefLevel [Byte0]: 42
3346 22:14:44.609249 [Byte1]: 42
3347 22:14:44.613349
3348 22:14:44.613415 Set Vref, RX VrefLevel [Byte0]: 43
3349 22:14:44.617345 [Byte1]: 43
3350 22:14:44.621564
3351 22:14:44.621634 Set Vref, RX VrefLevel [Byte0]: 44
3352 22:14:44.624949 [Byte1]: 44
3353 22:14:44.629004
3354 22:14:44.629099 Set Vref, RX VrefLevel [Byte0]: 45
3355 22:14:44.632463 [Byte1]: 45
3356 22:14:44.637202
3357 22:14:44.637277 Set Vref, RX VrefLevel [Byte0]: 46
3358 22:14:44.640630 [Byte1]: 46
3359 22:14:44.645132
3360 22:14:44.645200 Set Vref, RX VrefLevel [Byte0]: 47
3361 22:14:44.648438 [Byte1]: 47
3362 22:14:44.652840
3363 22:14:44.652908 Set Vref, RX VrefLevel [Byte0]: 48
3364 22:14:44.656530 [Byte1]: 48
3365 22:14:44.660859
3366 22:14:44.660957 Set Vref, RX VrefLevel [Byte0]: 49
3367 22:14:44.664088 [Byte1]: 49
3368 22:14:44.668655
3369 22:14:44.668761 Set Vref, RX VrefLevel [Byte0]: 50
3370 22:14:44.672111 [Byte1]: 50
3371 22:14:44.677016
3372 22:14:44.677118 Set Vref, RX VrefLevel [Byte0]: 51
3373 22:14:44.680052 [Byte1]: 51
3374 22:14:44.684818
3375 22:14:44.684917 Set Vref, RX VrefLevel [Byte0]: 52
3376 22:14:44.688177 [Byte1]: 52
3377 22:14:44.692693
3378 22:14:44.692794 Set Vref, RX VrefLevel [Byte0]: 53
3379 22:14:44.696155 [Byte1]: 53
3380 22:14:44.700639
3381 22:14:44.700709 Set Vref, RX VrefLevel [Byte0]: 54
3382 22:14:44.704023 [Byte1]: 54
3383 22:14:44.708532
3384 22:14:44.708630 Set Vref, RX VrefLevel [Byte0]: 55
3385 22:14:44.711925 [Byte1]: 55
3386 22:14:44.716586
3387 22:14:44.716655 Set Vref, RX VrefLevel [Byte0]: 56
3388 22:14:44.720206 [Byte1]: 56
3389 22:14:44.724111
3390 22:14:44.724212 Set Vref, RX VrefLevel [Byte0]: 57
3391 22:14:44.727703 [Byte1]: 57
3392 22:14:44.732060
3393 22:14:44.732163 Set Vref, RX VrefLevel [Byte0]: 58
3394 22:14:44.735403 [Byte1]: 58
3395 22:14:44.740487
3396 22:14:44.740561 Set Vref, RX VrefLevel [Byte0]: 59
3397 22:14:44.743349 [Byte1]: 59
3398 22:14:44.748304
3399 22:14:44.748383 Set Vref, RX VrefLevel [Byte0]: 60
3400 22:14:44.754491 [Byte1]: 60
3401 22:14:44.754568
3402 22:14:44.757860 Set Vref, RX VrefLevel [Byte0]: 61
3403 22:14:44.761241 [Byte1]: 61
3404 22:14:44.761343
3405 22:14:44.764832 Set Vref, RX VrefLevel [Byte0]: 62
3406 22:14:44.767731 [Byte1]: 62
3407 22:14:44.771787
3408 22:14:44.771910 Set Vref, RX VrefLevel [Byte0]: 63
3409 22:14:44.775009 [Byte1]: 63
3410 22:14:44.780073
3411 22:14:44.780179 Set Vref, RX VrefLevel [Byte0]: 64
3412 22:14:44.783322 [Byte1]: 64
3413 22:14:44.788375
3414 22:14:44.788482 Set Vref, RX VrefLevel [Byte0]: 65
3415 22:14:44.791185 [Byte1]: 65
3416 22:14:44.795508
3417 22:14:44.795608 Set Vref, RX VrefLevel [Byte0]: 66
3418 22:14:44.798706 [Byte1]: 66
3419 22:14:44.803753
3420 22:14:44.803851 Set Vref, RX VrefLevel [Byte0]: 67
3421 22:14:44.807014 [Byte1]: 67
3422 22:14:44.811585
3423 22:14:44.811686 Set Vref, RX VrefLevel [Byte0]: 68
3424 22:14:44.814897 [Byte1]: 68
3425 22:14:44.819411
3426 22:14:44.819483 Final RX Vref Byte 0 = 53 to rank0
3427 22:14:44.822803 Final RX Vref Byte 1 = 47 to rank0
3428 22:14:44.826039 Final RX Vref Byte 0 = 53 to rank1
3429 22:14:44.829827 Final RX Vref Byte 1 = 47 to rank1==
3430 22:14:44.832681 Dram Type= 6, Freq= 0, CH_1, rank 0
3431 22:14:44.839122 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3432 22:14:44.839230 ==
3433 22:14:44.839322 DQS Delay:
3434 22:14:44.842809 DQS0 = 0, DQS1 = 0
3435 22:14:44.842915 DQM Delay:
3436 22:14:44.842980 DQM0 = 114, DQM1 = 104
3437 22:14:44.845609 DQ Delay:
3438 22:14:44.848977 DQ0 =118, DQ1 =108, DQ2 =104, DQ3 =112
3439 22:14:44.852368 DQ4 =112, DQ5 =124, DQ6 =126, DQ7 =112
3440 22:14:44.855816 DQ8 =94, DQ9 =96, DQ10 =106, DQ11 =98
3441 22:14:44.859228 DQ12 =112, DQ13 =110, DQ14 =112, DQ15 =110
3442 22:14:44.859298
3443 22:14:44.859357
3444 22:14:44.865972 [DQSOSCAuto] RK0, (LSB)MR18= 0xedf4, (MSB)MR19= 0x303, tDQSOscB0 = 415 ps tDQSOscB1 = 417 ps
3445 22:14:44.869195 CH1 RK0: MR19=303, MR18=EDF4
3446 22:14:44.876149 CH1_RK0: MR19=0x303, MR18=0xEDF4, DQSOSC=415, MR23=63, INC=38, DEC=25
3447 22:14:44.876254
3448 22:14:44.879104 ----->DramcWriteLeveling(PI) begin...
3449 22:14:44.879180 ==
3450 22:14:44.882398 Dram Type= 6, Freq= 0, CH_1, rank 1
3451 22:14:44.885811 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3452 22:14:44.888923 ==
3453 22:14:44.889020 Write leveling (Byte 0): 25 => 25
3454 22:14:44.892645 Write leveling (Byte 1): 26 => 26
3455 22:14:44.895541 DramcWriteLeveling(PI) end<-----
3456 22:14:44.895622
3457 22:14:44.895686 ==
3458 22:14:44.898929 Dram Type= 6, Freq= 0, CH_1, rank 1
3459 22:14:44.905673 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3460 22:14:44.905785 ==
3461 22:14:44.909029 [Gating] SW mode calibration
3462 22:14:44.915714 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3463 22:14:44.919154 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3464 22:14:44.925752 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3465 22:14:44.928560 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3466 22:14:44.932033 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3467 22:14:44.938969 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3468 22:14:44.942120 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3469 22:14:44.945490 0 15 20 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
3470 22:14:44.952130 0 15 24 | B1->B0 | 3434 2727 | 1 0 | (1 0) (0 0)
3471 22:14:44.955539 0 15 28 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
3472 22:14:44.958746 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3473 22:14:44.964867 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3474 22:14:44.968247 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3475 22:14:44.971550 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3476 22:14:44.978098 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3477 22:14:44.981598 1 0 20 | B1->B0 | 2424 2a29 | 0 1 | (0 0) (0 0)
3478 22:14:44.985337 1 0 24 | B1->B0 | 3131 4646 | 1 0 | (0 0) (0 0)
3479 22:14:44.991680 1 0 28 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
3480 22:14:44.995029 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3481 22:14:44.998482 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3482 22:14:45.004456 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3483 22:14:45.008005 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3484 22:14:45.011396 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3485 22:14:45.017536 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3486 22:14:45.021386 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3487 22:14:45.024249 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3488 22:14:45.031244 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3489 22:14:45.034262 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3490 22:14:45.037522 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3491 22:14:45.044142 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3492 22:14:45.047796 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3493 22:14:45.050573 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3494 22:14:45.057173 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3495 22:14:45.060538 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3496 22:14:45.063905 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3497 22:14:45.070770 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3498 22:14:45.074106 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3499 22:14:45.077334 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3500 22:14:45.083898 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3501 22:14:45.087383 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3502 22:14:45.090686 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3503 22:14:45.096915 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3504 22:14:45.096999 Total UI for P1: 0, mck2ui 16
3505 22:14:45.100591 best dqsien dly found for B0: ( 1, 3, 24)
3506 22:14:45.103748 Total UI for P1: 0, mck2ui 16
3507 22:14:45.107282 best dqsien dly found for B1: ( 1, 3, 24)
3508 22:14:45.110002 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3509 22:14:45.116656 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3510 22:14:45.116739
3511 22:14:45.119933 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3512 22:14:45.123548 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3513 22:14:45.126867 [Gating] SW calibration Done
3514 22:14:45.126963 ==
3515 22:14:45.129960 Dram Type= 6, Freq= 0, CH_1, rank 1
3516 22:14:45.133129 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3517 22:14:45.133211 ==
3518 22:14:45.136590 RX Vref Scan: 0
3519 22:14:45.136679
3520 22:14:45.136750 RX Vref 0 -> 0, step: 1
3521 22:14:45.136810
3522 22:14:45.139852 RX Delay -40 -> 252, step: 8
3523 22:14:45.143216 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3524 22:14:45.149588 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3525 22:14:45.152912 iDelay=200, Bit 2, Center 99 (24 ~ 175) 152
3526 22:14:45.156518 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
3527 22:14:45.159622 iDelay=200, Bit 4, Center 107 (32 ~ 183) 152
3528 22:14:45.162977 iDelay=200, Bit 5, Center 119 (40 ~ 199) 160
3529 22:14:45.169718 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
3530 22:14:45.173060 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3531 22:14:45.175918 iDelay=200, Bit 8, Center 91 (24 ~ 159) 136
3532 22:14:45.179369 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3533 22:14:45.182545 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
3534 22:14:45.189553 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
3535 22:14:45.192862 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
3536 22:14:45.195910 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
3537 22:14:45.199235 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
3538 22:14:45.202624 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
3539 22:14:45.205947 ==
3540 22:14:45.209093 Dram Type= 6, Freq= 0, CH_1, rank 1
3541 22:14:45.212438 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3542 22:14:45.212519 ==
3543 22:14:45.212585 DQS Delay:
3544 22:14:45.215743 DQS0 = 0, DQS1 = 0
3545 22:14:45.215821 DQM Delay:
3546 22:14:45.218837 DQM0 = 110, DQM1 = 105
3547 22:14:45.218967 DQ Delay:
3548 22:14:45.222434 DQ0 =115, DQ1 =107, DQ2 =99, DQ3 =107
3549 22:14:45.225618 DQ4 =107, DQ5 =119, DQ6 =119, DQ7 =111
3550 22:14:45.229296 DQ8 =91, DQ9 =95, DQ10 =107, DQ11 =95
3551 22:14:45.232631 DQ12 =111, DQ13 =111, DQ14 =115, DQ15 =115
3552 22:14:45.232704
3553 22:14:45.232765
3554 22:14:45.232826 ==
3555 22:14:45.235326 Dram Type= 6, Freq= 0, CH_1, rank 1
3556 22:14:45.242274 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3557 22:14:45.242377 ==
3558 22:14:45.242467
3559 22:14:45.242554
3560 22:14:45.242639 TX Vref Scan disable
3561 22:14:45.245647 == TX Byte 0 ==
3562 22:14:45.249214 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3563 22:14:45.255773 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3564 22:14:45.255873 == TX Byte 1 ==
3565 22:14:45.259029 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3566 22:14:45.265394 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3567 22:14:45.265494 ==
3568 22:14:45.268522 Dram Type= 6, Freq= 0, CH_1, rank 1
3569 22:14:45.271863 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3570 22:14:45.271937 ==
3571 22:14:45.283508 TX Vref=22, minBit 2, minWin=25, winSum=417
3572 22:14:45.286711 TX Vref=24, minBit 9, minWin=25, winSum=422
3573 22:14:45.289555 TX Vref=26, minBit 7, minWin=26, winSum=427
3574 22:14:45.293059 TX Vref=28, minBit 3, minWin=26, winSum=429
3575 22:14:45.296399 TX Vref=30, minBit 1, minWin=26, winSum=434
3576 22:14:45.303022 TX Vref=32, minBit 9, minWin=26, winSum=432
3577 22:14:45.306361 [TxChooseVref] Worse bit 1, Min win 26, Win sum 434, Final Vref 30
3578 22:14:45.306457
3579 22:14:45.309770 Final TX Range 1 Vref 30
3580 22:14:45.309866
3581 22:14:45.309952 ==
3582 22:14:45.312853 Dram Type= 6, Freq= 0, CH_1, rank 1
3583 22:14:45.316128 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3584 22:14:45.319397 ==
3585 22:14:45.319470
3586 22:14:45.319532
3587 22:14:45.319590 TX Vref Scan disable
3588 22:14:45.323053 == TX Byte 0 ==
3589 22:14:45.326103 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3590 22:14:45.333005 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3591 22:14:45.333082 == TX Byte 1 ==
3592 22:14:45.336377 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3593 22:14:45.342938 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3594 22:14:45.343014
3595 22:14:45.343078 [DATLAT]
3596 22:14:45.343136 Freq=1200, CH1 RK1
3597 22:14:45.343192
3598 22:14:45.346247 DATLAT Default: 0xd
3599 22:14:45.349044 0, 0xFFFF, sum = 0
3600 22:14:45.349117 1, 0xFFFF, sum = 0
3601 22:14:45.352425 2, 0xFFFF, sum = 0
3602 22:14:45.352496 3, 0xFFFF, sum = 0
3603 22:14:45.355843 4, 0xFFFF, sum = 0
3604 22:14:45.355916 5, 0xFFFF, sum = 0
3605 22:14:45.358992 6, 0xFFFF, sum = 0
3606 22:14:45.359063 7, 0xFFFF, sum = 0
3607 22:14:45.362455 8, 0xFFFF, sum = 0
3608 22:14:45.362559 9, 0xFFFF, sum = 0
3609 22:14:45.365446 10, 0xFFFF, sum = 0
3610 22:14:45.365549 11, 0xFFFF, sum = 0
3611 22:14:45.369205 12, 0x0, sum = 1
3612 22:14:45.369307 13, 0x0, sum = 2
3613 22:14:45.372406 14, 0x0, sum = 3
3614 22:14:45.372506 15, 0x0, sum = 4
3615 22:14:45.375575 best_step = 13
3616 22:14:45.375646
3617 22:14:45.375705 ==
3618 22:14:45.378939 Dram Type= 6, Freq= 0, CH_1, rank 1
3619 22:14:45.382370 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3620 22:14:45.382464 ==
3621 22:14:45.385817 RX Vref Scan: 0
3622 22:14:45.385910
3623 22:14:45.385995 RX Vref 0 -> 0, step: 1
3624 22:14:45.386071
3625 22:14:45.388635 RX Delay -21 -> 252, step: 4
3626 22:14:45.395266 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3627 22:14:45.398371 iDelay=195, Bit 1, Center 108 (39 ~ 178) 140
3628 22:14:45.401849 iDelay=195, Bit 2, Center 100 (31 ~ 170) 140
3629 22:14:45.405119 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3630 22:14:45.408666 iDelay=195, Bit 4, Center 110 (39 ~ 182) 144
3631 22:14:45.415106 iDelay=195, Bit 5, Center 118 (47 ~ 190) 144
3632 22:14:45.418468 iDelay=195, Bit 6, Center 120 (47 ~ 194) 148
3633 22:14:45.421674 iDelay=195, Bit 7, Center 112 (47 ~ 178) 132
3634 22:14:45.424950 iDelay=195, Bit 8, Center 92 (27 ~ 158) 132
3635 22:14:45.428496 iDelay=195, Bit 9, Center 100 (35 ~ 166) 132
3636 22:14:45.434966 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
3637 22:14:45.438035 iDelay=195, Bit 11, Center 102 (39 ~ 166) 128
3638 22:14:45.441501 iDelay=195, Bit 12, Center 116 (55 ~ 178) 124
3639 22:14:45.444637 iDelay=195, Bit 13, Center 114 (51 ~ 178) 128
3640 22:14:45.451079 iDelay=195, Bit 14, Center 116 (55 ~ 178) 124
3641 22:14:45.454570 iDelay=195, Bit 15, Center 116 (51 ~ 182) 132
3642 22:14:45.454650 ==
3643 22:14:45.457767 Dram Type= 6, Freq= 0, CH_1, rank 1
3644 22:14:45.461207 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3645 22:14:45.461288 ==
3646 22:14:45.464472 DQS Delay:
3647 22:14:45.464555 DQS0 = 0, DQS1 = 0
3648 22:14:45.464618 DQM Delay:
3649 22:14:45.467583 DQM0 = 111, DQM1 = 108
3650 22:14:45.467663 DQ Delay:
3651 22:14:45.471523 DQ0 =114, DQ1 =108, DQ2 =100, DQ3 =108
3652 22:14:45.474351 DQ4 =110, DQ5 =118, DQ6 =120, DQ7 =112
3653 22:14:45.480886 DQ8 =92, DQ9 =100, DQ10 =110, DQ11 =102
3654 22:14:45.484283 DQ12 =116, DQ13 =114, DQ14 =116, DQ15 =116
3655 22:14:45.484380
3656 22:14:45.484445
3657 22:14:45.490526 [DQSOSCAuto] RK1, (LSB)MR18= 0xfc0c, (MSB)MR19= 0x304, tDQSOscB0 = 405 ps tDQSOscB1 = 411 ps
3658 22:14:45.493851 CH1 RK1: MR19=304, MR18=FC0C
3659 22:14:45.500555 CH1_RK1: MR19=0x304, MR18=0xFC0C, DQSOSC=405, MR23=63, INC=39, DEC=26
3660 22:14:45.504006 [RxdqsGatingPostProcess] freq 1200
3661 22:14:45.510603 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3662 22:14:45.513932 best DQS0 dly(2T, 0.5T) = (0, 11)
3663 22:14:45.514013 best DQS1 dly(2T, 0.5T) = (0, 11)
3664 22:14:45.517225 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3665 22:14:45.520419 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3666 22:14:45.523753 best DQS0 dly(2T, 0.5T) = (0, 11)
3667 22:14:45.526818 best DQS1 dly(2T, 0.5T) = (0, 11)
3668 22:14:45.530041 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3669 22:14:45.533454 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3670 22:14:45.537024 Pre-setting of DQS Precalculation
3671 22:14:45.543139 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3672 22:14:45.550170 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3673 22:14:45.556405 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3674 22:14:45.556487
3675 22:14:45.556549
3676 22:14:45.559713 [Calibration Summary] 2400 Mbps
3677 22:14:45.559793 CH 0, Rank 0
3678 22:14:45.563061 SW Impedance : PASS
3679 22:14:45.566486 DUTY Scan : NO K
3680 22:14:45.566567 ZQ Calibration : PASS
3681 22:14:45.569879 Jitter Meter : NO K
3682 22:14:45.573112 CBT Training : PASS
3683 22:14:45.573208 Write leveling : PASS
3684 22:14:45.576134 RX DQS gating : PASS
3685 22:14:45.579745 RX DQ/DQS(RDDQC) : PASS
3686 22:14:45.579825 TX DQ/DQS : PASS
3687 22:14:45.582679 RX DATLAT : PASS
3688 22:14:45.586350 RX DQ/DQS(Engine): PASS
3689 22:14:45.586431 TX OE : NO K
3690 22:14:45.589658 All Pass.
3691 22:14:45.589739
3692 22:14:45.589802 CH 0, Rank 1
3693 22:14:45.592545 SW Impedance : PASS
3694 22:14:45.592626 DUTY Scan : NO K
3695 22:14:45.596484 ZQ Calibration : PASS
3696 22:14:45.599626 Jitter Meter : NO K
3697 22:14:45.599707 CBT Training : PASS
3698 22:14:45.602637 Write leveling : PASS
3699 22:14:45.606112 RX DQS gating : PASS
3700 22:14:45.606193 RX DQ/DQS(RDDQC) : PASS
3701 22:14:45.609506 TX DQ/DQS : PASS
3702 22:14:45.609589 RX DATLAT : PASS
3703 22:14:45.612794 RX DQ/DQS(Engine): PASS
3704 22:14:45.616041 TX OE : NO K
3705 22:14:45.616122 All Pass.
3706 22:14:45.616184
3707 22:14:45.619138 CH 1, Rank 0
3708 22:14:45.619219 SW Impedance : PASS
3709 22:14:45.622203 DUTY Scan : NO K
3710 22:14:45.622283 ZQ Calibration : PASS
3711 22:14:45.626023 Jitter Meter : NO K
3712 22:14:45.628883 CBT Training : PASS
3713 22:14:45.628963 Write leveling : PASS
3714 22:14:45.632211 RX DQS gating : PASS
3715 22:14:45.635673 RX DQ/DQS(RDDQC) : PASS
3716 22:14:45.635753 TX DQ/DQS : PASS
3717 22:14:45.639111 RX DATLAT : PASS
3718 22:14:45.642444 RX DQ/DQS(Engine): PASS
3719 22:14:45.642524 TX OE : NO K
3720 22:14:45.645426 All Pass.
3721 22:14:45.645507
3722 22:14:45.645571 CH 1, Rank 1
3723 22:14:45.648619 SW Impedance : PASS
3724 22:14:45.648701 DUTY Scan : NO K
3725 22:14:45.651981 ZQ Calibration : PASS
3726 22:14:45.655210 Jitter Meter : NO K
3727 22:14:45.655291 CBT Training : PASS
3728 22:14:45.658665 Write leveling : PASS
3729 22:14:45.662042 RX DQS gating : PASS
3730 22:14:45.662123 RX DQ/DQS(RDDQC) : PASS
3731 22:14:45.665258 TX DQ/DQS : PASS
3732 22:14:45.668656 RX DATLAT : PASS
3733 22:14:45.668738 RX DQ/DQS(Engine): PASS
3734 22:14:45.671878 TX OE : NO K
3735 22:14:45.671961 All Pass.
3736 22:14:45.672025
3737 22:14:45.675242 DramC Write-DBI off
3738 22:14:45.678113 PER_BANK_REFRESH: Hybrid Mode
3739 22:14:45.678194 TX_TRACKING: ON
3740 22:14:45.687959 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3741 22:14:45.691625 [FAST_K] Save calibration result to emmc
3742 22:14:45.694945 dramc_set_vcore_voltage set vcore to 650000
3743 22:14:45.698230 Read voltage for 600, 5
3744 22:14:45.698306 Vio18 = 0
3745 22:14:45.698369 Vcore = 650000
3746 22:14:45.701103 Vdram = 0
3747 22:14:45.701174 Vddq = 0
3748 22:14:45.701239 Vmddr = 0
3749 22:14:45.708050 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3750 22:14:45.711532 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3751 22:14:45.714433 MEM_TYPE=3, freq_sel=19
3752 22:14:45.717936 sv_algorithm_assistance_LP4_1600
3753 22:14:45.721420 ============ PULL DRAM RESETB DOWN ============
3754 22:14:45.724824 ========== PULL DRAM RESETB DOWN end =========
3755 22:14:45.731404 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3756 22:14:45.734824 ===================================
3757 22:14:45.738228 LPDDR4 DRAM CONFIGURATION
3758 22:14:45.740920 ===================================
3759 22:14:45.740991 EX_ROW_EN[0] = 0x0
3760 22:14:45.744515 EX_ROW_EN[1] = 0x0
3761 22:14:45.744587 LP4Y_EN = 0x0
3762 22:14:45.747504 WORK_FSP = 0x0
3763 22:14:45.747575 WL = 0x2
3764 22:14:45.751168 RL = 0x2
3765 22:14:45.751240 BL = 0x2
3766 22:14:45.754182 RPST = 0x0
3767 22:14:45.754252 RD_PRE = 0x0
3768 22:14:45.757607 WR_PRE = 0x1
3769 22:14:45.760889 WR_PST = 0x0
3770 22:14:45.760960 DBI_WR = 0x0
3771 22:14:45.763994 DBI_RD = 0x0
3772 22:14:45.764063 OTF = 0x1
3773 22:14:45.767321 ===================================
3774 22:14:45.770742 ===================================
3775 22:14:45.770868 ANA top config
3776 22:14:45.774035 ===================================
3777 22:14:45.777500 DLL_ASYNC_EN = 0
3778 22:14:45.780433 ALL_SLAVE_EN = 1
3779 22:14:45.783770 NEW_RANK_MODE = 1
3780 22:14:45.787214 DLL_IDLE_MODE = 1
3781 22:14:45.787296 LP45_APHY_COMB_EN = 1
3782 22:14:45.790427 TX_ODT_DIS = 1
3783 22:14:45.794108 NEW_8X_MODE = 1
3784 22:14:45.797118 ===================================
3785 22:14:45.800650 ===================================
3786 22:14:45.803876 data_rate = 1200
3787 22:14:45.807476 CKR = 1
3788 22:14:45.810136 DQ_P2S_RATIO = 8
3789 22:14:45.813486 ===================================
3790 22:14:45.813568 CA_P2S_RATIO = 8
3791 22:14:45.816873 DQ_CA_OPEN = 0
3792 22:14:45.820503 DQ_SEMI_OPEN = 0
3793 22:14:45.823488 CA_SEMI_OPEN = 0
3794 22:14:45.826947 CA_FULL_RATE = 0
3795 22:14:45.830262 DQ_CKDIV4_EN = 1
3796 22:14:45.830342 CA_CKDIV4_EN = 1
3797 22:14:45.833480 CA_PREDIV_EN = 0
3798 22:14:45.836882 PH8_DLY = 0
3799 22:14:45.840241 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3800 22:14:45.843256 DQ_AAMCK_DIV = 4
3801 22:14:45.846528 CA_AAMCK_DIV = 4
3802 22:14:45.846608 CA_ADMCK_DIV = 4
3803 22:14:45.849570 DQ_TRACK_CA_EN = 0
3804 22:14:45.853378 CA_PICK = 600
3805 22:14:45.856408 CA_MCKIO = 600
3806 22:14:45.859560 MCKIO_SEMI = 0
3807 22:14:45.862939 PLL_FREQ = 2288
3808 22:14:45.866675 DQ_UI_PI_RATIO = 32
3809 22:14:45.866772 CA_UI_PI_RATIO = 0
3810 22:14:45.870089 ===================================
3811 22:14:45.872917 ===================================
3812 22:14:45.876389 memory_type:LPDDR4
3813 22:14:45.879604 GP_NUM : 10
3814 22:14:45.879685 SRAM_EN : 1
3815 22:14:45.882466 MD32_EN : 0
3816 22:14:45.886085 ===================================
3817 22:14:45.889291 [ANA_INIT] >>>>>>>>>>>>>>
3818 22:14:45.892682 <<<<<< [CONFIGURE PHASE]: ANA_TX
3819 22:14:45.895892 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3820 22:14:45.899307 ===================================
3821 22:14:45.902497 data_rate = 1200,PCW = 0X5800
3822 22:14:45.905836 ===================================
3823 22:14:45.909070 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3824 22:14:45.912953 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3825 22:14:45.919092 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3826 22:14:45.922257 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3827 22:14:45.925449 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3828 22:14:45.928795 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3829 22:14:45.932191 [ANA_INIT] flow start
3830 22:14:45.935490 [ANA_INIT] PLL >>>>>>>>
3831 22:14:45.935570 [ANA_INIT] PLL <<<<<<<<
3832 22:14:45.938864 [ANA_INIT] MIDPI >>>>>>>>
3833 22:14:45.942261 [ANA_INIT] MIDPI <<<<<<<<
3834 22:14:45.945158 [ANA_INIT] DLL >>>>>>>>
3835 22:14:45.945238 [ANA_INIT] flow end
3836 22:14:45.948563 ============ LP4 DIFF to SE enter ============
3837 22:14:45.955166 ============ LP4 DIFF to SE exit ============
3838 22:14:45.955265 [ANA_INIT] <<<<<<<<<<<<<
3839 22:14:45.958264 [Flow] Enable top DCM control >>>>>
3840 22:14:45.961878 [Flow] Enable top DCM control <<<<<
3841 22:14:45.965090 Enable DLL master slave shuffle
3842 22:14:45.971575 ==============================================================
3843 22:14:45.971656 Gating Mode config
3844 22:14:45.978298 ==============================================================
3845 22:14:45.981712 Config description:
3846 22:14:45.991345 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3847 22:14:45.997958 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3848 22:14:46.001123 SELPH_MODE 0: By rank 1: By Phase
3849 22:14:46.008291 ==============================================================
3850 22:14:46.011261 GAT_TRACK_EN = 1
3851 22:14:46.014265 RX_GATING_MODE = 2
3852 22:14:46.014346 RX_GATING_TRACK_MODE = 2
3853 22:14:46.018209 SELPH_MODE = 1
3854 22:14:46.020881 PICG_EARLY_EN = 1
3855 22:14:46.024486 VALID_LAT_VALUE = 1
3856 22:14:46.030794 ==============================================================
3857 22:14:46.034181 Enter into Gating configuration >>>>
3858 22:14:46.037551 Exit from Gating configuration <<<<
3859 22:14:46.040717 Enter into DVFS_PRE_config >>>>>
3860 22:14:46.050929 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3861 22:14:46.054110 Exit from DVFS_PRE_config <<<<<
3862 22:14:46.057536 Enter into PICG configuration >>>>
3863 22:14:46.060530 Exit from PICG configuration <<<<
3864 22:14:46.063726 [RX_INPUT] configuration >>>>>
3865 22:14:46.066940 [RX_INPUT] configuration <<<<<
3866 22:14:46.070632 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3867 22:14:46.076931 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3868 22:14:46.083477 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3869 22:14:46.090100 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3870 22:14:46.096766 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3871 22:14:46.103416 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3872 22:14:46.106184 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3873 22:14:46.109712 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3874 22:14:46.113164 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3875 22:14:46.119461 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3876 22:14:46.122902 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3877 22:14:46.126166 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3878 22:14:46.129369 ===================================
3879 22:14:46.132665 LPDDR4 DRAM CONFIGURATION
3880 22:14:46.136291 ===================================
3881 22:14:46.136398 EX_ROW_EN[0] = 0x0
3882 22:14:46.139671 EX_ROW_EN[1] = 0x0
3883 22:14:46.142379 LP4Y_EN = 0x0
3884 22:14:46.142462 WORK_FSP = 0x0
3885 22:14:46.146044 WL = 0x2
3886 22:14:46.146150 RL = 0x2
3887 22:14:46.149453 BL = 0x2
3888 22:14:46.149552 RPST = 0x0
3889 22:14:46.152750 RD_PRE = 0x0
3890 22:14:46.152824 WR_PRE = 0x1
3891 22:14:46.155702 WR_PST = 0x0
3892 22:14:46.155772 DBI_WR = 0x0
3893 22:14:46.159169 DBI_RD = 0x0
3894 22:14:46.159250 OTF = 0x1
3895 22:14:46.162579 ===================================
3896 22:14:46.166031 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3897 22:14:46.172071 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3898 22:14:46.175678 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3899 22:14:46.178805 ===================================
3900 22:14:46.182049 LPDDR4 DRAM CONFIGURATION
3901 22:14:46.185447 ===================================
3902 22:14:46.188809 EX_ROW_EN[0] = 0x10
3903 22:14:46.188902 EX_ROW_EN[1] = 0x0
3904 22:14:46.192149 LP4Y_EN = 0x0
3905 22:14:46.192230 WORK_FSP = 0x0
3906 22:14:46.195546 WL = 0x2
3907 22:14:46.195687 RL = 0x2
3908 22:14:46.198616 BL = 0x2
3909 22:14:46.198697 RPST = 0x0
3910 22:14:46.202045 RD_PRE = 0x0
3911 22:14:46.202126 WR_PRE = 0x1
3912 22:14:46.204859 WR_PST = 0x0
3913 22:14:46.204940 DBI_WR = 0x0
3914 22:14:46.208603 DBI_RD = 0x0
3915 22:14:46.208684 OTF = 0x1
3916 22:14:46.211423 ===================================
3917 22:14:46.218559 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3918 22:14:46.223100 nWR fixed to 30
3919 22:14:46.226444 [ModeRegInit_LP4] CH0 RK0
3920 22:14:46.226525 [ModeRegInit_LP4] CH0 RK1
3921 22:14:46.229383 [ModeRegInit_LP4] CH1 RK0
3922 22:14:46.233119 [ModeRegInit_LP4] CH1 RK1
3923 22:14:46.233200 match AC timing 17
3924 22:14:46.239382 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3925 22:14:46.243132 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3926 22:14:46.245977 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3927 22:14:46.252659 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3928 22:14:46.256001 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3929 22:14:46.256083 ==
3930 22:14:46.259544 Dram Type= 6, Freq= 0, CH_0, rank 0
3931 22:14:46.262882 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3932 22:14:46.262967 ==
3933 22:14:46.268946 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3934 22:14:46.275360 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3935 22:14:46.278933 [CA 0] Center 37 (7~67) winsize 61
3936 22:14:46.282375 [CA 1] Center 36 (6~67) winsize 62
3937 22:14:46.285566 [CA 2] Center 35 (5~65) winsize 61
3938 22:14:46.289066 [CA 3] Center 35 (5~65) winsize 61
3939 22:14:46.292098 [CA 4] Center 34 (4~64) winsize 61
3940 22:14:46.295567 [CA 5] Center 34 (4~64) winsize 61
3941 22:14:46.295676
3942 22:14:46.298633 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3943 22:14:46.298714
3944 22:14:46.302226 [CATrainingPosCal] consider 1 rank data
3945 22:14:46.305262 u2DelayCellTimex100 = 270/100 ps
3946 22:14:46.308594 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
3947 22:14:46.311907 CA1 delay=36 (6~67),Diff = 2 PI (19 cell)
3948 22:14:46.315278 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
3949 22:14:46.321651 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
3950 22:14:46.325378 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
3951 22:14:46.328544 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3952 22:14:46.328627
3953 22:14:46.331990 CA PerBit enable=1, Macro0, CA PI delay=34
3954 22:14:46.332111
3955 22:14:46.334795 [CBTSetCACLKResult] CA Dly = 34
3956 22:14:46.334943 CS Dly: 6 (0~37)
3957 22:14:46.335039 ==
3958 22:14:46.338402 Dram Type= 6, Freq= 0, CH_0, rank 1
3959 22:14:46.345173 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3960 22:14:46.345255 ==
3961 22:14:46.348304 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3962 22:14:46.354978 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3963 22:14:46.358244 [CA 0] Center 37 (7~67) winsize 61
3964 22:14:46.361662 [CA 1] Center 36 (6~67) winsize 62
3965 22:14:46.364948 [CA 2] Center 35 (5~65) winsize 61
3966 22:14:46.368307 [CA 3] Center 35 (5~65) winsize 61
3967 22:14:46.371676 [CA 4] Center 34 (4~65) winsize 62
3968 22:14:46.374973 [CA 5] Center 33 (3~64) winsize 62
3969 22:14:46.375055
3970 22:14:46.377923 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3971 22:14:46.378004
3972 22:14:46.381311 [CATrainingPosCal] consider 2 rank data
3973 22:14:46.384582 u2DelayCellTimex100 = 270/100 ps
3974 22:14:46.387798 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
3975 22:14:46.394529 CA1 delay=36 (6~67),Diff = 2 PI (19 cell)
3976 22:14:46.397842 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
3977 22:14:46.401484 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
3978 22:14:46.404400 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
3979 22:14:46.407626 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3980 22:14:46.407706
3981 22:14:46.411076 CA PerBit enable=1, Macro0, CA PI delay=34
3982 22:14:46.411156
3983 22:14:46.414457 [CBTSetCACLKResult] CA Dly = 34
3984 22:14:46.417571 CS Dly: 6 (0~38)
3985 22:14:46.417651
3986 22:14:46.421061 ----->DramcWriteLeveling(PI) begin...
3987 22:14:46.421143 ==
3988 22:14:46.424608 Dram Type= 6, Freq= 0, CH_0, rank 0
3989 22:14:46.427213 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3990 22:14:46.427295 ==
3991 22:14:46.430683 Write leveling (Byte 0): 32 => 32
3992 22:14:46.433926 Write leveling (Byte 1): 31 => 31
3993 22:14:46.437066 DramcWriteLeveling(PI) end<-----
3994 22:14:46.437147
3995 22:14:46.437209 ==
3996 22:14:46.440334 Dram Type= 6, Freq= 0, CH_0, rank 0
3997 22:14:46.444003 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3998 22:14:46.444084 ==
3999 22:14:46.446992 [Gating] SW mode calibration
4000 22:14:46.453816 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4001 22:14:46.460283 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4002 22:14:46.463536 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4003 22:14:46.470143 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4004 22:14:46.473781 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4005 22:14:46.476618 0 9 12 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
4006 22:14:46.483499 0 9 16 | B1->B0 | 3434 2c2c | 1 0 | (1 1) (1 1)
4007 22:14:46.486338 0 9 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4008 22:14:46.489735 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4009 22:14:46.496608 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4010 22:14:46.499450 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4011 22:14:46.503190 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4012 22:14:46.509825 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4013 22:14:46.513403 0 10 12 | B1->B0 | 2424 3030 | 1 0 | (0 0) (0 0)
4014 22:14:46.516535 0 10 16 | B1->B0 | 3535 3939 | 0 1 | (0 0) (0 0)
4015 22:14:46.522636 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4016 22:14:46.525878 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4017 22:14:46.529215 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4018 22:14:46.536044 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4019 22:14:46.539448 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4020 22:14:46.542758 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4021 22:14:46.548799 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4022 22:14:46.552336 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4023 22:14:46.555418 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4024 22:14:46.562070 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4025 22:14:46.565660 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4026 22:14:46.568770 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4027 22:14:46.575650 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4028 22:14:46.578500 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4029 22:14:46.581826 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4030 22:14:46.588554 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4031 22:14:46.591767 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4032 22:14:46.595486 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4033 22:14:46.601914 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4034 22:14:46.605216 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4035 22:14:46.608136 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4036 22:14:46.614556 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4037 22:14:46.618107 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4038 22:14:46.621639 Total UI for P1: 0, mck2ui 16
4039 22:14:46.624763 best dqsien dly found for B0: ( 0, 13, 10)
4040 22:14:46.627974 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4041 22:14:46.631464 Total UI for P1: 0, mck2ui 16
4042 22:14:46.634798 best dqsien dly found for B1: ( 0, 13, 14)
4043 22:14:46.638118 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4044 22:14:46.641510 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4045 22:14:46.641593
4046 22:14:46.647685 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4047 22:14:46.651012 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4048 22:14:46.654381 [Gating] SW calibration Done
4049 22:14:46.654477 ==
4050 22:14:46.658052 Dram Type= 6, Freq= 0, CH_0, rank 0
4051 22:14:46.661234 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4052 22:14:46.661316 ==
4053 22:14:46.661378 RX Vref Scan: 0
4054 22:14:46.661438
4055 22:14:46.664510 RX Vref 0 -> 0, step: 1
4056 22:14:46.664590
4057 22:14:46.667510 RX Delay -230 -> 252, step: 16
4058 22:14:46.671022 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4059 22:14:46.677709 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4060 22:14:46.680561 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4061 22:14:46.684107 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4062 22:14:46.687220 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4063 22:14:46.690538 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4064 22:14:46.697141 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4065 22:14:46.700541 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4066 22:14:46.703933 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4067 22:14:46.706958 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4068 22:14:46.713840 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4069 22:14:46.717028 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4070 22:14:46.719962 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4071 22:14:46.723522 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4072 22:14:46.730241 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4073 22:14:46.733097 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4074 22:14:46.733178 ==
4075 22:14:46.736441 Dram Type= 6, Freq= 0, CH_0, rank 0
4076 22:14:46.739926 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4077 22:14:46.740007 ==
4078 22:14:46.743323 DQS Delay:
4079 22:14:46.743404 DQS0 = 0, DQS1 = 0
4080 22:14:46.746143 DQM Delay:
4081 22:14:46.746223 DQM0 = 38, DQM1 = 29
4082 22:14:46.746286 DQ Delay:
4083 22:14:46.749447 DQ0 =33, DQ1 =41, DQ2 =33, DQ3 =33
4084 22:14:46.752909 DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49
4085 22:14:46.756092 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4086 22:14:46.759704 DQ12 =33, DQ13 =33, DQ14 =41, DQ15 =33
4087 22:14:46.759785
4088 22:14:46.759848
4089 22:14:46.762860 ==
4090 22:14:46.766220 Dram Type= 6, Freq= 0, CH_0, rank 0
4091 22:14:46.769528 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4092 22:14:46.769609 ==
4093 22:14:46.769672
4094 22:14:46.769729
4095 22:14:46.772508 TX Vref Scan disable
4096 22:14:46.772588 == TX Byte 0 ==
4097 22:14:46.779057 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4098 22:14:46.782153 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4099 22:14:46.782234 == TX Byte 1 ==
4100 22:14:46.789390 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4101 22:14:46.792598 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4102 22:14:46.792679 ==
4103 22:14:46.795312 Dram Type= 6, Freq= 0, CH_0, rank 0
4104 22:14:46.798715 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4105 22:14:46.798813 ==
4106 22:14:46.798896
4107 22:14:46.798954
4108 22:14:46.802011 TX Vref Scan disable
4109 22:14:46.805384 == TX Byte 0 ==
4110 22:14:46.808859 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4111 22:14:46.812156 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4112 22:14:46.815506 == TX Byte 1 ==
4113 22:14:46.818651 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4114 22:14:46.821986 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4115 22:14:46.825517
4116 22:14:46.825624 [DATLAT]
4117 22:14:46.825694 Freq=600, CH0 RK0
4118 22:14:46.825753
4119 22:14:46.828666 DATLAT Default: 0x9
4120 22:14:46.828746 0, 0xFFFF, sum = 0
4121 22:14:46.832312 1, 0xFFFF, sum = 0
4122 22:14:46.832397 2, 0xFFFF, sum = 0
4123 22:14:46.835884 3, 0xFFFF, sum = 0
4124 22:14:46.838773 4, 0xFFFF, sum = 0
4125 22:14:46.838913 5, 0xFFFF, sum = 0
4126 22:14:46.841605 6, 0xFFFF, sum = 0
4127 22:14:46.841699 7, 0xFFFF, sum = 0
4128 22:14:46.845122 8, 0x0, sum = 1
4129 22:14:46.845197 9, 0x0, sum = 2
4130 22:14:46.845266 10, 0x0, sum = 3
4131 22:14:46.848593 11, 0x0, sum = 4
4132 22:14:46.848665 best_step = 9
4133 22:14:46.848726
4134 22:14:46.851461 ==
4135 22:14:46.851540 Dram Type= 6, Freq= 0, CH_0, rank 0
4136 22:14:46.858142 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4137 22:14:46.858215 ==
4138 22:14:46.858284 RX Vref Scan: 1
4139 22:14:46.858345
4140 22:14:46.861340 RX Vref 0 -> 0, step: 1
4141 22:14:46.861435
4142 22:14:46.864740 RX Delay -195 -> 252, step: 8
4143 22:14:46.864838
4144 22:14:46.868576 Set Vref, RX VrefLevel [Byte0]: 64
4145 22:14:46.871436 [Byte1]: 58
4146 22:14:46.871559
4147 22:14:46.874817 Final RX Vref Byte 0 = 64 to rank0
4148 22:14:46.877672 Final RX Vref Byte 1 = 58 to rank0
4149 22:14:46.881329 Final RX Vref Byte 0 = 64 to rank1
4150 22:14:46.884588 Final RX Vref Byte 1 = 58 to rank1==
4151 22:14:46.887545 Dram Type= 6, Freq= 0, CH_0, rank 0
4152 22:14:46.890937 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4153 22:14:46.894486 ==
4154 22:14:46.894580 DQS Delay:
4155 22:14:46.894685 DQS0 = 0, DQS1 = 0
4156 22:14:46.897419 DQM Delay:
4157 22:14:46.897488 DQM0 = 35, DQM1 = 27
4158 22:14:46.900836 DQ Delay:
4159 22:14:46.904096 DQ0 =32, DQ1 =36, DQ2 =36, DQ3 =28
4160 22:14:46.907497 DQ4 =36, DQ5 =24, DQ6 =44, DQ7 =44
4161 22:14:46.907580 DQ8 =20, DQ9 =16, DQ10 =28, DQ11 =20
4162 22:14:46.914493 DQ12 =32, DQ13 =32, DQ14 =36, DQ15 =32
4163 22:14:46.914600
4164 22:14:46.914689
4165 22:14:46.920610 [DQSOSCAuto] RK0, (LSB)MR18= 0x3a3a, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 398 ps
4166 22:14:46.923918 CH0 RK0: MR19=808, MR18=3A3A
4167 22:14:46.930258 CH0_RK0: MR19=0x808, MR18=0x3A3A, DQSOSC=398, MR23=63, INC=165, DEC=110
4168 22:14:46.930364
4169 22:14:46.933915 ----->DramcWriteLeveling(PI) begin...
4170 22:14:46.934013 ==
4171 22:14:46.937243 Dram Type= 6, Freq= 0, CH_0, rank 1
4172 22:14:46.940634 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4173 22:14:46.940706 ==
4174 22:14:46.943743 Write leveling (Byte 0): 32 => 32
4175 22:14:46.947065 Write leveling (Byte 1): 32 => 32
4176 22:14:46.950341 DramcWriteLeveling(PI) end<-----
4177 22:14:46.950441
4178 22:14:46.950538 ==
4179 22:14:46.953493 Dram Type= 6, Freq= 0, CH_0, rank 1
4180 22:14:46.956943 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4181 22:14:46.957042 ==
4182 22:14:46.960246 [Gating] SW mode calibration
4183 22:14:46.966888 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4184 22:14:46.973461 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4185 22:14:46.976682 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4186 22:14:46.983348 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4187 22:14:46.986818 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4188 22:14:46.990035 0 9 12 | B1->B0 | 3333 3030 | 0 0 | (0 0) (0 1)
4189 22:14:46.996427 0 9 16 | B1->B0 | 2d2d 2323 | 0 0 | (0 0) (0 0)
4190 22:14:46.999501 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4191 22:14:47.003204 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4192 22:14:47.009692 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4193 22:14:47.013080 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4194 22:14:47.016491 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4195 22:14:47.023104 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4196 22:14:47.025972 0 10 12 | B1->B0 | 2323 3333 | 0 1 | (0 0) (0 0)
4197 22:14:47.029472 0 10 16 | B1->B0 | 3535 4646 | 0 0 | (0 0) (0 0)
4198 22:14:47.035792 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4199 22:14:47.039161 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4200 22:14:47.042733 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4201 22:14:47.049087 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4202 22:14:47.052685 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4203 22:14:47.055700 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4204 22:14:47.062237 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4205 22:14:47.065736 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4206 22:14:47.069000 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4207 22:14:47.075754 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4208 22:14:47.078825 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4209 22:14:47.082120 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4210 22:14:47.088638 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4211 22:14:47.092166 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4212 22:14:47.095709 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4213 22:14:47.101694 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4214 22:14:47.104984 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4215 22:14:47.108646 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4216 22:14:47.114973 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4217 22:14:47.118349 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4218 22:14:47.121740 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4219 22:14:47.128672 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4220 22:14:47.131635 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4221 22:14:47.135264 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4222 22:14:47.137939 Total UI for P1: 0, mck2ui 16
4223 22:14:47.141444 best dqsien dly found for B0: ( 0, 13, 12)
4224 22:14:47.147918 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4225 22:14:47.148001 Total UI for P1: 0, mck2ui 16
4226 22:14:47.154764 best dqsien dly found for B1: ( 0, 13, 16)
4227 22:14:47.158212 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4228 22:14:47.161721 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4229 22:14:47.161797
4230 22:14:47.164936 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4231 22:14:47.167764 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4232 22:14:47.171255 [Gating] SW calibration Done
4233 22:14:47.171336 ==
4234 22:14:47.174609 Dram Type= 6, Freq= 0, CH_0, rank 1
4235 22:14:47.177927 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4236 22:14:47.178009 ==
4237 22:14:47.181191 RX Vref Scan: 0
4238 22:14:47.181273
4239 22:14:47.181337 RX Vref 0 -> 0, step: 1
4240 22:14:47.184420
4241 22:14:47.184501 RX Delay -230 -> 252, step: 16
4242 22:14:47.191074 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4243 22:14:47.194369 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4244 22:14:47.197241 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4245 22:14:47.200512 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4246 22:14:47.208131 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4247 22:14:47.210736 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4248 22:14:47.213888 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4249 22:14:47.217454 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4250 22:14:47.220526 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4251 22:14:47.227142 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4252 22:14:47.230337 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4253 22:14:47.233726 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4254 22:14:47.237122 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4255 22:14:47.243458 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4256 22:14:47.246790 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4257 22:14:47.250302 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4258 22:14:47.250400 ==
4259 22:14:47.253616 Dram Type= 6, Freq= 0, CH_0, rank 1
4260 22:14:47.260082 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4261 22:14:47.260179 ==
4262 22:14:47.260272 DQS Delay:
4263 22:14:47.263165 DQS0 = 0, DQS1 = 0
4264 22:14:47.263263 DQM Delay:
4265 22:14:47.263357 DQM0 = 36, DQM1 = 27
4266 22:14:47.266832 DQ Delay:
4267 22:14:47.269987 DQ0 =33, DQ1 =33, DQ2 =33, DQ3 =33
4268 22:14:47.273363 DQ4 =33, DQ5 =25, DQ6 =49, DQ7 =49
4269 22:14:47.276420 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4270 22:14:47.279809 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4271 22:14:47.279906
4272 22:14:47.280000
4273 22:14:47.280073 ==
4274 22:14:47.282959 Dram Type= 6, Freq= 0, CH_0, rank 1
4275 22:14:47.286726 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4276 22:14:47.286811 ==
4277 22:14:47.286891
4278 22:14:47.286965
4279 22:14:47.290035 TX Vref Scan disable
4280 22:14:47.290117 == TX Byte 0 ==
4281 22:14:47.296544 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4282 22:14:47.299854 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4283 22:14:47.303311 == TX Byte 1 ==
4284 22:14:47.306129 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4285 22:14:47.309567 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4286 22:14:47.309650 ==
4287 22:14:47.312900 Dram Type= 6, Freq= 0, CH_0, rank 1
4288 22:14:47.316287 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4289 22:14:47.319690 ==
4290 22:14:47.319771
4291 22:14:47.319835
4292 22:14:47.319894 TX Vref Scan disable
4293 22:14:47.323356 == TX Byte 0 ==
4294 22:14:47.326474 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4295 22:14:47.333034 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4296 22:14:47.333115 == TX Byte 1 ==
4297 22:14:47.336376 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4298 22:14:47.343108 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4299 22:14:47.343188
4300 22:14:47.343250 [DATLAT]
4301 22:14:47.343307 Freq=600, CH0 RK1
4302 22:14:47.343363
4303 22:14:47.346469 DATLAT Default: 0x9
4304 22:14:47.346549 0, 0xFFFF, sum = 0
4305 22:14:47.349801 1, 0xFFFF, sum = 0
4306 22:14:47.353125 2, 0xFFFF, sum = 0
4307 22:14:47.353205 3, 0xFFFF, sum = 0
4308 22:14:47.356015 4, 0xFFFF, sum = 0
4309 22:14:47.356116 5, 0xFFFF, sum = 0
4310 22:14:47.359364 6, 0xFFFF, sum = 0
4311 22:14:47.359445 7, 0xFFFF, sum = 0
4312 22:14:47.362607 8, 0x0, sum = 1
4313 22:14:47.362691 9, 0x0, sum = 2
4314 22:14:47.362756 10, 0x0, sum = 3
4315 22:14:47.366014 11, 0x0, sum = 4
4316 22:14:47.366095 best_step = 9
4317 22:14:47.366156
4318 22:14:47.369312 ==
4319 22:14:47.369391 Dram Type= 6, Freq= 0, CH_0, rank 1
4320 22:14:47.376136 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4321 22:14:47.376233 ==
4322 22:14:47.376296 RX Vref Scan: 0
4323 22:14:47.376354
4324 22:14:47.379308 RX Vref 0 -> 0, step: 1
4325 22:14:47.379391
4326 22:14:47.382620 RX Delay -195 -> 252, step: 8
4327 22:14:47.389287 iDelay=205, Bit 0, Center 32 (-123 ~ 188) 312
4328 22:14:47.392505 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4329 22:14:47.395903 iDelay=205, Bit 2, Center 32 (-123 ~ 188) 312
4330 22:14:47.399027 iDelay=205, Bit 3, Center 28 (-131 ~ 188) 320
4331 22:14:47.402362 iDelay=205, Bit 4, Center 32 (-123 ~ 188) 312
4332 22:14:47.409092 iDelay=205, Bit 5, Center 20 (-139 ~ 180) 320
4333 22:14:47.412831 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4334 22:14:47.415767 iDelay=205, Bit 7, Center 44 (-115 ~ 204) 320
4335 22:14:47.419061 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4336 22:14:47.425953 iDelay=205, Bit 9, Center 12 (-147 ~ 172) 320
4337 22:14:47.428595 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4338 22:14:47.431983 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4339 22:14:47.435240 iDelay=205, Bit 12, Center 32 (-131 ~ 196) 328
4340 22:14:47.442027 iDelay=205, Bit 13, Center 32 (-131 ~ 196) 328
4341 22:14:47.445440 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4342 22:14:47.448347 iDelay=205, Bit 15, Center 32 (-131 ~ 196) 328
4343 22:14:47.448415 ==
4344 22:14:47.451772 Dram Type= 6, Freq= 0, CH_0, rank 1
4345 22:14:47.455031 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4346 22:14:47.458627 ==
4347 22:14:47.458721 DQS Delay:
4348 22:14:47.458811 DQS0 = 0, DQS1 = 0
4349 22:14:47.461139 DQM Delay:
4350 22:14:47.461205 DQM0 = 33, DQM1 = 26
4351 22:14:47.465210 DQ Delay:
4352 22:14:47.468088 DQ0 =32, DQ1 =36, DQ2 =32, DQ3 =28
4353 22:14:47.471514 DQ4 =32, DQ5 =20, DQ6 =44, DQ7 =44
4354 22:14:47.474642 DQ8 =20, DQ9 =12, DQ10 =28, DQ11 =20
4355 22:14:47.477781 DQ12 =32, DQ13 =32, DQ14 =36, DQ15 =32
4356 22:14:47.477861
4357 22:14:47.477923
4358 22:14:47.484536 [DQSOSCAuto] RK1, (LSB)MR18= 0x6d3b, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 389 ps
4359 22:14:47.487941 CH0 RK1: MR19=808, MR18=6D3B
4360 22:14:47.494556 CH0_RK1: MR19=0x808, MR18=0x6D3B, DQSOSC=389, MR23=63, INC=173, DEC=115
4361 22:14:47.497315 [RxdqsGatingPostProcess] freq 600
4362 22:14:47.500821 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4363 22:14:47.507250 Pre-setting of DQS Precalculation
4364 22:14:47.510695 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4365 22:14:47.510793 ==
4366 22:14:47.514010 Dram Type= 6, Freq= 0, CH_1, rank 0
4367 22:14:47.517313 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4368 22:14:47.517381 ==
4369 22:14:47.524064 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4370 22:14:47.530047 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4371 22:14:47.533359 [CA 0] Center 35 (5~66) winsize 62
4372 22:14:47.537429 [CA 1] Center 35 (5~66) winsize 62
4373 22:14:47.540051 [CA 2] Center 34 (4~65) winsize 62
4374 22:14:47.543199 [CA 3] Center 34 (4~65) winsize 62
4375 22:14:47.546796 [CA 4] Center 34 (4~65) winsize 62
4376 22:14:47.549842 [CA 5] Center 33 (3~64) winsize 62
4377 22:14:47.549923
4378 22:14:47.553064 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4379 22:14:47.553145
4380 22:14:47.556494 [CATrainingPosCal] consider 1 rank data
4381 22:14:47.559840 u2DelayCellTimex100 = 270/100 ps
4382 22:14:47.563594 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4383 22:14:47.566687 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4384 22:14:47.569550 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4385 22:14:47.572997 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4386 22:14:47.576396 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4387 22:14:47.582824 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4388 22:14:47.582974
4389 22:14:47.586265 CA PerBit enable=1, Macro0, CA PI delay=33
4390 22:14:47.586346
4391 22:14:47.589422 [CBTSetCACLKResult] CA Dly = 33
4392 22:14:47.589503 CS Dly: 5 (0~36)
4393 22:14:47.589566 ==
4394 22:14:47.592581 Dram Type= 6, Freq= 0, CH_1, rank 1
4395 22:14:47.599626 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4396 22:14:47.599708 ==
4397 22:14:47.602803 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4398 22:14:47.609678 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4399 22:14:47.612619 [CA 0] Center 36 (6~66) winsize 61
4400 22:14:47.616161 [CA 1] Center 36 (6~67) winsize 62
4401 22:14:47.619478 [CA 2] Center 34 (4~65) winsize 62
4402 22:14:47.622766 [CA 3] Center 34 (3~65) winsize 63
4403 22:14:47.626228 [CA 4] Center 34 (4~65) winsize 62
4404 22:14:47.629506 [CA 5] Center 33 (3~64) winsize 62
4405 22:14:47.629586
4406 22:14:47.632466 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4407 22:14:47.632547
4408 22:14:47.635674 [CATrainingPosCal] consider 2 rank data
4409 22:14:47.638997 u2DelayCellTimex100 = 270/100 ps
4410 22:14:47.642563 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4411 22:14:47.645980 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4412 22:14:47.652080 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4413 22:14:47.655732 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4414 22:14:47.658738 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4415 22:14:47.662483 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4416 22:14:47.662580
4417 22:14:47.665505 CA PerBit enable=1, Macro0, CA PI delay=33
4418 22:14:47.665586
4419 22:14:47.668792 [CBTSetCACLKResult] CA Dly = 33
4420 22:14:47.668925 CS Dly: 5 (0~37)
4421 22:14:47.672161
4422 22:14:47.675480 ----->DramcWriteLeveling(PI) begin...
4423 22:14:47.675561 ==
4424 22:14:47.678986 Dram Type= 6, Freq= 0, CH_1, rank 0
4425 22:14:47.681921 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4426 22:14:47.682018 ==
4427 22:14:47.685434 Write leveling (Byte 0): 29 => 29
4428 22:14:47.688291 Write leveling (Byte 1): 33 => 33
4429 22:14:47.691672 DramcWriteLeveling(PI) end<-----
4430 22:14:47.691820
4431 22:14:47.691924 ==
4432 22:14:47.695113 Dram Type= 6, Freq= 0, CH_1, rank 0
4433 22:14:47.698426 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4434 22:14:47.698524 ==
4435 22:14:47.701749 [Gating] SW mode calibration
4436 22:14:47.708425 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4437 22:14:47.714699 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4438 22:14:47.717747 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4439 22:14:47.721095 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4440 22:14:47.727867 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4441 22:14:47.731224 0 9 12 | B1->B0 | 3333 3232 | 1 0 | (1 1) (0 0)
4442 22:14:47.734467 0 9 16 | B1->B0 | 2626 2626 | 1 0 | (1 0) (0 0)
4443 22:14:47.741097 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4444 22:14:47.744597 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4445 22:14:47.747484 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4446 22:14:47.754666 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4447 22:14:47.757834 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4448 22:14:47.760861 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4449 22:14:47.767674 0 10 12 | B1->B0 | 3030 3131 | 0 1 | (0 0) (0 0)
4450 22:14:47.770823 0 10 16 | B1->B0 | 4444 4444 | 0 0 | (0 0) (0 0)
4451 22:14:47.774163 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4452 22:14:47.780896 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4453 22:14:47.783720 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4454 22:14:47.787073 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4455 22:14:47.793879 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4456 22:14:47.796993 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4457 22:14:47.800061 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4458 22:14:47.806995 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4459 22:14:47.810101 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4460 22:14:47.813486 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4461 22:14:47.820392 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4462 22:14:47.823475 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4463 22:14:47.826672 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4464 22:14:47.832965 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4465 22:14:47.836632 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4466 22:14:47.839873 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4467 22:14:47.846486 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4468 22:14:47.849280 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4469 22:14:47.852695 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4470 22:14:47.859477 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4471 22:14:47.862808 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4472 22:14:47.865689 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4473 22:14:47.872584 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4474 22:14:47.875934 Total UI for P1: 0, mck2ui 16
4475 22:14:47.878984 best dqsien dly found for B0: ( 0, 13, 10)
4476 22:14:47.882182 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4477 22:14:47.885546 Total UI for P1: 0, mck2ui 16
4478 22:14:47.888900 best dqsien dly found for B1: ( 0, 13, 14)
4479 22:14:47.892318 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4480 22:14:47.895692 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4481 22:14:47.895784
4482 22:14:47.899227 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4483 22:14:47.905728 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4484 22:14:47.905831 [Gating] SW calibration Done
4485 22:14:47.905920 ==
4486 22:14:47.909085 Dram Type= 6, Freq= 0, CH_1, rank 0
4487 22:14:47.915528 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4488 22:14:47.915612 ==
4489 22:14:47.915678 RX Vref Scan: 0
4490 22:14:47.915738
4491 22:14:47.918981 RX Vref 0 -> 0, step: 1
4492 22:14:47.919069
4493 22:14:47.922089 RX Delay -230 -> 252, step: 16
4494 22:14:47.925352 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4495 22:14:47.928717 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4496 22:14:47.935137 iDelay=218, Bit 2, Center 25 (-150 ~ 201) 352
4497 22:14:47.938628 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4498 22:14:47.941593 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4499 22:14:47.944837 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4500 22:14:47.951540 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4501 22:14:47.955050 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4502 22:14:47.958195 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4503 22:14:47.961801 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4504 22:14:47.964883 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4505 22:14:47.971541 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4506 22:14:47.974785 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4507 22:14:47.977908 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4508 22:14:47.984743 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4509 22:14:47.987863 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4510 22:14:47.987944 ==
4511 22:14:47.990969 Dram Type= 6, Freq= 0, CH_1, rank 0
4512 22:14:47.994466 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4513 22:14:47.994548 ==
4514 22:14:47.997833 DQS Delay:
4515 22:14:47.997914 DQS0 = 0, DQS1 = 0
4516 22:14:47.997977 DQM Delay:
4517 22:14:48.001220 DQM0 = 38, DQM1 = 28
4518 22:14:48.001325 DQ Delay:
4519 22:14:48.004088 DQ0 =49, DQ1 =33, DQ2 =25, DQ3 =33
4520 22:14:48.007339 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4521 22:14:48.010658 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4522 22:14:48.014208 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4523 22:14:48.014305
4524 22:14:48.014383
4525 22:14:48.014441 ==
4526 22:14:48.017318 Dram Type= 6, Freq= 0, CH_1, rank 0
4527 22:14:48.024476 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4528 22:14:48.024558 ==
4529 22:14:48.024621
4530 22:14:48.024677
4531 22:14:48.024733 TX Vref Scan disable
4532 22:14:48.027577 == TX Byte 0 ==
4533 22:14:48.030716 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4534 22:14:48.037229 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4535 22:14:48.037310 == TX Byte 1 ==
4536 22:14:48.040661 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4537 22:14:48.047307 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4538 22:14:48.047388 ==
4539 22:14:48.050641 Dram Type= 6, Freq= 0, CH_1, rank 0
4540 22:14:48.054083 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4541 22:14:48.054164 ==
4542 22:14:48.054226
4543 22:14:48.054283
4544 22:14:48.057509 TX Vref Scan disable
4545 22:14:48.060225 == TX Byte 0 ==
4546 22:14:48.063722 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4547 22:14:48.067202 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4548 22:14:48.070442 == TX Byte 1 ==
4549 22:14:48.073776 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4550 22:14:48.077214 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4551 22:14:48.077299
4552 22:14:48.079998 [DATLAT]
4553 22:14:48.080079 Freq=600, CH1 RK0
4554 22:14:48.080143
4555 22:14:48.083853 DATLAT Default: 0x9
4556 22:14:48.083923 0, 0xFFFF, sum = 0
4557 22:14:48.086631 1, 0xFFFF, sum = 0
4558 22:14:48.086701 2, 0xFFFF, sum = 0
4559 22:14:48.090330 3, 0xFFFF, sum = 0
4560 22:14:48.090412 4, 0xFFFF, sum = 0
4561 22:14:48.093404 5, 0xFFFF, sum = 0
4562 22:14:48.093478 6, 0xFFFF, sum = 0
4563 22:14:48.096387 7, 0xFFFF, sum = 0
4564 22:14:48.096471 8, 0x0, sum = 1
4565 22:14:48.100208 9, 0x0, sum = 2
4566 22:14:48.100284 10, 0x0, sum = 3
4567 22:14:48.103084 11, 0x0, sum = 4
4568 22:14:48.103157 best_step = 9
4569 22:14:48.103222
4570 22:14:48.103287 ==
4571 22:14:48.106424 Dram Type= 6, Freq= 0, CH_1, rank 0
4572 22:14:48.109884 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4573 22:14:48.113086 ==
4574 22:14:48.113156 RX Vref Scan: 1
4575 22:14:48.113222
4576 22:14:48.116505 RX Vref 0 -> 0, step: 1
4577 22:14:48.116571
4578 22:14:48.119795 RX Delay -195 -> 252, step: 8
4579 22:14:48.119861
4580 22:14:48.123009 Set Vref, RX VrefLevel [Byte0]: 53
4581 22:14:48.126179 [Byte1]: 47
4582 22:14:48.126333
4583 22:14:48.129455 Final RX Vref Byte 0 = 53 to rank0
4584 22:14:48.132630 Final RX Vref Byte 1 = 47 to rank0
4585 22:14:48.136369 Final RX Vref Byte 0 = 53 to rank1
4586 22:14:48.139448 Final RX Vref Byte 1 = 47 to rank1==
4587 22:14:48.142741 Dram Type= 6, Freq= 0, CH_1, rank 0
4588 22:14:48.146089 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4589 22:14:48.146162 ==
4590 22:14:48.149489 DQS Delay:
4591 22:14:48.149564 DQS0 = 0, DQS1 = 0
4592 22:14:48.149624 DQM Delay:
4593 22:14:48.152433 DQM0 = 37, DQM1 = 29
4594 22:14:48.152518 DQ Delay:
4595 22:14:48.156081 DQ0 =44, DQ1 =32, DQ2 =24, DQ3 =36
4596 22:14:48.159482 DQ4 =36, DQ5 =44, DQ6 =52, DQ7 =32
4597 22:14:48.162313 DQ8 =16, DQ9 =20, DQ10 =28, DQ11 =24
4598 22:14:48.165668 DQ12 =40, DQ13 =36, DQ14 =36, DQ15 =36
4599 22:14:48.165743
4600 22:14:48.165809
4601 22:14:48.175556 [DQSOSCAuto] RK0, (LSB)MR18= 0x202c, (MSB)MR19= 0x808, tDQSOscB0 = 401 ps tDQSOscB1 = 403 ps
4602 22:14:48.178846 CH1 RK0: MR19=808, MR18=202C
4603 22:14:48.182266 CH1_RK0: MR19=0x808, MR18=0x202C, DQSOSC=401, MR23=63, INC=163, DEC=108
4604 22:14:48.185447
4605 22:14:48.188873 ----->DramcWriteLeveling(PI) begin...
4606 22:14:48.188947 ==
4607 22:14:48.192272 Dram Type= 6, Freq= 0, CH_1, rank 1
4608 22:14:48.195515 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4609 22:14:48.195590 ==
4610 22:14:48.198673 Write leveling (Byte 0): 29 => 29
4611 22:14:48.201761 Write leveling (Byte 1): 29 => 29
4612 22:14:48.204980 DramcWriteLeveling(PI) end<-----
4613 22:14:48.205056
4614 22:14:48.205120 ==
4615 22:14:48.208758 Dram Type= 6, Freq= 0, CH_1, rank 1
4616 22:14:48.211530 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4617 22:14:48.211602 ==
4618 22:14:48.214952 [Gating] SW mode calibration
4619 22:14:48.221568 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4620 22:14:48.228075 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4621 22:14:48.231399 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4622 22:14:48.234866 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4623 22:14:48.241175 0 9 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
4624 22:14:48.244523 0 9 12 | B1->B0 | 3434 2929 | 0 0 | (0 1) (1 1)
4625 22:14:48.248129 0 9 16 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
4626 22:14:48.254390 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4627 22:14:48.257921 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4628 22:14:48.261038 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4629 22:14:48.267715 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4630 22:14:48.271113 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4631 22:14:48.274581 0 10 8 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
4632 22:14:48.280767 0 10 12 | B1->B0 | 3030 3a3a | 0 0 | (0 0) (1 1)
4633 22:14:48.284122 0 10 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
4634 22:14:48.287370 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4635 22:14:48.294226 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4636 22:14:48.297549 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4637 22:14:48.300991 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4638 22:14:48.307452 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4639 22:14:48.310497 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4640 22:14:48.314107 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4641 22:14:48.320398 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4642 22:14:48.323816 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4643 22:14:48.327398 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4644 22:14:48.333593 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4645 22:14:48.336981 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4646 22:14:48.339898 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4647 22:14:48.346749 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4648 22:14:48.349923 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4649 22:14:48.353583 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4650 22:14:48.359763 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4651 22:14:48.363489 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4652 22:14:48.366591 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4653 22:14:48.372867 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4654 22:14:48.376670 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4655 22:14:48.379494 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4656 22:14:48.386349 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4657 22:14:48.389497 Total UI for P1: 0, mck2ui 16
4658 22:14:48.392884 best dqsien dly found for B1: ( 0, 13, 10)
4659 22:14:48.396283 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4660 22:14:48.399689 Total UI for P1: 0, mck2ui 16
4661 22:14:48.402452 best dqsien dly found for B0: ( 0, 13, 12)
4662 22:14:48.405788 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4663 22:14:48.409117 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4664 22:14:48.409220
4665 22:14:48.412334 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4666 22:14:48.419144 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4667 22:14:48.419264 [Gating] SW calibration Done
4668 22:14:48.419361 ==
4669 22:14:48.422716 Dram Type= 6, Freq= 0, CH_1, rank 1
4670 22:14:48.429093 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4671 22:14:48.429197 ==
4672 22:14:48.429305 RX Vref Scan: 0
4673 22:14:48.429395
4674 22:14:48.432646 RX Vref 0 -> 0, step: 1
4675 22:14:48.432745
4676 22:14:48.435522 RX Delay -230 -> 252, step: 16
4677 22:14:48.439134 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4678 22:14:48.442301 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4679 22:14:48.448817 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4680 22:14:48.452036 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4681 22:14:48.455466 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4682 22:14:48.458710 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4683 22:14:48.461936 iDelay=218, Bit 6, Center 41 (-134 ~ 217) 352
4684 22:14:48.469006 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4685 22:14:48.472285 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4686 22:14:48.475189 iDelay=218, Bit 9, Center 25 (-150 ~ 201) 352
4687 22:14:48.478622 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4688 22:14:48.485088 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4689 22:14:48.488182 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4690 22:14:48.491614 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4691 22:14:48.498205 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4692 22:14:48.501082 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4693 22:14:48.501158 ==
4694 22:14:48.504556 Dram Type= 6, Freq= 0, CH_1, rank 1
4695 22:14:48.507756 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4696 22:14:48.507833 ==
4697 22:14:48.511096 DQS Delay:
4698 22:14:48.511202 DQS0 = 0, DQS1 = 0
4699 22:14:48.511293 DQM Delay:
4700 22:14:48.514661 DQM0 = 35, DQM1 = 29
4701 22:14:48.514756 DQ Delay:
4702 22:14:48.517879 DQ0 =33, DQ1 =33, DQ2 =25, DQ3 =33
4703 22:14:48.521021 DQ4 =33, DQ5 =49, DQ6 =41, DQ7 =33
4704 22:14:48.524598 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =25
4705 22:14:48.527398 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4706 22:14:48.527499
4707 22:14:48.527589
4708 22:14:48.527690 ==
4709 22:14:48.531007 Dram Type= 6, Freq= 0, CH_1, rank 1
4710 22:14:48.537660 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4711 22:14:48.537763 ==
4712 22:14:48.537859
4713 22:14:48.537958
4714 22:14:48.538044 TX Vref Scan disable
4715 22:14:48.541199 == TX Byte 0 ==
4716 22:14:48.544583 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4717 22:14:48.551103 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4718 22:14:48.551211 == TX Byte 1 ==
4719 22:14:48.554426 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4720 22:14:48.560898 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4721 22:14:48.561009 ==
4722 22:14:48.564531 Dram Type= 6, Freq= 0, CH_1, rank 1
4723 22:14:48.567655 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4724 22:14:48.567767 ==
4725 22:14:48.567859
4726 22:14:48.567945
4727 22:14:48.570576 TX Vref Scan disable
4728 22:14:48.573934 == TX Byte 0 ==
4729 22:14:48.577373 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4730 22:14:48.580869 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4731 22:14:48.584107 == TX Byte 1 ==
4732 22:14:48.587434 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4733 22:14:48.590727 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4734 22:14:48.590855
4735 22:14:48.590964 [DATLAT]
4736 22:14:48.593829 Freq=600, CH1 RK1
4737 22:14:48.593923
4738 22:14:48.597348 DATLAT Default: 0x9
4739 22:14:48.597446 0, 0xFFFF, sum = 0
4740 22:14:48.600978 1, 0xFFFF, sum = 0
4741 22:14:48.601087 2, 0xFFFF, sum = 0
4742 22:14:48.603938 3, 0xFFFF, sum = 0
4743 22:14:48.604050 4, 0xFFFF, sum = 0
4744 22:14:48.607013 5, 0xFFFF, sum = 0
4745 22:14:48.607113 6, 0xFFFF, sum = 0
4746 22:14:48.610263 7, 0xFFFF, sum = 0
4747 22:14:48.610364 8, 0x0, sum = 1
4748 22:14:48.613565 9, 0x0, sum = 2
4749 22:14:48.613649 10, 0x0, sum = 3
4750 22:14:48.617345 11, 0x0, sum = 4
4751 22:14:48.617427 best_step = 9
4752 22:14:48.617491
4753 22:14:48.617550 ==
4754 22:14:48.620321 Dram Type= 6, Freq= 0, CH_1, rank 1
4755 22:14:48.623754 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4756 22:14:48.623837 ==
4757 22:14:48.626609 RX Vref Scan: 0
4758 22:14:48.626691
4759 22:14:48.630412 RX Vref 0 -> 0, step: 1
4760 22:14:48.630493
4761 22:14:48.630556 RX Delay -195 -> 252, step: 8
4762 22:14:48.638627 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4763 22:14:48.641648 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4764 22:14:48.644945 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4765 22:14:48.648259 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4766 22:14:48.654937 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4767 22:14:48.658572 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4768 22:14:48.661411 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4769 22:14:48.664494 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4770 22:14:48.671372 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4771 22:14:48.674560 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4772 22:14:48.678017 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4773 22:14:48.681272 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4774 22:14:48.687722 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4775 22:14:48.691174 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4776 22:14:48.694509 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4777 22:14:48.697419 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4778 22:14:48.697501 ==
4779 22:14:48.700622 Dram Type= 6, Freq= 0, CH_1, rank 1
4780 22:14:48.707471 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4781 22:14:48.707556 ==
4782 22:14:48.707620 DQS Delay:
4783 22:14:48.711238 DQS0 = 0, DQS1 = 0
4784 22:14:48.711333 DQM Delay:
4785 22:14:48.711421 DQM0 = 36, DQM1 = 29
4786 22:14:48.714213 DQ Delay:
4787 22:14:48.717702 DQ0 =40, DQ1 =32, DQ2 =24, DQ3 =32
4788 22:14:48.720807 DQ4 =36, DQ5 =48, DQ6 =44, DQ7 =32
4789 22:14:48.724215 DQ8 =20, DQ9 =20, DQ10 =32, DQ11 =20
4790 22:14:48.727716 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4791 22:14:48.727788
4792 22:14:48.727847
4793 22:14:48.734238 [DQSOSCAuto] RK1, (LSB)MR18= 0x3b5c, (MSB)MR19= 0x808, tDQSOscB0 = 392 ps tDQSOscB1 = 398 ps
4794 22:14:48.737104 CH1 RK1: MR19=808, MR18=3B5C
4795 22:14:48.743621 CH1_RK1: MR19=0x808, MR18=0x3B5C, DQSOSC=392, MR23=63, INC=170, DEC=113
4796 22:14:48.747215 [RxdqsGatingPostProcess] freq 600
4797 22:14:48.750679 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4798 22:14:48.753966 Pre-setting of DQS Precalculation
4799 22:14:48.760267 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4800 22:14:48.767133 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4801 22:14:48.773340 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4802 22:14:48.773440
4803 22:14:48.773531
4804 22:14:48.776988 [Calibration Summary] 1200 Mbps
4805 22:14:48.780227 CH 0, Rank 0
4806 22:14:48.780306 SW Impedance : PASS
4807 22:14:48.783596 DUTY Scan : NO K
4808 22:14:48.783666 ZQ Calibration : PASS
4809 22:14:48.787119 Jitter Meter : NO K
4810 22:14:48.789847 CBT Training : PASS
4811 22:14:48.789914 Write leveling : PASS
4812 22:14:48.793146 RX DQS gating : PASS
4813 22:14:48.796595 RX DQ/DQS(RDDQC) : PASS
4814 22:14:48.796667 TX DQ/DQS : PASS
4815 22:14:48.800010 RX DATLAT : PASS
4816 22:14:48.803028 RX DQ/DQS(Engine): PASS
4817 22:14:48.803104 TX OE : NO K
4818 22:14:48.806370 All Pass.
4819 22:14:48.806466
4820 22:14:48.806555 CH 0, Rank 1
4821 22:14:48.809692 SW Impedance : PASS
4822 22:14:48.809758 DUTY Scan : NO K
4823 22:14:48.813016 ZQ Calibration : PASS
4824 22:14:48.816485 Jitter Meter : NO K
4825 22:14:48.816552 CBT Training : PASS
4826 22:14:48.819740 Write leveling : PASS
4827 22:14:48.823053 RX DQS gating : PASS
4828 22:14:48.823154 RX DQ/DQS(RDDQC) : PASS
4829 22:14:48.826417 TX DQ/DQS : PASS
4830 22:14:48.829717 RX DATLAT : PASS
4831 22:14:48.829788 RX DQ/DQS(Engine): PASS
4832 22:14:48.833011 TX OE : NO K
4833 22:14:48.833079 All Pass.
4834 22:14:48.833138
4835 22:14:48.836514 CH 1, Rank 0
4836 22:14:48.836581 SW Impedance : PASS
4837 22:14:48.839656 DUTY Scan : NO K
4838 22:14:48.842539 ZQ Calibration : PASS
4839 22:14:48.842623 Jitter Meter : NO K
4840 22:14:48.846313 CBT Training : PASS
4841 22:14:48.849413 Write leveling : PASS
4842 22:14:48.849495 RX DQS gating : PASS
4843 22:14:48.853165 RX DQ/DQS(RDDQC) : PASS
4844 22:14:48.853248 TX DQ/DQS : PASS
4845 22:14:48.856102 RX DATLAT : PASS
4846 22:14:48.859145 RX DQ/DQS(Engine): PASS
4847 22:14:48.859249 TX OE : NO K
4848 22:14:48.862789 All Pass.
4849 22:14:48.862911
4850 22:14:48.862993 CH 1, Rank 1
4851 22:14:48.865573 SW Impedance : PASS
4852 22:14:48.865656 DUTY Scan : NO K
4853 22:14:48.869270 ZQ Calibration : PASS
4854 22:14:48.872482 Jitter Meter : NO K
4855 22:14:48.872565 CBT Training : PASS
4856 22:14:48.875516 Write leveling : PASS
4857 22:14:48.879121 RX DQS gating : PASS
4858 22:14:48.879234 RX DQ/DQS(RDDQC) : PASS
4859 22:14:48.882419 TX DQ/DQS : PASS
4860 22:14:48.885636 RX DATLAT : PASS
4861 22:14:48.885718 RX DQ/DQS(Engine): PASS
4862 22:14:48.889098 TX OE : NO K
4863 22:14:48.889181 All Pass.
4864 22:14:48.889265
4865 22:14:48.892442 DramC Write-DBI off
4866 22:14:48.895847 PER_BANK_REFRESH: Hybrid Mode
4867 22:14:48.895930 TX_TRACKING: ON
4868 22:14:48.905284 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4869 22:14:48.908603 [FAST_K] Save calibration result to emmc
4870 22:14:48.912757 dramc_set_vcore_voltage set vcore to 662500
4871 22:14:48.915630 Read voltage for 933, 3
4872 22:14:48.915712 Vio18 = 0
4873 22:14:48.915794 Vcore = 662500
4874 22:14:48.918485 Vdram = 0
4875 22:14:48.918567 Vddq = 0
4876 22:14:48.918667 Vmddr = 0
4877 22:14:48.925184 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4878 22:14:48.928421 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4879 22:14:48.931687 MEM_TYPE=3, freq_sel=17
4880 22:14:48.935048 sv_algorithm_assistance_LP4_1600
4881 22:14:48.938451 ============ PULL DRAM RESETB DOWN ============
4882 22:14:48.945251 ========== PULL DRAM RESETB DOWN end =========
4883 22:14:48.947972 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4884 22:14:48.951374 ===================================
4885 22:14:48.954609 LPDDR4 DRAM CONFIGURATION
4886 22:14:48.957837 ===================================
4887 22:14:48.957945 EX_ROW_EN[0] = 0x0
4888 22:14:48.961858 EX_ROW_EN[1] = 0x0
4889 22:14:48.961941 LP4Y_EN = 0x0
4890 22:14:48.964688 WORK_FSP = 0x0
4891 22:14:48.964771 WL = 0x3
4892 22:14:48.967730 RL = 0x3
4893 22:14:48.971061 BL = 0x2
4894 22:14:48.971144 RPST = 0x0
4895 22:14:48.974505 RD_PRE = 0x0
4896 22:14:48.974588 WR_PRE = 0x1
4897 22:14:48.977744 WR_PST = 0x0
4898 22:14:48.977827 DBI_WR = 0x0
4899 22:14:48.980892 DBI_RD = 0x0
4900 22:14:48.980975 OTF = 0x1
4901 22:14:48.984426 ===================================
4902 22:14:48.987524 ===================================
4903 22:14:48.990471 ANA top config
4904 22:14:48.994325 ===================================
4905 22:14:48.994408 DLL_ASYNC_EN = 0
4906 22:14:48.997136 ALL_SLAVE_EN = 1
4907 22:14:49.000474 NEW_RANK_MODE = 1
4908 22:14:49.003901 DLL_IDLE_MODE = 1
4909 22:14:49.007202 LP45_APHY_COMB_EN = 1
4910 22:14:49.007325 TX_ODT_DIS = 1
4911 22:14:49.010414 NEW_8X_MODE = 1
4912 22:14:49.013750 ===================================
4913 22:14:49.017063 ===================================
4914 22:14:49.020337 data_rate = 1866
4915 22:14:49.023372 CKR = 1
4916 22:14:49.027200 DQ_P2S_RATIO = 8
4917 22:14:49.030555 ===================================
4918 22:14:49.033255 CA_P2S_RATIO = 8
4919 22:14:49.033337 DQ_CA_OPEN = 0
4920 22:14:49.036560 DQ_SEMI_OPEN = 0
4921 22:14:49.040059 CA_SEMI_OPEN = 0
4922 22:14:49.043474 CA_FULL_RATE = 0
4923 22:14:49.046806 DQ_CKDIV4_EN = 1
4924 22:14:49.050019 CA_CKDIV4_EN = 1
4925 22:14:49.050102 CA_PREDIV_EN = 0
4926 22:14:49.053336 PH8_DLY = 0
4927 22:14:49.056662 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4928 22:14:49.060107 DQ_AAMCK_DIV = 4
4929 22:14:49.063641 CA_AAMCK_DIV = 4
4930 22:14:49.066427 CA_ADMCK_DIV = 4
4931 22:14:49.066510 DQ_TRACK_CA_EN = 0
4932 22:14:49.069528 CA_PICK = 933
4933 22:14:49.072827 CA_MCKIO = 933
4934 22:14:49.076408 MCKIO_SEMI = 0
4935 22:14:49.079571 PLL_FREQ = 3732
4936 22:14:49.082595 DQ_UI_PI_RATIO = 32
4937 22:14:49.086289 CA_UI_PI_RATIO = 0
4938 22:14:49.089540 ===================================
4939 22:14:49.092560 ===================================
4940 22:14:49.092643 memory_type:LPDDR4
4941 22:14:49.096073 GP_NUM : 10
4942 22:14:49.099698 SRAM_EN : 1
4943 22:14:49.099781 MD32_EN : 0
4944 22:14:49.102933 ===================================
4945 22:14:49.105836 [ANA_INIT] >>>>>>>>>>>>>>
4946 22:14:49.109128 <<<<<< [CONFIGURE PHASE]: ANA_TX
4947 22:14:49.112607 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4948 22:14:49.115828 ===================================
4949 22:14:49.119349 data_rate = 1866,PCW = 0X8f00
4950 22:14:49.122522 ===================================
4951 22:14:49.126334 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4952 22:14:49.129163 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4953 22:14:49.135915 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4954 22:14:49.139259 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4955 22:14:49.142723 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4956 22:14:49.148892 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4957 22:14:49.148974 [ANA_INIT] flow start
4958 22:14:49.152199 [ANA_INIT] PLL >>>>>>>>
4959 22:14:49.152306 [ANA_INIT] PLL <<<<<<<<
4960 22:14:49.155387 [ANA_INIT] MIDPI >>>>>>>>
4961 22:14:49.158714 [ANA_INIT] MIDPI <<<<<<<<
4962 22:14:49.162158 [ANA_INIT] DLL >>>>>>>>
4963 22:14:49.162240 [ANA_INIT] flow end
4964 22:14:49.165877 ============ LP4 DIFF to SE enter ============
4965 22:14:49.172221 ============ LP4 DIFF to SE exit ============
4966 22:14:49.172305 [ANA_INIT] <<<<<<<<<<<<<
4967 22:14:49.175231 [Flow] Enable top DCM control >>>>>
4968 22:14:49.178682 [Flow] Enable top DCM control <<<<<
4969 22:14:49.181643 Enable DLL master slave shuffle
4970 22:14:49.188368 ==============================================================
4971 22:14:49.191958 Gating Mode config
4972 22:14:49.195176 ==============================================================
4973 22:14:49.198231 Config description:
4974 22:14:49.208029 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4975 22:14:49.215129 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4976 22:14:49.218400 SELPH_MODE 0: By rank 1: By Phase
4977 22:14:49.224665 ==============================================================
4978 22:14:49.227970 GAT_TRACK_EN = 1
4979 22:14:49.231401 RX_GATING_MODE = 2
4980 22:14:49.234874 RX_GATING_TRACK_MODE = 2
4981 22:14:49.234957 SELPH_MODE = 1
4982 22:14:49.238002 PICG_EARLY_EN = 1
4983 22:14:49.240998 VALID_LAT_VALUE = 1
4984 22:14:49.247753 ==============================================================
4985 22:14:49.251114 Enter into Gating configuration >>>>
4986 22:14:49.254606 Exit from Gating configuration <<<<
4987 22:14:49.258026 Enter into DVFS_PRE_config >>>>>
4988 22:14:49.268359 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4989 22:14:49.270734 Exit from DVFS_PRE_config <<<<<
4990 22:14:49.274191 Enter into PICG configuration >>>>
4991 22:14:49.277538 Exit from PICG configuration <<<<
4992 22:14:49.280903 [RX_INPUT] configuration >>>>>
4993 22:14:49.284571 [RX_INPUT] configuration <<<<<
4994 22:14:49.287690 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4995 22:14:49.294230 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4996 22:14:49.300474 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4997 22:14:49.307468 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4998 22:14:49.313932 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4999 22:14:49.320392 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5000 22:14:49.323606 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5001 22:14:49.327040 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5002 22:14:49.330534 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5003 22:14:49.337048 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5004 22:14:49.340449 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5005 22:14:49.343445 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5006 22:14:49.346785 ===================================
5007 22:14:49.350135 LPDDR4 DRAM CONFIGURATION
5008 22:14:49.353450 ===================================
5009 22:14:49.353531 EX_ROW_EN[0] = 0x0
5010 22:14:49.356901 EX_ROW_EN[1] = 0x0
5011 22:14:49.360294 LP4Y_EN = 0x0
5012 22:14:49.360391 WORK_FSP = 0x0
5013 22:14:49.363604 WL = 0x3
5014 22:14:49.363685 RL = 0x3
5015 22:14:49.366353 BL = 0x2
5016 22:14:49.366434 RPST = 0x0
5017 22:14:49.370062 RD_PRE = 0x0
5018 22:14:49.370143 WR_PRE = 0x1
5019 22:14:49.373307 WR_PST = 0x0
5020 22:14:49.373392 DBI_WR = 0x0
5021 22:14:49.376604 DBI_RD = 0x0
5022 22:14:49.376685 OTF = 0x1
5023 22:14:49.379930 ===================================
5024 22:14:49.383347 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5025 22:14:49.389503 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5026 22:14:49.393107 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5027 22:14:49.396407 ===================================
5028 22:14:49.399585 LPDDR4 DRAM CONFIGURATION
5029 22:14:49.402888 ===================================
5030 22:14:49.403000 EX_ROW_EN[0] = 0x10
5031 22:14:49.406052 EX_ROW_EN[1] = 0x0
5032 22:14:49.409093 LP4Y_EN = 0x0
5033 22:14:49.409174 WORK_FSP = 0x0
5034 22:14:49.412701 WL = 0x3
5035 22:14:49.412783 RL = 0x3
5036 22:14:49.415907 BL = 0x2
5037 22:14:49.415988 RPST = 0x0
5038 22:14:49.418996 RD_PRE = 0x0
5039 22:14:49.419077 WR_PRE = 0x1
5040 22:14:49.422433 WR_PST = 0x0
5041 22:14:49.422514 DBI_WR = 0x0
5042 22:14:49.425903 DBI_RD = 0x0
5043 22:14:49.425984 OTF = 0x1
5044 22:14:49.429165 ===================================
5045 22:14:49.435840 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5046 22:14:49.440072 nWR fixed to 30
5047 22:14:49.443513 [ModeRegInit_LP4] CH0 RK0
5048 22:14:49.443589 [ModeRegInit_LP4] CH0 RK1
5049 22:14:49.447194 [ModeRegInit_LP4] CH1 RK0
5050 22:14:49.450385 [ModeRegInit_LP4] CH1 RK1
5051 22:14:49.450483 match AC timing 9
5052 22:14:49.456937 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5053 22:14:49.460165 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5054 22:14:49.463475 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5055 22:14:49.469985 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5056 22:14:49.473565 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5057 22:14:49.473668 ==
5058 22:14:49.476598 Dram Type= 6, Freq= 0, CH_0, rank 0
5059 22:14:49.479480 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5060 22:14:49.479559 ==
5061 22:14:49.486100 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5062 22:14:49.492746 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5063 22:14:49.496002 [CA 0] Center 38 (8~69) winsize 62
5064 22:14:49.499614 [CA 1] Center 38 (8~69) winsize 62
5065 22:14:49.502943 [CA 2] Center 35 (5~65) winsize 61
5066 22:14:49.505840 [CA 3] Center 35 (5~65) winsize 61
5067 22:14:49.509037 [CA 4] Center 34 (4~65) winsize 62
5068 22:14:49.512865 [CA 5] Center 33 (3~64) winsize 62
5069 22:14:49.512962
5070 22:14:49.516031 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5071 22:14:49.516121
5072 22:14:49.519367 [CATrainingPosCal] consider 1 rank data
5073 22:14:49.522345 u2DelayCellTimex100 = 270/100 ps
5074 22:14:49.525610 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5075 22:14:49.528784 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5076 22:14:49.532304 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5077 22:14:49.539149 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5078 22:14:49.541861 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5079 22:14:49.545241 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5080 22:14:49.545340
5081 22:14:49.548591 CA PerBit enable=1, Macro0, CA PI delay=33
5082 22:14:49.548671
5083 22:14:49.552036 [CBTSetCACLKResult] CA Dly = 33
5084 22:14:49.552116 CS Dly: 7 (0~38)
5085 22:14:49.555548 ==
5086 22:14:49.558380 Dram Type= 6, Freq= 0, CH_0, rank 1
5087 22:14:49.561788 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5088 22:14:49.561870 ==
5089 22:14:49.565127 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5090 22:14:49.571911 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5091 22:14:49.575121 [CA 0] Center 38 (8~69) winsize 62
5092 22:14:49.578535 [CA 1] Center 38 (7~69) winsize 63
5093 22:14:49.581956 [CA 2] Center 35 (5~66) winsize 62
5094 22:14:49.585159 [CA 3] Center 35 (5~66) winsize 62
5095 22:14:49.588731 [CA 4] Center 34 (4~64) winsize 61
5096 22:14:49.591926 [CA 5] Center 34 (4~64) winsize 61
5097 22:14:49.592006
5098 22:14:49.595321 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5099 22:14:49.595401
5100 22:14:49.598121 [CATrainingPosCal] consider 2 rank data
5101 22:14:49.602305 u2DelayCellTimex100 = 270/100 ps
5102 22:14:49.608364 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5103 22:14:49.611580 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5104 22:14:49.614713 CA2 delay=35 (5~65),Diff = 1 PI (6 cell)
5105 22:14:49.618106 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5106 22:14:49.621158 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5107 22:14:49.625068 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5108 22:14:49.625149
5109 22:14:49.627966 CA PerBit enable=1, Macro0, CA PI delay=34
5110 22:14:49.628047
5111 22:14:49.631532 [CBTSetCACLKResult] CA Dly = 34
5112 22:14:49.634698 CS Dly: 7 (0~38)
5113 22:14:49.634779
5114 22:14:49.637936 ----->DramcWriteLeveling(PI) begin...
5115 22:14:49.638068 ==
5116 22:14:49.641423 Dram Type= 6, Freq= 0, CH_0, rank 0
5117 22:14:49.644430 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5118 22:14:49.644514 ==
5119 22:14:49.647642 Write leveling (Byte 0): 34 => 34
5120 22:14:49.651237 Write leveling (Byte 1): 29 => 29
5121 22:14:49.654663 DramcWriteLeveling(PI) end<-----
5122 22:14:49.654743
5123 22:14:49.654806 ==
5124 22:14:49.657771 Dram Type= 6, Freq= 0, CH_0, rank 0
5125 22:14:49.660807 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5126 22:14:49.660889 ==
5127 22:14:49.664493 [Gating] SW mode calibration
5128 22:14:49.670594 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5129 22:14:49.677300 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5130 22:14:49.680547 0 14 0 | B1->B0 | 2323 2d2d | 0 1 | (0 0) (1 1)
5131 22:14:49.687597 0 14 4 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
5132 22:14:49.690562 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5133 22:14:49.693799 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5134 22:14:49.700676 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5135 22:14:49.704008 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5136 22:14:49.707571 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5137 22:14:49.713836 0 14 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5138 22:14:49.717016 0 15 0 | B1->B0 | 3434 2c2c | 0 1 | (0 0) (1 0)
5139 22:14:49.720465 0 15 4 | B1->B0 | 2b2b 2323 | 1 0 | (1 0) (0 0)
5140 22:14:49.723665 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5141 22:14:49.730444 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5142 22:14:49.733511 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5143 22:14:49.737005 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5144 22:14:49.743410 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5145 22:14:49.747077 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5146 22:14:49.750073 1 0 0 | B1->B0 | 2525 3a3a | 0 1 | (0 0) (0 0)
5147 22:14:49.756536 1 0 4 | B1->B0 | 4141 4646 | 1 0 | (0 0) (0 0)
5148 22:14:49.760088 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5149 22:14:49.763440 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5150 22:14:49.769897 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5151 22:14:49.773754 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5152 22:14:49.776446 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5153 22:14:49.783155 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5154 22:14:49.786566 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
5155 22:14:49.789392 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5156 22:14:49.796038 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5157 22:14:49.799425 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5158 22:14:49.802770 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5159 22:14:49.809207 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5160 22:14:49.812512 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5161 22:14:49.815696 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5162 22:14:49.822598 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5163 22:14:49.825706 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5164 22:14:49.832182 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5165 22:14:49.835509 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5166 22:14:49.839049 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5167 22:14:49.845429 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5168 22:14:49.848946 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5169 22:14:49.852282 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5170 22:14:49.858539 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5171 22:14:49.858613 Total UI for P1: 0, mck2ui 16
5172 22:14:49.862377 best dqsien dly found for B0: ( 1, 2, 28)
5173 22:14:49.868717 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5174 22:14:49.872171 Total UI for P1: 0, mck2ui 16
5175 22:14:49.875029 best dqsien dly found for B1: ( 1, 3, 0)
5176 22:14:49.878394 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5177 22:14:49.881851 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5178 22:14:49.881933
5179 22:14:49.885174 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5180 22:14:49.888344 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5181 22:14:49.891589 [Gating] SW calibration Done
5182 22:14:49.891671 ==
5183 22:14:49.895032 Dram Type= 6, Freq= 0, CH_0, rank 0
5184 22:14:49.898407 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5185 22:14:49.898489 ==
5186 22:14:49.901673 RX Vref Scan: 0
5187 22:14:49.901755
5188 22:14:49.905575 RX Vref 0 -> 0, step: 1
5189 22:14:49.905656
5190 22:14:49.905721 RX Delay -80 -> 252, step: 8
5191 22:14:49.911313 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5192 22:14:49.914684 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5193 22:14:49.918213 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5194 22:14:49.921557 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5195 22:14:49.924820 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5196 22:14:49.931251 iDelay=208, Bit 5, Center 79 (-16 ~ 175) 192
5197 22:14:49.934711 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5198 22:14:49.938184 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5199 22:14:49.941303 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5200 22:14:49.944424 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5201 22:14:49.951153 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5202 22:14:49.954405 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5203 22:14:49.957516 iDelay=208, Bit 12, Center 83 (-16 ~ 183) 200
5204 22:14:49.960815 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5205 22:14:49.964389 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5206 22:14:49.970986 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5207 22:14:49.971060 ==
5208 22:14:49.974044 Dram Type= 6, Freq= 0, CH_0, rank 0
5209 22:14:49.977700 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5210 22:14:49.977775 ==
5211 22:14:49.977835 DQS Delay:
5212 22:14:49.980948 DQS0 = 0, DQS1 = 0
5213 22:14:49.981050 DQM Delay:
5214 22:14:49.984117 DQM0 = 94, DQM1 = 82
5215 22:14:49.984188 DQ Delay:
5216 22:14:49.987435 DQ0 =91, DQ1 =95, DQ2 =91, DQ3 =91
5217 22:14:49.990629 DQ4 =99, DQ5 =79, DQ6 =103, DQ7 =107
5218 22:14:49.994515 DQ8 =75, DQ9 =71, DQ10 =83, DQ11 =75
5219 22:14:49.997494 DQ12 =83, DQ13 =91, DQ14 =91, DQ15 =91
5220 22:14:49.997616
5221 22:14:49.997716
5222 22:14:49.997843 ==
5223 22:14:50.000408 Dram Type= 6, Freq= 0, CH_0, rank 0
5224 22:14:50.004141 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5225 22:14:50.007412 ==
5226 22:14:50.007486
5227 22:14:50.007548
5228 22:14:50.007607 TX Vref Scan disable
5229 22:14:50.010745 == TX Byte 0 ==
5230 22:14:50.013625 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5231 22:14:50.017149 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5232 22:14:50.020674 == TX Byte 1 ==
5233 22:14:50.024107 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5234 22:14:50.026758 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5235 22:14:50.030371 ==
5236 22:14:50.033658 Dram Type= 6, Freq= 0, CH_0, rank 0
5237 22:14:50.036900 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5238 22:14:50.036983 ==
5239 22:14:50.037048
5240 22:14:50.037127
5241 22:14:50.039920 TX Vref Scan disable
5242 22:14:50.039996 == TX Byte 0 ==
5243 22:14:50.046921 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5244 22:14:50.050015 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5245 22:14:50.050113 == TX Byte 1 ==
5246 22:14:50.056382 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5247 22:14:50.059921 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5248 22:14:50.060018
5249 22:14:50.060082 [DATLAT]
5250 22:14:50.063476 Freq=933, CH0 RK0
5251 22:14:50.063564
5252 22:14:50.063628 DATLAT Default: 0xd
5253 22:14:50.066254 0, 0xFFFF, sum = 0
5254 22:14:50.066353 1, 0xFFFF, sum = 0
5255 22:14:50.069393 2, 0xFFFF, sum = 0
5256 22:14:50.073018 3, 0xFFFF, sum = 0
5257 22:14:50.073103 4, 0xFFFF, sum = 0
5258 22:14:50.076719 5, 0xFFFF, sum = 0
5259 22:14:50.076805 6, 0xFFFF, sum = 0
5260 22:14:50.079877 7, 0xFFFF, sum = 0
5261 22:14:50.080001 8, 0xFFFF, sum = 0
5262 22:14:50.082719 9, 0xFFFF, sum = 0
5263 22:14:50.082804 10, 0x0, sum = 1
5264 22:14:50.086180 11, 0x0, sum = 2
5265 22:14:50.086265 12, 0x0, sum = 3
5266 22:14:50.089539 13, 0x0, sum = 4
5267 22:14:50.089624 best_step = 11
5268 22:14:50.089689
5269 22:14:50.089749 ==
5270 22:14:50.092637 Dram Type= 6, Freq= 0, CH_0, rank 0
5271 22:14:50.095980 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5272 22:14:50.096065 ==
5273 22:14:50.099420 RX Vref Scan: 1
5274 22:14:50.099504
5275 22:14:50.102619 RX Vref 0 -> 0, step: 1
5276 22:14:50.102702
5277 22:14:50.102768 RX Delay -69 -> 252, step: 4
5278 22:14:50.102836
5279 22:14:50.106010 Set Vref, RX VrefLevel [Byte0]: 64
5280 22:14:50.109402 [Byte1]: 58
5281 22:14:50.113838
5282 22:14:50.113921 Final RX Vref Byte 0 = 64 to rank0
5283 22:14:50.117198 Final RX Vref Byte 1 = 58 to rank0
5284 22:14:50.120417 Final RX Vref Byte 0 = 64 to rank1
5285 22:14:50.123766 Final RX Vref Byte 1 = 58 to rank1==
5286 22:14:50.127155 Dram Type= 6, Freq= 0, CH_0, rank 0
5287 22:14:50.133951 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5288 22:14:50.134035 ==
5289 22:14:50.134101 DQS Delay:
5290 22:14:50.137384 DQS0 = 0, DQS1 = 0
5291 22:14:50.137468 DQM Delay:
5292 22:14:50.137534 DQM0 = 96, DQM1 = 83
5293 22:14:50.140546 DQ Delay:
5294 22:14:50.144027 DQ0 =92, DQ1 =98, DQ2 =94, DQ3 =92
5295 22:14:50.147090 DQ4 =98, DQ5 =86, DQ6 =104, DQ7 =108
5296 22:14:50.150445 DQ8 =78, DQ9 =72, DQ10 =82, DQ11 =80
5297 22:14:50.153782 DQ12 =86, DQ13 =88, DQ14 =94, DQ15 =90
5298 22:14:50.153864
5299 22:14:50.153926
5300 22:14:50.160082 [DQSOSCAuto] RK0, (LSB)MR18= 0x1413, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 415 ps
5301 22:14:50.163654 CH0 RK0: MR19=505, MR18=1413
5302 22:14:50.169935 CH0_RK0: MR19=0x505, MR18=0x1413, DQSOSC=415, MR23=63, INC=62, DEC=41
5303 22:14:50.170015
5304 22:14:50.173546 ----->DramcWriteLeveling(PI) begin...
5305 22:14:50.173625 ==
5306 22:14:50.176621 Dram Type= 6, Freq= 0, CH_0, rank 1
5307 22:14:50.179712 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5308 22:14:50.179813 ==
5309 22:14:50.183006 Write leveling (Byte 0): 29 => 29
5310 22:14:50.186520 Write leveling (Byte 1): 28 => 28
5311 22:14:50.189846 DramcWriteLeveling(PI) end<-----
5312 22:14:50.189925
5313 22:14:50.189985 ==
5314 22:14:50.193078 Dram Type= 6, Freq= 0, CH_0, rank 1
5315 22:14:50.199752 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5316 22:14:50.199833 ==
5317 22:14:50.199925 [Gating] SW mode calibration
5318 22:14:50.209755 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5319 22:14:50.212809 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5320 22:14:50.215936 0 14 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
5321 22:14:50.222859 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5322 22:14:50.226148 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5323 22:14:50.229439 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5324 22:14:50.235687 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5325 22:14:50.239046 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5326 22:14:50.242322 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5327 22:14:50.248780 0 14 28 | B1->B0 | 3434 2b2b | 1 1 | (1 1) (1 0)
5328 22:14:50.252230 0 15 0 | B1->B0 | 2e2e 2323 | 0 0 | (0 1) (0 0)
5329 22:14:50.255471 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5330 22:14:50.262026 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5331 22:14:50.265407 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5332 22:14:50.269036 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5333 22:14:50.275611 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5334 22:14:50.278707 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5335 22:14:50.281836 0 15 28 | B1->B0 | 2323 3535 | 0 1 | (0 0) (1 1)
5336 22:14:50.288439 1 0 0 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
5337 22:14:50.292024 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5338 22:14:50.295037 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5339 22:14:50.301858 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5340 22:14:50.305059 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5341 22:14:50.308363 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5342 22:14:50.314836 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5343 22:14:50.318401 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
5344 22:14:50.321774 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5345 22:14:50.328031 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5346 22:14:50.331366 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5347 22:14:50.334903 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5348 22:14:50.341408 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5349 22:14:50.344683 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5350 22:14:50.351548 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5351 22:14:50.354462 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5352 22:14:50.357993 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5353 22:14:50.360965 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5354 22:14:50.367757 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5355 22:14:50.371140 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5356 22:14:50.377646 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5357 22:14:50.381403 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5358 22:14:50.383952 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5359 22:14:50.390740 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
5360 22:14:50.390934 Total UI for P1: 0, mck2ui 16
5361 22:14:50.393843 best dqsien dly found for B0: ( 1, 2, 24)
5362 22:14:50.400610 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5363 22:14:50.404116 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5364 22:14:50.407438 Total UI for P1: 0, mck2ui 16
5365 22:14:50.411221 best dqsien dly found for B1: ( 1, 3, 0)
5366 22:14:50.414154 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5367 22:14:50.417460 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5368 22:14:50.417922
5369 22:14:50.421029 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5370 22:14:50.427057 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5371 22:14:50.427516 [Gating] SW calibration Done
5372 22:14:50.427874 ==
5373 22:14:50.430336 Dram Type= 6, Freq= 0, CH_0, rank 1
5374 22:14:50.437143 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5375 22:14:50.437608 ==
5376 22:14:50.437969 RX Vref Scan: 0
5377 22:14:50.438302
5378 22:14:50.440525 RX Vref 0 -> 0, step: 1
5379 22:14:50.440983
5380 22:14:50.443669 RX Delay -80 -> 252, step: 8
5381 22:14:50.446855 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5382 22:14:50.450330 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5383 22:14:50.453710 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5384 22:14:50.460444 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5385 22:14:50.463344 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5386 22:14:50.466627 iDelay=208, Bit 5, Center 79 (-16 ~ 175) 192
5387 22:14:50.469892 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5388 22:14:50.473391 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5389 22:14:50.476641 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5390 22:14:50.483202 iDelay=208, Bit 9, Center 67 (-32 ~ 167) 200
5391 22:14:50.486761 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5392 22:14:50.489856 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5393 22:14:50.493088 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5394 22:14:50.496666 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5395 22:14:50.503322 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5396 22:14:50.506560 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5397 22:14:50.507014 ==
5398 22:14:50.509538 Dram Type= 6, Freq= 0, CH_0, rank 1
5399 22:14:50.513160 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5400 22:14:50.513585 ==
5401 22:14:50.516425 DQS Delay:
5402 22:14:50.516838 DQS0 = 0, DQS1 = 0
5403 22:14:50.517158 DQM Delay:
5404 22:14:50.519893 DQM0 = 93, DQM1 = 83
5405 22:14:50.520307 DQ Delay:
5406 22:14:50.523252 DQ0 =95, DQ1 =95, DQ2 =87, DQ3 =91
5407 22:14:50.526253 DQ4 =91, DQ5 =79, DQ6 =103, DQ7 =107
5408 22:14:50.529603 DQ8 =75, DQ9 =67, DQ10 =83, DQ11 =75
5409 22:14:50.532837 DQ12 =91, DQ13 =91, DQ14 =95, DQ15 =91
5410 22:14:50.533252
5411 22:14:50.533573
5412 22:14:50.533873 ==
5413 22:14:50.536199 Dram Type= 6, Freq= 0, CH_0, rank 1
5414 22:14:50.542902 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5415 22:14:50.543369 ==
5416 22:14:50.543733
5417 22:14:50.544069
5418 22:14:50.545698 TX Vref Scan disable
5419 22:14:50.546157 == TX Byte 0 ==
5420 22:14:50.549535 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5421 22:14:50.556120 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5422 22:14:50.556564 == TX Byte 1 ==
5423 22:14:50.559055 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5424 22:14:50.566047 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5425 22:14:50.566516 ==
5426 22:14:50.568842 Dram Type= 6, Freq= 0, CH_0, rank 1
5427 22:14:50.572019 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5428 22:14:50.572488 ==
5429 22:14:50.572861
5430 22:14:50.573205
5431 22:14:50.575519 TX Vref Scan disable
5432 22:14:50.578626 == TX Byte 0 ==
5433 22:14:50.581932 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5434 22:14:50.585302 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5435 22:14:50.589060 == TX Byte 1 ==
5436 22:14:50.591779 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5437 22:14:50.595524 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5438 22:14:50.595921
5439 22:14:50.598697 [DATLAT]
5440 22:14:50.599158 Freq=933, CH0 RK1
5441 22:14:50.599484
5442 22:14:50.601915 DATLAT Default: 0xb
5443 22:14:50.602366 0, 0xFFFF, sum = 0
5444 22:14:50.605619 1, 0xFFFF, sum = 0
5445 22:14:50.606103 2, 0xFFFF, sum = 0
5446 22:14:50.608798 3, 0xFFFF, sum = 0
5447 22:14:50.609357 4, 0xFFFF, sum = 0
5448 22:14:50.611946 5, 0xFFFF, sum = 0
5449 22:14:50.612388 6, 0xFFFF, sum = 0
5450 22:14:50.615366 7, 0xFFFF, sum = 0
5451 22:14:50.615808 8, 0xFFFF, sum = 0
5452 22:14:50.618429 9, 0xFFFF, sum = 0
5453 22:14:50.618901 10, 0x0, sum = 1
5454 22:14:50.621770 11, 0x0, sum = 2
5455 22:14:50.622346 12, 0x0, sum = 3
5456 22:14:50.625015 13, 0x0, sum = 4
5457 22:14:50.625449 best_step = 11
5458 22:14:50.625789
5459 22:14:50.626207 ==
5460 22:14:50.628148 Dram Type= 6, Freq= 0, CH_0, rank 1
5461 22:14:50.634970 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5462 22:14:50.635516 ==
5463 22:14:50.635864 RX Vref Scan: 0
5464 22:14:50.636182
5465 22:14:50.638761 RX Vref 0 -> 0, step: 1
5466 22:14:50.639231
5467 22:14:50.641376 RX Delay -77 -> 252, step: 4
5468 22:14:50.644849 iDelay=199, Bit 0, Center 90 (-1 ~ 182) 184
5469 22:14:50.648191 iDelay=199, Bit 1, Center 96 (7 ~ 186) 180
5470 22:14:50.655292 iDelay=199, Bit 2, Center 88 (-1 ~ 178) 180
5471 22:14:50.658536 iDelay=199, Bit 3, Center 86 (-9 ~ 182) 192
5472 22:14:50.661349 iDelay=199, Bit 4, Center 92 (-1 ~ 186) 188
5473 22:14:50.664871 iDelay=199, Bit 5, Center 80 (-9 ~ 170) 180
5474 22:14:50.668068 iDelay=199, Bit 6, Center 106 (15 ~ 198) 184
5475 22:14:50.675200 iDelay=199, Bit 7, Center 104 (11 ~ 198) 188
5476 22:14:50.678388 iDelay=199, Bit 8, Center 80 (-9 ~ 170) 180
5477 22:14:50.681371 iDelay=199, Bit 9, Center 72 (-17 ~ 162) 180
5478 22:14:50.684568 iDelay=199, Bit 10, Center 84 (-9 ~ 178) 188
5479 22:14:50.688318 iDelay=199, Bit 11, Center 80 (-9 ~ 170) 180
5480 22:14:50.691333 iDelay=199, Bit 12, Center 90 (-1 ~ 182) 184
5481 22:14:50.697629 iDelay=199, Bit 13, Center 90 (-1 ~ 182) 184
5482 22:14:50.701230 iDelay=199, Bit 14, Center 96 (7 ~ 186) 180
5483 22:14:50.704609 iDelay=199, Bit 15, Center 90 (-1 ~ 182) 184
5484 22:14:50.705072 ==
5485 22:14:50.707505 Dram Type= 6, Freq= 0, CH_0, rank 1
5486 22:14:50.711200 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5487 22:14:50.711663 ==
5488 22:14:50.714375 DQS Delay:
5489 22:14:50.714862 DQS0 = 0, DQS1 = 0
5490 22:14:50.717882 DQM Delay:
5491 22:14:50.718339 DQM0 = 92, DQM1 = 85
5492 22:14:50.718700 DQ Delay:
5493 22:14:50.721023 DQ0 =90, DQ1 =96, DQ2 =88, DQ3 =86
5494 22:14:50.724603 DQ4 =92, DQ5 =80, DQ6 =106, DQ7 =104
5495 22:14:50.727586 DQ8 =80, DQ9 =72, DQ10 =84, DQ11 =80
5496 22:14:50.731079 DQ12 =90, DQ13 =90, DQ14 =96, DQ15 =90
5497 22:14:50.731536
5498 22:14:50.733971
5499 22:14:50.740510 [DQSOSCAuto] RK1, (LSB)MR18= 0x2c0d, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 408 ps
5500 22:14:50.744337 CH0 RK1: MR19=505, MR18=2C0D
5501 22:14:50.750662 CH0_RK1: MR19=0x505, MR18=0x2C0D, DQSOSC=408, MR23=63, INC=65, DEC=43
5502 22:14:50.753868 [RxdqsGatingPostProcess] freq 933
5503 22:14:50.757092 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5504 22:14:50.760631 best DQS0 dly(2T, 0.5T) = (0, 10)
5505 22:14:50.763878 best DQS1 dly(2T, 0.5T) = (0, 11)
5506 22:14:50.767304 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5507 22:14:50.770414 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5508 22:14:50.773751 best DQS0 dly(2T, 0.5T) = (0, 10)
5509 22:14:50.776971 best DQS1 dly(2T, 0.5T) = (0, 11)
5510 22:14:50.780315 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5511 22:14:50.783724 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5512 22:14:50.787245 Pre-setting of DQS Precalculation
5513 22:14:50.790595 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5514 22:14:50.791159 ==
5515 22:14:50.793494 Dram Type= 6, Freq= 0, CH_1, rank 0
5516 22:14:50.800075 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5517 22:14:50.800540 ==
5518 22:14:50.803841 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5519 22:14:50.810143 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5520 22:14:50.813271 [CA 0] Center 37 (7~67) winsize 61
5521 22:14:50.816615 [CA 1] Center 37 (7~68) winsize 62
5522 22:14:50.819786 [CA 2] Center 34 (5~64) winsize 60
5523 22:14:50.823482 [CA 3] Center 34 (5~64) winsize 60
5524 22:14:50.826703 [CA 4] Center 34 (5~64) winsize 60
5525 22:14:50.829723 [CA 5] Center 34 (4~64) winsize 61
5526 22:14:50.830314
5527 22:14:50.833313 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5528 22:14:50.833849
5529 22:14:50.836431 [CATrainingPosCal] consider 1 rank data
5530 22:14:50.839463 u2DelayCellTimex100 = 270/100 ps
5531 22:14:50.842950 CA0 delay=37 (7~67),Diff = 3 PI (18 cell)
5532 22:14:50.849480 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5533 22:14:50.852880 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
5534 22:14:50.856329 CA3 delay=34 (5~64),Diff = 0 PI (0 cell)
5535 22:14:50.859198 CA4 delay=34 (5~64),Diff = 0 PI (0 cell)
5536 22:14:50.862648 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5537 22:14:50.863219
5538 22:14:50.865837 CA PerBit enable=1, Macro0, CA PI delay=34
5539 22:14:50.866512
5540 22:14:50.869264 [CBTSetCACLKResult] CA Dly = 34
5541 22:14:50.872565 CS Dly: 5 (0~36)
5542 22:14:50.873093 ==
5543 22:14:50.875974 Dram Type= 6, Freq= 0, CH_1, rank 1
5544 22:14:50.879334 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5545 22:14:50.879890 ==
5546 22:14:50.885462 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5547 22:14:50.889061 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5548 22:14:50.893370 [CA 0] Center 38 (8~68) winsize 61
5549 22:14:50.896951 [CA 1] Center 37 (7~68) winsize 62
5550 22:14:50.900181 [CA 2] Center 35 (5~65) winsize 61
5551 22:14:50.902894 [CA 3] Center 34 (4~64) winsize 61
5552 22:14:50.906574 [CA 4] Center 34 (4~65) winsize 62
5553 22:14:50.909388 [CA 5] Center 34 (4~64) winsize 61
5554 22:14:50.909909
5555 22:14:50.913361 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5556 22:14:50.913882
5557 22:14:50.916126 [CATrainingPosCal] consider 2 rank data
5558 22:14:50.919880 u2DelayCellTimex100 = 270/100 ps
5559 22:14:50.923066 CA0 delay=37 (8~67),Diff = 3 PI (18 cell)
5560 22:14:50.929438 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5561 22:14:50.932497 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
5562 22:14:50.936043 CA3 delay=34 (5~64),Diff = 0 PI (0 cell)
5563 22:14:50.939250 CA4 delay=34 (5~64),Diff = 0 PI (0 cell)
5564 22:14:50.942672 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5565 22:14:50.943237
5566 22:14:50.945866 CA PerBit enable=1, Macro0, CA PI delay=34
5567 22:14:50.946419
5568 22:14:50.948910 [CBTSetCACLKResult] CA Dly = 34
5569 22:14:50.952319 CS Dly: 6 (0~39)
5570 22:14:50.952866
5571 22:14:50.955932 ----->DramcWriteLeveling(PI) begin...
5572 22:14:50.956505 ==
5573 22:14:50.958934 Dram Type= 6, Freq= 0, CH_1, rank 0
5574 22:14:50.962068 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5575 22:14:50.962645 ==
5576 22:14:50.965522 Write leveling (Byte 0): 28 => 28
5577 22:14:50.968902 Write leveling (Byte 1): 30 => 30
5578 22:14:50.972350 DramcWriteLeveling(PI) end<-----
5579 22:14:50.972938
5580 22:14:50.973378 ==
5581 22:14:50.975428 Dram Type= 6, Freq= 0, CH_1, rank 0
5582 22:14:50.978768 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5583 22:14:50.979360 ==
5584 22:14:50.982061 [Gating] SW mode calibration
5585 22:14:50.988749 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5586 22:14:50.995494 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5587 22:14:50.998280 0 14 0 | B1->B0 | 2f2f 2f2f | 1 1 | (1 1) (1 1)
5588 22:14:51.005224 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5589 22:14:51.008389 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5590 22:14:51.011742 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5591 22:14:51.018221 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5592 22:14:51.021479 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5593 22:14:51.024895 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5594 22:14:51.031359 0 14 28 | B1->B0 | 2f2f 2f2f | 0 0 | (0 0) (0 0)
5595 22:14:51.034795 0 15 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5596 22:14:51.037994 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5597 22:14:51.044378 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5598 22:14:51.047992 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5599 22:14:51.050934 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5600 22:14:51.057825 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5601 22:14:51.061282 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5602 22:14:51.064515 0 15 28 | B1->B0 | 2e2e 2c2c | 0 1 | (0 0) (0 0)
5603 22:14:51.070933 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5604 22:14:51.074405 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5605 22:14:51.077564 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5606 22:14:51.084222 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5607 22:14:51.087805 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5608 22:14:51.090932 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5609 22:14:51.097428 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5610 22:14:51.100513 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5611 22:14:51.104243 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5612 22:14:51.110802 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5613 22:14:51.114108 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5614 22:14:51.116960 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5615 22:14:51.120430 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5616 22:14:51.127236 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5617 22:14:51.130960 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5618 22:14:51.133900 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5619 22:14:51.140001 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5620 22:14:51.143360 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5621 22:14:51.146870 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5622 22:14:51.153219 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5623 22:14:51.156986 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5624 22:14:51.160025 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5625 22:14:51.166352 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5626 22:14:51.169956 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5627 22:14:51.173263 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5628 22:14:51.176517 Total UI for P1: 0, mck2ui 16
5629 22:14:51.180244 best dqsien dly found for B1: ( 1, 2, 28)
5630 22:14:51.186591 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5631 22:14:51.189884 Total UI for P1: 0, mck2ui 16
5632 22:14:51.192710 best dqsien dly found for B0: ( 1, 2, 30)
5633 22:14:51.196039 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5634 22:14:51.199519 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5635 22:14:51.199944
5636 22:14:51.202929 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5637 22:14:51.206342 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5638 22:14:51.209233 [Gating] SW calibration Done
5639 22:14:51.209658 ==
5640 22:14:51.212607 Dram Type= 6, Freq= 0, CH_1, rank 0
5641 22:14:51.215852 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5642 22:14:51.216355 ==
5643 22:14:51.219390 RX Vref Scan: 0
5644 22:14:51.219814
5645 22:14:51.222347 RX Vref 0 -> 0, step: 1
5646 22:14:51.222768
5647 22:14:51.223149 RX Delay -80 -> 252, step: 8
5648 22:14:51.229243 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5649 22:14:51.232721 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5650 22:14:51.235876 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5651 22:14:51.238692 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5652 22:14:51.242204 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5653 22:14:51.249081 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5654 22:14:51.252171 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5655 22:14:51.255910 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5656 22:14:51.258698 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5657 22:14:51.262277 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5658 22:14:51.265499 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5659 22:14:51.272254 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5660 22:14:51.275432 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5661 22:14:51.278650 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5662 22:14:51.282127 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5663 22:14:51.288400 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5664 22:14:51.288608 ==
5665 22:14:51.292147 Dram Type= 6, Freq= 0, CH_1, rank 0
5666 22:14:51.295404 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5667 22:14:51.295644 ==
5668 22:14:51.295833 DQS Delay:
5669 22:14:51.298347 DQS0 = 0, DQS1 = 0
5670 22:14:51.298643 DQM Delay:
5671 22:14:51.301711 DQM0 = 94, DQM1 = 86
5672 22:14:51.302006 DQ Delay:
5673 22:14:51.305031 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =91
5674 22:14:51.308516 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =91
5675 22:14:51.311900 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =83
5676 22:14:51.315378 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =91
5677 22:14:51.315839
5678 22:14:51.316200
5679 22:14:51.316531 ==
5680 22:14:51.318273 Dram Type= 6, Freq= 0, CH_1, rank 0
5681 22:14:51.321523 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5682 22:14:51.322114 ==
5683 22:14:51.325455
5684 22:14:51.325971
5685 22:14:51.326338 TX Vref Scan disable
5686 22:14:51.328228 == TX Byte 0 ==
5687 22:14:51.332218 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5688 22:14:51.335268 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5689 22:14:51.338331 == TX Byte 1 ==
5690 22:14:51.341612 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5691 22:14:51.345032 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5692 22:14:51.345496 ==
5693 22:14:51.348351 Dram Type= 6, Freq= 0, CH_1, rank 0
5694 22:14:51.354919 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5695 22:14:51.355384 ==
5696 22:14:51.355745
5697 22:14:51.356076
5698 22:14:51.356398 TX Vref Scan disable
5699 22:14:51.359621 == TX Byte 0 ==
5700 22:14:51.362583 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5701 22:14:51.368728 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5702 22:14:51.369195 == TX Byte 1 ==
5703 22:14:51.372416 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5704 22:14:51.378925 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5705 22:14:51.379451
5706 22:14:51.379864 [DATLAT]
5707 22:14:51.380244 Freq=933, CH1 RK0
5708 22:14:51.380718
5709 22:14:51.382277 DATLAT Default: 0xd
5710 22:14:51.385273 0, 0xFFFF, sum = 0
5711 22:14:51.385787 1, 0xFFFF, sum = 0
5712 22:14:51.388502 2, 0xFFFF, sum = 0
5713 22:14:51.389026 3, 0xFFFF, sum = 0
5714 22:14:51.392111 4, 0xFFFF, sum = 0
5715 22:14:51.392660 5, 0xFFFF, sum = 0
5716 22:14:51.395459 6, 0xFFFF, sum = 0
5717 22:14:51.396048 7, 0xFFFF, sum = 0
5718 22:14:51.398505 8, 0xFFFF, sum = 0
5719 22:14:51.399069 9, 0xFFFF, sum = 0
5720 22:14:51.401961 10, 0x0, sum = 1
5721 22:14:51.402484 11, 0x0, sum = 2
5722 22:14:51.405142 12, 0x0, sum = 3
5723 22:14:51.405583 13, 0x0, sum = 4
5724 22:14:51.408513 best_step = 11
5725 22:14:51.408979
5726 22:14:51.409335 ==
5727 22:14:51.411914 Dram Type= 6, Freq= 0, CH_1, rank 0
5728 22:14:51.415244 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5729 22:14:51.415710 ==
5730 22:14:51.416071 RX Vref Scan: 1
5731 22:14:51.418575
5732 22:14:51.419210 RX Vref 0 -> 0, step: 1
5733 22:14:51.419720
5734 22:14:51.421435 RX Delay -61 -> 252, step: 4
5735 22:14:51.421898
5736 22:14:51.425066 Set Vref, RX VrefLevel [Byte0]: 53
5737 22:14:51.428480 [Byte1]: 47
5738 22:14:51.431910
5739 22:14:51.432371 Final RX Vref Byte 0 = 53 to rank0
5740 22:14:51.435174 Final RX Vref Byte 1 = 47 to rank0
5741 22:14:51.438409 Final RX Vref Byte 0 = 53 to rank1
5742 22:14:51.441378 Final RX Vref Byte 1 = 47 to rank1==
5743 22:14:51.444946 Dram Type= 6, Freq= 0, CH_1, rank 0
5744 22:14:51.451606 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5745 22:14:51.452027 ==
5746 22:14:51.452354 DQS Delay:
5747 22:14:51.454506 DQS0 = 0, DQS1 = 0
5748 22:14:51.454961 DQM Delay:
5749 22:14:51.455296 DQM0 = 95, DQM1 = 86
5750 22:14:51.457837 DQ Delay:
5751 22:14:51.461657 DQ0 =100, DQ1 =90, DQ2 =84, DQ3 =94
5752 22:14:51.464813 DQ4 =94, DQ5 =106, DQ6 =106, DQ7 =92
5753 22:14:51.467782 DQ8 =74, DQ9 =80, DQ10 =86, DQ11 =80
5754 22:14:51.471065 DQ12 =96, DQ13 =92, DQ14 =92, DQ15 =94
5755 22:14:51.471482
5756 22:14:51.471807
5757 22:14:51.478013 [DQSOSCAuto] RK0, (LSB)MR18= 0xff07, (MSB)MR19= 0x405, tDQSOscB0 = 419 ps tDQSOscB1 = 422 ps
5758 22:14:51.481051 CH1 RK0: MR19=405, MR18=FF07
5759 22:14:51.488075 CH1_RK0: MR19=0x405, MR18=0xFF07, DQSOSC=419, MR23=63, INC=61, DEC=41
5760 22:14:51.488514
5761 22:14:51.490889 ----->DramcWriteLeveling(PI) begin...
5762 22:14:51.491316 ==
5763 22:14:51.494752 Dram Type= 6, Freq= 0, CH_1, rank 1
5764 22:14:51.498022 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5765 22:14:51.498445 ==
5766 22:14:51.501290 Write leveling (Byte 0): 26 => 26
5767 22:14:51.504961 Write leveling (Byte 1): 26 => 26
5768 22:14:51.507361 DramcWriteLeveling(PI) end<-----
5769 22:14:51.507779
5770 22:14:51.508107 ==
5771 22:14:51.510633 Dram Type= 6, Freq= 0, CH_1, rank 1
5772 22:14:51.514039 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5773 22:14:51.517305 ==
5774 22:14:51.517771 [Gating] SW mode calibration
5775 22:14:51.527684 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5776 22:14:51.530811 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5777 22:14:51.534208 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5778 22:14:51.540282 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5779 22:14:51.543617 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5780 22:14:51.546961 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5781 22:14:51.553484 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5782 22:14:51.556771 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5783 22:14:51.560125 0 14 24 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 0)
5784 22:14:51.566231 0 14 28 | B1->B0 | 2f2f 2727 | 1 0 | (1 0) (1 0)
5785 22:14:51.569676 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5786 22:14:51.573194 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5787 22:14:51.579437 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5788 22:14:51.583094 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5789 22:14:51.586153 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5790 22:14:51.592929 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5791 22:14:51.596154 0 15 24 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
5792 22:14:51.599334 0 15 28 | B1->B0 | 3636 4444 | 0 0 | (0 0) (0 0)
5793 22:14:51.606419 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5794 22:14:51.609854 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5795 22:14:51.612913 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5796 22:14:51.619613 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5797 22:14:51.622741 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5798 22:14:51.626104 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5799 22:14:51.632493 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5800 22:14:51.635685 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5801 22:14:51.639078 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5802 22:14:51.645786 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5803 22:14:51.649370 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5804 22:14:51.652563 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5805 22:14:51.658952 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5806 22:14:51.662391 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5807 22:14:51.665679 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5808 22:14:51.672599 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5809 22:14:51.675597 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5810 22:14:51.678670 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5811 22:14:51.685016 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5812 22:14:51.688571 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5813 22:14:51.691881 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5814 22:14:51.698308 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5815 22:14:51.701425 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5816 22:14:51.705038 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5817 22:14:51.708121 Total UI for P1: 0, mck2ui 16
5818 22:14:51.711466 best dqsien dly found for B0: ( 1, 2, 22)
5819 22:14:51.718118 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5820 22:14:51.721627 Total UI for P1: 0, mck2ui 16
5821 22:14:51.724552 best dqsien dly found for B1: ( 1, 2, 26)
5822 22:14:51.727994 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5823 22:14:51.731192 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5824 22:14:51.731262
5825 22:14:51.734648 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5826 22:14:51.738004 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5827 22:14:51.741161 [Gating] SW calibration Done
5828 22:14:51.741241 ==
5829 22:14:51.744525 Dram Type= 6, Freq= 0, CH_1, rank 1
5830 22:14:51.747812 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5831 22:14:51.747894 ==
5832 22:14:51.751123 RX Vref Scan: 0
5833 22:14:51.751204
5834 22:14:51.754375 RX Vref 0 -> 0, step: 1
5835 22:14:51.754455
5836 22:14:51.754517 RX Delay -80 -> 252, step: 8
5837 22:14:51.761133 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5838 22:14:51.764501 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5839 22:14:51.767709 iDelay=208, Bit 2, Center 79 (-16 ~ 175) 192
5840 22:14:51.771025 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5841 22:14:51.774455 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5842 22:14:51.777604 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5843 22:14:51.783974 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5844 22:14:51.787844 iDelay=208, Bit 7, Center 87 (-16 ~ 191) 208
5845 22:14:51.790718 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5846 22:14:51.793873 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5847 22:14:51.797681 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5848 22:14:51.803962 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5849 22:14:51.807579 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5850 22:14:51.810737 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5851 22:14:51.813770 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5852 22:14:51.817050 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5853 22:14:51.820348 ==
5854 22:14:51.823586 Dram Type= 6, Freq= 0, CH_1, rank 1
5855 22:14:51.827023 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5856 22:14:51.827105 ==
5857 22:14:51.827169 DQS Delay:
5858 22:14:51.830585 DQS0 = 0, DQS1 = 0
5859 22:14:51.830666 DQM Delay:
5860 22:14:51.833701 DQM0 = 93, DQM1 = 87
5861 22:14:51.833782 DQ Delay:
5862 22:14:51.837158 DQ0 =99, DQ1 =91, DQ2 =79, DQ3 =91
5863 22:14:51.840091 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =87
5864 22:14:51.843748 DQ8 =75, DQ9 =79, DQ10 =95, DQ11 =79
5865 22:14:51.846720 DQ12 =91, DQ13 =91, DQ14 =95, DQ15 =95
5866 22:14:51.846800
5867 22:14:51.846918
5868 22:14:51.846978 ==
5869 22:14:51.850405 Dram Type= 6, Freq= 0, CH_1, rank 1
5870 22:14:51.853322 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5871 22:14:51.853403 ==
5872 22:14:51.853466
5873 22:14:51.853525
5874 22:14:51.856698 TX Vref Scan disable
5875 22:14:51.860034 == TX Byte 0 ==
5876 22:14:51.863208 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5877 22:14:51.866633 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5878 22:14:51.870007 == TX Byte 1 ==
5879 22:14:51.873323 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5880 22:14:51.876640 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5881 22:14:51.876721 ==
5882 22:14:51.879969 Dram Type= 6, Freq= 0, CH_1, rank 1
5883 22:14:51.886405 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5884 22:14:51.886487 ==
5885 22:14:51.886551
5886 22:14:51.886614
5887 22:14:51.886671 TX Vref Scan disable
5888 22:14:51.890515 == TX Byte 0 ==
5889 22:14:51.893787 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5890 22:14:51.900156 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5891 22:14:51.900238 == TX Byte 1 ==
5892 22:14:51.903833 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5893 22:14:51.910048 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5894 22:14:51.910130
5895 22:14:51.910193 [DATLAT]
5896 22:14:51.910252 Freq=933, CH1 RK1
5897 22:14:51.910310
5898 22:14:51.913366 DATLAT Default: 0xb
5899 22:14:51.913447 0, 0xFFFF, sum = 0
5900 22:14:51.916731 1, 0xFFFF, sum = 0
5901 22:14:51.920262 2, 0xFFFF, sum = 0
5902 22:14:51.920337 3, 0xFFFF, sum = 0
5903 22:14:51.923654 4, 0xFFFF, sum = 0
5904 22:14:51.923730 5, 0xFFFF, sum = 0
5905 22:14:51.926817 6, 0xFFFF, sum = 0
5906 22:14:51.926945 7, 0xFFFF, sum = 0
5907 22:14:51.929654 8, 0xFFFF, sum = 0
5908 22:14:51.929750 9, 0xFFFF, sum = 0
5909 22:14:51.933445 10, 0x0, sum = 1
5910 22:14:51.933522 11, 0x0, sum = 2
5911 22:14:51.936832 12, 0x0, sum = 3
5912 22:14:51.936917 13, 0x0, sum = 4
5913 22:14:51.939632 best_step = 11
5914 22:14:51.939715
5915 22:14:51.939779 ==
5916 22:14:51.943009 Dram Type= 6, Freq= 0, CH_1, rank 1
5917 22:14:51.946539 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5918 22:14:51.946625 ==
5919 22:14:51.946690 RX Vref Scan: 0
5920 22:14:51.949530
5921 22:14:51.949639 RX Vref 0 -> 0, step: 1
5922 22:14:51.949704
5923 22:14:51.952782 RX Delay -69 -> 252, step: 4
5924 22:14:51.959660 iDelay=203, Bit 0, Center 96 (-1 ~ 194) 196
5925 22:14:51.963009 iDelay=203, Bit 1, Center 88 (-9 ~ 186) 196
5926 22:14:51.965910 iDelay=203, Bit 2, Center 80 (-17 ~ 178) 196
5927 22:14:51.969130 iDelay=203, Bit 3, Center 88 (-9 ~ 186) 196
5928 22:14:51.972721 iDelay=203, Bit 4, Center 90 (-5 ~ 186) 192
5929 22:14:51.979455 iDelay=203, Bit 5, Center 100 (3 ~ 198) 196
5930 22:14:51.982359 iDelay=203, Bit 6, Center 106 (11 ~ 202) 192
5931 22:14:51.985773 iDelay=203, Bit 7, Center 88 (-9 ~ 186) 196
5932 22:14:51.989174 iDelay=203, Bit 8, Center 76 (-17 ~ 170) 188
5933 22:14:51.992325 iDelay=203, Bit 9, Center 82 (-9 ~ 174) 184
5934 22:14:51.999147 iDelay=203, Bit 10, Center 92 (-1 ~ 186) 188
5935 22:14:52.002416 iDelay=203, Bit 11, Center 84 (-5 ~ 174) 180
5936 22:14:52.005656 iDelay=203, Bit 12, Center 100 (11 ~ 190) 180
5937 22:14:52.009189 iDelay=203, Bit 13, Center 100 (11 ~ 190) 180
5938 22:14:52.012375 iDelay=203, Bit 14, Center 98 (11 ~ 186) 176
5939 22:14:52.019042 iDelay=203, Bit 15, Center 96 (7 ~ 186) 180
5940 22:14:52.019121 ==
5941 22:14:52.022057 Dram Type= 6, Freq= 0, CH_1, rank 1
5942 22:14:52.025345 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5943 22:14:52.025425 ==
5944 22:14:52.025493 DQS Delay:
5945 22:14:52.029123 DQS0 = 0, DQS1 = 0
5946 22:14:52.029194 DQM Delay:
5947 22:14:52.032333 DQM0 = 92, DQM1 = 91
5948 22:14:52.032411 DQ Delay:
5949 22:14:52.035130 DQ0 =96, DQ1 =88, DQ2 =80, DQ3 =88
5950 22:14:52.038557 DQ4 =90, DQ5 =100, DQ6 =106, DQ7 =88
5951 22:14:52.041886 DQ8 =76, DQ9 =82, DQ10 =92, DQ11 =84
5952 22:14:52.045258 DQ12 =100, DQ13 =100, DQ14 =98, DQ15 =96
5953 22:14:52.045357
5954 22:14:52.045422
5955 22:14:52.055157 [DQSOSCAuto] RK1, (LSB)MR18= 0x1226, (MSB)MR19= 0x505, tDQSOscB0 = 409 ps tDQSOscB1 = 416 ps
5956 22:14:52.055241 CH1 RK1: MR19=505, MR18=1226
5957 22:14:52.061649 CH1_RK1: MR19=0x505, MR18=0x1226, DQSOSC=409, MR23=63, INC=64, DEC=43
5958 22:14:52.065084 [RxdqsGatingPostProcess] freq 933
5959 22:14:52.071340 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5960 22:14:52.075091 best DQS0 dly(2T, 0.5T) = (0, 10)
5961 22:14:52.078401 best DQS1 dly(2T, 0.5T) = (0, 10)
5962 22:14:52.081488 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5963 22:14:52.084771 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5964 22:14:52.087914 best DQS0 dly(2T, 0.5T) = (0, 10)
5965 22:14:52.091061 best DQS1 dly(2T, 0.5T) = (0, 10)
5966 22:14:52.091145 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5967 22:14:52.094743 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5968 22:14:52.097966 Pre-setting of DQS Precalculation
5969 22:14:52.104926 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5970 22:14:52.111049 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5971 22:14:52.117919 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5972 22:14:52.118013
5973 22:14:52.118090
5974 22:14:52.121234 [Calibration Summary] 1866 Mbps
5975 22:14:52.124529 CH 0, Rank 0
5976 22:14:52.124611 SW Impedance : PASS
5977 22:14:52.127669 DUTY Scan : NO K
5978 22:14:52.131039 ZQ Calibration : PASS
5979 22:14:52.131135 Jitter Meter : NO K
5980 22:14:52.134591 CBT Training : PASS
5981 22:14:52.137813 Write leveling : PASS
5982 22:14:52.137920 RX DQS gating : PASS
5983 22:14:52.140766 RX DQ/DQS(RDDQC) : PASS
5984 22:14:52.140848 TX DQ/DQS : PASS
5985 22:14:52.144064 RX DATLAT : PASS
5986 22:14:52.147492 RX DQ/DQS(Engine): PASS
5987 22:14:52.147591 TX OE : NO K
5988 22:14:52.150672 All Pass.
5989 22:14:52.150753
5990 22:14:52.150817 CH 0, Rank 1
5991 22:14:52.154056 SW Impedance : PASS
5992 22:14:52.154137 DUTY Scan : NO K
5993 22:14:52.157335 ZQ Calibration : PASS
5994 22:14:52.160502 Jitter Meter : NO K
5995 22:14:52.160603 CBT Training : PASS
5996 22:14:52.163891 Write leveling : PASS
5997 22:14:52.167400 RX DQS gating : PASS
5998 22:14:52.167472 RX DQ/DQS(RDDQC) : PASS
5999 22:14:52.170741 TX DQ/DQS : PASS
6000 22:14:52.173587 RX DATLAT : PASS
6001 22:14:52.173689 RX DQ/DQS(Engine): PASS
6002 22:14:52.176860 TX OE : NO K
6003 22:14:52.176944 All Pass.
6004 22:14:52.177006
6005 22:14:52.180176 CH 1, Rank 0
6006 22:14:52.180249 SW Impedance : PASS
6007 22:14:52.183483 DUTY Scan : NO K
6008 22:14:52.187091 ZQ Calibration : PASS
6009 22:14:52.187174 Jitter Meter : NO K
6010 22:14:52.190299 CBT Training : PASS
6011 22:14:52.193617 Write leveling : PASS
6012 22:14:52.193693 RX DQS gating : PASS
6013 22:14:52.196991 RX DQ/DQS(RDDQC) : PASS
6014 22:14:52.200322 TX DQ/DQS : PASS
6015 22:14:52.200397 RX DATLAT : PASS
6016 22:14:52.203453 RX DQ/DQS(Engine): PASS
6017 22:14:52.206712 TX OE : NO K
6018 22:14:52.206812 All Pass.
6019 22:14:52.206951
6020 22:14:52.207052 CH 1, Rank 1
6021 22:14:52.210050 SW Impedance : PASS
6022 22:14:52.213586 DUTY Scan : NO K
6023 22:14:52.213690 ZQ Calibration : PASS
6024 22:14:52.216652 Jitter Meter : NO K
6025 22:14:52.220087 CBT Training : PASS
6026 22:14:52.220165 Write leveling : PASS
6027 22:14:52.223136 RX DQS gating : PASS
6028 22:14:52.223216 RX DQ/DQS(RDDQC) : PASS
6029 22:14:52.226670 TX DQ/DQS : PASS
6030 22:14:52.230001 RX DATLAT : PASS
6031 22:14:52.230075 RX DQ/DQS(Engine): PASS
6032 22:14:52.233071 TX OE : NO K
6033 22:14:52.233150 All Pass.
6034 22:14:52.233247
6035 22:14:52.236469 DramC Write-DBI off
6036 22:14:52.239610 PER_BANK_REFRESH: Hybrid Mode
6037 22:14:52.239686 TX_TRACKING: ON
6038 22:14:52.249543 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6039 22:14:52.253433 [FAST_K] Save calibration result to emmc
6040 22:14:52.256487 dramc_set_vcore_voltage set vcore to 650000
6041 22:14:52.259792 Read voltage for 400, 6
6042 22:14:52.259872 Vio18 = 0
6043 22:14:52.263355 Vcore = 650000
6044 22:14:52.263430 Vdram = 0
6045 22:14:52.263509 Vddq = 0
6046 22:14:52.263583 Vmddr = 0
6047 22:14:52.269336 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6048 22:14:52.276063 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6049 22:14:52.276141 MEM_TYPE=3, freq_sel=20
6050 22:14:52.279430 sv_algorithm_assistance_LP4_800
6051 22:14:52.282375 ============ PULL DRAM RESETB DOWN ============
6052 22:14:52.289513 ========== PULL DRAM RESETB DOWN end =========
6053 22:14:52.292479 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6054 22:14:52.296307 ===================================
6055 22:14:52.298926 LPDDR4 DRAM CONFIGURATION
6056 22:14:52.302403 ===================================
6057 22:14:52.302479 EX_ROW_EN[0] = 0x0
6058 22:14:52.306103 EX_ROW_EN[1] = 0x0
6059 22:14:52.306176 LP4Y_EN = 0x0
6060 22:14:52.308745 WORK_FSP = 0x0
6061 22:14:52.308820 WL = 0x2
6062 22:14:52.312519 RL = 0x2
6063 22:14:52.315815 BL = 0x2
6064 22:14:52.315913 RPST = 0x0
6065 22:14:52.318824 RD_PRE = 0x0
6066 22:14:52.318965 WR_PRE = 0x1
6067 22:14:52.322092 WR_PST = 0x0
6068 22:14:52.322167 DBI_WR = 0x0
6069 22:14:52.325586 DBI_RD = 0x0
6070 22:14:52.325689 OTF = 0x1
6071 22:14:52.329131 ===================================
6072 22:14:52.332385 ===================================
6073 22:14:52.335558 ANA top config
6074 22:14:52.338817 ===================================
6075 22:14:52.338926 DLL_ASYNC_EN = 0
6076 22:14:52.342021 ALL_SLAVE_EN = 1
6077 22:14:52.345441 NEW_RANK_MODE = 1
6078 22:14:52.348946 DLL_IDLE_MODE = 1
6079 22:14:52.349025 LP45_APHY_COMB_EN = 1
6080 22:14:52.352230 TX_ODT_DIS = 1
6081 22:14:52.355060 NEW_8X_MODE = 1
6082 22:14:52.358346 ===================================
6083 22:14:52.361777 ===================================
6084 22:14:52.364925 data_rate = 800
6085 22:14:52.368546 CKR = 1
6086 22:14:52.372035 DQ_P2S_RATIO = 4
6087 22:14:52.374933 ===================================
6088 22:14:52.375035 CA_P2S_RATIO = 4
6089 22:14:52.378174 DQ_CA_OPEN = 0
6090 22:14:52.381588 DQ_SEMI_OPEN = 1
6091 22:14:52.384945 CA_SEMI_OPEN = 1
6092 22:14:52.388424 CA_FULL_RATE = 0
6093 22:14:52.391418 DQ_CKDIV4_EN = 0
6094 22:14:52.391527 CA_CKDIV4_EN = 1
6095 22:14:52.395106 CA_PREDIV_EN = 0
6096 22:14:52.398292 PH8_DLY = 0
6097 22:14:52.401440 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6098 22:14:52.404760 DQ_AAMCK_DIV = 0
6099 22:14:52.408335 CA_AAMCK_DIV = 0
6100 22:14:52.408436 CA_ADMCK_DIV = 4
6101 22:14:52.411523 DQ_TRACK_CA_EN = 0
6102 22:14:52.414453 CA_PICK = 800
6103 22:14:52.417608 CA_MCKIO = 400
6104 22:14:52.420949 MCKIO_SEMI = 400
6105 22:14:52.424080 PLL_FREQ = 3016
6106 22:14:52.427485 DQ_UI_PI_RATIO = 32
6107 22:14:52.430978 CA_UI_PI_RATIO = 32
6108 22:14:52.434469 ===================================
6109 22:14:52.437500 ===================================
6110 22:14:52.437599 memory_type:LPDDR4
6111 22:14:52.441003 GP_NUM : 10
6112 22:14:52.444512 SRAM_EN : 1
6113 22:14:52.444593 MD32_EN : 0
6114 22:14:52.447308 ===================================
6115 22:14:52.450610 [ANA_INIT] >>>>>>>>>>>>>>
6116 22:14:52.454011 <<<<<< [CONFIGURE PHASE]: ANA_TX
6117 22:14:52.457053 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6118 22:14:52.460482 ===================================
6119 22:14:52.464133 data_rate = 800,PCW = 0X7400
6120 22:14:52.467120 ===================================
6121 22:14:52.470521 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6122 22:14:52.473841 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6123 22:14:52.486803 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6124 22:14:52.490410 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6125 22:14:52.493667 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6126 22:14:52.496663 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6127 22:14:52.500143 [ANA_INIT] flow start
6128 22:14:52.504739 [ANA_INIT] PLL >>>>>>>>
6129 22:14:52.504821 [ANA_INIT] PLL <<<<<<<<
6130 22:14:52.506701 [ANA_INIT] MIDPI >>>>>>>>
6131 22:14:52.510053 [ANA_INIT] MIDPI <<<<<<<<
6132 22:14:52.510146 [ANA_INIT] DLL >>>>>>>>
6133 22:14:52.513130 [ANA_INIT] flow end
6134 22:14:52.516584 ============ LP4 DIFF to SE enter ============
6135 22:14:52.523379 ============ LP4 DIFF to SE exit ============
6136 22:14:52.523464 [ANA_INIT] <<<<<<<<<<<<<
6137 22:14:52.526298 [Flow] Enable top DCM control >>>>>
6138 22:14:52.529457 [Flow] Enable top DCM control <<<<<
6139 22:14:52.532991 Enable DLL master slave shuffle
6140 22:14:52.539313 ==============================================================
6141 22:14:52.539397 Gating Mode config
6142 22:14:52.545843 ==============================================================
6143 22:14:52.549519 Config description:
6144 22:14:52.558853 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6145 22:14:52.566302 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6146 22:14:52.569129 SELPH_MODE 0: By rank 1: By Phase
6147 22:14:52.575536 ==============================================================
6148 22:14:52.578841 GAT_TRACK_EN = 0
6149 22:14:52.581988 RX_GATING_MODE = 2
6150 22:14:52.585291 RX_GATING_TRACK_MODE = 2
6151 22:14:52.585375 SELPH_MODE = 1
6152 22:14:52.588908 PICG_EARLY_EN = 1
6153 22:14:52.592099 VALID_LAT_VALUE = 1
6154 22:14:52.598465 ==============================================================
6155 22:14:52.601849 Enter into Gating configuration >>>>
6156 22:14:52.605261 Exit from Gating configuration <<<<
6157 22:14:52.608657 Enter into DVFS_PRE_config >>>>>
6158 22:14:52.618420 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6159 22:14:52.621630 Exit from DVFS_PRE_config <<<<<
6160 22:14:52.624965 Enter into PICG configuration >>>>
6161 22:14:52.628354 Exit from PICG configuration <<<<
6162 22:14:52.631135 [RX_INPUT] configuration >>>>>
6163 22:14:52.634704 [RX_INPUT] configuration <<<<<
6164 22:14:52.641521 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6165 22:14:52.644651 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6166 22:14:52.651091 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6167 22:14:52.657892 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6168 22:14:52.664402 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6169 22:14:52.671042 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6170 22:14:52.674526 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6171 22:14:52.677823 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6172 22:14:52.680674 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6173 22:14:52.687450 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6174 22:14:52.690438 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6175 22:14:52.694230 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6176 22:14:52.697429 ===================================
6177 22:14:52.700302 LPDDR4 DRAM CONFIGURATION
6178 22:14:52.703726 ===================================
6179 22:14:52.703803 EX_ROW_EN[0] = 0x0
6180 22:14:52.707077 EX_ROW_EN[1] = 0x0
6181 22:14:52.710537 LP4Y_EN = 0x0
6182 22:14:52.710635 WORK_FSP = 0x0
6183 22:14:52.713441 WL = 0x2
6184 22:14:52.713533 RL = 0x2
6185 22:14:52.716899 BL = 0x2
6186 22:14:52.716999 RPST = 0x0
6187 22:14:52.720117 RD_PRE = 0x0
6188 22:14:52.720191 WR_PRE = 0x1
6189 22:14:52.724025 WR_PST = 0x0
6190 22:14:52.724098 DBI_WR = 0x0
6191 22:14:52.727272 DBI_RD = 0x0
6192 22:14:52.727368 OTF = 0x1
6193 22:14:52.730546 ===================================
6194 22:14:52.733816 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6195 22:14:52.739867 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6196 22:14:52.743334 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6197 22:14:52.747033 ===================================
6198 22:14:52.749858 LPDDR4 DRAM CONFIGURATION
6199 22:14:52.753031 ===================================
6200 22:14:52.756637 EX_ROW_EN[0] = 0x10
6201 22:14:52.756710 EX_ROW_EN[1] = 0x0
6202 22:14:52.759869 LP4Y_EN = 0x0
6203 22:14:52.759943 WORK_FSP = 0x0
6204 22:14:52.763515 WL = 0x2
6205 22:14:52.763589 RL = 0x2
6206 22:14:52.766579 BL = 0x2
6207 22:14:52.766655 RPST = 0x0
6208 22:14:52.769839 RD_PRE = 0x0
6209 22:14:52.769939 WR_PRE = 0x1
6210 22:14:52.773395 WR_PST = 0x0
6211 22:14:52.773491 DBI_WR = 0x0
6212 22:14:52.776605 DBI_RD = 0x0
6213 22:14:52.776677 OTF = 0x1
6214 22:14:52.779653 ===================================
6215 22:14:52.786225 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6216 22:14:52.791260 nWR fixed to 30
6217 22:14:52.794501 [ModeRegInit_LP4] CH0 RK0
6218 22:14:52.794602 [ModeRegInit_LP4] CH0 RK1
6219 22:14:52.797558 [ModeRegInit_LP4] CH1 RK0
6220 22:14:52.801020 [ModeRegInit_LP4] CH1 RK1
6221 22:14:52.801095 match AC timing 19
6222 22:14:52.807344 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6223 22:14:52.810850 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6224 22:14:52.814199 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6225 22:14:52.821003 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6226 22:14:52.824090 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6227 22:14:52.824163 ==
6228 22:14:52.827374 Dram Type= 6, Freq= 0, CH_0, rank 0
6229 22:14:52.831151 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6230 22:14:52.831252 ==
6231 22:14:52.837390 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6232 22:14:52.843556 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6233 22:14:52.846929 [CA 0] Center 36 (8~64) winsize 57
6234 22:14:52.850257 [CA 1] Center 36 (8~64) winsize 57
6235 22:14:52.853511 [CA 2] Center 36 (8~64) winsize 57
6236 22:14:52.857365 [CA 3] Center 36 (8~64) winsize 57
6237 22:14:52.860374 [CA 4] Center 36 (8~64) winsize 57
6238 22:14:52.860477 [CA 5] Center 36 (8~64) winsize 57
6239 22:14:52.863557
6240 22:14:52.866853 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6241 22:14:52.866991
6242 22:14:52.870119 [CATrainingPosCal] consider 1 rank data
6243 22:14:52.873170 u2DelayCellTimex100 = 270/100 ps
6244 22:14:52.876562 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6245 22:14:52.880021 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6246 22:14:52.883204 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6247 22:14:52.886403 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6248 22:14:52.889734 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6249 22:14:52.893136 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6250 22:14:52.893218
6251 22:14:52.896397 CA PerBit enable=1, Macro0, CA PI delay=36
6252 22:14:52.899766
6253 22:14:52.899847 [CBTSetCACLKResult] CA Dly = 36
6254 22:14:52.903401 CS Dly: 1 (0~32)
6255 22:14:52.903500 ==
6256 22:14:52.906705 Dram Type= 6, Freq= 0, CH_0, rank 1
6257 22:14:52.909666 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6258 22:14:52.909749 ==
6259 22:14:52.916395 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6260 22:14:52.923288 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6261 22:14:52.926357 [CA 0] Center 36 (8~64) winsize 57
6262 22:14:52.929624 [CA 1] Center 36 (8~64) winsize 57
6263 22:14:52.933150 [CA 2] Center 36 (8~64) winsize 57
6264 22:14:52.933232 [CA 3] Center 36 (8~64) winsize 57
6265 22:14:52.936735 [CA 4] Center 36 (8~64) winsize 57
6266 22:14:52.939370 [CA 5] Center 36 (8~64) winsize 57
6267 22:14:52.939452
6268 22:14:52.942623 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6269 22:14:52.946098
6270 22:14:52.949530 [CATrainingPosCal] consider 2 rank data
6271 22:14:52.952910 u2DelayCellTimex100 = 270/100 ps
6272 22:14:52.955992 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6273 22:14:52.959234 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6274 22:14:52.962821 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6275 22:14:52.966199 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6276 22:14:52.969552 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6277 22:14:52.972639 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6278 22:14:52.972759
6279 22:14:52.975764 CA PerBit enable=1, Macro0, CA PI delay=36
6280 22:14:52.975851
6281 22:14:52.979359 [CBTSetCACLKResult] CA Dly = 36
6282 22:14:52.982316 CS Dly: 1 (0~32)
6283 22:14:52.982397
6284 22:14:52.985561 ----->DramcWriteLeveling(PI) begin...
6285 22:14:52.985645 ==
6286 22:14:52.989326 Dram Type= 6, Freq= 0, CH_0, rank 0
6287 22:14:52.992520 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6288 22:14:52.992604 ==
6289 22:14:52.995676 Write leveling (Byte 0): 40 => 8
6290 22:14:52.999044 Write leveling (Byte 1): 40 => 8
6291 22:14:53.002370 DramcWriteLeveling(PI) end<-----
6292 22:14:53.002450
6293 22:14:53.002526 ==
6294 22:14:53.005469 Dram Type= 6, Freq= 0, CH_0, rank 0
6295 22:14:53.008546 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6296 22:14:53.008629 ==
6297 22:14:53.011995 [Gating] SW mode calibration
6298 22:14:53.018674 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6299 22:14:53.025761 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6300 22:14:53.028719 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6301 22:14:53.035588 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6302 22:14:53.038310 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6303 22:14:53.041698 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6304 22:14:53.045341 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6305 22:14:53.051676 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6306 22:14:53.054981 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6307 22:14:53.058310 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6308 22:14:53.064771 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6309 22:14:53.068767 Total UI for P1: 0, mck2ui 16
6310 22:14:53.071647 best dqsien dly found for B0: ( 0, 14, 24)
6311 22:14:53.074962 Total UI for P1: 0, mck2ui 16
6312 22:14:53.078340 best dqsien dly found for B1: ( 0, 14, 24)
6313 22:14:53.081672 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6314 22:14:53.084649 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6315 22:14:53.084759
6316 22:14:53.088353 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6317 22:14:53.091444 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6318 22:14:53.094518 [Gating] SW calibration Done
6319 22:14:53.094616 ==
6320 22:14:53.097687 Dram Type= 6, Freq= 0, CH_0, rank 0
6321 22:14:53.101430 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6322 22:14:53.101544 ==
6323 22:14:53.104746 RX Vref Scan: 0
6324 22:14:53.104855
6325 22:14:53.107639 RX Vref 0 -> 0, step: 1
6326 22:14:53.107719
6327 22:14:53.111400 RX Delay -410 -> 252, step: 16
6328 22:14:53.114598 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6329 22:14:53.117874 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6330 22:14:53.121333 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6331 22:14:53.128052 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6332 22:14:53.131051 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6333 22:14:53.133963 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6334 22:14:53.137427 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6335 22:14:53.144108 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6336 22:14:53.147811 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6337 22:14:53.150886 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6338 22:14:53.153778 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6339 22:14:53.160661 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6340 22:14:53.164080 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6341 22:14:53.167511 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6342 22:14:53.174000 iDelay=230, Bit 14, Center -35 (-298 ~ 229) 528
6343 22:14:53.177115 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6344 22:14:53.177192 ==
6345 22:14:53.180168 Dram Type= 6, Freq= 0, CH_0, rank 0
6346 22:14:53.183566 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6347 22:14:53.183681 ==
6348 22:14:53.187239 DQS Delay:
6349 22:14:53.187341 DQS0 = 59, DQS1 = 59
6350 22:14:53.187431 DQM Delay:
6351 22:14:53.190283 DQM0 = 18, DQM1 = 10
6352 22:14:53.190367 DQ Delay:
6353 22:14:53.193585 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6354 22:14:53.197016 DQ4 =16, DQ5 =0, DQ6 =32, DQ7 =32
6355 22:14:53.200290 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6356 22:14:53.203644 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6357 22:14:53.203716
6358 22:14:53.203776
6359 22:14:53.203831 ==
6360 22:14:53.206337 Dram Type= 6, Freq= 0, CH_0, rank 0
6361 22:14:53.213165 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6362 22:14:53.213239 ==
6363 22:14:53.213299
6364 22:14:53.213356
6365 22:14:53.213410 TX Vref Scan disable
6366 22:14:53.216467 == TX Byte 0 ==
6367 22:14:53.219692 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6368 22:14:53.223212 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6369 22:14:53.226651 == TX Byte 1 ==
6370 22:14:53.229487 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6371 22:14:53.232792 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6372 22:14:53.232875 ==
6373 22:14:53.236137 Dram Type= 6, Freq= 0, CH_0, rank 0
6374 22:14:53.242565 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6375 22:14:53.242648 ==
6376 22:14:53.242712
6377 22:14:53.242772
6378 22:14:53.245935 TX Vref Scan disable
6379 22:14:53.246018 == TX Byte 0 ==
6380 22:14:53.249742 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6381 22:14:53.256257 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6382 22:14:53.256355 == TX Byte 1 ==
6383 22:14:53.259509 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6384 22:14:53.262812 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6385 22:14:53.266172
6386 22:14:53.266270 [DATLAT]
6387 22:14:53.266348 Freq=400, CH0 RK0
6388 22:14:53.266408
6389 22:14:53.268984 DATLAT Default: 0xf
6390 22:14:53.269091 0, 0xFFFF, sum = 0
6391 22:14:53.272422 1, 0xFFFF, sum = 0
6392 22:14:53.272505 2, 0xFFFF, sum = 0
6393 22:14:53.275794 3, 0xFFFF, sum = 0
6394 22:14:53.278894 4, 0xFFFF, sum = 0
6395 22:14:53.278996 5, 0xFFFF, sum = 0
6396 22:14:53.282740 6, 0xFFFF, sum = 0
6397 22:14:53.282823 7, 0xFFFF, sum = 0
6398 22:14:53.286169 8, 0xFFFF, sum = 0
6399 22:14:53.286252 9, 0xFFFF, sum = 0
6400 22:14:53.288798 10, 0xFFFF, sum = 0
6401 22:14:53.288881 11, 0xFFFF, sum = 0
6402 22:14:53.292456 12, 0xFFFF, sum = 0
6403 22:14:53.292539 13, 0x0, sum = 1
6404 22:14:53.295453 14, 0x0, sum = 2
6405 22:14:53.295536 15, 0x0, sum = 3
6406 22:14:53.298685 16, 0x0, sum = 4
6407 22:14:53.298801 best_step = 14
6408 22:14:53.298920
6409 22:14:53.299016 ==
6410 22:14:53.301979 Dram Type= 6, Freq= 0, CH_0, rank 0
6411 22:14:53.305578 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6412 22:14:53.308742 ==
6413 22:14:53.308824 RX Vref Scan: 1
6414 22:14:53.308889
6415 22:14:53.311931 RX Vref 0 -> 0, step: 1
6416 22:14:53.312013
6417 22:14:53.315177 RX Delay -359 -> 252, step: 8
6418 22:14:53.315260
6419 22:14:53.318774 Set Vref, RX VrefLevel [Byte0]: 64
6420 22:14:53.321961 [Byte1]: 58
6421 22:14:53.322043
6422 22:14:53.325487 Final RX Vref Byte 0 = 64 to rank0
6423 22:14:53.328467 Final RX Vref Byte 1 = 58 to rank0
6424 22:14:53.331822 Final RX Vref Byte 0 = 64 to rank1
6425 22:14:53.334798 Final RX Vref Byte 1 = 58 to rank1==
6426 22:14:53.338389 Dram Type= 6, Freq= 0, CH_0, rank 0
6427 22:14:53.341745 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6428 22:14:53.345006 ==
6429 22:14:53.345087 DQS Delay:
6430 22:14:53.345151 DQS0 = 60, DQS1 = 68
6431 22:14:53.348503 DQM Delay:
6432 22:14:53.348583 DQM0 = 15, DQM1 = 14
6433 22:14:53.351662 DQ Delay:
6434 22:14:53.354512 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =8
6435 22:14:53.354595 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6436 22:14:53.358086 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6437 22:14:53.361535 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =20
6438 22:14:53.361612
6439 22:14:53.364445
6440 22:14:53.371313 [DQSOSCAuto] RK0, (LSB)MR18= 0x817f, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
6441 22:14:53.374893 CH0 RK0: MR19=C0C, MR18=817F
6442 22:14:53.381357 CH0_RK0: MR19=0xC0C, MR18=0x817F, DQSOSC=393, MR23=63, INC=382, DEC=254
6443 22:14:53.381431 ==
6444 22:14:53.384758 Dram Type= 6, Freq= 0, CH_0, rank 1
6445 22:14:53.387911 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6446 22:14:53.388027 ==
6447 22:14:53.391201 [Gating] SW mode calibration
6448 22:14:53.397786 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6449 22:14:53.404223 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6450 22:14:53.407712 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6451 22:14:53.411010 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6452 22:14:53.417525 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6453 22:14:53.420787 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6454 22:14:53.424096 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6455 22:14:53.431255 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6456 22:14:53.434582 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6457 22:14:53.437550 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6458 22:14:53.443929 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6459 22:14:53.444012 Total UI for P1: 0, mck2ui 16
6460 22:14:53.450556 best dqsien dly found for B0: ( 0, 14, 24)
6461 22:14:53.450639 Total UI for P1: 0, mck2ui 16
6462 22:14:53.454049 best dqsien dly found for B1: ( 0, 14, 24)
6463 22:14:53.460517 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6464 22:14:53.463799 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6465 22:14:53.463881
6466 22:14:53.467042 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6467 22:14:53.470332 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6468 22:14:53.473646 [Gating] SW calibration Done
6469 22:14:53.473728 ==
6470 22:14:53.477295 Dram Type= 6, Freq= 0, CH_0, rank 1
6471 22:14:53.480375 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6472 22:14:53.480457 ==
6473 22:14:53.483811 RX Vref Scan: 0
6474 22:14:53.483893
6475 22:14:53.483957 RX Vref 0 -> 0, step: 1
6476 22:14:53.484017
6477 22:14:53.487090 RX Delay -410 -> 252, step: 16
6478 22:14:53.493403 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6479 22:14:53.496783 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6480 22:14:53.499640 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6481 22:14:53.503437 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6482 22:14:53.509923 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6483 22:14:53.513280 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6484 22:14:53.516374 iDelay=230, Bit 6, Center -35 (-298 ~ 229) 528
6485 22:14:53.519645 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6486 22:14:53.526225 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6487 22:14:53.529422 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6488 22:14:53.533090 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6489 22:14:53.539340 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6490 22:14:53.542574 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6491 22:14:53.546071 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6492 22:14:53.549509 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6493 22:14:53.556202 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6494 22:14:53.556286 ==
6495 22:14:53.559512 Dram Type= 6, Freq= 0, CH_0, rank 1
6496 22:14:53.562408 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6497 22:14:53.562491 ==
6498 22:14:53.562555 DQS Delay:
6499 22:14:53.565658 DQS0 = 59, DQS1 = 59
6500 22:14:53.565740 DQM Delay:
6501 22:14:53.569068 DQM0 = 17, DQM1 = 10
6502 22:14:53.569150 DQ Delay:
6503 22:14:53.572678 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6504 22:14:53.575977 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =32
6505 22:14:53.579249 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6506 22:14:53.582118 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6507 22:14:53.582200
6508 22:14:53.582265
6509 22:14:53.582323 ==
6510 22:14:53.585512 Dram Type= 6, Freq= 0, CH_0, rank 1
6511 22:14:53.588927 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6512 22:14:53.589014 ==
6513 22:14:53.592311
6514 22:14:53.592393
6515 22:14:53.592457 TX Vref Scan disable
6516 22:14:53.595163 == TX Byte 0 ==
6517 22:14:53.598949 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6518 22:14:53.602067 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6519 22:14:53.605528 == TX Byte 1 ==
6520 22:14:53.608388 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6521 22:14:53.612143 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6522 22:14:53.612226 ==
6523 22:14:53.615238 Dram Type= 6, Freq= 0, CH_0, rank 1
6524 22:14:53.618453 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6525 22:14:53.621988 ==
6526 22:14:53.622070
6527 22:14:53.622133
6528 22:14:53.622192 TX Vref Scan disable
6529 22:14:53.625338 == TX Byte 0 ==
6530 22:14:53.628419 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6531 22:14:53.631542 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6532 22:14:53.634849 == TX Byte 1 ==
6533 22:14:53.638177 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6534 22:14:53.641907 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6535 22:14:53.641990
6536 22:14:53.644845 [DATLAT]
6537 22:14:53.644927 Freq=400, CH0 RK1
6538 22:14:53.644991
6539 22:14:53.648313 DATLAT Default: 0xe
6540 22:14:53.648395 0, 0xFFFF, sum = 0
6541 22:14:53.651474 1, 0xFFFF, sum = 0
6542 22:14:53.651558 2, 0xFFFF, sum = 0
6543 22:14:53.654875 3, 0xFFFF, sum = 0
6544 22:14:53.654958 4, 0xFFFF, sum = 0
6545 22:14:53.658009 5, 0xFFFF, sum = 0
6546 22:14:53.658092 6, 0xFFFF, sum = 0
6547 22:14:53.661334 7, 0xFFFF, sum = 0
6548 22:14:53.661417 8, 0xFFFF, sum = 0
6549 22:14:53.664613 9, 0xFFFF, sum = 0
6550 22:14:53.664697 10, 0xFFFF, sum = 0
6551 22:14:53.668075 11, 0xFFFF, sum = 0
6552 22:14:53.671373 12, 0xFFFF, sum = 0
6553 22:14:53.671456 13, 0x0, sum = 1
6554 22:14:53.674675 14, 0x0, sum = 2
6555 22:14:53.674758 15, 0x0, sum = 3
6556 22:14:53.674823 16, 0x0, sum = 4
6557 22:14:53.678233 best_step = 14
6558 22:14:53.678315
6559 22:14:53.678378 ==
6560 22:14:53.681485 Dram Type= 6, Freq= 0, CH_0, rank 1
6561 22:14:53.684375 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6562 22:14:53.684461 ==
6563 22:14:53.687811 RX Vref Scan: 0
6564 22:14:53.687893
6565 22:14:53.687957 RX Vref 0 -> 0, step: 1
6566 22:14:53.691072
6567 22:14:53.691154 RX Delay -359 -> 252, step: 8
6568 22:14:53.699552 iDelay=217, Bit 0, Center -52 (-303 ~ 200) 504
6569 22:14:53.702785 iDelay=217, Bit 1, Center -44 (-295 ~ 208) 504
6570 22:14:53.706215 iDelay=217, Bit 2, Center -56 (-303 ~ 192) 496
6571 22:14:53.712590 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6572 22:14:53.715952 iDelay=217, Bit 4, Center -52 (-303 ~ 200) 504
6573 22:14:53.719069 iDelay=217, Bit 5, Center -60 (-311 ~ 192) 504
6574 22:14:53.722347 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
6575 22:14:53.729116 iDelay=217, Bit 7, Center -36 (-287 ~ 216) 504
6576 22:14:53.732295 iDelay=217, Bit 8, Center -60 (-311 ~ 192) 504
6577 22:14:53.735596 iDelay=217, Bit 9, Center -68 (-319 ~ 184) 504
6578 22:14:53.738854 iDelay=217, Bit 10, Center -52 (-303 ~ 200) 504
6579 22:14:53.745225 iDelay=217, Bit 11, Center -60 (-311 ~ 192) 504
6580 22:14:53.748884 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
6581 22:14:53.752353 iDelay=217, Bit 13, Center -52 (-303 ~ 200) 504
6582 22:14:53.758840 iDelay=217, Bit 14, Center -44 (-295 ~ 208) 504
6583 22:14:53.761987 iDelay=217, Bit 15, Center -48 (-303 ~ 208) 512
6584 22:14:53.762068 ==
6585 22:14:53.765359 Dram Type= 6, Freq= 0, CH_0, rank 1
6586 22:14:53.768786 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6587 22:14:53.768868 ==
6588 22:14:53.771644 DQS Delay:
6589 22:14:53.771725 DQS0 = 60, DQS1 = 68
6590 22:14:53.771789 DQM Delay:
6591 22:14:53.774860 DQM0 = 11, DQM1 = 14
6592 22:14:53.774954 DQ Delay:
6593 22:14:53.778258 DQ0 =8, DQ1 =16, DQ2 =4, DQ3 =8
6594 22:14:53.781694 DQ4 =8, DQ5 =0, DQ6 =24, DQ7 =24
6595 22:14:53.785396 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6596 22:14:53.788155 DQ12 =20, DQ13 =16, DQ14 =24, DQ15 =20
6597 22:14:53.788254
6598 22:14:53.788319
6599 22:14:53.798131 [DQSOSCAuto] RK1, (LSB)MR18= 0xca80, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 384 ps
6600 22:14:53.798214 CH0 RK1: MR19=C0C, MR18=CA80
6601 22:14:53.804631 CH0_RK1: MR19=0xC0C, MR18=0xCA80, DQSOSC=384, MR23=63, INC=400, DEC=267
6602 22:14:53.808111 [RxdqsGatingPostProcess] freq 400
6603 22:14:53.814104 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6604 22:14:53.817506 best DQS0 dly(2T, 0.5T) = (0, 10)
6605 22:14:53.820864 best DQS1 dly(2T, 0.5T) = (0, 10)
6606 22:14:53.824011 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6607 22:14:53.827747 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6608 22:14:53.830790 best DQS0 dly(2T, 0.5T) = (0, 10)
6609 22:14:53.834062 best DQS1 dly(2T, 0.5T) = (0, 10)
6610 22:14:53.837222 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6611 22:14:53.840939 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6612 22:14:53.844287 Pre-setting of DQS Precalculation
6613 22:14:53.847334 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6614 22:14:53.847408 ==
6615 22:14:53.850473 Dram Type= 6, Freq= 0, CH_1, rank 0
6616 22:14:53.853706 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6617 22:14:53.853780 ==
6618 22:14:53.860421 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6619 22:14:53.866759 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6620 22:14:53.870407 [CA 0] Center 36 (8~64) winsize 57
6621 22:14:53.873306 [CA 1] Center 36 (8~64) winsize 57
6622 22:14:53.876841 [CA 2] Center 36 (8~64) winsize 57
6623 22:14:53.880005 [CA 3] Center 36 (8~64) winsize 57
6624 22:14:53.883756 [CA 4] Center 36 (8~64) winsize 57
6625 22:14:53.886658 [CA 5] Center 36 (8~64) winsize 57
6626 22:14:53.886728
6627 22:14:53.890082 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6628 22:14:53.890162
6629 22:14:53.893562 [CATrainingPosCal] consider 1 rank data
6630 22:14:53.896418 u2DelayCellTimex100 = 270/100 ps
6631 22:14:53.899747 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6632 22:14:53.903359 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6633 22:14:53.906477 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6634 22:14:53.910038 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6635 22:14:53.913177 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6636 22:14:53.916614 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6637 22:14:53.916686
6638 22:14:53.922815 CA PerBit enable=1, Macro0, CA PI delay=36
6639 22:14:53.922925
6640 22:14:53.922987 [CBTSetCACLKResult] CA Dly = 36
6641 22:14:53.926358 CS Dly: 1 (0~32)
6642 22:14:53.926439 ==
6643 22:14:53.929759 Dram Type= 6, Freq= 0, CH_1, rank 1
6644 22:14:53.932782 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6645 22:14:53.932864 ==
6646 22:14:53.939667 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6647 22:14:53.946091 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6648 22:14:53.949275 [CA 0] Center 36 (8~64) winsize 57
6649 22:14:53.952507 [CA 1] Center 36 (8~64) winsize 57
6650 22:14:53.956271 [CA 2] Center 36 (8~64) winsize 57
6651 22:14:53.959097 [CA 3] Center 36 (8~64) winsize 57
6652 22:14:53.962629 [CA 4] Center 36 (8~64) winsize 57
6653 22:14:53.962709 [CA 5] Center 36 (8~64) winsize 57
6654 22:14:53.965837
6655 22:14:53.969034 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6656 22:14:53.969115
6657 22:14:53.972597 [CATrainingPosCal] consider 2 rank data
6658 22:14:53.975470 u2DelayCellTimex100 = 270/100 ps
6659 22:14:53.979275 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6660 22:14:53.982095 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6661 22:14:53.985569 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6662 22:14:53.988999 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6663 22:14:53.992446 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6664 22:14:53.995171 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6665 22:14:53.995252
6666 22:14:53.998931 CA PerBit enable=1, Macro0, CA PI delay=36
6667 22:14:54.002072
6668 22:14:54.002153 [CBTSetCACLKResult] CA Dly = 36
6669 22:14:54.005330 CS Dly: 1 (0~32)
6670 22:14:54.005411
6671 22:14:54.009014 ----->DramcWriteLeveling(PI) begin...
6672 22:14:54.009098 ==
6673 22:14:54.011854 Dram Type= 6, Freq= 0, CH_1, rank 0
6674 22:14:54.015165 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6675 22:14:54.015247 ==
6676 22:14:54.018450 Write leveling (Byte 0): 40 => 8
6677 22:14:54.021605 Write leveling (Byte 1): 40 => 8
6678 22:14:54.024976 DramcWriteLeveling(PI) end<-----
6679 22:14:54.025058
6680 22:14:54.025121 ==
6681 22:14:54.028444 Dram Type= 6, Freq= 0, CH_1, rank 0
6682 22:14:54.031360 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6683 22:14:54.035073 ==
6684 22:14:54.035155 [Gating] SW mode calibration
6685 22:14:54.041373 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6686 22:14:54.047994 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6687 22:14:54.051218 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6688 22:14:54.057907 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6689 22:14:54.061358 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6690 22:14:54.064810 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6691 22:14:54.071475 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6692 22:14:54.074389 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6693 22:14:54.077730 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6694 22:14:54.084629 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6695 22:14:54.087420 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6696 22:14:54.090806 Total UI for P1: 0, mck2ui 16
6697 22:14:54.094336 best dqsien dly found for B0: ( 0, 14, 24)
6698 22:14:54.097807 Total UI for P1: 0, mck2ui 16
6699 22:14:54.100578 best dqsien dly found for B1: ( 0, 14, 24)
6700 22:14:54.104552 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6701 22:14:54.107288 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6702 22:14:54.107362
6703 22:14:54.110777 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6704 22:14:54.117367 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6705 22:14:54.117473 [Gating] SW calibration Done
6706 22:14:54.117564 ==
6707 22:14:54.120697 Dram Type= 6, Freq= 0, CH_1, rank 0
6708 22:14:54.127339 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6709 22:14:54.127427 ==
6710 22:14:54.127490 RX Vref Scan: 0
6711 22:14:54.127548
6712 22:14:54.130324 RX Vref 0 -> 0, step: 1
6713 22:14:54.130405
6714 22:14:54.133834 RX Delay -410 -> 252, step: 16
6715 22:14:54.137148 iDelay=230, Bit 0, Center -35 (-298 ~ 229) 528
6716 22:14:54.140501 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6717 22:14:54.146779 iDelay=230, Bit 2, Center -51 (-314 ~ 213) 528
6718 22:14:54.150023 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6719 22:14:54.153541 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6720 22:14:54.156662 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6721 22:14:54.163086 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6722 22:14:54.166408 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6723 22:14:54.169871 iDelay=230, Bit 8, Center -67 (-330 ~ 197) 528
6724 22:14:54.172993 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6725 22:14:54.179645 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6726 22:14:54.183215 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6727 22:14:54.186372 iDelay=230, Bit 12, Center -35 (-298 ~ 229) 528
6728 22:14:54.192752 iDelay=230, Bit 13, Center -35 (-298 ~ 229) 528
6729 22:14:54.196388 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6730 22:14:54.199545 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6731 22:14:54.199620 ==
6732 22:14:54.203044 Dram Type= 6, Freq= 0, CH_1, rank 0
6733 22:14:54.205914 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6734 22:14:54.209205 ==
6735 22:14:54.209286 DQS Delay:
6736 22:14:54.209349 DQS0 = 51, DQS1 = 67
6737 22:14:54.212572 DQM Delay:
6738 22:14:54.212643 DQM0 = 12, DQM1 = 19
6739 22:14:54.216261 DQ Delay:
6740 22:14:54.216331 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6741 22:14:54.219384 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6742 22:14:54.222814 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6743 22:14:54.225959 DQ12 =32, DQ13 =32, DQ14 =24, DQ15 =24
6744 22:14:54.226059
6745 22:14:54.226137
6746 22:14:54.229519 ==
6747 22:14:54.229600 Dram Type= 6, Freq= 0, CH_1, rank 0
6748 22:14:54.236406 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6749 22:14:54.236484 ==
6750 22:14:54.236547
6751 22:14:54.236605
6752 22:14:54.239504 TX Vref Scan disable
6753 22:14:54.239577 == TX Byte 0 ==
6754 22:14:54.242594 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6755 22:14:54.249905 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6756 22:14:54.249979 == TX Byte 1 ==
6757 22:14:54.252264 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6758 22:14:54.259027 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6759 22:14:54.259109 ==
6760 22:14:54.262133 Dram Type= 6, Freq= 0, CH_1, rank 0
6761 22:14:54.265831 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6762 22:14:54.265912 ==
6763 22:14:54.265975
6764 22:14:54.266034
6765 22:14:54.268921 TX Vref Scan disable
6766 22:14:54.269001 == TX Byte 0 ==
6767 22:14:54.272118 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6768 22:14:54.278407 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6769 22:14:54.278488 == TX Byte 1 ==
6770 22:14:54.281791 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6771 22:14:54.288957 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6772 22:14:54.289063
6773 22:14:54.289170 [DATLAT]
6774 22:14:54.289262 Freq=400, CH1 RK0
6775 22:14:54.292111
6776 22:14:54.292192 DATLAT Default: 0xf
6777 22:14:54.295410 0, 0xFFFF, sum = 0
6778 22:14:54.295492 1, 0xFFFF, sum = 0
6779 22:14:54.298750 2, 0xFFFF, sum = 0
6780 22:14:54.298839 3, 0xFFFF, sum = 0
6781 22:14:54.302022 4, 0xFFFF, sum = 0
6782 22:14:54.302104 5, 0xFFFF, sum = 0
6783 22:14:54.305023 6, 0xFFFF, sum = 0
6784 22:14:54.305109 7, 0xFFFF, sum = 0
6785 22:14:54.308470 8, 0xFFFF, sum = 0
6786 22:14:54.308560 9, 0xFFFF, sum = 0
6787 22:14:54.311835 10, 0xFFFF, sum = 0
6788 22:14:54.311917 11, 0xFFFF, sum = 0
6789 22:14:54.315180 12, 0xFFFF, sum = 0
6790 22:14:54.315262 13, 0x0, sum = 1
6791 22:14:54.318311 14, 0x0, sum = 2
6792 22:14:54.318393 15, 0x0, sum = 3
6793 22:14:54.321849 16, 0x0, sum = 4
6794 22:14:54.321936 best_step = 14
6795 22:14:54.322000
6796 22:14:54.322059 ==
6797 22:14:54.325122 Dram Type= 6, Freq= 0, CH_1, rank 0
6798 22:14:54.331442 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6799 22:14:54.331525 ==
6800 22:14:54.331588 RX Vref Scan: 1
6801 22:14:54.331648
6802 22:14:54.335055 RX Vref 0 -> 0, step: 1
6803 22:14:54.335136
6804 22:14:54.338414 RX Delay -375 -> 252, step: 8
6805 22:14:54.338495
6806 22:14:54.341306 Set Vref, RX VrefLevel [Byte0]: 53
6807 22:14:54.344719 [Byte1]: 47
6808 22:14:54.348172
6809 22:14:54.348267 Final RX Vref Byte 0 = 53 to rank0
6810 22:14:54.351029 Final RX Vref Byte 1 = 47 to rank0
6811 22:14:54.354469 Final RX Vref Byte 0 = 53 to rank1
6812 22:14:54.358065 Final RX Vref Byte 1 = 47 to rank1==
6813 22:14:54.361405 Dram Type= 6, Freq= 0, CH_1, rank 0
6814 22:14:54.367626 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6815 22:14:54.367709 ==
6816 22:14:54.367773 DQS Delay:
6817 22:14:54.371387 DQS0 = 52, DQS1 = 68
6818 22:14:54.371469 DQM Delay:
6819 22:14:54.371534 DQM0 = 9, DQM1 = 14
6820 22:14:54.374589 DQ Delay:
6821 22:14:54.378023 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =4
6822 22:14:54.378129 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =4
6823 22:14:54.381130 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6824 22:14:54.384026 DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =20
6825 22:14:54.384137
6826 22:14:54.387479
6827 22:14:54.394768 [DQSOSCAuto] RK0, (LSB)MR18= 0x5a6d, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 398 ps
6828 22:14:54.397349 CH1 RK0: MR19=C0C, MR18=5A6D
6829 22:14:54.404196 CH1_RK0: MR19=0xC0C, MR18=0x5A6D, DQSOSC=396, MR23=63, INC=376, DEC=251
6830 22:14:54.404281 ==
6831 22:14:54.407647 Dram Type= 6, Freq= 0, CH_1, rank 1
6832 22:14:54.410386 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6833 22:14:54.410464 ==
6834 22:14:54.413725 [Gating] SW mode calibration
6835 22:14:54.420434 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6836 22:14:54.427134 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6837 22:14:54.430407 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6838 22:14:54.433730 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6839 22:14:54.440454 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6840 22:14:54.443698 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6841 22:14:54.447009 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6842 22:14:54.453368 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6843 22:14:54.457068 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6844 22:14:54.460192 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6845 22:14:54.466599 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6846 22:14:54.466681 Total UI for P1: 0, mck2ui 16
6847 22:14:54.473475 best dqsien dly found for B0: ( 0, 14, 24)
6848 22:14:54.473580 Total UI for P1: 0, mck2ui 16
6849 22:14:54.479608 best dqsien dly found for B1: ( 0, 14, 24)
6850 22:14:54.483118 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6851 22:14:54.486325 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6852 22:14:54.486427
6853 22:14:54.489617 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6854 22:14:54.493112 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6855 22:14:54.496350 [Gating] SW calibration Done
6856 22:14:54.496457 ==
6857 22:14:54.499549 Dram Type= 6, Freq= 0, CH_1, rank 1
6858 22:14:54.502989 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6859 22:14:54.503092 ==
6860 22:14:54.506135 RX Vref Scan: 0
6861 22:14:54.506206
6862 22:14:54.509595 RX Vref 0 -> 0, step: 1
6863 22:14:54.509682
6864 22:14:54.509746 RX Delay -410 -> 252, step: 16
6865 22:14:54.516089 iDelay=230, Bit 0, Center -35 (-298 ~ 229) 528
6866 22:14:54.519943 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6867 22:14:54.522416 iDelay=230, Bit 2, Center -59 (-314 ~ 197) 512
6868 22:14:54.525873 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6869 22:14:54.532557 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6870 22:14:54.535612 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6871 22:14:54.539539 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6872 22:14:54.542841 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6873 22:14:54.549427 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6874 22:14:54.552159 iDelay=230, Bit 9, Center -51 (-314 ~ 213) 528
6875 22:14:54.556029 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6876 22:14:54.562368 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6877 22:14:54.565702 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6878 22:14:54.568896 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6879 22:14:54.571974 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6880 22:14:54.578756 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6881 22:14:54.578877 ==
6882 22:14:54.582003 Dram Type= 6, Freq= 0, CH_1, rank 1
6883 22:14:54.585407 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6884 22:14:54.585491 ==
6885 22:14:54.585574 DQS Delay:
6886 22:14:54.588818 DQS0 = 59, DQS1 = 59
6887 22:14:54.588935 DQM Delay:
6888 22:14:54.591964 DQM0 = 19, DQM1 = 12
6889 22:14:54.592045 DQ Delay:
6890 22:14:54.595176 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6891 22:14:54.598748 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6892 22:14:54.601968 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6893 22:14:54.605224 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6894 22:14:54.605306
6895 22:14:54.605369
6896 22:14:54.605427 ==
6897 22:14:54.608524 Dram Type= 6, Freq= 0, CH_1, rank 1
6898 22:14:54.611919 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6899 22:14:54.615206 ==
6900 22:14:54.615287
6901 22:14:54.615350
6902 22:14:54.615409 TX Vref Scan disable
6903 22:14:54.618211 == TX Byte 0 ==
6904 22:14:54.621489 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6905 22:14:54.625023 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6906 22:14:54.628426 == TX Byte 1 ==
6907 22:14:54.631217 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6908 22:14:54.634635 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6909 22:14:54.634717 ==
6910 22:14:54.638114 Dram Type= 6, Freq= 0, CH_1, rank 1
6911 22:14:54.644694 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6912 22:14:54.644776 ==
6913 22:14:54.644839
6914 22:14:54.644898
6915 22:14:54.644954 TX Vref Scan disable
6916 22:14:54.648457 == TX Byte 0 ==
6917 22:14:54.650935 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6918 22:14:54.654672 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6919 22:14:54.657570 == TX Byte 1 ==
6920 22:14:54.660981 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6921 22:14:54.664284 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6922 22:14:54.664365
6923 22:14:54.667666 [DATLAT]
6924 22:14:54.667747 Freq=400, CH1 RK1
6925 22:14:54.667810
6926 22:14:54.671076 DATLAT Default: 0xe
6927 22:14:54.671157 0, 0xFFFF, sum = 0
6928 22:14:54.674149 1, 0xFFFF, sum = 0
6929 22:14:54.674231 2, 0xFFFF, sum = 0
6930 22:14:54.677400 3, 0xFFFF, sum = 0
6931 22:14:54.677482 4, 0xFFFF, sum = 0
6932 22:14:54.680557 5, 0xFFFF, sum = 0
6933 22:14:54.680640 6, 0xFFFF, sum = 0
6934 22:14:54.683741 7, 0xFFFF, sum = 0
6935 22:14:54.687313 8, 0xFFFF, sum = 0
6936 22:14:54.687397 9, 0xFFFF, sum = 0
6937 22:14:54.690455 10, 0xFFFF, sum = 0
6938 22:14:54.690540 11, 0xFFFF, sum = 0
6939 22:14:54.693534 12, 0xFFFF, sum = 0
6940 22:14:54.693628 13, 0x0, sum = 1
6941 22:14:54.697192 14, 0x0, sum = 2
6942 22:14:54.697274 15, 0x0, sum = 3
6943 22:14:54.700450 16, 0x0, sum = 4
6944 22:14:54.700526 best_step = 14
6945 22:14:54.700588
6946 22:14:54.700655 ==
6947 22:14:54.703728 Dram Type= 6, Freq= 0, CH_1, rank 1
6948 22:14:54.706726 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6949 22:14:54.706799 ==
6950 22:14:54.710536 RX Vref Scan: 0
6951 22:14:54.710606
6952 22:14:54.713655 RX Vref 0 -> 0, step: 1
6953 22:14:54.713735
6954 22:14:54.713796 RX Delay -359 -> 252, step: 8
6955 22:14:54.722539 iDelay=217, Bit 0, Center -40 (-287 ~ 208) 496
6956 22:14:54.726064 iDelay=217, Bit 1, Center -52 (-303 ~ 200) 504
6957 22:14:54.728964 iDelay=217, Bit 2, Center -60 (-311 ~ 192) 504
6958 22:14:54.735605 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6959 22:14:54.739096 iDelay=217, Bit 4, Center -44 (-295 ~ 208) 504
6960 22:14:54.742530 iDelay=217, Bit 5, Center -36 (-287 ~ 216) 504
6961 22:14:54.745786 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
6962 22:14:54.751860 iDelay=217, Bit 7, Center -52 (-303 ~ 200) 504
6963 22:14:54.755303 iDelay=217, Bit 8, Center -64 (-319 ~ 192) 512
6964 22:14:54.758595 iDelay=217, Bit 9, Center -64 (-319 ~ 192) 512
6965 22:14:54.762100 iDelay=217, Bit 10, Center -48 (-303 ~ 208) 512
6966 22:14:54.768959 iDelay=217, Bit 11, Center -60 (-311 ~ 192) 504
6967 22:14:54.772292 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
6968 22:14:54.775193 iDelay=217, Bit 13, Center -48 (-303 ~ 208) 512
6969 22:14:54.778574 iDelay=217, Bit 14, Center -48 (-303 ~ 208) 512
6970 22:14:54.785084 iDelay=217, Bit 15, Center -48 (-303 ~ 208) 512
6971 22:14:54.785186 ==
6972 22:14:54.788546 Dram Type= 6, Freq= 0, CH_1, rank 1
6973 22:14:54.791853 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6974 22:14:54.791954 ==
6975 22:14:54.792033 DQS Delay:
6976 22:14:54.795083 DQS0 = 60, DQS1 = 64
6977 22:14:54.795153 DQM Delay:
6978 22:14:54.798231 DQM0 = 13, DQM1 = 10
6979 22:14:54.798308 DQ Delay:
6980 22:14:54.801498 DQ0 =20, DQ1 =8, DQ2 =0, DQ3 =8
6981 22:14:54.805162 DQ4 =16, DQ5 =24, DQ6 =24, DQ7 =8
6982 22:14:54.808482 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6983 22:14:54.811685 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6984 22:14:54.811759
6985 22:14:54.811818
6986 22:14:54.821178 [DQSOSCAuto] RK1, (LSB)MR18= 0x7aab, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 394 ps
6987 22:14:54.821256 CH1 RK1: MR19=C0C, MR18=7AAB
6988 22:14:54.827993 CH1_RK1: MR19=0xC0C, MR18=0x7AAB, DQSOSC=388, MR23=63, INC=392, DEC=261
6989 22:14:54.831325 [RxdqsGatingPostProcess] freq 400
6990 22:14:54.838051 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6991 22:14:54.840934 best DQS0 dly(2T, 0.5T) = (0, 10)
6992 22:14:54.844360 best DQS1 dly(2T, 0.5T) = (0, 10)
6993 22:14:54.847609 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6994 22:14:54.850972 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6995 22:14:54.854321 best DQS0 dly(2T, 0.5T) = (0, 10)
6996 22:14:54.854411 best DQS1 dly(2T, 0.5T) = (0, 10)
6997 22:14:54.857559 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6998 22:14:54.861028 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6999 22:14:54.864090 Pre-setting of DQS Precalculation
7000 22:14:54.870798 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7001 22:14:54.877165 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7002 22:14:54.884371 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7003 22:14:54.884448
7004 22:14:54.884514
7005 22:14:54.887080 [Calibration Summary] 800 Mbps
7006 22:14:54.890247 CH 0, Rank 0
7007 22:14:54.890332 SW Impedance : PASS
7008 22:14:54.893981 DUTY Scan : NO K
7009 22:14:54.896877 ZQ Calibration : PASS
7010 22:14:54.896973 Jitter Meter : NO K
7011 22:14:54.900482 CBT Training : PASS
7012 22:14:54.903931 Write leveling : PASS
7013 22:14:54.904035 RX DQS gating : PASS
7014 22:14:54.907140 RX DQ/DQS(RDDQC) : PASS
7015 22:14:54.907213 TX DQ/DQS : PASS
7016 22:14:54.910418 RX DATLAT : PASS
7017 22:14:54.913600 RX DQ/DQS(Engine): PASS
7018 22:14:54.913681 TX OE : NO K
7019 22:14:54.916865 All Pass.
7020 22:14:54.916977
7021 22:14:54.917134 CH 0, Rank 1
7022 22:14:54.920016 SW Impedance : PASS
7023 22:14:54.920097 DUTY Scan : NO K
7024 22:14:54.923467 ZQ Calibration : PASS
7025 22:14:54.926558 Jitter Meter : NO K
7026 22:14:54.926639 CBT Training : PASS
7027 22:14:54.930060 Write leveling : NO K
7028 22:14:54.933598 RX DQS gating : PASS
7029 22:14:54.933710 RX DQ/DQS(RDDQC) : PASS
7030 22:14:54.936749 TX DQ/DQS : PASS
7031 22:14:54.939978 RX DATLAT : PASS
7032 22:14:54.940054 RX DQ/DQS(Engine): PASS
7033 22:14:54.943354 TX OE : NO K
7034 22:14:54.943427 All Pass.
7035 22:14:54.943527
7036 22:14:54.946717 CH 1, Rank 0
7037 22:14:54.946813 SW Impedance : PASS
7038 22:14:54.949591 DUTY Scan : NO K
7039 22:14:54.953430 ZQ Calibration : PASS
7040 22:14:54.953519 Jitter Meter : NO K
7041 22:14:54.956745 CBT Training : PASS
7042 22:14:54.959678 Write leveling : PASS
7043 22:14:54.959767 RX DQS gating : PASS
7044 22:14:54.962890 RX DQ/DQS(RDDQC) : PASS
7045 22:14:54.966489 TX DQ/DQS : PASS
7046 22:14:54.966585 RX DATLAT : PASS
7047 22:14:54.969820 RX DQ/DQS(Engine): PASS
7048 22:14:54.972748 TX OE : NO K
7049 22:14:54.972821 All Pass.
7050 22:14:54.972882
7051 22:14:54.972941 CH 1, Rank 1
7052 22:14:54.976767 SW Impedance : PASS
7053 22:14:54.979313 DUTY Scan : NO K
7054 22:14:54.979387 ZQ Calibration : PASS
7055 22:14:54.983037 Jitter Meter : NO K
7056 22:14:54.983111 CBT Training : PASS
7057 22:14:54.986207 Write leveling : NO K
7058 22:14:54.989546 RX DQS gating : PASS
7059 22:14:54.989677 RX DQ/DQS(RDDQC) : PASS
7060 22:14:54.993134 TX DQ/DQS : PASS
7061 22:14:54.995661 RX DATLAT : PASS
7062 22:14:54.995761 RX DQ/DQS(Engine): PASS
7063 22:14:54.999488 TX OE : NO K
7064 22:14:54.999562 All Pass.
7065 22:14:54.999623
7066 22:14:55.002518 DramC Write-DBI off
7067 22:14:55.005702 PER_BANK_REFRESH: Hybrid Mode
7068 22:14:55.005800 TX_TRACKING: ON
7069 22:14:55.015486 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7070 22:14:55.018689 [FAST_K] Save calibration result to emmc
7071 22:14:55.022378 dramc_set_vcore_voltage set vcore to 725000
7072 22:14:55.025790 Read voltage for 1600, 0
7073 22:14:55.025896 Vio18 = 0
7074 22:14:55.028900 Vcore = 725000
7075 22:14:55.029002 Vdram = 0
7076 22:14:55.029101 Vddq = 0
7077 22:14:55.029198 Vmddr = 0
7078 22:14:55.035267 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7079 22:14:55.041967 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7080 22:14:55.042074 MEM_TYPE=3, freq_sel=13
7081 22:14:55.045541 sv_algorithm_assistance_LP4_3733
7082 22:14:55.048836 ============ PULL DRAM RESETB DOWN ============
7083 22:14:55.055586 ========== PULL DRAM RESETB DOWN end =========
7084 22:14:55.058364 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7085 22:14:55.061693 ===================================
7086 22:14:55.065007 LPDDR4 DRAM CONFIGURATION
7087 22:14:55.068657 ===================================
7088 22:14:55.068769 EX_ROW_EN[0] = 0x0
7089 22:14:55.071584 EX_ROW_EN[1] = 0x0
7090 22:14:55.074920 LP4Y_EN = 0x0
7091 22:14:55.075024 WORK_FSP = 0x1
7092 22:14:55.078158 WL = 0x5
7093 22:14:55.078231 RL = 0x5
7094 22:14:55.081640 BL = 0x2
7095 22:14:55.081741 RPST = 0x0
7096 22:14:55.084638 RD_PRE = 0x0
7097 22:14:55.084733 WR_PRE = 0x1
7098 22:14:55.088120 WR_PST = 0x1
7099 22:14:55.088214 DBI_WR = 0x0
7100 22:14:55.091401 DBI_RD = 0x0
7101 22:14:55.091496 OTF = 0x1
7102 22:14:55.094922 ===================================
7103 22:14:55.097673 ===================================
7104 22:14:55.101347 ANA top config
7105 22:14:55.104208 ===================================
7106 22:14:55.107403 DLL_ASYNC_EN = 0
7107 22:14:55.107534 ALL_SLAVE_EN = 0
7108 22:14:55.111084 NEW_RANK_MODE = 1
7109 22:14:55.114411 DLL_IDLE_MODE = 1
7110 22:14:55.117596 LP45_APHY_COMB_EN = 1
7111 22:14:55.117694 TX_ODT_DIS = 0
7112 22:14:55.120782 NEW_8X_MODE = 1
7113 22:14:55.124387 ===================================
7114 22:14:55.127064 ===================================
7115 22:14:55.131233 data_rate = 3200
7116 22:14:55.134215 CKR = 1
7117 22:14:55.137493 DQ_P2S_RATIO = 8
7118 22:14:55.140585 ===================================
7119 22:14:55.143994 CA_P2S_RATIO = 8
7120 22:14:55.146912 DQ_CA_OPEN = 0
7121 22:14:55.147010 DQ_SEMI_OPEN = 0
7122 22:14:55.150424 CA_SEMI_OPEN = 0
7123 22:14:55.153668 CA_FULL_RATE = 0
7124 22:14:55.157053 DQ_CKDIV4_EN = 0
7125 22:14:55.160083 CA_CKDIV4_EN = 0
7126 22:14:55.163719 CA_PREDIV_EN = 0
7127 22:14:55.163860 PH8_DLY = 12
7128 22:14:55.166616 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7129 22:14:55.170399 DQ_AAMCK_DIV = 4
7130 22:14:55.173097 CA_AAMCK_DIV = 4
7131 22:14:55.176389 CA_ADMCK_DIV = 4
7132 22:14:55.180317 DQ_TRACK_CA_EN = 0
7133 22:14:55.183100 CA_PICK = 1600
7134 22:14:55.183189 CA_MCKIO = 1600
7135 22:14:55.186984 MCKIO_SEMI = 0
7136 22:14:55.189911 PLL_FREQ = 3068
7137 22:14:55.193273 DQ_UI_PI_RATIO = 32
7138 22:14:55.196132 CA_UI_PI_RATIO = 0
7139 22:14:55.199741 ===================================
7140 22:14:55.202959 ===================================
7141 22:14:55.206178 memory_type:LPDDR4
7142 22:14:55.206293 GP_NUM : 10
7143 22:14:55.209608 SRAM_EN : 1
7144 22:14:55.209715 MD32_EN : 0
7145 22:14:55.213009 ===================================
7146 22:14:55.216443 [ANA_INIT] >>>>>>>>>>>>>>
7147 22:14:55.219618 <<<<<< [CONFIGURE PHASE]: ANA_TX
7148 22:14:55.222852 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7149 22:14:55.226075 ===================================
7150 22:14:55.229208 data_rate = 3200,PCW = 0X7600
7151 22:14:55.232977 ===================================
7152 22:14:55.236026 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7153 22:14:55.242673 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7154 22:14:55.245752 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7155 22:14:55.252353 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7156 22:14:55.255770 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7157 22:14:55.259196 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7158 22:14:55.259271 [ANA_INIT] flow start
7159 22:14:55.262064 [ANA_INIT] PLL >>>>>>>>
7160 22:14:55.265907 [ANA_INIT] PLL <<<<<<<<
7161 22:14:55.268695 [ANA_INIT] MIDPI >>>>>>>>
7162 22:14:55.268768 [ANA_INIT] MIDPI <<<<<<<<
7163 22:14:55.272101 [ANA_INIT] DLL >>>>>>>>
7164 22:14:55.275392 [ANA_INIT] DLL <<<<<<<<
7165 22:14:55.275466 [ANA_INIT] flow end
7166 22:14:55.279130 ============ LP4 DIFF to SE enter ============
7167 22:14:55.285764 ============ LP4 DIFF to SE exit ============
7168 22:14:55.285862 [ANA_INIT] <<<<<<<<<<<<<
7169 22:14:55.288601 [Flow] Enable top DCM control >>>>>
7170 22:14:55.291994 [Flow] Enable top DCM control <<<<<
7171 22:14:55.295346 Enable DLL master slave shuffle
7172 22:14:55.302106 ==============================================================
7173 22:14:55.305550 Gating Mode config
7174 22:14:55.308454 ==============================================================
7175 22:14:55.311681 Config description:
7176 22:14:55.321876 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7177 22:14:55.328475 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7178 22:14:55.331620 SELPH_MODE 0: By rank 1: By Phase
7179 22:14:55.337874 ==============================================================
7180 22:14:55.341638 GAT_TRACK_EN = 1
7181 22:14:55.344685 RX_GATING_MODE = 2
7182 22:14:55.347954 RX_GATING_TRACK_MODE = 2
7183 22:14:55.348034 SELPH_MODE = 1
7184 22:14:55.351712 PICG_EARLY_EN = 1
7185 22:14:55.355040 VALID_LAT_VALUE = 1
7186 22:14:55.361712 ==============================================================
7187 22:14:55.364786 Enter into Gating configuration >>>>
7188 22:14:55.368023 Exit from Gating configuration <<<<
7189 22:14:55.371234 Enter into DVFS_PRE_config >>>>>
7190 22:14:55.381061 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7191 22:14:55.384557 Exit from DVFS_PRE_config <<<<<
7192 22:14:55.387995 Enter into PICG configuration >>>>
7193 22:14:55.391161 Exit from PICG configuration <<<<
7194 22:14:55.394584 [RX_INPUT] configuration >>>>>
7195 22:14:55.397898 [RX_INPUT] configuration <<<<<
7196 22:14:55.401229 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7197 22:14:55.407407 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7198 22:14:55.414309 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7199 22:14:55.421148 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7200 22:14:55.427286 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7201 22:14:55.434228 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7202 22:14:55.437441 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7203 22:14:55.440711 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7204 22:14:55.443771 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7205 22:14:55.450196 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7206 22:14:55.453406 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7207 22:14:55.457077 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7208 22:14:55.460650 ===================================
7209 22:14:55.463733 LPDDR4 DRAM CONFIGURATION
7210 22:14:55.466551 ===================================
7211 22:14:55.466631 EX_ROW_EN[0] = 0x0
7212 22:14:55.469860 EX_ROW_EN[1] = 0x0
7213 22:14:55.473240 LP4Y_EN = 0x0
7214 22:14:55.473311 WORK_FSP = 0x1
7215 22:14:55.476557 WL = 0x5
7216 22:14:55.476655 RL = 0x5
7217 22:14:55.480008 BL = 0x2
7218 22:14:55.480083 RPST = 0x0
7219 22:14:55.483019 RD_PRE = 0x0
7220 22:14:55.483090 WR_PRE = 0x1
7221 22:14:55.486741 WR_PST = 0x1
7222 22:14:55.486842 DBI_WR = 0x0
7223 22:14:55.489524 DBI_RD = 0x0
7224 22:14:55.489602 OTF = 0x1
7225 22:14:55.493271 ===================================
7226 22:14:55.496281 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7227 22:14:55.502965 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7228 22:14:55.506310 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7229 22:14:55.509346 ===================================
7230 22:14:55.512618 LPDDR4 DRAM CONFIGURATION
7231 22:14:55.516083 ===================================
7232 22:14:55.516155 EX_ROW_EN[0] = 0x10
7233 22:14:55.519505 EX_ROW_EN[1] = 0x0
7234 22:14:55.522721 LP4Y_EN = 0x0
7235 22:14:55.522819 WORK_FSP = 0x1
7236 22:14:55.525971 WL = 0x5
7237 22:14:55.526076 RL = 0x5
7238 22:14:55.529521 BL = 0x2
7239 22:14:55.529592 RPST = 0x0
7240 22:14:55.532550 RD_PRE = 0x0
7241 22:14:55.532631 WR_PRE = 0x1
7242 22:14:55.536091 WR_PST = 0x1
7243 22:14:55.536173 DBI_WR = 0x0
7244 22:14:55.539357 DBI_RD = 0x0
7245 22:14:55.539439 OTF = 0x1
7246 22:14:55.542348 ===================================
7247 22:14:55.549480 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7248 22:14:55.549563 ==
7249 22:14:55.552617 Dram Type= 6, Freq= 0, CH_0, rank 0
7250 22:14:55.555763 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7251 22:14:55.558947 ==
7252 22:14:55.559029 [Duty_Offset_Calibration]
7253 22:14:55.562451 B0:2 B1:0 CA:3
7254 22:14:55.562534
7255 22:14:55.565529 [DutyScan_Calibration_Flow] k_type=0
7256 22:14:55.574798
7257 22:14:55.574915 ==CLK 0==
7258 22:14:55.578279 Final CLK duty delay cell = 0
7259 22:14:55.581397 [0] MAX Duty = 5031%(X100), DQS PI = 12
7260 22:14:55.584775 [0] MIN Duty = 4907%(X100), DQS PI = 2
7261 22:14:55.584857 [0] AVG Duty = 4969%(X100)
7262 22:14:55.587960
7263 22:14:55.591279 CH0 CLK Duty spec in!! Max-Min= 124%
7264 22:14:55.594645 [DutyScan_Calibration_Flow] ====Done====
7265 22:14:55.594752
7266 22:14:55.597481 [DutyScan_Calibration_Flow] k_type=1
7267 22:14:55.614138
7268 22:14:55.614220 ==DQS 0 ==
7269 22:14:55.617404 Final DQS duty delay cell = 0
7270 22:14:55.620916 [0] MAX Duty = 5094%(X100), DQS PI = 14
7271 22:14:55.624325 [0] MIN Duty = 4875%(X100), DQS PI = 50
7272 22:14:55.627637 [0] AVG Duty = 4984%(X100)
7273 22:14:55.627719
7274 22:14:55.627784 ==DQS 1 ==
7275 22:14:55.630959 Final DQS duty delay cell = 0
7276 22:14:55.634297 [0] MAX Duty = 5156%(X100), DQS PI = 32
7277 22:14:55.637348 [0] MIN Duty = 5062%(X100), DQS PI = 8
7278 22:14:55.641030 [0] AVG Duty = 5109%(X100)
7279 22:14:55.641112
7280 22:14:55.644357 CH0 DQS 0 Duty spec in!! Max-Min= 219%
7281 22:14:55.644439
7282 22:14:55.647623 CH0 DQS 1 Duty spec in!! Max-Min= 94%
7283 22:14:55.650740 [DutyScan_Calibration_Flow] ====Done====
7284 22:14:55.650881
7285 22:14:55.653976 [DutyScan_Calibration_Flow] k_type=3
7286 22:14:55.672135
7287 22:14:55.672217 ==DQM 0 ==
7288 22:14:55.675077 Final DQM duty delay cell = 0
7289 22:14:55.678533 [0] MAX Duty = 5156%(X100), DQS PI = 30
7290 22:14:55.682028 [0] MIN Duty = 4875%(X100), DQS PI = 0
7291 22:14:55.685227 [0] AVG Duty = 5015%(X100)
7292 22:14:55.685309
7293 22:14:55.685373 ==DQM 1 ==
7294 22:14:55.688456 Final DQM duty delay cell = 4
7295 22:14:55.691807 [4] MAX Duty = 5187%(X100), DQS PI = 60
7296 22:14:55.695030 [4] MIN Duty = 5031%(X100), DQS PI = 12
7297 22:14:55.698501 [4] AVG Duty = 5109%(X100)
7298 22:14:55.698582
7299 22:14:55.701825 CH0 DQM 0 Duty spec in!! Max-Min= 281%
7300 22:14:55.701906
7301 22:14:55.704756 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7302 22:14:55.708258 [DutyScan_Calibration_Flow] ====Done====
7303 22:14:55.708338
7304 22:14:55.711510 [DutyScan_Calibration_Flow] k_type=2
7305 22:14:55.728462
7306 22:14:55.728542 ==DQ 0 ==
7307 22:14:55.731927 Final DQ duty delay cell = -4
7308 22:14:55.734792 [-4] MAX Duty = 5000%(X100), DQS PI = 12
7309 22:14:55.738167 [-4] MIN Duty = 4876%(X100), DQS PI = 0
7310 22:14:55.741500 [-4] AVG Duty = 4938%(X100)
7311 22:14:55.741579
7312 22:14:55.741641 ==DQ 1 ==
7313 22:14:55.744785 Final DQ duty delay cell = 0
7314 22:14:55.747834 [0] MAX Duty = 5156%(X100), DQS PI = 60
7315 22:14:55.751296 [0] MIN Duty = 5000%(X100), DQS PI = 16
7316 22:14:55.754318 [0] AVG Duty = 5078%(X100)
7317 22:14:55.754392
7318 22:14:55.757858 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7319 22:14:55.757932
7320 22:14:55.761213 CH0 DQ 1 Duty spec in!! Max-Min= 156%
7321 22:14:55.764408 [DutyScan_Calibration_Flow] ====Done====
7322 22:14:55.764478 ==
7323 22:14:55.767729 Dram Type= 6, Freq= 0, CH_1, rank 0
7324 22:14:55.770911 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7325 22:14:55.770985 ==
7326 22:14:55.774124 [Duty_Offset_Calibration]
7327 22:14:55.774197 B0:1 B1:-2 CA:0
7328 22:14:55.777166
7329 22:14:55.780379 [DutyScan_Calibration_Flow] k_type=0
7330 22:14:55.788607
7331 22:14:55.788685 ==CLK 0==
7332 22:14:55.792035 Final CLK duty delay cell = 0
7333 22:14:55.795544 [0] MAX Duty = 5093%(X100), DQS PI = 22
7334 22:14:55.798679 [0] MIN Duty = 4844%(X100), DQS PI = 58
7335 22:14:55.801614 [0] AVG Duty = 4968%(X100)
7336 22:14:55.801685
7337 22:14:55.805077 CH1 CLK Duty spec in!! Max-Min= 249%
7338 22:14:55.808418 [DutyScan_Calibration_Flow] ====Done====
7339 22:14:55.808488
7340 22:14:55.811787 [DutyScan_Calibration_Flow] k_type=1
7341 22:14:55.827635
7342 22:14:55.827712 ==DQS 0 ==
7343 22:14:55.830888 Final DQS duty delay cell = -4
7344 22:14:55.834352 [-4] MAX Duty = 5000%(X100), DQS PI = 26
7345 22:14:55.837413 [-4] MIN Duty = 4844%(X100), DQS PI = 46
7346 22:14:55.840674 [-4] AVG Duty = 4922%(X100)
7347 22:14:55.840745
7348 22:14:55.840806 ==DQS 1 ==
7349 22:14:55.843929 Final DQS duty delay cell = 0
7350 22:14:55.847122 [0] MAX Duty = 5093%(X100), DQS PI = 0
7351 22:14:55.850486 [0] MIN Duty = 4844%(X100), DQS PI = 24
7352 22:14:55.854082 [0] AVG Duty = 4968%(X100)
7353 22:14:55.854155
7354 22:14:55.857343 CH1 DQS 0 Duty spec in!! Max-Min= 156%
7355 22:14:55.857418
7356 22:14:55.860497 CH1 DQS 1 Duty spec in!! Max-Min= 249%
7357 22:14:55.864104 [DutyScan_Calibration_Flow] ====Done====
7358 22:14:55.864184
7359 22:14:55.866837 [DutyScan_Calibration_Flow] k_type=3
7360 22:14:55.884438
7361 22:14:55.884516 ==DQM 0 ==
7362 22:14:55.887682 Final DQM duty delay cell = 0
7363 22:14:55.890975 [0] MAX Duty = 5031%(X100), DQS PI = 24
7364 22:14:55.894694 [0] MIN Duty = 4813%(X100), DQS PI = 56
7365 22:14:55.897667 [0] AVG Duty = 4922%(X100)
7366 22:14:55.897740
7367 22:14:55.897802 ==DQM 1 ==
7368 22:14:55.901114 Final DQM duty delay cell = 0
7369 22:14:55.904217 [0] MAX Duty = 5093%(X100), DQS PI = 36
7370 22:14:55.907529 [0] MIN Duty = 4875%(X100), DQS PI = 24
7371 22:14:55.911000 [0] AVG Duty = 4984%(X100)
7372 22:14:55.911072
7373 22:14:55.914397 CH1 DQM 0 Duty spec in!! Max-Min= 218%
7374 22:14:55.914484
7375 22:14:55.917768 CH1 DQM 1 Duty spec in!! Max-Min= 218%
7376 22:14:55.921186 [DutyScan_Calibration_Flow] ====Done====
7377 22:14:55.921258
7378 22:14:55.923858 [DutyScan_Calibration_Flow] k_type=2
7379 22:14:55.941408
7380 22:14:55.941484 ==DQ 0 ==
7381 22:14:55.944893 Final DQ duty delay cell = 0
7382 22:14:55.947891 [0] MAX Duty = 5093%(X100), DQS PI = 22
7383 22:14:55.951232 [0] MIN Duty = 4907%(X100), DQS PI = 46
7384 22:14:55.954442 [0] AVG Duty = 5000%(X100)
7385 22:14:55.954520
7386 22:14:55.954584 ==DQ 1 ==
7387 22:14:55.957843 Final DQ duty delay cell = 0
7388 22:14:55.961175 [0] MAX Duty = 5156%(X100), DQS PI = 36
7389 22:14:55.964379 [0] MIN Duty = 4969%(X100), DQS PI = 24
7390 22:14:55.964451 [0] AVG Duty = 5062%(X100)
7391 22:14:55.967514
7392 22:14:55.971197 CH1 DQ 0 Duty spec in!! Max-Min= 186%
7393 22:14:55.971270
7394 22:14:55.974403 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7395 22:14:55.977632 [DutyScan_Calibration_Flow] ====Done====
7396 22:14:55.981180 nWR fixed to 30
7397 22:14:55.984441 [ModeRegInit_LP4] CH0 RK0
7398 22:14:55.984515 [ModeRegInit_LP4] CH0 RK1
7399 22:14:55.987690 [ModeRegInit_LP4] CH1 RK0
7400 22:14:55.990859 [ModeRegInit_LP4] CH1 RK1
7401 22:14:55.990972 match AC timing 5
7402 22:14:55.997935 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7403 22:14:56.001032 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7404 22:14:56.004211 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7405 22:14:56.010744 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7406 22:14:56.014046 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7407 22:14:56.014119 [MiockJmeterHQA]
7408 22:14:56.014180
7409 22:14:56.017449 [DramcMiockJmeter] u1RxGatingPI = 0
7410 22:14:56.020816 0 : 4255, 4029
7411 22:14:56.020889 4 : 4255, 4030
7412 22:14:56.023597 8 : 4255, 4029
7413 22:14:56.023668 12 : 4368, 4139
7414 22:14:56.026924 16 : 4253, 4027
7415 22:14:56.026994 20 : 4255, 4029
7416 22:14:56.027054 24 : 4255, 4029
7417 22:14:56.030208 28 : 4368, 4140
7418 22:14:56.030281 32 : 4368, 4140
7419 22:14:56.033631 36 : 4252, 4027
7420 22:14:56.033702 40 : 4257, 4029
7421 22:14:56.036847 44 : 4255, 4029
7422 22:14:56.036948 48 : 4255, 4029
7423 22:14:56.040463 52 : 4365, 4140
7424 22:14:56.040541 56 : 4368, 4140
7425 22:14:56.040621 60 : 4255, 4029
7426 22:14:56.043830 64 : 4257, 4029
7427 22:14:56.043900 68 : 4257, 4032
7428 22:14:56.046712 72 : 4365, 4139
7429 22:14:56.046783 76 : 4255, 4029
7430 22:14:56.050069 80 : 4366, 4140
7431 22:14:56.050140 84 : 4250, 4027
7432 22:14:56.053319 88 : 4254, 4029
7433 22:14:56.053392 92 : 4253, 4029
7434 22:14:56.053453 96 : 4253, 4029
7435 22:14:56.056694 100 : 4255, 4030
7436 22:14:56.056769 104 : 4363, 3779
7437 22:14:56.060398 108 : 4252, 1
7438 22:14:56.060477 112 : 4363, 0
7439 22:14:56.063418 116 : 4252, 0
7440 22:14:56.063490 120 : 4252, 0
7441 22:14:56.063551 124 : 4363, 0
7442 22:14:56.066839 128 : 4363, 0
7443 22:14:56.066943 132 : 4255, 0
7444 22:14:56.070022 136 : 4252, 0
7445 22:14:56.070092 140 : 4252, 0
7446 22:14:56.070151 144 : 4255, 0
7447 22:14:56.073186 148 : 4363, 0
7448 22:14:56.073257 152 : 4250, 0
7449 22:14:56.076771 156 : 4363, 0
7450 22:14:56.076851 160 : 4253, 0
7451 22:14:56.076912 164 : 4252, 0
7452 22:14:56.079993 168 : 4252, 0
7453 22:14:56.080064 172 : 4363, 0
7454 22:14:56.080124 176 : 4363, 0
7455 22:14:56.083473 180 : 4250, 0
7456 22:14:56.083547 184 : 4250, 0
7457 22:14:56.086395 188 : 4252, 0
7458 22:14:56.086498 192 : 4252, 0
7459 22:14:56.086587 196 : 4258, 0
7460 22:14:56.089433 200 : 4252, 0
7461 22:14:56.089536 204 : 4363, 0
7462 22:14:56.093134 208 : 4363, 0
7463 22:14:56.093214 212 : 4253, 0
7464 22:14:56.093277 216 : 4363, 0
7465 22:14:56.096165 220 : 4252, 0
7466 22:14:56.096236 224 : 4253, 0
7467 22:14:56.099601 228 : 4363, 0
7468 22:14:56.099679 232 : 4252, 0
7469 22:14:56.099742 236 : 4255, 1230
7470 22:14:56.103268 240 : 4254, 4029
7471 22:14:56.103339 244 : 4366, 4140
7472 22:14:56.105992 248 : 4255, 4030
7473 22:14:56.106060 252 : 4252, 4029
7474 22:14:56.109371 256 : 4368, 4142
7475 22:14:56.109445 260 : 4255, 4029
7476 22:14:56.112583 264 : 4255, 4029
7477 22:14:56.112683 268 : 4365, 4140
7478 22:14:56.115938 272 : 4255, 4029
7479 22:14:56.116010 276 : 4363, 4140
7480 22:14:56.119495 280 : 4366, 4140
7481 22:14:56.119566 284 : 4363, 4140
7482 22:14:56.122847 288 : 4250, 4027
7483 22:14:56.122921 292 : 4250, 4027
7484 22:14:56.122982 296 : 4254, 4030
7485 22:14:56.125801 300 : 4252, 4029
7486 22:14:56.125870 304 : 4253, 4029
7487 22:14:56.129023 308 : 4253, 4029
7488 22:14:56.129093 312 : 4255, 4029
7489 22:14:56.132958 316 : 4252, 4030
7490 22:14:56.133028 320 : 4253, 4029
7491 22:14:56.135644 324 : 4258, 4032
7492 22:14:56.135714 328 : 4363, 4140
7493 22:14:56.139002 332 : 4252, 4029
7494 22:14:56.139073 336 : 4363, 4140
7495 22:14:56.142424 340 : 4255, 4029
7496 22:14:56.142493 344 : 4255, 4029
7497 22:14:56.145451 348 : 4365, 4140
7498 22:14:56.145525 352 : 4255, 4027
7499 22:14:56.148793 356 : 4253, 2956
7500 22:14:56.148863 360 : 4368, 6
7501 22:14:56.148924
7502 22:14:56.152286 MIOCK jitter meter ch=0
7503 22:14:56.152357
7504 22:14:56.155635 1T = (360-108) = 252 dly cells
7505 22:14:56.158836 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 258/100 ps
7506 22:14:56.158942 ==
7507 22:14:56.162114 Dram Type= 6, Freq= 0, CH_0, rank 0
7508 22:14:56.168842 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7509 22:14:56.168952 ==
7510 22:14:56.172114 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7511 22:14:56.178434 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7512 22:14:56.182084 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7513 22:14:56.188534 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7514 22:14:56.196683 [CA 0] Center 44 (14~75) winsize 62
7515 22:14:56.199966 [CA 1] Center 43 (13~74) winsize 62
7516 22:14:56.203027 [CA 2] Center 39 (10~69) winsize 60
7517 22:14:56.206476 [CA 3] Center 39 (10~68) winsize 59
7518 22:14:56.209831 [CA 4] Center 37 (8~67) winsize 60
7519 22:14:56.213277 [CA 5] Center 37 (7~67) winsize 61
7520 22:14:56.213358
7521 22:14:56.216176 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7522 22:14:56.216256
7523 22:14:56.223108 [CATrainingPosCal] consider 1 rank data
7524 22:14:56.223189 u2DelayCellTimex100 = 258/100 ps
7525 22:14:56.229709 CA0 delay=44 (14~75),Diff = 7 PI (26 cell)
7526 22:14:56.232961 CA1 delay=43 (13~74),Diff = 6 PI (22 cell)
7527 22:14:56.236365 CA2 delay=39 (10~69),Diff = 2 PI (7 cell)
7528 22:14:56.239893 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7529 22:14:56.242593 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
7530 22:14:56.245969 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7531 22:14:56.246049
7532 22:14:56.249342 CA PerBit enable=1, Macro0, CA PI delay=37
7533 22:14:56.249422
7534 22:14:56.253032 [CBTSetCACLKResult] CA Dly = 37
7535 22:14:56.255836 CS Dly: 11 (0~42)
7536 22:14:56.259380 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7537 22:14:56.262824 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7538 22:14:56.262941 ==
7539 22:14:56.266279 Dram Type= 6, Freq= 0, CH_0, rank 1
7540 22:14:56.272380 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7541 22:14:56.272487 ==
7542 22:14:56.275715 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7543 22:14:56.282555 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7544 22:14:56.285707 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7545 22:14:56.292065 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7546 22:14:56.300516 [CA 0] Center 44 (14~75) winsize 62
7547 22:14:56.303586 [CA 1] Center 43 (13~74) winsize 62
7548 22:14:56.306681 [CA 2] Center 39 (10~69) winsize 60
7549 22:14:56.310504 [CA 3] Center 39 (10~69) winsize 60
7550 22:14:56.313581 [CA 4] Center 37 (8~67) winsize 60
7551 22:14:56.316348 [CA 5] Center 37 (7~67) winsize 61
7552 22:14:56.316430
7553 22:14:56.319750 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7554 22:14:56.323434
7555 22:14:56.326745 [CATrainingPosCal] consider 2 rank data
7556 22:14:56.326855 u2DelayCellTimex100 = 258/100 ps
7557 22:14:56.332824 CA0 delay=44 (14~75),Diff = 7 PI (26 cell)
7558 22:14:56.336155 CA1 delay=43 (13~74),Diff = 6 PI (22 cell)
7559 22:14:56.339547 CA2 delay=39 (10~69),Diff = 2 PI (7 cell)
7560 22:14:56.342965 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7561 22:14:56.346529 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
7562 22:14:56.350059 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7563 22:14:56.350140
7564 22:14:56.352974 CA PerBit enable=1, Macro0, CA PI delay=37
7565 22:14:56.353055
7566 22:14:56.356233 [CBTSetCACLKResult] CA Dly = 37
7567 22:14:56.359449 CS Dly: 11 (0~43)
7568 22:14:56.362717 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7569 22:14:56.366172 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7570 22:14:56.366253
7571 22:14:56.369342 ----->DramcWriteLeveling(PI) begin...
7572 22:14:56.372860 ==
7573 22:14:56.372942 Dram Type= 6, Freq= 0, CH_0, rank 0
7574 22:14:56.379553 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7575 22:14:56.379634 ==
7576 22:14:56.382757 Write leveling (Byte 0): 36 => 36
7577 22:14:56.386233 Write leveling (Byte 1): 28 => 28
7578 22:14:56.389421 DramcWriteLeveling(PI) end<-----
7579 22:14:56.389501
7580 22:14:56.389564 ==
7581 22:14:56.392405 Dram Type= 6, Freq= 0, CH_0, rank 0
7582 22:14:56.395943 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7583 22:14:56.396025 ==
7584 22:14:56.399184 [Gating] SW mode calibration
7585 22:14:56.405844 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7586 22:14:56.412496 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7587 22:14:56.415651 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7588 22:14:56.418969 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7589 22:14:56.425600 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7590 22:14:56.429037 1 4 12 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
7591 22:14:56.432494 1 4 16 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (1 0)
7592 22:14:56.439206 1 4 20 | B1->B0 | 2424 3434 | 0 0 | (0 0) (0 0)
7593 22:14:56.442212 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (0 0) (1 1)
7594 22:14:56.445624 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7595 22:14:56.451926 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7596 22:14:56.455206 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7597 22:14:56.458687 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7598 22:14:56.465736 1 5 12 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
7599 22:14:56.468148 1 5 16 | B1->B0 | 3434 2c2c | 1 0 | (1 1) (0 1)
7600 22:14:56.471981 1 5 20 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7601 22:14:56.478107 1 5 24 | B1->B0 | 2a2a 2323 | 0 0 | (1 0) (0 0)
7602 22:14:56.481445 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7603 22:14:56.484822 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7604 22:14:56.491928 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7605 22:14:56.494595 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7606 22:14:56.498419 1 6 12 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7607 22:14:56.504638 1 6 16 | B1->B0 | 2323 4141 | 0 0 | (0 0) (0 0)
7608 22:14:56.507916 1 6 20 | B1->B0 | 2828 4646 | 0 0 | (0 0) (0 0)
7609 22:14:56.511132 1 6 24 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
7610 22:14:56.518058 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7611 22:14:56.521100 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7612 22:14:56.524272 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7613 22:14:56.530997 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7614 22:14:56.533974 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7615 22:14:56.537871 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7616 22:14:56.544085 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7617 22:14:56.547566 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7618 22:14:56.550393 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7619 22:14:56.557626 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7620 22:14:56.560619 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7621 22:14:56.564083 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7622 22:14:56.570781 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7623 22:14:56.573690 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7624 22:14:56.576915 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7625 22:14:56.583598 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7626 22:14:56.586884 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7627 22:14:56.590189 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7628 22:14:56.596819 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7629 22:14:56.599889 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7630 22:14:56.603257 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7631 22:14:56.610172 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7632 22:14:56.613240 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7633 22:14:56.616456 Total UI for P1: 0, mck2ui 16
7634 22:14:56.620089 best dqsien dly found for B0: ( 1, 9, 16)
7635 22:14:56.623223 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7636 22:14:56.629649 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7637 22:14:56.629730 Total UI for P1: 0, mck2ui 16
7638 22:14:56.632958 best dqsien dly found for B1: ( 1, 9, 24)
7639 22:14:56.639906 best DQS0 dly(MCK, UI, PI) = (1, 9, 16)
7640 22:14:56.643299 best DQS1 dly(MCK, UI, PI) = (1, 9, 24)
7641 22:14:56.643374
7642 22:14:56.646303 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)
7643 22:14:56.649682 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 24)
7644 22:14:56.652816 [Gating] SW calibration Done
7645 22:14:56.652898 ==
7646 22:14:56.656320 Dram Type= 6, Freq= 0, CH_0, rank 0
7647 22:14:56.659128 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7648 22:14:56.659228 ==
7649 22:14:56.662454 RX Vref Scan: 0
7650 22:14:56.662549
7651 22:14:56.662636 RX Vref 0 -> 0, step: 1
7652 22:14:56.666026
7653 22:14:56.666122 RX Delay 0 -> 252, step: 8
7654 22:14:56.669349 iDelay=192, Bit 0, Center 127 (72 ~ 183) 112
7655 22:14:56.676008 iDelay=192, Bit 1, Center 131 (80 ~ 183) 104
7656 22:14:56.679195 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
7657 22:14:56.682238 iDelay=192, Bit 3, Center 119 (64 ~ 175) 112
7658 22:14:56.685561 iDelay=192, Bit 4, Center 127 (72 ~ 183) 112
7659 22:14:56.692066 iDelay=192, Bit 5, Center 111 (56 ~ 167) 112
7660 22:14:56.695533 iDelay=192, Bit 6, Center 139 (88 ~ 191) 104
7661 22:14:56.698942 iDelay=192, Bit 7, Center 139 (88 ~ 191) 104
7662 22:14:56.702303 iDelay=192, Bit 8, Center 115 (56 ~ 175) 120
7663 22:14:56.705445 iDelay=192, Bit 9, Center 111 (56 ~ 167) 112
7664 22:14:56.712024 iDelay=192, Bit 10, Center 123 (64 ~ 183) 120
7665 22:14:56.715282 iDelay=192, Bit 11, Center 119 (64 ~ 175) 112
7666 22:14:56.718849 iDelay=192, Bit 12, Center 127 (72 ~ 183) 112
7667 22:14:56.721987 iDelay=192, Bit 13, Center 131 (72 ~ 191) 120
7668 22:14:56.725075 iDelay=192, Bit 14, Center 131 (72 ~ 191) 120
7669 22:14:56.731867 iDelay=192, Bit 15, Center 131 (72 ~ 191) 120
7670 22:14:56.731949 ==
7671 22:14:56.735472 Dram Type= 6, Freq= 0, CH_0, rank 0
7672 22:14:56.738437 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7673 22:14:56.738519 ==
7674 22:14:56.738584 DQS Delay:
7675 22:14:56.741726 DQS0 = 0, DQS1 = 0
7676 22:14:56.741808 DQM Delay:
7677 22:14:56.744940 DQM0 = 127, DQM1 = 123
7678 22:14:56.745022 DQ Delay:
7679 22:14:56.748293 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =119
7680 22:14:56.751576 DQ4 =127, DQ5 =111, DQ6 =139, DQ7 =139
7681 22:14:56.755326 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =119
7682 22:14:56.758414 DQ12 =127, DQ13 =131, DQ14 =131, DQ15 =131
7683 22:14:56.761828
7684 22:14:56.761910
7685 22:14:56.761985 ==
7686 22:14:56.765672 Dram Type= 6, Freq= 0, CH_0, rank 0
7687 22:14:56.768427 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7688 22:14:56.768525 ==
7689 22:14:56.768590
7690 22:14:56.768653
7691 22:14:56.771621 TX Vref Scan disable
7692 22:14:56.771704 == TX Byte 0 ==
7693 22:14:56.778298 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
7694 22:14:56.781307 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
7695 22:14:56.781403 == TX Byte 1 ==
7696 22:14:56.787942 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7697 22:14:56.791184 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7698 22:14:56.791283 ==
7699 22:14:56.794702 Dram Type= 6, Freq= 0, CH_0, rank 0
7700 22:14:56.798070 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7701 22:14:56.798159 ==
7702 22:14:56.812894
7703 22:14:56.815406 TX Vref early break, caculate TX vref
7704 22:14:56.819249 TX Vref=16, minBit 8, minWin=21, winSum=365
7705 22:14:56.822618 TX Vref=18, minBit 8, minWin=21, winSum=370
7706 22:14:56.825896 TX Vref=20, minBit 8, minWin=23, winSum=384
7707 22:14:56.828958 TX Vref=22, minBit 8, minWin=23, winSum=396
7708 22:14:56.832045 TX Vref=24, minBit 8, minWin=23, winSum=402
7709 22:14:56.838763 TX Vref=26, minBit 3, minWin=25, winSum=409
7710 22:14:56.841945 TX Vref=28, minBit 8, minWin=24, winSum=412
7711 22:14:56.845132 TX Vref=30, minBit 8, minWin=23, winSum=400
7712 22:14:56.848670 TX Vref=32, minBit 8, minWin=23, winSum=391
7713 22:14:56.851799 TX Vref=34, minBit 8, minWin=22, winSum=389
7714 22:14:56.858421 [TxChooseVref] Worse bit 3, Min win 25, Win sum 409, Final Vref 26
7715 22:14:56.858504
7716 22:14:56.861627 Final TX Range 0 Vref 26
7717 22:14:56.861709
7718 22:14:56.861773 ==
7719 22:14:56.865088 Dram Type= 6, Freq= 0, CH_0, rank 0
7720 22:14:56.868228 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7721 22:14:56.868311 ==
7722 22:14:56.868376
7723 22:14:56.868434
7724 22:14:56.871659 TX Vref Scan disable
7725 22:14:56.878223 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
7726 22:14:56.878305 == TX Byte 0 ==
7727 22:14:56.881650 u2DelayCellOfst[0]=11 cells (3 PI)
7728 22:14:56.884726 u2DelayCellOfst[1]=15 cells (4 PI)
7729 22:14:56.887794 u2DelayCellOfst[2]=7 cells (2 PI)
7730 22:14:56.891699 u2DelayCellOfst[3]=7 cells (2 PI)
7731 22:14:56.894660 u2DelayCellOfst[4]=3 cells (1 PI)
7732 22:14:56.897976 u2DelayCellOfst[5]=0 cells (0 PI)
7733 22:14:56.901483 u2DelayCellOfst[6]=15 cells (4 PI)
7734 22:14:56.904416 u2DelayCellOfst[7]=15 cells (4 PI)
7735 22:14:56.907866 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7736 22:14:56.911211 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
7737 22:14:56.914110 == TX Byte 1 ==
7738 22:14:56.917511 u2DelayCellOfst[8]=0 cells (0 PI)
7739 22:14:56.920846 u2DelayCellOfst[9]=3 cells (1 PI)
7740 22:14:56.924220 u2DelayCellOfst[10]=7 cells (2 PI)
7741 22:14:56.927391 u2DelayCellOfst[11]=3 cells (1 PI)
7742 22:14:56.927471 u2DelayCellOfst[12]=11 cells (3 PI)
7743 22:14:56.930994 u2DelayCellOfst[13]=11 cells (3 PI)
7744 22:14:56.934178 u2DelayCellOfst[14]=15 cells (4 PI)
7745 22:14:56.937411 u2DelayCellOfst[15]=11 cells (3 PI)
7746 22:14:56.943670 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7747 22:14:56.947321 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7748 22:14:56.950399 DramC Write-DBI on
7749 22:14:56.950498 ==
7750 22:14:56.954046 Dram Type= 6, Freq= 0, CH_0, rank 0
7751 22:14:56.956948 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7752 22:14:56.957044 ==
7753 22:14:56.957133
7754 22:14:56.957218
7755 22:14:56.960566 TX Vref Scan disable
7756 22:14:56.960652 == TX Byte 0 ==
7757 22:14:56.966985 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
7758 22:14:56.967066 == TX Byte 1 ==
7759 22:14:56.970412 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
7760 22:14:56.973924 DramC Write-DBI off
7761 22:14:56.974005
7762 22:14:56.974068 [DATLAT]
7763 22:14:56.976613 Freq=1600, CH0 RK0
7764 22:14:56.976694
7765 22:14:56.976758 DATLAT Default: 0xf
7766 22:14:56.979906 0, 0xFFFF, sum = 0
7767 22:14:56.979989 1, 0xFFFF, sum = 0
7768 22:14:56.983346 2, 0xFFFF, sum = 0
7769 22:14:56.986644 3, 0xFFFF, sum = 0
7770 22:14:56.986726 4, 0xFFFF, sum = 0
7771 22:14:56.990125 5, 0xFFFF, sum = 0
7772 22:14:56.990207 6, 0xFFFF, sum = 0
7773 22:14:56.993475 7, 0xFFFF, sum = 0
7774 22:14:56.993558 8, 0xFFFF, sum = 0
7775 22:14:56.996904 9, 0xFFFF, sum = 0
7776 22:14:56.996986 10, 0xFFFF, sum = 0
7777 22:14:57.000058 11, 0xFFFF, sum = 0
7778 22:14:57.000141 12, 0xFFFF, sum = 0
7779 22:14:57.003487 13, 0xEFFF, sum = 0
7780 22:14:57.003569 14, 0x0, sum = 1
7781 22:14:57.006605 15, 0x0, sum = 2
7782 22:14:57.006686 16, 0x0, sum = 3
7783 22:14:57.009994 17, 0x0, sum = 4
7784 22:14:57.010075 best_step = 15
7785 22:14:57.010139
7786 22:14:57.010197 ==
7787 22:14:57.013260 Dram Type= 6, Freq= 0, CH_0, rank 0
7788 22:14:57.019597 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7789 22:14:57.019679 ==
7790 22:14:57.019743 RX Vref Scan: 1
7791 22:14:57.019803
7792 22:14:57.022779 Set Vref Range= 24 -> 127
7793 22:14:57.022911
7794 22:14:57.026086 RX Vref 24 -> 127, step: 1
7795 22:14:57.026167
7796 22:14:57.026231 RX Delay 11 -> 252, step: 4
7797 22:14:57.029611
7798 22:14:57.029691 Set Vref, RX VrefLevel [Byte0]: 24
7799 22:14:57.032746 [Byte1]: 24
7800 22:14:57.037203
7801 22:14:57.037286 Set Vref, RX VrefLevel [Byte0]: 25
7802 22:14:57.040509 [Byte1]: 25
7803 22:14:57.044580
7804 22:14:57.044661 Set Vref, RX VrefLevel [Byte0]: 26
7805 22:14:57.047809 [Byte1]: 26
7806 22:14:57.052385
7807 22:14:57.052465 Set Vref, RX VrefLevel [Byte0]: 27
7808 22:14:57.055552 [Byte1]: 27
7809 22:14:57.060133
7810 22:14:57.060219 Set Vref, RX VrefLevel [Byte0]: 28
7811 22:14:57.063212 [Byte1]: 28
7812 22:14:57.067436
7813 22:14:57.067516 Set Vref, RX VrefLevel [Byte0]: 29
7814 22:14:57.070782 [Byte1]: 29
7815 22:14:57.074801
7816 22:14:57.074893 Set Vref, RX VrefLevel [Byte0]: 30
7817 22:14:57.078459 [Byte1]: 30
7818 22:14:57.082767
7819 22:14:57.082904 Set Vref, RX VrefLevel [Byte0]: 31
7820 22:14:57.085946 [Byte1]: 31
7821 22:14:57.090565
7822 22:14:57.090646 Set Vref, RX VrefLevel [Byte0]: 32
7823 22:14:57.093383 [Byte1]: 32
7824 22:14:57.097857
7825 22:14:57.097938 Set Vref, RX VrefLevel [Byte0]: 33
7826 22:14:57.101272 [Byte1]: 33
7827 22:14:57.105551
7828 22:14:57.105632 Set Vref, RX VrefLevel [Byte0]: 34
7829 22:14:57.108953 [Byte1]: 34
7830 22:14:57.113239
7831 22:14:57.113319 Set Vref, RX VrefLevel [Byte0]: 35
7832 22:14:57.116517 [Byte1]: 35
7833 22:14:57.120512
7834 22:14:57.120593 Set Vref, RX VrefLevel [Byte0]: 36
7835 22:14:57.123803 [Byte1]: 36
7836 22:14:57.128228
7837 22:14:57.128309 Set Vref, RX VrefLevel [Byte0]: 37
7838 22:14:57.131676 [Byte1]: 37
7839 22:14:57.136057
7840 22:14:57.136137 Set Vref, RX VrefLevel [Byte0]: 38
7841 22:14:57.139145 [Byte1]: 38
7842 22:14:57.143311
7843 22:14:57.143391 Set Vref, RX VrefLevel [Byte0]: 39
7844 22:14:57.147021 [Byte1]: 39
7845 22:14:57.151216
7846 22:14:57.151295 Set Vref, RX VrefLevel [Byte0]: 40
7847 22:14:57.154275 [Byte1]: 40
7848 22:14:57.159045
7849 22:14:57.159125 Set Vref, RX VrefLevel [Byte0]: 41
7850 22:14:57.162067 [Byte1]: 41
7851 22:14:57.166185
7852 22:14:57.166265 Set Vref, RX VrefLevel [Byte0]: 42
7853 22:14:57.169803 [Byte1]: 42
7854 22:14:57.174217
7855 22:14:57.174297 Set Vref, RX VrefLevel [Byte0]: 43
7856 22:14:57.177595 [Byte1]: 43
7857 22:14:57.181890
7858 22:14:57.181971 Set Vref, RX VrefLevel [Byte0]: 44
7859 22:14:57.185429 [Byte1]: 44
7860 22:14:57.189407
7861 22:14:57.189487 Set Vref, RX VrefLevel [Byte0]: 45
7862 22:14:57.192801 [Byte1]: 45
7863 22:14:57.196636
7864 22:14:57.196720 Set Vref, RX VrefLevel [Byte0]: 46
7865 22:14:57.199974 [Byte1]: 46
7866 22:14:57.204431
7867 22:14:57.204511 Set Vref, RX VrefLevel [Byte0]: 47
7868 22:14:57.207747 [Byte1]: 47
7869 22:14:57.211977
7870 22:14:57.212058 Set Vref, RX VrefLevel [Byte0]: 48
7871 22:14:57.215405 [Byte1]: 48
7872 22:14:57.219875
7873 22:14:57.219955 Set Vref, RX VrefLevel [Byte0]: 49
7874 22:14:57.223016 [Byte1]: 49
7875 22:14:57.227251
7876 22:14:57.227331 Set Vref, RX VrefLevel [Byte0]: 50
7877 22:14:57.230492 [Byte1]: 50
7878 22:14:57.234936
7879 22:14:57.235016 Set Vref, RX VrefLevel [Byte0]: 51
7880 22:14:57.238549 [Byte1]: 51
7881 22:14:57.242230
7882 22:14:57.242310 Set Vref, RX VrefLevel [Byte0]: 52
7883 22:14:57.245983 [Byte1]: 52
7884 22:14:57.249795
7885 22:14:57.253157 Set Vref, RX VrefLevel [Byte0]: 53
7886 22:14:57.256189 [Byte1]: 53
7887 22:14:57.256270
7888 22:14:57.259762 Set Vref, RX VrefLevel [Byte0]: 54
7889 22:14:57.263047 [Byte1]: 54
7890 22:14:57.263128
7891 22:14:57.266530 Set Vref, RX VrefLevel [Byte0]: 55
7892 22:14:57.269657 [Byte1]: 55
7893 22:14:57.272879
7894 22:14:57.272960 Set Vref, RX VrefLevel [Byte0]: 56
7895 22:14:57.276012 [Byte1]: 56
7896 22:14:57.280665
7897 22:14:57.280745 Set Vref, RX VrefLevel [Byte0]: 57
7898 22:14:57.283941 [Byte1]: 57
7899 22:14:57.288130
7900 22:14:57.288211 Set Vref, RX VrefLevel [Byte0]: 58
7901 22:14:57.291675 [Byte1]: 58
7902 22:14:57.295616
7903 22:14:57.295696 Set Vref, RX VrefLevel [Byte0]: 59
7904 22:14:57.299050 [Byte1]: 59
7905 22:14:57.303572
7906 22:14:57.303653 Set Vref, RX VrefLevel [Byte0]: 60
7907 22:14:57.306410 [Byte1]: 60
7908 22:14:57.311232
7909 22:14:57.311314 Set Vref, RX VrefLevel [Byte0]: 61
7910 22:14:57.314207 [Byte1]: 61
7911 22:14:57.318562
7912 22:14:57.318643 Set Vref, RX VrefLevel [Byte0]: 62
7913 22:14:57.322204 [Byte1]: 62
7914 22:14:57.326594
7915 22:14:57.326681 Set Vref, RX VrefLevel [Byte0]: 63
7916 22:14:57.329454 [Byte1]: 63
7917 22:14:57.333769
7918 22:14:57.333870 Set Vref, RX VrefLevel [Byte0]: 64
7919 22:14:57.337712 [Byte1]: 64
7920 22:14:57.341600
7921 22:14:57.341709 Set Vref, RX VrefLevel [Byte0]: 65
7922 22:14:57.344922 [Byte1]: 65
7923 22:14:57.349822
7924 22:14:57.349957 Set Vref, RX VrefLevel [Byte0]: 66
7925 22:14:57.352474 [Byte1]: 66
7926 22:14:57.357200
7927 22:14:57.357351 Set Vref, RX VrefLevel [Byte0]: 67
7928 22:14:57.360101 [Byte1]: 67
7929 22:14:57.364490
7930 22:14:57.364692 Set Vref, RX VrefLevel [Byte0]: 68
7931 22:14:57.367908 [Byte1]: 68
7932 22:14:57.372008
7933 22:14:57.372247 Set Vref, RX VrefLevel [Byte0]: 69
7934 22:14:57.375583 [Byte1]: 69
7935 22:14:57.379600
7936 22:14:57.379984 Set Vref, RX VrefLevel [Byte0]: 70
7937 22:14:57.383183 [Byte1]: 70
7938 22:14:57.387498
7939 22:14:57.387959 Set Vref, RX VrefLevel [Byte0]: 71
7940 22:14:57.391137 [Byte1]: 71
7941 22:14:57.395093
7942 22:14:57.395676 Set Vref, RX VrefLevel [Byte0]: 72
7943 22:14:57.398242 [Byte1]: 72
7944 22:14:57.402719
7945 22:14:57.403222 Set Vref, RX VrefLevel [Byte0]: 73
7946 22:14:57.405992 [Byte1]: 73
7947 22:14:57.410585
7948 22:14:57.411096 Set Vref, RX VrefLevel [Byte0]: 74
7949 22:14:57.413821 [Byte1]: 74
7950 22:14:57.418439
7951 22:14:57.418964 Set Vref, RX VrefLevel [Byte0]: 75
7952 22:14:57.421505 [Byte1]: 75
7953 22:14:57.425397
7954 22:14:57.425857 Set Vref, RX VrefLevel [Byte0]: 76
7955 22:14:57.428974 [Byte1]: 76
7956 22:14:57.433200
7957 22:14:57.433658 Final RX Vref Byte 0 = 65 to rank0
7958 22:14:57.436609 Final RX Vref Byte 1 = 58 to rank0
7959 22:14:57.439943 Final RX Vref Byte 0 = 65 to rank1
7960 22:14:57.443081 Final RX Vref Byte 1 = 58 to rank1==
7961 22:14:57.446436 Dram Type= 6, Freq= 0, CH_0, rank 0
7962 22:14:57.452750 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7963 22:14:57.453179 ==
7964 22:14:57.453519 DQS Delay:
7965 22:14:57.453832 DQS0 = 0, DQS1 = 0
7966 22:14:57.456140 DQM Delay:
7967 22:14:57.456592 DQM0 = 126, DQM1 = 119
7968 22:14:57.459493 DQ Delay:
7969 22:14:57.462821 DQ0 =126, DQ1 =126, DQ2 =126, DQ3 =122
7970 22:14:57.466214 DQ4 =126, DQ5 =114, DQ6 =134, DQ7 =138
7971 22:14:57.469245 DQ8 =112, DQ9 =106, DQ10 =120, DQ11 =114
7972 22:14:57.473028 DQ12 =124, DQ13 =124, DQ14 =130, DQ15 =128
7973 22:14:57.473480
7974 22:14:57.473815
7975 22:14:57.474120
7976 22:14:57.475958 [DramC_TX_OE_Calibration] TA2
7977 22:14:57.479190 Original DQ_B0 (3 6) =30, OEN = 27
7978 22:14:57.482851 Original DQ_B1 (3 6) =30, OEN = 27
7979 22:14:57.485851 24, 0x0, End_B0=24 End_B1=24
7980 22:14:57.486278 25, 0x0, End_B0=25 End_B1=25
7981 22:14:57.489376 26, 0x0, End_B0=26 End_B1=26
7982 22:14:57.492892 27, 0x0, End_B0=27 End_B1=27
7983 22:14:57.495989 28, 0x0, End_B0=28 End_B1=28
7984 22:14:57.499192 29, 0x0, End_B0=29 End_B1=29
7985 22:14:57.499599 30, 0x0, End_B0=30 End_B1=30
7986 22:14:57.502588 31, 0x4141, End_B0=30 End_B1=30
7987 22:14:57.505431 Byte0 end_step=30 best_step=27
7988 22:14:57.508810 Byte1 end_step=30 best_step=27
7989 22:14:57.512147 Byte0 TX OE(2T, 0.5T) = (3, 3)
7990 22:14:57.515295 Byte1 TX OE(2T, 0.5T) = (3, 3)
7991 22:14:57.515679
7992 22:14:57.516000
7993 22:14:57.522005 [DQSOSCAuto] RK0, (LSB)MR18= 0x1515, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 399 ps
7994 22:14:57.525549 CH0 RK0: MR19=303, MR18=1515
7995 22:14:57.532075 CH0_RK0: MR19=0x303, MR18=0x1515, DQSOSC=399, MR23=63, INC=23, DEC=15
7996 22:14:57.532492
7997 22:14:57.535355 ----->DramcWriteLeveling(PI) begin...
7998 22:14:57.535785 ==
7999 22:14:57.538602 Dram Type= 6, Freq= 0, CH_0, rank 1
8000 22:14:57.542028 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8001 22:14:57.542389 ==
8002 22:14:57.545201 Write leveling (Byte 0): 32 => 32
8003 22:14:57.548483 Write leveling (Byte 1): 28 => 28
8004 22:14:57.551819 DramcWriteLeveling(PI) end<-----
8005 22:14:57.552194
8006 22:14:57.552497 ==
8007 22:14:57.555231 Dram Type= 6, Freq= 0, CH_0, rank 1
8008 22:14:57.558761 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8009 22:14:57.562099 ==
8010 22:14:57.562531 [Gating] SW mode calibration
8011 22:14:57.572180 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8012 22:14:57.575356 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8013 22:14:57.578298 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8014 22:14:57.585267 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8015 22:14:57.588404 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8016 22:14:57.591319 1 4 12 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
8017 22:14:57.598452 1 4 16 | B1->B0 | 2322 3434 | 1 1 | (0 0) (1 1)
8018 22:14:57.601263 1 4 20 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
8019 22:14:57.604931 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8020 22:14:57.611552 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8021 22:14:57.615228 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8022 22:14:57.618244 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8023 22:14:57.624291 1 5 8 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 1)
8024 22:14:57.628058 1 5 12 | B1->B0 | 3434 2727 | 1 0 | (1 1) (1 0)
8025 22:14:57.630986 1 5 16 | B1->B0 | 3333 2323 | 1 0 | (1 1) (0 0)
8026 22:14:57.637619 1 5 20 | B1->B0 | 2828 2323 | 0 0 | (0 1) (0 0)
8027 22:14:57.640985 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8028 22:14:57.644517 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8029 22:14:57.650934 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8030 22:14:57.654352 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8031 22:14:57.657680 1 6 8 | B1->B0 | 2323 2929 | 0 1 | (0 0) (0 0)
8032 22:14:57.664038 1 6 12 | B1->B0 | 2323 3d3d | 0 0 | (0 0) (0 0)
8033 22:14:57.667356 1 6 16 | B1->B0 | 3333 4646 | 0 0 | (0 0) (0 0)
8034 22:14:57.670718 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8035 22:14:57.677305 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8036 22:14:57.680714 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8037 22:14:57.684054 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8038 22:14:57.690676 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8039 22:14:57.693600 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8040 22:14:57.697200 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8041 22:14:57.704166 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8042 22:14:57.707295 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8043 22:14:57.710447 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8044 22:14:57.717104 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8045 22:14:57.720415 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8046 22:14:57.723719 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8047 22:14:57.730390 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8048 22:14:57.733348 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8049 22:14:57.736479 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8050 22:14:57.743498 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8051 22:14:57.746791 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8052 22:14:57.749821 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8053 22:14:57.756687 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8054 22:14:57.759801 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8055 22:14:57.762542 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8056 22:14:57.769362 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8057 22:14:57.772583 Total UI for P1: 0, mck2ui 16
8058 22:14:57.775917 best dqsien dly found for B0: ( 1, 9, 8)
8059 22:14:57.779354 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8060 22:14:57.782455 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8061 22:14:57.788842 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8062 22:14:57.788924 Total UI for P1: 0, mck2ui 16
8063 22:14:57.795994 best dqsien dly found for B1: ( 1, 9, 16)
8064 22:14:57.799069 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8065 22:14:57.802212 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8066 22:14:57.802294
8067 22:14:57.805273 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8068 22:14:57.808594 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8069 22:14:57.811851 [Gating] SW calibration Done
8070 22:14:57.811959 ==
8071 22:14:57.815646 Dram Type= 6, Freq= 0, CH_0, rank 1
8072 22:14:57.818704 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8073 22:14:57.818786 ==
8074 22:14:57.821788 RX Vref Scan: 0
8075 22:14:57.821869
8076 22:14:57.821933 RX Vref 0 -> 0, step: 1
8077 22:14:57.825519
8078 22:14:57.825600 RX Delay 0 -> 252, step: 8
8079 22:14:57.831596 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
8080 22:14:57.835345 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8081 22:14:57.838694 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8082 22:14:57.841423 iDelay=200, Bit 3, Center 123 (64 ~ 183) 120
8083 22:14:57.844791 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8084 22:14:57.852154 iDelay=200, Bit 5, Center 115 (56 ~ 175) 120
8085 22:14:57.854820 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8086 22:14:57.858273 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8087 22:14:57.861491 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8088 22:14:57.864762 iDelay=200, Bit 9, Center 107 (48 ~ 167) 120
8089 22:14:57.871585 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8090 22:14:57.874837 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8091 22:14:57.878141 iDelay=200, Bit 12, Center 127 (64 ~ 191) 128
8092 22:14:57.881433 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
8093 22:14:57.884886 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8094 22:14:57.891461 iDelay=200, Bit 15, Center 127 (64 ~ 191) 128
8095 22:14:57.891630 ==
8096 22:14:57.894954 Dram Type= 6, Freq= 0, CH_0, rank 1
8097 22:14:57.898368 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8098 22:14:57.898618 ==
8099 22:14:57.898904 DQS Delay:
8100 22:14:57.901642 DQS0 = 0, DQS1 = 0
8101 22:14:57.901934 DQM Delay:
8102 22:14:57.904756 DQM0 = 128, DQM1 = 121
8103 22:14:57.905028 DQ Delay:
8104 22:14:57.908386 DQ0 =127, DQ1 =131, DQ2 =123, DQ3 =123
8105 22:14:57.911499 DQ4 =127, DQ5 =115, DQ6 =139, DQ7 =139
8106 22:14:57.915334 DQ8 =115, DQ9 =107, DQ10 =123, DQ11 =115
8107 22:14:57.918311 DQ12 =127, DQ13 =127, DQ14 =131, DQ15 =127
8108 22:14:57.921289
8109 22:14:57.921751
8110 22:14:57.922113 ==
8111 22:14:57.924475 Dram Type= 6, Freq= 0, CH_0, rank 1
8112 22:14:57.928100 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8113 22:14:57.928573 ==
8114 22:14:57.928903
8115 22:14:57.929205
8116 22:14:57.931077 TX Vref Scan disable
8117 22:14:57.931497 == TX Byte 0 ==
8118 22:14:57.937656 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8119 22:14:57.941305 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
8120 22:14:57.941789 == TX Byte 1 ==
8121 22:14:57.947908 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8122 22:14:57.950769 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8123 22:14:57.951217 ==
8124 22:14:57.954241 Dram Type= 6, Freq= 0, CH_0, rank 1
8125 22:14:57.957943 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8126 22:14:57.958367 ==
8127 22:14:57.971801
8128 22:14:57.975069 TX Vref early break, caculate TX vref
8129 22:14:57.978598 TX Vref=16, minBit 8, minWin=21, winSum=366
8130 22:14:57.981509 TX Vref=18, minBit 8, minWin=22, winSum=373
8131 22:14:57.985118 TX Vref=20, minBit 8, minWin=22, winSum=381
8132 22:14:57.988591 TX Vref=22, minBit 8, minWin=23, winSum=387
8133 22:14:57.991451 TX Vref=24, minBit 1, minWin=24, winSum=400
8134 22:14:57.997970 TX Vref=26, minBit 8, minWin=24, winSum=408
8135 22:14:58.001405 TX Vref=28, minBit 8, minWin=24, winSum=411
8136 22:14:58.004814 TX Vref=30, minBit 8, minWin=24, winSum=407
8137 22:14:58.008113 TX Vref=32, minBit 8, minWin=23, winSum=394
8138 22:14:58.011175 TX Vref=34, minBit 8, minWin=22, winSum=388
8139 22:14:58.017929 [TxChooseVref] Worse bit 8, Min win 24, Win sum 411, Final Vref 28
8140 22:14:58.018397
8141 22:14:58.020868 Final TX Range 0 Vref 28
8142 22:14:58.021352
8143 22:14:58.021714 ==
8144 22:14:58.024397 Dram Type= 6, Freq= 0, CH_0, rank 1
8145 22:14:58.027345 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8146 22:14:58.027814 ==
8147 22:14:58.028177
8148 22:14:58.031213
8149 22:14:58.031672 TX Vref Scan disable
8150 22:14:58.037246 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8151 22:14:58.037711 == TX Byte 0 ==
8152 22:14:58.040905 u2DelayCellOfst[0]=11 cells (3 PI)
8153 22:14:58.044012 u2DelayCellOfst[1]=22 cells (6 PI)
8154 22:14:58.047191 u2DelayCellOfst[2]=11 cells (3 PI)
8155 22:14:58.050586 u2DelayCellOfst[3]=11 cells (3 PI)
8156 22:14:58.054024 u2DelayCellOfst[4]=7 cells (2 PI)
8157 22:14:58.056881 u2DelayCellOfst[5]=0 cells (0 PI)
8158 22:14:58.060383 u2DelayCellOfst[6]=18 cells (5 PI)
8159 22:14:58.063562 u2DelayCellOfst[7]=15 cells (4 PI)
8160 22:14:58.067287 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
8161 22:14:58.070381 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
8162 22:14:58.073348 == TX Byte 1 ==
8163 22:14:58.076813 u2DelayCellOfst[8]=0 cells (0 PI)
8164 22:14:58.080248 u2DelayCellOfst[9]=3 cells (1 PI)
8165 22:14:58.083615 u2DelayCellOfst[10]=11 cells (3 PI)
8166 22:14:58.087045 u2DelayCellOfst[11]=7 cells (2 PI)
8167 22:14:58.090175 u2DelayCellOfst[12]=15 cells (4 PI)
8168 22:14:58.093676 u2DelayCellOfst[13]=15 cells (4 PI)
8169 22:14:58.094273 u2DelayCellOfst[14]=18 cells (5 PI)
8170 22:14:58.096916 u2DelayCellOfst[15]=11 cells (3 PI)
8171 22:14:58.103224 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8172 22:14:58.106612 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8173 22:14:58.109860 DramC Write-DBI on
8174 22:14:58.110328 ==
8175 22:14:58.113319 Dram Type= 6, Freq= 0, CH_0, rank 1
8176 22:14:58.116667 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8177 22:14:58.117225 ==
8178 22:14:58.117696
8179 22:14:58.118135
8180 22:14:58.120260 TX Vref Scan disable
8181 22:14:58.120677 == TX Byte 0 ==
8182 22:14:58.126313 Update DQM dly =732 (2 ,6, 28) DQM OEN =(3 ,3)
8183 22:14:58.126735 == TX Byte 1 ==
8184 22:14:58.129854 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8185 22:14:58.133033 DramC Write-DBI off
8186 22:14:58.133451
8187 22:14:58.133780 [DATLAT]
8188 22:14:58.136065 Freq=1600, CH0 RK1
8189 22:14:58.136483
8190 22:14:58.136809 DATLAT Default: 0xf
8191 22:14:58.139788 0, 0xFFFF, sum = 0
8192 22:14:58.140213 1, 0xFFFF, sum = 0
8193 22:14:58.143074 2, 0xFFFF, sum = 0
8194 22:14:58.146219 3, 0xFFFF, sum = 0
8195 22:14:58.146644 4, 0xFFFF, sum = 0
8196 22:14:58.149304 5, 0xFFFF, sum = 0
8197 22:14:58.149827 6, 0xFFFF, sum = 0
8198 22:14:58.152534 7, 0xFFFF, sum = 0
8199 22:14:58.153010 8, 0xFFFF, sum = 0
8200 22:14:58.155741 9, 0xFFFF, sum = 0
8201 22:14:58.156240 10, 0xFFFF, sum = 0
8202 22:14:58.159243 11, 0xFFFF, sum = 0
8203 22:14:58.159908 12, 0xFFFF, sum = 0
8204 22:14:58.162768 13, 0xCFFF, sum = 0
8205 22:14:58.163299 14, 0x0, sum = 1
8206 22:14:58.165637 15, 0x0, sum = 2
8207 22:14:58.166223 16, 0x0, sum = 3
8208 22:14:58.169108 17, 0x0, sum = 4
8209 22:14:58.169627 best_step = 15
8210 22:14:58.170091
8211 22:14:58.170486 ==
8212 22:14:58.172489 Dram Type= 6, Freq= 0, CH_0, rank 1
8213 22:14:58.178796 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8214 22:14:58.179436 ==
8215 22:14:58.179957 RX Vref Scan: 0
8216 22:14:58.180339
8217 22:14:58.182395 RX Vref 0 -> 0, step: 1
8218 22:14:58.183060
8219 22:14:58.185318 RX Delay 3 -> 252, step: 4
8220 22:14:58.188987 iDelay=191, Bit 0, Center 124 (71 ~ 178) 108
8221 22:14:58.192350 iDelay=191, Bit 1, Center 126 (71 ~ 182) 112
8222 22:14:58.195654 iDelay=191, Bit 2, Center 120 (67 ~ 174) 108
8223 22:14:58.201906 iDelay=191, Bit 3, Center 122 (67 ~ 178) 112
8224 22:14:58.205382 iDelay=191, Bit 4, Center 124 (71 ~ 178) 108
8225 22:14:58.208810 iDelay=191, Bit 5, Center 112 (59 ~ 166) 108
8226 22:14:58.212090 iDelay=191, Bit 6, Center 134 (79 ~ 190) 112
8227 22:14:58.218324 iDelay=191, Bit 7, Center 134 (79 ~ 190) 112
8228 22:14:58.221549 iDelay=191, Bit 8, Center 110 (55 ~ 166) 112
8229 22:14:58.224904 iDelay=191, Bit 9, Center 106 (51 ~ 162) 112
8230 22:14:58.228135 iDelay=191, Bit 10, Center 120 (63 ~ 178) 116
8231 22:14:58.231988 iDelay=191, Bit 11, Center 112 (55 ~ 170) 116
8232 22:14:58.238517 iDelay=191, Bit 12, Center 124 (67 ~ 182) 116
8233 22:14:58.241716 iDelay=191, Bit 13, Center 124 (67 ~ 182) 116
8234 22:14:58.244822 iDelay=191, Bit 14, Center 128 (71 ~ 186) 116
8235 22:14:58.248401 iDelay=191, Bit 15, Center 124 (67 ~ 182) 116
8236 22:14:58.248970 ==
8237 22:14:58.251660 Dram Type= 6, Freq= 0, CH_0, rank 1
8238 22:14:58.258079 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8239 22:14:58.258725 ==
8240 22:14:58.259299 DQS Delay:
8241 22:14:58.261371 DQS0 = 0, DQS1 = 0
8242 22:14:58.261932 DQM Delay:
8243 22:14:58.262578 DQM0 = 124, DQM1 = 118
8244 22:14:58.264474 DQ Delay:
8245 22:14:58.268413 DQ0 =124, DQ1 =126, DQ2 =120, DQ3 =122
8246 22:14:58.271312 DQ4 =124, DQ5 =112, DQ6 =134, DQ7 =134
8247 22:14:58.274643 DQ8 =110, DQ9 =106, DQ10 =120, DQ11 =112
8248 22:14:58.277991 DQ12 =124, DQ13 =124, DQ14 =128, DQ15 =124
8249 22:14:58.278458
8250 22:14:58.278823
8251 22:14:58.279210
8252 22:14:58.281290 [DramC_TX_OE_Calibration] TA2
8253 22:14:58.284808 Original DQ_B0 (3 6) =30, OEN = 27
8254 22:14:58.287578 Original DQ_B1 (3 6) =30, OEN = 27
8255 22:14:58.291086 24, 0x0, End_B0=24 End_B1=24
8256 22:14:58.291563 25, 0x0, End_B0=25 End_B1=25
8257 22:14:58.294555 26, 0x0, End_B0=26 End_B1=26
8258 22:14:58.297961 27, 0x0, End_B0=27 End_B1=27
8259 22:14:58.301176 28, 0x0, End_B0=28 End_B1=28
8260 22:14:58.304523 29, 0x0, End_B0=29 End_B1=29
8261 22:14:58.304999 30, 0x0, End_B0=30 End_B1=30
8262 22:14:58.307354 31, 0x4141, End_B0=30 End_B1=30
8263 22:14:58.310762 Byte0 end_step=30 best_step=27
8264 22:14:58.314304 Byte1 end_step=30 best_step=27
8265 22:14:58.317490 Byte0 TX OE(2T, 0.5T) = (3, 3)
8266 22:14:58.320929 Byte1 TX OE(2T, 0.5T) = (3, 3)
8267 22:14:58.321465
8268 22:14:58.321902
8269 22:14:58.327415 [DQSOSCAuto] RK1, (LSB)MR18= 0x2310, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 392 ps
8270 22:14:58.330218 CH0 RK1: MR19=303, MR18=2310
8271 22:14:58.337170 CH0_RK1: MR19=0x303, MR18=0x2310, DQSOSC=392, MR23=63, INC=24, DEC=16
8272 22:14:58.340281 [RxdqsGatingPostProcess] freq 1600
8273 22:14:58.347108 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8274 22:14:58.347579 best DQS0 dly(2T, 0.5T) = (1, 1)
8275 22:14:58.350687 best DQS1 dly(2T, 0.5T) = (1, 1)
8276 22:14:58.353725 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8277 22:14:58.356889 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8278 22:14:58.360233 best DQS0 dly(2T, 0.5T) = (1, 1)
8279 22:14:58.363377 best DQS1 dly(2T, 0.5T) = (1, 1)
8280 22:14:58.366987 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8281 22:14:58.370241 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8282 22:14:58.373272 Pre-setting of DQS Precalculation
8283 22:14:58.376424 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8284 22:14:58.376899 ==
8285 22:14:58.379791 Dram Type= 6, Freq= 0, CH_1, rank 0
8286 22:14:58.386420 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8287 22:14:58.386877 ==
8288 22:14:58.389720 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8289 22:14:58.396680 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8290 22:14:58.399807 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8291 22:14:58.406223 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8292 22:14:58.414320 [CA 0] Center 41 (12~70) winsize 59
8293 22:14:58.417653 [CA 1] Center 42 (13~72) winsize 60
8294 22:14:58.420674 [CA 2] Center 37 (9~66) winsize 58
8295 22:14:58.423905 [CA 3] Center 37 (8~66) winsize 59
8296 22:14:58.427567 [CA 4] Center 37 (8~67) winsize 60
8297 22:14:58.430347 [CA 5] Center 36 (7~66) winsize 60
8298 22:14:58.430426
8299 22:14:58.433671 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8300 22:14:58.433751
8301 22:14:58.440175 [CATrainingPosCal] consider 1 rank data
8302 22:14:58.440254 u2DelayCellTimex100 = 258/100 ps
8303 22:14:58.446955 CA0 delay=41 (12~70),Diff = 5 PI (18 cell)
8304 22:14:58.449994 CA1 delay=42 (13~72),Diff = 6 PI (22 cell)
8305 22:14:58.453806 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8306 22:14:58.456881 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8307 22:14:58.459989 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8308 22:14:58.463192 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8309 22:14:58.463276
8310 22:14:58.466883 CA PerBit enable=1, Macro0, CA PI delay=36
8311 22:14:58.466963
8312 22:14:58.469906 [CBTSetCACLKResult] CA Dly = 36
8313 22:14:58.473109 CS Dly: 9 (0~40)
8314 22:14:58.476599 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8315 22:14:58.480066 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8316 22:14:58.480146 ==
8317 22:14:58.483188 Dram Type= 6, Freq= 0, CH_1, rank 1
8318 22:14:58.489943 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8319 22:14:58.490023 ==
8320 22:14:58.493173 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8321 22:14:58.499479 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8322 22:14:58.503326 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8323 22:14:58.509917 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8324 22:14:58.517169 [CA 0] Center 41 (12~71) winsize 60
8325 22:14:58.520512 [CA 1] Center 42 (12~72) winsize 61
8326 22:14:58.523998 [CA 2] Center 37 (8~67) winsize 60
8327 22:14:58.527284 [CA 3] Center 36 (7~66) winsize 60
8328 22:14:58.530104 [CA 4] Center 37 (8~67) winsize 60
8329 22:14:58.533428 [CA 5] Center 36 (6~66) winsize 61
8330 22:14:58.533509
8331 22:14:58.536921 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8332 22:14:58.537002
8333 22:14:58.543504 [CATrainingPosCal] consider 2 rank data
8334 22:14:58.543578 u2DelayCellTimex100 = 258/100 ps
8335 22:14:58.550257 CA0 delay=41 (12~70),Diff = 5 PI (18 cell)
8336 22:14:58.553331 CA1 delay=42 (13~72),Diff = 6 PI (22 cell)
8337 22:14:58.556536 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8338 22:14:58.560273 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8339 22:14:58.563583 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8340 22:14:58.566604 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8341 22:14:58.566699
8342 22:14:58.569880 CA PerBit enable=1, Macro0, CA PI delay=36
8343 22:14:58.569971
8344 22:14:58.573112 [CBTSetCACLKResult] CA Dly = 36
8345 22:14:58.576684 CS Dly: 10 (0~43)
8346 22:14:58.580076 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8347 22:14:58.583180 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8348 22:14:58.583265
8349 22:14:58.586417 ----->DramcWriteLeveling(PI) begin...
8350 22:14:58.586489 ==
8351 22:14:58.589649 Dram Type= 6, Freq= 0, CH_1, rank 0
8352 22:14:58.596379 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8353 22:14:58.596461 ==
8354 22:14:58.599685 Write leveling (Byte 0): 25 => 25
8355 22:14:58.603021 Write leveling (Byte 1): 27 => 27
8356 22:14:58.603107 DramcWriteLeveling(PI) end<-----
8357 22:14:58.606382
8358 22:14:58.606452 ==
8359 22:14:58.609421 Dram Type= 6, Freq= 0, CH_1, rank 0
8360 22:14:58.612896 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8361 22:14:58.612994 ==
8362 22:14:58.615915 [Gating] SW mode calibration
8363 22:14:58.622648 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8364 22:14:58.626129 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8365 22:14:58.632254 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8366 22:14:58.635686 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8367 22:14:58.642417 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8368 22:14:58.645774 1 4 12 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
8369 22:14:58.648821 1 4 16 | B1->B0 | 3434 3434 | 0 0 | (0 0) (0 0)
8370 22:14:58.655498 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8371 22:14:58.658670 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8372 22:14:58.662124 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8373 22:14:58.665376 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8374 22:14:58.672059 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8375 22:14:58.675164 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8376 22:14:58.678387 1 5 12 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 0)
8377 22:14:58.685098 1 5 16 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8378 22:14:58.688434 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8379 22:14:58.695224 1 5 24 | B1->B0 | 2323 2423 | 0 1 | (0 0) (0 0)
8380 22:14:58.698383 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8381 22:14:58.702272 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8382 22:14:58.705053 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8383 22:14:58.711772 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8384 22:14:58.714576 1 6 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8385 22:14:58.721326 1 6 16 | B1->B0 | 4040 4545 | 0 0 | (0 0) (0 0)
8386 22:14:58.724740 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8387 22:14:58.728085 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8388 22:14:58.731982 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8389 22:14:58.738478 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8390 22:14:58.741031 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8391 22:14:58.744628 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8392 22:14:58.750965 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8393 22:14:58.754275 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8394 22:14:58.757634 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8395 22:14:58.764065 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8396 22:14:58.767698 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8397 22:14:58.770784 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8398 22:14:58.777567 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8399 22:14:58.781104 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8400 22:14:58.784404 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8401 22:14:58.790686 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8402 22:14:58.794003 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8403 22:14:58.797666 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8404 22:14:58.804018 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8405 22:14:58.807317 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8406 22:14:58.810723 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8407 22:14:58.817595 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8408 22:14:58.820746 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8409 22:14:58.823546 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8410 22:14:58.830586 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8411 22:14:58.833443 Total UI for P1: 0, mck2ui 16
8412 22:14:58.836817 best dqsien dly found for B0: ( 1, 9, 14)
8413 22:14:58.840197 Total UI for P1: 0, mck2ui 16
8414 22:14:58.843661 best dqsien dly found for B1: ( 1, 9, 14)
8415 22:14:58.846605 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8416 22:14:58.849965 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8417 22:14:58.850032
8418 22:14:58.853477 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8419 22:14:58.856676 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8420 22:14:58.860099 [Gating] SW calibration Done
8421 22:14:58.860191 ==
8422 22:14:58.863360 Dram Type= 6, Freq= 0, CH_1, rank 0
8423 22:14:58.866633 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8424 22:14:58.866732 ==
8425 22:14:58.869846 RX Vref Scan: 0
8426 22:14:58.869917
8427 22:14:58.872914 RX Vref 0 -> 0, step: 1
8428 22:14:58.872984
8429 22:14:58.873083 RX Delay 0 -> 252, step: 8
8430 22:14:58.879595 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8431 22:14:58.883152 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8432 22:14:58.886187 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8433 22:14:58.889323 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8434 22:14:58.896210 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8435 22:14:58.899426 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8436 22:14:58.902527 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8437 22:14:58.905895 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8438 22:14:58.909220 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
8439 22:14:58.915715 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8440 22:14:58.919178 iDelay=200, Bit 10, Center 127 (80 ~ 175) 96
8441 22:14:58.922543 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8442 22:14:58.925517 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8443 22:14:58.928685 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8444 22:14:58.935548 iDelay=200, Bit 14, Center 131 (80 ~ 183) 104
8445 22:14:58.938951 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8446 22:14:58.939020 ==
8447 22:14:58.942312 Dram Type= 6, Freq= 0, CH_1, rank 0
8448 22:14:58.945625 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8449 22:14:58.945713 ==
8450 22:14:58.948613 DQS Delay:
8451 22:14:58.948679 DQS0 = 0, DQS1 = 0
8452 22:14:58.948737 DQM Delay:
8453 22:14:58.952004 DQM0 = 133, DQM1 = 125
8454 22:14:58.952084 DQ Delay:
8455 22:14:58.955441 DQ0 =135, DQ1 =131, DQ2 =119, DQ3 =131
8456 22:14:58.958825 DQ4 =131, DQ5 =143, DQ6 =143, DQ7 =131
8457 22:14:58.965028 DQ8 =111, DQ9 =115, DQ10 =127, DQ11 =119
8458 22:14:58.968447 DQ12 =135, DQ13 =131, DQ14 =131, DQ15 =135
8459 22:14:58.968516
8460 22:14:58.968574
8461 22:14:58.968629 ==
8462 22:14:58.971645 Dram Type= 6, Freq= 0, CH_1, rank 0
8463 22:14:58.974782 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8464 22:14:58.974902 ==
8465 22:14:58.974982
8466 22:14:58.975041
8467 22:14:58.978514 TX Vref Scan disable
8468 22:14:58.981576 == TX Byte 0 ==
8469 22:14:58.985359 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8470 22:14:58.987953 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8471 22:14:58.991203 == TX Byte 1 ==
8472 22:14:58.994917 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8473 22:14:58.997993 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8474 22:14:58.998071 ==
8475 22:14:59.001056 Dram Type= 6, Freq= 0, CH_1, rank 0
8476 22:14:59.007629 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8477 22:14:59.007702 ==
8478 22:14:59.019346
8479 22:14:59.022371 TX Vref early break, caculate TX vref
8480 22:14:59.025615 TX Vref=16, minBit 8, minWin=22, winSum=362
8481 22:14:59.028983 TX Vref=18, minBit 12, minWin=22, winSum=375
8482 22:14:59.032395 TX Vref=20, minBit 11, minWin=22, winSum=384
8483 22:14:59.035681 TX Vref=22, minBit 5, minWin=23, winSum=391
8484 22:14:59.038965 TX Vref=24, minBit 0, minWin=24, winSum=400
8485 22:14:59.045801 TX Vref=26, minBit 0, minWin=25, winSum=413
8486 22:14:59.049136 TX Vref=28, minBit 0, minWin=25, winSum=418
8487 22:14:59.052519 TX Vref=30, minBit 6, minWin=24, winSum=416
8488 22:14:59.055348 TX Vref=32, minBit 0, minWin=24, winSum=409
8489 22:14:59.058762 TX Vref=34, minBit 0, minWin=23, winSum=394
8490 22:14:59.065619 [TxChooseVref] Worse bit 0, Min win 25, Win sum 418, Final Vref 28
8491 22:14:59.065700
8492 22:14:59.068995 Final TX Range 0 Vref 28
8493 22:14:59.069076
8494 22:14:59.069139 ==
8495 22:14:59.071877 Dram Type= 6, Freq= 0, CH_1, rank 0
8496 22:14:59.075392 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8497 22:14:59.075473 ==
8498 22:14:59.075537
8499 22:14:59.075595
8500 22:14:59.078810 TX Vref Scan disable
8501 22:14:59.085073 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8502 22:14:59.085154 == TX Byte 0 ==
8503 22:14:59.088813 u2DelayCellOfst[0]=22 cells (6 PI)
8504 22:14:59.091896 u2DelayCellOfst[1]=15 cells (4 PI)
8505 22:14:59.095020 u2DelayCellOfst[2]=0 cells (0 PI)
8506 22:14:59.098523 u2DelayCellOfst[3]=7 cells (2 PI)
8507 22:14:59.101645 u2DelayCellOfst[4]=11 cells (3 PI)
8508 22:14:59.104889 u2DelayCellOfst[5]=22 cells (6 PI)
8509 22:14:59.108553 u2DelayCellOfst[6]=22 cells (6 PI)
8510 22:14:59.111576 u2DelayCellOfst[7]=7 cells (2 PI)
8511 22:14:59.115120 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8512 22:14:59.118316 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8513 22:14:59.121553 == TX Byte 1 ==
8514 22:14:59.124818 u2DelayCellOfst[8]=0 cells (0 PI)
8515 22:14:59.127957 u2DelayCellOfst[9]=7 cells (2 PI)
8516 22:14:59.131308 u2DelayCellOfst[10]=15 cells (4 PI)
8517 22:14:59.131391 u2DelayCellOfst[11]=11 cells (3 PI)
8518 22:14:59.134685 u2DelayCellOfst[12]=18 cells (5 PI)
8519 22:14:59.138011 u2DelayCellOfst[13]=22 cells (6 PI)
8520 22:14:59.141640 u2DelayCellOfst[14]=22 cells (6 PI)
8521 22:14:59.144438 u2DelayCellOfst[15]=22 cells (6 PI)
8522 22:14:59.150884 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8523 22:14:59.154537 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8524 22:14:59.154618 DramC Write-DBI on
8525 22:14:59.157382 ==
8526 22:14:59.160748 Dram Type= 6, Freq= 0, CH_1, rank 0
8527 22:14:59.164174 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8528 22:14:59.164256 ==
8529 22:14:59.164319
8530 22:14:59.164376
8531 22:14:59.167514 TX Vref Scan disable
8532 22:14:59.167595 == TX Byte 0 ==
8533 22:14:59.174466 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8534 22:14:59.174548 == TX Byte 1 ==
8535 22:14:59.177559 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8536 22:14:59.180709 DramC Write-DBI off
8537 22:14:59.180789
8538 22:14:59.180852 [DATLAT]
8539 22:14:59.183978 Freq=1600, CH1 RK0
8540 22:14:59.184059
8541 22:14:59.184122 DATLAT Default: 0xf
8542 22:14:59.187467 0, 0xFFFF, sum = 0
8543 22:14:59.187577 1, 0xFFFF, sum = 0
8544 22:14:59.190519 2, 0xFFFF, sum = 0
8545 22:14:59.190604 3, 0xFFFF, sum = 0
8546 22:14:59.194242 4, 0xFFFF, sum = 0
8547 22:14:59.194327 5, 0xFFFF, sum = 0
8548 22:14:59.197364 6, 0xFFFF, sum = 0
8549 22:14:59.200473 7, 0xFFFF, sum = 0
8550 22:14:59.200554 8, 0xFFFF, sum = 0
8551 22:14:59.203903 9, 0xFFFF, sum = 0
8552 22:14:59.203979 10, 0xFFFF, sum = 0
8553 22:14:59.207214 11, 0xFFFF, sum = 0
8554 22:14:59.207287 12, 0xFFFF, sum = 0
8555 22:14:59.210420 13, 0x8FFF, sum = 0
8556 22:14:59.210490 14, 0x0, sum = 1
8557 22:14:59.213553 15, 0x0, sum = 2
8558 22:14:59.213625 16, 0x0, sum = 3
8559 22:14:59.216802 17, 0x0, sum = 4
8560 22:14:59.216871 best_step = 15
8561 22:14:59.216928
8562 22:14:59.216984 ==
8563 22:14:59.220551 Dram Type= 6, Freq= 0, CH_1, rank 0
8564 22:14:59.223415 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8565 22:14:59.226679 ==
8566 22:14:59.226750 RX Vref Scan: 1
8567 22:14:59.226810
8568 22:14:59.230236 Set Vref Range= 24 -> 127
8569 22:14:59.230306
8570 22:14:59.233334 RX Vref 24 -> 127, step: 1
8571 22:14:59.233409
8572 22:14:59.233468 RX Delay 11 -> 252, step: 4
8573 22:14:59.233524
8574 22:14:59.236634 Set Vref, RX VrefLevel [Byte0]: 24
8575 22:14:59.240058 [Byte1]: 24
8576 22:14:59.243878
8577 22:14:59.243947 Set Vref, RX VrefLevel [Byte0]: 25
8578 22:14:59.247403 [Byte1]: 25
8579 22:14:59.251372
8580 22:14:59.251441 Set Vref, RX VrefLevel [Byte0]: 26
8581 22:14:59.254803 [Byte1]: 26
8582 22:14:59.259491
8583 22:14:59.259558 Set Vref, RX VrefLevel [Byte0]: 27
8584 22:14:59.262654 [Byte1]: 27
8585 22:14:59.266695
8586 22:14:59.266763 Set Vref, RX VrefLevel [Byte0]: 28
8587 22:14:59.270097 [Byte1]: 28
8588 22:14:59.274482
8589 22:14:59.274558 Set Vref, RX VrefLevel [Byte0]: 29
8590 22:14:59.277444 [Byte1]: 29
8591 22:14:59.282067
8592 22:14:59.282136 Set Vref, RX VrefLevel [Byte0]: 30
8593 22:14:59.285314 [Byte1]: 30
8594 22:14:59.289899
8595 22:14:59.289968 Set Vref, RX VrefLevel [Byte0]: 31
8596 22:14:59.293022 [Byte1]: 31
8597 22:14:59.297122
8598 22:14:59.297190 Set Vref, RX VrefLevel [Byte0]: 32
8599 22:14:59.300845 [Byte1]: 32
8600 22:14:59.304923
8601 22:14:59.304998 Set Vref, RX VrefLevel [Byte0]: 33
8602 22:14:59.308044 [Byte1]: 33
8603 22:14:59.312624
8604 22:14:59.312696 Set Vref, RX VrefLevel [Byte0]: 34
8605 22:14:59.315729 [Byte1]: 34
8606 22:14:59.320124
8607 22:14:59.320198 Set Vref, RX VrefLevel [Byte0]: 35
8608 22:14:59.323195 [Byte1]: 35
8609 22:14:59.327887
8610 22:14:59.327960 Set Vref, RX VrefLevel [Byte0]: 36
8611 22:14:59.331109 [Byte1]: 36
8612 22:14:59.335409
8613 22:14:59.335478 Set Vref, RX VrefLevel [Byte0]: 37
8614 22:14:59.338740 [Byte1]: 37
8615 22:14:59.342985
8616 22:14:59.343061 Set Vref, RX VrefLevel [Byte0]: 38
8617 22:14:59.346482 [Byte1]: 38
8618 22:14:59.350754
8619 22:14:59.350855 Set Vref, RX VrefLevel [Byte0]: 39
8620 22:14:59.354030 [Byte1]: 39
8621 22:14:59.358037
8622 22:14:59.358107 Set Vref, RX VrefLevel [Byte0]: 40
8623 22:14:59.361669 [Byte1]: 40
8624 22:14:59.365855
8625 22:14:59.365936 Set Vref, RX VrefLevel [Byte0]: 41
8626 22:14:59.369265 [Byte1]: 41
8627 22:14:59.373153
8628 22:14:59.373235 Set Vref, RX VrefLevel [Byte0]: 42
8629 22:14:59.376412 [Byte1]: 42
8630 22:14:59.381046
8631 22:14:59.381131 Set Vref, RX VrefLevel [Byte0]: 43
8632 22:14:59.384522 [Byte1]: 43
8633 22:14:59.388959
8634 22:14:59.389041 Set Vref, RX VrefLevel [Byte0]: 44
8635 22:14:59.391831 [Byte1]: 44
8636 22:14:59.396179
8637 22:14:59.396261 Set Vref, RX VrefLevel [Byte0]: 45
8638 22:14:59.399521 [Byte1]: 45
8639 22:14:59.403683
8640 22:14:59.403765 Set Vref, RX VrefLevel [Byte0]: 46
8641 22:14:59.407255 [Byte1]: 46
8642 22:14:59.411674
8643 22:14:59.411755 Set Vref, RX VrefLevel [Byte0]: 47
8644 22:14:59.414885 [Byte1]: 47
8645 22:14:59.419098
8646 22:14:59.419180 Set Vref, RX VrefLevel [Byte0]: 48
8647 22:14:59.422329 [Byte1]: 48
8648 22:14:59.426759
8649 22:14:59.426848 Set Vref, RX VrefLevel [Byte0]: 49
8650 22:14:59.429837 [Byte1]: 49
8651 22:14:59.434482
8652 22:14:59.434563 Set Vref, RX VrefLevel [Byte0]: 50
8653 22:14:59.437665 [Byte1]: 50
8654 22:14:59.442503
8655 22:14:59.442593 Set Vref, RX VrefLevel [Byte0]: 51
8656 22:14:59.445211 [Byte1]: 51
8657 22:14:59.449889
8658 22:14:59.449971 Set Vref, RX VrefLevel [Byte0]: 52
8659 22:14:59.453056 [Byte1]: 52
8660 22:14:59.457225
8661 22:14:59.457308 Set Vref, RX VrefLevel [Byte0]: 53
8662 22:14:59.460681 [Byte1]: 53
8663 22:14:59.464589
8664 22:14:59.464698 Set Vref, RX VrefLevel [Byte0]: 54
8665 22:14:59.467887 [Byte1]: 54
8666 22:14:59.472634
8667 22:14:59.472716 Set Vref, RX VrefLevel [Byte0]: 55
8668 22:14:59.475591 [Byte1]: 55
8669 22:14:59.480147
8670 22:14:59.480229 Set Vref, RX VrefLevel [Byte0]: 56
8671 22:14:59.483347 [Byte1]: 56
8672 22:14:59.487447
8673 22:14:59.487529 Set Vref, RX VrefLevel [Byte0]: 57
8674 22:14:59.490958 [Byte1]: 57
8675 22:14:59.495010
8676 22:14:59.495092 Set Vref, RX VrefLevel [Byte0]: 58
8677 22:14:59.498785 [Byte1]: 58
8678 22:14:59.502792
8679 22:14:59.502896 Set Vref, RX VrefLevel [Byte0]: 59
8680 22:14:59.506139 [Byte1]: 59
8681 22:14:59.510441
8682 22:14:59.510543 Set Vref, RX VrefLevel [Byte0]: 60
8683 22:14:59.513532 [Byte1]: 60
8684 22:14:59.518215
8685 22:14:59.518336 Set Vref, RX VrefLevel [Byte0]: 61
8686 22:14:59.521434 [Byte1]: 61
8687 22:14:59.525706
8688 22:14:59.525842 Set Vref, RX VrefLevel [Byte0]: 62
8689 22:14:59.529201 [Byte1]: 62
8690 22:14:59.533755
8691 22:14:59.533928 Set Vref, RX VrefLevel [Byte0]: 63
8692 22:14:59.536769 [Byte1]: 63
8693 22:14:59.540790
8694 22:14:59.541024 Set Vref, RX VrefLevel [Byte0]: 64
8695 22:14:59.544542 [Byte1]: 64
8696 22:14:59.548947
8697 22:14:59.549278 Set Vref, RX VrefLevel [Byte0]: 65
8698 22:14:59.552048 [Byte1]: 65
8699 22:14:59.556555
8700 22:14:59.556953 Set Vref, RX VrefLevel [Byte0]: 66
8701 22:14:59.559902 [Byte1]: 66
8702 22:14:59.564283
8703 22:14:59.564742 Set Vref, RX VrefLevel [Byte0]: 67
8704 22:14:59.567194 [Byte1]: 67
8705 22:14:59.572072
8706 22:14:59.572532 Set Vref, RX VrefLevel [Byte0]: 68
8707 22:14:59.575127 [Byte1]: 68
8708 22:14:59.579296
8709 22:14:59.579756 Set Vref, RX VrefLevel [Byte0]: 69
8710 22:14:59.582634 [Byte1]: 69
8711 22:14:59.587125
8712 22:14:59.587586 Set Vref, RX VrefLevel [Byte0]: 70
8713 22:14:59.590430 [Byte1]: 70
8714 22:14:59.594355
8715 22:14:59.594813 Final RX Vref Byte 0 = 57 to rank0
8716 22:14:59.597808 Final RX Vref Byte 1 = 54 to rank0
8717 22:14:59.601250 Final RX Vref Byte 0 = 57 to rank1
8718 22:14:59.604615 Final RX Vref Byte 1 = 54 to rank1==
8719 22:14:59.607781 Dram Type= 6, Freq= 0, CH_1, rank 0
8720 22:14:59.614362 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8721 22:14:59.614867 ==
8722 22:14:59.615266 DQS Delay:
8723 22:14:59.617405 DQS0 = 0, DQS1 = 0
8724 22:14:59.617874 DQM Delay:
8725 22:14:59.618238 DQM0 = 131, DQM1 = 123
8726 22:14:59.621184 DQ Delay:
8727 22:14:59.624348 DQ0 =136, DQ1 =126, DQ2 =120, DQ3 =126
8728 22:14:59.627817 DQ4 =130, DQ5 =142, DQ6 =142, DQ7 =128
8729 22:14:59.630566 DQ8 =108, DQ9 =114, DQ10 =122, DQ11 =116
8730 22:14:59.634694 DQ12 =134, DQ13 =132, DQ14 =132, DQ15 =132
8731 22:14:59.635260
8732 22:14:59.635628
8733 22:14:59.635968
8734 22:14:59.637543 [DramC_TX_OE_Calibration] TA2
8735 22:14:59.640779 Original DQ_B0 (3 6) =30, OEN = 27
8736 22:14:59.644113 Original DQ_B1 (3 6) =30, OEN = 27
8737 22:14:59.647052 24, 0x0, End_B0=24 End_B1=24
8738 22:14:59.650580 25, 0x0, End_B0=25 End_B1=25
8739 22:14:59.651153 26, 0x0, End_B0=26 End_B1=26
8740 22:14:59.653925 27, 0x0, End_B0=27 End_B1=27
8741 22:14:59.656945 28, 0x0, End_B0=28 End_B1=28
8742 22:14:59.660733 29, 0x0, End_B0=29 End_B1=29
8743 22:14:59.661206 30, 0x0, End_B0=30 End_B1=30
8744 22:14:59.663744 31, 0x4141, End_B0=30 End_B1=30
8745 22:14:59.666965 Byte0 end_step=30 best_step=27
8746 22:14:59.670723 Byte1 end_step=30 best_step=27
8747 22:14:59.673780 Byte0 TX OE(2T, 0.5T) = (3, 3)
8748 22:14:59.677258 Byte1 TX OE(2T, 0.5T) = (3, 3)
8749 22:14:59.677728
8750 22:14:59.678094
8751 22:14:59.683895 [DQSOSCAuto] RK0, (LSB)MR18= 0xa0f, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 404 ps
8752 22:14:59.687009 CH1 RK0: MR19=303, MR18=A0F
8753 22:14:59.693154 CH1_RK0: MR19=0x303, MR18=0xA0F, DQSOSC=402, MR23=63, INC=22, DEC=15
8754 22:14:59.693627
8755 22:14:59.696728 ----->DramcWriteLeveling(PI) begin...
8756 22:14:59.697203 ==
8757 22:14:59.700075 Dram Type= 6, Freq= 0, CH_1, rank 1
8758 22:14:59.703258 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8759 22:14:59.703726 ==
8760 22:14:59.706768 Write leveling (Byte 0): 24 => 24
8761 22:14:59.710000 Write leveling (Byte 1): 28 => 28
8762 22:14:59.713211 DramcWriteLeveling(PI) end<-----
8763 22:14:59.713642
8764 22:14:59.714098 ==
8765 22:14:59.716763 Dram Type= 6, Freq= 0, CH_1, rank 1
8766 22:14:59.719993 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8767 22:14:59.720432 ==
8768 22:14:59.723246 [Gating] SW mode calibration
8769 22:14:59.730092 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8770 22:14:59.736502 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8771 22:14:59.739974 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8772 22:14:59.746330 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8773 22:14:59.749512 1 4 8 | B1->B0 | 2323 3434 | 0 0 | (0 0) (1 1)
8774 22:14:59.752760 1 4 12 | B1->B0 | 3131 3434 | 1 1 | (0 0) (1 1)
8775 22:14:59.759473 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8776 22:14:59.762864 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8777 22:14:59.766051 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8778 22:14:59.773050 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8779 22:14:59.776282 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8780 22:14:59.779524 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8781 22:14:59.785835 1 5 8 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 0)
8782 22:14:59.789007 1 5 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8783 22:14:59.792207 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8784 22:14:59.799382 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8785 22:14:59.802289 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8786 22:14:59.805778 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8787 22:14:59.811994 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8788 22:14:59.815224 1 6 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8789 22:14:59.818408 1 6 8 | B1->B0 | 2626 4141 | 1 0 | (0 0) (0 0)
8790 22:14:59.825212 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8791 22:14:59.828413 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8792 22:14:59.832158 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8793 22:14:59.838269 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8794 22:14:59.841965 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8795 22:14:59.845214 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8796 22:14:59.851440 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8797 22:14:59.855165 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8798 22:14:59.858267 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8799 22:14:59.865303 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8800 22:14:59.868170 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8801 22:14:59.871527 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8802 22:14:59.878346 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8803 22:14:59.881587 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8804 22:14:59.884413 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8805 22:14:59.891283 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8806 22:14:59.894552 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8807 22:14:59.898121 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8808 22:14:59.904773 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8809 22:14:59.908164 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8810 22:14:59.911100 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8811 22:14:59.917911 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8812 22:14:59.921008 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8813 22:14:59.924465 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8814 22:14:59.930822 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8815 22:14:59.931308 Total UI for P1: 0, mck2ui 16
8816 22:14:59.937269 best dqsien dly found for B0: ( 1, 9, 8)
8817 22:14:59.940847 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8818 22:14:59.944132 Total UI for P1: 0, mck2ui 16
8819 22:14:59.947319 best dqsien dly found for B1: ( 1, 9, 12)
8820 22:14:59.950888 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8821 22:14:59.953987 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8822 22:14:59.954444
8823 22:14:59.957205 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8824 22:14:59.960318 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8825 22:14:59.964078 [Gating] SW calibration Done
8826 22:14:59.964521 ==
8827 22:14:59.967009 Dram Type= 6, Freq= 0, CH_1, rank 1
8828 22:14:59.973536 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8829 22:14:59.973973 ==
8830 22:14:59.974339 RX Vref Scan: 0
8831 22:14:59.974689
8832 22:14:59.976723 RX Vref 0 -> 0, step: 1
8833 22:14:59.977167
8834 22:14:59.980148 RX Delay 0 -> 252, step: 8
8835 22:14:59.983480 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8836 22:14:59.987200 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8837 22:14:59.989979 iDelay=200, Bit 2, Center 115 (56 ~ 175) 120
8838 22:14:59.993263 iDelay=200, Bit 3, Center 127 (64 ~ 191) 128
8839 22:15:00.000616 iDelay=200, Bit 4, Center 127 (64 ~ 191) 128
8840 22:15:00.003520 iDelay=200, Bit 5, Center 139 (80 ~ 199) 120
8841 22:15:00.006707 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8842 22:15:00.010162 iDelay=200, Bit 7, Center 127 (64 ~ 191) 128
8843 22:15:00.013699 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8844 22:15:00.019878 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8845 22:15:00.023287 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8846 22:15:00.026365 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8847 22:15:00.029912 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8848 22:15:00.036653 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8849 22:15:00.039428 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8850 22:15:00.042986 iDelay=200, Bit 15, Center 139 (80 ~ 199) 120
8851 22:15:00.043505 ==
8852 22:15:00.046327 Dram Type= 6, Freq= 0, CH_1, rank 1
8853 22:15:00.049481 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8854 22:15:00.049963 ==
8855 22:15:00.053022 DQS Delay:
8856 22:15:00.053513 DQS0 = 0, DQS1 = 0
8857 22:15:00.056051 DQM Delay:
8858 22:15:00.056528 DQM0 = 129, DQM1 = 128
8859 22:15:00.056948 DQ Delay:
8860 22:15:00.062932 DQ0 =131, DQ1 =127, DQ2 =115, DQ3 =127
8861 22:15:00.066014 DQ4 =127, DQ5 =139, DQ6 =139, DQ7 =127
8862 22:15:00.069184 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =123
8863 22:15:00.072724 DQ12 =131, DQ13 =139, DQ14 =131, DQ15 =139
8864 22:15:00.073147
8865 22:15:00.073473
8866 22:15:00.073839 ==
8867 22:15:00.075987 Dram Type= 6, Freq= 0, CH_1, rank 1
8868 22:15:00.079150 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8869 22:15:00.079574 ==
8870 22:15:00.079905
8871 22:15:00.080209
8872 22:15:00.082332 TX Vref Scan disable
8873 22:15:00.085766 == TX Byte 0 ==
8874 22:15:00.088892 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8875 22:15:00.092519 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8876 22:15:00.095545 == TX Byte 1 ==
8877 22:15:00.099417 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8878 22:15:00.102225 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8879 22:15:00.102763 ==
8880 22:15:00.105473 Dram Type= 6, Freq= 0, CH_1, rank 1
8881 22:15:00.112215 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8882 22:15:00.112678 ==
8883 22:15:00.125158
8884 22:15:00.128428 TX Vref early break, caculate TX vref
8885 22:15:00.131802 TX Vref=16, minBit 0, minWin=23, winSum=382
8886 22:15:00.135173 TX Vref=18, minBit 0, minWin=23, winSum=392
8887 22:15:00.138039 TX Vref=20, minBit 0, minWin=24, winSum=402
8888 22:15:00.141469 TX Vref=22, minBit 0, minWin=24, winSum=405
8889 22:15:00.144745 TX Vref=24, minBit 0, minWin=23, winSum=408
8890 22:15:00.151232 TX Vref=26, minBit 0, minWin=25, winSum=420
8891 22:15:00.154821 TX Vref=28, minBit 0, minWin=26, winSum=426
8892 22:15:00.158012 TX Vref=30, minBit 0, minWin=25, winSum=419
8893 22:15:00.161057 TX Vref=32, minBit 8, minWin=23, winSum=410
8894 22:15:00.164525 TX Vref=34, minBit 1, minWin=24, winSum=406
8895 22:15:00.171269 TX Vref=36, minBit 0, minWin=23, winSum=390
8896 22:15:00.174578 [TxChooseVref] Worse bit 0, Min win 26, Win sum 426, Final Vref 28
8897 22:15:00.175075
8898 22:15:00.177859 Final TX Range 0 Vref 28
8899 22:15:00.178323
8900 22:15:00.178787 ==
8901 22:15:00.181306 Dram Type= 6, Freq= 0, CH_1, rank 1
8902 22:15:00.184294 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8903 22:15:00.187924 ==
8904 22:15:00.188386
8905 22:15:00.188747
8906 22:15:00.189079 TX Vref Scan disable
8907 22:15:00.194487 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8908 22:15:00.195005 == TX Byte 0 ==
8909 22:15:00.197342 u2DelayCellOfst[0]=18 cells (5 PI)
8910 22:15:00.200780 u2DelayCellOfst[1]=15 cells (4 PI)
8911 22:15:00.204467 u2DelayCellOfst[2]=0 cells (0 PI)
8912 22:15:00.207326 u2DelayCellOfst[3]=7 cells (2 PI)
8913 22:15:00.210776 u2DelayCellOfst[4]=11 cells (3 PI)
8914 22:15:00.214104 u2DelayCellOfst[5]=22 cells (6 PI)
8915 22:15:00.217085 u2DelayCellOfst[6]=22 cells (6 PI)
8916 22:15:00.220778 u2DelayCellOfst[7]=7 cells (2 PI)
8917 22:15:00.223527 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8918 22:15:00.226881 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8919 22:15:00.230571 == TX Byte 1 ==
8920 22:15:00.233687 u2DelayCellOfst[8]=0 cells (0 PI)
8921 22:15:00.236772 u2DelayCellOfst[9]=7 cells (2 PI)
8922 22:15:00.240199 u2DelayCellOfst[10]=15 cells (4 PI)
8923 22:15:00.243721 u2DelayCellOfst[11]=7 cells (2 PI)
8924 22:15:00.247134 u2DelayCellOfst[12]=15 cells (4 PI)
8925 22:15:00.249895 u2DelayCellOfst[13]=18 cells (5 PI)
8926 22:15:00.253177 u2DelayCellOfst[14]=22 cells (6 PI)
8927 22:15:00.256660 u2DelayCellOfst[15]=22 cells (6 PI)
8928 22:15:00.259920 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8929 22:15:00.263307 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8930 22:15:00.266586 DramC Write-DBI on
8931 22:15:00.267087 ==
8932 22:15:00.269697 Dram Type= 6, Freq= 0, CH_1, rank 1
8933 22:15:00.273424 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8934 22:15:00.273898 ==
8935 22:15:00.274364
8936 22:15:00.274809
8937 22:15:00.276512 TX Vref Scan disable
8938 22:15:00.279774 == TX Byte 0 ==
8939 22:15:00.283243 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8940 22:15:00.283744 == TX Byte 1 ==
8941 22:15:00.289670 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8942 22:15:00.290151 DramC Write-DBI off
8943 22:15:00.290626
8944 22:15:00.291101 [DATLAT]
8945 22:15:00.292738 Freq=1600, CH1 RK1
8946 22:15:00.293215
8947 22:15:00.296474 DATLAT Default: 0xf
8948 22:15:00.296922 0, 0xFFFF, sum = 0
8949 22:15:00.299690 1, 0xFFFF, sum = 0
8950 22:15:00.300185 2, 0xFFFF, sum = 0
8951 22:15:00.303053 3, 0xFFFF, sum = 0
8952 22:15:00.303492 4, 0xFFFF, sum = 0
8953 22:15:00.306486 5, 0xFFFF, sum = 0
8954 22:15:00.306946 6, 0xFFFF, sum = 0
8955 22:15:00.309896 7, 0xFFFF, sum = 0
8956 22:15:00.310324 8, 0xFFFF, sum = 0
8957 22:15:00.312589 9, 0xFFFF, sum = 0
8958 22:15:00.313013 10, 0xFFFF, sum = 0
8959 22:15:00.315934 11, 0xFFFF, sum = 0
8960 22:15:00.316360 12, 0xFFFF, sum = 0
8961 22:15:00.319413 13, 0x8FFF, sum = 0
8962 22:15:00.319836 14, 0x0, sum = 1
8963 22:15:00.322457 15, 0x0, sum = 2
8964 22:15:00.322910 16, 0x0, sum = 3
8965 22:15:00.325814 17, 0x0, sum = 4
8966 22:15:00.326289 best_step = 15
8967 22:15:00.326665
8968 22:15:00.327116 ==
8969 22:15:00.329166 Dram Type= 6, Freq= 0, CH_1, rank 1
8970 22:15:00.335832 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8971 22:15:00.336327 ==
8972 22:15:00.336675 RX Vref Scan: 0
8973 22:15:00.337048
8974 22:15:00.339015 RX Vref 0 -> 0, step: 1
8975 22:15:00.339490
8976 22:15:00.342396 RX Delay 11 -> 252, step: 4
8977 22:15:00.345885 iDelay=195, Bit 0, Center 132 (79 ~ 186) 108
8978 22:15:00.349291 iDelay=195, Bit 1, Center 126 (75 ~ 178) 104
8979 22:15:00.355871 iDelay=195, Bit 2, Center 114 (59 ~ 170) 112
8980 22:15:00.359243 iDelay=195, Bit 3, Center 126 (71 ~ 182) 112
8981 22:15:00.362507 iDelay=195, Bit 4, Center 124 (67 ~ 182) 116
8982 22:15:00.365602 iDelay=195, Bit 5, Center 138 (83 ~ 194) 112
8983 22:15:00.369016 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
8984 22:15:00.375281 iDelay=195, Bit 7, Center 124 (67 ~ 182) 116
8985 22:15:00.378434 iDelay=195, Bit 8, Center 110 (51 ~ 170) 120
8986 22:15:00.382134 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
8987 22:15:00.385201 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
8988 22:15:00.388442 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8989 22:15:00.394972 iDelay=195, Bit 12, Center 132 (79 ~ 186) 108
8990 22:15:00.398183 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8991 22:15:00.401948 iDelay=195, Bit 14, Center 132 (79 ~ 186) 108
8992 22:15:00.405089 iDelay=195, Bit 15, Center 136 (83 ~ 190) 108
8993 22:15:00.405514 ==
8994 22:15:00.408522 Dram Type= 6, Freq= 0, CH_1, rank 1
8995 22:15:00.414686 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8996 22:15:00.415220 ==
8997 22:15:00.415590 DQS Delay:
8998 22:15:00.418422 DQS0 = 0, DQS1 = 0
8999 22:15:00.418938 DQM Delay:
9000 22:15:00.421272 DQM0 = 127, DQM1 = 125
9001 22:15:00.421742 DQ Delay:
9002 22:15:00.425560 DQ0 =132, DQ1 =126, DQ2 =114, DQ3 =126
9003 22:15:00.427978 DQ4 =124, DQ5 =138, DQ6 =138, DQ7 =124
9004 22:15:00.430696 DQ8 =110, DQ9 =112, DQ10 =128, DQ11 =120
9005 22:15:00.434150 DQ12 =132, DQ13 =132, DQ14 =132, DQ15 =136
9006 22:15:00.434232
9007 22:15:00.434296
9008 22:15:00.434355
9009 22:15:00.437643 [DramC_TX_OE_Calibration] TA2
9010 22:15:00.441023 Original DQ_B0 (3 6) =30, OEN = 27
9011 22:15:00.444309 Original DQ_B1 (3 6) =30, OEN = 27
9012 22:15:00.447385 24, 0x0, End_B0=24 End_B1=24
9013 22:15:00.450645 25, 0x0, End_B0=25 End_B1=25
9014 22:15:00.450728 26, 0x0, End_B0=26 End_B1=26
9015 22:15:00.453997 27, 0x0, End_B0=27 End_B1=27
9016 22:15:00.457390 28, 0x0, End_B0=28 End_B1=28
9017 22:15:00.460878 29, 0x0, End_B0=29 End_B1=29
9018 22:15:00.464067 30, 0x0, End_B0=30 End_B1=30
9019 22:15:00.464149 31, 0x4141, End_B0=30 End_B1=30
9020 22:15:00.467425 Byte0 end_step=30 best_step=27
9021 22:15:00.470698 Byte1 end_step=30 best_step=27
9022 22:15:00.474048 Byte0 TX OE(2T, 0.5T) = (3, 3)
9023 22:15:00.477263 Byte1 TX OE(2T, 0.5T) = (3, 3)
9024 22:15:00.477345
9025 22:15:00.477408
9026 22:15:00.483408 [DQSOSCAuto] RK1, (LSB)MR18= 0x111e, (MSB)MR19= 0x303, tDQSOscB0 = 394 ps tDQSOscB1 = 401 ps
9027 22:15:00.486881 CH1 RK1: MR19=303, MR18=111E
9028 22:15:00.493661 CH1_RK1: MR19=0x303, MR18=0x111E, DQSOSC=394, MR23=63, INC=23, DEC=15
9029 22:15:00.496852 [RxdqsGatingPostProcess] freq 1600
9030 22:15:00.503556 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9031 22:15:00.506676 best DQS0 dly(2T, 0.5T) = (1, 1)
9032 22:15:00.506758 best DQS1 dly(2T, 0.5T) = (1, 1)
9033 22:15:00.509776 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9034 22:15:00.513121 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9035 22:15:00.516645 best DQS0 dly(2T, 0.5T) = (1, 1)
9036 22:15:00.519978 best DQS1 dly(2T, 0.5T) = (1, 1)
9037 22:15:00.522931 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9038 22:15:00.526416 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9039 22:15:00.529882 Pre-setting of DQS Precalculation
9040 22:15:00.533718 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9041 22:15:00.542936 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9042 22:15:00.549302 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9043 22:15:00.549406
9044 22:15:00.549491
9045 22:15:00.552659 [Calibration Summary] 3200 Mbps
9046 22:15:00.552763 CH 0, Rank 0
9047 22:15:00.556034 SW Impedance : PASS
9048 22:15:00.559528 DUTY Scan : NO K
9049 22:15:00.559654 ZQ Calibration : PASS
9050 22:15:00.562954 Jitter Meter : NO K
9051 22:15:00.563086 CBT Training : PASS
9052 22:15:00.566249 Write leveling : PASS
9053 22:15:00.569363 RX DQS gating : PASS
9054 22:15:00.569512 RX DQ/DQS(RDDQC) : PASS
9055 22:15:00.572545 TX DQ/DQS : PASS
9056 22:15:00.576187 RX DATLAT : PASS
9057 22:15:00.576361 RX DQ/DQS(Engine): PASS
9058 22:15:00.579149 TX OE : PASS
9059 22:15:00.579373 All Pass.
9060 22:15:00.579547
9061 22:15:00.582898 CH 0, Rank 1
9062 22:15:00.583237 SW Impedance : PASS
9063 22:15:00.585852 DUTY Scan : NO K
9064 22:15:00.589659 ZQ Calibration : PASS
9065 22:15:00.590111 Jitter Meter : NO K
9066 22:15:00.592796 CBT Training : PASS
9067 22:15:00.596076 Write leveling : PASS
9068 22:15:00.596651 RX DQS gating : PASS
9069 22:15:00.599377 RX DQ/DQS(RDDQC) : PASS
9070 22:15:00.602464 TX DQ/DQS : PASS
9071 22:15:00.602990 RX DATLAT : PASS
9072 22:15:00.605881 RX DQ/DQS(Engine): PASS
9073 22:15:00.608975 TX OE : PASS
9074 22:15:00.609462 All Pass.
9075 22:15:00.609827
9076 22:15:00.610168 CH 1, Rank 0
9077 22:15:00.612690 SW Impedance : PASS
9078 22:15:00.615785 DUTY Scan : NO K
9079 22:15:00.616309 ZQ Calibration : PASS
9080 22:15:00.619351 Jitter Meter : NO K
9081 22:15:00.622494 CBT Training : PASS
9082 22:15:00.623005 Write leveling : PASS
9083 22:15:00.625950 RX DQS gating : PASS
9084 22:15:00.629148 RX DQ/DQS(RDDQC) : PASS
9085 22:15:00.629676 TX DQ/DQS : PASS
9086 22:15:00.632226 RX DATLAT : PASS
9087 22:15:00.635604 RX DQ/DQS(Engine): PASS
9088 22:15:00.636070 TX OE : PASS
9089 22:15:00.636435 All Pass.
9090 22:15:00.636770
9091 22:15:00.638791 CH 1, Rank 1
9092 22:15:00.642124 SW Impedance : PASS
9093 22:15:00.642589 DUTY Scan : NO K
9094 22:15:00.645377 ZQ Calibration : PASS
9095 22:15:00.645839 Jitter Meter : NO K
9096 22:15:00.648736 CBT Training : PASS
9097 22:15:00.652528 Write leveling : PASS
9098 22:15:00.652992 RX DQS gating : PASS
9099 22:15:00.655435 RX DQ/DQS(RDDQC) : PASS
9100 22:15:00.658768 TX DQ/DQS : PASS
9101 22:15:00.659272 RX DATLAT : PASS
9102 22:15:00.662192 RX DQ/DQS(Engine): PASS
9103 22:15:00.665583 TX OE : PASS
9104 22:15:00.666049 All Pass.
9105 22:15:00.666413
9106 22:15:00.668944 DramC Write-DBI on
9107 22:15:00.669406 PER_BANK_REFRESH: Hybrid Mode
9108 22:15:00.671843 TX_TRACKING: ON
9109 22:15:00.682100 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9110 22:15:00.688889 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9111 22:15:00.694894 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9112 22:15:00.698377 [FAST_K] Save calibration result to emmc
9113 22:15:00.701453 sync common calibartion params.
9114 22:15:00.704795 sync cbt_mode0:1, 1:1
9115 22:15:00.705259 dram_init: ddr_geometry: 2
9116 22:15:00.707910 dram_init: ddr_geometry: 2
9117 22:15:00.711442 dram_init: ddr_geometry: 2
9118 22:15:00.714582 0:dram_rank_size:100000000
9119 22:15:00.715102 1:dram_rank_size:100000000
9120 22:15:00.721452 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9121 22:15:00.724562 DFS_SHUFFLE_HW_MODE: ON
9122 22:15:00.727894 dramc_set_vcore_voltage set vcore to 725000
9123 22:15:00.731413 Read voltage for 1600, 0
9124 22:15:00.731860 Vio18 = 0
9125 22:15:00.732199 Vcore = 725000
9126 22:15:00.734616 Vdram = 0
9127 22:15:00.735096 Vddq = 0
9128 22:15:00.735422 Vmddr = 0
9129 22:15:00.738184 switch to 3200 Mbps bootup
9130 22:15:00.738646 [DramcRunTimeConfig]
9131 22:15:00.741114 PHYPLL
9132 22:15:00.741570 DPM_CONTROL_AFTERK: ON
9133 22:15:00.744322 PER_BANK_REFRESH: ON
9134 22:15:00.748019 REFRESH_OVERHEAD_REDUCTION: ON
9135 22:15:00.748479 CMD_PICG_NEW_MODE: OFF
9136 22:15:00.750781 XRTWTW_NEW_MODE: ON
9137 22:15:00.751283 XRTRTR_NEW_MODE: ON
9138 22:15:00.754065 TX_TRACKING: ON
9139 22:15:00.754546 RDSEL_TRACKING: OFF
9140 22:15:00.757875 DQS Precalculation for DVFS: ON
9141 22:15:00.760767 RX_TRACKING: OFF
9142 22:15:00.761244 HW_GATING DBG: ON
9143 22:15:00.764173 ZQCS_ENABLE_LP4: ON
9144 22:15:00.764631 RX_PICG_NEW_MODE: ON
9145 22:15:00.767562 TX_PICG_NEW_MODE: ON
9146 22:15:00.770885 ENABLE_RX_DCM_DPHY: ON
9147 22:15:00.771344 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9148 22:15:00.774276 DUMMY_READ_FOR_TRACKING: OFF
9149 22:15:00.777243 !!! SPM_CONTROL_AFTERK: OFF
9150 22:15:00.780441 !!! SPM could not control APHY
9151 22:15:00.780859 IMPEDANCE_TRACKING: ON
9152 22:15:00.783819 TEMP_SENSOR: ON
9153 22:15:00.784233 HW_SAVE_FOR_SR: OFF
9154 22:15:00.787167 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9155 22:15:00.793862 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9156 22:15:00.794275 Read ODT Tracking: ON
9157 22:15:00.797133 Refresh Rate DeBounce: ON
9158 22:15:00.797589 DFS_NO_QUEUE_FLUSH: ON
9159 22:15:00.800173 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9160 22:15:00.803476 ENABLE_DFS_RUNTIME_MRW: OFF
9161 22:15:00.807604 DDR_RESERVE_NEW_MODE: ON
9162 22:15:00.810213 MR_CBT_SWITCH_FREQ: ON
9163 22:15:00.810683 =========================
9164 22:15:00.829852 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9165 22:15:00.832877 dram_init: ddr_geometry: 2
9166 22:15:00.851257 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9167 22:15:00.854910 dram_init: dram init end (result: 0)
9168 22:15:00.861476 DRAM-K: Full calibration passed in 24580 msecs
9169 22:15:00.864679 MRC: failed to locate region type 0.
9170 22:15:00.865208 DRAM rank0 size:0x100000000,
9171 22:15:00.867625 DRAM rank1 size=0x100000000
9172 22:15:00.877530 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9173 22:15:00.884335 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9174 22:15:00.890800 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9175 22:15:00.900824 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9176 22:15:00.901294 DRAM rank0 size:0x100000000,
9177 22:15:00.904063 DRAM rank1 size=0x100000000
9178 22:15:00.904539 CBMEM:
9179 22:15:00.907431 IMD: root @ 0xfffff000 254 entries.
9180 22:15:00.910875 IMD: root @ 0xffffec00 62 entries.
9181 22:15:00.913875 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9182 22:15:00.920086 WARNING: RO_VPD is uninitialized or empty.
9183 22:15:00.923607 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9184 22:15:00.931319 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9185 22:15:00.943862 read SPI 0x42894 0xe01e: 6227 us, 9213 KB/s, 73.704 Mbps
9186 22:15:00.955308 BS: romstage times (exec / console): total (unknown) / 24042 ms
9187 22:15:00.955773
9188 22:15:00.956138
9189 22:15:00.965450 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9190 22:15:00.968564 ARM64: Exception handlers installed.
9191 22:15:00.971956 ARM64: Testing exception
9192 22:15:00.975247 ARM64: Done test exception
9193 22:15:00.975695 Enumerating buses...
9194 22:15:00.978726 Show all devs... Before device enumeration.
9195 22:15:00.982030 Root Device: enabled 1
9196 22:15:00.985245 CPU_CLUSTER: 0: enabled 1
9197 22:15:00.985669 CPU: 00: enabled 1
9198 22:15:00.988747 Compare with tree...
9199 22:15:00.989180 Root Device: enabled 1
9200 22:15:00.992036 CPU_CLUSTER: 0: enabled 1
9201 22:15:00.994824 CPU: 00: enabled 1
9202 22:15:00.995291 Root Device scanning...
9203 22:15:00.998532 scan_static_bus for Root Device
9204 22:15:01.001734 CPU_CLUSTER: 0 enabled
9205 22:15:01.005131 scan_static_bus for Root Device done
9206 22:15:01.008428 scan_bus: bus Root Device finished in 8 msecs
9207 22:15:01.008880 done
9208 22:15:01.014714 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9209 22:15:01.017943 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9210 22:15:01.024825 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9211 22:15:01.028582 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9212 22:15:01.031552 Allocating resources...
9213 22:15:01.035065 Reading resources...
9214 22:15:01.037841 Root Device read_resources bus 0 link: 0
9215 22:15:01.041491 DRAM rank0 size:0x100000000,
9216 22:15:01.041951 DRAM rank1 size=0x100000000
9217 22:15:01.048208 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9218 22:15:01.048674 CPU: 00 missing read_resources
9219 22:15:01.054347 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9220 22:15:01.057863 Root Device read_resources bus 0 link: 0 done
9221 22:15:01.061231 Done reading resources.
9222 22:15:01.064561 Show resources in subtree (Root Device)...After reading.
9223 22:15:01.067626 Root Device child on link 0 CPU_CLUSTER: 0
9224 22:15:01.071179 CPU_CLUSTER: 0 child on link 0 CPU: 00
9225 22:15:01.081161 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9226 22:15:01.081634 CPU: 00
9227 22:15:01.084409 Root Device assign_resources, bus 0 link: 0
9228 22:15:01.087607 CPU_CLUSTER: 0 missing set_resources
9229 22:15:01.094014 Root Device assign_resources, bus 0 link: 0 done
9230 22:15:01.094478 Done setting resources.
9231 22:15:01.100898 Show resources in subtree (Root Device)...After assigning values.
9232 22:15:01.103733 Root Device child on link 0 CPU_CLUSTER: 0
9233 22:15:01.107420 CPU_CLUSTER: 0 child on link 0 CPU: 00
9234 22:15:01.117283 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9235 22:15:01.117749 CPU: 00
9236 22:15:01.120622 Done allocating resources.
9237 22:15:01.127245 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9238 22:15:01.127716 Enabling resources...
9239 22:15:01.130289 done.
9240 22:15:01.133950 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9241 22:15:01.137041 Initializing devices...
9242 22:15:01.137538 Root Device init
9243 22:15:01.140064 init hardware done!
9244 22:15:01.140527 0x00000018: ctrlr->caps
9245 22:15:01.143552 52.000 MHz: ctrlr->f_max
9246 22:15:01.146858 0.400 MHz: ctrlr->f_min
9247 22:15:01.147334 0x40ff8080: ctrlr->voltages
9248 22:15:01.149915 sclk: 390625
9249 22:15:01.150376 Bus Width = 1
9250 22:15:01.153449 sclk: 390625
9251 22:15:01.153912 Bus Width = 1
9252 22:15:01.156655 Early init status = 3
9253 22:15:01.160213 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9254 22:15:01.163407 in-header: 03 fc 00 00 01 00 00 00
9255 22:15:01.166578 in-data: 00
9256 22:15:01.169975 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9257 22:15:01.174461 in-header: 03 fd 00 00 00 00 00 00
9258 22:15:01.177375 in-data:
9259 22:15:01.180956 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9260 22:15:01.184632 in-header: 03 fc 00 00 01 00 00 00
9261 22:15:01.187483 in-data: 00
9262 22:15:01.190935 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9263 22:15:01.195445 in-header: 03 fd 00 00 00 00 00 00
9264 22:15:01.198894 in-data:
9265 22:15:01.202293 [SSUSB] Setting up USB HOST controller...
9266 22:15:01.204951 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9267 22:15:01.208738 [SSUSB] phy power-on done.
9268 22:15:01.212216 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9269 22:15:01.218429 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9270 22:15:01.221849 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9271 22:15:01.228400 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9272 22:15:01.234912 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9273 22:15:01.241408 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9274 22:15:01.248035 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9275 22:15:01.254660 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9276 22:15:01.257763 SPM: binary array size = 0x9dc
9277 22:15:01.264287 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9278 22:15:01.267245 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9279 22:15:01.277555 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9280 22:15:01.280647 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9281 22:15:01.283736 configure_display: Starting display init
9282 22:15:01.318825 anx7625_power_on_init: Init interface.
9283 22:15:01.322106 anx7625_disable_pd_protocol: Disabled PD feature.
9284 22:15:01.325081 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9285 22:15:01.353359 anx7625_start_dp_work: Secure OCM version=00
9286 22:15:01.356182 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9287 22:15:01.371040 sp_tx_get_edid_block: EDID Block = 1
9288 22:15:01.473692 Extracted contents:
9289 22:15:01.476788 header: 00 ff ff ff ff ff ff 00
9290 22:15:01.480356 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9291 22:15:01.483755 version: 01 04
9292 22:15:01.486856 basic params: 95 1f 11 78 0a
9293 22:15:01.490399 chroma info: 76 90 94 55 54 90 27 21 50 54
9294 22:15:01.493673 established: 00 00 00
9295 22:15:01.499891 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9296 22:15:01.507135 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9297 22:15:01.509940 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9298 22:15:01.516452 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9299 22:15:01.523117 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9300 22:15:01.526684 extensions: 00
9301 22:15:01.527075 checksum: fb
9302 22:15:01.527363
9303 22:15:01.529943 Manufacturer: IVO Model 57d Serial Number 0
9304 22:15:01.532940 Made week 0 of 2020
9305 22:15:01.536285 EDID version: 1.4
9306 22:15:01.536668 Digital display
9307 22:15:01.539621 6 bits per primary color channel
9308 22:15:01.540035 DisplayPort interface
9309 22:15:01.543068 Maximum image size: 31 cm x 17 cm
9310 22:15:01.546201 Gamma: 220%
9311 22:15:01.546520 Check DPMS levels
9312 22:15:01.549493 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9313 22:15:01.556189 First detailed timing is preferred timing
9314 22:15:01.556516 Established timings supported:
9315 22:15:01.559530 Standard timings supported:
9316 22:15:01.563076 Detailed timings
9317 22:15:01.566571 Hex of detail: 383680a07038204018303c0035ae10000019
9318 22:15:01.572843 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9319 22:15:01.575819 0780 0798 07c8 0820 hborder 0
9320 22:15:01.579398 0438 043b 0447 0458 vborder 0
9321 22:15:01.582671 -hsync -vsync
9322 22:15:01.583073 Did detailed timing
9323 22:15:01.589244 Hex of detail: 000000000000000000000000000000000000
9324 22:15:01.592364 Manufacturer-specified data, tag 0
9325 22:15:01.596109 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9326 22:15:01.599304 ASCII string: InfoVision
9327 22:15:01.602752 Hex of detail: 000000fe00523134304e574635205248200a
9328 22:15:01.605651 ASCII string: R140NWF5 RH
9329 22:15:01.605976 Checksum
9330 22:15:01.608878 Checksum: 0xfb (valid)
9331 22:15:01.612483 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9332 22:15:01.615651 DSI data_rate: 832800000 bps
9333 22:15:01.622432 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9334 22:15:01.625812 anx7625_parse_edid: pixelclock(138800).
9335 22:15:01.629127 hactive(1920), hsync(48), hfp(24), hbp(88)
9336 22:15:01.631938 vactive(1080), vsync(12), vfp(3), vbp(17)
9337 22:15:01.635300 anx7625_dsi_config: config dsi.
9338 22:15:01.641998 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9339 22:15:01.655999 anx7625_dsi_config: success to config DSI
9340 22:15:01.658815 anx7625_dp_start: MIPI phy setup OK.
9341 22:15:01.662290 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9342 22:15:01.665630 mtk_ddp_mode_set invalid vrefresh 60
9343 22:15:01.668792 main_disp_path_setup
9344 22:15:01.669248 ovl_layer_smi_id_en
9345 22:15:01.672243 ovl_layer_smi_id_en
9346 22:15:01.672700 ccorr_config
9347 22:15:01.673054 aal_config
9348 22:15:01.675465 gamma_config
9349 22:15:01.675919 postmask_config
9350 22:15:01.678504 dither_config
9351 22:15:01.682039 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9352 22:15:01.688554 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9353 22:15:01.691777 Root Device init finished in 551 msecs
9354 22:15:01.695433 CPU_CLUSTER: 0 init
9355 22:15:01.701854 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9356 22:15:01.708384 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9357 22:15:01.708840 APU_MBOX 0x190000b0 = 0x10001
9358 22:15:01.711854 APU_MBOX 0x190001b0 = 0x10001
9359 22:15:01.715120 APU_MBOX 0x190005b0 = 0x10001
9360 22:15:01.718578 APU_MBOX 0x190006b0 = 0x10001
9361 22:15:01.724818 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9362 22:15:01.734954 read SPI 0x539f4 0xe237: 6251 us, 9264 KB/s, 74.112 Mbps
9363 22:15:01.747089 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9364 22:15:01.753690 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9365 22:15:01.765370 read SPI 0x61c74 0xe8ef: 6412 us, 9299 KB/s, 74.392 Mbps
9366 22:15:01.774499 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9367 22:15:01.778039 CPU_CLUSTER: 0 init finished in 81 msecs
9368 22:15:01.781117 Devices initialized
9369 22:15:01.784213 Show all devs... After init.
9370 22:15:01.784676 Root Device: enabled 1
9371 22:15:01.787645 CPU_CLUSTER: 0: enabled 1
9372 22:15:01.791264 CPU: 00: enabled 1
9373 22:15:01.794279 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9374 22:15:01.797802 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9375 22:15:01.800859 ELOG: NV offset 0x57f000 size 0x1000
9376 22:15:01.807507 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9377 22:15:01.813987 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9378 22:15:01.817426 ELOG: Event(17) added with size 13 at 2023-06-05 22:15:06 UTC
9379 22:15:01.823900 out: cmd=0x121: 03 db 21 01 00 00 00 00
9380 22:15:01.827112 in-header: 03 51 00 00 2c 00 00 00
9381 22:15:01.840517 in-data: 0d 69 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9382 22:15:01.843896 ELOG: Event(A1) added with size 10 at 2023-06-05 22:15:06 UTC
9383 22:15:01.850637 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9384 22:15:01.857151 ELOG: Event(A0) added with size 9 at 2023-06-05 22:15:06 UTC
9385 22:15:01.860457 elog_add_boot_reason: Logged dev mode boot
9386 22:15:01.867166 BS: BS_POST_DEVICE entry times (exec / console): 3 / 64 ms
9387 22:15:01.867632 Finalize devices...
9388 22:15:01.870045 Devices finalized
9389 22:15:01.873448 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9390 22:15:01.876786 Writing coreboot table at 0xffe64000
9391 22:15:01.883495 0. 000000000010a000-0000000000113fff: RAMSTAGE
9392 22:15:01.886288 1. 0000000040000000-00000000400fffff: RAM
9393 22:15:01.890312 2. 0000000040100000-000000004032afff: RAMSTAGE
9394 22:15:01.893643 3. 000000004032b000-00000000545fffff: RAM
9395 22:15:01.896471 4. 0000000054600000-000000005465ffff: BL31
9396 22:15:01.903197 5. 0000000054660000-00000000ffe63fff: RAM
9397 22:15:01.906175 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9398 22:15:01.909546 7. 0000000100000000-000000023fffffff: RAM
9399 22:15:01.912775 Passing 5 GPIOs to payload:
9400 22:15:01.919423 NAME | PORT | POLARITY | VALUE
9401 22:15:01.923187 EC in RW | 0x000000aa | low | undefined
9402 22:15:01.926011 EC interrupt | 0x00000005 | low | undefined
9403 22:15:01.932440 TPM interrupt | 0x000000ab | high | undefined
9404 22:15:01.936125 SD card detect | 0x00000011 | high | undefined
9405 22:15:01.942729 speaker enable | 0x00000093 | high | undefined
9406 22:15:01.945986 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9407 22:15:01.949198 in-header: 03 f9 00 00 02 00 00 00
9408 22:15:01.949620 in-data: 02 00
9409 22:15:01.952603 ADC[4]: Raw value=896670 ID=7
9410 22:15:01.955908 ADC[3]: Raw value=212330 ID=1
9411 22:15:01.956328 RAM Code: 0x71
9412 22:15:01.958811 ADC[6]: Raw value=74722 ID=0
9413 22:15:01.962075 ADC[5]: Raw value=212700 ID=1
9414 22:15:01.962497 SKU Code: 0x1
9415 22:15:01.968737 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 7dbf
9416 22:15:01.971978 coreboot table: 964 bytes.
9417 22:15:01.975379 IMD ROOT 0. 0xfffff000 0x00001000
9418 22:15:01.978944 IMD SMALL 1. 0xffffe000 0x00001000
9419 22:15:01.981785 RO MCACHE 2. 0xffffc000 0x00001104
9420 22:15:01.985213 CONSOLE 3. 0xfff7c000 0x00080000
9421 22:15:01.988616 FMAP 4. 0xfff7b000 0x00000452
9422 22:15:01.991867 TIME STAMP 5. 0xfff7a000 0x00000910
9423 22:15:01.995321 VBOOT WORK 6. 0xfff66000 0x00014000
9424 22:15:01.998252 RAMOOPS 7. 0xffe66000 0x00100000
9425 22:15:02.001921 COREBOOT 8. 0xffe64000 0x00002000
9426 22:15:02.002343 IMD small region:
9427 22:15:02.004836 IMD ROOT 0. 0xffffec00 0x00000400
9428 22:15:02.008319 VPD 1. 0xffffeba0 0x0000004c
9429 22:15:02.011745 MMC STATUS 2. 0xffffeb80 0x00000004
9430 22:15:02.018648 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9431 22:15:02.019104 Probing TPM: done!
9432 22:15:02.025275 Connected to device vid:did:rid of 1ae0:0028:00
9433 22:15:02.035013 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
9434 22:15:02.038165 Initialized TPM device CR50 revision 0
9435 22:15:02.041862 Checking cr50 for pending updates
9436 22:15:02.045031 Reading cr50 TPM mode
9437 22:15:02.053515 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9438 22:15:02.060384 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9439 22:15:02.100355 read SPI 0x3990ec 0x4f1b0: 34860 us, 9294 KB/s, 74.352 Mbps
9440 22:15:02.103818 Checking segment from ROM address 0x40100000
9441 22:15:02.107064 Checking segment from ROM address 0x4010001c
9442 22:15:02.113729 Loading segment from ROM address 0x40100000
9443 22:15:02.114300 code (compression=0)
9444 22:15:02.123865 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9445 22:15:02.130021 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9446 22:15:02.130448 it's not compressed!
9447 22:15:02.136892 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9448 22:15:02.143291 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9449 22:15:02.160710 Loading segment from ROM address 0x4010001c
9450 22:15:02.161132 Entry Point 0x80000000
9451 22:15:02.163819 Loaded segments
9452 22:15:02.167147 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9453 22:15:02.173841 Jumping to boot code at 0x80000000(0xffe64000)
9454 22:15:02.180458 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9455 22:15:02.186932 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9456 22:15:02.194929 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9457 22:15:02.198642 Checking segment from ROM address 0x40100000
9458 22:15:02.201562 Checking segment from ROM address 0x4010001c
9459 22:15:02.208144 Loading segment from ROM address 0x40100000
9460 22:15:02.208659 code (compression=1)
9461 22:15:02.214957 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9462 22:15:02.225074 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9463 22:15:02.225548 using LZMA
9464 22:15:02.233332 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9465 22:15:02.240025 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9466 22:15:02.243188 Loading segment from ROM address 0x4010001c
9467 22:15:02.243657 Entry Point 0x54601000
9468 22:15:02.246947 Loaded segments
9469 22:15:02.250138 NOTICE: MT8192 bl31_setup
9470 22:15:02.257226 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9471 22:15:02.260244 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9472 22:15:02.263918 WARNING: region 0:
9473 22:15:02.267685 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9474 22:15:02.268152 WARNING: region 1:
9475 22:15:02.273904 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9476 22:15:02.277359 WARNING: region 2:
9477 22:15:02.280419 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9478 22:15:02.283919 WARNING: region 3:
9479 22:15:02.286775 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9480 22:15:02.290714 WARNING: region 4:
9481 22:15:02.297008 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9482 22:15:02.297473 WARNING: region 5:
9483 22:15:02.300380 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9484 22:15:02.303781 WARNING: region 6:
9485 22:15:02.307092 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9486 22:15:02.310454 WARNING: region 7:
9487 22:15:02.313290 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9488 22:15:02.320084 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9489 22:15:02.323524 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9490 22:15:02.326782 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9491 22:15:02.333340 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9492 22:15:02.336530 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9493 22:15:02.343308 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9494 22:15:02.346498 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9495 22:15:02.349931 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9496 22:15:02.356212 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9497 22:15:02.359823 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9498 22:15:02.363250 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9499 22:15:02.369749 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9500 22:15:02.372966 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9501 22:15:02.379975 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9502 22:15:02.382893 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9503 22:15:02.386201 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9504 22:15:02.392930 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9505 22:15:02.396377 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9506 22:15:02.402498 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9507 22:15:02.405753 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9508 22:15:02.409589 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9509 22:15:02.415931 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9510 22:15:02.419254 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9511 22:15:02.425931 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9512 22:15:02.429108 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9513 22:15:02.432440 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9514 22:15:02.438917 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9515 22:15:02.442470 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9516 22:15:02.448730 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9517 22:15:02.452385 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9518 22:15:02.455624 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9519 22:15:02.462435 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9520 22:15:02.465526 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9521 22:15:02.469019 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9522 22:15:02.475497 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9523 22:15:02.479015 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9524 22:15:02.481785 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9525 22:15:02.485246 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9526 22:15:02.491861 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9527 22:15:02.495164 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9528 22:15:02.498529 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9529 22:15:02.501918 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9530 22:15:02.508581 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9531 22:15:02.511558 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9532 22:15:02.514812 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9533 22:15:02.518152 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9534 22:15:02.525042 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9535 22:15:02.528395 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9536 22:15:02.531925 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9537 22:15:02.538587 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9538 22:15:02.541324 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9539 22:15:02.548495 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9540 22:15:02.551549 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9541 22:15:02.557905 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9542 22:15:02.561554 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9543 22:15:02.564877 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9544 22:15:02.571486 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9545 22:15:02.574785 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9546 22:15:02.581320 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9547 22:15:02.584393 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9548 22:15:02.591438 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9549 22:15:02.594511 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9550 22:15:02.601344 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9551 22:15:02.604291 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9552 22:15:02.607717 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9553 22:15:02.614562 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9554 22:15:02.617466 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9555 22:15:02.624200 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9556 22:15:02.627590 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9557 22:15:02.634542 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9558 22:15:02.637765 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9559 22:15:02.640886 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9560 22:15:02.647330 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9561 22:15:02.650930 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9562 22:15:02.657523 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9563 22:15:02.661033 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9564 22:15:02.667421 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9565 22:15:02.670378 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9566 22:15:02.677217 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9567 22:15:02.680945 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9568 22:15:02.687454 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9569 22:15:02.690825 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9570 22:15:02.693852 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9571 22:15:02.700721 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9572 22:15:02.703689 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9573 22:15:02.710559 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9574 22:15:02.714187 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9575 22:15:02.720274 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9576 22:15:02.723728 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9577 22:15:02.727134 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9578 22:15:02.733315 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9579 22:15:02.736703 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9580 22:15:02.743328 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9581 22:15:02.746738 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9582 22:15:02.753422 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9583 22:15:02.756777 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9584 22:15:02.759737 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9585 22:15:02.766323 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9586 22:15:02.770042 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9587 22:15:02.772812 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9588 22:15:02.776364 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9589 22:15:02.783291 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9590 22:15:02.786260 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9591 22:15:02.792723 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9592 22:15:02.796062 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9593 22:15:02.799557 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9594 22:15:02.806245 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9595 22:15:02.809507 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9596 22:15:02.816503 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9597 22:15:02.819325 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9598 22:15:02.822532 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9599 22:15:02.829381 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9600 22:15:02.832779 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9601 22:15:02.839096 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9602 22:15:02.842734 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9603 22:15:02.849030 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9604 22:15:02.852463 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9605 22:15:02.855742 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9606 22:15:02.862173 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9607 22:15:02.865944 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9608 22:15:02.869308 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9609 22:15:02.872324 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9610 22:15:02.875933 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9611 22:15:02.882172 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9612 22:15:02.885853 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9613 22:15:02.891931 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9614 22:15:02.895639 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9615 22:15:02.898945 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9616 22:15:02.905222 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9617 22:15:02.908410 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9618 22:15:02.915167 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9619 22:15:02.918745 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9620 22:15:02.921820 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9621 22:15:02.928855 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9622 22:15:02.931804 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9623 22:15:02.938234 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9624 22:15:02.941928 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9625 22:15:02.945068 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9626 22:15:02.951875 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9627 22:15:02.955240 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9628 22:15:02.958554 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9629 22:15:02.965066 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9630 22:15:02.968481 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9631 22:15:02.975556 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9632 22:15:02.978610 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9633 22:15:02.981528 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9634 22:15:02.988490 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9635 22:15:02.991305 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9636 22:15:02.998366 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9637 22:15:03.001547 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9638 22:15:03.004939 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9639 22:15:03.011451 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9640 22:15:03.015176 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9641 22:15:03.021489 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9642 22:15:03.025056 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9643 22:15:03.028083 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9644 22:15:03.034826 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9645 22:15:03.038060 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9646 22:15:03.041550 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9647 22:15:03.048024 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9648 22:15:03.051440 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9649 22:15:03.057726 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9650 22:15:03.061027 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9651 22:15:03.067801 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9652 22:15:03.070990 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9653 22:15:03.074139 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9654 22:15:03.080784 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9655 22:15:03.084062 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9656 22:15:03.090784 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9657 22:15:03.094231 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9658 22:15:03.097255 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9659 22:15:03.104075 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9660 22:15:03.107306 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9661 22:15:03.113865 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9662 22:15:03.117029 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9663 22:15:03.120291 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9664 22:15:03.126895 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9665 22:15:03.130579 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9666 22:15:03.136972 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9667 22:15:03.140292 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9668 22:15:03.143079 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9669 22:15:03.149792 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9670 22:15:03.153277 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9671 22:15:03.160314 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9672 22:15:03.162776 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9673 22:15:03.166265 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9674 22:15:03.172877 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9675 22:15:03.176206 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9676 22:15:03.183256 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9677 22:15:03.186149 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9678 22:15:03.192690 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9679 22:15:03.195809 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9680 22:15:03.199424 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9681 22:15:03.206025 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9682 22:15:03.209226 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9683 22:15:03.215845 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9684 22:15:03.219189 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9685 22:15:03.225672 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9686 22:15:03.229000 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9687 22:15:03.232101 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9688 22:15:03.238461 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9689 22:15:03.241952 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9690 22:15:03.249039 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9691 22:15:03.252083 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9692 22:15:03.258402 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9693 22:15:03.261790 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9694 22:15:03.265270 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9695 22:15:03.271901 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9696 22:15:03.275225 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9697 22:15:03.281648 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9698 22:15:03.285254 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9699 22:15:03.288475 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9700 22:15:03.295140 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9701 22:15:03.298329 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9702 22:15:03.304554 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9703 22:15:03.308242 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9704 22:15:03.315123 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9705 22:15:03.318030 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9706 22:15:03.321136 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9707 22:15:03.327687 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9708 22:15:03.331026 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9709 22:15:03.338055 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9710 22:15:03.341316 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9711 22:15:03.347905 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9712 22:15:03.351173 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9713 22:15:03.354432 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9714 22:15:03.361171 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9715 22:15:03.363917 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9716 22:15:03.370849 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9717 22:15:03.374221 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9718 22:15:03.377497 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9719 22:15:03.380513 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9720 22:15:03.387208 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9721 22:15:03.390396 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9722 22:15:03.393579 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9723 22:15:03.400280 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9724 22:15:03.403498 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9725 22:15:03.407445 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9726 22:15:03.413856 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9727 22:15:03.416877 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9728 22:15:03.423177 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9729 22:15:03.426934 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9730 22:15:03.430346 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9731 22:15:03.436528 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9732 22:15:03.440057 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9733 22:15:03.443295 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9734 22:15:03.450114 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9735 22:15:03.453002 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9736 22:15:03.456421 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9737 22:15:03.462887 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9738 22:15:03.466430 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9739 22:15:03.473164 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9740 22:15:03.475985 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9741 22:15:03.479331 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9742 22:15:03.486233 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9743 22:15:03.489341 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9744 22:15:03.495887 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9745 22:15:03.498985 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9746 22:15:03.502733 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9747 22:15:03.509033 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9748 22:15:03.512499 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9749 22:15:03.516269 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9750 22:15:03.522276 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9751 22:15:03.525842 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9752 22:15:03.529068 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9753 22:15:03.535785 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9754 22:15:03.539341 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9755 22:15:03.545434 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9756 22:15:03.548795 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9757 22:15:03.551874 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9758 22:15:03.555366 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9759 22:15:03.561653 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9760 22:15:03.565420 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9761 22:15:03.568790 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9762 22:15:03.571551 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9763 22:15:03.578645 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9764 22:15:03.581716 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9765 22:15:03.585007 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9766 22:15:03.588412 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9767 22:15:03.595154 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9768 22:15:03.597951 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9769 22:15:03.601344 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9770 22:15:03.608636 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9771 22:15:03.611448 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9772 22:15:03.617967 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9773 22:15:03.621217 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9774 22:15:03.624306 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9775 22:15:03.631087 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9776 22:15:03.634225 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9777 22:15:03.640884 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9778 22:15:03.644101 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9779 22:15:03.650496 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9780 22:15:03.654003 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9781 22:15:03.657291 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9782 22:15:03.663877 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9783 22:15:03.667576 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9784 22:15:03.673734 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9785 22:15:03.677138 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9786 22:15:03.680421 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9787 22:15:03.687126 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9788 22:15:03.690096 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9789 22:15:03.696657 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9790 22:15:03.700075 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9791 22:15:03.706820 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9792 22:15:03.710189 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9793 22:15:03.713326 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9794 22:15:03.719845 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9795 22:15:03.722939 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9796 22:15:03.729820 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9797 22:15:03.732752 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9798 22:15:03.739842 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9799 22:15:03.742971 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9800 22:15:03.746107 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9801 22:15:03.752644 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9802 22:15:03.756307 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9803 22:15:03.763068 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9804 22:15:03.766145 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9805 22:15:03.769866 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9806 22:15:03.775919 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9807 22:15:03.779374 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9808 22:15:03.786401 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9809 22:15:03.789043 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9810 22:15:03.792615 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9811 22:15:03.799337 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9812 22:15:03.802517 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9813 22:15:03.808775 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9814 22:15:03.812672 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9815 22:15:03.818904 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9816 22:15:03.822477 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9817 22:15:03.825618 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9818 22:15:03.832167 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9819 22:15:03.835127 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9820 22:15:03.842114 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9821 22:15:03.845406 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9822 22:15:03.851933 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9823 22:15:03.854819 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9824 22:15:03.858504 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9825 22:15:03.865203 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9826 22:15:03.868437 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9827 22:15:03.875284 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9828 22:15:03.878377 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9829 22:15:03.881766 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9830 22:15:03.888434 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9831 22:15:03.891508 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9832 22:15:03.898167 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9833 22:15:03.901498 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9834 22:15:03.904933 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9835 22:15:03.911636 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9836 22:15:03.914374 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9837 22:15:03.920945 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9838 22:15:03.924817 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9839 22:15:03.931062 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9840 22:15:03.934672 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9841 22:15:03.937778 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9842 22:15:03.944527 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9843 22:15:03.947386 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9844 22:15:03.953895 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9845 22:15:03.957543 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9846 22:15:03.963860 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9847 22:15:03.967007 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9848 22:15:03.974145 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9849 22:15:03.977036 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9850 22:15:03.980733 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9851 22:15:03.987089 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9852 22:15:03.990278 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9853 22:15:03.996644 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9854 22:15:04.000318 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9855 22:15:04.007082 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9856 22:15:04.010040 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9857 22:15:04.016844 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9858 22:15:04.020195 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9859 22:15:04.023594 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9860 22:15:04.029822 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9861 22:15:04.033118 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9862 22:15:04.039951 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9863 22:15:04.043423 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9864 22:15:04.049832 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9865 22:15:04.052852 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9866 22:15:04.059586 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9867 22:15:04.062813 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9868 22:15:04.066300 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9869 22:15:04.072805 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9870 22:15:04.075936 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9871 22:15:04.082599 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9872 22:15:04.086168 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9873 22:15:04.092187 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9874 22:15:04.095706 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9875 22:15:04.102457 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9876 22:15:04.105945 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9877 22:15:04.109261 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9878 22:15:04.115947 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9879 22:15:04.118785 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9880 22:15:04.125501 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9881 22:15:04.128754 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9882 22:15:04.135489 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9883 22:15:04.138586 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9884 22:15:04.145462 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9885 22:15:04.148399 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9886 22:15:04.155180 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9887 22:15:04.158284 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9888 22:15:04.161925 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9889 22:15:04.168158 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9890 22:15:04.171770 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9891 22:15:04.178042 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9892 22:15:04.181670 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9893 22:15:04.188153 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9894 22:15:04.191480 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9895 22:15:04.195045 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9896 22:15:04.201485 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9897 22:15:04.204650 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9898 22:15:04.211346 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9899 22:15:04.214870 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9900 22:15:04.221174 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9901 22:15:04.224377 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9902 22:15:04.230738 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9903 22:15:04.234095 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9904 22:15:04.240884 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9905 22:15:04.244208 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9906 22:15:04.250373 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9907 22:15:04.254000 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9908 22:15:04.260221 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9909 22:15:04.264000 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9910 22:15:04.270616 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9911 22:15:04.273742 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9912 22:15:04.279944 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9913 22:15:04.283994 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9914 22:15:04.290380 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9915 22:15:04.293243 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9916 22:15:04.299888 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9917 22:15:04.306999 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9918 22:15:04.310312 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9919 22:15:04.316595 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9920 22:15:04.319979 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9921 22:15:04.326322 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9922 22:15:04.329703 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9923 22:15:04.330218 INFO: [APUAPC] vio 0
9924 22:15:04.337178 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9925 22:15:04.340643 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9926 22:15:04.343480 INFO: [APUAPC] D0_APC_0: 0x400510
9927 22:15:04.346909 INFO: [APUAPC] D0_APC_1: 0x0
9928 22:15:04.350088 INFO: [APUAPC] D0_APC_2: 0x1540
9929 22:15:04.353363 INFO: [APUAPC] D0_APC_3: 0x0
9930 22:15:04.357069 INFO: [APUAPC] D1_APC_0: 0xffffffff
9931 22:15:04.360145 INFO: [APUAPC] D1_APC_1: 0xffffffff
9932 22:15:04.363318 INFO: [APUAPC] D1_APC_2: 0x3fffff
9933 22:15:04.366486 INFO: [APUAPC] D1_APC_3: 0x0
9934 22:15:04.370185 INFO: [APUAPC] D2_APC_0: 0xffffffff
9935 22:15:04.373223 INFO: [APUAPC] D2_APC_1: 0xffffffff
9936 22:15:04.376739 INFO: [APUAPC] D2_APC_2: 0x3fffff
9937 22:15:04.379817 INFO: [APUAPC] D2_APC_3: 0x0
9938 22:15:04.382955 INFO: [APUAPC] D3_APC_0: 0xffffffff
9939 22:15:04.386443 INFO: [APUAPC] D3_APC_1: 0xffffffff
9940 22:15:04.389505 INFO: [APUAPC] D3_APC_2: 0x3fffff
9941 22:15:04.393155 INFO: [APUAPC] D3_APC_3: 0x0
9942 22:15:04.396172 INFO: [APUAPC] D4_APC_0: 0xffffffff
9943 22:15:04.399541 INFO: [APUAPC] D4_APC_1: 0xffffffff
9944 22:15:04.402899 INFO: [APUAPC] D4_APC_2: 0x3fffff
9945 22:15:04.406744 INFO: [APUAPC] D4_APC_3: 0x0
9946 22:15:04.409366 INFO: [APUAPC] D5_APC_0: 0xffffffff
9947 22:15:04.412985 INFO: [APUAPC] D5_APC_1: 0xffffffff
9948 22:15:04.416265 INFO: [APUAPC] D5_APC_2: 0x3fffff
9949 22:15:04.419270 INFO: [APUAPC] D5_APC_3: 0x0
9950 22:15:04.422719 INFO: [APUAPC] D6_APC_0: 0xffffffff
9951 22:15:04.426089 INFO: [APUAPC] D6_APC_1: 0xffffffff
9952 22:15:04.429707 INFO: [APUAPC] D6_APC_2: 0x3fffff
9953 22:15:04.432357 INFO: [APUAPC] D6_APC_3: 0x0
9954 22:15:04.435775 INFO: [APUAPC] D7_APC_0: 0xffffffff
9955 22:15:04.439052 INFO: [APUAPC] D7_APC_1: 0xffffffff
9956 22:15:04.442406 INFO: [APUAPC] D7_APC_2: 0x3fffff
9957 22:15:04.442921 INFO: [APUAPC] D7_APC_3: 0x0
9958 22:15:04.449137 INFO: [APUAPC] D8_APC_0: 0xffffffff
9959 22:15:04.452523 INFO: [APUAPC] D8_APC_1: 0xffffffff
9960 22:15:04.455913 INFO: [APUAPC] D8_APC_2: 0x3fffff
9961 22:15:04.456353 INFO: [APUAPC] D8_APC_3: 0x0
9962 22:15:04.458965 INFO: [APUAPC] D9_APC_0: 0xffffffff
9963 22:15:04.465642 INFO: [APUAPC] D9_APC_1: 0xffffffff
9964 22:15:04.468702 INFO: [APUAPC] D9_APC_2: 0x3fffff
9965 22:15:04.469157 INFO: [APUAPC] D9_APC_3: 0x0
9966 22:15:04.472498 INFO: [APUAPC] D10_APC_0: 0xffffffff
9967 22:15:04.478763 INFO: [APUAPC] D10_APC_1: 0xffffffff
9968 22:15:04.481835 INFO: [APUAPC] D10_APC_2: 0x3fffff
9969 22:15:04.482236 INFO: [APUAPC] D10_APC_3: 0x0
9970 22:15:04.485462 INFO: [APUAPC] D11_APC_0: 0xffffffff
9971 22:15:04.491852 INFO: [APUAPC] D11_APC_1: 0xffffffff
9972 22:15:04.495232 INFO: [APUAPC] D11_APC_2: 0x3fffff
9973 22:15:04.495655 INFO: [APUAPC] D11_APC_3: 0x0
9974 22:15:04.502019 INFO: [APUAPC] D12_APC_0: 0xffffffff
9975 22:15:04.505298 INFO: [APUAPC] D12_APC_1: 0xffffffff
9976 22:15:04.508747 INFO: [APUAPC] D12_APC_2: 0x3fffff
9977 22:15:04.511828 INFO: [APUAPC] D12_APC_3: 0x0
9978 22:15:04.515450 INFO: [APUAPC] D13_APC_0: 0xffffffff
9979 22:15:04.518963 INFO: [APUAPC] D13_APC_1: 0xffffffff
9980 22:15:04.521577 INFO: [APUAPC] D13_APC_2: 0x3fffff
9981 22:15:04.525270 INFO: [APUAPC] D13_APC_3: 0x0
9982 22:15:04.528112 INFO: [APUAPC] D14_APC_0: 0xffffffff
9983 22:15:04.531605 INFO: [APUAPC] D14_APC_1: 0xffffffff
9984 22:15:04.534945 INFO: [APUAPC] D14_APC_2: 0x3fffff
9985 22:15:04.538644 INFO: [APUAPC] D14_APC_3: 0x0
9986 22:15:04.541273 INFO: [APUAPC] D15_APC_0: 0xffffffff
9987 22:15:04.544501 INFO: [APUAPC] D15_APC_1: 0xffffffff
9988 22:15:04.547996 INFO: [APUAPC] D15_APC_2: 0x3fffff
9989 22:15:04.551456 INFO: [APUAPC] D15_APC_3: 0x0
9990 22:15:04.554347 INFO: [APUAPC] APC_CON: 0x4
9991 22:15:04.554805 INFO: [NOCDAPC] D0_APC_0: 0x0
9992 22:15:04.558220 INFO: [NOCDAPC] D0_APC_1: 0x0
9993 22:15:04.561338 INFO: [NOCDAPC] D1_APC_0: 0x0
9994 22:15:04.564383 INFO: [NOCDAPC] D1_APC_1: 0xfff
9995 22:15:04.567570 INFO: [NOCDAPC] D2_APC_0: 0x0
9996 22:15:04.571072 INFO: [NOCDAPC] D2_APC_1: 0xfff
9997 22:15:04.574095 INFO: [NOCDAPC] D3_APC_0: 0x0
9998 22:15:04.577797 INFO: [NOCDAPC] D3_APC_1: 0xfff
9999 22:15:04.581086 INFO: [NOCDAPC] D4_APC_0: 0x0
10000 22:15:04.584216 INFO: [NOCDAPC] D4_APC_1: 0xfff
10001 22:15:04.587364 INFO: [NOCDAPC] D5_APC_0: 0x0
10002 22:15:04.587870 INFO: [NOCDAPC] D5_APC_1: 0xfff
10003 22:15:04.590773 INFO: [NOCDAPC] D6_APC_0: 0x0
10004 22:15:04.594001 INFO: [NOCDAPC] D6_APC_1: 0xfff
10005 22:15:04.597177 INFO: [NOCDAPC] D7_APC_0: 0x0
10006 22:15:04.600892 INFO: [NOCDAPC] D7_APC_1: 0xfff
10007 22:15:04.603960 INFO: [NOCDAPC] D8_APC_0: 0x0
10008 22:15:04.607353 INFO: [NOCDAPC] D8_APC_1: 0xfff
10009 22:15:04.610388 INFO: [NOCDAPC] D9_APC_0: 0x0
10010 22:15:04.613787 INFO: [NOCDAPC] D9_APC_1: 0xfff
10011 22:15:04.617086 INFO: [NOCDAPC] D10_APC_0: 0x0
10012 22:15:04.620006 INFO: [NOCDAPC] D10_APC_1: 0xfff
10013 22:15:04.623708 INFO: [NOCDAPC] D11_APC_0: 0x0
10014 22:15:04.627337 INFO: [NOCDAPC] D11_APC_1: 0xfff
10015 22:15:04.630021 INFO: [NOCDAPC] D12_APC_0: 0x0
10016 22:15:04.630490 INFO: [NOCDAPC] D12_APC_1: 0xfff
10017 22:15:04.633251 INFO: [NOCDAPC] D13_APC_0: 0x0
10018 22:15:04.636681 INFO: [NOCDAPC] D13_APC_1: 0xfff
10019 22:15:04.640057 INFO: [NOCDAPC] D14_APC_0: 0x0
10020 22:15:04.643399 INFO: [NOCDAPC] D14_APC_1: 0xfff
10021 22:15:04.646900 INFO: [NOCDAPC] D15_APC_0: 0x0
10022 22:15:04.650198 INFO: [NOCDAPC] D15_APC_1: 0xfff
10023 22:15:04.653544 INFO: [NOCDAPC] APC_CON: 0x4
10024 22:15:04.656786 INFO: [APUAPC] set_apusys_apc done
10025 22:15:04.659968 INFO: [DEVAPC] devapc_init done
10026 22:15:04.663548 INFO: GICv3 without legacy support detected.
10027 22:15:04.666494 INFO: ARM GICv3 driver initialized in EL3
10028 22:15:04.669741 INFO: Maximum SPI INTID supported: 639
10029 22:15:04.676749 INFO: BL31: Initializing runtime services
10030 22:15:04.679840 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10031 22:15:04.682970 INFO: SPM: enable CPC mode
10032 22:15:04.689828 INFO: mcdi ready for mcusys-off-idle and system suspend
10033 22:15:04.692868 INFO: BL31: Preparing for EL3 exit to normal world
10034 22:15:04.695864 INFO: Entry point address = 0x80000000
10035 22:15:04.699635 INFO: SPSR = 0x8
10036 22:15:04.705270
10037 22:15:04.705735
10038 22:15:04.706098
10039 22:15:04.708255 Starting depthcharge on Spherion...
10040 22:15:04.708723
10041 22:15:04.709086 Wipe memory regions:
10042 22:15:04.709442
10043 22:15:04.711736 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10044 22:15:04.712245 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10045 22:15:04.712661 Setting prompt string to ['asurada:']
10046 22:15:04.713054 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10047 22:15:04.713703 [0x00000040000000, 0x00000054600000)
10048 22:15:04.834516
10049 22:15:04.835162 [0x00000054660000, 0x00000080000000)
10050 22:15:05.094423
10051 22:15:05.094959 [0x000000821a7280, 0x000000ffe64000)
10052 22:15:05.838490
10053 22:15:05.838637 [0x00000100000000, 0x00000240000000)
10054 22:15:07.726399
10055 22:15:07.729539 Initializing XHCI USB controller at 0x11200000.
10056 22:15:08.767209
10057 22:15:08.770366 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10058 22:15:08.770458
10059 22:15:08.770522
10060 22:15:08.770581
10061 22:15:08.770886 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10063 22:15:08.871203 asurada: tftpboot 192.168.201.1 10597227/tftp-deploy-x8cwzr0n/kernel/image.itb 10597227/tftp-deploy-x8cwzr0n/kernel/cmdline
10064 22:15:08.871350 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10065 22:15:08.871437 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10066 22:15:08.875575 tftpboot 192.168.201.1 10597227/tftp-deploy-x8cwzr0n/kernel/image.itp-deploy-x8cwzr0n/kernel/cmdline
10067 22:15:08.875663
10068 22:15:08.875728 Waiting for link
10069 22:15:09.036303
10070 22:15:09.036440 R8152: Initializing
10071 22:15:09.036510
10072 22:15:09.039500 Version 6 (ocp_data = 5c30)
10073 22:15:09.039582
10074 22:15:09.042890 R8152: Done initializing
10075 22:15:09.042972
10076 22:15:09.043037 Adding net device
10077 22:15:11.072917
10078 22:15:11.073479 done.
10079 22:15:11.073845
10080 22:15:11.074184 MAC: 00:24:32:30:78:ff
10081 22:15:11.074509
10082 22:15:11.076729 Sending DHCP discover... done.
10083 22:15:11.077293
10084 22:15:11.079442 Waiting for reply... done.
10085 22:15:11.080020
10086 22:15:11.082748 Sending DHCP request... done.
10087 22:15:11.083274
10088 22:15:11.088578 Waiting for reply... done.
10089 22:15:11.089047
10090 22:15:11.089412 My ip is 192.168.201.21
10091 22:15:11.089757
10092 22:15:11.091396 The DHCP server ip is 192.168.201.1
10093 22:15:11.091870
10094 22:15:11.098332 TFTP server IP predefined by user: 192.168.201.1
10095 22:15:11.098804
10096 22:15:11.105019 Bootfile predefined by user: 10597227/tftp-deploy-x8cwzr0n/kernel/image.itb
10097 22:15:11.105577
10098 22:15:11.108267 Sending tftp read request... done.
10099 22:15:11.108737
10100 22:15:11.114423 Waiting for the transfer...
10101 22:15:11.115031
10102 22:15:11.725622 00000000 ################################################################
10103 22:15:11.725894
10104 22:15:12.311988 00080000 ################################################################
10105 22:15:12.312134
10106 22:15:12.888034 00100000 ################################################################
10107 22:15:12.888166
10108 22:15:13.565157 00180000 ################################################################
10109 22:15:13.565728
10110 22:15:14.233649 00200000 ################################################################
10111 22:15:14.234098
10112 22:15:14.832569 00280000 ################################################################
10113 22:15:14.832703
10114 22:15:15.491616 00300000 ################################################################
10115 22:15:15.492190
10116 22:15:16.216329 00380000 ################################################################
10117 22:15:16.216933
10118 22:15:16.956246 00400000 ################################################################
10119 22:15:16.956862
10120 22:15:17.675947 00480000 ################################################################
10121 22:15:17.676514
10122 22:15:18.400414 00500000 ################################################################
10123 22:15:18.400997
10124 22:15:19.126894 00580000 ################################################################
10125 22:15:19.127470
10126 22:15:19.858500 00600000 ################################################################
10127 22:15:19.859125
10128 22:15:20.588610 00680000 ################################################################
10129 22:15:20.589191
10130 22:15:21.314263 00700000 ################################################################
10131 22:15:21.314901
10132 22:15:22.026473 00780000 ################################################################
10133 22:15:22.027142
10134 22:15:22.740000 00800000 ################################################################
10135 22:15:22.740562
10136 22:15:23.468560 00880000 ################################################################
10137 22:15:23.469146
10138 22:15:24.199793 00900000 ################################################################
10139 22:15:24.200394
10140 22:15:24.932084 00980000 ################################################################
10141 22:15:24.932701
10142 22:15:25.650953 00a00000 ################################################################
10143 22:15:25.651548
10144 22:15:26.356196 00a80000 ################################################################
10145 22:15:26.356688
10146 22:15:27.026524 00b00000 ################################################################
10147 22:15:27.027128
10148 22:15:27.744369 00b80000 ################################################################
10149 22:15:27.744951
10150 22:15:28.453236 00c00000 ################################################################
10151 22:15:28.453830
10152 22:15:29.183326 00c80000 ################################################################
10153 22:15:29.183885
10154 22:15:29.902929 00d00000 ################################################################
10155 22:15:29.903494
10156 22:15:30.631366 00d80000 ################################################################
10157 22:15:30.631920
10158 22:15:31.342724 00e00000 ################################################################
10159 22:15:31.343335
10160 22:15:32.061324 00e80000 ################################################################
10161 22:15:32.061916
10162 22:15:32.799945 00f00000 ################################################################
10163 22:15:32.800528
10164 22:15:33.511182 00f80000 ################################################################
10165 22:15:33.511813
10166 22:15:34.237918 01000000 ################################################################
10167 22:15:34.238593
10168 22:15:34.967294 01080000 ################################################################
10169 22:15:34.967863
10170 22:15:35.700754 01100000 ################################################################
10171 22:15:35.701324
10172 22:15:36.432924 01180000 ################################################################
10173 22:15:36.433531
10174 22:15:37.157447 01200000 ################################################################
10175 22:15:37.158122
10176 22:15:37.885540 01280000 ################################################################
10177 22:15:37.886192
10178 22:15:38.558395 01300000 ################################################################
10179 22:15:38.558977
10180 22:15:39.242935 01380000 ################################################################
10181 22:15:39.243526
10182 22:15:39.947243 01400000 ################################################################
10183 22:15:39.947744
10184 22:15:40.560087 01480000 ################################################################
10185 22:15:40.560674
10186 22:15:41.151846 01500000 ################################################################
10187 22:15:41.151982
10188 22:15:41.806028 01580000 ################################################################
10189 22:15:41.806576
10190 22:15:42.515153 01600000 ################################################################
10191 22:15:42.515717
10192 22:15:43.246795 01680000 ################################################################
10193 22:15:43.247385
10194 22:15:43.957245 01700000 ################################################################
10195 22:15:43.957810
10196 22:15:44.690461 01780000 ################################################################
10197 22:15:44.691112
10198 22:15:45.418496 01800000 ################################################################
10199 22:15:45.419080
10200 22:15:46.111363 01880000 ################################################################
10201 22:15:46.111869
10202 22:15:46.794334 01900000 ################################################################
10203 22:15:46.794879
10204 22:15:47.432464 01980000 ################################################################
10205 22:15:47.432855
10206 22:15:48.165841 01a00000 ################################################################
10207 22:15:48.166397
10208 22:15:48.904004 01a80000 ################################################################
10209 22:15:48.904518
10210 22:15:49.635994 01b00000 ################################################################
10211 22:15:49.636617
10212 22:15:50.364229 01b80000 ################################################################
10213 22:15:50.364782
10214 22:15:51.051886 01c00000 ################################################################
10215 22:15:51.052453
10216 22:15:51.729513 01c80000 ################################################################
10217 22:15:51.730061
10218 22:15:52.439474 01d00000 ################################################################
10219 22:15:52.440049
10220 22:15:53.143719 01d80000 ################################################################
10221 22:15:53.144276
10222 22:15:53.847554 01e00000 ################################################################
10223 22:15:53.848047
10224 22:15:54.535778 01e80000 ################################################################
10225 22:15:54.536360
10226 22:15:55.225653 01f00000 ################################################################
10227 22:15:55.226169
10228 22:15:55.894985 01f80000 ################################################################
10229 22:15:55.895565
10230 22:15:56.600045 02000000 ################################################################
10231 22:15:56.600614
10232 22:15:57.310075 02080000 ################################################################
10233 22:15:57.310671
10234 22:15:58.010982 02100000 ################################################################
10235 22:15:58.011591
10236 22:15:58.703177 02180000 ################################################################
10237 22:15:58.703748
10238 22:15:59.398469 02200000 ################################################################
10239 22:15:59.399067
10240 22:16:00.118051 02280000 ################################################################
10241 22:16:00.118612
10242 22:16:00.831329 02300000 ################################################################
10243 22:16:00.831901
10244 22:16:01.545259 02380000 ################################################################
10245 22:16:01.545841
10246 22:16:02.242245 02400000 ################################################################
10247 22:16:02.242880
10248 22:16:02.960907 02480000 ################################################################
10249 22:16:02.961912
10250 22:16:03.649575 02500000 ################################################################
10251 22:16:03.650099
10252 22:16:04.358424 02580000 ################################################################
10253 22:16:04.359045
10254 22:16:05.081237 02600000 ################################################################
10255 22:16:05.081826
10256 22:16:05.806662 02680000 ################################################################
10257 22:16:05.807270
10258 22:16:06.475502 02700000 ################################################################
10259 22:16:06.476095
10260 22:16:07.199258 02780000 ################################################################
10261 22:16:07.199857
10262 22:16:07.863324 02800000 ################################################################
10263 22:16:07.863457
10264 22:16:08.453312 02880000 ################################################################
10265 22:16:08.453462
10266 22:16:09.023196 02900000 ################################################################
10267 22:16:09.023338
10268 22:16:09.610146 02980000 ################################################################
10269 22:16:09.610297
10270 22:16:10.195547 02a00000 ################################################################
10271 22:16:10.195697
10272 22:16:10.782352 02a80000 ################################################################
10273 22:16:10.782505
10274 22:16:11.383631 02b00000 ################################################################
10275 22:16:11.383778
10276 22:16:11.977872 02b80000 ################################################################
10277 22:16:11.978016
10278 22:16:12.552827 02c00000 ################################################################
10279 22:16:12.552978
10280 22:16:13.119597 02c80000 ################################################################
10281 22:16:13.119748
10282 22:16:13.696725 02d00000 ################################################################
10283 22:16:13.696861
10284 22:16:14.262170 02d80000 ################################################################
10285 22:16:14.262316
10286 22:16:14.826328 02e00000 ################################################################
10287 22:16:14.826475
10288 22:16:15.415273 02e80000 ################################################################
10289 22:16:15.415424
10290 22:16:15.997021 02f00000 ################################################################
10291 22:16:15.997166
10292 22:16:16.581435 02f80000 ################################################################
10293 22:16:16.581588
10294 22:16:17.171546 03000000 ################################################################
10295 22:16:17.171700
10296 22:16:17.765600 03080000 ################################################################
10297 22:16:17.765746
10298 22:16:18.329373 03100000 ################################################################
10299 22:16:18.329531
10300 22:16:18.934707 03180000 ################################################################
10301 22:16:18.934902
10302 22:16:19.536615 03200000 ################################################################
10303 22:16:19.536764
10304 22:16:20.233100 03280000 ################################################################
10305 22:16:20.233255
10306 22:16:20.840060 03300000 ################################################################
10307 22:16:20.840220
10308 22:16:21.432859 03380000 ################################################################
10309 22:16:21.433016
10310 22:16:22.026701 03400000 ################################################################
10311 22:16:22.026940
10312 22:16:22.625335 03480000 ################################################################
10313 22:16:22.625474
10314 22:16:23.228447 03500000 ################################################################
10315 22:16:23.228590
10316 22:16:23.827992 03580000 ################################################################
10317 22:16:23.828148
10318 22:16:24.431040 03600000 ################################################################
10319 22:16:24.431189
10320 22:16:24.836670 03680000 ############################################ done.
10321 22:16:24.836812
10322 22:16:24.839968 The bootfile was 57503610 bytes long.
10323 22:16:24.840053
10324 22:16:24.843192 Sending tftp read request... done.
10325 22:16:24.843275
10326 22:16:24.843371 Waiting for the transfer...
10327 22:16:24.843503
10328 22:16:24.846437 00000000 # done.
10329 22:16:24.846522
10330 22:16:24.853149 Command line loaded dynamically from TFTP file: 10597227/tftp-deploy-x8cwzr0n/kernel/cmdline
10331 22:16:24.853232
10332 22:16:24.866138 The command line is: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10333 22:16:24.866223
10334 22:16:24.866288 Loading FIT.
10335 22:16:24.866346
10336 22:16:24.869376 Image ramdisk-1 has 47372346 bytes.
10337 22:16:24.869458
10338 22:16:24.872922 Image fdt-1 has 46924 bytes.
10339 22:16:24.873003
10340 22:16:24.876103 Image kernel-1 has 10082307 bytes.
10341 22:16:24.876185
10342 22:16:24.885935 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10343 22:16:24.886018
10344 22:16:24.902201 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10345 22:16:24.902288
10346 22:16:24.905780 Choosing best match conf-1 for compat google,spherion-rev2.
10347 22:16:24.911263
10348 22:16:24.915549 Connected to device vid:did:rid of 1ae0:0028:00
10349 22:16:24.923105
10350 22:16:24.926062 tpm_get_response: command 0x17b, return code 0x0
10351 22:16:24.926144
10352 22:16:24.929200 ec_init: CrosEC protocol v3 supported (256, 248)
10353 22:16:24.933214
10354 22:16:24.936898 tpm_cleanup: add release locality here.
10355 22:16:24.936980
10356 22:16:24.937044 Shutting down all USB controllers.
10357 22:16:24.940174
10358 22:16:24.940255 Removing current net device
10359 22:16:24.940318
10360 22:16:24.946627 Exiting depthcharge with code 4 at timestamp: 109557338
10361 22:16:24.946709
10362 22:16:24.950456 LZMA decompressing kernel-1 to 0x821a6718
10363 22:16:24.950538
10364 22:16:24.953601 LZMA decompressing kernel-1 to 0x40000000
10365 22:16:26.220537
10366 22:16:26.220685 jumping to kernel
10367 22:16:26.221122 end: 2.2.4 bootloader-commands (duration 00:01:22) [common]
10368 22:16:26.221219 start: 2.2.5 auto-login-action (timeout 00:03:04) [common]
10369 22:16:26.221294 Setting prompt string to ['Linux version [0-9]']
10370 22:16:26.221363 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10371 22:16:26.221429 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10372 22:16:26.303320
10373 22:16:26.306684 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10374 22:16:26.309884 start: 2.2.5.1 login-action (timeout 00:03:04) [common]
10375 22:16:26.309974 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10376 22:16:26.310061 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10377 22:16:26.310135 Using line separator: #'\n'#
10378 22:16:26.310194 No login prompt set.
10379 22:16:26.310253 Parsing kernel messages
10380 22:16:26.310307 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10381 22:16:26.310420 [login-action] Waiting for messages, (timeout 00:03:04)
10382 22:16:26.329508 [ 0.000000] Linux version 6.1.31 (KernelCI@build-j1612341-arm64-gcc-10-defconfig-arm64-chromebook-n674v) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Mon Jun 5 22:04:07 UTC 2023
10383 22:16:26.333325 [ 0.000000] random: crng init done
10384 22:16:26.339810 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10385 22:16:26.343013 [ 0.000000] efi: UEFI not found.
10386 22:16:26.349229 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10387 22:16:26.355861 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10388 22:16:26.365779 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10389 22:16:26.375869 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10390 22:16:26.382782 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10391 22:16:26.389194 [ 0.000000] printk: bootconsole [mtk8250] enabled
10392 22:16:26.395511 [ 0.000000] NUMA: No NUMA configuration found
10393 22:16:26.402102 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10394 22:16:26.405172 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcda00-0x23efcffff]
10395 22:16:26.408529 [ 0.000000] Zone ranges:
10396 22:16:26.415284 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10397 22:16:26.418645 [ 0.000000] DMA32 empty
10398 22:16:26.424726 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10399 22:16:26.428285 [ 0.000000] Movable zone start for each node
10400 22:16:26.431482 [ 0.000000] Early memory node ranges
10401 22:16:26.438264 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10402 22:16:26.444891 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10403 22:16:26.451251 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10404 22:16:26.458764 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10405 22:16:26.464579 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10406 22:16:26.471061 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10407 22:16:26.527422 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10408 22:16:26.533692 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10409 22:16:26.540266 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10410 22:16:26.544130 [ 0.000000] psci: probing for conduit method from DT.
10411 22:16:26.550545 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10412 22:16:26.553922 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10413 22:16:26.560195 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10414 22:16:26.563327 [ 0.000000] psci: SMC Calling Convention v1.2
10415 22:16:26.570374 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10416 22:16:26.573438 [ 0.000000] Detected VIPT I-cache on CPU0
10417 22:16:26.580156 [ 0.000000] CPU features: detected: GIC system register CPU interface
10418 22:16:26.586576 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10419 22:16:26.593053 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10420 22:16:26.599711 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10421 22:16:26.609636 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10422 22:16:26.616466 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10423 22:16:26.619345 [ 0.000000] alternatives: applying boot alternatives
10424 22:16:26.626373 [ 0.000000] Fallback order for Node 0: 0
10425 22:16:26.632628 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10426 22:16:26.636475 [ 0.000000] Policy zone: Normal
10427 22:16:26.649203 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10428 22:16:26.659241 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10429 22:16:26.669436 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10430 22:16:26.679371 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10431 22:16:26.686368 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10432 22:16:26.689113 <6>[ 0.000000] software IO TLB: area num 8.
10433 22:16:26.745897 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10434 22:16:26.895057 <6>[ 0.000000] Memory: 7926676K/8385536K available (17984K kernel code, 4098K rwdata, 14068K rodata, 8384K init, 615K bss, 426092K reserved, 32768K cma-reserved)
10435 22:16:26.901665 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10436 22:16:26.908294 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10437 22:16:26.911613 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10438 22:16:26.918726 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10439 22:16:26.924803 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10440 22:16:26.928188 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10441 22:16:26.937817 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10442 22:16:26.944898 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10443 22:16:26.951640 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10444 22:16:26.957749 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10445 22:16:26.961552 <6>[ 0.000000] GICv3: 608 SPIs implemented
10446 22:16:26.964637 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10447 22:16:26.971245 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10448 22:16:26.974208 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10449 22:16:26.980862 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10450 22:16:26.994488 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10451 22:16:27.007123 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10452 22:16:27.013595 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10453 22:16:27.021889 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10454 22:16:27.035131 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10455 22:16:27.041249 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10456 22:16:27.048065 <6>[ 0.009174] Console: colour dummy device 80x25
10457 22:16:27.058103 <6>[ 0.013900] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10458 22:16:27.064811 <6>[ 0.024406] pid_max: default: 32768 minimum: 301
10459 22:16:27.068248 <6>[ 0.029279] LSM: Security Framework initializing
10460 22:16:27.075151 <6>[ 0.034217] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10461 22:16:27.084956 <6>[ 0.042032] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10462 22:16:27.094522 <6>[ 0.051507] cblist_init_generic: Setting adjustable number of callback queues.
10463 22:16:27.101267 <6>[ 0.058962] cblist_init_generic: Setting shift to 3 and lim to 1.
10464 22:16:27.104437 <6>[ 0.065330] cblist_init_generic: Setting shift to 3 and lim to 1.
10465 22:16:27.110907 <6>[ 0.071738] rcu: Hierarchical SRCU implementation.
10466 22:16:27.117571 <6>[ 0.076753] rcu: Max phase no-delay instances is 1000.
10467 22:16:27.124184 <6>[ 0.083811] EFI services will not be available.
10468 22:16:27.127507 <6>[ 0.088790] smp: Bringing up secondary CPUs ...
10469 22:16:27.135300 <6>[ 0.093843] Detected VIPT I-cache on CPU1
10470 22:16:27.141711 <6>[ 0.093915] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10471 22:16:27.148227 <6>[ 0.093946] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10472 22:16:27.151649 <6>[ 0.094279] Detected VIPT I-cache on CPU2
10473 22:16:27.161466 <6>[ 0.094327] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10474 22:16:27.168051 <6>[ 0.094341] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10475 22:16:27.171718 <6>[ 0.094600] Detected VIPT I-cache on CPU3
10476 22:16:27.178348 <6>[ 0.094646] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10477 22:16:27.184343 <6>[ 0.094660] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10478 22:16:27.191423 <6>[ 0.094964] CPU features: detected: Spectre-v4
10479 22:16:27.194712 <6>[ 0.094971] CPU features: detected: Spectre-BHB
10480 22:16:27.197665 <6>[ 0.094976] Detected PIPT I-cache on CPU4
10481 22:16:27.204666 <6>[ 0.095034] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10482 22:16:27.211098 <6>[ 0.095051] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10483 22:16:27.217266 <6>[ 0.095344] Detected PIPT I-cache on CPU5
10484 22:16:27.224365 <6>[ 0.095409] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10485 22:16:27.230999 <6>[ 0.095425] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10486 22:16:27.233764 <6>[ 0.095711] Detected PIPT I-cache on CPU6
10487 22:16:27.243793 <6>[ 0.095776] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10488 22:16:27.250776 <6>[ 0.095793] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10489 22:16:27.253563 <6>[ 0.096089] Detected PIPT I-cache on CPU7
10490 22:16:27.260630 <6>[ 0.096155] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10491 22:16:27.266616 <6>[ 0.096171] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10492 22:16:27.270005 <6>[ 0.096218] smp: Brought up 1 node, 8 CPUs
10493 22:16:27.276485 <6>[ 0.237395] SMP: Total of 8 processors activated.
10494 22:16:27.283135 <6>[ 0.242316] CPU features: detected: 32-bit EL0 Support
10495 22:16:27.289936 <6>[ 0.247712] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10496 22:16:27.296457 <6>[ 0.256567] CPU features: detected: Common not Private translations
10497 22:16:27.303472 <6>[ 0.263043] CPU features: detected: CRC32 instructions
10498 22:16:27.309516 <6>[ 0.268394] CPU features: detected: RCpc load-acquire (LDAPR)
10499 22:16:27.312714 <6>[ 0.274354] CPU features: detected: LSE atomic instructions
10500 22:16:27.319652 <6>[ 0.280135] CPU features: detected: Privileged Access Never
10501 22:16:27.326606 <6>[ 0.285915] CPU features: detected: RAS Extension Support
10502 22:16:27.332787 <6>[ 0.291523] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10503 22:16:27.336082 <6>[ 0.298744] CPU: All CPU(s) started at EL2
10504 22:16:27.342369 <6>[ 0.303060] alternatives: applying system-wide alternatives
10505 22:16:27.352704 <6>[ 0.313718] devtmpfs: initialized
10506 22:16:27.368306 <6>[ 0.322687] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10507 22:16:27.374775 <6>[ 0.332650] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10508 22:16:27.381333 <6>[ 0.340870] pinctrl core: initialized pinctrl subsystem
10509 22:16:27.384908 <6>[ 0.347506] DMI not present or invalid.
10510 22:16:27.391280 <6>[ 0.351915] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10511 22:16:27.401170 <6>[ 0.358786] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10512 22:16:27.408037 <6>[ 0.366366] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10513 22:16:27.418007 <6>[ 0.374589] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10514 22:16:27.420917 <6>[ 0.382832] audit: initializing netlink subsys (disabled)
10515 22:16:27.431179 <5>[ 0.388529] audit: type=2000 audit(0.276:1): state=initialized audit_enabled=0 res=1
10516 22:16:27.437812 <6>[ 0.389227] thermal_sys: Registered thermal governor 'step_wise'
10517 22:16:27.444010 <6>[ 0.396496] thermal_sys: Registered thermal governor 'power_allocator'
10518 22:16:27.447274 <6>[ 0.402749] cpuidle: using governor menu
10519 22:16:27.454245 <6>[ 0.413709] NET: Registered PF_QIPCRTR protocol family
10520 22:16:27.460468 <6>[ 0.419182] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10521 22:16:27.467190 <6>[ 0.426283] ASID allocator initialised with 32768 entries
10522 22:16:27.470788 <6>[ 0.432848] Serial: AMBA PL011 UART driver
10523 22:16:27.480566 <4>[ 0.441470] Trying to register duplicate clock ID: 134
10524 22:16:27.536472 <6>[ 0.500784] KASLR enabled
10525 22:16:27.550998 <6>[ 0.508527] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10526 22:16:27.557328 <6>[ 0.515541] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10527 22:16:27.564187 <6>[ 0.522029] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10528 22:16:27.570441 <6>[ 0.529034] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10529 22:16:27.576964 <6>[ 0.535520] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10530 22:16:27.584611 <6>[ 0.542524] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10531 22:16:27.590294 <6>[ 0.549011] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10532 22:16:27.597025 <6>[ 0.556015] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10533 22:16:27.600086 <6>[ 0.563503] ACPI: Interpreter disabled.
10534 22:16:27.609411 <6>[ 0.569901] iommu: Default domain type: Translated
10535 22:16:27.615517 <6>[ 0.575062] iommu: DMA domain TLB invalidation policy: strict mode
10536 22:16:27.619005 <5>[ 0.581715] SCSI subsystem initialized
10537 22:16:27.625547 <6>[ 0.585956] usbcore: registered new interface driver usbfs
10538 22:16:27.632427 <6>[ 0.591686] usbcore: registered new interface driver hub
10539 22:16:27.635299 <6>[ 0.597239] usbcore: registered new device driver usb
10540 22:16:27.642239 <6>[ 0.603341] pps_core: LinuxPPS API ver. 1 registered
10541 22:16:27.652159 <6>[ 0.608532] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10542 22:16:27.655312 <6>[ 0.617878] PTP clock support registered
10543 22:16:27.658573 <6>[ 0.622116] EDAC MC: Ver: 3.0.0
10544 22:16:27.666636 <6>[ 0.627284] FPGA manager framework
10545 22:16:27.672743 <6>[ 0.630962] Advanced Linux Sound Architecture Driver Initialized.
10546 22:16:27.676346 <6>[ 0.637734] vgaarb: loaded
10547 22:16:27.682679 <6>[ 0.640886] clocksource: Switched to clocksource arch_sys_counter
10548 22:16:27.686218 <5>[ 0.647339] VFS: Disk quotas dquot_6.6.0
10549 22:16:27.692850 <6>[ 0.651523] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10550 22:16:27.695918 <6>[ 0.658714] pnp: PnP ACPI: disabled
10551 22:16:27.704561 <6>[ 0.665395] NET: Registered PF_INET protocol family
10552 22:16:27.713972 <6>[ 0.670979] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10553 22:16:27.725460 <6>[ 0.683280] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10554 22:16:27.735627 <6>[ 0.692096] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10555 22:16:27.742022 <6>[ 0.700066] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10556 22:16:27.751830 <6>[ 0.708768] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10557 22:16:27.758363 <6>[ 0.718506] TCP: Hash tables configured (established 65536 bind 65536)
10558 22:16:27.764755 <6>[ 0.725369] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10559 22:16:27.774955 <6>[ 0.732567] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10560 22:16:27.781666 <6>[ 0.740266] NET: Registered PF_UNIX/PF_LOCAL protocol family
10561 22:16:27.788234 <6>[ 0.746428] RPC: Registered named UNIX socket transport module.
10562 22:16:27.791363 <6>[ 0.752584] RPC: Registered udp transport module.
10563 22:16:27.798075 <6>[ 0.757518] RPC: Registered tcp transport module.
10564 22:16:27.804724 <6>[ 0.762448] RPC: Registered tcp NFSv4.1 backchannel transport module.
10565 22:16:27.807680 <6>[ 0.769115] PCI: CLS 0 bytes, default 64
10566 22:16:27.811080 <6>[ 0.773456] Unpacking initramfs...
10567 22:16:27.831965 <6>[ 0.789673] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10568 22:16:27.841816 <6>[ 0.798350] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10569 22:16:27.845340 <6>[ 0.807233] kvm [1]: IPA Size Limit: 40 bits
10570 22:16:27.851520 <6>[ 0.811769] kvm [1]: GICv3: no GICV resource entry
10571 22:16:27.855464 <6>[ 0.816792] kvm [1]: disabling GICv2 emulation
10572 22:16:27.861454 <6>[ 0.821483] kvm [1]: GIC system register CPU interface enabled
10573 22:16:27.864902 <6>[ 0.827638] kvm [1]: vgic interrupt IRQ18
10574 22:16:27.871430 <6>[ 0.832001] kvm [1]: VHE mode initialized successfully
10575 22:16:27.878078 <5>[ 0.838368] Initialise system trusted keyrings
10576 22:16:27.884554 <6>[ 0.843137] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10577 22:16:27.892646 <6>[ 0.853420] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10578 22:16:27.899395 <5>[ 0.859791] NFS: Registering the id_resolver key type
10579 22:16:27.902498 <5>[ 0.865090] Key type id_resolver registered
10580 22:16:27.908916 <5>[ 0.869505] Key type id_legacy registered
10581 22:16:27.915639 <6>[ 0.873804] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10582 22:16:27.921792 <6>[ 0.880727] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10583 22:16:27.929052 <6>[ 0.888428] 9p: Installing v9fs 9p2000 file system support
10584 22:16:27.965627 <5>[ 0.926312] Key type asymmetric registered
10585 22:16:27.968519 <5>[ 0.930641] Asymmetric key parser 'x509' registered
10586 22:16:27.978497 <6>[ 0.935773] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10587 22:16:27.982137 <6>[ 0.943386] io scheduler mq-deadline registered
10588 22:16:27.985009 <6>[ 0.948165] io scheduler kyber registered
10589 22:16:28.004096 <6>[ 0.964946] EINJ: ACPI disabled.
10590 22:16:28.036165 <4>[ 0.990383] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10591 22:16:28.045394 <4>[ 1.001033] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10592 22:16:28.060730 <6>[ 1.021763] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10593 22:16:28.069227 <6>[ 1.029745] printk: console [ttyS0] disabled
10594 22:16:28.096937 <6>[ 1.054393] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10595 22:16:28.103174 <6>[ 1.063857] printk: console [ttyS0] enabled
10596 22:16:28.106474 <6>[ 1.063857] printk: console [ttyS0] enabled
10597 22:16:28.113248 <6>[ 1.072750] printk: bootconsole [mtk8250] disabled
10598 22:16:28.116977 <6>[ 1.072750] printk: bootconsole [mtk8250] disabled
10599 22:16:28.123086 <6>[ 1.083784] SuperH (H)SCI(F) driver initialized
10600 22:16:28.126055 <6>[ 1.089061] msm_serial: driver initialized
10601 22:16:28.140272 <6>[ 1.097933] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10602 22:16:28.149993 <6>[ 1.106479] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10603 22:16:28.156501 <6>[ 1.115024] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10604 22:16:28.166495 <6>[ 1.123653] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10605 22:16:28.176599 <6>[ 1.132358] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10606 22:16:28.183110 <6>[ 1.141078] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10607 22:16:28.193038 <6>[ 1.149619] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10608 22:16:28.199393 <6>[ 1.158419] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10609 22:16:28.209401 <6>[ 1.166961] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10610 22:16:28.221101 <6>[ 1.182430] loop: module loaded
10611 22:16:28.227862 <6>[ 1.188387] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10612 22:16:28.251419 <4>[ 1.211879] mtk-pmic-keys: Failed to locate of_node [id: -1]
10613 22:16:28.258040 <6>[ 1.218824] megasas: 07.719.03.00-rc1
10614 22:16:28.267662 <6>[ 1.228550] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10615 22:16:28.279171 <6>[ 1.240272] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10616 22:16:28.296461 <6>[ 1.256900] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10617 22:16:28.356556 <6>[ 1.310794] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10618 22:16:29.838584 <6>[ 2.799593] Freeing initrd memory: 46256K
10619 22:16:29.848614 <6>[ 2.809852] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10620 22:16:29.859563 <6>[ 2.821027] tun: Universal TUN/TAP device driver, 1.6
10621 22:16:29.862950 <6>[ 2.827092] thunder_xcv, ver 1.0
10622 22:16:29.866360 <6>[ 2.830600] thunder_bgx, ver 1.0
10623 22:16:29.869726 <6>[ 2.834094] nicpf, ver 1.0
10624 22:16:29.880311 <6>[ 2.838120] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10625 22:16:29.883698 <6>[ 2.845597] hns3: Copyright (c) 2017 Huawei Corporation.
10626 22:16:29.890261 <6>[ 2.851185] hclge is initializing
10627 22:16:29.893426 <6>[ 2.854772] e1000: Intel(R) PRO/1000 Network Driver
10628 22:16:29.900047 <6>[ 2.859901] e1000: Copyright (c) 1999-2006 Intel Corporation.
10629 22:16:29.903430 <6>[ 2.865917] e1000e: Intel(R) PRO/1000 Network Driver
10630 22:16:29.909739 <6>[ 2.871134] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10631 22:16:29.917022 <6>[ 2.877318] igb: Intel(R) Gigabit Ethernet Network Driver
10632 22:16:29.923064 <6>[ 2.882967] igb: Copyright (c) 2007-2014 Intel Corporation.
10633 22:16:29.929733 <6>[ 2.888804] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10634 22:16:29.936604 <6>[ 2.895322] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10635 22:16:29.939594 <6>[ 2.901784] sky2: driver version 1.30
10636 22:16:29.946163 <6>[ 2.906774] VFIO - User Level meta-driver version: 0.3
10637 22:16:29.953700 <6>[ 2.915008] usbcore: registered new interface driver usb-storage
10638 22:16:29.960555 <6>[ 2.921455] usbcore: registered new device driver onboard-usb-hub
10639 22:16:29.969131 <6>[ 2.930581] mt6397-rtc mt6359-rtc: registered as rtc0
10640 22:16:29.979240 <6>[ 2.936047] mt6397-rtc mt6359-rtc: setting system clock to 2023-06-05T22:16:34 UTC (1686003394)
10641 22:16:29.982452 <6>[ 2.945615] i2c_dev: i2c /dev entries driver
10642 22:16:29.999475 <6>[ 2.957447] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10643 22:16:30.006662 <6>[ 2.967680] sdhci: Secure Digital Host Controller Interface driver
10644 22:16:30.013188 <6>[ 2.974118] sdhci: Copyright(c) Pierre Ossman
10645 22:16:30.019679 <6>[ 2.979510] Synopsys Designware Multimedia Card Interface Driver
10646 22:16:30.023463 <6>[ 2.986139] mmc0: CQHCI version 5.10
10647 22:16:30.029909 <6>[ 2.986656] sdhci-pltfm: SDHCI platform and OF driver helper
10648 22:16:30.037152 <6>[ 2.997995] ledtrig-cpu: registered to indicate activity on CPUs
10649 22:16:30.047509 <6>[ 3.005319] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10650 22:16:30.053962 <6>[ 3.012710] usbcore: registered new interface driver usbhid
10651 22:16:30.057410 <6>[ 3.018543] usbhid: USB HID core driver
10652 22:16:30.063583 <6>[ 3.022796] spi_master spi0: will run message pump with realtime priority
10653 22:16:30.112007 <6>[ 3.066525] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10654 22:16:30.130731 <6>[ 3.081610] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10655 22:16:30.134528 <6>[ 3.095183] mmc0: Command Queue Engine enabled
10656 22:16:30.141017 <6>[ 3.096522] cros-ec-spi spi0.0: Chrome EC device registered
10657 22:16:30.147348 <6>[ 3.099927] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10658 22:16:30.150809 <6>[ 3.113059] mmcblk0: mmc0:0001 DA4128 116 GiB
10659 22:16:30.165322 <6>[ 3.122981] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10660 22:16:30.171684 <6>[ 3.125784] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10661 22:16:30.178388 <6>[ 3.134471] NET: Registered PF_PACKET protocol family
10662 22:16:30.181445 <6>[ 3.139663] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10663 22:16:30.188356 <6>[ 3.143653] 9pnet: Installing 9P2000 support
10664 22:16:30.191513 <6>[ 3.149427] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10665 22:16:30.198168 <5>[ 3.153320] Key type dns_resolver registered
10666 22:16:30.204861 <6>[ 3.159127] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10667 22:16:30.208189 <6>[ 3.163626] registered taskstats version 1
10668 22:16:30.211517 <5>[ 3.173923] Loading compiled-in X.509 certificates
10669 22:16:30.247082 <4>[ 3.201366] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10670 22:16:30.256467 <4>[ 3.212061] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10671 22:16:30.266736 <3>[ 3.224809] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10672 22:16:30.279407 <6>[ 3.240246] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10673 22:16:30.285637 <6>[ 3.247138] xhci-mtk 11200000.usb: xHCI Host Controller
10674 22:16:30.292600 <6>[ 3.252648] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10675 22:16:30.302462 <6>[ 3.260500] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10676 22:16:30.309088 <6>[ 3.269930] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10677 22:16:30.315517 <6>[ 3.275998] xhci-mtk 11200000.usb: xHCI Host Controller
10678 22:16:30.322139 <6>[ 3.281481] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10679 22:16:30.328984 <6>[ 3.289132] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10680 22:16:30.335661 <6>[ 3.296838] hub 1-0:1.0: USB hub found
10681 22:16:30.338991 <6>[ 3.300860] hub 1-0:1.0: 1 port detected
10682 22:16:30.348630 <6>[ 3.305197] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10683 22:16:30.352074 <6>[ 3.313928] hub 2-0:1.0: USB hub found
10684 22:16:30.355235 <6>[ 3.317966] hub 2-0:1.0: 1 port detected
10685 22:16:30.363872 <6>[ 3.325241] mtk-msdc 11f70000.mmc: Got CD GPIO
10686 22:16:30.382170 <6>[ 3.339914] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10687 22:16:30.388634 <6>[ 3.348103] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10688 22:16:30.398244 <4>[ 3.356097] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10689 22:16:30.408658 <6>[ 3.365812] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10690 22:16:30.414973 <6>[ 3.373905] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10691 22:16:30.425412 <6>[ 3.381966] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10692 22:16:30.431800 <6>[ 3.389888] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10693 22:16:30.438162 <6>[ 3.397747] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10694 22:16:30.448041 <6>[ 3.405571] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10695 22:16:30.458639 <6>[ 3.416234] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10696 22:16:30.468068 <6>[ 3.424597] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10697 22:16:30.474844 <6>[ 3.432995] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10698 22:16:30.484858 <6>[ 3.441342] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10699 22:16:30.491718 <6>[ 3.449715] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10700 22:16:30.500974 <6>[ 3.458060] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10701 22:16:30.507675 <6>[ 3.466429] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10702 22:16:30.517915 <6>[ 3.474774] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10703 22:16:30.524550 <6>[ 3.483140] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10704 22:16:30.534030 <6>[ 3.491485] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10705 22:16:30.541392 <6>[ 3.499837] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10706 22:16:30.551001 <6>[ 3.508181] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10707 22:16:30.557756 <6>[ 3.516525] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10708 22:16:30.567082 <6>[ 3.524868] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10709 22:16:30.574154 <6>[ 3.533211] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10710 22:16:30.580670 <6>[ 3.542114] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10711 22:16:30.588072 <6>[ 3.549599] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10712 22:16:30.595537 <6>[ 3.556730] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10713 22:16:30.605987 <6>[ 3.563897] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10714 22:16:30.612336 <6>[ 3.571231] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10715 22:16:30.622518 <6>[ 3.578088] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10716 22:16:30.628834 <6>[ 3.587229] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10717 22:16:30.639132 <6>[ 3.596389] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10718 22:16:30.649399 <6>[ 3.605703] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10719 22:16:30.658665 <6>[ 3.615178] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10720 22:16:30.669057 <6>[ 3.624653] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10721 22:16:30.678284 <6>[ 3.633780] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10722 22:16:30.685077 <6>[ 3.643255] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10723 22:16:30.694867 <6>[ 3.652382] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10724 22:16:30.704927 <6>[ 3.661683] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10725 22:16:30.714510 <6>[ 3.671848] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10726 22:16:30.725308 <6>[ 3.683295] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10727 22:16:30.751175 <6>[ 3.709159] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10728 22:16:30.778058 <6>[ 3.739606] hub 2-1:1.0: USB hub found
10729 22:16:30.781826 <6>[ 3.744018] hub 2-1:1.0: 3 ports detected
10730 22:16:30.903017 <6>[ 3.861186] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10731 22:16:31.057624 <6>[ 4.018874] hub 1-1:1.0: USB hub found
10732 22:16:31.060751 <6>[ 4.023354] hub 1-1:1.0: 4 ports detected
10733 22:16:31.139248 <6>[ 4.097303] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10734 22:16:31.383062 <6>[ 4.341142] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10735 22:16:31.516469 <6>[ 4.477526] hub 1-1.4:1.0: USB hub found
10736 22:16:31.519814 <6>[ 4.482181] hub 1-1.4:1.0: 2 ports detected
10737 22:16:31.819086 <6>[ 4.777159] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10738 22:16:32.010957 <6>[ 4.969119] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10739 22:16:43.019644 <6>[ 15.985720] ALSA device list:
10740 22:16:43.025948 <6>[ 15.988975] No soundcards found.
10741 22:16:43.038972 <6>[ 16.001337] Freeing unused kernel memory: 8384K
10742 22:16:43.041630 <6>[ 16.006244] Run /init as init process
10743 22:16:43.071979 <6>[ 16.034865] NET: Registered PF_INET6 protocol family
10744 22:16:43.078851 <6>[ 16.041010] Segment Routing with IPv6
10745 22:16:43.081836 <6>[ 16.044954] In-situ OAM (IOAM) with IPv6
10746 22:16:43.116318 <30>[ 16.059465] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10747 22:16:43.119925 <30>[ 16.083284] systemd[1]: Detected architecture arm64.
10748 22:16:43.120019
10749 22:16:43.126115 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10750 22:16:43.126201
10751 22:16:43.142695 <30>[ 16.105266] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10752 22:16:43.294147 <30>[ 16.253343] systemd[1]: Queued start job for default target Graphical Interface.
10753 22:16:43.343955 <30>[ 16.306415] systemd[1]: Created slice system-getty.slice.
10754 22:16:43.350193 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10755 22:16:43.367534 <30>[ 16.329796] systemd[1]: Created slice system-modprobe.slice.
10756 22:16:43.373529 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10757 22:16:43.391517 <30>[ 16.354298] systemd[1]: Created slice system-serial\x2dgetty.slice.
10758 22:16:43.401439 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10759 22:16:43.415147 <30>[ 16.377661] systemd[1]: Created slice User and Session Slice.
10760 22:16:43.422122 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10761 22:16:43.442370 <30>[ 16.401775] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10762 22:16:43.452182 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10763 22:16:43.470044 <30>[ 16.429332] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10764 22:16:43.476225 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10765 22:16:43.496989 <30>[ 16.453264] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10766 22:16:43.503531 <30>[ 16.465338] systemd[1]: Reached target Local Encrypted Volumes.
10767 22:16:43.510084 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10768 22:16:43.526628 <30>[ 16.489529] systemd[1]: Reached target Paths.
10769 22:16:43.529852 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10770 22:16:43.546659 <30>[ 16.509209] systemd[1]: Reached target Remote File Systems.
10771 22:16:43.553005 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10772 22:16:43.566622 <30>[ 16.529182] systemd[1]: Reached target Slices.
10773 22:16:43.569698 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10774 22:16:43.586512 <30>[ 16.549214] systemd[1]: Reached target Swap.
10775 22:16:43.589949 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10776 22:16:43.610146 <30>[ 16.569546] systemd[1]: Listening on initctl Compatibility Named Pipe.
10777 22:16:43.616334 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10778 22:16:43.623245 <30>[ 16.584249] systemd[1]: Listening on Journal Audit Socket.
10779 22:16:43.629826 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10780 22:16:43.642961 <30>[ 16.605455] systemd[1]: Listening on Journal Socket (/dev/log).
10781 22:16:43.648934 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10782 22:16:43.666548 <30>[ 16.629484] systemd[1]: Listening on Journal Socket.
10783 22:16:43.673102 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10784 22:16:43.690016 <30>[ 16.649510] systemd[1]: Listening on Network Service Netlink Socket.
10785 22:16:43.696337 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10786 22:16:43.711365 <30>[ 16.673930] systemd[1]: Listening on udev Control Socket.
10787 22:16:43.717850 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10788 22:16:43.735494 <30>[ 16.697864] systemd[1]: Listening on udev Kernel Socket.
10789 22:16:43.741626 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10790 22:16:43.774737 <30>[ 16.737277] systemd[1]: Mounting Huge Pages File System...
10791 22:16:43.781043 Mounting [0;1;39mHuge Pages File System[0m...
10792 22:16:43.796786 <30>[ 16.759400] systemd[1]: Mounting POSIX Message Queue File System...
10793 22:16:43.803127 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10794 22:16:43.820351 <30>[ 16.783260] systemd[1]: Mounting Kernel Debug File System...
10795 22:16:43.826755 Mounting [0;1;39mKernel Debug File System[0m...
10796 22:16:43.845764 <30>[ 16.805425] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10797 22:16:43.857047 <30>[ 16.816520] systemd[1]: Starting Create list of static device nodes for the current kernel...
10798 22:16:43.863671 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10799 22:16:43.880492 <30>[ 16.843373] systemd[1]: Starting Load Kernel Module configfs...
10800 22:16:43.887290 Starting [0;1;39mLoad Kernel Module configfs[0m...
10801 22:16:43.908582 <30>[ 16.871511] systemd[1]: Starting Load Kernel Module drm...
10802 22:16:43.915169 Starting [0;1;39mLoad Kernel Module drm[0m...
10803 22:16:43.934193 <30>[ 16.893471] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10804 22:16:43.944140 <30>[ 16.907152] systemd[1]: Starting Journal Service...
10805 22:16:43.947642 Starting [0;1;39mJournal Service[0m...
10806 22:16:43.964826 <30>[ 16.927844] systemd[1]: Starting Load Kernel Modules...
10807 22:16:43.971613 Starting [0;1;39mLoad Kernel Modules[0m...
10808 22:16:43.992345 <30>[ 16.951819] systemd[1]: Starting Remount Root and Kernel File Systems...
10809 22:16:43.999094 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10810 22:16:44.012886 <30>[ 16.975779] systemd[1]: Starting Coldplug All udev Devices...
10811 22:16:44.019420 Starting [0;1;39mColdplug All udev Devices[0m...
10812 22:16:44.037277 <30>[ 17.000030] systemd[1]: Mounted Huge Pages File System.
10813 22:16:44.043829 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10814 22:16:44.063174 <30>[ 17.025631] systemd[1]: Started Journal Service.
10815 22:16:44.069484 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10816 22:16:44.084324 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10817 22:16:44.099223 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10818 22:16:44.119047 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10819 22:16:44.140034 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10820 22:16:44.156444 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10821 22:16:44.176138 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10822 22:16:44.195498 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10823 22:16:44.210454 See 'systemctl status systemd-remount-fs.service' for details.
10824 22:16:44.255000 Mounting [0;1;39mKernel Configuration File System[0m...
10825 22:16:44.272940 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10826 22:16:44.290184 <46>[ 17.249700] systemd-journald[174]: Received client request to flush runtime journal.
10827 22:16:44.299000 Starting [0;1;39mLoad/Save Random Seed[0m...
10828 22:16:44.320950 Starting [0;1;39mApply Kernel Variables[0m...
10829 22:16:44.337482 Starting [0;1;39mCreate System Users[0m...
10830 22:16:44.356263 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10831 22:16:44.374836 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10832 22:16:44.387459 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10833 22:16:44.403800 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10834 22:16:44.423666 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10835 22:16:44.442968 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10836 22:16:44.482774 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10837 22:16:44.505270 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10838 22:16:44.523092 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10839 22:16:44.538400 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10840 22:16:44.582750 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10841 22:16:44.606310 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10842 22:16:44.623618 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10843 22:16:44.643821 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10844 22:16:44.664506 Starting [0;1;39mNetwork Service[0m...
10845 22:16:44.685119 Starting [0;1;39mNetwork Time Synchronization[0m...
10846 22:16:44.703003 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10847 22:16:44.739054 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10848 22:16:44.762673 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10849 22:16:44.824226 Starting [0;1;39mNetwork Name Resolution[0m...
10850 22:16:44.841428 <6>[ 17.800954] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10851 22:16:44.847960 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10852 22:16:44.851153 <6>[ 17.815241] remoteproc remoteproc0: scp is available
10853 22:16:44.861867 <4>[ 17.821602] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10854 22:16:44.871030 <6>[ 17.833942] remoteproc remoteproc0: powering up scp
10855 22:16:44.877644 <3>[ 17.837203] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10856 22:16:44.887902 <4>[ 17.839229] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10857 22:16:44.897830 <3>[ 17.847449] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10858 22:16:44.904200 <3>[ 17.857171] remoteproc remoteproc0: request_firmware failed: -2
10859 22:16:44.910599 <3>[ 17.871626] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10860 22:16:44.917434 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10861 22:16:44.924380 <3>[ 17.885256] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10862 22:16:44.933938 <3>[ 17.893561] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10863 22:16:44.940612 <6>[ 17.901481] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10864 22:16:44.950607 <3>[ 17.901729] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10865 22:16:44.957001 <6>[ 17.909293] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10866 22:16:44.967463 <3>[ 17.917299] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10867 22:16:44.973455 <6>[ 17.926046] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10868 22:16:44.983299 <3>[ 17.934105] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10869 22:16:44.990130 <6>[ 17.943822] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10870 22:16:44.999766 <3>[ 17.951039] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10871 22:16:45.002950 <6>[ 17.960754] mc: Linux media interface: v0.10
10872 22:16:45.009986 <6>[ 17.963889] usbcore: registered new interface driver r8152
10873 22:16:45.016403 <3>[ 17.966717] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10874 22:16:45.026171 <3>[ 17.985079] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10875 22:16:45.032948 <3>[ 17.985092] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10876 22:16:45.042831 <4>[ 17.991013] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10877 22:16:45.046332 <4>[ 17.991013] Fallback method does not support PEC.
10878 22:16:45.052458 <6>[ 17.995562] videodev: Linux video capture interface: v2.00
10879 22:16:45.059479 <4>[ 18.018221] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10880 22:16:45.072609 [[0;32m OK [0m] Created slic<3>[ 18.029394] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10881 22:16:45.078970 e [0;1;39msyste<4>[ 18.029605] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10882 22:16:45.089200 m-systemd\x2dbac<3>[ 18.039164] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10883 22:16:45.096401 <6>[ 18.041343] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10884 22:16:45.106305 klight.slice[0m<3>[ 18.064161] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10885 22:16:45.106399 .
10886 22:16:45.116106 <4>[ 18.070204] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10887 22:16:45.122446 <3>[ 18.073643] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10888 22:16:45.132930 <3>[ 18.073658] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10889 22:16:45.139834 <3>[ 18.073926] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10890 22:16:45.145745 <6>[ 18.074356] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10891 22:16:45.152278 <6>[ 18.074366] pci_bus 0000:00: root bus resource [bus 00-ff]
10892 22:16:45.159034 <6>[ 18.074375] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10893 22:16:45.168946 <6>[ 18.074380] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10894 22:16:45.175540 <6>[ 18.074417] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10895 22:16:45.182490 <6>[ 18.074438] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10896 22:16:45.188943 <6>[ 18.074528] pci 0000:00:00.0: supports D1 D2
10897 22:16:45.195170 <6>[ 18.074534] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10898 22:16:45.202130 <4>[ 18.083458] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10899 22:16:45.211644 <6>[ 18.095717] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10900 22:16:45.221722 <6>[ 18.107976] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10901 22:16:45.228768 <3>[ 18.114513] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10902 22:16:45.235079 <6>[ 18.115238] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10903 22:16:45.245111 <6>[ 18.115276] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10904 22:16:45.251348 <6>[ 18.115561] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10905 22:16:45.258059 <6>[ 18.115580] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10906 22:16:45.261173 <6>[ 18.115742] pci 0000:01:00.0: supports D1 D2
10907 22:16:45.271115 <6>[ 18.115747] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10908 22:16:45.277838 <6>[ 18.125308] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10909 22:16:45.284555 <6>[ 18.136972] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10910 22:16:45.294771 <6>[ 18.226632] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10911 22:16:45.304462 <6>[ 18.231088] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10912 22:16:45.307708 <6>[ 18.241020] r8152 2-1.3:1.0 eth0: v1.12.13
10913 22:16:45.314400 <6>[ 18.246884] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10914 22:16:45.321066 <6>[ 18.247680] usbcore: registered new interface driver cdc_ether
10915 22:16:45.327737 <6>[ 18.254274] usbcore: registered new interface driver r8153_ecm
10916 22:16:45.334310 <6>[ 18.263084] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10917 22:16:45.340637 <6>[ 18.276575] Bluetooth: Core ver 2.22
10918 22:16:45.347560 <6>[ 18.283535] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10919 22:16:45.353927 <6>[ 18.284140] r8152 2-1.3:1.0 enx0024323078ff: renamed from eth0
10920 22:16:45.360533 <6>[ 18.289724] NET: Registered PF_BLUETOOTH protocol family
10921 22:16:45.367100 <6>[ 18.295742] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10922 22:16:45.374264 <6>[ 18.303724] Bluetooth: HCI device and connection manager initialized
10923 22:16:45.381291 <6>[ 18.304790] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10924 22:16:45.392299 <6>[ 18.306428] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10925 22:16:45.399489 <6>[ 18.306596] usbcore: registered new interface driver uvcvideo
10926 22:16:45.406653 <6>[ 18.307568] pci 0000:00:00.0: PCI bridge to [bus 01]
10927 22:16:45.409119 <6>[ 18.315576] Bluetooth: HCI socket layer initialized
10928 22:16:45.416004 <6>[ 18.316397] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10929 22:16:45.422172 <6>[ 18.320053] remoteproc remoteproc0: powering up scp
10930 22:16:45.432242 <4>[ 18.320100] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10931 22:16:45.436104 <3>[ 18.320108] remoteproc remoteproc0: request_firmware failed: -2
10932 22:16:45.445873 <3>[ 18.320111] fops_vcodec_open(),166: [MTK_V4L2][ERROR] vpu_load_firmware failed!
10933 22:16:45.452125 <6>[ 18.321647] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10934 22:16:45.459319 <6>[ 18.327208] Bluetooth: L2CAP socket layer initialized
10935 22:16:45.465614 <6>[ 18.335361] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10936 22:16:45.469126 <6>[ 18.341816] Bluetooth: SCO socket layer initialized
10937 22:16:45.475558 <6>[ 18.349749] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10938 22:16:45.485404 <3>[ 18.358018] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10939 22:16:45.491965 <3>[ 18.358862] power_supply sbs-5-000b: driver failed to report `temp' property: -6
10940 22:16:45.502023 <3>[ 18.363348] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10941 22:16:45.511658 <3>[ 18.364057] power_supply sbs-5-000b: driver failed to report `capacity_error_margin' property: -6
10942 22:16:45.515180 <6>[ 18.367717] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10943 22:16:45.525295 <3>[ 18.400540] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10944 22:16:45.531887 <6>[ 18.406376] usbcore: registered new interface driver btusb
10945 22:16:45.541449 <4>[ 18.426714] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10946 22:16:45.547961 <5>[ 18.429762] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10947 22:16:45.558375 <5>[ 18.443634] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10948 22:16:45.561578 <3>[ 18.444240] Bluetooth: hci0: Failed to load firmware file (-2)
10949 22:16:45.568840 <3>[ 18.444246] Bluetooth: hci0: Failed to set up firmware (-2)
10950 22:16:45.578531 <4>[ 18.444253] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10951 22:16:45.591538 [[0;32m OK [0m] Reached target [0;1;39mSyst<4>[ 18.550961] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10952 22:16:45.601458 em Time Set[0m.<3>[ 18.552782] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10953 22:16:45.608057 <6>[ 18.560873] cfg80211: failed to load regulatory.db
10954 22:16:45.608145
10955 22:16:45.624971 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10956 22:16:45.633766 <3>[ 18.592282] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10957 22:16:45.652587 <6>[ 18.611478] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10958 22:16:45.655523 <6>[ 18.618990] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10959 22:16:45.665508 <3>[ 18.621810] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10960 22:16:45.682618 Starting [0;1;39mLoad/Save Screen …o<6>[ 18.645704] mt7921e 0000:01:00.0: ASIC revision: 79610010
10961 22:16:45.686175 f leds:white:kbd_backlight[0m...
10962 22:16:45.696521 <3>[ 18.656123] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10963 22:16:45.703227 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10964 22:16:45.723218 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10965 22:16:45.790223 <4>[ 18.745955] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10966 22:16:45.917080 [[0;32m OK [<4>[ 18.873540] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10967 22:16:45.923756 0m] Reached target [0;1;39mBluetooth[0m.
10968 22:16:45.938841 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10969 22:16:45.957586 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10970 22:16:45.970246 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10971 22:16:45.990000 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10972 22:16:46.009629 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10973 22:16:46.022611 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10974 22:16:46.039443 <4>[ 18.995701] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10975 22:16:46.049355 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10976 22:16:46.062938 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10977 22:16:46.078393 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10978 22:16:46.097988 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10979 22:16:46.139524 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10980 22:16:46.160886 <4>[ 19.117443] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10981 22:16:46.172380 Starting [0;1;39mUser Login Management[0m...
10982 22:16:46.188875 Starting [0;1;39mPermit User Sessions[0m...
10983 22:16:46.207143 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10984 22:16:46.222583 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10985 22:16:46.239696 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10986 22:16:46.285519 [[0;32m OK [0m] Started [0;<4>[ 19.240580] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10987 22:16:46.285614 1;39mGetty on tty1[0m.
10988 22:16:46.312335 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10989 22:16:46.330633 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10990 22:16:46.351953 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10991 22:16:46.371319 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10992 22:16:46.390610 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10993 22:16:46.411156 <4>[ 19.367783] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10994 22:16:46.450756 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10995 22:16:46.473886 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10996 22:16:46.488575
10997 22:16:46.488658
10998 22:16:46.492384 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10999 22:16:46.492465
11000 22:16:46.495216 debian-bullseye-arm64 login: root (automatic login)
11001 22:16:46.495318
11002 22:16:46.495382
11003 22:16:46.511727 Linux debian-bullseye-arm64 6.1.31 #1 SMP PREEMPT Mon Jun 5 22:04:07 UTC 2023 aarch64
11004 22:16:46.511810
11005 22:16:46.518657 The programs included with the Debian GNU/Linux system are free software;
11006 22:16:46.535162 the exact distribution terms for each progr<4>[ 19.489572] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11007 22:16:46.535245 am are described in the
11008 22:16:46.538398 individual files in /usr/share/doc/*/copyright.
11009 22:16:46.541494
11010 22:16:46.544960 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11011 22:16:46.548066 permitted by applicable law.
11012 22:16:46.548441 Matched prompt #10: / #
11014 22:16:46.548643 Setting prompt string to ['/ #']
11015 22:16:46.548733 end: 2.2.5.1 login-action (duration 00:00:20) [common]
11017 22:16:46.548918 end: 2.2.5 auto-login-action (duration 00:00:20) [common]
11018 22:16:46.549002 start: 2.2.6 expect-shell-connection (timeout 00:02:43) [common]
11019 22:16:46.549069 Setting prompt string to ['/ #']
11020 22:16:46.549128 Forcing a shell prompt, looking for ['/ #']
11022 22:16:46.599353 / #
11023 22:16:46.599468 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11024 22:16:46.599627 Waiting using forced prompt support (timeout 00:02:30)
11025 22:16:46.604105
11026 22:16:46.604369 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11027 22:16:46.604459 start: 2.2.7 export-device-env (timeout 00:02:43) [common]
11028 22:16:46.604550 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11029 22:16:46.604659 end: 2.2 depthcharge-retry (duration 00:02:17) [common]
11030 22:16:46.604738 end: 2 depthcharge-action (duration 00:02:17) [common]
11031 22:16:46.604820 start: 3 lava-test-retry (timeout 00:05:00) [common]
11032 22:16:46.604919 start: 3.1 lava-test-shell (timeout 00:05:00) [common]
11033 22:16:46.605000 Using namespace: common
11035 22:16:46.705325 / # #
11036 22:16:46.705460 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:05:00)
11037 22:16:46.705666 <4>[ 19.611376] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11038 22:16:46.710705 #
11039 22:16:46.710979 Using /lava-10597227
11041 22:16:46.811301 / # export SHELL=/bin/sh
11042 22:16:46.811486 <4>[ 19.731029] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11043 22:16:46.816501 export SHELL=/bin/sh
11045 22:16:46.917021 / # . /lava-10597227/environment
11046 22:16:46.917269 . /lava-10597227/environment<4>[ 19.851145] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11047 22:16:46.921947
11049 22:16:47.022475 / # /lava-10597227/bin/lava-test-runner /lava-10597227/0
11050 22:16:47.022586 Test shell timeout: 10s (minimum of the action and connection timeout)
11051 22:16:47.023058 /lava-10597227/bin/lava-test-runner /lava-10597227/0<6>[ 19.955410] IPv6: ADDRCONF(NETDEV_CHANGE): enx0024323078ff: link becomes ready
11052 22:16:47.023134 <6>[ 19.964474] r8152 2-1.3:1.0 enx0024323078ff: carrier on
11053 22:16:47.023198 <3>[ 19.969847] mt7921e 0000:01:00.0: hardware init failed
11054 22:16:47.027623
11055 22:16:47.071038 + export TESTRUN_ID=0_cros-ec
11056 22:16:47.071124 + c<8>[ 20.014749] <LAVA_SIGNAL_STARTRUN 0_cros-ec 10597227_1.5.2.3.1>
11057 22:16:47.071191 d /lava-10597227/0/tests/0_cros-ec
11058 22:16:47.071251 + cat uuid
11059 22:16:47.071308 + UUID=10597227_1.5.2.3.1
11060 22:16:47.071363 + set +x
11061 22:16:47.071418 + python3 -m cros.runners.lava_runner -v
11062 22:16:47.071648 Received signal: <STARTRUN> 0_cros-ec 10597227_1.5.2.3.1
11063 22:16:47.071714 Starting test lava.0_cros-ec (10597227_1.5.2.3.1)
11064 22:16:47.071791 Skipping test definition patterns.
11065 22:16:47.760538 test_cros_ec_accel_iio_abi (cros.tests.cros_ec_accel.TestCrosECAccel)
11066 22:16:47.767285 Checks the cros-ec accelerometer IIO ABI. ... skipped 'No cros-ec-accel found'
11067 22:16:47.770303
11068 22:16:47.773777 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_accel_iio_abi RESULT=skip
11070 22:16:47.776843 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_accel_iio_abi RESULT=skip>
11071 22:16:47.783638 test_cros_ec_accel_iio_data_is_valid (cros.tests.cros_ec_accel.TestCrosECAccel)
11072 22:16:47.790042 Validates accelerometer data by computing the magnitude. If the ... skipped 'No accelerometer found'
11073 22:16:47.790125
11074 22:16:47.799973 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_accel_iio_data_is_valid RESULT=skip>
11075 22:16:47.800223 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_accel_iio_data_is_valid RESULT=skip
11077 22:16:47.807266 test_cros_ec_gyro_iio_abi (cros.tests.cros_ec_gyro.TestCrosECGyro)
11078 22:16:47.810397 Received signal: <ENDRUN> 0_cros-ec 10597227_1.5.2.3.1
11079 22:16:47.810488 Ending use of test pattern.
11080 22:16:47.810550 Ending test lava.0_cros-ec (10597227_1.5.2.3.1), duration 0.74
11082 22:16:47.813243 Checks t<8>[ 20.773425] <LAVA_SIGNAL_ENDRUN 0_cros-ec 10597227_1.5.2.3.1>
11083 22:16:47.817654 he cros-ec gyroscope IIO ABI. ... skipped 'No cros-ec-gyro found'
11084 22:16:47.817749
11085 22:16:47.823368 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_gyro_iio_abi RESULT=skip>
11086 22:16:47.823618 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_gyro_iio_abi RESULT=skip
11088 22:16:47.830364 test_cros_ec_abi (cros.tests.cros_ec_mcu.TestCrosECMCU)
11089 22:16:47.836623 Checks the standard ABI for the main Embedded Controller. ... ok
11090 22:16:47.836704
11091 22:16:47.839891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_abi RESULT=pass>
11092 22:16:47.840140 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_abi RESULT=pass
11094 22:16:47.846554 test_cros_ec_chardev (cros.tests.cros_ec_mcu.TestCrosECMCU)
11095 22:16:47.853123 Checks the main Embedded controller character device. ... ok
11096 22:16:47.853205
11097 22:16:47.856390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_chardev RESULT=pass>
11098 22:16:47.856655 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_chardev RESULT=pass
11100 22:16:47.863262 test_cros_ec_hello (cros.tests.cros_ec_mcu.TestCrosECMCU)
11101 22:16:47.869679 Checks basic comunication with the main Embedded controller. ... ok
11102 22:16:47.869761
11103 22:16:47.876373 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_hello RESULT=pass>
11104 22:16:47.876623 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_hello RESULT=pass
11106 22:16:47.879628 test_cros_fp_abi (cros.tests.cros_ec_mcu.TestCrosECMCU)
11107 22:16:47.889042 Checks the standard ABI for the Fingerprint EC. ... skipped 'MCU cros_fp not supported'
11108 22:16:47.889124
11109 22:16:47.892844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_abi RESULT=skip>
11110 22:16:47.893093 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_abi RESULT=skip
11112 22:16:47.898942 test_cros_fp_hello (cros.tests.cros_ec_mcu.TestCrosECMCU)
11113 22:16:47.905618 Checks basic comunication with the fingerprint controller. ... skipped 'MCU cros_fp not found'
11114 22:16:47.905699
11115 22:16:47.912420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_hello RESULT=skip>
11116 22:16:47.912669 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_hello RESULT=skip
11118 22:16:47.918761 test_cros_fp_reboot (cros.tests.cros_ec_mcu.TestCrosECMCU)
11119 22:16:47.925562 Test reboot command on Fingerprint MCU. ... skipped 'MCU cros_fp not found'
11120 22:16:47.925644
11121 22:16:47.932368 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_reboot RESULT=skip>
11122 22:16:47.932618 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_reboot RESULT=skip
11124 22:16:47.936424 test_cros_pd_abi (cros.tests.cros_ec_mcu.TestCrosECMCU)
11125 22:16:47.945511 Checks the standard ABI for the Power Delivery EC. ... skipped 'MCU cros_pd not supported'
11126 22:16:47.945592
11127 22:16:47.949253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_pd_abi RESULT=skip>
11128 22:16:47.949502 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_pd_abi RESULT=skip
11130 22:16:47.955119 test_cros_pd_hello (cros.tests.cros_ec_mcu.TestCrosECMCU)
11131 22:16:47.965127 Checks basic comunication with the power delivery controller. ... skipped 'MCU cros_pd not found'
11132 22:16:47.965208
11133 22:16:47.968334 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_pd_hello RESULT=skip>
11134 22:16:47.968585 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_pd_hello RESULT=skip
11136 22:16:47.975199 test_cros_tp_abi (cros.tests.cros_ec_mcu.TestCrosECMCU)
11137 22:16:47.981549 Checks the standard ABI for the Touchpad EC. ... skipped 'MCU cros_tp not supported'
11138 22:16:47.981630
11139 22:16:47.988499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_tp_abi RESULT=skip>
11140 22:16:47.988750 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_tp_abi RESULT=skip
11142 22:16:47.991932 test_cros_tp_hello (cros.tests.cros_ec_mcu.TestCrosECMCU)
11143 22:16:48.001486 Checks basic comunication with the touchpad controller. ... skipped 'MCU cros_tp not found'
11144 22:16:48.001568
11145 22:16:48.007968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_tp_hello RESULT=skip>
11146 22:16:48.008217 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_tp_hello RESULT=skip
11148 22:16:48.014485 test_cros_ec_pwm_backlight (cros.tests.cros_ec_pwm.TestCrosECPWM)
11149 22:16:48.021572 Check that the backlight is connected to a pwm of the EC and that ... skipped 'No backlight pwm found'
11150 22:16:48.021654
11151 22:16:48.027621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_pwm_backlight RESULT=skip>
11152 22:16:48.027871 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_pwm_backlight RESULT=skip
11154 22:16:48.034507 test_cros_ec_battery_abi (cros.tests.cros_ec_power.TestCrosECPower)
11155 22:16:48.041395 Check the cros battery ABI. ... skipped 'No BAT found'
11156 22:16:48.041474
11157 22:16:48.047663 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_battery_abi RESULT=skip>
11158 22:16:48.047938 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_battery_abi RESULT=skip
11160 22:16:48.054129 test_cros_ec_usbpd_charger_abi (cros.tests.cros_ec_power.TestCrosECPower)
11161 22:16:48.061095 Check the cros USBPD charger ABI. ... skipped 'No CROS_USBPD_CHARGER found'
11162 22:16:48.061174
11163 22:16:48.067282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_usbpd_charger_abi RESULT=skip>
11164 22:16:48.067531 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_usbpd_charger_abi RESULT=skip
11166 22:16:48.070686 test_cros_ec_rtc_abi (cros.tests.cros_ec_rtc.TestCrosECRTC)
11167 22:16:48.077579 Check the cros RTC ABI. ... skipped 'EC_FEATURE_RTC not supported, skipping'
11168 22:16:48.077659
11169 22:16:48.083959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_rtc_abi RESULT=skip>
11170 22:16:48.084209 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_rtc_abi RESULT=skip
11172 22:16:48.090511 test_cros_ec_extcon_usbc_abi (cros.tests.cros_ec_extcon.TestCrosECextcon)
11173 22:16:48.097238 Checks the cros-ec extcon ABI. ... skipped 'No extcon device found'
11174 22:16:48.097317
11175 22:16:48.103723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_extcon_usbc_abi RESULT=skip>
11176 22:16:48.103802
11177 22:16:48.104032 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_extcon_usbc_abi RESULT=skip
11179 22:16:48.110450 ----------------------------------------------------------------------
11180 22:16:48.113726 Ran 18 tests in 0.011s
11181 22:16:48.113805
11182 22:16:48.113865 OK (skipped=15)
11183 22:16:48.116933 + set +x
11184 22:16:48.117013 <LAVA_TEST_RUNNER EXIT>
11185 22:16:48.117246 ok: lava_test_shell seems to have completed
11186 22:16:48.117411 test_cros_ec_abi: pass
test_cros_ec_accel_iio_abi: skip
test_cros_ec_accel_iio_data_is_valid: skip
test_cros_ec_battery_abi: skip
test_cros_ec_chardev: pass
test_cros_ec_extcon_usbc_abi: skip
test_cros_ec_gyro_iio_abi: skip
test_cros_ec_hello: pass
test_cros_ec_pwm_backlight: skip
test_cros_ec_rtc_abi: skip
test_cros_ec_usbpd_charger_abi: skip
test_cros_fp_abi: skip
test_cros_fp_hello: skip
test_cros_fp_reboot: skip
test_cros_pd_abi: skip
test_cros_pd_hello: skip
test_cros_tp_abi: skip
test_cros_tp_hello: skip
11187 22:16:48.117501 end: 3.1 lava-test-shell (duration 00:00:02) [common]
11188 22:16:48.117590 end: 3 lava-test-retry (duration 00:00:02) [common]
11189 22:16:48.117719 start: 4 finalize (timeout 00:07:21) [common]
11190 22:16:48.117813 start: 4.1 power-off (timeout 00:00:30) [common]
11191 22:16:48.117961 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=off'
11192 22:16:48.193081 >> Command sent successfully.
11193 22:16:48.195415 Returned 0 in 0 seconds
11194 22:16:48.295802 end: 4.1 power-off (duration 00:00:00) [common]
11196 22:16:48.296138 start: 4.2 read-feedback (timeout 00:07:21) [common]
11197 22:16:48.296431 Listened to connection for namespace 'common' for up to 1s
11198 22:16:49.297353 Finalising connection for namespace 'common'
11199 22:16:49.297532 Disconnecting from shell: Finalise
11200 22:16:49.297612 / #
11201 22:16:49.397948 end: 4.2 read-feedback (duration 00:00:01) [common]
11202 22:16:49.398126 end: 4 finalize (duration 00:00:01) [common]
11203 22:16:49.398238 Cleaning after the job
11204 22:16:49.398330 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10597227/tftp-deploy-x8cwzr0n/ramdisk
11205 22:16:49.403386 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10597227/tftp-deploy-x8cwzr0n/kernel
11206 22:16:49.409166 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10597227/tftp-deploy-x8cwzr0n/dtb
11207 22:16:49.409318 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10597227/tftp-deploy-x8cwzr0n/modules
11208 22:16:49.414581 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/10597227
11209 22:16:49.510213 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/10597227
11210 22:16:49.510388 Job finished correctly