Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 32
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 26
1 22:13:44.551664 lava-dispatcher, installed at version: 2023.05.1
2 22:13:44.551866 start: 0 validate
3 22:13:44.552003 Start time: 2023-06-05 22:13:44.551995+00:00 (UTC)
4 22:13:44.552183 Using caching service: 'http://localhost/cache/?uri=%s'
5 22:13:44.552400 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-igt%2F20230527.0%2Farm64%2Frootfs.cpio.gz exists
6 22:13:44.860967 Using caching service: 'http://localhost/cache/?uri=%s'
7 22:13:44.861768 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1314-g1ab0ac1d7e2e3%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 22:13:44.867194 Using caching service: 'http://localhost/cache/?uri=%s'
9 22:13:44.868021 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1314-g1ab0ac1d7e2e3%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 22:13:45.182623 Using caching service: 'http://localhost/cache/?uri=%s'
11 22:13:45.182818 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1314-g1ab0ac1d7e2e3%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 22:13:45.496762 validate duration: 0.94
14 22:13:45.497024 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 22:13:45.497120 start: 1.1 download-retry (timeout 00:10:00) [common]
16 22:13:45.497208 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 22:13:45.497328 Not decompressing ramdisk as can be used compressed.
18 22:13:45.497410 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-igt/20230527.0/arm64/rootfs.cpio.gz
19 22:13:45.497473 saving as /var/lib/lava/dispatcher/tmp/10597245/tftp-deploy-igpa52ow/ramdisk/rootfs.cpio.gz
20 22:13:45.497533 total size: 43394293 (41MB)
21 22:13:45.498690 progress 0% (0MB)
22 22:13:45.510359 progress 5% (2MB)
23 22:13:45.521362 progress 10% (4MB)
24 22:13:45.532448 progress 15% (6MB)
25 22:13:45.543598 progress 20% (8MB)
26 22:13:45.554981 progress 25% (10MB)
27 22:13:45.566768 progress 30% (12MB)
28 22:13:45.578256 progress 35% (14MB)
29 22:13:45.589636 progress 40% (16MB)
30 22:13:45.600983 progress 45% (18MB)
31 22:13:45.613144 progress 50% (20MB)
32 22:13:45.624799 progress 55% (22MB)
33 22:13:45.635995 progress 60% (24MB)
34 22:13:45.647285 progress 65% (26MB)
35 22:13:45.658700 progress 70% (29MB)
36 22:13:45.669845 progress 75% (31MB)
37 22:13:45.681023 progress 80% (33MB)
38 22:13:45.692161 progress 85% (35MB)
39 22:13:45.703309 progress 90% (37MB)
40 22:13:45.714746 progress 95% (39MB)
41 22:13:45.726349 progress 100% (41MB)
42 22:13:45.726547 41MB downloaded in 0.23s (180.71MB/s)
43 22:13:45.726715 end: 1.1.1 http-download (duration 00:00:00) [common]
45 22:13:45.726952 end: 1.1 download-retry (duration 00:00:00) [common]
46 22:13:45.727067 start: 1.2 download-retry (timeout 00:10:00) [common]
47 22:13:45.727149 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 22:13:45.727282 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1314-g1ab0ac1d7e2e3/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 22:13:45.727354 saving as /var/lib/lava/dispatcher/tmp/10597245/tftp-deploy-igpa52ow/kernel/Image
50 22:13:45.727414 total size: 45746688 (43MB)
51 22:13:45.727473 No compression specified
52 22:13:45.728705 progress 0% (0MB)
53 22:13:45.741029 progress 5% (2MB)
54 22:13:45.753587 progress 10% (4MB)
55 22:13:45.765437 progress 15% (6MB)
56 22:13:45.777267 progress 20% (8MB)
57 22:13:45.789537 progress 25% (10MB)
58 22:13:45.801483 progress 30% (13MB)
59 22:13:45.813762 progress 35% (15MB)
60 22:13:45.825756 progress 40% (17MB)
61 22:13:45.837953 progress 45% (19MB)
62 22:13:45.850513 progress 50% (21MB)
63 22:13:45.862664 progress 55% (24MB)
64 22:13:45.874838 progress 60% (26MB)
65 22:13:45.886934 progress 65% (28MB)
66 22:13:45.899202 progress 70% (30MB)
67 22:13:45.911666 progress 75% (32MB)
68 22:13:45.923518 progress 80% (34MB)
69 22:13:45.935263 progress 85% (37MB)
70 22:13:45.947041 progress 90% (39MB)
71 22:13:45.958607 progress 95% (41MB)
72 22:13:45.970180 progress 100% (43MB)
73 22:13:45.970350 43MB downloaded in 0.24s (179.59MB/s)
74 22:13:45.970514 end: 1.2.1 http-download (duration 00:00:00) [common]
76 22:13:45.970747 end: 1.2 download-retry (duration 00:00:00) [common]
77 22:13:45.970835 start: 1.3 download-retry (timeout 00:10:00) [common]
78 22:13:45.970920 start: 1.3.1 http-download (timeout 00:10:00) [common]
79 22:13:45.971061 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1314-g1ab0ac1d7e2e3/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 22:13:45.971138 saving as /var/lib/lava/dispatcher/tmp/10597245/tftp-deploy-igpa52ow/dtb/mt8192-asurada-spherion-r0.dtb
81 22:13:45.971202 total size: 46924 (0MB)
82 22:13:45.971262 No compression specified
83 22:13:45.972370 progress 69% (0MB)
84 22:13:45.972643 progress 100% (0MB)
85 22:13:45.972798 0MB downloaded in 0.00s (28.08MB/s)
86 22:13:45.972920 end: 1.3.1 http-download (duration 00:00:00) [common]
88 22:13:45.973142 end: 1.3 download-retry (duration 00:00:00) [common]
89 22:13:45.973227 start: 1.4 download-retry (timeout 00:10:00) [common]
90 22:13:45.973311 start: 1.4.1 http-download (timeout 00:10:00) [common]
91 22:13:45.973422 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1314-g1ab0ac1d7e2e3/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 22:13:45.973490 saving as /var/lib/lava/dispatcher/tmp/10597245/tftp-deploy-igpa52ow/modules/modules.tar
93 22:13:45.973551 total size: 8543056 (8MB)
94 22:13:45.973612 Using unxz to decompress xz
95 22:13:45.977374 progress 0% (0MB)
96 22:13:45.999618 progress 5% (0MB)
97 22:13:46.025362 progress 10% (0MB)
98 22:13:46.051981 progress 15% (1MB)
99 22:13:46.076948 progress 20% (1MB)
100 22:13:46.100206 progress 25% (2MB)
101 22:13:46.127072 progress 30% (2MB)
102 22:13:46.153010 progress 35% (2MB)
103 22:13:46.177363 progress 40% (3MB)
104 22:13:46.201193 progress 45% (3MB)
105 22:13:46.226059 progress 50% (4MB)
106 22:13:46.250535 progress 55% (4MB)
107 22:13:46.275539 progress 60% (4MB)
108 22:13:46.300955 progress 65% (5MB)
109 22:13:46.325808 progress 70% (5MB)
110 22:13:46.349886 progress 75% (6MB)
111 22:13:46.374794 progress 80% (6MB)
112 22:13:46.401277 progress 85% (6MB)
113 22:13:46.430702 progress 90% (7MB)
114 22:13:46.456522 progress 95% (7MB)
115 22:13:46.480971 progress 100% (8MB)
116 22:13:46.486781 8MB downloaded in 0.51s (15.87MB/s)
117 22:13:46.487081 end: 1.4.1 http-download (duration 00:00:01) [common]
119 22:13:46.487343 end: 1.4 download-retry (duration 00:00:01) [common]
120 22:13:46.487435 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 22:13:46.487530 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 22:13:46.487610 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 22:13:46.487693 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 22:13:46.487898 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/10597245/lava-overlay-lscqmoag
125 22:13:46.488050 makedir: /var/lib/lava/dispatcher/tmp/10597245/lava-overlay-lscqmoag/lava-10597245/bin
126 22:13:46.488167 makedir: /var/lib/lava/dispatcher/tmp/10597245/lava-overlay-lscqmoag/lava-10597245/tests
127 22:13:46.488262 makedir: /var/lib/lava/dispatcher/tmp/10597245/lava-overlay-lscqmoag/lava-10597245/results
128 22:13:46.488377 Creating /var/lib/lava/dispatcher/tmp/10597245/lava-overlay-lscqmoag/lava-10597245/bin/lava-add-keys
129 22:13:46.488519 Creating /var/lib/lava/dispatcher/tmp/10597245/lava-overlay-lscqmoag/lava-10597245/bin/lava-add-sources
130 22:13:46.488645 Creating /var/lib/lava/dispatcher/tmp/10597245/lava-overlay-lscqmoag/lava-10597245/bin/lava-background-process-start
131 22:13:46.488773 Creating /var/lib/lava/dispatcher/tmp/10597245/lava-overlay-lscqmoag/lava-10597245/bin/lava-background-process-stop
132 22:13:46.488893 Creating /var/lib/lava/dispatcher/tmp/10597245/lava-overlay-lscqmoag/lava-10597245/bin/lava-common-functions
133 22:13:46.489012 Creating /var/lib/lava/dispatcher/tmp/10597245/lava-overlay-lscqmoag/lava-10597245/bin/lava-echo-ipv4
134 22:13:46.489130 Creating /var/lib/lava/dispatcher/tmp/10597245/lava-overlay-lscqmoag/lava-10597245/bin/lava-install-packages
135 22:13:46.489249 Creating /var/lib/lava/dispatcher/tmp/10597245/lava-overlay-lscqmoag/lava-10597245/bin/lava-installed-packages
136 22:13:46.489366 Creating /var/lib/lava/dispatcher/tmp/10597245/lava-overlay-lscqmoag/lava-10597245/bin/lava-os-build
137 22:13:46.489485 Creating /var/lib/lava/dispatcher/tmp/10597245/lava-overlay-lscqmoag/lava-10597245/bin/lava-probe-channel
138 22:13:46.489602 Creating /var/lib/lava/dispatcher/tmp/10597245/lava-overlay-lscqmoag/lava-10597245/bin/lava-probe-ip
139 22:13:46.489720 Creating /var/lib/lava/dispatcher/tmp/10597245/lava-overlay-lscqmoag/lava-10597245/bin/lava-target-ip
140 22:13:46.489837 Creating /var/lib/lava/dispatcher/tmp/10597245/lava-overlay-lscqmoag/lava-10597245/bin/lava-target-mac
141 22:13:46.489953 Creating /var/lib/lava/dispatcher/tmp/10597245/lava-overlay-lscqmoag/lava-10597245/bin/lava-target-storage
142 22:13:46.490074 Creating /var/lib/lava/dispatcher/tmp/10597245/lava-overlay-lscqmoag/lava-10597245/bin/lava-test-case
143 22:13:46.490191 Creating /var/lib/lava/dispatcher/tmp/10597245/lava-overlay-lscqmoag/lava-10597245/bin/lava-test-event
144 22:13:46.490307 Creating /var/lib/lava/dispatcher/tmp/10597245/lava-overlay-lscqmoag/lava-10597245/bin/lava-test-feedback
145 22:13:46.490424 Creating /var/lib/lava/dispatcher/tmp/10597245/lava-overlay-lscqmoag/lava-10597245/bin/lava-test-raise
146 22:13:46.490542 Creating /var/lib/lava/dispatcher/tmp/10597245/lava-overlay-lscqmoag/lava-10597245/bin/lava-test-reference
147 22:13:46.490660 Creating /var/lib/lava/dispatcher/tmp/10597245/lava-overlay-lscqmoag/lava-10597245/bin/lava-test-runner
148 22:13:46.490778 Creating /var/lib/lava/dispatcher/tmp/10597245/lava-overlay-lscqmoag/lava-10597245/bin/lava-test-set
149 22:13:46.490896 Creating /var/lib/lava/dispatcher/tmp/10597245/lava-overlay-lscqmoag/lava-10597245/bin/lava-test-shell
150 22:13:46.491017 Updating /var/lib/lava/dispatcher/tmp/10597245/lava-overlay-lscqmoag/lava-10597245/bin/lava-install-packages (oe)
151 22:13:46.491164 Updating /var/lib/lava/dispatcher/tmp/10597245/lava-overlay-lscqmoag/lava-10597245/bin/lava-installed-packages (oe)
152 22:13:46.491282 Creating /var/lib/lava/dispatcher/tmp/10597245/lava-overlay-lscqmoag/lava-10597245/environment
153 22:13:46.491387 LAVA metadata
154 22:13:46.491461 - LAVA_JOB_ID=10597245
155 22:13:46.491526 - LAVA_DISPATCHER_IP=192.168.201.1
156 22:13:46.491627 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 22:13:46.491693 skipped lava-vland-overlay
158 22:13:46.491766 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 22:13:46.491843 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 22:13:46.491902 skipped lava-multinode-overlay
161 22:13:46.491975 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 22:13:46.492091 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 22:13:46.492166 Loading test definitions
164 22:13:46.492255 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 22:13:46.492328 Using /lava-10597245 at stage 0
166 22:13:46.492623 uuid=10597245_1.5.2.3.1 testdef=None
167 22:13:46.492709 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 22:13:46.492791 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 22:13:46.493295 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 22:13:46.493516 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 22:13:46.494107 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 22:13:46.494336 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 22:13:46.495001 runner path: /var/lib/lava/dispatcher/tmp/10597245/lava-overlay-lscqmoag/lava-10597245/0/tests/0_igt-gpu-panfrost test_uuid 10597245_1.5.2.3.1
176 22:13:46.495152 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 22:13:46.495359 Creating lava-test-runner.conf files
179 22:13:46.495421 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10597245/lava-overlay-lscqmoag/lava-10597245/0 for stage 0
180 22:13:46.495507 - 0_igt-gpu-panfrost
181 22:13:46.495599 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 22:13:46.495681 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 22:13:46.502084 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 22:13:46.502193 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 22:13:46.502278 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 22:13:46.502362 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 22:13:46.502451 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 22:13:47.867243 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 22:13:47.867675 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 22:13:47.867833 extracting modules file /var/lib/lava/dispatcher/tmp/10597245/tftp-deploy-igpa52ow/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10597245/extract-overlay-ramdisk-z7b3xdfs/ramdisk
191 22:13:48.107739 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 22:13:48.107916 start: 1.5.5 apply-overlay-tftp (timeout 00:09:57) [common]
193 22:13:48.108015 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10597245/compress-overlay-x6wx7au4/overlay-1.5.2.4.tar.gz to ramdisk
194 22:13:48.108159 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10597245/compress-overlay-x6wx7au4/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/10597245/extract-overlay-ramdisk-z7b3xdfs/ramdisk
195 22:13:48.114636 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 22:13:48.114754 start: 1.5.6 configure-preseed-file (timeout 00:09:57) [common]
197 22:13:48.114848 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 22:13:48.114939 start: 1.5.7 compress-ramdisk (timeout 00:09:57) [common]
199 22:13:48.115021 Building ramdisk /var/lib/lava/dispatcher/tmp/10597245/extract-overlay-ramdisk-z7b3xdfs/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/10597245/extract-overlay-ramdisk-z7b3xdfs/ramdisk
200 22:13:49.038213 >> 369045 blocks
201 22:13:54.782606 rename /var/lib/lava/dispatcher/tmp/10597245/extract-overlay-ramdisk-z7b3xdfs/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/10597245/tftp-deploy-igpa52ow/ramdisk/ramdisk.cpio.gz
202 22:13:54.783166 end: 1.5.7 compress-ramdisk (duration 00:00:07) [common]
203 22:13:54.783340 start: 1.5.8 prepare-kernel (timeout 00:09:51) [common]
204 22:13:54.783483 start: 1.5.8.1 prepare-fit (timeout 00:09:51) [common]
205 22:13:54.783634 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/10597245/tftp-deploy-igpa52ow/kernel/Image'
206 22:14:07.178873 Returned 0 in 12 seconds
207 22:14:07.279796 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/10597245/tftp-deploy-igpa52ow/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/10597245/tftp-deploy-igpa52ow/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/10597245/tftp-deploy-igpa52ow/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/10597245/tftp-deploy-igpa52ow/kernel/image.itb
208 22:14:08.104898 output: FIT description: Kernel Image image with one or more FDT blobs
209 22:14:08.105241 output: Created: Mon Jun 5 23:14:07 2023
210 22:14:08.105317 output: Image 0 (kernel-1)
211 22:14:08.105381 output: Description:
212 22:14:08.105444 output: Created: Mon Jun 5 23:14:07 2023
213 22:14:08.105507 output: Type: Kernel Image
214 22:14:08.105580 output: Compression: lzma compressed
215 22:14:08.105681 output: Data Size: 10082307 Bytes = 9846.00 KiB = 9.62 MiB
216 22:14:08.105740 output: Architecture: AArch64
217 22:14:08.105799 output: OS: Linux
218 22:14:08.105854 output: Load Address: 0x00000000
219 22:14:08.105910 output: Entry Point: 0x00000000
220 22:14:08.105967 output: Hash algo: crc32
221 22:14:08.106023 output: Hash value: c242daf7
222 22:14:08.106076 output: Image 1 (fdt-1)
223 22:14:08.106128 output: Description: mt8192-asurada-spherion-r0
224 22:14:08.106181 output: Created: Mon Jun 5 23:14:07 2023
225 22:14:08.106234 output: Type: Flat Device Tree
226 22:14:08.106287 output: Compression: uncompressed
227 22:14:08.106340 output: Data Size: 46924 Bytes = 45.82 KiB = 0.04 MiB
228 22:14:08.106393 output: Architecture: AArch64
229 22:14:08.106445 output: Hash algo: crc32
230 22:14:08.106498 output: Hash value: 1df858fa
231 22:14:08.106550 output: Image 2 (ramdisk-1)
232 22:14:08.106603 output: Description: unavailable
233 22:14:08.106654 output: Created: Mon Jun 5 23:14:07 2023
234 22:14:08.106706 output: Type: RAMDisk Image
235 22:14:08.106758 output: Compression: Unknown Compression
236 22:14:08.106811 output: Data Size: 56360813 Bytes = 55039.86 KiB = 53.75 MiB
237 22:14:08.106901 output: Architecture: AArch64
238 22:14:08.106953 output: OS: Linux
239 22:14:08.107006 output: Load Address: unavailable
240 22:14:08.107058 output: Entry Point: unavailable
241 22:14:08.107110 output: Hash algo: crc32
242 22:14:08.107162 output: Hash value: 794e0ede
243 22:14:08.107215 output: Default Configuration: 'conf-1'
244 22:14:08.107267 output: Configuration 0 (conf-1)
245 22:14:08.107319 output: Description: mt8192-asurada-spherion-r0
246 22:14:08.107376 output: Kernel: kernel-1
247 22:14:08.107450 output: Init Ramdisk: ramdisk-1
248 22:14:08.107504 output: FDT: fdt-1
249 22:14:08.107557 output: Loadables: kernel-1
250 22:14:08.107608 output:
251 22:14:08.107793 end: 1.5.8.1 prepare-fit (duration 00:00:13) [common]
252 22:14:08.107895 end: 1.5.8 prepare-kernel (duration 00:00:13) [common]
253 22:14:08.107999 end: 1.5 prepare-tftp-overlay (duration 00:00:22) [common]
254 22:14:08.108154 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:37) [common]
255 22:14:08.108229 No LXC device requested
256 22:14:08.108309 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 22:14:08.108411 start: 1.7 deploy-device-env (timeout 00:09:37) [common]
258 22:14:08.108501 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 22:14:08.108570 Checking files for TFTP limit of 4294967296 bytes.
260 22:14:08.109077 end: 1 tftp-deploy (duration 00:00:23) [common]
261 22:14:08.109175 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 22:14:08.109264 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 22:14:08.109384 substitutions:
264 22:14:08.109452 - {DTB}: 10597245/tftp-deploy-igpa52ow/dtb/mt8192-asurada-spherion-r0.dtb
265 22:14:08.109516 - {INITRD}: 10597245/tftp-deploy-igpa52ow/ramdisk/ramdisk.cpio.gz
266 22:14:08.109574 - {KERNEL}: 10597245/tftp-deploy-igpa52ow/kernel/Image
267 22:14:08.109631 - {LAVA_MAC}: None
268 22:14:08.109687 - {PRESEED_CONFIG}: None
269 22:14:08.109741 - {PRESEED_LOCAL}: None
270 22:14:08.109796 - {RAMDISK}: 10597245/tftp-deploy-igpa52ow/ramdisk/ramdisk.cpio.gz
271 22:14:08.109852 - {ROOT_PART}: None
272 22:14:08.109905 - {ROOT}: None
273 22:14:08.109959 - {SERVER_IP}: 192.168.201.1
274 22:14:08.110012 - {TEE}: None
275 22:14:08.110066 Parsed boot commands:
276 22:14:08.110119 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 22:14:08.110288 Parsed boot commands: tftpboot 192.168.201.1 10597245/tftp-deploy-igpa52ow/kernel/image.itb 10597245/tftp-deploy-igpa52ow/kernel/cmdline
278 22:14:08.110379 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 22:14:08.110463 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 22:14:08.110556 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 22:14:08.110640 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 22:14:08.110711 Not connected, no need to disconnect.
283 22:14:08.110844 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 22:14:08.110920 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 22:14:08.110989 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost mt8192-asurada-spherion-r0-cbg-2'
286 22:14:08.114439 Setting prompt string to ['lava-test: # ']
287 22:14:08.114765 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 22:14:08.114868 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 22:14:08.114962 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 22:14:08.115057 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 22:14:08.115249 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-2' '--port=1' '--command=reboot'
292 22:14:13.248862 >> Command sent successfully.
293 22:14:13.251615 Returned 0 in 5 seconds
294 22:14:13.351963 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 22:14:13.352561 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 22:14:13.352671 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 22:14:13.352766 Setting prompt string to 'Starting depthcharge on Spherion...'
299 22:14:13.352839 Changing prompt to 'Starting depthcharge on Spherion...'
300 22:14:13.352913 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 22:14:13.353179 [Enter `^Ec?' for help]
302 22:14:13.525241
303 22:14:13.525375
304 22:14:13.525456 F0: 102B 0000
305 22:14:13.525521
306 22:14:13.525581 F3: 1001 0000 [0200]
307 22:14:13.529396
308 22:14:13.529477 F3: 1001 0000
309 22:14:13.529543
310 22:14:13.529603 F7: 102D 0000
311 22:14:13.529671
312 22:14:13.529729 F1: 0000 0000
313 22:14:13.532889
314 22:14:13.532970 V0: 0000 0000 [0001]
315 22:14:13.533034
316 22:14:13.533093 00: 0007 8000
317 22:14:13.533153
318 22:14:13.537230 01: 0000 0000
319 22:14:13.537309
320 22:14:13.537380 BP: 0C00 0209 [0000]
321 22:14:13.537441
322 22:14:13.540169 G0: 1182 0000
323 22:14:13.540245
324 22:14:13.540315 EC: 0000 0021 [4000]
325 22:14:13.540375
326 22:14:13.544350 S7: 0000 0000 [0000]
327 22:14:13.544433
328 22:14:13.544497 CC: 0000 0000 [0001]
329 22:14:13.544557
330 22:14:13.547802 T0: 0000 0040 [010F]
331 22:14:13.547880
332 22:14:13.547945 Jump to BL
333 22:14:13.548014
334 22:14:13.572702
335 22:14:13.572785
336 22:14:13.572858
337 22:14:13.580556 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 22:14:13.584074 ARM64: Exception handlers installed.
339 22:14:13.587555 ARM64: Testing exception
340 22:14:13.587635 ARM64: Done test exception
341 22:14:13.594931 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 22:14:13.606096 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 22:14:13.612989 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 22:14:13.622857 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 22:14:13.629731 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 22:14:13.640019 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 22:14:13.650619 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 22:14:13.657029 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 22:14:13.675108 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 22:14:13.678793 WDT: Last reset was cold boot
351 22:14:13.681649 SPI1(PAD0) initialized at 2873684 Hz
352 22:14:13.684889 SPI5(PAD0) initialized at 992727 Hz
353 22:14:13.688473 VBOOT: Loading verstage.
354 22:14:13.695377 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 22:14:13.698239 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 22:14:13.701625 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 22:14:13.704963 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 22:14:13.712707 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 22:14:13.718899 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 22:14:13.729816 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
361 22:14:13.729921
362 22:14:13.730021
363 22:14:13.739895 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 22:14:13.743586 ARM64: Exception handlers installed.
365 22:14:13.746737 ARM64: Testing exception
366 22:14:13.746809 ARM64: Done test exception
367 22:14:13.753992 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 22:14:13.757727 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 22:14:13.770797 Probing TPM: . done!
370 22:14:13.770877 TPM ready after 0 ms
371 22:14:13.778469 Connected to device vid:did:rid of 1ae0:0028:00
372 22:14:13.785139 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523
373 22:14:13.844048 Initialized TPM device CR50 revision 0
374 22:14:13.854087 tlcl_send_startup: Startup return code is 0
375 22:14:13.854179 TPM: setup succeeded
376 22:14:13.865887 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 22:14:13.874690 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 22:14:13.887185 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 22:14:13.896405 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 22:14:13.899727 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 22:14:13.905855 in-header: 03 07 00 00 08 00 00 00
382 22:14:13.909544 in-data: aa e4 47 04 13 02 00 00
383 22:14:13.912575 Chrome EC: UHEPI supported
384 22:14:13.919529 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 22:14:13.923304 in-header: 03 95 00 00 08 00 00 00
386 22:14:13.927139 in-data: 18 20 20 08 00 00 00 00
387 22:14:13.927212 Phase 1
388 22:14:13.930520 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 22:14:13.938384 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 22:14:13.942355 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 22:14:13.945835 Recovery requested (1009000e)
392 22:14:13.954000 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 22:14:13.959499 tlcl_extend: response is 0
394 22:14:13.968724 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 22:14:13.974529 tlcl_extend: response is 0
396 22:14:13.981413 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 22:14:14.001484 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
398 22:14:14.007807 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 22:14:14.007893
400 22:14:14.007958
401 22:14:14.018121 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 22:14:14.021530 ARM64: Exception handlers installed.
403 22:14:14.024653 ARM64: Testing exception
404 22:14:14.024741 ARM64: Done test exception
405 22:14:14.047017 pmic_efuse_setting: Set efuses in 11 msecs
406 22:14:14.049894 pmwrap_interface_init: Select PMIF_VLD_RDY
407 22:14:14.056489 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 22:14:14.060165 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 22:14:14.067003 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 22:14:14.070817 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 22:14:14.074335 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 22:14:14.081393 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 22:14:14.084948 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 22:14:14.089118 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 22:14:14.096283 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 22:14:14.099215 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 22:14:14.103285 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 22:14:14.106589 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 22:14:14.114075 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 22:14:14.117673 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 22:14:14.125153 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 22:14:14.132451 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 22:14:14.135690 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 22:14:14.142964 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 22:14:14.146456 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 22:14:14.153339 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 22:14:14.157181 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 22:14:14.164890 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 22:14:14.168722 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 22:14:14.175958 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 22:14:14.179764 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 22:14:14.186974 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 22:14:14.190589 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 22:14:14.197523 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 22:14:14.201371 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 22:14:14.204756 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 22:14:14.212228 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 22:14:14.215731 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 22:14:14.219433 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 22:14:14.226317 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 22:14:14.230438 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 22:14:14.237682 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 22:14:14.241399 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 22:14:14.244673 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 22:14:14.248737 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 22:14:14.256150 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 22:14:14.259572 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 22:14:14.263040 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 22:14:14.266602 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 22:14:14.274268 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 22:14:14.277854 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 22:14:14.281653 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 22:14:14.285328 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 22:14:14.289262 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 22:14:14.292150 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 22:14:14.299393 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 22:14:14.302835 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 22:14:14.310681 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 22:14:14.317776 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 22:14:14.321217 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 22:14:14.332239 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 22:14:14.340226 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 22:14:14.343512 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 22:14:14.347753 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 22:14:14.354482 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 22:14:14.358020 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6b, sec=0x3
467 22:14:14.365840 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 22:14:14.369858 [RTC]rtc_osc_init,62: osc32con val = 0xde6b
469 22:14:14.373112 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 22:14:14.384420 [RTC]rtc_get_frequency_meter,154: input=15, output=852
471 22:14:14.394577 [RTC]rtc_get_frequency_meter,154: input=7, output=725
472 22:14:14.403166 [RTC]rtc_get_frequency_meter,154: input=11, output=789
473 22:14:14.412988 [RTC]rtc_get_frequency_meter,154: input=13, output=821
474 22:14:14.422151 [RTC]rtc_get_frequency_meter,154: input=12, output=805
475 22:14:14.432222 [RTC]rtc_get_frequency_meter,154: input=11, output=788
476 22:14:14.441708 [RTC]rtc_get_frequency_meter,154: input=12, output=805
477 22:14:14.445092 [RTC]rtc_eosc_cali,47: left: 11, middle: 11, right: 12
478 22:14:14.448706 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6b
479 22:14:14.456196 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
480 22:14:14.459888 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
481 22:14:14.464024 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
482 22:14:14.467713 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
483 22:14:14.470850 ADC[4]: Raw value=903694 ID=7
484 22:14:14.474724 ADC[3]: Raw value=213546 ID=1
485 22:14:14.474808 RAM Code: 0x71
486 22:14:14.478364 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
487 22:14:14.485566 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
488 22:14:14.492824 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
489 22:14:14.500655 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
490 22:14:14.500739 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
491 22:14:14.505203 in-header: 03 07 00 00 08 00 00 00
492 22:14:14.508848 in-data: aa e4 47 04 13 02 00 00
493 22:14:14.512325 Chrome EC: UHEPI supported
494 22:14:14.519198 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
495 22:14:14.522852 in-header: 03 95 00 00 08 00 00 00
496 22:14:14.526473 in-data: 18 20 20 08 00 00 00 00
497 22:14:14.526579 MRC: failed to locate region type 0.
498 22:14:14.534073 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
499 22:14:14.537748 DRAM-K: Running full calibration
500 22:14:14.544697 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
501 22:14:14.544807 header.status = 0x0
502 22:14:14.548182 header.version = 0x6 (expected: 0x6)
503 22:14:14.551930 header.size = 0xd00 (expected: 0xd00)
504 22:14:14.555809 header.flags = 0x0
505 22:14:14.558806 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
506 22:14:14.578827 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
507 22:14:14.586248 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
508 22:14:14.589716 dram_init: ddr_geometry: 2
509 22:14:14.589818 [EMI] MDL number = 2
510 22:14:14.594049 [EMI] Get MDL freq = 0
511 22:14:14.594151 dram_init: ddr_type: 0
512 22:14:14.597704 is_discrete_lpddr4: 1
513 22:14:14.597784 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
514 22:14:14.601467
515 22:14:14.601577
516 22:14:14.601679 [Bian_co] ETT version 0.0.0.1
517 22:14:14.609058 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
518 22:14:14.609176
519 22:14:14.612817 dramc_set_vcore_voltage set vcore to 650000
520 22:14:14.612926 Read voltage for 800, 4
521 22:14:14.613019 Vio18 = 0
522 22:14:14.616344 Vcore = 650000
523 22:14:14.616427 Vdram = 0
524 22:14:14.616493 Vddq = 0
525 22:14:14.619671 Vmddr = 0
526 22:14:14.619763 dram_init: config_dvfs: 1
527 22:14:14.623948 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
528 22:14:14.630014 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
529 22:14:14.633416 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
530 22:14:14.636539 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
531 22:14:14.643435 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
532 22:14:14.646995 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
533 22:14:14.647078 MEM_TYPE=3, freq_sel=18
534 22:14:14.651396 sv_algorithm_assistance_LP4_1600
535 22:14:14.654568 ============ PULL DRAM RESETB DOWN ============
536 22:14:14.658354 ========== PULL DRAM RESETB DOWN end =========
537 22:14:14.665878 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
538 22:14:14.666034 ===================================
539 22:14:14.669288 LPDDR4 DRAM CONFIGURATION
540 22:14:14.672598 ===================================
541 22:14:14.676123 EX_ROW_EN[0] = 0x0
542 22:14:14.676206 EX_ROW_EN[1] = 0x0
543 22:14:14.679023 LP4Y_EN = 0x0
544 22:14:14.679105 WORK_FSP = 0x0
545 22:14:14.682731 WL = 0x2
546 22:14:14.682814 RL = 0x2
547 22:14:14.686615 BL = 0x2
548 22:14:14.686699 RPST = 0x0
549 22:14:14.689818 RD_PRE = 0x0
550 22:14:14.689909 WR_PRE = 0x1
551 22:14:14.693081 WR_PST = 0x0
552 22:14:14.693183 DBI_WR = 0x0
553 22:14:14.697172 DBI_RD = 0x0
554 22:14:14.697255 OTF = 0x1
555 22:14:14.700275 ===================================
556 22:14:14.703249 ===================================
557 22:14:14.706866 ANA top config
558 22:14:14.709835 ===================================
559 22:14:14.709918 DLL_ASYNC_EN = 0
560 22:14:14.713208 ALL_SLAVE_EN = 1
561 22:14:14.716697 NEW_RANK_MODE = 1
562 22:14:14.719876 DLL_IDLE_MODE = 1
563 22:14:14.723353 LP45_APHY_COMB_EN = 1
564 22:14:14.723436 TX_ODT_DIS = 1
565 22:14:14.726798 NEW_8X_MODE = 1
566 22:14:14.730061 ===================================
567 22:14:14.733118 ===================================
568 22:14:14.736289 data_rate = 1600
569 22:14:14.739996 CKR = 1
570 22:14:14.743027 DQ_P2S_RATIO = 8
571 22:14:14.746290 ===================================
572 22:14:14.750194 CA_P2S_RATIO = 8
573 22:14:14.750293 DQ_CA_OPEN = 0
574 22:14:14.753574 DQ_SEMI_OPEN = 0
575 22:14:14.757096 CA_SEMI_OPEN = 0
576 22:14:14.760179 CA_FULL_RATE = 0
577 22:14:14.760262 DQ_CKDIV4_EN = 1
578 22:14:14.763687 CA_CKDIV4_EN = 1
579 22:14:14.766728 CA_PREDIV_EN = 0
580 22:14:14.770393 PH8_DLY = 0
581 22:14:14.773808 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
582 22:14:14.776903 DQ_AAMCK_DIV = 4
583 22:14:14.776989 CA_AAMCK_DIV = 4
584 22:14:14.780395 CA_ADMCK_DIV = 4
585 22:14:14.783433 DQ_TRACK_CA_EN = 0
586 22:14:14.786896 CA_PICK = 800
587 22:14:14.790032 CA_MCKIO = 800
588 22:14:14.793198 MCKIO_SEMI = 0
589 22:14:14.797696 PLL_FREQ = 3068
590 22:14:14.797780 DQ_UI_PI_RATIO = 32
591 22:14:14.801176 CA_UI_PI_RATIO = 0
592 22:14:14.804849 ===================================
593 22:14:14.808629 ===================================
594 22:14:14.812029 memory_type:LPDDR4
595 22:14:14.812211 GP_NUM : 10
596 22:14:14.815971 SRAM_EN : 1
597 22:14:14.816103 MD32_EN : 0
598 22:14:14.819524 ===================================
599 22:14:14.823240 [ANA_INIT] >>>>>>>>>>>>>>
600 22:14:14.823352 <<<<<< [CONFIGURE PHASE]: ANA_TX
601 22:14:14.827184 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
602 22:14:14.830611 ===================================
603 22:14:14.833585 data_rate = 1600,PCW = 0X7600
604 22:14:14.837324 ===================================
605 22:14:14.840589 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
606 22:14:14.846803 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 22:14:14.850037 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
608 22:14:14.856925 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
609 22:14:14.859883 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
610 22:14:14.863455 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
611 22:14:14.867099 [ANA_INIT] flow start
612 22:14:14.867198 [ANA_INIT] PLL >>>>>>>>
613 22:14:14.870079 [ANA_INIT] PLL <<<<<<<<
614 22:14:14.873280 [ANA_INIT] MIDPI >>>>>>>>
615 22:14:14.873393 [ANA_INIT] MIDPI <<<<<<<<
616 22:14:14.876706 [ANA_INIT] DLL >>>>>>>>
617 22:14:14.879923 [ANA_INIT] flow end
618 22:14:14.883388 ============ LP4 DIFF to SE enter ============
619 22:14:14.886595 ============ LP4 DIFF to SE exit ============
620 22:14:14.890035 [ANA_INIT] <<<<<<<<<<<<<
621 22:14:14.893464 [Flow] Enable top DCM control >>>>>
622 22:14:14.896438 [Flow] Enable top DCM control <<<<<
623 22:14:14.899655 Enable DLL master slave shuffle
624 22:14:14.903399 ==============================================================
625 22:14:14.906902 Gating Mode config
626 22:14:14.913224 ==============================================================
627 22:14:14.913323 Config description:
628 22:14:14.923306 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
629 22:14:14.929732 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
630 22:14:14.932850 SELPH_MODE 0: By rank 1: By Phase
631 22:14:14.939433 ==============================================================
632 22:14:14.943152 GAT_TRACK_EN = 1
633 22:14:14.946378 RX_GATING_MODE = 2
634 22:14:14.949569 RX_GATING_TRACK_MODE = 2
635 22:14:14.952684 SELPH_MODE = 1
636 22:14:14.956347 PICG_EARLY_EN = 1
637 22:14:14.959415 VALID_LAT_VALUE = 1
638 22:14:14.962756 ==============================================================
639 22:14:14.966601 Enter into Gating configuration >>>>
640 22:14:14.969763 Exit from Gating configuration <<<<
641 22:14:14.972855 Enter into DVFS_PRE_config >>>>>
642 22:14:14.986150 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
643 22:14:14.986238 Exit from DVFS_PRE_config <<<<<
644 22:14:14.989780 Enter into PICG configuration >>>>
645 22:14:14.992893 Exit from PICG configuration <<<<
646 22:14:14.995981 [RX_INPUT] configuration >>>>>
647 22:14:14.999331 [RX_INPUT] configuration <<<<<
648 22:14:15.006061 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
649 22:14:15.009843 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
650 22:14:15.016026 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
651 22:14:15.022677 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
652 22:14:15.029391 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
653 22:14:15.036057 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
654 22:14:15.039234 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
655 22:14:15.042393 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
656 22:14:15.045869 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
657 22:14:15.052410 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
658 22:14:15.055666 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
659 22:14:15.059458 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
660 22:14:15.062360 ===================================
661 22:14:15.065981 LPDDR4 DRAM CONFIGURATION
662 22:14:15.069391 ===================================
663 22:14:15.069474 EX_ROW_EN[0] = 0x0
664 22:14:15.072353 EX_ROW_EN[1] = 0x0
665 22:14:15.075848 LP4Y_EN = 0x0
666 22:14:15.075950 WORK_FSP = 0x0
667 22:14:15.079105 WL = 0x2
668 22:14:15.079181 RL = 0x2
669 22:14:15.082631 BL = 0x2
670 22:14:15.082704 RPST = 0x0
671 22:14:15.085588 RD_PRE = 0x0
672 22:14:15.085662 WR_PRE = 0x1
673 22:14:15.089105 WR_PST = 0x0
674 22:14:15.089180 DBI_WR = 0x0
675 22:14:15.092520 DBI_RD = 0x0
676 22:14:15.092621 OTF = 0x1
677 22:14:15.095506 ===================================
678 22:14:15.099584 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
679 22:14:15.105843 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
680 22:14:15.108898 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
681 22:14:15.112098 ===================================
682 22:14:15.115627 LPDDR4 DRAM CONFIGURATION
683 22:14:15.118844 ===================================
684 22:14:15.118939 EX_ROW_EN[0] = 0x10
685 22:14:15.122109 EX_ROW_EN[1] = 0x0
686 22:14:15.125750 LP4Y_EN = 0x0
687 22:14:15.125827 WORK_FSP = 0x0
688 22:14:15.128731 WL = 0x2
689 22:14:15.128801 RL = 0x2
690 22:14:15.131978 BL = 0x2
691 22:14:15.132111 RPST = 0x0
692 22:14:15.135966 RD_PRE = 0x0
693 22:14:15.136100 WR_PRE = 0x1
694 22:14:15.138498 WR_PST = 0x0
695 22:14:15.138571 DBI_WR = 0x0
696 22:14:15.142221 DBI_RD = 0x0
697 22:14:15.142297 OTF = 0x1
698 22:14:15.145255 ===================================
699 22:14:15.151642 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
700 22:14:15.155978 nWR fixed to 40
701 22:14:15.159705 [ModeRegInit_LP4] CH0 RK0
702 22:14:15.159779 [ModeRegInit_LP4] CH0 RK1
703 22:14:15.162680 [ModeRegInit_LP4] CH1 RK0
704 22:14:15.166197 [ModeRegInit_LP4] CH1 RK1
705 22:14:15.166298 match AC timing 13
706 22:14:15.172786 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
707 22:14:15.176153 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
708 22:14:15.179422 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
709 22:14:15.186264 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
710 22:14:15.189233 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
711 22:14:15.189311 [EMI DOE] emi_dcm 0
712 22:14:15.196366 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
713 22:14:15.196461 ==
714 22:14:15.199492 Dram Type= 6, Freq= 0, CH_0, rank 0
715 22:14:15.202696 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
716 22:14:15.202773 ==
717 22:14:15.209237 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
718 22:14:15.215888 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
719 22:14:15.223585 [CA 0] Center 37 (7~68) winsize 62
720 22:14:15.227111 [CA 1] Center 37 (6~68) winsize 63
721 22:14:15.230231 [CA 2] Center 35 (4~66) winsize 63
722 22:14:15.233668 [CA 3] Center 35 (4~66) winsize 63
723 22:14:15.236897 [CA 4] Center 33 (3~64) winsize 62
724 22:14:15.240169 [CA 5] Center 33 (3~64) winsize 62
725 22:14:15.240243
726 22:14:15.243480 [CmdBusTrainingLP45] Vref(ca) range 1: 34
727 22:14:15.243551
728 22:14:15.246716 [CATrainingPosCal] consider 1 rank data
729 22:14:15.250229 u2DelayCellTimex100 = 270/100 ps
730 22:14:15.253433 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
731 22:14:15.260354 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
732 22:14:15.263427 CA2 delay=35 (4~66),Diff = 2 PI (14 cell)
733 22:14:15.266677 CA3 delay=35 (4~66),Diff = 2 PI (14 cell)
734 22:14:15.270022 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
735 22:14:15.273760 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
736 22:14:15.273867
737 22:14:15.276642 CA PerBit enable=1, Macro0, CA PI delay=33
738 22:14:15.276749
739 22:14:15.280021 [CBTSetCACLKResult] CA Dly = 33
740 22:14:15.280132 CS Dly: 5 (0~36)
741 22:14:15.283683 ==
742 22:14:15.286741 Dram Type= 6, Freq= 0, CH_0, rank 1
743 22:14:15.289881 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
744 22:14:15.289958 ==
745 22:14:15.293548 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
746 22:14:15.299893 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
747 22:14:15.310358 [CA 0] Center 38 (7~69) winsize 63
748 22:14:15.313200 [CA 1] Center 37 (7~68) winsize 62
749 22:14:15.317113 [CA 2] Center 35 (4~66) winsize 63
750 22:14:15.320164 [CA 3] Center 35 (4~66) winsize 63
751 22:14:15.323760 [CA 4] Center 34 (3~65) winsize 63
752 22:14:15.326765 [CA 5] Center 33 (3~64) winsize 62
753 22:14:15.326844
754 22:14:15.330330 [CmdBusTrainingLP45] Vref(ca) range 1: 34
755 22:14:15.330405
756 22:14:15.333339 [CATrainingPosCal] consider 2 rank data
757 22:14:15.336540 u2DelayCellTimex100 = 270/100 ps
758 22:14:15.339974 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
759 22:14:15.346492 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
760 22:14:15.349743 CA2 delay=35 (4~66),Diff = 2 PI (14 cell)
761 22:14:15.353138 CA3 delay=35 (4~66),Diff = 2 PI (14 cell)
762 22:14:15.356744 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
763 22:14:15.359572 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
764 22:14:15.359650
765 22:14:15.362913 CA PerBit enable=1, Macro0, CA PI delay=33
766 22:14:15.363048
767 22:14:15.366253 [CBTSetCACLKResult] CA Dly = 33
768 22:14:15.369874 CS Dly: 6 (0~38)
769 22:14:15.369960
770 22:14:15.372890 ----->DramcWriteLeveling(PI) begin...
771 22:14:15.372978 ==
772 22:14:15.376357 Dram Type= 6, Freq= 0, CH_0, rank 0
773 22:14:15.380228 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
774 22:14:15.380308 ==
775 22:14:15.384113 Write leveling (Byte 0): 30 => 30
776 22:14:15.387705 Write leveling (Byte 1): 26 => 26
777 22:14:15.387801 DramcWriteLeveling(PI) end<-----
778 22:14:15.387872
779 22:14:15.387935 ==
780 22:14:15.391397 Dram Type= 6, Freq= 0, CH_0, rank 0
781 22:14:15.397616 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
782 22:14:15.397697 ==
783 22:14:15.401214 [Gating] SW mode calibration
784 22:14:15.408332 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
785 22:14:15.411564 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
786 22:14:15.415225 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
787 22:14:15.421951 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
788 22:14:15.424869 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
789 22:14:15.428521 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 22:14:15.435043 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 22:14:15.438026 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 22:14:15.441959 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 22:14:15.448150 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 22:14:15.451320 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 22:14:15.454785 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 22:14:15.461607 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 22:14:15.464622 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 22:14:15.467844 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 22:14:15.474450 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 22:14:15.478022 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 22:14:15.481378 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 22:14:15.488232 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 22:14:15.491557 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
804 22:14:15.494722 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
805 22:14:15.498373 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 22:14:15.504811 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 22:14:15.507906 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 22:14:15.511635 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 22:14:15.518456 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 22:14:15.521540 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 22:14:15.524693 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 22:14:15.531428 0 9 8 | B1->B0 | 2323 3030 | 0 1 | (0 0) (1 1)
813 22:14:15.534709 0 9 12 | B1->B0 | 2d2d 3434 | 1 1 | (1 1) (1 1)
814 22:14:15.537880 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 22:14:15.544374 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 22:14:15.547929 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 22:14:15.551154 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 22:14:15.558221 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
819 22:14:15.561053 0 10 4 | B1->B0 | 3434 3030 | 1 0 | (1 0) (1 0)
820 22:14:15.564306 0 10 8 | B1->B0 | 3333 2525 | 0 0 | (1 0) (0 0)
821 22:14:15.571240 0 10 12 | B1->B0 | 2b2b 2323 | 0 0 | (1 1) (0 0)
822 22:14:15.574375 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 22:14:15.578189 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 22:14:15.584737 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 22:14:15.587611 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 22:14:15.591093 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 22:14:15.597711 0 11 4 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
828 22:14:15.600945 0 11 8 | B1->B0 | 2525 4040 | 0 1 | (0 0) (0 0)
829 22:14:15.604396 0 11 12 | B1->B0 | 3b3b 4646 | 1 0 | (0 0) (0 0)
830 22:14:15.610859 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 22:14:15.614521 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 22:14:15.617373 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 22:14:15.624339 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 22:14:15.627175 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 22:14:15.630767 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
836 22:14:15.637171 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
837 22:14:15.640466 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 22:14:15.644332 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 22:14:15.650401 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 22:14:15.654177 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 22:14:15.657350 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 22:14:15.660896 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 22:14:15.667232 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 22:14:15.670622 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 22:14:15.673807 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 22:14:15.680394 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 22:14:15.683927 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 22:14:15.687392 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 22:14:15.693514 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 22:14:15.697393 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 22:14:15.700233 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
852 22:14:15.707012 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
853 22:14:15.710483 Total UI for P1: 0, mck2ui 16
854 22:14:15.714055 best dqsien dly found for B0: ( 0, 14, 6)
855 22:14:15.717043 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
856 22:14:15.720552 Total UI for P1: 0, mck2ui 16
857 22:14:15.723959 best dqsien dly found for B1: ( 0, 14, 10)
858 22:14:15.726775 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
859 22:14:15.730619 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
860 22:14:15.730719
861 22:14:15.733745 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
862 22:14:15.736727 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
863 22:14:15.740586 [Gating] SW calibration Done
864 22:14:15.740687 ==
865 22:14:15.743220 Dram Type= 6, Freq= 0, CH_0, rank 0
866 22:14:15.750916 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
867 22:14:15.751017 ==
868 22:14:15.751117 RX Vref Scan: 0
869 22:14:15.751212
870 22:14:15.754291 RX Vref 0 -> 0, step: 1
871 22:14:15.754391
872 22:14:15.754490 RX Delay -130 -> 252, step: 16
873 22:14:15.760937 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
874 22:14:15.764036 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
875 22:14:15.767131 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
876 22:14:15.770734 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
877 22:14:15.773898 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
878 22:14:15.780557 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
879 22:14:15.784232 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
880 22:14:15.786952 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
881 22:14:15.790288 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
882 22:14:15.793916 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
883 22:14:15.800204 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
884 22:14:15.803866 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
885 22:14:15.807341 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
886 22:14:15.810462 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
887 22:14:15.817009 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
888 22:14:15.820378 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
889 22:14:15.820462 ==
890 22:14:15.823858 Dram Type= 6, Freq= 0, CH_0, rank 0
891 22:14:15.826925 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
892 22:14:15.827010 ==
893 22:14:15.830454 DQS Delay:
894 22:14:15.830539 DQS0 = 0, DQS1 = 0
895 22:14:15.830606 DQM Delay:
896 22:14:15.833569 DQM0 = 89, DQM1 = 76
897 22:14:15.833653 DQ Delay:
898 22:14:15.837383 DQ0 =93, DQ1 =85, DQ2 =85, DQ3 =85
899 22:14:15.840892 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =93
900 22:14:15.843587 DQ8 =69, DQ9 =61, DQ10 =69, DQ11 =69
901 22:14:15.847075 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
902 22:14:15.847198
903 22:14:15.847264
904 22:14:15.847326 ==
905 22:14:15.850470 Dram Type= 6, Freq= 0, CH_0, rank 0
906 22:14:15.853845 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
907 22:14:15.857205 ==
908 22:14:15.857288
909 22:14:15.857362
910 22:14:15.857463 TX Vref Scan disable
911 22:14:15.860577 == TX Byte 0 ==
912 22:14:15.863803 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
913 22:14:15.866823 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
914 22:14:15.870504 == TX Byte 1 ==
915 22:14:15.873591 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
916 22:14:15.877158 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
917 22:14:15.880250 ==
918 22:14:15.883417 Dram Type= 6, Freq= 0, CH_0, rank 0
919 22:14:15.886695 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
920 22:14:15.886797 ==
921 22:14:15.899667 TX Vref=22, minBit 0, minWin=27, winSum=440
922 22:14:15.902664 TX Vref=24, minBit 1, minWin=27, winSum=444
923 22:14:15.906521 TX Vref=26, minBit 2, minWin=27, winSum=445
924 22:14:15.909444 TX Vref=28, minBit 3, minWin=27, winSum=448
925 22:14:15.912546 TX Vref=30, minBit 1, minWin=27, winSum=450
926 22:14:15.919725 TX Vref=32, minBit 1, minWin=27, winSum=449
927 22:14:15.922545 [TxChooseVref] Worse bit 1, Min win 27, Win sum 450, Final Vref 30
928 22:14:15.922649
929 22:14:15.926329 Final TX Range 1 Vref 30
930 22:14:15.926429
931 22:14:15.926522 ==
932 22:14:15.929459 Dram Type= 6, Freq= 0, CH_0, rank 0
933 22:14:15.932919 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 22:14:15.933020 ==
935 22:14:15.936070
936 22:14:15.936142
937 22:14:15.936205 TX Vref Scan disable
938 22:14:15.939699 == TX Byte 0 ==
939 22:14:15.942733 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
940 22:14:15.949414 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
941 22:14:15.949519 == TX Byte 1 ==
942 22:14:15.952735 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
943 22:14:15.959401 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
944 22:14:15.959502
945 22:14:15.959595 [DATLAT]
946 22:14:15.959686 Freq=800, CH0 RK0
947 22:14:15.959774
948 22:14:15.962768 DATLAT Default: 0xa
949 22:14:15.962866 0, 0xFFFF, sum = 0
950 22:14:15.965874 1, 0xFFFF, sum = 0
951 22:14:15.965976 2, 0xFFFF, sum = 0
952 22:14:15.969076 3, 0xFFFF, sum = 0
953 22:14:15.972547 4, 0xFFFF, sum = 0
954 22:14:15.972650 5, 0xFFFF, sum = 0
955 22:14:15.975729 6, 0xFFFF, sum = 0
956 22:14:15.975831 7, 0xFFFF, sum = 0
957 22:14:15.979471 8, 0xFFFF, sum = 0
958 22:14:15.979583 9, 0x0, sum = 1
959 22:14:15.982753 10, 0x0, sum = 2
960 22:14:15.982834 11, 0x0, sum = 3
961 22:14:15.982918 12, 0x0, sum = 4
962 22:14:15.986103 best_step = 10
963 22:14:15.986217
964 22:14:15.986311 ==
965 22:14:15.989710 Dram Type= 6, Freq= 0, CH_0, rank 0
966 22:14:15.992913 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
967 22:14:15.992987 ==
968 22:14:15.995947 RX Vref Scan: 1
969 22:14:15.996087
970 22:14:15.996154 Set Vref Range= 32 -> 127
971 22:14:15.999451
972 22:14:15.999528 RX Vref 32 -> 127, step: 1
973 22:14:15.999591
974 22:14:16.002500 RX Delay -95 -> 252, step: 8
975 22:14:16.002602
976 22:14:16.006119 Set Vref, RX VrefLevel [Byte0]: 32
977 22:14:16.009611 [Byte1]: 32
978 22:14:16.009714
979 22:14:16.012552 Set Vref, RX VrefLevel [Byte0]: 33
980 22:14:16.015638 [Byte1]: 33
981 22:14:16.019642
982 22:14:16.019755 Set Vref, RX VrefLevel [Byte0]: 34
983 22:14:16.023099 [Byte1]: 34
984 22:14:16.027523
985 22:14:16.027622 Set Vref, RX VrefLevel [Byte0]: 35
986 22:14:16.030711 [Byte1]: 35
987 22:14:16.034822
988 22:14:16.034921 Set Vref, RX VrefLevel [Byte0]: 36
989 22:14:16.038842 [Byte1]: 36
990 22:14:16.043012
991 22:14:16.043086 Set Vref, RX VrefLevel [Byte0]: 37
992 22:14:16.046519 [Byte1]: 37
993 22:14:16.050724
994 22:14:16.050822 Set Vref, RX VrefLevel [Byte0]: 38
995 22:14:16.054063 [Byte1]: 38
996 22:14:16.058151
997 22:14:16.058225 Set Vref, RX VrefLevel [Byte0]: 39
998 22:14:16.061462 [Byte1]: 39
999 22:14:16.065597
1000 22:14:16.065692 Set Vref, RX VrefLevel [Byte0]: 40
1001 22:14:16.068667 [Byte1]: 40
1002 22:14:16.073354
1003 22:14:16.073451 Set Vref, RX VrefLevel [Byte0]: 41
1004 22:14:16.077015 [Byte1]: 41
1005 22:14:16.080651
1006 22:14:16.080734 Set Vref, RX VrefLevel [Byte0]: 42
1007 22:14:16.083666 [Byte1]: 42
1008 22:14:16.088006
1009 22:14:16.088128 Set Vref, RX VrefLevel [Byte0]: 43
1010 22:14:16.091598 [Byte1]: 43
1011 22:14:16.095543
1012 22:14:16.095626 Set Vref, RX VrefLevel [Byte0]: 44
1013 22:14:16.099044 [Byte1]: 44
1014 22:14:16.103413
1015 22:14:16.103496 Set Vref, RX VrefLevel [Byte0]: 45
1016 22:14:16.106409 [Byte1]: 45
1017 22:14:16.110720
1018 22:14:16.110803 Set Vref, RX VrefLevel [Byte0]: 46
1019 22:14:16.114228 [Byte1]: 46
1020 22:14:16.118817
1021 22:14:16.118900 Set Vref, RX VrefLevel [Byte0]: 47
1022 22:14:16.122164 [Byte1]: 47
1023 22:14:16.125933
1024 22:14:16.126015 Set Vref, RX VrefLevel [Byte0]: 48
1025 22:14:16.129362 [Byte1]: 48
1026 22:14:16.133636
1027 22:14:16.133721 Set Vref, RX VrefLevel [Byte0]: 49
1028 22:14:16.137027 [Byte1]: 49
1029 22:14:16.141461
1030 22:14:16.141542 Set Vref, RX VrefLevel [Byte0]: 50
1031 22:14:16.144666 [Byte1]: 50
1032 22:14:16.149141
1033 22:14:16.149222 Set Vref, RX VrefLevel [Byte0]: 51
1034 22:14:16.152060 [Byte1]: 51
1035 22:14:16.156557
1036 22:14:16.156638 Set Vref, RX VrefLevel [Byte0]: 52
1037 22:14:16.160097 [Byte1]: 52
1038 22:14:16.163997
1039 22:14:16.164116 Set Vref, RX VrefLevel [Byte0]: 53
1040 22:14:16.167539 [Byte1]: 53
1041 22:14:16.171539
1042 22:14:16.171648 Set Vref, RX VrefLevel [Byte0]: 54
1043 22:14:16.174773 [Byte1]: 54
1044 22:14:16.179166
1045 22:14:16.179242 Set Vref, RX VrefLevel [Byte0]: 55
1046 22:14:16.182871 [Byte1]: 55
1047 22:14:16.187082
1048 22:14:16.187181 Set Vref, RX VrefLevel [Byte0]: 56
1049 22:14:16.190134 [Byte1]: 56
1050 22:14:16.194287
1051 22:14:16.194388 Set Vref, RX VrefLevel [Byte0]: 57
1052 22:14:16.197571 [Byte1]: 57
1053 22:14:16.201866
1054 22:14:16.201948 Set Vref, RX VrefLevel [Byte0]: 58
1055 22:14:16.205279 [Byte1]: 58
1056 22:14:16.209404
1057 22:14:16.209485 Set Vref, RX VrefLevel [Byte0]: 59
1058 22:14:16.213142 [Byte1]: 59
1059 22:14:16.217039
1060 22:14:16.217120 Set Vref, RX VrefLevel [Byte0]: 60
1061 22:14:16.220748 [Byte1]: 60
1062 22:14:16.224745
1063 22:14:16.224826 Set Vref, RX VrefLevel [Byte0]: 61
1064 22:14:16.228539 [Byte1]: 61
1065 22:14:16.232429
1066 22:14:16.232510 Set Vref, RX VrefLevel [Byte0]: 62
1067 22:14:16.235470 [Byte1]: 62
1068 22:14:16.239884
1069 22:14:16.239964 Set Vref, RX VrefLevel [Byte0]: 63
1070 22:14:16.243249 [Byte1]: 63
1071 22:14:16.247933
1072 22:14:16.248014 Set Vref, RX VrefLevel [Byte0]: 64
1073 22:14:16.251446 [Byte1]: 64
1074 22:14:16.255044
1075 22:14:16.255125 Set Vref, RX VrefLevel [Byte0]: 65
1076 22:14:16.258467 [Byte1]: 65
1077 22:14:16.262801
1078 22:14:16.262883 Set Vref, RX VrefLevel [Byte0]: 66
1079 22:14:16.266101 [Byte1]: 66
1080 22:14:16.270445
1081 22:14:16.270528 Set Vref, RX VrefLevel [Byte0]: 67
1082 22:14:16.273848 [Byte1]: 67
1083 22:14:16.277883
1084 22:14:16.277983 Set Vref, RX VrefLevel [Byte0]: 68
1085 22:14:16.281053 [Byte1]: 68
1086 22:14:16.285599
1087 22:14:16.285681 Set Vref, RX VrefLevel [Byte0]: 69
1088 22:14:16.289065 [Byte1]: 69
1089 22:14:16.293228
1090 22:14:16.293313 Set Vref, RX VrefLevel [Byte0]: 70
1091 22:14:16.296502 [Byte1]: 70
1092 22:14:16.300664
1093 22:14:16.300746 Set Vref, RX VrefLevel [Byte0]: 71
1094 22:14:16.304264 [Byte1]: 71
1095 22:14:16.308347
1096 22:14:16.308429 Set Vref, RX VrefLevel [Byte0]: 72
1097 22:14:16.311594 [Byte1]: 72
1098 22:14:16.316176
1099 22:14:16.316258 Set Vref, RX VrefLevel [Byte0]: 73
1100 22:14:16.319063 [Byte1]: 73
1101 22:14:16.323727
1102 22:14:16.323810 Final RX Vref Byte 0 = 58 to rank0
1103 22:14:16.326961 Final RX Vref Byte 1 = 59 to rank0
1104 22:14:16.330416 Final RX Vref Byte 0 = 58 to rank1
1105 22:14:16.333587 Final RX Vref Byte 1 = 59 to rank1==
1106 22:14:16.336852 Dram Type= 6, Freq= 0, CH_0, rank 0
1107 22:14:16.343461 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1108 22:14:16.343545 ==
1109 22:14:16.343611 DQS Delay:
1110 22:14:16.343672 DQS0 = 0, DQS1 = 0
1111 22:14:16.346692 DQM Delay:
1112 22:14:16.346774 DQM0 = 88, DQM1 = 76
1113 22:14:16.350519 DQ Delay:
1114 22:14:16.353748 DQ0 =88, DQ1 =92, DQ2 =88, DQ3 =84
1115 22:14:16.353831 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1116 22:14:16.357003 DQ8 =68, DQ9 =60, DQ10 =76, DQ11 =72
1117 22:14:16.363524 DQ12 =84, DQ13 =80, DQ14 =84, DQ15 =84
1118 22:14:16.363607
1119 22:14:16.363672
1120 22:14:16.370031 [DQSOSCAuto] RK0, (LSB)MR18= 0x322b, (MSB)MR19= 0x606, tDQSOscB0 = 398 ps tDQSOscB1 = 397 ps
1121 22:14:16.373577 CH0 RK0: MR19=606, MR18=322B
1122 22:14:16.380210 CH0_RK0: MR19=0x606, MR18=0x322B, DQSOSC=397, MR23=63, INC=93, DEC=62
1123 22:14:16.380293
1124 22:14:16.383506 ----->DramcWriteLeveling(PI) begin...
1125 22:14:16.383589 ==
1126 22:14:16.387202 Dram Type= 6, Freq= 0, CH_0, rank 1
1127 22:14:16.390403 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1128 22:14:16.390526 ==
1129 22:14:16.393585 Write leveling (Byte 0): 31 => 31
1130 22:14:16.396712 Write leveling (Byte 1): 25 => 25
1131 22:14:16.400513 DramcWriteLeveling(PI) end<-----
1132 22:14:16.400595
1133 22:14:16.400661 ==
1134 22:14:16.403341 Dram Type= 6, Freq= 0, CH_0, rank 1
1135 22:14:16.407393 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1136 22:14:16.407476 ==
1137 22:14:16.410553 [Gating] SW mode calibration
1138 22:14:16.416970 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1139 22:14:16.423670 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1140 22:14:16.426766 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1141 22:14:16.430194 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1142 22:14:16.436592 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1143 22:14:16.480604 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1144 22:14:16.481139 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1145 22:14:16.481222 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1146 22:14:16.481607 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1147 22:14:16.482297 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1148 22:14:16.482567 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1149 22:14:16.482821 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1150 22:14:16.482889 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1151 22:14:16.483129 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1152 22:14:16.483372 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1153 22:14:16.525090 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1154 22:14:16.525375 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1155 22:14:16.525450 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1156 22:14:16.525690 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1157 22:14:16.525754 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1158 22:14:16.525826 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1159 22:14:16.526510 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 22:14:16.526593 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 22:14:16.526925 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 22:14:16.527187 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 22:14:16.569075 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 22:14:16.569342 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 22:14:16.569416 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 22:14:16.569658 0 9 8 | B1->B0 | 2323 3434 | 1 1 | (1 1) (1 1)
1167 22:14:16.569733 0 9 12 | B1->B0 | 3333 3434 | 0 1 | (1 1) (1 1)
1168 22:14:16.569805 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1169 22:14:16.570164 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1170 22:14:16.570246 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1171 22:14:16.570493 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1172 22:14:16.570562 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1173 22:14:16.583431 0 10 4 | B1->B0 | 3434 3131 | 1 1 | (1 0) (1 0)
1174 22:14:16.583722 0 10 8 | B1->B0 | 2f2f 2525 | 0 0 | (0 0) (0 0)
1175 22:14:16.583794 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 22:14:16.587005 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 22:14:16.590251 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 22:14:16.593182 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 22:14:16.596595 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 22:14:16.603672 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1181 22:14:16.607061 0 11 4 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
1182 22:14:16.609788 0 11 8 | B1->B0 | 3535 4646 | 0 0 | (0 0) (0 0)
1183 22:14:16.616773 0 11 12 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
1184 22:14:16.619806 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1185 22:14:16.623517 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1186 22:14:16.627637 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1187 22:14:16.634844 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1188 22:14:16.638237 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1189 22:14:16.642003 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1190 22:14:16.645048 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1191 22:14:16.652163 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1192 22:14:16.655386 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1193 22:14:16.658829 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1194 22:14:16.665517 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1195 22:14:16.668745 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1196 22:14:16.671937 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1197 22:14:16.678707 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1198 22:14:16.682263 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1199 22:14:16.685639 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1200 22:14:16.691734 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1201 22:14:16.695063 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1202 22:14:16.698816 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1203 22:14:16.705282 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 22:14:16.708359 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 22:14:16.712109 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1206 22:14:16.718821 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1207 22:14:16.718907 Total UI for P1: 0, mck2ui 16
1208 22:14:16.722168 best dqsien dly found for B0: ( 0, 14, 4)
1209 22:14:16.728808 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1210 22:14:16.731696 Total UI for P1: 0, mck2ui 16
1211 22:14:16.734874 best dqsien dly found for B1: ( 0, 14, 8)
1212 22:14:16.738565 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1213 22:14:16.742030 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1214 22:14:16.742104
1215 22:14:16.745194 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1216 22:14:16.748163 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1217 22:14:16.751376 [Gating] SW calibration Done
1218 22:14:16.751480 ==
1219 22:14:16.754925 Dram Type= 6, Freq= 0, CH_0, rank 1
1220 22:14:16.758349 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1221 22:14:16.758421 ==
1222 22:14:16.761888 RX Vref Scan: 0
1223 22:14:16.761989
1224 22:14:16.764698 RX Vref 0 -> 0, step: 1
1225 22:14:16.764778
1226 22:14:16.764841 RX Delay -130 -> 252, step: 16
1227 22:14:16.771409 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1228 22:14:16.774527 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
1229 22:14:16.777953 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1230 22:14:16.781531 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1231 22:14:16.784553 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1232 22:14:16.791629 iDelay=206, Bit 5, Center 69 (-50 ~ 189) 240
1233 22:14:16.794685 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1234 22:14:16.798192 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
1235 22:14:16.801277 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1236 22:14:16.804603 iDelay=206, Bit 9, Center 61 (-50 ~ 173) 224
1237 22:14:16.811081 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
1238 22:14:16.814904 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1239 22:14:16.818037 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1240 22:14:16.820969 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1241 22:14:16.827467 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1242 22:14:16.831176 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1243 22:14:16.831259 ==
1244 22:14:16.834341 Dram Type= 6, Freq= 0, CH_0, rank 1
1245 22:14:16.837522 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1246 22:14:16.837592 ==
1247 22:14:16.837661 DQS Delay:
1248 22:14:16.841086 DQS0 = 0, DQS1 = 0
1249 22:14:16.841157 DQM Delay:
1250 22:14:16.844185 DQM0 = 85, DQM1 = 77
1251 22:14:16.844254 DQ Delay:
1252 22:14:16.847780 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =85
1253 22:14:16.851062 DQ4 =93, DQ5 =69, DQ6 =93, DQ7 =93
1254 22:14:16.854401 DQ8 =69, DQ9 =61, DQ10 =77, DQ11 =69
1255 22:14:16.857745 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1256 22:14:16.857816
1257 22:14:16.857886
1258 22:14:16.857980 ==
1259 22:14:16.861371 Dram Type= 6, Freq= 0, CH_0, rank 1
1260 22:14:16.864307 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1261 22:14:16.867592 ==
1262 22:14:16.867662
1263 22:14:16.867747
1264 22:14:16.867824 TX Vref Scan disable
1265 22:14:16.870857 == TX Byte 0 ==
1266 22:14:16.874361 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1267 22:14:16.877478 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1268 22:14:16.880647 == TX Byte 1 ==
1269 22:14:16.883896 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1270 22:14:16.891186 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1271 22:14:16.891262 ==
1272 22:14:16.894004 Dram Type= 6, Freq= 0, CH_0, rank 1
1273 22:14:16.897401 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1274 22:14:16.897472 ==
1275 22:14:16.910363 TX Vref=22, minBit 0, minWin=27, winSum=439
1276 22:14:16.913561 TX Vref=24, minBit 1, minWin=27, winSum=446
1277 22:14:16.917229 TX Vref=26, minBit 1, minWin=27, winSum=445
1278 22:14:16.920302 TX Vref=28, minBit 1, minWin=27, winSum=450
1279 22:14:16.923502 TX Vref=30, minBit 0, minWin=28, winSum=454
1280 22:14:16.930246 TX Vref=32, minBit 1, minWin=27, winSum=451
1281 22:14:16.933583 [TxChooseVref] Worse bit 0, Min win 28, Win sum 454, Final Vref 30
1282 22:14:16.933685
1283 22:14:16.936914 Final TX Range 1 Vref 30
1284 22:14:16.937039
1285 22:14:16.937167 ==
1286 22:14:16.940485 Dram Type= 6, Freq= 0, CH_0, rank 1
1287 22:14:16.943483 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1288 22:14:16.943565 ==
1289 22:14:16.946631
1290 22:14:16.946727
1291 22:14:16.946805 TX Vref Scan disable
1292 22:14:16.950757 == TX Byte 0 ==
1293 22:14:16.953928 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1294 22:14:16.960336 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1295 22:14:16.960416 == TX Byte 1 ==
1296 22:14:16.963384 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1297 22:14:16.970092 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1298 22:14:16.970209
1299 22:14:16.970272 [DATLAT]
1300 22:14:16.970331 Freq=800, CH0 RK1
1301 22:14:16.970387
1302 22:14:16.973723 DATLAT Default: 0xa
1303 22:14:16.973802 0, 0xFFFF, sum = 0
1304 22:14:16.976626 1, 0xFFFF, sum = 0
1305 22:14:16.980020 2, 0xFFFF, sum = 0
1306 22:14:16.980121 3, 0xFFFF, sum = 0
1307 22:14:16.983277 4, 0xFFFF, sum = 0
1308 22:14:16.983357 5, 0xFFFF, sum = 0
1309 22:14:16.986559 6, 0xFFFF, sum = 0
1310 22:14:16.986639 7, 0xFFFF, sum = 0
1311 22:14:16.990150 8, 0xFFFF, sum = 0
1312 22:14:16.990230 9, 0x0, sum = 1
1313 22:14:16.993199 10, 0x0, sum = 2
1314 22:14:16.993279 11, 0x0, sum = 3
1315 22:14:16.993343 12, 0x0, sum = 4
1316 22:14:16.996877 best_step = 10
1317 22:14:16.996988
1318 22:14:16.997050 ==
1319 22:14:16.999997 Dram Type= 6, Freq= 0, CH_0, rank 1
1320 22:14:17.003319 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1321 22:14:17.003437 ==
1322 22:14:17.007027 RX Vref Scan: 0
1323 22:14:17.007121
1324 22:14:17.010183 RX Vref 0 -> 0, step: 1
1325 22:14:17.010262
1326 22:14:17.010323 RX Delay -95 -> 252, step: 8
1327 22:14:17.017157 iDelay=209, Bit 0, Center 84 (-23 ~ 192) 216
1328 22:14:17.020287 iDelay=209, Bit 1, Center 92 (-15 ~ 200) 216
1329 22:14:17.023508 iDelay=209, Bit 2, Center 84 (-23 ~ 192) 216
1330 22:14:17.027055 iDelay=209, Bit 3, Center 80 (-31 ~ 192) 224
1331 22:14:17.030193 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
1332 22:14:17.036881 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1333 22:14:17.040442 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1334 22:14:17.043739 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1335 22:14:17.047046 iDelay=209, Bit 8, Center 64 (-47 ~ 176) 224
1336 22:14:17.050513 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
1337 22:14:17.057028 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1338 22:14:17.060414 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
1339 22:14:17.063750 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
1340 22:14:17.066881 iDelay=209, Bit 13, Center 80 (-31 ~ 192) 224
1341 22:14:17.073822 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1342 22:14:17.077090 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
1343 22:14:17.077167 ==
1344 22:14:17.080120 Dram Type= 6, Freq= 0, CH_0, rank 1
1345 22:14:17.083730 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1346 22:14:17.083809 ==
1347 22:14:17.083872 DQS Delay:
1348 22:14:17.086641 DQS0 = 0, DQS1 = 0
1349 22:14:17.086720 DQM Delay:
1350 22:14:17.090131 DQM0 = 87, DQM1 = 76
1351 22:14:17.090235 DQ Delay:
1352 22:14:17.093177 DQ0 =84, DQ1 =92, DQ2 =84, DQ3 =80
1353 22:14:17.096794 DQ4 =92, DQ5 =76, DQ6 =96, DQ7 =96
1354 22:14:17.099967 DQ8 =64, DQ9 =64, DQ10 =80, DQ11 =68
1355 22:14:17.103272 DQ12 =80, DQ13 =80, DQ14 =88, DQ15 =84
1356 22:14:17.103368
1357 22:14:17.103446
1358 22:14:17.113049 [DQSOSCAuto] RK1, (LSB)MR18= 0x2621, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 400 ps
1359 22:14:17.113132 CH0 RK1: MR19=606, MR18=2621
1360 22:14:17.119797 CH0_RK1: MR19=0x606, MR18=0x2621, DQSOSC=400, MR23=63, INC=92, DEC=61
1361 22:14:17.123130 [RxdqsGatingPostProcess] freq 800
1362 22:14:17.129475 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1363 22:14:17.133035 Pre-setting of DQS Precalculation
1364 22:14:17.136217 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1365 22:14:17.136320 ==
1366 22:14:17.139895 Dram Type= 6, Freq= 0, CH_1, rank 0
1367 22:14:17.146393 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1368 22:14:17.146474 ==
1369 22:14:17.149555 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1370 22:14:17.155826 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1371 22:14:17.165447 [CA 0] Center 37 (6~68) winsize 63
1372 22:14:17.168855 [CA 1] Center 37 (6~68) winsize 63
1373 22:14:17.172043 [CA 2] Center 35 (5~65) winsize 61
1374 22:14:17.175365 [CA 3] Center 34 (4~65) winsize 62
1375 22:14:17.179241 [CA 4] Center 34 (4~65) winsize 62
1376 22:14:17.182172 [CA 5] Center 34 (3~65) winsize 63
1377 22:14:17.182250
1378 22:14:17.185158 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1379 22:14:17.185247
1380 22:14:17.188422 [CATrainingPosCal] consider 1 rank data
1381 22:14:17.192275 u2DelayCellTimex100 = 270/100 ps
1382 22:14:17.195623 CA0 delay=37 (6~68),Diff = 3 PI (21 cell)
1383 22:14:17.198735 CA1 delay=37 (6~68),Diff = 3 PI (21 cell)
1384 22:14:17.205416 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1385 22:14:17.208748 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1386 22:14:17.211503 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1387 22:14:17.215173 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1388 22:14:17.215254
1389 22:14:17.218342 CA PerBit enable=1, Macro0, CA PI delay=34
1390 22:14:17.218450
1391 22:14:17.221597 [CBTSetCACLKResult] CA Dly = 34
1392 22:14:17.221708 CS Dly: 4 (0~35)
1393 22:14:17.224750 ==
1394 22:14:17.228550 Dram Type= 6, Freq= 0, CH_1, rank 1
1395 22:14:17.231643 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1396 22:14:17.231744 ==
1397 22:14:17.234697 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1398 22:14:17.241302 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1399 22:14:17.251400 [CA 0] Center 36 (6~67) winsize 62
1400 22:14:17.254732 [CA 1] Center 36 (6~67) winsize 62
1401 22:14:17.258374 [CA 2] Center 34 (4~65) winsize 62
1402 22:14:17.261652 [CA 3] Center 34 (3~65) winsize 63
1403 22:14:17.264585 [CA 4] Center 34 (4~65) winsize 62
1404 22:14:17.268154 [CA 5] Center 33 (3~64) winsize 62
1405 22:14:17.268266
1406 22:14:17.271291 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1407 22:14:17.271396
1408 22:14:17.274840 [CATrainingPosCal] consider 2 rank data
1409 22:14:17.278421 u2DelayCellTimex100 = 270/100 ps
1410 22:14:17.281595 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1411 22:14:17.288198 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1412 22:14:17.291531 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
1413 22:14:17.295464 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1414 22:14:17.299428 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1415 22:14:17.302668 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1416 22:14:17.302751
1417 22:14:17.306210 CA PerBit enable=1, Macro0, CA PI delay=33
1418 22:14:17.306292
1419 22:14:17.309765 [CBTSetCACLKResult] CA Dly = 33
1420 22:14:17.309850 CS Dly: 5 (0~37)
1421 22:14:17.309916
1422 22:14:17.313324 ----->DramcWriteLeveling(PI) begin...
1423 22:14:17.313412 ==
1424 22:14:17.317565 Dram Type= 6, Freq= 0, CH_1, rank 0
1425 22:14:17.321249 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1426 22:14:17.321356 ==
1427 22:14:17.324509 Write leveling (Byte 0): 26 => 26
1428 22:14:17.327623 Write leveling (Byte 1): 27 => 27
1429 22:14:17.331225 DramcWriteLeveling(PI) end<-----
1430 22:14:17.331305
1431 22:14:17.331368 ==
1432 22:14:17.334393 Dram Type= 6, Freq= 0, CH_1, rank 0
1433 22:14:17.337689 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1434 22:14:17.337797 ==
1435 22:14:17.341116 [Gating] SW mode calibration
1436 22:14:17.347562 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1437 22:14:17.354639 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1438 22:14:17.357690 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1439 22:14:17.361002 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1440 22:14:17.367798 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1441 22:14:17.370832 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1442 22:14:17.374250 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1443 22:14:17.380903 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1444 22:14:17.384421 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1445 22:14:17.387463 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1446 22:14:17.391157 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1447 22:14:17.397397 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1448 22:14:17.400603 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1449 22:14:17.404281 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1450 22:14:17.410608 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1451 22:14:17.414212 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1452 22:14:17.417417 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1453 22:14:17.423680 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 22:14:17.427394 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1455 22:14:17.430444 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1456 22:14:17.437427 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1457 22:14:17.440761 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 22:14:17.444167 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 22:14:17.450320 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 22:14:17.454102 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 22:14:17.457210 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 22:14:17.463688 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 22:14:17.467038 0 9 4 | B1->B0 | 2323 2323 | 0 1 | (0 0) (1 1)
1464 22:14:17.470304 0 9 8 | B1->B0 | 2929 3434 | 1 1 | (1 1) (1 1)
1465 22:14:17.477271 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1466 22:14:17.480661 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1467 22:14:17.484189 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1468 22:14:17.490642 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1469 22:14:17.493536 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1470 22:14:17.496968 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1471 22:14:17.504566 0 10 4 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
1472 22:14:17.506828 0 10 8 | B1->B0 | 2828 2323 | 1 0 | (1 0) (0 0)
1473 22:14:17.510345 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 22:14:17.516908 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 22:14:17.520110 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 22:14:17.523557 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 22:14:17.529984 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1478 22:14:17.533805 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1479 22:14:17.536951 0 11 4 | B1->B0 | 2626 2e2e | 0 0 | (0 0) (0 0)
1480 22:14:17.544083 0 11 8 | B1->B0 | 4040 4242 | 0 0 | (0 0) (1 1)
1481 22:14:17.546793 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1482 22:14:17.550411 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1483 22:14:17.553629 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1484 22:14:17.560083 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1485 22:14:17.563583 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1486 22:14:17.566990 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1487 22:14:17.573094 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1488 22:14:17.576551 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1489 22:14:17.580017 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1490 22:14:17.586487 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1491 22:14:17.590149 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1492 22:14:17.593171 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1493 22:14:17.600284 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1494 22:14:17.603745 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1495 22:14:17.607022 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1496 22:14:17.613098 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1497 22:14:17.616689 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1498 22:14:17.619628 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1499 22:14:17.626444 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1500 22:14:17.630239 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1501 22:14:17.633066 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1502 22:14:17.640372 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 22:14:17.643083 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1504 22:14:17.646834 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1505 22:14:17.653048 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1506 22:14:17.653130 Total UI for P1: 0, mck2ui 16
1507 22:14:17.659742 best dqsien dly found for B0: ( 0, 14, 6)
1508 22:14:17.659824 Total UI for P1: 0, mck2ui 16
1509 22:14:17.662886 best dqsien dly found for B1: ( 0, 14, 6)
1510 22:14:17.669667 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1511 22:14:17.673127 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1512 22:14:17.673307
1513 22:14:17.676237 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1514 22:14:17.679480 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1515 22:14:17.682767 [Gating] SW calibration Done
1516 22:14:17.682848 ==
1517 22:14:17.686140 Dram Type= 6, Freq= 0, CH_1, rank 0
1518 22:14:17.689774 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1519 22:14:17.689856 ==
1520 22:14:17.692774 RX Vref Scan: 0
1521 22:14:17.692938
1522 22:14:17.693064 RX Vref 0 -> 0, step: 1
1523 22:14:17.693162
1524 22:14:17.696311 RX Delay -130 -> 252, step: 16
1525 22:14:17.699497 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1526 22:14:17.705963 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1527 22:14:17.709609 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1528 22:14:17.713243 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1529 22:14:17.716222 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1530 22:14:17.719421 iDelay=222, Bit 5, Center 93 (-18 ~ 205) 224
1531 22:14:17.726157 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1532 22:14:17.729159 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1533 22:14:17.732524 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1534 22:14:17.735696 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1535 22:14:17.739329 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1536 22:14:17.745832 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1537 22:14:17.748944 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1538 22:14:17.752519 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1539 22:14:17.755787 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1540 22:14:17.762562 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1541 22:14:17.762644 ==
1542 22:14:17.765610 Dram Type= 6, Freq= 0, CH_1, rank 0
1543 22:14:17.768988 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1544 22:14:17.769071 ==
1545 22:14:17.769137 DQS Delay:
1546 22:14:17.772383 DQS0 = 0, DQS1 = 0
1547 22:14:17.772482 DQM Delay:
1548 22:14:17.775514 DQM0 = 87, DQM1 = 81
1549 22:14:17.775596 DQ Delay:
1550 22:14:17.779092 DQ0 =93, DQ1 =85, DQ2 =69, DQ3 =85
1551 22:14:17.782419 DQ4 =85, DQ5 =93, DQ6 =101, DQ7 =85
1552 22:14:17.785345 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =77
1553 22:14:17.789062 DQ12 =93, DQ13 =85, DQ14 =85, DQ15 =85
1554 22:14:17.789144
1555 22:14:17.789209
1556 22:14:17.789269 ==
1557 22:14:17.792358 Dram Type= 6, Freq= 0, CH_1, rank 0
1558 22:14:17.795437 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1559 22:14:17.795519 ==
1560 22:14:17.795583
1561 22:14:17.795643
1562 22:14:17.798779 TX Vref Scan disable
1563 22:14:17.802191 == TX Byte 0 ==
1564 22:14:17.805651 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1565 22:14:17.809006 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1566 22:14:17.812194 == TX Byte 1 ==
1567 22:14:17.815555 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1568 22:14:17.818860 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1569 22:14:17.818942 ==
1570 22:14:17.821946 Dram Type= 6, Freq= 0, CH_1, rank 0
1571 22:14:17.828610 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1572 22:14:17.828692 ==
1573 22:14:17.840434 TX Vref=22, minBit 2, minWin=27, winSum=443
1574 22:14:17.843507 TX Vref=24, minBit 0, minWin=27, winSum=447
1575 22:14:17.847000 TX Vref=26, minBit 6, minWin=27, winSum=452
1576 22:14:17.849808 TX Vref=28, minBit 0, minWin=28, winSum=459
1577 22:14:17.853864 TX Vref=30, minBit 5, minWin=27, winSum=454
1578 22:14:17.859819 TX Vref=32, minBit 0, minWin=27, winSum=449
1579 22:14:17.863338 [TxChooseVref] Worse bit 0, Min win 28, Win sum 459, Final Vref 28
1580 22:14:17.863444
1581 22:14:17.867249 Final TX Range 1 Vref 28
1582 22:14:17.867347
1583 22:14:17.867436 ==
1584 22:14:17.870315 Dram Type= 6, Freq= 0, CH_1, rank 0
1585 22:14:17.874065 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1586 22:14:17.874165 ==
1587 22:14:17.874254
1588 22:14:17.874349
1589 22:14:17.877105 TX Vref Scan disable
1590 22:14:17.880812 == TX Byte 0 ==
1591 22:14:17.884079 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1592 22:14:17.887254 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1593 22:14:17.890968 == TX Byte 1 ==
1594 22:14:17.893713 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1595 22:14:17.897399 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1596 22:14:17.897482
1597 22:14:17.900489 [DATLAT]
1598 22:14:17.900570 Freq=800, CH1 RK0
1599 22:14:17.900635
1600 22:14:17.903807 DATLAT Default: 0xa
1601 22:14:17.903908 0, 0xFFFF, sum = 0
1602 22:14:17.907384 1, 0xFFFF, sum = 0
1603 22:14:17.907466 2, 0xFFFF, sum = 0
1604 22:14:17.910775 3, 0xFFFF, sum = 0
1605 22:14:17.910858 4, 0xFFFF, sum = 0
1606 22:14:17.913890 5, 0xFFFF, sum = 0
1607 22:14:17.913989 6, 0xFFFF, sum = 0
1608 22:14:17.917342 7, 0xFFFF, sum = 0
1609 22:14:17.917428 8, 0xFFFF, sum = 0
1610 22:14:17.920567 9, 0x0, sum = 1
1611 22:14:17.920680 10, 0x0, sum = 2
1612 22:14:17.923576 11, 0x0, sum = 3
1613 22:14:17.923676 12, 0x0, sum = 4
1614 22:14:17.927327 best_step = 10
1615 22:14:17.927404
1616 22:14:17.927467 ==
1617 22:14:17.930320 Dram Type= 6, Freq= 0, CH_1, rank 0
1618 22:14:17.933753 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1619 22:14:17.933869 ==
1620 22:14:17.937300 RX Vref Scan: 1
1621 22:14:17.937375
1622 22:14:17.937441 Set Vref Range= 32 -> 127
1623 22:14:17.937516
1624 22:14:17.940166 RX Vref 32 -> 127, step: 1
1625 22:14:17.940240
1626 22:14:17.943433 RX Delay -95 -> 252, step: 8
1627 22:14:17.943501
1628 22:14:17.946787 Set Vref, RX VrefLevel [Byte0]: 32
1629 22:14:17.950034 [Byte1]: 32
1630 22:14:17.950117
1631 22:14:17.953670 Set Vref, RX VrefLevel [Byte0]: 33
1632 22:14:17.957014 [Byte1]: 33
1633 22:14:17.960794
1634 22:14:17.960901 Set Vref, RX VrefLevel [Byte0]: 34
1635 22:14:17.963886 [Byte1]: 34
1636 22:14:17.967991
1637 22:14:17.968116 Set Vref, RX VrefLevel [Byte0]: 35
1638 22:14:17.971772 [Byte1]: 35
1639 22:14:17.975561
1640 22:14:17.975675 Set Vref, RX VrefLevel [Byte0]: 36
1641 22:14:17.978932 [Byte1]: 36
1642 22:14:17.983242
1643 22:14:17.983322 Set Vref, RX VrefLevel [Byte0]: 37
1644 22:14:17.986483 [Byte1]: 37
1645 22:14:17.990600
1646 22:14:17.990679 Set Vref, RX VrefLevel [Byte0]: 38
1647 22:14:17.994107 [Byte1]: 38
1648 22:14:17.998178
1649 22:14:17.998265 Set Vref, RX VrefLevel [Byte0]: 39
1650 22:14:18.001871 [Byte1]: 39
1651 22:14:18.005868
1652 22:14:18.005942 Set Vref, RX VrefLevel [Byte0]: 40
1653 22:14:18.009215 [Byte1]: 40
1654 22:14:18.013922
1655 22:14:18.013997 Set Vref, RX VrefLevel [Byte0]: 41
1656 22:14:18.016701 [Byte1]: 41
1657 22:14:18.021263
1658 22:14:18.021336 Set Vref, RX VrefLevel [Byte0]: 42
1659 22:14:18.024497 [Byte1]: 42
1660 22:14:18.028890
1661 22:14:18.028966 Set Vref, RX VrefLevel [Byte0]: 43
1662 22:14:18.032381 [Byte1]: 43
1663 22:14:18.036529
1664 22:14:18.036615 Set Vref, RX VrefLevel [Byte0]: 44
1665 22:14:18.040027 [Byte1]: 44
1666 22:14:18.044551
1667 22:14:18.044637 Set Vref, RX VrefLevel [Byte0]: 45
1668 22:14:18.047119 [Byte1]: 45
1669 22:14:18.051416
1670 22:14:18.051498 Set Vref, RX VrefLevel [Byte0]: 46
1671 22:14:18.055180 [Byte1]: 46
1672 22:14:18.059469
1673 22:14:18.059551 Set Vref, RX VrefLevel [Byte0]: 47
1674 22:14:18.062693 [Byte1]: 47
1675 22:14:18.066886
1676 22:14:18.066968 Set Vref, RX VrefLevel [Byte0]: 48
1677 22:14:18.070398 [Byte1]: 48
1678 22:14:18.074686
1679 22:14:18.074768 Set Vref, RX VrefLevel [Byte0]: 49
1680 22:14:18.077824 [Byte1]: 49
1681 22:14:18.081965
1682 22:14:18.082046 Set Vref, RX VrefLevel [Byte0]: 50
1683 22:14:18.085350 [Byte1]: 50
1684 22:14:18.089513
1685 22:14:18.089596 Set Vref, RX VrefLevel [Byte0]: 51
1686 22:14:18.092869 [Byte1]: 51
1687 22:14:18.097124
1688 22:14:18.097210 Set Vref, RX VrefLevel [Byte0]: 52
1689 22:14:18.100489 [Byte1]: 52
1690 22:14:18.105064
1691 22:14:18.105145 Set Vref, RX VrefLevel [Byte0]: 53
1692 22:14:18.108242 [Byte1]: 53
1693 22:14:18.112289
1694 22:14:18.112375 Set Vref, RX VrefLevel [Byte0]: 54
1695 22:14:18.115764 [Byte1]: 54
1696 22:14:18.119826
1697 22:14:18.119925 Set Vref, RX VrefLevel [Byte0]: 55
1698 22:14:18.123355 [Byte1]: 55
1699 22:14:18.127390
1700 22:14:18.127463 Set Vref, RX VrefLevel [Byte0]: 56
1701 22:14:18.131076 [Byte1]: 56
1702 22:14:18.135321
1703 22:14:18.135400 Set Vref, RX VrefLevel [Byte0]: 57
1704 22:14:18.138385 [Byte1]: 57
1705 22:14:18.142721
1706 22:14:18.142790 Set Vref, RX VrefLevel [Byte0]: 58
1707 22:14:18.146403 [Byte1]: 58
1708 22:14:18.150530
1709 22:14:18.150604 Set Vref, RX VrefLevel [Byte0]: 59
1710 22:14:18.153772 [Byte1]: 59
1711 22:14:18.158066
1712 22:14:18.158144 Set Vref, RX VrefLevel [Byte0]: 60
1713 22:14:18.161491 [Byte1]: 60
1714 22:14:18.165887
1715 22:14:18.165957 Set Vref, RX VrefLevel [Byte0]: 61
1716 22:14:18.169019 [Byte1]: 61
1717 22:14:18.172994
1718 22:14:18.173065 Set Vref, RX VrefLevel [Byte0]: 62
1719 22:14:18.176766 [Byte1]: 62
1720 22:14:18.180946
1721 22:14:18.181022 Set Vref, RX VrefLevel [Byte0]: 63
1722 22:14:18.184277 [Byte1]: 63
1723 22:14:18.188302
1724 22:14:18.188373 Set Vref, RX VrefLevel [Byte0]: 64
1725 22:14:18.191908 [Byte1]: 64
1726 22:14:18.196061
1727 22:14:18.199083 Set Vref, RX VrefLevel [Byte0]: 65
1728 22:14:18.202482 [Byte1]: 65
1729 22:14:18.202574
1730 22:14:18.205541 Set Vref, RX VrefLevel [Byte0]: 66
1731 22:14:18.209304 [Byte1]: 66
1732 22:14:18.209374
1733 22:14:18.212286 Set Vref, RX VrefLevel [Byte0]: 67
1734 22:14:18.215851 [Byte1]: 67
1735 22:14:18.215948
1736 22:14:18.218965 Set Vref, RX VrefLevel [Byte0]: 68
1737 22:14:18.222163 [Byte1]: 68
1738 22:14:18.226141
1739 22:14:18.226232 Set Vref, RX VrefLevel [Byte0]: 69
1740 22:14:18.229569 [Byte1]: 69
1741 22:14:18.234010
1742 22:14:18.234081 Set Vref, RX VrefLevel [Byte0]: 70
1743 22:14:18.238253 [Byte1]: 70
1744 22:14:18.241592
1745 22:14:18.241665 Set Vref, RX VrefLevel [Byte0]: 71
1746 22:14:18.244914 [Byte1]: 71
1747 22:14:18.248990
1748 22:14:18.249060 Set Vref, RX VrefLevel [Byte0]: 72
1749 22:14:18.252578 [Byte1]: 72
1750 22:14:18.256801
1751 22:14:18.256871 Set Vref, RX VrefLevel [Byte0]: 73
1752 22:14:18.259937 [Byte1]: 73
1753 22:14:18.264319
1754 22:14:18.264392 Set Vref, RX VrefLevel [Byte0]: 74
1755 22:14:18.267915 [Byte1]: 74
1756 22:14:18.271954
1757 22:14:18.272028 Set Vref, RX VrefLevel [Byte0]: 75
1758 22:14:18.275085 [Byte1]: 75
1759 22:14:18.279551
1760 22:14:18.279633 Final RX Vref Byte 0 = 57 to rank0
1761 22:14:18.282655 Final RX Vref Byte 1 = 57 to rank0
1762 22:14:18.286297 Final RX Vref Byte 0 = 57 to rank1
1763 22:14:18.289552 Final RX Vref Byte 1 = 57 to rank1==
1764 22:14:18.293181 Dram Type= 6, Freq= 0, CH_1, rank 0
1765 22:14:18.299534 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1766 22:14:18.299617 ==
1767 22:14:18.299682 DQS Delay:
1768 22:14:18.299743 DQS0 = 0, DQS1 = 0
1769 22:14:18.302795 DQM Delay:
1770 22:14:18.302864 DQM0 = 85, DQM1 = 80
1771 22:14:18.306282 DQ Delay:
1772 22:14:18.309783 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
1773 22:14:18.309884 DQ4 =80, DQ5 =96, DQ6 =96, DQ7 =80
1774 22:14:18.313029 DQ8 =68, DQ9 =72, DQ10 =76, DQ11 =72
1775 22:14:18.319358 DQ12 =88, DQ13 =88, DQ14 =88, DQ15 =88
1776 22:14:18.319435
1777 22:14:18.319499
1778 22:14:18.325797 [DQSOSCAuto] RK0, (LSB)MR18= 0x192c, (MSB)MR19= 0x606, tDQSOscB0 = 398 ps tDQSOscB1 = 403 ps
1779 22:14:18.329089 CH1 RK0: MR19=606, MR18=192C
1780 22:14:18.335974 CH1_RK0: MR19=0x606, MR18=0x192C, DQSOSC=398, MR23=63, INC=93, DEC=62
1781 22:14:18.336111
1782 22:14:18.339165 ----->DramcWriteLeveling(PI) begin...
1783 22:14:18.339241 ==
1784 22:14:18.342376 Dram Type= 6, Freq= 0, CH_1, rank 1
1785 22:14:18.345980 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1786 22:14:18.346072 ==
1787 22:14:18.349126 Write leveling (Byte 0): 26 => 26
1788 22:14:18.352615 Write leveling (Byte 1): 28 => 28
1789 22:14:18.355564 DramcWriteLeveling(PI) end<-----
1790 22:14:18.355639
1791 22:14:18.355716 ==
1792 22:14:18.359256 Dram Type= 6, Freq= 0, CH_1, rank 1
1793 22:14:18.361993 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1794 22:14:18.362070 ==
1795 22:14:18.365607 [Gating] SW mode calibration
1796 22:14:18.372472 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1797 22:14:18.379095 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1798 22:14:18.382460 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1799 22:14:18.388601 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1800 22:14:18.392246 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1801 22:14:18.395415 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1802 22:14:18.402109 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1803 22:14:18.405378 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1804 22:14:18.408515 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1805 22:14:18.412048 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1806 22:14:18.418966 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1807 22:14:18.422055 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1808 22:14:18.425639 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1809 22:14:18.431940 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1810 22:14:18.435450 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1811 22:14:18.438462 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1812 22:14:18.445021 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1813 22:14:18.448719 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1814 22:14:18.451731 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1815 22:14:18.458208 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1816 22:14:18.461856 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 22:14:18.465214 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 22:14:18.471911 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 22:14:18.475286 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 22:14:18.478121 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 22:14:18.484930 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 22:14:18.488493 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 22:14:18.491652 0 9 4 | B1->B0 | 2323 2e2e | 0 1 | (0 0) (1 1)
1824 22:14:18.498036 0 9 8 | B1->B0 | 2f2f 3434 | 1 1 | (1 1) (1 1)
1825 22:14:18.501585 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1826 22:14:18.504584 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1827 22:14:18.511485 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1828 22:14:18.514575 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1829 22:14:18.518153 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1830 22:14:18.524464 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1831 22:14:18.527521 0 10 4 | B1->B0 | 3333 2b2b | 1 1 | (0 0) (1 0)
1832 22:14:18.530914 0 10 8 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
1833 22:14:18.538150 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 22:14:18.541029 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 22:14:18.544121 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 22:14:18.551298 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 22:14:18.554400 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 22:14:18.557347 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 22:14:18.564075 0 11 4 | B1->B0 | 2424 3f3f | 1 0 | (0 0) (1 1)
1840 22:14:18.567588 0 11 8 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
1841 22:14:18.570833 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1842 22:14:18.577488 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1843 22:14:18.580688 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1844 22:14:18.584013 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1845 22:14:18.590860 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1846 22:14:18.594060 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1847 22:14:18.597339 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1848 22:14:18.603619 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1849 22:14:18.607404 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1850 22:14:18.610624 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1851 22:14:18.617246 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1852 22:14:18.620935 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1853 22:14:18.623907 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1854 22:14:18.630824 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1855 22:14:18.633724 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1856 22:14:18.636912 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1857 22:14:18.643959 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1858 22:14:18.647079 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1859 22:14:18.650408 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1860 22:14:18.654112 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1861 22:14:18.660456 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1862 22:14:18.663840 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1863 22:14:18.666959 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1864 22:14:18.673452 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1865 22:14:18.676775 Total UI for P1: 0, mck2ui 16
1866 22:14:18.680328 best dqsien dly found for B0: ( 0, 14, 2)
1867 22:14:18.683533 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1868 22:14:18.686766 Total UI for P1: 0, mck2ui 16
1869 22:14:18.690603 best dqsien dly found for B1: ( 0, 14, 8)
1870 22:14:18.693354 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1871 22:14:18.696983 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1872 22:14:18.697064
1873 22:14:18.700005 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1874 22:14:18.703512 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1875 22:14:18.706675 [Gating] SW calibration Done
1876 22:14:18.706765 ==
1877 22:14:18.709865 Dram Type= 6, Freq= 0, CH_1, rank 1
1878 22:14:18.716561 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1879 22:14:18.716656 ==
1880 22:14:18.716763 RX Vref Scan: 0
1881 22:14:18.716854
1882 22:14:18.720307 RX Vref 0 -> 0, step: 1
1883 22:14:18.720387
1884 22:14:18.723115 RX Delay -130 -> 252, step: 16
1885 22:14:18.726694 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1886 22:14:18.729808 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
1887 22:14:18.733398 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1888 22:14:18.736660 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1889 22:14:18.743687 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1890 22:14:18.746599 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1891 22:14:18.749792 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1892 22:14:18.753111 iDelay=206, Bit 7, Center 85 (-34 ~ 205) 240
1893 22:14:18.756656 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1894 22:14:18.762963 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1895 22:14:18.766401 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1896 22:14:18.769491 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1897 22:14:18.772984 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224
1898 22:14:18.779893 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1899 22:14:18.783009 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1900 22:14:18.785937 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1901 22:14:18.786013 ==
1902 22:14:18.789567 Dram Type= 6, Freq= 0, CH_1, rank 1
1903 22:14:18.792534 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1904 22:14:18.792619 ==
1905 22:14:18.796174 DQS Delay:
1906 22:14:18.796259 DQS0 = 0, DQS1 = 0
1907 22:14:18.799420 DQM Delay:
1908 22:14:18.799505 DQM0 = 85, DQM1 = 81
1909 22:14:18.799590 DQ Delay:
1910 22:14:18.802410 DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =85
1911 22:14:18.806121 DQ4 =85, DQ5 =93, DQ6 =93, DQ7 =85
1912 22:14:18.809047 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =77
1913 22:14:18.812305 DQ12 =93, DQ13 =85, DQ14 =85, DQ15 =85
1914 22:14:18.812418
1915 22:14:18.812531
1916 22:14:18.815901 ==
1917 22:14:18.819487 Dram Type= 6, Freq= 0, CH_1, rank 1
1918 22:14:18.822286 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1919 22:14:18.822363 ==
1920 22:14:18.822443
1921 22:14:18.822538
1922 22:14:18.825963 TX Vref Scan disable
1923 22:14:18.826054 == TX Byte 0 ==
1924 22:14:18.832270 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1925 22:14:18.835616 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1926 22:14:18.835726 == TX Byte 1 ==
1927 22:14:18.842591 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1928 22:14:18.845772 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1929 22:14:18.845848 ==
1930 22:14:18.848882 Dram Type= 6, Freq= 0, CH_1, rank 1
1931 22:14:18.852453 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1932 22:14:18.852549 ==
1933 22:14:18.865673 TX Vref=22, minBit 1, minWin=27, winSum=448
1934 22:14:18.869018 TX Vref=24, minBit 5, minWin=27, winSum=451
1935 22:14:18.872579 TX Vref=26, minBit 1, minWin=27, winSum=451
1936 22:14:18.875788 TX Vref=28, minBit 5, minWin=27, winSum=455
1937 22:14:18.878684 TX Vref=30, minBit 1, minWin=27, winSum=451
1938 22:14:18.885296 TX Vref=32, minBit 5, minWin=27, winSum=455
1939 22:14:18.889151 [TxChooseVref] Worse bit 5, Min win 27, Win sum 455, Final Vref 28
1940 22:14:18.889225
1941 22:14:18.892209 Final TX Range 1 Vref 28
1942 22:14:18.892279
1943 22:14:18.892339 ==
1944 22:14:18.895403 Dram Type= 6, Freq= 0, CH_1, rank 1
1945 22:14:18.898440 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1946 22:14:18.902221 ==
1947 22:14:18.902324
1948 22:14:18.902411
1949 22:14:18.902497 TX Vref Scan disable
1950 22:14:18.905905 == TX Byte 0 ==
1951 22:14:18.909060 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1952 22:14:18.915423 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1953 22:14:18.915501 == TX Byte 1 ==
1954 22:14:18.919151 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1955 22:14:18.925718 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1956 22:14:18.925811
1957 22:14:18.925888 [DATLAT]
1958 22:14:18.925947 Freq=800, CH1 RK1
1959 22:14:18.926022
1960 22:14:18.928922 DATLAT Default: 0xa
1961 22:14:18.929019 0, 0xFFFF, sum = 0
1962 22:14:18.932000 1, 0xFFFF, sum = 0
1963 22:14:18.932144 2, 0xFFFF, sum = 0
1964 22:14:18.935789 3, 0xFFFF, sum = 0
1965 22:14:18.938866 4, 0xFFFF, sum = 0
1966 22:14:18.938987 5, 0xFFFF, sum = 0
1967 22:14:18.942221 6, 0xFFFF, sum = 0
1968 22:14:18.942331 7, 0xFFFF, sum = 0
1969 22:14:18.945790 8, 0xFFFF, sum = 0
1970 22:14:18.945880 9, 0x0, sum = 1
1971 22:14:18.945974 10, 0x0, sum = 2
1972 22:14:18.948830 11, 0x0, sum = 3
1973 22:14:18.948918 12, 0x0, sum = 4
1974 22:14:18.952427 best_step = 10
1975 22:14:18.952529
1976 22:14:18.952656 ==
1977 22:14:18.955727 Dram Type= 6, Freq= 0, CH_1, rank 1
1978 22:14:18.958712 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1979 22:14:18.958810 ==
1980 22:14:18.962011 RX Vref Scan: 0
1981 22:14:18.962107
1982 22:14:18.962195 RX Vref 0 -> 0, step: 1
1983 22:14:18.965411
1984 22:14:18.965479 RX Delay -95 -> 252, step: 8
1985 22:14:18.972606 iDelay=209, Bit 0, Center 92 (-23 ~ 208) 232
1986 22:14:18.975973 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
1987 22:14:18.979257 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
1988 22:14:18.982265 iDelay=209, Bit 3, Center 80 (-31 ~ 192) 224
1989 22:14:18.985464 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1990 22:14:18.992157 iDelay=209, Bit 5, Center 96 (-15 ~ 208) 224
1991 22:14:18.995395 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
1992 22:14:18.999170 iDelay=209, Bit 7, Center 84 (-31 ~ 200) 232
1993 22:14:19.002236 iDelay=209, Bit 8, Center 72 (-39 ~ 184) 224
1994 22:14:19.005542 iDelay=209, Bit 9, Center 72 (-39 ~ 184) 224
1995 22:14:19.012176 iDelay=209, Bit 10, Center 84 (-31 ~ 200) 232
1996 22:14:19.015892 iDelay=209, Bit 11, Center 80 (-31 ~ 192) 224
1997 22:14:19.019079 iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216
1998 22:14:19.022268 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
1999 22:14:19.028854 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
2000 22:14:19.032158 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
2001 22:14:19.032246 ==
2002 22:14:19.035274 Dram Type= 6, Freq= 0, CH_1, rank 1
2003 22:14:19.038837 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2004 22:14:19.038942 ==
2005 22:14:19.039032 DQS Delay:
2006 22:14:19.041986 DQS0 = 0, DQS1 = 0
2007 22:14:19.042057 DQM Delay:
2008 22:14:19.045850 DQM0 = 86, DQM1 = 83
2009 22:14:19.045920 DQ Delay:
2010 22:14:19.048808 DQ0 =92, DQ1 =84, DQ2 =76, DQ3 =80
2011 22:14:19.052369 DQ4 =88, DQ5 =96, DQ6 =92, DQ7 =84
2012 22:14:19.055178 DQ8 =72, DQ9 =72, DQ10 =84, DQ11 =80
2013 22:14:19.058914 DQ12 =92, DQ13 =88, DQ14 =88, DQ15 =88
2014 22:14:19.058998
2015 22:14:19.059063
2016 22:14:19.068544 [DQSOSCAuto] RK1, (LSB)MR18= 0x1e3a, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 402 ps
2017 22:14:19.068629 CH1 RK1: MR19=606, MR18=1E3A
2018 22:14:19.075124 CH1_RK1: MR19=0x606, MR18=0x1E3A, DQSOSC=395, MR23=63, INC=94, DEC=63
2019 22:14:19.078298 [RxdqsGatingPostProcess] freq 800
2020 22:14:19.085575 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2021 22:14:19.088739 Pre-setting of DQS Precalculation
2022 22:14:19.091777 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2023 22:14:19.098637 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2024 22:14:19.108570 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2025 22:14:19.108655
2026 22:14:19.108721
2027 22:14:19.111752 [Calibration Summary] 1600 Mbps
2028 22:14:19.111835 CH 0, Rank 0
2029 22:14:19.114673 SW Impedance : PASS
2030 22:14:19.114760 DUTY Scan : NO K
2031 22:14:19.118137 ZQ Calibration : PASS
2032 22:14:19.121801 Jitter Meter : NO K
2033 22:14:19.121883 CBT Training : PASS
2034 22:14:19.125118 Write leveling : PASS
2035 22:14:19.125217 RX DQS gating : PASS
2036 22:14:19.128041 RX DQ/DQS(RDDQC) : PASS
2037 22:14:19.131292 TX DQ/DQS : PASS
2038 22:14:19.131373 RX DATLAT : PASS
2039 22:14:19.134579 RX DQ/DQS(Engine): PASS
2040 22:14:19.138007 TX OE : NO K
2041 22:14:19.138089 All Pass.
2042 22:14:19.138155
2043 22:14:19.138252 CH 0, Rank 1
2044 22:14:19.141475 SW Impedance : PASS
2045 22:14:19.144570 DUTY Scan : NO K
2046 22:14:19.144651 ZQ Calibration : PASS
2047 22:14:19.148095 Jitter Meter : NO K
2048 22:14:19.151549 CBT Training : PASS
2049 22:14:19.151630 Write leveling : PASS
2050 22:14:19.154806 RX DQS gating : PASS
2051 22:14:19.158048 RX DQ/DQS(RDDQC) : PASS
2052 22:14:19.158135 TX DQ/DQS : PASS
2053 22:14:19.161160 RX DATLAT : PASS
2054 22:14:19.165050 RX DQ/DQS(Engine): PASS
2055 22:14:19.165128 TX OE : NO K
2056 22:14:19.168012 All Pass.
2057 22:14:19.168111
2058 22:14:19.168174 CH 1, Rank 0
2059 22:14:19.171103 SW Impedance : PASS
2060 22:14:19.171174 DUTY Scan : NO K
2061 22:14:19.174503 ZQ Calibration : PASS
2062 22:14:19.178034 Jitter Meter : NO K
2063 22:14:19.178108 CBT Training : PASS
2064 22:14:19.181306 Write leveling : PASS
2065 22:14:19.181380 RX DQS gating : PASS
2066 22:14:19.184322 RX DQ/DQS(RDDQC) : PASS
2067 22:14:19.187635 TX DQ/DQS : PASS
2068 22:14:19.187706 RX DATLAT : PASS
2069 22:14:19.191009 RX DQ/DQS(Engine): PASS
2070 22:14:19.194604 TX OE : NO K
2071 22:14:19.194689 All Pass.
2072 22:14:19.194753
2073 22:14:19.194812 CH 1, Rank 1
2074 22:14:19.198029 SW Impedance : PASS
2075 22:14:19.200946 DUTY Scan : NO K
2076 22:14:19.201021 ZQ Calibration : PASS
2077 22:14:19.204786 Jitter Meter : NO K
2078 22:14:19.208174 CBT Training : PASS
2079 22:14:19.208256 Write leveling : PASS
2080 22:14:19.211217 RX DQS gating : PASS
2081 22:14:19.214157 RX DQ/DQS(RDDQC) : PASS
2082 22:14:19.214237 TX DQ/DQS : PASS
2083 22:14:19.217372 RX DATLAT : PASS
2084 22:14:19.221095 RX DQ/DQS(Engine): PASS
2085 22:14:19.221165 TX OE : NO K
2086 22:14:19.224366 All Pass.
2087 22:14:19.224437
2088 22:14:19.224534 DramC Write-DBI off
2089 22:14:19.227598 PER_BANK_REFRESH: Hybrid Mode
2090 22:14:19.227665 TX_TRACKING: ON
2091 22:14:19.230743 [GetDramInforAfterCalByMRR] Vendor 6.
2092 22:14:19.237145 [GetDramInforAfterCalByMRR] Revision 606.
2093 22:14:19.240535 [GetDramInforAfterCalByMRR] Revision 2 0.
2094 22:14:19.240606 MR0 0x3b3b
2095 22:14:19.240671 MR8 0x5151
2096 22:14:19.243762 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2097 22:14:19.243861
2098 22:14:19.247198 MR0 0x3b3b
2099 22:14:19.247275 MR8 0x5151
2100 22:14:19.250879 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2101 22:14:19.250953
2102 22:14:19.260569 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2103 22:14:19.263800 [FAST_K] Save calibration result to emmc
2104 22:14:19.267303 [FAST_K] Save calibration result to emmc
2105 22:14:19.270301 dram_init: config_dvfs: 1
2106 22:14:19.273814 dramc_set_vcore_voltage set vcore to 662500
2107 22:14:19.277453 Read voltage for 1200, 2
2108 22:14:19.277524 Vio18 = 0
2109 22:14:19.277586 Vcore = 662500
2110 22:14:19.280704 Vdram = 0
2111 22:14:19.280816 Vddq = 0
2112 22:14:19.280878 Vmddr = 0
2113 22:14:19.287201 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2114 22:14:19.290714 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2115 22:14:19.293668 MEM_TYPE=3, freq_sel=15
2116 22:14:19.297035 sv_algorithm_assistance_LP4_1600
2117 22:14:19.300409 ============ PULL DRAM RESETB DOWN ============
2118 22:14:19.303861 ========== PULL DRAM RESETB DOWN end =========
2119 22:14:19.310682 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2120 22:14:19.313692 ===================================
2121 22:14:19.313767 LPDDR4 DRAM CONFIGURATION
2122 22:14:19.316903 ===================================
2123 22:14:19.320438 EX_ROW_EN[0] = 0x0
2124 22:14:19.323819 EX_ROW_EN[1] = 0x0
2125 22:14:19.323894 LP4Y_EN = 0x0
2126 22:14:19.327199 WORK_FSP = 0x0
2127 22:14:19.327272 WL = 0x4
2128 22:14:19.330483 RL = 0x4
2129 22:14:19.330553 BL = 0x2
2130 22:14:19.333707 RPST = 0x0
2131 22:14:19.333809 RD_PRE = 0x0
2132 22:14:19.337493 WR_PRE = 0x1
2133 22:14:19.337564 WR_PST = 0x0
2134 22:14:19.340663 DBI_WR = 0x0
2135 22:14:19.340741 DBI_RD = 0x0
2136 22:14:19.343990 OTF = 0x1
2137 22:14:19.346859 ===================================
2138 22:14:19.350400 ===================================
2139 22:14:19.350476 ANA top config
2140 22:14:19.354028 ===================================
2141 22:14:19.357250 DLL_ASYNC_EN = 0
2142 22:14:19.360409 ALL_SLAVE_EN = 0
2143 22:14:19.363467 NEW_RANK_MODE = 1
2144 22:14:19.363538 DLL_IDLE_MODE = 1
2145 22:14:19.367415 LP45_APHY_COMB_EN = 1
2146 22:14:19.370307 TX_ODT_DIS = 1
2147 22:14:19.373453 NEW_8X_MODE = 1
2148 22:14:19.377047 ===================================
2149 22:14:19.380163 ===================================
2150 22:14:19.383433 data_rate = 2400
2151 22:14:19.383509 CKR = 1
2152 22:14:19.386590 DQ_P2S_RATIO = 8
2153 22:14:19.390000 ===================================
2154 22:14:19.393215 CA_P2S_RATIO = 8
2155 22:14:19.396603 DQ_CA_OPEN = 0
2156 22:14:19.399818 DQ_SEMI_OPEN = 0
2157 22:14:19.403093 CA_SEMI_OPEN = 0
2158 22:14:19.403171 CA_FULL_RATE = 0
2159 22:14:19.407057 DQ_CKDIV4_EN = 0
2160 22:14:19.409714 CA_CKDIV4_EN = 0
2161 22:14:19.413031 CA_PREDIV_EN = 0
2162 22:14:19.416849 PH8_DLY = 17
2163 22:14:19.419858 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2164 22:14:19.419967 DQ_AAMCK_DIV = 4
2165 22:14:19.423552 CA_AAMCK_DIV = 4
2166 22:14:19.426473 CA_ADMCK_DIV = 4
2167 22:14:19.430312 DQ_TRACK_CA_EN = 0
2168 22:14:19.433030 CA_PICK = 1200
2169 22:14:19.436739 CA_MCKIO = 1200
2170 22:14:19.436814 MCKIO_SEMI = 0
2171 22:14:19.439860 PLL_FREQ = 2366
2172 22:14:19.443286 DQ_UI_PI_RATIO = 32
2173 22:14:19.446614 CA_UI_PI_RATIO = 0
2174 22:14:19.449911 ===================================
2175 22:14:19.453518 ===================================
2176 22:14:19.456616 memory_type:LPDDR4
2177 22:14:19.456688 GP_NUM : 10
2178 22:14:19.459765 SRAM_EN : 1
2179 22:14:19.463018 MD32_EN : 0
2180 22:14:19.466704 ===================================
2181 22:14:19.466793 [ANA_INIT] >>>>>>>>>>>>>>
2182 22:14:19.470040 <<<<<< [CONFIGURE PHASE]: ANA_TX
2183 22:14:19.473236 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2184 22:14:19.476195 ===================================
2185 22:14:19.479595 data_rate = 2400,PCW = 0X5b00
2186 22:14:19.482940 ===================================
2187 22:14:19.486468 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2188 22:14:19.493047 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2189 22:14:19.496261 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2190 22:14:19.502651 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2191 22:14:19.505901 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2192 22:14:19.509449 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2193 22:14:19.512933 [ANA_INIT] flow start
2194 22:14:19.513015 [ANA_INIT] PLL >>>>>>>>
2195 22:14:19.516144 [ANA_INIT] PLL <<<<<<<<
2196 22:14:19.519113 [ANA_INIT] MIDPI >>>>>>>>
2197 22:14:19.519194 [ANA_INIT] MIDPI <<<<<<<<
2198 22:14:19.522717 [ANA_INIT] DLL >>>>>>>>
2199 22:14:19.526018 [ANA_INIT] DLL <<<<<<<<
2200 22:14:19.526097 [ANA_INIT] flow end
2201 22:14:19.532509 ============ LP4 DIFF to SE enter ============
2202 22:14:19.535900 ============ LP4 DIFF to SE exit ============
2203 22:14:19.536009 [ANA_INIT] <<<<<<<<<<<<<
2204 22:14:19.539437 [Flow] Enable top DCM control >>>>>
2205 22:14:19.542545 [Flow] Enable top DCM control <<<<<
2206 22:14:19.545858 Enable DLL master slave shuffle
2207 22:14:19.552662 ==============================================================
2208 22:14:19.555708 Gating Mode config
2209 22:14:19.558878 ==============================================================
2210 22:14:19.562305 Config description:
2211 22:14:19.572221 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2212 22:14:19.578831 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2213 22:14:19.582525 SELPH_MODE 0: By rank 1: By Phase
2214 22:14:19.589040 ==============================================================
2215 22:14:19.592204 GAT_TRACK_EN = 1
2216 22:14:19.595414 RX_GATING_MODE = 2
2217 22:14:19.598756 RX_GATING_TRACK_MODE = 2
2218 22:14:19.598830 SELPH_MODE = 1
2219 22:14:19.602270 PICG_EARLY_EN = 1
2220 22:14:19.605443 VALID_LAT_VALUE = 1
2221 22:14:19.612413 ==============================================================
2222 22:14:19.615319 Enter into Gating configuration >>>>
2223 22:14:19.618900 Exit from Gating configuration <<<<
2224 22:14:19.621723 Enter into DVFS_PRE_config >>>>>
2225 22:14:19.631973 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2226 22:14:19.635084 Exit from DVFS_PRE_config <<<<<
2227 22:14:19.638910 Enter into PICG configuration >>>>
2228 22:14:19.642061 Exit from PICG configuration <<<<
2229 22:14:19.645067 [RX_INPUT] configuration >>>>>
2230 22:14:19.648329 [RX_INPUT] configuration <<<<<
2231 22:14:19.651689 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2232 22:14:19.658282 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2233 22:14:19.665102 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2234 22:14:19.671873 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2235 22:14:19.678599 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2236 22:14:19.681663 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2237 22:14:19.688083 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2238 22:14:19.691482 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2239 22:14:19.694908 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2240 22:14:19.698163 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2241 22:14:19.705165 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2242 22:14:19.708167 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2243 22:14:19.711533 ===================================
2244 22:14:19.715414 LPDDR4 DRAM CONFIGURATION
2245 22:14:19.718137 ===================================
2246 22:14:19.718229 EX_ROW_EN[0] = 0x0
2247 22:14:19.721767 EX_ROW_EN[1] = 0x0
2248 22:14:19.721845 LP4Y_EN = 0x0
2249 22:14:19.724927 WORK_FSP = 0x0
2250 22:14:19.725001 WL = 0x4
2251 22:14:19.728023 RL = 0x4
2252 22:14:19.728128 BL = 0x2
2253 22:14:19.731680 RPST = 0x0
2254 22:14:19.731758 RD_PRE = 0x0
2255 22:14:19.734949 WR_PRE = 0x1
2256 22:14:19.735025 WR_PST = 0x0
2257 22:14:19.738380 DBI_WR = 0x0
2258 22:14:19.738451 DBI_RD = 0x0
2259 22:14:19.741530 OTF = 0x1
2260 22:14:19.744974 ===================================
2261 22:14:19.748107 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2262 22:14:19.751794 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2263 22:14:19.757814 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2264 22:14:19.761089 ===================================
2265 22:14:19.764647 LPDDR4 DRAM CONFIGURATION
2266 22:14:19.767784 ===================================
2267 22:14:19.767865 EX_ROW_EN[0] = 0x10
2268 22:14:19.771260 EX_ROW_EN[1] = 0x0
2269 22:14:19.771331 LP4Y_EN = 0x0
2270 22:14:19.774187 WORK_FSP = 0x0
2271 22:14:19.774268 WL = 0x4
2272 22:14:19.777886 RL = 0x4
2273 22:14:19.777957 BL = 0x2
2274 22:14:19.781234 RPST = 0x0
2275 22:14:19.781307 RD_PRE = 0x0
2276 22:14:19.784396 WR_PRE = 0x1
2277 22:14:19.787540 WR_PST = 0x0
2278 22:14:19.787617 DBI_WR = 0x0
2279 22:14:19.791104 DBI_RD = 0x0
2280 22:14:19.791178 OTF = 0x1
2281 22:14:19.794166 ===================================
2282 22:14:19.800666 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2283 22:14:19.800744 ==
2284 22:14:19.804036 Dram Type= 6, Freq= 0, CH_0, rank 0
2285 22:14:19.807272 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2286 22:14:19.807342 ==
2287 22:14:19.811057 [Duty_Offset_Calibration]
2288 22:14:19.811129 B0:2 B1:0 CA:4
2289 22:14:19.811191
2290 22:14:19.814164 [DutyScan_Calibration_Flow] k_type=0
2291 22:14:19.824184
2292 22:14:19.824265 ==CLK 0==
2293 22:14:19.827458 Final CLK duty delay cell = -4
2294 22:14:19.830648 [-4] MAX Duty = 5031%(X100), DQS PI = 14
2295 22:14:19.834158 [-4] MIN Duty = 4844%(X100), DQS PI = 8
2296 22:14:19.837526 [-4] AVG Duty = 4937%(X100)
2297 22:14:19.837603
2298 22:14:19.840677 CH0 CLK Duty spec in!! Max-Min= 187%
2299 22:14:19.844205 [DutyScan_Calibration_Flow] ====Done====
2300 22:14:19.844302
2301 22:14:19.847424 [DutyScan_Calibration_Flow] k_type=1
2302 22:14:19.863794
2303 22:14:19.863873 ==DQS 0 ==
2304 22:14:19.867187 Final DQS duty delay cell = 0
2305 22:14:19.870673 [0] MAX Duty = 5156%(X100), DQS PI = 18
2306 22:14:19.873982 [0] MIN Duty = 5093%(X100), DQS PI = 2
2307 22:14:19.874053 [0] AVG Duty = 5124%(X100)
2308 22:14:19.877080
2309 22:14:19.877153 ==DQS 1 ==
2310 22:14:19.880273 Final DQS duty delay cell = 0
2311 22:14:19.884089 [0] MAX Duty = 5125%(X100), DQS PI = 4
2312 22:14:19.886841 [0] MIN Duty = 5000%(X100), DQS PI = 0
2313 22:14:19.886947 [0] AVG Duty = 5062%(X100)
2314 22:14:19.890577
2315 22:14:19.893691 CH0 DQS 0 Duty spec in!! Max-Min= 63%
2316 22:14:19.893767
2317 22:14:19.896808 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2318 22:14:19.900314 [DutyScan_Calibration_Flow] ====Done====
2319 22:14:19.900386
2320 22:14:19.903283 [DutyScan_Calibration_Flow] k_type=3
2321 22:14:19.919950
2322 22:14:19.920027 ==DQM 0 ==
2323 22:14:19.923290 Final DQM duty delay cell = 0
2324 22:14:19.926923 [0] MAX Duty = 5125%(X100), DQS PI = 20
2325 22:14:19.930259 [0] MIN Duty = 4875%(X100), DQS PI = 50
2326 22:14:19.933471 [0] AVG Duty = 5000%(X100)
2327 22:14:19.933546
2328 22:14:19.933607 ==DQM 1 ==
2329 22:14:19.936470 Final DQM duty delay cell = 0
2330 22:14:19.939671 [0] MAX Duty = 4969%(X100), DQS PI = 0
2331 22:14:19.943321 [0] MIN Duty = 4876%(X100), DQS PI = 20
2332 22:14:19.946184 [0] AVG Duty = 4922%(X100)
2333 22:14:19.946258
2334 22:14:19.949426 CH0 DQM 0 Duty spec in!! Max-Min= 250%
2335 22:14:19.949494
2336 22:14:19.952755 CH0 DQM 1 Duty spec in!! Max-Min= 93%
2337 22:14:19.956555 [DutyScan_Calibration_Flow] ====Done====
2338 22:14:19.956620
2339 22:14:19.959643 [DutyScan_Calibration_Flow] k_type=2
2340 22:14:19.976303
2341 22:14:19.976389 ==DQ 0 ==
2342 22:14:19.979530 Final DQ duty delay cell = 0
2343 22:14:19.983359 [0] MAX Duty = 5125%(X100), DQS PI = 18
2344 22:14:19.986411 [0] MIN Duty = 5000%(X100), DQS PI = 8
2345 22:14:19.986482 [0] AVG Duty = 5062%(X100)
2346 22:14:19.989657
2347 22:14:19.989727 ==DQ 1 ==
2348 22:14:19.993195 Final DQ duty delay cell = 0
2349 22:14:19.996146 [0] MAX Duty = 5156%(X100), DQS PI = 4
2350 22:14:19.999547 [0] MIN Duty = 4938%(X100), DQS PI = 16
2351 22:14:19.999617 [0] AVG Duty = 5047%(X100)
2352 22:14:19.999716
2353 22:14:20.002644 CH0 DQ 0 Duty spec in!! Max-Min= 125%
2354 22:14:20.006224
2355 22:14:20.009269 CH0 DQ 1 Duty spec in!! Max-Min= 218%
2356 22:14:20.012744 [DutyScan_Calibration_Flow] ====Done====
2357 22:14:20.012821 ==
2358 22:14:20.016216 Dram Type= 6, Freq= 0, CH_1, rank 0
2359 22:14:20.019470 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2360 22:14:20.019565 ==
2361 22:14:20.022790 [Duty_Offset_Calibration]
2362 22:14:20.022883 B0:0 B1:-1 CA:3
2363 22:14:20.022961
2364 22:14:20.025685 [DutyScan_Calibration_Flow] k_type=0
2365 22:14:20.035447
2366 22:14:20.035529 ==CLK 0==
2367 22:14:20.038865 Final CLK duty delay cell = -4
2368 22:14:20.042208 [-4] MAX Duty = 5031%(X100), DQS PI = 44
2369 22:14:20.045640 [-4] MIN Duty = 4876%(X100), DQS PI = 36
2370 22:14:20.048668 [-4] AVG Duty = 4953%(X100)
2371 22:14:20.048763
2372 22:14:20.051939 CH1 CLK Duty spec in!! Max-Min= 155%
2373 22:14:20.055170 [DutyScan_Calibration_Flow] ====Done====
2374 22:14:20.055252
2375 22:14:20.058402 [DutyScan_Calibration_Flow] k_type=1
2376 22:14:20.075011
2377 22:14:20.075104 ==DQS 0 ==
2378 22:14:20.078423 Final DQS duty delay cell = 0
2379 22:14:20.082272 [0] MAX Duty = 5187%(X100), DQS PI = 18
2380 22:14:20.085646 [0] MIN Duty = 4907%(X100), DQS PI = 38
2381 22:14:20.088329 [0] AVG Duty = 5047%(X100)
2382 22:14:20.088414
2383 22:14:20.088479 ==DQS 1 ==
2384 22:14:20.091928 Final DQS duty delay cell = 0
2385 22:14:20.095243 [0] MAX Duty = 5156%(X100), DQS PI = 8
2386 22:14:20.098437 [0] MIN Duty = 5031%(X100), DQS PI = 20
2387 22:14:20.101796 [0] AVG Duty = 5093%(X100)
2388 22:14:20.101892
2389 22:14:20.104739 CH1 DQS 0 Duty spec in!! Max-Min= 280%
2390 22:14:20.104821
2391 22:14:20.107985 CH1 DQS 1 Duty spec in!! Max-Min= 125%
2392 22:14:20.111401 [DutyScan_Calibration_Flow] ====Done====
2393 22:14:20.111535
2394 22:14:20.114481 [DutyScan_Calibration_Flow] k_type=3
2395 22:14:20.131992
2396 22:14:20.132107 ==DQM 0 ==
2397 22:14:20.135057 Final DQM duty delay cell = 0
2398 22:14:20.138592 [0] MAX Duty = 5031%(X100), DQS PI = 28
2399 22:14:20.141970 [0] MIN Duty = 4782%(X100), DQS PI = 38
2400 22:14:20.145115 [0] AVG Duty = 4906%(X100)
2401 22:14:20.145197
2402 22:14:20.145262 ==DQM 1 ==
2403 22:14:20.148410 Final DQM duty delay cell = 0
2404 22:14:20.151453 [0] MAX Duty = 5000%(X100), DQS PI = 36
2405 22:14:20.155010 [0] MIN Duty = 4844%(X100), DQS PI = 0
2406 22:14:20.158328 [0] AVG Duty = 4922%(X100)
2407 22:14:20.158410
2408 22:14:20.161570 CH1 DQM 0 Duty spec in!! Max-Min= 249%
2409 22:14:20.161653
2410 22:14:20.164826 CH1 DQM 1 Duty spec in!! Max-Min= 156%
2411 22:14:20.167878 [DutyScan_Calibration_Flow] ====Done====
2412 22:14:20.167987
2413 22:14:20.171152 [DutyScan_Calibration_Flow] k_type=2
2414 22:14:20.188468
2415 22:14:20.188551 ==DQ 0 ==
2416 22:14:20.191497 Final DQ duty delay cell = -4
2417 22:14:20.194615 [-4] MAX Duty = 5031%(X100), DQS PI = 30
2418 22:14:20.198051 [-4] MIN Duty = 4876%(X100), DQS PI = 18
2419 22:14:20.201396 [-4] AVG Duty = 4953%(X100)
2420 22:14:20.201482
2421 22:14:20.201549 ==DQ 1 ==
2422 22:14:20.204977 Final DQ duty delay cell = 4
2423 22:14:20.207984 [4] MAX Duty = 5156%(X100), DQS PI = 10
2424 22:14:20.211182 [4] MIN Duty = 5031%(X100), DQS PI = 62
2425 22:14:20.215039 [4] AVG Duty = 5093%(X100)
2426 22:14:20.215146
2427 22:14:20.218100 CH1 DQ 0 Duty spec in!! Max-Min= 155%
2428 22:14:20.218174
2429 22:14:20.221279 CH1 DQ 1 Duty spec in!! Max-Min= 125%
2430 22:14:20.224535 [DutyScan_Calibration_Flow] ====Done====
2431 22:14:20.228064 nWR fixed to 30
2432 22:14:20.231018 [ModeRegInit_LP4] CH0 RK0
2433 22:14:20.231118 [ModeRegInit_LP4] CH0 RK1
2434 22:14:20.234472 [ModeRegInit_LP4] CH1 RK0
2435 22:14:20.237748 [ModeRegInit_LP4] CH1 RK1
2436 22:14:20.237827 match AC timing 7
2437 22:14:20.244366 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2438 22:14:20.247590 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2439 22:14:20.251067 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2440 22:14:20.257672 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2441 22:14:20.261353 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2442 22:14:20.261426 ==
2443 22:14:20.264692 Dram Type= 6, Freq= 0, CH_0, rank 0
2444 22:14:20.267569 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2445 22:14:20.267668 ==
2446 22:14:20.274649 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2447 22:14:20.280951 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2448 22:14:20.288413 [CA 0] Center 39 (9~70) winsize 62
2449 22:14:20.292217 [CA 1] Center 39 (9~69) winsize 61
2450 22:14:20.294922 [CA 2] Center 35 (5~66) winsize 62
2451 22:14:20.298235 [CA 3] Center 35 (5~66) winsize 62
2452 22:14:20.301679 [CA 4] Center 33 (3~64) winsize 62
2453 22:14:20.305249 [CA 5] Center 33 (3~64) winsize 62
2454 22:14:20.305334
2455 22:14:20.308344 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2456 22:14:20.308438
2457 22:14:20.311640 [CATrainingPosCal] consider 1 rank data
2458 22:14:20.315088 u2DelayCellTimex100 = 270/100 ps
2459 22:14:20.318159 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2460 22:14:20.325081 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2461 22:14:20.328111 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2462 22:14:20.331922 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2463 22:14:20.335108 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2464 22:14:20.338160 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2465 22:14:20.338263
2466 22:14:20.341619 CA PerBit enable=1, Macro0, CA PI delay=33
2467 22:14:20.341693
2468 22:14:20.345435 [CBTSetCACLKResult] CA Dly = 33
2469 22:14:20.345511 CS Dly: 7 (0~38)
2470 22:14:20.348823 ==
2471 22:14:20.351258 Dram Type= 6, Freq= 0, CH_0, rank 1
2472 22:14:20.354944 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2473 22:14:20.355052 ==
2474 22:14:20.358080 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2475 22:14:20.364596 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2476 22:14:20.374380 [CA 0] Center 39 (9~70) winsize 62
2477 22:14:20.377325 [CA 1] Center 39 (9~70) winsize 62
2478 22:14:20.380874 [CA 2] Center 35 (5~66) winsize 62
2479 22:14:20.384181 [CA 3] Center 35 (5~66) winsize 62
2480 22:14:20.387723 [CA 4] Center 34 (4~65) winsize 62
2481 22:14:20.390810 [CA 5] Center 33 (3~64) winsize 62
2482 22:14:20.390906
2483 22:14:20.393974 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2484 22:14:20.394047
2485 22:14:20.397638 [CATrainingPosCal] consider 2 rank data
2486 22:14:20.400522 u2DelayCellTimex100 = 270/100 ps
2487 22:14:20.404375 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2488 22:14:20.410699 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2489 22:14:20.414026 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2490 22:14:20.417195 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2491 22:14:20.420706 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
2492 22:14:20.424411 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2493 22:14:20.424493
2494 22:14:20.427538 CA PerBit enable=1, Macro0, CA PI delay=33
2495 22:14:20.427649
2496 22:14:20.430864 [CBTSetCACLKResult] CA Dly = 33
2497 22:14:20.430961 CS Dly: 8 (0~41)
2498 22:14:20.433891
2499 22:14:20.437598 ----->DramcWriteLeveling(PI) begin...
2500 22:14:20.437725 ==
2501 22:14:20.440797 Dram Type= 6, Freq= 0, CH_0, rank 0
2502 22:14:20.443870 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2503 22:14:20.443990 ==
2504 22:14:20.447459 Write leveling (Byte 0): 33 => 33
2505 22:14:20.450557 Write leveling (Byte 1): 26 => 26
2506 22:14:20.453888 DramcWriteLeveling(PI) end<-----
2507 22:14:20.453982
2508 22:14:20.454069 ==
2509 22:14:20.457389 Dram Type= 6, Freq= 0, CH_0, rank 0
2510 22:14:20.460656 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2511 22:14:20.460729 ==
2512 22:14:20.464190 [Gating] SW mode calibration
2513 22:14:20.470735 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2514 22:14:20.477015 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2515 22:14:20.480875 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2516 22:14:20.483634 0 15 4 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 1)
2517 22:14:20.490534 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2518 22:14:20.494081 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2519 22:14:20.497097 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2520 22:14:20.500568 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2521 22:14:20.507020 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2522 22:14:20.510258 0 15 28 | B1->B0 | 3434 2626 | 1 0 | (1 1) (0 0)
2523 22:14:20.513550 1 0 0 | B1->B0 | 3232 2323 | 0 0 | (0 0) (0 0)
2524 22:14:20.520223 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2525 22:14:20.523525 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2526 22:14:20.527607 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2527 22:14:20.533758 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2528 22:14:20.537021 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2529 22:14:20.540195 1 0 24 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
2530 22:14:20.547517 1 0 28 | B1->B0 | 2525 4646 | 0 0 | (0 0) (0 0)
2531 22:14:20.550425 1 1 0 | B1->B0 | 2929 4646 | 0 0 | (0 0) (0 0)
2532 22:14:20.553691 1 1 4 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
2533 22:14:20.560194 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2534 22:14:20.563764 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2535 22:14:20.566825 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2536 22:14:20.573626 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2537 22:14:20.576884 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2538 22:14:20.580113 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2539 22:14:20.587039 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2540 22:14:20.589918 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2541 22:14:20.593396 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2542 22:14:20.599683 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2543 22:14:20.603302 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2544 22:14:20.606650 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2545 22:14:20.613495 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2546 22:14:20.616617 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2547 22:14:20.619833 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2548 22:14:20.626896 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2549 22:14:20.629748 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2550 22:14:20.632959 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2551 22:14:20.640109 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2552 22:14:20.643165 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2553 22:14:20.646515 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2554 22:14:20.653325 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2555 22:14:20.656147 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2556 22:14:20.659581 Total UI for P1: 0, mck2ui 16
2557 22:14:20.662651 best dqsien dly found for B0: ( 1, 3, 26)
2558 22:14:20.666084 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2559 22:14:20.670000 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2560 22:14:20.672981 Total UI for P1: 0, mck2ui 16
2561 22:14:20.675960 best dqsien dly found for B1: ( 1, 4, 2)
2562 22:14:20.680011 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2563 22:14:20.686055 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2564 22:14:20.686139
2565 22:14:20.689699 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2566 22:14:20.692776 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2567 22:14:20.696141 [Gating] SW calibration Done
2568 22:14:20.696226 ==
2569 22:14:20.699598 Dram Type= 6, Freq= 0, CH_0, rank 0
2570 22:14:20.702789 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2571 22:14:20.702933 ==
2572 22:14:20.703064 RX Vref Scan: 0
2573 22:14:20.705814
2574 22:14:20.705924 RX Vref 0 -> 0, step: 1
2575 22:14:20.706022
2576 22:14:20.709459 RX Delay -40 -> 252, step: 8
2577 22:14:20.712585 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2578 22:14:20.716098 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2579 22:14:20.722358 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2580 22:14:20.726269 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2581 22:14:20.728956 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2582 22:14:20.732222 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2583 22:14:20.735877 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2584 22:14:20.743012 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2585 22:14:20.745719 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2586 22:14:20.748855 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2587 22:14:20.752507 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2588 22:14:20.755775 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2589 22:14:20.762223 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
2590 22:14:20.765525 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2591 22:14:20.769088 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2592 22:14:20.772395 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2593 22:14:20.772473 ==
2594 22:14:20.775700 Dram Type= 6, Freq= 0, CH_0, rank 0
2595 22:14:20.782413 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2596 22:14:20.782500 ==
2597 22:14:20.782568 DQS Delay:
2598 22:14:20.786109 DQS0 = 0, DQS1 = 0
2599 22:14:20.786190 DQM Delay:
2600 22:14:20.786264 DQM0 = 118, DQM1 = 108
2601 22:14:20.789208 DQ Delay:
2602 22:14:20.792351 DQ0 =115, DQ1 =119, DQ2 =119, DQ3 =111
2603 22:14:20.795388 DQ4 =119, DQ5 =111, DQ6 =127, DQ7 =127
2604 22:14:20.798859 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2605 22:14:20.802618 DQ12 =119, DQ13 =111, DQ14 =119, DQ15 =115
2606 22:14:20.802700
2607 22:14:20.802773
2608 22:14:20.802840 ==
2609 22:14:20.805304 Dram Type= 6, Freq= 0, CH_0, rank 0
2610 22:14:20.808833 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2611 22:14:20.811899 ==
2612 22:14:20.812014
2613 22:14:20.812126
2614 22:14:20.812231 TX Vref Scan disable
2615 22:14:20.815529 == TX Byte 0 ==
2616 22:14:20.818472 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2617 22:14:20.821819 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2618 22:14:20.825264 == TX Byte 1 ==
2619 22:14:20.828479 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2620 22:14:20.832007 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2621 22:14:20.835375 ==
2622 22:14:20.835486 Dram Type= 6, Freq= 0, CH_0, rank 0
2623 22:14:20.841782 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2624 22:14:20.841865 ==
2625 22:14:20.853415 TX Vref=22, minBit 3, minWin=25, winSum=414
2626 22:14:20.856566 TX Vref=24, minBit 4, minWin=25, winSum=418
2627 22:14:20.860390 TX Vref=26, minBit 4, minWin=25, winSum=422
2628 22:14:20.863234 TX Vref=28, minBit 5, minWin=26, winSum=432
2629 22:14:20.866657 TX Vref=30, minBit 5, minWin=26, winSum=430
2630 22:14:20.873236 TX Vref=32, minBit 4, minWin=26, winSum=430
2631 22:14:20.876712 [TxChooseVref] Worse bit 5, Min win 26, Win sum 432, Final Vref 28
2632 22:14:20.876829
2633 22:14:20.879765 Final TX Range 1 Vref 28
2634 22:14:20.879865
2635 22:14:20.879965 ==
2636 22:14:20.883330 Dram Type= 6, Freq= 0, CH_0, rank 0
2637 22:14:20.886673 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2638 22:14:20.886766 ==
2639 22:14:20.889799
2640 22:14:20.889885
2641 22:14:20.889979 TX Vref Scan disable
2642 22:14:20.892992 == TX Byte 0 ==
2643 22:14:20.896338 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2644 22:14:20.902936 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2645 22:14:20.903044 == TX Byte 1 ==
2646 22:14:20.906352 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
2647 22:14:20.913335 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
2648 22:14:20.913447
2649 22:14:20.913520 [DATLAT]
2650 22:14:20.913583 Freq=1200, CH0 RK0
2651 22:14:20.913652
2652 22:14:20.916419 DATLAT Default: 0xd
2653 22:14:20.919467 0, 0xFFFF, sum = 0
2654 22:14:20.919587 1, 0xFFFF, sum = 0
2655 22:14:20.922771 2, 0xFFFF, sum = 0
2656 22:14:20.922890 3, 0xFFFF, sum = 0
2657 22:14:20.926361 4, 0xFFFF, sum = 0
2658 22:14:20.926448 5, 0xFFFF, sum = 0
2659 22:14:20.929422 6, 0xFFFF, sum = 0
2660 22:14:20.929505 7, 0xFFFF, sum = 0
2661 22:14:20.933108 8, 0xFFFF, sum = 0
2662 22:14:20.933184 9, 0xFFFF, sum = 0
2663 22:14:20.935931 10, 0xFFFF, sum = 0
2664 22:14:20.936013 11, 0xFFFF, sum = 0
2665 22:14:20.939748 12, 0x0, sum = 1
2666 22:14:20.939832 13, 0x0, sum = 2
2667 22:14:20.942527 14, 0x0, sum = 3
2668 22:14:20.942609 15, 0x0, sum = 4
2669 22:14:20.946518 best_step = 13
2670 22:14:20.946628
2671 22:14:20.946733 ==
2672 22:14:20.949465 Dram Type= 6, Freq= 0, CH_0, rank 0
2673 22:14:20.952570 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2674 22:14:20.952657 ==
2675 22:14:20.952725 RX Vref Scan: 1
2676 22:14:20.956061
2677 22:14:20.956142 Set Vref Range= 32 -> 127
2678 22:14:20.956206
2679 22:14:20.959256 RX Vref 32 -> 127, step: 1
2680 22:14:20.959334
2681 22:14:20.963070 RX Delay -21 -> 252, step: 4
2682 22:14:20.963182
2683 22:14:20.966281 Set Vref, RX VrefLevel [Byte0]: 32
2684 22:14:20.969696 [Byte1]: 32
2685 22:14:20.969772
2686 22:14:20.972905 Set Vref, RX VrefLevel [Byte0]: 33
2687 22:14:20.976025 [Byte1]: 33
2688 22:14:20.979502
2689 22:14:20.979589 Set Vref, RX VrefLevel [Byte0]: 34
2690 22:14:20.983186 [Byte1]: 34
2691 22:14:20.987667
2692 22:14:20.987778 Set Vref, RX VrefLevel [Byte0]: 35
2693 22:14:20.993924 [Byte1]: 35
2694 22:14:20.994004
2695 22:14:20.997666 Set Vref, RX VrefLevel [Byte0]: 36
2696 22:14:21.000722 [Byte1]: 36
2697 22:14:21.000793
2698 22:14:21.004080 Set Vref, RX VrefLevel [Byte0]: 37
2699 22:14:21.007279 [Byte1]: 37
2700 22:14:21.011301
2701 22:14:21.011385 Set Vref, RX VrefLevel [Byte0]: 38
2702 22:14:21.014522 [Byte1]: 38
2703 22:14:21.019480
2704 22:14:21.019563 Set Vref, RX VrefLevel [Byte0]: 39
2705 22:14:21.022773 [Byte1]: 39
2706 22:14:21.027531
2707 22:14:21.027616 Set Vref, RX VrefLevel [Byte0]: 40
2708 22:14:21.030677 [Byte1]: 40
2709 22:14:21.035240
2710 22:14:21.035361 Set Vref, RX VrefLevel [Byte0]: 41
2711 22:14:21.038627 [Byte1]: 41
2712 22:14:21.043363
2713 22:14:21.043442 Set Vref, RX VrefLevel [Byte0]: 42
2714 22:14:21.046213 [Byte1]: 42
2715 22:14:21.050792
2716 22:14:21.050880 Set Vref, RX VrefLevel [Byte0]: 43
2717 22:14:21.054073 [Byte1]: 43
2718 22:14:21.058962
2719 22:14:21.059054 Set Vref, RX VrefLevel [Byte0]: 44
2720 22:14:21.061995 [Byte1]: 44
2721 22:14:21.066838
2722 22:14:21.066925 Set Vref, RX VrefLevel [Byte0]: 45
2723 22:14:21.070388 [Byte1]: 45
2724 22:14:21.074816
2725 22:14:21.074932 Set Vref, RX VrefLevel [Byte0]: 46
2726 22:14:21.078271 [Byte1]: 46
2727 22:14:21.082806
2728 22:14:21.082883 Set Vref, RX VrefLevel [Byte0]: 47
2729 22:14:21.085925 [Byte1]: 47
2730 22:14:21.090421
2731 22:14:21.090505 Set Vref, RX VrefLevel [Byte0]: 48
2732 22:14:21.093836 [Byte1]: 48
2733 22:14:21.098397
2734 22:14:21.098473 Set Vref, RX VrefLevel [Byte0]: 49
2735 22:14:21.102177 [Byte1]: 49
2736 22:14:21.106498
2737 22:14:21.106598 Set Vref, RX VrefLevel [Byte0]: 50
2738 22:14:21.109692 [Byte1]: 50
2739 22:14:21.114578
2740 22:14:21.114679 Set Vref, RX VrefLevel [Byte0]: 51
2741 22:14:21.117660 [Byte1]: 51
2742 22:14:21.122499
2743 22:14:21.125565 Set Vref, RX VrefLevel [Byte0]: 52
2744 22:14:21.128992 [Byte1]: 52
2745 22:14:21.129068
2746 22:14:21.132360 Set Vref, RX VrefLevel [Byte0]: 53
2747 22:14:21.135642 [Byte1]: 53
2748 22:14:21.135723
2749 22:14:21.138584 Set Vref, RX VrefLevel [Byte0]: 54
2750 22:14:21.141765 [Byte1]: 54
2751 22:14:21.146254
2752 22:14:21.146330 Set Vref, RX VrefLevel [Byte0]: 55
2753 22:14:21.149244 [Byte1]: 55
2754 22:14:21.154201
2755 22:14:21.154278 Set Vref, RX VrefLevel [Byte0]: 56
2756 22:14:21.157462 [Byte1]: 56
2757 22:14:21.161950
2758 22:14:21.162024 Set Vref, RX VrefLevel [Byte0]: 57
2759 22:14:21.165479 [Byte1]: 57
2760 22:14:21.169882
2761 22:14:21.169957 Set Vref, RX VrefLevel [Byte0]: 58
2762 22:14:21.173351 [Byte1]: 58
2763 22:14:21.177604
2764 22:14:21.177678 Set Vref, RX VrefLevel [Byte0]: 59
2765 22:14:21.181034 [Byte1]: 59
2766 22:14:21.185824
2767 22:14:21.185900 Set Vref, RX VrefLevel [Byte0]: 60
2768 22:14:21.188921 [Byte1]: 60
2769 22:14:21.193508
2770 22:14:21.193585 Set Vref, RX VrefLevel [Byte0]: 61
2771 22:14:21.197292 [Byte1]: 61
2772 22:14:21.201721
2773 22:14:21.201803 Set Vref, RX VrefLevel [Byte0]: 62
2774 22:14:21.204871 [Byte1]: 62
2775 22:14:21.209638
2776 22:14:21.209721 Set Vref, RX VrefLevel [Byte0]: 63
2777 22:14:21.212834 [Byte1]: 63
2778 22:14:21.217678
2779 22:14:21.217768 Set Vref, RX VrefLevel [Byte0]: 64
2780 22:14:21.223954 [Byte1]: 64
2781 22:14:21.224080
2782 22:14:21.227081 Set Vref, RX VrefLevel [Byte0]: 65
2783 22:14:21.230634 [Byte1]: 65
2784 22:14:21.230706
2785 22:14:21.233815 Set Vref, RX VrefLevel [Byte0]: 66
2786 22:14:21.237306 [Byte1]: 66
2787 22:14:21.241457
2788 22:14:21.241525 Set Vref, RX VrefLevel [Byte0]: 67
2789 22:14:21.244859 [Byte1]: 67
2790 22:14:21.249283
2791 22:14:21.249357 Set Vref, RX VrefLevel [Byte0]: 68
2792 22:14:21.252351 [Byte1]: 68
2793 22:14:21.257226
2794 22:14:21.257299 Set Vref, RX VrefLevel [Byte0]: 69
2795 22:14:21.260658 [Byte1]: 69
2796 22:14:21.265048
2797 22:14:21.265115 Final RX Vref Byte 0 = 52 to rank0
2798 22:14:21.268188 Final RX Vref Byte 1 = 59 to rank0
2799 22:14:21.271939 Final RX Vref Byte 0 = 52 to rank1
2800 22:14:21.275089 Final RX Vref Byte 1 = 59 to rank1==
2801 22:14:21.278268 Dram Type= 6, Freq= 0, CH_0, rank 0
2802 22:14:21.284928 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2803 22:14:21.285004 ==
2804 22:14:21.285070 DQS Delay:
2805 22:14:21.285139 DQS0 = 0, DQS1 = 0
2806 22:14:21.288386 DQM Delay:
2807 22:14:21.288479 DQM0 = 117, DQM1 = 105
2808 22:14:21.291344 DQ Delay:
2809 22:14:21.295009 DQ0 =118, DQ1 =116, DQ2 =114, DQ3 =114
2810 22:14:21.298537 DQ4 =118, DQ5 =110, DQ6 =124, DQ7 =122
2811 22:14:21.301569 DQ8 =94, DQ9 =90, DQ10 =106, DQ11 =100
2812 22:14:21.305197 DQ12 =114, DQ13 =110, DQ14 =118, DQ15 =114
2813 22:14:21.305282
2814 22:14:21.305351
2815 22:14:21.314661 [DQSOSCAuto] RK0, (LSB)MR18= 0x1fd, (MSB)MR19= 0x403, tDQSOscB0 = 411 ps tDQSOscB1 = 409 ps
2816 22:14:21.314744 CH0 RK0: MR19=403, MR18=1FD
2817 22:14:21.321404 CH0_RK0: MR19=0x403, MR18=0x1FD, DQSOSC=409, MR23=63, INC=39, DEC=26
2818 22:14:21.321490
2819 22:14:21.324838 ----->DramcWriteLeveling(PI) begin...
2820 22:14:21.324924 ==
2821 22:14:21.328052 Dram Type= 6, Freq= 0, CH_0, rank 1
2822 22:14:21.331303 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2823 22:14:21.334836 ==
2824 22:14:21.334919 Write leveling (Byte 0): 32 => 32
2825 22:14:21.337937 Write leveling (Byte 1): 26 => 26
2826 22:14:21.341153 DramcWriteLeveling(PI) end<-----
2827 22:14:21.341229
2828 22:14:21.341293 ==
2829 22:14:21.344416 Dram Type= 6, Freq= 0, CH_0, rank 1
2830 22:14:21.351207 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2831 22:14:21.351286 ==
2832 22:14:21.354632 [Gating] SW mode calibration
2833 22:14:21.360854 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2834 22:14:21.364502 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2835 22:14:21.370832 0 15 0 | B1->B0 | 2424 3434 | 0 1 | (0 0) (1 1)
2836 22:14:21.374184 0 15 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
2837 22:14:21.377602 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2838 22:14:21.384451 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2839 22:14:21.387937 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2840 22:14:21.390894 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2841 22:14:21.397374 0 15 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
2842 22:14:21.401128 0 15 28 | B1->B0 | 3434 2a2a | 1 0 | (1 1) (1 0)
2843 22:14:21.403990 1 0 0 | B1->B0 | 2a2a 2323 | 0 0 | (1 0) (0 0)
2844 22:14:21.407588 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2845 22:14:21.414507 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2846 22:14:21.417470 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2847 22:14:21.421203 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2848 22:14:21.427638 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2849 22:14:21.430799 1 0 24 | B1->B0 | 2323 3737 | 0 0 | (0 0) (0 0)
2850 22:14:21.434331 1 0 28 | B1->B0 | 2525 4545 | 0 0 | (0 0) (0 0)
2851 22:14:21.440908 1 1 0 | B1->B0 | 4242 4646 | 0 0 | (1 1) (0 0)
2852 22:14:21.444131 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2853 22:14:21.447369 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2854 22:14:21.454322 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2855 22:14:21.457687 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2856 22:14:21.460908 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2857 22:14:21.467025 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2858 22:14:21.470677 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2859 22:14:21.473892 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2860 22:14:21.480978 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2861 22:14:21.483661 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2862 22:14:21.487009 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2863 22:14:21.493689 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2864 22:14:21.497357 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2865 22:14:21.500350 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2866 22:14:21.506837 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2867 22:14:21.510408 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2868 22:14:21.513479 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2869 22:14:21.520403 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2870 22:14:21.523781 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2871 22:14:21.527025 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2872 22:14:21.533382 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2873 22:14:21.537084 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2874 22:14:21.540150 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2875 22:14:21.543557 Total UI for P1: 0, mck2ui 16
2876 22:14:21.546651 best dqsien dly found for B0: ( 1, 3, 26)
2877 22:14:21.553271 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2878 22:14:21.556745 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2879 22:14:21.560728 Total UI for P1: 0, mck2ui 16
2880 22:14:21.563220 best dqsien dly found for B1: ( 1, 3, 30)
2881 22:14:21.566961 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2882 22:14:21.569896 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2883 22:14:21.569967
2884 22:14:21.573395 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2885 22:14:21.576720 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2886 22:14:21.580048 [Gating] SW calibration Done
2887 22:14:21.580143 ==
2888 22:14:21.583038 Dram Type= 6, Freq= 0, CH_0, rank 1
2889 22:14:21.586954 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2890 22:14:21.587051 ==
2891 22:14:21.589952 RX Vref Scan: 0
2892 22:14:21.590033
2893 22:14:21.593147 RX Vref 0 -> 0, step: 1
2894 22:14:21.593228
2895 22:14:21.593293 RX Delay -40 -> 252, step: 8
2896 22:14:21.599614 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2897 22:14:21.603067 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2898 22:14:21.606275 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2899 22:14:21.609540 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2900 22:14:21.612915 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2901 22:14:21.619771 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2902 22:14:21.623024 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2903 22:14:21.626898 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
2904 22:14:21.630197 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2905 22:14:21.633196 iDelay=200, Bit 9, Center 91 (24 ~ 159) 136
2906 22:14:21.639511 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
2907 22:14:21.642983 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2908 22:14:21.646716 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2909 22:14:21.649835 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
2910 22:14:21.653024 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2911 22:14:21.659579 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2912 22:14:21.659676 ==
2913 22:14:21.663241 Dram Type= 6, Freq= 0, CH_0, rank 1
2914 22:14:21.666227 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2915 22:14:21.666301 ==
2916 22:14:21.666364 DQS Delay:
2917 22:14:21.669962 DQS0 = 0, DQS1 = 0
2918 22:14:21.670037 DQM Delay:
2919 22:14:21.672902 DQM0 = 116, DQM1 = 109
2920 22:14:21.672996 DQ Delay:
2921 22:14:21.676172 DQ0 =111, DQ1 =119, DQ2 =111, DQ3 =111
2922 22:14:21.679418 DQ4 =119, DQ5 =111, DQ6 =127, DQ7 =119
2923 22:14:21.683116 DQ8 =99, DQ9 =91, DQ10 =111, DQ11 =103
2924 22:14:21.686410 DQ12 =115, DQ13 =119, DQ14 =119, DQ15 =115
2925 22:14:21.686490
2926 22:14:21.689238
2927 22:14:21.689308 ==
2928 22:14:21.692582 Dram Type= 6, Freq= 0, CH_0, rank 1
2929 22:14:21.696156 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2930 22:14:21.696235 ==
2931 22:14:21.696296
2932 22:14:21.696354
2933 22:14:21.699294 TX Vref Scan disable
2934 22:14:21.699373 == TX Byte 0 ==
2935 22:14:21.706183 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2936 22:14:21.709350 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2937 22:14:21.709423 == TX Byte 1 ==
2938 22:14:21.715853 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2939 22:14:21.719288 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2940 22:14:21.719360 ==
2941 22:14:21.722736 Dram Type= 6, Freq= 0, CH_0, rank 1
2942 22:14:21.726174 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2943 22:14:21.726255 ==
2944 22:14:21.738644 TX Vref=22, minBit 2, minWin=25, winSum=415
2945 22:14:21.742247 TX Vref=24, minBit 12, minWin=25, winSum=420
2946 22:14:21.745099 TX Vref=26, minBit 1, minWin=26, winSum=424
2947 22:14:21.748456 TX Vref=28, minBit 10, minWin=26, winSum=428
2948 22:14:21.751914 TX Vref=30, minBit 2, minWin=26, winSum=427
2949 22:14:21.758441 TX Vref=32, minBit 8, minWin=26, winSum=428
2950 22:14:21.761978 [TxChooseVref] Worse bit 10, Min win 26, Win sum 428, Final Vref 28
2951 22:14:21.762054
2952 22:14:21.765030 Final TX Range 1 Vref 28
2953 22:14:21.765115
2954 22:14:21.765182 ==
2955 22:14:21.768540 Dram Type= 6, Freq= 0, CH_0, rank 1
2956 22:14:21.771442 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2957 22:14:21.774950 ==
2958 22:14:21.775027
2959 22:14:21.775124
2960 22:14:21.775202 TX Vref Scan disable
2961 22:14:21.778616 == TX Byte 0 ==
2962 22:14:21.781875 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2963 22:14:21.788987 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2964 22:14:21.789062 == TX Byte 1 ==
2965 22:14:21.792028 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2966 22:14:21.802751 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2967 22:14:21.802897
2968 22:14:21.802995 [DATLAT]
2969 22:14:21.803122 Freq=1200, CH0 RK1
2970 22:14:21.803232
2971 22:14:21.803360 DATLAT Default: 0xd
2972 22:14:21.803458 0, 0xFFFF, sum = 0
2973 22:14:21.805252 1, 0xFFFF, sum = 0
2974 22:14:21.805360 2, 0xFFFF, sum = 0
2975 22:14:21.808959 3, 0xFFFF, sum = 0
2976 22:14:21.812282 4, 0xFFFF, sum = 0
2977 22:14:21.812372 5, 0xFFFF, sum = 0
2978 22:14:21.815197 6, 0xFFFF, sum = 0
2979 22:14:21.815302 7, 0xFFFF, sum = 0
2980 22:14:21.818393 8, 0xFFFF, sum = 0
2981 22:14:21.818499 9, 0xFFFF, sum = 0
2982 22:14:21.821728 10, 0xFFFF, sum = 0
2983 22:14:21.821807 11, 0xFFFF, sum = 0
2984 22:14:21.824827 12, 0x0, sum = 1
2985 22:14:21.824903 13, 0x0, sum = 2
2986 22:14:21.828559 14, 0x0, sum = 3
2987 22:14:21.828661 15, 0x0, sum = 4
2988 22:14:21.831948 best_step = 13
2989 22:14:21.832053
2990 22:14:21.832137 ==
2991 22:14:21.835174 Dram Type= 6, Freq= 0, CH_0, rank 1
2992 22:14:21.838371 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2993 22:14:21.838444 ==
2994 22:14:21.838504 RX Vref Scan: 0
2995 22:14:21.841717
2996 22:14:21.841790 RX Vref 0 -> 0, step: 1
2997 22:14:21.841855
2998 22:14:21.844897 RX Delay -21 -> 252, step: 4
2999 22:14:21.848504 iDelay=195, Bit 0, Center 114 (51 ~ 178) 128
3000 22:14:21.855153 iDelay=195, Bit 1, Center 116 (47 ~ 186) 140
3001 22:14:21.858106 iDelay=195, Bit 2, Center 112 (47 ~ 178) 132
3002 22:14:21.861458 iDelay=195, Bit 3, Center 112 (47 ~ 178) 132
3003 22:14:21.864796 iDelay=195, Bit 4, Center 118 (51 ~ 186) 136
3004 22:14:21.868201 iDelay=195, Bit 5, Center 108 (43 ~ 174) 132
3005 22:14:21.874629 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3006 22:14:21.878284 iDelay=195, Bit 7, Center 122 (55 ~ 190) 136
3007 22:14:21.881495 iDelay=195, Bit 8, Center 96 (31 ~ 162) 132
3008 22:14:21.884886 iDelay=195, Bit 9, Center 92 (27 ~ 158) 132
3009 22:14:21.888398 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
3010 22:14:21.895026 iDelay=195, Bit 11, Center 100 (31 ~ 170) 140
3011 22:14:21.898278 iDelay=195, Bit 12, Center 112 (47 ~ 178) 132
3012 22:14:21.901512 iDelay=195, Bit 13, Center 110 (43 ~ 178) 136
3013 22:14:21.904876 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3014 22:14:21.911571 iDelay=195, Bit 15, Center 112 (47 ~ 178) 132
3015 22:14:21.911680 ==
3016 22:14:21.914539 Dram Type= 6, Freq= 0, CH_0, rank 1
3017 22:14:21.918161 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3018 22:14:21.918240 ==
3019 22:14:21.918305 DQS Delay:
3020 22:14:21.920894 DQS0 = 0, DQS1 = 0
3021 22:14:21.920975 DQM Delay:
3022 22:14:21.924347 DQM0 = 116, DQM1 = 106
3023 22:14:21.924422 DQ Delay:
3024 22:14:21.927995 DQ0 =114, DQ1 =116, DQ2 =112, DQ3 =112
3025 22:14:21.930969 DQ4 =118, DQ5 =108, DQ6 =126, DQ7 =122
3026 22:14:21.934341 DQ8 =96, DQ9 =92, DQ10 =110, DQ11 =100
3027 22:14:21.937589 DQ12 =112, DQ13 =110, DQ14 =118, DQ15 =112
3028 22:14:21.937665
3029 22:14:21.937730
3030 22:14:21.947738 [DQSOSCAuto] RK1, (LSB)MR18= 0xfffc, (MSB)MR19= 0x303, tDQSOscB0 = 411 ps tDQSOscB1 = 410 ps
3031 22:14:21.950977 CH0 RK1: MR19=303, MR18=FFFC
3032 22:14:21.954512 CH0_RK1: MR19=0x303, MR18=0xFFFC, DQSOSC=410, MR23=63, INC=39, DEC=26
3033 22:14:21.957456 [RxdqsGatingPostProcess] freq 1200
3034 22:14:21.964237 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3035 22:14:21.967692 best DQS0 dly(2T, 0.5T) = (0, 11)
3036 22:14:21.970782 best DQS1 dly(2T, 0.5T) = (0, 12)
3037 22:14:21.974439 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3038 22:14:21.977656 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3039 22:14:21.980802 best DQS0 dly(2T, 0.5T) = (0, 11)
3040 22:14:21.983940 best DQS1 dly(2T, 0.5T) = (0, 11)
3041 22:14:21.987628 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3042 22:14:21.990708 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3043 22:14:21.994492 Pre-setting of DQS Precalculation
3044 22:14:21.997192 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3045 22:14:21.997276 ==
3046 22:14:22.000767 Dram Type= 6, Freq= 0, CH_1, rank 0
3047 22:14:22.003842 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3048 22:14:22.003911 ==
3049 22:14:22.010312 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3050 22:14:22.016972 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3051 22:14:22.024909 [CA 0] Center 37 (7~68) winsize 62
3052 22:14:22.028358 [CA 1] Center 37 (7~68) winsize 62
3053 22:14:22.032095 [CA 2] Center 35 (5~65) winsize 61
3054 22:14:22.035022 [CA 3] Center 34 (4~64) winsize 61
3055 22:14:22.038265 [CA 4] Center 35 (5~65) winsize 61
3056 22:14:22.041510 [CA 5] Center 33 (4~63) winsize 60
3057 22:14:22.041580
3058 22:14:22.045164 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3059 22:14:22.045238
3060 22:14:22.048473 [CATrainingPosCal] consider 1 rank data
3061 22:14:22.051999 u2DelayCellTimex100 = 270/100 ps
3062 22:14:22.055279 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3063 22:14:22.061337 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3064 22:14:22.064892 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3065 22:14:22.068630 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3066 22:14:22.071553 CA4 delay=35 (5~65),Diff = 2 PI (9 cell)
3067 22:14:22.074923 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3068 22:14:22.075004
3069 22:14:22.077888 CA PerBit enable=1, Macro0, CA PI delay=33
3070 22:14:22.077964
3071 22:14:22.081660 [CBTSetCACLKResult] CA Dly = 33
3072 22:14:22.081732 CS Dly: 5 (0~36)
3073 22:14:22.084718 ==
3074 22:14:22.087896 Dram Type= 6, Freq= 0, CH_1, rank 1
3075 22:14:22.091545 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3076 22:14:22.091624 ==
3077 22:14:22.098078 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3078 22:14:22.101069 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3079 22:14:22.110448 [CA 0] Center 37 (7~68) winsize 62
3080 22:14:22.113858 [CA 1] Center 37 (7~68) winsize 62
3081 22:14:22.117677 [CA 2] Center 35 (5~65) winsize 61
3082 22:14:22.120433 [CA 3] Center 33 (3~64) winsize 62
3083 22:14:22.123775 [CA 4] Center 34 (4~64) winsize 61
3084 22:14:22.127196 [CA 5] Center 33 (3~63) winsize 61
3085 22:14:22.127275
3086 22:14:22.130827 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3087 22:14:22.130928
3088 22:14:22.133785 [CATrainingPosCal] consider 2 rank data
3089 22:14:22.137052 u2DelayCellTimex100 = 270/100 ps
3090 22:14:22.140725 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3091 22:14:22.147524 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3092 22:14:22.150303 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3093 22:14:22.154679 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3094 22:14:22.157392 CA4 delay=34 (5~64),Diff = 1 PI (4 cell)
3095 22:14:22.160563 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3096 22:14:22.160633
3097 22:14:22.164239 CA PerBit enable=1, Macro0, CA PI delay=33
3098 22:14:22.164337
3099 22:14:22.167291 [CBTSetCACLKResult] CA Dly = 33
3100 22:14:22.167363 CS Dly: 6 (0~39)
3101 22:14:22.167425
3102 22:14:22.173970 ----->DramcWriteLeveling(PI) begin...
3103 22:14:22.174048 ==
3104 22:14:22.177162 Dram Type= 6, Freq= 0, CH_1, rank 0
3105 22:14:22.180213 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3106 22:14:22.180292 ==
3107 22:14:22.183585 Write leveling (Byte 0): 23 => 23
3108 22:14:22.186791 Write leveling (Byte 1): 26 => 26
3109 22:14:22.189997 DramcWriteLeveling(PI) end<-----
3110 22:14:22.190110
3111 22:14:22.190204 ==
3112 22:14:22.193472 Dram Type= 6, Freq= 0, CH_1, rank 0
3113 22:14:22.197042 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3114 22:14:22.197117 ==
3115 22:14:22.200287 [Gating] SW mode calibration
3116 22:14:22.207178 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3117 22:14:22.213544 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3118 22:14:22.216712 0 15 0 | B1->B0 | 2f2f 3434 | 1 0 | (1 1) (0 0)
3119 22:14:22.220246 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3120 22:14:22.227107 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3121 22:14:22.229922 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3122 22:14:22.233545 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3123 22:14:22.240128 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3124 22:14:22.243435 0 15 24 | B1->B0 | 3434 3232 | 0 0 | (0 1) (0 1)
3125 22:14:22.246656 0 15 28 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
3126 22:14:22.253581 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3127 22:14:22.256594 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3128 22:14:22.260093 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3129 22:14:22.263182 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3130 22:14:22.270088 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3131 22:14:22.273062 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3132 22:14:22.276512 1 0 24 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
3133 22:14:22.283329 1 0 28 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
3134 22:14:22.286434 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3135 22:14:22.289960 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3136 22:14:22.296437 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3137 22:14:22.300046 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3138 22:14:22.303719 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3139 22:14:22.310016 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3140 22:14:22.313396 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3141 22:14:22.316494 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3142 22:14:22.323337 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3143 22:14:22.326552 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3144 22:14:22.330140 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3145 22:14:22.336136 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3146 22:14:22.339748 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3147 22:14:22.343183 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3148 22:14:22.349628 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3149 22:14:22.352855 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3150 22:14:22.356493 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3151 22:14:22.363540 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3152 22:14:22.366527 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3153 22:14:22.369823 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3154 22:14:22.376081 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3155 22:14:22.379761 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3156 22:14:22.382968 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3157 22:14:22.386185 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3158 22:14:22.393213 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3159 22:14:22.396212 Total UI for P1: 0, mck2ui 16
3160 22:14:22.399685 best dqsien dly found for B0: ( 1, 3, 26)
3161 22:14:22.402780 Total UI for P1: 0, mck2ui 16
3162 22:14:22.406040 best dqsien dly found for B1: ( 1, 3, 28)
3163 22:14:22.409615 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3164 22:14:22.413099 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3165 22:14:22.413171
3166 22:14:22.416327 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3167 22:14:22.419567 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3168 22:14:22.422848 [Gating] SW calibration Done
3169 22:14:22.422923 ==
3170 22:14:22.426226 Dram Type= 6, Freq= 0, CH_1, rank 0
3171 22:14:22.429442 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3172 22:14:22.429526 ==
3173 22:14:22.432908 RX Vref Scan: 0
3174 22:14:22.432983
3175 22:14:22.435905 RX Vref 0 -> 0, step: 1
3176 22:14:22.436017
3177 22:14:22.436114 RX Delay -40 -> 252, step: 8
3178 22:14:22.442645 iDelay=200, Bit 0, Center 123 (48 ~ 199) 152
3179 22:14:22.445953 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3180 22:14:22.448985 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3181 22:14:22.452697 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3182 22:14:22.455840 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3183 22:14:22.462294 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3184 22:14:22.465972 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3185 22:14:22.469282 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3186 22:14:22.472193 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3187 22:14:22.475730 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
3188 22:14:22.482499 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3189 22:14:22.485995 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3190 22:14:22.488781 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3191 22:14:22.492263 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
3192 22:14:22.498880 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3193 22:14:22.502062 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3194 22:14:22.502142 ==
3195 22:14:22.505406 Dram Type= 6, Freq= 0, CH_1, rank 0
3196 22:14:22.508635 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3197 22:14:22.508708 ==
3198 22:14:22.508776 DQS Delay:
3199 22:14:22.512149 DQS0 = 0, DQS1 = 0
3200 22:14:22.512216 DQM Delay:
3201 22:14:22.515621 DQM0 = 115, DQM1 = 113
3202 22:14:22.515688 DQ Delay:
3203 22:14:22.518545 DQ0 =123, DQ1 =111, DQ2 =103, DQ3 =115
3204 22:14:22.521918 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =111
3205 22:14:22.525494 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
3206 22:14:22.531813 DQ12 =123, DQ13 =123, DQ14 =119, DQ15 =119
3207 22:14:22.531921
3208 22:14:22.532011
3209 22:14:22.532126 ==
3210 22:14:22.535288 Dram Type= 6, Freq= 0, CH_1, rank 0
3211 22:14:22.538782 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3212 22:14:22.538881 ==
3213 22:14:22.538959
3214 22:14:22.539017
3215 22:14:22.541501 TX Vref Scan disable
3216 22:14:22.541595 == TX Byte 0 ==
3217 22:14:22.548036 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
3218 22:14:22.551484 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
3219 22:14:22.551554 == TX Byte 1 ==
3220 22:14:22.558285 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3221 22:14:22.561246 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3222 22:14:22.561318 ==
3223 22:14:22.565193 Dram Type= 6, Freq= 0, CH_1, rank 0
3224 22:14:22.568172 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3225 22:14:22.568242 ==
3226 22:14:22.580734 TX Vref=22, minBit 3, minWin=24, winSum=407
3227 22:14:22.584556 TX Vref=24, minBit 2, minWin=25, winSum=414
3228 22:14:22.587327 TX Vref=26, minBit 3, minWin=25, winSum=422
3229 22:14:22.590799 TX Vref=28, minBit 3, minWin=26, winSum=427
3230 22:14:22.593865 TX Vref=30, minBit 3, minWin=26, winSum=430
3231 22:14:22.597431 TX Vref=32, minBit 9, minWin=26, winSum=430
3232 22:14:22.604309 [TxChooseVref] Worse bit 3, Min win 26, Win sum 430, Final Vref 30
3233 22:14:22.604427
3234 22:14:22.607716 Final TX Range 1 Vref 30
3235 22:14:22.607787
3236 22:14:22.607869 ==
3237 22:14:22.610998 Dram Type= 6, Freq= 0, CH_1, rank 0
3238 22:14:22.614469 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3239 22:14:22.614564 ==
3240 22:14:22.617995
3241 22:14:22.618068
3242 22:14:22.618165 TX Vref Scan disable
3243 22:14:22.621105 == TX Byte 0 ==
3244 22:14:22.624229 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
3245 22:14:22.627964 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
3246 22:14:22.630606 == TX Byte 1 ==
3247 22:14:22.634118 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3248 22:14:22.637415 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3249 22:14:22.637488
3250 22:14:22.640707 [DATLAT]
3251 22:14:22.640781 Freq=1200, CH1 RK0
3252 22:14:22.640850
3253 22:14:22.644363 DATLAT Default: 0xd
3254 22:14:22.644469 0, 0xFFFF, sum = 0
3255 22:14:22.647311 1, 0xFFFF, sum = 0
3256 22:14:22.647400 2, 0xFFFF, sum = 0
3257 22:14:22.650584 3, 0xFFFF, sum = 0
3258 22:14:22.650671 4, 0xFFFF, sum = 0
3259 22:14:22.654057 5, 0xFFFF, sum = 0
3260 22:14:22.657369 6, 0xFFFF, sum = 0
3261 22:14:22.657441 7, 0xFFFF, sum = 0
3262 22:14:22.660533 8, 0xFFFF, sum = 0
3263 22:14:22.660647 9, 0xFFFF, sum = 0
3264 22:14:22.664368 10, 0xFFFF, sum = 0
3265 22:14:22.664447 11, 0xFFFF, sum = 0
3266 22:14:22.667503 12, 0x0, sum = 1
3267 22:14:22.667577 13, 0x0, sum = 2
3268 22:14:22.670412 14, 0x0, sum = 3
3269 22:14:22.670499 15, 0x0, sum = 4
3270 22:14:22.673844 best_step = 13
3271 22:14:22.673922
3272 22:14:22.674008 ==
3273 22:14:22.677148 Dram Type= 6, Freq= 0, CH_1, rank 0
3274 22:14:22.680314 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3275 22:14:22.680423 ==
3276 22:14:22.680489 RX Vref Scan: 1
3277 22:14:22.680547
3278 22:14:22.683701 Set Vref Range= 32 -> 127
3279 22:14:22.683808
3280 22:14:22.687145 RX Vref 32 -> 127, step: 1
3281 22:14:22.687223
3282 22:14:22.690285 RX Delay -13 -> 252, step: 4
3283 22:14:22.690358
3284 22:14:22.693544 Set Vref, RX VrefLevel [Byte0]: 32
3285 22:14:22.697338 [Byte1]: 32
3286 22:14:22.697414
3287 22:14:22.700885 Set Vref, RX VrefLevel [Byte0]: 33
3288 22:14:22.703496 [Byte1]: 33
3289 22:14:22.707097
3290 22:14:22.707208 Set Vref, RX VrefLevel [Byte0]: 34
3291 22:14:22.710152 [Byte1]: 34
3292 22:14:22.714780
3293 22:14:22.714853 Set Vref, RX VrefLevel [Byte0]: 35
3294 22:14:22.718526 [Byte1]: 35
3295 22:14:22.722597
3296 22:14:22.722676 Set Vref, RX VrefLevel [Byte0]: 36
3297 22:14:22.725867 [Byte1]: 36
3298 22:14:22.730877
3299 22:14:22.730983 Set Vref, RX VrefLevel [Byte0]: 37
3300 22:14:22.734101 [Byte1]: 37
3301 22:14:22.738878
3302 22:14:22.738949 Set Vref, RX VrefLevel [Byte0]: 38
3303 22:14:22.741943 [Byte1]: 38
3304 22:14:22.746707
3305 22:14:22.746780 Set Vref, RX VrefLevel [Byte0]: 39
3306 22:14:22.749628 [Byte1]: 39
3307 22:14:22.754198
3308 22:14:22.754271 Set Vref, RX VrefLevel [Byte0]: 40
3309 22:14:22.757607 [Byte1]: 40
3310 22:14:22.761988
3311 22:14:22.762064 Set Vref, RX VrefLevel [Byte0]: 41
3312 22:14:22.765685 [Byte1]: 41
3313 22:14:22.769928
3314 22:14:22.769999 Set Vref, RX VrefLevel [Byte0]: 42
3315 22:14:22.773200 [Byte1]: 42
3316 22:14:22.778264
3317 22:14:22.778340 Set Vref, RX VrefLevel [Byte0]: 43
3318 22:14:22.781223 [Byte1]: 43
3319 22:14:22.785533
3320 22:14:22.785603 Set Vref, RX VrefLevel [Byte0]: 44
3321 22:14:22.789079 [Byte1]: 44
3322 22:14:22.793617
3323 22:14:22.793710 Set Vref, RX VrefLevel [Byte0]: 45
3324 22:14:22.796902 [Byte1]: 45
3325 22:14:22.801797
3326 22:14:22.801867 Set Vref, RX VrefLevel [Byte0]: 46
3327 22:14:22.804857 [Byte1]: 46
3328 22:14:22.809207
3329 22:14:22.809276 Set Vref, RX VrefLevel [Byte0]: 47
3330 22:14:22.812763 [Byte1]: 47
3331 22:14:22.817611
3332 22:14:22.817696 Set Vref, RX VrefLevel [Byte0]: 48
3333 22:14:22.820518 [Byte1]: 48
3334 22:14:22.825157
3335 22:14:22.825237 Set Vref, RX VrefLevel [Byte0]: 49
3336 22:14:22.828568 [Byte1]: 49
3337 22:14:22.832879
3338 22:14:22.832956 Set Vref, RX VrefLevel [Byte0]: 50
3339 22:14:22.836779 [Byte1]: 50
3340 22:14:22.840830
3341 22:14:22.840904 Set Vref, RX VrefLevel [Byte0]: 51
3342 22:14:22.844408 [Byte1]: 51
3343 22:14:22.848897
3344 22:14:22.848970 Set Vref, RX VrefLevel [Byte0]: 52
3345 22:14:22.852174 [Byte1]: 52
3346 22:14:22.856851
3347 22:14:22.856925 Set Vref, RX VrefLevel [Byte0]: 53
3348 22:14:22.859988 [Byte1]: 53
3349 22:14:22.864542
3350 22:14:22.864621 Set Vref, RX VrefLevel [Byte0]: 54
3351 22:14:22.868142 [Byte1]: 54
3352 22:14:22.872311
3353 22:14:22.872383 Set Vref, RX VrefLevel [Byte0]: 55
3354 22:14:22.876199 [Byte1]: 55
3355 22:14:22.880384
3356 22:14:22.880470 Set Vref, RX VrefLevel [Byte0]: 56
3357 22:14:22.883740 [Byte1]: 56
3358 22:14:22.888206
3359 22:14:22.888278 Set Vref, RX VrefLevel [Byte0]: 57
3360 22:14:22.891676 [Byte1]: 57
3361 22:14:22.896183
3362 22:14:22.896282 Set Vref, RX VrefLevel [Byte0]: 58
3363 22:14:22.899228 [Byte1]: 58
3364 22:14:22.904206
3365 22:14:22.904295 Set Vref, RX VrefLevel [Byte0]: 59
3366 22:14:22.907325 [Byte1]: 59
3367 22:14:22.912130
3368 22:14:22.912203 Set Vref, RX VrefLevel [Byte0]: 60
3369 22:14:22.915592 [Byte1]: 60
3370 22:14:22.919622
3371 22:14:22.919708 Set Vref, RX VrefLevel [Byte0]: 61
3372 22:14:22.922843 [Byte1]: 61
3373 22:14:22.927826
3374 22:14:22.927921 Set Vref, RX VrefLevel [Byte0]: 62
3375 22:14:22.931297 [Byte1]: 62
3376 22:14:22.935550
3377 22:14:22.935622 Set Vref, RX VrefLevel [Byte0]: 63
3378 22:14:22.938626 [Byte1]: 63
3379 22:14:22.943397
3380 22:14:22.943467 Set Vref, RX VrefLevel [Byte0]: 64
3381 22:14:22.946843 [Byte1]: 64
3382 22:14:22.951445
3383 22:14:22.951519 Set Vref, RX VrefLevel [Byte0]: 65
3384 22:14:22.954467 [Byte1]: 65
3385 22:14:22.959549
3386 22:14:22.959624 Final RX Vref Byte 0 = 50 to rank0
3387 22:14:22.962392 Final RX Vref Byte 1 = 50 to rank0
3388 22:14:22.966043 Final RX Vref Byte 0 = 50 to rank1
3389 22:14:22.968926 Final RX Vref Byte 1 = 50 to rank1==
3390 22:14:22.972257 Dram Type= 6, Freq= 0, CH_1, rank 0
3391 22:14:22.979065 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3392 22:14:22.979140 ==
3393 22:14:22.979208 DQS Delay:
3394 22:14:22.979266 DQS0 = 0, DQS1 = 0
3395 22:14:22.982625 DQM Delay:
3396 22:14:22.982695 DQM0 = 114, DQM1 = 112
3397 22:14:22.986072 DQ Delay:
3398 22:14:22.989199 DQ0 =120, DQ1 =108, DQ2 =106, DQ3 =114
3399 22:14:22.992751 DQ4 =110, DQ5 =122, DQ6 =126, DQ7 =110
3400 22:14:22.995937 DQ8 =98, DQ9 =102, DQ10 =112, DQ11 =106
3401 22:14:22.999333 DQ12 =120, DQ13 =120, DQ14 =118, DQ15 =120
3402 22:14:22.999406
3403 22:14:22.999474
3404 22:14:23.006267 [DQSOSCAuto] RK0, (LSB)MR18= 0xf1fd, (MSB)MR19= 0x303, tDQSOscB0 = 411 ps tDQSOscB1 = 416 ps
3405 22:14:23.009320 CH1 RK0: MR19=303, MR18=F1FD
3406 22:14:23.015598 CH1_RK0: MR19=0x303, MR18=0xF1FD, DQSOSC=411, MR23=63, INC=38, DEC=25
3407 22:14:23.015670
3408 22:14:23.019433 ----->DramcWriteLeveling(PI) begin...
3409 22:14:23.019504 ==
3410 22:14:23.022406 Dram Type= 6, Freq= 0, CH_1, rank 1
3411 22:14:23.025672 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3412 22:14:23.029219 ==
3413 22:14:23.029292 Write leveling (Byte 0): 24 => 24
3414 22:14:23.032482 Write leveling (Byte 1): 29 => 29
3415 22:14:23.035936 DramcWriteLeveling(PI) end<-----
3416 22:14:23.036005
3417 22:14:23.036115 ==
3418 22:14:23.039328 Dram Type= 6, Freq= 0, CH_1, rank 1
3419 22:14:23.046040 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3420 22:14:23.046111 ==
3421 22:14:23.046172 [Gating] SW mode calibration
3422 22:14:23.055467 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3423 22:14:23.058912 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3424 22:14:23.065478 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3425 22:14:23.069204 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3426 22:14:23.072213 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3427 22:14:23.078493 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3428 22:14:23.082216 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3429 22:14:23.085004 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3430 22:14:23.091841 0 15 24 | B1->B0 | 3434 2424 | 1 0 | (1 1) (1 0)
3431 22:14:23.095094 0 15 28 | B1->B0 | 3030 2323 | 0 0 | (0 1) (0 0)
3432 22:14:23.098346 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3433 22:14:23.104784 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3434 22:14:23.108143 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3435 22:14:23.111413 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3436 22:14:23.118283 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3437 22:14:23.121693 1 0 20 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
3438 22:14:23.124876 1 0 24 | B1->B0 | 2525 4545 | 0 0 | (0 0) (0 0)
3439 22:14:23.131902 1 0 28 | B1->B0 | 3737 4646 | 1 0 | (0 0) (0 0)
3440 22:14:23.134822 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3441 22:14:23.137858 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3442 22:14:23.144408 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3443 22:14:23.148285 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3444 22:14:23.151459 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3445 22:14:23.157560 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3446 22:14:23.160981 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3447 22:14:23.164560 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3448 22:14:23.171158 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3449 22:14:23.174383 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3450 22:14:23.177463 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3451 22:14:23.183985 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3452 22:14:23.187699 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3453 22:14:23.190467 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3454 22:14:23.197109 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3455 22:14:23.200848 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3456 22:14:23.203691 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3457 22:14:23.210186 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3458 22:14:23.213630 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3459 22:14:23.216971 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3460 22:14:23.223560 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3461 22:14:23.226356 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3462 22:14:23.230224 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3463 22:14:23.236387 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3464 22:14:23.239766 Total UI for P1: 0, mck2ui 16
3465 22:14:23.242979 best dqsien dly found for B0: ( 1, 3, 22)
3466 22:14:23.246826 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3467 22:14:23.249526 Total UI for P1: 0, mck2ui 16
3468 22:14:23.253335 best dqsien dly found for B1: ( 1, 3, 28)
3469 22:14:23.255900 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3470 22:14:23.259663 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3471 22:14:23.259761
3472 22:14:23.262825 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3473 22:14:23.265836 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3474 22:14:23.269196 [Gating] SW calibration Done
3475 22:14:23.269278 ==
3476 22:14:23.272611 Dram Type= 6, Freq= 0, CH_1, rank 1
3477 22:14:23.279006 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3478 22:14:23.279086 ==
3479 22:14:23.279150 RX Vref Scan: 0
3480 22:14:23.279210
3481 22:14:23.282649 RX Vref 0 -> 0, step: 1
3482 22:14:23.282750
3483 22:14:23.285566 RX Delay -40 -> 252, step: 8
3484 22:14:23.289298 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3485 22:14:23.292487 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3486 22:14:23.295702 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3487 22:14:23.302074 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3488 22:14:23.305660 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3489 22:14:23.308889 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3490 22:14:23.312358 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
3491 22:14:23.315367 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3492 22:14:23.321680 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3493 22:14:23.324987 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3494 22:14:23.328283 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3495 22:14:23.331677 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3496 22:14:23.335159 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3497 22:14:23.341582 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3498 22:14:23.344868 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
3499 22:14:23.348693 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3500 22:14:23.348815 ==
3501 22:14:23.351747 Dram Type= 6, Freq= 0, CH_1, rank 1
3502 22:14:23.354920 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3503 22:14:23.358243 ==
3504 22:14:23.358323 DQS Delay:
3505 22:14:23.358387 DQS0 = 0, DQS1 = 0
3506 22:14:23.361307 DQM Delay:
3507 22:14:23.361387 DQM0 = 114, DQM1 = 111
3508 22:14:23.364860 DQ Delay:
3509 22:14:23.367981 DQ0 =119, DQ1 =107, DQ2 =103, DQ3 =115
3510 22:14:23.371238 DQ4 =119, DQ5 =123, DQ6 =119, DQ7 =111
3511 22:14:23.374376 DQ8 =99, DQ9 =99, DQ10 =115, DQ11 =107
3512 22:14:23.378048 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119
3513 22:14:23.378129
3514 22:14:23.378192
3515 22:14:23.378252 ==
3516 22:14:23.381232 Dram Type= 6, Freq= 0, CH_1, rank 1
3517 22:14:23.384287 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3518 22:14:23.384367 ==
3519 22:14:23.387567
3520 22:14:23.387647
3521 22:14:23.387710 TX Vref Scan disable
3522 22:14:23.390879 == TX Byte 0 ==
3523 22:14:23.394446 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3524 22:14:23.397652 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3525 22:14:23.400993 == TX Byte 1 ==
3526 22:14:23.404557 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3527 22:14:23.407227 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3528 22:14:23.410805 ==
3529 22:14:23.413851 Dram Type= 6, Freq= 0, CH_1, rank 1
3530 22:14:23.417156 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3531 22:14:23.417252 ==
3532 22:14:23.429045 TX Vref=22, minBit 2, minWin=25, winSum=419
3533 22:14:23.431683 TX Vref=24, minBit 1, minWin=26, winSum=426
3534 22:14:23.435224 TX Vref=26, minBit 9, minWin=26, winSum=429
3535 22:14:23.438317 TX Vref=28, minBit 7, minWin=26, winSum=431
3536 22:14:23.441743 TX Vref=30, minBit 10, minWin=26, winSum=431
3537 22:14:23.448659 TX Vref=32, minBit 10, minWin=26, winSum=431
3538 22:14:23.451910 [TxChooseVref] Worse bit 7, Min win 26, Win sum 431, Final Vref 28
3539 22:14:23.451992
3540 22:14:23.455005 Final TX Range 1 Vref 28
3541 22:14:23.455087
3542 22:14:23.455191 ==
3543 22:14:23.458446 Dram Type= 6, Freq= 0, CH_1, rank 1
3544 22:14:23.461786 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3545 22:14:23.464674 ==
3546 22:14:23.464749
3547 22:14:23.464813
3548 22:14:23.464872 TX Vref Scan disable
3549 22:14:23.468189 == TX Byte 0 ==
3550 22:14:23.471518 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3551 22:14:23.478110 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3552 22:14:23.478212 == TX Byte 1 ==
3553 22:14:23.481582 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3554 22:14:23.488000 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3555 22:14:23.488093
3556 22:14:23.488159 [DATLAT]
3557 22:14:23.488249 Freq=1200, CH1 RK1
3558 22:14:23.488337
3559 22:14:23.491351 DATLAT Default: 0xd
3560 22:14:23.491445 0, 0xFFFF, sum = 0
3561 22:14:23.494536 1, 0xFFFF, sum = 0
3562 22:14:23.498243 2, 0xFFFF, sum = 0
3563 22:14:23.498353 3, 0xFFFF, sum = 0
3564 22:14:23.501571 4, 0xFFFF, sum = 0
3565 22:14:23.501643 5, 0xFFFF, sum = 0
3566 22:14:23.505035 6, 0xFFFF, sum = 0
3567 22:14:23.505105 7, 0xFFFF, sum = 0
3568 22:14:23.508001 8, 0xFFFF, sum = 0
3569 22:14:23.508131 9, 0xFFFF, sum = 0
3570 22:14:23.511012 10, 0xFFFF, sum = 0
3571 22:14:23.511113 11, 0xFFFF, sum = 0
3572 22:14:23.514695 12, 0x0, sum = 1
3573 22:14:23.514793 13, 0x0, sum = 2
3574 22:14:23.517803 14, 0x0, sum = 3
3575 22:14:23.517905 15, 0x0, sum = 4
3576 22:14:23.520877 best_step = 13
3577 22:14:23.520954
3578 22:14:23.521017 ==
3579 22:14:23.524023 Dram Type= 6, Freq= 0, CH_1, rank 1
3580 22:14:23.527836 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3581 22:14:23.527937 ==
3582 22:14:23.531196 RX Vref Scan: 0
3583 22:14:23.531294
3584 22:14:23.531367 RX Vref 0 -> 0, step: 1
3585 22:14:23.531440
3586 22:14:23.534522 RX Delay -13 -> 252, step: 4
3587 22:14:23.540957 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
3588 22:14:23.543923 iDelay=195, Bit 1, Center 112 (43 ~ 182) 140
3589 22:14:23.547355 iDelay=195, Bit 2, Center 106 (39 ~ 174) 136
3590 22:14:23.550850 iDelay=195, Bit 3, Center 112 (43 ~ 182) 140
3591 22:14:23.553862 iDelay=195, Bit 4, Center 114 (47 ~ 182) 136
3592 22:14:23.560754 iDelay=195, Bit 5, Center 124 (55 ~ 194) 140
3593 22:14:23.563956 iDelay=195, Bit 6, Center 122 (55 ~ 190) 136
3594 22:14:23.567293 iDelay=195, Bit 7, Center 112 (43 ~ 182) 140
3595 22:14:23.570329 iDelay=195, Bit 8, Center 100 (39 ~ 162) 124
3596 22:14:23.573809 iDelay=195, Bit 9, Center 102 (39 ~ 166) 128
3597 22:14:23.580660 iDelay=195, Bit 10, Center 114 (51 ~ 178) 128
3598 22:14:23.583727 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3599 22:14:23.586626 iDelay=195, Bit 12, Center 120 (59 ~ 182) 124
3600 22:14:23.590113 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3601 22:14:23.596609 iDelay=195, Bit 14, Center 116 (55 ~ 178) 124
3602 22:14:23.599862 iDelay=195, Bit 15, Center 120 (55 ~ 186) 132
3603 22:14:23.599978 ==
3604 22:14:23.603255 Dram Type= 6, Freq= 0, CH_1, rank 1
3605 22:14:23.606663 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3606 22:14:23.606753 ==
3607 22:14:23.609653 DQS Delay:
3608 22:14:23.609722 DQS0 = 0, DQS1 = 0
3609 22:14:23.609786 DQM Delay:
3610 22:14:23.613541 DQM0 = 115, DQM1 = 112
3611 22:14:23.613623 DQ Delay:
3612 22:14:23.616242 DQ0 =118, DQ1 =112, DQ2 =106, DQ3 =112
3613 22:14:23.619956 DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =112
3614 22:14:23.626541 DQ8 =100, DQ9 =102, DQ10 =114, DQ11 =106
3615 22:14:23.629448 DQ12 =120, DQ13 =118, DQ14 =116, DQ15 =120
3616 22:14:23.629547
3617 22:14:23.629640
3618 22:14:23.636157 [DQSOSCAuto] RK1, (LSB)MR18= 0xf709, (MSB)MR19= 0x304, tDQSOscB0 = 406 ps tDQSOscB1 = 413 ps
3619 22:14:23.639275 CH1 RK1: MR19=304, MR18=F709
3620 22:14:23.646057 CH1_RK1: MR19=0x304, MR18=0xF709, DQSOSC=406, MR23=63, INC=39, DEC=26
3621 22:14:23.649430 [RxdqsGatingPostProcess] freq 1200
3622 22:14:23.655997 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3623 22:14:23.658981 best DQS0 dly(2T, 0.5T) = (0, 11)
3624 22:14:23.659082 best DQS1 dly(2T, 0.5T) = (0, 11)
3625 22:14:23.662359 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3626 22:14:23.665648 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3627 22:14:23.668849 best DQS0 dly(2T, 0.5T) = (0, 11)
3628 22:14:23.672551 best DQS1 dly(2T, 0.5T) = (0, 11)
3629 22:14:23.675658 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3630 22:14:23.678679 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3631 22:14:23.682019 Pre-setting of DQS Precalculation
3632 22:14:23.689036 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3633 22:14:23.695356 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3634 22:14:23.702220 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3635 22:14:23.702325
3636 22:14:23.702416
3637 22:14:23.705468 [Calibration Summary] 2400 Mbps
3638 22:14:23.705541 CH 0, Rank 0
3639 22:14:23.708619 SW Impedance : PASS
3640 22:14:23.711691 DUTY Scan : NO K
3641 22:14:23.711790 ZQ Calibration : PASS
3642 22:14:23.715522 Jitter Meter : NO K
3643 22:14:23.718795 CBT Training : PASS
3644 22:14:23.718896 Write leveling : PASS
3645 22:14:23.721697 RX DQS gating : PASS
3646 22:14:23.724877 RX DQ/DQS(RDDQC) : PASS
3647 22:14:23.724954 TX DQ/DQS : PASS
3648 22:14:23.728594 RX DATLAT : PASS
3649 22:14:23.732023 RX DQ/DQS(Engine): PASS
3650 22:14:23.732134 TX OE : NO K
3651 22:14:23.735067 All Pass.
3652 22:14:23.735159
3653 22:14:23.735246 CH 0, Rank 1
3654 22:14:23.738188 SW Impedance : PASS
3655 22:14:23.738280 DUTY Scan : NO K
3656 22:14:23.741784 ZQ Calibration : PASS
3657 22:14:23.744778 Jitter Meter : NO K
3658 22:14:23.744846 CBT Training : PASS
3659 22:14:23.747880 Write leveling : PASS
3660 22:14:23.751477 RX DQS gating : PASS
3661 22:14:23.751559 RX DQ/DQS(RDDQC) : PASS
3662 22:14:23.754617 TX DQ/DQS : PASS
3663 22:14:23.754710 RX DATLAT : PASS
3664 22:14:23.758212 RX DQ/DQS(Engine): PASS
3665 22:14:23.761200 TX OE : NO K
3666 22:14:23.761273 All Pass.
3667 22:14:23.761338
3668 22:14:23.761395 CH 1, Rank 0
3669 22:14:23.764563 SW Impedance : PASS
3670 22:14:23.767998 DUTY Scan : NO K
3671 22:14:23.768121 ZQ Calibration : PASS
3672 22:14:23.771035 Jitter Meter : NO K
3673 22:14:23.774791 CBT Training : PASS
3674 22:14:23.774886 Write leveling : PASS
3675 22:14:23.778111 RX DQS gating : PASS
3676 22:14:23.781206 RX DQ/DQS(RDDQC) : PASS
3677 22:14:23.781273 TX DQ/DQS : PASS
3678 22:14:23.784521 RX DATLAT : PASS
3679 22:14:23.787499 RX DQ/DQS(Engine): PASS
3680 22:14:23.787596 TX OE : NO K
3681 22:14:23.790805 All Pass.
3682 22:14:23.790899
3683 22:14:23.790989 CH 1, Rank 1
3684 22:14:23.794139 SW Impedance : PASS
3685 22:14:23.794212 DUTY Scan : NO K
3686 22:14:23.797660 ZQ Calibration : PASS
3687 22:14:23.800720 Jitter Meter : NO K
3688 22:14:23.800791 CBT Training : PASS
3689 22:14:23.803884 Write leveling : PASS
3690 22:14:23.807713 RX DQS gating : PASS
3691 22:14:23.807809 RX DQ/DQS(RDDQC) : PASS
3692 22:14:23.810763 TX DQ/DQS : PASS
3693 22:14:23.814109 RX DATLAT : PASS
3694 22:14:23.814204 RX DQ/DQS(Engine): PASS
3695 22:14:23.817253 TX OE : NO K
3696 22:14:23.817345 All Pass.
3697 22:14:23.817431
3698 22:14:23.820441 DramC Write-DBI off
3699 22:14:23.824346 PER_BANK_REFRESH: Hybrid Mode
3700 22:14:23.824445 TX_TRACKING: ON
3701 22:14:23.833843 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3702 22:14:23.836973 [FAST_K] Save calibration result to emmc
3703 22:14:23.840157 dramc_set_vcore_voltage set vcore to 650000
3704 22:14:23.843579 Read voltage for 600, 5
3705 22:14:23.843660 Vio18 = 0
3706 22:14:23.843746 Vcore = 650000
3707 22:14:23.847242 Vdram = 0
3708 22:14:23.847353 Vddq = 0
3709 22:14:23.847448 Vmddr = 0
3710 22:14:23.853728 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3711 22:14:23.856627 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3712 22:14:23.859860 MEM_TYPE=3, freq_sel=19
3713 22:14:23.863452 sv_algorithm_assistance_LP4_1600
3714 22:14:23.866624 ============ PULL DRAM RESETB DOWN ============
3715 22:14:23.873357 ========== PULL DRAM RESETB DOWN end =========
3716 22:14:23.876736 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3717 22:14:23.879791 ===================================
3718 22:14:23.883021 LPDDR4 DRAM CONFIGURATION
3719 22:14:23.886161 ===================================
3720 22:14:23.886255 EX_ROW_EN[0] = 0x0
3721 22:14:23.890161 EX_ROW_EN[1] = 0x0
3722 22:14:23.890242 LP4Y_EN = 0x0
3723 22:14:23.893119 WORK_FSP = 0x0
3724 22:14:23.893200 WL = 0x2
3725 22:14:23.896267 RL = 0x2
3726 22:14:23.896362 BL = 0x2
3727 22:14:23.899230 RPST = 0x0
3728 22:14:23.899311 RD_PRE = 0x0
3729 22:14:23.902718 WR_PRE = 0x1
3730 22:14:23.905797 WR_PST = 0x0
3731 22:14:23.905879 DBI_WR = 0x0
3732 22:14:23.909067 DBI_RD = 0x0
3733 22:14:23.909148 OTF = 0x1
3734 22:14:23.912594 ===================================
3735 22:14:23.915835 ===================================
3736 22:14:23.919316 ANA top config
3737 22:14:23.922381 ===================================
3738 22:14:23.922463 DLL_ASYNC_EN = 0
3739 22:14:23.925467 ALL_SLAVE_EN = 1
3740 22:14:23.929129 NEW_RANK_MODE = 1
3741 22:14:23.932351 DLL_IDLE_MODE = 1
3742 22:14:23.932432 LP45_APHY_COMB_EN = 1
3743 22:14:23.935540 TX_ODT_DIS = 1
3744 22:14:23.939339 NEW_8X_MODE = 1
3745 22:14:23.942572 ===================================
3746 22:14:23.945878 ===================================
3747 22:14:23.948899 data_rate = 1200
3748 22:14:23.952225 CKR = 1
3749 22:14:23.955789 DQ_P2S_RATIO = 8
3750 22:14:23.958838 ===================================
3751 22:14:23.958953 CA_P2S_RATIO = 8
3752 22:14:23.961820 DQ_CA_OPEN = 0
3753 22:14:23.965131 DQ_SEMI_OPEN = 0
3754 22:14:23.968538 CA_SEMI_OPEN = 0
3755 22:14:23.971608 CA_FULL_RATE = 0
3756 22:14:23.975348 DQ_CKDIV4_EN = 1
3757 22:14:23.975456 CA_CKDIV4_EN = 1
3758 22:14:23.978404 CA_PREDIV_EN = 0
3759 22:14:23.981703 PH8_DLY = 0
3760 22:14:23.985024 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3761 22:14:23.988812 DQ_AAMCK_DIV = 4
3762 22:14:23.991912 CA_AAMCK_DIV = 4
3763 22:14:23.992014 CA_ADMCK_DIV = 4
3764 22:14:23.994755 DQ_TRACK_CA_EN = 0
3765 22:14:23.997898 CA_PICK = 600
3766 22:14:24.001596 CA_MCKIO = 600
3767 22:14:24.004793 MCKIO_SEMI = 0
3768 22:14:24.007900 PLL_FREQ = 2288
3769 22:14:24.011141 DQ_UI_PI_RATIO = 32
3770 22:14:24.014705 CA_UI_PI_RATIO = 0
3771 22:14:24.017874 ===================================
3772 22:14:24.020960 ===================================
3773 22:14:24.021037 memory_type:LPDDR4
3774 22:14:24.024358 GP_NUM : 10
3775 22:14:24.027594 SRAM_EN : 1
3776 22:14:24.027686 MD32_EN : 0
3777 22:14:24.031258 ===================================
3778 22:14:24.034115 [ANA_INIT] >>>>>>>>>>>>>>
3779 22:14:24.037407 <<<<<< [CONFIGURE PHASE]: ANA_TX
3780 22:14:24.041038 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3781 22:14:24.044022 ===================================
3782 22:14:24.047136 data_rate = 1200,PCW = 0X5800
3783 22:14:24.050669 ===================================
3784 22:14:24.053861 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3785 22:14:24.057570 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3786 22:14:24.063754 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3787 22:14:24.067453 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3788 22:14:24.070314 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3789 22:14:24.077195 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3790 22:14:24.077284 [ANA_INIT] flow start
3791 22:14:24.080395 [ANA_INIT] PLL >>>>>>>>
3792 22:14:24.083514 [ANA_INIT] PLL <<<<<<<<
3793 22:14:24.083596 [ANA_INIT] MIDPI >>>>>>>>
3794 22:14:24.086888 [ANA_INIT] MIDPI <<<<<<<<
3795 22:14:24.090048 [ANA_INIT] DLL >>>>>>>>
3796 22:14:24.090122 [ANA_INIT] flow end
3797 22:14:24.096898 ============ LP4 DIFF to SE enter ============
3798 22:14:24.099807 ============ LP4 DIFF to SE exit ============
3799 22:14:24.099881 [ANA_INIT] <<<<<<<<<<<<<
3800 22:14:24.102962 [Flow] Enable top DCM control >>>>>
3801 22:14:24.106414 [Flow] Enable top DCM control <<<<<
3802 22:14:24.109779 Enable DLL master slave shuffle
3803 22:14:24.116212 ==============================================================
3804 22:14:24.119553 Gating Mode config
3805 22:14:24.123046 ==============================================================
3806 22:14:24.126269 Config description:
3807 22:14:24.136449 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3808 22:14:24.142994 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3809 22:14:24.146109 SELPH_MODE 0: By rank 1: By Phase
3810 22:14:24.152534 ==============================================================
3811 22:14:24.156092 GAT_TRACK_EN = 1
3812 22:14:24.159123 RX_GATING_MODE = 2
3813 22:14:24.162208 RX_GATING_TRACK_MODE = 2
3814 22:14:24.165785 SELPH_MODE = 1
3815 22:14:24.168844 PICG_EARLY_EN = 1
3816 22:14:24.168944 VALID_LAT_VALUE = 1
3817 22:14:24.175417 ==============================================================
3818 22:14:24.178818 Enter into Gating configuration >>>>
3819 22:14:24.182216 Exit from Gating configuration <<<<
3820 22:14:24.185675 Enter into DVFS_PRE_config >>>>>
3821 22:14:24.195239 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3822 22:14:24.198468 Exit from DVFS_PRE_config <<<<<
3823 22:14:24.201750 Enter into PICG configuration >>>>
3824 22:14:24.205165 Exit from PICG configuration <<<<
3825 22:14:24.208644 [RX_INPUT] configuration >>>>>
3826 22:14:24.211803 [RX_INPUT] configuration <<<<<
3827 22:14:24.218649 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3828 22:14:24.221599 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3829 22:14:24.228572 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3830 22:14:24.234727 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3831 22:14:24.241194 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3832 22:14:24.247894 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3833 22:14:24.251264 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3834 22:14:24.254338 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3835 22:14:24.258127 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3836 22:14:24.264670 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3837 22:14:24.268055 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3838 22:14:24.270877 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3839 22:14:24.274505 ===================================
3840 22:14:24.277607 LPDDR4 DRAM CONFIGURATION
3841 22:14:24.281237 ===================================
3842 22:14:24.284071 EX_ROW_EN[0] = 0x0
3843 22:14:24.284152 EX_ROW_EN[1] = 0x0
3844 22:14:24.287934 LP4Y_EN = 0x0
3845 22:14:24.288048 WORK_FSP = 0x0
3846 22:14:24.291074 WL = 0x2
3847 22:14:24.291155 RL = 0x2
3848 22:14:24.294221 BL = 0x2
3849 22:14:24.294303 RPST = 0x0
3850 22:14:24.297422 RD_PRE = 0x0
3851 22:14:24.297519 WR_PRE = 0x1
3852 22:14:24.300573 WR_PST = 0x0
3853 22:14:24.300687 DBI_WR = 0x0
3854 22:14:24.303654 DBI_RD = 0x0
3855 22:14:24.307089 OTF = 0x1
3856 22:14:24.310271 ===================================
3857 22:14:24.314276 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3858 22:14:24.317024 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3859 22:14:24.320101 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3860 22:14:24.323930 ===================================
3861 22:14:24.326795 LPDDR4 DRAM CONFIGURATION
3862 22:14:24.330525 ===================================
3863 22:14:24.333793 EX_ROW_EN[0] = 0x10
3864 22:14:24.333873 EX_ROW_EN[1] = 0x0
3865 22:14:24.336850 LP4Y_EN = 0x0
3866 22:14:24.336946 WORK_FSP = 0x0
3867 22:14:24.340652 WL = 0x2
3868 22:14:24.340733 RL = 0x2
3869 22:14:24.343251 BL = 0x2
3870 22:14:24.343332 RPST = 0x0
3871 22:14:24.346733 RD_PRE = 0x0
3872 22:14:24.346844 WR_PRE = 0x1
3873 22:14:24.350028 WR_PST = 0x0
3874 22:14:24.350109 DBI_WR = 0x0
3875 22:14:24.353544 DBI_RD = 0x0
3876 22:14:24.356765 OTF = 0x1
3877 22:14:24.359760 ===================================
3878 22:14:24.363010 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3879 22:14:24.368464 nWR fixed to 30
3880 22:14:24.371563 [ModeRegInit_LP4] CH0 RK0
3881 22:14:24.371644 [ModeRegInit_LP4] CH0 RK1
3882 22:14:24.375293 [ModeRegInit_LP4] CH1 RK0
3883 22:14:24.378415 [ModeRegInit_LP4] CH1 RK1
3884 22:14:24.378496 match AC timing 17
3885 22:14:24.384886 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3886 22:14:24.388136 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3887 22:14:24.391362 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3888 22:14:24.398164 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3889 22:14:24.401617 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3890 22:14:24.401699 ==
3891 22:14:24.404857 Dram Type= 6, Freq= 0, CH_0, rank 0
3892 22:14:24.407988 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3893 22:14:24.408103 ==
3894 22:14:24.414479 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3895 22:14:24.421524 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3896 22:14:24.424634 [CA 0] Center 36 (6~67) winsize 62
3897 22:14:24.428038 [CA 1] Center 35 (5~66) winsize 62
3898 22:14:24.431062 [CA 2] Center 34 (4~65) winsize 62
3899 22:14:24.434696 [CA 3] Center 34 (4~65) winsize 62
3900 22:14:24.437857 [CA 4] Center 33 (3~64) winsize 62
3901 22:14:24.440999 [CA 5] Center 33 (3~64) winsize 62
3902 22:14:24.441097
3903 22:14:24.444334 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3904 22:14:24.444415
3905 22:14:24.447490 [CATrainingPosCal] consider 1 rank data
3906 22:14:24.451101 u2DelayCellTimex100 = 270/100 ps
3907 22:14:24.454193 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3908 22:14:24.457585 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3909 22:14:24.460555 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3910 22:14:24.464048 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3911 22:14:24.470709 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3912 22:14:24.473860 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3913 22:14:24.473941
3914 22:14:24.477560 CA PerBit enable=1, Macro0, CA PI delay=33
3915 22:14:24.477664
3916 22:14:24.480639 [CBTSetCACLKResult] CA Dly = 33
3917 22:14:24.480773 CS Dly: 6 (0~37)
3918 22:14:24.480867 ==
3919 22:14:24.484038 Dram Type= 6, Freq= 0, CH_0, rank 1
3920 22:14:24.490688 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3921 22:14:24.490785 ==
3922 22:14:24.494352 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3923 22:14:24.500809 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3924 22:14:24.504134 [CA 0] Center 36 (6~67) winsize 62
3925 22:14:24.507235 [CA 1] Center 36 (6~67) winsize 62
3926 22:14:24.510224 [CA 2] Center 34 (4~65) winsize 62
3927 22:14:24.513614 [CA 3] Center 34 (4~65) winsize 62
3928 22:14:24.516884 [CA 4] Center 33 (3~64) winsize 62
3929 22:14:24.520174 [CA 5] Center 33 (3~64) winsize 62
3930 22:14:24.520255
3931 22:14:24.523599 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3932 22:14:24.523680
3933 22:14:24.526926 [CATrainingPosCal] consider 2 rank data
3934 22:14:24.530520 u2DelayCellTimex100 = 270/100 ps
3935 22:14:24.533040 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3936 22:14:24.540044 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3937 22:14:24.543394 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3938 22:14:24.546673 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3939 22:14:24.550291 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3940 22:14:24.552983 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3941 22:14:24.553094
3942 22:14:24.556409 CA PerBit enable=1, Macro0, CA PI delay=33
3943 22:14:24.556490
3944 22:14:24.559909 [CBTSetCACLKResult] CA Dly = 33
3945 22:14:24.563108 CS Dly: 6 (0~38)
3946 22:14:24.563216
3947 22:14:24.566042 ----->DramcWriteLeveling(PI) begin...
3948 22:14:24.566154 ==
3949 22:14:24.570333 Dram Type= 6, Freq= 0, CH_0, rank 0
3950 22:14:24.572809 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3951 22:14:24.572892 ==
3952 22:14:24.576193 Write leveling (Byte 0): 32 => 32
3953 22:14:24.579376 Write leveling (Byte 1): 31 => 31
3954 22:14:24.582789 DramcWriteLeveling(PI) end<-----
3955 22:14:24.582867
3956 22:14:24.582968 ==
3957 22:14:24.585906 Dram Type= 6, Freq= 0, CH_0, rank 0
3958 22:14:24.589518 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3959 22:14:24.589593 ==
3960 22:14:24.592614 [Gating] SW mode calibration
3961 22:14:24.599425 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3962 22:14:24.605795 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3963 22:14:24.609181 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3964 22:14:24.612360 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3965 22:14:24.619254 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3966 22:14:24.622343 0 9 12 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
3967 22:14:24.625326 0 9 16 | B1->B0 | 2c2c 2424 | 0 0 | (1 1) (0 0)
3968 22:14:24.632193 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3969 22:14:24.635251 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3970 22:14:24.638771 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3971 22:14:24.645265 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3972 22:14:24.648629 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3973 22:14:24.651653 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3974 22:14:24.658333 0 10 12 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
3975 22:14:24.661937 0 10 16 | B1->B0 | 3737 4646 | 0 0 | (0 0) (0 0)
3976 22:14:24.664916 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3977 22:14:24.671705 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3978 22:14:24.675365 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3979 22:14:24.678081 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3980 22:14:24.684634 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3981 22:14:24.687951 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3982 22:14:24.691312 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3983 22:14:24.697884 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3984 22:14:24.701539 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3985 22:14:24.707965 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3986 22:14:24.711453 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3987 22:14:24.714599 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3988 22:14:24.721267 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3989 22:14:24.724234 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3990 22:14:24.727300 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3991 22:14:24.734237 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3992 22:14:24.737428 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3993 22:14:24.740975 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3994 22:14:24.747143 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3995 22:14:24.750563 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3996 22:14:24.754155 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3997 22:14:24.760779 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3998 22:14:24.763954 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3999 22:14:24.767062 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4000 22:14:24.770626 Total UI for P1: 0, mck2ui 16
4001 22:14:24.773978 best dqsien dly found for B0: ( 0, 13, 14)
4002 22:14:24.777013 Total UI for P1: 0, mck2ui 16
4003 22:14:24.780333 best dqsien dly found for B1: ( 0, 13, 14)
4004 22:14:24.783498 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4005 22:14:24.787016 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4006 22:14:24.787099
4007 22:14:24.790270 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4008 22:14:24.797285 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4009 22:14:24.797379 [Gating] SW calibration Done
4010 22:14:24.800366 ==
4011 22:14:24.803494 Dram Type= 6, Freq= 0, CH_0, rank 0
4012 22:14:24.806513 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4013 22:14:24.806596 ==
4014 22:14:24.806662 RX Vref Scan: 0
4015 22:14:24.806724
4016 22:14:24.810061 RX Vref 0 -> 0, step: 1
4017 22:14:24.810144
4018 22:14:24.813421 RX Delay -230 -> 252, step: 16
4019 22:14:24.816496 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4020 22:14:24.819620 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4021 22:14:24.826772 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4022 22:14:24.829652 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4023 22:14:24.832866 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4024 22:14:24.836603 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4025 22:14:24.842826 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4026 22:14:24.845893 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4027 22:14:24.849461 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4028 22:14:24.852696 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4029 22:14:24.859352 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4030 22:14:24.862332 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4031 22:14:24.865699 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4032 22:14:24.869594 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4033 22:14:24.876064 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4034 22:14:24.878988 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4035 22:14:24.879069 ==
4036 22:14:24.882354 Dram Type= 6, Freq= 0, CH_0, rank 0
4037 22:14:24.885342 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4038 22:14:24.885426 ==
4039 22:14:24.888793 DQS Delay:
4040 22:14:24.888875 DQS0 = 0, DQS1 = 0
4041 22:14:24.888940 DQM Delay:
4042 22:14:24.891911 DQM0 = 40, DQM1 = 34
4043 22:14:24.891992 DQ Delay:
4044 22:14:24.895415 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =33
4045 22:14:24.898786 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4046 22:14:24.902096 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =33
4047 22:14:24.905108 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4048 22:14:24.905190
4049 22:14:24.905274
4050 22:14:24.905336 ==
4051 22:14:24.908585 Dram Type= 6, Freq= 0, CH_0, rank 0
4052 22:14:24.914938 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4053 22:14:24.915020 ==
4054 22:14:24.915098
4055 22:14:24.915172
4056 22:14:24.915230 TX Vref Scan disable
4057 22:14:24.918966 == TX Byte 0 ==
4058 22:14:24.922584 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4059 22:14:24.929214 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4060 22:14:24.929296 == TX Byte 1 ==
4061 22:14:24.932501 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4062 22:14:24.938976 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4063 22:14:24.939062 ==
4064 22:14:24.942513 Dram Type= 6, Freq= 0, CH_0, rank 0
4065 22:14:24.945269 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4066 22:14:24.945351 ==
4067 22:14:24.945416
4068 22:14:24.945475
4069 22:14:24.948847 TX Vref Scan disable
4070 22:14:24.951843 == TX Byte 0 ==
4071 22:14:24.955086 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4072 22:14:24.958896 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4073 22:14:24.961979 == TX Byte 1 ==
4074 22:14:24.965365 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4075 22:14:24.968685 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4076 22:14:24.968766
4077 22:14:24.972146 [DATLAT]
4078 22:14:24.972227 Freq=600, CH0 RK0
4079 22:14:24.972293
4080 22:14:24.975096 DATLAT Default: 0x9
4081 22:14:24.975193 0, 0xFFFF, sum = 0
4082 22:14:24.978189 1, 0xFFFF, sum = 0
4083 22:14:24.978271 2, 0xFFFF, sum = 0
4084 22:14:24.981800 3, 0xFFFF, sum = 0
4085 22:14:24.981883 4, 0xFFFF, sum = 0
4086 22:14:24.984782 5, 0xFFFF, sum = 0
4087 22:14:24.984865 6, 0xFFFF, sum = 0
4088 22:14:24.988070 7, 0xFFFF, sum = 0
4089 22:14:24.988166 8, 0x0, sum = 1
4090 22:14:24.991650 9, 0x0, sum = 2
4091 22:14:24.991733 10, 0x0, sum = 3
4092 22:14:24.994515 11, 0x0, sum = 4
4093 22:14:24.994662 best_step = 9
4094 22:14:24.994741
4095 22:14:24.994801 ==
4096 22:14:24.998266 Dram Type= 6, Freq= 0, CH_0, rank 0
4097 22:14:25.001253 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4098 22:14:25.004626 ==
4099 22:14:25.004707 RX Vref Scan: 1
4100 22:14:25.004772
4101 22:14:25.007640 RX Vref 0 -> 0, step: 1
4102 22:14:25.007721
4103 22:14:25.011530 RX Delay -195 -> 252, step: 8
4104 22:14:25.011611
4105 22:14:25.014432 Set Vref, RX VrefLevel [Byte0]: 52
4106 22:14:25.017542 [Byte1]: 59
4107 22:14:25.017622
4108 22:14:25.021025 Final RX Vref Byte 0 = 52 to rank0
4109 22:14:25.024361 Final RX Vref Byte 1 = 59 to rank0
4110 22:14:25.027603 Final RX Vref Byte 0 = 52 to rank1
4111 22:14:25.030944 Final RX Vref Byte 1 = 59 to rank1==
4112 22:14:25.033877 Dram Type= 6, Freq= 0, CH_0, rank 0
4113 22:14:25.037407 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4114 22:14:25.037520 ==
4115 22:14:25.040526 DQS Delay:
4116 22:14:25.040628 DQS0 = 0, DQS1 = 0
4117 22:14:25.040719 DQM Delay:
4118 22:14:25.043732 DQM0 = 42, DQM1 = 32
4119 22:14:25.043834 DQ Delay:
4120 22:14:25.047089 DQ0 =44, DQ1 =44, DQ2 =36, DQ3 =36
4121 22:14:25.050433 DQ4 =44, DQ5 =32, DQ6 =52, DQ7 =48
4122 22:14:25.053984 DQ8 =24, DQ9 =16, DQ10 =32, DQ11 =28
4123 22:14:25.056705 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4124 22:14:25.056811
4125 22:14:25.056902
4126 22:14:25.066826 [DQSOSCAuto] RK0, (LSB)MR18= 0x5047, (MSB)MR19= 0x808, tDQSOscB0 = 396 ps tDQSOscB1 = 394 ps
4127 22:14:25.070038 CH0 RK0: MR19=808, MR18=5047
4128 22:14:25.076541 CH0_RK0: MR19=0x808, MR18=0x5047, DQSOSC=394, MR23=63, INC=168, DEC=112
4129 22:14:25.076637
4130 22:14:25.080139 ----->DramcWriteLeveling(PI) begin...
4131 22:14:25.080216 ==
4132 22:14:25.083463 Dram Type= 6, Freq= 0, CH_0, rank 1
4133 22:14:25.086514 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4134 22:14:25.086613 ==
4135 22:14:25.089945 Write leveling (Byte 0): 31 => 31
4136 22:14:25.093396 Write leveling (Byte 1): 30 => 30
4137 22:14:25.096395 DramcWriteLeveling(PI) end<-----
4138 22:14:25.096488
4139 22:14:25.096553 ==
4140 22:14:25.099926 Dram Type= 6, Freq= 0, CH_0, rank 1
4141 22:14:25.102896 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4142 22:14:25.103011 ==
4143 22:14:25.106500 [Gating] SW mode calibration
4144 22:14:25.112745 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4145 22:14:25.119601 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4146 22:14:25.122949 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4147 22:14:25.126135 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4148 22:14:25.132646 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4149 22:14:25.136131 0 9 12 | B1->B0 | 3434 3333 | 0 0 | (0 0) (0 1)
4150 22:14:25.139559 0 9 16 | B1->B0 | 2a2a 2525 | 1 0 | (1 1) (0 0)
4151 22:14:25.145820 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4152 22:14:25.149132 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4153 22:14:25.152837 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4154 22:14:25.159467 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4155 22:14:25.162169 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4156 22:14:25.165831 0 10 8 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
4157 22:14:25.172500 0 10 12 | B1->B0 | 2424 3333 | 1 0 | (0 0) (0 0)
4158 22:14:25.175228 0 10 16 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
4159 22:14:25.178878 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4160 22:14:25.185461 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4161 22:14:25.188661 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4162 22:14:25.191757 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4163 22:14:25.198310 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4164 22:14:25.201658 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4165 22:14:25.205248 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4166 22:14:25.211875 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4167 22:14:25.215046 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4168 22:14:25.218713 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4169 22:14:25.224804 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4170 22:14:25.227916 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4171 22:14:25.231684 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4172 22:14:25.237998 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4173 22:14:25.241205 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4174 22:14:25.244606 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4175 22:14:25.251639 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4176 22:14:25.254118 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4177 22:14:25.257657 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4178 22:14:25.263945 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4179 22:14:25.267488 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4180 22:14:25.270633 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4181 22:14:25.277389 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4182 22:14:25.280896 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4183 22:14:25.284119 Total UI for P1: 0, mck2ui 16
4184 22:14:25.287276 best dqsien dly found for B0: ( 0, 13, 12)
4185 22:14:25.290411 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4186 22:14:25.293815 Total UI for P1: 0, mck2ui 16
4187 22:14:25.296973 best dqsien dly found for B1: ( 0, 13, 14)
4188 22:14:25.303739 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4189 22:14:25.307021 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4190 22:14:25.307115
4191 22:14:25.310125 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4192 22:14:25.313706 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4193 22:14:25.316866 [Gating] SW calibration Done
4194 22:14:25.316940 ==
4195 22:14:25.320375 Dram Type= 6, Freq= 0, CH_0, rank 1
4196 22:14:25.323449 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4197 22:14:25.323529 ==
4198 22:14:25.326551 RX Vref Scan: 0
4199 22:14:25.326626
4200 22:14:25.326690 RX Vref 0 -> 0, step: 1
4201 22:14:25.326748
4202 22:14:25.330490 RX Delay -230 -> 252, step: 16
4203 22:14:25.336366 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4204 22:14:25.340133 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4205 22:14:25.342994 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4206 22:14:25.346347 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4207 22:14:25.349809 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4208 22:14:25.356475 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4209 22:14:25.359652 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4210 22:14:25.363073 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4211 22:14:25.366703 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4212 22:14:25.373054 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4213 22:14:25.376317 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4214 22:14:25.379525 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4215 22:14:25.382772 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4216 22:14:25.389900 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4217 22:14:25.392652 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4218 22:14:25.396148 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4219 22:14:25.396255 ==
4220 22:14:25.399397 Dram Type= 6, Freq= 0, CH_0, rank 1
4221 22:14:25.402514 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4222 22:14:25.406315 ==
4223 22:14:25.406392 DQS Delay:
4224 22:14:25.406455 DQS0 = 0, DQS1 = 0
4225 22:14:25.409226 DQM Delay:
4226 22:14:25.409299 DQM0 = 41, DQM1 = 33
4227 22:14:25.409364 DQ Delay:
4228 22:14:25.412467 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =41
4229 22:14:25.415603 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4230 22:14:25.419529 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =33
4231 22:14:25.422376 DQ12 =33, DQ13 =33, DQ14 =41, DQ15 =41
4232 22:14:25.422454
4233 22:14:25.426012
4234 22:14:25.426094 ==
4235 22:14:25.429092 Dram Type= 6, Freq= 0, CH_0, rank 1
4236 22:14:25.432650 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4237 22:14:25.432731 ==
4238 22:14:25.432796
4239 22:14:25.432857
4240 22:14:25.435572 TX Vref Scan disable
4241 22:14:25.435646 == TX Byte 0 ==
4242 22:14:25.442263 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4243 22:14:25.445371 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4244 22:14:25.445449 == TX Byte 1 ==
4245 22:14:25.452224 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4246 22:14:25.455486 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4247 22:14:25.455568 ==
4248 22:14:25.459238 Dram Type= 6, Freq= 0, CH_0, rank 1
4249 22:14:25.462319 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4250 22:14:25.462409 ==
4251 22:14:25.462487
4252 22:14:25.462545
4253 22:14:25.465381 TX Vref Scan disable
4254 22:14:25.468567 == TX Byte 0 ==
4255 22:14:25.471931 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4256 22:14:25.478537 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4257 22:14:25.478624 == TX Byte 1 ==
4258 22:14:25.482061 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4259 22:14:25.488469 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4260 22:14:25.488546
4261 22:14:25.488612 [DATLAT]
4262 22:14:25.488687 Freq=600, CH0 RK1
4263 22:14:25.488750
4264 22:14:25.491592 DATLAT Default: 0x9
4265 22:14:25.491696 0, 0xFFFF, sum = 0
4266 22:14:25.495492 1, 0xFFFF, sum = 0
4267 22:14:25.498107 2, 0xFFFF, sum = 0
4268 22:14:25.498214 3, 0xFFFF, sum = 0
4269 22:14:25.501576 4, 0xFFFF, sum = 0
4270 22:14:25.501693 5, 0xFFFF, sum = 0
4271 22:14:25.505098 6, 0xFFFF, sum = 0
4272 22:14:25.505217 7, 0xFFFF, sum = 0
4273 22:14:25.508014 8, 0x0, sum = 1
4274 22:14:25.508148 9, 0x0, sum = 2
4275 22:14:25.511538 10, 0x0, sum = 3
4276 22:14:25.511639 11, 0x0, sum = 4
4277 22:14:25.511729 best_step = 9
4278 22:14:25.511818
4279 22:14:25.514668 ==
4280 22:14:25.517880 Dram Type= 6, Freq= 0, CH_0, rank 1
4281 22:14:25.521416 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4282 22:14:25.521506 ==
4283 22:14:25.521578 RX Vref Scan: 0
4284 22:14:25.521667
4285 22:14:25.524697 RX Vref 0 -> 0, step: 1
4286 22:14:25.524794
4287 22:14:25.528217 RX Delay -179 -> 252, step: 8
4288 22:14:25.534640 iDelay=197, Bit 0, Center 40 (-107 ~ 188) 296
4289 22:14:25.537963 iDelay=197, Bit 1, Center 44 (-107 ~ 196) 304
4290 22:14:25.541136 iDelay=197, Bit 2, Center 36 (-115 ~ 188) 304
4291 22:14:25.544096 iDelay=197, Bit 3, Center 36 (-115 ~ 188) 304
4292 22:14:25.548015 iDelay=197, Bit 4, Center 44 (-107 ~ 196) 304
4293 22:14:25.554598 iDelay=197, Bit 5, Center 28 (-123 ~ 180) 304
4294 22:14:25.557502 iDelay=197, Bit 6, Center 48 (-99 ~ 196) 296
4295 22:14:25.560919 iDelay=197, Bit 7, Center 48 (-99 ~ 196) 296
4296 22:14:25.563936 iDelay=197, Bit 8, Center 24 (-131 ~ 180) 312
4297 22:14:25.571196 iDelay=197, Bit 9, Center 16 (-139 ~ 172) 312
4298 22:14:25.574116 iDelay=197, Bit 10, Center 36 (-123 ~ 196) 320
4299 22:14:25.577469 iDelay=197, Bit 11, Center 28 (-123 ~ 180) 304
4300 22:14:25.580586 iDelay=197, Bit 12, Center 40 (-115 ~ 196) 312
4301 22:14:25.586964 iDelay=197, Bit 13, Center 40 (-115 ~ 196) 312
4302 22:14:25.590638 iDelay=197, Bit 14, Center 44 (-107 ~ 196) 304
4303 22:14:25.594105 iDelay=197, Bit 15, Center 40 (-115 ~ 196) 312
4304 22:14:25.594200 ==
4305 22:14:25.597204 Dram Type= 6, Freq= 0, CH_0, rank 1
4306 22:14:25.600316 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4307 22:14:25.603859 ==
4308 22:14:25.603956 DQS Delay:
4309 22:14:25.604084 DQS0 = 0, DQS1 = 0
4310 22:14:25.606883 DQM Delay:
4311 22:14:25.606950 DQM0 = 40, DQM1 = 33
4312 22:14:25.610297 DQ Delay:
4313 22:14:25.610366 DQ0 =40, DQ1 =44, DQ2 =36, DQ3 =36
4314 22:14:25.613687 DQ4 =44, DQ5 =28, DQ6 =48, DQ7 =48
4315 22:14:25.617252 DQ8 =24, DQ9 =16, DQ10 =36, DQ11 =28
4316 22:14:25.620311 DQ12 =40, DQ13 =40, DQ14 =44, DQ15 =40
4317 22:14:25.623228
4318 22:14:25.623324
4319 22:14:25.630139 [DQSOSCAuto] RK1, (LSB)MR18= 0x4540, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 396 ps
4320 22:14:25.633383 CH0 RK1: MR19=808, MR18=4540
4321 22:14:25.639700 CH0_RK1: MR19=0x808, MR18=0x4540, DQSOSC=396, MR23=63, INC=167, DEC=111
4322 22:14:25.643295 [RxdqsGatingPostProcess] freq 600
4323 22:14:25.646578 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4324 22:14:25.649970 Pre-setting of DQS Precalculation
4325 22:14:25.656297 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4326 22:14:25.656374 ==
4327 22:14:25.659460 Dram Type= 6, Freq= 0, CH_1, rank 0
4328 22:14:25.663155 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4329 22:14:25.663253 ==
4330 22:14:25.669422 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4331 22:14:25.672993 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4332 22:14:25.677311 [CA 0] Center 36 (6~66) winsize 61
4333 22:14:25.680444 [CA 1] Center 36 (6~66) winsize 61
4334 22:14:25.684487 [CA 2] Center 34 (4~65) winsize 62
4335 22:14:25.687540 [CA 3] Center 34 (3~65) winsize 63
4336 22:14:25.690565 [CA 4] Center 34 (3~65) winsize 63
4337 22:14:25.694015 [CA 5] Center 33 (3~64) winsize 62
4338 22:14:25.694094
4339 22:14:25.697460 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4340 22:14:25.697539
4341 22:14:25.700508 [CATrainingPosCal] consider 1 rank data
4342 22:14:25.703689 u2DelayCellTimex100 = 270/100 ps
4343 22:14:25.707382 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4344 22:14:25.713520 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4345 22:14:25.717126 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4346 22:14:25.720199 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4347 22:14:25.723278 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4348 22:14:25.726832 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4349 22:14:25.726923
4350 22:14:25.730068 CA PerBit enable=1, Macro0, CA PI delay=33
4351 22:14:25.730200
4352 22:14:25.733839 [CBTSetCACLKResult] CA Dly = 33
4353 22:14:25.736505 CS Dly: 4 (0~35)
4354 22:14:25.736599 ==
4355 22:14:25.740207 Dram Type= 6, Freq= 0, CH_1, rank 1
4356 22:14:25.743041 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4357 22:14:25.743152 ==
4358 22:14:25.749970 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4359 22:14:25.753113 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4360 22:14:25.757519 [CA 0] Center 36 (6~66) winsize 61
4361 22:14:25.761401 [CA 1] Center 36 (6~66) winsize 61
4362 22:14:25.763834 [CA 2] Center 34 (4~65) winsize 62
4363 22:14:25.767492 [CA 3] Center 34 (3~65) winsize 63
4364 22:14:25.770390 [CA 4] Center 34 (4~65) winsize 62
4365 22:14:25.774262 [CA 5] Center 34 (3~65) winsize 63
4366 22:14:25.774360
4367 22:14:25.777380 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4368 22:14:25.777484
4369 22:14:25.780322 [CATrainingPosCal] consider 2 rank data
4370 22:14:25.783872 u2DelayCellTimex100 = 270/100 ps
4371 22:14:25.787188 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4372 22:14:25.793677 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4373 22:14:25.797473 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4374 22:14:25.800010 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4375 22:14:25.803736 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4376 22:14:25.806689 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4377 22:14:25.806799
4378 22:14:25.809825 CA PerBit enable=1, Macro0, CA PI delay=33
4379 22:14:25.809932
4380 22:14:25.813445 [CBTSetCACLKResult] CA Dly = 33
4381 22:14:25.816288 CS Dly: 5 (0~37)
4382 22:14:25.816389
4383 22:14:25.819745 ----->DramcWriteLeveling(PI) begin...
4384 22:14:25.819880 ==
4385 22:14:25.823133 Dram Type= 6, Freq= 0, CH_1, rank 0
4386 22:14:25.826226 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4387 22:14:25.826324 ==
4388 22:14:25.829683 Write leveling (Byte 0): 29 => 29
4389 22:14:25.833181 Write leveling (Byte 1): 32 => 32
4390 22:14:25.836356 DramcWriteLeveling(PI) end<-----
4391 22:14:25.836449
4392 22:14:25.836527 ==
4393 22:14:25.839465 Dram Type= 6, Freq= 0, CH_1, rank 0
4394 22:14:25.842798 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4395 22:14:25.842911 ==
4396 22:14:25.846383 [Gating] SW mode calibration
4397 22:14:25.852862 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4398 22:14:25.859664 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4399 22:14:25.862651 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4400 22:14:25.869327 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4401 22:14:25.872491 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4402 22:14:25.875845 0 9 12 | B1->B0 | 3030 2e2e | 0 0 | (0 1) (0 0)
4403 22:14:25.882394 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4404 22:14:25.885652 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4405 22:14:25.889406 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4406 22:14:25.892209 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4407 22:14:25.898963 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4408 22:14:25.902289 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4409 22:14:25.905434 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4410 22:14:25.912113 0 10 12 | B1->B0 | 3535 3737 | 0 1 | (0 0) (0 0)
4411 22:14:25.915350 0 10 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
4412 22:14:25.919224 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4413 22:14:25.925252 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4414 22:14:25.928852 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4415 22:14:25.931861 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4416 22:14:25.938375 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4417 22:14:25.941837 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4418 22:14:25.945039 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4419 22:14:25.951904 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4420 22:14:25.955199 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4421 22:14:25.958255 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4422 22:14:25.965001 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4423 22:14:25.968341 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4424 22:14:25.971711 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4425 22:14:25.978437 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4426 22:14:25.981598 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4427 22:14:25.987647 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4428 22:14:25.991029 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4429 22:14:25.994837 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4430 22:14:26.001213 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4431 22:14:26.004238 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4432 22:14:26.007586 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4433 22:14:26.014143 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4434 22:14:26.017444 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4435 22:14:26.020463 Total UI for P1: 0, mck2ui 16
4436 22:14:26.023985 best dqsien dly found for B0: ( 0, 13, 10)
4437 22:14:26.027359 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4438 22:14:26.030696 Total UI for P1: 0, mck2ui 16
4439 22:14:26.034029 best dqsien dly found for B1: ( 0, 13, 12)
4440 22:14:26.036926 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4441 22:14:26.040590 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4442 22:14:26.040672
4443 22:14:26.046979 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4444 22:14:26.050071 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4445 22:14:26.050180 [Gating] SW calibration Done
4446 22:14:26.053909 ==
4447 22:14:26.057163 Dram Type= 6, Freq= 0, CH_1, rank 0
4448 22:14:26.060220 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4449 22:14:26.060301 ==
4450 22:14:26.060366 RX Vref Scan: 0
4451 22:14:26.060445
4452 22:14:26.063875 RX Vref 0 -> 0, step: 1
4453 22:14:26.063955
4454 22:14:26.067086 RX Delay -230 -> 252, step: 16
4455 22:14:26.070337 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4456 22:14:26.073374 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4457 22:14:26.079931 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4458 22:14:26.083270 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4459 22:14:26.086821 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4460 22:14:26.089762 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4461 22:14:26.096266 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4462 22:14:26.099581 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4463 22:14:26.103464 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4464 22:14:26.106521 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4465 22:14:26.112954 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4466 22:14:26.116362 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4467 22:14:26.119472 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4468 22:14:26.122585 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4469 22:14:26.129268 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4470 22:14:26.132918 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4471 22:14:26.133002 ==
4472 22:14:26.136207 Dram Type= 6, Freq= 0, CH_1, rank 0
4473 22:14:26.139246 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4474 22:14:26.139331 ==
4475 22:14:26.142744 DQS Delay:
4476 22:14:26.142828 DQS0 = 0, DQS1 = 0
4477 22:14:26.142911 DQM Delay:
4478 22:14:26.145935 DQM0 = 43, DQM1 = 37
4479 22:14:26.146019 DQ Delay:
4480 22:14:26.149113 DQ0 =49, DQ1 =41, DQ2 =33, DQ3 =41
4481 22:14:26.152525 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =41
4482 22:14:26.155699 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =33
4483 22:14:26.159512 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =41
4484 22:14:26.159596
4485 22:14:26.159679
4486 22:14:26.159777 ==
4487 22:14:26.162729 Dram Type= 6, Freq= 0, CH_1, rank 0
4488 22:14:26.168962 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4489 22:14:26.169095 ==
4490 22:14:26.169176
4491 22:14:26.169237
4492 22:14:26.169296 TX Vref Scan disable
4493 22:14:26.172788 == TX Byte 0 ==
4494 22:14:26.176457 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4495 22:14:26.182270 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4496 22:14:26.182382 == TX Byte 1 ==
4497 22:14:26.185546 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4498 22:14:26.192445 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4499 22:14:26.192558 ==
4500 22:14:26.195751 Dram Type= 6, Freq= 0, CH_1, rank 0
4501 22:14:26.199137 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4502 22:14:26.199219 ==
4503 22:14:26.199284
4504 22:14:26.199343
4505 22:14:26.202186 TX Vref Scan disable
4506 22:14:26.205345 == TX Byte 0 ==
4507 22:14:26.208811 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4508 22:14:26.212006 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4509 22:14:26.215810 == TX Byte 1 ==
4510 22:14:26.218820 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4511 22:14:26.222265 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4512 22:14:26.222349
4513 22:14:26.222414 [DATLAT]
4514 22:14:26.225637 Freq=600, CH1 RK0
4515 22:14:26.225731
4516 22:14:26.228799 DATLAT Default: 0x9
4517 22:14:26.228889 0, 0xFFFF, sum = 0
4518 22:14:26.232254 1, 0xFFFF, sum = 0
4519 22:14:26.232334 2, 0xFFFF, sum = 0
4520 22:14:26.235367 3, 0xFFFF, sum = 0
4521 22:14:26.235480 4, 0xFFFF, sum = 0
4522 22:14:26.238628 5, 0xFFFF, sum = 0
4523 22:14:26.238727 6, 0xFFFF, sum = 0
4524 22:14:26.242383 7, 0xFFFF, sum = 0
4525 22:14:26.242481 8, 0x0, sum = 1
4526 22:14:26.245501 9, 0x0, sum = 2
4527 22:14:26.245575 10, 0x0, sum = 3
4528 22:14:26.248485 11, 0x0, sum = 4
4529 22:14:26.248557 best_step = 9
4530 22:14:26.248634
4531 22:14:26.248696 ==
4532 22:14:26.251977 Dram Type= 6, Freq= 0, CH_1, rank 0
4533 22:14:26.255011 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4534 22:14:26.255108 ==
4535 22:14:26.258672 RX Vref Scan: 1
4536 22:14:26.258768
4537 22:14:26.261874 RX Vref 0 -> 0, step: 1
4538 22:14:26.261945
4539 22:14:26.262017 RX Delay -179 -> 252, step: 8
4540 22:14:26.265051
4541 22:14:26.265129 Set Vref, RX VrefLevel [Byte0]: 50
4542 22:14:26.268461 [Byte1]: 50
4543 22:14:26.273199
4544 22:14:26.273296 Final RX Vref Byte 0 = 50 to rank0
4545 22:14:26.276267 Final RX Vref Byte 1 = 50 to rank0
4546 22:14:26.280148 Final RX Vref Byte 0 = 50 to rank1
4547 22:14:26.283585 Final RX Vref Byte 1 = 50 to rank1==
4548 22:14:26.286204 Dram Type= 6, Freq= 0, CH_1, rank 0
4549 22:14:26.292835 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4550 22:14:26.292911 ==
4551 22:14:26.292988 DQS Delay:
4552 22:14:26.296574 DQS0 = 0, DQS1 = 0
4553 22:14:26.296647 DQM Delay:
4554 22:14:26.296709 DQM0 = 41, DQM1 = 35
4555 22:14:26.299520 DQ Delay:
4556 22:14:26.302792 DQ0 =48, DQ1 =36, DQ2 =32, DQ3 =40
4557 22:14:26.306069 DQ4 =36, DQ5 =48, DQ6 =52, DQ7 =36
4558 22:14:26.309071 DQ8 =20, DQ9 =24, DQ10 =36, DQ11 =28
4559 22:14:26.312371 DQ12 =44, DQ13 =44, DQ14 =44, DQ15 =40
4560 22:14:26.312441
4561 22:14:26.312518
4562 22:14:26.318975 [DQSOSCAuto] RK0, (LSB)MR18= 0x2942, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 402 ps
4563 22:14:26.322525 CH1 RK0: MR19=808, MR18=2942
4564 22:14:26.328817 CH1_RK0: MR19=0x808, MR18=0x2942, DQSOSC=397, MR23=63, INC=166, DEC=110
4565 22:14:26.328901
4566 22:14:26.332458 ----->DramcWriteLeveling(PI) begin...
4567 22:14:26.332547 ==
4568 22:14:26.335548 Dram Type= 6, Freq= 0, CH_1, rank 1
4569 22:14:26.338956 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4570 22:14:26.339036 ==
4571 22:14:26.342049 Write leveling (Byte 0): 29 => 29
4572 22:14:26.345353 Write leveling (Byte 1): 29 => 29
4573 22:14:26.348820 DramcWriteLeveling(PI) end<-----
4574 22:14:26.348898
4575 22:14:26.348966 ==
4576 22:14:26.351947 Dram Type= 6, Freq= 0, CH_1, rank 1
4577 22:14:26.358988 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4578 22:14:26.359062 ==
4579 22:14:26.359124 [Gating] SW mode calibration
4580 22:14:26.368477 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4581 22:14:26.372377 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4582 22:14:26.375100 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4583 22:14:26.381951 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4584 22:14:26.384948 0 9 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
4585 22:14:26.388350 0 9 12 | B1->B0 | 3333 2e2e | 1 1 | (1 0) (1 0)
4586 22:14:26.394769 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4587 22:14:26.398186 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4588 22:14:26.401289 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4589 22:14:26.408165 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4590 22:14:26.411441 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4591 22:14:26.414670 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4592 22:14:26.421485 0 10 8 | B1->B0 | 2323 2424 | 0 1 | (0 0) (0 0)
4593 22:14:26.424622 0 10 12 | B1->B0 | 3232 4040 | 1 0 | (0 0) (0 0)
4594 22:14:26.427704 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4595 22:14:26.434447 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4596 22:14:26.437745 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4597 22:14:26.441067 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4598 22:14:26.447572 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4599 22:14:26.450810 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4600 22:14:26.454620 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4601 22:14:26.460648 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4602 22:14:26.464324 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4603 22:14:26.467316 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4604 22:14:26.474585 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4605 22:14:26.477329 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4606 22:14:26.480600 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4607 22:14:26.487292 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4608 22:14:26.490464 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4609 22:14:26.496907 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4610 22:14:26.500112 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4611 22:14:26.503566 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4612 22:14:26.509915 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4613 22:14:26.513167 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4614 22:14:26.516661 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4615 22:14:26.523171 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4616 22:14:26.526317 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4617 22:14:26.530019 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4618 22:14:26.533059 Total UI for P1: 0, mck2ui 16
4619 22:14:26.536577 best dqsien dly found for B1: ( 0, 13, 10)
4620 22:14:26.542651 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4621 22:14:26.542739 Total UI for P1: 0, mck2ui 16
4622 22:14:26.546271 best dqsien dly found for B0: ( 0, 13, 12)
4623 22:14:26.553002 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4624 22:14:26.556046 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4625 22:14:26.556125
4626 22:14:26.559138 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4627 22:14:26.562718 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4628 22:14:26.565875 [Gating] SW calibration Done
4629 22:14:26.565949 ==
4630 22:14:26.569380 Dram Type= 6, Freq= 0, CH_1, rank 1
4631 22:14:26.572411 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4632 22:14:26.572484 ==
4633 22:14:26.575929 RX Vref Scan: 0
4634 22:14:26.576013
4635 22:14:26.576090 RX Vref 0 -> 0, step: 1
4636 22:14:26.576153
4637 22:14:26.579177 RX Delay -230 -> 252, step: 16
4638 22:14:26.585659 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4639 22:14:26.588836 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4640 22:14:26.592282 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4641 22:14:26.596293 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4642 22:14:26.599174 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4643 22:14:26.605287 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4644 22:14:26.608431 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4645 22:14:26.612393 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4646 22:14:26.615577 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4647 22:14:26.621630 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4648 22:14:26.625164 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4649 22:14:26.628551 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4650 22:14:26.631760 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4651 22:14:26.638013 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4652 22:14:26.641511 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4653 22:14:26.644835 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4654 22:14:26.644933 ==
4655 22:14:26.648412 Dram Type= 6, Freq= 0, CH_1, rank 1
4656 22:14:26.654469 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4657 22:14:26.654569 ==
4658 22:14:26.654666 DQS Delay:
4659 22:14:26.658089 DQS0 = 0, DQS1 = 0
4660 22:14:26.658187 DQM Delay:
4661 22:14:26.658269 DQM0 = 40, DQM1 = 39
4662 22:14:26.661315 DQ Delay:
4663 22:14:26.664364 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =33
4664 22:14:26.667903 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =33
4665 22:14:26.670994 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =33
4666 22:14:26.674156 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =49
4667 22:14:26.674238
4668 22:14:26.674312
4669 22:14:26.674373 ==
4670 22:14:26.677544 Dram Type= 6, Freq= 0, CH_1, rank 1
4671 22:14:26.681068 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4672 22:14:26.681150 ==
4673 22:14:26.681216
4674 22:14:26.681276
4675 22:14:26.684633 TX Vref Scan disable
4676 22:14:26.687446 == TX Byte 0 ==
4677 22:14:26.691382 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4678 22:14:26.694040 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4679 22:14:26.697559 == TX Byte 1 ==
4680 22:14:26.701134 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4681 22:14:26.704113 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4682 22:14:26.704195 ==
4683 22:14:26.707642 Dram Type= 6, Freq= 0, CH_1, rank 1
4684 22:14:26.710471 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4685 22:14:26.713864 ==
4686 22:14:26.713963
4687 22:14:26.714059
4688 22:14:26.714163 TX Vref Scan disable
4689 22:14:26.718177 == TX Byte 0 ==
4690 22:14:26.721046 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4691 22:14:26.727682 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4692 22:14:26.727783 == TX Byte 1 ==
4693 22:14:26.730843 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4694 22:14:26.737538 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4695 22:14:26.737672
4696 22:14:26.737813 [DATLAT]
4697 22:14:26.737935 Freq=600, CH1 RK1
4698 22:14:26.738055
4699 22:14:26.741266 DATLAT Default: 0x9
4700 22:14:26.741391 0, 0xFFFF, sum = 0
4701 22:14:26.744502 1, 0xFFFF, sum = 0
4702 22:14:26.747424 2, 0xFFFF, sum = 0
4703 22:14:26.747532 3, 0xFFFF, sum = 0
4704 22:14:26.751013 4, 0xFFFF, sum = 0
4705 22:14:26.751114 5, 0xFFFF, sum = 0
4706 22:14:26.753926 6, 0xFFFF, sum = 0
4707 22:14:26.754026 7, 0xFFFF, sum = 0
4708 22:14:26.757372 8, 0x0, sum = 1
4709 22:14:26.757472 9, 0x0, sum = 2
4710 22:14:26.757572 10, 0x0, sum = 3
4711 22:14:26.760483 11, 0x0, sum = 4
4712 22:14:26.760583 best_step = 9
4713 22:14:26.760651
4714 22:14:26.764177 ==
4715 22:14:26.764276 Dram Type= 6, Freq= 0, CH_1, rank 1
4716 22:14:26.770622 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4717 22:14:26.770713 ==
4718 22:14:26.770810 RX Vref Scan: 0
4719 22:14:26.770904
4720 22:14:26.774117 RX Vref 0 -> 0, step: 1
4721 22:14:26.774215
4722 22:14:26.776969 RX Delay -179 -> 252, step: 8
4723 22:14:26.783710 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4724 22:14:26.787149 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4725 22:14:26.790219 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4726 22:14:26.793780 iDelay=205, Bit 3, Center 36 (-123 ~ 196) 320
4727 22:14:26.796890 iDelay=205, Bit 4, Center 40 (-115 ~ 196) 312
4728 22:14:26.803423 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4729 22:14:26.806988 iDelay=205, Bit 6, Center 44 (-107 ~ 196) 304
4730 22:14:26.809870 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4731 22:14:26.813498 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4732 22:14:26.820249 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4733 22:14:26.823033 iDelay=205, Bit 10, Center 40 (-115 ~ 196) 312
4734 22:14:26.826351 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4735 22:14:26.830133 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4736 22:14:26.836438 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4737 22:14:26.839702 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4738 22:14:26.842855 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4739 22:14:26.842932 ==
4740 22:14:26.846052 Dram Type= 6, Freq= 0, CH_1, rank 1
4741 22:14:26.849830 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4742 22:14:26.853130 ==
4743 22:14:26.853207 DQS Delay:
4744 22:14:26.853271 DQS0 = 0, DQS1 = 0
4745 22:14:26.856288 DQM Delay:
4746 22:14:26.856364 DQM0 = 37, DQM1 = 35
4747 22:14:26.859107 DQ Delay:
4748 22:14:26.862937 DQ0 =40, DQ1 =36, DQ2 =24, DQ3 =36
4749 22:14:26.866070 DQ4 =40, DQ5 =48, DQ6 =44, DQ7 =32
4750 22:14:26.869033 DQ8 =24, DQ9 =24, DQ10 =40, DQ11 =28
4751 22:14:26.872301 DQ12 =44, DQ13 =40, DQ14 =40, DQ15 =40
4752 22:14:26.872377
4753 22:14:26.872441
4754 22:14:26.879034 [DQSOSCAuto] RK1, (LSB)MR18= 0x3459, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 400 ps
4755 22:14:26.882481 CH1 RK1: MR19=808, MR18=3459
4756 22:14:26.888812 CH1_RK1: MR19=0x808, MR18=0x3459, DQSOSC=393, MR23=63, INC=169, DEC=113
4757 22:14:26.891921 [RxdqsGatingPostProcess] freq 600
4758 22:14:26.895606 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4759 22:14:26.898696 Pre-setting of DQS Precalculation
4760 22:14:26.905211 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4761 22:14:26.912363 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4762 22:14:26.918461 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4763 22:14:26.918540
4764 22:14:26.918604
4765 22:14:26.921678 [Calibration Summary] 1200 Mbps
4766 22:14:26.921754 CH 0, Rank 0
4767 22:14:26.925502 SW Impedance : PASS
4768 22:14:26.928430 DUTY Scan : NO K
4769 22:14:26.928506 ZQ Calibration : PASS
4770 22:14:26.931876 Jitter Meter : NO K
4771 22:14:26.935329 CBT Training : PASS
4772 22:14:26.935407 Write leveling : PASS
4773 22:14:26.938355 RX DQS gating : PASS
4774 22:14:26.941695 RX DQ/DQS(RDDQC) : PASS
4775 22:14:26.941769 TX DQ/DQS : PASS
4776 22:14:26.945299 RX DATLAT : PASS
4777 22:14:26.948723 RX DQ/DQS(Engine): PASS
4778 22:14:26.948794 TX OE : NO K
4779 22:14:26.951765 All Pass.
4780 22:14:26.951835
4781 22:14:26.951902 CH 0, Rank 1
4782 22:14:26.954946 SW Impedance : PASS
4783 22:14:26.955015 DUTY Scan : NO K
4784 22:14:26.958187 ZQ Calibration : PASS
4785 22:14:26.961314 Jitter Meter : NO K
4786 22:14:26.961388 CBT Training : PASS
4787 22:14:26.965233 Write leveling : PASS
4788 22:14:26.967781 RX DQS gating : PASS
4789 22:14:26.967854 RX DQ/DQS(RDDQC) : PASS
4790 22:14:26.971116 TX DQ/DQS : PASS
4791 22:14:26.974611 RX DATLAT : PASS
4792 22:14:26.974684 RX DQ/DQS(Engine): PASS
4793 22:14:26.977617 TX OE : NO K
4794 22:14:26.977692 All Pass.
4795 22:14:26.977756
4796 22:14:26.981574 CH 1, Rank 0
4797 22:14:26.981646 SW Impedance : PASS
4798 22:14:26.984506 DUTY Scan : NO K
4799 22:14:26.987908 ZQ Calibration : PASS
4800 22:14:26.987981 Jitter Meter : NO K
4801 22:14:26.991042 CBT Training : PASS
4802 22:14:26.991121 Write leveling : PASS
4803 22:14:26.994186 RX DQS gating : PASS
4804 22:14:26.997686 RX DQ/DQS(RDDQC) : PASS
4805 22:14:26.997757 TX DQ/DQS : PASS
4806 22:14:27.000784 RX DATLAT : PASS
4807 22:14:27.004092 RX DQ/DQS(Engine): PASS
4808 22:14:27.004162 TX OE : NO K
4809 22:14:27.007714 All Pass.
4810 22:14:27.007783
4811 22:14:27.007843 CH 1, Rank 1
4812 22:14:27.010893 SW Impedance : PASS
4813 22:14:27.010969 DUTY Scan : NO K
4814 22:14:27.014348 ZQ Calibration : PASS
4815 22:14:27.017209 Jitter Meter : NO K
4816 22:14:27.017280 CBT Training : PASS
4817 22:14:27.020968 Write leveling : PASS
4818 22:14:27.023858 RX DQS gating : PASS
4819 22:14:27.023928 RX DQ/DQS(RDDQC) : PASS
4820 22:14:27.026995 TX DQ/DQS : PASS
4821 22:14:27.030315 RX DATLAT : PASS
4822 22:14:27.030388 RX DQ/DQS(Engine): PASS
4823 22:14:27.033997 TX OE : NO K
4824 22:14:27.034073 All Pass.
4825 22:14:27.034136
4826 22:14:27.037040 DramC Write-DBI off
4827 22:14:27.040420 PER_BANK_REFRESH: Hybrid Mode
4828 22:14:27.040502 TX_TRACKING: ON
4829 22:14:27.050097 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4830 22:14:27.053599 [FAST_K] Save calibration result to emmc
4831 22:14:27.056821 dramc_set_vcore_voltage set vcore to 662500
4832 22:14:27.060148 Read voltage for 933, 3
4833 22:14:27.060222 Vio18 = 0
4834 22:14:27.060286 Vcore = 662500
4835 22:14:27.063383 Vdram = 0
4836 22:14:27.063451 Vddq = 0
4837 22:14:27.063513 Vmddr = 0
4838 22:14:27.069757 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4839 22:14:27.073091 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4840 22:14:27.076723 MEM_TYPE=3, freq_sel=17
4841 22:14:27.080100 sv_algorithm_assistance_LP4_1600
4842 22:14:27.082868 ============ PULL DRAM RESETB DOWN ============
4843 22:14:27.089483 ========== PULL DRAM RESETB DOWN end =========
4844 22:14:27.093348 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4845 22:14:27.096406 ===================================
4846 22:14:27.099692 LPDDR4 DRAM CONFIGURATION
4847 22:14:27.102716 ===================================
4848 22:14:27.102794 EX_ROW_EN[0] = 0x0
4849 22:14:27.105969 EX_ROW_EN[1] = 0x0
4850 22:14:27.106043 LP4Y_EN = 0x0
4851 22:14:27.109254 WORK_FSP = 0x0
4852 22:14:27.109333 WL = 0x3
4853 22:14:27.112374 RL = 0x3
4854 22:14:27.115659 BL = 0x2
4855 22:14:27.115734 RPST = 0x0
4856 22:14:27.119160 RD_PRE = 0x0
4857 22:14:27.119239 WR_PRE = 0x1
4858 22:14:27.122438 WR_PST = 0x0
4859 22:14:27.122542 DBI_WR = 0x0
4860 22:14:27.125887 DBI_RD = 0x0
4861 22:14:27.125965 OTF = 0x1
4862 22:14:27.129245 ===================================
4863 22:14:27.132397 ===================================
4864 22:14:27.135831 ANA top config
4865 22:14:27.138808 ===================================
4866 22:14:27.138883 DLL_ASYNC_EN = 0
4867 22:14:27.142607 ALL_SLAVE_EN = 1
4868 22:14:27.145802 NEW_RANK_MODE = 1
4869 22:14:27.148887 DLL_IDLE_MODE = 1
4870 22:14:27.152291 LP45_APHY_COMB_EN = 1
4871 22:14:27.152363 TX_ODT_DIS = 1
4872 22:14:27.155375 NEW_8X_MODE = 1
4873 22:14:27.158562 ===================================
4874 22:14:27.162308 ===================================
4875 22:14:27.165070 data_rate = 1866
4876 22:14:27.168549 CKR = 1
4877 22:14:27.171640 DQ_P2S_RATIO = 8
4878 22:14:27.175204 ===================================
4879 22:14:27.178253 CA_P2S_RATIO = 8
4880 22:14:27.178326 DQ_CA_OPEN = 0
4881 22:14:27.181496 DQ_SEMI_OPEN = 0
4882 22:14:27.185170 CA_SEMI_OPEN = 0
4883 22:14:27.188107 CA_FULL_RATE = 0
4884 22:14:27.191721 DQ_CKDIV4_EN = 1
4885 22:14:27.195119 CA_CKDIV4_EN = 1
4886 22:14:27.195228 CA_PREDIV_EN = 0
4887 22:14:27.198016 PH8_DLY = 0
4888 22:14:27.201110 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4889 22:14:27.204485 DQ_AAMCK_DIV = 4
4890 22:14:27.207743 CA_AAMCK_DIV = 4
4891 22:14:27.211439 CA_ADMCK_DIV = 4
4892 22:14:27.211541 DQ_TRACK_CA_EN = 0
4893 22:14:27.214783 CA_PICK = 933
4894 22:14:27.217818 CA_MCKIO = 933
4895 22:14:27.221484 MCKIO_SEMI = 0
4896 22:14:27.224190 PLL_FREQ = 3732
4897 22:14:27.227478 DQ_UI_PI_RATIO = 32
4898 22:14:27.231415 CA_UI_PI_RATIO = 0
4899 22:14:27.234338 ===================================
4900 22:14:27.237436 ===================================
4901 22:14:27.237517 memory_type:LPDDR4
4902 22:14:27.240924 GP_NUM : 10
4903 22:14:27.243975 SRAM_EN : 1
4904 22:14:27.244090 MD32_EN : 0
4905 22:14:27.247320 ===================================
4906 22:14:27.251099 [ANA_INIT] >>>>>>>>>>>>>>
4907 22:14:27.254150 <<<<<< [CONFIGURE PHASE]: ANA_TX
4908 22:14:27.257051 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4909 22:14:27.260592 ===================================
4910 22:14:27.263638 data_rate = 1866,PCW = 0X8f00
4911 22:14:27.266843 ===================================
4912 22:14:27.270282 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4913 22:14:27.273542 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4914 22:14:27.280282 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4915 22:14:27.286663 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4916 22:14:27.290330 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4917 22:14:27.293266 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4918 22:14:27.293337 [ANA_INIT] flow start
4919 22:14:27.296903 [ANA_INIT] PLL >>>>>>>>
4920 22:14:27.300713 [ANA_INIT] PLL <<<<<<<<
4921 22:14:27.300782 [ANA_INIT] MIDPI >>>>>>>>
4922 22:14:27.303173 [ANA_INIT] MIDPI <<<<<<<<
4923 22:14:27.306641 [ANA_INIT] DLL >>>>>>>>
4924 22:14:27.306710 [ANA_INIT] flow end
4925 22:14:27.313230 ============ LP4 DIFF to SE enter ============
4926 22:14:27.316607 ============ LP4 DIFF to SE exit ============
4927 22:14:27.319930 [ANA_INIT] <<<<<<<<<<<<<
4928 22:14:27.320079 [Flow] Enable top DCM control >>>>>
4929 22:14:27.323288 [Flow] Enable top DCM control <<<<<
4930 22:14:27.326823 Enable DLL master slave shuffle
4931 22:14:27.332966 ==============================================================
4932 22:14:27.336965 Gating Mode config
4933 22:14:27.339862 ==============================================================
4934 22:14:27.342872 Config description:
4935 22:14:27.352628 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4936 22:14:27.359192 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4937 22:14:27.363075 SELPH_MODE 0: By rank 1: By Phase
4938 22:14:27.369290 ==============================================================
4939 22:14:27.372529 GAT_TRACK_EN = 1
4940 22:14:27.375885 RX_GATING_MODE = 2
4941 22:14:27.378890 RX_GATING_TRACK_MODE = 2
4942 22:14:27.382555 SELPH_MODE = 1
4943 22:14:27.385730 PICG_EARLY_EN = 1
4944 22:14:27.385826 VALID_LAT_VALUE = 1
4945 22:14:27.392078 ==============================================================
4946 22:14:27.395566 Enter into Gating configuration >>>>
4947 22:14:27.398564 Exit from Gating configuration <<<<
4948 22:14:27.402284 Enter into DVFS_PRE_config >>>>>
4949 22:14:27.415392 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4950 22:14:27.415480 Exit from DVFS_PRE_config <<<<<
4951 22:14:27.418594 Enter into PICG configuration >>>>
4952 22:14:27.421595 Exit from PICG configuration <<<<
4953 22:14:27.424897 [RX_INPUT] configuration >>>>>
4954 22:14:27.428439 [RX_INPUT] configuration <<<<<
4955 22:14:27.435119 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4956 22:14:27.438016 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4957 22:14:27.444749 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4958 22:14:27.451326 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4959 22:14:27.457683 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4960 22:14:27.464560 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4961 22:14:27.467736 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4962 22:14:27.470968 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4963 22:14:27.477449 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4964 22:14:27.481168 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4965 22:14:27.484335 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4966 22:14:27.487780 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4967 22:14:27.490781 ===================================
4968 22:14:27.494076 LPDDR4 DRAM CONFIGURATION
4969 22:14:27.497646 ===================================
4970 22:14:27.500982 EX_ROW_EN[0] = 0x0
4971 22:14:27.501055 EX_ROW_EN[1] = 0x0
4972 22:14:27.504094 LP4Y_EN = 0x0
4973 22:14:27.504168 WORK_FSP = 0x0
4974 22:14:27.507372 WL = 0x3
4975 22:14:27.507440 RL = 0x3
4976 22:14:27.510411 BL = 0x2
4977 22:14:27.510482 RPST = 0x0
4978 22:14:27.513624 RD_PRE = 0x0
4979 22:14:27.517448 WR_PRE = 0x1
4980 22:14:27.517518 WR_PST = 0x0
4981 22:14:27.520446 DBI_WR = 0x0
4982 22:14:27.520513 DBI_RD = 0x0
4983 22:14:27.523837 OTF = 0x1
4984 22:14:27.526981 ===================================
4985 22:14:27.530195 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4986 22:14:27.533487 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4987 22:14:27.536872 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4988 22:14:27.540380 ===================================
4989 22:14:27.543379 LPDDR4 DRAM CONFIGURATION
4990 22:14:27.546872 ===================================
4991 22:14:27.549689 EX_ROW_EN[0] = 0x10
4992 22:14:27.549794 EX_ROW_EN[1] = 0x0
4993 22:14:27.553359 LP4Y_EN = 0x0
4994 22:14:27.553432 WORK_FSP = 0x0
4995 22:14:27.556576 WL = 0x3
4996 22:14:27.556658 RL = 0x3
4997 22:14:27.559953 BL = 0x2
4998 22:14:27.563529 RPST = 0x0
4999 22:14:27.563670 RD_PRE = 0x0
5000 22:14:27.566202 WR_PRE = 0x1
5001 22:14:27.566300 WR_PST = 0x0
5002 22:14:27.570031 DBI_WR = 0x0
5003 22:14:27.570134 DBI_RD = 0x0
5004 22:14:27.572872 OTF = 0x1
5005 22:14:27.576494 ===================================
5006 22:14:27.582472 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5007 22:14:27.586190 nWR fixed to 30
5008 22:14:27.586295 [ModeRegInit_LP4] CH0 RK0
5009 22:14:27.589155 [ModeRegInit_LP4] CH0 RK1
5010 22:14:27.592630 [ModeRegInit_LP4] CH1 RK0
5011 22:14:27.592740 [ModeRegInit_LP4] CH1 RK1
5012 22:14:27.596186 match AC timing 9
5013 22:14:27.599183 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5014 22:14:27.602804 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5015 22:14:27.609313 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5016 22:14:27.615584 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5017 22:14:27.618753 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5018 22:14:27.618846 ==
5019 22:14:27.622663 Dram Type= 6, Freq= 0, CH_0, rank 0
5020 22:14:27.626031 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5021 22:14:27.626112 ==
5022 22:14:27.632414 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5023 22:14:27.639004 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5024 22:14:27.642296 [CA 0] Center 37 (7~68) winsize 62
5025 22:14:27.645087 [CA 1] Center 37 (7~68) winsize 62
5026 22:14:27.649200 [CA 2] Center 34 (4~64) winsize 61
5027 22:14:27.652439 [CA 3] Center 34 (4~65) winsize 62
5028 22:14:27.655119 [CA 4] Center 33 (2~64) winsize 63
5029 22:14:27.658112 [CA 5] Center 32 (2~63) winsize 62
5030 22:14:27.658194
5031 22:14:27.661939 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5032 22:14:27.662019
5033 22:14:27.665021 [CATrainingPosCal] consider 1 rank data
5034 22:14:27.668236 u2DelayCellTimex100 = 270/100 ps
5035 22:14:27.671316 CA0 delay=37 (7~68),Diff = 5 PI (31 cell)
5036 22:14:27.674776 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5037 22:14:27.677901 CA2 delay=34 (4~64),Diff = 2 PI (12 cell)
5038 22:14:27.681196 CA3 delay=34 (4~65),Diff = 2 PI (12 cell)
5039 22:14:27.684720 CA4 delay=33 (2~64),Diff = 1 PI (6 cell)
5040 22:14:27.691075 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5041 22:14:27.691165
5042 22:14:27.694882 CA PerBit enable=1, Macro0, CA PI delay=32
5043 22:14:27.694985
5044 22:14:27.697603 [CBTSetCACLKResult] CA Dly = 32
5045 22:14:27.697706 CS Dly: 5 (0~36)
5046 22:14:27.697793 ==
5047 22:14:27.701170 Dram Type= 6, Freq= 0, CH_0, rank 1
5048 22:14:27.704374 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5049 22:14:27.708376 ==
5050 22:14:27.710834 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5051 22:14:27.717452 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5052 22:14:27.720988 [CA 0] Center 37 (7~68) winsize 62
5053 22:14:27.724259 [CA 1] Center 37 (7~68) winsize 62
5054 22:14:27.727466 [CA 2] Center 35 (5~65) winsize 61
5055 22:14:27.730810 [CA 3] Center 34 (4~65) winsize 62
5056 22:14:27.734008 [CA 4] Center 33 (3~64) winsize 62
5057 22:14:27.737223 [CA 5] Center 32 (2~63) winsize 62
5058 22:14:27.737306
5059 22:14:27.740705 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5060 22:14:27.740789
5061 22:14:27.743912 [CATrainingPosCal] consider 2 rank data
5062 22:14:27.747498 u2DelayCellTimex100 = 270/100 ps
5063 22:14:27.750473 CA0 delay=37 (7~68),Diff = 5 PI (31 cell)
5064 22:14:27.754199 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5065 22:14:27.760581 CA2 delay=34 (5~64),Diff = 2 PI (12 cell)
5066 22:14:27.763562 CA3 delay=34 (4~65),Diff = 2 PI (12 cell)
5067 22:14:27.766765 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5068 22:14:27.770109 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5069 22:14:27.770186
5070 22:14:27.773325 CA PerBit enable=1, Macro0, CA PI delay=32
5071 22:14:27.773399
5072 22:14:27.777006 [CBTSetCACLKResult] CA Dly = 32
5073 22:14:27.777118 CS Dly: 6 (0~39)
5074 22:14:27.777221
5075 22:14:27.780424 ----->DramcWriteLeveling(PI) begin...
5076 22:14:27.783599 ==
5077 22:14:27.786811 Dram Type= 6, Freq= 0, CH_0, rank 0
5078 22:14:27.790076 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5079 22:14:27.790151 ==
5080 22:14:27.793226 Write leveling (Byte 0): 31 => 31
5081 22:14:27.796359 Write leveling (Byte 1): 27 => 27
5082 22:14:27.800095 DramcWriteLeveling(PI) end<-----
5083 22:14:27.800169
5084 22:14:27.800231 ==
5085 22:14:27.803199 Dram Type= 6, Freq= 0, CH_0, rank 0
5086 22:14:27.806928 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5087 22:14:27.807028 ==
5088 22:14:27.810216 [Gating] SW mode calibration
5089 22:14:27.816467 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5090 22:14:27.823120 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5091 22:14:27.826233 0 14 0 | B1->B0 | 2424 3333 | 0 1 | (0 0) (1 1)
5092 22:14:27.829546 0 14 4 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
5093 22:14:27.835898 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5094 22:14:27.839120 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5095 22:14:27.842472 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5096 22:14:27.849106 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5097 22:14:27.852321 0 14 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
5098 22:14:27.855862 0 14 28 | B1->B0 | 3434 2f2f | 1 1 | (1 0) (1 0)
5099 22:14:27.862621 0 15 0 | B1->B0 | 2f2f 2323 | 1 0 | (1 1) (0 0)
5100 22:14:27.865854 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
5101 22:14:27.869684 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5102 22:14:27.875384 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5103 22:14:27.878809 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5104 22:14:27.882176 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5105 22:14:27.888494 0 15 24 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
5106 22:14:27.892282 0 15 28 | B1->B0 | 2323 3939 | 0 0 | (0 0) (0 0)
5107 22:14:27.895365 1 0 0 | B1->B0 | 3535 4646 | 0 0 | (1 1) (0 0)
5108 22:14:27.901588 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5109 22:14:27.905340 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5110 22:14:27.908459 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5111 22:14:27.914876 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5112 22:14:27.918011 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5113 22:14:27.921504 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5114 22:14:27.927790 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5115 22:14:27.931762 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5116 22:14:27.934486 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5117 22:14:27.941392 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5118 22:14:27.944291 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5119 22:14:27.948021 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5120 22:14:27.954359 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5121 22:14:27.957651 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5122 22:14:27.963978 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5123 22:14:27.967988 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5124 22:14:27.970854 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5125 22:14:27.977630 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5126 22:14:27.981084 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5127 22:14:27.983767 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5128 22:14:27.990936 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5129 22:14:27.993704 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5130 22:14:27.996941 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5131 22:14:28.003666 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5132 22:14:28.003779 Total UI for P1: 0, mck2ui 16
5133 22:14:28.010440 best dqsien dly found for B0: ( 1, 2, 28)
5134 22:14:28.013362 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5135 22:14:28.016798 Total UI for P1: 0, mck2ui 16
5136 22:14:28.020066 best dqsien dly found for B1: ( 1, 3, 0)
5137 22:14:28.023170 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5138 22:14:28.026389 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5139 22:14:28.026473
5140 22:14:28.029743 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5141 22:14:28.033443 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5142 22:14:28.036408 [Gating] SW calibration Done
5143 22:14:28.036489 ==
5144 22:14:28.040070 Dram Type= 6, Freq= 0, CH_0, rank 0
5145 22:14:28.043451 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5146 22:14:28.043533 ==
5147 22:14:28.046323 RX Vref Scan: 0
5148 22:14:28.046404
5149 22:14:28.049660 RX Vref 0 -> 0, step: 1
5150 22:14:28.049741
5151 22:14:28.049806 RX Delay -80 -> 252, step: 8
5152 22:14:28.056352 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5153 22:14:28.059662 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5154 22:14:28.063337 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5155 22:14:28.066646 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5156 22:14:28.069535 iDelay=208, Bit 4, Center 103 (8 ~ 199) 192
5157 22:14:28.075940 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5158 22:14:28.079219 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5159 22:14:28.082605 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5160 22:14:28.085692 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5161 22:14:28.089329 iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184
5162 22:14:28.092209 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5163 22:14:28.098820 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5164 22:14:28.102063 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5165 22:14:28.105848 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5166 22:14:28.108717 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5167 22:14:28.111980 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5168 22:14:28.115585 ==
5169 22:14:28.115665 Dram Type= 6, Freq= 0, CH_0, rank 0
5170 22:14:28.121875 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5171 22:14:28.121989 ==
5172 22:14:28.122085 DQS Delay:
5173 22:14:28.125238 DQS0 = 0, DQS1 = 0
5174 22:14:28.125319 DQM Delay:
5175 22:14:28.128380 DQM0 = 99, DQM1 = 88
5176 22:14:28.128462 DQ Delay:
5177 22:14:28.131670 DQ0 =103, DQ1 =99, DQ2 =95, DQ3 =95
5178 22:14:28.135056 DQ4 =103, DQ5 =87, DQ6 =107, DQ7 =107
5179 22:14:28.138272 DQ8 =83, DQ9 =75, DQ10 =87, DQ11 =83
5180 22:14:28.141938 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5181 22:14:28.142020
5182 22:14:28.142084
5183 22:14:28.142143 ==
5184 22:14:28.145124 Dram Type= 6, Freq= 0, CH_0, rank 0
5185 22:14:28.148573 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5186 22:14:28.148696 ==
5187 22:14:28.148808
5188 22:14:28.151626
5189 22:14:28.151706 TX Vref Scan disable
5190 22:14:28.155242 == TX Byte 0 ==
5191 22:14:28.158034 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5192 22:14:28.161590 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5193 22:14:28.164741 == TX Byte 1 ==
5194 22:14:28.168087 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5195 22:14:28.171565 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5196 22:14:28.171646 ==
5197 22:14:28.174501 Dram Type= 6, Freq= 0, CH_0, rank 0
5198 22:14:28.181217 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5199 22:14:28.181299 ==
5200 22:14:28.181364
5201 22:14:28.181461
5202 22:14:28.184434 TX Vref Scan disable
5203 22:14:28.184515 == TX Byte 0 ==
5204 22:14:28.191184 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5205 22:14:28.194327 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5206 22:14:28.194438 == TX Byte 1 ==
5207 22:14:28.200770 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5208 22:14:28.204419 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5209 22:14:28.204514
5210 22:14:28.204578 [DATLAT]
5211 22:14:28.207742 Freq=933, CH0 RK0
5212 22:14:28.207866
5213 22:14:28.207984 DATLAT Default: 0xd
5214 22:14:28.210977 0, 0xFFFF, sum = 0
5215 22:14:28.211059 1, 0xFFFF, sum = 0
5216 22:14:28.214414 2, 0xFFFF, sum = 0
5217 22:14:28.214496 3, 0xFFFF, sum = 0
5218 22:14:28.217429 4, 0xFFFF, sum = 0
5219 22:14:28.217542 5, 0xFFFF, sum = 0
5220 22:14:28.221146 6, 0xFFFF, sum = 0
5221 22:14:28.221257 7, 0xFFFF, sum = 0
5222 22:14:28.224068 8, 0xFFFF, sum = 0
5223 22:14:28.227277 9, 0xFFFF, sum = 0
5224 22:14:28.227374 10, 0x0, sum = 1
5225 22:14:28.227440 11, 0x0, sum = 2
5226 22:14:28.230831 12, 0x0, sum = 3
5227 22:14:28.230947 13, 0x0, sum = 4
5228 22:14:28.234077 best_step = 11
5229 22:14:28.234198
5230 22:14:28.234292 ==
5231 22:14:28.237558 Dram Type= 6, Freq= 0, CH_0, rank 0
5232 22:14:28.240405 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5233 22:14:28.240487 ==
5234 22:14:28.243678 RX Vref Scan: 1
5235 22:14:28.243759
5236 22:14:28.246966 RX Vref 0 -> 0, step: 1
5237 22:14:28.247060
5238 22:14:28.247139 RX Delay -61 -> 252, step: 4
5239 22:14:28.247200
5240 22:14:28.250318 Set Vref, RX VrefLevel [Byte0]: 52
5241 22:14:28.253915 [Byte1]: 59
5242 22:14:28.258142
5243 22:14:28.258223 Final RX Vref Byte 0 = 52 to rank0
5244 22:14:28.262079 Final RX Vref Byte 1 = 59 to rank0
5245 22:14:28.264757 Final RX Vref Byte 0 = 52 to rank1
5246 22:14:28.268399 Final RX Vref Byte 1 = 59 to rank1==
5247 22:14:28.271335 Dram Type= 6, Freq= 0, CH_0, rank 0
5248 22:14:28.277933 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5249 22:14:28.278015 ==
5250 22:14:28.278101 DQS Delay:
5251 22:14:28.281009 DQS0 = 0, DQS1 = 0
5252 22:14:28.281107 DQM Delay:
5253 22:14:28.281174 DQM0 = 99, DQM1 = 88
5254 22:14:28.284444 DQ Delay:
5255 22:14:28.287542 DQ0 =100, DQ1 =100, DQ2 =94, DQ3 =96
5256 22:14:28.290813 DQ4 =100, DQ5 =90, DQ6 =108, DQ7 =106
5257 22:14:28.294040 DQ8 =80, DQ9 =74, DQ10 =88, DQ11 =84
5258 22:14:28.297469 DQ12 =96, DQ13 =92, DQ14 =98, DQ15 =92
5259 22:14:28.297539
5260 22:14:28.297599
5261 22:14:28.304006 [DQSOSCAuto] RK0, (LSB)MR18= 0x1610, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 414 ps
5262 22:14:28.307228 CH0 RK0: MR19=505, MR18=1610
5263 22:14:28.313896 CH0_RK0: MR19=0x505, MR18=0x1610, DQSOSC=414, MR23=63, INC=63, DEC=42
5264 22:14:28.313980
5265 22:14:28.317017 ----->DramcWriteLeveling(PI) begin...
5266 22:14:28.317089 ==
5267 22:14:28.320835 Dram Type= 6, Freq= 0, CH_0, rank 1
5268 22:14:28.324332 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5269 22:14:28.327315 ==
5270 22:14:28.327409 Write leveling (Byte 0): 30 => 30
5271 22:14:28.330518 Write leveling (Byte 1): 27 => 27
5272 22:14:28.334030 DramcWriteLeveling(PI) end<-----
5273 22:14:28.334099
5274 22:14:28.334159 ==
5275 22:14:28.337171 Dram Type= 6, Freq= 0, CH_0, rank 1
5276 22:14:28.343706 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5277 22:14:28.343790 ==
5278 22:14:28.347001 [Gating] SW mode calibration
5279 22:14:28.353671 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5280 22:14:28.357155 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5281 22:14:28.363591 0 14 0 | B1->B0 | 2525 3434 | 0 0 | (0 0) (0 0)
5282 22:14:28.366809 0 14 4 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
5283 22:14:28.370083 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5284 22:14:28.376779 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5285 22:14:28.380339 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5286 22:14:28.383209 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5287 22:14:28.390451 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5288 22:14:28.393102 0 14 28 | B1->B0 | 3434 2e2e | 0 0 | (0 1) (0 1)
5289 22:14:28.397215 0 15 0 | B1->B0 | 2e2e 2323 | 0 0 | (0 0) (0 0)
5290 22:14:28.403170 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
5291 22:14:28.406228 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5292 22:14:28.409445 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5293 22:14:28.416095 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5294 22:14:28.419186 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5295 22:14:28.422876 0 15 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5296 22:14:28.429138 0 15 28 | B1->B0 | 2b2b 3b3b | 0 0 | (0 0) (0 0)
5297 22:14:28.432563 1 0 0 | B1->B0 | 3939 4646 | 0 0 | (1 1) (0 0)
5298 22:14:28.435877 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5299 22:14:28.442415 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5300 22:14:28.446104 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5301 22:14:28.449164 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5302 22:14:28.455512 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5303 22:14:28.459318 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5304 22:14:28.462550 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5305 22:14:28.468626 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5306 22:14:28.472500 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5307 22:14:28.475393 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5308 22:14:28.482033 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5309 22:14:28.485228 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5310 22:14:28.488430 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5311 22:14:28.495176 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5312 22:14:28.498803 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5313 22:14:28.501829 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5314 22:14:28.508710 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5315 22:14:28.511801 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5316 22:14:28.514782 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5317 22:14:28.521670 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5318 22:14:28.524975 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5319 22:14:28.528185 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5320 22:14:28.535083 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5321 22:14:28.535189 Total UI for P1: 0, mck2ui 16
5322 22:14:28.541600 best dqsien dly found for B0: ( 1, 2, 24)
5323 22:14:28.544704 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5324 22:14:28.547726 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5325 22:14:28.551357 Total UI for P1: 0, mck2ui 16
5326 22:14:28.554368 best dqsien dly found for B1: ( 1, 2, 30)
5327 22:14:28.557946 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5328 22:14:28.561233 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5329 22:14:28.561313
5330 22:14:28.567333 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5331 22:14:28.570942 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5332 22:14:28.574251 [Gating] SW calibration Done
5333 22:14:28.574335 ==
5334 22:14:28.577470 Dram Type= 6, Freq= 0, CH_0, rank 1
5335 22:14:28.580571 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5336 22:14:28.580651 ==
5337 22:14:28.580715 RX Vref Scan: 0
5338 22:14:28.580774
5339 22:14:28.583813 RX Vref 0 -> 0, step: 1
5340 22:14:28.583893
5341 22:14:28.587006 RX Delay -80 -> 252, step: 8
5342 22:14:28.590677 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5343 22:14:28.593545 iDelay=200, Bit 1, Center 103 (8 ~ 199) 192
5344 22:14:28.600489 iDelay=200, Bit 2, Center 95 (0 ~ 191) 192
5345 22:14:28.603657 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5346 22:14:28.607033 iDelay=200, Bit 4, Center 99 (0 ~ 199) 200
5347 22:14:28.610220 iDelay=200, Bit 5, Center 83 (-8 ~ 175) 184
5348 22:14:28.613262 iDelay=200, Bit 6, Center 107 (16 ~ 199) 184
5349 22:14:28.616957 iDelay=200, Bit 7, Center 107 (16 ~ 199) 184
5350 22:14:28.623701 iDelay=200, Bit 8, Center 83 (-8 ~ 175) 184
5351 22:14:28.626776 iDelay=200, Bit 9, Center 79 (-8 ~ 167) 176
5352 22:14:28.630197 iDelay=200, Bit 10, Center 91 (0 ~ 183) 184
5353 22:14:28.633226 iDelay=200, Bit 11, Center 83 (-8 ~ 175) 184
5354 22:14:28.636511 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5355 22:14:28.643227 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5356 22:14:28.646469 iDelay=200, Bit 14, Center 99 (8 ~ 191) 184
5357 22:14:28.649511 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5358 22:14:28.649593 ==
5359 22:14:28.652929 Dram Type= 6, Freq= 0, CH_0, rank 1
5360 22:14:28.656550 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5361 22:14:28.656633 ==
5362 22:14:28.659656 DQS Delay:
5363 22:14:28.659769 DQS0 = 0, DQS1 = 0
5364 22:14:28.663160 DQM Delay:
5365 22:14:28.663242 DQM0 = 98, DQM1 = 90
5366 22:14:28.663308 DQ Delay:
5367 22:14:28.666252 DQ0 =95, DQ1 =103, DQ2 =95, DQ3 =95
5368 22:14:28.669621 DQ4 =99, DQ5 =83, DQ6 =107, DQ7 =107
5369 22:14:28.672848 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =83
5370 22:14:28.676206 DQ12 =95, DQ13 =95, DQ14 =99, DQ15 =95
5371 22:14:28.676288
5372 22:14:28.676353
5373 22:14:28.679469 ==
5374 22:14:28.682666 Dram Type= 6, Freq= 0, CH_0, rank 1
5375 22:14:28.685914 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5376 22:14:28.685997 ==
5377 22:14:28.686062
5378 22:14:28.686133
5379 22:14:28.689611 TX Vref Scan disable
5380 22:14:28.689693 == TX Byte 0 ==
5381 22:14:28.695489 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5382 22:14:28.699252 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5383 22:14:28.699334 == TX Byte 1 ==
5384 22:14:28.705840 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5385 22:14:28.708797 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5386 22:14:28.708879 ==
5387 22:14:28.712383 Dram Type= 6, Freq= 0, CH_0, rank 1
5388 22:14:28.715867 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5389 22:14:28.715940 ==
5390 22:14:28.716002
5391 22:14:28.716098
5392 22:14:28.718905 TX Vref Scan disable
5393 22:14:28.721975 == TX Byte 0 ==
5394 22:14:28.725613 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5395 22:14:28.728688 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5396 22:14:28.731850 == TX Byte 1 ==
5397 22:14:28.735058 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5398 22:14:28.738207 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5399 22:14:28.738322
5400 22:14:28.741902 [DATLAT]
5401 22:14:28.741983 Freq=933, CH0 RK1
5402 22:14:28.742049
5403 22:14:28.745290 DATLAT Default: 0xb
5404 22:14:28.745372 0, 0xFFFF, sum = 0
5405 22:14:28.748433 1, 0xFFFF, sum = 0
5406 22:14:28.748507 2, 0xFFFF, sum = 0
5407 22:14:28.751959 3, 0xFFFF, sum = 0
5408 22:14:28.752083 4, 0xFFFF, sum = 0
5409 22:14:28.754976 5, 0xFFFF, sum = 0
5410 22:14:28.755074 6, 0xFFFF, sum = 0
5411 22:14:28.758140 7, 0xFFFF, sum = 0
5412 22:14:28.758213 8, 0xFFFF, sum = 0
5413 22:14:28.761718 9, 0xFFFF, sum = 0
5414 22:14:28.761789 10, 0x0, sum = 1
5415 22:14:28.765106 11, 0x0, sum = 2
5416 22:14:28.765176 12, 0x0, sum = 3
5417 22:14:28.768123 13, 0x0, sum = 4
5418 22:14:28.768194 best_step = 11
5419 22:14:28.768254
5420 22:14:28.768311 ==
5421 22:14:28.771369 Dram Type= 6, Freq= 0, CH_0, rank 1
5422 22:14:28.778416 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5423 22:14:28.778522 ==
5424 22:14:28.778584 RX Vref Scan: 0
5425 22:14:28.778643
5426 22:14:28.781230 RX Vref 0 -> 0, step: 1
5427 22:14:28.781300
5428 22:14:28.784600 RX Delay -53 -> 252, step: 4
5429 22:14:28.787819 iDelay=195, Bit 0, Center 96 (11 ~ 182) 172
5430 22:14:28.794493 iDelay=195, Bit 1, Center 98 (7 ~ 190) 184
5431 22:14:28.797804 iDelay=195, Bit 2, Center 96 (7 ~ 186) 180
5432 22:14:28.801143 iDelay=195, Bit 3, Center 94 (7 ~ 182) 176
5433 22:14:28.804342 iDelay=195, Bit 4, Center 102 (11 ~ 194) 184
5434 22:14:28.807667 iDelay=195, Bit 5, Center 88 (-1 ~ 178) 180
5435 22:14:28.810802 iDelay=195, Bit 6, Center 108 (23 ~ 194) 172
5436 22:14:28.817383 iDelay=195, Bit 7, Center 104 (19 ~ 190) 172
5437 22:14:28.821587 iDelay=195, Bit 8, Center 82 (-5 ~ 170) 176
5438 22:14:28.824303 iDelay=195, Bit 9, Center 76 (-9 ~ 162) 172
5439 22:14:28.827632 iDelay=195, Bit 10, Center 88 (-1 ~ 178) 180
5440 22:14:28.830667 iDelay=195, Bit 11, Center 82 (-5 ~ 170) 176
5441 22:14:28.837875 iDelay=195, Bit 12, Center 94 (7 ~ 182) 176
5442 22:14:28.840808 iDelay=195, Bit 13, Center 94 (7 ~ 182) 176
5443 22:14:28.843967 iDelay=195, Bit 14, Center 98 (7 ~ 190) 184
5444 22:14:28.847029 iDelay=195, Bit 15, Center 96 (7 ~ 186) 180
5445 22:14:28.847102 ==
5446 22:14:28.850707 Dram Type= 6, Freq= 0, CH_0, rank 1
5447 22:14:28.854011 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5448 22:14:28.856971 ==
5449 22:14:28.857045 DQS Delay:
5450 22:14:28.857106 DQS0 = 0, DQS1 = 0
5451 22:14:28.860145 DQM Delay:
5452 22:14:28.860215 DQM0 = 98, DQM1 = 88
5453 22:14:28.863425 DQ Delay:
5454 22:14:28.866987 DQ0 =96, DQ1 =98, DQ2 =96, DQ3 =94
5455 22:14:28.870000 DQ4 =102, DQ5 =88, DQ6 =108, DQ7 =104
5456 22:14:28.873246 DQ8 =82, DQ9 =76, DQ10 =88, DQ11 =82
5457 22:14:28.876463 DQ12 =94, DQ13 =94, DQ14 =98, DQ15 =96
5458 22:14:28.876552
5459 22:14:28.876633
5460 22:14:28.883359 [DQSOSCAuto] RK1, (LSB)MR18= 0x1410, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 415 ps
5461 22:14:28.887107 CH0 RK1: MR19=505, MR18=1410
5462 22:14:28.893350 CH0_RK1: MR19=0x505, MR18=0x1410, DQSOSC=415, MR23=63, INC=62, DEC=41
5463 22:14:28.896714 [RxdqsGatingPostProcess] freq 933
5464 22:14:28.900184 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5465 22:14:28.903529 best DQS0 dly(2T, 0.5T) = (0, 10)
5466 22:14:28.906676 best DQS1 dly(2T, 0.5T) = (0, 11)
5467 22:14:28.909888 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5468 22:14:28.913125 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5469 22:14:28.916363 best DQS0 dly(2T, 0.5T) = (0, 10)
5470 22:14:28.919737 best DQS1 dly(2T, 0.5T) = (0, 10)
5471 22:14:28.923227 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5472 22:14:28.926335 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5473 22:14:28.929748 Pre-setting of DQS Precalculation
5474 22:14:28.932921 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5475 22:14:28.936366 ==
5476 22:14:28.940090 Dram Type= 6, Freq= 0, CH_1, rank 0
5477 22:14:28.942727 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5478 22:14:28.942801 ==
5479 22:14:28.945871 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5480 22:14:28.952307 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5481 22:14:28.956212 [CA 0] Center 36 (6~67) winsize 62
5482 22:14:28.959526 [CA 1] Center 36 (6~67) winsize 62
5483 22:14:28.962796 [CA 2] Center 34 (4~65) winsize 62
5484 22:14:28.965929 [CA 3] Center 34 (3~65) winsize 63
5485 22:14:28.969305 [CA 4] Center 34 (4~65) winsize 62
5486 22:14:28.973135 [CA 5] Center 33 (3~64) winsize 62
5487 22:14:28.973217
5488 22:14:28.975821 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5489 22:14:28.975903
5490 22:14:28.979424 [CATrainingPosCal] consider 1 rank data
5491 22:14:28.982745 u2DelayCellTimex100 = 270/100 ps
5492 22:14:28.989075 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5493 22:14:28.992078 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5494 22:14:28.995313 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5495 22:14:28.998963 CA3 delay=34 (3~65),Diff = 1 PI (6 cell)
5496 22:14:29.002158 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5497 22:14:29.005237 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5498 22:14:29.005319
5499 22:14:29.009006 CA PerBit enable=1, Macro0, CA PI delay=33
5500 22:14:29.009088
5501 22:14:29.012190 [CBTSetCACLKResult] CA Dly = 33
5502 22:14:29.015405 CS Dly: 5 (0~36)
5503 22:14:29.015489 ==
5504 22:14:29.018592 Dram Type= 6, Freq= 0, CH_1, rank 1
5505 22:14:29.021923 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5506 22:14:29.022006 ==
5507 22:14:29.028720 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5508 22:14:29.032220 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5509 22:14:29.036023 [CA 0] Center 36 (6~67) winsize 62
5510 22:14:29.039553 [CA 1] Center 36 (6~67) winsize 62
5511 22:14:29.042857 [CA 2] Center 34 (4~65) winsize 62
5512 22:14:29.046297 [CA 3] Center 33 (3~64) winsize 62
5513 22:14:29.049764 [CA 4] Center 33 (3~64) winsize 62
5514 22:14:29.052584 [CA 5] Center 33 (3~64) winsize 62
5515 22:14:29.052666
5516 22:14:29.055912 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5517 22:14:29.056025
5518 22:14:29.059531 [CATrainingPosCal] consider 2 rank data
5519 22:14:29.062350 u2DelayCellTimex100 = 270/100 ps
5520 22:14:29.065976 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5521 22:14:29.072193 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5522 22:14:29.075613 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5523 22:14:29.078719 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5524 22:14:29.082004 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5525 22:14:29.085339 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5526 22:14:29.085421
5527 22:14:29.088625 CA PerBit enable=1, Macro0, CA PI delay=33
5528 22:14:29.088706
5529 22:14:29.091943 [CBTSetCACLKResult] CA Dly = 33
5530 22:14:29.095089 CS Dly: 6 (0~38)
5531 22:14:29.095205
5532 22:14:29.098349 ----->DramcWriteLeveling(PI) begin...
5533 22:14:29.098433 ==
5534 22:14:29.101699 Dram Type= 6, Freq= 0, CH_1, rank 0
5535 22:14:29.105325 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5536 22:14:29.105408 ==
5537 22:14:29.108607 Write leveling (Byte 0): 25 => 25
5538 22:14:29.111867 Write leveling (Byte 1): 27 => 27
5539 22:14:29.115032 DramcWriteLeveling(PI) end<-----
5540 22:14:29.115113
5541 22:14:29.115178 ==
5542 22:14:29.118474 Dram Type= 6, Freq= 0, CH_1, rank 0
5543 22:14:29.121676 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5544 22:14:29.121763 ==
5545 22:14:29.125036 [Gating] SW mode calibration
5546 22:14:29.131494 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5547 22:14:29.138120 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5548 22:14:29.141587 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5549 22:14:29.147830 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5550 22:14:29.151494 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5551 22:14:29.154236 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5552 22:14:29.160746 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5553 22:14:29.164124 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5554 22:14:29.167356 0 14 24 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
5555 22:14:29.174425 0 14 28 | B1->B0 | 2929 2727 | 0 0 | (1 0) (1 0)
5556 22:14:29.177606 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
5557 22:14:29.181187 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5558 22:14:29.187061 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5559 22:14:29.190809 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5560 22:14:29.193959 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5561 22:14:29.200435 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5562 22:14:29.203720 0 15 24 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
5563 22:14:29.206952 0 15 28 | B1->B0 | 3838 3d3d | 0 1 | (1 1) (0 0)
5564 22:14:29.213577 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5565 22:14:29.216992 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5566 22:14:29.220172 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5567 22:14:29.226975 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5568 22:14:29.230148 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5569 22:14:29.233611 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5570 22:14:29.240210 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5571 22:14:29.243313 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5572 22:14:29.246896 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5573 22:14:29.252964 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5574 22:14:29.256829 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5575 22:14:29.259557 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5576 22:14:29.266158 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5577 22:14:29.269563 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5578 22:14:29.272926 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5579 22:14:29.279537 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5580 22:14:29.282735 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5581 22:14:29.286556 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5582 22:14:29.292424 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5583 22:14:29.296178 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5584 22:14:29.299005 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5585 22:14:29.305763 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5586 22:14:29.308824 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5587 22:14:29.312658 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5588 22:14:29.319183 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5589 22:14:29.319267 Total UI for P1: 0, mck2ui 16
5590 22:14:29.325512 best dqsien dly found for B0: ( 1, 2, 26)
5591 22:14:29.325619 Total UI for P1: 0, mck2ui 16
5592 22:14:29.331755 best dqsien dly found for B1: ( 1, 2, 26)
5593 22:14:29.335173 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5594 22:14:29.338687 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5595 22:14:29.338770
5596 22:14:29.341760 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5597 22:14:29.345190 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5598 22:14:29.348935 [Gating] SW calibration Done
5599 22:14:29.349011 ==
5600 22:14:29.351775 Dram Type= 6, Freq= 0, CH_1, rank 0
5601 22:14:29.355113 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5602 22:14:29.355188 ==
5603 22:14:29.358289 RX Vref Scan: 0
5604 22:14:29.358390
5605 22:14:29.358481 RX Vref 0 -> 0, step: 1
5606 22:14:29.361724
5607 22:14:29.361794 RX Delay -80 -> 252, step: 8
5608 22:14:29.368432 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5609 22:14:29.371920 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5610 22:14:29.374649 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5611 22:14:29.378072 iDelay=208, Bit 3, Center 99 (0 ~ 199) 200
5612 22:14:29.381670 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5613 22:14:29.384671 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5614 22:14:29.391559 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5615 22:14:29.394654 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5616 22:14:29.398178 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5617 22:14:29.401219 iDelay=208, Bit 9, Center 87 (-8 ~ 183) 192
5618 22:14:29.404449 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5619 22:14:29.407911 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5620 22:14:29.414497 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5621 22:14:29.417695 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5622 22:14:29.420960 iDelay=208, Bit 14, Center 103 (8 ~ 199) 192
5623 22:14:29.424213 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5624 22:14:29.424308 ==
5625 22:14:29.427325 Dram Type= 6, Freq= 0, CH_1, rank 0
5626 22:14:29.434432 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5627 22:14:29.434533 ==
5628 22:14:29.434634 DQS Delay:
5629 22:14:29.437610 DQS0 = 0, DQS1 = 0
5630 22:14:29.437707 DQM Delay:
5631 22:14:29.437796 DQM0 = 100, DQM1 = 96
5632 22:14:29.440681 DQ Delay:
5633 22:14:29.444279 DQ0 =103, DQ1 =95, DQ2 =91, DQ3 =99
5634 22:14:29.447812 DQ4 =95, DQ5 =111, DQ6 =111, DQ7 =95
5635 22:14:29.450711 DQ8 =83, DQ9 =87, DQ10 =95, DQ11 =91
5636 22:14:29.454100 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =103
5637 22:14:29.454199
5638 22:14:29.454300
5639 22:14:29.454397 ==
5640 22:14:29.457055 Dram Type= 6, Freq= 0, CH_1, rank 0
5641 22:14:29.461196 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5642 22:14:29.461270 ==
5643 22:14:29.461332
5644 22:14:29.461390
5645 22:14:29.463818 TX Vref Scan disable
5646 22:14:29.467235 == TX Byte 0 ==
5647 22:14:29.470413 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5648 22:14:29.473713 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5649 22:14:29.476831 == TX Byte 1 ==
5650 22:14:29.480139 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5651 22:14:29.483369 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5652 22:14:29.483449 ==
5653 22:14:29.486823 Dram Type= 6, Freq= 0, CH_1, rank 0
5654 22:14:29.493450 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5655 22:14:29.493532 ==
5656 22:14:29.493596
5657 22:14:29.493655
5658 22:14:29.493741 TX Vref Scan disable
5659 22:14:29.497969 == TX Byte 0 ==
5660 22:14:29.501038 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5661 22:14:29.507538 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5662 22:14:29.507644 == TX Byte 1 ==
5663 22:14:29.510463 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5664 22:14:29.517418 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5665 22:14:29.517501
5666 22:14:29.517566 [DATLAT]
5667 22:14:29.517627 Freq=933, CH1 RK0
5668 22:14:29.517686
5669 22:14:29.520443 DATLAT Default: 0xd
5670 22:14:29.520525 0, 0xFFFF, sum = 0
5671 22:14:29.523733 1, 0xFFFF, sum = 0
5672 22:14:29.527592 2, 0xFFFF, sum = 0
5673 22:14:29.527685 3, 0xFFFF, sum = 0
5674 22:14:29.530585 4, 0xFFFF, sum = 0
5675 22:14:29.530669 5, 0xFFFF, sum = 0
5676 22:14:29.534013 6, 0xFFFF, sum = 0
5677 22:14:29.534103 7, 0xFFFF, sum = 0
5678 22:14:29.537161 8, 0xFFFF, sum = 0
5679 22:14:29.537244 9, 0xFFFF, sum = 0
5680 22:14:29.540284 10, 0x0, sum = 1
5681 22:14:29.540367 11, 0x0, sum = 2
5682 22:14:29.543671 12, 0x0, sum = 3
5683 22:14:29.543754 13, 0x0, sum = 4
5684 22:14:29.547320 best_step = 11
5685 22:14:29.547401
5686 22:14:29.547467 ==
5687 22:14:29.550396 Dram Type= 6, Freq= 0, CH_1, rank 0
5688 22:14:29.553790 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5689 22:14:29.553881 ==
5690 22:14:29.553947 RX Vref Scan: 1
5691 22:14:29.554009
5692 22:14:29.556873 RX Vref 0 -> 0, step: 1
5693 22:14:29.556954
5694 22:14:29.560218 RX Delay -53 -> 252, step: 4
5695 22:14:29.560300
5696 22:14:29.563946 Set Vref, RX VrefLevel [Byte0]: 50
5697 22:14:29.566898 [Byte1]: 50
5698 22:14:29.569927
5699 22:14:29.570009 Final RX Vref Byte 0 = 50 to rank0
5700 22:14:29.573549 Final RX Vref Byte 1 = 50 to rank0
5701 22:14:29.576601 Final RX Vref Byte 0 = 50 to rank1
5702 22:14:29.579905 Final RX Vref Byte 1 = 50 to rank1==
5703 22:14:29.583110 Dram Type= 6, Freq= 0, CH_1, rank 0
5704 22:14:29.589873 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5705 22:14:29.589956 ==
5706 22:14:29.590021 DQS Delay:
5707 22:14:29.593269 DQS0 = 0, DQS1 = 0
5708 22:14:29.593350 DQM Delay:
5709 22:14:29.593416 DQM0 = 98, DQM1 = 94
5710 22:14:29.596183 DQ Delay:
5711 22:14:29.600103 DQ0 =102, DQ1 =92, DQ2 =88, DQ3 =100
5712 22:14:29.603085 DQ4 =96, DQ5 =108, DQ6 =108, DQ7 =92
5713 22:14:29.606439 DQ8 =80, DQ9 =84, DQ10 =94, DQ11 =88
5714 22:14:29.609671 DQ12 =102, DQ13 =102, DQ14 =100, DQ15 =102
5715 22:14:29.609767
5716 22:14:29.609832
5717 22:14:29.616118 [DQSOSCAuto] RK0, (LSB)MR18= 0xa1a, (MSB)MR19= 0x505, tDQSOscB0 = 413 ps tDQSOscB1 = 418 ps
5718 22:14:29.619623 CH1 RK0: MR19=505, MR18=A1A
5719 22:14:29.625989 CH1_RK0: MR19=0x505, MR18=0xA1A, DQSOSC=413, MR23=63, INC=63, DEC=42
5720 22:14:29.626071
5721 22:14:29.629551 ----->DramcWriteLeveling(PI) begin...
5722 22:14:29.629636 ==
5723 22:14:29.632805 Dram Type= 6, Freq= 0, CH_1, rank 1
5724 22:14:29.635995 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5725 22:14:29.636099 ==
5726 22:14:29.639170 Write leveling (Byte 0): 27 => 27
5727 22:14:29.642710 Write leveling (Byte 1): 29 => 29
5728 22:14:29.646015 DramcWriteLeveling(PI) end<-----
5729 22:14:29.646098
5730 22:14:29.646163 ==
5731 22:14:29.649012 Dram Type= 6, Freq= 0, CH_1, rank 1
5732 22:14:29.655676 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5733 22:14:29.655758 ==
5734 22:14:29.655860 [Gating] SW mode calibration
5735 22:14:29.666116 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5736 22:14:29.669711 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5737 22:14:29.675536 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5738 22:14:29.678869 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5739 22:14:29.682111 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5740 22:14:29.688723 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5741 22:14:29.692201 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5742 22:14:29.695143 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5743 22:14:29.701786 0 14 24 | B1->B0 | 3333 2d2d | 1 1 | (1 0) (1 0)
5744 22:14:29.705042 0 14 28 | B1->B0 | 2c2c 2323 | 0 0 | (0 1) (0 0)
5745 22:14:29.708765 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5746 22:14:29.715481 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5747 22:14:29.718499 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5748 22:14:29.721878 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5749 22:14:29.724901 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5750 22:14:29.731616 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5751 22:14:29.734832 0 15 24 | B1->B0 | 2424 3231 | 1 1 | (0 0) (0 0)
5752 22:14:29.738223 0 15 28 | B1->B0 | 3e3e 4646 | 0 0 | (1 1) (0 0)
5753 22:14:29.744767 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5754 22:14:29.747902 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5755 22:14:29.751303 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5756 22:14:29.758176 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5757 22:14:29.761407 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5758 22:14:29.764950 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5759 22:14:29.771275 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5760 22:14:29.774287 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5761 22:14:29.777704 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5762 22:14:29.784511 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5763 22:14:29.787744 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5764 22:14:29.791114 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5765 22:14:29.797854 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5766 22:14:29.800837 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5767 22:14:29.803900 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5768 22:14:29.810483 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5769 22:14:29.814281 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5770 22:14:29.817619 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5771 22:14:29.824193 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5772 22:14:29.827117 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5773 22:14:29.830724 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5774 22:14:29.837168 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5775 22:14:29.840309 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5776 22:14:29.847009 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5777 22:14:29.847083 Total UI for P1: 0, mck2ui 16
5778 22:14:29.850310 best dqsien dly found for B0: ( 1, 2, 26)
5779 22:14:29.856598 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5780 22:14:29.859971 Total UI for P1: 0, mck2ui 16
5781 22:14:29.863079 best dqsien dly found for B1: ( 1, 2, 28)
5782 22:14:29.866731 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5783 22:14:29.870216 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5784 22:14:29.870286
5785 22:14:29.873331 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5786 22:14:29.876360 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5787 22:14:29.879740 [Gating] SW calibration Done
5788 22:14:29.879835 ==
5789 22:14:29.882856 Dram Type= 6, Freq= 0, CH_1, rank 1
5790 22:14:29.886660 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5791 22:14:29.886741 ==
5792 22:14:29.889654 RX Vref Scan: 0
5793 22:14:29.889731
5794 22:14:29.892823 RX Vref 0 -> 0, step: 1
5795 22:14:29.892973
5796 22:14:29.893064 RX Delay -80 -> 252, step: 8
5797 22:14:29.900125 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5798 22:14:29.903412 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5799 22:14:29.906227 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5800 22:14:29.909735 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5801 22:14:29.913087 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5802 22:14:29.919892 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5803 22:14:29.922546 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5804 22:14:29.926397 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5805 22:14:29.929653 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5806 22:14:29.932412 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5807 22:14:29.935971 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5808 22:14:29.942608 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5809 22:14:29.945745 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5810 22:14:29.949160 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5811 22:14:29.952414 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5812 22:14:29.955878 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5813 22:14:29.958730 ==
5814 22:14:29.961975 Dram Type= 6, Freq= 0, CH_1, rank 1
5815 22:14:29.965666 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5816 22:14:29.965740 ==
5817 22:14:29.965802 DQS Delay:
5818 22:14:29.968879 DQS0 = 0, DQS1 = 0
5819 22:14:29.968950 DQM Delay:
5820 22:14:29.972535 DQM0 = 97, DQM1 = 94
5821 22:14:29.972619 DQ Delay:
5822 22:14:29.975332 DQ0 =103, DQ1 =91, DQ2 =87, DQ3 =95
5823 22:14:29.978862 DQ4 =95, DQ5 =107, DQ6 =103, DQ7 =95
5824 22:14:29.982372 DQ8 =79, DQ9 =83, DQ10 =95, DQ11 =87
5825 22:14:29.985167 DQ12 =103, DQ13 =103, DQ14 =99, DQ15 =103
5826 22:14:29.985239
5827 22:14:29.985301
5828 22:14:29.985359 ==
5829 22:14:29.988475 Dram Type= 6, Freq= 0, CH_1, rank 1
5830 22:14:29.992803 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5831 22:14:29.992915 ==
5832 22:14:29.995175
5833 22:14:29.995245
5834 22:14:29.995305 TX Vref Scan disable
5835 22:14:29.998641 == TX Byte 0 ==
5836 22:14:30.001758 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5837 22:14:30.004995 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5838 22:14:30.008585 == TX Byte 1 ==
5839 22:14:30.011834 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5840 22:14:30.015086 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5841 22:14:30.015163 ==
5842 22:14:30.018445 Dram Type= 6, Freq= 0, CH_1, rank 1
5843 22:14:30.025171 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5844 22:14:30.025248 ==
5845 22:14:30.025310
5846 22:14:30.025369
5847 22:14:30.025427 TX Vref Scan disable
5848 22:14:30.029160 == TX Byte 0 ==
5849 22:14:30.032544 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5850 22:14:30.039195 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5851 22:14:30.039295 == TX Byte 1 ==
5852 22:14:30.042474 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5853 22:14:30.049374 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5854 22:14:30.049447
5855 22:14:30.049510 [DATLAT]
5856 22:14:30.049570 Freq=933, CH1 RK1
5857 22:14:30.049627
5858 22:14:30.052287 DATLAT Default: 0xb
5859 22:14:30.055515 0, 0xFFFF, sum = 0
5860 22:14:30.055585 1, 0xFFFF, sum = 0
5861 22:14:30.058901 2, 0xFFFF, sum = 0
5862 22:14:30.058972 3, 0xFFFF, sum = 0
5863 22:14:30.062024 4, 0xFFFF, sum = 0
5864 22:14:30.062094 5, 0xFFFF, sum = 0
5865 22:14:30.065269 6, 0xFFFF, sum = 0
5866 22:14:30.065341 7, 0xFFFF, sum = 0
5867 22:14:30.068979 8, 0xFFFF, sum = 0
5868 22:14:30.069047 9, 0xFFFF, sum = 0
5869 22:14:30.072163 10, 0x0, sum = 1
5870 22:14:30.072233 11, 0x0, sum = 2
5871 22:14:30.075210 12, 0x0, sum = 3
5872 22:14:30.075307 13, 0x0, sum = 4
5873 22:14:30.078615 best_step = 11
5874 22:14:30.078688
5875 22:14:30.078750 ==
5876 22:14:30.081878 Dram Type= 6, Freq= 0, CH_1, rank 1
5877 22:14:30.085137 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5878 22:14:30.085208 ==
5879 22:14:30.088406 RX Vref Scan: 0
5880 22:14:30.088476
5881 22:14:30.088548 RX Vref 0 -> 0, step: 1
5882 22:14:30.088622
5883 22:14:30.091455 RX Delay -61 -> 252, step: 4
5884 22:14:30.098500 iDelay=199, Bit 0, Center 102 (11 ~ 194) 184
5885 22:14:30.101778 iDelay=199, Bit 1, Center 94 (-1 ~ 190) 192
5886 22:14:30.104859 iDelay=199, Bit 2, Center 86 (-5 ~ 178) 184
5887 22:14:30.108126 iDelay=199, Bit 3, Center 96 (3 ~ 190) 188
5888 22:14:30.111458 iDelay=199, Bit 4, Center 96 (3 ~ 190) 188
5889 22:14:30.117790 iDelay=199, Bit 5, Center 106 (15 ~ 198) 184
5890 22:14:30.121199 iDelay=199, Bit 6, Center 104 (15 ~ 194) 180
5891 22:14:30.124424 iDelay=199, Bit 7, Center 92 (-1 ~ 186) 188
5892 22:14:30.127804 iDelay=199, Bit 8, Center 80 (-9 ~ 170) 180
5893 22:14:30.131259 iDelay=199, Bit 9, Center 82 (-9 ~ 174) 184
5894 22:14:30.137647 iDelay=199, Bit 10, Center 90 (-1 ~ 182) 184
5895 22:14:30.140853 iDelay=199, Bit 11, Center 84 (-9 ~ 178) 188
5896 22:14:30.144408 iDelay=199, Bit 12, Center 100 (11 ~ 190) 180
5897 22:14:30.147748 iDelay=199, Bit 13, Center 100 (11 ~ 190) 180
5898 22:14:30.151054 iDelay=199, Bit 14, Center 98 (11 ~ 186) 176
5899 22:14:30.157250 iDelay=199, Bit 15, Center 102 (11 ~ 194) 184
5900 22:14:30.157326 ==
5901 22:14:30.160835 Dram Type= 6, Freq= 0, CH_1, rank 1
5902 22:14:30.164153 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5903 22:14:30.164222 ==
5904 22:14:30.164287 DQS Delay:
5905 22:14:30.167339 DQS0 = 0, DQS1 = 0
5906 22:14:30.167415 DQM Delay:
5907 22:14:30.170519 DQM0 = 97, DQM1 = 92
5908 22:14:30.170585 DQ Delay:
5909 22:14:30.173642 DQ0 =102, DQ1 =94, DQ2 =86, DQ3 =96
5910 22:14:30.176840 DQ4 =96, DQ5 =106, DQ6 =104, DQ7 =92
5911 22:14:30.180428 DQ8 =80, DQ9 =82, DQ10 =90, DQ11 =84
5912 22:14:30.183560 DQ12 =100, DQ13 =100, DQ14 =98, DQ15 =102
5913 22:14:30.183629
5914 22:14:30.183689
5915 22:14:30.193242 [DQSOSCAuto] RK1, (LSB)MR18= 0xe24, (MSB)MR19= 0x505, tDQSOscB0 = 410 ps tDQSOscB1 = 417 ps
5916 22:14:30.196734 CH1 RK1: MR19=505, MR18=E24
5917 22:14:30.200028 CH1_RK1: MR19=0x505, MR18=0xE24, DQSOSC=410, MR23=63, INC=64, DEC=42
5918 22:14:30.203666 [RxdqsGatingPostProcess] freq 933
5919 22:14:30.209733 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5920 22:14:30.213290 best DQS0 dly(2T, 0.5T) = (0, 10)
5921 22:14:30.216575 best DQS1 dly(2T, 0.5T) = (0, 10)
5922 22:14:30.219874 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5923 22:14:30.223661 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5924 22:14:30.226296 best DQS0 dly(2T, 0.5T) = (0, 10)
5925 22:14:30.229848 best DQS1 dly(2T, 0.5T) = (0, 10)
5926 22:14:30.233495 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5927 22:14:30.236127 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5928 22:14:30.236226 Pre-setting of DQS Precalculation
5929 22:14:30.242769 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5930 22:14:30.249456 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5931 22:14:30.256394 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5932 22:14:30.256474
5933 22:14:30.256542
5934 22:14:30.259699 [Calibration Summary] 1866 Mbps
5935 22:14:30.262773 CH 0, Rank 0
5936 22:14:30.262847 SW Impedance : PASS
5937 22:14:30.265960 DUTY Scan : NO K
5938 22:14:30.269205 ZQ Calibration : PASS
5939 22:14:30.269280 Jitter Meter : NO K
5940 22:14:30.272526 CBT Training : PASS
5941 22:14:30.276188 Write leveling : PASS
5942 22:14:30.276262 RX DQS gating : PASS
5943 22:14:30.279297 RX DQ/DQS(RDDQC) : PASS
5944 22:14:30.282344 TX DQ/DQS : PASS
5945 22:14:30.282420 RX DATLAT : PASS
5946 22:14:30.286142 RX DQ/DQS(Engine): PASS
5947 22:14:30.289429 TX OE : NO K
5948 22:14:30.289505 All Pass.
5949 22:14:30.289568
5950 22:14:30.289627 CH 0, Rank 1
5951 22:14:30.292425 SW Impedance : PASS
5952 22:14:30.295681 DUTY Scan : NO K
5953 22:14:30.295767 ZQ Calibration : PASS
5954 22:14:30.298861 Jitter Meter : NO K
5955 22:14:30.302690 CBT Training : PASS
5956 22:14:30.302763 Write leveling : PASS
5957 22:14:30.305224 RX DQS gating : PASS
5958 22:14:30.305297 RX DQ/DQS(RDDQC) : PASS
5959 22:14:30.308812 TX DQ/DQS : PASS
5960 22:14:30.312304 RX DATLAT : PASS
5961 22:14:30.312379 RX DQ/DQS(Engine): PASS
5962 22:14:30.315205 TX OE : NO K
5963 22:14:30.315305 All Pass.
5964 22:14:30.315398
5965 22:14:30.318638 CH 1, Rank 0
5966 22:14:30.318714 SW Impedance : PASS
5967 22:14:30.321905 DUTY Scan : NO K
5968 22:14:30.325362 ZQ Calibration : PASS
5969 22:14:30.325463 Jitter Meter : NO K
5970 22:14:30.328657 CBT Training : PASS
5971 22:14:30.331753 Write leveling : PASS
5972 22:14:30.331866 RX DQS gating : PASS
5973 22:14:30.334892 RX DQ/DQS(RDDQC) : PASS
5974 22:14:30.338178 TX DQ/DQS : PASS
5975 22:14:30.338257 RX DATLAT : PASS
5976 22:14:30.341805 RX DQ/DQS(Engine): PASS
5977 22:14:30.345249 TX OE : NO K
5978 22:14:30.345320 All Pass.
5979 22:14:30.345381
5980 22:14:30.345438 CH 1, Rank 1
5981 22:14:30.348237 SW Impedance : PASS
5982 22:14:30.351267 DUTY Scan : NO K
5983 22:14:30.351334 ZQ Calibration : PASS
5984 22:14:30.354831 Jitter Meter : NO K
5985 22:14:30.357993 CBT Training : PASS
5986 22:14:30.358060 Write leveling : PASS
5987 22:14:30.361233 RX DQS gating : PASS
5988 22:14:30.364610 RX DQ/DQS(RDDQC) : PASS
5989 22:14:30.364680 TX DQ/DQS : PASS
5990 22:14:30.368357 RX DATLAT : PASS
5991 22:14:30.371717 RX DQ/DQS(Engine): PASS
5992 22:14:30.371785 TX OE : NO K
5993 22:14:30.374857 All Pass.
5994 22:14:30.374928
5995 22:14:30.374987 DramC Write-DBI off
5996 22:14:30.377992 PER_BANK_REFRESH: Hybrid Mode
5997 22:14:30.378058 TX_TRACKING: ON
5998 22:14:30.387794 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
5999 22:14:30.391225 [FAST_K] Save calibration result to emmc
6000 22:14:30.394044 dramc_set_vcore_voltage set vcore to 650000
6001 22:14:30.397662 Read voltage for 400, 6
6002 22:14:30.397733 Vio18 = 0
6003 22:14:30.400994 Vcore = 650000
6004 22:14:30.401063 Vdram = 0
6005 22:14:30.401123 Vddq = 0
6006 22:14:30.403963 Vmddr = 0
6007 22:14:30.407324 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6008 22:14:30.414182 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6009 22:14:30.414264 MEM_TYPE=3, freq_sel=20
6010 22:14:30.417490 sv_algorithm_assistance_LP4_800
6011 22:14:30.423838 ============ PULL DRAM RESETB DOWN ============
6012 22:14:30.426956 ========== PULL DRAM RESETB DOWN end =========
6013 22:14:30.430638 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6014 22:14:30.433845 ===================================
6015 22:14:30.436967 LPDDR4 DRAM CONFIGURATION
6016 22:14:30.440456 ===================================
6017 22:14:30.443433 EX_ROW_EN[0] = 0x0
6018 22:14:30.443507 EX_ROW_EN[1] = 0x0
6019 22:14:30.446746 LP4Y_EN = 0x0
6020 22:14:30.446817 WORK_FSP = 0x0
6021 22:14:30.450188 WL = 0x2
6022 22:14:30.450296 RL = 0x2
6023 22:14:30.453419 BL = 0x2
6024 22:14:30.453519 RPST = 0x0
6025 22:14:30.456400 RD_PRE = 0x0
6026 22:14:30.456482 WR_PRE = 0x1
6027 22:14:30.460496 WR_PST = 0x0
6028 22:14:30.460577 DBI_WR = 0x0
6029 22:14:30.463184 DBI_RD = 0x0
6030 22:14:30.463265 OTF = 0x1
6031 22:14:30.466478 ===================================
6032 22:14:30.470131 ===================================
6033 22:14:30.473401 ANA top config
6034 22:14:30.476723 ===================================
6035 22:14:30.479588 DLL_ASYNC_EN = 0
6036 22:14:30.479704 ALL_SLAVE_EN = 1
6037 22:14:30.482801 NEW_RANK_MODE = 1
6038 22:14:30.486607 DLL_IDLE_MODE = 1
6039 22:14:30.489836 LP45_APHY_COMB_EN = 1
6040 22:14:30.493152 TX_ODT_DIS = 1
6041 22:14:30.493234 NEW_8X_MODE = 1
6042 22:14:30.496288 ===================================
6043 22:14:30.499544 ===================================
6044 22:14:30.502687 data_rate = 800
6045 22:14:30.505861 CKR = 1
6046 22:14:30.509347 DQ_P2S_RATIO = 4
6047 22:14:30.512519 ===================================
6048 22:14:30.516015 CA_P2S_RATIO = 4
6049 22:14:30.518918 DQ_CA_OPEN = 0
6050 22:14:30.518999 DQ_SEMI_OPEN = 1
6051 22:14:30.522607 CA_SEMI_OPEN = 1
6052 22:14:30.525978 CA_FULL_RATE = 0
6053 22:14:30.529027 DQ_CKDIV4_EN = 0
6054 22:14:30.532498 CA_CKDIV4_EN = 1
6055 22:14:30.535402 CA_PREDIV_EN = 0
6056 22:14:30.538860 PH8_DLY = 0
6057 22:14:30.538957 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6058 22:14:30.542158 DQ_AAMCK_DIV = 0
6059 22:14:30.545450 CA_AAMCK_DIV = 0
6060 22:14:30.549012 CA_ADMCK_DIV = 4
6061 22:14:30.552381 DQ_TRACK_CA_EN = 0
6062 22:14:30.555239 CA_PICK = 800
6063 22:14:30.555320 CA_MCKIO = 400
6064 22:14:30.558745 MCKIO_SEMI = 400
6065 22:14:30.561726 PLL_FREQ = 3016
6066 22:14:30.565415 DQ_UI_PI_RATIO = 32
6067 22:14:30.568467 CA_UI_PI_RATIO = 32
6068 22:14:30.572079 ===================================
6069 22:14:30.574833 ===================================
6070 22:14:30.578406 memory_type:LPDDR4
6071 22:14:30.578487 GP_NUM : 10
6072 22:14:30.581744 SRAM_EN : 1
6073 22:14:30.584977 MD32_EN : 0
6074 22:14:30.588360 ===================================
6075 22:14:30.588442 [ANA_INIT] >>>>>>>>>>>>>>
6076 22:14:30.591514 <<<<<< [CONFIGURE PHASE]: ANA_TX
6077 22:14:30.594642 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6078 22:14:30.598433 ===================================
6079 22:14:30.601654 data_rate = 800,PCW = 0X7400
6080 22:14:30.605541 ===================================
6081 22:14:30.607950 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6082 22:14:30.614479 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6083 22:14:30.624879 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6084 22:14:30.631216 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6085 22:14:30.634762 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6086 22:14:30.637752 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6087 22:14:30.637861 [ANA_INIT] flow start
6088 22:14:30.641254 [ANA_INIT] PLL >>>>>>>>
6089 22:14:30.644443 [ANA_INIT] PLL <<<<<<<<
6090 22:14:30.644520 [ANA_INIT] MIDPI >>>>>>>>
6091 22:14:30.647600 [ANA_INIT] MIDPI <<<<<<<<
6092 22:14:30.651055 [ANA_INIT] DLL >>>>>>>>
6093 22:14:30.651152 [ANA_INIT] flow end
6094 22:14:30.657871 ============ LP4 DIFF to SE enter ============
6095 22:14:30.660727 ============ LP4 DIFF to SE exit ============
6096 22:14:30.664373 [ANA_INIT] <<<<<<<<<<<<<
6097 22:14:30.667129 [Flow] Enable top DCM control >>>>>
6098 22:14:30.670552 [Flow] Enable top DCM control <<<<<
6099 22:14:30.673869 Enable DLL master slave shuffle
6100 22:14:30.677389 ==============================================================
6101 22:14:30.680392 Gating Mode config
6102 22:14:30.683706 ==============================================================
6103 22:14:30.686836 Config description:
6104 22:14:30.697232 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6105 22:14:30.703236 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6106 22:14:30.706499 SELPH_MODE 0: By rank 1: By Phase
6107 22:14:30.713518 ==============================================================
6108 22:14:30.716642 GAT_TRACK_EN = 0
6109 22:14:30.719804 RX_GATING_MODE = 2
6110 22:14:30.723299 RX_GATING_TRACK_MODE = 2
6111 22:14:30.726609 SELPH_MODE = 1
6112 22:14:30.729803 PICG_EARLY_EN = 1
6113 22:14:30.733017 VALID_LAT_VALUE = 1
6114 22:14:30.736359 ==============================================================
6115 22:14:30.739608 Enter into Gating configuration >>>>
6116 22:14:30.742805 Exit from Gating configuration <<<<
6117 22:14:30.746390 Enter into DVFS_PRE_config >>>>>
6118 22:14:30.759482 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6119 22:14:30.759616 Exit from DVFS_PRE_config <<<<<
6120 22:14:30.762643 Enter into PICG configuration >>>>
6121 22:14:30.766408 Exit from PICG configuration <<<<
6122 22:14:30.769724 [RX_INPUT] configuration >>>>>
6123 22:14:30.772491 [RX_INPUT] configuration <<<<<
6124 22:14:30.779372 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6125 22:14:30.782409 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6126 22:14:30.789215 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6127 22:14:30.795395 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6128 22:14:30.802238 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6129 22:14:30.808681 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6130 22:14:30.811922 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6131 22:14:30.815414 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6132 22:14:30.822043 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6133 22:14:30.825109 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6134 22:14:30.828328 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6135 22:14:30.831612 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6136 22:14:30.834911 ===================================
6137 22:14:30.838114 LPDDR4 DRAM CONFIGURATION
6138 22:14:30.841970 ===================================
6139 22:14:30.844589 EX_ROW_EN[0] = 0x0
6140 22:14:30.844663 EX_ROW_EN[1] = 0x0
6141 22:14:30.848132 LP4Y_EN = 0x0
6142 22:14:30.848225 WORK_FSP = 0x0
6143 22:14:30.851313 WL = 0x2
6144 22:14:30.851385 RL = 0x2
6145 22:14:30.854529 BL = 0x2
6146 22:14:30.857855 RPST = 0x0
6147 22:14:30.857956 RD_PRE = 0x0
6148 22:14:30.861256 WR_PRE = 0x1
6149 22:14:30.861353 WR_PST = 0x0
6150 22:14:30.864729 DBI_WR = 0x0
6151 22:14:30.864801 DBI_RD = 0x0
6152 22:14:30.867812 OTF = 0x1
6153 22:14:30.871314 ===================================
6154 22:14:30.874295 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6155 22:14:30.877757 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6156 22:14:30.884110 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6157 22:14:30.887580 ===================================
6158 22:14:30.887662 LPDDR4 DRAM CONFIGURATION
6159 22:14:30.891304 ===================================
6160 22:14:30.893928 EX_ROW_EN[0] = 0x10
6161 22:14:30.893999 EX_ROW_EN[1] = 0x0
6162 22:14:30.897472 LP4Y_EN = 0x0
6163 22:14:30.900621 WORK_FSP = 0x0
6164 22:14:30.900701 WL = 0x2
6165 22:14:30.903831 RL = 0x2
6166 22:14:30.903932 BL = 0x2
6167 22:14:30.907166 RPST = 0x0
6168 22:14:30.907249 RD_PRE = 0x0
6169 22:14:30.910314 WR_PRE = 0x1
6170 22:14:30.910383 WR_PST = 0x0
6171 22:14:30.913630 DBI_WR = 0x0
6172 22:14:30.913701 DBI_RD = 0x0
6173 22:14:30.917482 OTF = 0x1
6174 22:14:30.920174 ===================================
6175 22:14:30.927052 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6176 22:14:30.930117 nWR fixed to 30
6177 22:14:30.933252 [ModeRegInit_LP4] CH0 RK0
6178 22:14:30.933348 [ModeRegInit_LP4] CH0 RK1
6179 22:14:30.936444 [ModeRegInit_LP4] CH1 RK0
6180 22:14:30.939709 [ModeRegInit_LP4] CH1 RK1
6181 22:14:30.939807 match AC timing 19
6182 22:14:30.946371 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6183 22:14:30.949751 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6184 22:14:30.953512 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6185 22:14:30.959953 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6186 22:14:30.963062 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6187 22:14:30.963141 ==
6188 22:14:30.966364 Dram Type= 6, Freq= 0, CH_0, rank 0
6189 22:14:30.969540 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6190 22:14:30.969616 ==
6191 22:14:30.976386 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6192 22:14:30.982765 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6193 22:14:30.985940 [CA 0] Center 36 (8~64) winsize 57
6194 22:14:30.989271 [CA 1] Center 36 (8~64) winsize 57
6195 22:14:30.992767 [CA 2] Center 36 (8~64) winsize 57
6196 22:14:30.995805 [CA 3] Center 36 (8~64) winsize 57
6197 22:14:30.995888 [CA 4] Center 36 (8~64) winsize 57
6198 22:14:30.999181 [CA 5] Center 36 (8~64) winsize 57
6199 22:14:30.999264
6200 22:14:31.005658 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6201 22:14:31.005741
6202 22:14:31.008859 [CATrainingPosCal] consider 1 rank data
6203 22:14:31.012770 u2DelayCellTimex100 = 270/100 ps
6204 22:14:31.015417 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6205 22:14:31.019176 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6206 22:14:31.022345 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6207 22:14:31.025657 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6208 22:14:31.028714 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6209 22:14:31.032447 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6210 22:14:31.032530
6211 22:14:31.035393 CA PerBit enable=1, Macro0, CA PI delay=36
6212 22:14:31.035476
6213 22:14:31.038545 [CBTSetCACLKResult] CA Dly = 36
6214 22:14:31.042221 CS Dly: 1 (0~32)
6215 22:14:31.042303 ==
6216 22:14:31.045450 Dram Type= 6, Freq= 0, CH_0, rank 1
6217 22:14:31.049030 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6218 22:14:31.049113 ==
6219 22:14:31.055280 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6220 22:14:31.061502 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6221 22:14:31.064953 [CA 0] Center 36 (8~64) winsize 57
6222 22:14:31.068216 [CA 1] Center 36 (8~64) winsize 57
6223 22:14:31.071707 [CA 2] Center 36 (8~64) winsize 57
6224 22:14:31.071789 [CA 3] Center 36 (8~64) winsize 57
6225 22:14:31.074911 [CA 4] Center 36 (8~64) winsize 57
6226 22:14:31.078300 [CA 5] Center 36 (8~64) winsize 57
6227 22:14:31.078384
6228 22:14:31.084517 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6229 22:14:31.084616
6230 22:14:31.088099 [CATrainingPosCal] consider 2 rank data
6231 22:14:31.091383 u2DelayCellTimex100 = 270/100 ps
6232 22:14:31.094676 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6233 22:14:31.098389 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6234 22:14:31.101069 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6235 22:14:31.104594 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6236 22:14:31.108001 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6237 22:14:31.111069 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6238 22:14:31.111155
6239 22:14:31.114739 CA PerBit enable=1, Macro0, CA PI delay=36
6240 22:14:31.114811
6241 22:14:31.117354 [CBTSetCACLKResult] CA Dly = 36
6242 22:14:31.120889 CS Dly: 1 (0~32)
6243 22:14:31.120976
6244 22:14:31.124655 ----->DramcWriteLeveling(PI) begin...
6245 22:14:31.124742 ==
6246 22:14:31.127430 Dram Type= 6, Freq= 0, CH_0, rank 0
6247 22:14:31.130512 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6248 22:14:31.130609 ==
6249 22:14:31.134242 Write leveling (Byte 0): 40 => 8
6250 22:14:31.137461 Write leveling (Byte 1): 40 => 8
6251 22:14:31.141134 DramcWriteLeveling(PI) end<-----
6252 22:14:31.141209
6253 22:14:31.141277 ==
6254 22:14:31.143789 Dram Type= 6, Freq= 0, CH_0, rank 0
6255 22:14:31.147367 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6256 22:14:31.147439 ==
6257 22:14:31.150665 [Gating] SW mode calibration
6258 22:14:31.157079 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6259 22:14:31.163651 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6260 22:14:31.167006 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6261 22:14:31.173212 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6262 22:14:31.176634 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6263 22:14:31.180133 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6264 22:14:31.186686 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6265 22:14:31.190013 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6266 22:14:31.193003 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6267 22:14:31.199668 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6268 22:14:31.202996 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6269 22:14:31.206398 Total UI for P1: 0, mck2ui 16
6270 22:14:31.209667 best dqsien dly found for B0: ( 0, 14, 24)
6271 22:14:31.213202 Total UI for P1: 0, mck2ui 16
6272 22:14:31.216417 best dqsien dly found for B1: ( 0, 14, 24)
6273 22:14:31.219657 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6274 22:14:31.222832 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6275 22:14:31.222900
6276 22:14:31.226107 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6277 22:14:31.229451 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6278 22:14:31.232973 [Gating] SW calibration Done
6279 22:14:31.233044 ==
6280 22:14:31.236277 Dram Type= 6, Freq= 0, CH_0, rank 0
6281 22:14:31.242445 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6282 22:14:31.242518 ==
6283 22:14:31.242580 RX Vref Scan: 0
6284 22:14:31.242637
6285 22:14:31.246053 RX Vref 0 -> 0, step: 1
6286 22:14:31.246123
6287 22:14:31.249328 RX Delay -410 -> 252, step: 16
6288 22:14:31.252527 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6289 22:14:31.256107 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6290 22:14:31.262239 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6291 22:14:31.266138 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6292 22:14:31.268896 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6293 22:14:31.272005 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6294 22:14:31.278954 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6295 22:14:31.281859 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6296 22:14:31.285439 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6297 22:14:31.288719 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6298 22:14:31.295426 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6299 22:14:31.298689 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6300 22:14:31.301475 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6301 22:14:31.308267 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6302 22:14:31.311826 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6303 22:14:31.314597 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6304 22:14:31.314694 ==
6305 22:14:31.318123 Dram Type= 6, Freq= 0, CH_0, rank 0
6306 22:14:31.321278 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6307 22:14:31.324940 ==
6308 22:14:31.325007 DQS Delay:
6309 22:14:31.325066 DQS0 = 35, DQS1 = 51
6310 22:14:31.328206 DQM Delay:
6311 22:14:31.328279 DQM0 = 4, DQM1 = 10
6312 22:14:31.331349 DQ Delay:
6313 22:14:31.331418 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6314 22:14:31.334762 DQ4 =0, DQ5 =0, DQ6 =16, DQ7 =16
6315 22:14:31.337813 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6316 22:14:31.341210 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6317 22:14:31.341277
6318 22:14:31.341339
6319 22:14:31.341395 ==
6320 22:14:31.344232 Dram Type= 6, Freq= 0, CH_0, rank 0
6321 22:14:31.350838 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6322 22:14:31.350909 ==
6323 22:14:31.350968
6324 22:14:31.351024
6325 22:14:31.354729 TX Vref Scan disable
6326 22:14:31.354796 == TX Byte 0 ==
6327 22:14:31.357382 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6328 22:14:31.364244 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6329 22:14:31.364313 == TX Byte 1 ==
6330 22:14:31.367569 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6331 22:14:31.373923 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6332 22:14:31.373995 ==
6333 22:14:31.377024 Dram Type= 6, Freq= 0, CH_0, rank 0
6334 22:14:31.380658 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6335 22:14:31.380726 ==
6336 22:14:31.380788
6337 22:14:31.380881
6338 22:14:31.384540 TX Vref Scan disable
6339 22:14:31.384610 == TX Byte 0 ==
6340 22:14:31.387276 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6341 22:14:31.394064 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6342 22:14:31.394136 == TX Byte 1 ==
6343 22:14:31.397153 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6344 22:14:31.403477 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6345 22:14:31.403549
6346 22:14:31.403609 [DATLAT]
6347 22:14:31.403671 Freq=400, CH0 RK0
6348 22:14:31.406863
6349 22:14:31.406956 DATLAT Default: 0xf
6350 22:14:31.410432 0, 0xFFFF, sum = 0
6351 22:14:31.410503 1, 0xFFFF, sum = 0
6352 22:14:31.413646 2, 0xFFFF, sum = 0
6353 22:14:31.413712 3, 0xFFFF, sum = 0
6354 22:14:31.416870 4, 0xFFFF, sum = 0
6355 22:14:31.416939 5, 0xFFFF, sum = 0
6356 22:14:31.420061 6, 0xFFFF, sum = 0
6357 22:14:31.420152 7, 0xFFFF, sum = 0
6358 22:14:31.423330 8, 0xFFFF, sum = 0
6359 22:14:31.423406 9, 0xFFFF, sum = 0
6360 22:14:31.426476 10, 0xFFFF, sum = 0
6361 22:14:31.426543 11, 0xFFFF, sum = 0
6362 22:14:31.429853 12, 0xFFFF, sum = 0
6363 22:14:31.429923 13, 0x0, sum = 1
6364 22:14:31.433038 14, 0x0, sum = 2
6365 22:14:31.433105 15, 0x0, sum = 3
6366 22:14:31.436606 16, 0x0, sum = 4
6367 22:14:31.436701 best_step = 14
6368 22:14:31.436790
6369 22:14:31.436875 ==
6370 22:14:31.439965 Dram Type= 6, Freq= 0, CH_0, rank 0
6371 22:14:31.446246 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6372 22:14:31.446344 ==
6373 22:14:31.446432 RX Vref Scan: 1
6374 22:14:31.446551
6375 22:14:31.449825 RX Vref 0 -> 0, step: 1
6376 22:14:31.449903
6377 22:14:31.453038 RX Delay -343 -> 252, step: 8
6378 22:14:31.453107
6379 22:14:31.456128 Set Vref, RX VrefLevel [Byte0]: 52
6380 22:14:31.459391 [Byte1]: 59
6381 22:14:31.462811
6382 22:14:31.462898 Final RX Vref Byte 0 = 52 to rank0
6383 22:14:31.466001 Final RX Vref Byte 1 = 59 to rank0
6384 22:14:31.469704 Final RX Vref Byte 0 = 52 to rank1
6385 22:14:31.472864 Final RX Vref Byte 1 = 59 to rank1==
6386 22:14:31.476129 Dram Type= 6, Freq= 0, CH_0, rank 0
6387 22:14:31.482550 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6388 22:14:31.482662 ==
6389 22:14:31.482770 DQS Delay:
6390 22:14:31.485659 DQS0 = 40, DQS1 = 60
6391 22:14:31.485729 DQM Delay:
6392 22:14:31.485788 DQM0 = 6, DQM1 = 17
6393 22:14:31.488961 DQ Delay:
6394 22:14:31.492576 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =0
6395 22:14:31.492643 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =12
6396 22:14:31.495953 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =12
6397 22:14:31.499114 DQ12 =24, DQ13 =24, DQ14 =28, DQ15 =24
6398 22:14:31.502552
6399 22:14:31.502621
6400 22:14:31.508878 [DQSOSCAuto] RK0, (LSB)MR18= 0x8e81, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 392 ps
6401 22:14:31.512292 CH0 RK0: MR19=C0C, MR18=8E81
6402 22:14:31.518646 CH0_RK0: MR19=0xC0C, MR18=0x8E81, DQSOSC=392, MR23=63, INC=384, DEC=256
6403 22:14:31.518725 ==
6404 22:14:31.522329 Dram Type= 6, Freq= 0, CH_0, rank 1
6405 22:14:31.525567 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6406 22:14:31.525652 ==
6407 22:14:31.528600 [Gating] SW mode calibration
6408 22:14:31.535110 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6409 22:14:31.541821 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6410 22:14:31.545247 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6411 22:14:31.548559 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6412 22:14:31.555162 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6413 22:14:31.558141 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6414 22:14:31.561580 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6415 22:14:31.567964 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6416 22:14:31.571388 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6417 22:14:31.574627 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6418 22:14:31.581194 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6419 22:14:31.585110 Total UI for P1: 0, mck2ui 16
6420 22:14:31.588090 best dqsien dly found for B0: ( 0, 14, 24)
6421 22:14:31.588161 Total UI for P1: 0, mck2ui 16
6422 22:14:31.594332 best dqsien dly found for B1: ( 0, 14, 24)
6423 22:14:31.597537 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6424 22:14:31.601090 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6425 22:14:31.601164
6426 22:14:31.604250 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6427 22:14:31.607653 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6428 22:14:31.611066 [Gating] SW calibration Done
6429 22:14:31.611182 ==
6430 22:14:31.614492 Dram Type= 6, Freq= 0, CH_0, rank 1
6431 22:14:31.617435 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6432 22:14:31.617513 ==
6433 22:14:31.620788 RX Vref Scan: 0
6434 22:14:31.620865
6435 22:14:31.624225 RX Vref 0 -> 0, step: 1
6436 22:14:31.624297
6437 22:14:31.624358 RX Delay -410 -> 252, step: 16
6438 22:14:31.631317 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6439 22:14:31.634432 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6440 22:14:31.637840 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6441 22:14:31.643824 iDelay=230, Bit 3, Center -27 (-266 ~ 213) 480
6442 22:14:31.647407 iDelay=230, Bit 4, Center -19 (-266 ~ 229) 496
6443 22:14:31.650577 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6444 22:14:31.653820 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6445 22:14:31.660761 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6446 22:14:31.663901 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6447 22:14:31.667205 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6448 22:14:31.670429 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6449 22:14:31.676932 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6450 22:14:31.680237 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6451 22:14:31.683472 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6452 22:14:31.689732 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6453 22:14:31.693036 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6454 22:14:31.693109 ==
6455 22:14:31.696399 Dram Type= 6, Freq= 0, CH_0, rank 1
6456 22:14:31.700015 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6457 22:14:31.700111 ==
6458 22:14:31.702857 DQS Delay:
6459 22:14:31.702930 DQS0 = 35, DQS1 = 51
6460 22:14:31.702998 DQM Delay:
6461 22:14:31.706413 DQM0 = 10, DQM1 = 9
6462 22:14:31.706487 DQ Delay:
6463 22:14:31.709679 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6464 22:14:31.713084 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6465 22:14:31.716413 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6466 22:14:31.719407 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6467 22:14:31.719502
6468 22:14:31.719565
6469 22:14:31.719623 ==
6470 22:14:31.722822 Dram Type= 6, Freq= 0, CH_0, rank 1
6471 22:14:31.726062 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6472 22:14:31.729048 ==
6473 22:14:31.729126
6474 22:14:31.729189
6475 22:14:31.729247 TX Vref Scan disable
6476 22:14:31.732832 == TX Byte 0 ==
6477 22:14:31.736314 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6478 22:14:31.739062 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6479 22:14:31.742483 == TX Byte 1 ==
6480 22:14:31.745535 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6481 22:14:31.749122 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6482 22:14:31.749203 ==
6483 22:14:31.752358 Dram Type= 6, Freq= 0, CH_0, rank 1
6484 22:14:31.759068 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6485 22:14:31.759150 ==
6486 22:14:31.759215
6487 22:14:31.759274
6488 22:14:31.759348 TX Vref Scan disable
6489 22:14:31.762096 == TX Byte 0 ==
6490 22:14:31.765765 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6491 22:14:31.768734 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6492 22:14:31.772395 == TX Byte 1 ==
6493 22:14:31.775812 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6494 22:14:31.778536 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6495 22:14:31.778618
6496 22:14:31.781837 [DATLAT]
6497 22:14:31.781918 Freq=400, CH0 RK1
6498 22:14:31.781982
6499 22:14:31.785019 DATLAT Default: 0xe
6500 22:14:31.785100 0, 0xFFFF, sum = 0
6501 22:14:31.788542 1, 0xFFFF, sum = 0
6502 22:14:31.788624 2, 0xFFFF, sum = 0
6503 22:14:31.791792 3, 0xFFFF, sum = 0
6504 22:14:31.791919 4, 0xFFFF, sum = 0
6505 22:14:31.795091 5, 0xFFFF, sum = 0
6506 22:14:31.795187 6, 0xFFFF, sum = 0
6507 22:14:31.799423 7, 0xFFFF, sum = 0
6508 22:14:31.799505 8, 0xFFFF, sum = 0
6509 22:14:31.802260 9, 0xFFFF, sum = 0
6510 22:14:31.804991 10, 0xFFFF, sum = 0
6511 22:14:31.805074 11, 0xFFFF, sum = 0
6512 22:14:31.808446 12, 0xFFFF, sum = 0
6513 22:14:31.808566 13, 0x0, sum = 1
6514 22:14:31.811753 14, 0x0, sum = 2
6515 22:14:31.811859 15, 0x0, sum = 3
6516 22:14:31.814746 16, 0x0, sum = 4
6517 22:14:31.814824 best_step = 14
6518 22:14:31.814887
6519 22:14:31.814947 ==
6520 22:14:31.817921 Dram Type= 6, Freq= 0, CH_0, rank 1
6521 22:14:31.821367 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6522 22:14:31.821446 ==
6523 22:14:31.824599 RX Vref Scan: 0
6524 22:14:31.824674
6525 22:14:31.828281 RX Vref 0 -> 0, step: 1
6526 22:14:31.828381
6527 22:14:31.828471 RX Delay -343 -> 252, step: 8
6528 22:14:31.836660 iDelay=209, Bit 0, Center -36 (-271 ~ 200) 472
6529 22:14:31.840338 iDelay=209, Bit 1, Center -32 (-271 ~ 208) 480
6530 22:14:31.843487 iDelay=209, Bit 2, Center -40 (-279 ~ 200) 480
6531 22:14:31.849948 iDelay=209, Bit 3, Center -36 (-271 ~ 200) 472
6532 22:14:31.853210 iDelay=209, Bit 4, Center -32 (-271 ~ 208) 480
6533 22:14:31.856602 iDelay=209, Bit 5, Center -44 (-279 ~ 192) 472
6534 22:14:31.859762 iDelay=209, Bit 6, Center -28 (-263 ~ 208) 472
6535 22:14:31.866511 iDelay=209, Bit 7, Center -28 (-263 ~ 208) 472
6536 22:14:31.869436 iDelay=209, Bit 8, Center -52 (-295 ~ 192) 488
6537 22:14:31.872642 iDelay=209, Bit 9, Center -60 (-303 ~ 184) 488
6538 22:14:31.876023 iDelay=209, Bit 10, Center -44 (-287 ~ 200) 488
6539 22:14:31.882656 iDelay=209, Bit 11, Center -52 (-295 ~ 192) 488
6540 22:14:31.886101 iDelay=209, Bit 12, Center -36 (-279 ~ 208) 488
6541 22:14:31.889142 iDelay=209, Bit 13, Center -36 (-279 ~ 208) 488
6542 22:14:31.892892 iDelay=209, Bit 14, Center -36 (-279 ~ 208) 488
6543 22:14:31.899328 iDelay=209, Bit 15, Center -36 (-279 ~ 208) 488
6544 22:14:31.899405 ==
6545 22:14:31.902619 Dram Type= 6, Freq= 0, CH_0, rank 1
6546 22:14:31.905895 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6547 22:14:31.905971 ==
6548 22:14:31.908992 DQS Delay:
6549 22:14:31.909067 DQS0 = 44, DQS1 = 60
6550 22:14:31.909130 DQM Delay:
6551 22:14:31.912154 DQM0 = 9, DQM1 = 16
6552 22:14:31.912229 DQ Delay:
6553 22:14:31.915589 DQ0 =8, DQ1 =12, DQ2 =4, DQ3 =8
6554 22:14:31.918845 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =16
6555 22:14:31.921936 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6556 22:14:31.925648 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6557 22:14:31.925745
6558 22:14:31.925834
6559 22:14:31.935561 [DQSOSCAuto] RK1, (LSB)MR18= 0x857d, (MSB)MR19= 0xc0c, tDQSOscB0 = 394 ps tDQSOscB1 = 393 ps
6560 22:14:31.935666 CH0 RK1: MR19=C0C, MR18=857D
6561 22:14:31.942151 CH0_RK1: MR19=0xC0C, MR18=0x857D, DQSOSC=393, MR23=63, INC=382, DEC=254
6562 22:14:31.945213 [RxdqsGatingPostProcess] freq 400
6563 22:14:31.951544 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6564 22:14:31.954835 best DQS0 dly(2T, 0.5T) = (0, 10)
6565 22:14:31.958454 best DQS1 dly(2T, 0.5T) = (0, 10)
6566 22:14:31.961443 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6567 22:14:31.964934 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6568 22:14:31.968021 best DQS0 dly(2T, 0.5T) = (0, 10)
6569 22:14:31.971601 best DQS1 dly(2T, 0.5T) = (0, 10)
6570 22:14:31.974521 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6571 22:14:31.977732 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6572 22:14:31.980984 Pre-setting of DQS Precalculation
6573 22:14:31.984339 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6574 22:14:31.984409 ==
6575 22:14:31.988328 Dram Type= 6, Freq= 0, CH_1, rank 0
6576 22:14:31.991256 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6577 22:14:31.991352 ==
6578 22:14:31.997745 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6579 22:14:32.004171 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6580 22:14:32.007807 [CA 0] Center 36 (8~64) winsize 57
6581 22:14:32.011111 [CA 1] Center 36 (8~64) winsize 57
6582 22:14:32.014141 [CA 2] Center 36 (8~64) winsize 57
6583 22:14:32.017470 [CA 3] Center 36 (8~64) winsize 57
6584 22:14:32.021236 [CA 4] Center 36 (8~64) winsize 57
6585 22:14:32.024252 [CA 5] Center 36 (8~64) winsize 57
6586 22:14:32.024327
6587 22:14:32.027439 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6588 22:14:32.027511
6589 22:14:32.030319 [CATrainingPosCal] consider 1 rank data
6590 22:14:32.034338 u2DelayCellTimex100 = 270/100 ps
6591 22:14:32.037719 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6592 22:14:32.040226 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6593 22:14:32.044057 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6594 22:14:32.047062 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6595 22:14:32.050284 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6596 22:14:32.053774 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6597 22:14:32.053865
6598 22:14:32.060123 CA PerBit enable=1, Macro0, CA PI delay=36
6599 22:14:32.060200
6600 22:14:32.060264 [CBTSetCACLKResult] CA Dly = 36
6601 22:14:32.063369 CS Dly: 1 (0~32)
6602 22:14:32.063441 ==
6603 22:14:32.066682 Dram Type= 6, Freq= 0, CH_1, rank 1
6604 22:14:32.070455 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6605 22:14:32.070528 ==
6606 22:14:32.076714 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6607 22:14:32.083541 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6608 22:14:32.086857 [CA 0] Center 36 (8~64) winsize 57
6609 22:14:32.090038 [CA 1] Center 36 (8~64) winsize 57
6610 22:14:32.093079 [CA 2] Center 36 (8~64) winsize 57
6611 22:14:32.096518 [CA 3] Center 36 (8~64) winsize 57
6612 22:14:32.099801 [CA 4] Center 36 (8~64) winsize 57
6613 22:14:32.099873 [CA 5] Center 36 (8~64) winsize 57
6614 22:14:32.103135
6615 22:14:32.106170 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6616 22:14:32.106242
6617 22:14:32.109385 [CATrainingPosCal] consider 2 rank data
6618 22:14:32.112836 u2DelayCellTimex100 = 270/100 ps
6619 22:14:32.115957 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6620 22:14:32.119756 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6621 22:14:32.122935 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6622 22:14:32.125822 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6623 22:14:32.129189 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6624 22:14:32.132584 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6625 22:14:32.132661
6626 22:14:32.139173 CA PerBit enable=1, Macro0, CA PI delay=36
6627 22:14:32.139275
6628 22:14:32.139375 [CBTSetCACLKResult] CA Dly = 36
6629 22:14:32.142419 CS Dly: 1 (0~32)
6630 22:14:32.142504
6631 22:14:32.145416 ----->DramcWriteLeveling(PI) begin...
6632 22:14:32.145486 ==
6633 22:14:32.149270 Dram Type= 6, Freq= 0, CH_1, rank 0
6634 22:14:32.152190 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6635 22:14:32.152261 ==
6636 22:14:32.155301 Write leveling (Byte 0): 40 => 8
6637 22:14:32.158936 Write leveling (Byte 1): 40 => 8
6638 22:14:32.162478 DramcWriteLeveling(PI) end<-----
6639 22:14:32.162546
6640 22:14:32.162606 ==
6641 22:14:32.165211 Dram Type= 6, Freq= 0, CH_1, rank 0
6642 22:14:32.168647 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6643 22:14:32.172107 ==
6644 22:14:32.172172 [Gating] SW mode calibration
6645 22:14:32.181993 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6646 22:14:32.185290 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6647 22:14:32.188444 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6648 22:14:32.194568 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6649 22:14:32.197934 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6650 22:14:32.201176 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6651 22:14:32.208204 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6652 22:14:32.211285 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6653 22:14:32.217764 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6654 22:14:32.220930 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6655 22:14:32.224368 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6656 22:14:32.227650 Total UI for P1: 0, mck2ui 16
6657 22:14:32.231039 best dqsien dly found for B0: ( 0, 14, 24)
6658 22:14:32.234399 Total UI for P1: 0, mck2ui 16
6659 22:14:32.237784 best dqsien dly found for B1: ( 0, 14, 24)
6660 22:14:32.241092 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6661 22:14:32.244225 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6662 22:14:32.244296
6663 22:14:32.247805 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6664 22:14:32.254226 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6665 22:14:32.254304 [Gating] SW calibration Done
6666 22:14:32.254368 ==
6667 22:14:32.257641 Dram Type= 6, Freq= 0, CH_1, rank 0
6668 22:14:32.264209 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6669 22:14:32.264288 ==
6670 22:14:32.264351 RX Vref Scan: 0
6671 22:14:32.264410
6672 22:14:32.267454 RX Vref 0 -> 0, step: 1
6673 22:14:32.267524
6674 22:14:32.270809 RX Delay -410 -> 252, step: 16
6675 22:14:32.274036 iDelay=230, Bit 0, Center -19 (-266 ~ 229) 496
6676 22:14:32.277463 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6677 22:14:32.283948 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6678 22:14:32.287357 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6679 22:14:32.290697 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6680 22:14:32.293744 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6681 22:14:32.300276 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6682 22:14:32.303850 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6683 22:14:32.307323 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6684 22:14:32.310278 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6685 22:14:32.317106 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6686 22:14:32.320136 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6687 22:14:32.323204 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6688 22:14:32.330146 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6689 22:14:32.333365 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6690 22:14:32.336959 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6691 22:14:32.337033 ==
6692 22:14:32.339909 Dram Type= 6, Freq= 0, CH_1, rank 0
6693 22:14:32.346347 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6694 22:14:32.346429 ==
6695 22:14:32.346493 DQS Delay:
6696 22:14:32.349487 DQS0 = 35, DQS1 = 51
6697 22:14:32.349562 DQM Delay:
6698 22:14:32.349623 DQM0 = 6, DQM1 = 14
6699 22:14:32.353045 DQ Delay:
6700 22:14:32.356074 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =0
6701 22:14:32.356161 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6702 22:14:32.359160 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6703 22:14:32.362828 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =16
6704 22:14:32.362899
6705 22:14:32.365851
6706 22:14:32.365920 ==
6707 22:14:32.369179 Dram Type= 6, Freq= 0, CH_1, rank 0
6708 22:14:32.372814 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6709 22:14:32.372889 ==
6710 22:14:32.372953
6711 22:14:32.373015
6712 22:14:32.376328 TX Vref Scan disable
6713 22:14:32.376395 == TX Byte 0 ==
6714 22:14:32.379040 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6715 22:14:32.386106 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6716 22:14:32.386197 == TX Byte 1 ==
6717 22:14:32.389087 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6718 22:14:32.396106 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6719 22:14:32.396183 ==
6720 22:14:32.399103 Dram Type= 6, Freq= 0, CH_1, rank 0
6721 22:14:32.402228 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6722 22:14:32.402298 ==
6723 22:14:32.402361
6724 22:14:32.402435
6725 22:14:32.405726 TX Vref Scan disable
6726 22:14:32.405797 == TX Byte 0 ==
6727 22:14:32.409134 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6728 22:14:32.415410 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6729 22:14:32.415485 == TX Byte 1 ==
6730 22:14:32.418664 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6731 22:14:32.425693 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6732 22:14:32.425766
6733 22:14:32.425826 [DATLAT]
6734 22:14:32.429034 Freq=400, CH1 RK0
6735 22:14:32.429105
6736 22:14:32.429162 DATLAT Default: 0xf
6737 22:14:32.432271 0, 0xFFFF, sum = 0
6738 22:14:32.432345 1, 0xFFFF, sum = 0
6739 22:14:32.435216 2, 0xFFFF, sum = 0
6740 22:14:32.435285 3, 0xFFFF, sum = 0
6741 22:14:32.438599 4, 0xFFFF, sum = 0
6742 22:14:32.438669 5, 0xFFFF, sum = 0
6743 22:14:32.441823 6, 0xFFFF, sum = 0
6744 22:14:32.441896 7, 0xFFFF, sum = 0
6745 22:14:32.445816 8, 0xFFFF, sum = 0
6746 22:14:32.445890 9, 0xFFFF, sum = 0
6747 22:14:32.448969 10, 0xFFFF, sum = 0
6748 22:14:32.449048 11, 0xFFFF, sum = 0
6749 22:14:32.452728 12, 0xFFFF, sum = 0
6750 22:14:32.452801 13, 0x0, sum = 1
6751 22:14:32.454974 14, 0x0, sum = 2
6752 22:14:32.455046 15, 0x0, sum = 3
6753 22:14:32.458782 16, 0x0, sum = 4
6754 22:14:32.458850 best_step = 14
6755 22:14:32.458913
6756 22:14:32.458970 ==
6757 22:14:32.461557 Dram Type= 6, Freq= 0, CH_1, rank 0
6758 22:14:32.468447 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6759 22:14:32.468524 ==
6760 22:14:32.468586 RX Vref Scan: 1
6761 22:14:32.468644
6762 22:14:32.471703 RX Vref 0 -> 0, step: 1
6763 22:14:32.471822
6764 22:14:32.475085 RX Delay -343 -> 252, step: 8
6765 22:14:32.475167
6766 22:14:32.478370 Set Vref, RX VrefLevel [Byte0]: 50
6767 22:14:32.481833 [Byte1]: 50
6768 22:14:32.485191
6769 22:14:32.485261 Final RX Vref Byte 0 = 50 to rank0
6770 22:14:32.488167 Final RX Vref Byte 1 = 50 to rank0
6771 22:14:32.491954 Final RX Vref Byte 0 = 50 to rank1
6772 22:14:32.494972 Final RX Vref Byte 1 = 50 to rank1==
6773 22:14:32.498192 Dram Type= 6, Freq= 0, CH_1, rank 0
6774 22:14:32.504587 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6775 22:14:32.504661 ==
6776 22:14:32.504727 DQS Delay:
6777 22:14:32.507816 DQS0 = 44, DQS1 = 52
6778 22:14:32.507880 DQM Delay:
6779 22:14:32.507939 DQM0 = 11, DQM1 = 10
6780 22:14:32.511432 DQ Delay:
6781 22:14:32.514578 DQ0 =20, DQ1 =4, DQ2 =0, DQ3 =12
6782 22:14:32.518057 DQ4 =8, DQ5 =20, DQ6 =24, DQ7 =4
6783 22:14:32.518126 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =4
6784 22:14:32.521580 DQ12 =20, DQ13 =20, DQ14 =16, DQ15 =16
6785 22:14:32.521648
6786 22:14:32.524529
6787 22:14:32.531721 [DQSOSCAuto] RK0, (LSB)MR18= 0x6187, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 397 ps
6788 22:14:32.534412 CH1 RK0: MR19=C0C, MR18=6187
6789 22:14:32.541239 CH1_RK0: MR19=0xC0C, MR18=0x6187, DQSOSC=392, MR23=63, INC=384, DEC=256
6790 22:14:32.541312 ==
6791 22:14:32.544606 Dram Type= 6, Freq= 0, CH_1, rank 1
6792 22:14:32.547628 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6793 22:14:32.547696 ==
6794 22:14:32.551351 [Gating] SW mode calibration
6795 22:14:32.557628 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6796 22:14:32.564251 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6797 22:14:32.567364 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6798 22:14:32.570630 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6799 22:14:32.577601 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6800 22:14:32.580844 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6801 22:14:32.584321 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6802 22:14:32.590596 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6803 22:14:32.594122 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6804 22:14:32.597196 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6805 22:14:32.604123 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6806 22:14:32.604196 Total UI for P1: 0, mck2ui 16
6807 22:14:32.610588 best dqsien dly found for B0: ( 0, 14, 24)
6808 22:14:32.610662 Total UI for P1: 0, mck2ui 16
6809 22:14:32.617309 best dqsien dly found for B1: ( 0, 14, 24)
6810 22:14:32.620781 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6811 22:14:32.623832 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6812 22:14:32.623924
6813 22:14:32.627076 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6814 22:14:32.630122 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6815 22:14:32.633582 [Gating] SW calibration Done
6816 22:14:32.633665 ==
6817 22:14:32.636635 Dram Type= 6, Freq= 0, CH_1, rank 1
6818 22:14:32.640100 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6819 22:14:32.640173 ==
6820 22:14:32.643506 RX Vref Scan: 0
6821 22:14:32.643582
6822 22:14:32.643644 RX Vref 0 -> 0, step: 1
6823 22:14:32.643702
6824 22:14:32.646675 RX Delay -410 -> 252, step: 16
6825 22:14:32.653644 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6826 22:14:32.656628 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6827 22:14:32.660145 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6828 22:14:32.663282 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6829 22:14:32.670271 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6830 22:14:32.672964 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6831 22:14:32.676270 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6832 22:14:32.679601 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6833 22:14:32.686500 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6834 22:14:32.689443 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6835 22:14:32.692906 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6836 22:14:32.699084 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6837 22:14:32.702597 iDelay=230, Bit 12, Center -19 (-266 ~ 229) 496
6838 22:14:32.705685 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6839 22:14:32.709372 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6840 22:14:32.715850 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6841 22:14:32.715954 ==
6842 22:14:32.718677 Dram Type= 6, Freq= 0, CH_1, rank 1
6843 22:14:32.722018 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6844 22:14:32.722099 ==
6845 22:14:32.722163 DQS Delay:
6846 22:14:32.725917 DQS0 = 43, DQS1 = 51
6847 22:14:32.725997 DQM Delay:
6848 22:14:32.728610 DQM0 = 9, DQM1 = 15
6849 22:14:32.728691 DQ Delay:
6850 22:14:32.732353 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6851 22:14:32.735327 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =8
6852 22:14:32.738496 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6853 22:14:32.742091 DQ12 =32, DQ13 =24, DQ14 =16, DQ15 =24
6854 22:14:32.742199
6855 22:14:32.742283
6856 22:14:32.742344 ==
6857 22:14:32.745557 Dram Type= 6, Freq= 0, CH_1, rank 1
6858 22:14:32.748676 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6859 22:14:32.748757 ==
6860 22:14:32.748857
6861 22:14:32.751876
6862 22:14:32.751956 TX Vref Scan disable
6863 22:14:32.755700 == TX Byte 0 ==
6864 22:14:32.758304 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6865 22:14:32.761756 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6866 22:14:32.764955 == TX Byte 1 ==
6867 22:14:32.768622 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6868 22:14:32.771848 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6869 22:14:32.771942 ==
6870 22:14:32.774729 Dram Type= 6, Freq= 0, CH_1, rank 1
6871 22:14:32.778140 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6872 22:14:32.781374 ==
6873 22:14:32.781454
6874 22:14:32.781517
6875 22:14:32.781576 TX Vref Scan disable
6876 22:14:32.784508 == TX Byte 0 ==
6877 22:14:32.788227 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6878 22:14:32.791332 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6879 22:14:32.794613 == TX Byte 1 ==
6880 22:14:32.797698 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6881 22:14:32.801575 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6882 22:14:32.801655
6883 22:14:32.804522 [DATLAT]
6884 22:14:32.804606 Freq=400, CH1 RK1
6885 22:14:32.804743
6886 22:14:32.807787 DATLAT Default: 0xe
6887 22:14:32.807868 0, 0xFFFF, sum = 0
6888 22:14:32.810823 1, 0xFFFF, sum = 0
6889 22:14:32.810905 2, 0xFFFF, sum = 0
6890 22:14:32.814077 3, 0xFFFF, sum = 0
6891 22:14:32.814160 4, 0xFFFF, sum = 0
6892 22:14:32.817929 5, 0xFFFF, sum = 0
6893 22:14:32.818011 6, 0xFFFF, sum = 0
6894 22:14:32.820736 7, 0xFFFF, sum = 0
6895 22:14:32.820817 8, 0xFFFF, sum = 0
6896 22:14:32.824404 9, 0xFFFF, sum = 0
6897 22:14:32.824486 10, 0xFFFF, sum = 0
6898 22:14:32.827820 11, 0xFFFF, sum = 0
6899 22:14:32.830434 12, 0xFFFF, sum = 0
6900 22:14:32.830515 13, 0x0, sum = 1
6901 22:14:32.834244 14, 0x0, sum = 2
6902 22:14:32.834339 15, 0x0, sum = 3
6903 22:14:32.834404 16, 0x0, sum = 4
6904 22:14:32.837354 best_step = 14
6905 22:14:32.837434
6906 22:14:32.837498 ==
6907 22:14:32.840629 Dram Type= 6, Freq= 0, CH_1, rank 1
6908 22:14:32.843793 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6909 22:14:32.843869 ==
6910 22:14:32.847027 RX Vref Scan: 0
6911 22:14:32.847099
6912 22:14:32.847160 RX Vref 0 -> 0, step: 1
6913 22:14:32.850346
6914 22:14:32.850415 RX Delay -343 -> 252, step: 8
6915 22:14:32.859059 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6916 22:14:32.862292 iDelay=217, Bit 1, Center -40 (-287 ~ 208) 496
6917 22:14:32.865654 iDelay=217, Bit 2, Center -44 (-287 ~ 200) 488
6918 22:14:32.871921 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6919 22:14:32.875573 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6920 22:14:32.878550 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6921 22:14:32.882219 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6922 22:14:32.888483 iDelay=217, Bit 7, Center -40 (-287 ~ 208) 496
6923 22:14:32.891927 iDelay=217, Bit 8, Center -56 (-295 ~ 184) 480
6924 22:14:32.894944 iDelay=217, Bit 9, Center -48 (-287 ~ 192) 480
6925 22:14:32.898287 iDelay=217, Bit 10, Center -40 (-287 ~ 208) 496
6926 22:14:32.905012 iDelay=217, Bit 11, Center -48 (-287 ~ 192) 480
6927 22:14:32.908251 iDelay=217, Bit 12, Center -32 (-271 ~ 208) 480
6928 22:14:32.911440 iDelay=217, Bit 13, Center -32 (-271 ~ 208) 480
6929 22:14:32.914937 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6930 22:14:32.921453 iDelay=217, Bit 15, Center -32 (-279 ~ 216) 496
6931 22:14:32.921531 ==
6932 22:14:32.924893 Dram Type= 6, Freq= 0, CH_1, rank 1
6933 22:14:32.927991 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6934 22:14:32.928081 ==
6935 22:14:32.931195 DQS Delay:
6936 22:14:32.931290 DQS0 = 44, DQS1 = 56
6937 22:14:32.931389 DQM Delay:
6938 22:14:32.934638 DQM0 = 8, DQM1 = 15
6939 22:14:32.934733 DQ Delay:
6940 22:14:32.937727 DQ0 =8, DQ1 =4, DQ2 =0, DQ3 =8
6941 22:14:32.941247 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =4
6942 22:14:32.944419 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6943 22:14:32.947608 DQ12 =24, DQ13 =24, DQ14 =20, DQ15 =24
6944 22:14:32.947688
6945 22:14:32.947752
6946 22:14:32.957438 [DQSOSCAuto] RK1, (LSB)MR18= 0x6fa6, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 395 ps
6947 22:14:32.957520 CH1 RK1: MR19=C0C, MR18=6FA6
6948 22:14:32.963766 CH1_RK1: MR19=0xC0C, MR18=0x6FA6, DQSOSC=389, MR23=63, INC=390, DEC=260
6949 22:14:32.967062 [RxdqsGatingPostProcess] freq 400
6950 22:14:32.973748 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6951 22:14:32.976869 best DQS0 dly(2T, 0.5T) = (0, 10)
6952 22:14:32.980467 best DQS1 dly(2T, 0.5T) = (0, 10)
6953 22:14:32.983696 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6954 22:14:32.986949 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6955 22:14:32.990232 best DQS0 dly(2T, 0.5T) = (0, 10)
6956 22:14:32.993710 best DQS1 dly(2T, 0.5T) = (0, 10)
6957 22:14:32.996809 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6958 22:14:33.000139 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6959 22:14:33.000214 Pre-setting of DQS Precalculation
6960 22:14:33.006699 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6961 22:14:33.013104 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6962 22:14:33.019895 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6963 22:14:33.020008
6964 22:14:33.020119
6965 22:14:33.023240 [Calibration Summary] 800 Mbps
6966 22:14:33.026340 CH 0, Rank 0
6967 22:14:33.026436 SW Impedance : PASS
6968 22:14:33.029810 DUTY Scan : NO K
6969 22:14:33.033123 ZQ Calibration : PASS
6970 22:14:33.033223 Jitter Meter : NO K
6971 22:14:33.036401 CBT Training : PASS
6972 22:14:33.039558 Write leveling : PASS
6973 22:14:33.039629 RX DQS gating : PASS
6974 22:14:33.043016 RX DQ/DQS(RDDQC) : PASS
6975 22:14:33.046195 TX DQ/DQS : PASS
6976 22:14:33.046292 RX DATLAT : PASS
6977 22:14:33.049219 RX DQ/DQS(Engine): PASS
6978 22:14:33.052991 TX OE : NO K
6979 22:14:33.053069 All Pass.
6980 22:14:33.053131
6981 22:14:33.053189 CH 0, Rank 1
6982 22:14:33.056589 SW Impedance : PASS
6983 22:14:33.059610 DUTY Scan : NO K
6984 22:14:33.059703 ZQ Calibration : PASS
6985 22:14:33.062593 Jitter Meter : NO K
6986 22:14:33.062686 CBT Training : PASS
6987 22:14:33.065835 Write leveling : NO K
6988 22:14:33.069500 RX DQS gating : PASS
6989 22:14:33.069600 RX DQ/DQS(RDDQC) : PASS
6990 22:14:33.072653 TX DQ/DQS : PASS
6991 22:14:33.075583 RX DATLAT : PASS
6992 22:14:33.075679 RX DQ/DQS(Engine): PASS
6993 22:14:33.079075 TX OE : NO K
6994 22:14:33.079169 All Pass.
6995 22:14:33.079263
6996 22:14:33.082495 CH 1, Rank 0
6997 22:14:33.082594 SW Impedance : PASS
6998 22:14:33.085739 DUTY Scan : NO K
6999 22:14:33.088765 ZQ Calibration : PASS
7000 22:14:33.088859 Jitter Meter : NO K
7001 22:14:33.092053 CBT Training : PASS
7002 22:14:33.095310 Write leveling : PASS
7003 22:14:33.095403 RX DQS gating : PASS
7004 22:14:33.098938 RX DQ/DQS(RDDQC) : PASS
7005 22:14:33.102034 TX DQ/DQS : PASS
7006 22:14:33.102106 RX DATLAT : PASS
7007 22:14:33.105217 RX DQ/DQS(Engine): PASS
7008 22:14:33.109062 TX OE : NO K
7009 22:14:33.109142 All Pass.
7010 22:14:33.109206
7011 22:14:33.109266 CH 1, Rank 1
7012 22:14:33.111723 SW Impedance : PASS
7013 22:14:33.114986 DUTY Scan : NO K
7014 22:14:33.115081 ZQ Calibration : PASS
7015 22:14:33.119117 Jitter Meter : NO K
7016 22:14:33.121691 CBT Training : PASS
7017 22:14:33.121789 Write leveling : NO K
7018 22:14:33.125092 RX DQS gating : PASS
7019 22:14:33.128188 RX DQ/DQS(RDDQC) : PASS
7020 22:14:33.128268 TX DQ/DQS : PASS
7021 22:14:33.131712 RX DATLAT : PASS
7022 22:14:33.134978 RX DQ/DQS(Engine): PASS
7023 22:14:33.135098 TX OE : NO K
7024 22:14:33.137993 All Pass.
7025 22:14:33.138114
7026 22:14:33.138180 DramC Write-DBI off
7027 22:14:33.141382 PER_BANK_REFRESH: Hybrid Mode
7028 22:14:33.141462 TX_TRACKING: ON
7029 22:14:33.151475 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7030 22:14:33.154861 [FAST_K] Save calibration result to emmc
7031 22:14:33.158128 dramc_set_vcore_voltage set vcore to 725000
7032 22:14:33.161393 Read voltage for 1600, 0
7033 22:14:33.161464 Vio18 = 0
7034 22:14:33.164368 Vcore = 725000
7035 22:14:33.164463 Vdram = 0
7036 22:14:33.164580 Vddq = 0
7037 22:14:33.167974 Vmddr = 0
7038 22:14:33.171114 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7039 22:14:33.177545 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7040 22:14:33.177642 MEM_TYPE=3, freq_sel=13
7041 22:14:33.180796 sv_algorithm_assistance_LP4_3733
7042 22:14:33.187628 ============ PULL DRAM RESETB DOWN ============
7043 22:14:33.190889 ========== PULL DRAM RESETB DOWN end =========
7044 22:14:33.194193 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7045 22:14:33.197980 ===================================
7046 22:14:33.200987 LPDDR4 DRAM CONFIGURATION
7047 22:14:33.204185 ===================================
7048 22:14:33.207812 EX_ROW_EN[0] = 0x0
7049 22:14:33.207910 EX_ROW_EN[1] = 0x0
7050 22:14:33.210623 LP4Y_EN = 0x0
7051 22:14:33.210724 WORK_FSP = 0x1
7052 22:14:33.214313 WL = 0x5
7053 22:14:33.214387 RL = 0x5
7054 22:14:33.217233 BL = 0x2
7055 22:14:33.217324 RPST = 0x0
7056 22:14:33.220508 RD_PRE = 0x0
7057 22:14:33.220588 WR_PRE = 0x1
7058 22:14:33.224011 WR_PST = 0x1
7059 22:14:33.224146 DBI_WR = 0x0
7060 22:14:33.227413 DBI_RD = 0x0
7061 22:14:33.227493 OTF = 0x1
7062 22:14:33.230269 ===================================
7063 22:14:33.234119 ===================================
7064 22:14:33.237166 ANA top config
7065 22:14:33.240238 ===================================
7066 22:14:33.243483 DLL_ASYNC_EN = 0
7067 22:14:33.243565 ALL_SLAVE_EN = 0
7068 22:14:33.246800 NEW_RANK_MODE = 1
7069 22:14:33.250358 DLL_IDLE_MODE = 1
7070 22:14:33.253699 LP45_APHY_COMB_EN = 1
7071 22:14:33.257230 TX_ODT_DIS = 0
7072 22:14:33.257319 NEW_8X_MODE = 1
7073 22:14:33.260370 ===================================
7074 22:14:33.263501 ===================================
7075 22:14:33.266758 data_rate = 3200
7076 22:14:33.270171 CKR = 1
7077 22:14:33.273454 DQ_P2S_RATIO = 8
7078 22:14:33.276608 ===================================
7079 22:14:33.279828 CA_P2S_RATIO = 8
7080 22:14:33.283193 DQ_CA_OPEN = 0
7081 22:14:33.283300 DQ_SEMI_OPEN = 0
7082 22:14:33.286630 CA_SEMI_OPEN = 0
7083 22:14:33.289571 CA_FULL_RATE = 0
7084 22:14:33.292996 DQ_CKDIV4_EN = 0
7085 22:14:33.296146 CA_CKDIV4_EN = 0
7086 22:14:33.299903 CA_PREDIV_EN = 0
7087 22:14:33.300002 PH8_DLY = 12
7088 22:14:33.302672 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7089 22:14:33.305991 DQ_AAMCK_DIV = 4
7090 22:14:33.309434 CA_AAMCK_DIV = 4
7091 22:14:33.313115 CA_ADMCK_DIV = 4
7092 22:14:33.316117 DQ_TRACK_CA_EN = 0
7093 22:14:33.319071 CA_PICK = 1600
7094 22:14:33.322732 CA_MCKIO = 1600
7095 22:14:33.322816 MCKIO_SEMI = 0
7096 22:14:33.325792 PLL_FREQ = 3068
7097 22:14:33.329380 DQ_UI_PI_RATIO = 32
7098 22:14:33.332620 CA_UI_PI_RATIO = 0
7099 22:14:33.335740 ===================================
7100 22:14:33.339313 ===================================
7101 22:14:33.342816 memory_type:LPDDR4
7102 22:14:33.342890 GP_NUM : 10
7103 22:14:33.345831 SRAM_EN : 1
7104 22:14:33.348732 MD32_EN : 0
7105 22:14:33.352171 ===================================
7106 22:14:33.352251 [ANA_INIT] >>>>>>>>>>>>>>
7107 22:14:33.355729 <<<<<< [CONFIGURE PHASE]: ANA_TX
7108 22:14:33.359029 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7109 22:14:33.361960 ===================================
7110 22:14:33.365312 data_rate = 3200,PCW = 0X7600
7111 22:14:33.368554 ===================================
7112 22:14:33.371959 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7113 22:14:33.378719 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7114 22:14:33.381724 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7115 22:14:33.388427 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7116 22:14:33.392104 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7117 22:14:33.395335 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7118 22:14:33.398281 [ANA_INIT] flow start
7119 22:14:33.398351 [ANA_INIT] PLL >>>>>>>>
7120 22:14:33.401261 [ANA_INIT] PLL <<<<<<<<
7121 22:14:33.405063 [ANA_INIT] MIDPI >>>>>>>>
7122 22:14:33.405132 [ANA_INIT] MIDPI <<<<<<<<
7123 22:14:33.408301 [ANA_INIT] DLL >>>>>>>>
7124 22:14:33.411438 [ANA_INIT] DLL <<<<<<<<
7125 22:14:33.411508 [ANA_INIT] flow end
7126 22:14:33.418192 ============ LP4 DIFF to SE enter ============
7127 22:14:33.421640 ============ LP4 DIFF to SE exit ============
7128 22:14:33.421712 [ANA_INIT] <<<<<<<<<<<<<
7129 22:14:33.425334 [Flow] Enable top DCM control >>>>>
7130 22:14:33.428151 [Flow] Enable top DCM control <<<<<
7131 22:14:33.430954 Enable DLL master slave shuffle
7132 22:14:33.437548 ==============================================================
7133 22:14:33.441132 Gating Mode config
7134 22:14:33.444651 ==============================================================
7135 22:14:33.447966 Config description:
7136 22:14:33.457582 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7137 22:14:33.464229 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7138 22:14:33.467673 SELPH_MODE 0: By rank 1: By Phase
7139 22:14:33.474039 ==============================================================
7140 22:14:33.477840 GAT_TRACK_EN = 1
7141 22:14:33.480992 RX_GATING_MODE = 2
7142 22:14:33.484004 RX_GATING_TRACK_MODE = 2
7143 22:14:33.484109 SELPH_MODE = 1
7144 22:14:33.487275 PICG_EARLY_EN = 1
7145 22:14:33.490660 VALID_LAT_VALUE = 1
7146 22:14:33.497221 ==============================================================
7147 22:14:33.500705 Enter into Gating configuration >>>>
7148 22:14:33.503875 Exit from Gating configuration <<<<
7149 22:14:33.507089 Enter into DVFS_PRE_config >>>>>
7150 22:14:33.517107 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7151 22:14:33.520073 Exit from DVFS_PRE_config <<<<<
7152 22:14:33.523625 Enter into PICG configuration >>>>
7153 22:14:33.527059 Exit from PICG configuration <<<<
7154 22:14:33.529810 [RX_INPUT] configuration >>>>>
7155 22:14:33.533459 [RX_INPUT] configuration <<<<<
7156 22:14:33.540203 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7157 22:14:33.543564 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7158 22:14:33.549875 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7159 22:14:33.556191 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7160 22:14:33.563091 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7161 22:14:33.569218 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7162 22:14:33.572609 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7163 22:14:33.575823 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7164 22:14:33.579461 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7165 22:14:33.585766 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7166 22:14:33.589382 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7167 22:14:33.592607 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7168 22:14:33.595931 ===================================
7169 22:14:33.599292 LPDDR4 DRAM CONFIGURATION
7170 22:14:33.602313 ===================================
7171 22:14:33.605788 EX_ROW_EN[0] = 0x0
7172 22:14:33.605859 EX_ROW_EN[1] = 0x0
7173 22:14:33.609107 LP4Y_EN = 0x0
7174 22:14:33.609176 WORK_FSP = 0x1
7175 22:14:33.612253 WL = 0x5
7176 22:14:33.612322 RL = 0x5
7177 22:14:33.615203 BL = 0x2
7178 22:14:33.615270 RPST = 0x0
7179 22:14:33.618659 RD_PRE = 0x0
7180 22:14:33.618725 WR_PRE = 0x1
7181 22:14:33.621973 WR_PST = 0x1
7182 22:14:33.622040 DBI_WR = 0x0
7183 22:14:33.625537 DBI_RD = 0x0
7184 22:14:33.628396 OTF = 0x1
7185 22:14:33.631782 ===================================
7186 22:14:33.635060 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7187 22:14:33.638306 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7188 22:14:33.641766 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7189 22:14:33.644986 ===================================
7190 22:14:33.648300 LPDDR4 DRAM CONFIGURATION
7191 22:14:33.651755 ===================================
7192 22:14:33.655183 EX_ROW_EN[0] = 0x10
7193 22:14:33.655249 EX_ROW_EN[1] = 0x0
7194 22:14:33.658312 LP4Y_EN = 0x0
7195 22:14:33.658387 WORK_FSP = 0x1
7196 22:14:33.661523 WL = 0x5
7197 22:14:33.661601 RL = 0x5
7198 22:14:33.664746 BL = 0x2
7199 22:14:33.664817 RPST = 0x0
7200 22:14:33.668534 RD_PRE = 0x0
7201 22:14:33.668606 WR_PRE = 0x1
7202 22:14:33.671733 WR_PST = 0x1
7203 22:14:33.671801 DBI_WR = 0x0
7204 22:14:33.674503 DBI_RD = 0x0
7205 22:14:33.677813 OTF = 0x1
7206 22:14:33.681555 ===================================
7207 22:14:33.684511 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7208 22:14:33.684577 ==
7209 22:14:33.687739 Dram Type= 6, Freq= 0, CH_0, rank 0
7210 22:14:33.694544 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7211 22:14:33.694614 ==
7212 22:14:33.697544 [Duty_Offset_Calibration]
7213 22:14:33.697613 B0:2 B1:0 CA:4
7214 22:14:33.697672
7215 22:14:33.701128 [DutyScan_Calibration_Flow] k_type=0
7216 22:14:33.710185
7217 22:14:33.710259 ==CLK 0==
7218 22:14:33.713170 Final CLK duty delay cell = -4
7219 22:14:33.716471 [-4] MAX Duty = 5031%(X100), DQS PI = 30
7220 22:14:33.719785 [-4] MIN Duty = 4813%(X100), DQS PI = 8
7221 22:14:33.723386 [-4] AVG Duty = 4922%(X100)
7222 22:14:33.723454
7223 22:14:33.726259 CH0 CLK Duty spec in!! Max-Min= 218%
7224 22:14:33.729676 [DutyScan_Calibration_Flow] ====Done====
7225 22:14:33.729750
7226 22:14:33.733324 [DutyScan_Calibration_Flow] k_type=1
7227 22:14:33.749396
7228 22:14:33.749471 ==DQS 0 ==
7229 22:14:33.752804 Final DQS duty delay cell = -4
7230 22:14:33.755994 [-4] MAX Duty = 4907%(X100), DQS PI = 46
7231 22:14:33.759374 [-4] MIN Duty = 4782%(X100), DQS PI = 2
7232 22:14:33.762776 [-4] AVG Duty = 4844%(X100)
7233 22:14:33.762848
7234 22:14:33.762908 ==DQS 1 ==
7235 22:14:33.766020 Final DQS duty delay cell = 0
7236 22:14:33.769220 [0] MAX Duty = 5187%(X100), DQS PI = 2
7237 22:14:33.772598 [0] MIN Duty = 4969%(X100), DQS PI = 10
7238 22:14:33.775523 [0] AVG Duty = 5078%(X100)
7239 22:14:33.775590
7240 22:14:33.778814 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7241 22:14:33.778886
7242 22:14:33.782380 CH0 DQS 1 Duty spec in!! Max-Min= 218%
7243 22:14:33.785573 [DutyScan_Calibration_Flow] ====Done====
7244 22:14:33.785642
7245 22:14:33.789008 [DutyScan_Calibration_Flow] k_type=3
7246 22:14:33.806800
7247 22:14:33.806875 ==DQM 0 ==
7248 22:14:33.810612 Final DQM duty delay cell = 0
7249 22:14:33.813855 [0] MAX Duty = 5124%(X100), DQS PI = 20
7250 22:14:33.817028 [0] MIN Duty = 4907%(X100), DQS PI = 52
7251 22:14:33.817100 [0] AVG Duty = 5015%(X100)
7252 22:14:33.820337
7253 22:14:33.820410 ==DQM 1 ==
7254 22:14:33.823689 Final DQM duty delay cell = 0
7255 22:14:33.826785 [0] MAX Duty = 4969%(X100), DQS PI = 2
7256 22:14:33.830352 [0] MIN Duty = 4844%(X100), DQS PI = 18
7257 22:14:33.833537 [0] AVG Duty = 4906%(X100)
7258 22:14:33.833602
7259 22:14:33.837114 CH0 DQM 0 Duty spec in!! Max-Min= 217%
7260 22:14:33.837193
7261 22:14:33.839866 CH0 DQM 1 Duty spec in!! Max-Min= 125%
7262 22:14:33.843481 [DutyScan_Calibration_Flow] ====Done====
7263 22:14:33.843556
7264 22:14:33.846845 [DutyScan_Calibration_Flow] k_type=2
7265 22:14:33.864293
7266 22:14:33.864370 ==DQ 0 ==
7267 22:14:33.867318 Final DQ duty delay cell = 0
7268 22:14:33.870894 [0] MAX Duty = 5156%(X100), DQS PI = 22
7269 22:14:33.874255 [0] MIN Duty = 4969%(X100), DQS PI = 12
7270 22:14:33.877125 [0] AVG Duty = 5062%(X100)
7271 22:14:33.877194
7272 22:14:33.877254 ==DQ 1 ==
7273 22:14:33.880559 Final DQ duty delay cell = 0
7274 22:14:33.884287 [0] MAX Duty = 5218%(X100), DQS PI = 2
7275 22:14:33.887492 [0] MIN Duty = 4938%(X100), DQS PI = 12
7276 22:14:33.887565 [0] AVG Duty = 5078%(X100)
7277 22:14:33.890394
7278 22:14:33.893856 CH0 DQ 0 Duty spec in!! Max-Min= 187%
7279 22:14:33.893924
7280 22:14:33.897117 CH0 DQ 1 Duty spec in!! Max-Min= 280%
7281 22:14:33.900143 [DutyScan_Calibration_Flow] ====Done====
7282 22:14:33.900212 ==
7283 22:14:33.903391 Dram Type= 6, Freq= 0, CH_1, rank 0
7284 22:14:33.906548 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7285 22:14:33.906620 ==
7286 22:14:33.910063 [Duty_Offset_Calibration]
7287 22:14:33.910139 B0:0 B1:-1 CA:3
7288 22:14:33.910199
7289 22:14:33.913116 [DutyScan_Calibration_Flow] k_type=0
7290 22:14:33.923351
7291 22:14:33.923452 ==CLK 0==
7292 22:14:33.926665 Final CLK duty delay cell = -4
7293 22:14:33.929820 [-4] MAX Duty = 5000%(X100), DQS PI = 4
7294 22:14:33.933684 [-4] MIN Duty = 4875%(X100), DQS PI = 12
7295 22:14:33.936606 [-4] AVG Duty = 4937%(X100)
7296 22:14:33.936676
7297 22:14:33.939901 CH1 CLK Duty spec in!! Max-Min= 125%
7298 22:14:33.943251 [DutyScan_Calibration_Flow] ====Done====
7299 22:14:33.943326
7300 22:14:33.946276 [DutyScan_Calibration_Flow] k_type=1
7301 22:14:33.962651
7302 22:14:33.962725 ==DQS 0 ==
7303 22:14:33.965801 Final DQS duty delay cell = 0
7304 22:14:33.968976 [0] MAX Duty = 5250%(X100), DQS PI = 28
7305 22:14:33.972620 [0] MIN Duty = 4907%(X100), DQS PI = 58
7306 22:14:33.976025 [0] AVG Duty = 5078%(X100)
7307 22:14:33.976114
7308 22:14:33.976179 ==DQS 1 ==
7309 22:14:33.978864 Final DQS duty delay cell = -4
7310 22:14:33.982207 [-4] MAX Duty = 5000%(X100), DQS PI = 28
7311 22:14:33.985560 [-4] MIN Duty = 4813%(X100), DQS PI = 0
7312 22:14:33.989256 [-4] AVG Duty = 4906%(X100)
7313 22:14:33.989336
7314 22:14:33.992178 CH1 DQS 0 Duty spec in!! Max-Min= 343%
7315 22:14:33.992250
7316 22:14:33.995537 CH1 DQS 1 Duty spec in!! Max-Min= 187%
7317 22:14:33.998965 [DutyScan_Calibration_Flow] ====Done====
7318 22:14:33.999036
7319 22:14:34.002079 [DutyScan_Calibration_Flow] k_type=3
7320 22:14:34.019628
7321 22:14:34.019703 ==DQM 0 ==
7322 22:14:34.023279 Final DQM duty delay cell = 0
7323 22:14:34.026450 [0] MAX Duty = 5062%(X100), DQS PI = 30
7324 22:14:34.029660 [0] MIN Duty = 4750%(X100), DQS PI = 40
7325 22:14:34.032817 [0] AVG Duty = 4906%(X100)
7326 22:14:34.032883
7327 22:14:34.032968 ==DQM 1 ==
7328 22:14:34.036605 Final DQM duty delay cell = 0
7329 22:14:34.039574 [0] MAX Duty = 5000%(X100), DQS PI = 30
7330 22:14:34.042983 [0] MIN Duty = 4813%(X100), DQS PI = 0
7331 22:14:34.046246 [0] AVG Duty = 4906%(X100)
7332 22:14:34.046321
7333 22:14:34.049467 CH1 DQM 0 Duty spec in!! Max-Min= 312%
7334 22:14:34.049538
7335 22:14:34.053105 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7336 22:14:34.056182 [DutyScan_Calibration_Flow] ====Done====
7337 22:14:34.056250
7338 22:14:34.059139 [DutyScan_Calibration_Flow] k_type=2
7339 22:14:34.076396
7340 22:14:34.076464 ==DQ 0 ==
7341 22:14:34.079375 Final DQ duty delay cell = -4
7342 22:14:34.082361 [-4] MAX Duty = 4938%(X100), DQS PI = 0
7343 22:14:34.085669 [-4] MIN Duty = 4813%(X100), DQS PI = 36
7344 22:14:34.089163 [-4] AVG Duty = 4875%(X100)
7345 22:14:34.089232
7346 22:14:34.089299 ==DQ 1 ==
7347 22:14:34.092176 Final DQ duty delay cell = 0
7348 22:14:34.095512 [0] MAX Duty = 5031%(X100), DQS PI = 30
7349 22:14:34.099065 [0] MIN Duty = 4875%(X100), DQS PI = 0
7350 22:14:34.102260 [0] AVG Duty = 4953%(X100)
7351 22:14:34.102326
7352 22:14:34.105705 CH1 DQ 0 Duty spec in!! Max-Min= 125%
7353 22:14:34.105775
7354 22:14:34.108894 CH1 DQ 1 Duty spec in!! Max-Min= 156%
7355 22:14:34.112436 [DutyScan_Calibration_Flow] ====Done====
7356 22:14:34.115654 nWR fixed to 30
7357 22:14:34.118689 [ModeRegInit_LP4] CH0 RK0
7358 22:14:34.118760 [ModeRegInit_LP4] CH0 RK1
7359 22:14:34.122050 [ModeRegInit_LP4] CH1 RK0
7360 22:14:34.125220 [ModeRegInit_LP4] CH1 RK1
7361 22:14:34.125299 match AC timing 5
7362 22:14:34.132129 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7363 22:14:34.135178 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7364 22:14:34.138299 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7365 22:14:34.145111 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7366 22:14:34.148262 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7367 22:14:34.151644 [MiockJmeterHQA]
7368 22:14:34.151722
7369 22:14:34.154665 [DramcMiockJmeter] u1RxGatingPI = 0
7370 22:14:34.154743 0 : 4253, 4026
7371 22:14:34.154807 4 : 4363, 4138
7372 22:14:34.158049 8 : 4253, 4027
7373 22:14:34.158129 12 : 4363, 4138
7374 22:14:34.161070 16 : 4362, 4137
7375 22:14:34.161154 20 : 4252, 4027
7376 22:14:34.164614 24 : 4252, 4027
7377 22:14:34.164695 28 : 4252, 4027
7378 22:14:34.168058 32 : 4363, 4138
7379 22:14:34.168152 36 : 4253, 4026
7380 22:14:34.168215 40 : 4361, 4137
7381 22:14:34.171503 44 : 4252, 4026
7382 22:14:34.171582 48 : 4250, 4027
7383 22:14:34.174356 52 : 4250, 4027
7384 22:14:34.174435 56 : 4250, 4026
7385 22:14:34.177495 60 : 4360, 4138
7386 22:14:34.177574 64 : 4250, 4027
7387 22:14:34.181308 68 : 4361, 4137
7388 22:14:34.181387 72 : 4250, 4027
7389 22:14:34.181450 76 : 4250, 4026
7390 22:14:34.184323 80 : 4250, 4027
7391 22:14:34.184438 84 : 4361, 4137
7392 22:14:34.187757 88 : 4250, 4026
7393 22:14:34.187838 92 : 4360, 4138
7394 22:14:34.190765 96 : 4250, 2987
7395 22:14:34.190846 100 : 4250, 0
7396 22:14:34.190911 104 : 4250, 0
7397 22:14:34.194085 108 : 4252, 0
7398 22:14:34.194167 112 : 4252, 0
7399 22:14:34.197690 116 : 4250, 0
7400 22:14:34.197797 120 : 4250, 0
7401 22:14:34.197891 124 : 4250, 0
7402 22:14:34.200646 128 : 4250, 0
7403 22:14:34.200728 132 : 4363, 0
7404 22:14:34.203775 136 : 4361, 0
7405 22:14:34.203856 140 : 4363, 0
7406 22:14:34.203921 144 : 4252, 0
7407 22:14:34.207257 148 : 4253, 0
7408 22:14:34.207391 152 : 4250, 0
7409 22:14:34.210448 156 : 4252, 0
7410 22:14:34.210529 160 : 4252, 0
7411 22:14:34.210594 164 : 4249, 0
7412 22:14:34.213931 168 : 4250, 0
7413 22:14:34.214012 172 : 4252, 0
7414 22:14:34.217566 176 : 4249, 0
7415 22:14:34.217647 180 : 4252, 0
7416 22:14:34.217712 184 : 4363, 0
7417 22:14:34.220310 188 : 4361, 0
7418 22:14:34.220397 192 : 4363, 0
7419 22:14:34.220528 196 : 4253, 0
7420 22:14:34.223551 200 : 4253, 0
7421 22:14:34.223633 204 : 4250, 0
7422 22:14:34.227404 208 : 4252, 0
7423 22:14:34.227485 212 : 4252, 0
7424 22:14:34.227550 216 : 4250, 0
7425 22:14:34.230051 220 : 4252, 910
7426 22:14:34.230133 224 : 4360, 4120
7427 22:14:34.233543 228 : 4252, 4027
7428 22:14:34.233624 232 : 4250, 4027
7429 22:14:34.237165 236 : 4252, 4029
7430 22:14:34.237246 240 : 4250, 4027
7431 22:14:34.240405 244 : 4250, 4026
7432 22:14:34.240486 248 : 4250, 4027
7433 22:14:34.243506 252 : 4250, 4026
7434 22:14:34.243587 256 : 4250, 4027
7435 22:14:34.246725 260 : 4360, 4138
7436 22:14:34.246806 264 : 4361, 4137
7437 22:14:34.249971 268 : 4248, 4024
7438 22:14:34.250052 272 : 4361, 4137
7439 22:14:34.250150 276 : 4360, 4138
7440 22:14:34.253192 280 : 4250, 4026
7441 22:14:34.253274 284 : 4250, 4027
7442 22:14:34.256776 288 : 4250, 4026
7443 22:14:34.256858 292 : 4250, 4027
7444 22:14:34.259806 296 : 4250, 4027
7445 22:14:34.259887 300 : 4250, 4027
7446 22:14:34.263238 304 : 4250, 4026
7447 22:14:34.263320 308 : 4250, 4027
7448 22:14:34.266775 312 : 4360, 4138
7449 22:14:34.266857 316 : 4361, 4137
7450 22:14:34.270248 320 : 4250, 4026
7451 22:14:34.270344 324 : 4361, 4137
7452 22:14:34.273489 328 : 4360, 4138
7453 22:14:34.273570 332 : 4250, 3999
7454 22:14:34.273634 336 : 4250, 2053
7455 22:14:34.276410
7456 22:14:34.276490 MIOCK jitter meter ch=0
7457 22:14:34.276555
7458 22:14:34.279604 1T = (336-100) = 236 dly cells
7459 22:14:34.286274 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7460 22:14:34.286354 ==
7461 22:14:34.289826 Dram Type= 6, Freq= 0, CH_0, rank 0
7462 22:14:34.293570 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7463 22:14:34.293651 ==
7464 22:14:34.299293 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7465 22:14:34.302921 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7466 22:14:34.305988 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7467 22:14:34.312535 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7468 22:14:34.322588 [CA 0] Center 44 (14~74) winsize 61
7469 22:14:34.326044 [CA 1] Center 43 (13~74) winsize 62
7470 22:14:34.328984 [CA 2] Center 39 (10~68) winsize 59
7471 22:14:34.332203 [CA 3] Center 38 (9~68) winsize 60
7472 22:14:34.335781 [CA 4] Center 36 (7~66) winsize 60
7473 22:14:34.339260 [CA 5] Center 36 (6~66) winsize 61
7474 22:14:34.339340
7475 22:14:34.342363 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7476 22:14:34.342445
7477 22:14:34.345381 [CATrainingPosCal] consider 1 rank data
7478 22:14:34.349102 u2DelayCellTimex100 = 275/100 ps
7479 22:14:34.355366 CA0 delay=44 (14~74),Diff = 8 PI (28 cell)
7480 22:14:34.358540 CA1 delay=43 (13~74),Diff = 7 PI (24 cell)
7481 22:14:34.362343 CA2 delay=39 (10~68),Diff = 3 PI (10 cell)
7482 22:14:34.365443 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7483 22:14:34.368755 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7484 22:14:34.372337 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7485 22:14:34.372420
7486 22:14:34.375230 CA PerBit enable=1, Macro0, CA PI delay=36
7487 22:14:34.375312
7488 22:14:34.378312 [CBTSetCACLKResult] CA Dly = 36
7489 22:14:34.382208 CS Dly: 10 (0~41)
7490 22:14:34.385374 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7491 22:14:34.388618 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7492 22:14:34.388700 ==
7493 22:14:34.391845 Dram Type= 6, Freq= 0, CH_0, rank 1
7494 22:14:34.398485 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7495 22:14:34.398568 ==
7496 22:14:34.401641 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7497 22:14:34.408567 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7498 22:14:34.411988 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7499 22:14:34.418412 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7500 22:14:34.426059 [CA 0] Center 43 (13~74) winsize 62
7501 22:14:34.429535 [CA 1] Center 43 (13~73) winsize 61
7502 22:14:34.432649 [CA 2] Center 38 (9~68) winsize 60
7503 22:14:34.436427 [CA 3] Center 38 (9~68) winsize 60
7504 22:14:34.439221 [CA 4] Center 36 (6~67) winsize 62
7505 22:14:34.443083 [CA 5] Center 36 (6~66) winsize 61
7506 22:14:34.443182
7507 22:14:34.446286 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7508 22:14:34.446384
7509 22:14:34.449423 [CATrainingPosCal] consider 2 rank data
7510 22:14:34.452201 u2DelayCellTimex100 = 275/100 ps
7511 22:14:34.458857 CA0 delay=44 (14~74),Diff = 8 PI (28 cell)
7512 22:14:34.462663 CA1 delay=43 (13~73),Diff = 7 PI (24 cell)
7513 22:14:34.465848 CA2 delay=39 (10~68),Diff = 3 PI (10 cell)
7514 22:14:34.468945 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7515 22:14:34.472085 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7516 22:14:34.475699 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7517 22:14:34.475770
7518 22:14:34.478776 CA PerBit enable=1, Macro0, CA PI delay=36
7519 22:14:34.478875
7520 22:14:34.482616 [CBTSetCACLKResult] CA Dly = 36
7521 22:14:34.485823 CS Dly: 11 (0~43)
7522 22:14:34.489074 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7523 22:14:34.492079 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7524 22:14:34.492150
7525 22:14:34.495548 ----->DramcWriteLeveling(PI) begin...
7526 22:14:34.495646 ==
7527 22:14:34.498676 Dram Type= 6, Freq= 0, CH_0, rank 0
7528 22:14:34.505084 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7529 22:14:34.505164 ==
7530 22:14:34.508623 Write leveling (Byte 0): 34 => 34
7531 22:14:34.511760 Write leveling (Byte 1): 27 => 27
7532 22:14:34.515223 DramcWriteLeveling(PI) end<-----
7533 22:14:34.515295
7534 22:14:34.515357 ==
7535 22:14:34.518220 Dram Type= 6, Freq= 0, CH_0, rank 0
7536 22:14:34.521598 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7537 22:14:34.521673 ==
7538 22:14:34.524969 [Gating] SW mode calibration
7539 22:14:34.531697 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7540 22:14:34.538388 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7541 22:14:34.541832 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7542 22:14:34.544817 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7543 22:14:34.551239 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7544 22:14:34.554727 1 4 12 | B1->B0 | 2323 3232 | 0 1 | (0 0) (1 1)
7545 22:14:34.558147 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7546 22:14:34.561496 1 4 20 | B1->B0 | 2828 3434 | 1 1 | (1 1) (1 1)
7547 22:14:34.567756 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7548 22:14:34.571378 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7549 22:14:34.574481 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7550 22:14:34.581328 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7551 22:14:34.584486 1 5 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
7552 22:14:34.587928 1 5 12 | B1->B0 | 3434 2424 | 1 0 | (1 1) (0 0)
7553 22:14:34.594551 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7554 22:14:34.597962 1 5 20 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
7555 22:14:34.603989 1 5 24 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
7556 22:14:34.607608 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7557 22:14:34.610727 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7558 22:14:34.617367 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7559 22:14:34.620799 1 6 8 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
7560 22:14:34.624324 1 6 12 | B1->B0 | 2323 4241 | 0 1 | (0 0) (0 0)
7561 22:14:34.630509 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7562 22:14:34.634092 1 6 20 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
7563 22:14:34.636889 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7564 22:14:34.644058 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7565 22:14:34.647303 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7566 22:14:34.650173 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7567 22:14:34.656748 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7568 22:14:34.659805 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7569 22:14:34.663063 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7570 22:14:34.670103 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7571 22:14:34.673425 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7572 22:14:34.676714 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7573 22:14:34.682938 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7574 22:14:34.686657 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7575 22:14:34.689869 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7576 22:14:34.696465 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7577 22:14:34.699978 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7578 22:14:34.702972 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7579 22:14:34.709488 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7580 22:14:34.712653 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7581 22:14:34.716121 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7582 22:14:34.722559 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7583 22:14:34.726206 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7584 22:14:34.729154 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7585 22:14:34.732378 Total UI for P1: 0, mck2ui 16
7586 22:14:34.735777 best dqsien dly found for B0: ( 1, 9, 10)
7587 22:14:34.742129 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7588 22:14:34.746066 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7589 22:14:34.748985 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7590 22:14:34.752009 Total UI for P1: 0, mck2ui 16
7591 22:14:34.755596 best dqsien dly found for B1: ( 1, 9, 20)
7592 22:14:34.758737 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7593 22:14:34.762184 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7594 22:14:34.762255
7595 22:14:34.768959 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7596 22:14:34.771967 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7597 22:14:34.775035 [Gating] SW calibration Done
7598 22:14:34.775104 ==
7599 22:14:34.778505 Dram Type= 6, Freq= 0, CH_0, rank 0
7600 22:14:34.781765 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7601 22:14:34.781838 ==
7602 22:14:34.781898 RX Vref Scan: 0
7603 22:14:34.781955
7604 22:14:34.785029 RX Vref 0 -> 0, step: 1
7605 22:14:34.785097
7606 22:14:34.788450 RX Delay 0 -> 252, step: 8
7607 22:14:34.791587 iDelay=192, Bit 0, Center 131 (80 ~ 183) 104
7608 22:14:34.794934 iDelay=192, Bit 1, Center 135 (80 ~ 191) 112
7609 22:14:34.801452 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
7610 22:14:34.805155 iDelay=192, Bit 3, Center 127 (72 ~ 183) 112
7611 22:14:34.808156 iDelay=192, Bit 4, Center 135 (80 ~ 191) 112
7612 22:14:34.811645 iDelay=192, Bit 5, Center 119 (64 ~ 175) 112
7613 22:14:34.814698 iDelay=192, Bit 6, Center 139 (88 ~ 191) 104
7614 22:14:34.821828 iDelay=192, Bit 7, Center 139 (88 ~ 191) 104
7615 22:14:34.825078 iDelay=192, Bit 8, Center 119 (64 ~ 175) 112
7616 22:14:34.828137 iDelay=192, Bit 9, Center 115 (64 ~ 167) 104
7617 22:14:34.831476 iDelay=192, Bit 10, Center 127 (80 ~ 175) 96
7618 22:14:34.834346 iDelay=192, Bit 11, Center 123 (72 ~ 175) 104
7619 22:14:34.841152 iDelay=192, Bit 12, Center 135 (80 ~ 191) 112
7620 22:14:34.844009 iDelay=192, Bit 13, Center 131 (80 ~ 183) 104
7621 22:14:34.847900 iDelay=192, Bit 14, Center 135 (80 ~ 191) 112
7622 22:14:34.851400 iDelay=192, Bit 15, Center 131 (80 ~ 183) 104
7623 22:14:34.851483 ==
7624 22:14:34.854496 Dram Type= 6, Freq= 0, CH_0, rank 0
7625 22:14:34.860713 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7626 22:14:34.860788 ==
7627 22:14:34.860850 DQS Delay:
7628 22:14:34.864010 DQS0 = 0, DQS1 = 0
7629 22:14:34.864112 DQM Delay:
7630 22:14:34.867474 DQM0 = 131, DQM1 = 127
7631 22:14:34.867554 DQ Delay:
7632 22:14:34.870721 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
7633 22:14:34.874334 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =139
7634 22:14:34.877603 DQ8 =119, DQ9 =115, DQ10 =127, DQ11 =123
7635 22:14:34.880799 DQ12 =135, DQ13 =131, DQ14 =135, DQ15 =131
7636 22:14:34.880880
7637 22:14:34.880943
7638 22:14:34.881002 ==
7639 22:14:34.883844 Dram Type= 6, Freq= 0, CH_0, rank 0
7640 22:14:34.890790 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7641 22:14:34.890871 ==
7642 22:14:34.890934
7643 22:14:34.890992
7644 22:14:34.891047 TX Vref Scan disable
7645 22:14:34.894084 == TX Byte 0 ==
7646 22:14:34.897214 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7647 22:14:34.903864 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7648 22:14:34.903943 == TX Byte 1 ==
7649 22:14:34.907102 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7650 22:14:34.913316 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7651 22:14:34.913397 ==
7652 22:14:34.916897 Dram Type= 6, Freq= 0, CH_0, rank 0
7653 22:14:34.920075 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7654 22:14:34.920156 ==
7655 22:14:34.933391
7656 22:14:34.936871 TX Vref early break, caculate TX vref
7657 22:14:34.939937 TX Vref=16, minBit 1, minWin=21, winSum=362
7658 22:14:34.943034 TX Vref=18, minBit 7, minWin=21, winSum=368
7659 22:14:34.946488 TX Vref=20, minBit 6, minWin=22, winSum=383
7660 22:14:34.949670 TX Vref=22, minBit 1, minWin=22, winSum=389
7661 22:14:34.953416 TX Vref=24, minBit 0, minWin=24, winSum=403
7662 22:14:34.959596 TX Vref=26, minBit 0, minWin=24, winSum=409
7663 22:14:34.963173 TX Vref=28, minBit 0, minWin=24, winSum=413
7664 22:14:34.966621 TX Vref=30, minBit 4, minWin=23, winSum=409
7665 22:14:34.969560 TX Vref=32, minBit 0, minWin=23, winSum=400
7666 22:14:34.973370 TX Vref=34, minBit 0, minWin=23, winSum=388
7667 22:14:34.979254 [TxChooseVref] Worse bit 0, Min win 24, Win sum 413, Final Vref 28
7668 22:14:34.979329
7669 22:14:34.982449 Final TX Range 0 Vref 28
7670 22:14:34.982521
7671 22:14:34.982583 ==
7672 22:14:34.986297 Dram Type= 6, Freq= 0, CH_0, rank 0
7673 22:14:34.989467 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7674 22:14:34.989541 ==
7675 22:14:34.989604
7676 22:14:34.992334
7677 22:14:34.992405 TX Vref Scan disable
7678 22:14:34.999066 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7679 22:14:34.999142 == TX Byte 0 ==
7680 22:14:35.002237 u2DelayCellOfst[0]=14 cells (4 PI)
7681 22:14:35.005956 u2DelayCellOfst[1]=14 cells (4 PI)
7682 22:14:35.009446 u2DelayCellOfst[2]=10 cells (3 PI)
7683 22:14:35.012130 u2DelayCellOfst[3]=10 cells (3 PI)
7684 22:14:35.015981 u2DelayCellOfst[4]=7 cells (2 PI)
7685 22:14:35.018725 u2DelayCellOfst[5]=0 cells (0 PI)
7686 22:14:35.022181 u2DelayCellOfst[6]=21 cells (6 PI)
7687 22:14:35.025552 u2DelayCellOfst[7]=17 cells (5 PI)
7688 22:14:35.028803 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7689 22:14:35.032265 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7690 22:14:35.035414 == TX Byte 1 ==
7691 22:14:35.038412 u2DelayCellOfst[8]=0 cells (0 PI)
7692 22:14:35.041659 u2DelayCellOfst[9]=0 cells (0 PI)
7693 22:14:35.045118 u2DelayCellOfst[10]=7 cells (2 PI)
7694 22:14:35.048574 u2DelayCellOfst[11]=3 cells (1 PI)
7695 22:14:35.048649 u2DelayCellOfst[12]=10 cells (3 PI)
7696 22:14:35.051869 u2DelayCellOfst[13]=10 cells (3 PI)
7697 22:14:35.055207 u2DelayCellOfst[14]=14 cells (4 PI)
7698 22:14:35.058755 u2DelayCellOfst[15]=10 cells (3 PI)
7699 22:14:35.064943 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7700 22:14:35.068188 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7701 22:14:35.071554 DramC Write-DBI on
7702 22:14:35.071628 ==
7703 22:14:35.075049 Dram Type= 6, Freq= 0, CH_0, rank 0
7704 22:14:35.077929 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7705 22:14:35.078003 ==
7706 22:14:35.078064
7707 22:14:35.078122
7708 22:14:35.081283 TX Vref Scan disable
7709 22:14:35.081370 == TX Byte 0 ==
7710 22:14:35.087764 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
7711 22:14:35.087838 == TX Byte 1 ==
7712 22:14:35.091253 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
7713 22:14:35.094630 DramC Write-DBI off
7714 22:14:35.094706
7715 22:14:35.094767 [DATLAT]
7716 22:14:35.097626 Freq=1600, CH0 RK0
7717 22:14:35.097695
7718 22:14:35.097754 DATLAT Default: 0xf
7719 22:14:35.101203 0, 0xFFFF, sum = 0
7720 22:14:35.104164 1, 0xFFFF, sum = 0
7721 22:14:35.104238 2, 0xFFFF, sum = 0
7722 22:14:35.107469 3, 0xFFFF, sum = 0
7723 22:14:35.107547 4, 0xFFFF, sum = 0
7724 22:14:35.110964 5, 0xFFFF, sum = 0
7725 22:14:35.111062 6, 0xFFFF, sum = 0
7726 22:14:35.114045 7, 0xFFFF, sum = 0
7727 22:14:35.114118 8, 0xFFFF, sum = 0
7728 22:14:35.117699 9, 0xFFFF, sum = 0
7729 22:14:35.117773 10, 0xFFFF, sum = 0
7730 22:14:35.120594 11, 0xFFFF, sum = 0
7731 22:14:35.120671 12, 0xFFFF, sum = 0
7732 22:14:35.123951 13, 0xFFFF, sum = 0
7733 22:14:35.124051 14, 0x0, sum = 1
7734 22:14:35.127127 15, 0x0, sum = 2
7735 22:14:35.127197 16, 0x0, sum = 3
7736 22:14:35.130550 17, 0x0, sum = 4
7737 22:14:35.130621 best_step = 15
7738 22:14:35.130680
7739 22:14:35.130739 ==
7740 22:14:35.133743 Dram Type= 6, Freq= 0, CH_0, rank 0
7741 22:14:35.140534 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7742 22:14:35.140618 ==
7743 22:14:35.140685 RX Vref Scan: 1
7744 22:14:35.140753
7745 22:14:35.143582 Set Vref Range= 24 -> 127
7746 22:14:35.143653
7747 22:14:35.146720 RX Vref 24 -> 127, step: 1
7748 22:14:35.146793
7749 22:14:35.150014 RX Delay 19 -> 252, step: 4
7750 22:14:35.150086
7751 22:14:35.153560 Set Vref, RX VrefLevel [Byte0]: 24
7752 22:14:35.156752 [Byte1]: 24
7753 22:14:35.156835
7754 22:14:35.160292 Set Vref, RX VrefLevel [Byte0]: 25
7755 22:14:35.163558 [Byte1]: 25
7756 22:14:35.163659
7757 22:14:35.166692 Set Vref, RX VrefLevel [Byte0]: 26
7758 22:14:35.170058 [Byte1]: 26
7759 22:14:35.170130
7760 22:14:35.173778 Set Vref, RX VrefLevel [Byte0]: 27
7761 22:14:35.176501 [Byte1]: 27
7762 22:14:35.180841
7763 22:14:35.180948 Set Vref, RX VrefLevel [Byte0]: 28
7764 22:14:35.183885 [Byte1]: 28
7765 22:14:35.188507
7766 22:14:35.188602 Set Vref, RX VrefLevel [Byte0]: 29
7767 22:14:35.191418 [Byte1]: 29
7768 22:14:35.195678
7769 22:14:35.195758 Set Vref, RX VrefLevel [Byte0]: 30
7770 22:14:35.199241 [Byte1]: 30
7771 22:14:35.203510
7772 22:14:35.203590 Set Vref, RX VrefLevel [Byte0]: 31
7773 22:14:35.206677 [Byte1]: 31
7774 22:14:35.210782
7775 22:14:35.210862 Set Vref, RX VrefLevel [Byte0]: 32
7776 22:14:35.214407 [Byte1]: 32
7777 22:14:35.218933
7778 22:14:35.219014 Set Vref, RX VrefLevel [Byte0]: 33
7779 22:14:35.221958 [Byte1]: 33
7780 22:14:35.226600
7781 22:14:35.226681 Set Vref, RX VrefLevel [Byte0]: 34
7782 22:14:35.229711 [Byte1]: 34
7783 22:14:35.233854
7784 22:14:35.233935 Set Vref, RX VrefLevel [Byte0]: 35
7785 22:14:35.237246 [Byte1]: 35
7786 22:14:35.241581
7787 22:14:35.241669 Set Vref, RX VrefLevel [Byte0]: 36
7788 22:14:35.244661 [Byte1]: 36
7789 22:14:35.248811
7790 22:14:35.248913 Set Vref, RX VrefLevel [Byte0]: 37
7791 22:14:35.251989 [Byte1]: 37
7792 22:14:35.256600
7793 22:14:35.256675 Set Vref, RX VrefLevel [Byte0]: 38
7794 22:14:35.259623 [Byte1]: 38
7795 22:14:35.263912
7796 22:14:35.263987 Set Vref, RX VrefLevel [Byte0]: 39
7797 22:14:35.267105 [Byte1]: 39
7798 22:14:35.271931
7799 22:14:35.272015 Set Vref, RX VrefLevel [Byte0]: 40
7800 22:14:35.275168 [Byte1]: 40
7801 22:14:35.279055
7802 22:14:35.279137 Set Vref, RX VrefLevel [Byte0]: 41
7803 22:14:35.282194 [Byte1]: 41
7804 22:14:35.286416
7805 22:14:35.286491 Set Vref, RX VrefLevel [Byte0]: 42
7806 22:14:35.289884 [Byte1]: 42
7807 22:14:35.294590
7808 22:14:35.294661 Set Vref, RX VrefLevel [Byte0]: 43
7809 22:14:35.297838 [Byte1]: 43
7810 22:14:35.301681
7811 22:14:35.301749 Set Vref, RX VrefLevel [Byte0]: 44
7812 22:14:35.305166 [Byte1]: 44
7813 22:14:35.309370
7814 22:14:35.309463 Set Vref, RX VrefLevel [Byte0]: 45
7815 22:14:35.312753 [Byte1]: 45
7816 22:14:35.317059
7817 22:14:35.317141 Set Vref, RX VrefLevel [Byte0]: 46
7818 22:14:35.320234 [Byte1]: 46
7819 22:14:35.324451
7820 22:14:35.324532 Set Vref, RX VrefLevel [Byte0]: 47
7821 22:14:35.327750 [Byte1]: 47
7822 22:14:35.332301
7823 22:14:35.332383 Set Vref, RX VrefLevel [Byte0]: 48
7824 22:14:35.335367 [Byte1]: 48
7825 22:14:35.339677
7826 22:14:35.339762 Set Vref, RX VrefLevel [Byte0]: 49
7827 22:14:35.342857 [Byte1]: 49
7828 22:14:35.347468
7829 22:14:35.347545 Set Vref, RX VrefLevel [Byte0]: 50
7830 22:14:35.350650 [Byte1]: 50
7831 22:14:35.354828
7832 22:14:35.354899 Set Vref, RX VrefLevel [Byte0]: 51
7833 22:14:35.358475 [Byte1]: 51
7834 22:14:35.362698
7835 22:14:35.362768 Set Vref, RX VrefLevel [Byte0]: 52
7836 22:14:35.365960 [Byte1]: 52
7837 22:14:35.370125
7838 22:14:35.370197 Set Vref, RX VrefLevel [Byte0]: 53
7839 22:14:35.373794 [Byte1]: 53
7840 22:14:35.377890
7841 22:14:35.377972 Set Vref, RX VrefLevel [Byte0]: 54
7842 22:14:35.380683 [Byte1]: 54
7843 22:14:35.385351
7844 22:14:35.385428 Set Vref, RX VrefLevel [Byte0]: 55
7845 22:14:35.388349 [Byte1]: 55
7846 22:14:35.392711
7847 22:14:35.392785 Set Vref, RX VrefLevel [Byte0]: 56
7848 22:14:35.396371 [Byte1]: 56
7849 22:14:35.400313
7850 22:14:35.400385 Set Vref, RX VrefLevel [Byte0]: 57
7851 22:14:35.403487 [Byte1]: 57
7852 22:14:35.407756
7853 22:14:35.407826 Set Vref, RX VrefLevel [Byte0]: 58
7854 22:14:35.411289 [Byte1]: 58
7855 22:14:35.415288
7856 22:14:35.415359 Set Vref, RX VrefLevel [Byte0]: 59
7857 22:14:35.419159 [Byte1]: 59
7858 22:14:35.423187
7859 22:14:35.423275 Set Vref, RX VrefLevel [Byte0]: 60
7860 22:14:35.426432 [Byte1]: 60
7861 22:14:35.430745
7862 22:14:35.430842 Set Vref, RX VrefLevel [Byte0]: 61
7863 22:14:35.433992 [Byte1]: 61
7864 22:14:35.437928
7865 22:14:35.438013 Set Vref, RX VrefLevel [Byte0]: 62
7866 22:14:35.441289 [Byte1]: 62
7867 22:14:35.445608
7868 22:14:35.445707 Set Vref, RX VrefLevel [Byte0]: 63
7869 22:14:35.448887 [Byte1]: 63
7870 22:14:35.453209
7871 22:14:35.453307 Set Vref, RX VrefLevel [Byte0]: 64
7872 22:14:35.456364 [Byte1]: 64
7873 22:14:35.460988
7874 22:14:35.461084 Set Vref, RX VrefLevel [Byte0]: 65
7875 22:14:35.464373 [Byte1]: 65
7876 22:14:35.468303
7877 22:14:35.468402 Set Vref, RX VrefLevel [Byte0]: 66
7878 22:14:35.471622 [Byte1]: 66
7879 22:14:35.475929
7880 22:14:35.476023 Set Vref, RX VrefLevel [Byte0]: 67
7881 22:14:35.479026 [Byte1]: 67
7882 22:14:35.483544
7883 22:14:35.483638 Set Vref, RX VrefLevel [Byte0]: 68
7884 22:14:35.486961 [Byte1]: 68
7885 22:14:35.490953
7886 22:14:35.491047 Set Vref, RX VrefLevel [Byte0]: 69
7887 22:14:35.494434 [Byte1]: 69
7888 22:14:35.498479
7889 22:14:35.498580 Set Vref, RX VrefLevel [Byte0]: 70
7890 22:14:35.501990 [Byte1]: 70
7891 22:14:35.506070
7892 22:14:35.506166 Set Vref, RX VrefLevel [Byte0]: 71
7893 22:14:35.509497 [Byte1]: 71
7894 22:14:35.513679
7895 22:14:35.513748 Final RX Vref Byte 0 = 63 to rank0
7896 22:14:35.517090 Final RX Vref Byte 1 = 55 to rank0
7897 22:14:35.520744 Final RX Vref Byte 0 = 63 to rank1
7898 22:14:35.524092 Final RX Vref Byte 1 = 55 to rank1==
7899 22:14:35.527094 Dram Type= 6, Freq= 0, CH_0, rank 0
7900 22:14:35.533489 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7901 22:14:35.533585 ==
7902 22:14:35.533681 DQS Delay:
7903 22:14:35.537105 DQS0 = 0, DQS1 = 0
7904 22:14:35.537198 DQM Delay:
7905 22:14:35.537268 DQM0 = 129, DQM1 = 124
7906 22:14:35.540055 DQ Delay:
7907 22:14:35.543426 DQ0 =132, DQ1 =130, DQ2 =126, DQ3 =124
7908 22:14:35.546679 DQ4 =132, DQ5 =120, DQ6 =138, DQ7 =136
7909 22:14:35.550276 DQ8 =112, DQ9 =110, DQ10 =126, DQ11 =120
7910 22:14:35.553163 DQ12 =130, DQ13 =130, DQ14 =134, DQ15 =132
7911 22:14:35.553243
7912 22:14:35.553330
7913 22:14:35.553415
7914 22:14:35.556720 [DramC_TX_OE_Calibration] TA2
7915 22:14:35.559921 Original DQ_B0 (3 6) =30, OEN = 27
7916 22:14:35.563307 Original DQ_B1 (3 6) =30, OEN = 27
7917 22:14:35.566647 24, 0x0, End_B0=24 End_B1=24
7918 22:14:35.569788 25, 0x0, End_B0=25 End_B1=25
7919 22:14:35.569858 26, 0x0, End_B0=26 End_B1=26
7920 22:14:35.573035 27, 0x0, End_B0=27 End_B1=27
7921 22:14:35.576311 28, 0x0, End_B0=28 End_B1=28
7922 22:14:35.579667 29, 0x0, End_B0=29 End_B1=29
7923 22:14:35.579765 30, 0x0, End_B0=30 End_B1=30
7924 22:14:35.582771 31, 0x4141, End_B0=30 End_B1=30
7925 22:14:35.586573 Byte0 end_step=30 best_step=27
7926 22:14:35.589429 Byte1 end_step=30 best_step=27
7927 22:14:35.592842 Byte0 TX OE(2T, 0.5T) = (3, 3)
7928 22:14:35.596340 Byte1 TX OE(2T, 0.5T) = (3, 3)
7929 22:14:35.596437
7930 22:14:35.596524
7931 22:14:35.602807 [DQSOSCAuto] RK0, (LSB)MR18= 0x1916, (MSB)MR19= 0x303, tDQSOscB0 = 398 ps tDQSOscB1 = 397 ps
7932 22:14:35.606269 CH0 RK0: MR19=303, MR18=1916
7933 22:14:35.612526 CH0_RK0: MR19=0x303, MR18=0x1916, DQSOSC=397, MR23=63, INC=23, DEC=15
7934 22:14:35.612612
7935 22:14:35.615855 ----->DramcWriteLeveling(PI) begin...
7936 22:14:35.615954 ==
7937 22:14:35.619025 Dram Type= 6, Freq= 0, CH_0, rank 1
7938 22:14:35.622647 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7939 22:14:35.622730 ==
7940 22:14:35.626075 Write leveling (Byte 0): 35 => 35
7941 22:14:35.629460 Write leveling (Byte 1): 27 => 27
7942 22:14:35.632418 DramcWriteLeveling(PI) end<-----
7943 22:14:35.632500
7944 22:14:35.632566 ==
7945 22:14:35.636037 Dram Type= 6, Freq= 0, CH_0, rank 1
7946 22:14:35.642570 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7947 22:14:35.642654 ==
7948 22:14:35.642719 [Gating] SW mode calibration
7949 22:14:35.652512 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7950 22:14:35.655643 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7951 22:14:35.658961 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7952 22:14:35.665662 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7953 22:14:35.668777 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
7954 22:14:35.675112 1 4 12 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
7955 22:14:35.678865 1 4 16 | B1->B0 | 2828 3434 | 1 1 | (0 0) (1 1)
7956 22:14:35.681855 1 4 20 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
7957 22:14:35.688186 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7958 22:14:35.691966 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7959 22:14:35.694842 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7960 22:14:35.701893 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7961 22:14:35.705124 1 5 8 | B1->B0 | 3434 2d2d | 1 1 | (1 1) (1 0)
7962 22:14:35.708132 1 5 12 | B1->B0 | 3434 2828 | 1 0 | (1 1) (1 1)
7963 22:14:35.714578 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
7964 22:14:35.717784 1 5 20 | B1->B0 | 2e2e 2323 | 0 0 | (0 1) (0 0)
7965 22:14:35.721378 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
7966 22:14:35.727660 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7967 22:14:35.730988 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7968 22:14:35.734322 1 6 4 | B1->B0 | 2323 2929 | 0 1 | (0 0) (0 0)
7969 22:14:35.741217 1 6 8 | B1->B0 | 2323 3e3e | 0 0 | (0 0) (0 0)
7970 22:14:35.744410 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7971 22:14:35.747440 1 6 16 | B1->B0 | 3030 4646 | 0 0 | (0 0) (0 0)
7972 22:14:35.754286 1 6 20 | B1->B0 | 4040 4646 | 0 0 | (1 1) (0 0)
7973 22:14:35.757317 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7974 22:14:35.760433 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7975 22:14:35.767108 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7976 22:14:35.770489 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7977 22:14:35.773585 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7978 22:14:35.780489 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7979 22:14:35.783723 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7980 22:14:35.786877 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7981 22:14:35.793766 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7982 22:14:35.797095 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7983 22:14:35.800361 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7984 22:14:35.807233 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7985 22:14:35.810053 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7986 22:14:35.813148 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7987 22:14:35.820412 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7988 22:14:35.823455 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7989 22:14:35.826516 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7990 22:14:35.833388 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7991 22:14:35.836601 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7992 22:14:35.839964 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7993 22:14:35.846470 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7994 22:14:35.849487 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7995 22:14:35.852927 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7996 22:14:35.856402 Total UI for P1: 0, mck2ui 16
7997 22:14:35.859637 best dqsien dly found for B0: ( 1, 9, 8)
7998 22:14:35.865900 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7999 22:14:35.869388 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8000 22:14:35.872460 Total UI for P1: 0, mck2ui 16
8001 22:14:35.875852 best dqsien dly found for B1: ( 1, 9, 18)
8002 22:14:35.879153 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8003 22:14:35.882937 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8004 22:14:35.883019
8005 22:14:35.886153 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8006 22:14:35.889643 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8007 22:14:35.892723 [Gating] SW calibration Done
8008 22:14:35.892805 ==
8009 22:14:35.895660 Dram Type= 6, Freq= 0, CH_0, rank 1
8010 22:14:35.899002 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8011 22:14:35.902402 ==
8012 22:14:35.902484 RX Vref Scan: 0
8013 22:14:35.902550
8014 22:14:35.905939 RX Vref 0 -> 0, step: 1
8015 22:14:35.906028
8016 22:14:35.908869 RX Delay 0 -> 252, step: 8
8017 22:14:35.912245 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
8018 22:14:35.915630 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8019 22:14:35.918711 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
8020 22:14:35.921941 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8021 22:14:35.928738 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8022 22:14:35.932024 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
8023 22:14:35.935288 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8024 22:14:35.938367 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8025 22:14:35.941542 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8026 22:14:35.948488 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8027 22:14:35.951442 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8028 22:14:35.955301 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8029 22:14:35.958304 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8030 22:14:35.965165 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8031 22:14:35.968166 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8032 22:14:35.971534 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8033 22:14:35.971617 ==
8034 22:14:35.974556 Dram Type= 6, Freq= 0, CH_0, rank 1
8035 22:14:35.977946 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8036 22:14:35.978029 ==
8037 22:14:35.981223 DQS Delay:
8038 22:14:35.981309 DQS0 = 0, DQS1 = 0
8039 22:14:35.984527 DQM Delay:
8040 22:14:35.984609 DQM0 = 133, DQM1 = 125
8041 22:14:35.987882 DQ Delay:
8042 22:14:35.991117 DQ0 =127, DQ1 =135, DQ2 =131, DQ3 =127
8043 22:14:35.994166 DQ4 =139, DQ5 =119, DQ6 =143, DQ7 =143
8044 22:14:35.997312 DQ8 =115, DQ9 =111, DQ10 =127, DQ11 =119
8045 22:14:36.001007 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =131
8046 22:14:36.001090
8047 22:14:36.001155
8048 22:14:36.001222 ==
8049 22:14:36.003986 Dram Type= 6, Freq= 0, CH_0, rank 1
8050 22:14:36.007096 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8051 22:14:36.007179 ==
8052 22:14:36.010612
8053 22:14:36.010694
8054 22:14:36.010759 TX Vref Scan disable
8055 22:14:36.013712 == TX Byte 0 ==
8056 22:14:36.017082 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
8057 22:14:36.020403 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8058 22:14:36.024449 == TX Byte 1 ==
8059 22:14:36.027295 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8060 22:14:36.030215 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8061 22:14:36.030298 ==
8062 22:14:36.033700 Dram Type= 6, Freq= 0, CH_0, rank 1
8063 22:14:36.040551 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8064 22:14:36.040635 ==
8065 22:14:36.054230
8066 22:14:36.057559 TX Vref early break, caculate TX vref
8067 22:14:36.060971 TX Vref=16, minBit 0, minWin=22, winSum=374
8068 22:14:36.064009 TX Vref=18, minBit 3, minWin=22, winSum=385
8069 22:14:36.067374 TX Vref=20, minBit 1, minWin=23, winSum=392
8070 22:14:36.070726 TX Vref=22, minBit 0, minWin=24, winSum=399
8071 22:14:36.074267 TX Vref=24, minBit 0, minWin=24, winSum=408
8072 22:14:36.080339 TX Vref=26, minBit 2, minWin=24, winSum=411
8073 22:14:36.084182 TX Vref=28, minBit 0, minWin=25, winSum=415
8074 22:14:36.087146 TX Vref=30, minBit 1, minWin=24, winSum=411
8075 22:14:36.090329 TX Vref=32, minBit 4, minWin=23, winSum=403
8076 22:14:36.093712 TX Vref=34, minBit 0, minWin=24, winSum=395
8077 22:14:36.100275 TX Vref=36, minBit 4, minWin=22, winSum=385
8078 22:14:36.103997 [TxChooseVref] Worse bit 0, Min win 25, Win sum 415, Final Vref 28
8079 22:14:36.104100
8080 22:14:36.107014 Final TX Range 0 Vref 28
8081 22:14:36.107100
8082 22:14:36.107167 ==
8083 22:14:36.110306 Dram Type= 6, Freq= 0, CH_0, rank 1
8084 22:14:36.113734 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8085 22:14:36.116761 ==
8086 22:14:36.116845
8087 22:14:36.116917
8088 22:14:36.116980 TX Vref Scan disable
8089 22:14:36.123925 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8090 22:14:36.124009 == TX Byte 0 ==
8091 22:14:36.126844 u2DelayCellOfst[0]=14 cells (4 PI)
8092 22:14:36.130417 u2DelayCellOfst[1]=17 cells (5 PI)
8093 22:14:36.133282 u2DelayCellOfst[2]=14 cells (4 PI)
8094 22:14:36.136573 u2DelayCellOfst[3]=14 cells (4 PI)
8095 22:14:36.140064 u2DelayCellOfst[4]=10 cells (3 PI)
8096 22:14:36.143081 u2DelayCellOfst[5]=0 cells (0 PI)
8097 22:14:36.146433 u2DelayCellOfst[6]=17 cells (5 PI)
8098 22:14:36.149925 u2DelayCellOfst[7]=17 cells (5 PI)
8099 22:14:36.153248 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8100 22:14:36.159609 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8101 22:14:36.159710 == TX Byte 1 ==
8102 22:14:36.162741 u2DelayCellOfst[8]=0 cells (0 PI)
8103 22:14:36.166267 u2DelayCellOfst[9]=0 cells (0 PI)
8104 22:14:36.169350 u2DelayCellOfst[10]=7 cells (2 PI)
8105 22:14:36.173146 u2DelayCellOfst[11]=3 cells (1 PI)
8106 22:14:36.175734 u2DelayCellOfst[12]=10 cells (3 PI)
8107 22:14:36.178989 u2DelayCellOfst[13]=10 cells (3 PI)
8108 22:14:36.182663 u2DelayCellOfst[14]=14 cells (4 PI)
8109 22:14:36.185656 u2DelayCellOfst[15]=10 cells (3 PI)
8110 22:14:36.189488 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8111 22:14:36.192588 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8112 22:14:36.195823 DramC Write-DBI on
8113 22:14:36.195906 ==
8114 22:14:36.199113 Dram Type= 6, Freq= 0, CH_0, rank 1
8115 22:14:36.202541 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8116 22:14:36.202624 ==
8117 22:14:36.202690
8118 22:14:36.202750
8119 22:14:36.205901 TX Vref Scan disable
8120 22:14:36.208783 == TX Byte 0 ==
8121 22:14:36.212250 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
8122 22:14:36.212333 == TX Byte 1 ==
8123 22:14:36.218803 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8124 22:14:36.218911 DramC Write-DBI off
8125 22:14:36.219004
8126 22:14:36.222119 [DATLAT]
8127 22:14:36.222201 Freq=1600, CH0 RK1
8128 22:14:36.222267
8129 22:14:36.225212 DATLAT Default: 0xf
8130 22:14:36.225300 0, 0xFFFF, sum = 0
8131 22:14:36.228301 1, 0xFFFF, sum = 0
8132 22:14:36.228411 2, 0xFFFF, sum = 0
8133 22:14:36.231785 3, 0xFFFF, sum = 0
8134 22:14:36.231874 4, 0xFFFF, sum = 0
8135 22:14:36.235139 5, 0xFFFF, sum = 0
8136 22:14:36.235223 6, 0xFFFF, sum = 0
8137 22:14:36.238578 7, 0xFFFF, sum = 0
8138 22:14:36.238661 8, 0xFFFF, sum = 0
8139 22:14:36.242141 9, 0xFFFF, sum = 0
8140 22:14:36.242240 10, 0xFFFF, sum = 0
8141 22:14:36.245286 11, 0xFFFF, sum = 0
8142 22:14:36.248382 12, 0xFFFF, sum = 0
8143 22:14:36.248465 13, 0xFFFF, sum = 0
8144 22:14:36.251619 14, 0x0, sum = 1
8145 22:14:36.251702 15, 0x0, sum = 2
8146 22:14:36.254885 16, 0x0, sum = 3
8147 22:14:36.254968 17, 0x0, sum = 4
8148 22:14:36.255034 best_step = 15
8149 22:14:36.255095
8150 22:14:36.258195 ==
8151 22:14:36.261513 Dram Type= 6, Freq= 0, CH_0, rank 1
8152 22:14:36.264753 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8153 22:14:36.264836 ==
8154 22:14:36.264902 RX Vref Scan: 0
8155 22:14:36.264965
8156 22:14:36.267789 RX Vref 0 -> 0, step: 1
8157 22:14:36.267871
8158 22:14:36.271299 RX Delay 11 -> 252, step: 4
8159 22:14:36.274446 iDelay=191, Bit 0, Center 126 (75 ~ 178) 104
8160 22:14:36.281000 iDelay=191, Bit 1, Center 130 (79 ~ 182) 104
8161 22:14:36.284504 iDelay=191, Bit 2, Center 124 (75 ~ 174) 100
8162 22:14:36.287873 iDelay=191, Bit 3, Center 128 (79 ~ 178) 100
8163 22:14:36.290922 iDelay=191, Bit 4, Center 130 (83 ~ 178) 96
8164 22:14:36.294262 iDelay=191, Bit 5, Center 120 (67 ~ 174) 108
8165 22:14:36.300914 iDelay=191, Bit 6, Center 138 (87 ~ 190) 104
8166 22:14:36.304395 iDelay=191, Bit 7, Center 136 (83 ~ 190) 108
8167 22:14:36.307229 iDelay=191, Bit 8, Center 114 (63 ~ 166) 104
8168 22:14:36.310860 iDelay=191, Bit 9, Center 110 (59 ~ 162) 104
8169 22:14:36.314366 iDelay=191, Bit 10, Center 126 (75 ~ 178) 104
8170 22:14:36.320566 iDelay=191, Bit 11, Center 120 (71 ~ 170) 100
8171 22:14:36.323773 iDelay=191, Bit 12, Center 128 (75 ~ 182) 108
8172 22:14:36.327017 iDelay=191, Bit 13, Center 128 (79 ~ 178) 100
8173 22:14:36.330589 iDelay=191, Bit 14, Center 136 (83 ~ 190) 108
8174 22:14:36.336902 iDelay=191, Bit 15, Center 130 (79 ~ 182) 104
8175 22:14:36.336992 ==
8176 22:14:36.340091 Dram Type= 6, Freq= 0, CH_0, rank 1
8177 22:14:36.343612 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8178 22:14:36.343694 ==
8179 22:14:36.343775 DQS Delay:
8180 22:14:36.347054 DQS0 = 0, DQS1 = 0
8181 22:14:36.347137 DQM Delay:
8182 22:14:36.350066 DQM0 = 129, DQM1 = 124
8183 22:14:36.350149 DQ Delay:
8184 22:14:36.353643 DQ0 =126, DQ1 =130, DQ2 =124, DQ3 =128
8185 22:14:36.356919 DQ4 =130, DQ5 =120, DQ6 =138, DQ7 =136
8186 22:14:36.359900 DQ8 =114, DQ9 =110, DQ10 =126, DQ11 =120
8187 22:14:36.363624 DQ12 =128, DQ13 =128, DQ14 =136, DQ15 =130
8188 22:14:36.363730
8189 22:14:36.363829
8190 22:14:36.366987
8191 22:14:36.367069 [DramC_TX_OE_Calibration] TA2
8192 22:14:36.369982 Original DQ_B0 (3 6) =30, OEN = 27
8193 22:14:36.373216 Original DQ_B1 (3 6) =30, OEN = 27
8194 22:14:36.376414 24, 0x0, End_B0=24 End_B1=24
8195 22:14:36.379642 25, 0x0, End_B0=25 End_B1=25
8196 22:14:36.382994 26, 0x0, End_B0=26 End_B1=26
8197 22:14:36.383077 27, 0x0, End_B0=27 End_B1=27
8198 22:14:36.386661 28, 0x0, End_B0=28 End_B1=28
8199 22:14:36.390003 29, 0x0, End_B0=29 End_B1=29
8200 22:14:36.393039 30, 0x0, End_B0=30 End_B1=30
8201 22:14:36.396179 31, 0x5151, End_B0=30 End_B1=30
8202 22:14:36.396277 Byte0 end_step=30 best_step=27
8203 22:14:36.399811 Byte1 end_step=30 best_step=27
8204 22:14:36.402828 Byte0 TX OE(2T, 0.5T) = (3, 3)
8205 22:14:36.406200 Byte1 TX OE(2T, 0.5T) = (3, 3)
8206 22:14:36.406309
8207 22:14:36.406423
8208 22:14:36.416316 [DQSOSCAuto] RK1, (LSB)MR18= 0x1312, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 400 ps
8209 22:14:36.416402 CH0 RK1: MR19=303, MR18=1312
8210 22:14:36.422788 CH0_RK1: MR19=0x303, MR18=0x1312, DQSOSC=400, MR23=63, INC=23, DEC=15
8211 22:14:36.425852 [RxdqsGatingPostProcess] freq 1600
8212 22:14:36.432550 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8213 22:14:36.435889 best DQS0 dly(2T, 0.5T) = (1, 1)
8214 22:14:36.439228 best DQS1 dly(2T, 0.5T) = (1, 1)
8215 22:14:36.442453 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8216 22:14:36.445842 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8217 22:14:36.445978 best DQS0 dly(2T, 0.5T) = (1, 1)
8218 22:14:36.448844 best DQS1 dly(2T, 0.5T) = (1, 1)
8219 22:14:36.452136 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8220 22:14:36.455838 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8221 22:14:36.458826 Pre-setting of DQS Precalculation
8222 22:14:36.465379 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8223 22:14:36.465463 ==
8224 22:14:36.468915 Dram Type= 6, Freq= 0, CH_1, rank 0
8225 22:14:36.472015 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8226 22:14:36.472112 ==
8227 22:14:36.478741 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8228 22:14:36.481940 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8229 22:14:36.485307 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8230 22:14:36.491712 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8231 22:14:36.500656 [CA 0] Center 41 (11~72) winsize 62
8232 22:14:36.504678 [CA 1] Center 42 (12~72) winsize 61
8233 22:14:36.507365 [CA 2] Center 38 (9~67) winsize 59
8234 22:14:36.510944 [CA 3] Center 37 (8~66) winsize 59
8235 22:14:36.514361 [CA 4] Center 37 (7~68) winsize 62
8236 22:14:36.517535 [CA 5] Center 36 (7~66) winsize 60
8237 22:14:36.517604
8238 22:14:36.520808 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8239 22:14:36.520879
8240 22:14:36.523826 [CATrainingPosCal] consider 1 rank data
8241 22:14:36.527026 u2DelayCellTimex100 = 275/100 ps
8242 22:14:36.533986 CA0 delay=41 (11~72),Diff = 5 PI (17 cell)
8243 22:14:36.537147 CA1 delay=42 (12~72),Diff = 6 PI (21 cell)
8244 22:14:36.540528 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8245 22:14:36.543816 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8246 22:14:36.547056 CA4 delay=37 (7~68),Diff = 1 PI (3 cell)
8247 22:14:36.550370 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8248 22:14:36.550470
8249 22:14:36.553354 CA PerBit enable=1, Macro0, CA PI delay=36
8250 22:14:36.553454
8251 22:14:36.556650 [CBTSetCACLKResult] CA Dly = 36
8252 22:14:36.560037 CS Dly: 8 (0~39)
8253 22:14:36.563180 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8254 22:14:36.566611 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8255 22:14:36.566681 ==
8256 22:14:36.569800 Dram Type= 6, Freq= 0, CH_1, rank 1
8257 22:14:36.576527 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8258 22:14:36.576599 ==
8259 22:14:36.580254 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8260 22:14:36.586313 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8261 22:14:36.590078 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8262 22:14:36.595986 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8263 22:14:36.603689 [CA 0] Center 42 (12~72) winsize 61
8264 22:14:36.607380 [CA 1] Center 42 (13~72) winsize 60
8265 22:14:36.610528 [CA 2] Center 38 (9~68) winsize 60
8266 22:14:36.613819 [CA 3] Center 37 (8~67) winsize 60
8267 22:14:36.617115 [CA 4] Center 37 (8~67) winsize 60
8268 22:14:36.620395 [CA 5] Center 37 (7~67) winsize 61
8269 22:14:36.620476
8270 22:14:36.623597 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8271 22:14:36.623693
8272 22:14:36.627449 [CATrainingPosCal] consider 2 rank data
8273 22:14:36.630096 u2DelayCellTimex100 = 275/100 ps
8274 22:14:36.637022 CA0 delay=42 (12~72),Diff = 6 PI (21 cell)
8275 22:14:36.640074 CA1 delay=42 (13~72),Diff = 6 PI (21 cell)
8276 22:14:36.643547 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8277 22:14:36.647208 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8278 22:14:36.649986 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8279 22:14:36.653181 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8280 22:14:36.653261
8281 22:14:36.657074 CA PerBit enable=1, Macro0, CA PI delay=36
8282 22:14:36.657150
8283 22:14:36.660020 [CBTSetCACLKResult] CA Dly = 36
8284 22:14:36.663070 CS Dly: 9 (0~42)
8285 22:14:36.666335 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8286 22:14:36.669840 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8287 22:14:36.669921
8288 22:14:36.672867 ----->DramcWriteLeveling(PI) begin...
8289 22:14:36.672949 ==
8290 22:14:36.676385 Dram Type= 6, Freq= 0, CH_1, rank 0
8291 22:14:36.682942 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8292 22:14:36.683023 ==
8293 22:14:36.686405 Write leveling (Byte 0): 22 => 22
8294 22:14:36.689665 Write leveling (Byte 1): 27 => 27
8295 22:14:36.692694 DramcWriteLeveling(PI) end<-----
8296 22:14:36.692773
8297 22:14:36.692834 ==
8298 22:14:36.696037 Dram Type= 6, Freq= 0, CH_1, rank 0
8299 22:14:36.699018 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8300 22:14:36.699098 ==
8301 22:14:36.702333 [Gating] SW mode calibration
8302 22:14:36.709527 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8303 22:14:36.715552 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8304 22:14:36.719159 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8305 22:14:36.722313 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8306 22:14:36.728655 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8307 22:14:36.731851 1 4 12 | B1->B0 | 2323 3232 | 0 1 | (0 0) (1 1)
8308 22:14:36.735619 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8309 22:14:36.741688 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8310 22:14:36.745129 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8311 22:14:36.748372 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8312 22:14:36.754793 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8313 22:14:36.758311 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8314 22:14:36.761584 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8315 22:14:36.768213 1 5 12 | B1->B0 | 2c2c 2323 | 0 0 | (0 1) (1 0)
8316 22:14:36.771473 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8317 22:14:36.774855 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8318 22:14:36.781504 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8319 22:14:36.784784 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8320 22:14:36.787997 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8321 22:14:36.794676 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8322 22:14:36.797875 1 6 8 | B1->B0 | 2323 3332 | 0 1 | (0 0) (0 0)
8323 22:14:36.801409 1 6 12 | B1->B0 | 3130 4646 | 1 0 | (0 0) (0 0)
8324 22:14:36.808332 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8325 22:14:36.811780 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8326 22:14:36.814524 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8327 22:14:36.821442 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8328 22:14:36.824715 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8329 22:14:36.827523 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8330 22:14:36.833898 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8331 22:14:36.837419 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8332 22:14:36.840630 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8333 22:14:36.847299 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8334 22:14:36.850494 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8335 22:14:36.853785 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8336 22:14:36.860297 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8337 22:14:36.863749 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8338 22:14:36.867212 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8339 22:14:36.873734 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8340 22:14:36.876736 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8341 22:14:36.879916 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8342 22:14:36.886723 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8343 22:14:36.890052 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8344 22:14:36.893320 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8345 22:14:36.899984 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8346 22:14:36.903000 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8347 22:14:36.906347 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8348 22:14:36.913013 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8349 22:14:36.913095 Total UI for P1: 0, mck2ui 16
8350 22:14:36.919457 best dqsien dly found for B0: ( 1, 9, 10)
8351 22:14:36.922666 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8352 22:14:36.926139 Total UI for P1: 0, mck2ui 16
8353 22:14:36.929488 best dqsien dly found for B1: ( 1, 9, 14)
8354 22:14:36.932665 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8355 22:14:36.935897 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8356 22:14:36.935978
8357 22:14:36.939625 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8358 22:14:36.942427 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8359 22:14:36.946053 [Gating] SW calibration Done
8360 22:14:36.946134 ==
8361 22:14:36.949141 Dram Type= 6, Freq= 0, CH_1, rank 0
8362 22:14:36.956009 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8363 22:14:36.956114 ==
8364 22:14:36.956179 RX Vref Scan: 0
8365 22:14:36.956240
8366 22:14:36.959337 RX Vref 0 -> 0, step: 1
8367 22:14:36.959418
8368 22:14:36.962265 RX Delay 0 -> 252, step: 8
8369 22:14:36.965578 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8370 22:14:36.969134 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8371 22:14:36.972083 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
8372 22:14:36.979699 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8373 22:14:36.982005 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8374 22:14:36.985552 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8375 22:14:36.988811 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8376 22:14:36.991757 iDelay=200, Bit 7, Center 131 (80 ~ 183) 104
8377 22:14:36.998810 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8378 22:14:37.001792 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8379 22:14:37.004840 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8380 22:14:37.008187 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8381 22:14:37.011392 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8382 22:14:37.018081 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8383 22:14:37.021755 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8384 22:14:37.025111 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8385 22:14:37.025193 ==
8386 22:14:37.028099 Dram Type= 6, Freq= 0, CH_1, rank 0
8387 22:14:37.031374 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8388 22:14:37.034981 ==
8389 22:14:37.035062 DQS Delay:
8390 22:14:37.035127 DQS0 = 0, DQS1 = 0
8391 22:14:37.037928 DQM Delay:
8392 22:14:37.038009 DQM0 = 134, DQM1 = 131
8393 22:14:37.041578 DQ Delay:
8394 22:14:37.044918 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8395 22:14:37.048166 DQ4 =131, DQ5 =143, DQ6 =143, DQ7 =131
8396 22:14:37.051088 DQ8 =115, DQ9 =119, DQ10 =131, DQ11 =127
8397 22:14:37.054629 DQ12 =139, DQ13 =143, DQ14 =139, DQ15 =139
8398 22:14:37.054710
8399 22:14:37.054775
8400 22:14:37.054834 ==
8401 22:14:37.057512 Dram Type= 6, Freq= 0, CH_1, rank 0
8402 22:14:37.061017 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8403 22:14:37.064259 ==
8404 22:14:37.064340
8405 22:14:37.064404
8406 22:14:37.064465 TX Vref Scan disable
8407 22:14:37.067512 == TX Byte 0 ==
8408 22:14:37.070872 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8409 22:14:37.074375 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
8410 22:14:37.077355 == TX Byte 1 ==
8411 22:14:37.080770 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8412 22:14:37.084409 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8413 22:14:37.087423 ==
8414 22:14:37.087504 Dram Type= 6, Freq= 0, CH_1, rank 0
8415 22:14:37.094041 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8416 22:14:37.094124 ==
8417 22:14:37.106349
8418 22:14:37.109662 TX Vref early break, caculate TX vref
8419 22:14:37.113281 TX Vref=16, minBit 8, minWin=21, winSum=367
8420 22:14:37.116555 TX Vref=18, minBit 9, minWin=21, winSum=379
8421 22:14:37.119474 TX Vref=20, minBit 8, minWin=23, winSum=387
8422 22:14:37.122836 TX Vref=22, minBit 9, minWin=23, winSum=393
8423 22:14:37.126136 TX Vref=24, minBit 9, minWin=24, winSum=407
8424 22:14:37.132553 TX Vref=26, minBit 8, minWin=25, winSum=413
8425 22:14:37.136329 TX Vref=28, minBit 0, minWin=25, winSum=420
8426 22:14:37.139124 TX Vref=30, minBit 0, minWin=25, winSum=412
8427 22:14:37.142708 TX Vref=32, minBit 9, minWin=23, winSum=403
8428 22:14:37.145798 TX Vref=34, minBit 0, minWin=24, winSum=396
8429 22:14:37.152575 [TxChooseVref] Worse bit 0, Min win 25, Win sum 420, Final Vref 28
8430 22:14:37.152682
8431 22:14:37.155620 Final TX Range 0 Vref 28
8432 22:14:37.155701
8433 22:14:37.155766 ==
8434 22:14:37.159044 Dram Type= 6, Freq= 0, CH_1, rank 0
8435 22:14:37.162132 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8436 22:14:37.162213 ==
8437 22:14:37.162278
8438 22:14:37.162338
8439 22:14:37.165477 TX Vref Scan disable
8440 22:14:37.171882 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8441 22:14:37.171964 == TX Byte 0 ==
8442 22:14:37.175540 u2DelayCellOfst[0]=14 cells (4 PI)
8443 22:14:37.178663 u2DelayCellOfst[1]=10 cells (3 PI)
8444 22:14:37.182233 u2DelayCellOfst[2]=0 cells (0 PI)
8445 22:14:37.185299 u2DelayCellOfst[3]=10 cells (3 PI)
8446 22:14:37.188429 u2DelayCellOfst[4]=10 cells (3 PI)
8447 22:14:37.191979 u2DelayCellOfst[5]=17 cells (5 PI)
8448 22:14:37.195056 u2DelayCellOfst[6]=14 cells (4 PI)
8449 22:14:37.198565 u2DelayCellOfst[7]=7 cells (2 PI)
8450 22:14:37.201826 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8451 22:14:37.204790 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
8452 22:14:37.208181 == TX Byte 1 ==
8453 22:14:37.211460 u2DelayCellOfst[8]=0 cells (0 PI)
8454 22:14:37.215343 u2DelayCellOfst[9]=0 cells (0 PI)
8455 22:14:37.218257 u2DelayCellOfst[10]=10 cells (3 PI)
8456 22:14:37.221513 u2DelayCellOfst[11]=3 cells (1 PI)
8457 22:14:37.224752 u2DelayCellOfst[12]=10 cells (3 PI)
8458 22:14:37.224833 u2DelayCellOfst[13]=14 cells (4 PI)
8459 22:14:37.228174 u2DelayCellOfst[14]=14 cells (4 PI)
8460 22:14:37.231511 u2DelayCellOfst[15]=14 cells (4 PI)
8461 22:14:37.238269 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8462 22:14:37.241093 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8463 22:14:37.241175 DramC Write-DBI on
8464 22:14:37.244710 ==
8465 22:14:37.247664 Dram Type= 6, Freq= 0, CH_1, rank 0
8466 22:14:37.251258 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8467 22:14:37.251341 ==
8468 22:14:37.251406
8469 22:14:37.251477
8470 22:14:37.254607 TX Vref Scan disable
8471 22:14:37.254697 == TX Byte 0 ==
8472 22:14:37.260977 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8473 22:14:37.261060 == TX Byte 1 ==
8474 22:14:37.264332 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8475 22:14:37.267428 DramC Write-DBI off
8476 22:14:37.267511
8477 22:14:37.267575 [DATLAT]
8478 22:14:37.270575 Freq=1600, CH1 RK0
8479 22:14:37.270667
8480 22:14:37.270749 DATLAT Default: 0xf
8481 22:14:37.273887 0, 0xFFFF, sum = 0
8482 22:14:37.273968 1, 0xFFFF, sum = 0
8483 22:14:37.277168 2, 0xFFFF, sum = 0
8484 22:14:37.280775 3, 0xFFFF, sum = 0
8485 22:14:37.280851 4, 0xFFFF, sum = 0
8486 22:14:37.283722 5, 0xFFFF, sum = 0
8487 22:14:37.283833 6, 0xFFFF, sum = 0
8488 22:14:37.287195 7, 0xFFFF, sum = 0
8489 22:14:37.287270 8, 0xFFFF, sum = 0
8490 22:14:37.290631 9, 0xFFFF, sum = 0
8491 22:14:37.290705 10, 0xFFFF, sum = 0
8492 22:14:37.293676 11, 0xFFFF, sum = 0
8493 22:14:37.293753 12, 0xFFFF, sum = 0
8494 22:14:37.297103 13, 0xFFFF, sum = 0
8495 22:14:37.297177 14, 0x0, sum = 1
8496 22:14:37.300435 15, 0x0, sum = 2
8497 22:14:37.300511 16, 0x0, sum = 3
8498 22:14:37.304165 17, 0x0, sum = 4
8499 22:14:37.304246 best_step = 15
8500 22:14:37.304326
8501 22:14:37.304403 ==
8502 22:14:37.307248 Dram Type= 6, Freq= 0, CH_1, rank 0
8503 22:14:37.313799 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8504 22:14:37.313904 ==
8505 22:14:37.313983 RX Vref Scan: 1
8506 22:14:37.314045
8507 22:14:37.316776 Set Vref Range= 24 -> 127
8508 22:14:37.316847
8509 22:14:37.320075 RX Vref 24 -> 127, step: 1
8510 22:14:37.320146
8511 22:14:37.320207 RX Delay 19 -> 252, step: 4
8512 22:14:37.323371
8513 22:14:37.323445 Set Vref, RX VrefLevel [Byte0]: 24
8514 22:14:37.326786 [Byte1]: 24
8515 22:14:37.331093
8516 22:14:37.331162 Set Vref, RX VrefLevel [Byte0]: 25
8517 22:14:37.334080 [Byte1]: 25
8518 22:14:37.338727
8519 22:14:37.338804 Set Vref, RX VrefLevel [Byte0]: 26
8520 22:14:37.341724 [Byte1]: 26
8521 22:14:37.346312
8522 22:14:37.346384 Set Vref, RX VrefLevel [Byte0]: 27
8523 22:14:37.349409 [Byte1]: 27
8524 22:14:37.353786
8525 22:14:37.353858 Set Vref, RX VrefLevel [Byte0]: 28
8526 22:14:37.357033 [Byte1]: 28
8527 22:14:37.361273
8528 22:14:37.361345 Set Vref, RX VrefLevel [Byte0]: 29
8529 22:14:37.368013 [Byte1]: 29
8530 22:14:37.368117
8531 22:14:37.370735 Set Vref, RX VrefLevel [Byte0]: 30
8532 22:14:37.374636 [Byte1]: 30
8533 22:14:37.374719
8534 22:14:37.377657 Set Vref, RX VrefLevel [Byte0]: 31
8535 22:14:37.381144 [Byte1]: 31
8536 22:14:37.381215
8537 22:14:37.384308 Set Vref, RX VrefLevel [Byte0]: 32
8538 22:14:37.387320 [Byte1]: 32
8539 22:14:37.391646
8540 22:14:37.391720 Set Vref, RX VrefLevel [Byte0]: 33
8541 22:14:37.394720 [Byte1]: 33
8542 22:14:37.399361
8543 22:14:37.399436 Set Vref, RX VrefLevel [Byte0]: 34
8544 22:14:37.402589 [Byte1]: 34
8545 22:14:37.406940
8546 22:14:37.407013 Set Vref, RX VrefLevel [Byte0]: 35
8547 22:14:37.409961 [Byte1]: 35
8548 22:14:37.414273
8549 22:14:37.414345 Set Vref, RX VrefLevel [Byte0]: 36
8550 22:14:37.417359 [Byte1]: 36
8551 22:14:37.421644
8552 22:14:37.421721 Set Vref, RX VrefLevel [Byte0]: 37
8553 22:14:37.425112 [Byte1]: 37
8554 22:14:37.429632
8555 22:14:37.429699 Set Vref, RX VrefLevel [Byte0]: 38
8556 22:14:37.432833 [Byte1]: 38
8557 22:14:37.437248
8558 22:14:37.437321 Set Vref, RX VrefLevel [Byte0]: 39
8559 22:14:37.440184 [Byte1]: 39
8560 22:14:37.444520
8561 22:14:37.444594 Set Vref, RX VrefLevel [Byte0]: 40
8562 22:14:37.447869 [Byte1]: 40
8563 22:14:37.452206
8564 22:14:37.452280 Set Vref, RX VrefLevel [Byte0]: 41
8565 22:14:37.455326 [Byte1]: 41
8566 22:14:37.459660
8567 22:14:37.459730 Set Vref, RX VrefLevel [Byte0]: 42
8568 22:14:37.462783 [Byte1]: 42
8569 22:14:37.467492
8570 22:14:37.467563 Set Vref, RX VrefLevel [Byte0]: 43
8571 22:14:37.470497 [Byte1]: 43
8572 22:14:37.474800
8573 22:14:37.474876 Set Vref, RX VrefLevel [Byte0]: 44
8574 22:14:37.478309 [Byte1]: 44
8575 22:14:37.482559
8576 22:14:37.482629 Set Vref, RX VrefLevel [Byte0]: 45
8577 22:14:37.485634 [Byte1]: 45
8578 22:14:37.490139
8579 22:14:37.490212 Set Vref, RX VrefLevel [Byte0]: 46
8580 22:14:37.493344 [Byte1]: 46
8581 22:14:37.497301
8582 22:14:37.497391 Set Vref, RX VrefLevel [Byte0]: 47
8583 22:14:37.500981 [Byte1]: 47
8584 22:14:37.504990
8585 22:14:37.505072 Set Vref, RX VrefLevel [Byte0]: 48
8586 22:14:37.508756 [Byte1]: 48
8587 22:14:37.512926
8588 22:14:37.513007 Set Vref, RX VrefLevel [Byte0]: 49
8589 22:14:37.515940 [Byte1]: 49
8590 22:14:37.520343
8591 22:14:37.520423 Set Vref, RX VrefLevel [Byte0]: 50
8592 22:14:37.523668 [Byte1]: 50
8593 22:14:37.527612
8594 22:14:37.527691 Set Vref, RX VrefLevel [Byte0]: 51
8595 22:14:37.530995 [Byte1]: 51
8596 22:14:37.535294
8597 22:14:37.535374 Set Vref, RX VrefLevel [Byte0]: 52
8598 22:14:37.538964 [Byte1]: 52
8599 22:14:37.542717
8600 22:14:37.542828 Set Vref, RX VrefLevel [Byte0]: 53
8601 22:14:37.546208 [Byte1]: 53
8602 22:14:37.550499
8603 22:14:37.550580 Set Vref, RX VrefLevel [Byte0]: 54
8604 22:14:37.553606 [Byte1]: 54
8605 22:14:37.557833
8606 22:14:37.557915 Set Vref, RX VrefLevel [Byte0]: 55
8607 22:14:37.561203 [Byte1]: 55
8608 22:14:37.565865
8609 22:14:37.565948 Set Vref, RX VrefLevel [Byte0]: 56
8610 22:14:37.568748 [Byte1]: 56
8611 22:14:37.573337
8612 22:14:37.573418 Set Vref, RX VrefLevel [Byte0]: 57
8613 22:14:37.576417 [Byte1]: 57
8614 22:14:37.581145
8615 22:14:37.581227 Set Vref, RX VrefLevel [Byte0]: 58
8616 22:14:37.584408 [Byte1]: 58
8617 22:14:37.588442
8618 22:14:37.588523 Set Vref, RX VrefLevel [Byte0]: 59
8619 22:14:37.591611 [Byte1]: 59
8620 22:14:37.596307
8621 22:14:37.596390 Set Vref, RX VrefLevel [Byte0]: 60
8622 22:14:37.599163 [Byte1]: 60
8623 22:14:37.603203
8624 22:14:37.603284 Set Vref, RX VrefLevel [Byte0]: 61
8625 22:14:37.607126 [Byte1]: 61
8626 22:14:37.611077
8627 22:14:37.611158 Set Vref, RX VrefLevel [Byte0]: 62
8628 22:14:37.614379 [Byte1]: 62
8629 22:14:37.619134
8630 22:14:37.619215 Set Vref, RX VrefLevel [Byte0]: 63
8631 22:14:37.621770 [Byte1]: 63
8632 22:14:37.626132
8633 22:14:37.626214 Set Vref, RX VrefLevel [Byte0]: 64
8634 22:14:37.629299 [Byte1]: 64
8635 22:14:37.633980
8636 22:14:37.634062 Set Vref, RX VrefLevel [Byte0]: 65
8637 22:14:37.637173 [Byte1]: 65
8638 22:14:37.641711
8639 22:14:37.641793 Set Vref, RX VrefLevel [Byte0]: 66
8640 22:14:37.644935 [Byte1]: 66
8641 22:14:37.649011
8642 22:14:37.649092 Set Vref, RX VrefLevel [Byte0]: 67
8643 22:14:37.651982 [Byte1]: 67
8644 22:14:37.656656
8645 22:14:37.656738 Set Vref, RX VrefLevel [Byte0]: 68
8646 22:14:37.660100 [Byte1]: 68
8647 22:14:37.664621
8648 22:14:37.664702 Set Vref, RX VrefLevel [Byte0]: 69
8649 22:14:37.667584 [Byte1]: 69
8650 22:14:37.671796
8651 22:14:37.671878 Set Vref, RX VrefLevel [Byte0]: 70
8652 22:14:37.674803 [Byte1]: 70
8653 22:14:37.679401
8654 22:14:37.679482 Final RX Vref Byte 0 = 58 to rank0
8655 22:14:37.682696 Final RX Vref Byte 1 = 56 to rank0
8656 22:14:37.686015 Final RX Vref Byte 0 = 58 to rank1
8657 22:14:37.689102 Final RX Vref Byte 1 = 56 to rank1==
8658 22:14:37.692377 Dram Type= 6, Freq= 0, CH_1, rank 0
8659 22:14:37.698883 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8660 22:14:37.698966 ==
8661 22:14:37.699032 DQS Delay:
8662 22:14:37.702035 DQS0 = 0, DQS1 = 0
8663 22:14:37.702116 DQM Delay:
8664 22:14:37.702191 DQM0 = 133, DQM1 = 129
8665 22:14:37.705359 DQ Delay:
8666 22:14:37.708613 DQ0 =142, DQ1 =130, DQ2 =118, DQ3 =132
8667 22:14:37.712020 DQ4 =128, DQ5 =142, DQ6 =144, DQ7 =130
8668 22:14:37.715264 DQ8 =112, DQ9 =118, DQ10 =130, DQ11 =122
8669 22:14:37.718417 DQ12 =140, DQ13 =138, DQ14 =136, DQ15 =138
8670 22:14:37.718499
8671 22:14:37.718572
8672 22:14:37.718632
8673 22:14:37.722211 [DramC_TX_OE_Calibration] TA2
8674 22:14:37.724982 Original DQ_B0 (3 6) =30, OEN = 27
8675 22:14:37.728456 Original DQ_B1 (3 6) =30, OEN = 27
8676 22:14:37.731617 24, 0x0, End_B0=24 End_B1=24
8677 22:14:37.735455 25, 0x0, End_B0=25 End_B1=25
8678 22:14:37.735538 26, 0x0, End_B0=26 End_B1=26
8679 22:14:37.738356 27, 0x0, End_B0=27 End_B1=27
8680 22:14:37.741607 28, 0x0, End_B0=28 End_B1=28
8681 22:14:37.744989 29, 0x0, End_B0=29 End_B1=29
8682 22:14:37.748308 30, 0x0, End_B0=30 End_B1=30
8683 22:14:37.748384 31, 0x4545, End_B0=30 End_B1=30
8684 22:14:37.751209 Byte0 end_step=30 best_step=27
8685 22:14:37.754731 Byte1 end_step=30 best_step=27
8686 22:14:37.758332 Byte0 TX OE(2T, 0.5T) = (3, 3)
8687 22:14:37.761444 Byte1 TX OE(2T, 0.5T) = (3, 3)
8688 22:14:37.761519
8689 22:14:37.761583
8690 22:14:37.768086 [DQSOSCAuto] RK0, (LSB)MR18= 0xe18, (MSB)MR19= 0x303, tDQSOscB0 = 397 ps tDQSOscB1 = 402 ps
8691 22:14:37.771140 CH1 RK0: MR19=303, MR18=E18
8692 22:14:37.778128 CH1_RK0: MR19=0x303, MR18=0xE18, DQSOSC=397, MR23=63, INC=23, DEC=15
8693 22:14:37.778230
8694 22:14:37.781047 ----->DramcWriteLeveling(PI) begin...
8695 22:14:37.781133 ==
8696 22:14:37.784305 Dram Type= 6, Freq= 0, CH_1, rank 1
8697 22:14:37.787515 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8698 22:14:37.787598 ==
8699 22:14:37.791366 Write leveling (Byte 0): 23 => 23
8700 22:14:37.794090 Write leveling (Byte 1): 26 => 26
8701 22:14:37.797716 DramcWriteLeveling(PI) end<-----
8702 22:14:37.797828
8703 22:14:37.797924 ==
8704 22:14:37.800597 Dram Type= 6, Freq= 0, CH_1, rank 1
8705 22:14:37.807282 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8706 22:14:37.807364 ==
8707 22:14:37.807428 [Gating] SW mode calibration
8708 22:14:37.817401 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8709 22:14:37.820387 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8710 22:14:37.827004 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8711 22:14:37.830457 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8712 22:14:37.833604 1 4 8 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
8713 22:14:37.840143 1 4 12 | B1->B0 | 2524 3434 | 1 1 | (0 0) (1 1)
8714 22:14:37.843508 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8715 22:14:37.846885 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8716 22:14:37.853482 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8717 22:14:37.856593 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8718 22:14:37.859788 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8719 22:14:37.866283 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8720 22:14:37.869908 1 5 8 | B1->B0 | 3434 2828 | 1 0 | (1 1) (0 0)
8721 22:14:37.873094 1 5 12 | B1->B0 | 3434 2323 | 0 0 | (0 0) (0 0)
8722 22:14:37.879746 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8723 22:14:37.882772 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8724 22:14:37.886112 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8725 22:14:37.893224 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8726 22:14:37.896506 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8727 22:14:37.899699 1 6 4 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
8728 22:14:37.906105 1 6 8 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8729 22:14:37.909269 1 6 12 | B1->B0 | 2d2d 4646 | 0 0 | (0 0) (0 0)
8730 22:14:37.912629 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8731 22:14:37.918988 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8732 22:14:37.922753 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8733 22:14:37.925786 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8734 22:14:37.932932 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8735 22:14:37.935603 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8736 22:14:37.939376 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8737 22:14:37.945371 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8738 22:14:37.949006 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8739 22:14:37.952012 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8740 22:14:37.958742 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8741 22:14:37.962013 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8742 22:14:37.965517 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8743 22:14:37.972356 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8744 22:14:37.975095 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8745 22:14:37.978296 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8746 22:14:37.984819 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8747 22:14:37.988731 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8748 22:14:37.991459 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8749 22:14:37.998267 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8750 22:14:38.001300 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8751 22:14:38.004626 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8752 22:14:38.011319 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8753 22:14:38.014672 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8754 22:14:38.017915 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8755 22:14:38.021514 Total UI for P1: 0, mck2ui 16
8756 22:14:38.024675 best dqsien dly found for B0: ( 1, 9, 8)
8757 22:14:38.027667 Total UI for P1: 0, mck2ui 16
8758 22:14:38.031288 best dqsien dly found for B1: ( 1, 9, 12)
8759 22:14:38.034324 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8760 22:14:38.037662 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8761 22:14:38.037743
8762 22:14:38.044053 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8763 22:14:38.047472 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8764 22:14:38.047553 [Gating] SW calibration Done
8765 22:14:38.050649 ==
8766 22:14:38.054313 Dram Type= 6, Freq= 0, CH_1, rank 1
8767 22:14:38.057466 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8768 22:14:38.057547 ==
8769 22:14:38.057612 RX Vref Scan: 0
8770 22:14:38.057670
8771 22:14:38.060720 RX Vref 0 -> 0, step: 1
8772 22:14:38.060800
8773 22:14:38.064272 RX Delay 0 -> 252, step: 8
8774 22:14:38.067272 iDelay=200, Bit 0, Center 143 (88 ~ 199) 112
8775 22:14:38.070594 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8776 22:14:38.073919 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8777 22:14:38.080695 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8778 22:14:38.083565 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8779 22:14:38.087480 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8780 22:14:38.090612 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8781 22:14:38.096678 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8782 22:14:38.100169 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8783 22:14:38.103788 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8784 22:14:38.106796 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8785 22:14:38.110417 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8786 22:14:38.116769 iDelay=200, Bit 12, Center 139 (80 ~ 199) 120
8787 22:14:38.119942 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8788 22:14:38.123701 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8789 22:14:38.126662 iDelay=200, Bit 15, Center 143 (88 ~ 199) 112
8790 22:14:38.126743 ==
8791 22:14:38.129834 Dram Type= 6, Freq= 0, CH_1, rank 1
8792 22:14:38.136677 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8793 22:14:38.136759 ==
8794 22:14:38.136824 DQS Delay:
8795 22:14:38.140009 DQS0 = 0, DQS1 = 0
8796 22:14:38.140147 DQM Delay:
8797 22:14:38.140226 DQM0 = 137, DQM1 = 131
8798 22:14:38.142997 DQ Delay:
8799 22:14:38.146244 DQ0 =143, DQ1 =135, DQ2 =127, DQ3 =135
8800 22:14:38.149933 DQ4 =131, DQ5 =147, DQ6 =143, DQ7 =135
8801 22:14:38.152973 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
8802 22:14:38.156266 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =143
8803 22:14:38.156389
8804 22:14:38.156485
8805 22:14:38.156608 ==
8806 22:14:38.159496 Dram Type= 6, Freq= 0, CH_1, rank 1
8807 22:14:38.165852 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8808 22:14:38.165933 ==
8809 22:14:38.165998
8810 22:14:38.166056
8811 22:14:38.166113 TX Vref Scan disable
8812 22:14:38.169629 == TX Byte 0 ==
8813 22:14:38.173132 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8814 22:14:38.179281 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8815 22:14:38.179419 == TX Byte 1 ==
8816 22:14:38.182498 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8817 22:14:38.189136 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8818 22:14:38.189218 ==
8819 22:14:38.192512 Dram Type= 6, Freq= 0, CH_1, rank 1
8820 22:14:38.195613 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8821 22:14:38.195695 ==
8822 22:14:38.209302
8823 22:14:38.212849 TX Vref early break, caculate TX vref
8824 22:14:38.216278 TX Vref=16, minBit 9, minWin=22, winSum=376
8825 22:14:38.219301 TX Vref=18, minBit 9, minWin=22, winSum=385
8826 22:14:38.222607 TX Vref=20, minBit 9, minWin=23, winSum=393
8827 22:14:38.225961 TX Vref=22, minBit 9, minWin=23, winSum=403
8828 22:14:38.229192 TX Vref=24, minBit 9, minWin=24, winSum=410
8829 22:14:38.235934 TX Vref=26, minBit 9, minWin=24, winSum=415
8830 22:14:38.238872 TX Vref=28, minBit 9, minWin=25, winSum=422
8831 22:14:38.242589 TX Vref=30, minBit 9, minWin=24, winSum=416
8832 22:14:38.245525 TX Vref=32, minBit 5, minWin=24, winSum=408
8833 22:14:38.249021 TX Vref=34, minBit 0, minWin=24, winSum=404
8834 22:14:38.255663 TX Vref=36, minBit 8, minWin=23, winSum=396
8835 22:14:38.258689 [TxChooseVref] Worse bit 9, Min win 25, Win sum 422, Final Vref 28
8836 22:14:38.258771
8837 22:14:38.261885 Final TX Range 0 Vref 28
8838 22:14:38.261997
8839 22:14:38.262128 ==
8840 22:14:38.265398 Dram Type= 6, Freq= 0, CH_1, rank 1
8841 22:14:38.268759 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8842 22:14:38.271677 ==
8843 22:14:38.271758
8844 22:14:38.271821
8845 22:14:38.271881 TX Vref Scan disable
8846 22:14:38.278784 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8847 22:14:38.278867 == TX Byte 0 ==
8848 22:14:38.282023 u2DelayCellOfst[0]=10 cells (3 PI)
8849 22:14:38.285257 u2DelayCellOfst[1]=7 cells (2 PI)
8850 22:14:38.288610 u2DelayCellOfst[2]=0 cells (0 PI)
8851 22:14:38.291977 u2DelayCellOfst[3]=3 cells (1 PI)
8852 22:14:38.295156 u2DelayCellOfst[4]=7 cells (2 PI)
8853 22:14:38.298515 u2DelayCellOfst[5]=10 cells (3 PI)
8854 22:14:38.301660 u2DelayCellOfst[6]=10 cells (3 PI)
8855 22:14:38.305095 u2DelayCellOfst[7]=3 cells (1 PI)
8856 22:14:38.308173 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8857 22:14:38.311739 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8858 22:14:38.315140 == TX Byte 1 ==
8859 22:14:38.318386 u2DelayCellOfst[8]=0 cells (0 PI)
8860 22:14:38.321286 u2DelayCellOfst[9]=3 cells (1 PI)
8861 22:14:38.324544 u2DelayCellOfst[10]=14 cells (4 PI)
8862 22:14:38.327974 u2DelayCellOfst[11]=10 cells (3 PI)
8863 22:14:38.331137 u2DelayCellOfst[12]=17 cells (5 PI)
8864 22:14:38.334535 u2DelayCellOfst[13]=17 cells (5 PI)
8865 22:14:38.337698 u2DelayCellOfst[14]=21 cells (6 PI)
8866 22:14:38.341479 u2DelayCellOfst[15]=21 cells (6 PI)
8867 22:14:38.344378 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8868 22:14:38.347557 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8869 22:14:38.350761 DramC Write-DBI on
8870 22:14:38.350842 ==
8871 22:14:38.354761 Dram Type= 6, Freq= 0, CH_1, rank 1
8872 22:14:38.357809 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8873 22:14:38.357890 ==
8874 22:14:38.357955
8875 22:14:38.358015
8876 22:14:38.361521 TX Vref Scan disable
8877 22:14:38.364296 == TX Byte 0 ==
8878 22:14:38.367408 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8879 22:14:38.367489 == TX Byte 1 ==
8880 22:14:38.373899 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8881 22:14:38.373980 DramC Write-DBI off
8882 22:14:38.374045
8883 22:14:38.374105 [DATLAT]
8884 22:14:38.377480 Freq=1600, CH1 RK1
8885 22:14:38.377561
8886 22:14:38.380540 DATLAT Default: 0xf
8887 22:14:38.380620 0, 0xFFFF, sum = 0
8888 22:14:38.383839 1, 0xFFFF, sum = 0
8889 22:14:38.383922 2, 0xFFFF, sum = 0
8890 22:14:38.387141 3, 0xFFFF, sum = 0
8891 22:14:38.387224 4, 0xFFFF, sum = 0
8892 22:14:38.390751 5, 0xFFFF, sum = 0
8893 22:14:38.390833 6, 0xFFFF, sum = 0
8894 22:14:38.393532 7, 0xFFFF, sum = 0
8895 22:14:38.393614 8, 0xFFFF, sum = 0
8896 22:14:38.396975 9, 0xFFFF, sum = 0
8897 22:14:38.397058 10, 0xFFFF, sum = 0
8898 22:14:38.400382 11, 0xFFFF, sum = 0
8899 22:14:38.400464 12, 0xFFFF, sum = 0
8900 22:14:38.403492 13, 0xFFFF, sum = 0
8901 22:14:38.403575 14, 0x0, sum = 1
8902 22:14:38.406862 15, 0x0, sum = 2
8903 22:14:38.406944 16, 0x0, sum = 3
8904 22:14:38.410220 17, 0x0, sum = 4
8905 22:14:38.410303 best_step = 15
8906 22:14:38.410367
8907 22:14:38.410427 ==
8908 22:14:38.413700 Dram Type= 6, Freq= 0, CH_1, rank 1
8909 22:14:38.420225 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8910 22:14:38.420306 ==
8911 22:14:38.420371 RX Vref Scan: 0
8912 22:14:38.420431
8913 22:14:38.423623 RX Vref 0 -> 0, step: 1
8914 22:14:38.423704
8915 22:14:38.426572 RX Delay 19 -> 252, step: 4
8916 22:14:38.429810 iDelay=195, Bit 0, Center 136 (87 ~ 186) 100
8917 22:14:38.433397 iDelay=195, Bit 1, Center 130 (79 ~ 182) 104
8918 22:14:38.439966 iDelay=195, Bit 2, Center 122 (71 ~ 174) 104
8919 22:14:38.443019 iDelay=195, Bit 3, Center 128 (75 ~ 182) 108
8920 22:14:38.446294 iDelay=195, Bit 4, Center 132 (79 ~ 186) 108
8921 22:14:38.449513 iDelay=195, Bit 5, Center 142 (91 ~ 194) 104
8922 22:14:38.453108 iDelay=195, Bit 6, Center 140 (87 ~ 194) 108
8923 22:14:38.459567 iDelay=195, Bit 7, Center 130 (79 ~ 182) 104
8924 22:14:38.462904 iDelay=195, Bit 8, Center 114 (59 ~ 170) 112
8925 22:14:38.466152 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8926 22:14:38.469701 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
8927 22:14:38.473160 iDelay=195, Bit 11, Center 122 (67 ~ 178) 112
8928 22:14:38.479326 iDelay=195, Bit 12, Center 136 (83 ~ 190) 108
8929 22:14:38.483020 iDelay=195, Bit 13, Center 136 (83 ~ 190) 108
8930 22:14:38.485744 iDelay=195, Bit 14, Center 132 (79 ~ 186) 108
8931 22:14:38.489453 iDelay=195, Bit 15, Center 136 (83 ~ 190) 108
8932 22:14:38.489534 ==
8933 22:14:38.492604 Dram Type= 6, Freq= 0, CH_1, rank 1
8934 22:14:38.499144 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8935 22:14:38.499226 ==
8936 22:14:38.499291 DQS Delay:
8937 22:14:38.502466 DQS0 = 0, DQS1 = 0
8938 22:14:38.502547 DQM Delay:
8939 22:14:38.505921 DQM0 = 132, DQM1 = 127
8940 22:14:38.506001 DQ Delay:
8941 22:14:38.509275 DQ0 =136, DQ1 =130, DQ2 =122, DQ3 =128
8942 22:14:38.512425 DQ4 =132, DQ5 =142, DQ6 =140, DQ7 =130
8943 22:14:38.515715 DQ8 =114, DQ9 =118, DQ10 =128, DQ11 =122
8944 22:14:38.519077 DQ12 =136, DQ13 =136, DQ14 =132, DQ15 =136
8945 22:14:38.519159
8946 22:14:38.519246
8947 22:14:38.519309
8948 22:14:38.522200 [DramC_TX_OE_Calibration] TA2
8949 22:14:38.525779 Original DQ_B0 (3 6) =30, OEN = 27
8950 22:14:38.528695 Original DQ_B1 (3 6) =30, OEN = 27
8951 22:14:38.532237 24, 0x0, End_B0=24 End_B1=24
8952 22:14:38.535289 25, 0x0, End_B0=25 End_B1=25
8953 22:14:38.535372 26, 0x0, End_B0=26 End_B1=26
8954 22:14:38.538862 27, 0x0, End_B0=27 End_B1=27
8955 22:14:38.541992 28, 0x0, End_B0=28 End_B1=28
8956 22:14:38.545205 29, 0x0, End_B0=29 End_B1=29
8957 22:14:38.548571 30, 0x0, End_B0=30 End_B1=30
8958 22:14:38.548655 31, 0x4141, End_B0=30 End_B1=30
8959 22:14:38.551923 Byte0 end_step=30 best_step=27
8960 22:14:38.555129 Byte1 end_step=30 best_step=27
8961 22:14:38.558682 Byte0 TX OE(2T, 0.5T) = (3, 3)
8962 22:14:38.561760 Byte1 TX OE(2T, 0.5T) = (3, 3)
8963 22:14:38.561843
8964 22:14:38.561926
8965 22:14:38.568624 [DQSOSCAuto] RK1, (LSB)MR18= 0x111f, (MSB)MR19= 0x303, tDQSOscB0 = 394 ps tDQSOscB1 = 401 ps
8966 22:14:38.571917 CH1 RK1: MR19=303, MR18=111F
8967 22:14:38.578123 CH1_RK1: MR19=0x303, MR18=0x111F, DQSOSC=394, MR23=63, INC=23, DEC=15
8968 22:14:38.581354 [RxdqsGatingPostProcess] freq 1600
8969 22:14:38.587980 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8970 22:14:38.591232 best DQS0 dly(2T, 0.5T) = (1, 1)
8971 22:14:38.591315 best DQS1 dly(2T, 0.5T) = (1, 1)
8972 22:14:38.594468 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8973 22:14:38.598055 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8974 22:14:38.601196 best DQS0 dly(2T, 0.5T) = (1, 1)
8975 22:14:38.604656 best DQS1 dly(2T, 0.5T) = (1, 1)
8976 22:14:38.607912 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8977 22:14:38.611357 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8978 22:14:38.614757 Pre-setting of DQS Precalculation
8979 22:14:38.620805 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8980 22:14:38.627600 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
8981 22:14:38.634049 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8982 22:14:38.634132
8983 22:14:38.634197
8984 22:14:38.637292 [Calibration Summary] 3200 Mbps
8985 22:14:38.637374 CH 0, Rank 0
8986 22:14:38.640690 SW Impedance : PASS
8987 22:14:38.643930 DUTY Scan : NO K
8988 22:14:38.644012 ZQ Calibration : PASS
8989 22:14:38.647325 Jitter Meter : NO K
8990 22:14:38.650411 CBT Training : PASS
8991 22:14:38.650493 Write leveling : PASS
8992 22:14:38.653672 RX DQS gating : PASS
8993 22:14:38.657455 RX DQ/DQS(RDDQC) : PASS
8994 22:14:38.657537 TX DQ/DQS : PASS
8995 22:14:38.660486 RX DATLAT : PASS
8996 22:14:38.663432 RX DQ/DQS(Engine): PASS
8997 22:14:38.663514 TX OE : PASS
8998 22:14:38.663580 All Pass.
8999 22:14:38.667134
9000 22:14:38.667215 CH 0, Rank 1
9001 22:14:38.670068 SW Impedance : PASS
9002 22:14:38.670149 DUTY Scan : NO K
9003 22:14:38.673521 ZQ Calibration : PASS
9004 22:14:38.676889 Jitter Meter : NO K
9005 22:14:38.676971 CBT Training : PASS
9006 22:14:38.679928 Write leveling : PASS
9007 22:14:38.680041 RX DQS gating : PASS
9008 22:14:38.683474 RX DQ/DQS(RDDQC) : PASS
9009 22:14:38.686677 TX DQ/DQS : PASS
9010 22:14:38.686763 RX DATLAT : PASS
9011 22:14:38.689784 RX DQ/DQS(Engine): PASS
9012 22:14:38.693597 TX OE : PASS
9013 22:14:38.693681 All Pass.
9014 22:14:38.693747
9015 22:14:38.693808 CH 1, Rank 0
9016 22:14:38.696774 SW Impedance : PASS
9017 22:14:38.699811 DUTY Scan : NO K
9018 22:14:38.699893 ZQ Calibration : PASS
9019 22:14:38.703271 Jitter Meter : NO K
9020 22:14:38.706806 CBT Training : PASS
9021 22:14:38.706891 Write leveling : PASS
9022 22:14:38.709603 RX DQS gating : PASS
9023 22:14:38.713290 RX DQ/DQS(RDDQC) : PASS
9024 22:14:38.713374 TX DQ/DQS : PASS
9025 22:14:38.716185 RX DATLAT : PASS
9026 22:14:38.719717 RX DQ/DQS(Engine): PASS
9027 22:14:38.719814 TX OE : PASS
9028 22:14:38.722998 All Pass.
9029 22:14:38.723080
9030 22:14:38.723144 CH 1, Rank 1
9031 22:14:38.726750 SW Impedance : PASS
9032 22:14:38.726831 DUTY Scan : NO K
9033 22:14:38.729112 ZQ Calibration : PASS
9034 22:14:38.732623 Jitter Meter : NO K
9035 22:14:38.732705 CBT Training : PASS
9036 22:14:38.736402 Write leveling : PASS
9037 22:14:38.739457 RX DQS gating : PASS
9038 22:14:38.739539 RX DQ/DQS(RDDQC) : PASS
9039 22:14:38.742433 TX DQ/DQS : PASS
9040 22:14:38.745837 RX DATLAT : PASS
9041 22:14:38.745945 RX DQ/DQS(Engine): PASS
9042 22:14:38.749344 TX OE : PASS
9043 22:14:38.749426 All Pass.
9044 22:14:38.749490
9045 22:14:38.752573 DramC Write-DBI on
9046 22:14:38.755380 PER_BANK_REFRESH: Hybrid Mode
9047 22:14:38.755462 TX_TRACKING: ON
9048 22:14:38.765357 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9049 22:14:38.772244 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9050 22:14:38.778548 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9051 22:14:38.785001 [FAST_K] Save calibration result to emmc
9052 22:14:38.785083 sync common calibartion params.
9053 22:14:38.788268 sync cbt_mode0:1, 1:1
9054 22:14:38.791725 dram_init: ddr_geometry: 2
9055 22:14:38.791807 dram_init: ddr_geometry: 2
9056 22:14:38.795019 dram_init: ddr_geometry: 2
9057 22:14:38.797944 0:dram_rank_size:100000000
9058 22:14:38.801532 1:dram_rank_size:100000000
9059 22:14:38.804695 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9060 22:14:38.808007 DFS_SHUFFLE_HW_MODE: ON
9061 22:14:38.811654 dramc_set_vcore_voltage set vcore to 725000
9062 22:14:38.814686 Read voltage for 1600, 0
9063 22:14:38.814768 Vio18 = 0
9064 22:14:38.817891 Vcore = 725000
9065 22:14:38.817973 Vdram = 0
9066 22:14:38.818059 Vddq = 0
9067 22:14:38.818137 Vmddr = 0
9068 22:14:38.821185 switch to 3200 Mbps bootup
9069 22:14:38.824523 [DramcRunTimeConfig]
9070 22:14:38.824611 PHYPLL
9071 22:14:38.827635 DPM_CONTROL_AFTERK: ON
9072 22:14:38.827716 PER_BANK_REFRESH: ON
9073 22:14:38.831051 REFRESH_OVERHEAD_REDUCTION: ON
9074 22:14:38.834558 CMD_PICG_NEW_MODE: OFF
9075 22:14:38.834640 XRTWTW_NEW_MODE: ON
9076 22:14:38.837392 XRTRTR_NEW_MODE: ON
9077 22:14:38.837473 TX_TRACKING: ON
9078 22:14:38.840803 RDSEL_TRACKING: OFF
9079 22:14:38.843966 DQS Precalculation for DVFS: ON
9080 22:14:38.844085 RX_TRACKING: OFF
9081 22:14:38.847701 HW_GATING DBG: ON
9082 22:14:38.847783 ZQCS_ENABLE_LP4: ON
9083 22:14:38.850675 RX_PICG_NEW_MODE: ON
9084 22:14:38.850760 TX_PICG_NEW_MODE: ON
9085 22:14:38.854092 ENABLE_RX_DCM_DPHY: ON
9086 22:14:38.857662 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9087 22:14:38.860482 DUMMY_READ_FOR_TRACKING: OFF
9088 22:14:38.860572 !!! SPM_CONTROL_AFTERK: OFF
9089 22:14:38.864183 !!! SPM could not control APHY
9090 22:14:38.867457 IMPEDANCE_TRACKING: ON
9091 22:14:38.867539 TEMP_SENSOR: ON
9092 22:14:38.870564 HW_SAVE_FOR_SR: OFF
9093 22:14:38.873799 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9094 22:14:38.877554 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9095 22:14:38.877636 Read ODT Tracking: ON
9096 22:14:38.880296 Refresh Rate DeBounce: ON
9097 22:14:38.883646 DFS_NO_QUEUE_FLUSH: ON
9098 22:14:38.887225 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9099 22:14:38.890496 ENABLE_DFS_RUNTIME_MRW: OFF
9100 22:14:38.890584 DDR_RESERVE_NEW_MODE: ON
9101 22:14:38.893729 MR_CBT_SWITCH_FREQ: ON
9102 22:14:38.896981 =========================
9103 22:14:38.914457 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9104 22:14:38.917659 dram_init: ddr_geometry: 2
9105 22:14:38.935702 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9106 22:14:38.939052 dram_init: dram init end (result: 0)
9107 22:14:38.945235 DRAM-K: Full calibration passed in 24396 msecs
9108 22:14:38.948534 MRC: failed to locate region type 0.
9109 22:14:38.948611 DRAM rank0 size:0x100000000,
9110 22:14:38.952028 DRAM rank1 size=0x100000000
9111 22:14:38.961859 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9112 22:14:38.968485 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9113 22:14:38.978024 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9114 22:14:38.984868 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9115 22:14:38.984949 DRAM rank0 size:0x100000000,
9116 22:14:38.988167 DRAM rank1 size=0x100000000
9117 22:14:38.988250 CBMEM:
9118 22:14:38.991263 IMD: root @ 0xfffff000 254 entries.
9119 22:14:38.994890 IMD: root @ 0xffffec00 62 entries.
9120 22:14:39.001284 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9121 22:14:39.004496 WARNING: RO_VPD is uninitialized or empty.
9122 22:14:39.007778 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9123 22:14:39.015614 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9124 22:14:39.028851 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9125 22:14:39.039945 BS: romstage times (exec / console): total (unknown) / 23933 ms
9126 22:14:39.040086
9127 22:14:39.040187
9128 22:14:39.049808 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9129 22:14:39.053296 ARM64: Exception handlers installed.
9130 22:14:39.056214 ARM64: Testing exception
9131 22:14:39.059670 ARM64: Done test exception
9132 22:14:39.059752 Enumerating buses...
9133 22:14:39.062823 Show all devs... Before device enumeration.
9134 22:14:39.066364 Root Device: enabled 1
9135 22:14:39.069598 CPU_CLUSTER: 0: enabled 1
9136 22:14:39.069677 CPU: 00: enabled 1
9137 22:14:39.072860 Compare with tree...
9138 22:14:39.072937 Root Device: enabled 1
9139 22:14:39.075938 CPU_CLUSTER: 0: enabled 1
9140 22:14:39.079289 CPU: 00: enabled 1
9141 22:14:39.079365 Root Device scanning...
9142 22:14:39.083067 scan_static_bus for Root Device
9143 22:14:39.086001 CPU_CLUSTER: 0 enabled
9144 22:14:39.089627 scan_static_bus for Root Device done
9145 22:14:39.092586 scan_bus: bus Root Device finished in 8 msecs
9146 22:14:39.092661 done
9147 22:14:39.099352 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9148 22:14:39.102260 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9149 22:14:39.109573 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9150 22:14:39.112691 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9151 22:14:39.115741 Allocating resources...
9152 22:14:39.119208 Reading resources...
9153 22:14:39.122447 Root Device read_resources bus 0 link: 0
9154 22:14:39.125826 DRAM rank0 size:0x100000000,
9155 22:14:39.125902 DRAM rank1 size=0x100000000
9156 22:14:39.132217 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9157 22:14:39.132294 CPU: 00 missing read_resources
9158 22:14:39.139107 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9159 22:14:39.142275 Root Device read_resources bus 0 link: 0 done
9160 22:14:39.145423 Done reading resources.
9161 22:14:39.148529 Show resources in subtree (Root Device)...After reading.
9162 22:14:39.152201 Root Device child on link 0 CPU_CLUSTER: 0
9163 22:14:39.155249 CPU_CLUSTER: 0 child on link 0 CPU: 00
9164 22:14:39.165266 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9165 22:14:39.165367 CPU: 00
9166 22:14:39.168752 Root Device assign_resources, bus 0 link: 0
9167 22:14:39.171823 CPU_CLUSTER: 0 missing set_resources
9168 22:14:39.178612 Root Device assign_resources, bus 0 link: 0 done
9169 22:14:39.178688 Done setting resources.
9170 22:14:39.184841 Show resources in subtree (Root Device)...After assigning values.
9171 22:14:39.188289 Root Device child on link 0 CPU_CLUSTER: 0
9172 22:14:39.192192 CPU_CLUSTER: 0 child on link 0 CPU: 00
9173 22:14:39.201309 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9174 22:14:39.201390 CPU: 00
9175 22:14:39.204522 Done allocating resources.
9176 22:14:39.211385 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9177 22:14:39.211466 Enabling resources...
9178 22:14:39.214479 done.
9179 22:14:39.217617 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9180 22:14:39.220930 Initializing devices...
9181 22:14:39.221011 Root Device init
9182 22:14:39.224387 init hardware done!
9183 22:14:39.224468 0x00000018: ctrlr->caps
9184 22:14:39.227854 52.000 MHz: ctrlr->f_max
9185 22:14:39.231127 0.400 MHz: ctrlr->f_min
9186 22:14:39.234038 0x40ff8080: ctrlr->voltages
9187 22:14:39.234147 sclk: 390625
9188 22:14:39.234252 Bus Width = 1
9189 22:14:39.237341 sclk: 390625
9190 22:14:39.237421 Bus Width = 1
9191 22:14:39.240577 Early init status = 3
9192 22:14:39.244055 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9193 22:14:39.248701 in-header: 03 fc 00 00 01 00 00 00
9194 22:14:39.251684 in-data: 00
9195 22:14:39.255064 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9196 22:14:39.260767 in-header: 03 fd 00 00 00 00 00 00
9197 22:14:39.263909 in-data:
9198 22:14:39.267215 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9199 22:14:39.271680 in-header: 03 fc 00 00 01 00 00 00
9200 22:14:39.275261 in-data: 00
9201 22:14:39.278298 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9202 22:14:39.283682 in-header: 03 fd 00 00 00 00 00 00
9203 22:14:39.287289 in-data:
9204 22:14:39.290812 [SSUSB] Setting up USB HOST controller...
9205 22:14:39.293713 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9206 22:14:39.296776 [SSUSB] phy power-on done.
9207 22:14:39.300067 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9208 22:14:39.306940 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9209 22:14:39.310116 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9210 22:14:39.316790 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9211 22:14:39.323467 read SPI 0x50eb0 0x2ad3: 1175 us, 9330 KB/s, 74.640 Mbps
9212 22:14:39.329782 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9213 22:14:39.336836 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9214 22:14:39.343265 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9215 22:14:39.346748 SPM: binary array size = 0x9dc
9216 22:14:39.350025 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9217 22:14:39.356606 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9218 22:14:39.362832 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9219 22:14:39.369215 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9220 22:14:39.372916 configure_display: Starting display init
9221 22:14:39.407389 anx7625_power_on_init: Init interface.
9222 22:14:39.410489 anx7625_disable_pd_protocol: Disabled PD feature.
9223 22:14:39.413697 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9224 22:14:39.441715 anx7625_start_dp_work: Secure OCM version=00
9225 22:14:39.444729 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9226 22:14:39.459555 sp_tx_get_edid_block: EDID Block = 1
9227 22:14:39.561930 Extracted contents:
9228 22:14:39.565199 header: 00 ff ff ff ff ff ff 00
9229 22:14:39.568709 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9230 22:14:39.572286 version: 01 04
9231 22:14:39.575426 basic params: 95 1f 11 78 0a
9232 22:14:39.578870 chroma info: 76 90 94 55 54 90 27 21 50 54
9233 22:14:39.581783 established: 00 00 00
9234 22:14:39.588649 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9235 22:14:39.595081 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9236 22:14:39.598579 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9237 22:14:39.605209 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9238 22:14:39.611357 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9239 22:14:39.614966 extensions: 00
9240 22:14:39.615046 checksum: fb
9241 22:14:39.615111
9242 22:14:39.621617 Manufacturer: IVO Model 57d Serial Number 0
9243 22:14:39.621699 Made week 0 of 2020
9244 22:14:39.624720 EDID version: 1.4
9245 22:14:39.624801 Digital display
9246 22:14:39.627651 6 bits per primary color channel
9247 22:14:39.631631 DisplayPort interface
9248 22:14:39.631712 Maximum image size: 31 cm x 17 cm
9249 22:14:39.634532 Gamma: 220%
9250 22:14:39.634613 Check DPMS levels
9251 22:14:39.641201 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9252 22:14:39.644322 First detailed timing is preferred timing
9253 22:14:39.647757 Established timings supported:
9254 22:14:39.647842 Standard timings supported:
9255 22:14:39.651100 Detailed timings
9256 22:14:39.654224 Hex of detail: 383680a07038204018303c0035ae10000019
9257 22:14:39.660762 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9258 22:14:39.664431 0780 0798 07c8 0820 hborder 0
9259 22:14:39.667883 0438 043b 0447 0458 vborder 0
9260 22:14:39.670968 -hsync -vsync
9261 22:14:39.671049 Did detailed timing
9262 22:14:39.677559 Hex of detail: 000000000000000000000000000000000000
9263 22:14:39.680609 Manufacturer-specified data, tag 0
9264 22:14:39.683948 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9265 22:14:39.687397 ASCII string: InfoVision
9266 22:14:39.690638 Hex of detail: 000000fe00523134304e574635205248200a
9267 22:14:39.693789 ASCII string: R140NWF5 RH
9268 22:14:39.693872 Checksum
9269 22:14:39.697294 Checksum: 0xfb (valid)
9270 22:14:39.700618 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9271 22:14:39.704135 DSI data_rate: 832800000 bps
9272 22:14:39.710306 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9273 22:14:39.714014 anx7625_parse_edid: pixelclock(138800).
9274 22:14:39.716884 hactive(1920), hsync(48), hfp(24), hbp(88)
9275 22:14:39.720143 vactive(1080), vsync(12), vfp(3), vbp(17)
9276 22:14:39.723397 anx7625_dsi_config: config dsi.
9277 22:14:39.730107 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9278 22:14:39.743972 anx7625_dsi_config: success to config DSI
9279 22:14:39.748112 anx7625_dp_start: MIPI phy setup OK.
9280 22:14:39.751378 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9281 22:14:39.754011 mtk_ddp_mode_set invalid vrefresh 60
9282 22:14:39.757716 main_disp_path_setup
9283 22:14:39.757793 ovl_layer_smi_id_en
9284 22:14:39.760352 ovl_layer_smi_id_en
9285 22:14:39.760424 ccorr_config
9286 22:14:39.760485 aal_config
9287 22:14:39.763954 gamma_config
9288 22:14:39.764070 postmask_config
9289 22:14:39.767520 dither_config
9290 22:14:39.770780 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9291 22:14:39.777341 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9292 22:14:39.780272 Root Device init finished in 555 msecs
9293 22:14:39.783726 CPU_CLUSTER: 0 init
9294 22:14:39.790120 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9295 22:14:39.796532 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9296 22:14:39.796631 APU_MBOX 0x190000b0 = 0x10001
9297 22:14:39.800270 APU_MBOX 0x190001b0 = 0x10001
9298 22:14:39.803325 APU_MBOX 0x190005b0 = 0x10001
9299 22:14:39.806651 APU_MBOX 0x190006b0 = 0x10001
9300 22:14:39.813146 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9301 22:14:39.823073 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9302 22:14:39.835645 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9303 22:14:39.842379 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9304 22:14:39.854450 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9305 22:14:39.863326 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9306 22:14:39.866869 CPU_CLUSTER: 0 init finished in 81 msecs
9307 22:14:39.869634 Devices initialized
9308 22:14:39.873460 Show all devs... After init.
9309 22:14:39.873870 Root Device: enabled 1
9310 22:14:39.876706 CPU_CLUSTER: 0: enabled 1
9311 22:14:39.879815 CPU: 00: enabled 1
9312 22:14:39.883180 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9313 22:14:39.886420 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9314 22:14:39.889943 ELOG: NV offset 0x57f000 size 0x1000
9315 22:14:39.896491 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9316 22:14:39.903261 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9317 22:14:39.906272 ELOG: Event(17) added with size 13 at 2023-06-05 22:14:44 UTC
9318 22:14:39.913075 out: cmd=0x121: 03 db 21 01 00 00 00 00
9319 22:14:39.916298 in-header: 03 47 00 00 2c 00 00 00
9320 22:14:39.926200 in-data: 18 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9321 22:14:39.932556 ELOG: Event(A1) added with size 10 at 2023-06-05 22:14:44 UTC
9322 22:14:39.939432 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9323 22:14:39.946465 ELOG: Event(A0) added with size 9 at 2023-06-05 22:14:44 UTC
9324 22:14:39.949254 elog_add_boot_reason: Logged dev mode boot
9325 22:14:39.955727 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9326 22:14:39.956183 Finalize devices...
9327 22:14:39.958934 Devices finalized
9328 22:14:39.962461 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9329 22:14:39.966162 Writing coreboot table at 0xffe64000
9330 22:14:39.969266 0. 000000000010a000-0000000000113fff: RAMSTAGE
9331 22:14:39.975853 1. 0000000040000000-00000000400fffff: RAM
9332 22:14:39.978679 2. 0000000040100000-000000004032afff: RAMSTAGE
9333 22:14:39.982090 3. 000000004032b000-00000000545fffff: RAM
9334 22:14:39.985725 4. 0000000054600000-000000005465ffff: BL31
9335 22:14:39.988797 5. 0000000054660000-00000000ffe63fff: RAM
9336 22:14:39.995241 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9337 22:14:39.998693 7. 0000000100000000-000000023fffffff: RAM
9338 22:14:40.002243 Passing 5 GPIOs to payload:
9339 22:14:40.005287 NAME | PORT | POLARITY | VALUE
9340 22:14:40.012029 EC in RW | 0x000000aa | low | undefined
9341 22:14:40.015666 EC interrupt | 0x00000005 | low | undefined
9342 22:14:40.018733 TPM interrupt | 0x000000ab | high | undefined
9343 22:14:40.025190 SD card detect | 0x00000011 | high | undefined
9344 22:14:40.028487 speaker enable | 0x00000093 | high | undefined
9345 22:14:40.031988 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9346 22:14:40.035449 in-header: 03 f9 00 00 02 00 00 00
9347 22:14:40.038337 in-data: 02 00
9348 22:14:40.041577 ADC[4]: Raw value=903325 ID=7
9349 22:14:40.042012 ADC[3]: Raw value=213546 ID=1
9350 22:14:40.045163 RAM Code: 0x71
9351 22:14:40.048371 ADC[6]: Raw value=75000 ID=0
9352 22:14:40.048821 ADC[5]: Raw value=213546 ID=1
9353 22:14:40.051332 SKU Code: 0x1
9354 22:14:40.058365 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum a53a
9355 22:14:40.058786 coreboot table: 964 bytes.
9356 22:14:40.061464 IMD ROOT 0. 0xfffff000 0x00001000
9357 22:14:40.064613 IMD SMALL 1. 0xffffe000 0x00001000
9358 22:14:40.068025 RO MCACHE 2. 0xffffc000 0x00001104
9359 22:14:40.071202 CONSOLE 3. 0xfff7c000 0x00080000
9360 22:14:40.074329 FMAP 4. 0xfff7b000 0x00000452
9361 22:14:40.077830 TIME STAMP 5. 0xfff7a000 0x00000910
9362 22:14:40.081197 VBOOT WORK 6. 0xfff66000 0x00014000
9363 22:14:40.084360 RAMOOPS 7. 0xffe66000 0x00100000
9364 22:14:40.087358 COREBOOT 8. 0xffe64000 0x00002000
9365 22:14:40.090867 IMD small region:
9366 22:14:40.094367 IMD ROOT 0. 0xffffec00 0x00000400
9367 22:14:40.097606 VPD 1. 0xffffeba0 0x0000004c
9368 22:14:40.100832 MMC STATUS 2. 0xffffeb80 0x00000004
9369 22:14:40.107273 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9370 22:14:40.107694 Probing TPM: done!
9371 22:14:40.113894 Connected to device vid:did:rid of 1ae0:0028:00
9372 22:14:40.121061 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523
9373 22:14:40.124264 Initialized TPM device CR50 revision 0
9374 22:14:40.127829 Checking cr50 for pending updates
9375 22:14:40.133317 Reading cr50 TPM mode
9376 22:14:40.141570 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9377 22:14:40.148473 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9378 22:14:40.188574 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9379 22:14:40.191688 Checking segment from ROM address 0x40100000
9380 22:14:40.194956 Checking segment from ROM address 0x4010001c
9381 22:14:40.201769 Loading segment from ROM address 0x40100000
9382 22:14:40.202188 code (compression=0)
9383 22:14:40.211295 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9384 22:14:40.218436 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9385 22:14:40.218857 it's not compressed!
9386 22:14:40.224978 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9387 22:14:40.231368 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9388 22:14:40.248537 Loading segment from ROM address 0x4010001c
9389 22:14:40.249083 Entry Point 0x80000000
9390 22:14:40.251855 Loaded segments
9391 22:14:40.255330 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9392 22:14:40.261949 Jumping to boot code at 0x80000000(0xffe64000)
9393 22:14:40.268835 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9394 22:14:40.275097 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9395 22:14:40.282924 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9396 22:14:40.286306 Checking segment from ROM address 0x40100000
9397 22:14:40.290181 Checking segment from ROM address 0x4010001c
9398 22:14:40.296467 Loading segment from ROM address 0x40100000
9399 22:14:40.296916 code (compression=1)
9400 22:14:40.303382 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9401 22:14:40.313285 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9402 22:14:40.313733 using LZMA
9403 22:14:40.321563 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9404 22:14:40.328129 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9405 22:14:40.331414 Loading segment from ROM address 0x4010001c
9406 22:14:40.332003 Entry Point 0x54601000
9407 22:14:40.334689 Loaded segments
9408 22:14:40.338377 NOTICE: MT8192 bl31_setup
9409 22:14:40.345217 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9410 22:14:40.348347 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9411 22:14:40.351558 WARNING: region 0:
9412 22:14:40.355283 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9413 22:14:40.355728 WARNING: region 1:
9414 22:14:40.362284 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9415 22:14:40.365135 WARNING: region 2:
9416 22:14:40.368319 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9417 22:14:40.372308 WARNING: region 3:
9418 22:14:40.375455 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9419 22:14:40.378791 WARNING: region 4:
9420 22:14:40.385349 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9421 22:14:40.385939 WARNING: region 5:
9422 22:14:40.388289 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9423 22:14:40.392132 WARNING: region 6:
9424 22:14:40.394974 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9425 22:14:40.399003 WARNING: region 7:
9426 22:14:40.401364 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9427 22:14:40.408328 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9428 22:14:40.411389 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9429 22:14:40.414757 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9430 22:14:40.421629 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9431 22:14:40.424791 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9432 22:14:40.428527 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9433 22:14:40.434644 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9434 22:14:40.437923 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9435 22:14:40.444939 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9436 22:14:40.447954 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9437 22:14:40.451609 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9438 22:14:40.458386 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9439 22:14:40.461115 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9440 22:14:40.464692 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9441 22:14:40.471087 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9442 22:14:40.474419 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9443 22:14:40.481528 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9444 22:14:40.484638 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9445 22:14:40.487923 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9446 22:14:40.494218 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9447 22:14:40.497743 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9448 22:14:40.500922 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9449 22:14:40.507607 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9450 22:14:40.510842 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9451 22:14:40.517540 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9452 22:14:40.521129 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9453 22:14:40.527577 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9454 22:14:40.530967 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9455 22:14:40.534497 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9456 22:14:40.540587 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9457 22:14:40.544459 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9458 22:14:40.550788 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9459 22:14:40.554047 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9460 22:14:40.557475 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9461 22:14:40.560978 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9462 22:14:40.567648 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9463 22:14:40.570855 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9464 22:14:40.574372 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9465 22:14:40.577339 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9466 22:14:40.583970 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9467 22:14:40.587245 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9468 22:14:40.590272 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9469 22:14:40.594265 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9470 22:14:40.600483 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9471 22:14:40.603684 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9472 22:14:40.606858 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9473 22:14:40.610238 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9474 22:14:40.617082 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9475 22:14:40.620752 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9476 22:14:40.627302 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9477 22:14:40.630549 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9478 22:14:40.633775 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9479 22:14:40.640548 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9480 22:14:40.643718 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9481 22:14:40.650783 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9482 22:14:40.653762 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9483 22:14:40.657026 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9484 22:14:40.664195 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9485 22:14:40.667238 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9486 22:14:40.673767 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9487 22:14:40.677114 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9488 22:14:40.684001 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9489 22:14:40.686887 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9490 22:14:40.693740 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9491 22:14:40.696897 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9492 22:14:40.703504 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9493 22:14:40.706663 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9494 22:14:40.710264 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9495 22:14:40.716828 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9496 22:14:40.720234 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9497 22:14:40.726803 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9498 22:14:40.730294 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9499 22:14:40.736770 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9500 22:14:40.739931 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9501 22:14:40.743394 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9502 22:14:40.750097 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9503 22:14:40.753432 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9504 22:14:40.760027 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9505 22:14:40.763081 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9506 22:14:40.770084 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9507 22:14:40.772960 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9508 22:14:40.779926 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9509 22:14:40.783023 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9510 22:14:40.786774 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9511 22:14:40.793113 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9512 22:14:40.796977 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9513 22:14:40.803166 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9514 22:14:40.806570 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9515 22:14:40.813255 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9516 22:14:40.816368 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9517 22:14:40.819847 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9518 22:14:40.826264 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9519 22:14:40.829628 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9520 22:14:40.835974 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9521 22:14:40.839459 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9522 22:14:40.846079 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9523 22:14:40.849374 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9524 22:14:40.852707 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9525 22:14:40.859213 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9526 22:14:40.862534 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9527 22:14:40.865988 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9528 22:14:40.869136 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9529 22:14:40.876404 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9530 22:14:40.879418 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9531 22:14:40.885752 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9532 22:14:40.889045 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9533 22:14:40.892390 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9534 22:14:40.899360 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9535 22:14:40.902470 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9536 22:14:40.909124 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9537 22:14:40.912522 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9538 22:14:40.915654 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9539 22:14:40.922230 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9540 22:14:40.925563 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9541 22:14:40.932162 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9542 22:14:40.935502 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9543 22:14:40.938942 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9544 22:14:40.946144 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9545 22:14:40.948877 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9546 22:14:40.952198 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9547 22:14:40.955635 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9548 22:14:40.961961 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9549 22:14:40.965195 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9550 22:14:40.968694 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9551 22:14:40.975389 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9552 22:14:40.978968 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9553 22:14:40.981827 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9554 22:14:40.988566 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9555 22:14:40.991921 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9556 22:14:40.998356 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9557 22:14:41.001806 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9558 22:14:41.005211 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9559 22:14:41.011869 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9560 22:14:41.015231 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9561 22:14:41.021811 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9562 22:14:41.025329 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9563 22:14:41.028343 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9564 22:14:41.035102 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9565 22:14:41.038732 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9566 22:14:41.041845 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9567 22:14:41.048076 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9568 22:14:41.051474 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9569 22:14:41.058059 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9570 22:14:41.061488 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9571 22:14:41.064863 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9572 22:14:41.071610 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9573 22:14:41.074614 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9574 22:14:41.081787 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9575 22:14:41.084598 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9576 22:14:41.088240 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9577 22:14:41.095027 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9578 22:14:41.098047 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9579 22:14:41.104837 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9580 22:14:41.107939 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9581 22:14:41.111766 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9582 22:14:41.118132 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9583 22:14:41.122007 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9584 22:14:41.128406 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9585 22:14:41.131737 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9586 22:14:41.134966 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9587 22:14:41.141448 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9588 22:14:41.144759 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9589 22:14:41.151310 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9590 22:14:41.154239 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9591 22:14:41.157700 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9592 22:14:41.164382 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9593 22:14:41.167728 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9594 22:14:41.171190 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9595 22:14:41.177414 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9596 22:14:41.180648 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9597 22:14:41.187416 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9598 22:14:41.190651 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9599 22:14:41.193874 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9600 22:14:41.200712 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9601 22:14:41.203830 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9602 22:14:41.210936 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9603 22:14:41.213778 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9604 22:14:41.220316 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9605 22:14:41.223456 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9606 22:14:41.227233 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9607 22:14:41.233773 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9608 22:14:41.236793 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9609 22:14:41.243409 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9610 22:14:41.246747 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9611 22:14:41.249961 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9612 22:14:41.256748 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9613 22:14:41.259791 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9614 22:14:41.266822 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9615 22:14:41.269803 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9616 22:14:41.273072 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9617 22:14:41.279672 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9618 22:14:41.283048 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9619 22:14:41.289665 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9620 22:14:41.293119 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9621 22:14:41.299544 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9622 22:14:41.302604 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9623 22:14:41.306289 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9624 22:14:41.313233 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9625 22:14:41.315888 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9626 22:14:41.322673 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9627 22:14:41.325953 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9628 22:14:41.329280 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9629 22:14:41.335661 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9630 22:14:41.339030 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9631 22:14:41.345695 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9632 22:14:41.349009 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9633 22:14:41.355439 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9634 22:14:41.359378 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9635 22:14:41.362548 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9636 22:14:41.369280 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9637 22:14:41.372197 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9638 22:14:41.379222 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9639 22:14:41.382474 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9640 22:14:41.389151 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9641 22:14:41.391865 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9642 22:14:41.395398 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9643 22:14:41.401811 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9644 22:14:41.405442 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9645 22:14:41.411994 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9646 22:14:41.415141 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9647 22:14:41.421916 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9648 22:14:41.425044 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9649 22:14:41.428284 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9650 22:14:41.435020 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9651 22:14:41.438319 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9652 22:14:41.445034 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9653 22:14:41.448075 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9654 22:14:41.455063 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9655 22:14:41.457957 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9656 22:14:41.461700 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9657 22:14:41.464651 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9658 22:14:41.471189 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9659 22:14:41.474778 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9660 22:14:41.477593 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9661 22:14:41.481209 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9662 22:14:41.487722 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9663 22:14:41.491119 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9664 22:14:41.497825 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9665 22:14:41.500725 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9666 22:14:41.504422 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9667 22:14:41.510341 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9668 22:14:41.513815 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9669 22:14:41.520563 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9670 22:14:41.523970 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9671 22:14:41.527203 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9672 22:14:41.533931 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9673 22:14:41.536974 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9674 22:14:41.543806 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9675 22:14:41.546881 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9676 22:14:41.549975 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9677 22:14:41.556634 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9678 22:14:41.560116 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9679 22:14:41.563364 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9680 22:14:41.569829 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9681 22:14:41.573432 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9682 22:14:41.576536 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9683 22:14:41.583163 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9684 22:14:41.586663 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9685 22:14:41.592500 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9686 22:14:41.596104 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9687 22:14:41.599215 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9688 22:14:41.606299 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9689 22:14:41.609311 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9690 22:14:41.612452 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9691 22:14:41.619324 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9692 22:14:41.622728 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9693 22:14:41.628879 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9694 22:14:41.632254 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9695 22:14:41.635318 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9696 22:14:41.642006 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9697 22:14:41.645124 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9698 22:14:41.648371 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9699 22:14:41.651950 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9700 22:14:41.655172 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9701 22:14:41.661728 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9702 22:14:41.665183 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9703 22:14:41.668498 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9704 22:14:41.671553 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9705 22:14:41.678055 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9706 22:14:41.681529 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9707 22:14:41.684563 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9708 22:14:41.691339 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9709 22:14:41.694388 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9710 22:14:41.698403 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9711 22:14:41.704410 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9712 22:14:41.708636 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9713 22:14:41.714000 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9714 22:14:41.717348 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9715 22:14:41.724061 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9716 22:14:41.727731 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9717 22:14:41.730840 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9718 22:14:41.737405 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9719 22:14:41.740526 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9720 22:14:41.747154 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9721 22:14:41.750809 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9722 22:14:41.757305 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9723 22:14:41.760302 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9724 22:14:41.763657 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9725 22:14:41.769976 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9726 22:14:41.773680 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9727 22:14:41.780163 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9728 22:14:41.783335 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9729 22:14:41.790083 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9730 22:14:41.793184 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9731 22:14:41.796482 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9732 22:14:41.803244 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9733 22:14:41.806250 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9734 22:14:41.812910 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9735 22:14:41.816441 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9736 22:14:41.819690 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9737 22:14:41.826520 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9738 22:14:41.829697 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9739 22:14:41.836320 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9740 22:14:41.839467 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9741 22:14:41.846220 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9742 22:14:41.849135 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9743 22:14:41.852941 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9744 22:14:41.859659 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9745 22:14:41.862995 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9746 22:14:41.869017 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9747 22:14:41.872462 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9748 22:14:41.875414 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9749 22:14:41.881840 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9750 22:14:41.885270 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9751 22:14:41.892196 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9752 22:14:41.895674 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9753 22:14:41.902308 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9754 22:14:41.905474 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9755 22:14:41.911910 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9756 22:14:41.915232 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9757 22:14:41.918693 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9758 22:14:41.925111 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9759 22:14:41.928735 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9760 22:14:41.935173 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9761 22:14:41.938681 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9762 22:14:41.941496 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9763 22:14:41.948001 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9764 22:14:41.951635 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9765 22:14:41.958854 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9766 22:14:41.961503 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9767 22:14:41.965143 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9768 22:14:41.971138 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9769 22:14:41.974853 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9770 22:14:41.980989 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9771 22:14:41.984294 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9772 22:14:41.991021 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9773 22:14:41.994850 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9774 22:14:41.997740 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9775 22:14:42.003791 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9776 22:14:42.007129 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9777 22:14:42.014146 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9778 22:14:42.017201 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9779 22:14:42.023496 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9780 22:14:42.026984 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9781 22:14:42.030149 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9782 22:14:42.037120 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9783 22:14:42.039910 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9784 22:14:42.046868 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9785 22:14:42.049857 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9786 22:14:42.056752 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9787 22:14:42.059733 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9788 22:14:42.063475 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9789 22:14:42.069684 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9790 22:14:42.073205 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9791 22:14:42.079633 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9792 22:14:42.082615 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9793 22:14:42.089113 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9794 22:14:42.092827 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9795 22:14:42.098997 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9796 22:14:42.102275 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9797 22:14:42.109219 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9798 22:14:42.112387 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9799 22:14:42.115936 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9800 22:14:42.122621 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9801 22:14:42.125588 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9802 22:14:42.132342 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9803 22:14:42.135450 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9804 22:14:42.142363 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9805 22:14:42.145266 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9806 22:14:42.149276 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9807 22:14:42.155558 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9808 22:14:42.158750 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9809 22:14:42.165363 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9810 22:14:42.168493 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9811 22:14:42.175179 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9812 22:14:42.178103 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9813 22:14:42.185148 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9814 22:14:42.188628 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9815 22:14:42.194747 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9816 22:14:42.198142 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9817 22:14:42.201225 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9818 22:14:42.208744 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9819 22:14:42.211399 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9820 22:14:42.217939 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9821 22:14:42.221268 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9822 22:14:42.227771 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9823 22:14:42.230926 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9824 22:14:42.237873 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9825 22:14:42.240814 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9826 22:14:42.247258 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9827 22:14:42.250603 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9828 22:14:42.254250 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9829 22:14:42.260844 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9830 22:14:42.264308 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9831 22:14:42.270529 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9832 22:14:42.274091 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9833 22:14:42.280435 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9834 22:14:42.283682 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9835 22:14:42.290123 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9836 22:14:42.294156 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9837 22:14:42.300264 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9838 22:14:42.303359 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9839 22:14:42.306731 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9840 22:14:42.313723 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9841 22:14:42.316592 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9842 22:14:42.323555 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9843 22:14:42.326608 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9844 22:14:42.333178 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9845 22:14:42.336508 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9846 22:14:42.342972 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9847 22:14:42.346597 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9848 22:14:42.352846 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9849 22:14:42.356314 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9850 22:14:42.362875 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9851 22:14:42.366243 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9852 22:14:42.372933 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9853 22:14:42.378983 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9854 22:14:42.382212 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9855 22:14:42.389085 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9856 22:14:42.392415 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9857 22:14:42.398433 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9858 22:14:42.402325 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9859 22:14:42.408679 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9860 22:14:42.412156 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9861 22:14:42.415325 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9862 22:14:42.418356 INFO: [APUAPC] vio 0
9863 22:14:42.425176 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9864 22:14:42.428269 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9865 22:14:42.431836 INFO: [APUAPC] D0_APC_0: 0x400510
9866 22:14:42.434792 INFO: [APUAPC] D0_APC_1: 0x0
9867 22:14:42.438015 INFO: [APUAPC] D0_APC_2: 0x1540
9868 22:14:42.441362 INFO: [APUAPC] D0_APC_3: 0x0
9869 22:14:42.444961 INFO: [APUAPC] D1_APC_0: 0xffffffff
9870 22:14:42.448137 INFO: [APUAPC] D1_APC_1: 0xffffffff
9871 22:14:42.451119 INFO: [APUAPC] D1_APC_2: 0x3fffff
9872 22:14:42.454761 INFO: [APUAPC] D1_APC_3: 0x0
9873 22:14:42.457958 INFO: [APUAPC] D2_APC_0: 0xffffffff
9874 22:14:42.461053 INFO: [APUAPC] D2_APC_1: 0xffffffff
9875 22:14:42.464258 INFO: [APUAPC] D2_APC_2: 0x3fffff
9876 22:14:42.467811 INFO: [APUAPC] D2_APC_3: 0x0
9877 22:14:42.471596 INFO: [APUAPC] D3_APC_0: 0xffffffff
9878 22:14:42.474400 INFO: [APUAPC] D3_APC_1: 0xffffffff
9879 22:14:42.477532 INFO: [APUAPC] D3_APC_2: 0x3fffff
9880 22:14:42.481104 INFO: [APUAPC] D3_APC_3: 0x0
9881 22:14:42.484071 INFO: [APUAPC] D4_APC_0: 0xffffffff
9882 22:14:42.487397 INFO: [APUAPC] D4_APC_1: 0xffffffff
9883 22:14:42.490637 INFO: [APUAPC] D4_APC_2: 0x3fffff
9884 22:14:42.493993 INFO: [APUAPC] D4_APC_3: 0x0
9885 22:14:42.497786 INFO: [APUAPC] D5_APC_0: 0xffffffff
9886 22:14:42.500540 INFO: [APUAPC] D5_APC_1: 0xffffffff
9887 22:14:42.504261 INFO: [APUAPC] D5_APC_2: 0x3fffff
9888 22:14:42.504346 INFO: [APUAPC] D5_APC_3: 0x0
9889 22:14:42.510517 INFO: [APUAPC] D6_APC_0: 0xffffffff
9890 22:14:42.513683 INFO: [APUAPC] D6_APC_1: 0xffffffff
9891 22:14:42.517380 INFO: [APUAPC] D6_APC_2: 0x3fffff
9892 22:14:42.517464 INFO: [APUAPC] D6_APC_3: 0x0
9893 22:14:42.520442 INFO: [APUAPC] D7_APC_0: 0xffffffff
9894 22:14:42.526993 INFO: [APUAPC] D7_APC_1: 0xffffffff
9895 22:14:42.530801 INFO: [APUAPC] D7_APC_2: 0x3fffff
9896 22:14:42.530892 INFO: [APUAPC] D7_APC_3: 0x0
9897 22:14:42.533321 INFO: [APUAPC] D8_APC_0: 0xffffffff
9898 22:14:42.539915 INFO: [APUAPC] D8_APC_1: 0xffffffff
9899 22:14:42.543449 INFO: [APUAPC] D8_APC_2: 0x3fffff
9900 22:14:42.543568 INFO: [APUAPC] D8_APC_3: 0x0
9901 22:14:42.546635 INFO: [APUAPC] D9_APC_0: 0xffffffff
9902 22:14:42.550441 INFO: [APUAPC] D9_APC_1: 0xffffffff
9903 22:14:42.553038 INFO: [APUAPC] D9_APC_2: 0x3fffff
9904 22:14:42.556868 INFO: [APUAPC] D9_APC_3: 0x0
9905 22:14:42.559875 INFO: [APUAPC] D10_APC_0: 0xffffffff
9906 22:14:42.563287 INFO: [APUAPC] D10_APC_1: 0xffffffff
9907 22:14:42.566352 INFO: [APUAPC] D10_APC_2: 0x3fffff
9908 22:14:42.569771 INFO: [APUAPC] D10_APC_3: 0x0
9909 22:14:42.572760 INFO: [APUAPC] D11_APC_0: 0xffffffff
9910 22:14:42.579802 INFO: [APUAPC] D11_APC_1: 0xffffffff
9911 22:14:42.582850 INFO: [APUAPC] D11_APC_2: 0x3fffff
9912 22:14:42.582935 INFO: [APUAPC] D11_APC_3: 0x0
9913 22:14:42.589516 INFO: [APUAPC] D12_APC_0: 0xffffffff
9914 22:14:42.592762 INFO: [APUAPC] D12_APC_1: 0xffffffff
9915 22:14:42.596468 INFO: [APUAPC] D12_APC_2: 0x3fffff
9916 22:14:42.599410 INFO: [APUAPC] D12_APC_3: 0x0
9917 22:14:42.602556 INFO: [APUAPC] D13_APC_0: 0xffffffff
9918 22:14:42.605965 INFO: [APUAPC] D13_APC_1: 0xffffffff
9919 22:14:42.608957 INFO: [APUAPC] D13_APC_2: 0x3fffff
9920 22:14:42.612307 INFO: [APUAPC] D13_APC_3: 0x0
9921 22:14:42.616008 INFO: [APUAPC] D14_APC_0: 0xffffffff
9922 22:14:42.619335 INFO: [APUAPC] D14_APC_1: 0xffffffff
9923 22:14:42.622449 INFO: [APUAPC] D14_APC_2: 0x3fffff
9924 22:14:42.625524 INFO: [APUAPC] D14_APC_3: 0x0
9925 22:14:42.629097 INFO: [APUAPC] D15_APC_0: 0xffffffff
9926 22:14:42.632313 INFO: [APUAPC] D15_APC_1: 0xffffffff
9927 22:14:42.635513 INFO: [APUAPC] D15_APC_2: 0x3fffff
9928 22:14:42.638974 INFO: [APUAPC] D15_APC_3: 0x0
9929 22:14:42.639048 INFO: [APUAPC] APC_CON: 0x4
9930 22:14:42.642140 INFO: [NOCDAPC] D0_APC_0: 0x0
9931 22:14:42.645477 INFO: [NOCDAPC] D0_APC_1: 0x0
9932 22:14:42.648869 INFO: [NOCDAPC] D1_APC_0: 0x0
9933 22:14:42.652286 INFO: [NOCDAPC] D1_APC_1: 0xfff
9934 22:14:42.655493 INFO: [NOCDAPC] D2_APC_0: 0x0
9935 22:14:42.658680 INFO: [NOCDAPC] D2_APC_1: 0xfff
9936 22:14:42.661953 INFO: [NOCDAPC] D3_APC_0: 0x0
9937 22:14:42.665557 INFO: [NOCDAPC] D3_APC_1: 0xfff
9938 22:14:42.668637 INFO: [NOCDAPC] D4_APC_0: 0x0
9939 22:14:42.671733 INFO: [NOCDAPC] D4_APC_1: 0xfff
9940 22:14:42.671841 INFO: [NOCDAPC] D5_APC_0: 0x0
9941 22:14:42.674956 INFO: [NOCDAPC] D5_APC_1: 0xfff
9942 22:14:42.678682 INFO: [NOCDAPC] D6_APC_0: 0x0
9943 22:14:42.681537 INFO: [NOCDAPC] D6_APC_1: 0xfff
9944 22:14:42.685210 INFO: [NOCDAPC] D7_APC_0: 0x0
9945 22:14:42.688422 INFO: [NOCDAPC] D7_APC_1: 0xfff
9946 22:14:42.692124 INFO: [NOCDAPC] D8_APC_0: 0x0
9947 22:14:42.695378 INFO: [NOCDAPC] D8_APC_1: 0xfff
9948 22:14:42.698728 INFO: [NOCDAPC] D9_APC_0: 0x0
9949 22:14:42.702095 INFO: [NOCDAPC] D9_APC_1: 0xfff
9950 22:14:42.704966 INFO: [NOCDAPC] D10_APC_0: 0x0
9951 22:14:42.708574 INFO: [NOCDAPC] D10_APC_1: 0xfff
9952 22:14:42.708661 INFO: [NOCDAPC] D11_APC_0: 0x0
9953 22:14:42.711639 INFO: [NOCDAPC] D11_APC_1: 0xfff
9954 22:14:42.714883 INFO: [NOCDAPC] D12_APC_0: 0x0
9955 22:14:42.718116 INFO: [NOCDAPC] D12_APC_1: 0xfff
9956 22:14:42.721337 INFO: [NOCDAPC] D13_APC_0: 0x0
9957 22:14:42.724521 INFO: [NOCDAPC] D13_APC_1: 0xfff
9958 22:14:42.728050 INFO: [NOCDAPC] D14_APC_0: 0x0
9959 22:14:42.731051 INFO: [NOCDAPC] D14_APC_1: 0xfff
9960 22:14:42.734408 INFO: [NOCDAPC] D15_APC_0: 0x0
9961 22:14:42.737717 INFO: [NOCDAPC] D15_APC_1: 0xfff
9962 22:14:42.741594 INFO: [NOCDAPC] APC_CON: 0x4
9963 22:14:42.744398 INFO: [APUAPC] set_apusys_apc done
9964 22:14:42.747965 INFO: [DEVAPC] devapc_init done
9965 22:14:42.751204 INFO: GICv3 without legacy support detected.
9966 22:14:42.754238 INFO: ARM GICv3 driver initialized in EL3
9967 22:14:42.757793 INFO: Maximum SPI INTID supported: 639
9968 22:14:42.764005 INFO: BL31: Initializing runtime services
9969 22:14:42.767623 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
9970 22:14:42.770920 INFO: SPM: enable CPC mode
9971 22:14:42.777215 INFO: mcdi ready for mcusys-off-idle and system suspend
9972 22:14:42.780473 INFO: BL31: Preparing for EL3 exit to normal world
9973 22:14:42.783731 INFO: Entry point address = 0x80000000
9974 22:14:42.787307 INFO: SPSR = 0x8
9975 22:14:42.792531
9976 22:14:42.792613
9977 22:14:42.792696
9978 22:14:42.796282 Starting depthcharge on Spherion...
9979 22:14:42.796365
9980 22:14:42.796448 Wipe memory regions:
9981 22:14:42.796526
9982 22:14:42.797316 end: 2.2.3 depthcharge-start (duration 00:00:29) [common]
9983 22:14:42.797451 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
9984 22:14:42.797546 Setting prompt string to ['asurada:']
9985 22:14:42.797639 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
9986 22:14:42.799508 [0x00000040000000, 0x00000054600000)
9987 22:14:42.921760
9988 22:14:42.924828 [0x00000054660000, 0x00000080000000)
9989 22:14:43.182464
9990 22:14:43.182606 [0x000000821a7280, 0x000000ffe64000)
9991 22:14:43.927677
9992 22:14:43.928234 [0x00000100000000, 0x00000240000000)
9993 22:14:45.817839
9994 22:14:45.821421 Initializing XHCI USB controller at 0x11200000.
9995 22:14:46.859516
9996 22:14:46.862518 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
9997 22:14:46.862956
9998 22:14:46.863416
9999 22:14:46.863863
10000 22:14:46.864820 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10002 22:14:46.966021 asurada: tftpboot 192.168.201.1 10597245/tftp-deploy-igpa52ow/kernel/image.itb 10597245/tftp-deploy-igpa52ow/kernel/cmdline
10003 22:14:46.966644 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10004 22:14:46.967049 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10005 22:14:46.971426 tftpboot 192.168.201.1 10597245/tftp-deploy-igpa52ow/kernel/image.itbtp-deploy-igpa52ow/kernel/cmdline
10006 22:14:46.971849
10007 22:14:46.972223 Waiting for link
10008 22:14:47.130066
10009 22:14:47.130582 R8152: Initializing
10010 22:14:47.130917
10011 22:14:47.133229 Version 6 (ocp_data = 5c30)
10012 22:14:47.133645
10013 22:14:47.136697 R8152: Done initializing
10014 22:14:47.137111
10015 22:14:47.137440 Adding net device
10016 22:14:49.069793
10017 22:14:49.070266 done.
10018 22:14:49.070599
10019 22:14:49.070906 MAC: 00:24:32:30:7c:7b
10020 22:14:49.071208
10021 22:14:49.072403 Sending DHCP discover... done.
10022 22:14:49.072828
10023 22:14:53.778403 Waiting for reply... done.
10024 22:14:53.778909
10025 22:14:53.779237 Sending DHCP request... done.
10026 22:14:53.780854
10027 22:14:53.786522 Waiting for reply... done.
10028 22:14:53.787031
10029 22:14:53.787494 My ip is 192.168.201.14
10030 22:14:53.787847
10031 22:14:53.789983 The DHCP server ip is 192.168.201.1
10032 22:14:53.790390
10033 22:14:53.795379 TFTP server IP predefined by user: 192.168.201.1
10034 22:14:53.795467
10035 22:14:53.802056 Bootfile predefined by user: 10597245/tftp-deploy-igpa52ow/kernel/image.itb
10036 22:14:53.802140
10037 22:14:53.805784 Sending tftp read request... done.
10038 22:14:53.805878
10039 22:14:53.805943 Waiting for the transfer...
10040 22:14:53.806003
10041 22:14:54.398141 00000000 ################################################################
10042 22:14:54.398282
10043 22:14:54.972727 00080000 ################################################################
10044 22:14:54.972861
10045 22:14:55.572841 00100000 ################################################################
10046 22:14:55.573012
10047 22:14:56.175004 00180000 ################################################################
10048 22:14:56.175147
10049 22:14:56.788403 00200000 ################################################################
10050 22:14:56.788553
10051 22:14:57.380162 00280000 ################################################################
10052 22:14:57.380308
10053 22:14:57.969081 00300000 ################################################################
10054 22:14:57.969227
10055 22:14:58.560700 00380000 ################################################################
10056 22:14:58.560834
10057 22:14:59.146450 00400000 ################################################################
10058 22:14:59.146595
10059 22:14:59.757627 00480000 ################################################################
10060 22:14:59.757773
10061 22:15:00.344769 00500000 ################################################################
10062 22:15:00.344915
10063 22:15:00.902381 00580000 ################################################################
10064 22:15:00.902528
10065 22:15:01.489071 00600000 ################################################################
10066 22:15:01.489215
10067 22:15:02.090157 00680000 ################################################################
10068 22:15:02.090295
10069 22:15:02.659920 00700000 ################################################################
10070 22:15:02.660119
10071 22:15:03.226974 00780000 ################################################################
10072 22:15:03.227109
10073 22:15:03.811557 00800000 ################################################################
10074 22:15:03.811689
10075 22:15:04.362514 00880000 ################################################################
10076 22:15:04.362642
10077 22:15:04.932603 00900000 ################################################################
10078 22:15:04.932739
10079 22:15:05.515708 00980000 ################################################################
10080 22:15:05.515844
10081 22:15:06.074064 00a00000 ################################################################
10082 22:15:06.074207
10083 22:15:06.648363 00a80000 ################################################################
10084 22:15:06.648507
10085 22:15:07.231389 00b00000 ################################################################
10086 22:15:07.231538
10087 22:15:07.844551 00b80000 ################################################################
10088 22:15:07.844696
10089 22:15:08.441756 00c00000 ################################################################
10090 22:15:08.441900
10091 22:15:09.010350 00c80000 ################################################################
10092 22:15:09.010496
10093 22:15:09.638622 00d00000 ################################################################
10094 22:15:09.639132
10095 22:15:10.241477 00d80000 ################################################################
10096 22:15:10.241607
10097 22:15:10.812887 00e00000 ################################################################
10098 22:15:10.813046
10099 22:15:11.402664 00e80000 ################################################################
10100 22:15:11.402810
10101 22:15:11.992954 00f00000 ################################################################
10102 22:15:11.993098
10103 22:15:12.582211 00f80000 ################################################################
10104 22:15:12.582355
10105 22:15:13.158403 01000000 ################################################################
10106 22:15:13.158538
10107 22:15:13.724780 01080000 ################################################################
10108 22:15:13.724911
10109 22:15:14.294365 01100000 ################################################################
10110 22:15:14.294501
10111 22:15:14.869210 01180000 ################################################################
10112 22:15:14.869343
10113 22:15:15.435887 01200000 ################################################################
10114 22:15:15.436022
10115 22:15:15.995515 01280000 ################################################################
10116 22:15:15.995648
10117 22:15:16.565711 01300000 ################################################################
10118 22:15:16.565874
10119 22:15:17.210372 01380000 ################################################################
10120 22:15:17.211011
10121 22:15:17.818077 01400000 ################################################################
10122 22:15:17.818222
10123 22:15:18.394310 01480000 ################################################################
10124 22:15:18.394841
10125 22:15:19.041665 01500000 ################################################################
10126 22:15:19.042200
10127 22:15:19.705699 01580000 ################################################################
10128 22:15:19.706213
10129 22:15:20.369736 01600000 ################################################################
10130 22:15:20.370358
10131 22:15:21.016656 01680000 ################################################################
10132 22:15:21.016803
10133 22:15:21.608705 01700000 ################################################################
10134 22:15:21.609214
10135 22:15:22.277649 01780000 ################################################################
10136 22:15:22.278173
10137 22:15:22.989835 01800000 ################################################################
10138 22:15:22.990368
10139 22:15:23.725727 01880000 ################################################################
10140 22:15:23.726347
10141 22:15:24.408040 01900000 ################################################################
10142 22:15:24.408180
10143 22:15:25.111273 01980000 ################################################################
10144 22:15:25.111823
10145 22:15:25.789568 01a00000 ################################################################
10146 22:15:25.789705
10147 22:15:26.358882 01a80000 ################################################################
10148 22:15:26.359018
10149 22:15:26.954324 01b00000 ################################################################
10150 22:15:26.954810
10151 22:15:27.635468 01b80000 ################################################################
10152 22:15:27.635609
10153 22:15:28.210451 01c00000 ################################################################
10154 22:15:28.210579
10155 22:15:28.777356 01c80000 ################################################################
10156 22:15:28.777504
10157 22:15:29.347558 01d00000 ################################################################
10158 22:15:29.347697
10159 22:15:29.935259 01d80000 ################################################################
10160 22:15:29.935410
10161 22:15:30.504541 01e00000 ################################################################
10162 22:15:30.504689
10163 22:15:31.095547 01e80000 ################################################################
10164 22:15:31.095697
10165 22:15:31.682230 01f00000 ################################################################
10166 22:15:31.682718
10167 22:15:32.294428 01f80000 ################################################################
10168 22:15:32.294579
10169 22:15:32.898088 02000000 ################################################################
10170 22:15:32.898232
10171 22:15:33.502861 02080000 ################################################################
10172 22:15:33.503010
10173 22:15:34.104582 02100000 ################################################################
10174 22:15:34.104729
10175 22:15:34.707260 02180000 ################################################################
10176 22:15:34.707408
10177 22:15:35.313601 02200000 ################################################################
10178 22:15:35.313758
10179 22:15:35.918163 02280000 ################################################################
10180 22:15:35.918312
10181 22:15:36.527578 02300000 ################################################################
10182 22:15:36.527722
10183 22:15:37.132504 02380000 ################################################################
10184 22:15:37.132687
10185 22:15:37.736208 02400000 ################################################################
10186 22:15:37.736356
10187 22:15:38.338793 02480000 ################################################################
10188 22:15:38.338943
10189 22:15:38.944712 02500000 ################################################################
10190 22:15:38.944898
10191 22:15:39.543825 02580000 ################################################################
10192 22:15:39.543972
10193 22:15:40.138790 02600000 ################################################################
10194 22:15:40.138938
10195 22:15:40.742132 02680000 ################################################################
10196 22:15:40.742280
10197 22:15:41.349467 02700000 ################################################################
10198 22:15:41.349617
10199 22:15:41.950088 02780000 ################################################################
10200 22:15:41.950242
10201 22:15:42.520815 02800000 ################################################################
10202 22:15:42.520954
10203 22:15:43.120325 02880000 ################################################################
10204 22:15:43.120484
10205 22:15:43.713000 02900000 ################################################################
10206 22:15:43.713143
10207 22:15:44.284767 02980000 ################################################################
10208 22:15:44.284921
10209 22:15:44.868704 02a00000 ################################################################
10210 22:15:44.868856
10211 22:15:45.451312 02a80000 ################################################################
10212 22:15:45.451473
10213 22:15:46.047958 02b00000 ################################################################
10214 22:15:46.048155
10215 22:15:46.625599 02b80000 ################################################################
10216 22:15:46.625798
10217 22:15:47.206979 02c00000 ################################################################
10218 22:15:47.207175
10219 22:15:47.794446 02c80000 ################################################################
10220 22:15:47.794601
10221 22:15:48.389792 02d00000 ################################################################
10222 22:15:48.389947
10223 22:15:48.979225 02d80000 ################################################################
10224 22:15:48.979376
10225 22:15:49.567875 02e00000 ################################################################
10226 22:15:49.568025
10227 22:15:50.135326 02e80000 ################################################################
10228 22:15:50.135470
10229 22:15:50.697690 02f00000 ################################################################
10230 22:15:50.697842
10231 22:15:51.273766 02f80000 ################################################################
10232 22:15:51.273912
10233 22:15:51.837670 03000000 ################################################################
10234 22:15:51.837821
10235 22:15:52.420467 03080000 ################################################################
10236 22:15:52.420619
10237 22:15:53.004495 03100000 ################################################################
10238 22:15:53.004629
10239 22:15:53.586417 03180000 ################################################################
10240 22:15:53.586569
10241 22:15:54.176362 03200000 ################################################################
10242 22:15:54.176524
10243 22:15:54.768627 03280000 ################################################################
10244 22:15:54.768782
10245 22:15:55.361443 03300000 ################################################################
10246 22:15:55.361589
10247 22:15:55.956352 03380000 ################################################################
10248 22:15:55.956503
10249 22:15:56.630534 03400000 ################################################################
10250 22:15:56.630684
10251 22:15:57.204994 03480000 ################################################################
10252 22:15:57.205137
10253 22:15:57.784743 03500000 ################################################################
10254 22:15:57.784923
10255 22:15:58.389289 03580000 ################################################################
10256 22:15:58.389444
10257 22:15:58.957320 03600000 ################################################################
10258 22:15:58.957464
10259 22:15:59.514613 03680000 ################################################################
10260 22:15:59.514752
10261 22:16:00.064798 03700000 ################################################################
10262 22:16:00.064933
10263 22:16:00.619675 03780000 ################################################################
10264 22:16:00.619809
10265 22:16:01.195469 03800000 ################################################################
10266 22:16:01.195604
10267 22:16:01.770361 03880000 ################################################################
10268 22:16:01.770496
10269 22:16:02.353587 03900000 ################################################################
10270 22:16:02.353724
10271 22:16:02.950347 03980000 ################################################################
10272 22:16:02.950485
10273 22:16:03.546473 03a00000 ################################################################
10274 22:16:03.546623
10275 22:16:04.132814 03a80000 ################################################################
10276 22:16:04.132959
10277 22:16:04.709381 03b00000 ################################################################
10278 22:16:04.709525
10279 22:16:05.278615 03b80000 ################################################################
10280 22:16:05.278766
10281 22:16:05.852398 03c00000 ################################################################
10282 22:16:05.852536
10283 22:16:06.426989 03c80000 ################################################################
10284 22:16:06.427134
10285 22:16:06.981324 03d00000 ################################################################
10286 22:16:06.981478
10287 22:16:07.535554 03d80000 ################################################################
10288 22:16:07.535704
10289 22:16:08.099232 03e00000 ################################################################
10290 22:16:08.099388
10291 22:16:08.654830 03e80000 ################################################################
10292 22:16:08.654973
10293 22:16:09.116889 03f00000 ##################################################### done.
10294 22:16:09.117034
10295 22:16:09.120198 The bootfile was 66492078 bytes long.
10296 22:16:09.120299
10297 22:16:09.123845 Sending tftp read request... done.
10298 22:16:09.123927
10299 22:16:09.123992 Waiting for the transfer...
10300 22:16:09.124083
10301 22:16:09.127095 00000000 # done.
10302 22:16:09.127177
10303 22:16:09.133247 Command line loaded dynamically from TFTP file: 10597245/tftp-deploy-igpa52ow/kernel/cmdline
10304 22:16:09.133329
10305 22:16:09.146165 The command line is: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10306 22:16:09.146249
10307 22:16:09.146315 Loading FIT.
10308 22:16:09.146376
10309 22:16:09.149656 Image ramdisk-1 has 56360813 bytes.
10310 22:16:09.149739
10311 22:16:09.152876 Image fdt-1 has 46924 bytes.
10312 22:16:09.152957
10313 22:16:09.156086 Image kernel-1 has 10082307 bytes.
10314 22:16:09.156167
10315 22:16:09.166385 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10316 22:16:09.166466
10317 22:16:09.182556 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10318 22:16:09.182643
10319 22:16:09.189479 Choosing best match conf-1 for compat google,spherion-rev2.
10320 22:16:09.189561
10321 22:16:09.196980 Connected to device vid:did:rid of 1ae0:0028:00
10322 22:16:09.203452
10323 22:16:09.206893 tpm_get_response: command 0x17b, return code 0x0
10324 22:16:09.206974
10325 22:16:09.210138 ec_init: CrosEC protocol v3 supported (256, 248)
10326 22:16:09.213861
10327 22:16:09.217130 tpm_cleanup: add release locality here.
10328 22:16:09.217211
10329 22:16:09.217276 Shutting down all USB controllers.
10330 22:16:09.220628
10331 22:16:09.220709 Removing current net device
10332 22:16:09.220774
10333 22:16:09.227210 Exiting depthcharge with code 4 at timestamp: 115651169
10334 22:16:09.227292
10335 22:16:09.230351 LZMA decompressing kernel-1 to 0x821a6718
10336 22:16:09.230433
10337 22:16:09.233288 LZMA decompressing kernel-1 to 0x40000000
10338 22:16:10.501009
10339 22:16:10.501159 jumping to kernel
10340 22:16:10.501591 end: 2.2.4 bootloader-commands (duration 00:01:28) [common]
10341 22:16:10.501695 start: 2.2.5 auto-login-action (timeout 00:02:58) [common]
10342 22:16:10.501774 Setting prompt string to ['Linux version [0-9]']
10343 22:16:10.501843 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10344 22:16:10.501910 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10345 22:16:10.582837
10346 22:16:10.585671 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10347 22:16:10.589452 start: 2.2.5.1 login-action (timeout 00:02:58) [common]
10348 22:16:10.589546 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10349 22:16:10.589632 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10350 22:16:10.589707 Using line separator: #'\n'#
10351 22:16:10.589768 No login prompt set.
10352 22:16:10.589832 Parsing kernel messages
10353 22:16:10.589887 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10354 22:16:10.589989 [login-action] Waiting for messages, (timeout 00:02:58)
10355 22:16:10.609053 [ 0.000000] Linux version 6.1.31 (KernelCI@build-j1612341-arm64-gcc-10-defconfig-arm64-chromebook-n674v) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Mon Jun 5 22:04:07 UTC 2023
10356 22:16:10.611885 [ 0.000000] random: crng init done
10357 22:16:10.618499 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10358 22:16:10.621750 [ 0.000000] efi: UEFI not found.
10359 22:16:10.628894 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10360 22:16:10.635475 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10361 22:16:10.645016 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10362 22:16:10.654913 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10363 22:16:10.661676 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10364 22:16:10.668224 [ 0.000000] printk: bootconsole [mtk8250] enabled
10365 22:16:10.674692 [ 0.000000] NUMA: No NUMA configuration found
10366 22:16:10.681206 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10367 22:16:10.684616 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcda00-0x23efcffff]
10368 22:16:10.688305 [ 0.000000] Zone ranges:
10369 22:16:10.694067 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10370 22:16:10.697779 [ 0.000000] DMA32 empty
10371 22:16:10.704352 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10372 22:16:10.707654 [ 0.000000] Movable zone start for each node
10373 22:16:10.710763 [ 0.000000] Early memory node ranges
10374 22:16:10.717401 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10375 22:16:10.723882 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10376 22:16:10.731382 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10377 22:16:10.737313 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10378 22:16:10.743755 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10379 22:16:10.750033 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10380 22:16:10.806661 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10381 22:16:10.813313 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10382 22:16:10.819988 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10383 22:16:10.823139 [ 0.000000] psci: probing for conduit method from DT.
10384 22:16:10.829941 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10385 22:16:10.833046 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10386 22:16:10.839935 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10387 22:16:10.843158 [ 0.000000] psci: SMC Calling Convention v1.2
10388 22:16:10.849657 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10389 22:16:10.853046 [ 0.000000] Detected VIPT I-cache on CPU0
10390 22:16:10.859739 [ 0.000000] CPU features: detected: GIC system register CPU interface
10391 22:16:10.865811 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10392 22:16:10.873074 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10393 22:16:10.879176 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10394 22:16:10.886168 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10395 22:16:10.895651 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10396 22:16:10.898838 [ 0.000000] alternatives: applying boot alternatives
10397 22:16:10.905651 [ 0.000000] Fallback order for Node 0: 0
10398 22:16:10.911642 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10399 22:16:10.915059 [ 0.000000] Policy zone: Normal
10400 22:16:10.928627 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10401 22:16:10.938867 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10402 22:16:10.948671 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10403 22:16:10.959005 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10404 22:16:10.964991 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10405 22:16:10.968279 <6>[ 0.000000] software IO TLB: area num 8.
10406 22:16:11.025173 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10407 22:16:11.174192 <6>[ 0.000000] Memory: 7917900K/8385536K available (17984K kernel code, 4098K rwdata, 14068K rodata, 8384K init, 615K bss, 434868K reserved, 32768K cma-reserved)
10408 22:16:11.180474 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10409 22:16:11.187653 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10410 22:16:11.190438 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10411 22:16:11.197988 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10412 22:16:11.203530 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10413 22:16:11.207020 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10414 22:16:11.216867 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10415 22:16:11.224327 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10416 22:16:11.230860 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10417 22:16:11.236461 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10418 22:16:11.239966 <6>[ 0.000000] GICv3: 608 SPIs implemented
10419 22:16:11.243409 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10420 22:16:11.249889 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10421 22:16:11.253303 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10422 22:16:11.259886 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10423 22:16:11.273549 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10424 22:16:11.285795 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10425 22:16:11.292617 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10426 22:16:11.300347 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10427 22:16:11.313519 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10428 22:16:11.320581 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10429 22:16:11.327056 <6>[ 0.009173] Console: colour dummy device 80x25
10430 22:16:11.336998 <6>[ 0.013900] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10431 22:16:11.343309 <6>[ 0.024407] pid_max: default: 32768 minimum: 301
10432 22:16:11.346878 <6>[ 0.029280] LSM: Security Framework initializing
10433 22:16:11.353217 <6>[ 0.034220] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10434 22:16:11.363046 <6>[ 0.042033] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10435 22:16:11.372951 <6>[ 0.051526] cblist_init_generic: Setting adjustable number of callback queues.
10436 22:16:11.379909 <6>[ 0.058981] cblist_init_generic: Setting shift to 3 and lim to 1.
10437 22:16:11.382501 <6>[ 0.065321] cblist_init_generic: Setting shift to 3 and lim to 1.
10438 22:16:11.389359 <6>[ 0.071726] rcu: Hierarchical SRCU implementation.
10439 22:16:11.395945 <6>[ 0.076740] rcu: Max phase no-delay instances is 1000.
10440 22:16:11.402622 <6>[ 0.083764] EFI services will not be available.
10441 22:16:11.405718 <6>[ 0.088737] smp: Bringing up secondary CPUs ...
10442 22:16:11.413872 <6>[ 0.093793] Detected VIPT I-cache on CPU1
10443 22:16:11.420899 <6>[ 0.093865] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10444 22:16:11.427149 <6>[ 0.093896] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10445 22:16:11.430398 <6>[ 0.094231] Detected VIPT I-cache on CPU2
10446 22:16:11.437311 <6>[ 0.094279] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10447 22:16:11.447042 <6>[ 0.094295] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10448 22:16:11.450414 <6>[ 0.094552] Detected VIPT I-cache on CPU3
10449 22:16:11.457268 <6>[ 0.094597] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10450 22:16:11.463550 <6>[ 0.094611] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10451 22:16:11.466748 <6>[ 0.094916] CPU features: detected: Spectre-v4
10452 22:16:11.473381 <6>[ 0.094923] CPU features: detected: Spectre-BHB
10453 22:16:11.476965 <6>[ 0.094929] Detected PIPT I-cache on CPU4
10454 22:16:11.483408 <6>[ 0.094987] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10455 22:16:11.490968 <6>[ 0.095003] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10456 22:16:11.496534 <6>[ 0.095298] Detected PIPT I-cache on CPU5
10457 22:16:11.503235 <6>[ 0.095364] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10458 22:16:11.509701 <6>[ 0.095381] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10459 22:16:11.513350 <6>[ 0.095665] Detected PIPT I-cache on CPU6
10460 22:16:11.520008 <6>[ 0.095730] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10461 22:16:11.526125 <6>[ 0.095747] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10462 22:16:11.532631 <6>[ 0.096045] Detected PIPT I-cache on CPU7
10463 22:16:11.539270 <6>[ 0.096109] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10464 22:16:11.545717 <6>[ 0.096126] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10465 22:16:11.549498 <6>[ 0.096174] smp: Brought up 1 node, 8 CPUs
10466 22:16:11.555608 <6>[ 0.237582] SMP: Total of 8 processors activated.
10467 22:16:11.559111 <6>[ 0.242533] CPU features: detected: 32-bit EL0 Support
10468 22:16:11.569073 <6>[ 0.247929] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10469 22:16:11.575887 <6>[ 0.256729] CPU features: detected: Common not Private translations
10470 22:16:11.582289 <6>[ 0.263205] CPU features: detected: CRC32 instructions
10471 22:16:11.588608 <6>[ 0.268556] CPU features: detected: RCpc load-acquire (LDAPR)
10472 22:16:11.591585 <6>[ 0.274516] CPU features: detected: LSE atomic instructions
10473 22:16:11.598898 <6>[ 0.280298] CPU features: detected: Privileged Access Never
10474 22:16:11.605262 <6>[ 0.286077] CPU features: detected: RAS Extension Support
10475 22:16:11.611828 <6>[ 0.291686] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10476 22:16:11.614768 <6>[ 0.298906] CPU: All CPU(s) started at EL2
10477 22:16:11.621594 <6>[ 0.303249] alternatives: applying system-wide alternatives
10478 22:16:11.631319 <6>[ 0.313950] devtmpfs: initialized
10479 22:16:11.646857 <6>[ 0.322878] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10480 22:16:11.653969 <6>[ 0.332839] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10481 22:16:11.660420 <6>[ 0.341008] pinctrl core: initialized pinctrl subsystem
10482 22:16:11.663388 <6>[ 0.347643] DMI not present or invalid.
10483 22:16:11.670299 <6>[ 0.352046] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10484 22:16:11.680266 <6>[ 0.358912] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10485 22:16:11.686829 <6>[ 0.366487] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10486 22:16:11.696485 <6>[ 0.374707] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10487 22:16:11.699626 <6>[ 0.382946] audit: initializing netlink subsys (disabled)
10488 22:16:11.709181 <5>[ 0.388643] audit: type=2000 audit(0.276:1): state=initialized audit_enabled=0 res=1
10489 22:16:11.716047 <6>[ 0.389341] thermal_sys: Registered thermal governor 'step_wise'
10490 22:16:11.722795 <6>[ 0.396605] thermal_sys: Registered thermal governor 'power_allocator'
10491 22:16:11.726136 <6>[ 0.402864] cpuidle: using governor menu
10492 22:16:11.732766 <6>[ 0.413825] NET: Registered PF_QIPCRTR protocol family
10493 22:16:11.739124 <6>[ 0.419300] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10494 22:16:11.745971 <6>[ 0.426399] ASID allocator initialised with 32768 entries
10495 22:16:11.748953 <6>[ 0.432959] Serial: AMBA PL011 UART driver
10496 22:16:11.759113 <4>[ 0.441529] Trying to register duplicate clock ID: 134
10497 22:16:11.813097 <6>[ 0.498663] KASLR enabled
10498 22:16:11.827263 <6>[ 0.506376] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10499 22:16:11.833637 <6>[ 0.513392] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10500 22:16:11.840797 <6>[ 0.519881] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10501 22:16:11.847321 <6>[ 0.526885] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10502 22:16:11.853703 <6>[ 0.533372] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10503 22:16:11.860495 <6>[ 0.540376] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10504 22:16:11.866693 <6>[ 0.546866] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10505 22:16:11.873147 <6>[ 0.553868] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10506 22:16:11.876621 <6>[ 0.561352] ACPI: Interpreter disabled.
10507 22:16:11.885689 <6>[ 0.567772] iommu: Default domain type: Translated
10508 22:16:11.892438 <6>[ 0.572887] iommu: DMA domain TLB invalidation policy: strict mode
10509 22:16:11.895225 <5>[ 0.579543] SCSI subsystem initialized
10510 22:16:11.901568 <6>[ 0.583783] usbcore: registered new interface driver usbfs
10511 22:16:11.908504 <6>[ 0.589513] usbcore: registered new interface driver hub
10512 22:16:11.911742 <6>[ 0.595069] usbcore: registered new device driver usb
10513 22:16:11.919107 <6>[ 0.601174] pps_core: LinuxPPS API ver. 1 registered
10514 22:16:11.928873 <6>[ 0.606370] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10515 22:16:11.931649 <6>[ 0.615714] PTP clock support registered
10516 22:16:11.935073 <6>[ 0.619953] EDAC MC: Ver: 3.0.0
10517 22:16:11.942690 <6>[ 0.625133] FPGA manager framework
10518 22:16:11.949163 <6>[ 0.628808] Advanced Linux Sound Architecture Driver Initialized.
10519 22:16:11.952202 <6>[ 0.635567] vgaarb: loaded
10520 22:16:11.959164 <6>[ 0.638658] clocksource: Switched to clocksource arch_sys_counter
10521 22:16:11.962245 <5>[ 0.645105] VFS: Disk quotas dquot_6.6.0
10522 22:16:11.969285 <6>[ 0.649292] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10523 22:16:11.971951 <6>[ 0.656483] pnp: PnP ACPI: disabled
10524 22:16:11.980803 <6>[ 0.663147] NET: Registered PF_INET protocol family
10525 22:16:11.991173 <6>[ 0.668732] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10526 22:16:12.001673 <6>[ 0.681023] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10527 22:16:12.011643 <6>[ 0.689841] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10528 22:16:12.018414 <6>[ 0.697813] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10529 22:16:12.028632 <6>[ 0.706514] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10530 22:16:12.034806 <6>[ 0.716259] TCP: Hash tables configured (established 65536 bind 65536)
10531 22:16:12.041975 <6>[ 0.723118] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10532 22:16:12.051484 <6>[ 0.730313] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10533 22:16:12.057781 <6>[ 0.738017] NET: Registered PF_UNIX/PF_LOCAL protocol family
10534 22:16:12.064494 <6>[ 0.744179] RPC: Registered named UNIX socket transport module.
10535 22:16:12.068085 <6>[ 0.750334] RPC: Registered udp transport module.
10536 22:16:12.074471 <6>[ 0.755264] RPC: Registered tcp transport module.
10537 22:16:12.081247 <6>[ 0.760192] RPC: Registered tcp NFSv4.1 backchannel transport module.
10538 22:16:12.084518 <6>[ 0.766862] PCI: CLS 0 bytes, default 64
10539 22:16:12.088320 <6>[ 0.771239] Unpacking initramfs...
10540 22:16:12.104016 <6>[ 0.783239] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10541 22:16:12.114456 <6>[ 0.791896] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10542 22:16:12.117022 <6>[ 0.800738] kvm [1]: IPA Size Limit: 40 bits
10543 22:16:12.124314 <6>[ 0.805269] kvm [1]: GICv3: no GICV resource entry
10544 22:16:12.126967 <6>[ 0.810292] kvm [1]: disabling GICv2 emulation
10545 22:16:12.133908 <6>[ 0.814978] kvm [1]: GIC system register CPU interface enabled
10546 22:16:12.137386 <6>[ 0.821147] kvm [1]: vgic interrupt IRQ18
10547 22:16:12.143446 <6>[ 0.825510] kvm [1]: VHE mode initialized successfully
10548 22:16:12.149993 <5>[ 0.832052] Initialise system trusted keyrings
10549 22:16:12.156834 <6>[ 0.836881] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10550 22:16:12.164382 <6>[ 0.847019] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10551 22:16:12.170952 <5>[ 0.853418] NFS: Registering the id_resolver key type
10552 22:16:12.174410 <5>[ 0.858722] Key type id_resolver registered
10553 22:16:12.181147 <5>[ 0.863135] Key type id_legacy registered
10554 22:16:12.187962 <6>[ 0.867421] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10555 22:16:12.194852 <6>[ 0.874340] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10556 22:16:12.200783 <6>[ 0.882066] 9p: Installing v9fs 9p2000 file system support
10557 22:16:12.238649 <5>[ 0.921036] Key type asymmetric registered
10558 22:16:12.242096 <5>[ 0.925370] Asymmetric key parser 'x509' registered
10559 22:16:12.252181 <6>[ 0.930513] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10560 22:16:12.255391 <6>[ 0.938125] io scheduler mq-deadline registered
10561 22:16:12.258457 <6>[ 0.942886] io scheduler kyber registered
10562 22:16:12.277241 <6>[ 0.959653] EINJ: ACPI disabled.
10563 22:16:12.309615 <4>[ 0.985568] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10564 22:16:12.319973 <4>[ 0.996433] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10565 22:16:12.334833 <6>[ 1.017077] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10566 22:16:12.342723 <6>[ 1.024968] printk: console [ttyS0] disabled
10567 22:16:12.370943 <6>[ 1.049614] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10568 22:16:12.377093 <6>[ 1.059085] printk: console [ttyS0] enabled
10569 22:16:12.380156 <6>[ 1.059085] printk: console [ttyS0] enabled
10570 22:16:12.387404 <6>[ 1.067979] printk: bootconsole [mtk8250] disabled
10571 22:16:12.390437 <6>[ 1.067979] printk: bootconsole [mtk8250] disabled
10572 22:16:12.396946 <6>[ 1.079264] SuperH (H)SCI(F) driver initialized
10573 22:16:12.400436 <6>[ 1.084527] msm_serial: driver initialized
10574 22:16:12.414229 <6>[ 1.093459] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10575 22:16:12.424226 <6>[ 1.102008] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10576 22:16:12.430928 <6>[ 1.110550] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10577 22:16:12.440719 <6>[ 1.119178] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10578 22:16:12.450998 <6>[ 1.127883] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10579 22:16:12.457253 <6>[ 1.136595] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10580 22:16:12.467405 <6>[ 1.145135] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10581 22:16:12.474287 <6>[ 1.153950] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10582 22:16:12.484246 <6>[ 1.162494] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10583 22:16:12.495189 <6>[ 1.177822] loop: module loaded
10584 22:16:12.501637 <6>[ 1.183905] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10585 22:16:12.524452 <4>[ 1.207101] mtk-pmic-keys: Failed to locate of_node [id: -1]
10586 22:16:12.531425 <6>[ 1.213875] megasas: 07.719.03.00-rc1
10587 22:16:12.540761 <6>[ 1.223382] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10588 22:16:12.551712 <6>[ 1.234049] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10589 22:16:12.568872 <6>[ 1.250817] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10590 22:16:12.625405 <6>[ 1.301141] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9
10591 22:16:14.490489 <6>[ 3.173313] Freeing initrd memory: 55036K
10592 22:16:14.501048 <6>[ 3.183790] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10593 22:16:14.511853 <6>[ 3.194619] tun: Universal TUN/TAP device driver, 1.6
10594 22:16:14.515030 <6>[ 3.200670] thunder_xcv, ver 1.0
10595 22:16:14.518330 <6>[ 3.204179] thunder_bgx, ver 1.0
10596 22:16:14.521631 <6>[ 3.207677] nicpf, ver 1.0
10597 22:16:14.532787 <6>[ 3.211681] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10598 22:16:14.536340 <6>[ 3.219156] hns3: Copyright (c) 2017 Huawei Corporation.
10599 22:16:14.542005 <6>[ 3.224742] hclge is initializing
10600 22:16:14.545329 <6>[ 3.228317] e1000: Intel(R) PRO/1000 Network Driver
10601 22:16:14.552162 <6>[ 3.233446] e1000: Copyright (c) 1999-2006 Intel Corporation.
10602 22:16:14.556336 <6>[ 3.239462] e1000e: Intel(R) PRO/1000 Network Driver
10603 22:16:14.562166 <6>[ 3.244677] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10604 22:16:14.569077 <6>[ 3.250861] igb: Intel(R) Gigabit Ethernet Network Driver
10605 22:16:14.575169 <6>[ 3.256511] igb: Copyright (c) 2007-2014 Intel Corporation.
10606 22:16:14.581769 <6>[ 3.262347] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10607 22:16:14.588514 <6>[ 3.268864] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10608 22:16:14.591855 <6>[ 3.275325] sky2: driver version 1.30
10609 22:16:14.598785 <6>[ 3.280298] VFIO - User Level meta-driver version: 0.3
10610 22:16:14.605731 <6>[ 3.288502] usbcore: registered new interface driver usb-storage
10611 22:16:14.612394 <6>[ 3.294946] usbcore: registered new device driver onboard-usb-hub
10612 22:16:14.621572 <6>[ 3.303979] mt6397-rtc mt6359-rtc: registered as rtc0
10613 22:16:14.631217 <6>[ 3.309444] mt6397-rtc mt6359-rtc: setting system clock to 2023-06-05T22:16:19 UTC (1686003379)
10614 22:16:14.634702 <6>[ 3.319015] i2c_dev: i2c /dev entries driver
10615 22:16:14.651354 <6>[ 3.330706] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10616 22:16:14.658095 <6>[ 3.340881] sdhci: Secure Digital Host Controller Interface driver
10617 22:16:14.664723 <6>[ 3.347322] sdhci: Copyright(c) Pierre Ossman
10618 22:16:14.671305 <6>[ 3.352738] Synopsys Designware Multimedia Card Interface Driver
10619 22:16:14.674541 <6>[ 3.359382] mmc0: CQHCI version 5.10
10620 22:16:14.681285 <6>[ 3.359901] sdhci-pltfm: SDHCI platform and OF driver helper
10621 22:16:14.688688 <6>[ 3.371320] ledtrig-cpu: registered to indicate activity on CPUs
10622 22:16:14.699315 <6>[ 3.378669] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10623 22:16:14.702579 <6>[ 3.386051] usbcore: registered new interface driver usbhid
10624 22:16:14.709520 <6>[ 3.391883] usbhid: USB HID core driver
10625 22:16:14.715365 <6>[ 3.396127] spi_master spi0: will run message pump with realtime priority
10626 22:16:14.759250 <6>[ 3.435164] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10627 22:16:14.779446 <6>[ 3.451220] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10628 22:16:14.782315 <6>[ 3.464795] mmc0: Command Queue Engine enabled
10629 22:16:14.788979 <6>[ 3.467205] cros-ec-spi spi0.0: Chrome EC device registered
10630 22:16:14.795908 <6>[ 3.469531] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10631 22:16:14.799038 <6>[ 3.482561] mmcblk0: mmc0:0001 DA4128 116 GiB
10632 22:16:14.812045 <6>[ 3.491374] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10633 22:16:14.818719 <6>[ 3.492364] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10634 22:16:14.825651 <6>[ 3.502757] NET: Registered PF_PACKET protocol family
10635 22:16:14.828747 <6>[ 3.508083] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10636 22:16:14.835034 <6>[ 3.512020] 9pnet: Installing 9P2000 support
10637 22:16:14.838385 <6>[ 3.517746] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10638 22:16:14.844996 <5>[ 3.521699] Key type dns_resolver registered
10639 22:16:14.851572 <6>[ 3.527506] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10640 22:16:14.854916 <6>[ 3.531940] registered taskstats version 1
10641 22:16:14.858505 <5>[ 3.542303] Loading compiled-in X.509 certificates
10642 22:16:14.894159 <4>[ 3.570302] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10643 22:16:14.903852 <4>[ 3.580984] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10644 22:16:14.914301 <3>[ 3.593731] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10645 22:16:14.927101 <6>[ 3.609280] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10646 22:16:14.934083 <6>[ 3.616020] xhci-mtk 11200000.usb: xHCI Host Controller
10647 22:16:14.939780 <6>[ 3.621521] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10648 22:16:14.949859 <6>[ 3.629381] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10649 22:16:14.956719 <6>[ 3.638842] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10650 22:16:14.963591 <6>[ 3.645027] xhci-mtk 11200000.usb: xHCI Host Controller
10651 22:16:14.969644 <6>[ 3.650522] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10652 22:16:14.976697 <6>[ 3.658184] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10653 22:16:14.984027 <6>[ 3.666077] hub 1-0:1.0: USB hub found
10654 22:16:14.987107 <6>[ 3.670132] hub 1-0:1.0: 1 port detected
10655 22:16:14.996783 <6>[ 3.674484] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10656 22:16:14.999582 <6>[ 3.683339] hub 2-0:1.0: USB hub found
10657 22:16:15.003283 <6>[ 3.687376] hub 2-0:1.0: 1 port detected
10658 22:16:15.011398 <6>[ 3.694453] mtk-msdc 11f70000.mmc: Got CD GPIO
10659 22:16:15.028206 <6>[ 3.707277] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10660 22:16:15.034525 <6>[ 3.715300] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10661 22:16:15.044730 <4>[ 3.723371] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10662 22:16:15.054507 <6>[ 3.733048] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10663 22:16:15.060741 <6>[ 3.741178] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10664 22:16:15.070856 <6>[ 3.749211] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10665 22:16:15.077387 <6>[ 3.757168] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10666 22:16:15.083987 <6>[ 3.764993] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10667 22:16:15.093536 <6>[ 3.772847] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10668 22:16:15.104038 <6>[ 3.783490] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10669 22:16:15.113738 <6>[ 3.791902] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10670 22:16:15.120734 <6>[ 3.800254] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10671 22:16:15.130256 <6>[ 3.808624] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10672 22:16:15.137153 <6>[ 3.816970] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10673 22:16:15.146971 <6>[ 3.825342] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10674 22:16:15.153927 <6>[ 3.833688] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10675 22:16:15.164263 <6>[ 3.842056] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10676 22:16:15.171315 <6>[ 3.850400] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10677 22:16:15.180352 <6>[ 3.858765] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10678 22:16:15.186917 <6>[ 3.867108] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10679 22:16:15.196713 <6>[ 3.875451] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10680 22:16:15.203511 <6>[ 3.883794] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10681 22:16:15.213362 <6>[ 3.892138] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10682 22:16:15.219493 <6>[ 3.900481] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10683 22:16:15.227093 <6>[ 3.909390] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10684 22:16:15.233823 <6>[ 3.916846] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10685 22:16:15.241205 <6>[ 3.923946] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10686 22:16:15.251504 <6>[ 3.931109] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10687 22:16:15.257955 <6>[ 3.938441] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10688 22:16:15.268197 <6>[ 3.945381] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10689 22:16:15.274758 <6>[ 3.954523] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10690 22:16:15.284604 <6>[ 3.963650] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10691 22:16:15.294337 <6>[ 3.972996] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10692 22:16:15.304744 <6>[ 3.982603] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10693 22:16:15.314444 <6>[ 3.992082] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10694 22:16:15.324121 <6>[ 4.001210] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10695 22:16:15.330697 <6>[ 4.010684] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10696 22:16:15.340862 <6>[ 4.019813] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10697 22:16:15.350626 <6>[ 4.029121] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10698 22:16:15.360777 <6>[ 4.039287] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10699 22:16:15.371586 <6>[ 4.051260] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10700 22:16:15.427536 <6>[ 4.106979] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10701 22:16:15.581251 <6>[ 4.264345] hub 1-1:1.0: USB hub found
10702 22:16:15.585157 <6>[ 4.268830] hub 1-1:1.0: 4 ports detected
10703 22:16:15.707394 <6>[ 4.387085] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10704 22:16:15.732701 <6>[ 4.415139] hub 2-1:1.0: USB hub found
10705 22:16:15.735665 <6>[ 4.419534] hub 2-1:1.0: 3 ports detected
10706 22:16:15.907211 <6>[ 4.586941] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10707 22:16:16.040491 <6>[ 4.723199] hub 1-1.4:1.0: USB hub found
10708 22:16:16.043442 <6>[ 4.727826] hub 1-1.4:1.0: 2 ports detected
10709 22:16:16.119476 <6>[ 4.799181] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10710 22:16:16.339477 <6>[ 5.018940] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10711 22:16:16.531159 <6>[ 5.210942] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10712 22:16:27.643942 <6>[ 16.331498] ALSA device list:
10713 22:16:27.650604 <6>[ 16.334753] No soundcards found.
10714 22:16:27.662948 <6>[ 16.347178] Freeing unused kernel memory: 8384K
10715 22:16:27.666568 <6>[ 16.352110] Run /init as init process
10716 22:16:27.696989 <6>[ 16.380898] NET: Registered PF_INET6 protocol family
10717 22:16:27.703750 <6>[ 16.387705] Segment Routing with IPv6
10718 22:16:27.707463 <6>[ 16.391670] In-situ OAM (IOAM) with IPv6
10719 22:16:27.741043 <30>[ 16.405895] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10720 22:16:27.744775 <30>[ 16.429894] systemd[1]: Detected architecture arm64.
10721 22:16:27.747961
10722 22:16:27.751238 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10723 22:16:27.751320
10724 22:16:27.767006 <30>[ 16.451148] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10725 22:16:27.905331 <30>[ 16.586366] systemd[1]: Queued start job for default target Graphical Interface.
10726 22:16:27.948447 <30>[ 16.632366] systemd[1]: Created slice system-getty.slice.
10727 22:16:27.954519 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10728 22:16:27.971593 <30>[ 16.655560] systemd[1]: Created slice system-modprobe.slice.
10729 22:16:27.977924 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10730 22:16:27.995612 <30>[ 16.679515] systemd[1]: Created slice system-serial\x2dgetty.slice.
10731 22:16:28.005101 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10732 22:16:28.019865 <30>[ 16.703969] systemd[1]: Created slice User and Session Slice.
10733 22:16:28.026076 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10734 22:16:28.046495 <30>[ 16.727495] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10735 22:16:28.056277 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10736 22:16:28.074556 <30>[ 16.755477] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10737 22:16:28.081747 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10738 22:16:28.101099 <30>[ 16.779028] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10739 22:16:28.107656 <30>[ 16.791061] systemd[1]: Reached target Local Encrypted Volumes.
10740 22:16:28.114249 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10741 22:16:28.131072 <30>[ 16.815301] systemd[1]: Reached target Paths.
10742 22:16:28.134252 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10743 22:16:28.150841 <30>[ 16.834974] systemd[1]: Reached target Remote File Systems.
10744 22:16:28.157381 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10745 22:16:28.170743 <30>[ 16.854967] systemd[1]: Reached target Slices.
10746 22:16:28.174056 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10747 22:16:28.190690 <30>[ 16.874983] systemd[1]: Reached target Swap.
10748 22:16:28.194031 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10749 22:16:28.214437 <30>[ 16.895278] systemd[1]: Listening on initctl Compatibility Named Pipe.
10750 22:16:28.220949 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10751 22:16:28.227480 <30>[ 16.910048] systemd[1]: Listening on Journal Audit Socket.
10752 22:16:28.233625 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10753 22:16:28.246698 <30>[ 16.931217] systemd[1]: Listening on Journal Socket (/dev/log).
10754 22:16:28.253619 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10755 22:16:28.271061 <30>[ 16.955241] systemd[1]: Listening on Journal Socket.
10756 22:16:28.277550 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10757 22:16:28.290776 <30>[ 16.975243] systemd[1]: Listening on udev Control Socket.
10758 22:16:28.297716 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10759 22:16:28.315201 <30>[ 16.999607] systemd[1]: Listening on udev Kernel Socket.
10760 22:16:28.322008 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10761 22:16:28.358928 <30>[ 17.043291] systemd[1]: Mounting Huge Pages File System...
10762 22:16:28.365431 Mounting [0;1;39mHuge Pages File System[0m...
10763 22:16:28.380648 <30>[ 17.064993] systemd[1]: Mounting POSIX Message Queue File System...
10764 22:16:28.387896 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10765 22:16:28.404678 <30>[ 17.089023] systemd[1]: Mounting Kernel Debug File System...
10766 22:16:28.412000 Mounting [0;1;39mKernel Debug File System[0m...
10767 22:16:28.430509 <30>[ 17.111181] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10768 22:16:28.441375 <30>[ 17.122128] systemd[1]: Starting Create list of static device nodes for the current kernel...
10769 22:16:28.447668 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10770 22:16:28.465305 <30>[ 17.149367] systemd[1]: Starting Load Kernel Module configfs...
10771 22:16:28.472760 Starting [0;1;39mLoad Kernel Module configfs[0m...
10772 22:16:28.488945 <30>[ 17.173345] systemd[1]: Starting Load Kernel Module drm...
10773 22:16:28.495646 Starting [0;1;39mLoad Kernel Module drm[0m...
10774 22:16:28.514489 <30>[ 17.195152] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10775 22:16:28.524966 <30>[ 17.208934] systemd[1]: Starting Journal Service...
10776 22:16:28.528460 Starting [0;1;39mJournal Service[0m...
10777 22:16:28.545724 <30>[ 17.229836] systemd[1]: Starting Load Kernel Modules...
10778 22:16:28.552179 Starting [0;1;39mLoad Kernel Modules[0m...
10779 22:16:28.572828 <30>[ 17.253787] systemd[1]: Starting Remount Root and Kernel File Systems...
10780 22:16:28.579360 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10781 22:16:28.597204 <30>[ 17.281761] systemd[1]: Starting Coldplug All udev Devices...
10782 22:16:28.604263 Starting [0;1;39mColdplug All udev Devices[0m...
10783 22:16:28.621340 <30>[ 17.305804] systemd[1]: Mounted Huge Pages File System.
10784 22:16:28.627905 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10785 22:16:28.643141 <30>[ 17.327404] systemd[1]: Started Journal Service.
10786 22:16:28.649692 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10787 22:16:28.664331 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10788 22:16:28.679459 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10789 22:16:28.699364 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10790 22:16:28.716151 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10791 22:16:28.732174 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10792 22:16:28.747892 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10793 22:16:28.767168 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10794 22:16:28.782579 See 'systemctl status systemd-remount-fs.service' for details.
10795 22:16:28.832603 Mounting [0;1;39mKernel Configuration File System[0m...
10796 22:16:28.853378 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10797 22:16:28.870498 <46>[ 17.551469] systemd-journald[180]: Received client request to flush runtime journal.
10798 22:16:28.879272 Starting [0;1;39mLoad/Save Random Seed[0m...
10799 22:16:28.901672 Starting [0;1;39mApply Kernel Variables[0m...
10800 22:16:28.921465 Starting [0;1;39mCreate System Users[0m...
10801 22:16:28.943300 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10802 22:16:28.963257 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10803 22:16:28.976270 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10804 22:16:28.992189 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10805 22:16:29.012323 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10806 22:16:29.031449 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10807 22:16:29.075064 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10808 22:16:29.098087 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10809 22:16:29.111222 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10810 22:16:29.126628 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10811 22:16:29.179450 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10812 22:16:29.202360 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10813 22:16:29.219879 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10814 22:16:29.240401 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10815 22:16:29.280908 Starting [0;1;39mNetwork Time Synchronization[0m...
10816 22:16:29.299907 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10817 22:16:29.333945 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10818 22:16:29.402551 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10819 22:16:29.444153 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbac<6>[ 18.126409] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10820 22:16:29.447219 klight.slice[0m.
10821 22:16:29.459110 <3>[ 18.140404] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10822 22:16:29.468967 <3>[ 18.149079] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10823 22:16:29.475927 <3>[ 18.157494] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10824 22:16:29.482282 <6>[ 18.160928] remoteproc remoteproc0: scp is available
10825 22:16:29.488967 <6>[ 18.170029] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10826 22:16:29.498820 [[0;32m OK [<4>[ 18.171034] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10827 22:16:29.508917 0m] Reached targ<3>[ 18.171368] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10828 22:16:29.518938 et [0;1;39mSyst<3>[ 18.171384] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10829 22:16:29.528903 em Time Set[0m.<3>[ 18.171392] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10830 22:16:29.529000
10831 22:16:29.535892 <3>[ 18.171402] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10832 22:16:29.545250 <3>[ 18.171409] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10833 22:16:29.555126 <6>[ 18.178434] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10834 22:16:29.562414 <3>[ 18.182620] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10835 22:16:29.568313 <6>[ 18.189712] remoteproc remoteproc0: powering up scp
10836 22:16:29.575301 <6>[ 18.199291] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10837 22:16:29.585009 <3>[ 18.207188] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10838 22:16:29.591735 <3>[ 18.207221] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10839 22:16:29.601257 <3>[ 18.207231] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10840 22:16:29.608225 <4>[ 18.208721] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10841 22:16:29.618851 <3>[ 18.218942] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10842 22:16:29.624558 <3>[ 18.226329] remoteproc remoteproc0: request_firmware failed: -2
10843 22:16:29.631007 <3>[ 18.234471] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10844 22:16:29.637743 <4>[ 18.297202] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10845 22:16:29.647768 <3>[ 18.299058] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10846 22:16:29.654152 <3>[ 18.299071] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10847 22:16:29.664359 <4>[ 18.312592] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10848 22:16:29.667180 <6>[ 18.313255] mc: Linux media interface: v0.10
10849 22:16:29.674003 <3>[ 18.313344] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10850 22:16:29.683937 <6>[ 18.322867] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10851 22:16:29.690421 <6>[ 18.327536] usbcore: registered new interface driver r8152
10852 22:16:29.697330 <3>[ 18.330464] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10853 22:16:29.703923 <6>[ 18.344507] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10854 22:16:29.710267 <6>[ 18.353496] videodev: Linux video capture interface: v2.00
10855 22:16:29.717612 <6>[ 18.357205] pci_bus 0000:00: root bus resource [bus 00-ff]
10856 22:16:29.723876 <6>[ 18.405750] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10857 22:16:29.733655 <6>[ 18.408125] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10858 22:16:29.743748 [[0;32m OK [<6>[ 18.413235] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10859 22:16:29.753420 0m] Reached targ<4>[ 18.416651] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10860 22:16:29.759854 <4>[ 18.416651] Fallback method does not support PEC.
10861 22:16:29.769837 et [0;1;39mSyst<6>[ 18.424283] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10862 22:16:29.776974 em Time Synchron<6>[ 18.434433] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10863 22:16:29.787119 <6>[ 18.438844] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10864 22:16:29.787205 ized[0m.
10865 22:16:29.797197 <6>[ 18.478135] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10866 22:16:29.803968 <6>[ 18.478532] usbcore: registered new interface driver cdc_ether
10867 22:16:29.810493 <6>[ 18.485793] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10868 22:16:29.813747 <6>[ 18.492973] Bluetooth: Core ver 2.22
10869 22:16:29.817309 <6>[ 18.499068] pci 0000:00:00.0: supports D1 D2
10870 22:16:29.824383 <6>[ 18.499394] usbcore: registered new interface driver r8153_ecm
10871 22:16:29.830980 <6>[ 18.503780] NET: Registered PF_BLUETOOTH protocol family
10872 22:16:29.837446 <6>[ 18.504242] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10873 22:16:29.851168 <6>[ 18.505434] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10874 22:16:29.854500 <6>[ 18.505615] usbcore: registered new interface driver uvcvideo
10875 22:16:29.861977 <6>[ 18.507910] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10876 22:16:29.868756 <6>[ 18.513651] Bluetooth: HCI device and connection manager initialized
10877 22:16:29.879129 <3>[ 18.516054] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10878 22:16:29.885677 <3>[ 18.516742] power_supply sbs-5-000b: driver failed to report `capacity_level' property: -6
10879 22:16:29.895961 <6>[ 18.522192] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10880 22:16:29.898807 <6>[ 18.526205] Bluetooth: HCI socket layer initialized
10881 22:16:29.906022 <6>[ 18.538822] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10882 22:16:29.912347 <6>[ 18.544762] Bluetooth: L2CAP socket layer initialized
10883 22:16:29.919039 <6>[ 18.545428] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10884 22:16:29.923014 <6>[ 18.549384] remoteproc remoteproc0: powering up scp
10885 22:16:29.931966 <4>[ 18.549433] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10886 22:16:29.939426 <3>[ 18.549441] remoteproc remoteproc0: request_firmware failed: -2
10887 22:16:29.946938 <3>[ 18.549444] fops_vcodec_open(),166: [MTK_V4L2][ERROR] vpu_load_firmware failed!
10888 22:16:29.956245 <3>[ 18.550642] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10889 22:16:29.963307 <3>[ 18.551504] power_supply sbs-5-000b: driver failed to report `cycle_count' property: -6
10890 22:16:29.970113 <6>[ 18.551558] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10891 22:16:29.979733 <6>[ 18.551586] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10892 22:16:29.986908 <6>[ 18.551615] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10893 22:16:29.990340 <6>[ 18.551899] pci 0000:01:00.0: supports D1 D2
10894 22:16:29.996521 <6>[ 18.558349] Bluetooth: SCO socket layer initialized
10895 22:16:30.003120 <6>[ 18.567131] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10896 22:16:30.009629 <4>[ 18.568083] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10897 22:16:30.019648 <4>[ 18.568095] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10898 22:16:30.024015 <6>[ 18.607832] usbcore: registered new interface driver btusb
10899 22:16:30.037069 <4>[ 18.608747] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10900 22:16:30.040500 <3>[ 18.608758] Bluetooth: hci0: Failed to load firmware file (-2)
10901 22:16:30.047416 <3>[ 18.608762] Bluetooth: hci0: Failed to set up firmware (-2)
10902 22:16:30.057100 <4>[ 18.608767] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10903 22:16:30.061124 <6>[ 18.610947] r8152 2-1.3:1.0 eth0: v1.12.13
10904 22:16:30.070903 <3>[ 18.614552] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10905 22:16:30.077546 <6>[ 18.623276] r8152 2-1.3:1.0 enx002432307c7b: renamed from eth0
10906 22:16:30.083894 <6>[ 18.628360] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10907 22:16:30.094222 <3>[ 18.629421] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10908 22:16:30.101537 <3>[ 18.651539] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10909 22:16:30.110601 <6>[ 18.652863] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10910 22:16:30.117827 <3>[ 18.681382] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10911 22:16:30.127844 <6>[ 18.684896] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10912 22:16:30.134792 <6>[ 18.684910] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10913 22:16:30.141411 <3>[ 18.715916] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10914 22:16:30.151898 <6>[ 18.725132] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10915 22:16:30.158806 <3>[ 18.752998] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10916 22:16:30.168749 <6>[ 18.760584] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10917 22:16:30.171997 <6>[ 18.857450] pci 0000:00:00.0: PCI bridge to [bus 01]
10918 22:16:30.182317 <6>[ 18.857459] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10919 22:16:30.189061 <6>[ 18.857654] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10920 22:16:30.195102 Startin<6>[ 18.878305] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10921 22:16:30.202392 g [0;1;39mLoad/<6>[ 18.885388] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10922 22:16:30.208709 Save Screen …of leds:white:kbd_backlight[0m...
10923 22:16:30.222667 <5>[ 18.903846] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10924 22:16:30.233657 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10925 22:16:30.243899 <5>[ 18.924836] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10926 22:16:30.250512 <4>[ 18.931805] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10927 22:16:30.257244 <6>[ 18.940703] cfg80211: failed to load regulatory.db
10928 22:16:30.259989 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10929 22:16:30.304676 <6>[ 18.985979] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10930 22:16:30.311609 <6>[ 18.993517] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10931 22:16:30.335938 <6>[ 19.020311] mt7921e 0000:01:00.0: ASIC revision: 79610010
10932 22:16:30.441175 <4>[ 19.118435] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10933 22:16:30.447156 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10934 22:16:30.463161 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10935 22:16:30.482769 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10936 22:16:30.498105 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10937 22:16:30.510627 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10938 22:16:30.530029 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10939 22:16:30.547675 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10940 22:16:30.560609 <4>[ 19.237508] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10941 22:16:30.567597 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10942 22:16:30.582809 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10943 22:16:30.622853 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10944 22:16:30.652938 Starting [0;1;39mUser Login Management[0m...
10945 22:16:30.679798 <4>[ 19.357924] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10946 22:16:30.686323 Starting [0;1;39mPermit User Sessions[0m...
10947 22:16:30.703911 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10948 22:16:30.759854 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10949 22:16:30.777112 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10950 22:16:30.783984 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10951 22:16:30.803777 <4>[ 19.481685] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10952 22:16:30.819807 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10953 22:16:30.836722 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10954 22:16:30.855590 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10955 22:16:30.871296 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10956 22:16:30.886822 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10957 22:16:30.927743 <4>[ 19.605461] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10958 22:16:30.933795 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10959 22:16:30.962871 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10960 22:16:31.019740
10961 22:16:31.019835
10962 22:16:31.022962 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10963 22:16:31.023038
10964 22:16:31.026067 debian-bullseye-arm64 login: root (automatic login)
10965 22:16:31.026147
10966 22:16:31.026213
10967 22:16:31.047877 <4>[ 19.726129] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10968 22:16:31.054747 Linux debian-bullseye-arm64 6.1.31 #1 SMP PREEMPT Mon Jun 5 22:04:07 UTC 2023 aarch64
10969 22:16:31.054829
10970 22:16:31.061084 The programs included with the Debian GNU/Linux system are free software;
10971 22:16:31.067980 the exact distribution terms for each program are described in the
10972 22:16:31.071369 individual files in /usr/share/doc/*/copyright.
10973 22:16:31.074548
10974 22:16:31.077852 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10975 22:16:31.080914 permitted by applicable law.
10976 22:16:31.081258 Matched prompt #10: / #
10978 22:16:31.081470 Setting prompt string to ['/ #']
10979 22:16:31.081568 end: 2.2.5.1 login-action (duration 00:00:20) [common]
10981 22:16:31.081762 end: 2.2.5 auto-login-action (duration 00:00:21) [common]
10982 22:16:31.081855 start: 2.2.6 expect-shell-connection (timeout 00:02:37) [common]
10983 22:16:31.081932 Setting prompt string to ['/ #']
10984 22:16:31.081996 Forcing a shell prompt, looking for ['/ #']
10986 22:16:31.132176 / #
10987 22:16:31.132281 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10988 22:16:31.132360 Waiting using forced prompt support (timeout 00:02:30)
10989 22:16:31.137340
10990 22:16:31.137604 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10991 22:16:31.137696 start: 2.2.7 export-device-env (timeout 00:02:37) [common]
10992 22:16:31.137797 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10993 22:16:31.137888 end: 2.2 depthcharge-retry (duration 00:02:23) [common]
10994 22:16:31.137969 end: 2 depthcharge-action (duration 00:02:23) [common]
10995 22:16:31.138054 start: 3 lava-test-retry (timeout 00:07:14) [common]
10996 22:16:31.138142 start: 3.1 lava-test-shell (timeout 00:07:14) [common]
10997 22:16:31.138218 Using namespace: common
10999 22:16:31.238484 / # #
11000 22:16:31.238602 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11001 22:16:31.238715 <4>[ 19.849491] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11002 22:16:31.243687 #
11003 22:16:31.243941 Using /lava-10597245
11005 22:16:31.344217 / # export SHELL=/bin/sh
11006 22:16:31.344373 <4>[ 19.969221] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11007 22:16:31.349354 export SHELL=/bin/sh
11009 22:16:31.449810 / # . /lava-10597245/environment
11010 22:16:31.449952 <4>[ 20.088859] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11011 22:16:31.454709 . /lava-10597245/environment
11013 22:16:31.555199 / # /lava-10597245/bin/lava-test-runner /lava-10597245/0
11014 22:16:31.555317 Test shell timeout: 10s (minimum of the action and connection timeout)
11015 22:16:31.555653 /lava-10597245/bin/lava-test-runner /lava-10597245/0<4>[ 20.209555] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11016 22:16:31.560412
11017 22:16:31.604215 + export TESTRUN_ID=0_igt-gpu-pa<8>[ 20.268394] <LAVA_SIGNAL_STARTRUN 0_igt-gpu-panfrost 10597245_1.5.2.3.1>
11018 22:16:31.604310 nfrost
11019 22:16:31.604376 + cd /lava-10597245/0/tests/0_igt-gpu-panfrost
11020 22:16:31.604451 + cat uuid
11021 22:16:31.604523 + UUID=10597245_1.5.2.3.1
11022 22:16:31.604582 + set +x
11023 22:16:31.604818 Received signal: <STARTRUN> 0_igt-gpu-panfrost 10597245_1.5.2.3.1
11024 22:16:31.604889 Starting test lava.0_igt-gpu-panfrost (10597245_1.5.2.3.1)
11025 22:16:31.604966 Skipping test definition patterns.
11026 22:16:31.605534 + IGT_FORCE_DRIVER=panfrost /usr/bin/igt-parser.sh panfrost_gem_new panfrost_get_param panfrost_prime panfrost_submit
11027 22:16:31.615334 <8>[ 20.300116] <LAVA_SIGNAL_TESTSET START panfrost_gem_new>
11028 22:16:31.615585 Received signal: <TESTSET> START panfrost_gem_new
11029 22:16:31.615656 Starting test_set panfrost_gem_new
11030 22:16:31.643333 <3>[ 20.327740] mt7921e 0000:01:00.0: hardware init failed
11031 22:16:31.650202 <14>[ 20.333277] [IGT] panfrost_gem_new: executing
11032 22:16:31.659566 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6<14>[ 20.341420] [IGT] panfrost_gem_new: exiting, ret=77
11033 22:16:31.659649 .1.31 aarch64)
11034 22:16:31.672542 Test requirement not met in function drm_open_driver, file ../li<8>[ 20.353699] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-new-4096 RESULT=skip>
11035 22:16:31.672630 b/drmtest.c:621:
11036 22:16:31.672867 Received signal: <TESTCASE> TEST_CASE_ID=gem-new-4096 RESULT=skip
11038 22:16:31.675991 Test requirement: !(fd<0)
11039 22:16:31.679099 No known gpu found for chipset flags 0x32 (panfrost)
11040 22:16:31.682613 Last errno: 2, No such file or directory
11041 22:16:31.689124 [1mSubtest gem-new-4096: SKIP (0.000s)[0m
11042 22:16:31.692652 <14>[ 20.379045] [IGT] panfrost_gem_new: executing
11043 22:16:31.702636 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6<14>[ 20.387225] [IGT] panfrost_gem_new: exiting, ret=77
11044 22:16:31.705768 .1.31 aarch64)
11045 22:16:31.716003 Test requirement not met in function drm_open_driver, file ../li<8>[ 20.399584] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-new-0 RESULT=skip>
11046 22:16:31.716303 Received signal: <TESTCASE> TEST_CASE_ID=gem-new-0 RESULT=skip
11048 22:16:31.719558 b/drmtest.c:621:
11049 22:16:31.722753 Test requirement: !(fd<0)
11050 22:16:31.726042 No known gpu found for chipset flags 0x32 (panfrost)
11051 22:16:31.729035 Last errno: 2, No such file or directory
11052 22:16:31.732392 [1mSubtest gem-new-0: SKIP (0.000s)[0m
11053 22:16:31.740023 <14>[ 20.424531] [IGT] panfrost_gem_new: executing
11054 22:16:31.749741 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6<14>[ 20.432599] [IGT] panfrost_gem_new: exiting, ret=77
11055 22:16:31.749823 .1.31 aarch64)
11056 22:16:31.762827 Test requirement not met in function drm_open_driver, file ../li<8>[ 20.445056] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-new-zeroed RESULT=skip>
11057 22:16:31.763081 Received signal: <TESTCASE> TEST_CASE_ID=gem-new-zeroed RESULT=skip
11059 22:16:31.766531 b/drmtest.c:621:
11060 22:16:31.769591 Test requireme<8>[ 20.455011] <LAVA_SIGNAL_TESTSET STOP>
11061 22:16:31.769844 Received signal: <TESTSET> STOP
11062 22:16:31.769918 Closing test_set panfrost_gem_new
11063 22:16:31.773124 nt: !(fd<0)
11064 22:16:31.775977 No known gpu found for chipset flags 0x32 (panfrost)
11065 22:16:31.779553 Last errno: 2, No such file or directory
11066 22:16:31.782741 [1mSubtest gem-new-zeroed: SKIP (0.000s)[0m
11067 22:16:31.797114 <8>[ 20.481485] <LAVA_SIGNAL_TESTSET START panfrost_get_param>
11068 22:16:31.797372 Received signal: <TESTSET> START panfrost_get_param
11069 22:16:31.797443 Starting test_set panfrost_get_param
11070 22:16:31.819916 <14>[ 20.504543] [IGT] panfrost_get_param: executing
11071 22:16:31.830211 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6<14>[ 20.512969] [IGT] panfrost_get_param: exiting, ret=77
11072 22:16:31.830294 .1.31 aarch64)
11073 22:16:31.842932 Test requirement not met in function drm_open_driver, file ../li<8>[ 20.525198] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=base-params RESULT=skip>
11074 22:16:31.843188 Received signal: <TESTCASE> TEST_CASE_ID=base-params RESULT=skip
11076 22:16:31.846379 b/drmtest.c:621:
11077 22:16:31.846460 Test requirement: !(fd<0)
11078 22:16:31.852813 No known gpu found for chipset flags 0x32 (panfrost)
11079 22:16:31.856848 Last errno: 2, No such file or directory
11080 22:16:31.859823 [1mSubtest base-params: SKIP (0.000s)[0m
11081 22:16:31.866527 <14>[ 20.550060] [IGT] panfrost_get_param: executing
11082 22:16:31.876265 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6<14>[ 20.558246] [IGT] panfrost_get_param: exiting, ret=77
11083 22:16:31.876369 .1.31 aarch64)
11084 22:16:31.889438 Test requirement not met in function drm_open_driver, file ../li<8>[ 20.570865] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=get-bad-param RESULT=skip>
11085 22:16:31.889611 b/drmtest.c:621:
11086 22:16:31.889913 Received signal: <TESTCASE> TEST_CASE_ID=get-bad-param RESULT=skip
11088 22:16:31.892851 Test requirement: !(fd<0)
11089 22:16:31.899680 No known gpu found for chipset flags 0x32 (panfrost)
11090 22:16:31.902977 Last errno: 2, No such file or directory
11091 22:16:31.905944 [1mSubtest get-bad-param: SKIP (0.000s)[0m
11092 22:16:31.912378 <14>[ 20.597397] [IGT] panfrost_get_param: executing
11093 22:16:31.922567 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6<14>[ 20.606052] [IGT] panfrost_get_param: exiting, ret=77
11094 22:16:31.922652 .1.31 aarch64)
11095 22:16:31.935845 Test requirement not met in function drm_open_driver, file ../li<8>[ 20.618073] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=get-bad-padding RESULT=skip>
11096 22:16:31.936107 Received signal: <TESTCASE> TEST_CASE_ID=get-bad-padding RESULT=skip
11098 22:16:31.939198 b/drmtest.c:621:
11099 22:16:31.942503 Test requireme<8>[ 20.628084] <LAVA_SIGNAL_TESTSET STOP>
11100 22:16:31.942755 Received signal: <TESTSET> STOP
11101 22:16:31.942826 Closing test_set panfrost_get_param
11102 22:16:31.945963 nt: !(fd<0)
11103 22:16:31.948906 No known gpu found for chipset flags 0x32 (panfrost)
11104 22:16:31.952501 Last errno: 2, No such file or directory
11105 22:16:31.955739 [1mSubtest get-bad-padding: SKIP (0.000s)[0m
11106 22:16:31.970769 <8>[ 20.654923] <LAVA_SIGNAL_TESTSET START panfrost_prime>
11107 22:16:31.971023 Received signal: <TESTSET> START panfrost_prime
11108 22:16:31.971093 Starting test_set panfrost_prime
11109 22:16:31.993765 <14>[ 20.678579] [IGT] panfrost_prime: executing
11110 22:16:32.004165 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6<14>[ 20.686553] [IGT] panfrost_prime: exiting, ret=77
11111 22:16:32.004254 .1.31 aarch64)
11112 22:16:32.017369 Test requirement not met in function drm_open_driver, file ../li<8>[ 20.699265] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-prime-import RESULT=skip>
11113 22:16:32.017626 Received signal: <TESTCASE> TEST_CASE_ID=gem-prime-import RESULT=skip
11115 22:16:32.020230 b/drmtest.c:621:
11116 22:16:32.023461 Test requireme<8>[ 20.708482] <LAVA_SIGNAL_TESTSET STOP>
11117 22:16:32.023545 nt: !(fd<0)
11118 22:16:32.023779 Received signal: <TESTSET> STOP
11119 22:16:32.023843 Closing test_set panfrost_prime
11120 22:16:32.029991 No known gpu found for chipset flags 0x32 (panfrost)
11121 22:16:32.033269 Last errno: 2, No such file or directory
11122 22:16:32.036615 [1mSubtest gem-prime-import: SKIP (0.000s)[0m
11123 22:16:32.049486 <8>[ 20.734327] <LAVA_SIGNAL_TESTSET START panfrost_submit>
11124 22:16:32.049739 Received signal: <TESTSET> START panfrost_submit
11125 22:16:32.049809 Starting test_set panfrost_submit
11126 22:16:32.072462 <14>[ 20.756968] [IGT] panfrost_submit: executing
11127 22:16:32.082175 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6<14>[ 20.765127] [IGT] panfrost_submit: exiting, ret=77
11128 22:16:32.082259 .1.31 aarch64)
11129 22:16:32.095470 Test requirement not met in function drm_open_driver, file ../li<8>[ 20.777252] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit RESULT=skip>
11130 22:16:32.095558 b/drmtest.c:621:
11131 22:16:32.095812 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit RESULT=skip
11133 22:16:32.098669 Test requirement: !(fd<0)
11134 22:16:32.105191 No known gpu found for chipset flags 0x32 (panfrost)
11135 22:16:32.108754 Last errno: 2, No such file or directory
11136 22:16:32.111748 [1mSubtest pan-submit: SKIP (0.000s)[0m
11137 22:16:32.118712 <14>[ 20.803416] [IGT] panfrost_submit: executing
11138 22:16:32.128812 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6<14>[ 20.811635] [IGT] panfrost_submit: exiting, ret=77
11139 22:16:32.128897 .1.31 aarch64)
11140 22:16:32.142163 Test requirement not met in function drm_open_driver, file ../li<8>[ 20.823804] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-no-jc RESULT=skip>
11141 22:16:32.142434 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-no-jc RESULT=skip
11143 22:16:32.145668 b/drmtest.c:621:
11144 22:16:32.145750 Test requirement: !(fd<0)
11145 22:16:32.152227 No known gpu found for chipset flags 0x32 (panfrost)
11146 22:16:32.155491 Last errno: 2, No such file or directory
11147 22:16:32.158864 [1mSubtest pan-submit-error-no-jc: SKIP (0.000s)[0m
11148 22:16:32.165133 <14>[ 20.849261] [IGT] panfrost_submit: executing
11149 22:16:32.175427 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6<14>[ 20.857268] [IGT] panfrost_submit: exiting, ret=77
11150 22:16:32.175511 .1.31 aarch64)
11151 22:16:32.188119 Test requirement not met in function drm_open_driver, file ../li<8>[ 20.869939] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-in-syncs RESULT=skip>
11152 22:16:32.188374 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-in-syncs RESULT=skip
11154 22:16:32.191356 b/drmtest.c:621:
11155 22:16:32.191437 Test requirement: !(fd<0)
11156 22:16:32.198039 No known gpu found for chipset flags 0x32 (panfrost)
11157 22:16:32.201559 Last errno: 2, No such file or directory
11158 22:16:32.208482 [1mSubtest pan-submit-error-bad-in-syncs: SKIP (0.000s)[0m
11159 22:16:32.211262 <14>[ 20.896319] [IGT] panfrost_submit: executing
11160 22:16:32.221210 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6<14>[ 20.904501] [IGT] panfrost_submit: exiting, ret=77
11161 22:16:32.221294 .1.31 aarch64)
11162 22:16:32.234926 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-bo-handles RESULT=skip
11164 22:16:32.237823 Test requirement not met in function drm_open_driver, file ../li<8>[ 20.917113] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-bo-handles RESULT=skip>
11165 22:16:32.237908 b/drmtest.c:621:
11166 22:16:32.241095 Test requirement: !(fd<0)
11167 22:16:32.244906 No known gpu found for chipset flags 0x32 (panfrost)
11168 22:16:32.247969 Last errno: 2, No such file or directory
11169 22:16:32.254520 [1mSubtest pan-submit-error-bad-bo-handles: SKIP (0.000s)[0m
11170 22:16:32.257627 <14>[ 20.943195] [IGT] panfrost_submit: executing
11171 22:16:32.267914 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6<14>[ 20.951957] [IGT] panfrost_submit: exiting, ret=77
11172 22:16:32.270615 .1.31 aarch64)
11173 22:16:32.283881 Test requirement not met in function drm_open_driver, file ../li<8>[ 20.964349] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-requirements RESULT=skip>
11174 22:16:32.284139 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-requirements RESULT=skip
11176 22:16:32.287262 b/drmtest.c:621:
11177 22:16:32.287345 Test requirement: !(fd<0)
11178 22:16:32.293898 No known gpu found for chipset flags 0x32 (panfrost)
11179 22:16:32.297172 Last errno: 2, No such file or directory
11180 22:16:32.300437 [1mSubtest pan-submit-error-bad-requirements: SKIP (0.000s)[0m
11181 22:16:32.306869 <14>[ 20.991238] [IGT] panfrost_submit: executing
11182 22:16:32.317494 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6<14>[ 20.999725] [IGT] panfrost_submit: exiting, ret=77
11183 22:16:32.317578 .1.31 aarch64)
11184 22:16:32.330402 Test requirement not met in function drm_open_driver, file ../li<8>[ 21.012238] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-out-sync RESULT=skip>
11185 22:16:32.330659 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-out-sync RESULT=skip
11187 22:16:32.333932 b/drmtest.c:621:
11188 22:16:32.336677 Test requirement: !(fd<0)
11189 22:16:32.340556 No known gpu found for chipset flags 0x32 (panfrost)
11190 22:16:32.343460 Last errno: 2, No such file or directory
11191 22:16:32.350152 [1mSubtest pan-submit-error-bad-out-sync: SKIP (0.000s)[0m
11192 22:16:32.353339 <14>[ 21.038845] [IGT] panfrost_submit: executing
11193 22:16:32.363241 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6<14>[ 21.046890] [IGT] panfrost_submit: exiting, ret=77
11194 22:16:32.363338 .1.31 aarch64)
11195 22:16:32.376285 Test requirement not met in function drm_open_driver, file ../li<8>[ 21.059172] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-reset RESULT=skip>
11196 22:16:32.376541 Received signal: <TESTCASE> TEST_CASE_ID=pan-reset RESULT=skip
11198 22:16:32.379463 b/drmtest.c:621:
11199 22:16:32.379545 Test requirement: !(fd<0)
11200 22:16:32.386059 No known gpu found for chipset flags 0x32 (panfrost)
11201 22:16:32.389253 Last errno: 2, No such file or directory
11202 22:16:32.393110 [1mSubtest pan-reset: SKIP (0.000s)[0m
11203 22:16:32.399474 <14>[ 21.084114] [IGT] panfrost_submit: executing
11204 22:16:32.409146 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6<14>[ 21.092092] [IGT] panfrost_submit: exiting, ret=77
11205 22:16:32.409230 .1.31 aarch64)
11206 22:16:32.422302 Test requirement not met in function drm_open_driver, file ../li<8>[ 21.104285] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-and-close RESULT=skip>
11207 22:16:32.422557 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-and-close RESULT=skip
11209 22:16:32.425715 b/drmtest.c:621:
11210 22:16:32.425798 Test requirement: !(fd<0)
11211 22:16:32.431965 No known gpu found for chipset flags 0x32 (panfrost)
11212 22:16:32.435538 Last errno: 2, No such file or directory
11213 22:16:32.439046 [1mSubtest pan-submit-and-close: SKIP (0.000s)[0m
11214 22:16:32.445477 <14>[ 21.129997] [IGT] panfrost_submit: executing
11215 22:16:32.455498 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6<14>[ 21.137924] [IGT] panfrost_submit: exiting, ret=77
11216 22:16:32.455582 .1.31 aarch64)
11217 22:16:32.468570 Test requirement not met in function drm_open_driver, file ../li<8>[ 21.150441] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-unhandled-pagefault RESULT=skip>
11218 22:16:32.468831 Received signal: <TESTCASE> TEST_CASE_ID=pan-unhandled-pagefault RESULT=skip
11220 22:16:32.471844 b/drmtest.c:621:
11221 22:16:32.475267 Test requireme<8>[ 21.160793] <LAVA_SIGNAL_TESTSET STOP>
11222 22:16:32.475521 Received signal: <TESTSET> STOP
11223 22:16:32.475592 Closing test_set panfrost_submit
11224 22:16:32.478993 nt: !(fd<0)
11225 22:16:32.485307 No <8>[ 21.166420] <LAVA_SIGNAL_ENDRUN 0_igt-gpu-panfrost 10597245_1.5.2.3.1>
11226 22:16:32.485560 Received signal: <ENDRUN> 0_igt-gpu-panfrost 10597245_1.5.2.3.1
11227 22:16:32.485645 Ending use of test pattern.
11228 22:16:32.485709 Ending test lava.0_igt-gpu-panfrost (10597245_1.5.2.3.1), duration 0.88
11230 22:16:32.488538 known gpu found for chipset flags 0x32 (panfrost)
11231 22:16:32.491809 Last errno: 2, No such file or directory
11232 22:16:32.498821 [1mSubtest pan-unhandled-pagefault: SKIP (0.000s)[0m
11233 22:16:32.498904 + set +x
11234 22:16:32.499140 ok: lava_test_shell seems to have completed
11235 22:16:32.499446 base-params:
result: skip
set: panfrost_get_param
gem-new-0:
result: skip
set: panfrost_gem_new
gem-new-4096:
result: skip
set: panfrost_gem_new
gem-new-zeroed:
result: skip
set: panfrost_gem_new
gem-prime-import:
result: skip
set: panfrost_prime
get-bad-padding:
result: skip
set: panfrost_get_param
get-bad-param:
result: skip
set: panfrost_get_param
pan-reset:
result: skip
set: panfrost_submit
pan-submit:
result: skip
set: panfrost_submit
pan-submit-and-close:
result: skip
set: panfrost_submit
pan-submit-error-bad-bo-handles:
result: skip
set: panfrost_submit
pan-submit-error-bad-in-syncs:
result: skip
set: panfrost_submit
pan-submit-error-bad-out-sync:
result: skip
set: panfrost_submit
pan-submit-error-bad-requirements:
result: skip
set: panfrost_submit
pan-submit-error-no-jc:
result: skip
set: panfrost_submit
pan-unhandled-pagefault:
result: skip
set: panfrost_submit
11236 22:16:32.499551 end: 3.1 lava-test-shell (duration 00:00:01) [common]
11237 22:16:32.499640 end: 3 lava-test-retry (duration 00:00:01) [common]
11238 22:16:32.499729 start: 4 finalize (timeout 00:07:13) [common]
11239 22:16:32.499816 start: 4.1 power-off (timeout 00:00:30) [common]
11240 22:16:32.499976 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-2' '--port=1' '--command=off'
11241 22:16:32.578483 >> Command sent successfully.
11242 22:16:32.580971 Returned 0 in 0 seconds
11243 22:16:32.681375 end: 4.1 power-off (duration 00:00:00) [common]
11245 22:16:32.681696 start: 4.2 read-feedback (timeout 00:07:13) [common]
11247 22:16:32.682236 Listened to connection for namespace 'common' for up to 1s
11248 22:16:33.682908 Finalising connection for namespace 'common'
11249 22:16:33.683083 Disconnecting from shell: Finalise
11250 22:16:33.683169 / #
11251 22:16:33.783482 end: 4.2 read-feedback (duration 00:00:01) [common]
11252 22:16:33.783630 end: 4 finalize (duration 00:00:01) [common]
11253 22:16:33.783741 Cleaning after the job
11254 22:16:33.783838 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10597245/tftp-deploy-igpa52ow/ramdisk
11255 22:16:33.789968 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10597245/tftp-deploy-igpa52ow/kernel
11256 22:16:33.795835 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10597245/tftp-deploy-igpa52ow/dtb
11257 22:16:33.796004 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10597245/tftp-deploy-igpa52ow/modules
11258 22:16:33.801405 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/10597245
11259 22:16:33.896078 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/10597245
11260 22:16:33.896253 Job finished correctly