Boot log: mt8192-asurada-spherion-r0
- Errors: 2
- Kernel Errors: 31
- Boot result: FAIL
- Warnings: 1
- Kernel Warnings: 26
1 22:13:49.478646 lava-dispatcher, installed at version: 2023.05.1
2 22:13:49.478867 start: 0 validate
3 22:13:49.479048 Start time: 2023-06-05 22:13:49.479023+00:00 (UTC)
4 22:13:49.479207 Using caching service: 'http://localhost/cache/?uri=%s'
5 22:13:49.479334 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-igt%2F20230527.0%2Farm64%2Frootfs.cpio.gz exists
6 22:13:49.779179 Using caching service: 'http://localhost/cache/?uri=%s'
7 22:13:49.779391 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1314-g1ab0ac1d7e2e3%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 22:13:50.081047 Using caching service: 'http://localhost/cache/?uri=%s'
9 22:13:50.081844 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1314-g1ab0ac1d7e2e3%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 22:13:50.377580 Using caching service: 'http://localhost/cache/?uri=%s'
11 22:13:50.378373 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1314-g1ab0ac1d7e2e3%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 22:13:53.176845 validate duration: 3.70
14 22:13:53.177105 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 22:13:53.177205 start: 1.1 download-retry (timeout 00:10:00) [common]
16 22:13:53.177294 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 22:13:53.177420 Not decompressing ramdisk as can be used compressed.
18 22:13:53.177505 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-igt/20230527.0/arm64/rootfs.cpio.gz
19 22:13:53.177596 saving as /var/lib/lava/dispatcher/tmp/10597244/tftp-deploy-2dx16yrn/ramdisk/rootfs.cpio.gz
20 22:13:53.177674 total size: 43394293 (41MB)
21 22:13:53.178767 progress 0% (0MB)
22 22:13:53.190171 progress 5% (2MB)
23 22:13:53.201462 progress 10% (4MB)
24 22:13:53.213025 progress 15% (6MB)
25 22:13:53.224336 progress 20% (8MB)
26 22:13:53.235755 progress 25% (10MB)
27 22:13:53.247039 progress 30% (12MB)
28 22:13:53.258287 progress 35% (14MB)
29 22:13:53.269280 progress 40% (16MB)
30 22:13:53.280637 progress 45% (18MB)
31 22:13:53.292146 progress 50% (20MB)
32 22:13:53.303469 progress 55% (22MB)
33 22:13:53.314838 progress 60% (24MB)
34 22:13:53.326195 progress 65% (26MB)
35 22:13:53.337524 progress 70% (29MB)
36 22:13:53.348764 progress 75% (31MB)
37 22:13:53.359893 progress 80% (33MB)
38 22:13:53.370954 progress 85% (35MB)
39 22:13:53.382095 progress 90% (37MB)
40 22:13:53.393202 progress 95% (39MB)
41 22:13:53.404133 progress 100% (41MB)
42 22:13:53.404330 41MB downloaded in 0.23s (182.59MB/s)
43 22:13:53.404499 end: 1.1.1 http-download (duration 00:00:00) [common]
45 22:13:53.404747 end: 1.1 download-retry (duration 00:00:00) [common]
46 22:13:53.404837 start: 1.2 download-retry (timeout 00:10:00) [common]
47 22:13:53.404924 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 22:13:53.405062 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1314-g1ab0ac1d7e2e3/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 22:13:53.405138 saving as /var/lib/lava/dispatcher/tmp/10597244/tftp-deploy-2dx16yrn/kernel/Image
50 22:13:53.405202 total size: 45746688 (43MB)
51 22:13:53.405265 No compression specified
52 22:13:53.406404 progress 0% (0MB)
53 22:13:53.418051 progress 5% (2MB)
54 22:13:53.429977 progress 10% (4MB)
55 22:13:53.442060 progress 15% (6MB)
56 22:13:53.454636 progress 20% (8MB)
57 22:13:53.467060 progress 25% (10MB)
58 22:13:53.479430 progress 30% (13MB)
59 22:13:53.492033 progress 35% (15MB)
60 22:13:53.504556 progress 40% (17MB)
61 22:13:53.516328 progress 45% (19MB)
62 22:13:53.528019 progress 50% (21MB)
63 22:13:53.539662 progress 55% (24MB)
64 22:13:53.551559 progress 60% (26MB)
65 22:13:53.563270 progress 65% (28MB)
66 22:13:53.575045 progress 70% (30MB)
67 22:13:53.586867 progress 75% (32MB)
68 22:13:53.598461 progress 80% (34MB)
69 22:13:53.610749 progress 85% (37MB)
70 22:13:53.622633 progress 90% (39MB)
71 22:13:53.634266 progress 95% (41MB)
72 22:13:53.646069 progress 100% (43MB)
73 22:13:53.646261 43MB downloaded in 0.24s (180.99MB/s)
74 22:13:53.646418 end: 1.2.1 http-download (duration 00:00:00) [common]
76 22:13:53.646652 end: 1.2 download-retry (duration 00:00:00) [common]
77 22:13:53.646742 start: 1.3 download-retry (timeout 00:10:00) [common]
78 22:13:53.646831 start: 1.3.1 http-download (timeout 00:10:00) [common]
79 22:13:53.646970 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1314-g1ab0ac1d7e2e3/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 22:13:53.647049 saving as /var/lib/lava/dispatcher/tmp/10597244/tftp-deploy-2dx16yrn/dtb/mt8192-asurada-spherion-r0.dtb
81 22:13:53.647114 total size: 46924 (0MB)
82 22:13:53.647176 No compression specified
83 22:13:53.648299 progress 69% (0MB)
84 22:13:53.648575 progress 100% (0MB)
85 22:13:53.648731 0MB downloaded in 0.00s (27.72MB/s)
86 22:13:53.648856 end: 1.3.1 http-download (duration 00:00:00) [common]
88 22:13:53.649109 end: 1.3 download-retry (duration 00:00:00) [common]
89 22:13:53.649197 start: 1.4 download-retry (timeout 00:10:00) [common]
90 22:13:53.649284 start: 1.4.1 http-download (timeout 00:10:00) [common]
91 22:13:53.649396 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1314-g1ab0ac1d7e2e3/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 22:13:53.649466 saving as /var/lib/lava/dispatcher/tmp/10597244/tftp-deploy-2dx16yrn/modules/modules.tar
93 22:13:53.649530 total size: 8543056 (8MB)
94 22:13:53.649592 Using unxz to decompress xz
95 22:13:53.653453 progress 0% (0MB)
96 22:13:53.677033 progress 5% (0MB)
97 22:13:53.704003 progress 10% (0MB)
98 22:13:53.732384 progress 15% (1MB)
99 22:13:53.759575 progress 20% (1MB)
100 22:13:53.784314 progress 25% (2MB)
101 22:13:53.811323 progress 30% (2MB)
102 22:13:53.836701 progress 35% (2MB)
103 22:13:53.862511 progress 40% (3MB)
104 22:13:53.888488 progress 45% (3MB)
105 22:13:53.915103 progress 50% (4MB)
106 22:13:53.940139 progress 55% (4MB)
107 22:13:53.966002 progress 60% (4MB)
108 22:13:53.993312 progress 65% (5MB)
109 22:13:54.018458 progress 70% (5MB)
110 22:13:54.042426 progress 75% (6MB)
111 22:13:54.067334 progress 80% (6MB)
112 22:13:54.093773 progress 85% (6MB)
113 22:13:54.124924 progress 90% (7MB)
114 22:13:54.157774 progress 95% (7MB)
115 22:13:54.184037 progress 100% (8MB)
116 22:13:54.189975 8MB downloaded in 0.54s (15.08MB/s)
117 22:13:54.190287 end: 1.4.1 http-download (duration 00:00:01) [common]
119 22:13:54.190677 end: 1.4 download-retry (duration 00:00:01) [common]
120 22:13:54.190809 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 22:13:54.190914 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 22:13:54.190999 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 22:13:54.191085 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 22:13:54.191322 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/10597244/lava-overlay-2b53xq8m
125 22:13:54.191508 makedir: /var/lib/lava/dispatcher/tmp/10597244/lava-overlay-2b53xq8m/lava-10597244/bin
126 22:13:54.191612 makedir: /var/lib/lava/dispatcher/tmp/10597244/lava-overlay-2b53xq8m/lava-10597244/tests
127 22:13:54.191715 makedir: /var/lib/lava/dispatcher/tmp/10597244/lava-overlay-2b53xq8m/lava-10597244/results
128 22:13:54.191867 Creating /var/lib/lava/dispatcher/tmp/10597244/lava-overlay-2b53xq8m/lava-10597244/bin/lava-add-keys
129 22:13:54.192058 Creating /var/lib/lava/dispatcher/tmp/10597244/lava-overlay-2b53xq8m/lava-10597244/bin/lava-add-sources
130 22:13:54.192191 Creating /var/lib/lava/dispatcher/tmp/10597244/lava-overlay-2b53xq8m/lava-10597244/bin/lava-background-process-start
131 22:13:54.192328 Creating /var/lib/lava/dispatcher/tmp/10597244/lava-overlay-2b53xq8m/lava-10597244/bin/lava-background-process-stop
132 22:13:54.192454 Creating /var/lib/lava/dispatcher/tmp/10597244/lava-overlay-2b53xq8m/lava-10597244/bin/lava-common-functions
133 22:13:54.192578 Creating /var/lib/lava/dispatcher/tmp/10597244/lava-overlay-2b53xq8m/lava-10597244/bin/lava-echo-ipv4
134 22:13:54.192707 Creating /var/lib/lava/dispatcher/tmp/10597244/lava-overlay-2b53xq8m/lava-10597244/bin/lava-install-packages
135 22:13:54.192879 Creating /var/lib/lava/dispatcher/tmp/10597244/lava-overlay-2b53xq8m/lava-10597244/bin/lava-installed-packages
136 22:13:54.193025 Creating /var/lib/lava/dispatcher/tmp/10597244/lava-overlay-2b53xq8m/lava-10597244/bin/lava-os-build
137 22:13:54.193152 Creating /var/lib/lava/dispatcher/tmp/10597244/lava-overlay-2b53xq8m/lava-10597244/bin/lava-probe-channel
138 22:13:54.193329 Creating /var/lib/lava/dispatcher/tmp/10597244/lava-overlay-2b53xq8m/lava-10597244/bin/lava-probe-ip
139 22:13:54.193484 Creating /var/lib/lava/dispatcher/tmp/10597244/lava-overlay-2b53xq8m/lava-10597244/bin/lava-target-ip
140 22:13:54.193610 Creating /var/lib/lava/dispatcher/tmp/10597244/lava-overlay-2b53xq8m/lava-10597244/bin/lava-target-mac
141 22:13:54.193759 Creating /var/lib/lava/dispatcher/tmp/10597244/lava-overlay-2b53xq8m/lava-10597244/bin/lava-target-storage
142 22:13:54.193918 Creating /var/lib/lava/dispatcher/tmp/10597244/lava-overlay-2b53xq8m/lava-10597244/bin/lava-test-case
143 22:13:54.194076 Creating /var/lib/lava/dispatcher/tmp/10597244/lava-overlay-2b53xq8m/lava-10597244/bin/lava-test-event
144 22:13:54.194237 Creating /var/lib/lava/dispatcher/tmp/10597244/lava-overlay-2b53xq8m/lava-10597244/bin/lava-test-feedback
145 22:13:54.194393 Creating /var/lib/lava/dispatcher/tmp/10597244/lava-overlay-2b53xq8m/lava-10597244/bin/lava-test-raise
146 22:13:54.194551 Creating /var/lib/lava/dispatcher/tmp/10597244/lava-overlay-2b53xq8m/lava-10597244/bin/lava-test-reference
147 22:13:54.194707 Creating /var/lib/lava/dispatcher/tmp/10597244/lava-overlay-2b53xq8m/lava-10597244/bin/lava-test-runner
148 22:13:54.194832 Creating /var/lib/lava/dispatcher/tmp/10597244/lava-overlay-2b53xq8m/lava-10597244/bin/lava-test-set
149 22:13:54.194958 Creating /var/lib/lava/dispatcher/tmp/10597244/lava-overlay-2b53xq8m/lava-10597244/bin/lava-test-shell
150 22:13:54.195086 Updating /var/lib/lava/dispatcher/tmp/10597244/lava-overlay-2b53xq8m/lava-10597244/bin/lava-install-packages (oe)
151 22:13:54.195562 Updating /var/lib/lava/dispatcher/tmp/10597244/lava-overlay-2b53xq8m/lava-10597244/bin/lava-installed-packages (oe)
152 22:13:54.195689 Creating /var/lib/lava/dispatcher/tmp/10597244/lava-overlay-2b53xq8m/lava-10597244/environment
153 22:13:54.195796 LAVA metadata
154 22:13:54.195874 - LAVA_JOB_ID=10597244
155 22:13:54.195942 - LAVA_DISPATCHER_IP=192.168.201.1
156 22:13:54.196051 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 22:13:54.196127 skipped lava-vland-overlay
158 22:13:54.196206 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 22:13:54.196294 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 22:13:54.196358 skipped lava-multinode-overlay
161 22:13:54.196434 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 22:13:54.196523 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 22:13:54.196604 Loading test definitions
164 22:13:54.196698 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 22:13:54.196774 Using /lava-10597244 at stage 0
166 22:13:54.197154 uuid=10597244_1.5.2.3.1 testdef=None
167 22:13:54.197254 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 22:13:54.197341 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 22:13:54.197869 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 22:13:54.198233 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 22:13:54.199116 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 22:13:54.199458 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 22:13:54.203073 runner path: /var/lib/lava/dispatcher/tmp/10597244/lava-overlay-2b53xq8m/lava-10597244/0/tests/0_igt-kms-mediatek test_uuid 10597244_1.5.2.3.1
176 22:13:54.203272 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 22:13:54.203526 Creating lava-test-runner.conf files
179 22:13:54.203592 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10597244/lava-overlay-2b53xq8m/lava-10597244/0 for stage 0
180 22:13:54.203680 - 0_igt-kms-mediatek
181 22:13:54.203782 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 22:13:54.203868 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 22:13:54.211013 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 22:13:54.211146 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 22:13:54.211242 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 22:13:54.211334 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 22:13:54.211443 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 22:13:55.602176 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 22:13:55.602777 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 22:13:55.603003 extracting modules file /var/lib/lava/dispatcher/tmp/10597244/tftp-deploy-2dx16yrn/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10597244/extract-overlay-ramdisk-4ztu1o5_/ramdisk
191 22:13:55.899013 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 22:13:55.899201 start: 1.5.5 apply-overlay-tftp (timeout 00:09:57) [common]
193 22:13:55.899345 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10597244/compress-overlay-172k13dz/overlay-1.5.2.4.tar.gz to ramdisk
194 22:13:55.899439 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10597244/compress-overlay-172k13dz/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/10597244/extract-overlay-ramdisk-4ztu1o5_/ramdisk
195 22:13:55.906247 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 22:13:55.906391 start: 1.5.6 configure-preseed-file (timeout 00:09:57) [common]
197 22:13:55.906503 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 22:13:55.906616 start: 1.5.7 compress-ramdisk (timeout 00:09:57) [common]
199 22:13:55.906715 Building ramdisk /var/lib/lava/dispatcher/tmp/10597244/extract-overlay-ramdisk-4ztu1o5_/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/10597244/extract-overlay-ramdisk-4ztu1o5_/ramdisk
200 22:13:56.878074 >> 369045 blocks
201 22:14:02.850669 rename /var/lib/lava/dispatcher/tmp/10597244/extract-overlay-ramdisk-4ztu1o5_/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/10597244/tftp-deploy-2dx16yrn/ramdisk/ramdisk.cpio.gz
202 22:14:02.851219 end: 1.5.7 compress-ramdisk (duration 00:00:07) [common]
203 22:14:02.851453 start: 1.5.8 prepare-kernel (timeout 00:09:50) [common]
204 22:14:02.851600 start: 1.5.8.1 prepare-fit (timeout 00:09:50) [common]
205 22:14:02.851760 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/10597244/tftp-deploy-2dx16yrn/kernel/Image'
206 22:14:15.732074 Returned 0 in 12 seconds
207 22:14:15.832693 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/10597244/tftp-deploy-2dx16yrn/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/10597244/tftp-deploy-2dx16yrn/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/10597244/tftp-deploy-2dx16yrn/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/10597244/tftp-deploy-2dx16yrn/kernel/image.itb
208 22:14:16.617992 output: FIT description: Kernel Image image with one or more FDT blobs
209 22:14:16.618349 output: Created: Mon Jun 5 23:14:16 2023
210 22:14:16.618435 output: Image 0 (kernel-1)
211 22:14:16.618504 output: Description:
212 22:14:16.618567 output: Created: Mon Jun 5 23:14:16 2023
213 22:14:16.618631 output: Type: Kernel Image
214 22:14:16.618694 output: Compression: lzma compressed
215 22:14:16.618754 output: Data Size: 10082307 Bytes = 9846.00 KiB = 9.62 MiB
216 22:14:16.618816 output: Architecture: AArch64
217 22:14:16.618875 output: OS: Linux
218 22:14:16.618936 output: Load Address: 0x00000000
219 22:14:16.618993 output: Entry Point: 0x00000000
220 22:14:16.619052 output: Hash algo: crc32
221 22:14:16.619109 output: Hash value: c242daf7
222 22:14:16.619165 output: Image 1 (fdt-1)
223 22:14:16.619248 output: Description: mt8192-asurada-spherion-r0
224 22:14:16.619337 output: Created: Mon Jun 5 23:14:16 2023
225 22:14:16.619441 output: Type: Flat Device Tree
226 22:14:16.619498 output: Compression: uncompressed
227 22:14:16.619553 output: Data Size: 46924 Bytes = 45.82 KiB = 0.04 MiB
228 22:14:16.619608 output: Architecture: AArch64
229 22:14:16.619663 output: Hash algo: crc32
230 22:14:16.619721 output: Hash value: 1df858fa
231 22:14:16.619776 output: Image 2 (ramdisk-1)
232 22:14:16.619879 output: Description: unavailable
233 22:14:16.619943 output: Created: Mon Jun 5 23:14:16 2023
234 22:14:16.620031 output: Type: RAMDisk Image
235 22:14:16.620093 output: Compression: Unknown Compression
236 22:14:16.620149 output: Data Size: 56374687 Bytes = 55053.41 KiB = 53.76 MiB
237 22:14:16.620204 output: Architecture: AArch64
238 22:14:16.620259 output: OS: Linux
239 22:14:16.620313 output: Load Address: unavailable
240 22:14:16.620367 output: Entry Point: unavailable
241 22:14:16.620420 output: Hash algo: crc32
242 22:14:16.620474 output: Hash value: e02ce17f
243 22:14:16.620528 output: Default Configuration: 'conf-1'
244 22:14:16.620581 output: Configuration 0 (conf-1)
245 22:14:16.620635 output: Description: mt8192-asurada-spherion-r0
246 22:14:16.620689 output: Kernel: kernel-1
247 22:14:16.620742 output: Init Ramdisk: ramdisk-1
248 22:14:16.620795 output: FDT: fdt-1
249 22:14:16.620853 output: Loadables: kernel-1
250 22:14:16.620906 output:
251 22:14:16.621107 end: 1.5.8.1 prepare-fit (duration 00:00:14) [common]
252 22:14:16.621207 end: 1.5.8 prepare-kernel (duration 00:00:14) [common]
253 22:14:16.621315 end: 1.5 prepare-tftp-overlay (duration 00:00:22) [common]
254 22:14:16.621411 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:37) [common]
255 22:14:16.621492 No LXC device requested
256 22:14:16.621573 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 22:14:16.621658 start: 1.7 deploy-device-env (timeout 00:09:37) [common]
258 22:14:16.621741 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 22:14:16.621847 Checking files for TFTP limit of 4294967296 bytes.
260 22:14:16.622354 end: 1 tftp-deploy (duration 00:00:23) [common]
261 22:14:16.622460 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 22:14:16.622555 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 22:14:16.622674 substitutions:
264 22:14:16.622742 - {DTB}: 10597244/tftp-deploy-2dx16yrn/dtb/mt8192-asurada-spherion-r0.dtb
265 22:14:16.622810 - {INITRD}: 10597244/tftp-deploy-2dx16yrn/ramdisk/ramdisk.cpio.gz
266 22:14:16.622871 - {KERNEL}: 10597244/tftp-deploy-2dx16yrn/kernel/Image
267 22:14:16.622930 - {LAVA_MAC}: None
268 22:14:16.622987 - {PRESEED_CONFIG}: None
269 22:14:16.623044 - {PRESEED_LOCAL}: None
270 22:14:16.623100 - {RAMDISK}: 10597244/tftp-deploy-2dx16yrn/ramdisk/ramdisk.cpio.gz
271 22:14:16.623156 - {ROOT_PART}: None
272 22:14:16.623212 - {ROOT}: None
273 22:14:16.623267 - {SERVER_IP}: 192.168.201.1
274 22:14:16.623321 - {TEE}: None
275 22:14:16.623412 Parsed boot commands:
276 22:14:16.623481 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 22:14:16.623671 Parsed boot commands: tftpboot 192.168.201.1 10597244/tftp-deploy-2dx16yrn/kernel/image.itb 10597244/tftp-deploy-2dx16yrn/kernel/cmdline
278 22:14:16.623790 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 22:14:16.623893 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 22:14:16.623984 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 22:14:16.624070 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 22:14:16.624140 Not connected, no need to disconnect.
283 22:14:16.624215 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 22:14:16.624296 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 22:14:16.624365 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost mt8192-asurada-spherion-r0-cbg-3'
286 22:14:16.628038 Setting prompt string to ['lava-test: # ']
287 22:14:16.628405 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 22:14:16.628519 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 22:14:16.628622 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 22:14:16.628716 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 22:14:16.628918 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-3' '--port=1' '--command=reboot'
292 22:14:21.762575 >> Command sent successfully.
293 22:14:21.764853 Returned 0 in 5 seconds
294 22:14:21.865221 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 22:14:21.865936 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 22:14:21.866058 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 22:14:21.866168 Setting prompt string to 'Starting depthcharge on Spherion...'
299 22:14:21.866251 Changing prompt to 'Starting depthcharge on Spherion...'
300 22:14:21.866332 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 22:14:21.866623 [Enter `^Ec?' for help]
302 22:14:22.039113
303 22:14:22.039262
304 22:14:22.039341 F0: 102B 0000
305 22:14:22.039412
306 22:14:22.039472 F3: 1001 0000 [0200]
307 22:14:22.039532
308 22:14:22.042679 F3: 1001 0000
309 22:14:22.042772
310 22:14:22.042858 F7: 102D 0000
311 22:14:22.042940
312 22:14:22.045721 F1: 0000 0000
313 22:14:22.045879
314 22:14:22.045996 V0: 0000 0000 [0001]
315 22:14:22.046090
316 22:14:22.049341 00: 0007 8000
317 22:14:22.049503
318 22:14:22.049610 01: 0000 0000
319 22:14:22.049697
320 22:14:22.052539 BP: 0C00 0209 [0000]
321 22:14:22.052625
322 22:14:22.052711 G0: 1182 0000
323 22:14:22.052792
324 22:14:22.052871 EC: 0000 0021 [4000]
325 22:14:22.055864
326 22:14:22.055966 S7: 0000 0000 [0000]
327 22:14:22.056048
328 22:14:22.059457 CC: 0000 0000 [0001]
329 22:14:22.059543
330 22:14:22.059629 T0: 0000 0040 [010F]
331 22:14:22.059710
332 22:14:22.059789 Jump to BL
333 22:14:22.059886
334 22:14:22.086118
335 22:14:22.086251
336 22:14:22.086355
337 22:14:22.093311 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 22:14:22.096550 ARM64: Exception handlers installed.
339 22:14:22.100647 ARM64: Testing exception
340 22:14:22.103728 ARM64: Done test exception
341 22:14:22.109857 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 22:14:22.120275 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 22:14:22.127196 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 22:14:22.136991 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 22:14:22.144033 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 22:14:22.154046 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 22:14:22.164008 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 22:14:22.170967 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 22:14:22.188810 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 22:14:22.192277 WDT: Last reset was cold boot
351 22:14:22.195499 SPI1(PAD0) initialized at 2873684 Hz
352 22:14:22.198759 SPI5(PAD0) initialized at 992727 Hz
353 22:14:22.202234 VBOOT: Loading verstage.
354 22:14:22.208816 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 22:14:22.212572 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 22:14:22.215566 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 22:14:22.219270 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 22:14:22.226577 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 22:14:22.232750 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 22:14:22.243668 read SPI 0x96554 0xa1eb: 4595 us, 9020 KB/s, 72.160 Mbps
361 22:14:22.243758
362 22:14:22.243827
363 22:14:22.253958 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 22:14:22.257150 ARM64: Exception handlers installed.
365 22:14:22.260696 ARM64: Testing exception
366 22:14:22.260783 ARM64: Done test exception
367 22:14:22.267058 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 22:14:22.270598 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 22:14:22.286339 Probing TPM: . done!
370 22:14:22.286431 TPM ready after 0 ms
371 22:14:22.293584 Connected to device vid:did:rid of 1ae0:0028:00
372 22:14:22.300727 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
373 22:14:22.358674 Initialized TPM device CR50 revision 0
374 22:14:22.370521 tlcl_send_startup: Startup return code is 0
375 22:14:22.370630 TPM: setup succeeded
376 22:14:22.382258 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 22:14:22.390544 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 22:14:22.402727 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 22:14:22.412069 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 22:14:22.415732 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 22:14:22.420420 in-header: 03 07 00 00 08 00 00 00
382 22:14:22.424046 in-data: aa e4 47 04 13 02 00 00
383 22:14:22.427400 Chrome EC: UHEPI supported
384 22:14:22.434490 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 22:14:22.438621 in-header: 03 ad 00 00 08 00 00 00
386 22:14:22.442152 in-data: 00 20 20 08 00 00 00 00
387 22:14:22.442238 Phase 1
388 22:14:22.445959 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 22:14:22.453456 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 22:14:22.457542 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 22:14:22.461151 Recovery requested (1009000e)
392 22:14:22.471054 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 22:14:22.474382 tlcl_extend: response is 0
394 22:14:22.484547 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 22:14:22.490337 tlcl_extend: response is 0
396 22:14:22.497446 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 22:14:22.517595 read SPI 0x210d4 0x2173b: 15144 us, 9047 KB/s, 72.376 Mbps
398 22:14:22.524082 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 22:14:22.524181
400 22:14:22.524250
401 22:14:22.534764 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 22:14:22.538191 ARM64: Exception handlers installed.
403 22:14:22.538278 ARM64: Testing exception
404 22:14:22.541732 ARM64: Done test exception
405 22:14:22.562931 pmic_efuse_setting: Set efuses in 11 msecs
406 22:14:22.566720 pmwrap_interface_init: Select PMIF_VLD_RDY
407 22:14:22.573404 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 22:14:22.576695 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 22:14:22.580287 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 22:14:22.587955 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 22:14:22.590914 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 22:14:22.595171 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 22:14:22.601947 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 22:14:22.605498 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 22:14:22.609327 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 22:14:22.617087 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 22:14:22.621066 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 22:14:22.624901 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 22:14:22.628565 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 22:14:22.636011 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 22:14:22.639583 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 22:14:22.646673 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 22:14:22.654318 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 22:14:22.657686 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 22:14:22.665712 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 22:14:22.668651 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 22:14:22.676416 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 22:14:22.680171 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 22:14:22.687213 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 22:14:22.690630 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 22:14:22.698067 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 22:14:22.701347 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 22:14:22.708839 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 22:14:22.713063 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 22:14:22.716219 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 22:14:22.719994 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 22:14:22.727376 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 22:14:22.730997 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 22:14:22.738486 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 22:14:22.741435 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 22:14:22.745131 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 22:14:22.752474 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 22:14:22.756184 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 22:14:22.763919 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 22:14:22.767317 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 22:14:22.771247 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 22:14:22.774701 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 22:14:22.778380 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 22:14:22.785507 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 22:14:22.789453 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 22:14:22.793715 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 22:14:22.796882 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 22:14:22.800256 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 22:14:22.804229 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 22:14:22.811504 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 22:14:22.814954 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 22:14:22.818602 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 22:14:22.826214 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 22:14:22.833112 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 22:14:22.840602 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 22:14:22.847601 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 22:14:22.855667 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 22:14:22.859061 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 22:14:22.866292 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 22:14:22.869767 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 22:14:22.877128 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x0
467 22:14:22.881051 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 22:14:22.888119 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
469 22:14:22.891540 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 22:14:22.900481 [RTC]rtc_get_frequency_meter,154: input=15, output=791
471 22:14:22.909703 [RTC]rtc_get_frequency_meter,154: input=23, output=978
472 22:14:22.919242 [RTC]rtc_get_frequency_meter,154: input=19, output=884
473 22:14:22.929041 [RTC]rtc_get_frequency_meter,154: input=17, output=837
474 22:14:22.938123 [RTC]rtc_get_frequency_meter,154: input=16, output=813
475 22:14:22.948070 [RTC]rtc_get_frequency_meter,154: input=15, output=791
476 22:14:22.957658 [RTC]rtc_get_frequency_meter,154: input=16, output=813
477 22:14:22.961861 [RTC]rtc_eosc_cali,47: left: 15, middle: 15, right: 16
478 22:14:22.968608 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
479 22:14:22.972412 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
480 22:14:22.976067 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
481 22:14:22.979794 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
482 22:14:22.983617 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
483 22:14:22.986886 ADC[4]: Raw value=901328 ID=7
484 22:14:22.990937 ADC[3]: Raw value=213336 ID=1
485 22:14:22.991022 RAM Code: 0x71
486 22:14:22.995058 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
487 22:14:23.002176 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
488 22:14:23.009065 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
489 22:14:23.016713 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
490 22:14:23.016799 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
491 22:14:23.020718 in-header: 03 07 00 00 08 00 00 00
492 22:14:23.024704 in-data: aa e4 47 04 13 02 00 00
493 22:14:23.028186 Chrome EC: UHEPI supported
494 22:14:23.035422 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
495 22:14:23.039462 in-header: 03 ed 00 00 08 00 00 00
496 22:14:23.042475 in-data: 80 20 60 08 00 00 00 00
497 22:14:23.046531 MRC: failed to locate region type 0.
498 22:14:23.054118 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
499 22:14:23.054204 DRAM-K: Running full calibration
500 22:14:23.060921 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
501 22:14:23.064638 header.status = 0x0
502 22:14:23.068621 header.version = 0x6 (expected: 0x6)
503 22:14:23.068707 header.size = 0xd00 (expected: 0xd00)
504 22:14:23.072330 header.flags = 0x0
505 22:14:23.076536 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
506 22:14:23.095810 read SPI 0x72590 0x1c583: 12503 us, 9285 KB/s, 74.280 Mbps
507 22:14:23.103564 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
508 22:14:23.107247 dram_init: ddr_geometry: 2
509 22:14:23.107340 [EMI] MDL number = 2
510 22:14:23.110409 [EMI] Get MDL freq = 0
511 22:14:23.110496 dram_init: ddr_type: 0
512 22:14:23.114028 is_discrete_lpddr4: 1
513 22:14:23.117860 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
514 22:14:23.117990
515 22:14:23.118062
516 22:14:23.121891 [Bian_co] ETT version 0.0.0.1
517 22:14:23.124963 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
518 22:14:23.125053
519 22:14:23.128431 dramc_set_vcore_voltage set vcore to 650000
520 22:14:23.132146 Read voltage for 800, 4
521 22:14:23.132234 Vio18 = 0
522 22:14:23.132303 Vcore = 650000
523 22:14:23.132367 Vdram = 0
524 22:14:23.136384 Vddq = 0
525 22:14:23.136486 Vmddr = 0
526 22:14:23.139890 dram_init: config_dvfs: 1
527 22:14:23.143340 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
528 22:14:23.147207 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
529 22:14:23.154631 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=10
530 22:14:23.157452 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=10
531 22:14:23.161131 [SwImpedanceCal] DRVP=12, DRVN=25, ODTN=9
532 22:14:23.163889 freq_region=1, Reg: DRVP=12, DRVN=25, ODTN=9
533 22:14:23.167869 MEM_TYPE=3, freq_sel=18
534 22:14:23.168059 sv_algorithm_assistance_LP4_1600
535 22:14:23.173991 ============ PULL DRAM RESETB DOWN ============
536 22:14:23.177484 ========== PULL DRAM RESETB DOWN end =========
537 22:14:23.180678 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
538 22:14:23.183899 ===================================
539 22:14:23.187757 LPDDR4 DRAM CONFIGURATION
540 22:14:23.190522 ===================================
541 22:14:23.194376 EX_ROW_EN[0] = 0x0
542 22:14:23.194633 EX_ROW_EN[1] = 0x0
543 22:14:23.197939 LP4Y_EN = 0x0
544 22:14:23.198240 WORK_FSP = 0x0
545 22:14:23.201199 WL = 0x2
546 22:14:23.201518 RL = 0x2
547 22:14:23.204489 BL = 0x2
548 22:14:23.204833 RPST = 0x0
549 22:14:23.207751 RD_PRE = 0x0
550 22:14:23.208075 WR_PRE = 0x1
551 22:14:23.211034 WR_PST = 0x0
552 22:14:23.211451 DBI_WR = 0x0
553 22:14:23.214999 DBI_RD = 0x0
554 22:14:23.215600 OTF = 0x1
555 22:14:23.217978 ===================================
556 22:14:23.221450 ===================================
557 22:14:23.224472 ANA top config
558 22:14:23.228104 ===================================
559 22:14:23.228510 DLL_ASYNC_EN = 0
560 22:14:23.231451 ALL_SLAVE_EN = 1
561 22:14:23.234976 NEW_RANK_MODE = 1
562 22:14:23.237708 DLL_IDLE_MODE = 1
563 22:14:23.241461 LP45_APHY_COMB_EN = 1
564 22:14:23.241967 TX_ODT_DIS = 1
565 22:14:23.244831 NEW_8X_MODE = 1
566 22:14:23.247754 ===================================
567 22:14:23.251535 ===================================
568 22:14:23.254564 data_rate = 1600
569 22:14:23.258016 CKR = 1
570 22:14:23.261518 DQ_P2S_RATIO = 8
571 22:14:23.265155 ===================================
572 22:14:23.265660 CA_P2S_RATIO = 8
573 22:14:23.268637 DQ_CA_OPEN = 0
574 22:14:23.271592 DQ_SEMI_OPEN = 0
575 22:14:23.274898 CA_SEMI_OPEN = 0
576 22:14:23.277982 CA_FULL_RATE = 0
577 22:14:23.281626 DQ_CKDIV4_EN = 1
578 22:14:23.282213 CA_CKDIV4_EN = 1
579 22:14:23.284913 CA_PREDIV_EN = 0
580 22:14:23.287932 PH8_DLY = 0
581 22:14:23.291609 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
582 22:14:23.295111 DQ_AAMCK_DIV = 4
583 22:14:23.295540 CA_AAMCK_DIV = 4
584 22:14:23.298099 CA_ADMCK_DIV = 4
585 22:14:23.301412 DQ_TRACK_CA_EN = 0
586 22:14:23.304746 CA_PICK = 800
587 22:14:23.308164 CA_MCKIO = 800
588 22:14:23.311607 MCKIO_SEMI = 0
589 22:14:23.315336 PLL_FREQ = 3068
590 22:14:23.315875 DQ_UI_PI_RATIO = 32
591 22:14:23.318976 CA_UI_PI_RATIO = 0
592 22:14:23.322462 ===================================
593 22:14:23.325757 ===================================
594 22:14:23.329377 memory_type:LPDDR4
595 22:14:23.329813 GP_NUM : 10
596 22:14:23.333227 SRAM_EN : 1
597 22:14:23.333664 MD32_EN : 0
598 22:14:23.336906 ===================================
599 22:14:23.340361 [ANA_INIT] >>>>>>>>>>>>>>
600 22:14:23.344422 <<<<<< [CONFIGURE PHASE]: ANA_TX
601 22:14:23.347435 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
602 22:14:23.350834 ===================================
603 22:14:23.351238 data_rate = 1600,PCW = 0X7600
604 22:14:23.354758 ===================================
605 22:14:23.357315 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
606 22:14:23.364195 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 22:14:23.371123 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
608 22:14:23.374277 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
609 22:14:23.377490 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
610 22:14:23.381021 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
611 22:14:23.384039 [ANA_INIT] flow start
612 22:14:23.384443 [ANA_INIT] PLL >>>>>>>>
613 22:14:23.387579 [ANA_INIT] PLL <<<<<<<<
614 22:14:23.391013 [ANA_INIT] MIDPI >>>>>>>>
615 22:14:23.394357 [ANA_INIT] MIDPI <<<<<<<<
616 22:14:23.394804 [ANA_INIT] DLL >>>>>>>>
617 22:14:23.397735 [ANA_INIT] flow end
618 22:14:23.400863 ============ LP4 DIFF to SE enter ============
619 22:14:23.404123 ============ LP4 DIFF to SE exit ============
620 22:14:23.407890 [ANA_INIT] <<<<<<<<<<<<<
621 22:14:23.411125 [Flow] Enable top DCM control >>>>>
622 22:14:23.414292 [Flow] Enable top DCM control <<<<<
623 22:14:23.418157 Enable DLL master slave shuffle
624 22:14:23.421462 ==============================================================
625 22:14:23.424515 Gating Mode config
626 22:14:23.431705 ==============================================================
627 22:14:23.432217 Config description:
628 22:14:23.441148 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
629 22:14:23.448070 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
630 22:14:23.454625 SELPH_MODE 0: By rank 1: By Phase
631 22:14:23.457678 ==============================================================
632 22:14:23.461489 GAT_TRACK_EN = 1
633 22:14:23.464352 RX_GATING_MODE = 2
634 22:14:23.468155 RX_GATING_TRACK_MODE = 2
635 22:14:23.470894 SELPH_MODE = 1
636 22:14:23.474871 PICG_EARLY_EN = 1
637 22:14:23.477455 VALID_LAT_VALUE = 1
638 22:14:23.481101 ==============================================================
639 22:14:23.484902 Enter into Gating configuration >>>>
640 22:14:23.487984 Exit from Gating configuration <<<<
641 22:14:23.491431 Enter into DVFS_PRE_config >>>>>
642 22:14:23.504595 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
643 22:14:23.505204 Exit from DVFS_PRE_config <<<<<
644 22:14:23.508135 Enter into PICG configuration >>>>
645 22:14:23.511033 Exit from PICG configuration <<<<
646 22:14:23.514695 [RX_INPUT] configuration >>>>>
647 22:14:23.517705 [RX_INPUT] configuration <<<<<
648 22:14:23.524676 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
649 22:14:23.528039 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
650 22:14:23.534879 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
651 22:14:23.542667 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
652 22:14:23.545810 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
653 22:14:23.552249 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
654 22:14:23.555855 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
655 22:14:23.562211 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
656 22:14:23.564913 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
657 22:14:23.568786 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
658 22:14:23.572141 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
659 22:14:23.578995 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
660 22:14:23.581777 ===================================
661 22:14:23.584918 LPDDR4 DRAM CONFIGURATION
662 22:14:23.588372 ===================================
663 22:14:23.588918 EX_ROW_EN[0] = 0x0
664 22:14:23.592282 EX_ROW_EN[1] = 0x0
665 22:14:23.592835 LP4Y_EN = 0x0
666 22:14:23.595310 WORK_FSP = 0x0
667 22:14:23.595894 WL = 0x2
668 22:14:23.598565 RL = 0x2
669 22:14:23.599108 BL = 0x2
670 22:14:23.601987 RPST = 0x0
671 22:14:23.602531 RD_PRE = 0x0
672 22:14:23.605527 WR_PRE = 0x1
673 22:14:23.606084 WR_PST = 0x0
674 22:14:23.608158 DBI_WR = 0x0
675 22:14:23.608604 DBI_RD = 0x0
676 22:14:23.612119 OTF = 0x1
677 22:14:23.615110 ===================================
678 22:14:23.618226 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
679 22:14:23.622021 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
680 22:14:23.628383 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
681 22:14:23.632048 ===================================
682 22:14:23.632552 LPDDR4 DRAM CONFIGURATION
683 22:14:23.635737 ===================================
684 22:14:23.638373 EX_ROW_EN[0] = 0x10
685 22:14:23.641875 EX_ROW_EN[1] = 0x0
686 22:14:23.642317 LP4Y_EN = 0x0
687 22:14:23.645996 WORK_FSP = 0x0
688 22:14:23.646517 WL = 0x2
689 22:14:23.648477 RL = 0x2
690 22:14:23.649033 BL = 0x2
691 22:14:23.651964 RPST = 0x0
692 22:14:23.652404 RD_PRE = 0x0
693 22:14:23.655931 WR_PRE = 0x1
694 22:14:23.656469 WR_PST = 0x0
695 22:14:23.658702 DBI_WR = 0x0
696 22:14:23.659238 DBI_RD = 0x0
697 22:14:23.662775 OTF = 0x1
698 22:14:23.665282 ===================================
699 22:14:23.671603 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
700 22:14:23.675511 nWR fixed to 40
701 22:14:23.676048 [ModeRegInit_LP4] CH0 RK0
702 22:14:23.678589 [ModeRegInit_LP4] CH0 RK1
703 22:14:23.682236 [ModeRegInit_LP4] CH1 RK0
704 22:14:23.682792 [ModeRegInit_LP4] CH1 RK1
705 22:14:23.685277 match AC timing 13
706 22:14:23.688680 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
707 22:14:23.692062 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
708 22:14:23.699097 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
709 22:14:23.701611 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
710 22:14:23.708862 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
711 22:14:23.709402 [EMI DOE] emi_dcm 0
712 22:14:23.715340 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
713 22:14:23.715928 ==
714 22:14:23.718580 Dram Type= 6, Freq= 0, CH_0, rank 0
715 22:14:23.722082 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
716 22:14:23.722689 ==
717 22:14:23.724804 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
718 22:14:23.731776 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
719 22:14:23.741805 [CA 0] Center 37 (7~68) winsize 62
720 22:14:23.744933 [CA 1] Center 37 (6~68) winsize 63
721 22:14:23.748232 [CA 2] Center 35 (4~66) winsize 63
722 22:14:23.751936 [CA 3] Center 34 (4~65) winsize 62
723 22:14:23.755164 [CA 4] Center 34 (4~64) winsize 61
724 22:14:23.758870 [CA 5] Center 34 (4~64) winsize 61
725 22:14:23.759462
726 22:14:23.762388 [CmdBusTrainingLP45] Vref(ca) range 1: 34
727 22:14:23.762937
728 22:14:23.765128 [CATrainingPosCal] consider 1 rank data
729 22:14:23.768907 u2DelayCellTimex100 = 270/100 ps
730 22:14:23.771879 CA0 delay=37 (7~68),Diff = 3 PI (21 cell)
731 22:14:23.778750 CA1 delay=37 (6~68),Diff = 3 PI (21 cell)
732 22:14:23.781514 CA2 delay=35 (4~66),Diff = 1 PI (7 cell)
733 22:14:23.785252 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
734 22:14:23.788927 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
735 22:14:23.791664 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
736 22:14:23.792110
737 22:14:23.795431 CA PerBit enable=1, Macro0, CA PI delay=34
738 22:14:23.796137
739 22:14:23.798696 [CBTSetCACLKResult] CA Dly = 34
740 22:14:23.799248 CS Dly: 5 (0~36)
741 22:14:23.801514 ==
742 22:14:23.801977 Dram Type= 6, Freq= 0, CH_0, rank 1
743 22:14:23.808034 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
744 22:14:23.808482 ==
745 22:14:23.811458 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
746 22:14:23.818740 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
747 22:14:23.828144 [CA 0] Center 37 (6~68) winsize 63
748 22:14:23.831512 [CA 1] Center 37 (7~68) winsize 62
749 22:14:23.834991 [CA 2] Center 35 (4~66) winsize 63
750 22:14:23.837896 [CA 3] Center 35 (4~66) winsize 63
751 22:14:23.841907 [CA 4] Center 34 (3~65) winsize 63
752 22:14:23.844627 [CA 5] Center 33 (3~64) winsize 62
753 22:14:23.845071
754 22:14:23.847991 [CmdBusTrainingLP45] Vref(ca) range 1: 34
755 22:14:23.848431
756 22:14:23.851503 [CATrainingPosCal] consider 2 rank data
757 22:14:23.854400 u2DelayCellTimex100 = 270/100 ps
758 22:14:23.857933 CA0 delay=37 (7~68),Diff = 3 PI (21 cell)
759 22:14:23.860995 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
760 22:14:23.868157 CA2 delay=35 (4~66),Diff = 1 PI (7 cell)
761 22:14:23.871439 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
762 22:14:23.875171 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
763 22:14:23.878308 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
764 22:14:23.878748
765 22:14:23.881037 CA PerBit enable=1, Macro0, CA PI delay=34
766 22:14:23.881520
767 22:14:23.884705 [CBTSetCACLKResult] CA Dly = 34
768 22:14:23.885146 CS Dly: 5 (0~37)
769 22:14:23.885500
770 22:14:23.888428 ----->DramcWriteLeveling(PI) begin...
771 22:14:23.891689 ==
772 22:14:23.892226 Dram Type= 6, Freq= 0, CH_0, rank 0
773 22:14:23.898336 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
774 22:14:23.898785 ==
775 22:14:23.902010 Write leveling (Byte 0): 28 => 28
776 22:14:23.902452 Write leveling (Byte 1): 28 => 28
777 22:14:23.905905 DramcWriteLeveling(PI) end<-----
778 22:14:23.906461
779 22:14:23.906825 ==
780 22:14:23.909584 Dram Type= 6, Freq= 0, CH_0, rank 0
781 22:14:23.915983 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
782 22:14:23.916437 ==
783 22:14:23.916793 [Gating] SW mode calibration
784 22:14:23.923445 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
785 22:14:23.929636 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
786 22:14:23.933264 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
787 22:14:23.939883 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
788 22:14:23.943436 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
789 22:14:23.946929 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 22:14:23.950159 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 22:14:23.956569 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 22:14:23.959896 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 22:14:23.963443 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 22:14:23.969543 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 22:14:23.973524 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 22:14:23.976706 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 22:14:23.983736 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 22:14:23.987053 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 22:14:23.990198 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 22:14:23.996341 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 22:14:24.000073 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 22:14:24.002976 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 22:14:24.010003 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
804 22:14:24.013505 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
805 22:14:24.016814 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 22:14:24.023454 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 22:14:24.027179 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 22:14:24.030082 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 22:14:24.033925 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 22:14:24.040190 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 22:14:24.043440 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 22:14:24.046886 0 9 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
813 22:14:24.053817 0 9 12 | B1->B0 | 2b2b 3333 | 0 0 | (0 0) (0 0)
814 22:14:24.057363 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 22:14:24.060024 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 22:14:24.066782 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 22:14:24.069952 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 22:14:24.073453 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
819 22:14:24.080346 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
820 22:14:24.083149 0 10 8 | B1->B0 | 3333 2f2f | 1 1 | (1 1) (1 0)
821 22:14:24.087126 0 10 12 | B1->B0 | 2c2c 2424 | 0 0 | (1 0) (1 0)
822 22:14:24.093370 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 22:14:24.096984 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 22:14:24.100750 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 22:14:24.103321 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 22:14:24.110320 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 22:14:24.113427 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
828 22:14:24.116848 0 11 8 | B1->B0 | 2525 3131 | 1 0 | (0 0) (0 0)
829 22:14:24.123502 0 11 12 | B1->B0 | 3939 4242 | 0 0 | (0 0) (0 0)
830 22:14:24.126677 0 11 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
831 22:14:24.130311 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 22:14:24.136898 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 22:14:24.139929 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 22:14:24.143561 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 22:14:24.150827 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
836 22:14:24.153542 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
837 22:14:24.157305 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
838 22:14:24.163868 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 22:14:24.167246 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 22:14:24.170135 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 22:14:24.176750 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 22:14:24.180328 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 22:14:24.183474 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 22:14:24.187036 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 22:14:24.193485 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 22:14:24.197375 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 22:14:24.200178 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 22:14:24.207200 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 22:14:24.210239 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 22:14:24.214187 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 22:14:24.220168 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
852 22:14:24.223613 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
853 22:14:24.227203 Total UI for P1: 0, mck2ui 16
854 22:14:24.230419 best dqsien dly found for B0: ( 0, 14, 6)
855 22:14:24.233503 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
856 22:14:24.240708 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
857 22:14:24.241088 Total UI for P1: 0, mck2ui 16
858 22:14:24.247314 best dqsien dly found for B1: ( 0, 14, 10)
859 22:14:24.250591 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
860 22:14:24.253574 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
861 22:14:24.254121
862 22:14:24.256869 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
863 22:14:24.260934 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
864 22:14:24.263471 [Gating] SW calibration Done
865 22:14:24.263986 ==
866 22:14:24.267191 Dram Type= 6, Freq= 0, CH_0, rank 0
867 22:14:24.269954 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
868 22:14:24.270525 ==
869 22:14:24.273748 RX Vref Scan: 0
870 22:14:24.274309
871 22:14:24.274821 RX Vref 0 -> 0, step: 1
872 22:14:24.275346
873 22:14:24.276777 RX Delay -130 -> 252, step: 16
874 22:14:24.280219 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
875 22:14:24.286751 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
876 22:14:24.290169 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
877 22:14:24.293791 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
878 22:14:24.296525 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
879 22:14:24.300318 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
880 22:14:24.306760 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
881 22:14:24.310352 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
882 22:14:24.313445 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
883 22:14:24.317354 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
884 22:14:24.320468 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
885 22:14:24.327257 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
886 22:14:24.330205 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
887 22:14:24.333646 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
888 22:14:24.337084 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
889 22:14:24.340041 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
890 22:14:24.343596 ==
891 22:14:24.344003 Dram Type= 6, Freq= 0, CH_0, rank 0
892 22:14:24.350669 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
893 22:14:24.351199 ==
894 22:14:24.351676 DQS Delay:
895 22:14:24.354013 DQS0 = 0, DQS1 = 0
896 22:14:24.354422 DQM Delay:
897 22:14:24.354748 DQM0 = 84, DQM1 = 78
898 22:14:24.356612 DQ Delay:
899 22:14:24.360475 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
900 22:14:24.363131 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =85
901 22:14:24.366292 DQ8 =61, DQ9 =69, DQ10 =77, DQ11 =77
902 22:14:24.370469 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
903 22:14:24.370555
904 22:14:24.370625
905 22:14:24.370688 ==
906 22:14:24.373267 Dram Type= 6, Freq= 0, CH_0, rank 0
907 22:14:24.376182 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
908 22:14:24.376268 ==
909 22:14:24.376337
910 22:14:24.376401
911 22:14:24.379624 TX Vref Scan disable
912 22:14:24.383237 == TX Byte 0 ==
913 22:14:24.386293 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
914 22:14:24.389993 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
915 22:14:24.393353 == TX Byte 1 ==
916 22:14:24.396577 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
917 22:14:24.399889 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
918 22:14:24.399975 ==
919 22:14:24.403245 Dram Type= 6, Freq= 0, CH_0, rank 0
920 22:14:24.406547 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
921 22:14:24.406636 ==
922 22:14:24.420766 TX Vref=22, minBit 7, minWin=26, winSum=435
923 22:14:24.424215 TX Vref=24, minBit 3, minWin=27, winSum=442
924 22:14:24.427903 TX Vref=26, minBit 0, minWin=27, winSum=446
925 22:14:24.430944 TX Vref=28, minBit 0, minWin=28, winSum=451
926 22:14:24.434443 TX Vref=30, minBit 8, minWin=27, winSum=450
927 22:14:24.437888 TX Vref=32, minBit 3, minWin=27, winSum=450
928 22:14:24.444229 [TxChooseVref] Worse bit 0, Min win 28, Win sum 451, Final Vref 28
929 22:14:24.444314
930 22:14:24.447749 Final TX Range 1 Vref 28
931 22:14:24.447834
932 22:14:24.447901 ==
933 22:14:24.450728 Dram Type= 6, Freq= 0, CH_0, rank 0
934 22:14:24.454280 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
935 22:14:24.454365 ==
936 22:14:24.454433
937 22:14:24.454508
938 22:14:24.457759 TX Vref Scan disable
939 22:14:24.460785 == TX Byte 0 ==
940 22:14:24.464736 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
941 22:14:24.467624 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
942 22:14:24.470832 == TX Byte 1 ==
943 22:14:24.474255 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
944 22:14:24.478158 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
945 22:14:24.478243
946 22:14:24.481139 [DATLAT]
947 22:14:24.481223 Freq=800, CH0 RK0
948 22:14:24.481290
949 22:14:24.484605 DATLAT Default: 0xa
950 22:14:24.484688 0, 0xFFFF, sum = 0
951 22:14:24.488008 1, 0xFFFF, sum = 0
952 22:14:24.488097 2, 0xFFFF, sum = 0
953 22:14:24.491010 3, 0xFFFF, sum = 0
954 22:14:24.491122 4, 0xFFFF, sum = 0
955 22:14:24.494144 5, 0xFFFF, sum = 0
956 22:14:24.494257 6, 0xFFFF, sum = 0
957 22:14:24.498333 7, 0xFFFF, sum = 0
958 22:14:24.498418 8, 0xFFFF, sum = 0
959 22:14:24.501328 9, 0x0, sum = 1
960 22:14:24.501413 10, 0x0, sum = 2
961 22:14:24.504847 11, 0x0, sum = 3
962 22:14:24.504933 12, 0x0, sum = 4
963 22:14:24.508014 best_step = 10
964 22:14:24.508098
965 22:14:24.508164 ==
966 22:14:24.511189 Dram Type= 6, Freq= 0, CH_0, rank 0
967 22:14:24.514732 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
968 22:14:24.514827 ==
969 22:14:24.518114 RX Vref Scan: 1
970 22:14:24.518197
971 22:14:24.518264 Set Vref Range= 32 -> 127
972 22:14:24.518326
973 22:14:24.521521 RX Vref 32 -> 127, step: 1
974 22:14:24.521605
975 22:14:24.524544 RX Delay -95 -> 252, step: 8
976 22:14:24.524628
977 22:14:24.527883 Set Vref, RX VrefLevel [Byte0]: 32
978 22:14:24.531177 [Byte1]: 32
979 22:14:24.531262
980 22:14:24.534937 Set Vref, RX VrefLevel [Byte0]: 33
981 22:14:24.538419 [Byte1]: 33
982 22:14:24.538505
983 22:14:24.541938 Set Vref, RX VrefLevel [Byte0]: 34
984 22:14:24.545370 [Byte1]: 34
985 22:14:24.548460
986 22:14:24.548546 Set Vref, RX VrefLevel [Byte0]: 35
987 22:14:24.552026 [Byte1]: 35
988 22:14:24.556188
989 22:14:24.556274 Set Vref, RX VrefLevel [Byte0]: 36
990 22:14:24.559330 [Byte1]: 36
991 22:14:24.563628
992 22:14:24.563714 Set Vref, RX VrefLevel [Byte0]: 37
993 22:14:24.567235 [Byte1]: 37
994 22:14:24.572034
995 22:14:24.572120 Set Vref, RX VrefLevel [Byte0]: 38
996 22:14:24.575245 [Byte1]: 38
997 22:14:24.579244
998 22:14:24.579381 Set Vref, RX VrefLevel [Byte0]: 39
999 22:14:24.582771 [Byte1]: 39
1000 22:14:24.586890
1001 22:14:24.586975 Set Vref, RX VrefLevel [Byte0]: 40
1002 22:14:24.590406 [Byte1]: 40
1003 22:14:24.594751
1004 22:14:24.594836 Set Vref, RX VrefLevel [Byte0]: 41
1005 22:14:24.597500 [Byte1]: 41
1006 22:14:24.602052
1007 22:14:24.602137 Set Vref, RX VrefLevel [Byte0]: 42
1008 22:14:24.605385 [Byte1]: 42
1009 22:14:24.609129
1010 22:14:24.609214 Set Vref, RX VrefLevel [Byte0]: 43
1011 22:14:24.612328 [Byte1]: 43
1012 22:14:24.616740
1013 22:14:24.616828 Set Vref, RX VrefLevel [Byte0]: 44
1014 22:14:24.619901 [Byte1]: 44
1015 22:14:24.624587
1016 22:14:24.624673 Set Vref, RX VrefLevel [Byte0]: 45
1017 22:14:24.627976 [Byte1]: 45
1018 22:14:24.632105
1019 22:14:24.632190 Set Vref, RX VrefLevel [Byte0]: 46
1020 22:14:24.635674 [Byte1]: 46
1021 22:14:24.639827
1022 22:14:24.639911 Set Vref, RX VrefLevel [Byte0]: 47
1023 22:14:24.642777 [Byte1]: 47
1024 22:14:24.647155
1025 22:14:24.647244 Set Vref, RX VrefLevel [Byte0]: 48
1026 22:14:24.650666 [Byte1]: 48
1027 22:14:24.654850
1028 22:14:24.654932 Set Vref, RX VrefLevel [Byte0]: 49
1029 22:14:24.658432 [Byte1]: 49
1030 22:14:24.662601
1031 22:14:24.662684 Set Vref, RX VrefLevel [Byte0]: 50
1032 22:14:24.665537 [Byte1]: 50
1033 22:14:24.669915
1034 22:14:24.670002 Set Vref, RX VrefLevel [Byte0]: 51
1035 22:14:24.673641 [Byte1]: 51
1036 22:14:24.677575
1037 22:14:24.677659 Set Vref, RX VrefLevel [Byte0]: 52
1038 22:14:24.681174 [Byte1]: 52
1039 22:14:24.685469
1040 22:14:24.685552 Set Vref, RX VrefLevel [Byte0]: 53
1041 22:14:24.688422 [Byte1]: 53
1042 22:14:24.692862
1043 22:14:24.692945 Set Vref, RX VrefLevel [Byte0]: 54
1044 22:14:24.699288 [Byte1]: 54
1045 22:14:24.699426
1046 22:14:24.702675 Set Vref, RX VrefLevel [Byte0]: 55
1047 22:14:24.706204 [Byte1]: 55
1048 22:14:24.706288
1049 22:14:24.709204 Set Vref, RX VrefLevel [Byte0]: 56
1050 22:14:24.712384 [Byte1]: 56
1051 22:14:24.712467
1052 22:14:24.715791 Set Vref, RX VrefLevel [Byte0]: 57
1053 22:14:24.719480 [Byte1]: 57
1054 22:14:24.722995
1055 22:14:24.723078 Set Vref, RX VrefLevel [Byte0]: 58
1056 22:14:24.726495 [Byte1]: 58
1057 22:14:24.730916
1058 22:14:24.730999 Set Vref, RX VrefLevel [Byte0]: 59
1059 22:14:24.734130 [Byte1]: 59
1060 22:14:24.738557
1061 22:14:24.738640 Set Vref, RX VrefLevel [Byte0]: 60
1062 22:14:24.741482 [Byte1]: 60
1063 22:14:24.746101
1064 22:14:24.746185 Set Vref, RX VrefLevel [Byte0]: 61
1065 22:14:24.749124 [Byte1]: 61
1066 22:14:24.753592
1067 22:14:24.753675 Set Vref, RX VrefLevel [Byte0]: 62
1068 22:14:24.756578 [Byte1]: 62
1069 22:14:24.761232
1070 22:14:24.761315 Set Vref, RX VrefLevel [Byte0]: 63
1071 22:14:24.764349 [Byte1]: 63
1072 22:14:24.768991
1073 22:14:24.769073 Set Vref, RX VrefLevel [Byte0]: 64
1074 22:14:24.771800 [Byte1]: 64
1075 22:14:24.776416
1076 22:14:24.776499 Set Vref, RX VrefLevel [Byte0]: 65
1077 22:14:24.779395 [Byte1]: 65
1078 22:14:24.783845
1079 22:14:24.783928 Set Vref, RX VrefLevel [Byte0]: 66
1080 22:14:24.787185 [Byte1]: 66
1081 22:14:24.791757
1082 22:14:24.791840 Set Vref, RX VrefLevel [Byte0]: 67
1083 22:14:24.794814 [Byte1]: 67
1084 22:14:24.798981
1085 22:14:24.799064 Set Vref, RX VrefLevel [Byte0]: 68
1086 22:14:24.802404 [Byte1]: 68
1087 22:14:24.806502
1088 22:14:24.806584 Set Vref, RX VrefLevel [Byte0]: 69
1089 22:14:24.810005 [Byte1]: 69
1090 22:14:24.814439
1091 22:14:24.814522 Set Vref, RX VrefLevel [Byte0]: 70
1092 22:14:24.817859 [Byte1]: 70
1093 22:14:24.821720
1094 22:14:24.821803 Set Vref, RX VrefLevel [Byte0]: 71
1095 22:14:24.825215 [Byte1]: 71
1096 22:14:24.829534
1097 22:14:24.829617 Set Vref, RX VrefLevel [Byte0]: 72
1098 22:14:24.833101 [Byte1]: 72
1099 22:14:24.836982
1100 22:14:24.837068 Set Vref, RX VrefLevel [Byte0]: 73
1101 22:14:24.840811 [Byte1]: 73
1102 22:14:24.845050
1103 22:14:24.845132 Set Vref, RX VrefLevel [Byte0]: 74
1104 22:14:24.847860 [Byte1]: 74
1105 22:14:24.852135
1106 22:14:24.852218 Set Vref, RX VrefLevel [Byte0]: 75
1107 22:14:24.855537 [Byte1]: 75
1108 22:14:24.859653
1109 22:14:24.859762 Set Vref, RX VrefLevel [Byte0]: 76
1110 22:14:24.863282 [Byte1]: 76
1111 22:14:24.867436
1112 22:14:24.867518 Final RX Vref Byte 0 = 61 to rank0
1113 22:14:24.871082 Final RX Vref Byte 1 = 56 to rank0
1114 22:14:24.874157 Final RX Vref Byte 0 = 61 to rank1
1115 22:14:24.877462 Final RX Vref Byte 1 = 56 to rank1==
1116 22:14:24.880895 Dram Type= 6, Freq= 0, CH_0, rank 0
1117 22:14:24.884425 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1118 22:14:24.887887 ==
1119 22:14:24.887961 DQS Delay:
1120 22:14:24.888024 DQS0 = 0, DQS1 = 0
1121 22:14:24.891234 DQM Delay:
1122 22:14:24.891336 DQM0 = 88, DQM1 = 78
1123 22:14:24.894158 DQ Delay:
1124 22:14:24.897724 DQ0 =88, DQ1 =92, DQ2 =84, DQ3 =84
1125 22:14:24.897828 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1126 22:14:24.901137 DQ8 =68, DQ9 =64, DQ10 =80, DQ11 =76
1127 22:14:24.904147 DQ12 =84, DQ13 =80, DQ14 =88, DQ15 =88
1128 22:14:24.907682
1129 22:14:24.907763
1130 22:14:24.914437 [DQSOSCAuto] RK0, (LSB)MR18= 0x2a11, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 399 ps
1131 22:14:24.917652 CH0 RK0: MR19=606, MR18=2A11
1132 22:14:24.924370 CH0_RK0: MR19=0x606, MR18=0x2A11, DQSOSC=399, MR23=63, INC=92, DEC=61
1133 22:14:24.924457
1134 22:14:24.927633 ----->DramcWriteLeveling(PI) begin...
1135 22:14:24.927718 ==
1136 22:14:24.931063 Dram Type= 6, Freq= 0, CH_0, rank 1
1137 22:14:24.934304 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1138 22:14:24.934390 ==
1139 22:14:24.937615 Write leveling (Byte 0): 29 => 29
1140 22:14:24.941132 Write leveling (Byte 1): 28 => 28
1141 22:14:24.944821 DramcWriteLeveling(PI) end<-----
1142 22:14:24.944899
1143 22:14:24.944973 ==
1144 22:14:24.947704 Dram Type= 6, Freq= 0, CH_0, rank 1
1145 22:14:24.951446 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1146 22:14:24.951526 ==
1147 22:14:24.954450 [Gating] SW mode calibration
1148 22:14:24.961355 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1149 22:14:24.967851 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1150 22:14:24.971152 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1151 22:14:24.974827 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1152 22:14:25.018628 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1153 22:14:25.018902 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1154 22:14:25.019194 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1155 22:14:25.019300 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1156 22:14:25.019626 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 22:14:25.019697 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 22:14:25.019955 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 22:14:25.020272 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 22:14:25.020363 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 22:14:25.020608 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 22:14:25.062726 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 22:14:25.063015 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 22:14:25.063107 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 22:14:25.063177 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 22:14:25.063438 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 22:14:25.063521 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
1168 22:14:25.063619 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1169 22:14:25.063707 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 22:14:25.063801 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 22:14:25.063918 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 22:14:25.089143 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 22:14:25.089427 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 22:14:25.089731 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 22:14:25.089807 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 22:14:25.090057 0 9 8 | B1->B0 | 2323 3030 | 0 1 | (0 0) (1 1)
1177 22:14:25.093222 0 9 12 | B1->B0 | 2f2f 3434 | 1 1 | (1 1) (1 1)
1178 22:14:25.096265 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1179 22:14:25.099714 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1180 22:14:25.103322 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1181 22:14:25.106750 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1182 22:14:25.112761 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1183 22:14:25.116194 0 10 4 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
1184 22:14:25.119632 0 10 8 | B1->B0 | 3333 2828 | 1 0 | (1 0) (0 0)
1185 22:14:25.123188 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1186 22:14:25.129652 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1187 22:14:25.133068 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 22:14:25.136983 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 22:14:25.143057 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 22:14:25.147025 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 22:14:25.150623 0 11 4 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
1192 22:14:25.154291 0 11 8 | B1->B0 | 2626 4545 | 0 0 | (0 0) (0 0)
1193 22:14:25.158274 0 11 12 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
1194 22:14:25.165201 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1195 22:14:25.168612 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1196 22:14:25.172043 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1197 22:14:25.179038 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1198 22:14:25.181987 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1199 22:14:25.185622 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1200 22:14:25.189129 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1201 22:14:25.195868 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1202 22:14:25.198798 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1203 22:14:25.202350 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 22:14:25.208910 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 22:14:25.212357 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 22:14:25.215875 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 22:14:25.222352 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 22:14:25.225425 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 22:14:25.229006 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 22:14:25.235336 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 22:14:25.238746 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 22:14:25.242062 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 22:14:25.249015 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 22:14:25.252043 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 22:14:25.255737 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 22:14:25.262001 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1217 22:14:25.262085 Total UI for P1: 0, mck2ui 16
1218 22:14:25.269177 best dqsien dly found for B0: ( 0, 14, 6)
1219 22:14:25.272277 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1220 22:14:25.275759 Total UI for P1: 0, mck2ui 16
1221 22:14:25.279838 best dqsien dly found for B1: ( 0, 14, 8)
1222 22:14:25.281990 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1223 22:14:25.285666 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1224 22:14:25.285742
1225 22:14:25.289176 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1226 22:14:25.292126 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1227 22:14:25.295840 [Gating] SW calibration Done
1228 22:14:25.295917 ==
1229 22:14:25.299485 Dram Type= 6, Freq= 0, CH_0, rank 1
1230 22:14:25.302372 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1231 22:14:25.302449 ==
1232 22:14:25.306161 RX Vref Scan: 0
1233 22:14:25.306241
1234 22:14:25.306315 RX Vref 0 -> 0, step: 1
1235 22:14:25.306381
1236 22:14:25.309055 RX Delay -130 -> 252, step: 16
1237 22:14:25.316258 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1238 22:14:25.319073 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1239 22:14:25.322019 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1240 22:14:25.325645 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1241 22:14:25.328712 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1242 22:14:25.335715 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
1243 22:14:25.338759 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1244 22:14:25.342216 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1245 22:14:25.345589 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1246 22:14:25.348674 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1247 22:14:25.355330 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1248 22:14:25.358653 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1249 22:14:25.361863 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
1250 22:14:25.365607 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1251 22:14:25.368955 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1252 22:14:25.375144 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1253 22:14:25.375231 ==
1254 22:14:25.378525 Dram Type= 6, Freq= 0, CH_0, rank 1
1255 22:14:25.382312 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1256 22:14:25.382401 ==
1257 22:14:25.382468 DQS Delay:
1258 22:14:25.385690 DQS0 = 0, DQS1 = 0
1259 22:14:25.385774 DQM Delay:
1260 22:14:25.388798 DQM0 = 88, DQM1 = 77
1261 22:14:25.388881 DQ Delay:
1262 22:14:25.391698 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
1263 22:14:25.395074 DQ4 =85, DQ5 =77, DQ6 =101, DQ7 =101
1264 22:14:25.398360 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1265 22:14:25.401803 DQ12 =77, DQ13 =85, DQ14 =85, DQ15 =85
1266 22:14:25.401903
1267 22:14:25.401969
1268 22:14:25.402030 ==
1269 22:14:25.405183 Dram Type= 6, Freq= 0, CH_0, rank 1
1270 22:14:25.408879 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1271 22:14:25.412094 ==
1272 22:14:25.412179
1273 22:14:25.412245
1274 22:14:25.412307 TX Vref Scan disable
1275 22:14:25.415392 == TX Byte 0 ==
1276 22:14:25.418760 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1277 22:14:25.421779 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1278 22:14:25.425015 == TX Byte 1 ==
1279 22:14:25.428403 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1280 22:14:25.431421 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1281 22:14:25.434936 ==
1282 22:14:25.438751 Dram Type= 6, Freq= 0, CH_0, rank 1
1283 22:14:25.441924 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1284 22:14:25.442029 ==
1285 22:14:25.454451 TX Vref=22, minBit 2, minWin=27, winSum=444
1286 22:14:25.457278 TX Vref=24, minBit 6, minWin=27, winSum=445
1287 22:14:25.460908 TX Vref=26, minBit 9, minWin=27, winSum=448
1288 22:14:25.465021 TX Vref=28, minBit 9, minWin=27, winSum=457
1289 22:14:25.467521 TX Vref=30, minBit 0, minWin=28, winSum=455
1290 22:14:25.470758 TX Vref=32, minBit 0, minWin=28, winSum=451
1291 22:14:25.477485 [TxChooseVref] Worse bit 0, Min win 28, Win sum 455, Final Vref 30
1292 22:14:25.477574
1293 22:14:25.480838 Final TX Range 1 Vref 30
1294 22:14:25.480924
1295 22:14:25.480989 ==
1296 22:14:25.484005 Dram Type= 6, Freq= 0, CH_0, rank 1
1297 22:14:25.487800 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1298 22:14:25.487889 ==
1299 22:14:25.487954
1300 22:14:25.488015
1301 22:14:25.491172 TX Vref Scan disable
1302 22:14:25.494484 == TX Byte 0 ==
1303 22:14:25.497556 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1304 22:14:25.501179 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1305 22:14:25.504051 == TX Byte 1 ==
1306 22:14:25.507407 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1307 22:14:25.510885 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1308 22:14:25.510975
1309 22:14:25.513977 [DATLAT]
1310 22:14:25.514057 Freq=800, CH0 RK1
1311 22:14:25.514124
1312 22:14:25.517348 DATLAT Default: 0xa
1313 22:14:25.517425 0, 0xFFFF, sum = 0
1314 22:14:25.521092 1, 0xFFFF, sum = 0
1315 22:14:25.521172 2, 0xFFFF, sum = 0
1316 22:14:25.524112 3, 0xFFFF, sum = 0
1317 22:14:25.524195 4, 0xFFFF, sum = 0
1318 22:14:25.527370 5, 0xFFFF, sum = 0
1319 22:14:25.527473 6, 0xFFFF, sum = 0
1320 22:14:25.531097 7, 0xFFFF, sum = 0
1321 22:14:25.531182 8, 0xFFFF, sum = 0
1322 22:14:25.534388 9, 0x0, sum = 1
1323 22:14:25.534460 10, 0x0, sum = 2
1324 22:14:25.537382 11, 0x0, sum = 3
1325 22:14:25.537472 12, 0x0, sum = 4
1326 22:14:25.541078 best_step = 10
1327 22:14:25.541154
1328 22:14:25.541222 ==
1329 22:14:25.543934 Dram Type= 6, Freq= 0, CH_0, rank 1
1330 22:14:25.547536 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1331 22:14:25.547618 ==
1332 22:14:25.550901 RX Vref Scan: 0
1333 22:14:25.550984
1334 22:14:25.551048 RX Vref 0 -> 0, step: 1
1335 22:14:25.551109
1336 22:14:25.554398 RX Delay -95 -> 252, step: 8
1337 22:14:25.561077 iDelay=209, Bit 0, Center 84 (-31 ~ 200) 232
1338 22:14:25.564125 iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224
1339 22:14:25.567585 iDelay=209, Bit 2, Center 84 (-31 ~ 200) 232
1340 22:14:25.570706 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
1341 22:14:25.574065 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1342 22:14:25.580916 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1343 22:14:25.583997 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1344 22:14:25.587424 iDelay=209, Bit 7, Center 92 (-23 ~ 208) 232
1345 22:14:25.590691 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
1346 22:14:25.594171 iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216
1347 22:14:25.600612 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1348 22:14:25.603966 iDelay=209, Bit 11, Center 68 (-39 ~ 176) 216
1349 22:14:25.607527 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
1350 22:14:25.610760 iDelay=209, Bit 13, Center 80 (-31 ~ 192) 224
1351 22:14:25.614303 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1352 22:14:25.620933 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1353 22:14:25.621031 ==
1354 22:14:25.624046 Dram Type= 6, Freq= 0, CH_0, rank 1
1355 22:14:25.627320 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1356 22:14:25.627448 ==
1357 22:14:25.627517 DQS Delay:
1358 22:14:25.630813 DQS0 = 0, DQS1 = 0
1359 22:14:25.630897 DQM Delay:
1360 22:14:25.634315 DQM0 = 86, DQM1 = 77
1361 22:14:25.634399 DQ Delay:
1362 22:14:25.637247 DQ0 =84, DQ1 =88, DQ2 =84, DQ3 =84
1363 22:14:25.640832 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =92
1364 22:14:25.644222 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
1365 22:14:25.647252 DQ12 =80, DQ13 =80, DQ14 =88, DQ15 =88
1366 22:14:25.647387
1367 22:14:25.647469
1368 22:14:25.654103 [DQSOSCAuto] RK1, (LSB)MR18= 0x331c, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 396 ps
1369 22:14:25.657482 CH0 RK1: MR19=606, MR18=331C
1370 22:14:25.664149 CH0_RK1: MR19=0x606, MR18=0x331C, DQSOSC=396, MR23=63, INC=94, DEC=62
1371 22:14:25.667692 [RxdqsGatingPostProcess] freq 800
1372 22:14:25.674159 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1373 22:14:25.677938 Pre-setting of DQS Precalculation
1374 22:14:25.680587 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1375 22:14:25.680671 ==
1376 22:14:25.684387 Dram Type= 6, Freq= 0, CH_1, rank 0
1377 22:14:25.687542 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1378 22:14:25.687626 ==
1379 22:14:25.693675 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1380 22:14:25.700377 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1381 22:14:25.708870 [CA 0] Center 36 (6~66) winsize 61
1382 22:14:25.712462 [CA 1] Center 36 (6~66) winsize 61
1383 22:14:25.715805 [CA 2] Center 34 (4~65) winsize 62
1384 22:14:25.719157 [CA 3] Center 33 (3~64) winsize 62
1385 22:14:25.722249 [CA 4] Center 34 (4~65) winsize 62
1386 22:14:25.725775 [CA 5] Center 34 (4~64) winsize 61
1387 22:14:25.725860
1388 22:14:25.728752 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1389 22:14:25.728836
1390 22:14:25.732228 [CATrainingPosCal] consider 1 rank data
1391 22:14:25.735630 u2DelayCellTimex100 = 270/100 ps
1392 22:14:25.738710 CA0 delay=36 (6~66),Diff = 3 PI (21 cell)
1393 22:14:25.745109 CA1 delay=36 (6~66),Diff = 3 PI (21 cell)
1394 22:14:25.748694 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1395 22:14:25.752173 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
1396 22:14:25.755276 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1397 22:14:25.758877 CA5 delay=34 (4~64),Diff = 1 PI (7 cell)
1398 22:14:25.758960
1399 22:14:25.762365 CA PerBit enable=1, Macro0, CA PI delay=33
1400 22:14:25.762448
1401 22:14:25.765169 [CBTSetCACLKResult] CA Dly = 33
1402 22:14:25.765251 CS Dly: 4 (0~35)
1403 22:14:25.768666 ==
1404 22:14:25.768749 Dram Type= 6, Freq= 0, CH_1, rank 1
1405 22:14:25.775882 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1406 22:14:25.775965 ==
1407 22:14:25.778712 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1408 22:14:25.785293 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1409 22:14:25.795300 [CA 0] Center 36 (6~66) winsize 61
1410 22:14:25.798655 [CA 1] Center 36 (6~66) winsize 61
1411 22:14:25.801564 [CA 2] Center 34 (4~64) winsize 61
1412 22:14:25.804929 [CA 3] Center 33 (3~64) winsize 62
1413 22:14:25.809005 [CA 4] Center 34 (4~65) winsize 62
1414 22:14:25.812512 [CA 5] Center 33 (3~64) winsize 62
1415 22:14:25.812596
1416 22:14:25.815864 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1417 22:14:25.815973
1418 22:14:25.819796 [CATrainingPosCal] consider 2 rank data
1419 22:14:25.823091 u2DelayCellTimex100 = 270/100 ps
1420 22:14:25.826821 CA0 delay=36 (6~66),Diff = 3 PI (21 cell)
1421 22:14:25.830417 CA1 delay=36 (6~66),Diff = 3 PI (21 cell)
1422 22:14:25.833935 CA2 delay=34 (4~64),Diff = 1 PI (7 cell)
1423 22:14:25.837733 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
1424 22:14:25.841441 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1425 22:14:25.844943 CA5 delay=34 (4~64),Diff = 1 PI (7 cell)
1426 22:14:25.845075
1427 22:14:25.848557 CA PerBit enable=1, Macro0, CA PI delay=33
1428 22:14:25.848655
1429 22:14:25.851580 [CBTSetCACLKResult] CA Dly = 33
1430 22:14:25.851663 CS Dly: 5 (0~37)
1431 22:14:25.851729
1432 22:14:25.854979 ----->DramcWriteLeveling(PI) begin...
1433 22:14:25.855064 ==
1434 22:14:25.858609 Dram Type= 6, Freq= 0, CH_1, rank 0
1435 22:14:25.865147 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1436 22:14:25.865231 ==
1437 22:14:25.868260 Write leveling (Byte 0): 26 => 26
1438 22:14:25.871786 Write leveling (Byte 1): 31 => 31
1439 22:14:25.871869 DramcWriteLeveling(PI) end<-----
1440 22:14:25.875373
1441 22:14:25.875469 ==
1442 22:14:25.878510 Dram Type= 6, Freq= 0, CH_1, rank 0
1443 22:14:25.882101 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1444 22:14:25.882185 ==
1445 22:14:25.885175 [Gating] SW mode calibration
1446 22:14:25.891530 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1447 22:14:25.895555 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1448 22:14:25.902044 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1449 22:14:25.905557 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1450 22:14:25.908744 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1451 22:14:25.915129 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1452 22:14:25.919145 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1453 22:14:25.922153 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 22:14:25.928431 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 22:14:25.932066 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 22:14:25.935369 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 22:14:25.942145 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 22:14:25.945185 0 7 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1459 22:14:25.948474 0 7 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1460 22:14:25.952059 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 22:14:25.958470 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 22:14:25.962097 0 7 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1463 22:14:25.965133 0 7 28 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1464 22:14:25.972118 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 22:14:25.975614 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1466 22:14:25.978500 0 8 8 | B1->B0 | 2424 2323 | 0 0 | (1 1) (1 0)
1467 22:14:25.985241 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1468 22:14:25.988799 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 22:14:25.991800 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 22:14:25.998875 0 8 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1471 22:14:26.002711 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 22:14:26.005245 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 22:14:26.011891 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 22:14:26.015156 0 9 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
1475 22:14:26.018924 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1476 22:14:26.025716 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1477 22:14:26.028856 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1478 22:14:26.032091 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1479 22:14:26.035277 0 9 28 | B1->B0 | 3535 3434 | 1 1 | (0 0) (1 1)
1480 22:14:26.042013 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1481 22:14:26.045602 0 10 4 | B1->B0 | 3535 3434 | 0 1 | (0 1) (1 0)
1482 22:14:26.048953 0 10 8 | B1->B0 | 2f2f 2f2f | 1 1 | (1 0) (1 0)
1483 22:14:26.055251 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1484 22:14:26.058627 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1485 22:14:26.062425 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 22:14:26.068783 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 22:14:26.071887 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 22:14:26.075605 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 22:14:26.082161 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 22:14:26.085474 0 11 8 | B1->B0 | 3636 3434 | 0 0 | (1 1) (0 0)
1491 22:14:26.088397 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1492 22:14:26.095510 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1493 22:14:26.098487 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1494 22:14:26.102207 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1495 22:14:26.108594 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1496 22:14:26.112063 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1497 22:14:26.115099 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1498 22:14:26.122102 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1499 22:14:26.125549 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1500 22:14:26.128454 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1501 22:14:26.132540 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1502 22:14:26.138698 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 22:14:26.142179 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 22:14:26.145383 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 22:14:26.152209 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 22:14:26.155456 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 22:14:26.159072 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 22:14:26.165609 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 22:14:26.168486 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 22:14:26.172147 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 22:14:26.178643 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 22:14:26.181961 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 22:14:26.185380 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1514 22:14:26.191805 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1515 22:14:26.195727 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1516 22:14:26.198930 Total UI for P1: 0, mck2ui 16
1517 22:14:26.202012 best dqsien dly found for B0: ( 0, 14, 10)
1518 22:14:26.205046 Total UI for P1: 0, mck2ui 16
1519 22:14:26.208522 best dqsien dly found for B1: ( 0, 14, 6)
1520 22:14:26.212142 best DQS0 dly(MCK, UI, PI) = (0, 14, 10)
1521 22:14:26.215543 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1522 22:14:26.215626
1523 22:14:26.218930 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 10)
1524 22:14:26.221791 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1525 22:14:26.225341 [Gating] SW calibration Done
1526 22:14:26.225423 ==
1527 22:14:26.228407 Dram Type= 6, Freq= 0, CH_1, rank 0
1528 22:14:26.232362 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1529 22:14:26.232445 ==
1530 22:14:26.235408 RX Vref Scan: 0
1531 22:14:26.235516
1532 22:14:26.238701 RX Vref 0 -> 0, step: 1
1533 22:14:26.238784
1534 22:14:26.238850 RX Delay -130 -> 252, step: 16
1535 22:14:26.245178 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1536 22:14:26.248394 iDelay=222, Bit 1, Center 69 (-50 ~ 189) 240
1537 22:14:26.252188 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1538 22:14:26.255656 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1539 22:14:26.258842 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1540 22:14:26.265424 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1541 22:14:26.268269 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1542 22:14:26.272053 iDelay=222, Bit 7, Center 69 (-50 ~ 189) 240
1543 22:14:26.275443 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1544 22:14:26.278453 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
1545 22:14:26.285395 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1546 22:14:26.288374 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1547 22:14:26.291953 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1548 22:14:26.295633 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1549 22:14:26.298646 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1550 22:14:26.305700 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1551 22:14:26.305783 ==
1552 22:14:26.308558 Dram Type= 6, Freq= 0, CH_1, rank 0
1553 22:14:26.312250 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1554 22:14:26.312334 ==
1555 22:14:26.312400 DQS Delay:
1556 22:14:26.315227 DQS0 = 0, DQS1 = 0
1557 22:14:26.315309 DQM Delay:
1558 22:14:26.318724 DQM0 = 82, DQM1 = 76
1559 22:14:26.318806 DQ Delay:
1560 22:14:26.321737 DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =85
1561 22:14:26.325165 DQ4 =85, DQ5 =101, DQ6 =93, DQ7 =69
1562 22:14:26.328387 DQ8 =69, DQ9 =61, DQ10 =69, DQ11 =69
1563 22:14:26.331758 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1564 22:14:26.331840
1565 22:14:26.331905
1566 22:14:26.331965 ==
1567 22:14:26.335195 Dram Type= 6, Freq= 0, CH_1, rank 0
1568 22:14:26.338518 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1569 22:14:26.341796 ==
1570 22:14:26.341879
1571 22:14:26.341944
1572 22:14:26.342006 TX Vref Scan disable
1573 22:14:26.345091 == TX Byte 0 ==
1574 22:14:26.348290 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1575 22:14:26.352103 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1576 22:14:26.354980 == TX Byte 1 ==
1577 22:14:26.358378 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1578 22:14:26.361556 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1579 22:14:26.365455 ==
1580 22:14:26.365538 Dram Type= 6, Freq= 0, CH_1, rank 0
1581 22:14:26.371508 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1582 22:14:26.371592 ==
1583 22:14:26.384694 TX Vref=22, minBit 11, minWin=26, winSum=438
1584 22:14:26.388067 TX Vref=24, minBit 0, minWin=27, winSum=440
1585 22:14:26.391020 TX Vref=26, minBit 4, minWin=27, winSum=445
1586 22:14:26.394695 TX Vref=28, minBit 3, minWin=27, winSum=448
1587 22:14:26.398244 TX Vref=30, minBit 0, minWin=28, winSum=453
1588 22:14:26.401832 TX Vref=32, minBit 1, minWin=28, winSum=453
1589 22:14:26.408130 [TxChooseVref] Worse bit 0, Min win 28, Win sum 453, Final Vref 30
1590 22:14:26.408213
1591 22:14:26.411791 Final TX Range 1 Vref 30
1592 22:14:26.411874
1593 22:14:26.411940 ==
1594 22:14:26.414815 Dram Type= 6, Freq= 0, CH_1, rank 0
1595 22:14:26.418376 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1596 22:14:26.418460 ==
1597 22:14:26.418527
1598 22:14:26.418588
1599 22:14:26.421448 TX Vref Scan disable
1600 22:14:26.424751 == TX Byte 0 ==
1601 22:14:26.428191 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1602 22:14:26.431697 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1603 22:14:26.434775 == TX Byte 1 ==
1604 22:14:26.438188 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1605 22:14:26.441529 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1606 22:14:26.441613
1607 22:14:26.444730 [DATLAT]
1608 22:14:26.444813 Freq=800, CH1 RK0
1609 22:14:26.444879
1610 22:14:26.448175 DATLAT Default: 0xa
1611 22:14:26.448257 0, 0xFFFF, sum = 0
1612 22:14:26.451650 1, 0xFFFF, sum = 0
1613 22:14:26.451734 2, 0xFFFF, sum = 0
1614 22:14:26.455259 3, 0xFFFF, sum = 0
1615 22:14:26.455343 4, 0xFFFF, sum = 0
1616 22:14:26.458327 5, 0xFFFF, sum = 0
1617 22:14:26.458411 6, 0xFFFF, sum = 0
1618 22:14:26.461723 7, 0xFFFF, sum = 0
1619 22:14:26.461807 8, 0xFFFF, sum = 0
1620 22:14:26.464684 9, 0x0, sum = 1
1621 22:14:26.464768 10, 0x0, sum = 2
1622 22:14:26.468062 11, 0x0, sum = 3
1623 22:14:26.468146 12, 0x0, sum = 4
1624 22:14:26.471259 best_step = 10
1625 22:14:26.471404
1626 22:14:26.471472 ==
1627 22:14:26.475233 Dram Type= 6, Freq= 0, CH_1, rank 0
1628 22:14:26.478073 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1629 22:14:26.478157 ==
1630 22:14:26.481696 RX Vref Scan: 1
1631 22:14:26.481779
1632 22:14:26.481845 Set Vref Range= 32 -> 127
1633 22:14:26.481906
1634 22:14:26.484722 RX Vref 32 -> 127, step: 1
1635 22:14:26.484804
1636 22:14:26.488168 RX Delay -95 -> 252, step: 8
1637 22:14:26.488250
1638 22:14:26.491090 Set Vref, RX VrefLevel [Byte0]: 32
1639 22:14:26.494570 [Byte1]: 32
1640 22:14:26.494653
1641 22:14:26.498233 Set Vref, RX VrefLevel [Byte0]: 33
1642 22:14:26.501209 [Byte1]: 33
1643 22:14:26.504462
1644 22:14:26.504546 Set Vref, RX VrefLevel [Byte0]: 34
1645 22:14:26.508245 [Byte1]: 34
1646 22:14:26.512381
1647 22:14:26.512465 Set Vref, RX VrefLevel [Byte0]: 35
1648 22:14:26.515767 [Byte1]: 35
1649 22:14:26.519975
1650 22:14:26.520059 Set Vref, RX VrefLevel [Byte0]: 36
1651 22:14:26.522972 [Byte1]: 36
1652 22:14:26.527694
1653 22:14:26.527776 Set Vref, RX VrefLevel [Byte0]: 37
1654 22:14:26.530958 [Byte1]: 37
1655 22:14:26.535172
1656 22:14:26.535256 Set Vref, RX VrefLevel [Byte0]: 38
1657 22:14:26.538198 [Byte1]: 38
1658 22:14:26.542697
1659 22:14:26.542781 Set Vref, RX VrefLevel [Byte0]: 39
1660 22:14:26.545886 [Byte1]: 39
1661 22:14:26.550456
1662 22:14:26.550540 Set Vref, RX VrefLevel [Byte0]: 40
1663 22:14:26.553317 [Byte1]: 40
1664 22:14:26.558046
1665 22:14:26.558129 Set Vref, RX VrefLevel [Byte0]: 41
1666 22:14:26.561275 [Byte1]: 41
1667 22:14:26.565341
1668 22:14:26.565431 Set Vref, RX VrefLevel [Byte0]: 42
1669 22:14:26.568652 [Byte1]: 42
1670 22:14:26.573164
1671 22:14:26.573248 Set Vref, RX VrefLevel [Byte0]: 43
1672 22:14:26.576166 [Byte1]: 43
1673 22:14:26.580579
1674 22:14:26.580662 Set Vref, RX VrefLevel [Byte0]: 44
1675 22:14:26.583835 [Byte1]: 44
1676 22:14:26.588486
1677 22:14:26.588569 Set Vref, RX VrefLevel [Byte0]: 45
1678 22:14:26.591377 [Byte1]: 45
1679 22:14:26.595910
1680 22:14:26.595993 Set Vref, RX VrefLevel [Byte0]: 46
1681 22:14:26.599380 [Byte1]: 46
1682 22:14:26.603487
1683 22:14:26.603570 Set Vref, RX VrefLevel [Byte0]: 47
1684 22:14:26.607180 [Byte1]: 47
1685 22:14:26.610912
1686 22:14:26.610998 Set Vref, RX VrefLevel [Byte0]: 48
1687 22:14:26.614983 [Byte1]: 48
1688 22:14:26.618796
1689 22:14:26.618879 Set Vref, RX VrefLevel [Byte0]: 49
1690 22:14:26.622256 [Byte1]: 49
1691 22:14:26.626785
1692 22:14:26.626869 Set Vref, RX VrefLevel [Byte0]: 50
1693 22:14:26.629513 [Byte1]: 50
1694 22:14:26.634151
1695 22:14:26.634234 Set Vref, RX VrefLevel [Byte0]: 51
1696 22:14:26.637007 [Byte1]: 51
1697 22:14:26.641256
1698 22:14:26.641339 Set Vref, RX VrefLevel [Byte0]: 52
1699 22:14:26.644707 [Byte1]: 52
1700 22:14:26.649001
1701 22:14:26.649085 Set Vref, RX VrefLevel [Byte0]: 53
1702 22:14:26.652543 [Byte1]: 53
1703 22:14:26.656539
1704 22:14:26.656622 Set Vref, RX VrefLevel [Byte0]: 54
1705 22:14:26.660036 [Byte1]: 54
1706 22:14:26.664023
1707 22:14:26.664106 Set Vref, RX VrefLevel [Byte0]: 55
1708 22:14:26.667960 [Byte1]: 55
1709 22:14:26.671869
1710 22:14:26.671953 Set Vref, RX VrefLevel [Byte0]: 56
1711 22:14:26.675056 [Byte1]: 56
1712 22:14:26.679579
1713 22:14:26.679661 Set Vref, RX VrefLevel [Byte0]: 57
1714 22:14:26.682863 [Byte1]: 57
1715 22:14:26.686969
1716 22:14:26.687053 Set Vref, RX VrefLevel [Byte0]: 58
1717 22:14:26.690407 [Byte1]: 58
1718 22:14:26.694563
1719 22:14:26.694646 Set Vref, RX VrefLevel [Byte0]: 59
1720 22:14:26.698035 [Byte1]: 59
1721 22:14:26.702046
1722 22:14:26.702130 Set Vref, RX VrefLevel [Byte0]: 60
1723 22:14:26.705477 [Byte1]: 60
1724 22:14:26.710186
1725 22:14:26.710269 Set Vref, RX VrefLevel [Byte0]: 61
1726 22:14:26.713016 [Byte1]: 61
1727 22:14:26.717190
1728 22:14:26.720767 Set Vref, RX VrefLevel [Byte0]: 62
1729 22:14:26.723580 [Byte1]: 62
1730 22:14:26.723663
1731 22:14:26.727176 Set Vref, RX VrefLevel [Byte0]: 63
1732 22:14:26.730589 [Byte1]: 63
1733 22:14:26.730673
1734 22:14:26.733867 Set Vref, RX VrefLevel [Byte0]: 64
1735 22:14:26.737203 [Byte1]: 64
1736 22:14:26.737287
1737 22:14:26.740586 Set Vref, RX VrefLevel [Byte0]: 65
1738 22:14:26.743553 [Byte1]: 65
1739 22:14:26.747785
1740 22:14:26.747868 Set Vref, RX VrefLevel [Byte0]: 66
1741 22:14:26.751220 [Byte1]: 66
1742 22:14:26.755075
1743 22:14:26.755158 Set Vref, RX VrefLevel [Byte0]: 67
1744 22:14:26.758566 [Byte1]: 67
1745 22:14:26.762711
1746 22:14:26.762794 Set Vref, RX VrefLevel [Byte0]: 68
1747 22:14:26.766284 [Byte1]: 68
1748 22:14:26.770474
1749 22:14:26.770557 Set Vref, RX VrefLevel [Byte0]: 69
1750 22:14:26.773697 [Byte1]: 69
1751 22:14:26.777945
1752 22:14:26.778028 Set Vref, RX VrefLevel [Byte0]: 70
1753 22:14:26.781621 [Byte1]: 70
1754 22:14:26.785932
1755 22:14:26.786015 Set Vref, RX VrefLevel [Byte0]: 71
1756 22:14:26.789160 [Byte1]: 71
1757 22:14:26.793455
1758 22:14:26.793551 Set Vref, RX VrefLevel [Byte0]: 72
1759 22:14:26.796477 [Byte1]: 72
1760 22:14:26.800918
1761 22:14:26.801002 Set Vref, RX VrefLevel [Byte0]: 73
1762 22:14:26.804360 [Byte1]: 73
1763 22:14:26.808472
1764 22:14:26.808559 Set Vref, RX VrefLevel [Byte0]: 74
1765 22:14:26.811898 [Byte1]: 74
1766 22:14:26.816147
1767 22:14:26.816226 Set Vref, RX VrefLevel [Byte0]: 75
1768 22:14:26.819499 [Byte1]: 75
1769 22:14:26.823573
1770 22:14:26.823652 Set Vref, RX VrefLevel [Byte0]: 76
1771 22:14:26.826998 [Byte1]: 76
1772 22:14:26.831500
1773 22:14:26.831579 Set Vref, RX VrefLevel [Byte0]: 77
1774 22:14:26.834676 [Byte1]: 77
1775 22:14:26.838889
1776 22:14:26.838960 Set Vref, RX VrefLevel [Byte0]: 78
1777 22:14:26.842546 [Byte1]: 78
1778 22:14:26.846350
1779 22:14:26.846430 Set Vref, RX VrefLevel [Byte0]: 79
1780 22:14:26.852783 [Byte1]: 79
1781 22:14:26.852860
1782 22:14:26.856327 Set Vref, RX VrefLevel [Byte0]: 80
1783 22:14:26.859565 [Byte1]: 80
1784 22:14:26.859641
1785 22:14:26.863104 Set Vref, RX VrefLevel [Byte0]: 81
1786 22:14:26.866495 [Byte1]: 81
1787 22:14:26.866576
1788 22:14:26.869681 Final RX Vref Byte 0 = 61 to rank0
1789 22:14:26.872682 Final RX Vref Byte 1 = 56 to rank0
1790 22:14:26.876483 Final RX Vref Byte 0 = 61 to rank1
1791 22:14:26.879225 Final RX Vref Byte 1 = 56 to rank1==
1792 22:14:26.883250 Dram Type= 6, Freq= 0, CH_1, rank 0
1793 22:14:26.886066 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1794 22:14:26.889744 ==
1795 22:14:26.889820 DQS Delay:
1796 22:14:26.889883 DQS0 = 0, DQS1 = 0
1797 22:14:26.892666 DQM Delay:
1798 22:14:26.892744 DQM0 = 84, DQM1 = 74
1799 22:14:26.895930 DQ Delay:
1800 22:14:26.896014 DQ0 =88, DQ1 =76, DQ2 =72, DQ3 =84
1801 22:14:26.899208 DQ4 =84, DQ5 =96, DQ6 =92, DQ7 =80
1802 22:14:26.902509 DQ8 =60, DQ9 =60, DQ10 =76, DQ11 =68
1803 22:14:26.906310 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =76
1804 22:14:26.906393
1805 22:14:26.909525
1806 22:14:26.916051 [DQSOSCAuto] RK0, (LSB)MR18= 0x27fc, (MSB)MR19= 0x605, tDQSOscB0 = 411 ps tDQSOscB1 = 400 ps
1807 22:14:26.919361 CH1 RK0: MR19=605, MR18=27FC
1808 22:14:26.925918 CH1_RK0: MR19=0x605, MR18=0x27FC, DQSOSC=400, MR23=63, INC=92, DEC=61
1809 22:14:26.926002
1810 22:14:26.929423 ----->DramcWriteLeveling(PI) begin...
1811 22:14:26.929507 ==
1812 22:14:26.932827 Dram Type= 6, Freq= 0, CH_1, rank 1
1813 22:14:26.936343 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1814 22:14:26.936427 ==
1815 22:14:26.939361 Write leveling (Byte 0): 27 => 27
1816 22:14:26.943010 Write leveling (Byte 1): 31 => 31
1817 22:14:26.945905 DramcWriteLeveling(PI) end<-----
1818 22:14:26.945988
1819 22:14:26.946053 ==
1820 22:14:26.949312 Dram Type= 6, Freq= 0, CH_1, rank 1
1821 22:14:26.952911 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1822 22:14:26.952994 ==
1823 22:14:26.956555 [Gating] SW mode calibration
1824 22:14:26.962859 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1825 22:14:26.969563 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1826 22:14:26.972600 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1827 22:14:26.976270 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1828 22:14:26.982874 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1829 22:14:26.986487 0 6 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1830 22:14:26.989658 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 22:14:26.996152 0 6 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1832 22:14:26.999630 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 22:14:27.002988 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 22:14:27.006215 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 22:14:27.013168 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 22:14:27.015913 0 7 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1837 22:14:27.019552 0 7 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1838 22:14:27.026126 0 7 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1839 22:14:27.029540 0 7 20 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1840 22:14:27.032652 0 7 24 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1841 22:14:27.039766 0 7 28 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1842 22:14:27.043163 0 8 0 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 1)
1843 22:14:27.046252 0 8 4 | B1->B0 | 2424 2323 | 0 0 | (0 1) (0 1)
1844 22:14:27.052495 0 8 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1845 22:14:27.056364 0 8 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1846 22:14:27.059327 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1847 22:14:27.066217 0 8 20 | B1->B0 | 2322 2323 | 1 0 | (0 0) (0 0)
1848 22:14:27.069564 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1849 22:14:27.072973 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1850 22:14:27.079578 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1851 22:14:27.083130 0 9 4 | B1->B0 | 2323 2727 | 0 1 | (0 0) (0 0)
1852 22:14:27.086235 0 9 8 | B1->B0 | 3131 3434 | 1 1 | (0 0) (1 1)
1853 22:14:27.092678 0 9 12 | B1->B0 | 3534 3434 | 1 1 | (0 0) (1 1)
1854 22:14:27.096158 0 9 16 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1855 22:14:27.099202 0 9 20 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1856 22:14:27.106032 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1857 22:14:27.109797 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1858 22:14:27.112771 0 10 0 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 0)
1859 22:14:27.116277 0 10 4 | B1->B0 | 3131 2d2d | 1 1 | (0 1) (1 0)
1860 22:14:27.123051 0 10 8 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
1861 22:14:27.126254 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1862 22:14:27.129551 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1863 22:14:27.136453 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1864 22:14:27.139229 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1865 22:14:27.142908 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1866 22:14:27.149539 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1867 22:14:27.153139 0 11 4 | B1->B0 | 2e2e 3939 | 0 0 | (0 0) (1 1)
1868 22:14:27.155997 0 11 8 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
1869 22:14:27.162979 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1870 22:14:27.166787 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1871 22:14:27.169502 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1872 22:14:27.175977 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1873 22:14:27.179714 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1874 22:14:27.182586 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1875 22:14:27.189224 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1876 22:14:27.192731 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1877 22:14:27.196174 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1878 22:14:27.202587 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1879 22:14:27.206064 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1880 22:14:27.209217 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1881 22:14:27.216228 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1882 22:14:27.219650 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1883 22:14:27.222714 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1884 22:14:27.225765 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1885 22:14:27.232690 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1886 22:14:27.236057 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1887 22:14:27.239334 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1888 22:14:27.246298 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1889 22:14:27.249085 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1890 22:14:27.252742 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1891 22:14:27.259633 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1892 22:14:27.262664 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1893 22:14:27.266195 Total UI for P1: 0, mck2ui 16
1894 22:14:27.268999 best dqsien dly found for B0: ( 0, 14, 2)
1895 22:14:27.272594 Total UI for P1: 0, mck2ui 16
1896 22:14:27.275904 best dqsien dly found for B1: ( 0, 14, 4)
1897 22:14:27.279278 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1898 22:14:27.282833 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1899 22:14:27.282916
1900 22:14:27.285883 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1901 22:14:27.289468 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1902 22:14:27.292498 [Gating] SW calibration Done
1903 22:14:27.292581 ==
1904 22:14:27.295863 Dram Type= 6, Freq= 0, CH_1, rank 1
1905 22:14:27.299141 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1906 22:14:27.299224 ==
1907 22:14:27.303256 RX Vref Scan: 0
1908 22:14:27.303338
1909 22:14:27.306168 RX Vref 0 -> 0, step: 1
1910 22:14:27.306249
1911 22:14:27.306313 RX Delay -130 -> 252, step: 16
1912 22:14:27.312850 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1913 22:14:27.315699 iDelay=206, Bit 1, Center 77 (-34 ~ 189) 224
1914 22:14:27.319248 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1915 22:14:27.322845 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1916 22:14:27.325891 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1917 22:14:27.332531 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1918 22:14:27.336382 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
1919 22:14:27.339199 iDelay=206, Bit 7, Center 77 (-34 ~ 189) 224
1920 22:14:27.342706 iDelay=206, Bit 8, Center 61 (-66 ~ 189) 256
1921 22:14:27.345845 iDelay=206, Bit 9, Center 61 (-66 ~ 189) 256
1922 22:14:27.352461 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1923 22:14:27.356365 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1924 22:14:27.359161 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1925 22:14:27.362392 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1926 22:14:27.365888 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1927 22:14:27.372539 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1928 22:14:27.372622 ==
1929 22:14:27.375988 Dram Type= 6, Freq= 0, CH_1, rank 1
1930 22:14:27.379564 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1931 22:14:27.379647 ==
1932 22:14:27.379713 DQS Delay:
1933 22:14:27.382420 DQS0 = 0, DQS1 = 0
1934 22:14:27.382501 DQM Delay:
1935 22:14:27.385856 DQM0 = 82, DQM1 = 78
1936 22:14:27.385939 DQ Delay:
1937 22:14:27.389423 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =85
1938 22:14:27.392983 DQ4 =85, DQ5 =93, DQ6 =85, DQ7 =77
1939 22:14:27.395859 DQ8 =61, DQ9 =61, DQ10 =85, DQ11 =77
1940 22:14:27.399395 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1941 22:14:27.399477
1942 22:14:27.399542
1943 22:14:27.399601 ==
1944 22:14:27.402755 Dram Type= 6, Freq= 0, CH_1, rank 1
1945 22:14:27.405825 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1946 22:14:27.405909 ==
1947 22:14:27.409385
1948 22:14:27.409467
1949 22:14:27.409532 TX Vref Scan disable
1950 22:14:27.412785 == TX Byte 0 ==
1951 22:14:27.416063 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1952 22:14:27.419079 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1953 22:14:27.422649 == TX Byte 1 ==
1954 22:14:27.425715 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1955 22:14:27.429149 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1956 22:14:27.429232 ==
1957 22:14:27.432499 Dram Type= 6, Freq= 0, CH_1, rank 1
1958 22:14:27.438762 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1959 22:14:27.438847 ==
1960 22:14:27.451713 TX Vref=22, minBit 1, minWin=27, winSum=440
1961 22:14:27.455035 TX Vref=24, minBit 1, minWin=27, winSum=446
1962 22:14:27.457782 TX Vref=26, minBit 8, minWin=27, winSum=446
1963 22:14:27.461109 TX Vref=28, minBit 1, minWin=27, winSum=448
1964 22:14:27.464400 TX Vref=30, minBit 0, minWin=28, winSum=455
1965 22:14:27.467760 TX Vref=32, minBit 0, minWin=28, winSum=458
1966 22:14:27.474496 [TxChooseVref] Worse bit 0, Min win 28, Win sum 458, Final Vref 32
1967 22:14:27.474578
1968 22:14:27.478136 Final TX Range 1 Vref 32
1969 22:14:27.478218
1970 22:14:27.478283 ==
1971 22:14:27.481175 Dram Type= 6, Freq= 0, CH_1, rank 1
1972 22:14:27.484799 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1973 22:14:27.484881 ==
1974 22:14:27.484946
1975 22:14:27.485006
1976 22:14:27.488151 TX Vref Scan disable
1977 22:14:27.491577 == TX Byte 0 ==
1978 22:14:27.494654 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1979 22:14:27.498108 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1980 22:14:27.501602 == TX Byte 1 ==
1981 22:14:27.504590 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1982 22:14:27.508137 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1983 22:14:27.511098
1984 22:14:27.511180 [DATLAT]
1985 22:14:27.511246 Freq=800, CH1 RK1
1986 22:14:27.511359
1987 22:14:27.514628 DATLAT Default: 0xa
1988 22:14:27.514710 0, 0xFFFF, sum = 0
1989 22:14:27.517924 1, 0xFFFF, sum = 0
1990 22:14:27.518007 2, 0xFFFF, sum = 0
1991 22:14:27.521322 3, 0xFFFF, sum = 0
1992 22:14:27.521406 4, 0xFFFF, sum = 0
1993 22:14:27.524808 5, 0xFFFF, sum = 0
1994 22:14:27.524891 6, 0xFFFF, sum = 0
1995 22:14:27.527810 7, 0xFFFF, sum = 0
1996 22:14:27.531334 8, 0xFFFF, sum = 0
1997 22:14:27.531456 9, 0x0, sum = 1
1998 22:14:27.531523 10, 0x0, sum = 2
1999 22:14:27.534738 11, 0x0, sum = 3
2000 22:14:27.534821 12, 0x0, sum = 4
2001 22:14:27.538162 best_step = 10
2002 22:14:27.538244
2003 22:14:27.538309 ==
2004 22:14:27.541548 Dram Type= 6, Freq= 0, CH_1, rank 1
2005 22:14:27.544541 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2006 22:14:27.544624 ==
2007 22:14:27.547754 RX Vref Scan: 0
2008 22:14:27.547836
2009 22:14:27.547901 RX Vref 0 -> 0, step: 1
2010 22:14:27.547960
2011 22:14:27.551204 RX Delay -111 -> 252, step: 8
2012 22:14:27.558250 iDelay=209, Bit 0, Center 84 (-31 ~ 200) 232
2013 22:14:27.561906 iDelay=209, Bit 1, Center 76 (-39 ~ 192) 232
2014 22:14:27.565048 iDelay=209, Bit 2, Center 68 (-47 ~ 184) 232
2015 22:14:27.568171 iDelay=209, Bit 3, Center 76 (-39 ~ 192) 232
2016 22:14:27.572032 iDelay=209, Bit 4, Center 80 (-39 ~ 200) 240
2017 22:14:27.578138 iDelay=209, Bit 5, Center 92 (-15 ~ 200) 216
2018 22:14:27.581654 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
2019 22:14:27.585041 iDelay=209, Bit 7, Center 76 (-39 ~ 192) 232
2020 22:14:27.588222 iDelay=209, Bit 8, Center 64 (-55 ~ 184) 240
2021 22:14:27.591589 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
2022 22:14:27.598222 iDelay=209, Bit 10, Center 76 (-39 ~ 192) 232
2023 22:14:27.602194 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
2024 22:14:27.605107 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
2025 22:14:27.608631 iDelay=209, Bit 13, Center 84 (-31 ~ 200) 232
2026 22:14:27.611257 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
2027 22:14:27.618086 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
2028 22:14:27.618170 ==
2029 22:14:27.621392 Dram Type= 6, Freq= 0, CH_1, rank 1
2030 22:14:27.625075 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2031 22:14:27.625160 ==
2032 22:14:27.625228 DQS Delay:
2033 22:14:27.628201 DQS0 = 0, DQS1 = 0
2034 22:14:27.628285 DQM Delay:
2035 22:14:27.631385 DQM0 = 80, DQM1 = 75
2036 22:14:27.631468 DQ Delay:
2037 22:14:27.634743 DQ0 =84, DQ1 =76, DQ2 =68, DQ3 =76
2038 22:14:27.637746 DQ4 =80, DQ5 =92, DQ6 =92, DQ7 =76
2039 22:14:27.641123 DQ8 =64, DQ9 =64, DQ10 =76, DQ11 =68
2040 22:14:27.644543 DQ12 =80, DQ13 =84, DQ14 =80, DQ15 =84
2041 22:14:27.644627
2042 22:14:27.644693
2043 22:14:27.651356 [DQSOSCAuto] RK1, (LSB)MR18= 0x202c, (MSB)MR19= 0x606, tDQSOscB0 = 398 ps tDQSOscB1 = 401 ps
2044 22:14:27.654824 CH1 RK1: MR19=606, MR18=202C
2045 22:14:27.661192 CH1_RK1: MR19=0x606, MR18=0x202C, DQSOSC=398, MR23=63, INC=93, DEC=62
2046 22:14:27.664590 [RxdqsGatingPostProcess] freq 800
2047 22:14:27.671379 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2048 22:14:27.674665 Pre-setting of DQS Precalculation
2049 22:14:27.678077 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2050 22:14:27.684662 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2051 22:14:27.691388 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2052 22:14:27.691486
2053 22:14:27.691553
2054 22:14:27.694727 [Calibration Summary] 1600 Mbps
2055 22:14:27.698058 CH 0, Rank 0
2056 22:14:27.698141 SW Impedance : PASS
2057 22:14:27.701138 DUTY Scan : NO K
2058 22:14:27.704805 ZQ Calibration : PASS
2059 22:14:27.704888 Jitter Meter : NO K
2060 22:14:27.708291 CBT Training : PASS
2061 22:14:27.711165 Write leveling : PASS
2062 22:14:27.711247 RX DQS gating : PASS
2063 22:14:27.714574 RX DQ/DQS(RDDQC) : PASS
2064 22:14:27.718174 TX DQ/DQS : PASS
2065 22:14:27.718285 RX DATLAT : PASS
2066 22:14:27.721669 RX DQ/DQS(Engine): PASS
2067 22:14:27.721779 TX OE : NO K
2068 22:14:27.724721 All Pass.
2069 22:14:27.724803
2070 22:14:27.724868 CH 0, Rank 1
2071 22:14:27.728459 SW Impedance : PASS
2072 22:14:27.728570 DUTY Scan : NO K
2073 22:14:27.731524 ZQ Calibration : PASS
2074 22:14:27.734994 Jitter Meter : NO K
2075 22:14:27.735103 CBT Training : PASS
2076 22:14:27.738029 Write leveling : PASS
2077 22:14:27.741496 RX DQS gating : PASS
2078 22:14:27.741579 RX DQ/DQS(RDDQC) : PASS
2079 22:14:27.744925 TX DQ/DQS : PASS
2080 22:14:27.748474 RX DATLAT : PASS
2081 22:14:27.748557 RX DQ/DQS(Engine): PASS
2082 22:14:27.751129 TX OE : NO K
2083 22:14:27.751212 All Pass.
2084 22:14:27.751277
2085 22:14:27.754589 CH 1, Rank 0
2086 22:14:27.754671 SW Impedance : PASS
2087 22:14:27.758038 DUTY Scan : NO K
2088 22:14:27.761516 ZQ Calibration : PASS
2089 22:14:27.761598 Jitter Meter : NO K
2090 22:14:27.764915 CBT Training : PASS
2091 22:14:27.764998 Write leveling : PASS
2092 22:14:27.768396 RX DQS gating : PASS
2093 22:14:27.771326 RX DQ/DQS(RDDQC) : PASS
2094 22:14:27.771447 TX DQ/DQS : PASS
2095 22:14:27.774706 RX DATLAT : PASS
2096 22:14:27.778307 RX DQ/DQS(Engine): PASS
2097 22:14:27.778390 TX OE : NO K
2098 22:14:27.781194 All Pass.
2099 22:14:27.781276
2100 22:14:27.781341 CH 1, Rank 1
2101 22:14:27.785011 SW Impedance : PASS
2102 22:14:27.785101 DUTY Scan : NO K
2103 22:14:27.787917 ZQ Calibration : PASS
2104 22:14:27.791413 Jitter Meter : NO K
2105 22:14:27.791520 CBT Training : PASS
2106 22:14:27.794691 Write leveling : PASS
2107 22:14:27.798078 RX DQS gating : PASS
2108 22:14:27.798183 RX DQ/DQS(RDDQC) : PASS
2109 22:14:27.801349 TX DQ/DQS : PASS
2110 22:14:27.801432 RX DATLAT : PASS
2111 22:14:27.804750 RX DQ/DQS(Engine): PASS
2112 22:14:27.808497 TX OE : NO K
2113 22:14:27.808581 All Pass.
2114 22:14:27.808647
2115 22:14:27.811385 DramC Write-DBI off
2116 22:14:27.811481 PER_BANK_REFRESH: Hybrid Mode
2117 22:14:27.814914 TX_TRACKING: ON
2118 22:14:27.817901 [GetDramInforAfterCalByMRR] Vendor 6.
2119 22:14:27.821387 [GetDramInforAfterCalByMRR] Revision 606.
2120 22:14:27.824414 [GetDramInforAfterCalByMRR] Revision 2 0.
2121 22:14:27.827955 MR0 0x3b3b
2122 22:14:27.828038 MR8 0x5151
2123 22:14:27.831683 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2124 22:14:27.831768
2125 22:14:27.831834 MR0 0x3b3b
2126 22:14:27.835057 MR8 0x5151
2127 22:14:27.838142 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2128 22:14:27.838226
2129 22:14:27.844579 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2130 22:14:27.848106 [FAST_K] Save calibration result to emmc
2131 22:14:27.854661 [FAST_K] Save calibration result to emmc
2132 22:14:27.854745 dram_init: config_dvfs: 1
2133 22:14:27.857766 dramc_set_vcore_voltage set vcore to 662500
2134 22:14:27.861191 Read voltage for 1200, 2
2135 22:14:27.861275 Vio18 = 0
2136 22:14:27.864977 Vcore = 662500
2137 22:14:27.865060 Vdram = 0
2138 22:14:27.865127 Vddq = 0
2139 22:14:27.868181 Vmddr = 0
2140 22:14:27.871182 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2141 22:14:27.877955 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2142 22:14:27.878039 MEM_TYPE=3, freq_sel=15
2143 22:14:27.881147 sv_algorithm_assistance_LP4_1600
2144 22:14:27.887929 ============ PULL DRAM RESETB DOWN ============
2145 22:14:27.891519 ========== PULL DRAM RESETB DOWN end =========
2146 22:14:27.895126 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2147 22:14:27.897927 ===================================
2148 22:14:27.901185 LPDDR4 DRAM CONFIGURATION
2149 22:14:27.904555 ===================================
2150 22:14:27.904637 EX_ROW_EN[0] = 0x0
2151 22:14:27.907663 EX_ROW_EN[1] = 0x0
2152 22:14:27.911448 LP4Y_EN = 0x0
2153 22:14:27.911558 WORK_FSP = 0x0
2154 22:14:27.914468 WL = 0x4
2155 22:14:27.914545 RL = 0x4
2156 22:14:27.917950 BL = 0x2
2157 22:14:27.918029 RPST = 0x0
2158 22:14:27.920906 RD_PRE = 0x0
2159 22:14:27.921007 WR_PRE = 0x1
2160 22:14:27.924510 WR_PST = 0x0
2161 22:14:27.924589 DBI_WR = 0x0
2162 22:14:27.927846 DBI_RD = 0x0
2163 22:14:27.927925 OTF = 0x1
2164 22:14:27.931061 ===================================
2165 22:14:27.934585 ===================================
2166 22:14:27.938109 ANA top config
2167 22:14:27.940963 ===================================
2168 22:14:27.941047 DLL_ASYNC_EN = 0
2169 22:14:27.944557 ALL_SLAVE_EN = 0
2170 22:14:27.948140 NEW_RANK_MODE = 1
2171 22:14:27.951152 DLL_IDLE_MODE = 1
2172 22:14:27.954595 LP45_APHY_COMB_EN = 1
2173 22:14:27.954677 TX_ODT_DIS = 1
2174 22:14:27.957990 NEW_8X_MODE = 1
2175 22:14:27.961121 ===================================
2176 22:14:27.964573 ===================================
2177 22:14:27.967544 data_rate = 2400
2178 22:14:27.971036 CKR = 1
2179 22:14:27.974522 DQ_P2S_RATIO = 8
2180 22:14:27.977446 ===================================
2181 22:14:27.977527 CA_P2S_RATIO = 8
2182 22:14:27.980837 DQ_CA_OPEN = 0
2183 22:14:27.984501 DQ_SEMI_OPEN = 0
2184 22:14:27.987421 CA_SEMI_OPEN = 0
2185 22:14:27.990830 CA_FULL_RATE = 0
2186 22:14:27.994512 DQ_CKDIV4_EN = 0
2187 22:14:27.994594 CA_CKDIV4_EN = 0
2188 22:14:27.997786 CA_PREDIV_EN = 0
2189 22:14:28.000892 PH8_DLY = 17
2190 22:14:28.004265 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2191 22:14:28.007681 DQ_AAMCK_DIV = 4
2192 22:14:28.010932 CA_AAMCK_DIV = 4
2193 22:14:28.011011 CA_ADMCK_DIV = 4
2194 22:14:28.014187 DQ_TRACK_CA_EN = 0
2195 22:14:28.017857 CA_PICK = 1200
2196 22:14:28.020838 CA_MCKIO = 1200
2197 22:14:28.024403 MCKIO_SEMI = 0
2198 22:14:28.027236 PLL_FREQ = 2366
2199 22:14:28.030750 DQ_UI_PI_RATIO = 32
2200 22:14:28.030832 CA_UI_PI_RATIO = 0
2201 22:14:28.034279 ===================================
2202 22:14:28.037823 ===================================
2203 22:14:28.041127 memory_type:LPDDR4
2204 22:14:28.044140 GP_NUM : 10
2205 22:14:28.044222 SRAM_EN : 1
2206 22:14:28.047842 MD32_EN : 0
2207 22:14:28.050847 ===================================
2208 22:14:28.054501 [ANA_INIT] >>>>>>>>>>>>>>
2209 22:14:28.057848 <<<<<< [CONFIGURE PHASE]: ANA_TX
2210 22:14:28.060855 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2211 22:14:28.064940 ===================================
2212 22:14:28.065023 data_rate = 2400,PCW = 0X5b00
2213 22:14:28.067762 ===================================
2214 22:14:28.070717 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2215 22:14:28.077569 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2216 22:14:28.084888 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2217 22:14:28.087379 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2218 22:14:28.091068 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2219 22:14:28.094045 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2220 22:14:28.097578 [ANA_INIT] flow start
2221 22:14:28.097660 [ANA_INIT] PLL >>>>>>>>
2222 22:14:28.101069 [ANA_INIT] PLL <<<<<<<<
2223 22:14:28.104048 [ANA_INIT] MIDPI >>>>>>>>
2224 22:14:28.107944 [ANA_INIT] MIDPI <<<<<<<<
2225 22:14:28.108026 [ANA_INIT] DLL >>>>>>>>
2226 22:14:28.110865 [ANA_INIT] DLL <<<<<<<<
2227 22:14:28.114243 [ANA_INIT] flow end
2228 22:14:28.117624 ============ LP4 DIFF to SE enter ============
2229 22:14:28.120857 ============ LP4 DIFF to SE exit ============
2230 22:14:28.124100 [ANA_INIT] <<<<<<<<<<<<<
2231 22:14:28.127360 [Flow] Enable top DCM control >>>>>
2232 22:14:28.130855 [Flow] Enable top DCM control <<<<<
2233 22:14:28.134168 Enable DLL master slave shuffle
2234 22:14:28.137488 ==============================================================
2235 22:14:28.141049 Gating Mode config
2236 22:14:28.144559 ==============================================================
2237 22:14:28.147776 Config description:
2238 22:14:28.157695 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2239 22:14:28.164394 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2240 22:14:28.167346 SELPH_MODE 0: By rank 1: By Phase
2241 22:14:28.174425 ==============================================================
2242 22:14:28.177408 GAT_TRACK_EN = 1
2243 22:14:28.180860 RX_GATING_MODE = 2
2244 22:14:28.184292 RX_GATING_TRACK_MODE = 2
2245 22:14:28.187676 SELPH_MODE = 1
2246 22:14:28.190507 PICG_EARLY_EN = 1
2247 22:14:28.190635 VALID_LAT_VALUE = 1
2248 22:14:28.197566 ==============================================================
2249 22:14:28.200530 Enter into Gating configuration >>>>
2250 22:14:28.203930 Exit from Gating configuration <<<<
2251 22:14:28.207460 Enter into DVFS_PRE_config >>>>>
2252 22:14:28.217234 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2253 22:14:28.220684 Exit from DVFS_PRE_config <<<<<
2254 22:14:28.223921 Enter into PICG configuration >>>>
2255 22:14:28.227189 Exit from PICG configuration <<<<
2256 22:14:28.230592 [RX_INPUT] configuration >>>>>
2257 22:14:28.234335 [RX_INPUT] configuration <<<<<
2258 22:14:28.237627 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2259 22:14:28.244125 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2260 22:14:28.250773 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2261 22:14:28.257503 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2262 22:14:28.263932 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2263 22:14:28.267047 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2264 22:14:28.274078 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2265 22:14:28.277059 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2266 22:14:28.280408 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2267 22:14:28.283957 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2268 22:14:28.291060 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2269 22:14:28.293936 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2270 22:14:28.297440 ===================================
2271 22:14:28.301127 LPDDR4 DRAM CONFIGURATION
2272 22:14:28.303851 ===================================
2273 22:14:28.303926 EX_ROW_EN[0] = 0x0
2274 22:14:28.307300 EX_ROW_EN[1] = 0x0
2275 22:14:28.307405 LP4Y_EN = 0x0
2276 22:14:28.310903 WORK_FSP = 0x0
2277 22:14:28.311010 WL = 0x4
2278 22:14:28.313771 RL = 0x4
2279 22:14:28.313875 BL = 0x2
2280 22:14:28.317375 RPST = 0x0
2281 22:14:28.317461 RD_PRE = 0x0
2282 22:14:28.320494 WR_PRE = 0x1
2283 22:14:28.320578 WR_PST = 0x0
2284 22:14:28.323930 DBI_WR = 0x0
2285 22:14:28.324014 DBI_RD = 0x0
2286 22:14:28.327096 OTF = 0x1
2287 22:14:28.330586 ===================================
2288 22:14:28.334301 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2289 22:14:28.337083 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2290 22:14:28.343918 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2291 22:14:28.347040 ===================================
2292 22:14:28.347136 LPDDR4 DRAM CONFIGURATION
2293 22:14:28.351028 ===================================
2294 22:14:28.353720 EX_ROW_EN[0] = 0x10
2295 22:14:28.357334 EX_ROW_EN[1] = 0x0
2296 22:14:28.357414 LP4Y_EN = 0x0
2297 22:14:28.360466 WORK_FSP = 0x0
2298 22:14:28.360546 WL = 0x4
2299 22:14:28.363679 RL = 0x4
2300 22:14:28.363759 BL = 0x2
2301 22:14:28.367073 RPST = 0x0
2302 22:14:28.367153 RD_PRE = 0x0
2303 22:14:28.370651 WR_PRE = 0x1
2304 22:14:28.370730 WR_PST = 0x0
2305 22:14:28.374160 DBI_WR = 0x0
2306 22:14:28.374240 DBI_RD = 0x0
2307 22:14:28.377101 OTF = 0x1
2308 22:14:28.380734 ===================================
2309 22:14:28.387053 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2310 22:14:28.387142 ==
2311 22:14:28.390472 Dram Type= 6, Freq= 0, CH_0, rank 0
2312 22:14:28.393946 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2313 22:14:28.394028 ==
2314 22:14:28.397198 [Duty_Offset_Calibration]
2315 22:14:28.397278 B0:2 B1:-1 CA:1
2316 22:14:28.397341
2317 22:14:28.400622 [DutyScan_Calibration_Flow] k_type=0
2318 22:14:28.409866
2319 22:14:28.409946 ==CLK 0==
2320 22:14:28.413583 Final CLK duty delay cell = -4
2321 22:14:28.417073 [-4] MAX Duty = 5031%(X100), DQS PI = 4
2322 22:14:28.420095 [-4] MIN Duty = 4875%(X100), DQS PI = 32
2323 22:14:28.423652 [-4] AVG Duty = 4953%(X100)
2324 22:14:28.423733
2325 22:14:28.426506 CH0 CLK Duty spec in!! Max-Min= 156%
2326 22:14:28.430005 [DutyScan_Calibration_Flow] ====Done====
2327 22:14:28.430086
2328 22:14:28.433496 [DutyScan_Calibration_Flow] k_type=1
2329 22:14:28.448128
2330 22:14:28.448213 ==DQS 0 ==
2331 22:14:28.451335 Final DQS duty delay cell = -4
2332 22:14:28.454913 [-4] MAX Duty = 5000%(X100), DQS PI = 54
2333 22:14:28.458124 [-4] MIN Duty = 4876%(X100), DQS PI = 12
2334 22:14:28.461543 [-4] AVG Duty = 4938%(X100)
2335 22:14:28.461623
2336 22:14:28.461688 ==DQS 1 ==
2337 22:14:28.465031 Final DQS duty delay cell = -4
2338 22:14:28.468119 [-4] MAX Duty = 5124%(X100), DQS PI = 6
2339 22:14:28.471532 [-4] MIN Duty = 5000%(X100), DQS PI = 44
2340 22:14:28.474722 [-4] AVG Duty = 5062%(X100)
2341 22:14:28.474801
2342 22:14:28.478444 CH0 DQS 0 Duty spec in!! Max-Min= 124%
2343 22:14:28.478524
2344 22:14:28.481378 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2345 22:14:28.484786 [DutyScan_Calibration_Flow] ====Done====
2346 22:14:28.484867
2347 22:14:28.487831 [DutyScan_Calibration_Flow] k_type=3
2348 22:14:28.505152
2349 22:14:28.505237 ==DQM 0 ==
2350 22:14:28.508694 Final DQM duty delay cell = 0
2351 22:14:28.512242 [0] MAX Duty = 5031%(X100), DQS PI = 54
2352 22:14:28.515575 [0] MIN Duty = 4907%(X100), DQS PI = 2
2353 22:14:28.515686 [0] AVG Duty = 4969%(X100)
2354 22:14:28.518557
2355 22:14:28.518642 ==DQM 1 ==
2356 22:14:28.521671 Final DQM duty delay cell = 0
2357 22:14:28.525381 [0] MAX Duty = 5156%(X100), DQS PI = 62
2358 22:14:28.528762 [0] MIN Duty = 4969%(X100), DQS PI = 10
2359 22:14:28.528848 [0] AVG Duty = 5062%(X100)
2360 22:14:28.531863
2361 22:14:28.535484 CH0 DQM 0 Duty spec in!! Max-Min= 124%
2362 22:14:28.535569
2363 22:14:28.538539 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2364 22:14:28.541848 [DutyScan_Calibration_Flow] ====Done====
2365 22:14:28.541933
2366 22:14:28.545024 [DutyScan_Calibration_Flow] k_type=2
2367 22:14:28.560876
2368 22:14:28.560960 ==DQ 0 ==
2369 22:14:28.564229 Final DQ duty delay cell = -4
2370 22:14:28.567616 [-4] MAX Duty = 5031%(X100), DQS PI = 0
2371 22:14:28.571001 [-4] MIN Duty = 4907%(X100), DQS PI = 10
2372 22:14:28.574428 [-4] AVG Duty = 4969%(X100)
2373 22:14:28.574512
2374 22:14:28.574614 ==DQ 1 ==
2375 22:14:28.577871 Final DQ duty delay cell = 0
2376 22:14:28.580925 [0] MAX Duty = 5031%(X100), DQS PI = 18
2377 22:14:28.584608 [0] MIN Duty = 4907%(X100), DQS PI = 46
2378 22:14:28.587335 [0] AVG Duty = 4969%(X100)
2379 22:14:28.587445
2380 22:14:28.590828 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2381 22:14:28.590912
2382 22:14:28.594433 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2383 22:14:28.597582 [DutyScan_Calibration_Flow] ====Done====
2384 22:14:28.597666 ==
2385 22:14:28.600787 Dram Type= 6, Freq= 0, CH_1, rank 0
2386 22:14:28.604269 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2387 22:14:28.604355 ==
2388 22:14:28.607846 [Duty_Offset_Calibration]
2389 22:14:28.607930 B0:1 B1:1 CA:2
2390 22:14:28.608014
2391 22:14:28.610754 [DutyScan_Calibration_Flow] k_type=0
2392 22:14:28.621218
2393 22:14:28.621301 ==CLK 0==
2394 22:14:28.624725 Final CLK duty delay cell = 0
2395 22:14:28.627813 [0] MAX Duty = 5156%(X100), DQS PI = 24
2396 22:14:28.631304 [0] MIN Duty = 4969%(X100), DQS PI = 40
2397 22:14:28.631427 [0] AVG Duty = 5062%(X100)
2398 22:14:28.634531
2399 22:14:28.637812 CH1 CLK Duty spec in!! Max-Min= 187%
2400 22:14:28.640911 [DutyScan_Calibration_Flow] ====Done====
2401 22:14:28.640995
2402 22:14:28.644274 [DutyScan_Calibration_Flow] k_type=1
2403 22:14:28.660466
2404 22:14:28.660549 ==DQS 0 ==
2405 22:14:28.663607 Final DQS duty delay cell = 0
2406 22:14:28.667462 [0] MAX Duty = 5062%(X100), DQS PI = 18
2407 22:14:28.670217 [0] MIN Duty = 4844%(X100), DQS PI = 50
2408 22:14:28.673858 [0] AVG Duty = 4953%(X100)
2409 22:14:28.673942
2410 22:14:28.674026 ==DQS 1 ==
2411 22:14:28.677218 Final DQS duty delay cell = 0
2412 22:14:28.680865 [0] MAX Duty = 5062%(X100), DQS PI = 36
2413 22:14:28.683815 [0] MIN Duty = 4907%(X100), DQS PI = 16
2414 22:14:28.687543 [0] AVG Duty = 4984%(X100)
2415 22:14:28.687651
2416 22:14:28.690311 CH1 DQS 0 Duty spec in!! Max-Min= 218%
2417 22:14:28.690395
2418 22:14:28.693717 CH1 DQS 1 Duty spec in!! Max-Min= 155%
2419 22:14:28.697333 [DutyScan_Calibration_Flow] ====Done====
2420 22:14:28.697417
2421 22:14:28.700799 [DutyScan_Calibration_Flow] k_type=3
2422 22:14:28.717166
2423 22:14:28.717251 ==DQM 0 ==
2424 22:14:28.720734 Final DQM duty delay cell = 0
2425 22:14:28.723665 [0] MAX Duty = 5093%(X100), DQS PI = 18
2426 22:14:28.727181 [0] MIN Duty = 4907%(X100), DQS PI = 48
2427 22:14:28.727266 [0] AVG Duty = 5000%(X100)
2428 22:14:28.731138
2429 22:14:28.731222 ==DQM 1 ==
2430 22:14:28.733827 Final DQM duty delay cell = 0
2431 22:14:28.737397 [0] MAX Duty = 5156%(X100), DQS PI = 0
2432 22:14:28.740663 [0] MIN Duty = 4938%(X100), DQS PI = 22
2433 22:14:28.740755 [0] AVG Duty = 5047%(X100)
2434 22:14:28.744309
2435 22:14:28.747464 CH1 DQM 0 Duty spec in!! Max-Min= 186%
2436 22:14:28.747549
2437 22:14:28.750471 CH1 DQM 1 Duty spec in!! Max-Min= 218%
2438 22:14:28.753868 [DutyScan_Calibration_Flow] ====Done====
2439 22:14:28.753952
2440 22:14:28.757128 [DutyScan_Calibration_Flow] k_type=2
2441 22:14:28.773911
2442 22:14:28.773995 ==DQ 0 ==
2443 22:14:28.777294 Final DQ duty delay cell = 0
2444 22:14:28.780783 [0] MAX Duty = 5156%(X100), DQS PI = 18
2445 22:14:28.783779 [0] MIN Duty = 4938%(X100), DQS PI = 50
2446 22:14:28.783864 [0] AVG Duty = 5047%(X100)
2447 22:14:28.783949
2448 22:14:28.787012 ==DQ 1 ==
2449 22:14:28.790841 Final DQ duty delay cell = 0
2450 22:14:28.794204 [0] MAX Duty = 5093%(X100), DQS PI = 8
2451 22:14:28.797459 [0] MIN Duty = 5031%(X100), DQS PI = 4
2452 22:14:28.797541 [0] AVG Duty = 5062%(X100)
2453 22:14:28.797606
2454 22:14:28.800576 CH1 DQ 0 Duty spec in!! Max-Min= 218%
2455 22:14:28.800658
2456 22:14:28.804042 CH1 DQ 1 Duty spec in!! Max-Min= 62%
2457 22:14:28.807381 [DutyScan_Calibration_Flow] ====Done====
2458 22:14:28.812723 nWR fixed to 30
2459 22:14:28.815679 [ModeRegInit_LP4] CH0 RK0
2460 22:14:28.815760 [ModeRegInit_LP4] CH0 RK1
2461 22:14:28.819278 [ModeRegInit_LP4] CH1 RK0
2462 22:14:28.822724 [ModeRegInit_LP4] CH1 RK1
2463 22:14:28.822806 match AC timing 7
2464 22:14:28.829300 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2465 22:14:28.832791 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2466 22:14:28.835694 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2467 22:14:28.842938 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2468 22:14:28.846098 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2469 22:14:28.846180 ==
2470 22:14:28.849363 Dram Type= 6, Freq= 0, CH_0, rank 0
2471 22:14:28.852607 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2472 22:14:28.852690 ==
2473 22:14:28.859385 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2474 22:14:28.865948 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2475 22:14:28.873726 [CA 0] Center 40 (10~71) winsize 62
2476 22:14:28.876872 [CA 1] Center 39 (9~70) winsize 62
2477 22:14:28.880088 [CA 2] Center 36 (6~67) winsize 62
2478 22:14:28.883408 [CA 3] Center 36 (6~66) winsize 61
2479 22:14:28.886955 [CA 4] Center 34 (4~65) winsize 62
2480 22:14:28.890368 [CA 5] Center 34 (4~64) winsize 61
2481 22:14:28.890451
2482 22:14:28.893896 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2483 22:14:28.893979
2484 22:14:28.896719 [CATrainingPosCal] consider 1 rank data
2485 22:14:28.900161 u2DelayCellTimex100 = 270/100 ps
2486 22:14:28.903401 CA0 delay=40 (10~71),Diff = 6 PI (28 cell)
2487 22:14:28.910360 CA1 delay=39 (9~70),Diff = 5 PI (24 cell)
2488 22:14:28.913746 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2489 22:14:28.916605 CA3 delay=36 (6~66),Diff = 2 PI (9 cell)
2490 22:14:28.920495 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
2491 22:14:28.923682 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2492 22:14:28.923764
2493 22:14:28.926946 CA PerBit enable=1, Macro0, CA PI delay=34
2494 22:14:28.927029
2495 22:14:28.930395 [CBTSetCACLKResult] CA Dly = 34
2496 22:14:28.930478 CS Dly: 7 (0~38)
2497 22:14:28.933366 ==
2498 22:14:28.933450 Dram Type= 6, Freq= 0, CH_0, rank 1
2499 22:14:28.940521 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2500 22:14:28.940605 ==
2501 22:14:28.944018 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2502 22:14:28.950452 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2503 22:14:28.959678 [CA 0] Center 39 (9~70) winsize 62
2504 22:14:28.962535 [CA 1] Center 39 (9~70) winsize 62
2505 22:14:28.965853 [CA 2] Center 36 (6~67) winsize 62
2506 22:14:28.969595 [CA 3] Center 36 (5~67) winsize 63
2507 22:14:28.973067 [CA 4] Center 34 (4~65) winsize 62
2508 22:14:28.975997 [CA 5] Center 34 (4~64) winsize 61
2509 22:14:28.976080
2510 22:14:28.979734 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2511 22:14:28.979827
2512 22:14:28.982890 [CATrainingPosCal] consider 2 rank data
2513 22:14:28.986139 u2DelayCellTimex100 = 270/100 ps
2514 22:14:28.989483 CA0 delay=40 (10~70),Diff = 6 PI (28 cell)
2515 22:14:28.992703 CA1 delay=39 (9~70),Diff = 5 PI (24 cell)
2516 22:14:28.999774 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2517 22:14:29.002693 CA3 delay=36 (6~66),Diff = 2 PI (9 cell)
2518 22:14:29.005877 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
2519 22:14:29.009205 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2520 22:14:29.009288
2521 22:14:29.013455 CA PerBit enable=1, Macro0, CA PI delay=34
2522 22:14:29.013535
2523 22:14:29.016036 [CBTSetCACLKResult] CA Dly = 34
2524 22:14:29.016114 CS Dly: 8 (0~41)
2525 22:14:29.016180
2526 22:14:29.019839 ----->DramcWriteLeveling(PI) begin...
2527 22:14:29.022766 ==
2528 22:14:29.022856 Dram Type= 6, Freq= 0, CH_0, rank 0
2529 22:14:29.029252 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2530 22:14:29.029336 ==
2531 22:14:29.033027 Write leveling (Byte 0): 30 => 30
2532 22:14:29.036493 Write leveling (Byte 1): 29 => 29
2533 22:14:29.039278 DramcWriteLeveling(PI) end<-----
2534 22:14:29.039419
2535 22:14:29.039488 ==
2536 22:14:29.042842 Dram Type= 6, Freq= 0, CH_0, rank 0
2537 22:14:29.046269 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2538 22:14:29.046353 ==
2539 22:14:29.049418 [Gating] SW mode calibration
2540 22:14:29.055874 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2541 22:14:29.059436 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2542 22:14:29.065944 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2543 22:14:29.069546 0 15 4 | B1->B0 | 2323 3232 | 0 1 | (0 0) (1 1)
2544 22:14:29.073010 0 15 8 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
2545 22:14:29.079297 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2546 22:14:29.082762 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2547 22:14:29.086111 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2548 22:14:29.092853 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2549 22:14:29.095954 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2550 22:14:29.099290 1 0 0 | B1->B0 | 3434 3232 | 1 1 | (1 0) (1 0)
2551 22:14:29.106377 1 0 4 | B1->B0 | 2b2b 2323 | 0 0 | (1 0) (0 0)
2552 22:14:29.109483 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2553 22:14:29.112727 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2554 22:14:29.119654 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2555 22:14:29.123116 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2556 22:14:29.126609 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2557 22:14:29.132750 1 0 28 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
2558 22:14:29.136474 1 1 0 | B1->B0 | 2323 2c2c | 0 1 | (0 0) (0 0)
2559 22:14:29.139618 1 1 4 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
2560 22:14:29.143100 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2561 22:14:29.149804 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2562 22:14:29.152702 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2563 22:14:29.156410 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2564 22:14:29.162822 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2565 22:14:29.166371 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2566 22:14:29.169630 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2567 22:14:29.176132 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2568 22:14:29.179672 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2569 22:14:29.182973 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2570 22:14:29.189948 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2571 22:14:29.192742 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2572 22:14:29.196599 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2573 22:14:29.202755 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2574 22:14:29.206468 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2575 22:14:29.209860 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2576 22:14:29.216041 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2577 22:14:29.219276 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2578 22:14:29.222634 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2579 22:14:29.229633 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2580 22:14:29.233041 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2581 22:14:29.236561 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2582 22:14:29.239534 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2583 22:14:29.245848 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2584 22:14:29.249406 Total UI for P1: 0, mck2ui 16
2585 22:14:29.253131 best dqsien dly found for B0: ( 1, 3, 30)
2586 22:14:29.256085 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2587 22:14:29.259496 Total UI for P1: 0, mck2ui 16
2588 22:14:29.262425 best dqsien dly found for B1: ( 1, 4, 2)
2589 22:14:29.266052 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2590 22:14:29.269879 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2591 22:14:29.269987
2592 22:14:29.272866 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2593 22:14:29.276059 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2594 22:14:29.279529 [Gating] SW calibration Done
2595 22:14:29.279675 ==
2596 22:14:29.282766 Dram Type= 6, Freq= 0, CH_0, rank 0
2597 22:14:29.286234 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2598 22:14:29.289649 ==
2599 22:14:29.289785 RX Vref Scan: 0
2600 22:14:29.289854
2601 22:14:29.292758 RX Vref 0 -> 0, step: 1
2602 22:14:29.292911
2603 22:14:29.296309 RX Delay -40 -> 252, step: 8
2604 22:14:29.299621 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2605 22:14:29.302402 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2606 22:14:29.305705 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2607 22:14:29.309386 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2608 22:14:29.316398 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2609 22:14:29.319501 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2610 22:14:29.322751 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2611 22:14:29.326129 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2612 22:14:29.329387 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2613 22:14:29.332793 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2614 22:14:29.339240 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2615 22:14:29.342947 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2616 22:14:29.345834 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2617 22:14:29.349504 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2618 22:14:29.356180 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2619 22:14:29.359085 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2620 22:14:29.359169 ==
2621 22:14:29.362738 Dram Type= 6, Freq= 0, CH_0, rank 0
2622 22:14:29.366474 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2623 22:14:29.366559 ==
2624 22:14:29.366626 DQS Delay:
2625 22:14:29.369355 DQS0 = 0, DQS1 = 0
2626 22:14:29.369435 DQM Delay:
2627 22:14:29.372910 DQM0 = 116, DQM1 = 107
2628 22:14:29.372986 DQ Delay:
2629 22:14:29.375958 DQ0 =115, DQ1 =115, DQ2 =115, DQ3 =115
2630 22:14:29.379076 DQ4 =115, DQ5 =111, DQ6 =123, DQ7 =123
2631 22:14:29.382594 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2632 22:14:29.385917 DQ12 =115, DQ13 =115, DQ14 =119, DQ15 =111
2633 22:14:29.389315
2634 22:14:29.389395
2635 22:14:29.389461 ==
2636 22:14:29.392925 Dram Type= 6, Freq= 0, CH_0, rank 0
2637 22:14:29.395779 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2638 22:14:29.395860 ==
2639 22:14:29.395924
2640 22:14:29.395983
2641 22:14:29.399481 TX Vref Scan disable
2642 22:14:29.399552 == TX Byte 0 ==
2643 22:14:29.405947 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2644 22:14:29.409156 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2645 22:14:29.409241 == TX Byte 1 ==
2646 22:14:29.416377 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2647 22:14:29.419791 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2648 22:14:29.419876 ==
2649 22:14:29.422629 Dram Type= 6, Freq= 0, CH_0, rank 0
2650 22:14:29.426331 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2651 22:14:29.426416 ==
2652 22:14:29.438216 TX Vref=22, minBit 7, minWin=24, winSum=415
2653 22:14:29.441547 TX Vref=24, minBit 1, minWin=25, winSum=420
2654 22:14:29.444617 TX Vref=26, minBit 5, minWin=25, winSum=426
2655 22:14:29.448192 TX Vref=28, minBit 0, minWin=26, winSum=428
2656 22:14:29.451740 TX Vref=30, minBit 1, minWin=26, winSum=436
2657 22:14:29.454767 TX Vref=32, minBit 0, minWin=26, winSum=431
2658 22:14:29.461223 [TxChooseVref] Worse bit 1, Min win 26, Win sum 436, Final Vref 30
2659 22:14:29.461308
2660 22:14:29.465429 Final TX Range 1 Vref 30
2661 22:14:29.465513
2662 22:14:29.465579 ==
2663 22:14:29.468406 Dram Type= 6, Freq= 0, CH_0, rank 0
2664 22:14:29.471307 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2665 22:14:29.471398 ==
2666 22:14:29.471465
2667 22:14:29.474787
2668 22:14:29.474870 TX Vref Scan disable
2669 22:14:29.478251 == TX Byte 0 ==
2670 22:14:29.481804 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2671 22:14:29.485255 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2672 22:14:29.488134 == TX Byte 1 ==
2673 22:14:29.491592 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2674 22:14:29.494965 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2675 22:14:29.495050
2676 22:14:29.498013 [DATLAT]
2677 22:14:29.498097 Freq=1200, CH0 RK0
2678 22:14:29.498163
2679 22:14:29.501483 DATLAT Default: 0xd
2680 22:14:29.501566 0, 0xFFFF, sum = 0
2681 22:14:29.505004 1, 0xFFFF, sum = 0
2682 22:14:29.505089 2, 0xFFFF, sum = 0
2683 22:14:29.507849 3, 0xFFFF, sum = 0
2684 22:14:29.507934 4, 0xFFFF, sum = 0
2685 22:14:29.511397 5, 0xFFFF, sum = 0
2686 22:14:29.511483 6, 0xFFFF, sum = 0
2687 22:14:29.514880 7, 0xFFFF, sum = 0
2688 22:14:29.514966 8, 0xFFFF, sum = 0
2689 22:14:29.518225 9, 0xFFFF, sum = 0
2690 22:14:29.521637 10, 0xFFFF, sum = 0
2691 22:14:29.521723 11, 0xFFFF, sum = 0
2692 22:14:29.524738 12, 0x0, sum = 1
2693 22:14:29.524823 13, 0x0, sum = 2
2694 22:14:29.524890 14, 0x0, sum = 3
2695 22:14:29.528045 15, 0x0, sum = 4
2696 22:14:29.528130 best_step = 13
2697 22:14:29.528197
2698 22:14:29.531665 ==
2699 22:14:29.531749 Dram Type= 6, Freq= 0, CH_0, rank 0
2700 22:14:29.538152 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2701 22:14:29.538237 ==
2702 22:14:29.538304 RX Vref Scan: 1
2703 22:14:29.538366
2704 22:14:29.541330 Set Vref Range= 32 -> 127
2705 22:14:29.541438
2706 22:14:29.544640 RX Vref 32 -> 127, step: 1
2707 22:14:29.544723
2708 22:14:29.548001 RX Delay -21 -> 252, step: 4
2709 22:14:29.548083
2710 22:14:29.551306 Set Vref, RX VrefLevel [Byte0]: 32
2711 22:14:29.555166 [Byte1]: 32
2712 22:14:29.555249
2713 22:14:29.558345 Set Vref, RX VrefLevel [Byte0]: 33
2714 22:14:29.561511 [Byte1]: 33
2715 22:14:29.561621
2716 22:14:29.565141 Set Vref, RX VrefLevel [Byte0]: 34
2717 22:14:29.568099 [Byte1]: 34
2718 22:14:29.572122
2719 22:14:29.572230 Set Vref, RX VrefLevel [Byte0]: 35
2720 22:14:29.578640 [Byte1]: 35
2721 22:14:29.578722
2722 22:14:29.581965 Set Vref, RX VrefLevel [Byte0]: 36
2723 22:14:29.585514 [Byte1]: 36
2724 22:14:29.585621
2725 22:14:29.588874 Set Vref, RX VrefLevel [Byte0]: 37
2726 22:14:29.592009 [Byte1]: 37
2727 22:14:29.595976
2728 22:14:29.596060 Set Vref, RX VrefLevel [Byte0]: 38
2729 22:14:29.599418 [Byte1]: 38
2730 22:14:29.603687
2731 22:14:29.603791 Set Vref, RX VrefLevel [Byte0]: 39
2732 22:14:29.607087 [Byte1]: 39
2733 22:14:29.612493
2734 22:14:29.612663 Set Vref, RX VrefLevel [Byte0]: 40
2735 22:14:29.615685 [Byte1]: 40
2736 22:14:29.619909
2737 22:14:29.619991 Set Vref, RX VrefLevel [Byte0]: 41
2738 22:14:29.623654 [Byte1]: 41
2739 22:14:29.627579
2740 22:14:29.627681 Set Vref, RX VrefLevel [Byte0]: 42
2741 22:14:29.630945 [Byte1]: 42
2742 22:14:29.635760
2743 22:14:29.635846 Set Vref, RX VrefLevel [Byte0]: 43
2744 22:14:29.638741 [Byte1]: 43
2745 22:14:29.643296
2746 22:14:29.643416 Set Vref, RX VrefLevel [Byte0]: 44
2747 22:14:29.647003 [Byte1]: 44
2748 22:14:29.651466
2749 22:14:29.651551 Set Vref, RX VrefLevel [Byte0]: 45
2750 22:14:29.654940 [Byte1]: 45
2751 22:14:29.659641
2752 22:14:29.659726 Set Vref, RX VrefLevel [Byte0]: 46
2753 22:14:29.662833 [Byte1]: 46
2754 22:14:29.667522
2755 22:14:29.667611 Set Vref, RX VrefLevel [Byte0]: 47
2756 22:14:29.670483 [Byte1]: 47
2757 22:14:29.675390
2758 22:14:29.675491 Set Vref, RX VrefLevel [Byte0]: 48
2759 22:14:29.678861 [Byte1]: 48
2760 22:14:29.683046
2761 22:14:29.683131 Set Vref, RX VrefLevel [Byte0]: 49
2762 22:14:29.686373 [Byte1]: 49
2763 22:14:29.691560
2764 22:14:29.691647 Set Vref, RX VrefLevel [Byte0]: 50
2765 22:14:29.694376 [Byte1]: 50
2766 22:14:29.698999
2767 22:14:29.699098 Set Vref, RX VrefLevel [Byte0]: 51
2768 22:14:29.702293 [Byte1]: 51
2769 22:14:29.707172
2770 22:14:29.707257 Set Vref, RX VrefLevel [Byte0]: 52
2771 22:14:29.709994 [Byte1]: 52
2772 22:14:29.714555
2773 22:14:29.714703 Set Vref, RX VrefLevel [Byte0]: 53
2774 22:14:29.718033 [Byte1]: 53
2775 22:14:29.722769
2776 22:14:29.722870 Set Vref, RX VrefLevel [Byte0]: 54
2777 22:14:29.726277 [Byte1]: 54
2778 22:14:29.730842
2779 22:14:29.730934 Set Vref, RX VrefLevel [Byte0]: 55
2780 22:14:29.734077 [Byte1]: 55
2781 22:14:29.738521
2782 22:14:29.738599 Set Vref, RX VrefLevel [Byte0]: 56
2783 22:14:29.742041 [Byte1]: 56
2784 22:14:29.746603
2785 22:14:29.746692 Set Vref, RX VrefLevel [Byte0]: 57
2786 22:14:29.749761 [Byte1]: 57
2787 22:14:29.754768
2788 22:14:29.754883 Set Vref, RX VrefLevel [Byte0]: 58
2789 22:14:29.757809 [Byte1]: 58
2790 22:14:29.762650
2791 22:14:29.762762 Set Vref, RX VrefLevel [Byte0]: 59
2792 22:14:29.765685 [Byte1]: 59
2793 22:14:29.770515
2794 22:14:29.770626 Set Vref, RX VrefLevel [Byte0]: 60
2795 22:14:29.773500 [Byte1]: 60
2796 22:14:29.778251
2797 22:14:29.778332 Set Vref, RX VrefLevel [Byte0]: 61
2798 22:14:29.781423 [Byte1]: 61
2799 22:14:29.786150
2800 22:14:29.786319 Set Vref, RX VrefLevel [Byte0]: 62
2801 22:14:29.789246 [Byte1]: 62
2802 22:14:29.793876
2803 22:14:29.794013 Set Vref, RX VrefLevel [Byte0]: 63
2804 22:14:29.797439 [Byte1]: 63
2805 22:14:29.802373
2806 22:14:29.802454 Set Vref, RX VrefLevel [Byte0]: 64
2807 22:14:29.805471 [Byte1]: 64
2808 22:14:29.809859
2809 22:14:29.809938 Set Vref, RX VrefLevel [Byte0]: 65
2810 22:14:29.813241 [Byte1]: 65
2811 22:14:29.817678
2812 22:14:29.817769 Set Vref, RX VrefLevel [Byte0]: 66
2813 22:14:29.821079 [Byte1]: 66
2814 22:14:29.826040
2815 22:14:29.826120 Set Vref, RX VrefLevel [Byte0]: 67
2816 22:14:29.829290 [Byte1]: 67
2817 22:14:29.833714
2818 22:14:29.833795 Set Vref, RX VrefLevel [Byte0]: 68
2819 22:14:29.837100 [Byte1]: 68
2820 22:14:29.841635
2821 22:14:29.841723 Final RX Vref Byte 0 = 52 to rank0
2822 22:14:29.844849 Final RX Vref Byte 1 = 51 to rank0
2823 22:14:29.848512 Final RX Vref Byte 0 = 52 to rank1
2824 22:14:29.851736 Final RX Vref Byte 1 = 51 to rank1==
2825 22:14:29.854762 Dram Type= 6, Freq= 0, CH_0, rank 0
2826 22:14:29.861963 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2827 22:14:29.862049 ==
2828 22:14:29.862117 DQS Delay:
2829 22:14:29.862180 DQS0 = 0, DQS1 = 0
2830 22:14:29.864638 DQM Delay:
2831 22:14:29.864724 DQM0 = 115, DQM1 = 104
2832 22:14:29.868255 DQ Delay:
2833 22:14:29.871743 DQ0 =116, DQ1 =114, DQ2 =112, DQ3 =114
2834 22:14:29.874706 DQ4 =116, DQ5 =108, DQ6 =120, DQ7 =122
2835 22:14:29.878341 DQ8 =92, DQ9 =90, DQ10 =104, DQ11 =96
2836 22:14:29.881664 DQ12 =114, DQ13 =110, DQ14 =118, DQ15 =114
2837 22:14:29.881750
2838 22:14:29.881817
2839 22:14:29.888151 [DQSOSCAuto] RK0, (LSB)MR18= 0xfceb, (MSB)MR19= 0x303, tDQSOscB0 = 418 ps tDQSOscB1 = 411 ps
2840 22:14:29.891697 CH0 RK0: MR19=303, MR18=FCEB
2841 22:14:29.898767 CH0_RK0: MR19=0x303, MR18=0xFCEB, DQSOSC=411, MR23=63, INC=38, DEC=25
2842 22:14:29.898853
2843 22:14:29.902176 ----->DramcWriteLeveling(PI) begin...
2844 22:14:29.902263 ==
2845 22:14:29.905653 Dram Type= 6, Freq= 0, CH_0, rank 1
2846 22:14:29.908193 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2847 22:14:29.908278 ==
2848 22:14:29.911897 Write leveling (Byte 0): 33 => 33
2849 22:14:29.915211 Write leveling (Byte 1): 29 => 29
2850 22:14:29.918436 DramcWriteLeveling(PI) end<-----
2851 22:14:29.918520
2852 22:14:29.918588 ==
2853 22:14:29.922156 Dram Type= 6, Freq= 0, CH_0, rank 1
2854 22:14:29.928514 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2855 22:14:29.928600 ==
2856 22:14:29.928668 [Gating] SW mode calibration
2857 22:14:29.938219 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2858 22:14:29.941649 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2859 22:14:29.945211 0 15 0 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
2860 22:14:29.951835 0 15 4 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 1)
2861 22:14:29.955354 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2862 22:14:29.958035 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2863 22:14:29.965149 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2864 22:14:29.968163 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2865 22:14:29.971728 0 15 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
2866 22:14:29.978156 0 15 28 | B1->B0 | 3434 2525 | 1 0 | (1 1) (1 0)
2867 22:14:29.981702 1 0 0 | B1->B0 | 2a2a 2323 | 1 0 | (1 1) (0 0)
2868 22:14:29.985469 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2869 22:14:29.991745 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2870 22:14:29.995166 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2871 22:14:29.998570 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2872 22:14:30.004853 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2873 22:14:30.008128 1 0 24 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
2874 22:14:30.011849 1 0 28 | B1->B0 | 2323 4444 | 0 0 | (0 0) (0 0)
2875 22:14:30.018459 1 1 0 | B1->B0 | 3232 4343 | 0 0 | (0 0) (0 0)
2876 22:14:30.021985 1 1 4 | B1->B0 | 4545 4646 | 1 0 | (0 0) (0 0)
2877 22:14:30.024665 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2878 22:14:30.028235 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2879 22:14:30.035161 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2880 22:14:30.037904 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2881 22:14:30.041565 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2882 22:14:30.048029 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2883 22:14:30.051436 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2884 22:14:30.054797 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2885 22:14:30.062086 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2886 22:14:30.064921 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2887 22:14:30.068515 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2888 22:14:30.074919 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2889 22:14:30.078369 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2890 22:14:30.081651 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2891 22:14:30.089088 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2892 22:14:30.091689 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2893 22:14:30.095106 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2894 22:14:30.101765 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2895 22:14:30.105328 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2896 22:14:30.108394 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2897 22:14:30.111850 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2898 22:14:30.118287 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2899 22:14:30.121761 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
2900 22:14:30.125398 Total UI for P1: 0, mck2ui 16
2901 22:14:30.128518 best dqsien dly found for B0: ( 1, 3, 26)
2902 22:14:30.131734 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2903 22:14:30.135353 Total UI for P1: 0, mck2ui 16
2904 22:14:30.138265 best dqsien dly found for B1: ( 1, 4, 2)
2905 22:14:30.141587 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2906 22:14:30.144727 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2907 22:14:30.144829
2908 22:14:30.152121 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2909 22:14:30.154740 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2910 22:14:30.158688 [Gating] SW calibration Done
2911 22:14:30.158793 ==
2912 22:14:30.161961 Dram Type= 6, Freq= 0, CH_0, rank 1
2913 22:14:30.164811 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2914 22:14:30.164916 ==
2915 22:14:30.165013 RX Vref Scan: 0
2916 22:14:30.165123
2917 22:14:30.168425 RX Vref 0 -> 0, step: 1
2918 22:14:30.168532
2919 22:14:30.171990 RX Delay -40 -> 252, step: 8
2920 22:14:30.174775 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2921 22:14:30.178264 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2922 22:14:30.181757 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2923 22:14:30.188242 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2924 22:14:30.191699 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2925 22:14:30.194777 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152
2926 22:14:30.198351 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2927 22:14:30.201898 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2928 22:14:30.208115 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2929 22:14:30.211343 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2930 22:14:30.214937 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2931 22:14:30.218275 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2932 22:14:30.221481 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2933 22:14:30.228382 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2934 22:14:30.231352 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2935 22:14:30.234878 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2936 22:14:30.234969 ==
2937 22:14:30.238402 Dram Type= 6, Freq= 0, CH_0, rank 1
2938 22:14:30.241953 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2939 22:14:30.242037 ==
2940 22:14:30.244993 DQS Delay:
2941 22:14:30.245076 DQS0 = 0, DQS1 = 0
2942 22:14:30.248251 DQM Delay:
2943 22:14:30.248337 DQM0 = 115, DQM1 = 106
2944 22:14:30.251657 DQ Delay:
2945 22:14:30.255083 DQ0 =115, DQ1 =115, DQ2 =111, DQ3 =115
2946 22:14:30.258442 DQ4 =115, DQ5 =107, DQ6 =123, DQ7 =123
2947 22:14:30.261716 DQ8 =95, DQ9 =95, DQ10 =103, DQ11 =99
2948 22:14:30.265225 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =111
2949 22:14:30.265325
2950 22:14:30.265391
2951 22:14:30.265453 ==
2952 22:14:30.268697 Dram Type= 6, Freq= 0, CH_0, rank 1
2953 22:14:30.271692 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2954 22:14:30.271776 ==
2955 22:14:30.271842
2956 22:14:30.271903
2957 22:14:30.275096 TX Vref Scan disable
2958 22:14:30.278182 == TX Byte 0 ==
2959 22:14:30.281465 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2960 22:14:30.285077 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2961 22:14:30.288444 == TX Byte 1 ==
2962 22:14:30.292278 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2963 22:14:30.295103 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2964 22:14:30.295200 ==
2965 22:14:30.298196 Dram Type= 6, Freq= 0, CH_0, rank 1
2966 22:14:30.301699 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2967 22:14:30.301842 ==
2968 22:14:30.315458 TX Vref=22, minBit 0, minWin=25, winSum=417
2969 22:14:30.318224 TX Vref=24, minBit 5, minWin=25, winSum=429
2970 22:14:30.321800 TX Vref=26, minBit 2, minWin=26, winSum=434
2971 22:14:30.324915 TX Vref=28, minBit 0, minWin=27, winSum=438
2972 22:14:30.328728 TX Vref=30, minBit 0, minWin=27, winSum=439
2973 22:14:30.331768 TX Vref=32, minBit 13, minWin=26, winSum=437
2974 22:14:30.338127 [TxChooseVref] Worse bit 0, Min win 27, Win sum 439, Final Vref 30
2975 22:14:30.338248
2976 22:14:30.341350 Final TX Range 1 Vref 30
2977 22:14:30.341447
2978 22:14:30.341538 ==
2979 22:14:30.344780 Dram Type= 6, Freq= 0, CH_0, rank 1
2980 22:14:30.348281 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2981 22:14:30.348361 ==
2982 22:14:30.351595
2983 22:14:30.351680
2984 22:14:30.351746 TX Vref Scan disable
2985 22:14:30.354969 == TX Byte 0 ==
2986 22:14:30.358345 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2987 22:14:30.361605 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2988 22:14:30.365097 == TX Byte 1 ==
2989 22:14:30.368367 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2990 22:14:30.374929 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2991 22:14:30.375014
2992 22:14:30.375081 [DATLAT]
2993 22:14:30.375144 Freq=1200, CH0 RK1
2994 22:14:30.375204
2995 22:14:30.378203 DATLAT Default: 0xd
2996 22:14:30.378287 0, 0xFFFF, sum = 0
2997 22:14:30.381821 1, 0xFFFF, sum = 0
2998 22:14:30.381906 2, 0xFFFF, sum = 0
2999 22:14:30.384792 3, 0xFFFF, sum = 0
3000 22:14:30.388731 4, 0xFFFF, sum = 0
3001 22:14:30.388817 5, 0xFFFF, sum = 0
3002 22:14:30.391612 6, 0xFFFF, sum = 0
3003 22:14:30.391698 7, 0xFFFF, sum = 0
3004 22:14:30.394747 8, 0xFFFF, sum = 0
3005 22:14:30.394833 9, 0xFFFF, sum = 0
3006 22:14:30.398038 10, 0xFFFF, sum = 0
3007 22:14:30.398124 11, 0xFFFF, sum = 0
3008 22:14:30.401541 12, 0x0, sum = 1
3009 22:14:30.401627 13, 0x0, sum = 2
3010 22:14:30.404447 14, 0x0, sum = 3
3011 22:14:30.404533 15, 0x0, sum = 4
3012 22:14:30.408054 best_step = 13
3013 22:14:30.408135
3014 22:14:30.408203 ==
3015 22:14:30.411584 Dram Type= 6, Freq= 0, CH_0, rank 1
3016 22:14:30.414639 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3017 22:14:30.414720 ==
3018 22:14:30.414794 RX Vref Scan: 0
3019 22:14:30.414857
3020 22:14:30.418249 RX Vref 0 -> 0, step: 1
3021 22:14:30.418334
3022 22:14:30.421162 RX Delay -21 -> 252, step: 4
3023 22:14:30.424979 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3024 22:14:30.431439 iDelay=195, Bit 1, Center 114 (43 ~ 186) 144
3025 22:14:30.434728 iDelay=195, Bit 2, Center 110 (39 ~ 182) 144
3026 22:14:30.438144 iDelay=195, Bit 3, Center 114 (43 ~ 186) 144
3027 22:14:30.441324 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3028 22:14:30.444856 iDelay=195, Bit 5, Center 104 (35 ~ 174) 140
3029 22:14:30.451242 iDelay=195, Bit 6, Center 122 (51 ~ 194) 144
3030 22:14:30.454770 iDelay=195, Bit 7, Center 122 (51 ~ 194) 144
3031 22:14:30.458305 iDelay=195, Bit 8, Center 94 (27 ~ 162) 136
3032 22:14:30.461347 iDelay=195, Bit 9, Center 92 (23 ~ 162) 140
3033 22:14:30.464715 iDelay=195, Bit 10, Center 106 (39 ~ 174) 136
3034 22:14:30.467990 iDelay=195, Bit 11, Center 94 (27 ~ 162) 136
3035 22:14:30.474970 iDelay=195, Bit 12, Center 110 (43 ~ 178) 136
3036 22:14:30.478120 iDelay=195, Bit 13, Center 110 (43 ~ 178) 136
3037 22:14:30.481624 iDelay=195, Bit 14, Center 116 (51 ~ 182) 132
3038 22:14:30.484527 iDelay=195, Bit 15, Center 114 (47 ~ 182) 136
3039 22:14:30.484610 ==
3040 22:14:30.488192 Dram Type= 6, Freq= 0, CH_0, rank 1
3041 22:14:30.494625 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3042 22:14:30.494736 ==
3043 22:14:30.494802 DQS Delay:
3044 22:14:30.498208 DQS0 = 0, DQS1 = 0
3045 22:14:30.498305 DQM Delay:
3046 22:14:30.498400 DQM0 = 114, DQM1 = 104
3047 22:14:30.501336 DQ Delay:
3048 22:14:30.504743 DQ0 =114, DQ1 =114, DQ2 =110, DQ3 =114
3049 22:14:30.508466 DQ4 =112, DQ5 =104, DQ6 =122, DQ7 =122
3050 22:14:30.511618 DQ8 =94, DQ9 =92, DQ10 =106, DQ11 =94
3051 22:14:30.515111 DQ12 =110, DQ13 =110, DQ14 =116, DQ15 =114
3052 22:14:30.515187
3053 22:14:30.515250
3054 22:14:30.521779 [DQSOSCAuto] RK1, (LSB)MR18= 0x1f2, (MSB)MR19= 0x403, tDQSOscB0 = 415 ps tDQSOscB1 = 409 ps
3055 22:14:30.525102 CH0 RK1: MR19=403, MR18=1F2
3056 22:14:30.531455 CH0_RK1: MR19=0x403, MR18=0x1F2, DQSOSC=409, MR23=63, INC=39, DEC=26
3057 22:14:30.535316 [RxdqsGatingPostProcess] freq 1200
3058 22:14:30.541823 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3059 22:14:30.541935 best DQS0 dly(2T, 0.5T) = (0, 11)
3060 22:14:30.545055 best DQS1 dly(2T, 0.5T) = (0, 12)
3061 22:14:30.548682 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3062 22:14:30.552105 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3063 22:14:30.555111 best DQS0 dly(2T, 0.5T) = (0, 11)
3064 22:14:30.558538 best DQS1 dly(2T, 0.5T) = (0, 12)
3065 22:14:30.562135 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3066 22:14:30.565113 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3067 22:14:30.568610 Pre-setting of DQS Precalculation
3068 22:14:30.571709 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3069 22:14:30.571797 ==
3070 22:14:30.575259 Dram Type= 6, Freq= 0, CH_1, rank 0
3071 22:14:30.581898 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3072 22:14:30.582005 ==
3073 22:14:30.585298 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3074 22:14:30.591939 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3075 22:14:30.601156 [CA 0] Center 38 (9~68) winsize 60
3076 22:14:30.603708 [CA 1] Center 38 (8~68) winsize 61
3077 22:14:30.607356 [CA 2] Center 35 (5~65) winsize 61
3078 22:14:30.610386 [CA 3] Center 34 (4~65) winsize 62
3079 22:14:30.613913 [CA 4] Center 34 (4~65) winsize 62
3080 22:14:30.617032 [CA 5] Center 34 (4~64) winsize 61
3081 22:14:30.617107
3082 22:14:30.620469 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3083 22:14:30.620552
3084 22:14:30.623528 [CATrainingPosCal] consider 1 rank data
3085 22:14:30.627045 u2DelayCellTimex100 = 270/100 ps
3086 22:14:30.630311 CA0 delay=38 (9~68),Diff = 4 PI (19 cell)
3087 22:14:30.636687 CA1 delay=38 (8~68),Diff = 4 PI (19 cell)
3088 22:14:30.639964 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3089 22:14:30.643436 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
3090 22:14:30.647030 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3091 22:14:30.650563 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3092 22:14:30.650666
3093 22:14:30.653462 CA PerBit enable=1, Macro0, CA PI delay=34
3094 22:14:30.653561
3095 22:14:30.657086 [CBTSetCACLKResult] CA Dly = 34
3096 22:14:30.657188 CS Dly: 6 (0~37)
3097 22:14:30.660551 ==
3098 22:14:30.664013 Dram Type= 6, Freq= 0, CH_1, rank 1
3099 22:14:30.667376 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3100 22:14:30.667492 ==
3101 22:14:30.673678 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3102 22:14:30.677064 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3103 22:14:30.686508 [CA 0] Center 38 (8~68) winsize 61
3104 22:14:30.689858 [CA 1] Center 38 (8~68) winsize 61
3105 22:14:30.692826 [CA 2] Center 34 (4~65) winsize 62
3106 22:14:30.696395 [CA 3] Center 34 (4~65) winsize 62
3107 22:14:30.699732 [CA 4] Center 34 (4~65) winsize 62
3108 22:14:30.703370 [CA 5] Center 33 (3~63) winsize 61
3109 22:14:30.703444
3110 22:14:30.706270 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3111 22:14:30.706344
3112 22:14:30.709842 [CATrainingPosCal] consider 2 rank data
3113 22:14:30.712927 u2DelayCellTimex100 = 270/100 ps
3114 22:14:30.716444 CA0 delay=38 (9~68),Diff = 5 PI (24 cell)
3115 22:14:30.720006 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3116 22:14:30.723461 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3117 22:14:30.730171 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3118 22:14:30.732973 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
3119 22:14:30.736681 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3120 22:14:30.736788
3121 22:14:30.739468 CA PerBit enable=1, Macro0, CA PI delay=33
3122 22:14:30.739564
3123 22:14:30.742875 [CBTSetCACLKResult] CA Dly = 33
3124 22:14:30.742976 CS Dly: 7 (0~40)
3125 22:14:30.743134
3126 22:14:30.746427 ----->DramcWriteLeveling(PI) begin...
3127 22:14:30.746546 ==
3128 22:14:30.749981 Dram Type= 6, Freq= 0, CH_1, rank 0
3129 22:14:30.756390 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3130 22:14:30.756481 ==
3131 22:14:30.760204 Write leveling (Byte 0): 25 => 25
3132 22:14:30.762833 Write leveling (Byte 1): 28 => 28
3133 22:14:30.762938 DramcWriteLeveling(PI) end<-----
3134 22:14:30.766365
3135 22:14:30.766462 ==
3136 22:14:30.769334 Dram Type= 6, Freq= 0, CH_1, rank 0
3137 22:14:30.773060 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3138 22:14:30.773189 ==
3139 22:14:30.776626 [Gating] SW mode calibration
3140 22:14:30.783238 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3141 22:14:30.786144 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3142 22:14:30.792861 0 15 0 | B1->B0 | 2828 2323 | 1 1 | (0 0) (0 0)
3143 22:14:30.796698 0 15 4 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
3144 22:14:30.799741 0 15 8 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
3145 22:14:30.806218 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3146 22:14:30.809820 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3147 22:14:30.812869 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3148 22:14:30.819329 0 15 24 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
3149 22:14:30.822935 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3150 22:14:30.826457 1 0 0 | B1->B0 | 2525 2c2c | 0 1 | (0 0) (1 0)
3151 22:14:30.832893 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3152 22:14:30.836277 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3153 22:14:30.839714 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3154 22:14:30.846306 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3155 22:14:30.849504 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3156 22:14:30.852975 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3157 22:14:30.859701 1 0 28 | B1->B0 | 2d2c 2828 | 1 0 | (0 0) (0 0)
3158 22:14:30.863135 1 1 0 | B1->B0 | 4242 3636 | 0 0 | (0 0) (0 0)
3159 22:14:30.866191 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3160 22:14:30.872765 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3161 22:14:30.876281 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3162 22:14:30.879687 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3163 22:14:30.882979 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3164 22:14:30.889648 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3165 22:14:30.893031 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3166 22:14:30.896282 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3167 22:14:30.902543 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3168 22:14:30.906055 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3169 22:14:30.909844 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3170 22:14:30.916131 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3171 22:14:30.919735 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3172 22:14:30.922575 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3173 22:14:30.929577 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3174 22:14:30.933124 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3175 22:14:30.936516 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3176 22:14:30.942911 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3177 22:14:30.946183 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3178 22:14:30.949581 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3179 22:14:30.956225 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3180 22:14:30.959286 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3181 22:14:30.962543 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3182 22:14:30.969423 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3183 22:14:30.969549 Total UI for P1: 0, mck2ui 16
3184 22:14:30.973061 best dqsien dly found for B1: ( 1, 3, 28)
3185 22:14:30.979259 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3186 22:14:30.982929 Total UI for P1: 0, mck2ui 16
3187 22:14:30.986250 best dqsien dly found for B0: ( 1, 3, 30)
3188 22:14:30.989570 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
3189 22:14:30.993011 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3190 22:14:30.993137
3191 22:14:30.996094 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
3192 22:14:30.999517 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3193 22:14:31.003076 [Gating] SW calibration Done
3194 22:14:31.003188 ==
3195 22:14:31.005994 Dram Type= 6, Freq= 0, CH_1, rank 0
3196 22:14:31.009577 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3197 22:14:31.009710 ==
3198 22:14:31.012615 RX Vref Scan: 0
3199 22:14:31.012735
3200 22:14:31.012835 RX Vref 0 -> 0, step: 1
3201 22:14:31.016092
3202 22:14:31.016206 RX Delay -40 -> 252, step: 8
3203 22:14:31.022659 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3204 22:14:31.025909 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3205 22:14:31.029599 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3206 22:14:31.032611 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3207 22:14:31.036074 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3208 22:14:31.039734 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3209 22:14:31.045881 iDelay=200, Bit 6, Center 123 (56 ~ 191) 136
3210 22:14:31.049366 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3211 22:14:31.052774 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3212 22:14:31.056067 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3213 22:14:31.059330 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
3214 22:14:31.066252 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3215 22:14:31.069680 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3216 22:14:31.073402 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
3217 22:14:31.076149 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3218 22:14:31.079641 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3219 22:14:31.083034 ==
3220 22:14:31.086259 Dram Type= 6, Freq= 0, CH_1, rank 0
3221 22:14:31.089520 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3222 22:14:31.089629 ==
3223 22:14:31.089746 DQS Delay:
3224 22:14:31.092909 DQS0 = 0, DQS1 = 0
3225 22:14:31.093015 DQM Delay:
3226 22:14:31.096372 DQM0 = 115, DQM1 = 108
3227 22:14:31.096462 DQ Delay:
3228 22:14:31.099652 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =115
3229 22:14:31.102968 DQ4 =111, DQ5 =127, DQ6 =123, DQ7 =111
3230 22:14:31.106358 DQ8 =99, DQ9 =95, DQ10 =107, DQ11 =107
3231 22:14:31.109197 DQ12 =119, DQ13 =115, DQ14 =111, DQ15 =111
3232 22:14:31.109300
3233 22:14:31.109401
3234 22:14:31.109502 ==
3235 22:14:31.112738 Dram Type= 6, Freq= 0, CH_1, rank 0
3236 22:14:31.119546 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3237 22:14:31.119651 ==
3238 22:14:31.119721
3239 22:14:31.119784
3240 22:14:31.119845 TX Vref Scan disable
3241 22:14:31.123126 == TX Byte 0 ==
3242 22:14:31.126151 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3243 22:14:31.129646 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3244 22:14:31.132695 == TX Byte 1 ==
3245 22:14:31.136390 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3246 22:14:31.142826 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3247 22:14:31.142913 ==
3248 22:14:31.146121 Dram Type= 6, Freq= 0, CH_1, rank 0
3249 22:14:31.149120 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3250 22:14:31.149246 ==
3251 22:14:31.161090 TX Vref=22, minBit 1, minWin=25, winSum=415
3252 22:14:31.164053 TX Vref=24, minBit 1, minWin=25, winSum=417
3253 22:14:31.167588 TX Vref=26, minBit 0, minWin=26, winSum=425
3254 22:14:31.170941 TX Vref=28, minBit 0, minWin=26, winSum=427
3255 22:14:31.174410 TX Vref=30, minBit 3, minWin=26, winSum=429
3256 22:14:31.177520 TX Vref=32, minBit 1, minWin=26, winSum=429
3257 22:14:31.184299 [TxChooseVref] Worse bit 3, Min win 26, Win sum 429, Final Vref 30
3258 22:14:31.184389
3259 22:14:31.187491 Final TX Range 1 Vref 30
3260 22:14:31.187576
3261 22:14:31.187644 ==
3262 22:14:31.190761 Dram Type= 6, Freq= 0, CH_1, rank 0
3263 22:14:31.194021 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3264 22:14:31.194106 ==
3265 22:14:31.194173
3266 22:14:31.197636
3267 22:14:31.197719 TX Vref Scan disable
3268 22:14:31.200698 == TX Byte 0 ==
3269 22:14:31.204186 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3270 22:14:31.207570 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3271 22:14:31.210799 == TX Byte 1 ==
3272 22:14:31.214394 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3273 22:14:31.217373 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3274 22:14:31.217461
3275 22:14:31.220613 [DATLAT]
3276 22:14:31.220698 Freq=1200, CH1 RK0
3277 22:14:31.220765
3278 22:14:31.223940 DATLAT Default: 0xd
3279 22:14:31.224024 0, 0xFFFF, sum = 0
3280 22:14:31.227841 1, 0xFFFF, sum = 0
3281 22:14:31.227927 2, 0xFFFF, sum = 0
3282 22:14:31.230593 3, 0xFFFF, sum = 0
3283 22:14:31.230711 4, 0xFFFF, sum = 0
3284 22:14:31.234476 5, 0xFFFF, sum = 0
3285 22:14:31.234585 6, 0xFFFF, sum = 0
3286 22:14:31.237134 7, 0xFFFF, sum = 0
3287 22:14:31.240810 8, 0xFFFF, sum = 0
3288 22:14:31.240902 9, 0xFFFF, sum = 0
3289 22:14:31.243841 10, 0xFFFF, sum = 0
3290 22:14:31.243954 11, 0xFFFF, sum = 0
3291 22:14:31.247458 12, 0x0, sum = 1
3292 22:14:31.247545 13, 0x0, sum = 2
3293 22:14:31.250952 14, 0x0, sum = 3
3294 22:14:31.251064 15, 0x0, sum = 4
3295 22:14:31.251161 best_step = 13
3296 22:14:31.251251
3297 22:14:31.253916 ==
3298 22:14:31.257558 Dram Type= 6, Freq= 0, CH_1, rank 0
3299 22:14:31.260829 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3300 22:14:31.260915 ==
3301 22:14:31.261013 RX Vref Scan: 1
3302 22:14:31.261116
3303 22:14:31.263881 Set Vref Range= 32 -> 127
3304 22:14:31.263985
3305 22:14:31.267241 RX Vref 32 -> 127, step: 1
3306 22:14:31.267358
3307 22:14:31.270687 RX Delay -21 -> 252, step: 4
3308 22:14:31.270767
3309 22:14:31.273979 Set Vref, RX VrefLevel [Byte0]: 32
3310 22:14:31.277436 [Byte1]: 32
3311 22:14:31.277511
3312 22:14:31.280523 Set Vref, RX VrefLevel [Byte0]: 33
3313 22:14:31.283732 [Byte1]: 33
3314 22:14:31.283814
3315 22:14:31.287330 Set Vref, RX VrefLevel [Byte0]: 34
3316 22:14:31.290797 [Byte1]: 34
3317 22:14:31.294697
3318 22:14:31.294780 Set Vref, RX VrefLevel [Byte0]: 35
3319 22:14:31.298108 [Byte1]: 35
3320 22:14:31.303160
3321 22:14:31.303270 Set Vref, RX VrefLevel [Byte0]: 36
3322 22:14:31.306450 [Byte1]: 36
3323 22:14:31.310941
3324 22:14:31.311019 Set Vref, RX VrefLevel [Byte0]: 37
3325 22:14:31.314315 [Byte1]: 37
3326 22:14:31.318759
3327 22:14:31.318885 Set Vref, RX VrefLevel [Byte0]: 38
3328 22:14:31.321772 [Byte1]: 38
3329 22:14:31.326742
3330 22:14:31.326850 Set Vref, RX VrefLevel [Byte0]: 39
3331 22:14:31.329792 [Byte1]: 39
3332 22:14:31.334638
3333 22:14:31.334727 Set Vref, RX VrefLevel [Byte0]: 40
3334 22:14:31.338202 [Byte1]: 40
3335 22:14:31.342434
3336 22:14:31.342549 Set Vref, RX VrefLevel [Byte0]: 41
3337 22:14:31.345608 [Byte1]: 41
3338 22:14:31.350533
3339 22:14:31.350611 Set Vref, RX VrefLevel [Byte0]: 42
3340 22:14:31.353438 [Byte1]: 42
3341 22:14:31.358244
3342 22:14:31.358336 Set Vref, RX VrefLevel [Byte0]: 43
3343 22:14:31.361878 [Byte1]: 43
3344 22:14:31.366093
3345 22:14:31.366195 Set Vref, RX VrefLevel [Byte0]: 44
3346 22:14:31.369917 [Byte1]: 44
3347 22:14:31.374500
3348 22:14:31.374586 Set Vref, RX VrefLevel [Byte0]: 45
3349 22:14:31.377536 [Byte1]: 45
3350 22:14:31.381741
3351 22:14:31.381816 Set Vref, RX VrefLevel [Byte0]: 46
3352 22:14:31.385489 [Byte1]: 46
3353 22:14:31.389998
3354 22:14:31.390073 Set Vref, RX VrefLevel [Byte0]: 47
3355 22:14:31.393623 [Byte1]: 47
3356 22:14:31.397713
3357 22:14:31.397788 Set Vref, RX VrefLevel [Byte0]: 48
3358 22:14:31.401498 [Byte1]: 48
3359 22:14:31.406090
3360 22:14:31.406175 Set Vref, RX VrefLevel [Byte0]: 49
3361 22:14:31.409529 [Byte1]: 49
3362 22:14:31.414059
3363 22:14:31.414144 Set Vref, RX VrefLevel [Byte0]: 50
3364 22:14:31.416803 [Byte1]: 50
3365 22:14:31.421325
3366 22:14:31.421436 Set Vref, RX VrefLevel [Byte0]: 51
3367 22:14:31.424676 [Byte1]: 51
3368 22:14:31.429392
3369 22:14:31.429477 Set Vref, RX VrefLevel [Byte0]: 52
3370 22:14:31.433055 [Byte1]: 52
3371 22:14:31.437838
3372 22:14:31.437922 Set Vref, RX VrefLevel [Byte0]: 53
3373 22:14:31.440814 [Byte1]: 53
3374 22:14:31.445468
3375 22:14:31.445551 Set Vref, RX VrefLevel [Byte0]: 54
3376 22:14:31.449194 [Byte1]: 54
3377 22:14:31.453345
3378 22:14:31.453423 Set Vref, RX VrefLevel [Byte0]: 55
3379 22:14:31.456332 [Byte1]: 55
3380 22:14:31.461255
3381 22:14:31.461345 Set Vref, RX VrefLevel [Byte0]: 56
3382 22:14:31.464917 [Byte1]: 56
3383 22:14:31.469362
3384 22:14:31.469447 Set Vref, RX VrefLevel [Byte0]: 57
3385 22:14:31.472499 [Byte1]: 57
3386 22:14:31.476940
3387 22:14:31.477051 Set Vref, RX VrefLevel [Byte0]: 58
3388 22:14:31.480198 [Byte1]: 58
3389 22:14:31.484912
3390 22:14:31.485018 Set Vref, RX VrefLevel [Byte0]: 59
3391 22:14:31.488155 [Byte1]: 59
3392 22:14:31.492977
3393 22:14:31.493091 Set Vref, RX VrefLevel [Byte0]: 60
3394 22:14:31.495976 [Byte1]: 60
3395 22:14:31.500567
3396 22:14:31.500644 Set Vref, RX VrefLevel [Byte0]: 61
3397 22:14:31.503959 [Byte1]: 61
3398 22:14:31.508489
3399 22:14:31.508566 Set Vref, RX VrefLevel [Byte0]: 62
3400 22:14:31.511773 [Byte1]: 62
3401 22:14:31.516945
3402 22:14:31.517059 Set Vref, RX VrefLevel [Byte0]: 63
3403 22:14:31.520201 [Byte1]: 63
3404 22:14:31.524729
3405 22:14:31.524808 Set Vref, RX VrefLevel [Byte0]: 64
3406 22:14:31.527596 [Byte1]: 64
3407 22:14:31.532552
3408 22:14:31.532657 Set Vref, RX VrefLevel [Byte0]: 65
3409 22:14:31.535743 [Byte1]: 65
3410 22:14:31.540484
3411 22:14:31.540562 Set Vref, RX VrefLevel [Byte0]: 66
3412 22:14:31.543524 [Byte1]: 66
3413 22:14:31.548213
3414 22:14:31.548309 Set Vref, RX VrefLevel [Byte0]: 67
3415 22:14:31.551709 [Byte1]: 67
3416 22:14:31.556530
3417 22:14:31.556613 Set Vref, RX VrefLevel [Byte0]: 68
3418 22:14:31.559529 [Byte1]: 68
3419 22:14:31.564217
3420 22:14:31.564299 Set Vref, RX VrefLevel [Byte0]: 69
3421 22:14:31.567815 [Byte1]: 69
3422 22:14:31.572465
3423 22:14:31.572549 Set Vref, RX VrefLevel [Byte0]: 70
3424 22:14:31.575808 [Byte1]: 70
3425 22:14:31.580168
3426 22:14:31.580356 Set Vref, RX VrefLevel [Byte0]: 71
3427 22:14:31.583471 [Byte1]: 71
3428 22:14:31.587989
3429 22:14:31.588073 Final RX Vref Byte 0 = 59 to rank0
3430 22:14:31.591488 Final RX Vref Byte 1 = 53 to rank0
3431 22:14:31.594382 Final RX Vref Byte 0 = 59 to rank1
3432 22:14:31.597777 Final RX Vref Byte 1 = 53 to rank1==
3433 22:14:31.600923 Dram Type= 6, Freq= 0, CH_1, rank 0
3434 22:14:31.607697 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3435 22:14:31.607782 ==
3436 22:14:31.607861 DQS Delay:
3437 22:14:31.611059 DQS0 = 0, DQS1 = 0
3438 22:14:31.611189 DQM Delay:
3439 22:14:31.611267 DQM0 = 115, DQM1 = 109
3440 22:14:31.614463 DQ Delay:
3441 22:14:31.617637 DQ0 =118, DQ1 =110, DQ2 =106, DQ3 =114
3442 22:14:31.621041 DQ4 =114, DQ5 =124, DQ6 =126, DQ7 =114
3443 22:14:31.624340 DQ8 =98, DQ9 =98, DQ10 =112, DQ11 =104
3444 22:14:31.627633 DQ12 =116, DQ13 =116, DQ14 =116, DQ15 =114
3445 22:14:31.627725
3446 22:14:31.627797
3447 22:14:31.637980 [DQSOSCAuto] RK0, (LSB)MR18= 0xe4, (MSB)MR19= 0x403, tDQSOscB0 = 421 ps tDQSOscB1 = 410 ps
3448 22:14:31.638064 CH1 RK0: MR19=403, MR18=E4
3449 22:14:31.644341 CH1_RK0: MR19=0x403, MR18=0xE4, DQSOSC=410, MR23=63, INC=39, DEC=26
3450 22:14:31.644424
3451 22:14:31.647294 ----->DramcWriteLeveling(PI) begin...
3452 22:14:31.647432 ==
3453 22:14:31.651039 Dram Type= 6, Freq= 0, CH_1, rank 1
3454 22:14:31.654268 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3455 22:14:31.654350 ==
3456 22:14:31.657706 Write leveling (Byte 0): 26 => 26
3457 22:14:31.661380 Write leveling (Byte 1): 31 => 31
3458 22:14:31.664636 DramcWriteLeveling(PI) end<-----
3459 22:14:31.664718
3460 22:14:31.664783 ==
3461 22:14:31.667513 Dram Type= 6, Freq= 0, CH_1, rank 1
3462 22:14:31.674045 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3463 22:14:31.674128 ==
3464 22:14:31.674194 [Gating] SW mode calibration
3465 22:14:31.684477 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3466 22:14:31.687757 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3467 22:14:31.691006 0 15 0 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
3468 22:14:31.697329 0 15 4 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
3469 22:14:31.700987 0 15 8 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
3470 22:14:31.704357 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3471 22:14:31.711050 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3472 22:14:31.714132 0 15 20 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
3473 22:14:31.717465 0 15 24 | B1->B0 | 3434 2a2a | 0 0 | (0 1) (1 0)
3474 22:14:31.724097 0 15 28 | B1->B0 | 2626 2323 | 0 0 | (1 0) (0 0)
3475 22:14:31.727595 1 0 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3476 22:14:31.730446 1 0 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3477 22:14:31.737477 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3478 22:14:31.740702 1 0 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3479 22:14:31.744128 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3480 22:14:31.750534 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3481 22:14:31.753695 1 0 24 | B1->B0 | 2727 4444 | 0 0 | (1 1) (0 0)
3482 22:14:31.757180 1 0 28 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
3483 22:14:31.764322 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3484 22:14:31.766881 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3485 22:14:31.770418 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3486 22:14:31.777510 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3487 22:14:31.780014 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3488 22:14:31.783634 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3489 22:14:31.790389 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3490 22:14:31.793682 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
3491 22:14:31.796933 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3492 22:14:31.803565 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3493 22:14:31.806589 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3494 22:14:31.810189 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3495 22:14:31.816962 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3496 22:14:31.819824 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3497 22:14:31.823059 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3498 22:14:31.830038 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3499 22:14:31.832978 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3500 22:14:31.836099 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3501 22:14:31.842880 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3502 22:14:31.846399 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3503 22:14:31.849571 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3504 22:14:31.856205 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3505 22:14:31.859588 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3506 22:14:31.863036 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3507 22:14:31.866346 Total UI for P1: 0, mck2ui 16
3508 22:14:31.869561 best dqsien dly found for B0: ( 1, 3, 22)
3509 22:14:31.875750 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3510 22:14:31.875845 Total UI for P1: 0, mck2ui 16
3511 22:14:31.879655 best dqsien dly found for B1: ( 1, 3, 28)
3512 22:14:31.886051 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3513 22:14:31.889551 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3514 22:14:31.889633
3515 22:14:31.892695 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3516 22:14:31.896105 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3517 22:14:31.899271 [Gating] SW calibration Done
3518 22:14:31.899362 ==
3519 22:14:31.902801 Dram Type= 6, Freq= 0, CH_1, rank 1
3520 22:14:31.906093 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3521 22:14:31.906176 ==
3522 22:14:31.909384 RX Vref Scan: 0
3523 22:14:31.909467
3524 22:14:31.909532 RX Vref 0 -> 0, step: 1
3525 22:14:31.909591
3526 22:14:31.912489 RX Delay -40 -> 252, step: 8
3527 22:14:31.916024 iDelay=192, Bit 0, Center 111 (40 ~ 183) 144
3528 22:14:31.922817 iDelay=192, Bit 1, Center 111 (40 ~ 183) 144
3529 22:14:31.925591 iDelay=192, Bit 2, Center 103 (32 ~ 175) 144
3530 22:14:31.929014 iDelay=192, Bit 3, Center 115 (48 ~ 183) 136
3531 22:14:31.932525 iDelay=192, Bit 4, Center 111 (40 ~ 183) 144
3532 22:14:31.935987 iDelay=192, Bit 5, Center 123 (56 ~ 191) 136
3533 22:14:31.942176 iDelay=192, Bit 6, Center 119 (48 ~ 191) 144
3534 22:14:31.945737 iDelay=192, Bit 7, Center 111 (48 ~ 175) 128
3535 22:14:31.948996 iDelay=192, Bit 8, Center 103 (32 ~ 175) 144
3536 22:14:31.952572 iDelay=192, Bit 9, Center 95 (24 ~ 167) 144
3537 22:14:31.955476 iDelay=192, Bit 10, Center 111 (40 ~ 183) 144
3538 22:14:31.962529 iDelay=192, Bit 11, Center 103 (32 ~ 175) 144
3539 22:14:31.965897 iDelay=192, Bit 12, Center 115 (48 ~ 183) 136
3540 22:14:31.969036 iDelay=192, Bit 13, Center 123 (56 ~ 191) 136
3541 22:14:31.972099 iDelay=192, Bit 14, Center 119 (48 ~ 191) 144
3542 22:14:31.975783 iDelay=192, Bit 15, Center 119 (48 ~ 191) 144
3543 22:14:31.975866 ==
3544 22:14:31.979315 Dram Type= 6, Freq= 0, CH_1, rank 1
3545 22:14:31.985774 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3546 22:14:31.985858 ==
3547 22:14:31.985923 DQS Delay:
3548 22:14:31.988750 DQS0 = 0, DQS1 = 0
3549 22:14:31.988832 DQM Delay:
3550 22:14:31.992109 DQM0 = 113, DQM1 = 111
3551 22:14:31.992191 DQ Delay:
3552 22:14:31.995888 DQ0 =111, DQ1 =111, DQ2 =103, DQ3 =115
3553 22:14:31.998827 DQ4 =111, DQ5 =123, DQ6 =119, DQ7 =111
3554 22:14:32.001939 DQ8 =103, DQ9 =95, DQ10 =111, DQ11 =103
3555 22:14:32.005318 DQ12 =115, DQ13 =123, DQ14 =119, DQ15 =119
3556 22:14:32.005401
3557 22:14:32.005467
3558 22:14:32.005527 ==
3559 22:14:32.008908 Dram Type= 6, Freq= 0, CH_1, rank 1
3560 22:14:32.015492 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3561 22:14:32.015575 ==
3562 22:14:32.015641
3563 22:14:32.015701
3564 22:14:32.015759 TX Vref Scan disable
3565 22:14:32.018536 == TX Byte 0 ==
3566 22:14:32.021891 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3567 22:14:32.028626 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3568 22:14:32.028709 == TX Byte 1 ==
3569 22:14:32.031960 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
3570 22:14:32.038724 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
3571 22:14:32.038808 ==
3572 22:14:32.041957 Dram Type= 6, Freq= 0, CH_1, rank 1
3573 22:14:32.045305 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3574 22:14:32.045389 ==
3575 22:14:32.057041 TX Vref=22, minBit 1, minWin=25, winSum=412
3576 22:14:32.059879 TX Vref=24, minBit 4, minWin=25, winSum=421
3577 22:14:32.063978 TX Vref=26, minBit 13, minWin=25, winSum=424
3578 22:14:32.066970 TX Vref=28, minBit 15, minWin=25, winSum=430
3579 22:14:32.070270 TX Vref=30, minBit 1, minWin=26, winSum=432
3580 22:14:32.076730 TX Vref=32, minBit 5, minWin=26, winSum=428
3581 22:14:32.079974 [TxChooseVref] Worse bit 1, Min win 26, Win sum 432, Final Vref 30
3582 22:14:32.080053
3583 22:14:32.083431 Final TX Range 1 Vref 30
3584 22:14:32.083507
3585 22:14:32.083587 ==
3586 22:14:32.086818 Dram Type= 6, Freq= 0, CH_1, rank 1
3587 22:14:32.090226 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3588 22:14:32.093200 ==
3589 22:14:32.093278
3590 22:14:32.093359
3591 22:14:32.093441 TX Vref Scan disable
3592 22:14:32.096794 == TX Byte 0 ==
3593 22:14:32.099939 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3594 22:14:32.106525 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3595 22:14:32.106605 == TX Byte 1 ==
3596 22:14:32.110413 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
3597 22:14:32.116524 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
3598 22:14:32.116608
3599 22:14:32.116698 [DATLAT]
3600 22:14:32.116776 Freq=1200, CH1 RK1
3601 22:14:32.116853
3602 22:14:32.120158 DATLAT Default: 0xd
3603 22:14:32.120235 0, 0xFFFF, sum = 0
3604 22:14:32.123142 1, 0xFFFF, sum = 0
3605 22:14:32.126486 2, 0xFFFF, sum = 0
3606 22:14:32.126589 3, 0xFFFF, sum = 0
3607 22:14:32.129827 4, 0xFFFF, sum = 0
3608 22:14:32.129934 5, 0xFFFF, sum = 0
3609 22:14:32.133086 6, 0xFFFF, sum = 0
3610 22:14:32.133169 7, 0xFFFF, sum = 0
3611 22:14:32.136610 8, 0xFFFF, sum = 0
3612 22:14:32.136693 9, 0xFFFF, sum = 0
3613 22:14:32.139772 10, 0xFFFF, sum = 0
3614 22:14:32.139888 11, 0xFFFF, sum = 0
3615 22:14:32.143303 12, 0x0, sum = 1
3616 22:14:32.143438 13, 0x0, sum = 2
3617 22:14:32.147096 14, 0x0, sum = 3
3618 22:14:32.147205 15, 0x0, sum = 4
3619 22:14:32.149550 best_step = 13
3620 22:14:32.149653
3621 22:14:32.149760 ==
3622 22:14:32.152933 Dram Type= 6, Freq= 0, CH_1, rank 1
3623 22:14:32.156465 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3624 22:14:32.156573 ==
3625 22:14:32.156671 RX Vref Scan: 0
3626 22:14:32.159334
3627 22:14:32.159462 RX Vref 0 -> 0, step: 1
3628 22:14:32.159547
3629 22:14:32.162949 RX Delay -21 -> 252, step: 4
3630 22:14:32.166298 iDelay=191, Bit 0, Center 114 (47 ~ 182) 136
3631 22:14:32.173184 iDelay=191, Bit 1, Center 108 (43 ~ 174) 132
3632 22:14:32.176058 iDelay=191, Bit 2, Center 104 (39 ~ 170) 132
3633 22:14:32.179670 iDelay=191, Bit 3, Center 112 (47 ~ 178) 132
3634 22:14:32.182985 iDelay=191, Bit 4, Center 116 (51 ~ 182) 132
3635 22:14:32.185903 iDelay=191, Bit 5, Center 124 (59 ~ 190) 132
3636 22:14:32.192805 iDelay=191, Bit 6, Center 122 (55 ~ 190) 136
3637 22:14:32.196526 iDelay=191, Bit 7, Center 110 (47 ~ 174) 128
3638 22:14:32.199318 iDelay=191, Bit 8, Center 98 (31 ~ 166) 136
3639 22:14:32.202762 iDelay=191, Bit 9, Center 98 (35 ~ 162) 128
3640 22:14:32.206305 iDelay=191, Bit 10, Center 110 (43 ~ 178) 136
3641 22:14:32.212964 iDelay=191, Bit 11, Center 102 (35 ~ 170) 136
3642 22:14:32.215818 iDelay=191, Bit 12, Center 114 (51 ~ 178) 128
3643 22:14:32.219200 iDelay=191, Bit 13, Center 118 (55 ~ 182) 128
3644 22:14:32.222888 iDelay=191, Bit 14, Center 116 (51 ~ 182) 132
3645 22:14:32.229398 iDelay=191, Bit 15, Center 118 (51 ~ 186) 136
3646 22:14:32.229481 ==
3647 22:14:32.232827 Dram Type= 6, Freq= 0, CH_1, rank 1
3648 22:14:32.236083 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3649 22:14:32.236166 ==
3650 22:14:32.236231 DQS Delay:
3651 22:14:32.239534 DQS0 = 0, DQS1 = 0
3652 22:14:32.239681 DQM Delay:
3653 22:14:32.242839 DQM0 = 113, DQM1 = 109
3654 22:14:32.242946 DQ Delay:
3655 22:14:32.245615 DQ0 =114, DQ1 =108, DQ2 =104, DQ3 =112
3656 22:14:32.248960 DQ4 =116, DQ5 =124, DQ6 =122, DQ7 =110
3657 22:14:32.252287 DQ8 =98, DQ9 =98, DQ10 =110, DQ11 =102
3658 22:14:32.255729 DQ12 =114, DQ13 =118, DQ14 =116, DQ15 =118
3659 22:14:32.255844
3660 22:14:32.255945
3661 22:14:32.265904 [DQSOSCAuto] RK1, (LSB)MR18= 0xf7fe, (MSB)MR19= 0x303, tDQSOscB0 = 410 ps tDQSOscB1 = 413 ps
3662 22:14:32.269282 CH1 RK1: MR19=303, MR18=F7FE
3663 22:14:32.272496 CH1_RK1: MR19=0x303, MR18=0xF7FE, DQSOSC=410, MR23=63, INC=39, DEC=26
3664 22:14:32.275884 [RxdqsGatingPostProcess] freq 1200
3665 22:14:32.282537 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3666 22:14:32.286054 best DQS0 dly(2T, 0.5T) = (0, 11)
3667 22:14:32.289548 best DQS1 dly(2T, 0.5T) = (0, 11)
3668 22:14:32.292169 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3669 22:14:32.295810 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3670 22:14:32.299203 best DQS0 dly(2T, 0.5T) = (0, 11)
3671 22:14:32.302256 best DQS1 dly(2T, 0.5T) = (0, 11)
3672 22:14:32.305723 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3673 22:14:32.309405 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3674 22:14:32.312977 Pre-setting of DQS Precalculation
3675 22:14:32.315670 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3676 22:14:32.322583 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3677 22:14:32.328861 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3678 22:14:32.328973
3679 22:14:32.332011
3680 22:14:32.332092 [Calibration Summary] 2400 Mbps
3681 22:14:32.335520 CH 0, Rank 0
3682 22:14:32.335622 SW Impedance : PASS
3683 22:14:32.339193 DUTY Scan : NO K
3684 22:14:32.342061 ZQ Calibration : PASS
3685 22:14:32.342145 Jitter Meter : NO K
3686 22:14:32.345754 CBT Training : PASS
3687 22:14:32.348953 Write leveling : PASS
3688 22:14:32.349045 RX DQS gating : PASS
3689 22:14:32.352038 RX DQ/DQS(RDDQC) : PASS
3690 22:14:32.355277 TX DQ/DQS : PASS
3691 22:14:32.355414 RX DATLAT : PASS
3692 22:14:32.358734 RX DQ/DQS(Engine): PASS
3693 22:14:32.358818 TX OE : NO K
3694 22:14:32.362118 All Pass.
3695 22:14:32.362222
3696 22:14:32.362324 CH 0, Rank 1
3697 22:14:32.365562 SW Impedance : PASS
3698 22:14:32.368419 DUTY Scan : NO K
3699 22:14:32.368494 ZQ Calibration : PASS
3700 22:14:32.371839 Jitter Meter : NO K
3701 22:14:32.371915 CBT Training : PASS
3702 22:14:32.375385 Write leveling : PASS
3703 22:14:32.378955 RX DQS gating : PASS
3704 22:14:32.379032 RX DQ/DQS(RDDQC) : PASS
3705 22:14:32.382006 TX DQ/DQS : PASS
3706 22:14:32.385256 RX DATLAT : PASS
3707 22:14:32.385330 RX DQ/DQS(Engine): PASS
3708 22:14:32.388826 TX OE : NO K
3709 22:14:32.388909 All Pass.
3710 22:14:32.388973
3711 22:14:32.391953 CH 1, Rank 0
3712 22:14:32.392051 SW Impedance : PASS
3713 22:14:32.395146 DUTY Scan : NO K
3714 22:14:32.398679 ZQ Calibration : PASS
3715 22:14:32.398752 Jitter Meter : NO K
3716 22:14:32.402122 CBT Training : PASS
3717 22:14:32.404959 Write leveling : PASS
3718 22:14:32.405035 RX DQS gating : PASS
3719 22:14:32.408657 RX DQ/DQS(RDDQC) : PASS
3720 22:14:32.412601 TX DQ/DQS : PASS
3721 22:14:32.412686 RX DATLAT : PASS
3722 22:14:32.415283 RX DQ/DQS(Engine): PASS
3723 22:14:32.418376 TX OE : NO K
3724 22:14:32.418459 All Pass.
3725 22:14:32.418523
3726 22:14:32.418631 CH 1, Rank 1
3727 22:14:32.421534 SW Impedance : PASS
3728 22:14:32.425075 DUTY Scan : NO K
3729 22:14:32.425164 ZQ Calibration : PASS
3730 22:14:32.428387 Jitter Meter : NO K
3731 22:14:32.428466 CBT Training : PASS
3732 22:14:32.432040 Write leveling : PASS
3733 22:14:32.434985 RX DQS gating : PASS
3734 22:14:32.435061 RX DQ/DQS(RDDQC) : PASS
3735 22:14:32.438665 TX DQ/DQS : PASS
3736 22:14:32.441887 RX DATLAT : PASS
3737 22:14:32.441963 RX DQ/DQS(Engine): PASS
3738 22:14:32.445080 TX OE : NO K
3739 22:14:32.445182 All Pass.
3740 22:14:32.445248
3741 22:14:32.447998 DramC Write-DBI off
3742 22:14:32.451381 PER_BANK_REFRESH: Hybrid Mode
3743 22:14:32.451476 TX_TRACKING: ON
3744 22:14:32.461447 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3745 22:14:32.464958 [FAST_K] Save calibration result to emmc
3746 22:14:32.468317 dramc_set_vcore_voltage set vcore to 650000
3747 22:14:32.471376 Read voltage for 600, 5
3748 22:14:32.471475 Vio18 = 0
3749 22:14:32.471539 Vcore = 650000
3750 22:14:32.474600 Vdram = 0
3751 22:14:32.474679 Vddq = 0
3752 22:14:32.474741 Vmddr = 0
3753 22:14:32.481232 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3754 22:14:32.484752 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3755 22:14:32.488363 MEM_TYPE=3, freq_sel=19
3756 22:14:32.491371 sv_algorithm_assistance_LP4_1600
3757 22:14:32.494754 ============ PULL DRAM RESETB DOWN ============
3758 22:14:32.498433 ========== PULL DRAM RESETB DOWN end =========
3759 22:14:32.504765 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3760 22:14:32.508228 ===================================
3761 22:14:32.508303 LPDDR4 DRAM CONFIGURATION
3762 22:14:32.511739 ===================================
3763 22:14:32.514812 EX_ROW_EN[0] = 0x0
3764 22:14:32.518221 EX_ROW_EN[1] = 0x0
3765 22:14:32.518298 LP4Y_EN = 0x0
3766 22:14:32.521568 WORK_FSP = 0x0
3767 22:14:32.521652 WL = 0x2
3768 22:14:32.524741 RL = 0x2
3769 22:14:32.524823 BL = 0x2
3770 22:14:32.528012 RPST = 0x0
3771 22:14:32.528091 RD_PRE = 0x0
3772 22:14:32.531571 WR_PRE = 0x1
3773 22:14:32.531645 WR_PST = 0x0
3774 22:14:32.535127 DBI_WR = 0x0
3775 22:14:32.535229 DBI_RD = 0x0
3776 22:14:32.538034 OTF = 0x1
3777 22:14:32.541543 ===================================
3778 22:14:32.544881 ===================================
3779 22:14:32.544956 ANA top config
3780 22:14:32.548066 ===================================
3781 22:14:32.551757 DLL_ASYNC_EN = 0
3782 22:14:32.554468 ALL_SLAVE_EN = 1
3783 22:14:32.557872 NEW_RANK_MODE = 1
3784 22:14:32.557948 DLL_IDLE_MODE = 1
3785 22:14:32.561637 LP45_APHY_COMB_EN = 1
3786 22:14:32.564368 TX_ODT_DIS = 1
3787 22:14:32.567768 NEW_8X_MODE = 1
3788 22:14:32.571010 ===================================
3789 22:14:32.574472 ===================================
3790 22:14:32.577955 data_rate = 1200
3791 22:14:32.578030 CKR = 1
3792 22:14:32.581314 DQ_P2S_RATIO = 8
3793 22:14:32.584372 ===================================
3794 22:14:32.587771 CA_P2S_RATIO = 8
3795 22:14:32.591026 DQ_CA_OPEN = 0
3796 22:14:32.594022 DQ_SEMI_OPEN = 0
3797 22:14:32.597564 CA_SEMI_OPEN = 0
3798 22:14:32.597639 CA_FULL_RATE = 0
3799 22:14:32.601016 DQ_CKDIV4_EN = 1
3800 22:14:32.604119 CA_CKDIV4_EN = 1
3801 22:14:32.607497 CA_PREDIV_EN = 0
3802 22:14:32.610993 PH8_DLY = 0
3803 22:14:32.613910 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3804 22:14:32.613984 DQ_AAMCK_DIV = 4
3805 22:14:32.617336 CA_AAMCK_DIV = 4
3806 22:14:32.621234 CA_ADMCK_DIV = 4
3807 22:14:32.624519 DQ_TRACK_CA_EN = 0
3808 22:14:32.627444 CA_PICK = 600
3809 22:14:32.630842 CA_MCKIO = 600
3810 22:14:32.634323 MCKIO_SEMI = 0
3811 22:14:32.634405 PLL_FREQ = 2288
3812 22:14:32.637161 DQ_UI_PI_RATIO = 32
3813 22:14:32.640762 CA_UI_PI_RATIO = 0
3814 22:14:32.644312 ===================================
3815 22:14:32.647213 ===================================
3816 22:14:32.650532 memory_type:LPDDR4
3817 22:14:32.650614 GP_NUM : 10
3818 22:14:32.653921 SRAM_EN : 1
3819 22:14:32.657307 MD32_EN : 0
3820 22:14:32.660589 ===================================
3821 22:14:32.660675 [ANA_INIT] >>>>>>>>>>>>>>
3822 22:14:32.663985 <<<<<< [CONFIGURE PHASE]: ANA_TX
3823 22:14:32.667225 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3824 22:14:32.670603 ===================================
3825 22:14:32.674083 data_rate = 1200,PCW = 0X5800
3826 22:14:32.677110 ===================================
3827 22:14:32.680384 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3828 22:14:32.686850 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3829 22:14:32.690405 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3830 22:14:32.696918 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3831 22:14:32.700598 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3832 22:14:32.703590 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3833 22:14:32.706972 [ANA_INIT] flow start
3834 22:14:32.707054 [ANA_INIT] PLL >>>>>>>>
3835 22:14:32.709854 [ANA_INIT] PLL <<<<<<<<
3836 22:14:32.713473 [ANA_INIT] MIDPI >>>>>>>>
3837 22:14:32.713553 [ANA_INIT] MIDPI <<<<<<<<
3838 22:14:32.716901 [ANA_INIT] DLL >>>>>>>>
3839 22:14:32.719955 [ANA_INIT] flow end
3840 22:14:32.723595 ============ LP4 DIFF to SE enter ============
3841 22:14:32.727071 ============ LP4 DIFF to SE exit ============
3842 22:14:32.730092 [ANA_INIT] <<<<<<<<<<<<<
3843 22:14:32.733574 [Flow] Enable top DCM control >>>>>
3844 22:14:32.736970 [Flow] Enable top DCM control <<<<<
3845 22:14:32.739862 Enable DLL master slave shuffle
3846 22:14:32.743471 ==============================================================
3847 22:14:32.746926 Gating Mode config
3848 22:14:32.753553 ==============================================================
3849 22:14:32.753638 Config description:
3850 22:14:32.763515 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3851 22:14:32.769943 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3852 22:14:32.773389 SELPH_MODE 0: By rank 1: By Phase
3853 22:14:32.780065 ==============================================================
3854 22:14:32.783376 GAT_TRACK_EN = 1
3855 22:14:32.786334 RX_GATING_MODE = 2
3856 22:14:32.789747 RX_GATING_TRACK_MODE = 2
3857 22:14:32.793369 SELPH_MODE = 1
3858 22:14:32.796394 PICG_EARLY_EN = 1
3859 22:14:32.799977 VALID_LAT_VALUE = 1
3860 22:14:32.803738 ==============================================================
3861 22:14:32.806513 Enter into Gating configuration >>>>
3862 22:14:32.810006 Exit from Gating configuration <<<<
3863 22:14:32.813024 Enter into DVFS_PRE_config >>>>>
3864 22:14:32.826639 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3865 22:14:32.826724 Exit from DVFS_PRE_config <<<<<
3866 22:14:32.829632 Enter into PICG configuration >>>>
3867 22:14:32.833165 Exit from PICG configuration <<<<
3868 22:14:32.836194 [RX_INPUT] configuration >>>>>
3869 22:14:32.839755 [RX_INPUT] configuration <<<<<
3870 22:14:32.846171 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3871 22:14:32.849406 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3872 22:14:32.856644 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3873 22:14:32.863015 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3874 22:14:32.869966 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3875 22:14:32.876661 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3876 22:14:32.879864 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3877 22:14:32.883179 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3878 22:14:32.886757 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3879 22:14:32.893270 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3880 22:14:32.896833 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3881 22:14:32.899806 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3882 22:14:32.903110 ===================================
3883 22:14:32.906485 LPDDR4 DRAM CONFIGURATION
3884 22:14:32.909415 ===================================
3885 22:14:32.909499 EX_ROW_EN[0] = 0x0
3886 22:14:32.912949 EX_ROW_EN[1] = 0x0
3887 22:14:32.916478 LP4Y_EN = 0x0
3888 22:14:32.916561 WORK_FSP = 0x0
3889 22:14:32.919908 WL = 0x2
3890 22:14:32.919992 RL = 0x2
3891 22:14:32.923385 BL = 0x2
3892 22:14:32.923481 RPST = 0x0
3893 22:14:32.926197 RD_PRE = 0x0
3894 22:14:32.926280 WR_PRE = 0x1
3895 22:14:32.929410 WR_PST = 0x0
3896 22:14:32.929492 DBI_WR = 0x0
3897 22:14:32.932907 DBI_RD = 0x0
3898 22:14:32.933005 OTF = 0x1
3899 22:14:32.936148 ===================================
3900 22:14:32.939408 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3901 22:14:32.946007 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3902 22:14:32.949387 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3903 22:14:32.952407 ===================================
3904 22:14:32.956530 LPDDR4 DRAM CONFIGURATION
3905 22:14:32.959171 ===================================
3906 22:14:32.959254 EX_ROW_EN[0] = 0x10
3907 22:14:32.962527 EX_ROW_EN[1] = 0x0
3908 22:14:32.962610 LP4Y_EN = 0x0
3909 22:14:32.965960 WORK_FSP = 0x0
3910 22:14:32.969239 WL = 0x2
3911 22:14:32.969321 RL = 0x2
3912 22:14:32.972558 BL = 0x2
3913 22:14:32.972663 RPST = 0x0
3914 22:14:32.975868 RD_PRE = 0x0
3915 22:14:32.975951 WR_PRE = 0x1
3916 22:14:32.979489 WR_PST = 0x0
3917 22:14:32.979572 DBI_WR = 0x0
3918 22:14:32.982502 DBI_RD = 0x0
3919 22:14:32.982585 OTF = 0x1
3920 22:14:32.986125 ===================================
3921 22:14:32.992165 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3922 22:14:32.996299 nWR fixed to 30
3923 22:14:33.000029 [ModeRegInit_LP4] CH0 RK0
3924 22:14:33.000111 [ModeRegInit_LP4] CH0 RK1
3925 22:14:33.002963 [ModeRegInit_LP4] CH1 RK0
3926 22:14:33.006388 [ModeRegInit_LP4] CH1 RK1
3927 22:14:33.006487 match AC timing 17
3928 22:14:33.012968 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3929 22:14:33.016883 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3930 22:14:33.019556 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3931 22:14:33.026447 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3932 22:14:33.029990 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3933 22:14:33.030105 ==
3934 22:14:33.032948 Dram Type= 6, Freq= 0, CH_0, rank 0
3935 22:14:33.036484 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3936 22:14:33.036568 ==
3937 22:14:33.043318 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3938 22:14:33.049545 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3939 22:14:33.052966 [CA 0] Center 36 (6~67) winsize 62
3940 22:14:33.055987 [CA 1] Center 35 (5~66) winsize 62
3941 22:14:33.059390 [CA 2] Center 34 (4~65) winsize 62
3942 22:14:33.062963 [CA 3] Center 34 (4~64) winsize 61
3943 22:14:33.066294 [CA 4] Center 33 (3~64) winsize 62
3944 22:14:33.069437 [CA 5] Center 33 (3~64) winsize 62
3945 22:14:33.069520
3946 22:14:33.073225 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3947 22:14:33.073323
3948 22:14:33.076097 [CATrainingPosCal] consider 1 rank data
3949 22:14:33.079610 u2DelayCellTimex100 = 270/100 ps
3950 22:14:33.082840 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3951 22:14:33.086074 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3952 22:14:33.089646 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3953 22:14:33.093420 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
3954 22:14:33.095832 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3955 22:14:33.102716 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3956 22:14:33.102799
3957 22:14:33.106163 CA PerBit enable=1, Macro0, CA PI delay=33
3958 22:14:33.106246
3959 22:14:33.108960 [CBTSetCACLKResult] CA Dly = 33
3960 22:14:33.109043 CS Dly: 4 (0~35)
3961 22:14:33.109108 ==
3962 22:14:33.112445 Dram Type= 6, Freq= 0, CH_0, rank 1
3963 22:14:33.115874 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3964 22:14:33.119494 ==
3965 22:14:33.122531 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3966 22:14:33.129121 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3967 22:14:33.132551 [CA 0] Center 36 (6~66) winsize 61
3968 22:14:33.135596 [CA 1] Center 36 (6~66) winsize 61
3969 22:14:33.139161 [CA 2] Center 34 (4~65) winsize 62
3970 22:14:33.142067 [CA 3] Center 34 (4~65) winsize 62
3971 22:14:33.145601 [CA 4] Center 33 (3~64) winsize 62
3972 22:14:33.149032 [CA 5] Center 33 (3~64) winsize 62
3973 22:14:33.149114
3974 22:14:33.152349 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3975 22:14:33.152431
3976 22:14:33.155164 [CATrainingPosCal] consider 2 rank data
3977 22:14:33.159503 u2DelayCellTimex100 = 270/100 ps
3978 22:14:33.162042 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3979 22:14:33.165448 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3980 22:14:33.168461 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3981 22:14:33.175331 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
3982 22:14:33.179010 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3983 22:14:33.182528 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3984 22:14:33.182610
3985 22:14:33.185232 CA PerBit enable=1, Macro0, CA PI delay=33
3986 22:14:33.185314
3987 22:14:33.188644 [CBTSetCACLKResult] CA Dly = 33
3988 22:14:33.188727 CS Dly: 4 (0~35)
3989 22:14:33.188792
3990 22:14:33.191792 ----->DramcWriteLeveling(PI) begin...
3991 22:14:33.191876 ==
3992 22:14:33.195292 Dram Type= 6, Freq= 0, CH_0, rank 0
3993 22:14:33.201900 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3994 22:14:33.201981 ==
3995 22:14:33.205581 Write leveling (Byte 0): 33 => 33
3996 22:14:33.209217 Write leveling (Byte 1): 29 => 29
3997 22:14:33.209300 DramcWriteLeveling(PI) end<-----
3998 22:14:33.209367
3999 22:14:33.212157 ==
4000 22:14:33.215131 Dram Type= 6, Freq= 0, CH_0, rank 0
4001 22:14:33.218628 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4002 22:14:33.218733 ==
4003 22:14:33.222273 [Gating] SW mode calibration
4004 22:14:33.229795 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4005 22:14:33.232230 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4006 22:14:33.238643 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4007 22:14:33.241737 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4008 22:14:33.245338 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4009 22:14:33.251758 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4010 22:14:33.255037 0 9 16 | B1->B0 | 3131 2929 | 1 0 | (1 0) (0 0)
4011 22:14:33.258191 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4012 22:14:33.265213 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4013 22:14:33.268330 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4014 22:14:33.271951 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4015 22:14:33.278732 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4016 22:14:33.281705 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4017 22:14:33.285095 0 10 12 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4018 22:14:33.291875 0 10 16 | B1->B0 | 3030 3f3f | 0 0 | (0 0) (0 0)
4019 22:14:33.295532 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4020 22:14:33.298516 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4021 22:14:33.305248 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4022 22:14:33.308052 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4023 22:14:33.311687 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4024 22:14:33.318726 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4025 22:14:33.321743 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4026 22:14:33.324707 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4027 22:14:33.328689 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4028 22:14:33.335307 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4029 22:14:33.338276 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4030 22:14:33.341875 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4031 22:14:33.348344 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4032 22:14:33.351308 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4033 22:14:33.354612 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4034 22:14:33.361226 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4035 22:14:33.364998 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4036 22:14:33.368034 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4037 22:14:33.374472 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4038 22:14:33.377761 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4039 22:14:33.381051 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4040 22:14:33.387595 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4041 22:14:33.391083 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4042 22:14:33.394485 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4043 22:14:33.397886 Total UI for P1: 0, mck2ui 16
4044 22:14:33.401089 best dqsien dly found for B1: ( 0, 13, 14)
4045 22:14:33.407836 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4046 22:14:33.407947 Total UI for P1: 0, mck2ui 16
4047 22:14:33.414184 best dqsien dly found for B0: ( 0, 13, 14)
4048 22:14:33.417827 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4049 22:14:33.421224 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4050 22:14:33.421339
4051 22:14:33.424264 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4052 22:14:33.428031 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4053 22:14:33.431422 [Gating] SW calibration Done
4054 22:14:33.431535 ==
4055 22:14:33.434522 Dram Type= 6, Freq= 0, CH_0, rank 0
4056 22:14:33.437652 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4057 22:14:33.437767 ==
4058 22:14:33.441251 RX Vref Scan: 0
4059 22:14:33.441363
4060 22:14:33.441475 RX Vref 0 -> 0, step: 1
4061 22:14:33.441570
4062 22:14:33.444251 RX Delay -230 -> 252, step: 16
4063 22:14:33.450790 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4064 22:14:33.454408 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4065 22:14:33.458208 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4066 22:14:33.461071 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4067 22:14:33.464530 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4068 22:14:33.470907 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4069 22:14:33.474265 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4070 22:14:33.477830 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4071 22:14:33.480625 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4072 22:14:33.487863 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4073 22:14:33.490986 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4074 22:14:33.494230 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4075 22:14:33.497383 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4076 22:14:33.504308 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4077 22:14:33.507613 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4078 22:14:33.511060 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4079 22:14:33.511137 ==
4080 22:14:33.514360 Dram Type= 6, Freq= 0, CH_0, rank 0
4081 22:14:33.517431 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4082 22:14:33.517546 ==
4083 22:14:33.520726 DQS Delay:
4084 22:14:33.520811 DQS0 = 0, DQS1 = 0
4085 22:14:33.524072 DQM Delay:
4086 22:14:33.524158 DQM0 = 41, DQM1 = 31
4087 22:14:33.524226 DQ Delay:
4088 22:14:33.527274 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =41
4089 22:14:33.530664 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4090 22:14:33.534059 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4091 22:14:33.537124 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =41
4092 22:14:33.537230
4093 22:14:33.537328
4094 22:14:33.540500 ==
4095 22:14:33.540610 Dram Type= 6, Freq= 0, CH_0, rank 0
4096 22:14:33.547083 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4097 22:14:33.547186 ==
4098 22:14:33.547292
4099 22:14:33.547414
4100 22:14:33.550612 TX Vref Scan disable
4101 22:14:33.550687 == TX Byte 0 ==
4102 22:14:33.553641 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4103 22:14:33.560803 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4104 22:14:33.560905 == TX Byte 1 ==
4105 22:14:33.563800 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4106 22:14:33.570361 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4107 22:14:33.570438 ==
4108 22:14:33.573684 Dram Type= 6, Freq= 0, CH_0, rank 0
4109 22:14:33.577531 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4110 22:14:33.577609 ==
4111 22:14:33.577675
4112 22:14:33.577734
4113 22:14:33.580520 TX Vref Scan disable
4114 22:14:33.584029 == TX Byte 0 ==
4115 22:14:33.587809 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4116 22:14:33.590797 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4117 22:14:33.593869 == TX Byte 1 ==
4118 22:14:33.597111 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4119 22:14:33.600681 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4120 22:14:33.600768
4121 22:14:33.604076 [DATLAT]
4122 22:14:33.604179 Freq=600, CH0 RK0
4123 22:14:33.604277
4124 22:14:33.607167 DATLAT Default: 0x9
4125 22:14:33.607252 0, 0xFFFF, sum = 0
4126 22:14:33.610346 1, 0xFFFF, sum = 0
4127 22:14:33.610430 2, 0xFFFF, sum = 0
4128 22:14:33.614218 3, 0xFFFF, sum = 0
4129 22:14:33.614302 4, 0xFFFF, sum = 0
4130 22:14:33.617600 5, 0xFFFF, sum = 0
4131 22:14:33.617778 6, 0xFFFF, sum = 0
4132 22:14:33.620558 7, 0xFFFF, sum = 0
4133 22:14:33.620647 8, 0x0, sum = 1
4134 22:14:33.623965 9, 0x0, sum = 2
4135 22:14:33.624049 10, 0x0, sum = 3
4136 22:14:33.627473 11, 0x0, sum = 4
4137 22:14:33.627561 best_step = 9
4138 22:14:33.627652
4139 22:14:33.627735 ==
4140 22:14:33.630616 Dram Type= 6, Freq= 0, CH_0, rank 0
4141 22:14:33.634052 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4142 22:14:33.634157 ==
4143 22:14:33.637281 RX Vref Scan: 1
4144 22:14:33.637372
4145 22:14:33.640870 RX Vref 0 -> 0, step: 1
4146 22:14:33.640956
4147 22:14:33.641051 RX Delay -195 -> 252, step: 8
4148 22:14:33.644130
4149 22:14:33.644211 Set Vref, RX VrefLevel [Byte0]: 52
4150 22:14:33.647096 [Byte1]: 51
4151 22:14:33.651741
4152 22:14:33.651838 Final RX Vref Byte 0 = 52 to rank0
4153 22:14:33.655468 Final RX Vref Byte 1 = 51 to rank0
4154 22:14:33.658481 Final RX Vref Byte 0 = 52 to rank1
4155 22:14:33.662058 Final RX Vref Byte 1 = 51 to rank1==
4156 22:14:33.665128 Dram Type= 6, Freq= 0, CH_0, rank 0
4157 22:14:33.671921 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4158 22:14:33.672009 ==
4159 22:14:33.672105 DQS Delay:
4160 22:14:33.675449 DQS0 = 0, DQS1 = 0
4161 22:14:33.675538 DQM Delay:
4162 22:14:33.675627 DQM0 = 42, DQM1 = 33
4163 22:14:33.678714 DQ Delay:
4164 22:14:33.681964 DQ0 =44, DQ1 =44, DQ2 =36, DQ3 =40
4165 22:14:33.685267 DQ4 =44, DQ5 =32, DQ6 =52, DQ7 =44
4166 22:14:33.688791 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =28
4167 22:14:33.691762 DQ12 =40, DQ13 =36, DQ14 =44, DQ15 =44
4168 22:14:33.691854
4169 22:14:33.691949
4170 22:14:33.698390 [DQSOSCAuto] RK0, (LSB)MR18= 0x4423, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 396 ps
4171 22:14:33.701859 CH0 RK0: MR19=808, MR18=4423
4172 22:14:33.708361 CH0_RK0: MR19=0x808, MR18=0x4423, DQSOSC=396, MR23=63, INC=167, DEC=111
4173 22:14:33.708457
4174 22:14:33.711426 ----->DramcWriteLeveling(PI) begin...
4175 22:14:33.711517 ==
4176 22:14:33.714746 Dram Type= 6, Freq= 0, CH_0, rank 1
4177 22:14:33.718048 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4178 22:14:33.718141 ==
4179 22:14:33.721713 Write leveling (Byte 0): 31 => 31
4180 22:14:33.724866 Write leveling (Byte 1): 30 => 30
4181 22:14:33.728005 DramcWriteLeveling(PI) end<-----
4182 22:14:33.728096
4183 22:14:33.728186 ==
4184 22:14:33.731460 Dram Type= 6, Freq= 0, CH_0, rank 1
4185 22:14:33.734944 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4186 22:14:33.735028 ==
4187 22:14:33.738200 [Gating] SW mode calibration
4188 22:14:33.744830 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4189 22:14:33.751206 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4190 22:14:33.754852 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4191 22:14:33.761391 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4192 22:14:33.764427 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4193 22:14:33.768382 0 9 12 | B1->B0 | 3434 2e2e | 1 0 | (1 1) (1 0)
4194 22:14:33.774334 0 9 16 | B1->B0 | 2e2e 2424 | 1 0 | (0 1) (0 0)
4195 22:14:33.778036 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4196 22:14:33.781429 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4197 22:14:33.788242 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4198 22:14:33.791330 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4199 22:14:33.794525 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4200 22:14:33.797911 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4201 22:14:33.804936 0 10 12 | B1->B0 | 2323 3838 | 0 1 | (0 0) (0 0)
4202 22:14:33.808274 0 10 16 | B1->B0 | 3434 4646 | 0 0 | (0 0) (0 0)
4203 22:14:33.811140 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4204 22:14:33.817751 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4205 22:14:33.821228 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4206 22:14:33.825109 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4207 22:14:33.831385 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4208 22:14:33.835027 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4209 22:14:33.837874 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4210 22:14:33.844628 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4211 22:14:33.848050 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4212 22:14:33.851027 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4213 22:14:33.858178 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4214 22:14:33.861158 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4215 22:14:33.864781 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4216 22:14:33.871165 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4217 22:14:33.874771 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4218 22:14:33.878314 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4219 22:14:33.884130 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4220 22:14:33.888132 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4221 22:14:33.891218 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4222 22:14:33.897679 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4223 22:14:33.900824 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4224 22:14:33.904191 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4225 22:14:33.910975 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4226 22:14:33.914518 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4227 22:14:33.917588 Total UI for P1: 0, mck2ui 16
4228 22:14:33.920967 best dqsien dly found for B0: ( 0, 13, 12)
4229 22:14:33.924150 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4230 22:14:33.927764 Total UI for P1: 0, mck2ui 16
4231 22:14:33.931121 best dqsien dly found for B1: ( 0, 13, 16)
4232 22:14:33.933991 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4233 22:14:33.937385 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4234 22:14:33.937468
4235 22:14:33.941623 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4236 22:14:33.947592 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4237 22:14:33.947716 [Gating] SW calibration Done
4238 22:14:33.947787 ==
4239 22:14:33.950998 Dram Type= 6, Freq= 0, CH_0, rank 1
4240 22:14:33.957629 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4241 22:14:33.957712 ==
4242 22:14:33.957779 RX Vref Scan: 0
4243 22:14:33.957840
4244 22:14:33.961133 RX Vref 0 -> 0, step: 1
4245 22:14:33.961215
4246 22:14:33.964053 RX Delay -230 -> 252, step: 16
4247 22:14:33.967787 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4248 22:14:33.971262 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4249 22:14:33.974098 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4250 22:14:33.981242 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4251 22:14:33.984226 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4252 22:14:33.987723 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4253 22:14:33.991377 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4254 22:14:33.997302 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4255 22:14:34.000501 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4256 22:14:34.003782 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4257 22:14:34.007515 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4258 22:14:34.010940 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4259 22:14:34.017502 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4260 22:14:34.020594 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4261 22:14:34.023804 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4262 22:14:34.027216 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4263 22:14:34.030719 ==
4264 22:14:34.034047 Dram Type= 6, Freq= 0, CH_0, rank 1
4265 22:14:34.037500 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4266 22:14:34.037583 ==
4267 22:14:34.037649 DQS Delay:
4268 22:14:34.040677 DQS0 = 0, DQS1 = 0
4269 22:14:34.040759 DQM Delay:
4270 22:14:34.044114 DQM0 = 40, DQM1 = 32
4271 22:14:34.044196 DQ Delay:
4272 22:14:34.046995 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =33
4273 22:14:34.050256 DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49
4274 22:14:34.053905 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4275 22:14:34.056782 DQ12 =33, DQ13 =41, DQ14 =49, DQ15 =41
4276 22:14:34.056864
4277 22:14:34.056929
4278 22:14:34.056989 ==
4279 22:14:34.060225 Dram Type= 6, Freq= 0, CH_0, rank 1
4280 22:14:34.063997 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4281 22:14:34.064080 ==
4282 22:14:34.064145
4283 22:14:34.064206
4284 22:14:34.066801 TX Vref Scan disable
4285 22:14:34.070369 == TX Byte 0 ==
4286 22:14:34.073847 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4287 22:14:34.076902 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4288 22:14:34.080297 == TX Byte 1 ==
4289 22:14:34.083863 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4290 22:14:34.086831 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4291 22:14:34.086914 ==
4292 22:14:34.090228 Dram Type= 6, Freq= 0, CH_0, rank 1
4293 22:14:34.096789 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4294 22:14:34.096870 ==
4295 22:14:34.096934
4296 22:14:34.096993
4297 22:14:34.097050 TX Vref Scan disable
4298 22:14:34.101016 == TX Byte 0 ==
4299 22:14:34.104183 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4300 22:14:34.111269 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4301 22:14:34.111359 == TX Byte 1 ==
4302 22:14:34.114767 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4303 22:14:34.121061 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4304 22:14:34.121143
4305 22:14:34.121206 [DATLAT]
4306 22:14:34.121265 Freq=600, CH0 RK1
4307 22:14:34.121322
4308 22:14:34.124316 DATLAT Default: 0x9
4309 22:14:34.124411 0, 0xFFFF, sum = 0
4310 22:14:34.127648 1, 0xFFFF, sum = 0
4311 22:14:34.127729 2, 0xFFFF, sum = 0
4312 22:14:34.131126 3, 0xFFFF, sum = 0
4313 22:14:34.134339 4, 0xFFFF, sum = 0
4314 22:14:34.134423 5, 0xFFFF, sum = 0
4315 22:14:34.137517 6, 0xFFFF, sum = 0
4316 22:14:34.137598 7, 0xFFFF, sum = 0
4317 22:14:34.140960 8, 0x0, sum = 1
4318 22:14:34.141044 9, 0x0, sum = 2
4319 22:14:34.141110 10, 0x0, sum = 3
4320 22:14:34.144200 11, 0x0, sum = 4
4321 22:14:34.144284 best_step = 9
4322 22:14:34.144348
4323 22:14:34.144408 ==
4324 22:14:34.147407 Dram Type= 6, Freq= 0, CH_0, rank 1
4325 22:14:34.154401 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4326 22:14:34.154484 ==
4327 22:14:34.154550 RX Vref Scan: 0
4328 22:14:34.154610
4329 22:14:34.157352 RX Vref 0 -> 0, step: 1
4330 22:14:34.157434
4331 22:14:34.160953 RX Delay -195 -> 252, step: 8
4332 22:14:34.163933 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4333 22:14:34.170900 iDelay=205, Bit 1, Center 40 (-115 ~ 196) 312
4334 22:14:34.174611 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4335 22:14:34.178003 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4336 22:14:34.180949 iDelay=205, Bit 4, Center 40 (-107 ~ 188) 296
4337 22:14:34.184469 iDelay=205, Bit 5, Center 28 (-123 ~ 180) 304
4338 22:14:34.190605 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4339 22:14:34.194140 iDelay=205, Bit 7, Center 44 (-107 ~ 196) 304
4340 22:14:34.197656 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4341 22:14:34.200613 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4342 22:14:34.208076 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4343 22:14:34.210757 iDelay=205, Bit 11, Center 24 (-123 ~ 172) 296
4344 22:14:34.213947 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4345 22:14:34.217246 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4346 22:14:34.224336 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4347 22:14:34.227344 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4348 22:14:34.227435 ==
4349 22:14:34.230529 Dram Type= 6, Freq= 0, CH_0, rank 1
4350 22:14:34.233702 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4351 22:14:34.233786 ==
4352 22:14:34.237077 DQS Delay:
4353 22:14:34.237159 DQS0 = 0, DQS1 = 0
4354 22:14:34.237225 DQM Delay:
4355 22:14:34.240466 DQM0 = 39, DQM1 = 33
4356 22:14:34.240581 DQ Delay:
4357 22:14:34.243663 DQ0 =40, DQ1 =40, DQ2 =36, DQ3 =40
4358 22:14:34.247104 DQ4 =40, DQ5 =28, DQ6 =48, DQ7 =44
4359 22:14:34.250391 DQ8 =24, DQ9 =24, DQ10 =32, DQ11 =24
4360 22:14:34.253854 DQ12 =36, DQ13 =40, DQ14 =44, DQ15 =40
4361 22:14:34.253932
4362 22:14:34.253997
4363 22:14:34.264053 [DQSOSCAuto] RK1, (LSB)MR18= 0x492a, (MSB)MR19= 0x808, tDQSOscB0 = 401 ps tDQSOscB1 = 396 ps
4364 22:14:34.264134 CH0 RK1: MR19=808, MR18=492A
4365 22:14:34.270612 CH0_RK1: MR19=0x808, MR18=0x492A, DQSOSC=396, MR23=63, INC=167, DEC=111
4366 22:14:34.274135 [RxdqsGatingPostProcess] freq 600
4367 22:14:34.280636 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4368 22:14:34.283639 Pre-setting of DQS Precalculation
4369 22:14:34.287081 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4370 22:14:34.287188 ==
4371 22:14:34.290770 Dram Type= 6, Freq= 0, CH_1, rank 0
4372 22:14:34.297333 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4373 22:14:34.297439 ==
4374 22:14:34.300450 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4375 22:14:34.307012 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4376 22:14:34.310520 [CA 0] Center 35 (5~66) winsize 62
4377 22:14:34.313625 [CA 1] Center 35 (5~66) winsize 62
4378 22:14:34.317348 [CA 2] Center 34 (4~65) winsize 62
4379 22:14:34.320592 [CA 3] Center 33 (3~64) winsize 62
4380 22:14:34.323790 [CA 4] Center 34 (3~65) winsize 63
4381 22:14:34.327000 [CA 5] Center 33 (3~64) winsize 62
4382 22:14:34.327122
4383 22:14:34.330111 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4384 22:14:34.330219
4385 22:14:34.333846 [CATrainingPosCal] consider 1 rank data
4386 22:14:34.336966 u2DelayCellTimex100 = 270/100 ps
4387 22:14:34.340331 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4388 22:14:34.343524 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4389 22:14:34.347170 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4390 22:14:34.353649 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4391 22:14:34.356814 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4392 22:14:34.360368 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4393 22:14:34.360447
4394 22:14:34.363733 CA PerBit enable=1, Macro0, CA PI delay=33
4395 22:14:34.363822
4396 22:14:34.367088 [CBTSetCACLKResult] CA Dly = 33
4397 22:14:34.367164 CS Dly: 4 (0~35)
4398 22:14:34.367227 ==
4399 22:14:34.369983 Dram Type= 6, Freq= 0, CH_1, rank 1
4400 22:14:34.377024 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4401 22:14:34.377113 ==
4402 22:14:34.380110 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4403 22:14:34.387147 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4404 22:14:34.390261 [CA 0] Center 35 (5~66) winsize 62
4405 22:14:34.394018 [CA 1] Center 36 (6~66) winsize 61
4406 22:14:34.396831 [CA 2] Center 34 (3~65) winsize 63
4407 22:14:34.400314 [CA 3] Center 34 (3~65) winsize 63
4408 22:14:34.403869 [CA 4] Center 34 (3~65) winsize 63
4409 22:14:34.407086 [CA 5] Center 33 (3~64) winsize 62
4410 22:14:34.407161
4411 22:14:34.410339 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4412 22:14:34.410421
4413 22:14:34.413438 [CATrainingPosCal] consider 2 rank data
4414 22:14:34.416986 u2DelayCellTimex100 = 270/100 ps
4415 22:14:34.420156 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4416 22:14:34.426695 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4417 22:14:34.429736 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4418 22:14:34.433092 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4419 22:14:34.436931 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4420 22:14:34.439721 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4421 22:14:34.439818
4422 22:14:34.442922 CA PerBit enable=1, Macro0, CA PI delay=33
4423 22:14:34.443109
4424 22:14:34.446308 [CBTSetCACLKResult] CA Dly = 33
4425 22:14:34.446390 CS Dly: 4 (0~35)
4426 22:14:34.449563
4427 22:14:34.453089 ----->DramcWriteLeveling(PI) begin...
4428 22:14:34.453175 ==
4429 22:14:34.456476 Dram Type= 6, Freq= 0, CH_1, rank 0
4430 22:14:34.459674 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4431 22:14:34.459794 ==
4432 22:14:34.463105 Write leveling (Byte 0): 30 => 30
4433 22:14:34.466510 Write leveling (Byte 1): 32 => 32
4434 22:14:34.469803 DramcWriteLeveling(PI) end<-----
4435 22:14:34.469899
4436 22:14:34.469963 ==
4437 22:14:34.473403 Dram Type= 6, Freq= 0, CH_1, rank 0
4438 22:14:34.476210 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4439 22:14:34.476293 ==
4440 22:14:34.479666 [Gating] SW mode calibration
4441 22:14:34.486008 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4442 22:14:34.492690 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4443 22:14:34.496301 0 9 0 | B1->B0 | 3535 3434 | 1 1 | (0 0) (1 1)
4444 22:14:34.499253 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4445 22:14:34.506282 0 9 8 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
4446 22:14:34.509204 0 9 12 | B1->B0 | 3434 3333 | 1 1 | (0 0) (1 0)
4447 22:14:34.512658 0 9 16 | B1->B0 | 2727 2828 | 0 0 | (0 0) (0 0)
4448 22:14:34.519796 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4449 22:14:34.522479 0 9 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4450 22:14:34.525827 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4451 22:14:34.532979 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4452 22:14:34.535874 0 10 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4453 22:14:34.539909 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4454 22:14:34.542794 0 10 12 | B1->B0 | 2626 2c2c | 0 0 | (0 0) (0 0)
4455 22:14:34.549564 0 10 16 | B1->B0 | 3c3c 4040 | 0 0 | (0 0) (0 0)
4456 22:14:34.552765 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4457 22:14:34.556320 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4458 22:14:34.562396 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4459 22:14:34.565789 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4460 22:14:34.569276 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4461 22:14:34.576062 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4462 22:14:34.579531 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4463 22:14:34.582698 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4464 22:14:34.589089 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4465 22:14:34.592117 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4466 22:14:34.595542 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4467 22:14:34.602118 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4468 22:14:34.605661 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4469 22:14:34.609128 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4470 22:14:34.615557 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4471 22:14:34.619218 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4472 22:14:34.622086 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4473 22:14:34.628895 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4474 22:14:34.632105 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4475 22:14:34.635532 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4476 22:14:34.642165 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4477 22:14:34.645645 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4478 22:14:34.648986 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4479 22:14:34.655215 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4480 22:14:34.655343 Total UI for P1: 0, mck2ui 16
4481 22:14:34.661966 best dqsien dly found for B0: ( 0, 13, 12)
4482 22:14:34.662061 Total UI for P1: 0, mck2ui 16
4483 22:14:34.668548 best dqsien dly found for B1: ( 0, 13, 14)
4484 22:14:34.672140 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4485 22:14:34.675051 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4486 22:14:34.675143
4487 22:14:34.678518 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4488 22:14:34.681875 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4489 22:14:34.685072 [Gating] SW calibration Done
4490 22:14:34.685157 ==
4491 22:14:34.688729 Dram Type= 6, Freq= 0, CH_1, rank 0
4492 22:14:34.691640 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4493 22:14:34.691726 ==
4494 22:14:34.695181 RX Vref Scan: 0
4495 22:14:34.695265
4496 22:14:34.695333 RX Vref 0 -> 0, step: 1
4497 22:14:34.695402
4498 22:14:34.698761 RX Delay -230 -> 252, step: 16
4499 22:14:34.705561 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4500 22:14:34.708270 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4501 22:14:34.711634 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4502 22:14:34.715284 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4503 22:14:34.718221 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4504 22:14:34.724888 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4505 22:14:34.728306 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4506 22:14:34.731828 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4507 22:14:34.735095 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4508 22:14:34.738494 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4509 22:14:34.744812 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4510 22:14:34.748188 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4511 22:14:34.751917 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4512 22:14:34.754958 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4513 22:14:34.761546 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4514 22:14:34.765436 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4515 22:14:34.765516 ==
4516 22:14:34.768313 Dram Type= 6, Freq= 0, CH_1, rank 0
4517 22:14:34.771704 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4518 22:14:34.771796 ==
4519 22:14:34.775020 DQS Delay:
4520 22:14:34.775142 DQS0 = 0, DQS1 = 0
4521 22:14:34.777978 DQM Delay:
4522 22:14:34.778103 DQM0 = 44, DQM1 = 35
4523 22:14:34.778226 DQ Delay:
4524 22:14:34.781377 DQ0 =49, DQ1 =41, DQ2 =25, DQ3 =41
4525 22:14:34.784753 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4526 22:14:34.787846 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =33
4527 22:14:34.791346 DQ12 =49, DQ13 =41, DQ14 =41, DQ15 =41
4528 22:14:34.791442
4529 22:14:34.791516
4530 22:14:34.794756 ==
4531 22:14:34.794867 Dram Type= 6, Freq= 0, CH_1, rank 0
4532 22:14:34.801289 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4533 22:14:34.801386 ==
4534 22:14:34.801465
4535 22:14:34.801534
4536 22:14:34.804412 TX Vref Scan disable
4537 22:14:34.804500 == TX Byte 0 ==
4538 22:14:34.807917 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4539 22:14:34.815072 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4540 22:14:34.815194 == TX Byte 1 ==
4541 22:14:34.818309 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4542 22:14:34.824712 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4543 22:14:34.824796 ==
4544 22:14:34.828365 Dram Type= 6, Freq= 0, CH_1, rank 0
4545 22:14:34.831143 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4546 22:14:34.831242 ==
4547 22:14:34.831310
4548 22:14:34.831396
4549 22:14:34.834780 TX Vref Scan disable
4550 22:14:34.838272 == TX Byte 0 ==
4551 22:14:34.841114 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4552 22:14:34.844414 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4553 22:14:34.848205 == TX Byte 1 ==
4554 22:14:34.851105 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4555 22:14:34.854370 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4556 22:14:34.854455
4557 22:14:34.858324 [DATLAT]
4558 22:14:34.858409 Freq=600, CH1 RK0
4559 22:14:34.858478
4560 22:14:34.861074 DATLAT Default: 0x9
4561 22:14:34.861158 0, 0xFFFF, sum = 0
4562 22:14:34.864682 1, 0xFFFF, sum = 0
4563 22:14:34.864769 2, 0xFFFF, sum = 0
4564 22:14:34.867662 3, 0xFFFF, sum = 0
4565 22:14:34.867748 4, 0xFFFF, sum = 0
4566 22:14:34.870997 5, 0xFFFF, sum = 0
4567 22:14:34.871084 6, 0xFFFF, sum = 0
4568 22:14:34.874207 7, 0xFFFF, sum = 0
4569 22:14:34.874296 8, 0x0, sum = 1
4570 22:14:34.877529 9, 0x0, sum = 2
4571 22:14:34.877615 10, 0x0, sum = 3
4572 22:14:34.881061 11, 0x0, sum = 4
4573 22:14:34.881147 best_step = 9
4574 22:14:34.881214
4575 22:14:34.881274 ==
4576 22:14:34.884367 Dram Type= 6, Freq= 0, CH_1, rank 0
4577 22:14:34.887888 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4578 22:14:34.891222 ==
4579 22:14:34.891339 RX Vref Scan: 1
4580 22:14:34.891420
4581 22:14:34.894184 RX Vref 0 -> 0, step: 1
4582 22:14:34.894278
4583 22:14:34.894349 RX Delay -195 -> 252, step: 8
4584 22:14:34.897766
4585 22:14:34.897844 Set Vref, RX VrefLevel [Byte0]: 59
4586 22:14:34.901355 [Byte1]: 53
4587 22:14:34.905983
4588 22:14:34.906064 Final RX Vref Byte 0 = 59 to rank0
4589 22:14:34.909577 Final RX Vref Byte 1 = 53 to rank0
4590 22:14:34.912459 Final RX Vref Byte 0 = 59 to rank1
4591 22:14:34.915987 Final RX Vref Byte 1 = 53 to rank1==
4592 22:14:34.918957 Dram Type= 6, Freq= 0, CH_1, rank 0
4593 22:14:34.926374 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4594 22:14:34.926464 ==
4595 22:14:34.926533 DQS Delay:
4596 22:14:34.928954 DQS0 = 0, DQS1 = 0
4597 22:14:34.929039 DQM Delay:
4598 22:14:34.929105 DQM0 = 40, DQM1 = 33
4599 22:14:34.932392 DQ Delay:
4600 22:14:34.935383 DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =40
4601 22:14:34.939008 DQ4 =40, DQ5 =48, DQ6 =48, DQ7 =36
4602 22:14:34.942495 DQ8 =20, DQ9 =24, DQ10 =36, DQ11 =28
4603 22:14:34.945774 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4604 22:14:34.945856
4605 22:14:34.945931
4606 22:14:34.952543 [DQSOSCAuto] RK0, (LSB)MR18= 0x430a, (MSB)MR19= 0x808, tDQSOscB0 = 408 ps tDQSOscB1 = 397 ps
4607 22:14:34.956005 CH1 RK0: MR19=808, MR18=430A
4608 22:14:34.962512 CH1_RK0: MR19=0x808, MR18=0x430A, DQSOSC=397, MR23=63, INC=166, DEC=110
4609 22:14:34.962597
4610 22:14:34.965884 ----->DramcWriteLeveling(PI) begin...
4611 22:14:34.965962 ==
4612 22:14:34.969093 Dram Type= 6, Freq= 0, CH_1, rank 1
4613 22:14:34.972268 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4614 22:14:34.972352 ==
4615 22:14:34.975691 Write leveling (Byte 0): 31 => 31
4616 22:14:34.979062 Write leveling (Byte 1): 31 => 31
4617 22:14:34.982391 DramcWriteLeveling(PI) end<-----
4618 22:14:34.982468
4619 22:14:34.982533 ==
4620 22:14:34.985380 Dram Type= 6, Freq= 0, CH_1, rank 1
4621 22:14:34.989286 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4622 22:14:34.989373 ==
4623 22:14:34.992552 [Gating] SW mode calibration
4624 22:14:34.999252 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4625 22:14:35.005644 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4626 22:14:35.008763 0 9 0 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
4627 22:14:35.012577 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4628 22:14:35.018832 0 9 8 | B1->B0 | 3535 3434 | 1 1 | (0 0) (1 1)
4629 22:14:35.022261 0 9 12 | B1->B0 | 3030 2a2a | 1 1 | (1 0) (1 0)
4630 22:14:35.025206 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4631 22:14:35.032144 0 9 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4632 22:14:35.035552 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4633 22:14:35.038505 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4634 22:14:35.045749 0 10 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4635 22:14:35.049137 0 10 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4636 22:14:35.052128 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4637 22:14:35.058361 0 10 12 | B1->B0 | 2f2f 3b3b | 0 0 | (0 0) (0 0)
4638 22:14:35.062088 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4639 22:14:35.065586 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4640 22:14:35.071810 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4641 22:14:35.075187 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4642 22:14:35.078339 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4643 22:14:35.084894 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4644 22:14:35.088112 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4645 22:14:35.091568 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4646 22:14:35.098155 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4647 22:14:35.101683 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4648 22:14:35.105366 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4649 22:14:35.111873 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4650 22:14:35.114727 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4651 22:14:35.118169 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4652 22:14:35.124604 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4653 22:14:35.128603 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4654 22:14:35.131532 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4655 22:14:35.138026 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4656 22:14:35.141589 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4657 22:14:35.144658 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4658 22:14:35.151759 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4659 22:14:35.155078 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4660 22:14:35.158612 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4661 22:14:35.161276 Total UI for P1: 0, mck2ui 16
4662 22:14:35.164524 best dqsien dly found for B0: ( 0, 13, 6)
4663 22:14:35.171659 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4664 22:14:35.171766 Total UI for P1: 0, mck2ui 16
4665 22:14:35.174548 best dqsien dly found for B1: ( 0, 13, 10)
4666 22:14:35.178352 best DQS0 dly(MCK, UI, PI) = (0, 13, 6)
4667 22:14:35.185057 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4668 22:14:35.185140
4669 22:14:35.187747 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 6)
4670 22:14:35.191233 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4671 22:14:35.194779 [Gating] SW calibration Done
4672 22:14:35.194864 ==
4673 22:14:35.198029 Dram Type= 6, Freq= 0, CH_1, rank 1
4674 22:14:35.201374 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4675 22:14:35.201453 ==
4676 22:14:35.204850 RX Vref Scan: 0
4677 22:14:35.204928
4678 22:14:35.204993 RX Vref 0 -> 0, step: 1
4679 22:14:35.205062
4680 22:14:35.207675 RX Delay -230 -> 252, step: 16
4681 22:14:35.211291 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4682 22:14:35.218361 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4683 22:14:35.221194 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4684 22:14:35.224769 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4685 22:14:35.228534 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4686 22:14:35.231135 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4687 22:14:35.237999 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4688 22:14:35.241378 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4689 22:14:35.244849 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4690 22:14:35.247787 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4691 22:14:35.254252 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4692 22:14:35.257942 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4693 22:14:35.260930 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4694 22:14:35.264204 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4695 22:14:35.271046 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4696 22:14:35.274557 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4697 22:14:35.274667 ==
4698 22:14:35.277909 Dram Type= 6, Freq= 0, CH_1, rank 1
4699 22:14:35.281311 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4700 22:14:35.281395 ==
4701 22:14:35.284125 DQS Delay:
4702 22:14:35.284208 DQS0 = 0, DQS1 = 0
4703 22:14:35.284274 DQM Delay:
4704 22:14:35.287490 DQM0 = 40, DQM1 = 34
4705 22:14:35.287573 DQ Delay:
4706 22:14:35.290914 DQ0 =41, DQ1 =33, DQ2 =25, DQ3 =41
4707 22:14:35.294193 DQ4 =41, DQ5 =57, DQ6 =49, DQ7 =33
4708 22:14:35.297775 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =33
4709 22:14:35.301147 DQ12 =41, DQ13 =49, DQ14 =41, DQ15 =41
4710 22:14:35.301243
4711 22:14:35.301338
4712 22:14:35.301413 ==
4713 22:14:35.304090 Dram Type= 6, Freq= 0, CH_1, rank 1
4714 22:14:35.311045 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4715 22:14:35.311129 ==
4716 22:14:35.311196
4717 22:14:35.311257
4718 22:14:35.311316 TX Vref Scan disable
4719 22:14:35.314451 == TX Byte 0 ==
4720 22:14:35.317489 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4721 22:14:35.321021 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4722 22:14:35.324532 == TX Byte 1 ==
4723 22:14:35.327861 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4724 22:14:35.334438 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4725 22:14:35.334516 ==
4726 22:14:35.337551 Dram Type= 6, Freq= 0, CH_1, rank 1
4727 22:14:35.341025 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4728 22:14:35.341111 ==
4729 22:14:35.341179
4730 22:14:35.341242
4731 22:14:35.344507 TX Vref Scan disable
4732 22:14:35.347206 == TX Byte 0 ==
4733 22:14:35.350591 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4734 22:14:35.354229 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4735 22:14:35.357308 == TX Byte 1 ==
4736 22:14:35.361234 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4737 22:14:35.364095 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4738 22:14:35.364180
4739 22:14:35.364247 [DATLAT]
4740 22:14:35.367281 Freq=600, CH1 RK1
4741 22:14:35.367395
4742 22:14:35.367465 DATLAT Default: 0x9
4743 22:14:35.370469 0, 0xFFFF, sum = 0
4744 22:14:35.373850 1, 0xFFFF, sum = 0
4745 22:14:35.373959 2, 0xFFFF, sum = 0
4746 22:14:35.377316 3, 0xFFFF, sum = 0
4747 22:14:35.377397 4, 0xFFFF, sum = 0
4748 22:14:35.381151 5, 0xFFFF, sum = 0
4749 22:14:35.381231 6, 0xFFFF, sum = 0
4750 22:14:35.384257 7, 0xFFFF, sum = 0
4751 22:14:35.384349 8, 0x0, sum = 1
4752 22:14:35.387602 9, 0x0, sum = 2
4753 22:14:35.387697 10, 0x0, sum = 3
4754 22:14:35.387763 11, 0x0, sum = 4
4755 22:14:35.390833 best_step = 9
4756 22:14:35.390935
4757 22:14:35.391035 ==
4758 22:14:35.393801 Dram Type= 6, Freq= 0, CH_1, rank 1
4759 22:14:35.397118 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4760 22:14:35.397221 ==
4761 22:14:35.400408 RX Vref Scan: 0
4762 22:14:35.400510
4763 22:14:35.400619 RX Vref 0 -> 0, step: 1
4764 22:14:35.400709
4765 22:14:35.404169 RX Delay -195 -> 252, step: 8
4766 22:14:35.411228 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4767 22:14:35.414683 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4768 22:14:35.418296 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4769 22:14:35.421294 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4770 22:14:35.427827 iDelay=205, Bit 4, Center 40 (-115 ~ 196) 312
4771 22:14:35.431539 iDelay=205, Bit 5, Center 52 (-99 ~ 204) 304
4772 22:14:35.434548 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4773 22:14:35.437961 iDelay=205, Bit 7, Center 36 (-115 ~ 188) 304
4774 22:14:35.441520 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4775 22:14:35.448014 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4776 22:14:35.451313 iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320
4777 22:14:35.454399 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4778 22:14:35.457940 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4779 22:14:35.464287 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4780 22:14:35.468461 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4781 22:14:35.471111 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4782 22:14:35.471229 ==
4783 22:14:35.474382 Dram Type= 6, Freq= 0, CH_1, rank 1
4784 22:14:35.477786 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4785 22:14:35.480888 ==
4786 22:14:35.480972 DQS Delay:
4787 22:14:35.481057 DQS0 = 0, DQS1 = 0
4788 22:14:35.484195 DQM Delay:
4789 22:14:35.484280 DQM0 = 38, DQM1 = 33
4790 22:14:35.487471 DQ Delay:
4791 22:14:35.490796 DQ0 =40, DQ1 =32, DQ2 =24, DQ3 =36
4792 22:14:35.490912 DQ4 =40, DQ5 =52, DQ6 =48, DQ7 =36
4793 22:14:35.494084 DQ8 =20, DQ9 =24, DQ10 =36, DQ11 =24
4794 22:14:35.500664 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4795 22:14:35.500747
4796 22:14:35.500812
4797 22:14:35.507362 [DQSOSCAuto] RK1, (LSB)MR18= 0x3b49, (MSB)MR19= 0x808, tDQSOscB0 = 396 ps tDQSOscB1 = 398 ps
4798 22:14:35.510796 CH1 RK1: MR19=808, MR18=3B49
4799 22:14:35.517511 CH1_RK1: MR19=0x808, MR18=0x3B49, DQSOSC=396, MR23=63, INC=167, DEC=111
4800 22:14:35.520491 [RxdqsGatingPostProcess] freq 600
4801 22:14:35.524035 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4802 22:14:35.527076 Pre-setting of DQS Precalculation
4803 22:14:35.534204 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4804 22:14:35.540533 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4805 22:14:35.547323 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4806 22:14:35.547450
4807 22:14:35.547561
4808 22:14:35.550297 [Calibration Summary] 1200 Mbps
4809 22:14:35.550412 CH 0, Rank 0
4810 22:14:35.553914 SW Impedance : PASS
4811 22:14:35.557605 DUTY Scan : NO K
4812 22:14:35.557685 ZQ Calibration : PASS
4813 22:14:35.560724 Jitter Meter : NO K
4814 22:14:35.563783 CBT Training : PASS
4815 22:14:35.563886 Write leveling : PASS
4816 22:14:35.567193 RX DQS gating : PASS
4817 22:14:35.570503 RX DQ/DQS(RDDQC) : PASS
4818 22:14:35.570588 TX DQ/DQS : PASS
4819 22:14:35.573848 RX DATLAT : PASS
4820 22:14:35.573933 RX DQ/DQS(Engine): PASS
4821 22:14:35.577020 TX OE : NO K
4822 22:14:35.577106 All Pass.
4823 22:14:35.577191
4824 22:14:35.580402 CH 0, Rank 1
4825 22:14:35.580486 SW Impedance : PASS
4826 22:14:35.583634 DUTY Scan : NO K
4827 22:14:35.586783 ZQ Calibration : PASS
4828 22:14:35.586868 Jitter Meter : NO K
4829 22:14:35.590341 CBT Training : PASS
4830 22:14:35.593819 Write leveling : PASS
4831 22:14:35.593904 RX DQS gating : PASS
4832 22:14:35.596663 RX DQ/DQS(RDDQC) : PASS
4833 22:14:35.600615 TX DQ/DQS : PASS
4834 22:14:35.600776 RX DATLAT : PASS
4835 22:14:35.603341 RX DQ/DQS(Engine): PASS
4836 22:14:35.607167 TX OE : NO K
4837 22:14:35.607253 All Pass.
4838 22:14:35.607321
4839 22:14:35.607412 CH 1, Rank 0
4840 22:14:35.609998 SW Impedance : PASS
4841 22:14:35.613442 DUTY Scan : NO K
4842 22:14:35.613574 ZQ Calibration : PASS
4843 22:14:35.616873 Jitter Meter : NO K
4844 22:14:35.619887 CBT Training : PASS
4845 22:14:35.620012 Write leveling : PASS
4846 22:14:35.623411 RX DQS gating : PASS
4847 22:14:35.626910 RX DQ/DQS(RDDQC) : PASS
4848 22:14:35.626995 TX DQ/DQS : PASS
4849 22:14:35.630309 RX DATLAT : PASS
4850 22:14:35.630468 RX DQ/DQS(Engine): PASS
4851 22:14:35.633550 TX OE : NO K
4852 22:14:35.633636 All Pass.
4853 22:14:35.633750
4854 22:14:35.636542 CH 1, Rank 1
4855 22:14:35.636651 SW Impedance : PASS
4856 22:14:35.640070 DUTY Scan : NO K
4857 22:14:35.643553 ZQ Calibration : PASS
4858 22:14:35.643638 Jitter Meter : NO K
4859 22:14:35.646544 CBT Training : PASS
4860 22:14:35.650004 Write leveling : PASS
4861 22:14:35.650089 RX DQS gating : PASS
4862 22:14:35.653430 RX DQ/DQS(RDDQC) : PASS
4863 22:14:35.656716 TX DQ/DQS : PASS
4864 22:14:35.656801 RX DATLAT : PASS
4865 22:14:35.659871 RX DQ/DQS(Engine): PASS
4866 22:14:35.663053 TX OE : NO K
4867 22:14:35.663139 All Pass.
4868 22:14:35.663206
4869 22:14:35.663269 DramC Write-DBI off
4870 22:14:35.666975 PER_BANK_REFRESH: Hybrid Mode
4871 22:14:35.669728 TX_TRACKING: ON
4872 22:14:35.676730 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4873 22:14:35.679916 [FAST_K] Save calibration result to emmc
4874 22:14:35.686528 dramc_set_vcore_voltage set vcore to 662500
4875 22:14:35.686613 Read voltage for 933, 3
4876 22:14:35.689810 Vio18 = 0
4877 22:14:35.689895 Vcore = 662500
4878 22:14:35.689963 Vdram = 0
4879 22:14:35.693113 Vddq = 0
4880 22:14:35.693198 Vmddr = 0
4881 22:14:35.696567 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4882 22:14:35.702726 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4883 22:14:35.706179 MEM_TYPE=3, freq_sel=17
4884 22:14:35.709616 sv_algorithm_assistance_LP4_1600
4885 22:14:35.712860 ============ PULL DRAM RESETB DOWN ============
4886 22:14:35.716412 ========== PULL DRAM RESETB DOWN end =========
4887 22:14:35.719275 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4888 22:14:35.722760 ===================================
4889 22:14:35.726394 LPDDR4 DRAM CONFIGURATION
4890 22:14:35.729384 ===================================
4891 22:14:35.732901 EX_ROW_EN[0] = 0x0
4892 22:14:35.732986 EX_ROW_EN[1] = 0x0
4893 22:14:35.735860 LP4Y_EN = 0x0
4894 22:14:35.735945 WORK_FSP = 0x0
4895 22:14:35.739419 WL = 0x3
4896 22:14:35.739519 RL = 0x3
4897 22:14:35.742946 BL = 0x2
4898 22:14:35.743029 RPST = 0x0
4899 22:14:35.745970 RD_PRE = 0x0
4900 22:14:35.749500 WR_PRE = 0x1
4901 22:14:35.749584 WR_PST = 0x0
4902 22:14:35.753239 DBI_WR = 0x0
4903 22:14:35.753365 DBI_RD = 0x0
4904 22:14:35.755782 OTF = 0x1
4905 22:14:35.759203 ===================================
4906 22:14:35.762795 ===================================
4907 22:14:35.762873 ANA top config
4908 22:14:35.765710 ===================================
4909 22:14:35.768903 DLL_ASYNC_EN = 0
4910 22:14:35.772586 ALL_SLAVE_EN = 1
4911 22:14:35.772663 NEW_RANK_MODE = 1
4912 22:14:35.775805 DLL_IDLE_MODE = 1
4913 22:14:35.779555 LP45_APHY_COMB_EN = 1
4914 22:14:35.782290 TX_ODT_DIS = 1
4915 22:14:35.782367 NEW_8X_MODE = 1
4916 22:14:35.785626 ===================================
4917 22:14:35.789504 ===================================
4918 22:14:35.792216 data_rate = 1866
4919 22:14:35.795747 CKR = 1
4920 22:14:35.799017 DQ_P2S_RATIO = 8
4921 22:14:35.802373 ===================================
4922 22:14:35.805776 CA_P2S_RATIO = 8
4923 22:14:35.809230 DQ_CA_OPEN = 0
4924 22:14:35.811991 DQ_SEMI_OPEN = 0
4925 22:14:35.812070 CA_SEMI_OPEN = 0
4926 22:14:35.815694 CA_FULL_RATE = 0
4927 22:14:35.818597 DQ_CKDIV4_EN = 1
4928 22:14:35.821938 CA_CKDIV4_EN = 1
4929 22:14:35.825342 CA_PREDIV_EN = 0
4930 22:14:35.825430 PH8_DLY = 0
4931 22:14:35.828794 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4932 22:14:35.832381 DQ_AAMCK_DIV = 4
4933 22:14:35.835378 CA_AAMCK_DIV = 4
4934 22:14:35.838865 CA_ADMCK_DIV = 4
4935 22:14:35.842445 DQ_TRACK_CA_EN = 0
4936 22:14:35.842545 CA_PICK = 933
4937 22:14:35.845440 CA_MCKIO = 933
4938 22:14:35.849014 MCKIO_SEMI = 0
4939 22:14:35.851934 PLL_FREQ = 3732
4940 22:14:35.855318 DQ_UI_PI_RATIO = 32
4941 22:14:35.858979 CA_UI_PI_RATIO = 0
4942 22:14:35.861906 ===================================
4943 22:14:35.865797 ===================================
4944 22:14:35.868847 memory_type:LPDDR4
4945 22:14:35.868941 GP_NUM : 10
4946 22:14:35.872221 SRAM_EN : 1
4947 22:14:35.872313 MD32_EN : 0
4948 22:14:35.875167 ===================================
4949 22:14:35.878620 [ANA_INIT] >>>>>>>>>>>>>>
4950 22:14:35.882261 <<<<<< [CONFIGURE PHASE]: ANA_TX
4951 22:14:35.885175 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4952 22:14:35.888516 ===================================
4953 22:14:35.891914 data_rate = 1866,PCW = 0X8f00
4954 22:14:35.895452 ===================================
4955 22:14:35.898826 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4956 22:14:35.902226 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4957 22:14:35.908541 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4958 22:14:35.911909 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4959 22:14:35.918452 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4960 22:14:35.922380 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4961 22:14:35.922493 [ANA_INIT] flow start
4962 22:14:35.925363 [ANA_INIT] PLL >>>>>>>>
4963 22:14:35.928821 [ANA_INIT] PLL <<<<<<<<
4964 22:14:35.928907 [ANA_INIT] MIDPI >>>>>>>>
4965 22:14:35.932269 [ANA_INIT] MIDPI <<<<<<<<
4966 22:14:35.935233 [ANA_INIT] DLL >>>>>>>>
4967 22:14:35.935321 [ANA_INIT] flow end
4968 22:14:35.938738 ============ LP4 DIFF to SE enter ============
4969 22:14:35.945163 ============ LP4 DIFF to SE exit ============
4970 22:14:35.945247 [ANA_INIT] <<<<<<<<<<<<<
4971 22:14:35.948782 [Flow] Enable top DCM control >>>>>
4972 22:14:35.951815 [Flow] Enable top DCM control <<<<<
4973 22:14:35.955267 Enable DLL master slave shuffle
4974 22:14:35.962062 ==============================================================
4975 22:14:35.962197 Gating Mode config
4976 22:14:35.968658 ==============================================================
4977 22:14:35.971909 Config description:
4978 22:14:35.981909 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4979 22:14:35.988490 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4980 22:14:35.992763 SELPH_MODE 0: By rank 1: By Phase
4981 22:14:35.999261 ==============================================================
4982 22:14:36.002352 GAT_TRACK_EN = 1
4983 22:14:36.002435 RX_GATING_MODE = 2
4984 22:14:36.005205 RX_GATING_TRACK_MODE = 2
4985 22:14:36.008646 SELPH_MODE = 1
4986 22:14:36.012016 PICG_EARLY_EN = 1
4987 22:14:36.015238 VALID_LAT_VALUE = 1
4988 22:14:36.021758 ==============================================================
4989 22:14:36.025178 Enter into Gating configuration >>>>
4990 22:14:36.028501 Exit from Gating configuration <<<<
4991 22:14:36.032053 Enter into DVFS_PRE_config >>>>>
4992 22:14:36.041964 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4993 22:14:36.044932 Exit from DVFS_PRE_config <<<<<
4994 22:14:36.048528 Enter into PICG configuration >>>>
4995 22:14:36.051456 Exit from PICG configuration <<<<
4996 22:14:36.055053 [RX_INPUT] configuration >>>>>
4997 22:14:36.058222 [RX_INPUT] configuration <<<<<
4998 22:14:36.062073 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4999 22:14:36.068401 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5000 22:14:36.075334 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5001 22:14:36.078464 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5002 22:14:36.084835 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5003 22:14:36.091235 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5004 22:14:36.094751 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5005 22:14:36.101732 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5006 22:14:36.104590 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5007 22:14:36.107834 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5008 22:14:36.111458 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5009 22:14:36.117748 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5010 22:14:36.121502 ===================================
5011 22:14:36.121582 LPDDR4 DRAM CONFIGURATION
5012 22:14:36.124688 ===================================
5013 22:14:36.128125 EX_ROW_EN[0] = 0x0
5014 22:14:36.131068 EX_ROW_EN[1] = 0x0
5015 22:14:36.131170 LP4Y_EN = 0x0
5016 22:14:36.134525 WORK_FSP = 0x0
5017 22:14:36.134625 WL = 0x3
5018 22:14:36.137907 RL = 0x3
5019 22:14:36.137982 BL = 0x2
5020 22:14:36.141244 RPST = 0x0
5021 22:14:36.141325 RD_PRE = 0x0
5022 22:14:36.144315 WR_PRE = 0x1
5023 22:14:36.144390 WR_PST = 0x0
5024 22:14:36.147940 DBI_WR = 0x0
5025 22:14:36.148012 DBI_RD = 0x0
5026 22:14:36.151281 OTF = 0x1
5027 22:14:36.155081 ===================================
5028 22:14:36.157768 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5029 22:14:36.161492 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5030 22:14:36.168044 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5031 22:14:36.170967 ===================================
5032 22:14:36.171074 LPDDR4 DRAM CONFIGURATION
5033 22:14:36.174667 ===================================
5034 22:14:36.177830 EX_ROW_EN[0] = 0x10
5035 22:14:36.177932 EX_ROW_EN[1] = 0x0
5036 22:14:36.181379 LP4Y_EN = 0x0
5037 22:14:36.184320 WORK_FSP = 0x0
5038 22:14:36.184392 WL = 0x3
5039 22:14:36.187771 RL = 0x3
5040 22:14:36.187844 BL = 0x2
5041 22:14:36.190858 RPST = 0x0
5042 22:14:36.190955 RD_PRE = 0x0
5043 22:14:36.194287 WR_PRE = 0x1
5044 22:14:36.194385 WR_PST = 0x0
5045 22:14:36.197918 DBI_WR = 0x0
5046 22:14:36.198018 DBI_RD = 0x0
5047 22:14:36.201093 OTF = 0x1
5048 22:14:36.204252 ===================================
5049 22:14:36.210642 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5050 22:14:36.214290 nWR fixed to 30
5051 22:14:36.214395 [ModeRegInit_LP4] CH0 RK0
5052 22:14:36.217375 [ModeRegInit_LP4] CH0 RK1
5053 22:14:36.221325 [ModeRegInit_LP4] CH1 RK0
5054 22:14:36.221403 [ModeRegInit_LP4] CH1 RK1
5055 22:14:36.224168 match AC timing 9
5056 22:14:36.227558 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5057 22:14:36.231205 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5058 22:14:36.238458 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5059 22:14:36.240982 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5060 22:14:36.247475 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5061 22:14:36.247564 ==
5062 22:14:36.251313 Dram Type= 6, Freq= 0, CH_0, rank 0
5063 22:14:36.254124 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5064 22:14:36.254202 ==
5065 22:14:36.260912 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5066 22:14:36.263859 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5067 22:14:36.268626 [CA 0] Center 38 (8~69) winsize 62
5068 22:14:36.271574 [CA 1] Center 38 (8~69) winsize 62
5069 22:14:36.275177 [CA 2] Center 35 (5~66) winsize 62
5070 22:14:36.278158 [CA 3] Center 35 (5~65) winsize 61
5071 22:14:36.281434 [CA 4] Center 34 (4~65) winsize 62
5072 22:14:36.285137 [CA 5] Center 34 (4~64) winsize 61
5073 22:14:36.285215
5074 22:14:36.288600 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5075 22:14:36.288675
5076 22:14:36.291461 [CATrainingPosCal] consider 1 rank data
5077 22:14:36.294970 u2DelayCellTimex100 = 270/100 ps
5078 22:14:36.298564 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5079 22:14:36.302006 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5080 22:14:36.308613 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5081 22:14:36.311963 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5082 22:14:36.315284 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5083 22:14:36.318711 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5084 22:14:36.318796
5085 22:14:36.322076 CA PerBit enable=1, Macro0, CA PI delay=34
5086 22:14:36.322189
5087 22:14:36.324746 [CBTSetCACLKResult] CA Dly = 34
5088 22:14:36.324858 CS Dly: 6 (0~37)
5089 22:14:36.328457 ==
5090 22:14:36.328543 Dram Type= 6, Freq= 0, CH_0, rank 1
5091 22:14:36.335136 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5092 22:14:36.335222 ==
5093 22:14:36.337943 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5094 22:14:36.344866 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5095 22:14:36.348292 [CA 0] Center 38 (8~69) winsize 62
5096 22:14:36.351746 [CA 1] Center 38 (8~69) winsize 62
5097 22:14:36.355285 [CA 2] Center 35 (5~66) winsize 62
5098 22:14:36.358074 [CA 3] Center 35 (4~66) winsize 63
5099 22:14:36.361767 [CA 4] Center 33 (3~64) winsize 62
5100 22:14:36.364989 [CA 5] Center 33 (3~64) winsize 62
5101 22:14:36.365087
5102 22:14:36.368080 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5103 22:14:36.368166
5104 22:14:36.371477 [CATrainingPosCal] consider 2 rank data
5105 22:14:36.375070 u2DelayCellTimex100 = 270/100 ps
5106 22:14:36.377892 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5107 22:14:36.384963 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5108 22:14:36.388120 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5109 22:14:36.391448 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5110 22:14:36.394547 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5111 22:14:36.398081 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5112 22:14:36.398163
5113 22:14:36.401660 CA PerBit enable=1, Macro0, CA PI delay=34
5114 22:14:36.401740
5115 22:14:36.404641 [CBTSetCACLKResult] CA Dly = 34
5116 22:14:36.404729 CS Dly: 7 (0~39)
5117 22:14:36.408435
5118 22:14:36.411257 ----->DramcWriteLeveling(PI) begin...
5119 22:14:36.411380 ==
5120 22:14:36.414742 Dram Type= 6, Freq= 0, CH_0, rank 0
5121 22:14:36.418204 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5122 22:14:36.418294 ==
5123 22:14:36.421565 Write leveling (Byte 0): 30 => 30
5124 22:14:36.425133 Write leveling (Byte 1): 27 => 27
5125 22:14:36.428450 DramcWriteLeveling(PI) end<-----
5126 22:14:36.428563
5127 22:14:36.428681 ==
5128 22:14:36.431753 Dram Type= 6, Freq= 0, CH_0, rank 0
5129 22:14:36.434939 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5130 22:14:36.435048 ==
5131 22:14:36.438459 [Gating] SW mode calibration
5132 22:14:36.444664 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5133 22:14:36.451354 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5134 22:14:36.454776 0 14 0 | B1->B0 | 2323 2929 | 0 1 | (0 0) (0 0)
5135 22:14:36.458370 0 14 4 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
5136 22:14:36.461344 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5137 22:14:36.468061 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5138 22:14:36.471114 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5139 22:14:36.474807 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5140 22:14:36.481170 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5141 22:14:36.484847 0 14 28 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
5142 22:14:36.488019 0 15 0 | B1->B0 | 3333 2929 | 0 0 | (0 1) (1 0)
5143 22:14:36.494335 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
5144 22:14:36.497707 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5145 22:14:36.501142 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5146 22:14:36.508017 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5147 22:14:36.511713 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5148 22:14:36.514390 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5149 22:14:36.520871 0 15 28 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
5150 22:14:36.524323 1 0 0 | B1->B0 | 2d2d 3d3d | 0 0 | (1 1) (0 0)
5151 22:14:36.527524 1 0 4 | B1->B0 | 4141 4646 | 1 0 | (0 0) (0 0)
5152 22:14:36.534397 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5153 22:14:36.537913 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5154 22:14:36.540886 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5155 22:14:36.547467 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5156 22:14:36.550897 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5157 22:14:36.554188 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5158 22:14:36.560848 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5159 22:14:36.564289 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5160 22:14:36.567707 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5161 22:14:36.574112 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5162 22:14:36.577650 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5163 22:14:36.580684 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5164 22:14:36.587363 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5165 22:14:36.591093 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5166 22:14:36.594252 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5167 22:14:36.600609 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5168 22:14:36.604204 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5169 22:14:36.607254 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5170 22:14:36.614009 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5171 22:14:36.617840 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5172 22:14:36.620920 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5173 22:14:36.623911 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5174 22:14:36.631039 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5175 22:14:36.634100 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5176 22:14:36.637360 Total UI for P1: 0, mck2ui 16
5177 22:14:36.640921 best dqsien dly found for B0: ( 1, 3, 0)
5178 22:14:36.644083 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5179 22:14:36.647249 Total UI for P1: 0, mck2ui 16
5180 22:14:36.650798 best dqsien dly found for B1: ( 1, 3, 4)
5181 22:14:36.654083 best DQS0 dly(MCK, UI, PI) = (1, 3, 0)
5182 22:14:36.657287 best DQS1 dly(MCK, UI, PI) = (1, 3, 4)
5183 22:14:36.660280
5184 22:14:36.663524 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 0)
5185 22:14:36.667066 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 4)
5186 22:14:36.670675 [Gating] SW calibration Done
5187 22:14:36.670762 ==
5188 22:14:36.673589 Dram Type= 6, Freq= 0, CH_0, rank 0
5189 22:14:36.676982 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5190 22:14:36.677069 ==
5191 22:14:36.677139 RX Vref Scan: 0
5192 22:14:36.677203
5193 22:14:36.680673 RX Vref 0 -> 0, step: 1
5194 22:14:36.680759
5195 22:14:36.683494 RX Delay -80 -> 252, step: 8
5196 22:14:36.687107 iDelay=208, Bit 0, Center 99 (8 ~ 191) 184
5197 22:14:36.690649 iDelay=208, Bit 1, Center 103 (8 ~ 199) 192
5198 22:14:36.693522 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5199 22:14:36.700566 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5200 22:14:36.703371 iDelay=208, Bit 4, Center 103 (8 ~ 199) 192
5201 22:14:36.706955 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5202 22:14:36.710457 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5203 22:14:36.713424 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5204 22:14:36.716962 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5205 22:14:36.723459 iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184
5206 22:14:36.726759 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5207 22:14:36.730045 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5208 22:14:36.733563 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5209 22:14:36.736723 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5210 22:14:36.742967 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5211 22:14:36.746341 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5212 22:14:36.746428 ==
5213 22:14:36.749976 Dram Type= 6, Freq= 0, CH_0, rank 0
5214 22:14:36.752954 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5215 22:14:36.753073 ==
5216 22:14:36.756854 DQS Delay:
5217 22:14:36.756964 DQS0 = 0, DQS1 = 0
5218 22:14:36.757082 DQM Delay:
5219 22:14:36.759683 DQM0 = 99, DQM1 = 87
5220 22:14:36.759791 DQ Delay:
5221 22:14:36.763090 DQ0 =99, DQ1 =103, DQ2 =95, DQ3 =95
5222 22:14:36.766425 DQ4 =103, DQ5 =87, DQ6 =107, DQ7 =103
5223 22:14:36.769952 DQ8 =79, DQ9 =75, DQ10 =87, DQ11 =79
5224 22:14:36.773446 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5225 22:14:36.773537
5226 22:14:36.773605
5227 22:14:36.773667 ==
5228 22:14:36.776355 Dram Type= 6, Freq= 0, CH_0, rank 0
5229 22:14:36.782824 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5230 22:14:36.782954 ==
5231 22:14:36.783061
5232 22:14:36.783154
5233 22:14:36.783253 TX Vref Scan disable
5234 22:14:36.786764 == TX Byte 0 ==
5235 22:14:36.790259 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5236 22:14:36.797104 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5237 22:14:36.797223 == TX Byte 1 ==
5238 22:14:36.799546 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5239 22:14:36.806718 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5240 22:14:36.806834 ==
5241 22:14:36.809656 Dram Type= 6, Freq= 0, CH_0, rank 0
5242 22:14:36.813222 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5243 22:14:36.813328 ==
5244 22:14:36.813444
5245 22:14:36.813536
5246 22:14:36.816194 TX Vref Scan disable
5247 22:14:36.816296 == TX Byte 0 ==
5248 22:14:36.823003 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5249 22:14:36.826752 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5250 22:14:36.826860 == TX Byte 1 ==
5251 22:14:36.833256 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5252 22:14:36.836436 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5253 22:14:36.836521
5254 22:14:36.836588 [DATLAT]
5255 22:14:36.839718 Freq=933, CH0 RK0
5256 22:14:36.839802
5257 22:14:36.839870 DATLAT Default: 0xd
5258 22:14:36.842984 0, 0xFFFF, sum = 0
5259 22:14:36.843101 1, 0xFFFF, sum = 0
5260 22:14:36.846454 2, 0xFFFF, sum = 0
5261 22:14:36.846566 3, 0xFFFF, sum = 0
5262 22:14:36.849378 4, 0xFFFF, sum = 0
5263 22:14:36.853205 5, 0xFFFF, sum = 0
5264 22:14:36.853291 6, 0xFFFF, sum = 0
5265 22:14:36.856183 7, 0xFFFF, sum = 0
5266 22:14:36.856270 8, 0xFFFF, sum = 0
5267 22:14:36.859860 9, 0xFFFF, sum = 0
5268 22:14:36.859947 10, 0x0, sum = 1
5269 22:14:36.862791 11, 0x0, sum = 2
5270 22:14:36.862877 12, 0x0, sum = 3
5271 22:14:36.862945 13, 0x0, sum = 4
5272 22:14:36.866220 best_step = 11
5273 22:14:36.866304
5274 22:14:36.866372 ==
5275 22:14:36.869761 Dram Type= 6, Freq= 0, CH_0, rank 0
5276 22:14:36.872966 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5277 22:14:36.873052 ==
5278 22:14:36.876020 RX Vref Scan: 1
5279 22:14:36.876105
5280 22:14:36.879520 RX Vref 0 -> 0, step: 1
5281 22:14:36.879605
5282 22:14:36.879673 RX Delay -61 -> 252, step: 4
5283 22:14:36.879736
5284 22:14:36.882945 Set Vref, RX VrefLevel [Byte0]: 52
5285 22:14:36.886034 [Byte1]: 51
5286 22:14:36.890809
5287 22:14:36.890924 Final RX Vref Byte 0 = 52 to rank0
5288 22:14:36.893661 Final RX Vref Byte 1 = 51 to rank0
5289 22:14:36.897375 Final RX Vref Byte 0 = 52 to rank1
5290 22:14:36.900964 Final RX Vref Byte 1 = 51 to rank1==
5291 22:14:36.903898 Dram Type= 6, Freq= 0, CH_0, rank 0
5292 22:14:36.910979 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5293 22:14:36.911070 ==
5294 22:14:36.911138 DQS Delay:
5295 22:14:36.911200 DQS0 = 0, DQS1 = 0
5296 22:14:36.913977 DQM Delay:
5297 22:14:36.914062 DQM0 = 96, DQM1 = 88
5298 22:14:36.917311 DQ Delay:
5299 22:14:36.920264 DQ0 =98, DQ1 =98, DQ2 =94, DQ3 =94
5300 22:14:36.923780 DQ4 =98, DQ5 =86, DQ6 =104, DQ7 =102
5301 22:14:36.927285 DQ8 =78, DQ9 =76, DQ10 =90, DQ11 =82
5302 22:14:36.930191 DQ12 =94, DQ13 =90, DQ14 =98, DQ15 =98
5303 22:14:36.930265
5304 22:14:36.930336
5305 22:14:36.937375 [DQSOSCAuto] RK0, (LSB)MR18= 0x14ff, (MSB)MR19= 0x504, tDQSOscB0 = 422 ps tDQSOscB1 = 415 ps
5306 22:14:36.941002 CH0 RK0: MR19=504, MR18=14FF
5307 22:14:36.947246 CH0_RK0: MR19=0x504, MR18=0x14FF, DQSOSC=415, MR23=63, INC=62, DEC=41
5308 22:14:36.947336
5309 22:14:36.950576 ----->DramcWriteLeveling(PI) begin...
5310 22:14:36.950662 ==
5311 22:14:36.953521 Dram Type= 6, Freq= 0, CH_0, rank 1
5312 22:14:36.956836 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5313 22:14:36.956912 ==
5314 22:14:36.960123 Write leveling (Byte 0): 30 => 30
5315 22:14:36.963914 Write leveling (Byte 1): 29 => 29
5316 22:14:36.966908 DramcWriteLeveling(PI) end<-----
5317 22:14:36.966988
5318 22:14:36.967068 ==
5319 22:14:36.970568 Dram Type= 6, Freq= 0, CH_0, rank 1
5320 22:14:36.973918 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5321 22:14:36.974013 ==
5322 22:14:36.976894 [Gating] SW mode calibration
5323 22:14:36.983843 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5324 22:14:36.990162 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5325 22:14:36.993477 0 14 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
5326 22:14:36.996793 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5327 22:14:37.003815 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5328 22:14:37.007045 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5329 22:14:37.010342 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5330 22:14:37.016999 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5331 22:14:37.019982 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5332 22:14:37.023401 0 14 28 | B1->B0 | 3434 2f2f | 0 0 | (0 0) (0 0)
5333 22:14:37.030826 0 15 0 | B1->B0 | 2d2d 2323 | 1 0 | (1 1) (0 0)
5334 22:14:37.033516 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5335 22:14:37.037108 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5336 22:14:37.043845 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5337 22:14:37.047034 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5338 22:14:37.050057 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5339 22:14:37.056895 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5340 22:14:37.060259 0 15 28 | B1->B0 | 2b2b 3c3c | 0 0 | (0 0) (0 0)
5341 22:14:37.063617 1 0 0 | B1->B0 | 3939 4646 | 1 0 | (0 0) (0 0)
5342 22:14:37.070408 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5343 22:14:37.073856 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5344 22:14:37.076582 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5345 22:14:37.083552 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5346 22:14:37.086729 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5347 22:14:37.090149 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5348 22:14:37.097038 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5349 22:14:37.100150 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5350 22:14:37.103290 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5351 22:14:37.110201 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5352 22:14:37.113578 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5353 22:14:37.117050 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5354 22:14:37.120525 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5355 22:14:37.127359 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5356 22:14:37.129955 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5357 22:14:37.133483 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5358 22:14:37.140231 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5359 22:14:37.143006 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5360 22:14:37.146780 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5361 22:14:37.153187 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5362 22:14:37.156819 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5363 22:14:37.160063 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5364 22:14:37.166524 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5365 22:14:37.169933 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5366 22:14:37.173256 Total UI for P1: 0, mck2ui 16
5367 22:14:37.176751 best dqsien dly found for B0: ( 1, 2, 26)
5368 22:14:37.179677 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5369 22:14:37.186601 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5370 22:14:37.186719 Total UI for P1: 0, mck2ui 16
5371 22:14:37.193007 best dqsien dly found for B1: ( 1, 3, 0)
5372 22:14:37.196636 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5373 22:14:37.199472 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5374 22:14:37.199558
5375 22:14:37.203036 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5376 22:14:37.206176 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5377 22:14:37.209490 [Gating] SW calibration Done
5378 22:14:37.209572 ==
5379 22:14:37.212933 Dram Type= 6, Freq= 0, CH_0, rank 1
5380 22:14:37.216175 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5381 22:14:37.216265 ==
5382 22:14:37.219570 RX Vref Scan: 0
5383 22:14:37.219649
5384 22:14:37.219724 RX Vref 0 -> 0, step: 1
5385 22:14:37.219791
5386 22:14:37.222900 RX Delay -80 -> 252, step: 8
5387 22:14:37.226312 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5388 22:14:37.232959 iDelay=200, Bit 1, Center 99 (0 ~ 199) 200
5389 22:14:37.236375 iDelay=200, Bit 2, Center 95 (0 ~ 191) 192
5390 22:14:37.239426 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5391 22:14:37.242907 iDelay=200, Bit 4, Center 99 (8 ~ 191) 184
5392 22:14:37.245954 iDelay=200, Bit 5, Center 87 (-8 ~ 183) 192
5393 22:14:37.249512 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5394 22:14:37.252890 iDelay=200, Bit 7, Center 103 (8 ~ 199) 192
5395 22:14:37.259119 iDelay=200, Bit 8, Center 83 (-8 ~ 175) 184
5396 22:14:37.262647 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5397 22:14:37.266087 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5398 22:14:37.269462 iDelay=200, Bit 11, Center 75 (-16 ~ 167) 184
5399 22:14:37.272398 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5400 22:14:37.279118 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5401 22:14:37.282535 iDelay=200, Bit 14, Center 99 (8 ~ 191) 184
5402 22:14:37.286162 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5403 22:14:37.286242 ==
5404 22:14:37.289393 Dram Type= 6, Freq= 0, CH_0, rank 1
5405 22:14:37.292563 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5406 22:14:37.292644 ==
5407 22:14:37.295853 DQS Delay:
5408 22:14:37.295931 DQS0 = 0, DQS1 = 0
5409 22:14:37.299089 DQM Delay:
5410 22:14:37.299179 DQM0 = 97, DQM1 = 88
5411 22:14:37.299259 DQ Delay:
5412 22:14:37.302127 DQ0 =95, DQ1 =99, DQ2 =95, DQ3 =95
5413 22:14:37.305496 DQ4 =99, DQ5 =87, DQ6 =103, DQ7 =103
5414 22:14:37.309019 DQ8 =83, DQ9 =79, DQ10 =87, DQ11 =75
5415 22:14:37.311967 DQ12 =95, DQ13 =95, DQ14 =99, DQ15 =95
5416 22:14:37.312045
5417 22:14:37.312120
5418 22:14:37.315662 ==
5419 22:14:37.319260 Dram Type= 6, Freq= 0, CH_0, rank 1
5420 22:14:37.322027 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5421 22:14:37.322110 ==
5422 22:14:37.322179
5423 22:14:37.322248
5424 22:14:37.325412 TX Vref Scan disable
5425 22:14:37.325497 == TX Byte 0 ==
5426 22:14:37.328891 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5427 22:14:37.335621 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5428 22:14:37.335715 == TX Byte 1 ==
5429 22:14:37.338557 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5430 22:14:37.345633 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5431 22:14:37.345758 ==
5432 22:14:37.348851 Dram Type= 6, Freq= 0, CH_0, rank 1
5433 22:14:37.352385 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5434 22:14:37.352468 ==
5435 22:14:37.352536
5436 22:14:37.352606
5437 22:14:37.355216 TX Vref Scan disable
5438 22:14:37.358662 == TX Byte 0 ==
5439 22:14:37.362098 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5440 22:14:37.365393 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5441 22:14:37.368812 == TX Byte 1 ==
5442 22:14:37.372145 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5443 22:14:37.375533 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5444 22:14:37.375627
5445 22:14:37.378580 [DATLAT]
5446 22:14:37.378657 Freq=933, CH0 RK1
5447 22:14:37.378722
5448 22:14:37.381975 DATLAT Default: 0xb
5449 22:14:37.382047 0, 0xFFFF, sum = 0
5450 22:14:37.385863 1, 0xFFFF, sum = 0
5451 22:14:37.385932 2, 0xFFFF, sum = 0
5452 22:14:37.388613 3, 0xFFFF, sum = 0
5453 22:14:37.388732 4, 0xFFFF, sum = 0
5454 22:14:37.391883 5, 0xFFFF, sum = 0
5455 22:14:37.391967 6, 0xFFFF, sum = 0
5456 22:14:37.395481 7, 0xFFFF, sum = 0
5457 22:14:37.395565 8, 0xFFFF, sum = 0
5458 22:14:37.398491 9, 0xFFFF, sum = 0
5459 22:14:37.398575 10, 0x0, sum = 1
5460 22:14:37.402057 11, 0x0, sum = 2
5461 22:14:37.402141 12, 0x0, sum = 3
5462 22:14:37.404904 13, 0x0, sum = 4
5463 22:14:37.404989 best_step = 11
5464 22:14:37.405056
5465 22:14:37.405118 ==
5466 22:14:37.408467 Dram Type= 6, Freq= 0, CH_0, rank 1
5467 22:14:37.411954 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5468 22:14:37.414966 ==
5469 22:14:37.415063 RX Vref Scan: 0
5470 22:14:37.415128
5471 22:14:37.418578 RX Vref 0 -> 0, step: 1
5472 22:14:37.418662
5473 22:14:37.421940 RX Delay -61 -> 252, step: 4
5474 22:14:37.424854 iDelay=199, Bit 0, Center 96 (3 ~ 190) 188
5475 22:14:37.428534 iDelay=199, Bit 1, Center 96 (3 ~ 190) 188
5476 22:14:37.431709 iDelay=199, Bit 2, Center 92 (-1 ~ 186) 188
5477 22:14:37.438311 iDelay=199, Bit 3, Center 94 (-1 ~ 190) 192
5478 22:14:37.441783 iDelay=199, Bit 4, Center 94 (3 ~ 186) 184
5479 22:14:37.445210 iDelay=199, Bit 5, Center 84 (-9 ~ 178) 188
5480 22:14:37.448232 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5481 22:14:37.451495 iDelay=199, Bit 7, Center 102 (11 ~ 194) 184
5482 22:14:37.455257 iDelay=199, Bit 8, Center 80 (-9 ~ 170) 180
5483 22:14:37.461533 iDelay=199, Bit 9, Center 78 (-13 ~ 170) 184
5484 22:14:37.464760 iDelay=199, Bit 10, Center 90 (3 ~ 178) 176
5485 22:14:37.468434 iDelay=199, Bit 11, Center 80 (-5 ~ 166) 172
5486 22:14:37.471798 iDelay=199, Bit 12, Center 92 (3 ~ 182) 180
5487 22:14:37.474987 iDelay=199, Bit 13, Center 92 (3 ~ 182) 180
5488 22:14:37.481515 iDelay=199, Bit 14, Center 94 (7 ~ 182) 176
5489 22:14:37.484545 iDelay=199, Bit 15, Center 94 (7 ~ 182) 176
5490 22:14:37.484630 ==
5491 22:14:37.487994 Dram Type= 6, Freq= 0, CH_0, rank 1
5492 22:14:37.491462 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5493 22:14:37.491548 ==
5494 22:14:37.491615 DQS Delay:
5495 22:14:37.494895 DQS0 = 0, DQS1 = 0
5496 22:14:37.494980 DQM Delay:
5497 22:14:37.498080 DQM0 = 95, DQM1 = 87
5498 22:14:37.498194 DQ Delay:
5499 22:14:37.501522 DQ0 =96, DQ1 =96, DQ2 =92, DQ3 =94
5500 22:14:37.504979 DQ4 =94, DQ5 =84, DQ6 =104, DQ7 =102
5501 22:14:37.507985 DQ8 =80, DQ9 =78, DQ10 =90, DQ11 =80
5502 22:14:37.511287 DQ12 =92, DQ13 =92, DQ14 =94, DQ15 =94
5503 22:14:37.511381
5504 22:14:37.511467
5505 22:14:37.521433 [DQSOSCAuto] RK1, (LSB)MR18= 0x1e0c, (MSB)MR19= 0x505, tDQSOscB0 = 418 ps tDQSOscB1 = 412 ps
5506 22:14:37.521522 CH0 RK1: MR19=505, MR18=1E0C
5507 22:14:37.527816 CH0_RK1: MR19=0x505, MR18=0x1E0C, DQSOSC=412, MR23=63, INC=63, DEC=42
5508 22:14:37.531459 [RxdqsGatingPostProcess] freq 933
5509 22:14:37.537798 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5510 22:14:37.541391 best DQS0 dly(2T, 0.5T) = (0, 11)
5511 22:14:37.544386 best DQS1 dly(2T, 0.5T) = (0, 11)
5512 22:14:37.547927 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
5513 22:14:37.550973 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5514 22:14:37.554691 best DQS0 dly(2T, 0.5T) = (0, 10)
5515 22:14:37.554829 best DQS1 dly(2T, 0.5T) = (0, 11)
5516 22:14:37.557951 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5517 22:14:37.560981 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5518 22:14:37.564527 Pre-setting of DQS Precalculation
5519 22:14:37.571258 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5520 22:14:37.571388 ==
5521 22:14:37.574753 Dram Type= 6, Freq= 0, CH_1, rank 0
5522 22:14:37.577638 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5523 22:14:37.577722 ==
5524 22:14:37.584387 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5525 22:14:37.590646 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5526 22:14:37.594045 [CA 0] Center 36 (6~67) winsize 62
5527 22:14:37.597391 [CA 1] Center 36 (6~67) winsize 62
5528 22:14:37.600659 [CA 2] Center 34 (4~64) winsize 61
5529 22:14:37.604166 [CA 3] Center 33 (3~64) winsize 62
5530 22:14:37.607638 [CA 4] Center 33 (3~64) winsize 62
5531 22:14:37.610618 [CA 5] Center 33 (3~64) winsize 62
5532 22:14:37.610701
5533 22:14:37.614218 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5534 22:14:37.614314
5535 22:14:37.617154 [CATrainingPosCal] consider 1 rank data
5536 22:14:37.620599 u2DelayCellTimex100 = 270/100 ps
5537 22:14:37.624095 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5538 22:14:37.627083 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5539 22:14:37.630338 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5540 22:14:37.633917 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5541 22:14:37.637068 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5542 22:14:37.640516 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5543 22:14:37.640601
5544 22:14:37.647181 CA PerBit enable=1, Macro0, CA PI delay=33
5545 22:14:37.647267
5546 22:14:37.647334 [CBTSetCACLKResult] CA Dly = 33
5547 22:14:37.650568 CS Dly: 4 (0~35)
5548 22:14:37.650653 ==
5549 22:14:37.653509 Dram Type= 6, Freq= 0, CH_1, rank 1
5550 22:14:37.657063 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5551 22:14:37.657148 ==
5552 22:14:37.663805 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5553 22:14:37.670138 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5554 22:14:37.673666 [CA 0] Center 36 (6~67) winsize 62
5555 22:14:37.676662 [CA 1] Center 36 (6~67) winsize 62
5556 22:14:37.679945 [CA 2] Center 33 (3~64) winsize 62
5557 22:14:37.683236 [CA 3] Center 34 (4~64) winsize 61
5558 22:14:37.686772 [CA 4] Center 34 (4~65) winsize 62
5559 22:14:37.690343 [CA 5] Center 33 (3~63) winsize 61
5560 22:14:37.690428
5561 22:14:37.693201 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5562 22:14:37.693286
5563 22:14:37.696745 [CATrainingPosCal] consider 2 rank data
5564 22:14:37.699852 u2DelayCellTimex100 = 270/100 ps
5565 22:14:37.703182 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5566 22:14:37.706541 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5567 22:14:37.709982 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5568 22:14:37.713357 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5569 22:14:37.716428 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5570 22:14:37.723028 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5571 22:14:37.723121
5572 22:14:37.726389 CA PerBit enable=1, Macro0, CA PI delay=33
5573 22:14:37.726480
5574 22:14:37.729452 [CBTSetCACLKResult] CA Dly = 33
5575 22:14:37.729533 CS Dly: 5 (0~37)
5576 22:14:37.729602
5577 22:14:37.733267 ----->DramcWriteLeveling(PI) begin...
5578 22:14:37.733356 ==
5579 22:14:37.736669 Dram Type= 6, Freq= 0, CH_1, rank 0
5580 22:14:37.743213 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5581 22:14:37.743299 ==
5582 22:14:37.746142 Write leveling (Byte 0): 25 => 25
5583 22:14:37.746227 Write leveling (Byte 1): 29 => 29
5584 22:14:37.749690 DramcWriteLeveling(PI) end<-----
5585 22:14:37.749774
5586 22:14:37.749849 ==
5587 22:14:37.753334 Dram Type= 6, Freq= 0, CH_1, rank 0
5588 22:14:37.759729 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5589 22:14:37.759826 ==
5590 22:14:37.762704 [Gating] SW mode calibration
5591 22:14:37.769297 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5592 22:14:37.772640 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5593 22:14:37.779666 0 14 0 | B1->B0 | 2e2e 3030 | 1 1 | (1 1) (1 1)
5594 22:14:37.783319 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5595 22:14:37.786131 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5596 22:14:37.792592 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5597 22:14:37.796139 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5598 22:14:37.799585 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5599 22:14:37.806045 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5600 22:14:37.809551 0 14 28 | B1->B0 | 3131 3333 | 0 0 | (1 0) (0 1)
5601 22:14:37.812592 0 15 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5602 22:14:37.816015 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5603 22:14:37.822930 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5604 22:14:37.825861 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5605 22:14:37.829255 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5606 22:14:37.835838 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5607 22:14:37.839195 0 15 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5608 22:14:37.842863 0 15 28 | B1->B0 | 2d2d 2928 | 0 1 | (0 0) (0 0)
5609 22:14:37.849456 1 0 0 | B1->B0 | 4444 4343 | 0 0 | (0 0) (0 0)
5610 22:14:37.852848 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5611 22:14:37.855790 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5612 22:14:37.862781 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5613 22:14:37.865609 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5614 22:14:37.869164 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5615 22:14:37.876182 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5616 22:14:37.879010 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5617 22:14:37.882472 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5618 22:14:37.889380 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5619 22:14:37.892827 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5620 22:14:37.895637 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5621 22:14:37.902885 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5622 22:14:37.905766 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5623 22:14:37.909041 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5624 22:14:37.916084 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5625 22:14:37.919067 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5626 22:14:37.922527 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5627 22:14:37.929177 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5628 22:14:37.932239 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5629 22:14:37.935613 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5630 22:14:37.939377 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5631 22:14:37.945658 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5632 22:14:37.949199 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5633 22:14:37.952855 Total UI for P1: 0, mck2ui 16
5634 22:14:37.955852 best dqsien dly found for B0: ( 1, 2, 26)
5635 22:14:37.959310 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5636 22:14:37.962310 Total UI for P1: 0, mck2ui 16
5637 22:14:37.965824 best dqsien dly found for B1: ( 1, 2, 28)
5638 22:14:37.968738 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5639 22:14:37.972226 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5640 22:14:37.975672
5641 22:14:37.979094 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5642 22:14:37.982336 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5643 22:14:37.985735 [Gating] SW calibration Done
5644 22:14:37.985816 ==
5645 22:14:37.988638 Dram Type= 6, Freq= 0, CH_1, rank 0
5646 22:14:37.992065 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5647 22:14:37.992145 ==
5648 22:14:37.992211 RX Vref Scan: 0
5649 22:14:37.992273
5650 22:14:37.995345 RX Vref 0 -> 0, step: 1
5651 22:14:37.995435
5652 22:14:37.998740 RX Delay -80 -> 252, step: 8
5653 22:14:38.002446 iDelay=200, Bit 0, Center 99 (8 ~ 191) 184
5654 22:14:38.005374 iDelay=200, Bit 1, Center 91 (-8 ~ 191) 200
5655 22:14:38.012260 iDelay=200, Bit 2, Center 83 (-8 ~ 175) 184
5656 22:14:38.015505 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5657 22:14:38.018401 iDelay=200, Bit 4, Center 95 (0 ~ 191) 192
5658 22:14:38.021903 iDelay=200, Bit 5, Center 103 (8 ~ 199) 192
5659 22:14:38.025341 iDelay=200, Bit 6, Center 107 (16 ~ 199) 184
5660 22:14:38.028676 iDelay=200, Bit 7, Center 91 (-8 ~ 191) 200
5661 22:14:38.035110 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5662 22:14:38.038626 iDelay=200, Bit 9, Center 75 (-24 ~ 175) 200
5663 22:14:38.042130 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5664 22:14:38.045264 iDelay=200, Bit 11, Center 83 (-16 ~ 183) 200
5665 22:14:38.048842 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5666 22:14:38.051845 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5667 22:14:38.058434 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5668 22:14:38.061877 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5669 22:14:38.061971 ==
5670 22:14:38.065515 Dram Type= 6, Freq= 0, CH_1, rank 0
5671 22:14:38.068811 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5672 22:14:38.068889 ==
5673 22:14:38.071959 DQS Delay:
5674 22:14:38.072043 DQS0 = 0, DQS1 = 0
5675 22:14:38.072122 DQM Delay:
5676 22:14:38.075346 DQM0 = 95, DQM1 = 88
5677 22:14:38.075451 DQ Delay:
5678 22:14:38.078684 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =95
5679 22:14:38.082057 DQ4 =95, DQ5 =103, DQ6 =107, DQ7 =91
5680 22:14:38.085562 DQ8 =79, DQ9 =75, DQ10 =87, DQ11 =83
5681 22:14:38.088277 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5682 22:14:38.088375
5683 22:14:38.088457
5684 22:14:38.088524 ==
5685 22:14:38.091886 Dram Type= 6, Freq= 0, CH_1, rank 0
5686 22:14:38.098615 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5687 22:14:38.098723 ==
5688 22:14:38.098834
5689 22:14:38.098940
5690 22:14:38.099034 TX Vref Scan disable
5691 22:14:38.101938 == TX Byte 0 ==
5692 22:14:38.105145 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5693 22:14:38.111810 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5694 22:14:38.111892 == TX Byte 1 ==
5695 22:14:38.115178 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5696 22:14:38.121560 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5697 22:14:38.121650 ==
5698 22:14:38.125197 Dram Type= 6, Freq= 0, CH_1, rank 0
5699 22:14:38.128377 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5700 22:14:38.128490 ==
5701 22:14:38.128564
5702 22:14:38.128634
5703 22:14:38.131756 TX Vref Scan disable
5704 22:14:38.131838 == TX Byte 0 ==
5705 22:14:38.138796 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5706 22:14:38.141622 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5707 22:14:38.141710 == TX Byte 1 ==
5708 22:14:38.148443 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5709 22:14:38.151472 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5710 22:14:38.151564
5711 22:14:38.151639 [DATLAT]
5712 22:14:38.154957 Freq=933, CH1 RK0
5713 22:14:38.155063
5714 22:14:38.155138 DATLAT Default: 0xd
5715 22:14:38.158373 0, 0xFFFF, sum = 0
5716 22:14:38.158467 1, 0xFFFF, sum = 0
5717 22:14:38.161349 2, 0xFFFF, sum = 0
5718 22:14:38.164836 3, 0xFFFF, sum = 0
5719 22:14:38.164929 4, 0xFFFF, sum = 0
5720 22:14:38.168456 5, 0xFFFF, sum = 0
5721 22:14:38.168543 6, 0xFFFF, sum = 0
5722 22:14:38.171435 7, 0xFFFF, sum = 0
5723 22:14:38.171513 8, 0xFFFF, sum = 0
5724 22:14:38.174956 9, 0xFFFF, sum = 0
5725 22:14:38.175064 10, 0x0, sum = 1
5726 22:14:38.178460 11, 0x0, sum = 2
5727 22:14:38.178563 12, 0x0, sum = 3
5728 22:14:38.178651 13, 0x0, sum = 4
5729 22:14:38.181452 best_step = 11
5730 22:14:38.181559
5731 22:14:38.181655 ==
5732 22:14:38.185195 Dram Type= 6, Freq= 0, CH_1, rank 0
5733 22:14:38.188776 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5734 22:14:38.188853 ==
5735 22:14:38.191369 RX Vref Scan: 1
5736 22:14:38.191459
5737 22:14:38.191523 RX Vref 0 -> 0, step: 1
5738 22:14:38.194747
5739 22:14:38.194825 RX Delay -69 -> 252, step: 4
5740 22:14:38.194900
5741 22:14:38.198252 Set Vref, RX VrefLevel [Byte0]: 59
5742 22:14:38.201603 [Byte1]: 53
5743 22:14:38.205727
5744 22:14:38.205836 Final RX Vref Byte 0 = 59 to rank0
5745 22:14:38.209503 Final RX Vref Byte 1 = 53 to rank0
5746 22:14:38.212814 Final RX Vref Byte 0 = 59 to rank1
5747 22:14:38.215719 Final RX Vref Byte 1 = 53 to rank1==
5748 22:14:38.218997 Dram Type= 6, Freq= 0, CH_1, rank 0
5749 22:14:38.225712 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5750 22:14:38.225795 ==
5751 22:14:38.225863 DQS Delay:
5752 22:14:38.225926 DQS0 = 0, DQS1 = 0
5753 22:14:38.231561 DQM Delay:
5754 22:14:38.231675 DQM0 = 98, DQM1 = 89
5755 22:14:38.232365 DQ Delay:
5756 22:14:38.235937 DQ0 =102, DQ1 =92, DQ2 =88, DQ3 =98
5757 22:14:38.239494 DQ4 =96, DQ5 =108, DQ6 =108, DQ7 =94
5758 22:14:38.242388 DQ8 =80, DQ9 =80, DQ10 =90, DQ11 =86
5759 22:14:38.245625 DQ12 =96, DQ13 =96, DQ14 =94, DQ15 =96
5760 22:14:38.245720
5761 22:14:38.245794
5762 22:14:38.252537 [DQSOSCAuto] RK0, (LSB)MR18= 0x17f4, (MSB)MR19= 0x504, tDQSOscB0 = 426 ps tDQSOscB1 = 414 ps
5763 22:14:38.255632 CH1 RK0: MR19=504, MR18=17F4
5764 22:14:38.262227 CH1_RK0: MR19=0x504, MR18=0x17F4, DQSOSC=414, MR23=63, INC=63, DEC=42
5765 22:14:38.262315
5766 22:14:38.265883 ----->DramcWriteLeveling(PI) begin...
5767 22:14:38.265970 ==
5768 22:14:38.269419 Dram Type= 6, Freq= 0, CH_1, rank 1
5769 22:14:38.272231 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5770 22:14:38.272317 ==
5771 22:14:38.275852 Write leveling (Byte 0): 26 => 26
5772 22:14:38.278797 Write leveling (Byte 1): 26 => 26
5773 22:14:38.282389 DramcWriteLeveling(PI) end<-----
5774 22:14:38.282474
5775 22:14:38.282541 ==
5776 22:14:38.285363 Dram Type= 6, Freq= 0, CH_1, rank 1
5777 22:14:38.288987 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5778 22:14:38.289066 ==
5779 22:14:38.292864 [Gating] SW mode calibration
5780 22:14:38.298911 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5781 22:14:38.305443 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5782 22:14:38.308933 0 14 0 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5783 22:14:38.315691 0 14 4 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5784 22:14:38.319127 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5785 22:14:38.322082 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5786 22:14:38.329321 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5787 22:14:38.332196 0 14 20 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
5788 22:14:38.336079 0 14 24 | B1->B0 | 3434 2c2c | 0 1 | (0 0) (1 0)
5789 22:14:38.342214 0 14 28 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
5790 22:14:38.345382 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5791 22:14:38.348674 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5792 22:14:38.352137 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5793 22:14:38.358632 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5794 22:14:38.361675 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5795 22:14:38.365256 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5796 22:14:38.372105 0 15 24 | B1->B0 | 2525 3333 | 0 0 | (0 0) (0 0)
5797 22:14:38.375518 0 15 28 | B1->B0 | 3a3a 4444 | 0 0 | (0 0) (0 0)
5798 22:14:38.378604 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5799 22:14:38.385142 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5800 22:14:38.388651 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5801 22:14:38.391505 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5802 22:14:38.398451 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5803 22:14:38.401699 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5804 22:14:38.405210 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5805 22:14:38.411493 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5806 22:14:38.415334 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5807 22:14:38.418544 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5808 22:14:38.424719 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5809 22:14:38.428066 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5810 22:14:38.432114 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5811 22:14:38.438005 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5812 22:14:38.441704 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5813 22:14:38.445120 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5814 22:14:38.451462 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5815 22:14:38.454678 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5816 22:14:38.458334 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5817 22:14:38.464788 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5818 22:14:38.467886 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5819 22:14:38.471312 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5820 22:14:38.477793 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5821 22:14:38.477879 Total UI for P1: 0, mck2ui 16
5822 22:14:38.484968 best dqsien dly found for B0: ( 1, 2, 20)
5823 22:14:38.488073 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5824 22:14:38.491562 Total UI for P1: 0, mck2ui 16
5825 22:14:38.494802 best dqsien dly found for B1: ( 1, 2, 24)
5826 22:14:38.497653 best DQS0 dly(MCK, UI, PI) = (1, 2, 20)
5827 22:14:38.501049 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5828 22:14:38.501146
5829 22:14:38.504424 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 20)
5830 22:14:38.507788 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5831 22:14:38.511242 [Gating] SW calibration Done
5832 22:14:38.511325 ==
5833 22:14:38.514578 Dram Type= 6, Freq= 0, CH_1, rank 1
5834 22:14:38.517905 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5835 22:14:38.517987 ==
5836 22:14:38.521126 RX Vref Scan: 0
5837 22:14:38.521211
5838 22:14:38.524540 RX Vref 0 -> 0, step: 1
5839 22:14:38.524623
5840 22:14:38.524692 RX Delay -80 -> 252, step: 8
5841 22:14:38.531321 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5842 22:14:38.534221 iDelay=200, Bit 1, Center 91 (-8 ~ 191) 200
5843 22:14:38.537912 iDelay=200, Bit 2, Center 87 (-8 ~ 183) 192
5844 22:14:38.541438 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5845 22:14:38.544298 iDelay=200, Bit 4, Center 95 (0 ~ 191) 192
5846 22:14:38.547631 iDelay=200, Bit 5, Center 103 (8 ~ 199) 192
5847 22:14:38.554657 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5848 22:14:38.557650 iDelay=200, Bit 7, Center 91 (0 ~ 183) 184
5849 22:14:38.561167 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5850 22:14:38.564678 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5851 22:14:38.567657 iDelay=200, Bit 10, Center 91 (-8 ~ 191) 200
5852 22:14:38.574154 iDelay=200, Bit 11, Center 83 (-8 ~ 175) 184
5853 22:14:38.577813 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5854 22:14:38.580616 iDelay=200, Bit 13, Center 99 (0 ~ 199) 200
5855 22:14:38.584321 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5856 22:14:38.587175 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5857 22:14:38.587279 ==
5858 22:14:38.590585 Dram Type= 6, Freq= 0, CH_1, rank 1
5859 22:14:38.597136 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5860 22:14:38.597224 ==
5861 22:14:38.597290 DQS Delay:
5862 22:14:38.597353 DQS0 = 0, DQS1 = 0
5863 22:14:38.600545 DQM Delay:
5864 22:14:38.600617 DQM0 = 95, DQM1 = 89
5865 22:14:38.604004 DQ Delay:
5866 22:14:38.607325 DQ0 =95, DQ1 =91, DQ2 =87, DQ3 =95
5867 22:14:38.610795 DQ4 =95, DQ5 =103, DQ6 =103, DQ7 =91
5868 22:14:38.613978 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =83
5869 22:14:38.617287 DQ12 =95, DQ13 =99, DQ14 =95, DQ15 =95
5870 22:14:38.617365
5871 22:14:38.617434
5872 22:14:38.617494 ==
5873 22:14:38.620685 Dram Type= 6, Freq= 0, CH_1, rank 1
5874 22:14:38.623857 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5875 22:14:38.623937 ==
5876 22:14:38.624002
5877 22:14:38.624068
5878 22:14:38.627304 TX Vref Scan disable
5879 22:14:38.627405 == TX Byte 0 ==
5880 22:14:38.634023 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5881 22:14:38.637215 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5882 22:14:38.637292 == TX Byte 1 ==
5883 22:14:38.643721 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5884 22:14:38.647229 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5885 22:14:38.647335 ==
5886 22:14:38.650452 Dram Type= 6, Freq= 0, CH_1, rank 1
5887 22:14:38.653912 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5888 22:14:38.654028 ==
5889 22:14:38.654124
5890 22:14:38.654221
5891 22:14:38.657229 TX Vref Scan disable
5892 22:14:38.660432 == TX Byte 0 ==
5893 22:14:38.663928 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5894 22:14:38.666980 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5895 22:14:38.670545 == TX Byte 1 ==
5896 22:14:38.673711 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5897 22:14:38.677066 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5898 22:14:38.677177
5899 22:14:38.680577 [DATLAT]
5900 22:14:38.680660 Freq=933, CH1 RK1
5901 22:14:38.680727
5902 22:14:38.683896 DATLAT Default: 0xb
5903 22:14:38.684006 0, 0xFFFF, sum = 0
5904 22:14:38.686872 1, 0xFFFF, sum = 0
5905 22:14:38.686958 2, 0xFFFF, sum = 0
5906 22:14:38.690579 3, 0xFFFF, sum = 0
5907 22:14:38.690690 4, 0xFFFF, sum = 0
5908 22:14:38.693586 5, 0xFFFF, sum = 0
5909 22:14:38.693664 6, 0xFFFF, sum = 0
5910 22:14:38.697019 7, 0xFFFF, sum = 0
5911 22:14:38.697104 8, 0xFFFF, sum = 0
5912 22:14:38.700125 9, 0xFFFF, sum = 0
5913 22:14:38.700210 10, 0x0, sum = 1
5914 22:14:38.703841 11, 0x0, sum = 2
5915 22:14:38.703926 12, 0x0, sum = 3
5916 22:14:38.706820 13, 0x0, sum = 4
5917 22:14:38.706927 best_step = 11
5918 22:14:38.706995
5919 22:14:38.707056 ==
5920 22:14:38.710260 Dram Type= 6, Freq= 0, CH_1, rank 1
5921 22:14:38.717190 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5922 22:14:38.717309 ==
5923 22:14:38.717407 RX Vref Scan: 0
5924 22:14:38.717499
5925 22:14:38.720009 RX Vref 0 -> 0, step: 1
5926 22:14:38.720095
5927 22:14:38.723294 RX Delay -61 -> 252, step: 4
5928 22:14:38.727099 iDelay=199, Bit 0, Center 98 (7 ~ 190) 184
5929 22:14:38.730017 iDelay=199, Bit 1, Center 90 (-1 ~ 182) 184
5930 22:14:38.737065 iDelay=199, Bit 2, Center 86 (-5 ~ 178) 184
5931 22:14:38.740154 iDelay=199, Bit 3, Center 92 (-1 ~ 186) 188
5932 22:14:38.743458 iDelay=199, Bit 4, Center 96 (7 ~ 186) 180
5933 22:14:38.746770 iDelay=199, Bit 5, Center 106 (19 ~ 194) 176
5934 22:14:38.750045 iDelay=199, Bit 6, Center 106 (15 ~ 198) 184
5935 22:14:38.756844 iDelay=199, Bit 7, Center 92 (3 ~ 182) 180
5936 22:14:38.759856 iDelay=199, Bit 8, Center 80 (-13 ~ 174) 188
5937 22:14:38.763154 iDelay=199, Bit 9, Center 78 (-13 ~ 170) 184
5938 22:14:38.766969 iDelay=199, Bit 10, Center 90 (-5 ~ 186) 192
5939 22:14:38.769636 iDelay=199, Bit 11, Center 84 (-5 ~ 174) 180
5940 22:14:38.773150 iDelay=199, Bit 12, Center 96 (7 ~ 186) 180
5941 22:14:38.779752 iDelay=199, Bit 13, Center 98 (7 ~ 190) 184
5942 22:14:38.783359 iDelay=199, Bit 14, Center 102 (15 ~ 190) 176
5943 22:14:38.786477 iDelay=199, Bit 15, Center 98 (7 ~ 190) 184
5944 22:14:38.786562 ==
5945 22:14:38.789884 Dram Type= 6, Freq= 0, CH_1, rank 1
5946 22:14:38.793635 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5947 22:14:38.793720 ==
5948 22:14:38.796819 DQS Delay:
5949 22:14:38.796931 DQS0 = 0, DQS1 = 0
5950 22:14:38.799887 DQM Delay:
5951 22:14:38.799996 DQM0 = 95, DQM1 = 90
5952 22:14:38.800069 DQ Delay:
5953 22:14:38.803364 DQ0 =98, DQ1 =90, DQ2 =86, DQ3 =92
5954 22:14:38.806409 DQ4 =96, DQ5 =106, DQ6 =106, DQ7 =92
5955 22:14:38.810297 DQ8 =80, DQ9 =78, DQ10 =90, DQ11 =84
5956 22:14:38.812862 DQ12 =96, DQ13 =98, DQ14 =102, DQ15 =98
5957 22:14:38.812946
5958 22:14:38.813019
5959 22:14:38.823035 [DQSOSCAuto] RK1, (LSB)MR18= 0xd16, (MSB)MR19= 0x505, tDQSOscB0 = 414 ps tDQSOscB1 = 417 ps
5960 22:14:38.826446 CH1 RK1: MR19=505, MR18=D16
5961 22:14:38.829756 CH1_RK1: MR19=0x505, MR18=0xD16, DQSOSC=414, MR23=63, INC=63, DEC=42
5962 22:14:38.833014 [RxdqsGatingPostProcess] freq 933
5963 22:14:38.839580 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5964 22:14:38.842734 best DQS0 dly(2T, 0.5T) = (0, 10)
5965 22:14:38.846028 best DQS1 dly(2T, 0.5T) = (0, 10)
5966 22:14:38.849401 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5967 22:14:38.852710 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5968 22:14:38.856313 best DQS0 dly(2T, 0.5T) = (0, 10)
5969 22:14:38.859281 best DQS1 dly(2T, 0.5T) = (0, 10)
5970 22:14:38.862606 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5971 22:14:38.865924 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5972 22:14:38.869312 Pre-setting of DQS Precalculation
5973 22:14:38.872928 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5974 22:14:38.879506 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5975 22:14:38.885733 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5976 22:14:38.885808
5977 22:14:38.889326
5978 22:14:38.889400 [Calibration Summary] 1866 Mbps
5979 22:14:38.892443 CH 0, Rank 0
5980 22:14:38.892515 SW Impedance : PASS
5981 22:14:38.895977 DUTY Scan : NO K
5982 22:14:38.899130 ZQ Calibration : PASS
5983 22:14:38.899205 Jitter Meter : NO K
5984 22:14:38.902651 CBT Training : PASS
5985 22:14:38.906156 Write leveling : PASS
5986 22:14:38.906232 RX DQS gating : PASS
5987 22:14:38.909382 RX DQ/DQS(RDDQC) : PASS
5988 22:14:38.912724 TX DQ/DQS : PASS
5989 22:14:38.912798 RX DATLAT : PASS
5990 22:14:38.915648 RX DQ/DQS(Engine): PASS
5991 22:14:38.919165 TX OE : NO K
5992 22:14:38.919267 All Pass.
5993 22:14:38.919380
5994 22:14:38.919476 CH 0, Rank 1
5995 22:14:38.922421 SW Impedance : PASS
5996 22:14:38.925751 DUTY Scan : NO K
5997 22:14:38.925850 ZQ Calibration : PASS
5998 22:14:38.929033 Jitter Meter : NO K
5999 22:14:38.932463 CBT Training : PASS
6000 22:14:38.932540 Write leveling : PASS
6001 22:14:38.935796 RX DQS gating : PASS
6002 22:14:38.935902 RX DQ/DQS(RDDQC) : PASS
6003 22:14:38.939161 TX DQ/DQS : PASS
6004 22:14:38.942611 RX DATLAT : PASS
6005 22:14:38.942691 RX DQ/DQS(Engine): PASS
6006 22:14:38.945883 TX OE : NO K
6007 22:14:38.945962 All Pass.
6008 22:14:38.946030
6009 22:14:38.949321 CH 1, Rank 0
6010 22:14:38.949394 SW Impedance : PASS
6011 22:14:38.952471 DUTY Scan : NO K
6012 22:14:38.955555 ZQ Calibration : PASS
6013 22:14:38.955632 Jitter Meter : NO K
6014 22:14:38.959026 CBT Training : PASS
6015 22:14:38.962349 Write leveling : PASS
6016 22:14:38.962424 RX DQS gating : PASS
6017 22:14:38.965827 RX DQ/DQS(RDDQC) : PASS
6018 22:14:38.969069 TX DQ/DQS : PASS
6019 22:14:38.969144 RX DATLAT : PASS
6020 22:14:38.972449 RX DQ/DQS(Engine): PASS
6021 22:14:38.975905 TX OE : NO K
6022 22:14:38.975979 All Pass.
6023 22:14:38.976042
6024 22:14:38.976101 CH 1, Rank 1
6025 22:14:38.978848 SW Impedance : PASS
6026 22:14:38.982363 DUTY Scan : NO K
6027 22:14:38.982460 ZQ Calibration : PASS
6028 22:14:38.985834 Jitter Meter : NO K
6029 22:14:38.985903 CBT Training : PASS
6030 22:14:38.988962 Write leveling : PASS
6031 22:14:38.992543 RX DQS gating : PASS
6032 22:14:38.992617 RX DQ/DQS(RDDQC) : PASS
6033 22:14:38.995465 TX DQ/DQS : PASS
6034 22:14:38.998841 RX DATLAT : PASS
6035 22:14:38.998916 RX DQ/DQS(Engine): PASS
6036 22:14:39.001967 TX OE : NO K
6037 22:14:39.002036 All Pass.
6038 22:14:39.002096
6039 22:14:39.005428 DramC Write-DBI off
6040 22:14:39.009002 PER_BANK_REFRESH: Hybrid Mode
6041 22:14:39.009074 TX_TRACKING: ON
6042 22:14:39.018965 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6043 22:14:39.021913 [FAST_K] Save calibration result to emmc
6044 22:14:39.025414 dramc_set_vcore_voltage set vcore to 650000
6045 22:14:39.028750 Read voltage for 400, 6
6046 22:14:39.028832 Vio18 = 0
6047 22:14:39.028903 Vcore = 650000
6048 22:14:39.032454 Vdram = 0
6049 22:14:39.032544 Vddq = 0
6050 22:14:39.032616 Vmddr = 0
6051 22:14:39.039166 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6052 22:14:39.042049 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6053 22:14:39.045405 MEM_TYPE=3, freq_sel=20
6054 22:14:39.048906 sv_algorithm_assistance_LP4_800
6055 22:14:39.051807 ============ PULL DRAM RESETB DOWN ============
6056 22:14:39.055217 ========== PULL DRAM RESETB DOWN end =========
6057 22:14:39.061733 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6058 22:14:39.065486 ===================================
6059 22:14:39.065562 LPDDR4 DRAM CONFIGURATION
6060 22:14:39.069023 ===================================
6061 22:14:39.071850 EX_ROW_EN[0] = 0x0
6062 22:14:39.075060 EX_ROW_EN[1] = 0x0
6063 22:14:39.075146 LP4Y_EN = 0x0
6064 22:14:39.078548 WORK_FSP = 0x0
6065 22:14:39.078633 WL = 0x2
6066 22:14:39.082102 RL = 0x2
6067 22:14:39.082186 BL = 0x2
6068 22:14:39.085382 RPST = 0x0
6069 22:14:39.085467 RD_PRE = 0x0
6070 22:14:39.088416 WR_PRE = 0x1
6071 22:14:39.088501 WR_PST = 0x0
6072 22:14:39.091979 DBI_WR = 0x0
6073 22:14:39.092063 DBI_RD = 0x0
6074 22:14:39.095017 OTF = 0x1
6075 22:14:39.098589 ===================================
6076 22:14:39.101568 ===================================
6077 22:14:39.101652 ANA top config
6078 22:14:39.105046 ===================================
6079 22:14:39.108643 DLL_ASYNC_EN = 0
6080 22:14:39.111761 ALL_SLAVE_EN = 1
6081 22:14:39.115399 NEW_RANK_MODE = 1
6082 22:14:39.115485 DLL_IDLE_MODE = 1
6083 22:14:39.118306 LP45_APHY_COMB_EN = 1
6084 22:14:39.122354 TX_ODT_DIS = 1
6085 22:14:39.125404 NEW_8X_MODE = 1
6086 22:14:39.128567 ===================================
6087 22:14:39.131512 ===================================
6088 22:14:39.134862 data_rate = 800
6089 22:14:39.134946 CKR = 1
6090 22:14:39.138192 DQ_P2S_RATIO = 4
6091 22:14:39.141536 ===================================
6092 22:14:39.144918 CA_P2S_RATIO = 4
6093 22:14:39.148262 DQ_CA_OPEN = 0
6094 22:14:39.151626 DQ_SEMI_OPEN = 1
6095 22:14:39.155100 CA_SEMI_OPEN = 1
6096 22:14:39.155211 CA_FULL_RATE = 0
6097 22:14:39.157961 DQ_CKDIV4_EN = 0
6098 22:14:39.161303 CA_CKDIV4_EN = 1
6099 22:14:39.164676 CA_PREDIV_EN = 0
6100 22:14:39.168347 PH8_DLY = 0
6101 22:14:39.171372 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6102 22:14:39.171474 DQ_AAMCK_DIV = 0
6103 22:14:39.174865 CA_AAMCK_DIV = 0
6104 22:14:39.178259 CA_ADMCK_DIV = 4
6105 22:14:39.181685 DQ_TRACK_CA_EN = 0
6106 22:14:39.185103 CA_PICK = 800
6107 22:14:39.187984 CA_MCKIO = 400
6108 22:14:39.191687 MCKIO_SEMI = 400
6109 22:14:39.191764 PLL_FREQ = 3016
6110 22:14:39.194591 DQ_UI_PI_RATIO = 32
6111 22:14:39.198593 CA_UI_PI_RATIO = 32
6112 22:14:39.201367 ===================================
6113 22:14:39.204666 ===================================
6114 22:14:39.208032 memory_type:LPDDR4
6115 22:14:39.211141 GP_NUM : 10
6116 22:14:39.211233 SRAM_EN : 1
6117 22:14:39.214822 MD32_EN : 0
6118 22:14:39.217678 ===================================
6119 22:14:39.217757 [ANA_INIT] >>>>>>>>>>>>>>
6120 22:14:39.221322 <<<<<< [CONFIGURE PHASE]: ANA_TX
6121 22:14:39.224715 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6122 22:14:39.228107 ===================================
6123 22:14:39.231480 data_rate = 800,PCW = 0X7400
6124 22:14:39.234892 ===================================
6125 22:14:39.237843 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6126 22:14:39.244464 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6127 22:14:39.254935 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6128 22:14:39.261449 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6129 22:14:39.264306 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6130 22:14:39.267669 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6131 22:14:39.267746 [ANA_INIT] flow start
6132 22:14:39.270993 [ANA_INIT] PLL >>>>>>>>
6133 22:14:39.274654 [ANA_INIT] PLL <<<<<<<<
6134 22:14:39.274727 [ANA_INIT] MIDPI >>>>>>>>
6135 22:14:39.277672 [ANA_INIT] MIDPI <<<<<<<<
6136 22:14:39.281217 [ANA_INIT] DLL >>>>>>>>
6137 22:14:39.281302 [ANA_INIT] flow end
6138 22:14:39.287524 ============ LP4 DIFF to SE enter ============
6139 22:14:39.291129 ============ LP4 DIFF to SE exit ============
6140 22:14:39.294012 [ANA_INIT] <<<<<<<<<<<<<
6141 22:14:39.297536 [Flow] Enable top DCM control >>>>>
6142 22:14:39.300652 [Flow] Enable top DCM control <<<<<
6143 22:14:39.300737 Enable DLL master slave shuffle
6144 22:14:39.307738 ==============================================================
6145 22:14:39.310747 Gating Mode config
6146 22:14:39.314383 ==============================================================
6147 22:14:39.317261 Config description:
6148 22:14:39.327287 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6149 22:14:39.334354 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6150 22:14:39.337260 SELPH_MODE 0: By rank 1: By Phase
6151 22:14:39.344023 ==============================================================
6152 22:14:39.347443 GAT_TRACK_EN = 0
6153 22:14:39.350520 RX_GATING_MODE = 2
6154 22:14:39.353890 RX_GATING_TRACK_MODE = 2
6155 22:14:39.357502 SELPH_MODE = 1
6156 22:14:39.357587 PICG_EARLY_EN = 1
6157 22:14:39.360842 VALID_LAT_VALUE = 1
6158 22:14:39.367220 ==============================================================
6159 22:14:39.370480 Enter into Gating configuration >>>>
6160 22:14:39.374000 Exit from Gating configuration <<<<
6161 22:14:39.376939 Enter into DVFS_PRE_config >>>>>
6162 22:14:39.387303 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6163 22:14:39.390618 Exit from DVFS_PRE_config <<<<<
6164 22:14:39.394014 Enter into PICG configuration >>>>
6165 22:14:39.397155 Exit from PICG configuration <<<<
6166 22:14:39.401003 [RX_INPUT] configuration >>>>>
6167 22:14:39.403698 [RX_INPUT] configuration <<<<<
6168 22:14:39.407302 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6169 22:14:39.413868 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6170 22:14:39.420425 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6171 22:14:39.426819 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6172 22:14:39.433592 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6173 22:14:39.437132 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6174 22:14:39.443679 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6175 22:14:39.447052 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6176 22:14:39.450340 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6177 22:14:39.453767 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6178 22:14:39.460380 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6179 22:14:39.464207 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6180 22:14:39.467114 ===================================
6181 22:14:39.470137 LPDDR4 DRAM CONFIGURATION
6182 22:14:39.473563 ===================================
6183 22:14:39.473641 EX_ROW_EN[0] = 0x0
6184 22:14:39.476846 EX_ROW_EN[1] = 0x0
6185 22:14:39.476933 LP4Y_EN = 0x0
6186 22:14:39.480074 WORK_FSP = 0x0
6187 22:14:39.480191 WL = 0x2
6188 22:14:39.483422 RL = 0x2
6189 22:14:39.483500 BL = 0x2
6190 22:14:39.487037 RPST = 0x0
6191 22:14:39.487124 RD_PRE = 0x0
6192 22:14:39.490182 WR_PRE = 0x1
6193 22:14:39.490269 WR_PST = 0x0
6194 22:14:39.493513 DBI_WR = 0x0
6195 22:14:39.497119 DBI_RD = 0x0
6196 22:14:39.497211 OTF = 0x1
6197 22:14:39.499976 ===================================
6198 22:14:39.503509 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6199 22:14:39.506517 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6200 22:14:39.513538 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6201 22:14:39.517122 ===================================
6202 22:14:39.520116 LPDDR4 DRAM CONFIGURATION
6203 22:14:39.523161 ===================================
6204 22:14:39.523233 EX_ROW_EN[0] = 0x10
6205 22:14:39.526701 EX_ROW_EN[1] = 0x0
6206 22:14:39.526784 LP4Y_EN = 0x0
6207 22:14:39.530263 WORK_FSP = 0x0
6208 22:14:39.530344 WL = 0x2
6209 22:14:39.533289 RL = 0x2
6210 22:14:39.533363 BL = 0x2
6211 22:14:39.536796 RPST = 0x0
6212 22:14:39.536872 RD_PRE = 0x0
6213 22:14:39.539916 WR_PRE = 0x1
6214 22:14:39.539988 WR_PST = 0x0
6215 22:14:39.543135 DBI_WR = 0x0
6216 22:14:39.543211 DBI_RD = 0x0
6217 22:14:39.546744 OTF = 0x1
6218 22:14:39.549797 ===================================
6219 22:14:39.556441 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6220 22:14:39.559793 nWR fixed to 30
6221 22:14:39.563043 [ModeRegInit_LP4] CH0 RK0
6222 22:14:39.563125 [ModeRegInit_LP4] CH0 RK1
6223 22:14:39.566334 [ModeRegInit_LP4] CH1 RK0
6224 22:14:39.569630 [ModeRegInit_LP4] CH1 RK1
6225 22:14:39.569712 match AC timing 19
6226 22:14:39.576272 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6227 22:14:39.579958 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6228 22:14:39.582690 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6229 22:14:39.589603 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6230 22:14:39.592979 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6231 22:14:39.593113 ==
6232 22:14:39.596357 Dram Type= 6, Freq= 0, CH_0, rank 0
6233 22:14:39.599612 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6234 22:14:39.599692 ==
6235 22:14:39.605972 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6236 22:14:39.612531 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6237 22:14:39.616073 [CA 0] Center 36 (8~64) winsize 57
6238 22:14:39.619604 [CA 1] Center 36 (8~64) winsize 57
6239 22:14:39.622533 [CA 2] Center 36 (8~64) winsize 57
6240 22:14:39.626141 [CA 3] Center 36 (8~64) winsize 57
6241 22:14:39.626227 [CA 4] Center 36 (8~64) winsize 57
6242 22:14:39.629108 [CA 5] Center 36 (8~64) winsize 57
6243 22:14:39.629194
6244 22:14:39.635898 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6245 22:14:39.636019
6246 22:14:39.639533 [CATrainingPosCal] consider 1 rank data
6247 22:14:39.642827 u2DelayCellTimex100 = 270/100 ps
6248 22:14:39.645716 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6249 22:14:39.649204 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6250 22:14:39.653007 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6251 22:14:39.655664 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6252 22:14:39.659463 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6253 22:14:39.662287 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6254 22:14:39.662389
6255 22:14:39.666024 CA PerBit enable=1, Macro0, CA PI delay=36
6256 22:14:39.666103
6257 22:14:39.668987 [CBTSetCACLKResult] CA Dly = 36
6258 22:14:39.672884 CS Dly: 1 (0~32)
6259 22:14:39.672961 ==
6260 22:14:39.675605 Dram Type= 6, Freq= 0, CH_0, rank 1
6261 22:14:39.679501 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6262 22:14:39.679674 ==
6263 22:14:39.685485 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6264 22:14:39.692410 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6265 22:14:39.692535 [CA 0] Center 36 (8~64) winsize 57
6266 22:14:39.695509 [CA 1] Center 36 (8~64) winsize 57
6267 22:14:39.698728 [CA 2] Center 36 (8~64) winsize 57
6268 22:14:39.701985 [CA 3] Center 36 (8~64) winsize 57
6269 22:14:39.705569 [CA 4] Center 36 (8~64) winsize 57
6270 22:14:39.709257 [CA 5] Center 36 (8~64) winsize 57
6271 22:14:39.709333
6272 22:14:39.712473 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6273 22:14:39.712573
6274 22:14:39.715774 [CATrainingPosCal] consider 2 rank data
6275 22:14:39.719468 u2DelayCellTimex100 = 270/100 ps
6276 22:14:39.722241 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6277 22:14:39.725736 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6278 22:14:39.732709 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6279 22:14:39.735513 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6280 22:14:39.739205 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6281 22:14:39.742245 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6282 22:14:39.742347
6283 22:14:39.745688 CA PerBit enable=1, Macro0, CA PI delay=36
6284 22:14:39.745764
6285 22:14:39.749120 [CBTSetCACLKResult] CA Dly = 36
6286 22:14:39.749197 CS Dly: 1 (0~32)
6287 22:14:39.749260
6288 22:14:39.752082 ----->DramcWriteLeveling(PI) begin...
6289 22:14:39.755565 ==
6290 22:14:39.758971 Dram Type= 6, Freq= 0, CH_0, rank 0
6291 22:14:39.762206 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6292 22:14:39.762284 ==
6293 22:14:39.765498 Write leveling (Byte 0): 40 => 8
6294 22:14:39.768942 Write leveling (Byte 1): 32 => 0
6295 22:14:39.772247 DramcWriteLeveling(PI) end<-----
6296 22:14:39.772325
6297 22:14:39.772389 ==
6298 22:14:39.775600 Dram Type= 6, Freq= 0, CH_0, rank 0
6299 22:14:39.778990 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6300 22:14:39.779078 ==
6301 22:14:39.781971 [Gating] SW mode calibration
6302 22:14:39.788723 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6303 22:14:39.792151 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6304 22:14:39.798982 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6305 22:14:39.802247 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6306 22:14:39.805498 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6307 22:14:39.812019 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6308 22:14:39.815589 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6309 22:14:39.818589 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6310 22:14:39.825141 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6311 22:14:39.828458 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6312 22:14:39.832097 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6313 22:14:39.835916 Total UI for P1: 0, mck2ui 16
6314 22:14:39.838647 best dqsien dly found for B0: ( 0, 14, 24)
6315 22:14:39.842290 Total UI for P1: 0, mck2ui 16
6316 22:14:39.845214 best dqsien dly found for B1: ( 0, 14, 24)
6317 22:14:39.848771 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6318 22:14:39.851638 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6319 22:14:39.851748
6320 22:14:39.858613 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6321 22:14:39.862104 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6322 22:14:39.865323 [Gating] SW calibration Done
6323 22:14:39.865401 ==
6324 22:14:39.868857 Dram Type= 6, Freq= 0, CH_0, rank 0
6325 22:14:39.871909 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6326 22:14:39.871988 ==
6327 22:14:39.872069 RX Vref Scan: 0
6328 22:14:39.872133
6329 22:14:39.875591 RX Vref 0 -> 0, step: 1
6330 22:14:39.875664
6331 22:14:39.878833 RX Delay -410 -> 252, step: 16
6332 22:14:39.882071 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6333 22:14:39.888438 iDelay=230, Bit 1, Center -27 (-282 ~ 229) 512
6334 22:14:39.891696 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6335 22:14:39.895070 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6336 22:14:39.898491 iDelay=230, Bit 4, Center -19 (-266 ~ 229) 496
6337 22:14:39.902086 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6338 22:14:39.908573 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6339 22:14:39.911908 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6340 22:14:39.915126 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6341 22:14:39.918761 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6342 22:14:39.925213 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6343 22:14:39.928742 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6344 22:14:39.932350 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6345 22:14:39.935373 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6346 22:14:39.941792 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6347 22:14:39.945389 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6348 22:14:39.945471 ==
6349 22:14:39.948823 Dram Type= 6, Freq= 0, CH_0, rank 0
6350 22:14:39.951857 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6351 22:14:39.951950 ==
6352 22:14:39.955207 DQS Delay:
6353 22:14:39.955312 DQS0 = 43, DQS1 = 51
6354 22:14:39.958608 DQM Delay:
6355 22:14:39.958696 DQM0 = 14, DQM1 = 9
6356 22:14:39.958760 DQ Delay:
6357 22:14:39.961623 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6358 22:14:39.965268 DQ4 =24, DQ5 =0, DQ6 =24, DQ7 =24
6359 22:14:39.968202 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6360 22:14:39.971749 DQ12 =8, DQ13 =16, DQ14 =16, DQ15 =16
6361 22:14:39.971848
6362 22:14:39.971954
6363 22:14:39.972046 ==
6364 22:14:39.975050 Dram Type= 6, Freq= 0, CH_0, rank 0
6365 22:14:39.981651 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6366 22:14:39.981748 ==
6367 22:14:39.981817
6368 22:14:39.981882
6369 22:14:39.981960 TX Vref Scan disable
6370 22:14:39.984986 == TX Byte 0 ==
6371 22:14:39.988280 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6372 22:14:39.992459 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6373 22:14:39.995012 == TX Byte 1 ==
6374 22:14:39.998276 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6375 22:14:40.001544 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6376 22:14:40.001625 ==
6377 22:14:40.005304 Dram Type= 6, Freq= 0, CH_0, rank 0
6378 22:14:40.011411 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6379 22:14:40.011500 ==
6380 22:14:40.011614
6381 22:14:40.011706
6382 22:14:40.015108 TX Vref Scan disable
6383 22:14:40.015180 == TX Byte 0 ==
6384 22:14:40.018390 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6385 22:14:40.024907 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6386 22:14:40.024999 == TX Byte 1 ==
6387 22:14:40.027820 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6388 22:14:40.034895 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6389 22:14:40.034986
6390 22:14:40.035056 [DATLAT]
6391 22:14:40.035121 Freq=400, CH0 RK0
6392 22:14:40.035189
6393 22:14:40.037970 DATLAT Default: 0xf
6394 22:14:40.038076 0, 0xFFFF, sum = 0
6395 22:14:40.041453 1, 0xFFFF, sum = 0
6396 22:14:40.041542 2, 0xFFFF, sum = 0
6397 22:14:40.044606 3, 0xFFFF, sum = 0
6398 22:14:40.048160 4, 0xFFFF, sum = 0
6399 22:14:40.048252 5, 0xFFFF, sum = 0
6400 22:14:40.051367 6, 0xFFFF, sum = 0
6401 22:14:40.051486 7, 0xFFFF, sum = 0
6402 22:14:40.054605 8, 0xFFFF, sum = 0
6403 22:14:40.054686 9, 0xFFFF, sum = 0
6404 22:14:40.057514 10, 0xFFFF, sum = 0
6405 22:14:40.057599 11, 0xFFFF, sum = 0
6406 22:14:40.061426 12, 0xFFFF, sum = 0
6407 22:14:40.061536 13, 0x0, sum = 1
6408 22:14:40.064572 14, 0x0, sum = 2
6409 22:14:40.064665 15, 0x0, sum = 3
6410 22:14:40.067682 16, 0x0, sum = 4
6411 22:14:40.067791 best_step = 14
6412 22:14:40.067855
6413 22:14:40.067923 ==
6414 22:14:40.071400 Dram Type= 6, Freq= 0, CH_0, rank 0
6415 22:14:40.074508 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6416 22:14:40.078126 ==
6417 22:14:40.078206 RX Vref Scan: 1
6418 22:14:40.078273
6419 22:14:40.081098 RX Vref 0 -> 0, step: 1
6420 22:14:40.081182
6421 22:14:40.084435 RX Delay -343 -> 252, step: 8
6422 22:14:40.084520
6423 22:14:40.087587 Set Vref, RX VrefLevel [Byte0]: 52
6424 22:14:40.091306 [Byte1]: 51
6425 22:14:40.091427
6426 22:14:40.094330 Final RX Vref Byte 0 = 52 to rank0
6427 22:14:40.097659 Final RX Vref Byte 1 = 51 to rank0
6428 22:14:40.100883 Final RX Vref Byte 0 = 52 to rank1
6429 22:14:40.104180 Final RX Vref Byte 1 = 51 to rank1==
6430 22:14:40.107486 Dram Type= 6, Freq= 0, CH_0, rank 0
6431 22:14:40.110728 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6432 22:14:40.110849 ==
6433 22:14:40.114404 DQS Delay:
6434 22:14:40.114525 DQS0 = 44, DQS1 = 60
6435 22:14:40.117765 DQM Delay:
6436 22:14:40.117857 DQM0 = 11, DQM1 = 15
6437 22:14:40.117962 DQ Delay:
6438 22:14:40.121028 DQ0 =12, DQ1 =12, DQ2 =4, DQ3 =8
6439 22:14:40.124121 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6440 22:14:40.127752 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =12
6441 22:14:40.130670 DQ12 =20, DQ13 =16, DQ14 =28, DQ15 =28
6442 22:14:40.130749
6443 22:14:40.130824
6444 22:14:40.140940 [DQSOSCAuto] RK0, (LSB)MR18= 0x8654, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 393 ps
6445 22:14:40.144604 CH0 RK0: MR19=C0C, MR18=8654
6446 22:14:40.147537 CH0_RK0: MR19=0xC0C, MR18=0x8654, DQSOSC=393, MR23=63, INC=382, DEC=254
6447 22:14:40.147617 ==
6448 22:14:40.150790 Dram Type= 6, Freq= 0, CH_0, rank 1
6449 22:14:40.157614 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6450 22:14:40.157697 ==
6451 22:14:40.161100 [Gating] SW mode calibration
6452 22:14:40.167645 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6453 22:14:40.171037 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6454 22:14:40.177462 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6455 22:14:40.180870 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6456 22:14:40.184527 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6457 22:14:40.187502 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6458 22:14:40.194652 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6459 22:14:40.197933 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6460 22:14:40.201180 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6461 22:14:40.207776 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6462 22:14:40.211281 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6463 22:14:40.214495 Total UI for P1: 0, mck2ui 16
6464 22:14:40.217750 best dqsien dly found for B0: ( 0, 14, 24)
6465 22:14:40.220681 Total UI for P1: 0, mck2ui 16
6466 22:14:40.223959 best dqsien dly found for B1: ( 0, 14, 24)
6467 22:14:40.227253 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6468 22:14:40.230516 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6469 22:14:40.230599
6470 22:14:40.234003 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6471 22:14:40.240545 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6472 22:14:40.240652 [Gating] SW calibration Done
6473 22:14:40.240759 ==
6474 22:14:40.244180 Dram Type= 6, Freq= 0, CH_0, rank 1
6475 22:14:40.250636 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6476 22:14:40.250719 ==
6477 22:14:40.250787 RX Vref Scan: 0
6478 22:14:40.250887
6479 22:14:40.253600 RX Vref 0 -> 0, step: 1
6480 22:14:40.253702
6481 22:14:40.257178 RX Delay -410 -> 252, step: 16
6482 22:14:40.260594 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6483 22:14:40.263572 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6484 22:14:40.270660 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6485 22:14:40.273640 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6486 22:14:40.276974 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6487 22:14:40.280473 iDelay=230, Bit 5, Center -43 (-282 ~ 197) 480
6488 22:14:40.287066 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6489 22:14:40.290723 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6490 22:14:40.293615 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6491 22:14:40.297303 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6492 22:14:40.303717 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6493 22:14:40.307080 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6494 22:14:40.310626 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6495 22:14:40.313824 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6496 22:14:40.320498 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6497 22:14:40.323707 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6498 22:14:40.323792 ==
6499 22:14:40.326961 Dram Type= 6, Freq= 0, CH_0, rank 1
6500 22:14:40.330484 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6501 22:14:40.330572 ==
6502 22:14:40.333807 DQS Delay:
6503 22:14:40.333891 DQS0 = 43, DQS1 = 51
6504 22:14:40.337199 DQM Delay:
6505 22:14:40.337273 DQM0 = 11, DQM1 = 10
6506 22:14:40.337335 DQ Delay:
6507 22:14:40.340305 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6508 22:14:40.343386 DQ4 =8, DQ5 =0, DQ6 =24, DQ7 =24
6509 22:14:40.346890 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6510 22:14:40.350290 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6511 22:14:40.350367
6512 22:14:40.350430
6513 22:14:40.350491 ==
6514 22:14:40.353848 Dram Type= 6, Freq= 0, CH_0, rank 1
6515 22:14:40.360420 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6516 22:14:40.360510 ==
6517 22:14:40.360578
6518 22:14:40.360639
6519 22:14:40.360698 TX Vref Scan disable
6520 22:14:40.363996 == TX Byte 0 ==
6521 22:14:40.366966 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6522 22:14:40.370304 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6523 22:14:40.373271 == TX Byte 1 ==
6524 22:14:40.376626 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6525 22:14:40.380245 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6526 22:14:40.380319 ==
6527 22:14:40.383682 Dram Type= 6, Freq= 0, CH_0, rank 1
6528 22:14:40.390198 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6529 22:14:40.390306 ==
6530 22:14:40.390399
6531 22:14:40.390494
6532 22:14:40.390584 TX Vref Scan disable
6533 22:14:40.393613 == TX Byte 0 ==
6534 22:14:40.396622 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6535 22:14:40.400135 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6536 22:14:40.403510 == TX Byte 1 ==
6537 22:14:40.406469 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6538 22:14:40.410069 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6539 22:14:40.410154
6540 22:14:40.413326 [DATLAT]
6541 22:14:40.413409 Freq=400, CH0 RK1
6542 22:14:40.413477
6543 22:14:40.416949 DATLAT Default: 0xe
6544 22:14:40.417034 0, 0xFFFF, sum = 0
6545 22:14:40.419955 1, 0xFFFF, sum = 0
6546 22:14:40.420040 2, 0xFFFF, sum = 0
6547 22:14:40.423317 3, 0xFFFF, sum = 0
6548 22:14:40.423436 4, 0xFFFF, sum = 0
6549 22:14:40.426672 5, 0xFFFF, sum = 0
6550 22:14:40.426757 6, 0xFFFF, sum = 0
6551 22:14:40.429773 7, 0xFFFF, sum = 0
6552 22:14:40.429859 8, 0xFFFF, sum = 0
6553 22:14:40.433052 9, 0xFFFF, sum = 0
6554 22:14:40.433164 10, 0xFFFF, sum = 0
6555 22:14:40.436643 11, 0xFFFF, sum = 0
6556 22:14:40.436729 12, 0xFFFF, sum = 0
6557 22:14:40.440015 13, 0x0, sum = 1
6558 22:14:40.440100 14, 0x0, sum = 2
6559 22:14:40.443475 15, 0x0, sum = 3
6560 22:14:40.443595 16, 0x0, sum = 4
6561 22:14:40.446937 best_step = 14
6562 22:14:40.447020
6563 22:14:40.447096 ==
6564 22:14:40.449858 Dram Type= 6, Freq= 0, CH_0, rank 1
6565 22:14:40.453341 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6566 22:14:40.453450 ==
6567 22:14:40.456324 RX Vref Scan: 0
6568 22:14:40.456411
6569 22:14:40.456499 RX Vref 0 -> 0, step: 1
6570 22:14:40.456588
6571 22:14:40.460088 RX Delay -343 -> 252, step: 8
6572 22:14:40.467977 iDelay=217, Bit 0, Center -32 (-271 ~ 208) 480
6573 22:14:40.471179 iDelay=217, Bit 1, Center -32 (-271 ~ 208) 480
6574 22:14:40.474832 iDelay=217, Bit 2, Center -36 (-271 ~ 200) 472
6575 22:14:40.478263 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6576 22:14:40.484255 iDelay=217, Bit 4, Center -36 (-271 ~ 200) 472
6577 22:14:40.487671 iDelay=217, Bit 5, Center -44 (-279 ~ 192) 472
6578 22:14:40.491228 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6579 22:14:40.494823 iDelay=217, Bit 7, Center -28 (-263 ~ 208) 472
6580 22:14:40.501220 iDelay=217, Bit 8, Center -60 (-303 ~ 184) 488
6581 22:14:40.504634 iDelay=217, Bit 9, Center -56 (-303 ~ 192) 496
6582 22:14:40.507515 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6583 22:14:40.511289 iDelay=217, Bit 11, Center -56 (-295 ~ 184) 480
6584 22:14:40.517528 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6585 22:14:40.520837 iDelay=217, Bit 13, Center -40 (-279 ~ 200) 480
6586 22:14:40.524535 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6587 22:14:40.530886 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6588 22:14:40.530966 ==
6589 22:14:40.534151 Dram Type= 6, Freq= 0, CH_0, rank 1
6590 22:14:40.537875 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6591 22:14:40.537964 ==
6592 22:14:40.538059 DQS Delay:
6593 22:14:40.541265 DQS0 = 44, DQS1 = 60
6594 22:14:40.541347 DQM Delay:
6595 22:14:40.544181 DQM0 = 10, DQM1 = 13
6596 22:14:40.544261 DQ Delay:
6597 22:14:40.547461 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =8
6598 22:14:40.550929 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6599 22:14:40.554558 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =4
6600 22:14:40.558067 DQ12 =16, DQ13 =20, DQ14 =24, DQ15 =24
6601 22:14:40.558149
6602 22:14:40.558235
6603 22:14:40.564409 [DQSOSCAuto] RK1, (LSB)MR18= 0x9262, (MSB)MR19= 0xc0c, tDQSOscB0 = 397 ps tDQSOscB1 = 391 ps
6604 22:14:40.567856 CH0 RK1: MR19=C0C, MR18=9262
6605 22:14:40.574083 CH0_RK1: MR19=0xC0C, MR18=0x9262, DQSOSC=391, MR23=63, INC=386, DEC=257
6606 22:14:40.577989 [RxdqsGatingPostProcess] freq 400
6607 22:14:40.580812 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6608 22:14:40.584468 best DQS0 dly(2T, 0.5T) = (0, 10)
6609 22:14:40.587926 best DQS1 dly(2T, 0.5T) = (0, 10)
6610 22:14:40.590983 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6611 22:14:40.594377 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6612 22:14:40.597850 best DQS0 dly(2T, 0.5T) = (0, 10)
6613 22:14:40.600822 best DQS1 dly(2T, 0.5T) = (0, 10)
6614 22:14:40.603925 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6615 22:14:40.607566 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6616 22:14:40.611053 Pre-setting of DQS Precalculation
6617 22:14:40.614247 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6618 22:14:40.617167 ==
6619 22:14:40.620494 Dram Type= 6, Freq= 0, CH_1, rank 0
6620 22:14:40.623909 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6621 22:14:40.623997 ==
6622 22:14:40.627276 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6623 22:14:40.633976 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6624 22:14:40.637174 [CA 0] Center 36 (8~64) winsize 57
6625 22:14:40.640560 [CA 1] Center 36 (8~64) winsize 57
6626 22:14:40.644102 [CA 2] Center 36 (8~64) winsize 57
6627 22:14:40.647870 [CA 3] Center 36 (8~64) winsize 57
6628 22:14:40.650557 [CA 4] Center 36 (8~64) winsize 57
6629 22:14:40.653987 [CA 5] Center 36 (8~64) winsize 57
6630 22:14:40.654073
6631 22:14:40.657440 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6632 22:14:40.657526
6633 22:14:40.660903 [CATrainingPosCal] consider 1 rank data
6634 22:14:40.664075 u2DelayCellTimex100 = 270/100 ps
6635 22:14:40.667095 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6636 22:14:40.670516 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6637 22:14:40.674205 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6638 22:14:40.677147 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6639 22:14:40.683673 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6640 22:14:40.687309 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6641 22:14:40.687431
6642 22:14:40.690692 CA PerBit enable=1, Macro0, CA PI delay=36
6643 22:14:40.690821
6644 22:14:40.693819 [CBTSetCACLKResult] CA Dly = 36
6645 22:14:40.693941 CS Dly: 1 (0~32)
6646 22:14:40.694044 ==
6647 22:14:40.697372 Dram Type= 6, Freq= 0, CH_1, rank 1
6648 22:14:40.703717 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6649 22:14:40.703803 ==
6650 22:14:40.707501 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6651 22:14:40.713610 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6652 22:14:40.717174 [CA 0] Center 36 (8~64) winsize 57
6653 22:14:40.720752 [CA 1] Center 36 (8~64) winsize 57
6654 22:14:40.723600 [CA 2] Center 36 (8~64) winsize 57
6655 22:14:40.726927 [CA 3] Center 36 (8~64) winsize 57
6656 22:14:40.730175 [CA 4] Center 36 (8~64) winsize 57
6657 22:14:40.733527 [CA 5] Center 36 (8~64) winsize 57
6658 22:14:40.733632
6659 22:14:40.737082 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6660 22:14:40.737160
6661 22:14:40.740180 [CATrainingPosCal] consider 2 rank data
6662 22:14:40.743880 u2DelayCellTimex100 = 270/100 ps
6663 22:14:40.747067 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6664 22:14:40.749885 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6665 22:14:40.753490 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6666 22:14:40.756919 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6667 22:14:40.760168 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6668 22:14:40.763847 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6669 22:14:40.763958
6670 22:14:40.770224 CA PerBit enable=1, Macro0, CA PI delay=36
6671 22:14:40.770307
6672 22:14:40.770389 [CBTSetCACLKResult] CA Dly = 36
6673 22:14:40.773698 CS Dly: 1 (0~32)
6674 22:14:40.773781
6675 22:14:40.776549 ----->DramcWriteLeveling(PI) begin...
6676 22:14:40.776634 ==
6677 22:14:40.780177 Dram Type= 6, Freq= 0, CH_1, rank 0
6678 22:14:40.783748 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6679 22:14:40.783831 ==
6680 22:14:40.786567 Write leveling (Byte 0): 40 => 8
6681 22:14:40.789949 Write leveling (Byte 1): 40 => 8
6682 22:14:40.793510 DramcWriteLeveling(PI) end<-----
6683 22:14:40.793594
6684 22:14:40.793659 ==
6685 22:14:40.796633 Dram Type= 6, Freq= 0, CH_1, rank 0
6686 22:14:40.799891 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6687 22:14:40.803378 ==
6688 22:14:40.803488 [Gating] SW mode calibration
6689 22:14:40.810430 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6690 22:14:40.816697 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6691 22:14:40.820378 0 11 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
6692 22:14:40.826303 0 11 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
6693 22:14:40.829600 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6694 22:14:40.832933 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6695 22:14:40.839828 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6696 22:14:40.843102 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6697 22:14:40.846467 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6698 22:14:40.853405 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6699 22:14:40.856327 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6700 22:14:40.859831 Total UI for P1: 0, mck2ui 16
6701 22:14:40.862918 best dqsien dly found for B0: ( 0, 14, 24)
6702 22:14:40.866554 Total UI for P1: 0, mck2ui 16
6703 22:14:40.869698 best dqsien dly found for B1: ( 0, 14, 24)
6704 22:14:40.872754 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6705 22:14:40.876050 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6706 22:14:40.876157
6707 22:14:40.879555 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6708 22:14:40.883232 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6709 22:14:40.886602 [Gating] SW calibration Done
6710 22:14:40.886711 ==
6711 22:14:40.889604 Dram Type= 6, Freq= 0, CH_1, rank 0
6712 22:14:40.893138 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6713 22:14:40.893247 ==
6714 22:14:40.896044 RX Vref Scan: 0
6715 22:14:40.896135
6716 22:14:40.899607 RX Vref 0 -> 0, step: 1
6717 22:14:40.899712
6718 22:14:40.903024 RX Delay -410 -> 252, step: 16
6719 22:14:40.906068 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6720 22:14:40.909418 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6721 22:14:40.913441 iDelay=230, Bit 2, Center -43 (-282 ~ 197) 480
6722 22:14:40.919470 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6723 22:14:40.922905 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6724 22:14:40.925813 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6725 22:14:40.929156 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6726 22:14:40.936293 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6727 22:14:40.939490 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6728 22:14:40.942678 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6729 22:14:40.946538 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6730 22:14:40.952485 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6731 22:14:40.955707 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6732 22:14:40.959238 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6733 22:14:40.962658 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6734 22:14:40.968943 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6735 22:14:40.969028 ==
6736 22:14:40.972455 Dram Type= 6, Freq= 0, CH_1, rank 0
6737 22:14:40.975928 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6738 22:14:40.976004 ==
6739 22:14:40.976070 DQS Delay:
6740 22:14:40.978954 DQS0 = 43, DQS1 = 59
6741 22:14:40.979029 DQM Delay:
6742 22:14:40.982556 DQM0 = 12, DQM1 = 16
6743 22:14:40.982655 DQ Delay:
6744 22:14:40.985979 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6745 22:14:40.988883 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6746 22:14:40.992563 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6747 22:14:40.995523 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6748 22:14:40.995629
6749 22:14:40.995717
6750 22:14:40.995809 ==
6751 22:14:40.999025 Dram Type= 6, Freq= 0, CH_1, rank 0
6752 22:14:41.002670 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6753 22:14:41.002778 ==
6754 22:14:41.006068
6755 22:14:41.006167
6756 22:14:41.006261 TX Vref Scan disable
6757 22:14:41.009116 == TX Byte 0 ==
6758 22:14:41.012070 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6759 22:14:41.015691 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6760 22:14:41.019026 == TX Byte 1 ==
6761 22:14:41.022152 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6762 22:14:41.025611 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6763 22:14:41.025715 ==
6764 22:14:41.028588 Dram Type= 6, Freq= 0, CH_1, rank 0
6765 22:14:41.032143 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6766 22:14:41.035185 ==
6767 22:14:41.035278
6768 22:14:41.035404
6769 22:14:41.035497 TX Vref Scan disable
6770 22:14:41.039106 == TX Byte 0 ==
6771 22:14:41.041701 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6772 22:14:41.045028 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6773 22:14:41.048742 == TX Byte 1 ==
6774 22:14:41.051736 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6775 22:14:41.055036 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6776 22:14:41.055146
6777 22:14:41.058630 [DATLAT]
6778 22:14:41.058734 Freq=400, CH1 RK0
6779 22:14:41.058828
6780 22:14:41.061985 DATLAT Default: 0xf
6781 22:14:41.062064 0, 0xFFFF, sum = 0
6782 22:14:41.065444 1, 0xFFFF, sum = 0
6783 22:14:41.065527 2, 0xFFFF, sum = 0
6784 22:14:41.068308 3, 0xFFFF, sum = 0
6785 22:14:41.068387 4, 0xFFFF, sum = 0
6786 22:14:41.072212 5, 0xFFFF, sum = 0
6787 22:14:41.072289 6, 0xFFFF, sum = 0
6788 22:14:41.075390 7, 0xFFFF, sum = 0
6789 22:14:41.075468 8, 0xFFFF, sum = 0
6790 22:14:41.078233 9, 0xFFFF, sum = 0
6791 22:14:41.078342 10, 0xFFFF, sum = 0
6792 22:14:41.082030 11, 0xFFFF, sum = 0
6793 22:14:41.082108 12, 0xFFFF, sum = 0
6794 22:14:41.085147 13, 0x0, sum = 1
6795 22:14:41.085230 14, 0x0, sum = 2
6796 22:14:41.088797 15, 0x0, sum = 3
6797 22:14:41.088876 16, 0x0, sum = 4
6798 22:14:41.091593 best_step = 14
6799 22:14:41.091668
6800 22:14:41.091731 ==
6801 22:14:41.095033 Dram Type= 6, Freq= 0, CH_1, rank 0
6802 22:14:41.098521 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6803 22:14:41.098625 ==
6804 22:14:41.102189 RX Vref Scan: 1
6805 22:14:41.102265
6806 22:14:41.102329 RX Vref 0 -> 0, step: 1
6807 22:14:41.102390
6808 22:14:41.105123 RX Delay -359 -> 252, step: 8
6809 22:14:41.105198
6810 22:14:41.108717 Set Vref, RX VrefLevel [Byte0]: 59
6811 22:14:41.111717 [Byte1]: 53
6812 22:14:41.116654
6813 22:14:41.116759 Final RX Vref Byte 0 = 59 to rank0
6814 22:14:41.119606 Final RX Vref Byte 1 = 53 to rank0
6815 22:14:41.123266 Final RX Vref Byte 0 = 59 to rank1
6816 22:14:41.126162 Final RX Vref Byte 1 = 53 to rank1==
6817 22:14:41.129742 Dram Type= 6, Freq= 0, CH_1, rank 0
6818 22:14:41.135955 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6819 22:14:41.136045 ==
6820 22:14:41.136115 DQS Delay:
6821 22:14:41.139300 DQS0 = 48, DQS1 = 60
6822 22:14:41.139394 DQM Delay:
6823 22:14:41.139458 DQM0 = 12, DQM1 = 13
6824 22:14:41.142680 DQ Delay:
6825 22:14:41.146010 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6826 22:14:41.146116 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =12
6827 22:14:41.149330 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =12
6828 22:14:41.153098 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =20
6829 22:14:41.156050
6830 22:14:41.156128
6831 22:14:41.162737 [DQSOSCAuto] RK0, (LSB)MR18= 0x8e36, (MSB)MR19= 0xc0c, tDQSOscB0 = 403 ps tDQSOscB1 = 392 ps
6832 22:14:41.166313 CH1 RK0: MR19=C0C, MR18=8E36
6833 22:14:41.172840 CH1_RK0: MR19=0xC0C, MR18=0x8E36, DQSOSC=392, MR23=63, INC=384, DEC=256
6834 22:14:41.172925 ==
6835 22:14:41.176086 Dram Type= 6, Freq= 0, CH_1, rank 1
6836 22:14:41.179558 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6837 22:14:41.179633 ==
6838 22:14:41.182511 [Gating] SW mode calibration
6839 22:14:41.189028 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6840 22:14:41.195961 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6841 22:14:41.198897 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6842 22:14:41.202391 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6843 22:14:41.208955 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6844 22:14:41.212379 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6845 22:14:41.215956 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6846 22:14:41.222478 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6847 22:14:41.225549 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6848 22:14:41.229069 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6849 22:14:41.235452 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6850 22:14:41.235538 Total UI for P1: 0, mck2ui 16
6851 22:14:41.242125 best dqsien dly found for B0: ( 0, 14, 24)
6852 22:14:41.242234 Total UI for P1: 0, mck2ui 16
6853 22:14:41.245693 best dqsien dly found for B1: ( 0, 14, 24)
6854 22:14:41.252366 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6855 22:14:41.255830 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6856 22:14:41.255915
6857 22:14:41.258924 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6858 22:14:41.261891 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6859 22:14:41.265296 [Gating] SW calibration Done
6860 22:14:41.265397 ==
6861 22:14:41.268577 Dram Type= 6, Freq= 0, CH_1, rank 1
6862 22:14:41.272202 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6863 22:14:41.272284 ==
6864 22:14:41.275641 RX Vref Scan: 0
6865 22:14:41.275743
6866 22:14:41.275840 RX Vref 0 -> 0, step: 1
6867 22:14:41.275932
6868 22:14:41.279031 RX Delay -410 -> 252, step: 16
6869 22:14:41.285731 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6870 22:14:41.288700 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6871 22:14:41.292278 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6872 22:14:41.295793 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6873 22:14:41.301726 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6874 22:14:41.305132 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6875 22:14:41.309076 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6876 22:14:41.311754 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6877 22:14:41.318727 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6878 22:14:41.321673 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6879 22:14:41.325175 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6880 22:14:41.328876 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6881 22:14:41.335585 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6882 22:14:41.338457 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6883 22:14:41.342029 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6884 22:14:41.345112 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6885 22:14:41.345202 ==
6886 22:14:41.348424 Dram Type= 6, Freq= 0, CH_1, rank 1
6887 22:14:41.355140 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6888 22:14:41.355248 ==
6889 22:14:41.355358 DQS Delay:
6890 22:14:41.358575 DQS0 = 43, DQS1 = 59
6891 22:14:41.358659 DQM Delay:
6892 22:14:41.361531 DQM0 = 9, DQM1 = 19
6893 22:14:41.361640 DQ Delay:
6894 22:14:41.364898 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =8
6895 22:14:41.368193 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6896 22:14:41.368271 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6897 22:14:41.371604 DQ12 =24, DQ13 =32, DQ14 =32, DQ15 =32
6898 22:14:41.375471
6899 22:14:41.375555
6900 22:14:41.375623 ==
6901 22:14:41.378345 Dram Type= 6, Freq= 0, CH_1, rank 1
6902 22:14:41.381810 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6903 22:14:41.381888 ==
6904 22:14:41.381959
6905 22:14:41.382042
6906 22:14:41.385085 TX Vref Scan disable
6907 22:14:41.385162 == TX Byte 0 ==
6908 22:14:41.388373 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6909 22:14:41.394882 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6910 22:14:41.395002 == TX Byte 1 ==
6911 22:14:41.398511 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6912 22:14:41.405327 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6913 22:14:41.405429 ==
6914 22:14:41.408262 Dram Type= 6, Freq= 0, CH_1, rank 1
6915 22:14:41.411923 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6916 22:14:41.412001 ==
6917 22:14:41.412076
6918 22:14:41.412138
6919 22:14:41.414978 TX Vref Scan disable
6920 22:14:41.415059 == TX Byte 0 ==
6921 22:14:41.418145 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6922 22:14:41.424894 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6923 22:14:41.424999 == TX Byte 1 ==
6924 22:14:41.428388 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6925 22:14:41.434679 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6926 22:14:41.434763
6927 22:14:41.434839 [DATLAT]
6928 22:14:41.434903 Freq=400, CH1 RK1
6929 22:14:41.434965
6930 22:14:41.438244 DATLAT Default: 0xe
6931 22:14:41.441819 0, 0xFFFF, sum = 0
6932 22:14:41.441912 1, 0xFFFF, sum = 0
6933 22:14:41.444673 2, 0xFFFF, sum = 0
6934 22:14:41.444796 3, 0xFFFF, sum = 0
6935 22:14:41.448201 4, 0xFFFF, sum = 0
6936 22:14:41.448304 5, 0xFFFF, sum = 0
6937 22:14:41.451212 6, 0xFFFF, sum = 0
6938 22:14:41.451296 7, 0xFFFF, sum = 0
6939 22:14:41.454609 8, 0xFFFF, sum = 0
6940 22:14:41.454692 9, 0xFFFF, sum = 0
6941 22:14:41.458051 10, 0xFFFF, sum = 0
6942 22:14:41.458132 11, 0xFFFF, sum = 0
6943 22:14:41.461349 12, 0xFFFF, sum = 0
6944 22:14:41.461439 13, 0x0, sum = 1
6945 22:14:41.465006 14, 0x0, sum = 2
6946 22:14:41.465094 15, 0x0, sum = 3
6947 22:14:41.467859 16, 0x0, sum = 4
6948 22:14:41.467956 best_step = 14
6949 22:14:41.468042
6950 22:14:41.468125 ==
6951 22:14:41.471162 Dram Type= 6, Freq= 0, CH_1, rank 1
6952 22:14:41.474960 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6953 22:14:41.478383 ==
6954 22:14:41.478473 RX Vref Scan: 0
6955 22:14:41.478568
6956 22:14:41.481296 RX Vref 0 -> 0, step: 1
6957 22:14:41.481379
6958 22:14:41.484521 RX Delay -359 -> 252, step: 8
6959 22:14:41.491264 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6960 22:14:41.494797 iDelay=217, Bit 1, Center -44 (-287 ~ 200) 488
6961 22:14:41.497735 iDelay=217, Bit 2, Center -52 (-295 ~ 192) 488
6962 22:14:41.501367 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6963 22:14:41.507914 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6964 22:14:41.511541 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6965 22:14:41.514426 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6966 22:14:41.518014 iDelay=217, Bit 7, Center -44 (-287 ~ 200) 488
6967 22:14:41.524510 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
6968 22:14:41.528311 iDelay=217, Bit 9, Center -56 (-303 ~ 192) 496
6969 22:14:41.530964 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6970 22:14:41.534504 iDelay=217, Bit 11, Center -56 (-303 ~ 192) 496
6971 22:14:41.541475 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6972 22:14:41.544814 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6973 22:14:41.547876 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6974 22:14:41.551400 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6975 22:14:41.551491 ==
6976 22:14:41.554347 Dram Type= 6, Freq= 0, CH_1, rank 1
6977 22:14:41.561077 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6978 22:14:41.561187 ==
6979 22:14:41.561286 DQS Delay:
6980 22:14:41.564384 DQS0 = 52, DQS1 = 56
6981 22:14:41.564464 DQM Delay:
6982 22:14:41.567797 DQM0 = 14, DQM1 = 8
6983 22:14:41.567874 DQ Delay:
6984 22:14:41.571281 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =16
6985 22:14:41.574703 DQ4 =16, DQ5 =24, DQ6 =24, DQ7 =8
6986 22:14:41.574780 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6987 22:14:41.581190 DQ12 =12, DQ13 =16, DQ14 =16, DQ15 =16
6988 22:14:41.581270
6989 22:14:41.581336
6990 22:14:41.587503 [DQSOSCAuto] RK1, (LSB)MR18= 0x7990, (MSB)MR19= 0xc0c, tDQSOscB0 = 391 ps tDQSOscB1 = 394 ps
6991 22:14:41.590840 CH1 RK1: MR19=C0C, MR18=7990
6992 22:14:41.597457 CH1_RK1: MR19=0xC0C, MR18=0x7990, DQSOSC=391, MR23=63, INC=386, DEC=257
6993 22:14:41.601221 [RxdqsGatingPostProcess] freq 400
6994 22:14:41.604337 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6995 22:14:41.607753 best DQS0 dly(2T, 0.5T) = (0, 10)
6996 22:14:41.611176 best DQS1 dly(2T, 0.5T) = (0, 10)
6997 22:14:41.614251 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6998 22:14:41.617825 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6999 22:14:41.621152 best DQS0 dly(2T, 0.5T) = (0, 10)
7000 22:14:41.624195 best DQS1 dly(2T, 0.5T) = (0, 10)
7001 22:14:41.627637 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7002 22:14:41.630931 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7003 22:14:41.634411 Pre-setting of DQS Precalculation
7004 22:14:41.638088 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7005 22:14:41.643877 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7006 22:14:41.654006 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7007 22:14:41.654088
7008 22:14:41.654156
7009 22:14:41.657194 [Calibration Summary] 800 Mbps
7010 22:14:41.657274 CH 0, Rank 0
7011 22:14:41.660861 SW Impedance : PASS
7012 22:14:41.660939 DUTY Scan : NO K
7013 22:14:41.664139 ZQ Calibration : PASS
7014 22:14:41.667491 Jitter Meter : NO K
7015 22:14:41.667569 CBT Training : PASS
7016 22:14:41.670874 Write leveling : PASS
7017 22:14:41.670951 RX DQS gating : PASS
7018 22:14:41.673839 RX DQ/DQS(RDDQC) : PASS
7019 22:14:41.677139 TX DQ/DQS : PASS
7020 22:14:41.677216 RX DATLAT : PASS
7021 22:14:41.680976 RX DQ/DQS(Engine): PASS
7022 22:14:41.683728 TX OE : NO K
7023 22:14:41.683804 All Pass.
7024 22:14:41.683882
7025 22:14:41.683948 CH 0, Rank 1
7026 22:14:41.687104 SW Impedance : PASS
7027 22:14:41.690534 DUTY Scan : NO K
7028 22:14:41.690626 ZQ Calibration : PASS
7029 22:14:41.693994 Jitter Meter : NO K
7030 22:14:41.697117 CBT Training : PASS
7031 22:14:41.697204 Write leveling : NO K
7032 22:14:41.700526 RX DQS gating : PASS
7033 22:14:41.703907 RX DQ/DQS(RDDQC) : PASS
7034 22:14:41.703991 TX DQ/DQS : PASS
7035 22:14:41.707480 RX DATLAT : PASS
7036 22:14:41.710467 RX DQ/DQS(Engine): PASS
7037 22:14:41.710552 TX OE : NO K
7038 22:14:41.710619 All Pass.
7039 22:14:41.713937
7040 22:14:41.714021 CH 1, Rank 0
7041 22:14:41.717714 SW Impedance : PASS
7042 22:14:41.717802 DUTY Scan : NO K
7043 22:14:41.720415 ZQ Calibration : PASS
7044 22:14:41.720501 Jitter Meter : NO K
7045 22:14:41.724070 CBT Training : PASS
7046 22:14:41.727150 Write leveling : PASS
7047 22:14:41.727234 RX DQS gating : PASS
7048 22:14:41.730792 RX DQ/DQS(RDDQC) : PASS
7049 22:14:41.734348 TX DQ/DQS : PASS
7050 22:14:41.734430 RX DATLAT : PASS
7051 22:14:41.737102 RX DQ/DQS(Engine): PASS
7052 22:14:41.740677 TX OE : NO K
7053 22:14:41.740753 All Pass.
7054 22:14:41.740818
7055 22:14:41.740879 CH 1, Rank 1
7056 22:14:41.744186 SW Impedance : PASS
7057 22:14:41.747190 DUTY Scan : NO K
7058 22:14:41.747263 ZQ Calibration : PASS
7059 22:14:41.750597 Jitter Meter : NO K
7060 22:14:41.753611 CBT Training : PASS
7061 22:14:41.753691 Write leveling : NO K
7062 22:14:41.757216 RX DQS gating : PASS
7063 22:14:41.760877 RX DQ/DQS(RDDQC) : PASS
7064 22:14:41.760952 TX DQ/DQS : PASS
7065 22:14:41.763846 RX DATLAT : PASS
7066 22:14:41.763932 RX DQ/DQS(Engine): PASS
7067 22:14:41.767130 TX OE : NO K
7068 22:14:41.767211 All Pass.
7069 22:14:41.767275
7070 22:14:41.770387 DramC Write-DBI off
7071 22:14:41.774133 PER_BANK_REFRESH: Hybrid Mode
7072 22:14:41.774211 TX_TRACKING: ON
7073 22:14:41.784250 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7074 22:14:41.787151 [FAST_K] Save calibration result to emmc
7075 22:14:41.790351 dramc_set_vcore_voltage set vcore to 725000
7076 22:14:41.793595 Read voltage for 1600, 0
7077 22:14:41.793678 Vio18 = 0
7078 22:14:41.796723 Vcore = 725000
7079 22:14:41.796807 Vdram = 0
7080 22:14:41.796873 Vddq = 0
7081 22:14:41.796934 Vmddr = 0
7082 22:14:41.803885 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7083 22:14:41.810316 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7084 22:14:41.810411 MEM_TYPE=3, freq_sel=13
7085 22:14:41.813749 sv_algorithm_assistance_LP4_3733
7086 22:14:41.817182 ============ PULL DRAM RESETB DOWN ============
7087 22:14:41.823889 ========== PULL DRAM RESETB DOWN end =========
7088 22:14:41.827102 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7089 22:14:41.830086 ===================================
7090 22:14:41.833706 LPDDR4 DRAM CONFIGURATION
7091 22:14:41.837022 ===================================
7092 22:14:41.837107 EX_ROW_EN[0] = 0x0
7093 22:14:41.840574 EX_ROW_EN[1] = 0x0
7094 22:14:41.840657 LP4Y_EN = 0x0
7095 22:14:41.843477 WORK_FSP = 0x1
7096 22:14:41.843566 WL = 0x5
7097 22:14:41.847097 RL = 0x5
7098 22:14:41.847190 BL = 0x2
7099 22:14:41.850565 RPST = 0x0
7100 22:14:41.850653 RD_PRE = 0x0
7101 22:14:41.853515 WR_PRE = 0x1
7102 22:14:41.856621 WR_PST = 0x1
7103 22:14:41.856715 DBI_WR = 0x0
7104 22:14:41.860071 DBI_RD = 0x0
7105 22:14:41.860151 OTF = 0x1
7106 22:14:41.863525 ===================================
7107 22:14:41.866846 ===================================
7108 22:14:41.866934 ANA top config
7109 22:14:41.870165 ===================================
7110 22:14:41.873764 DLL_ASYNC_EN = 0
7111 22:14:41.876742 ALL_SLAVE_EN = 0
7112 22:14:41.880223 NEW_RANK_MODE = 1
7113 22:14:41.883553 DLL_IDLE_MODE = 1
7114 22:14:41.883640 LP45_APHY_COMB_EN = 1
7115 22:14:41.886493 TX_ODT_DIS = 0
7116 22:14:41.889940 NEW_8X_MODE = 1
7117 22:14:41.893239 ===================================
7118 22:14:41.896959 ===================================
7119 22:14:41.900011 data_rate = 3200
7120 22:14:41.902985 CKR = 1
7121 22:14:41.906934 DQ_P2S_RATIO = 8
7122 22:14:41.907021 ===================================
7123 22:14:41.910007 CA_P2S_RATIO = 8
7124 22:14:41.913119 DQ_CA_OPEN = 0
7125 22:14:41.916376 DQ_SEMI_OPEN = 0
7126 22:14:41.920020 CA_SEMI_OPEN = 0
7127 22:14:41.922982 CA_FULL_RATE = 0
7128 22:14:41.923095 DQ_CKDIV4_EN = 0
7129 22:14:41.926385 CA_CKDIV4_EN = 0
7130 22:14:41.929942 CA_PREDIV_EN = 0
7131 22:14:41.933456 PH8_DLY = 12
7132 22:14:41.936329 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7133 22:14:41.939872 DQ_AAMCK_DIV = 4
7134 22:14:41.939956 CA_AAMCK_DIV = 4
7135 22:14:41.943235 CA_ADMCK_DIV = 4
7136 22:14:41.946210 DQ_TRACK_CA_EN = 0
7137 22:14:41.949730 CA_PICK = 1600
7138 22:14:41.953086 CA_MCKIO = 1600
7139 22:14:41.956109 MCKIO_SEMI = 0
7140 22:14:41.959497 PLL_FREQ = 3068
7141 22:14:41.963153 DQ_UI_PI_RATIO = 32
7142 22:14:41.963265 CA_UI_PI_RATIO = 0
7143 22:14:41.966536 ===================================
7144 22:14:41.969510 ===================================
7145 22:14:41.972899 memory_type:LPDDR4
7146 22:14:41.976459 GP_NUM : 10
7147 22:14:41.976544 SRAM_EN : 1
7148 22:14:41.979176 MD32_EN : 0
7149 22:14:41.982542 ===================================
7150 22:14:41.986009 [ANA_INIT] >>>>>>>>>>>>>>
7151 22:14:41.989295 <<<<<< [CONFIGURE PHASE]: ANA_TX
7152 22:14:41.992762 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7153 22:14:41.995903 ===================================
7154 22:14:41.996033 data_rate = 3200,PCW = 0X7600
7155 22:14:41.999282 ===================================
7156 22:14:42.002411 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7157 22:14:42.009423 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7158 22:14:42.015706 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7159 22:14:42.018978 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7160 22:14:42.022558 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7161 22:14:42.025660 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7162 22:14:42.029005 [ANA_INIT] flow start
7163 22:14:42.029090 [ANA_INIT] PLL >>>>>>>>
7164 22:14:42.032692 [ANA_INIT] PLL <<<<<<<<
7165 22:14:42.035570 [ANA_INIT] MIDPI >>>>>>>>
7166 22:14:42.039254 [ANA_INIT] MIDPI <<<<<<<<
7167 22:14:42.039365 [ANA_INIT] DLL >>>>>>>>
7168 22:14:42.042490 [ANA_INIT] DLL <<<<<<<<
7169 22:14:42.046008 [ANA_INIT] flow end
7170 22:14:42.049022 ============ LP4 DIFF to SE enter ============
7171 22:14:42.052716 ============ LP4 DIFF to SE exit ============
7172 22:14:42.055626 [ANA_INIT] <<<<<<<<<<<<<
7173 22:14:42.059020 [Flow] Enable top DCM control >>>>>
7174 22:14:42.062578 [Flow] Enable top DCM control <<<<<
7175 22:14:42.065697 Enable DLL master slave shuffle
7176 22:14:42.069051 ==============================================================
7177 22:14:42.072254 Gating Mode config
7178 22:14:42.076128 ==============================================================
7179 22:14:42.078716 Config description:
7180 22:14:42.089074 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7181 22:14:42.095474 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7182 22:14:42.099113 SELPH_MODE 0: By rank 1: By Phase
7183 22:14:42.105941 ==============================================================
7184 22:14:42.109563 GAT_TRACK_EN = 1
7185 22:14:42.112477 RX_GATING_MODE = 2
7186 22:14:42.115571 RX_GATING_TRACK_MODE = 2
7187 22:14:42.118884 SELPH_MODE = 1
7188 22:14:42.122222 PICG_EARLY_EN = 1
7189 22:14:42.125125 VALID_LAT_VALUE = 1
7190 22:14:42.128678 ==============================================================
7191 22:14:42.132220 Enter into Gating configuration >>>>
7192 22:14:42.135551 Exit from Gating configuration <<<<
7193 22:14:42.139216 Enter into DVFS_PRE_config >>>>>
7194 22:14:42.148922 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7195 22:14:42.151988 Exit from DVFS_PRE_config <<<<<
7196 22:14:42.155519 Enter into PICG configuration >>>>
7197 22:14:42.158422 Exit from PICG configuration <<<<
7198 22:14:42.162073 [RX_INPUT] configuration >>>>>
7199 22:14:42.164941 [RX_INPUT] configuration <<<<<
7200 22:14:42.171563 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7201 22:14:42.175147 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7202 22:14:42.181528 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7203 22:14:42.188240 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7204 22:14:42.195050 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7205 22:14:42.201632 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7206 22:14:42.204831 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7207 22:14:42.208391 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7208 22:14:42.211236 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7209 22:14:42.218118 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7210 22:14:42.221592 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7211 22:14:42.224579 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7212 22:14:42.227816 ===================================
7213 22:14:42.231389 LPDDR4 DRAM CONFIGURATION
7214 22:14:42.234972 ===================================
7215 22:14:42.235081 EX_ROW_EN[0] = 0x0
7216 22:14:42.238063 EX_ROW_EN[1] = 0x0
7217 22:14:42.241050 LP4Y_EN = 0x0
7218 22:14:42.241129 WORK_FSP = 0x1
7219 22:14:42.245079 WL = 0x5
7220 22:14:42.245155 RL = 0x5
7221 22:14:42.248221 BL = 0x2
7222 22:14:42.248296 RPST = 0x0
7223 22:14:42.251360 RD_PRE = 0x0
7224 22:14:42.251502 WR_PRE = 0x1
7225 22:14:42.254779 WR_PST = 0x1
7226 22:14:42.254875 DBI_WR = 0x0
7227 22:14:42.258359 DBI_RD = 0x0
7228 22:14:42.258443 OTF = 0x1
7229 22:14:42.261231 ===================================
7230 22:14:42.264701 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7231 22:14:42.271244 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7232 22:14:42.274797 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7233 22:14:42.277630 ===================================
7234 22:14:42.281110 LPDDR4 DRAM CONFIGURATION
7235 22:14:42.284675 ===================================
7236 22:14:42.284786 EX_ROW_EN[0] = 0x10
7237 22:14:42.288109 EX_ROW_EN[1] = 0x0
7238 22:14:42.288227 LP4Y_EN = 0x0
7239 22:14:42.290941 WORK_FSP = 0x1
7240 22:14:42.294653 WL = 0x5
7241 22:14:42.294755 RL = 0x5
7242 22:14:42.298533 BL = 0x2
7243 22:14:42.298640 RPST = 0x0
7244 22:14:42.301189 RD_PRE = 0x0
7245 22:14:42.301371 WR_PRE = 0x1
7246 22:14:42.304704 WR_PST = 0x1
7247 22:14:42.304815 DBI_WR = 0x0
7248 22:14:42.307770 DBI_RD = 0x0
7249 22:14:42.307884 OTF = 0x1
7250 22:14:42.311023 ===================================
7251 22:14:42.317622 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7252 22:14:42.317730 ==
7253 22:14:42.321321 Dram Type= 6, Freq= 0, CH_0, rank 0
7254 22:14:42.324496 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7255 22:14:42.324602 ==
7256 22:14:42.327550 [Duty_Offset_Calibration]
7257 22:14:42.330860 B0:2 B1:-1 CA:1
7258 22:14:42.330965
7259 22:14:42.334261 [DutyScan_Calibration_Flow] k_type=0
7260 22:14:42.341891
7261 22:14:42.342014 ==CLK 0==
7262 22:14:42.345360 Final CLK duty delay cell = -4
7263 22:14:42.348296 [-4] MAX Duty = 5031%(X100), DQS PI = 22
7264 22:14:42.351958 [-4] MIN Duty = 4844%(X100), DQS PI = 32
7265 22:14:42.354994 [-4] AVG Duty = 4937%(X100)
7266 22:14:42.355109
7267 22:14:42.358580 CH0 CLK Duty spec in!! Max-Min= 187%
7268 22:14:42.362446 [DutyScan_Calibration_Flow] ====Done====
7269 22:14:42.362556
7270 22:14:42.365002 [DutyScan_Calibration_Flow] k_type=1
7271 22:14:42.381435
7272 22:14:42.381542 ==DQS 0 ==
7273 22:14:42.384797 Final DQS duty delay cell = 0
7274 22:14:42.388343 [0] MAX Duty = 5125%(X100), DQS PI = 22
7275 22:14:42.391770 [0] MIN Duty = 5000%(X100), DQS PI = 14
7276 22:14:42.395163 [0] AVG Duty = 5062%(X100)
7277 22:14:42.395294
7278 22:14:42.395415 ==DQS 1 ==
7279 22:14:42.398327 Final DQS duty delay cell = -4
7280 22:14:42.401584 [-4] MAX Duty = 5125%(X100), DQS PI = 2
7281 22:14:42.405060 [-4] MIN Duty = 5000%(X100), DQS PI = 40
7282 22:14:42.408343 [-4] AVG Duty = 5062%(X100)
7283 22:14:42.408448
7284 22:14:42.411252 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7285 22:14:42.411386
7286 22:14:42.414706 CH0 DQS 1 Duty spec in!! Max-Min= 125%
7287 22:14:42.418024 [DutyScan_Calibration_Flow] ====Done====
7288 22:14:42.418138
7289 22:14:42.421163 [DutyScan_Calibration_Flow] k_type=3
7290 22:14:42.439440
7291 22:14:42.439533 ==DQM 0 ==
7292 22:14:42.442075 Final DQM duty delay cell = 0
7293 22:14:42.445557 [0] MAX Duty = 5000%(X100), DQS PI = 20
7294 22:14:42.448799 [0] MIN Duty = 4875%(X100), DQS PI = 6
7295 22:14:42.452083 [0] AVG Duty = 4937%(X100)
7296 22:14:42.452158
7297 22:14:42.452220 ==DQM 1 ==
7298 22:14:42.455638 Final DQM duty delay cell = 0
7299 22:14:42.458593 [0] MAX Duty = 5187%(X100), DQS PI = 58
7300 22:14:42.462147 [0] MIN Duty = 4969%(X100), DQS PI = 20
7301 22:14:42.465466 [0] AVG Duty = 5078%(X100)
7302 22:14:42.465543
7303 22:14:42.468515 CH0 DQM 0 Duty spec in!! Max-Min= 125%
7304 22:14:42.468592
7305 22:14:42.471833 CH0 DQM 1 Duty spec in!! Max-Min= 218%
7306 22:14:42.475454 [DutyScan_Calibration_Flow] ====Done====
7307 22:14:42.475530
7308 22:14:42.478331 [DutyScan_Calibration_Flow] k_type=2
7309 22:14:42.494851
7310 22:14:42.494963 ==DQ 0 ==
7311 22:14:42.498210 Final DQ duty delay cell = -4
7312 22:14:42.501628 [-4] MAX Duty = 5031%(X100), DQS PI = 56
7313 22:14:42.505166 [-4] MIN Duty = 4844%(X100), DQS PI = 14
7314 22:14:42.508469 [-4] AVG Duty = 4937%(X100)
7315 22:14:42.508605
7316 22:14:42.508717 ==DQ 1 ==
7317 22:14:42.511416 Final DQ duty delay cell = 0
7318 22:14:42.514720 [0] MAX Duty = 5031%(X100), DQS PI = 30
7319 22:14:42.518130 [0] MIN Duty = 4907%(X100), DQS PI = 18
7320 22:14:42.521425 [0] AVG Duty = 4969%(X100)
7321 22:14:42.521539
7322 22:14:42.524675 CH0 DQ 0 Duty spec in!! Max-Min= 187%
7323 22:14:42.524782
7324 22:14:42.527973 CH0 DQ 1 Duty spec in!! Max-Min= 124%
7325 22:14:42.531321 [DutyScan_Calibration_Flow] ====Done====
7326 22:14:42.531467 ==
7327 22:14:42.534682 Dram Type= 6, Freq= 0, CH_1, rank 0
7328 22:14:42.537954 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7329 22:14:42.538057 ==
7330 22:14:42.541911 [Duty_Offset_Calibration]
7331 22:14:42.542015 B0:1 B1:1 CA:2
7332 22:14:42.542118
7333 22:14:42.544608 [DutyScan_Calibration_Flow] k_type=0
7334 22:14:42.555941
7335 22:14:42.556051 ==CLK 0==
7336 22:14:42.558984 Final CLK duty delay cell = 0
7337 22:14:42.562458 [0] MAX Duty = 5218%(X100), DQS PI = 26
7338 22:14:42.565341 [0] MIN Duty = 4938%(X100), DQS PI = 50
7339 22:14:42.568957 [0] AVG Duty = 5078%(X100)
7340 22:14:42.569069
7341 22:14:42.572470 CH1 CLK Duty spec in!! Max-Min= 280%
7342 22:14:42.575599 [DutyScan_Calibration_Flow] ====Done====
7343 22:14:42.575713
7344 22:14:42.578871 [DutyScan_Calibration_Flow] k_type=1
7345 22:14:42.595698
7346 22:14:42.595808 ==DQS 0 ==
7347 22:14:42.598521 Final DQS duty delay cell = 0
7348 22:14:42.602259 [0] MAX Duty = 5062%(X100), DQS PI = 20
7349 22:14:42.605214 [0] MIN Duty = 4813%(X100), DQS PI = 50
7350 22:14:42.608620 [0] AVG Duty = 4937%(X100)
7351 22:14:42.608729
7352 22:14:42.608833 ==DQS 1 ==
7353 22:14:42.611884 Final DQS duty delay cell = 0
7354 22:14:42.615473 [0] MAX Duty = 5062%(X100), DQS PI = 56
7355 22:14:42.618872 [0] MIN Duty = 4938%(X100), DQS PI = 12
7356 22:14:42.622152 [0] AVG Duty = 5000%(X100)
7357 22:14:42.622258
7358 22:14:42.625542 CH1 DQS 0 Duty spec in!! Max-Min= 249%
7359 22:14:42.625656
7360 22:14:42.628826 CH1 DQS 1 Duty spec in!! Max-Min= 124%
7361 22:14:42.631647 [DutyScan_Calibration_Flow] ====Done====
7362 22:14:42.631754
7363 22:14:42.635188 [DutyScan_Calibration_Flow] k_type=3
7364 22:14:42.652507
7365 22:14:42.652626 ==DQM 0 ==
7366 22:14:42.655702 Final DQM duty delay cell = 0
7367 22:14:42.658747 [0] MAX Duty = 5156%(X100), DQS PI = 20
7368 22:14:42.662471 [0] MIN Duty = 4844%(X100), DQS PI = 50
7369 22:14:42.665335 [0] AVG Duty = 5000%(X100)
7370 22:14:42.665457
7371 22:14:42.665562 ==DQM 1 ==
7372 22:14:42.668789 Final DQM duty delay cell = 0
7373 22:14:42.672577 [0] MAX Duty = 5125%(X100), DQS PI = 10
7374 22:14:42.675278 [0] MIN Duty = 4875%(X100), DQS PI = 20
7375 22:14:42.679073 [0] AVG Duty = 5000%(X100)
7376 22:14:42.679196
7377 22:14:42.681885 CH1 DQM 0 Duty spec in!! Max-Min= 312%
7378 22:14:42.681998
7379 22:14:42.685448 CH1 DQM 1 Duty spec in!! Max-Min= 250%
7380 22:14:42.688775 [DutyScan_Calibration_Flow] ====Done====
7381 22:14:42.688889
7382 22:14:42.691791 [DutyScan_Calibration_Flow] k_type=2
7383 22:14:42.708916
7384 22:14:42.709033 ==DQ 0 ==
7385 22:14:42.712214 Final DQ duty delay cell = 0
7386 22:14:42.715579 [0] MAX Duty = 5187%(X100), DQS PI = 20
7387 22:14:42.718778 [0] MIN Duty = 4907%(X100), DQS PI = 52
7388 22:14:42.722322 [0] AVG Duty = 5047%(X100)
7389 22:14:42.722433
7390 22:14:42.722531 ==DQ 1 ==
7391 22:14:42.725534 Final DQ duty delay cell = 0
7392 22:14:42.729298 [0] MAX Duty = 5093%(X100), DQS PI = 6
7393 22:14:42.732117 [0] MIN Duty = 5031%(X100), DQS PI = 0
7394 22:14:42.732243 [0] AVG Duty = 5062%(X100)
7395 22:14:42.735733
7396 22:14:42.739180 CH1 DQ 0 Duty spec in!! Max-Min= 280%
7397 22:14:42.739290
7398 22:14:42.742010 CH1 DQ 1 Duty spec in!! Max-Min= 62%
7399 22:14:42.745434 [DutyScan_Calibration_Flow] ====Done====
7400 22:14:42.749160 nWR fixed to 30
7401 22:14:42.749291 [ModeRegInit_LP4] CH0 RK0
7402 22:14:42.752102 [ModeRegInit_LP4] CH0 RK1
7403 22:14:42.755079 [ModeRegInit_LP4] CH1 RK0
7404 22:14:42.758782 [ModeRegInit_LP4] CH1 RK1
7405 22:14:42.758877 match AC timing 5
7406 22:14:42.762127 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7407 22:14:42.768861 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7408 22:14:42.772167 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7409 22:14:42.778664 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7410 22:14:42.782215 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7411 22:14:42.782298 [MiockJmeterHQA]
7412 22:14:42.782364
7413 22:14:42.785252 [DramcMiockJmeter] u1RxGatingPI = 0
7414 22:14:42.788761 0 : 4260, 4032
7415 22:14:42.788880 4 : 4253, 4027
7416 22:14:42.788949 8 : 4257, 4029
7417 22:14:42.791770 12 : 4252, 4027
7418 22:14:42.791853 16 : 4253, 4026
7419 22:14:42.795366 20 : 4368, 4140
7420 22:14:42.795463 24 : 4252, 4029
7421 22:14:42.798423 28 : 4366, 4140
7422 22:14:42.798506 32 : 4252, 4027
7423 22:14:42.802183 36 : 4360, 4138
7424 22:14:42.802268 40 : 4368, 4140
7425 22:14:42.802335 44 : 4252, 4027
7426 22:14:42.805511 48 : 4363, 4140
7427 22:14:42.805594 52 : 4366, 4140
7428 22:14:42.808422 56 : 4368, 4145
7429 22:14:42.808505 60 : 4250, 4027
7430 22:14:42.811754 64 : 4257, 4031
7431 22:14:42.811837 68 : 4252, 4030
7432 22:14:42.815097 72 : 4253, 4027
7433 22:14:42.815202 76 : 4252, 4029
7434 22:14:42.815270 80 : 4253, 4029
7435 22:14:42.818360 84 : 4252, 4029
7436 22:14:42.818445 88 : 4368, 4145
7437 22:14:42.821765 92 : 4360, 4138
7438 22:14:42.821859 96 : 4249, 3109
7439 22:14:42.825339 100 : 4255, 0
7440 22:14:42.825428 104 : 4363, 0
7441 22:14:42.825491 108 : 4252, 0
7442 22:14:42.828342 112 : 4363, 0
7443 22:14:42.828413 116 : 4255, 0
7444 22:14:42.831617 120 : 4255, 0
7445 22:14:42.831741 124 : 4360, 0
7446 22:14:42.831846 128 : 4253, 0
7447 22:14:42.834898 132 : 4250, 0
7448 22:14:42.835000 136 : 4250, 0
7449 22:14:42.835102 140 : 4250, 0
7450 22:14:42.838547 144 : 4255, 0
7451 22:14:42.838647 148 : 4361, 0
7452 22:14:42.841633 152 : 4255, 0
7453 22:14:42.841713 156 : 4252, 0
7454 22:14:42.841819 160 : 4250, 0
7455 22:14:42.845160 164 : 4253, 0
7456 22:14:42.845240 168 : 4255, 0
7457 22:14:42.848619 172 : 4250, 0
7458 22:14:42.848700 176 : 4250, 0
7459 22:14:42.848785 180 : 4253, 0
7460 22:14:42.852230 184 : 4255, 0
7461 22:14:42.852351 188 : 4252, 0
7462 22:14:42.855115 192 : 4250, 0
7463 22:14:42.855219 196 : 4255, 0
7464 22:14:42.855337 200 : 4253, 0
7465 22:14:42.858433 204 : 4360, 0
7466 22:14:42.858530 208 : 4365, 0
7467 22:14:42.858633 212 : 4252, 169
7468 22:14:42.861849 216 : 4361, 3935
7469 22:14:42.861972 220 : 4255, 4029
7470 22:14:42.864970 224 : 4250, 4027
7471 22:14:42.865096 228 : 4250, 4026
7472 22:14:42.868534 232 : 4250, 4026
7473 22:14:42.868648 236 : 4360, 4137
7474 22:14:42.872108 240 : 4253, 4029
7475 22:14:42.872193 244 : 4255, 4029
7476 22:14:42.874867 248 : 4255, 4032
7477 22:14:42.874956 252 : 4250, 4027
7478 22:14:42.878398 256 : 4253, 4029
7479 22:14:42.878481 260 : 4250, 4026
7480 22:14:42.881863 264 : 4257, 4032
7481 22:14:42.881947 268 : 4360, 4138
7482 22:14:42.882013 272 : 4252, 4029
7483 22:14:42.884906 276 : 4253, 4029
7484 22:14:42.884988 280 : 4250, 4027
7485 22:14:42.888558 284 : 4255, 4029
7486 22:14:42.888647 288 : 4360, 4138
7487 22:14:42.891475 292 : 4250, 4026
7488 22:14:42.891558 296 : 4250, 4027
7489 22:14:42.895035 300 : 4363, 4138
7490 22:14:42.895143 304 : 4360, 4138
7491 22:14:42.898088 308 : 4253, 4029
7492 22:14:42.898219 312 : 4255, 4029
7493 22:14:42.901501 316 : 4252, 4030
7494 22:14:42.901611 320 : 4255, 4029
7495 22:14:42.905089 324 : 4365, 4139
7496 22:14:42.905201 328 : 4250, 4027
7497 22:14:42.907905 332 : 4250, 2917
7498 22:14:42.908012 336 : 4254, 27
7499 22:14:42.908112
7500 22:14:42.911272 MIOCK jitter meter ch=0
7501 22:14:42.911416
7502 22:14:42.914750 1T = (336-100) = 236 dly cells
7503 22:14:42.917935 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7504 22:14:42.918040 ==
7505 22:14:42.921030 Dram Type= 6, Freq= 0, CH_0, rank 0
7506 22:14:42.927814 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7507 22:14:42.927895 ==
7508 22:14:42.931325 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7509 22:14:42.937939 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7510 22:14:42.941739 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7511 22:14:42.947812 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7512 22:14:42.955422 [CA 0] Center 44 (14~75) winsize 62
7513 22:14:42.958817 [CA 1] Center 44 (14~74) winsize 61
7514 22:14:42.962173 [CA 2] Center 39 (10~68) winsize 59
7515 22:14:42.965464 [CA 3] Center 39 (10~68) winsize 59
7516 22:14:42.969132 [CA 4] Center 37 (7~67) winsize 61
7517 22:14:42.972146 [CA 5] Center 37 (7~67) winsize 61
7518 22:14:42.972225
7519 22:14:42.975853 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7520 22:14:42.975935
7521 22:14:42.978652 [CATrainingPosCal] consider 1 rank data
7522 22:14:42.982223 u2DelayCellTimex100 = 275/100 ps
7523 22:14:42.988885 CA0 delay=44 (14~75),Diff = 7 PI (24 cell)
7524 22:14:42.992282 CA1 delay=44 (14~74),Diff = 7 PI (24 cell)
7525 22:14:42.995157 CA2 delay=39 (10~68),Diff = 2 PI (7 cell)
7526 22:14:42.998714 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7527 22:14:43.001776 CA4 delay=37 (7~67),Diff = 0 PI (0 cell)
7528 22:14:43.005280 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7529 22:14:43.005357
7530 22:14:43.008894 CA PerBit enable=1, Macro0, CA PI delay=37
7531 22:14:43.008976
7532 22:14:43.011922 [CBTSetCACLKResult] CA Dly = 37
7533 22:14:43.015437 CS Dly: 11 (0~42)
7534 22:14:43.018976 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7535 22:14:43.021708 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7536 22:14:43.021807 ==
7537 22:14:43.025225 Dram Type= 6, Freq= 0, CH_0, rank 1
7538 22:14:43.031778 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7539 22:14:43.031888 ==
7540 22:14:43.035172 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7541 22:14:43.038608 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7542 22:14:43.045247 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7543 22:14:43.051749 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7544 22:14:43.059561 [CA 0] Center 43 (13~74) winsize 62
7545 22:14:43.062388 [CA 1] Center 43 (13~74) winsize 62
7546 22:14:43.065763 [CA 2] Center 39 (10~69) winsize 60
7547 22:14:43.068874 [CA 3] Center 38 (9~68) winsize 60
7548 22:14:43.072522 [CA 4] Center 37 (7~67) winsize 61
7549 22:14:43.075597 [CA 5] Center 37 (7~67) winsize 61
7550 22:14:43.075681
7551 22:14:43.079024 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7552 22:14:43.079109
7553 22:14:43.082581 [CATrainingPosCal] consider 2 rank data
7554 22:14:43.086127 u2DelayCellTimex100 = 275/100 ps
7555 22:14:43.092516 CA0 delay=44 (14~74),Diff = 7 PI (24 cell)
7556 22:14:43.095520 CA1 delay=44 (14~74),Diff = 7 PI (24 cell)
7557 22:14:43.099158 CA2 delay=39 (10~68),Diff = 2 PI (7 cell)
7558 22:14:43.102158 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7559 22:14:43.105675 CA4 delay=37 (7~67),Diff = 0 PI (0 cell)
7560 22:14:43.109277 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7561 22:14:43.109351
7562 22:14:43.112254 CA PerBit enable=1, Macro0, CA PI delay=37
7563 22:14:43.112330
7564 22:14:43.115936 [CBTSetCACLKResult] CA Dly = 37
7565 22:14:43.118995 CS Dly: 12 (0~44)
7566 22:14:43.122144 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7567 22:14:43.125577 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7568 22:14:43.125680
7569 22:14:43.129052 ----->DramcWriteLeveling(PI) begin...
7570 22:14:43.129127 ==
7571 22:14:43.132347 Dram Type= 6, Freq= 0, CH_0, rank 0
7572 22:14:43.139044 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7573 22:14:43.139125 ==
7574 22:14:43.142028 Write leveling (Byte 0): 36 => 36
7575 22:14:43.142128 Write leveling (Byte 1): 27 => 27
7576 22:14:43.145467 DramcWriteLeveling(PI) end<-----
7577 22:14:43.145552
7578 22:14:43.148582 ==
7579 22:14:43.152102 Dram Type= 6, Freq= 0, CH_0, rank 0
7580 22:14:43.155248 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7581 22:14:43.155363 ==
7582 22:14:43.158930 [Gating] SW mode calibration
7583 22:14:43.165325 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7584 22:14:43.168758 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7585 22:14:43.175540 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7586 22:14:43.178634 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7587 22:14:43.182171 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7588 22:14:43.188875 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7589 22:14:43.191816 1 4 16 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7590 22:14:43.195297 1 4 20 | B1->B0 | 2525 3333 | 0 1 | (0 0) (1 1)
7591 22:14:43.201934 1 4 24 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
7592 22:14:43.205283 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7593 22:14:43.208818 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7594 22:14:43.215021 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7595 22:14:43.218444 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7596 22:14:43.221649 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7597 22:14:43.229302 1 5 16 | B1->B0 | 3434 2d2d | 1 1 | (1 0) (1 0)
7598 22:14:43.231629 1 5 20 | B1->B0 | 3434 2323 | 1 0 | (1 0) (1 0)
7599 22:14:43.235469 1 5 24 | B1->B0 | 2d2d 2323 | 1 0 | (1 0) (0 0)
7600 22:14:43.241853 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7601 22:14:43.245390 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7602 22:14:43.248240 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7603 22:14:43.255157 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7604 22:14:43.258425 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7605 22:14:43.261720 1 6 16 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
7606 22:14:43.268125 1 6 20 | B1->B0 | 2e2e 4646 | 0 0 | (0 0) (0 0)
7607 22:14:43.271385 1 6 24 | B1->B0 | 4040 4646 | 1 0 | (0 0) (0 0)
7608 22:14:43.275126 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7609 22:14:43.277911 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7610 22:14:43.285028 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7611 22:14:43.288240 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7612 22:14:43.291611 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7613 22:14:43.297817 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7614 22:14:43.301313 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7615 22:14:43.304830 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7616 22:14:43.311861 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7617 22:14:43.314732 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7618 22:14:43.317617 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7619 22:14:43.324799 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7620 22:14:43.327539 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7621 22:14:43.331191 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7622 22:14:43.337999 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7623 22:14:43.341340 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7624 22:14:43.344560 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7625 22:14:43.351210 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7626 22:14:43.354022 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7627 22:14:43.357472 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7628 22:14:43.364039 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7629 22:14:43.367523 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7630 22:14:43.371068 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7631 22:14:43.374424 Total UI for P1: 0, mck2ui 16
7632 22:14:43.377777 best dqsien dly found for B0: ( 1, 9, 14)
7633 22:14:43.384152 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7634 22:14:43.387647 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7635 22:14:43.390795 Total UI for P1: 0, mck2ui 16
7636 22:14:43.394039 best dqsien dly found for B1: ( 1, 9, 22)
7637 22:14:43.397728 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
7638 22:14:43.400736 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7639 22:14:43.400838
7640 22:14:43.404243 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
7641 22:14:43.407892 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7642 22:14:43.410688 [Gating] SW calibration Done
7643 22:14:43.410790 ==
7644 22:14:43.414388 Dram Type= 6, Freq= 0, CH_0, rank 0
7645 22:14:43.417367 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7646 22:14:43.421344 ==
7647 22:14:43.421448 RX Vref Scan: 0
7648 22:14:43.421548
7649 22:14:43.424299 RX Vref 0 -> 0, step: 1
7650 22:14:43.424408
7651 22:14:43.424501 RX Delay 0 -> 252, step: 8
7652 22:14:43.430881 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
7653 22:14:43.434008 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
7654 22:14:43.437321 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7655 22:14:43.440845 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7656 22:14:43.444378 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7657 22:14:43.450893 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7658 22:14:43.454499 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
7659 22:14:43.457076 iDelay=200, Bit 7, Center 139 (88 ~ 191) 104
7660 22:14:43.460404 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7661 22:14:43.463875 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7662 22:14:43.470300 iDelay=200, Bit 10, Center 119 (64 ~ 175) 112
7663 22:14:43.473917 iDelay=200, Bit 11, Center 115 (64 ~ 167) 104
7664 22:14:43.476826 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7665 22:14:43.480535 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
7666 22:14:43.486932 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7667 22:14:43.490461 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7668 22:14:43.490539 ==
7669 22:14:43.493419 Dram Type= 6, Freq= 0, CH_0, rank 0
7670 22:14:43.496942 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7671 22:14:43.497026 ==
7672 22:14:43.500733 DQS Delay:
7673 22:14:43.500822 DQS0 = 0, DQS1 = 0
7674 22:14:43.500889 DQM Delay:
7675 22:14:43.503617 DQM0 = 132, DQM1 = 123
7676 22:14:43.503705 DQ Delay:
7677 22:14:43.507002 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
7678 22:14:43.510168 DQ4 =135, DQ5 =119, DQ6 =143, DQ7 =139
7679 22:14:43.514086 DQ8 =111, DQ9 =111, DQ10 =119, DQ11 =115
7680 22:14:43.520777 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =135
7681 22:14:43.520861
7682 22:14:43.520928
7683 22:14:43.520991 ==
7684 22:14:43.523702 Dram Type= 6, Freq= 0, CH_0, rank 0
7685 22:14:43.526773 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7686 22:14:43.526857 ==
7687 22:14:43.526924
7688 22:14:43.526985
7689 22:14:43.530137 TX Vref Scan disable
7690 22:14:43.530221 == TX Byte 0 ==
7691 22:14:43.536704 Update DQ dly =994 (3 ,6, 34) DQ OEN =(3 ,3)
7692 22:14:43.540330 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
7693 22:14:43.540415 == TX Byte 1 ==
7694 22:14:43.547033 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7695 22:14:43.549859 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7696 22:14:43.549979 ==
7697 22:14:43.553355 Dram Type= 6, Freq= 0, CH_0, rank 0
7698 22:14:43.556587 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7699 22:14:43.556672 ==
7700 22:14:43.572741
7701 22:14:43.576267 TX Vref early break, caculate TX vref
7702 22:14:43.579697 TX Vref=16, minBit 1, minWin=21, winSum=355
7703 22:14:43.583157 TX Vref=18, minBit 1, minWin=21, winSum=368
7704 22:14:43.586445 TX Vref=20, minBit 7, minWin=22, winSum=385
7705 22:14:43.589744 TX Vref=22, minBit 12, minWin=23, winSum=393
7706 22:14:43.593145 TX Vref=24, minBit 7, minWin=24, winSum=403
7707 22:14:43.599609 TX Vref=26, minBit 1, minWin=25, winSum=416
7708 22:14:43.602646 TX Vref=28, minBit 1, minWin=25, winSum=421
7709 22:14:43.606278 TX Vref=30, minBit 0, minWin=25, winSum=416
7710 22:14:43.609288 TX Vref=32, minBit 4, minWin=24, winSum=412
7711 22:14:43.612739 TX Vref=34, minBit 0, minWin=24, winSum=403
7712 22:14:43.616253 TX Vref=36, minBit 9, minWin=23, winSum=393
7713 22:14:43.622949 [TxChooseVref] Worse bit 1, Min win 25, Win sum 421, Final Vref 28
7714 22:14:43.623033
7715 22:14:43.626274 Final TX Range 0 Vref 28
7716 22:14:43.626359
7717 22:14:43.626425 ==
7718 22:14:43.629913 Dram Type= 6, Freq= 0, CH_0, rank 0
7719 22:14:43.632857 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7720 22:14:43.632942 ==
7721 22:14:43.633010
7722 22:14:43.633071
7723 22:14:43.636175 TX Vref Scan disable
7724 22:14:43.642573 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7725 22:14:43.642673 == TX Byte 0 ==
7726 22:14:43.646288 u2DelayCellOfst[0]=14 cells (4 PI)
7727 22:14:43.649687 u2DelayCellOfst[1]=17 cells (5 PI)
7728 22:14:43.652984 u2DelayCellOfst[2]=10 cells (3 PI)
7729 22:14:43.655887 u2DelayCellOfst[3]=10 cells (3 PI)
7730 22:14:43.659236 u2DelayCellOfst[4]=7 cells (2 PI)
7731 22:14:43.662866 u2DelayCellOfst[5]=0 cells (0 PI)
7732 22:14:43.665753 u2DelayCellOfst[6]=21 cells (6 PI)
7733 22:14:43.668965 u2DelayCellOfst[7]=17 cells (5 PI)
7734 22:14:43.672702 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7735 22:14:43.675796 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
7736 22:14:43.679477 == TX Byte 1 ==
7737 22:14:43.682569 u2DelayCellOfst[8]=0 cells (0 PI)
7738 22:14:43.685874 u2DelayCellOfst[9]=0 cells (0 PI)
7739 22:14:43.689306 u2DelayCellOfst[10]=7 cells (2 PI)
7740 22:14:43.689390 u2DelayCellOfst[11]=0 cells (0 PI)
7741 22:14:43.692710 u2DelayCellOfst[12]=10 cells (3 PI)
7742 22:14:43.696066 u2DelayCellOfst[13]=10 cells (3 PI)
7743 22:14:43.698978 u2DelayCellOfst[14]=17 cells (5 PI)
7744 22:14:43.702525 u2DelayCellOfst[15]=10 cells (3 PI)
7745 22:14:43.709117 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7746 22:14:43.712644 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7747 22:14:43.712807 DramC Write-DBI on
7748 22:14:43.712875 ==
7749 22:14:43.715843 Dram Type= 6, Freq= 0, CH_0, rank 0
7750 22:14:43.722233 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7751 22:14:43.722318 ==
7752 22:14:43.722386
7753 22:14:43.722448
7754 22:14:43.722508 TX Vref Scan disable
7755 22:14:43.726354 == TX Byte 0 ==
7756 22:14:43.730162 Update DQM dly =738 (2 ,6, 34) DQM OEN =(3 ,3)
7757 22:14:43.733355 == TX Byte 1 ==
7758 22:14:43.736294 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
7759 22:14:43.739647 DramC Write-DBI off
7760 22:14:43.739755
7761 22:14:43.739850 [DATLAT]
7762 22:14:43.739939 Freq=1600, CH0 RK0
7763 22:14:43.740031
7764 22:14:43.743204 DATLAT Default: 0xf
7765 22:14:43.743313 0, 0xFFFF, sum = 0
7766 22:14:43.746810 1, 0xFFFF, sum = 0
7767 22:14:43.750077 2, 0xFFFF, sum = 0
7768 22:14:43.750182 3, 0xFFFF, sum = 0
7769 22:14:43.753170 4, 0xFFFF, sum = 0
7770 22:14:43.753278 5, 0xFFFF, sum = 0
7771 22:14:43.756319 6, 0xFFFF, sum = 0
7772 22:14:43.756431 7, 0xFFFF, sum = 0
7773 22:14:43.759590 8, 0xFFFF, sum = 0
7774 22:14:43.759700 9, 0xFFFF, sum = 0
7775 22:14:43.762933 10, 0xFFFF, sum = 0
7776 22:14:43.763044 11, 0xFFFF, sum = 0
7777 22:14:43.766247 12, 0xFFFF, sum = 0
7778 22:14:43.766354 13, 0xFFFF, sum = 0
7779 22:14:43.769529 14, 0x0, sum = 1
7780 22:14:43.769640 15, 0x0, sum = 2
7781 22:14:43.772750 16, 0x0, sum = 3
7782 22:14:43.772860 17, 0x0, sum = 4
7783 22:14:43.776086 best_step = 15
7784 22:14:43.776277
7785 22:14:43.776373 ==
7786 22:14:43.779366 Dram Type= 6, Freq= 0, CH_0, rank 0
7787 22:14:43.782792 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7788 22:14:43.782898 ==
7789 22:14:43.786132 RX Vref Scan: 1
7790 22:14:43.786236
7791 22:14:43.786335 Set Vref Range= 24 -> 127
7792 22:14:43.786427
7793 22:14:43.789561 RX Vref 24 -> 127, step: 1
7794 22:14:43.789679
7795 22:14:43.792937 RX Delay 11 -> 252, step: 4
7796 22:14:43.793048
7797 22:14:43.796244 Set Vref, RX VrefLevel [Byte0]: 24
7798 22:14:43.799707 [Byte1]: 24
7799 22:14:43.799822
7800 22:14:43.802914 Set Vref, RX VrefLevel [Byte0]: 25
7801 22:14:43.806334 [Byte1]: 25
7802 22:14:43.809175
7803 22:14:43.809249 Set Vref, RX VrefLevel [Byte0]: 26
7804 22:14:43.812716 [Byte1]: 26
7805 22:14:43.817017
7806 22:14:43.817131 Set Vref, RX VrefLevel [Byte0]: 27
7807 22:14:43.820464 [Byte1]: 27
7808 22:14:43.824660
7809 22:14:43.824743 Set Vref, RX VrefLevel [Byte0]: 28
7810 22:14:43.828153 [Byte1]: 28
7811 22:14:43.832241
7812 22:14:43.832325 Set Vref, RX VrefLevel [Byte0]: 29
7813 22:14:43.835735 [Byte1]: 29
7814 22:14:43.839763
7815 22:14:43.839861 Set Vref, RX VrefLevel [Byte0]: 30
7816 22:14:43.843297 [Byte1]: 30
7817 22:14:43.847384
7818 22:14:43.847490 Set Vref, RX VrefLevel [Byte0]: 31
7819 22:14:43.850919 [Byte1]: 31
7820 22:14:43.855113
7821 22:14:43.855201 Set Vref, RX VrefLevel [Byte0]: 32
7822 22:14:43.858614 [Byte1]: 32
7823 22:14:43.862527
7824 22:14:43.862617 Set Vref, RX VrefLevel [Byte0]: 33
7825 22:14:43.865734 [Byte1]: 33
7826 22:14:43.870186
7827 22:14:43.870299 Set Vref, RX VrefLevel [Byte0]: 34
7828 22:14:43.877067 [Byte1]: 34
7829 22:14:43.877144
7830 22:14:43.880312 Set Vref, RX VrefLevel [Byte0]: 35
7831 22:14:43.883306 [Byte1]: 35
7832 22:14:43.883430
7833 22:14:43.886514 Set Vref, RX VrefLevel [Byte0]: 36
7834 22:14:43.889797 [Byte1]: 36
7835 22:14:43.889873
7836 22:14:43.893433 Set Vref, RX VrefLevel [Byte0]: 37
7837 22:14:43.896806 [Byte1]: 37
7838 22:14:43.901048
7839 22:14:43.901151 Set Vref, RX VrefLevel [Byte0]: 38
7840 22:14:43.904078 [Byte1]: 38
7841 22:14:43.908262
7842 22:14:43.908369 Set Vref, RX VrefLevel [Byte0]: 39
7843 22:14:43.912281 [Byte1]: 39
7844 22:14:43.915926
7845 22:14:43.916001 Set Vref, RX VrefLevel [Byte0]: 40
7846 22:14:43.919502 [Byte1]: 40
7847 22:14:43.923702
7848 22:14:43.923777 Set Vref, RX VrefLevel [Byte0]: 41
7849 22:14:43.926646 [Byte1]: 41
7850 22:14:43.931226
7851 22:14:43.931327 Set Vref, RX VrefLevel [Byte0]: 42
7852 22:14:43.934160 [Byte1]: 42
7853 22:14:43.938939
7854 22:14:43.939045 Set Vref, RX VrefLevel [Byte0]: 43
7855 22:14:43.942862 [Byte1]: 43
7856 22:14:43.946588
7857 22:14:43.946660 Set Vref, RX VrefLevel [Byte0]: 44
7858 22:14:43.949578 [Byte1]: 44
7859 22:14:43.954211
7860 22:14:43.954316 Set Vref, RX VrefLevel [Byte0]: 45
7861 22:14:43.958030 [Byte1]: 45
7862 22:14:43.961788
7863 22:14:43.961859 Set Vref, RX VrefLevel [Byte0]: 46
7864 22:14:43.965348 [Byte1]: 46
7865 22:14:43.969311
7866 22:14:43.969379 Set Vref, RX VrefLevel [Byte0]: 47
7867 22:14:43.972498 [Byte1]: 47
7868 22:14:43.976850
7869 22:14:43.976924 Set Vref, RX VrefLevel [Byte0]: 48
7870 22:14:43.980194 [Byte1]: 48
7871 22:14:43.984609
7872 22:14:43.984681 Set Vref, RX VrefLevel [Byte0]: 49
7873 22:14:43.988297 [Byte1]: 49
7874 22:14:43.992023
7875 22:14:43.992093 Set Vref, RX VrefLevel [Byte0]: 50
7876 22:14:43.995126 [Byte1]: 50
7877 22:14:43.999625
7878 22:14:43.999700 Set Vref, RX VrefLevel [Byte0]: 51
7879 22:14:44.002868 [Byte1]: 51
7880 22:14:44.007081
7881 22:14:44.007184 Set Vref, RX VrefLevel [Byte0]: 52
7882 22:14:44.010413 [Byte1]: 52
7883 22:14:44.014615
7884 22:14:44.014689 Set Vref, RX VrefLevel [Byte0]: 53
7885 22:14:44.018269 [Byte1]: 53
7886 22:14:44.022387
7887 22:14:44.022457 Set Vref, RX VrefLevel [Byte0]: 54
7888 22:14:44.026013 [Byte1]: 54
7889 22:14:44.030176
7890 22:14:44.030270 Set Vref, RX VrefLevel [Byte0]: 55
7891 22:14:44.033872 [Byte1]: 55
7892 22:14:44.037903
7893 22:14:44.037980 Set Vref, RX VrefLevel [Byte0]: 56
7894 22:14:44.040734 [Byte1]: 56
7895 22:14:44.045377
7896 22:14:44.045475 Set Vref, RX VrefLevel [Byte0]: 57
7897 22:14:44.048773 [Byte1]: 57
7898 22:14:44.052871
7899 22:14:44.052950 Set Vref, RX VrefLevel [Byte0]: 58
7900 22:14:44.056351 [Byte1]: 58
7901 22:14:44.060448
7902 22:14:44.060525 Set Vref, RX VrefLevel [Byte0]: 59
7903 22:14:44.063884 [Byte1]: 59
7904 22:14:44.068043
7905 22:14:44.068113 Set Vref, RX VrefLevel [Byte0]: 60
7906 22:14:44.071734 [Byte1]: 60
7907 22:14:44.076186
7908 22:14:44.076255 Set Vref, RX VrefLevel [Byte0]: 61
7909 22:14:44.079454 [Byte1]: 61
7910 22:14:44.083611
7911 22:14:44.083679 Set Vref, RX VrefLevel [Byte0]: 62
7912 22:14:44.086942 [Byte1]: 62
7913 22:14:44.090940
7914 22:14:44.091015 Set Vref, RX VrefLevel [Byte0]: 63
7915 22:14:44.094092 [Byte1]: 63
7916 22:14:44.098743
7917 22:14:44.098829 Set Vref, RX VrefLevel [Byte0]: 64
7918 22:14:44.101950 [Byte1]: 64
7919 22:14:44.106499
7920 22:14:44.106603 Set Vref, RX VrefLevel [Byte0]: 65
7921 22:14:44.109676 [Byte1]: 65
7922 22:14:44.114061
7923 22:14:44.114145 Set Vref, RX VrefLevel [Byte0]: 66
7924 22:14:44.117369 [Byte1]: 66
7925 22:14:44.121687
7926 22:14:44.121779 Set Vref, RX VrefLevel [Byte0]: 67
7927 22:14:44.124811 [Byte1]: 67
7928 22:14:44.129383
7929 22:14:44.129466 Set Vref, RX VrefLevel [Byte0]: 68
7930 22:14:44.132265 [Byte1]: 68
7931 22:14:44.136610
7932 22:14:44.136695 Set Vref, RX VrefLevel [Byte0]: 69
7933 22:14:44.140288 [Byte1]: 69
7934 22:14:44.144283
7935 22:14:44.144366 Set Vref, RX VrefLevel [Byte0]: 70
7936 22:14:44.147551 [Byte1]: 70
7937 22:14:44.151789
7938 22:14:44.151872 Set Vref, RX VrefLevel [Byte0]: 71
7939 22:14:44.155110 [Byte1]: 71
7940 22:14:44.159577
7941 22:14:44.159661 Set Vref, RX VrefLevel [Byte0]: 72
7942 22:14:44.163126 [Byte1]: 72
7943 22:14:44.167107
7944 22:14:44.167190 Set Vref, RX VrefLevel [Byte0]: 73
7945 22:14:44.170603 [Byte1]: 73
7946 22:14:44.174884
7947 22:14:44.174968 Set Vref, RX VrefLevel [Byte0]: 74
7948 22:14:44.178221 [Byte1]: 74
7949 22:14:44.182458
7950 22:14:44.182542 Set Vref, RX VrefLevel [Byte0]: 75
7951 22:14:44.186146 [Byte1]: 75
7952 22:14:44.190268
7953 22:14:44.190376 Set Vref, RX VrefLevel [Byte0]: 76
7954 22:14:44.193147 [Byte1]: 76
7955 22:14:44.197495
7956 22:14:44.197606 Final RX Vref Byte 0 = 61 to rank0
7957 22:14:44.200913 Final RX Vref Byte 1 = 61 to rank0
7958 22:14:44.203988 Final RX Vref Byte 0 = 61 to rank1
7959 22:14:44.207368 Final RX Vref Byte 1 = 61 to rank1==
7960 22:14:44.211067 Dram Type= 6, Freq= 0, CH_0, rank 0
7961 22:14:44.217551 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7962 22:14:44.217722 ==
7963 22:14:44.217819 DQS Delay:
7964 22:14:44.220940 DQS0 = 0, DQS1 = 0
7965 22:14:44.221025 DQM Delay:
7966 22:14:44.221089 DQM0 = 129, DQM1 = 121
7967 22:14:44.224051 DQ Delay:
7968 22:14:44.227427 DQ0 =130, DQ1 =132, DQ2 =124, DQ3 =126
7969 22:14:44.231100 DQ4 =132, DQ5 =118, DQ6 =136, DQ7 =138
7970 22:14:44.234040 DQ8 =110, DQ9 =110, DQ10 =122, DQ11 =116
7971 22:14:44.237491 DQ12 =126, DQ13 =126, DQ14 =132, DQ15 =132
7972 22:14:44.237578
7973 22:14:44.237643
7974 22:14:44.237702
7975 22:14:44.240619 [DramC_TX_OE_Calibration] TA2
7976 22:14:44.244197 Original DQ_B0 (3 6) =30, OEN = 27
7977 22:14:44.247184 Original DQ_B1 (3 6) =30, OEN = 27
7978 22:14:44.250719 24, 0x0, End_B0=24 End_B1=24
7979 22:14:44.250804 25, 0x0, End_B0=25 End_B1=25
7980 22:14:44.254201 26, 0x0, End_B0=26 End_B1=26
7981 22:14:44.257373 27, 0x0, End_B0=27 End_B1=27
7982 22:14:44.260802 28, 0x0, End_B0=28 End_B1=28
7983 22:14:44.263879 29, 0x0, End_B0=29 End_B1=29
7984 22:14:44.263964 30, 0x0, End_B0=30 End_B1=30
7985 22:14:44.267495 31, 0x4141, End_B0=30 End_B1=30
7986 22:14:44.270391 Byte0 end_step=30 best_step=27
7987 22:14:44.273970 Byte1 end_step=30 best_step=27
7988 22:14:44.277145 Byte0 TX OE(2T, 0.5T) = (3, 3)
7989 22:14:44.280537 Byte1 TX OE(2T, 0.5T) = (3, 3)
7990 22:14:44.280620
7991 22:14:44.280723
7992 22:14:44.287610 [DQSOSCAuto] RK0, (LSB)MR18= 0x1509, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 399 ps
7993 22:14:44.291066 CH0 RK0: MR19=303, MR18=1509
7994 22:14:44.297759 CH0_RK0: MR19=0x303, MR18=0x1509, DQSOSC=399, MR23=63, INC=23, DEC=15
7995 22:14:44.297843
7996 22:14:44.300576 ----->DramcWriteLeveling(PI) begin...
7997 22:14:44.300661 ==
7998 22:14:44.303828 Dram Type= 6, Freq= 0, CH_0, rank 1
7999 22:14:44.307293 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8000 22:14:44.307399 ==
8001 22:14:44.310629 Write leveling (Byte 0): 34 => 34
8002 22:14:44.313946 Write leveling (Byte 1): 28 => 28
8003 22:14:44.317365 DramcWriteLeveling(PI) end<-----
8004 22:14:44.317467
8005 22:14:44.317570 ==
8006 22:14:44.320474 Dram Type= 6, Freq= 0, CH_0, rank 1
8007 22:14:44.323910 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8008 22:14:44.323996 ==
8009 22:14:44.326909 [Gating] SW mode calibration
8010 22:14:44.333959 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8011 22:14:44.340179 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8012 22:14:44.343819 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8013 22:14:44.347230 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8014 22:14:44.353508 1 4 8 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
8015 22:14:44.356985 1 4 12 | B1->B0 | 2323 3131 | 0 1 | (0 0) (1 1)
8016 22:14:44.360306 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8017 22:14:44.367033 1 4 20 | B1->B0 | 2929 3434 | 0 1 | (0 0) (1 1)
8018 22:14:44.370197 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8019 22:14:44.373590 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8020 22:14:44.380296 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8021 22:14:44.383543 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8022 22:14:44.386788 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8023 22:14:44.393395 1 5 12 | B1->B0 | 3434 2525 | 1 0 | (1 1) (0 0)
8024 22:14:44.396351 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
8025 22:14:44.399657 1 5 20 | B1->B0 | 3131 2323 | 1 0 | (1 0) (0 0)
8026 22:14:44.406913 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8027 22:14:44.409608 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8028 22:14:44.413002 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8029 22:14:44.419844 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8030 22:14:44.423097 1 6 8 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
8031 22:14:44.426440 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8032 22:14:44.432928 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8033 22:14:44.436744 1 6 20 | B1->B0 | 3838 4646 | 1 0 | (0 0) (0 0)
8034 22:14:44.439654 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8035 22:14:44.446455 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8036 22:14:44.449674 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8037 22:14:44.453265 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8038 22:14:44.459699 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8039 22:14:44.463178 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8040 22:14:44.466649 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8041 22:14:44.473275 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8042 22:14:44.476320 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8043 22:14:44.479725 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8044 22:14:44.483346 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8045 22:14:44.489799 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8046 22:14:44.493634 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8047 22:14:44.496262 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8048 22:14:44.502858 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8049 22:14:44.506174 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8050 22:14:44.509943 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8051 22:14:44.516182 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8052 22:14:44.519655 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8053 22:14:44.523104 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8054 22:14:44.529419 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8055 22:14:44.532685 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8056 22:14:44.536024 Total UI for P1: 0, mck2ui 16
8057 22:14:44.539510 best dqsien dly found for B0: ( 1, 9, 8)
8058 22:14:44.542697 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8059 22:14:44.549759 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8060 22:14:44.553105 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8061 22:14:44.556192 Total UI for P1: 0, mck2ui 16
8062 22:14:44.559373 best dqsien dly found for B1: ( 1, 9, 20)
8063 22:14:44.563014 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8064 22:14:44.566429 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
8065 22:14:44.566513
8066 22:14:44.569605 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8067 22:14:44.573065 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
8068 22:14:44.576035 [Gating] SW calibration Done
8069 22:14:44.576118 ==
8070 22:14:44.579623 Dram Type= 6, Freq= 0, CH_0, rank 1
8071 22:14:44.582993 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8072 22:14:44.586148 ==
8073 22:14:44.586232 RX Vref Scan: 0
8074 22:14:44.586299
8075 22:14:44.589399 RX Vref 0 -> 0, step: 1
8076 22:14:44.589483
8077 22:14:44.589550 RX Delay 0 -> 252, step: 8
8078 22:14:44.596114 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8079 22:14:44.599067 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8080 22:14:44.602697 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8081 22:14:44.606283 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8082 22:14:44.609400 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8083 22:14:44.616060 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
8084 22:14:44.619042 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8085 22:14:44.622488 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8086 22:14:44.626107 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8087 22:14:44.632570 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8088 22:14:44.635672 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8089 22:14:44.639140 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8090 22:14:44.642364 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8091 22:14:44.645628 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8092 22:14:44.652489 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8093 22:14:44.655667 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8094 22:14:44.655751 ==
8095 22:14:44.658904 Dram Type= 6, Freq= 0, CH_0, rank 1
8096 22:14:44.662448 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8097 22:14:44.662532 ==
8098 22:14:44.665385 DQS Delay:
8099 22:14:44.665467 DQS0 = 0, DQS1 = 0
8100 22:14:44.665534 DQM Delay:
8101 22:14:44.669024 DQM0 = 131, DQM1 = 124
8102 22:14:44.669107 DQ Delay:
8103 22:14:44.672561 DQ0 =131, DQ1 =131, DQ2 =127, DQ3 =131
8104 22:14:44.675500 DQ4 =131, DQ5 =119, DQ6 =139, DQ7 =139
8105 22:14:44.679002 DQ8 =115, DQ9 =115, DQ10 =123, DQ11 =119
8106 22:14:44.685586 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =131
8107 22:14:44.685669
8108 22:14:44.685738
8109 22:14:44.685845 ==
8110 22:14:44.689022 Dram Type= 6, Freq= 0, CH_0, rank 1
8111 22:14:44.692194 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8112 22:14:44.692274 ==
8113 22:14:44.692356
8114 22:14:44.692433
8115 22:14:44.695672 TX Vref Scan disable
8116 22:14:44.695747 == TX Byte 0 ==
8117 22:14:44.702157 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8118 22:14:44.705542 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8119 22:14:44.705628 == TX Byte 1 ==
8120 22:14:44.712816 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8121 22:14:44.715501 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8122 22:14:44.715586 ==
8123 22:14:44.718642 Dram Type= 6, Freq= 0, CH_0, rank 1
8124 22:14:44.722005 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8125 22:14:44.722088 ==
8126 22:14:44.738884
8127 22:14:44.742170 TX Vref early break, caculate TX vref
8128 22:14:44.745325 TX Vref=16, minBit 1, minWin=22, winSum=374
8129 22:14:44.749193 TX Vref=18, minBit 1, minWin=23, winSum=384
8130 22:14:44.752226 TX Vref=20, minBit 5, minWin=23, winSum=391
8131 22:14:44.755149 TX Vref=22, minBit 0, minWin=24, winSum=399
8132 22:14:44.758596 TX Vref=24, minBit 4, minWin=24, winSum=412
8133 22:14:44.765252 TX Vref=26, minBit 1, minWin=25, winSum=416
8134 22:14:44.768428 TX Vref=28, minBit 0, minWin=25, winSum=419
8135 22:14:44.772275 TX Vref=30, minBit 2, minWin=25, winSum=420
8136 22:14:44.775317 TX Vref=32, minBit 0, minWin=25, winSum=414
8137 22:14:44.778306 TX Vref=34, minBit 0, minWin=24, winSum=403
8138 22:14:44.782044 TX Vref=36, minBit 0, minWin=24, winSum=399
8139 22:14:44.788925 TX Vref=38, minBit 0, minWin=23, winSum=388
8140 22:14:44.792186 [TxChooseVref] Worse bit 2, Min win 25, Win sum 420, Final Vref 30
8141 22:14:44.792261
8142 22:14:44.795153 Final TX Range 0 Vref 30
8143 22:14:44.795227
8144 22:14:44.795288 ==
8145 22:14:44.798519 Dram Type= 6, Freq= 0, CH_0, rank 1
8146 22:14:44.802086 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8147 22:14:44.805134 ==
8148 22:14:44.805209
8149 22:14:44.805272
8150 22:14:44.805330 TX Vref Scan disable
8151 22:14:44.812129 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8152 22:14:44.812208 == TX Byte 0 ==
8153 22:14:44.815179 u2DelayCellOfst[0]=14 cells (4 PI)
8154 22:14:44.818472 u2DelayCellOfst[1]=17 cells (5 PI)
8155 22:14:44.821966 u2DelayCellOfst[2]=10 cells (3 PI)
8156 22:14:44.825288 u2DelayCellOfst[3]=10 cells (3 PI)
8157 22:14:44.828581 u2DelayCellOfst[4]=10 cells (3 PI)
8158 22:14:44.832238 u2DelayCellOfst[5]=0 cells (0 PI)
8159 22:14:44.835184 u2DelayCellOfst[6]=17 cells (5 PI)
8160 22:14:44.838862 u2DelayCellOfst[7]=17 cells (5 PI)
8161 22:14:44.842141 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
8162 22:14:44.845351 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8163 22:14:44.849189 == TX Byte 1 ==
8164 22:14:44.851627 u2DelayCellOfst[8]=0 cells (0 PI)
8165 22:14:44.855018 u2DelayCellOfst[9]=0 cells (0 PI)
8166 22:14:44.858424 u2DelayCellOfst[10]=7 cells (2 PI)
8167 22:14:44.861696 u2DelayCellOfst[11]=0 cells (0 PI)
8168 22:14:44.865049 u2DelayCellOfst[12]=14 cells (4 PI)
8169 22:14:44.865133 u2DelayCellOfst[13]=10 cells (3 PI)
8170 22:14:44.868622 u2DelayCellOfst[14]=14 cells (4 PI)
8171 22:14:44.871620 u2DelayCellOfst[15]=14 cells (4 PI)
8172 22:14:44.878521 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8173 22:14:44.881959 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8174 22:14:44.882043 DramC Write-DBI on
8175 22:14:44.885182 ==
8176 22:14:44.885296 Dram Type= 6, Freq= 0, CH_0, rank 1
8177 22:14:44.892022 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8178 22:14:44.892107 ==
8179 22:14:44.892173
8180 22:14:44.892234
8181 22:14:44.895098 TX Vref Scan disable
8182 22:14:44.895182 == TX Byte 0 ==
8183 22:14:44.901545 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
8184 22:14:44.901629 == TX Byte 1 ==
8185 22:14:44.905013 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
8186 22:14:44.908515 DramC Write-DBI off
8187 22:14:44.908599
8188 22:14:44.908665 [DATLAT]
8189 22:14:44.911585 Freq=1600, CH0 RK1
8190 22:14:44.911669
8191 22:14:44.911735 DATLAT Default: 0xf
8192 22:14:44.915237 0, 0xFFFF, sum = 0
8193 22:14:44.915359 1, 0xFFFF, sum = 0
8194 22:14:44.918290 2, 0xFFFF, sum = 0
8195 22:14:44.918402 3, 0xFFFF, sum = 0
8196 22:14:44.921888 4, 0xFFFF, sum = 0
8197 22:14:44.921999 5, 0xFFFF, sum = 0
8198 22:14:44.924761 6, 0xFFFF, sum = 0
8199 22:14:44.924867 7, 0xFFFF, sum = 0
8200 22:14:44.928415 8, 0xFFFF, sum = 0
8201 22:14:44.928524 9, 0xFFFF, sum = 0
8202 22:14:44.931529 10, 0xFFFF, sum = 0
8203 22:14:44.934563 11, 0xFFFF, sum = 0
8204 22:14:44.934675 12, 0xFFFF, sum = 0
8205 22:14:44.938164 13, 0xFFFF, sum = 0
8206 22:14:44.938273 14, 0x0, sum = 1
8207 22:14:44.942026 15, 0x0, sum = 2
8208 22:14:44.942137 16, 0x0, sum = 3
8209 22:14:44.944595 17, 0x0, sum = 4
8210 22:14:44.944672 best_step = 15
8211 22:14:44.944736
8212 22:14:44.944795 ==
8213 22:14:44.947976 Dram Type= 6, Freq= 0, CH_0, rank 1
8214 22:14:44.951551 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8215 22:14:44.951697 ==
8216 22:14:44.954373 RX Vref Scan: 0
8217 22:14:44.954448
8218 22:14:44.958069 RX Vref 0 -> 0, step: 1
8219 22:14:44.958156
8220 22:14:44.958218 RX Delay 11 -> 252, step: 4
8221 22:14:44.965001 iDelay=191, Bit 0, Center 126 (71 ~ 182) 112
8222 22:14:44.968247 iDelay=191, Bit 1, Center 130 (75 ~ 186) 112
8223 22:14:44.971590 iDelay=191, Bit 2, Center 122 (67 ~ 178) 112
8224 22:14:44.974849 iDelay=191, Bit 3, Center 126 (71 ~ 182) 112
8225 22:14:44.978152 iDelay=191, Bit 4, Center 126 (71 ~ 182) 112
8226 22:14:44.985516 iDelay=191, Bit 5, Center 116 (63 ~ 170) 108
8227 22:14:44.988458 iDelay=191, Bit 6, Center 136 (83 ~ 190) 108
8228 22:14:44.991458 iDelay=191, Bit 7, Center 134 (79 ~ 190) 112
8229 22:14:44.994799 iDelay=191, Bit 8, Center 114 (59 ~ 170) 112
8230 22:14:44.998427 iDelay=191, Bit 9, Center 110 (55 ~ 166) 112
8231 22:14:45.004796 iDelay=191, Bit 10, Center 122 (67 ~ 178) 112
8232 22:14:45.008304 iDelay=191, Bit 11, Center 116 (63 ~ 170) 108
8233 22:14:45.011967 iDelay=191, Bit 12, Center 126 (75 ~ 178) 104
8234 22:14:45.014771 iDelay=191, Bit 13, Center 130 (75 ~ 186) 112
8235 22:14:45.021487 iDelay=191, Bit 14, Center 134 (79 ~ 190) 112
8236 22:14:45.024851 iDelay=191, Bit 15, Center 130 (75 ~ 186) 112
8237 22:14:45.024934 ==
8238 22:14:45.028215 Dram Type= 6, Freq= 0, CH_0, rank 1
8239 22:14:45.031172 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8240 22:14:45.031256 ==
8241 22:14:45.034397 DQS Delay:
8242 22:14:45.034493 DQS0 = 0, DQS1 = 0
8243 22:14:45.034559 DQM Delay:
8244 22:14:45.037998 DQM0 = 127, DQM1 = 122
8245 22:14:45.038080 DQ Delay:
8246 22:14:45.041013 DQ0 =126, DQ1 =130, DQ2 =122, DQ3 =126
8247 22:14:45.044123 DQ4 =126, DQ5 =116, DQ6 =136, DQ7 =134
8248 22:14:45.051381 DQ8 =114, DQ9 =110, DQ10 =122, DQ11 =116
8249 22:14:45.054208 DQ12 =126, DQ13 =130, DQ14 =134, DQ15 =130
8250 22:14:45.054283
8251 22:14:45.054358
8252 22:14:45.054418
8253 22:14:45.057539 [DramC_TX_OE_Calibration] TA2
8254 22:14:45.060857 Original DQ_B0 (3 6) =30, OEN = 27
8255 22:14:45.060929 Original DQ_B1 (3 6) =30, OEN = 27
8256 22:14:45.064121 24, 0x0, End_B0=24 End_B1=24
8257 22:14:45.067747 25, 0x0, End_B0=25 End_B1=25
8258 22:14:45.070674 26, 0x0, End_B0=26 End_B1=26
8259 22:14:45.073920 27, 0x0, End_B0=27 End_B1=27
8260 22:14:45.073997 28, 0x0, End_B0=28 End_B1=28
8261 22:14:45.077205 29, 0x0, End_B0=29 End_B1=29
8262 22:14:45.081024 30, 0x0, End_B0=30 End_B1=30
8263 22:14:45.084509 31, 0x4141, End_B0=30 End_B1=30
8264 22:14:45.087216 Byte0 end_step=30 best_step=27
8265 22:14:45.090716 Byte1 end_step=30 best_step=27
8266 22:14:45.090829 Byte0 TX OE(2T, 0.5T) = (3, 3)
8267 22:14:45.094590 Byte1 TX OE(2T, 0.5T) = (3, 3)
8268 22:14:45.094668
8269 22:14:45.094732
8270 22:14:45.103758 [DQSOSCAuto] RK1, (LSB)MR18= 0x150a, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 399 ps
8271 22:14:45.107335 CH0 RK1: MR19=303, MR18=150A
8272 22:14:45.110785 CH0_RK1: MR19=0x303, MR18=0x150A, DQSOSC=399, MR23=63, INC=23, DEC=15
8273 22:14:45.113762 [RxdqsGatingPostProcess] freq 1600
8274 22:14:45.120383 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8275 22:14:45.124018 best DQS0 dly(2T, 0.5T) = (1, 1)
8276 22:14:45.126956 best DQS1 dly(2T, 0.5T) = (1, 1)
8277 22:14:45.130459 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8278 22:14:45.134212 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8279 22:14:45.137267 best DQS0 dly(2T, 0.5T) = (1, 1)
8280 22:14:45.137350 best DQS1 dly(2T, 0.5T) = (1, 1)
8281 22:14:45.140304 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8282 22:14:45.143775 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8283 22:14:45.147325 Pre-setting of DQS Precalculation
8284 22:14:45.153926 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8285 22:14:45.154041 ==
8286 22:14:45.157167 Dram Type= 6, Freq= 0, CH_1, rank 0
8287 22:14:45.160564 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8288 22:14:45.160642 ==
8289 22:14:45.167102 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8290 22:14:45.170516 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8291 22:14:45.173305 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8292 22:14:45.180717 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8293 22:14:45.189490 [CA 0] Center 42 (14~71) winsize 58
8294 22:14:45.192338 [CA 1] Center 42 (13~71) winsize 59
8295 22:14:45.195709 [CA 2] Center 37 (8~66) winsize 59
8296 22:14:45.199278 [CA 3] Center 36 (7~65) winsize 59
8297 22:14:45.202213 [CA 4] Center 37 (7~67) winsize 61
8298 22:14:45.205720 [CA 5] Center 36 (7~66) winsize 60
8299 22:14:45.205827
8300 22:14:45.209723 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8301 22:14:45.209804
8302 22:14:45.212592 [CATrainingPosCal] consider 1 rank data
8303 22:14:45.215987 u2DelayCellTimex100 = 275/100 ps
8304 22:14:45.219262 CA0 delay=42 (14~71),Diff = 6 PI (21 cell)
8305 22:14:45.225652 CA1 delay=42 (13~71),Diff = 6 PI (21 cell)
8306 22:14:45.229268 CA2 delay=37 (8~66),Diff = 1 PI (3 cell)
8307 22:14:45.232280 CA3 delay=36 (7~65),Diff = 0 PI (0 cell)
8308 22:14:45.236431 CA4 delay=37 (7~67),Diff = 1 PI (3 cell)
8309 22:14:45.238883 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8310 22:14:45.238981
8311 22:14:45.242078 CA PerBit enable=1, Macro0, CA PI delay=36
8312 22:14:45.242175
8313 22:14:45.245604 [CBTSetCACLKResult] CA Dly = 36
8314 22:14:45.249145 CS Dly: 9 (0~40)
8315 22:14:45.252185 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8316 22:14:45.255512 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8317 22:14:45.255584 ==
8318 22:14:45.259382 Dram Type= 6, Freq= 0, CH_1, rank 1
8319 22:14:45.262314 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8320 22:14:45.265775 ==
8321 22:14:45.268651 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8322 22:14:45.271999 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8323 22:14:45.278632 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8324 22:14:45.285175 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8325 22:14:45.292615 [CA 0] Center 42 (13~72) winsize 60
8326 22:14:45.295949 [CA 1] Center 43 (15~72) winsize 58
8327 22:14:45.299490 [CA 2] Center 37 (8~67) winsize 60
8328 22:14:45.302137 [CA 3] Center 37 (8~66) winsize 59
8329 22:14:45.305675 [CA 4] Center 37 (8~67) winsize 60
8330 22:14:45.309300 [CA 5] Center 36 (7~66) winsize 60
8331 22:14:45.309384
8332 22:14:45.312067 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8333 22:14:45.312142
8334 22:14:45.315355 [CATrainingPosCal] consider 2 rank data
8335 22:14:45.319143 u2DelayCellTimex100 = 275/100 ps
8336 22:14:45.322025 CA0 delay=42 (14~71),Diff = 6 PI (21 cell)
8337 22:14:45.329122 CA1 delay=43 (15~71),Diff = 7 PI (24 cell)
8338 22:14:45.332062 CA2 delay=37 (8~66),Diff = 1 PI (3 cell)
8339 22:14:45.335697 CA3 delay=36 (8~65),Diff = 0 PI (0 cell)
8340 22:14:45.338739 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8341 22:14:45.342288 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8342 22:14:45.342403
8343 22:14:45.345627 CA PerBit enable=1, Macro0, CA PI delay=36
8344 22:14:45.345725
8345 22:14:45.349098 [CBTSetCACLKResult] CA Dly = 36
8346 22:14:45.352087 CS Dly: 11 (0~45)
8347 22:14:45.355729 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8348 22:14:45.358805 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8349 22:14:45.358903
8350 22:14:45.362100 ----->DramcWriteLeveling(PI) begin...
8351 22:14:45.362201 ==
8352 22:14:45.365712 Dram Type= 6, Freq= 0, CH_1, rank 0
8353 22:14:45.369139 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8354 22:14:45.371928 ==
8355 22:14:45.372028 Write leveling (Byte 0): 24 => 24
8356 22:14:45.375266 Write leveling (Byte 1): 27 => 27
8357 22:14:45.378755 DramcWriteLeveling(PI) end<-----
8358 22:14:45.378837
8359 22:14:45.378902 ==
8360 22:14:45.382080 Dram Type= 6, Freq= 0, CH_1, rank 0
8361 22:14:45.388581 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8362 22:14:45.388664 ==
8363 22:14:45.388729 [Gating] SW mode calibration
8364 22:14:45.398624 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8365 22:14:45.402469 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8366 22:14:45.408934 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8367 22:14:45.412310 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8368 22:14:45.415149 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8369 22:14:45.418774 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8370 22:14:45.425239 1 4 16 | B1->B0 | 2e2e 2828 | 0 0 | (0 0) (0 0)
8371 22:14:45.428823 1 4 20 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
8372 22:14:45.431752 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8373 22:14:45.438666 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8374 22:14:45.442556 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8375 22:14:45.445396 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8376 22:14:45.452082 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8377 22:14:45.455090 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
8378 22:14:45.458746 1 5 16 | B1->B0 | 2929 3131 | 0 1 | (1 0) (1 0)
8379 22:14:45.465391 1 5 20 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
8380 22:14:45.468720 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8381 22:14:45.472266 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8382 22:14:45.478467 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8383 22:14:45.481895 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8384 22:14:45.485354 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8385 22:14:45.492195 1 6 12 | B1->B0 | 2323 2323 | 0 1 | (0 0) (0 0)
8386 22:14:45.495088 1 6 16 | B1->B0 | 3939 2d2d | 0 0 | (0 0) (0 0)
8387 22:14:45.498462 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8388 22:14:45.505174 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8389 22:14:45.508611 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8390 22:14:45.511702 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8391 22:14:45.518761 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8392 22:14:45.521565 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8393 22:14:45.525022 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8394 22:14:45.531669 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8395 22:14:45.534742 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8396 22:14:45.538285 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8397 22:14:45.544745 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8398 22:14:45.548644 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8399 22:14:45.551464 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8400 22:14:45.558388 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8401 22:14:45.561957 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8402 22:14:45.564897 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8403 22:14:45.571298 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8404 22:14:45.575052 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8405 22:14:45.577822 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8406 22:14:45.581631 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8407 22:14:45.588261 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8408 22:14:45.591622 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8409 22:14:45.594395 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8410 22:14:45.601084 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8411 22:14:45.604471 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8412 22:14:45.607967 Total UI for P1: 0, mck2ui 16
8413 22:14:45.611486 best dqsien dly found for B0: ( 1, 9, 16)
8414 22:14:45.614238 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8415 22:14:45.617879 Total UI for P1: 0, mck2ui 16
8416 22:14:45.620886 best dqsien dly found for B1: ( 1, 9, 16)
8417 22:14:45.624266 best DQS0 dly(MCK, UI, PI) = (1, 9, 16)
8418 22:14:45.627947 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8419 22:14:45.631552
8420 22:14:45.634434 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)
8421 22:14:45.637670 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8422 22:14:45.641185 [Gating] SW calibration Done
8423 22:14:45.641268 ==
8424 22:14:45.644911 Dram Type= 6, Freq= 0, CH_1, rank 0
8425 22:14:45.647903 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8426 22:14:45.647987 ==
8427 22:14:45.648053 RX Vref Scan: 0
8428 22:14:45.650828
8429 22:14:45.650911 RX Vref 0 -> 0, step: 1
8430 22:14:45.650977
8431 22:14:45.654070 RX Delay 0 -> 252, step: 8
8432 22:14:45.657309 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8433 22:14:45.660778 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8434 22:14:45.667207 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8435 22:14:45.670727 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8436 22:14:45.674491 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8437 22:14:45.677663 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8438 22:14:45.681031 iDelay=200, Bit 6, Center 143 (96 ~ 191) 96
8439 22:14:45.687488 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8440 22:14:45.690889 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8441 22:14:45.693774 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
8442 22:14:45.697224 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8443 22:14:45.700587 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8444 22:14:45.707364 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8445 22:14:45.710705 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8446 22:14:45.713889 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8447 22:14:45.717312 iDelay=200, Bit 15, Center 131 (80 ~ 183) 104
8448 22:14:45.717454 ==
8449 22:14:45.720648 Dram Type= 6, Freq= 0, CH_1, rank 0
8450 22:14:45.727145 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8451 22:14:45.727267 ==
8452 22:14:45.727420 DQS Delay:
8453 22:14:45.730541 DQS0 = 0, DQS1 = 0
8454 22:14:45.730616 DQM Delay:
8455 22:14:45.730679 DQM0 = 133, DQM1 = 127
8456 22:14:45.733456 DQ Delay:
8457 22:14:45.737166 DQ0 =139, DQ1 =127, DQ2 =119, DQ3 =135
8458 22:14:45.740207 DQ4 =135, DQ5 =143, DQ6 =143, DQ7 =127
8459 22:14:45.743548 DQ8 =115, DQ9 =115, DQ10 =127, DQ11 =123
8460 22:14:45.747116 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =131
8461 22:14:45.747220
8462 22:14:45.747312
8463 22:14:45.747432 ==
8464 22:14:45.750063 Dram Type= 6, Freq= 0, CH_1, rank 0
8465 22:14:45.756635 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8466 22:14:45.756715 ==
8467 22:14:45.756780
8468 22:14:45.756872
8469 22:14:45.756949 TX Vref Scan disable
8470 22:14:45.760022 == TX Byte 0 ==
8471 22:14:45.763326 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8472 22:14:45.766759 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8473 22:14:45.769832 == TX Byte 1 ==
8474 22:14:45.773151 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8475 22:14:45.776892 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8476 22:14:45.780223 ==
8477 22:14:45.783648 Dram Type= 6, Freq= 0, CH_1, rank 0
8478 22:14:45.786847 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8479 22:14:45.786924 ==
8480 22:14:45.798552
8481 22:14:45.802067 TX Vref early break, caculate TX vref
8482 22:14:45.805763 TX Vref=16, minBit 8, minWin=21, winSum=364
8483 22:14:45.808945 TX Vref=18, minBit 11, minWin=21, winSum=375
8484 22:14:45.812011 TX Vref=20, minBit 8, minWin=21, winSum=389
8485 22:14:45.815470 TX Vref=22, minBit 8, minWin=23, winSum=395
8486 22:14:45.818703 TX Vref=24, minBit 8, minWin=24, winSum=407
8487 22:14:45.825344 TX Vref=26, minBit 5, minWin=25, winSum=415
8488 22:14:45.828807 TX Vref=28, minBit 0, minWin=26, winSum=425
8489 22:14:45.832095 TX Vref=30, minBit 8, minWin=24, winSum=421
8490 22:14:45.835266 TX Vref=32, minBit 0, minWin=25, winSum=411
8491 22:14:45.838837 TX Vref=34, minBit 3, minWin=24, winSum=399
8492 22:14:45.845347 [TxChooseVref] Worse bit 0, Min win 26, Win sum 425, Final Vref 28
8493 22:14:45.845441
8494 22:14:45.848979 Final TX Range 0 Vref 28
8495 22:14:45.849052
8496 22:14:45.849121 ==
8497 22:14:45.851936 Dram Type= 6, Freq= 0, CH_1, rank 0
8498 22:14:45.855634 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8499 22:14:45.855712 ==
8500 22:14:45.855777
8501 22:14:45.855835
8502 22:14:45.858771 TX Vref Scan disable
8503 22:14:45.865500 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8504 22:14:45.865578 == TX Byte 0 ==
8505 22:14:45.868789 u2DelayCellOfst[0]=17 cells (5 PI)
8506 22:14:45.872261 u2DelayCellOfst[1]=14 cells (4 PI)
8507 22:14:45.875414 u2DelayCellOfst[2]=0 cells (0 PI)
8508 22:14:45.878932 u2DelayCellOfst[3]=7 cells (2 PI)
8509 22:14:45.882009 u2DelayCellOfst[4]=7 cells (2 PI)
8510 22:14:45.885571 u2DelayCellOfst[5]=17 cells (5 PI)
8511 22:14:45.888932 u2DelayCellOfst[6]=17 cells (5 PI)
8512 22:14:45.889014 u2DelayCellOfst[7]=7 cells (2 PI)
8513 22:14:45.895406 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8514 22:14:45.898607 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8515 22:14:45.898718 == TX Byte 1 ==
8516 22:14:45.901896 u2DelayCellOfst[8]=0 cells (0 PI)
8517 22:14:45.905062 u2DelayCellOfst[9]=3 cells (1 PI)
8518 22:14:45.908615 u2DelayCellOfst[10]=10 cells (3 PI)
8519 22:14:45.912014 u2DelayCellOfst[11]=7 cells (2 PI)
8520 22:14:45.915234 u2DelayCellOfst[12]=14 cells (4 PI)
8521 22:14:45.918624 u2DelayCellOfst[13]=14 cells (4 PI)
8522 22:14:45.921892 u2DelayCellOfst[14]=17 cells (5 PI)
8523 22:14:45.925083 u2DelayCellOfst[15]=17 cells (5 PI)
8524 22:14:45.928538 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8525 22:14:45.934917 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8526 22:14:45.935025 DramC Write-DBI on
8527 22:14:45.935119 ==
8528 22:14:45.938395 Dram Type= 6, Freq= 0, CH_1, rank 0
8529 22:14:45.942020 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8530 22:14:45.942107 ==
8531 22:14:45.945122
8532 22:14:45.945204
8533 22:14:45.945269 TX Vref Scan disable
8534 22:14:45.948136 == TX Byte 0 ==
8535 22:14:45.951704 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8536 22:14:45.955278 == TX Byte 1 ==
8537 22:14:45.958164 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8538 22:14:45.958276 DramC Write-DBI off
8539 22:14:45.961562
8540 22:14:45.961675 [DATLAT]
8541 22:14:45.961768 Freq=1600, CH1 RK0
8542 22:14:45.961870
8543 22:14:45.964976 DATLAT Default: 0xf
8544 22:14:45.965088 0, 0xFFFF, sum = 0
8545 22:14:45.968289 1, 0xFFFF, sum = 0
8546 22:14:45.968397 2, 0xFFFF, sum = 0
8547 22:14:45.971568 3, 0xFFFF, sum = 0
8548 22:14:45.975146 4, 0xFFFF, sum = 0
8549 22:14:45.975254 5, 0xFFFF, sum = 0
8550 22:14:45.978082 6, 0xFFFF, sum = 0
8551 22:14:45.978189 7, 0xFFFF, sum = 0
8552 22:14:45.981508 8, 0xFFFF, sum = 0
8553 22:14:45.981622 9, 0xFFFF, sum = 0
8554 22:14:45.985336 10, 0xFFFF, sum = 0
8555 22:14:45.985458 11, 0xFFFF, sum = 0
8556 22:14:45.988015 12, 0xFFFF, sum = 0
8557 22:14:45.988129 13, 0xFFFF, sum = 0
8558 22:14:45.991129 14, 0x0, sum = 1
8559 22:14:45.991243 15, 0x0, sum = 2
8560 22:14:45.994989 16, 0x0, sum = 3
8561 22:14:45.995122 17, 0x0, sum = 4
8562 22:14:45.998453 best_step = 15
8563 22:14:45.998563
8564 22:14:45.998665 ==
8565 22:14:46.001213 Dram Type= 6, Freq= 0, CH_1, rank 0
8566 22:14:46.004654 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8567 22:14:46.004764 ==
8568 22:14:46.008307 RX Vref Scan: 1
8569 22:14:46.008428
8570 22:14:46.008528 Set Vref Range= 24 -> 127
8571 22:14:46.008621
8572 22:14:46.011223 RX Vref 24 -> 127, step: 1
8573 22:14:46.011355
8574 22:14:46.014717 RX Delay 19 -> 252, step: 4
8575 22:14:46.014828
8576 22:14:46.018200 Set Vref, RX VrefLevel [Byte0]: 24
8577 22:14:46.021419 [Byte1]: 24
8578 22:14:46.021525
8579 22:14:46.024966 Set Vref, RX VrefLevel [Byte0]: 25
8580 22:14:46.028534 [Byte1]: 25
8581 22:14:46.028638
8582 22:14:46.031866 Set Vref, RX VrefLevel [Byte0]: 26
8583 22:14:46.034892 [Byte1]: 26
8584 22:14:46.038822
8585 22:14:46.038939 Set Vref, RX VrefLevel [Byte0]: 27
8586 22:14:46.041749 [Byte1]: 27
8587 22:14:46.045989
8588 22:14:46.046095 Set Vref, RX VrefLevel [Byte0]: 28
8589 22:14:46.049508 [Byte1]: 28
8590 22:14:46.053748
8591 22:14:46.053864 Set Vref, RX VrefLevel [Byte0]: 29
8592 22:14:46.056888 [Byte1]: 29
8593 22:14:46.060946
8594 22:14:46.061053 Set Vref, RX VrefLevel [Byte0]: 30
8595 22:14:46.064479 [Byte1]: 30
8596 22:14:46.068972
8597 22:14:46.069058 Set Vref, RX VrefLevel [Byte0]: 31
8598 22:14:46.072369 [Byte1]: 31
8599 22:14:46.076157
8600 22:14:46.076234 Set Vref, RX VrefLevel [Byte0]: 32
8601 22:14:46.079458 [Byte1]: 32
8602 22:14:46.084111
8603 22:14:46.084186 Set Vref, RX VrefLevel [Byte0]: 33
8604 22:14:46.087208 [Byte1]: 33
8605 22:14:46.091449
8606 22:14:46.091523 Set Vref, RX VrefLevel [Byte0]: 34
8607 22:14:46.095038 [Byte1]: 34
8608 22:14:46.098917
8609 22:14:46.099034 Set Vref, RX VrefLevel [Byte0]: 35
8610 22:14:46.102437 [Byte1]: 35
8611 22:14:46.107255
8612 22:14:46.107364 Set Vref, RX VrefLevel [Byte0]: 36
8613 22:14:46.110344 [Byte1]: 36
8614 22:14:46.114030
8615 22:14:46.114105 Set Vref, RX VrefLevel [Byte0]: 37
8616 22:14:46.117545 [Byte1]: 37
8617 22:14:46.122125
8618 22:14:46.122228 Set Vref, RX VrefLevel [Byte0]: 38
8619 22:14:46.125466 [Byte1]: 38
8620 22:14:46.129288
8621 22:14:46.132336 Set Vref, RX VrefLevel [Byte0]: 39
8622 22:14:46.135563 [Byte1]: 39
8623 22:14:46.135668
8624 22:14:46.139198 Set Vref, RX VrefLevel [Byte0]: 40
8625 22:14:46.142262 [Byte1]: 40
8626 22:14:46.142363
8627 22:14:46.145694 Set Vref, RX VrefLevel [Byte0]: 41
8628 22:14:46.148789 [Byte1]: 41
8629 22:14:46.148886
8630 22:14:46.152343 Set Vref, RX VrefLevel [Byte0]: 42
8631 22:14:46.155736 [Byte1]: 42
8632 22:14:46.159938
8633 22:14:46.160012 Set Vref, RX VrefLevel [Byte0]: 43
8634 22:14:46.163211 [Byte1]: 43
8635 22:14:46.166965
8636 22:14:46.167065 Set Vref, RX VrefLevel [Byte0]: 44
8637 22:14:46.170955 [Byte1]: 44
8638 22:14:46.175085
8639 22:14:46.175167 Set Vref, RX VrefLevel [Byte0]: 45
8640 22:14:46.177957 [Byte1]: 45
8641 22:14:46.182550
8642 22:14:46.182655 Set Vref, RX VrefLevel [Byte0]: 46
8643 22:14:46.186322 [Byte1]: 46
8644 22:14:46.190045
8645 22:14:46.190128 Set Vref, RX VrefLevel [Byte0]: 47
8646 22:14:46.193162 [Byte1]: 47
8647 22:14:46.197650
8648 22:14:46.197755 Set Vref, RX VrefLevel [Byte0]: 48
8649 22:14:46.200577 [Byte1]: 48
8650 22:14:46.205112
8651 22:14:46.205203 Set Vref, RX VrefLevel [Byte0]: 49
8652 22:14:46.208593 [Byte1]: 49
8653 22:14:46.212846
8654 22:14:46.213002 Set Vref, RX VrefLevel [Byte0]: 50
8655 22:14:46.216262 [Byte1]: 50
8656 22:14:46.220212
8657 22:14:46.220295 Set Vref, RX VrefLevel [Byte0]: 51
8658 22:14:46.223594 [Byte1]: 51
8659 22:14:46.227719
8660 22:14:46.227802 Set Vref, RX VrefLevel [Byte0]: 52
8661 22:14:46.230884 [Byte1]: 52
8662 22:14:46.235326
8663 22:14:46.235433 Set Vref, RX VrefLevel [Byte0]: 53
8664 22:14:46.238896 [Byte1]: 53
8665 22:14:46.242822
8666 22:14:46.242922 Set Vref, RX VrefLevel [Byte0]: 54
8667 22:14:46.246458 [Byte1]: 54
8668 22:14:46.250592
8669 22:14:46.250676 Set Vref, RX VrefLevel [Byte0]: 55
8670 22:14:46.254092 [Byte1]: 55
8671 22:14:46.258163
8672 22:14:46.258247 Set Vref, RX VrefLevel [Byte0]: 56
8673 22:14:46.264637 [Byte1]: 56
8674 22:14:46.264720
8675 22:14:46.267614 Set Vref, RX VrefLevel [Byte0]: 57
8676 22:14:46.271191 [Byte1]: 57
8677 22:14:46.271280
8678 22:14:46.274550 Set Vref, RX VrefLevel [Byte0]: 58
8679 22:14:46.277659 [Byte1]: 58
8680 22:14:46.277747
8681 22:14:46.281169 Set Vref, RX VrefLevel [Byte0]: 59
8682 22:14:46.284448 [Byte1]: 59
8683 22:14:46.288535
8684 22:14:46.288627 Set Vref, RX VrefLevel [Byte0]: 60
8685 22:14:46.291492 [Byte1]: 60
8686 22:14:46.295849
8687 22:14:46.295971 Set Vref, RX VrefLevel [Byte0]: 61
8688 22:14:46.299251 [Byte1]: 61
8689 22:14:46.303613
8690 22:14:46.303697 Set Vref, RX VrefLevel [Byte0]: 62
8691 22:14:46.306546 [Byte1]: 62
8692 22:14:46.311132
8693 22:14:46.311216 Set Vref, RX VrefLevel [Byte0]: 63
8694 22:14:46.314869 [Byte1]: 63
8695 22:14:46.318946
8696 22:14:46.319051 Set Vref, RX VrefLevel [Byte0]: 64
8697 22:14:46.322039 [Byte1]: 64
8698 22:14:46.326373
8699 22:14:46.326463 Set Vref, RX VrefLevel [Byte0]: 65
8700 22:14:46.329594 [Byte1]: 65
8701 22:14:46.333943
8702 22:14:46.334033 Set Vref, RX VrefLevel [Byte0]: 66
8703 22:14:46.337294 [Byte1]: 66
8704 22:14:46.341231
8705 22:14:46.341326 Set Vref, RX VrefLevel [Byte0]: 67
8706 22:14:46.344568 [Byte1]: 67
8707 22:14:46.349421
8708 22:14:46.349512 Set Vref, RX VrefLevel [Byte0]: 68
8709 22:14:46.352317 [Byte1]: 68
8710 22:14:46.356505
8711 22:14:46.356595 Set Vref, RX VrefLevel [Byte0]: 69
8712 22:14:46.360183 [Byte1]: 69
8713 22:14:46.364720
8714 22:14:46.364803 Set Vref, RX VrefLevel [Byte0]: 70
8715 22:14:46.367188 [Byte1]: 70
8716 22:14:46.371867
8717 22:14:46.371949 Set Vref, RX VrefLevel [Byte0]: 71
8718 22:14:46.374756 [Byte1]: 71
8719 22:14:46.378993
8720 22:14:46.379080 Set Vref, RX VrefLevel [Byte0]: 72
8721 22:14:46.382542 [Byte1]: 72
8722 22:14:46.387003
8723 22:14:46.387091 Set Vref, RX VrefLevel [Byte0]: 73
8724 22:14:46.389902 [Byte1]: 73
8725 22:14:46.394594
8726 22:14:46.394687 Set Vref, RX VrefLevel [Byte0]: 74
8727 22:14:46.397610 [Byte1]: 74
8728 22:14:46.402373
8729 22:14:46.402455 Set Vref, RX VrefLevel [Byte0]: 75
8730 22:14:46.405185 [Byte1]: 75
8731 22:14:46.409488
8732 22:14:46.409572 Final RX Vref Byte 0 = 59 to rank0
8733 22:14:46.412698 Final RX Vref Byte 1 = 56 to rank0
8734 22:14:46.416146 Final RX Vref Byte 0 = 59 to rank1
8735 22:14:46.419737 Final RX Vref Byte 1 = 56 to rank1==
8736 22:14:46.423126 Dram Type= 6, Freq= 0, CH_1, rank 0
8737 22:14:46.429527 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8738 22:14:46.429627 ==
8739 22:14:46.429702 DQS Delay:
8740 22:14:46.429767 DQS0 = 0, DQS1 = 0
8741 22:14:46.432929 DQM Delay:
8742 22:14:46.433016 DQM0 = 131, DQM1 = 124
8743 22:14:46.436152 DQ Delay:
8744 22:14:46.439110 DQ0 =134, DQ1 =126, DQ2 =120, DQ3 =130
8745 22:14:46.442565 DQ4 =130, DQ5 =142, DQ6 =142, DQ7 =128
8746 22:14:46.446518 DQ8 =112, DQ9 =112, DQ10 =126, DQ11 =120
8747 22:14:46.449283 DQ12 =132, DQ13 =132, DQ14 =130, DQ15 =132
8748 22:14:46.449369
8749 22:14:46.449453
8750 22:14:46.449533
8751 22:14:46.452671 [DramC_TX_OE_Calibration] TA2
8752 22:14:46.456144 Original DQ_B0 (3 6) =30, OEN = 27
8753 22:14:46.459024 Original DQ_B1 (3 6) =30, OEN = 27
8754 22:14:46.462785 24, 0x0, End_B0=24 End_B1=24
8755 22:14:46.462869 25, 0x0, End_B0=25 End_B1=25
8756 22:14:46.465840 26, 0x0, End_B0=26 End_B1=26
8757 22:14:46.469580 27, 0x0, End_B0=27 End_B1=27
8758 22:14:46.472653 28, 0x0, End_B0=28 End_B1=28
8759 22:14:46.475743 29, 0x0, End_B0=29 End_B1=29
8760 22:14:46.475828 30, 0x0, End_B0=30 End_B1=30
8761 22:14:46.479185 31, 0x4141, End_B0=30 End_B1=30
8762 22:14:46.482743 Byte0 end_step=30 best_step=27
8763 22:14:46.485981 Byte1 end_step=30 best_step=27
8764 22:14:46.489416 Byte0 TX OE(2T, 0.5T) = (3, 3)
8765 22:14:46.492923 Byte1 TX OE(2T, 0.5T) = (3, 3)
8766 22:14:46.493005
8767 22:14:46.493070
8768 22:14:46.499090 [DQSOSCAuto] RK0, (LSB)MR18= 0x13fd, (MSB)MR19= 0x302, tDQSOscB0 = 411 ps tDQSOscB1 = 400 ps
8769 22:14:46.502755 CH1 RK0: MR19=302, MR18=13FD
8770 22:14:46.509209 CH1_RK0: MR19=0x302, MR18=0x13FD, DQSOSC=400, MR23=63, INC=23, DEC=15
8771 22:14:46.509307
8772 22:14:46.512486 ----->DramcWriteLeveling(PI) begin...
8773 22:14:46.512571 ==
8774 22:14:46.516115 Dram Type= 6, Freq= 0, CH_1, rank 1
8775 22:14:46.519303 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8776 22:14:46.519426 ==
8777 22:14:46.522350 Write leveling (Byte 0): 23 => 23
8778 22:14:46.526032 Write leveling (Byte 1): 27 => 27
8779 22:14:46.529448 DramcWriteLeveling(PI) end<-----
8780 22:14:46.529534
8781 22:14:46.529601 ==
8782 22:14:46.532413 Dram Type= 6, Freq= 0, CH_1, rank 1
8783 22:14:46.535684 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8784 22:14:46.535787 ==
8785 22:14:46.539145 [Gating] SW mode calibration
8786 22:14:46.545791 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8787 22:14:46.552289 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8788 22:14:46.555735 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8789 22:14:46.559286 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8790 22:14:46.565291 1 4 8 | B1->B0 | 2323 2525 | 0 1 | (0 0) (1 1)
8791 22:14:46.568709 1 4 12 | B1->B0 | 2727 3333 | 0 0 | (0 0) (0 0)
8792 22:14:46.572412 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8793 22:14:46.578933 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8794 22:14:46.581909 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8795 22:14:46.585461 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8796 22:14:46.592002 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8797 22:14:46.595446 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8798 22:14:46.598770 1 5 8 | B1->B0 | 3434 2d2d | 1 0 | (1 0) (1 0)
8799 22:14:46.605639 1 5 12 | B1->B0 | 2b2b 2323 | 0 0 | (0 0) (0 0)
8800 22:14:46.608923 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8801 22:14:46.612496 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8802 22:14:46.619227 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8803 22:14:46.622275 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8804 22:14:46.625284 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8805 22:14:46.632248 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8806 22:14:46.635291 1 6 8 | B1->B0 | 2626 4141 | 0 0 | (0 0) (0 0)
8807 22:14:46.638834 1 6 12 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
8808 22:14:46.645510 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8809 22:14:46.648618 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8810 22:14:46.651718 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8811 22:14:46.658384 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8812 22:14:46.662016 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8813 22:14:46.665043 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8814 22:14:46.671540 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8815 22:14:46.675104 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8816 22:14:46.678160 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8817 22:14:46.685198 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8818 22:14:46.688265 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8819 22:14:46.691493 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8820 22:14:46.695373 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8821 22:14:46.701474 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8822 22:14:46.705292 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8823 22:14:46.708123 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8824 22:14:46.715609 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8825 22:14:46.718262 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8826 22:14:46.721890 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8827 22:14:46.728350 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8828 22:14:46.731896 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8829 22:14:46.734787 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8830 22:14:46.741958 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8831 22:14:46.745145 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8832 22:14:46.748632 Total UI for P1: 0, mck2ui 16
8833 22:14:46.751950 best dqsien dly found for B0: ( 1, 9, 6)
8834 22:14:46.755280 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8835 22:14:46.761507 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8836 22:14:46.761591 Total UI for P1: 0, mck2ui 16
8837 22:14:46.768029 best dqsien dly found for B1: ( 1, 9, 12)
8838 22:14:46.771589 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8839 22:14:46.774553 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8840 22:14:46.774637
8841 22:14:46.778024 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8842 22:14:46.781686 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8843 22:14:46.784652 [Gating] SW calibration Done
8844 22:14:46.784736 ==
8845 22:14:46.788488 Dram Type= 6, Freq= 0, CH_1, rank 1
8846 22:14:46.791593 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8847 22:14:46.791677 ==
8848 22:14:46.794624 RX Vref Scan: 0
8849 22:14:46.794708
8850 22:14:46.794775 RX Vref 0 -> 0, step: 1
8851 22:14:46.794837
8852 22:14:46.798451 RX Delay 0 -> 252, step: 8
8853 22:14:46.801297 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8854 22:14:46.808354 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8855 22:14:46.811230 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8856 22:14:46.814798 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8857 22:14:46.817791 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8858 22:14:46.821146 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8859 22:14:46.827908 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8860 22:14:46.830945 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8861 22:14:46.834994 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8862 22:14:46.837960 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8863 22:14:46.841288 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8864 22:14:46.848140 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8865 22:14:46.851456 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8866 22:14:46.854790 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8867 22:14:46.857660 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8868 22:14:46.860984 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8869 22:14:46.864377 ==
8870 22:14:46.864495 Dram Type= 6, Freq= 0, CH_1, rank 1
8871 22:14:46.870879 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8872 22:14:46.870981 ==
8873 22:14:46.871081 DQS Delay:
8874 22:14:46.874467 DQS0 = 0, DQS1 = 0
8875 22:14:46.874544 DQM Delay:
8876 22:14:46.878041 DQM0 = 133, DQM1 = 127
8877 22:14:46.878147 DQ Delay:
8878 22:14:46.880954 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =131
8879 22:14:46.884654 DQ4 =135, DQ5 =147, DQ6 =143, DQ7 =127
8880 22:14:46.887523 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =119
8881 22:14:46.890933 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8882 22:14:46.891037
8883 22:14:46.891101
8884 22:14:46.891206 ==
8885 22:14:46.894262 Dram Type= 6, Freq= 0, CH_1, rank 1
8886 22:14:46.901224 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8887 22:14:46.901355 ==
8888 22:14:46.901488
8889 22:14:46.901592
8890 22:14:46.901688 TX Vref Scan disable
8891 22:14:46.904479 == TX Byte 0 ==
8892 22:14:46.907895 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8893 22:14:46.914407 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8894 22:14:46.914515 == TX Byte 1 ==
8895 22:14:46.917838 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8896 22:14:46.924094 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8897 22:14:46.924214 ==
8898 22:14:46.927663 Dram Type= 6, Freq= 0, CH_1, rank 1
8899 22:14:46.930637 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8900 22:14:46.930721 ==
8901 22:14:46.944777
8902 22:14:46.947954 TX Vref early break, caculate TX vref
8903 22:14:46.951543 TX Vref=16, minBit 8, minWin=22, winSum=381
8904 22:14:46.954739 TX Vref=18, minBit 8, minWin=22, winSum=394
8905 22:14:46.957613 TX Vref=20, minBit 8, minWin=23, winSum=398
8906 22:14:46.960962 TX Vref=22, minBit 8, minWin=24, winSum=407
8907 22:14:46.964693 TX Vref=24, minBit 15, minWin=24, winSum=417
8908 22:14:46.971624 TX Vref=26, minBit 8, minWin=25, winSum=422
8909 22:14:46.974477 TX Vref=28, minBit 0, minWin=25, winSum=424
8910 22:14:46.978134 TX Vref=30, minBit 5, minWin=25, winSum=420
8911 22:14:46.980955 TX Vref=32, minBit 0, minWin=25, winSum=418
8912 22:14:46.984515 TX Vref=34, minBit 0, minWin=25, winSum=410
8913 22:14:46.987981 TX Vref=36, minBit 0, minWin=24, winSum=399
8914 22:14:46.994546 [TxChooseVref] Worse bit 0, Min win 25, Win sum 424, Final Vref 28
8915 22:14:46.994656
8916 22:14:46.997614 Final TX Range 0 Vref 28
8917 22:14:46.997714
8918 22:14:46.997808 ==
8919 22:14:47.001053 Dram Type= 6, Freq= 0, CH_1, rank 1
8920 22:14:47.004322 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8921 22:14:47.004424 ==
8922 22:14:47.004526
8923 22:14:47.007635
8924 22:14:47.007803 TX Vref Scan disable
8925 22:14:47.014317 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8926 22:14:47.014423 == TX Byte 0 ==
8927 22:14:47.017433 u2DelayCellOfst[0]=17 cells (5 PI)
8928 22:14:47.020760 u2DelayCellOfst[1]=14 cells (4 PI)
8929 22:14:47.024237 u2DelayCellOfst[2]=0 cells (0 PI)
8930 22:14:47.027675 u2DelayCellOfst[3]=7 cells (2 PI)
8931 22:14:47.030786 u2DelayCellOfst[4]=7 cells (2 PI)
8932 22:14:47.033831 u2DelayCellOfst[5]=17 cells (5 PI)
8933 22:14:47.037263 u2DelayCellOfst[6]=17 cells (5 PI)
8934 22:14:47.040707 u2DelayCellOfst[7]=3 cells (1 PI)
8935 22:14:47.044000 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8936 22:14:47.047303 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8937 22:14:47.051362 == TX Byte 1 ==
8938 22:14:47.054364 u2DelayCellOfst[8]=0 cells (0 PI)
8939 22:14:47.057496 u2DelayCellOfst[9]=3 cells (1 PI)
8940 22:14:47.060606 u2DelayCellOfst[10]=10 cells (3 PI)
8941 22:14:47.060688 u2DelayCellOfst[11]=3 cells (1 PI)
8942 22:14:47.064077 u2DelayCellOfst[12]=14 cells (4 PI)
8943 22:14:47.066986 u2DelayCellOfst[13]=14 cells (4 PI)
8944 22:14:47.070388 u2DelayCellOfst[14]=17 cells (5 PI)
8945 22:14:47.073643 u2DelayCellOfst[15]=14 cells (4 PI)
8946 22:14:47.080697 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8947 22:14:47.083652 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8948 22:14:47.083735 DramC Write-DBI on
8949 22:14:47.086853 ==
8950 22:14:47.086935 Dram Type= 6, Freq= 0, CH_1, rank 1
8951 22:14:47.093163 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8952 22:14:47.093246 ==
8953 22:14:47.093312
8954 22:14:47.093372
8955 22:14:47.096557 TX Vref Scan disable
8956 22:14:47.096675 == TX Byte 0 ==
8957 22:14:47.103201 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8958 22:14:47.103309 == TX Byte 1 ==
8959 22:14:47.106950 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8960 22:14:47.109773 DramC Write-DBI off
8961 22:14:47.109855
8962 22:14:47.109921 [DATLAT]
8963 22:14:47.113360 Freq=1600, CH1 RK1
8964 22:14:47.113443
8965 22:14:47.113508 DATLAT Default: 0xf
8966 22:14:47.117069 0, 0xFFFF, sum = 0
8967 22:14:47.117154 1, 0xFFFF, sum = 0
8968 22:14:47.119984 2, 0xFFFF, sum = 0
8969 22:14:47.120068 3, 0xFFFF, sum = 0
8970 22:14:47.123467 4, 0xFFFF, sum = 0
8971 22:14:47.123580 5, 0xFFFF, sum = 0
8972 22:14:47.126317 6, 0xFFFF, sum = 0
8973 22:14:47.126451 7, 0xFFFF, sum = 0
8974 22:14:47.129842 8, 0xFFFF, sum = 0
8975 22:14:47.133409 9, 0xFFFF, sum = 0
8976 22:14:47.133515 10, 0xFFFF, sum = 0
8977 22:14:47.136423 11, 0xFFFF, sum = 0
8978 22:14:47.136526 12, 0xFFFF, sum = 0
8979 22:14:47.139809 13, 0xFFFF, sum = 0
8980 22:14:47.139920 14, 0x0, sum = 1
8981 22:14:47.143027 15, 0x0, sum = 2
8982 22:14:47.143132 16, 0x0, sum = 3
8983 22:14:47.146390 17, 0x0, sum = 4
8984 22:14:47.146500 best_step = 15
8985 22:14:47.146592
8986 22:14:47.146681 ==
8987 22:14:47.149792 Dram Type= 6, Freq= 0, CH_1, rank 1
8988 22:14:47.153061 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8989 22:14:47.153165 ==
8990 22:14:47.156231 RX Vref Scan: 0
8991 22:14:47.156420
8992 22:14:47.159322 RX Vref 0 -> 0, step: 1
8993 22:14:47.159449
8994 22:14:47.159542 RX Delay 11 -> 252, step: 4
8995 22:14:47.167093 iDelay=195, Bit 0, Center 132 (83 ~ 182) 100
8996 22:14:47.170248 iDelay=195, Bit 1, Center 126 (75 ~ 178) 104
8997 22:14:47.173496 iDelay=195, Bit 2, Center 116 (63 ~ 170) 108
8998 22:14:47.176821 iDelay=195, Bit 3, Center 126 (75 ~ 178) 104
8999 22:14:47.180189 iDelay=195, Bit 4, Center 128 (75 ~ 182) 108
9000 22:14:47.186643 iDelay=195, Bit 5, Center 144 (95 ~ 194) 100
9001 22:14:47.190264 iDelay=195, Bit 6, Center 138 (87 ~ 190) 104
9002 22:14:47.193308 iDelay=195, Bit 7, Center 124 (71 ~ 178) 108
9003 22:14:47.196806 iDelay=195, Bit 8, Center 114 (59 ~ 170) 112
9004 22:14:47.200336 iDelay=195, Bit 9, Center 114 (59 ~ 170) 112
9005 22:14:47.206316 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
9006 22:14:47.209951 iDelay=195, Bit 11, Center 118 (67 ~ 170) 104
9007 22:14:47.213196 iDelay=195, Bit 12, Center 134 (83 ~ 186) 104
9008 22:14:47.216391 iDelay=195, Bit 13, Center 136 (83 ~ 190) 108
9009 22:14:47.222913 iDelay=195, Bit 14, Center 136 (83 ~ 190) 108
9010 22:14:47.226320 iDelay=195, Bit 15, Center 136 (83 ~ 190) 108
9011 22:14:47.226404 ==
9012 22:14:47.229423 Dram Type= 6, Freq= 0, CH_1, rank 1
9013 22:14:47.232739 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9014 22:14:47.232823 ==
9015 22:14:47.236202 DQS Delay:
9016 22:14:47.236286 DQS0 = 0, DQS1 = 0
9017 22:14:47.236354 DQM Delay:
9018 22:14:47.239265 DQM0 = 129, DQM1 = 127
9019 22:14:47.239373 DQ Delay:
9020 22:14:47.243453 DQ0 =132, DQ1 =126, DQ2 =116, DQ3 =126
9021 22:14:47.246289 DQ4 =128, DQ5 =144, DQ6 =138, DQ7 =124
9022 22:14:47.252726 DQ8 =114, DQ9 =114, DQ10 =128, DQ11 =118
9023 22:14:47.256171 DQ12 =134, DQ13 =136, DQ14 =136, DQ15 =136
9024 22:14:47.256255
9025 22:14:47.256321
9026 22:14:47.256383
9027 22:14:47.259554 [DramC_TX_OE_Calibration] TA2
9028 22:14:47.262863 Original DQ_B0 (3 6) =30, OEN = 27
9029 22:14:47.262948 Original DQ_B1 (3 6) =30, OEN = 27
9030 22:14:47.266116 24, 0x0, End_B0=24 End_B1=24
9031 22:14:47.269328 25, 0x0, End_B0=25 End_B1=25
9032 22:14:47.272718 26, 0x0, End_B0=26 End_B1=26
9033 22:14:47.276129 27, 0x0, End_B0=27 End_B1=27
9034 22:14:47.276214 28, 0x0, End_B0=28 End_B1=28
9035 22:14:47.279530 29, 0x0, End_B0=29 End_B1=29
9036 22:14:47.282371 30, 0x0, End_B0=30 End_B1=30
9037 22:14:47.285720 31, 0x4141, End_B0=30 End_B1=30
9038 22:14:47.289300 Byte0 end_step=30 best_step=27
9039 22:14:47.292215 Byte1 end_step=30 best_step=27
9040 22:14:47.292299 Byte0 TX OE(2T, 0.5T) = (3, 3)
9041 22:14:47.295758 Byte1 TX OE(2T, 0.5T) = (3, 3)
9042 22:14:47.295842
9043 22:14:47.295909
9044 22:14:47.305703 [DQSOSCAuto] RK1, (LSB)MR18= 0xd12, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 403 ps
9045 22:14:47.305789 CH1 RK1: MR19=303, MR18=D12
9046 22:14:47.312265 CH1_RK1: MR19=0x303, MR18=0xD12, DQSOSC=400, MR23=63, INC=23, DEC=15
9047 22:14:47.315740 [RxdqsGatingPostProcess] freq 1600
9048 22:14:47.322555 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9049 22:14:47.325775 best DQS0 dly(2T, 0.5T) = (1, 1)
9050 22:14:47.328872 best DQS1 dly(2T, 0.5T) = (1, 1)
9051 22:14:47.332222 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9052 22:14:47.335570 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9053 22:14:47.335654 best DQS0 dly(2T, 0.5T) = (1, 1)
9054 22:14:47.338890 best DQS1 dly(2T, 0.5T) = (1, 1)
9055 22:14:47.342487 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9056 22:14:47.345974 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9057 22:14:47.348936 Pre-setting of DQS Precalculation
9058 22:14:47.355717 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9059 22:14:47.362290 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9060 22:14:47.368807 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9061 22:14:47.368892
9062 22:14:47.368959
9063 22:14:47.372438 [Calibration Summary] 3200 Mbps
9064 22:14:47.372550 CH 0, Rank 0
9065 22:14:47.375742 SW Impedance : PASS
9066 22:14:47.379220 DUTY Scan : NO K
9067 22:14:47.379304 ZQ Calibration : PASS
9068 22:14:47.382498 Jitter Meter : NO K
9069 22:14:47.385122 CBT Training : PASS
9070 22:14:47.385206 Write leveling : PASS
9071 22:14:47.388756 RX DQS gating : PASS
9072 22:14:47.392272 RX DQ/DQS(RDDQC) : PASS
9073 22:14:47.392356 TX DQ/DQS : PASS
9074 22:14:47.395516 RX DATLAT : PASS
9075 22:14:47.398948 RX DQ/DQS(Engine): PASS
9076 22:14:47.399031 TX OE : PASS
9077 22:14:47.399098 All Pass.
9078 22:14:47.401892
9079 22:14:47.401976 CH 0, Rank 1
9080 22:14:47.405244 SW Impedance : PASS
9081 22:14:47.405328 DUTY Scan : NO K
9082 22:14:47.408266 ZQ Calibration : PASS
9083 22:14:47.408375 Jitter Meter : NO K
9084 22:14:47.411673 CBT Training : PASS
9085 22:14:47.415221 Write leveling : PASS
9086 22:14:47.415305 RX DQS gating : PASS
9087 22:14:47.418874 RX DQ/DQS(RDDQC) : PASS
9088 22:14:47.421810 TX DQ/DQS : PASS
9089 22:14:47.421894 RX DATLAT : PASS
9090 22:14:47.425183 RX DQ/DQS(Engine): PASS
9091 22:14:47.428647 TX OE : PASS
9092 22:14:47.428752 All Pass.
9093 22:14:47.428824
9094 22:14:47.428901 CH 1, Rank 0
9095 22:14:47.431538 SW Impedance : PASS
9096 22:14:47.435292 DUTY Scan : NO K
9097 22:14:47.435430 ZQ Calibration : PASS
9098 22:14:47.438191 Jitter Meter : NO K
9099 22:14:47.441553 CBT Training : PASS
9100 22:14:47.441637 Write leveling : PASS
9101 22:14:47.444849 RX DQS gating : PASS
9102 22:14:47.448397 RX DQ/DQS(RDDQC) : PASS
9103 22:14:47.448481 TX DQ/DQS : PASS
9104 22:14:47.451846 RX DATLAT : PASS
9105 22:14:47.454947 RX DQ/DQS(Engine): PASS
9106 22:14:47.455030 TX OE : PASS
9107 22:14:47.455098 All Pass.
9108 22:14:47.458436
9109 22:14:47.458520 CH 1, Rank 1
9110 22:14:47.461846 SW Impedance : PASS
9111 22:14:47.461930 DUTY Scan : NO K
9112 22:14:47.464837 ZQ Calibration : PASS
9113 22:14:47.464948 Jitter Meter : NO K
9114 22:14:47.468410 CBT Training : PASS
9115 22:14:47.471710 Write leveling : PASS
9116 22:14:47.471815 RX DQS gating : PASS
9117 22:14:47.474970 RX DQ/DQS(RDDQC) : PASS
9118 22:14:47.477886 TX DQ/DQS : PASS
9119 22:14:47.477993 RX DATLAT : PASS
9120 22:14:47.481273 RX DQ/DQS(Engine): PASS
9121 22:14:47.484702 TX OE : PASS
9122 22:14:47.484817 All Pass.
9123 22:14:47.484917
9124 22:14:47.488030 DramC Write-DBI on
9125 22:14:47.488139 PER_BANK_REFRESH: Hybrid Mode
9126 22:14:47.491311 TX_TRACKING: ON
9127 22:14:47.501495 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9128 22:14:47.507831 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9129 22:14:47.514599 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9130 22:14:47.517799 [FAST_K] Save calibration result to emmc
9131 22:14:47.521041 sync common calibartion params.
9132 22:14:47.524564 sync cbt_mode0:1, 1:1
9133 22:14:47.524648 dram_init: ddr_geometry: 2
9134 22:14:47.527983 dram_init: ddr_geometry: 2
9135 22:14:47.531418 dram_init: ddr_geometry: 2
9136 22:14:47.534507 0:dram_rank_size:100000000
9137 22:14:47.534593 1:dram_rank_size:100000000
9138 22:14:47.541190 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9139 22:14:47.544021 DFS_SHUFFLE_HW_MODE: ON
9140 22:14:47.548010 dramc_set_vcore_voltage set vcore to 725000
9141 22:14:47.551060 Read voltage for 1600, 0
9142 22:14:47.551143 Vio18 = 0
9143 22:14:47.551208 Vcore = 725000
9144 22:14:47.554479 Vdram = 0
9145 22:14:47.554564 Vddq = 0
9146 22:14:47.554629 Vmddr = 0
9147 22:14:47.557506 switch to 3200 Mbps bootup
9148 22:14:47.557589 [DramcRunTimeConfig]
9149 22:14:47.560543 PHYPLL
9150 22:14:47.560626 DPM_CONTROL_AFTERK: ON
9151 22:14:47.564010 PER_BANK_REFRESH: ON
9152 22:14:47.567276 REFRESH_OVERHEAD_REDUCTION: ON
9153 22:14:47.567401 CMD_PICG_NEW_MODE: OFF
9154 22:14:47.570476 XRTWTW_NEW_MODE: ON
9155 22:14:47.570558 XRTRTR_NEW_MODE: ON
9156 22:14:47.574072 TX_TRACKING: ON
9157 22:14:47.574155 RDSEL_TRACKING: OFF
9158 22:14:47.576979 DQS Precalculation for DVFS: ON
9159 22:14:47.580925 RX_TRACKING: OFF
9160 22:14:47.581034 HW_GATING DBG: ON
9161 22:14:47.583865 ZQCS_ENABLE_LP4: ON
9162 22:14:47.583962 RX_PICG_NEW_MODE: ON
9163 22:14:47.587308 TX_PICG_NEW_MODE: ON
9164 22:14:47.587423 ENABLE_RX_DCM_DPHY: ON
9165 22:14:47.590904 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9166 22:14:47.594046 DUMMY_READ_FOR_TRACKING: OFF
9167 22:14:47.596921 !!! SPM_CONTROL_AFTERK: OFF
9168 22:14:47.600603 !!! SPM could not control APHY
9169 22:14:47.600687 IMPEDANCE_TRACKING: ON
9170 22:14:47.603622 TEMP_SENSOR: ON
9171 22:14:47.603706 HW_SAVE_FOR_SR: OFF
9172 22:14:47.607193 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9173 22:14:47.610731 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9174 22:14:47.613614 Read ODT Tracking: ON
9175 22:14:47.617217 Refresh Rate DeBounce: ON
9176 22:14:47.617299 DFS_NO_QUEUE_FLUSH: ON
9177 22:14:47.620170 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9178 22:14:47.623665 ENABLE_DFS_RUNTIME_MRW: OFF
9179 22:14:47.627190 DDR_RESERVE_NEW_MODE: ON
9180 22:14:47.627272 MR_CBT_SWITCH_FREQ: ON
9181 22:14:47.630205 =========================
9182 22:14:47.649103 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9183 22:14:47.652406 dram_init: ddr_geometry: 2
9184 22:14:47.670819 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9185 22:14:47.674264 dram_init: dram init end (result: 0)
9186 22:14:47.680498 DRAM-K: Full calibration passed in 24613 msecs
9187 22:14:47.683829 MRC: failed to locate region type 0.
9188 22:14:47.683913 DRAM rank0 size:0x100000000,
9189 22:14:47.687112 DRAM rank1 size=0x100000000
9190 22:14:47.697350 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9191 22:14:47.703812 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9192 22:14:47.710318 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9193 22:14:47.716972 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9194 22:14:47.720597 DRAM rank0 size:0x100000000,
9195 22:14:47.723490 DRAM rank1 size=0x100000000
9196 22:14:47.723573 CBMEM:
9197 22:14:47.727058 IMD: root @ 0xfffff000 254 entries.
9198 22:14:47.730144 IMD: root @ 0xffffec00 62 entries.
9199 22:14:47.733832 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9200 22:14:47.739999 WARNING: RO_VPD is uninitialized or empty.
9201 22:14:47.743264 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9202 22:14:47.750608 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9203 22:14:47.763560 read SPI 0x42894 0xe01e: 6227 us, 9213 KB/s, 73.704 Mbps
9204 22:14:47.774791 BS: romstage times (exec / console): total (unknown) / 24114 ms
9205 22:14:47.774878
9206 22:14:47.774945
9207 22:14:47.784921 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9208 22:14:47.788525 ARM64: Exception handlers installed.
9209 22:14:47.791691 ARM64: Testing exception
9210 22:14:47.794863 ARM64: Done test exception
9211 22:14:47.794979 Enumerating buses...
9212 22:14:47.798481 Show all devs... Before device enumeration.
9213 22:14:47.801652 Root Device: enabled 1
9214 22:14:47.805000 CPU_CLUSTER: 0: enabled 1
9215 22:14:47.805078 CPU: 00: enabled 1
9216 22:14:47.807999 Compare with tree...
9217 22:14:47.808074 Root Device: enabled 1
9218 22:14:47.811552 CPU_CLUSTER: 0: enabled 1
9219 22:14:47.815109 CPU: 00: enabled 1
9220 22:14:47.815182 Root Device scanning...
9221 22:14:47.818102 scan_static_bus for Root Device
9222 22:14:47.821713 CPU_CLUSTER: 0 enabled
9223 22:14:47.824622 scan_static_bus for Root Device done
9224 22:14:47.828154 scan_bus: bus Root Device finished in 8 msecs
9225 22:14:47.828228 done
9226 22:14:47.834684 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9227 22:14:47.838079 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9228 22:14:47.844747 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9229 22:14:47.848434 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9230 22:14:47.851235 Allocating resources...
9231 22:14:47.854823 Reading resources...
9232 22:14:47.858155 Root Device read_resources bus 0 link: 0
9233 22:14:47.858231 DRAM rank0 size:0x100000000,
9234 22:14:47.861334 DRAM rank1 size=0x100000000
9235 22:14:47.864728 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9236 22:14:47.868143 CPU: 00 missing read_resources
9237 22:14:47.871499 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9238 22:14:47.877886 Root Device read_resources bus 0 link: 0 done
9239 22:14:47.877995 Done reading resources.
9240 22:14:47.884741 Show resources in subtree (Root Device)...After reading.
9241 22:14:47.888175 Root Device child on link 0 CPU_CLUSTER: 0
9242 22:14:47.891511 CPU_CLUSTER: 0 child on link 0 CPU: 00
9243 22:14:47.901078 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9244 22:14:47.901165 CPU: 00
9245 22:14:47.904845 Root Device assign_resources, bus 0 link: 0
9246 22:14:47.908185 CPU_CLUSTER: 0 missing set_resources
9247 22:14:47.911323 Root Device assign_resources, bus 0 link: 0 done
9248 22:14:47.914783 Done setting resources.
9249 22:14:47.921312 Show resources in subtree (Root Device)...After assigning values.
9250 22:14:47.924826 Root Device child on link 0 CPU_CLUSTER: 0
9251 22:14:47.927792 CPU_CLUSTER: 0 child on link 0 CPU: 00
9252 22:14:47.937978 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9253 22:14:47.938061 CPU: 00
9254 22:14:47.941123 Done allocating resources.
9255 22:14:47.943934 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9256 22:14:47.947335 Enabling resources...
9257 22:14:47.947455 done.
9258 22:14:47.954006 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9259 22:14:47.954089 Initializing devices...
9260 22:14:47.957195 Root Device init
9261 22:14:47.957277 init hardware done!
9262 22:14:47.961093 0x00000018: ctrlr->caps
9263 22:14:47.963957 52.000 MHz: ctrlr->f_max
9264 22:14:47.964041 0.400 MHz: ctrlr->f_min
9265 22:14:47.967807 0x40ff8080: ctrlr->voltages
9266 22:14:47.967890 sclk: 390625
9267 22:14:47.970804 Bus Width = 1
9268 22:14:47.970886 sclk: 390625
9269 22:14:47.974241 Bus Width = 1
9270 22:14:47.974322 Early init status = 3
9271 22:14:47.980933 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9272 22:14:47.984493 in-header: 03 fc 00 00 01 00 00 00
9273 22:14:47.984575 in-data: 00
9274 22:14:47.991147 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9275 22:14:47.993960 in-header: 03 fd 00 00 00 00 00 00
9276 22:14:47.997808 in-data:
9277 22:14:48.001276 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9278 22:14:48.004001 in-header: 03 fc 00 00 01 00 00 00
9279 22:14:48.007544 in-data: 00
9280 22:14:48.010919 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9281 22:14:48.016057 in-header: 03 fd 00 00 00 00 00 00
9282 22:14:48.018925 in-data:
9283 22:14:48.022381 [SSUSB] Setting up USB HOST controller...
9284 22:14:48.026026 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9285 22:14:48.028969 [SSUSB] phy power-on done.
9286 22:14:48.032036 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9287 22:14:48.039166 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9288 22:14:48.042012 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9289 22:14:48.048859 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9290 22:14:48.055219 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9291 22:14:48.061957 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9292 22:14:48.068753 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9293 22:14:48.075620 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9294 22:14:48.078698 SPM: binary array size = 0x9dc
9295 22:14:48.082168 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9296 22:14:48.089033 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9297 22:14:48.095293 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9298 22:14:48.101970 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9299 22:14:48.105579 configure_display: Starting display init
9300 22:14:48.139323 anx7625_power_on_init: Init interface.
9301 22:14:48.142422 anx7625_disable_pd_protocol: Disabled PD feature.
9302 22:14:48.145563 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9303 22:14:48.173656 anx7625_start_dp_work: Secure OCM version=00
9304 22:14:48.176905 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9305 22:14:48.191630 sp_tx_get_edid_block: EDID Block = 1
9306 22:14:48.293975 Extracted contents:
9307 22:14:48.297558 header: 00 ff ff ff ff ff ff 00
9308 22:14:48.300973 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9309 22:14:48.304116 version: 01 04
9310 22:14:48.307421 basic params: 95 1f 11 78 0a
9311 22:14:48.311057 chroma info: 76 90 94 55 54 90 27 21 50 54
9312 22:14:48.314109 established: 00 00 00
9313 22:14:48.320660 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9314 22:14:48.324025 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9315 22:14:48.330376 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9316 22:14:48.337110 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9317 22:14:48.344060 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9318 22:14:48.347327 extensions: 00
9319 22:14:48.347419 checksum: fb
9320 22:14:48.347520
9321 22:14:48.350486 Manufacturer: IVO Model 57d Serial Number 0
9322 22:14:48.353761 Made week 0 of 2020
9323 22:14:48.353866 EDID version: 1.4
9324 22:14:48.357218 Digital display
9325 22:14:48.360188 6 bits per primary color channel
9326 22:14:48.360298 DisplayPort interface
9327 22:14:48.363837 Maximum image size: 31 cm x 17 cm
9328 22:14:48.367118 Gamma: 220%
9329 22:14:48.367196 Check DPMS levels
9330 22:14:48.370627 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9331 22:14:48.377030 First detailed timing is preferred timing
9332 22:14:48.377115 Established timings supported:
9333 22:14:48.380098 Standard timings supported:
9334 22:14:48.383681 Detailed timings
9335 22:14:48.386536 Hex of detail: 383680a07038204018303c0035ae10000019
9336 22:14:48.389956 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9337 22:14:48.397003 0780 0798 07c8 0820 hborder 0
9338 22:14:48.400592 0438 043b 0447 0458 vborder 0
9339 22:14:48.403964 -hsync -vsync
9340 22:14:48.404073 Did detailed timing
9341 22:14:48.410450 Hex of detail: 000000000000000000000000000000000000
9342 22:14:48.413941 Manufacturer-specified data, tag 0
9343 22:14:48.416891 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9344 22:14:48.420213 ASCII string: InfoVision
9345 22:14:48.423132 Hex of detail: 000000fe00523134304e574635205248200a
9346 22:14:48.426447 ASCII string: R140NWF5 RH
9347 22:14:48.426530 Checksum
9348 22:14:48.429783 Checksum: 0xfb (valid)
9349 22:14:48.433095 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9350 22:14:48.436637 DSI data_rate: 832800000 bps
9351 22:14:48.443226 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9352 22:14:48.446913 anx7625_parse_edid: pixelclock(138800).
9353 22:14:48.449799 hactive(1920), hsync(48), hfp(24), hbp(88)
9354 22:14:48.453059 vactive(1080), vsync(12), vfp(3), vbp(17)
9355 22:14:48.456469 anx7625_dsi_config: config dsi.
9356 22:14:48.462849 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9357 22:14:48.476332 anx7625_dsi_config: success to config DSI
9358 22:14:48.479826 anx7625_dp_start: MIPI phy setup OK.
9359 22:14:48.482729 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9360 22:14:48.486311 mtk_ddp_mode_set invalid vrefresh 60
9361 22:14:48.489858 main_disp_path_setup
9362 22:14:48.489941 ovl_layer_smi_id_en
9363 22:14:48.492938 ovl_layer_smi_id_en
9364 22:14:48.493021 ccorr_config
9365 22:14:48.493087 aal_config
9366 22:14:48.496430 gamma_config
9367 22:14:48.496511 postmask_config
9368 22:14:48.499851 dither_config
9369 22:14:48.503119 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9370 22:14:48.509751 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9371 22:14:48.513245 Root Device init finished in 552 msecs
9372 22:14:48.513328 CPU_CLUSTER: 0 init
9373 22:14:48.522723 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9374 22:14:48.526124 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9375 22:14:48.529313 APU_MBOX 0x190000b0 = 0x10001
9376 22:14:48.532664 APU_MBOX 0x190001b0 = 0x10001
9377 22:14:48.535949 APU_MBOX 0x190005b0 = 0x10001
9378 22:14:48.539442 APU_MBOX 0x190006b0 = 0x10001
9379 22:14:48.542638 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9380 22:14:48.555264 read SPI 0x539f4 0xe237: 6249 us, 9267 KB/s, 74.136 Mbps
9381 22:14:48.567584 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9382 22:14:48.574169 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9383 22:14:48.586053 read SPI 0x61c74 0xe8ef: 6411 us, 9301 KB/s, 74.408 Mbps
9384 22:14:48.594887 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9385 22:14:48.598415 CPU_CLUSTER: 0 init finished in 81 msecs
9386 22:14:48.601688 Devices initialized
9387 22:14:48.605142 Show all devs... After init.
9388 22:14:48.605222 Root Device: enabled 1
9389 22:14:48.608177 CPU_CLUSTER: 0: enabled 1
9390 22:14:48.611445 CPU: 00: enabled 1
9391 22:14:48.614878 BS: BS_DEV_INIT run times (exec / console): 210 / 447 ms
9392 22:14:48.618323 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9393 22:14:48.621510 ELOG: NV offset 0x57f000 size 0x1000
9394 22:14:48.628267 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9395 22:14:48.635027 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9396 22:14:48.638381 ELOG: Event(17) added with size 13 at 2023-06-05 22:14:53 UTC
9397 22:14:48.644878 out: cmd=0x121: 03 db 21 01 00 00 00 00
9398 22:14:48.647787 in-header: 03 af 00 00 2c 00 00 00
9399 22:14:48.661234 in-data: b0 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9400 22:14:48.664763 ELOG: Event(A1) added with size 10 at 2023-06-05 22:14:53 UTC
9401 22:14:48.671054 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9402 22:14:48.677680 ELOG: Event(A0) added with size 9 at 2023-06-05 22:14:53 UTC
9403 22:14:48.681242 elog_add_boot_reason: Logged dev mode boot
9404 22:14:48.687857 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9405 22:14:48.687942 Finalize devices...
9406 22:14:48.691523 Devices finalized
9407 22:14:48.694515 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9408 22:14:48.697913 Writing coreboot table at 0xffe64000
9409 22:14:48.701436 0. 000000000010a000-0000000000113fff: RAMSTAGE
9410 22:14:48.708053 1. 0000000040000000-00000000400fffff: RAM
9411 22:14:48.711534 2. 0000000040100000-000000004032afff: RAMSTAGE
9412 22:14:48.714949 3. 000000004032b000-00000000545fffff: RAM
9413 22:14:48.717916 4. 0000000054600000-000000005465ffff: BL31
9414 22:14:48.721308 5. 0000000054660000-00000000ffe63fff: RAM
9415 22:14:48.728001 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9416 22:14:48.731422 7. 0000000100000000-000000023fffffff: RAM
9417 22:14:48.734718 Passing 5 GPIOs to payload:
9418 22:14:48.738009 NAME | PORT | POLARITY | VALUE
9419 22:14:48.744652 EC in RW | 0x000000aa | low | undefined
9420 22:14:48.748204 EC interrupt | 0x00000005 | low | undefined
9421 22:14:48.751089 TPM interrupt | 0x000000ab | high | undefined
9422 22:14:48.758040 SD card detect | 0x00000011 | high | undefined
9423 22:14:48.761398 speaker enable | 0x00000093 | high | undefined
9424 22:14:48.764600 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9425 22:14:48.768133 in-header: 03 f9 00 00 02 00 00 00
9426 22:14:48.771178 in-data: 02 00
9427 22:14:48.774246 ADC[4]: Raw value=900221 ID=7
9428 22:14:48.774351 ADC[3]: Raw value=213336 ID=1
9429 22:14:48.777523 RAM Code: 0x71
9430 22:14:48.781120 ADC[6]: Raw value=74926 ID=0
9431 22:14:48.781204 ADC[5]: Raw value=212229 ID=1
9432 22:14:48.784431 SKU Code: 0x1
9433 22:14:48.787568 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum ded1
9434 22:14:48.791166 coreboot table: 964 bytes.
9435 22:14:48.794177 IMD ROOT 0. 0xfffff000 0x00001000
9436 22:14:48.797734 IMD SMALL 1. 0xffffe000 0x00001000
9437 22:14:48.801215 RO MCACHE 2. 0xffffc000 0x00001104
9438 22:14:48.804309 CONSOLE 3. 0xfff7c000 0x00080000
9439 22:14:48.807680 FMAP 4. 0xfff7b000 0x00000452
9440 22:14:48.811057 TIME STAMP 5. 0xfff7a000 0x00000910
9441 22:14:48.814205 VBOOT WORK 6. 0xfff66000 0x00014000
9442 22:14:48.817657 RAMOOPS 7. 0xffe66000 0x00100000
9443 22:14:48.821035 COREBOOT 8. 0xffe64000 0x00002000
9444 22:14:48.824458 IMD small region:
9445 22:14:48.827222 IMD ROOT 0. 0xffffec00 0x00000400
9446 22:14:48.830641 VPD 1. 0xffffeba0 0x0000004c
9447 22:14:48.833958 MMC STATUS 2. 0xffffeb80 0x00000004
9448 22:14:48.837995 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9449 22:14:48.840882 Probing TPM: done!
9450 22:14:48.844414 Connected to device vid:did:rid of 1ae0:0028:00
9451 22:14:48.854691 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
9452 22:14:48.857635 Initialized TPM device CR50 revision 0
9453 22:14:48.861474 Checking cr50 for pending updates
9454 22:14:48.865732 Reading cr50 TPM mode
9455 22:14:48.873782 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9456 22:14:48.880724 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9457 22:14:48.920688 read SPI 0x3990ec 0x4f1b0: 34855 us, 9296 KB/s, 74.368 Mbps
9458 22:14:48.923946 Checking segment from ROM address 0x40100000
9459 22:14:48.927327 Checking segment from ROM address 0x4010001c
9460 22:14:48.934560 Loading segment from ROM address 0x40100000
9461 22:14:48.934642 code (compression=0)
9462 22:14:48.940878 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9463 22:14:48.950970 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9464 22:14:48.951083 it's not compressed!
9465 22:14:48.957179 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9466 22:14:48.960605 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9467 22:14:48.980952 Loading segment from ROM address 0x4010001c
9468 22:14:48.981039 Entry Point 0x80000000
9469 22:14:48.984387 Loaded segments
9470 22:14:48.987434 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9471 22:14:48.994633 Jumping to boot code at 0x80000000(0xffe64000)
9472 22:14:49.000780 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9473 22:14:49.007905 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9474 22:14:49.015502 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9475 22:14:49.018992 Checking segment from ROM address 0x40100000
9476 22:14:49.022181 Checking segment from ROM address 0x4010001c
9477 22:14:49.029077 Loading segment from ROM address 0x40100000
9478 22:14:49.029162 code (compression=1)
9479 22:14:49.035716 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9480 22:14:49.045729 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9481 22:14:49.045814 using LZMA
9482 22:14:49.054052 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9483 22:14:49.061137 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9484 22:14:49.063894 Loading segment from ROM address 0x4010001c
9485 22:14:49.063978 Entry Point 0x54601000
9486 22:14:49.067319 Loaded segments
9487 22:14:49.070780 NOTICE: MT8192 bl31_setup
9488 22:14:49.077915 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9489 22:14:49.080814 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9490 22:14:49.084743 WARNING: region 0:
9491 22:14:49.087978 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9492 22:14:49.088061 WARNING: region 1:
9493 22:14:49.094520 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9494 22:14:49.097752 WARNING: region 2:
9495 22:14:49.101309 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9496 22:14:49.104138 WARNING: region 3:
9497 22:14:49.107638 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9498 22:14:49.111026 WARNING: region 4:
9499 22:14:49.114503 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9500 22:14:49.118036 WARNING: region 5:
9501 22:14:49.121036 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9502 22:14:49.124882 WARNING: region 6:
9503 22:14:49.127863 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9504 22:14:49.127945 WARNING: region 7:
9505 22:14:49.134197 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9506 22:14:49.140857 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9507 22:14:49.144238 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9508 22:14:49.147670 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9509 22:14:49.154492 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9510 22:14:49.157363 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9511 22:14:49.160734 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9512 22:14:49.167629 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9513 22:14:49.170871 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9514 22:14:49.177374 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9515 22:14:49.180999 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9516 22:14:49.183781 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9517 22:14:49.190987 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9518 22:14:49.193998 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9519 22:14:49.197574 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9520 22:14:49.204501 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9521 22:14:49.207264 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9522 22:14:49.210833 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9523 22:14:49.217590 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9524 22:14:49.220932 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9525 22:14:49.227616 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9526 22:14:49.230722 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9527 22:14:49.234077 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9528 22:14:49.240920 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9529 22:14:49.244303 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9530 22:14:49.251146 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9531 22:14:49.254404 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9532 22:14:49.257857 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9533 22:14:49.264056 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9534 22:14:49.267588 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9535 22:14:49.270998 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9536 22:14:49.277945 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9537 22:14:49.280963 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9538 22:14:49.287671 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9539 22:14:49.290843 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9540 22:14:49.294430 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9541 22:14:49.297311 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9542 22:14:49.300866 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9543 22:14:49.307475 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9544 22:14:49.311414 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9545 22:14:49.314296 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9546 22:14:49.317887 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9547 22:14:49.324212 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9548 22:14:49.327394 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9549 22:14:49.330937 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9550 22:14:49.337545 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9551 22:14:49.341104 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9552 22:14:49.344095 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9553 22:14:49.347536 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9554 22:14:49.354118 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9555 22:14:49.357476 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9556 22:14:49.364260 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9557 22:14:49.367563 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9558 22:14:49.371079 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9559 22:14:49.377749 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9560 22:14:49.381247 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9561 22:14:49.387768 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9562 22:14:49.391374 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9563 22:14:49.394194 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9564 22:14:49.401181 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9565 22:14:49.404673 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9566 22:14:49.411049 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9567 22:14:49.414392 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9568 22:14:49.421449 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9569 22:14:49.424342 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9570 22:14:49.431005 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9571 22:14:49.434291 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9572 22:14:49.437925 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9573 22:14:49.444150 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9574 22:14:49.447585 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9575 22:14:49.454342 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9576 22:14:49.457855 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9577 22:14:49.464484 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9578 22:14:49.467492 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9579 22:14:49.471168 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9580 22:14:49.477814 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9581 22:14:49.481003 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9582 22:14:49.488110 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9583 22:14:49.490975 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9584 22:14:49.497428 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9585 22:14:49.501103 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9586 22:14:49.507558 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9587 22:14:49.511116 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9588 22:14:49.514602 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9589 22:14:49.520976 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9590 22:14:49.524453 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9591 22:14:49.531545 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9592 22:14:49.534068 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9593 22:14:49.537543 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9594 22:14:49.544547 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9595 22:14:49.547863 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9596 22:14:49.554520 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9597 22:14:49.557909 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9598 22:14:49.564206 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9599 22:14:49.567937 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9600 22:14:49.571443 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9601 22:14:49.577645 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9602 22:14:49.580953 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9603 22:14:49.584113 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9604 22:14:49.590955 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9605 22:14:49.594408 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9606 22:14:49.597433 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9607 22:14:49.604032 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9608 22:14:49.607775 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9609 22:14:49.610658 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9610 22:14:49.617625 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9611 22:14:49.621194 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9612 22:14:49.627735 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9613 22:14:49.630669 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9614 22:14:49.634275 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9615 22:14:49.640889 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9616 22:14:49.644225 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9617 22:14:49.650719 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9618 22:14:49.654106 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9619 22:14:49.657449 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9620 22:14:49.664510 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9621 22:14:49.667999 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9622 22:14:49.670662 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9623 22:14:49.677292 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9624 22:14:49.680725 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9625 22:14:49.684090 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9626 22:14:49.690813 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9627 22:14:49.694563 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9628 22:14:49.697452 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9629 22:14:49.700908 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9630 22:14:49.707545 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9631 22:14:49.710574 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9632 22:14:49.714078 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9633 22:14:49.720926 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9634 22:14:49.724440 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9635 22:14:49.731033 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9636 22:14:49.733993 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9637 22:14:49.737506 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9638 22:14:49.744135 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9639 22:14:49.747312 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9640 22:14:49.754108 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9641 22:14:49.757538 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9642 22:14:49.761114 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9643 22:14:49.767324 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9644 22:14:49.770674 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9645 22:14:49.774047 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9646 22:14:49.780711 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9647 22:14:49.784098 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9648 22:14:49.790714 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9649 22:14:49.793974 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9650 22:14:49.797541 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9651 22:14:49.804134 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9652 22:14:49.807176 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9653 22:14:49.814013 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9654 22:14:49.817493 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9655 22:14:49.820434 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9656 22:14:49.827271 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9657 22:14:49.830677 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9658 22:14:49.834240 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9659 22:14:49.840895 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9660 22:14:49.843993 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9661 22:14:49.850573 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9662 22:14:49.853969 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9663 22:14:49.857388 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9664 22:14:49.864083 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9665 22:14:49.867025 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9666 22:14:49.873911 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9667 22:14:49.877259 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9668 22:14:49.880616 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9669 22:14:49.887217 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9670 22:14:49.890668 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9671 22:14:49.897276 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9672 22:14:49.900887 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9673 22:14:49.903972 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9674 22:14:49.910457 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9675 22:14:49.914165 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9676 22:14:49.920374 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9677 22:14:49.923734 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9678 22:14:49.927268 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9679 22:14:49.934065 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9680 22:14:49.937158 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9681 22:14:49.940728 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9682 22:14:49.947186 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9683 22:14:49.950657 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9684 22:14:49.957165 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9685 22:14:49.960299 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9686 22:14:49.963768 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9687 22:14:49.970681 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9688 22:14:49.973548 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9689 22:14:49.980364 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9690 22:14:49.983623 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9691 22:14:49.987295 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9692 22:14:49.993967 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9693 22:14:49.997127 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9694 22:14:50.003296 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9695 22:14:50.006751 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9696 22:14:50.009842 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9697 22:14:50.016566 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9698 22:14:50.020016 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9699 22:14:50.026503 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9700 22:14:50.029984 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9701 22:14:50.033333 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9702 22:14:50.040099 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9703 22:14:50.043497 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9704 22:14:50.050032 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9705 22:14:50.053499 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9706 22:14:50.060375 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9707 22:14:50.063801 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9708 22:14:50.066419 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9709 22:14:50.073248 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9710 22:14:50.076828 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9711 22:14:50.083525 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9712 22:14:50.086774 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9713 22:14:50.090187 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9714 22:14:50.096530 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9715 22:14:50.099761 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9716 22:14:50.106502 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9717 22:14:50.109802 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9718 22:14:50.116266 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9719 22:14:50.119985 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9720 22:14:50.123327 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9721 22:14:50.129755 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9722 22:14:50.133262 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9723 22:14:50.139998 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9724 22:14:50.142682 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9725 22:14:50.149771 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9726 22:14:50.152890 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9727 22:14:50.156447 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9728 22:14:50.162890 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9729 22:14:50.166332 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9730 22:14:50.172496 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9731 22:14:50.175945 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9732 22:14:50.179232 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9733 22:14:50.186173 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9734 22:14:50.189584 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9735 22:14:50.192667 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9736 22:14:50.199240 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9737 22:14:50.202658 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9738 22:14:50.205824 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9739 22:14:50.209301 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9740 22:14:50.215708 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9741 22:14:50.219297 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9742 22:14:50.225628 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9743 22:14:50.229231 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9744 22:14:50.232646 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9745 22:14:50.239083 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9746 22:14:50.242480 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9747 22:14:50.246110 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9748 22:14:50.252097 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9749 22:14:50.255818 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9750 22:14:50.258884 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9751 22:14:50.265403 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9752 22:14:50.268959 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9753 22:14:50.275703 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9754 22:14:50.278801 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9755 22:14:50.282301 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9756 22:14:50.288580 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9757 22:14:50.291783 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9758 22:14:50.295716 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9759 22:14:50.302146 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9760 22:14:50.305445 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9761 22:14:50.308699 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9762 22:14:50.315322 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9763 22:14:50.318382 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9764 22:14:50.325165 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9765 22:14:50.328581 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9766 22:14:50.331456 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9767 22:14:50.338566 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9768 22:14:50.341624 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9769 22:14:50.345071 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9770 22:14:50.351752 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9771 22:14:50.355287 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9772 22:14:50.361793 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9773 22:14:50.364919 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9774 22:14:50.368560 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9775 22:14:50.371501 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9776 22:14:50.378133 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9777 22:14:50.381597 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9778 22:14:50.384870 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9779 22:14:50.387905 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9780 22:14:50.394707 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9781 22:14:50.398336 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9782 22:14:50.401592 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9783 22:14:50.404492 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9784 22:14:50.411208 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9785 22:14:50.414397 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9786 22:14:50.418392 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9787 22:14:50.421198 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9788 22:14:50.428088 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9789 22:14:50.431475 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9790 22:14:50.437589 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9791 22:14:50.441439 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9792 22:14:50.447605 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9793 22:14:50.451204 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9794 22:14:50.454656 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9795 22:14:50.461267 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9796 22:14:50.464605 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9797 22:14:50.471244 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9798 22:14:50.474249 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9799 22:14:50.477608 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9800 22:14:50.484277 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9801 22:14:50.487680 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9802 22:14:50.494634 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9803 22:14:50.497458 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9804 22:14:50.500752 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9805 22:14:50.507323 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9806 22:14:50.511269 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9807 22:14:50.517613 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9808 22:14:50.520487 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9809 22:14:50.527407 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9810 22:14:50.530966 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9811 22:14:50.533947 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9812 22:14:50.540995 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9813 22:14:50.543813 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9814 22:14:50.550664 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9815 22:14:50.554041 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9816 22:14:50.556940 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9817 22:14:50.564053 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9818 22:14:50.566952 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9819 22:14:50.573872 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9820 22:14:50.576945 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9821 22:14:50.580495 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9822 22:14:50.587274 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9823 22:14:50.590989 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9824 22:14:50.596899 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9825 22:14:50.600383 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9826 22:14:50.607156 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9827 22:14:50.610113 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9828 22:14:50.613423 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9829 22:14:50.619908 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9830 22:14:50.623383 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9831 22:14:50.630021 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9832 22:14:50.633314 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9833 22:14:50.636726 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9834 22:14:50.643696 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9835 22:14:50.646842 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9836 22:14:50.653392 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9837 22:14:50.656792 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9838 22:14:50.660370 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9839 22:14:50.666878 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9840 22:14:50.669845 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9841 22:14:50.676253 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9842 22:14:50.679780 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9843 22:14:50.683420 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9844 22:14:50.689678 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9845 22:14:50.693033 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9846 22:14:50.700015 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9847 22:14:50.703002 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9848 22:14:50.710104 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9849 22:14:50.713498 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9850 22:14:50.716317 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9851 22:14:50.723144 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9852 22:14:50.726793 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9853 22:14:50.733405 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9854 22:14:50.736514 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9855 22:14:50.739913 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9856 22:14:50.746291 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9857 22:14:50.749875 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9858 22:14:50.756608 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9859 22:14:50.760228 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9860 22:14:50.763666 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9861 22:14:50.769725 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9862 22:14:50.773467 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9863 22:14:50.779920 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9864 22:14:50.783501 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9865 22:14:50.789796 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9866 22:14:50.793460 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9867 22:14:50.796462 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9868 22:14:50.803013 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9869 22:14:50.806376 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9870 22:14:50.813196 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9871 22:14:50.816562 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9872 22:14:50.822771 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9873 22:14:50.826163 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9874 22:14:50.832784 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9875 22:14:50.836433 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9876 22:14:50.839391 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9877 22:14:50.845970 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9878 22:14:50.849445 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9879 22:14:50.855994 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9880 22:14:50.859499 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9881 22:14:50.866096 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9882 22:14:50.869700 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9883 22:14:50.872815 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9884 22:14:50.879303 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9885 22:14:50.882823 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9886 22:14:50.889345 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9887 22:14:50.892748 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9888 22:14:50.899208 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9889 22:14:50.902626 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9890 22:14:50.905860 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9891 22:14:50.912232 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9892 22:14:50.915792 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9893 22:14:50.922238 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9894 22:14:50.925735 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9895 22:14:50.932274 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9896 22:14:50.935748 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9897 22:14:50.938946 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9898 22:14:50.945417 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9899 22:14:50.948952 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9900 22:14:50.955604 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9901 22:14:50.958640 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9902 22:14:50.965403 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9903 22:14:50.968917 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9904 22:14:50.972327 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9905 22:14:50.978974 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9906 22:14:50.981912 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9907 22:14:50.988958 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9908 22:14:50.991910 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9909 22:14:50.995486 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9910 22:14:51.002070 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9911 22:14:51.005535 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9912 22:14:51.012269 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9913 22:14:51.015642 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9914 22:14:51.022015 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9915 22:14:51.025460 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9916 22:14:51.032143 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9917 22:14:51.035544 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9918 22:14:51.041947 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9919 22:14:51.045534 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9920 22:14:51.051819 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9921 22:14:51.055454 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9922 22:14:51.061859 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9923 22:14:51.065441 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9924 22:14:51.071898 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9925 22:14:51.075315 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9926 22:14:51.082331 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9927 22:14:51.085270 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9928 22:14:51.091827 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9929 22:14:51.095328 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9930 22:14:51.102133 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9931 22:14:51.105463 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9932 22:14:51.111998 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9933 22:14:51.115503 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9934 22:14:51.121783 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9935 22:14:51.125027 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9936 22:14:51.131935 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9937 22:14:51.134727 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9938 22:14:51.142229 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9939 22:14:51.144861 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9940 22:14:51.148170 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9941 22:14:51.151803 INFO: [APUAPC] vio 0
9942 22:14:51.158188 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9943 22:14:51.161520 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9944 22:14:51.164572 INFO: [APUAPC] D0_APC_0: 0x400510
9945 22:14:51.168122 INFO: [APUAPC] D0_APC_1: 0x0
9946 22:14:51.171175 INFO: [APUAPC] D0_APC_2: 0x1540
9947 22:14:51.174754 INFO: [APUAPC] D0_APC_3: 0x0
9948 22:14:51.178361 INFO: [APUAPC] D1_APC_0: 0xffffffff
9949 22:14:51.181475 INFO: [APUAPC] D1_APC_1: 0xffffffff
9950 22:14:51.184909 INFO: [APUAPC] D1_APC_2: 0x3fffff
9951 22:14:51.184992 INFO: [APUAPC] D1_APC_3: 0x0
9952 22:14:51.191463 INFO: [APUAPC] D2_APC_0: 0xffffffff
9953 22:14:51.194545 INFO: [APUAPC] D2_APC_1: 0xffffffff
9954 22:14:51.198266 INFO: [APUAPC] D2_APC_2: 0x3fffff
9955 22:14:51.198370 INFO: [APUAPC] D2_APC_3: 0x0
9956 22:14:51.201115 INFO: [APUAPC] D3_APC_0: 0xffffffff
9957 22:14:51.208214 INFO: [APUAPC] D3_APC_1: 0xffffffff
9958 22:14:51.208323 INFO: [APUAPC] D3_APC_2: 0x3fffff
9959 22:14:51.211087 INFO: [APUAPC] D3_APC_3: 0x0
9960 22:14:51.214558 INFO: [APUAPC] D4_APC_0: 0xffffffff
9961 22:14:51.217774 INFO: [APUAPC] D4_APC_1: 0xffffffff
9962 22:14:51.221349 INFO: [APUAPC] D4_APC_2: 0x3fffff
9963 22:14:51.224488 INFO: [APUAPC] D4_APC_3: 0x0
9964 22:14:51.227879 INFO: [APUAPC] D5_APC_0: 0xffffffff
9965 22:14:51.231232 INFO: [APUAPC] D5_APC_1: 0xffffffff
9966 22:14:51.234702 INFO: [APUAPC] D5_APC_2: 0x3fffff
9967 22:14:51.237816 INFO: [APUAPC] D5_APC_3: 0x0
9968 22:14:51.240817 INFO: [APUAPC] D6_APC_0: 0xffffffff
9969 22:14:51.244121 INFO: [APUAPC] D6_APC_1: 0xffffffff
9970 22:14:51.247763 INFO: [APUAPC] D6_APC_2: 0x3fffff
9971 22:14:51.251181 INFO: [APUAPC] D6_APC_3: 0x0
9972 22:14:51.254384 INFO: [APUAPC] D7_APC_0: 0xffffffff
9973 22:14:51.257850 INFO: [APUAPC] D7_APC_1: 0xffffffff
9974 22:14:51.261051 INFO: [APUAPC] D7_APC_2: 0x3fffff
9975 22:14:51.264261 INFO: [APUAPC] D7_APC_3: 0x0
9976 22:14:51.267632 INFO: [APUAPC] D8_APC_0: 0xffffffff
9977 22:14:51.271013 INFO: [APUAPC] D8_APC_1: 0xffffffff
9978 22:14:51.274317 INFO: [APUAPC] D8_APC_2: 0x3fffff
9979 22:14:51.277792 INFO: [APUAPC] D8_APC_3: 0x0
9980 22:14:51.281033 INFO: [APUAPC] D9_APC_0: 0xffffffff
9981 22:14:51.284080 INFO: [APUAPC] D9_APC_1: 0xffffffff
9982 22:14:51.287510 INFO: [APUAPC] D9_APC_2: 0x3fffff
9983 22:14:51.291018 INFO: [APUAPC] D9_APC_3: 0x0
9984 22:14:51.294012 INFO: [APUAPC] D10_APC_0: 0xffffffff
9985 22:14:51.297436 INFO: [APUAPC] D10_APC_1: 0xffffffff
9986 22:14:51.301128 INFO: [APUAPC] D10_APC_2: 0x3fffff
9987 22:14:51.304103 INFO: [APUAPC] D10_APC_3: 0x0
9988 22:14:51.307608 INFO: [APUAPC] D11_APC_0: 0xffffffff
9989 22:14:51.310770 INFO: [APUAPC] D11_APC_1: 0xffffffff
9990 22:14:51.314060 INFO: [APUAPC] D11_APC_2: 0x3fffff
9991 22:14:51.317348 INFO: [APUAPC] D11_APC_3: 0x0
9992 22:14:51.320696 INFO: [APUAPC] D12_APC_0: 0xffffffff
9993 22:14:51.324327 INFO: [APUAPC] D12_APC_1: 0xffffffff
9994 22:14:51.327333 INFO: [APUAPC] D12_APC_2: 0x3fffff
9995 22:14:51.330726 INFO: [APUAPC] D12_APC_3: 0x0
9996 22:14:51.334287 INFO: [APUAPC] D13_APC_0: 0xffffffff
9997 22:14:51.337393 INFO: [APUAPC] D13_APC_1: 0xffffffff
9998 22:14:51.340370 INFO: [APUAPC] D13_APC_2: 0x3fffff
9999 22:14:51.344269 INFO: [APUAPC] D13_APC_3: 0x0
10000 22:14:51.347098 INFO: [APUAPC] D14_APC_0: 0xffffffff
10001 22:14:51.350715 INFO: [APUAPC] D14_APC_1: 0xffffffff
10002 22:14:51.353875 INFO: [APUAPC] D14_APC_2: 0x3fffff
10003 22:14:51.357435 INFO: [APUAPC] D14_APC_3: 0x0
10004 22:14:51.360461 INFO: [APUAPC] D15_APC_0: 0xffffffff
10005 22:14:51.363827 INFO: [APUAPC] D15_APC_1: 0xffffffff
10006 22:14:51.367120 INFO: [APUAPC] D15_APC_2: 0x3fffff
10007 22:14:51.370636 INFO: [APUAPC] D15_APC_3: 0x0
10008 22:14:51.373642 INFO: [APUAPC] APC_CON: 0x4
10009 22:14:51.377290 INFO: [NOCDAPC] D0_APC_0: 0x0
10010 22:14:51.380688 INFO: [NOCDAPC] D0_APC_1: 0x0
10011 22:14:51.380794 INFO: [NOCDAPC] D1_APC_0: 0x0
10012 22:14:51.384149 INFO: [NOCDAPC] D1_APC_1: 0xfff
10013 22:14:51.387320 INFO: [NOCDAPC] D2_APC_0: 0x0
10014 22:14:51.390752 INFO: [NOCDAPC] D2_APC_1: 0xfff
10015 22:14:51.393676 INFO: [NOCDAPC] D3_APC_0: 0x0
10016 22:14:51.397282 INFO: [NOCDAPC] D3_APC_1: 0xfff
10017 22:14:51.400838 INFO: [NOCDAPC] D4_APC_0: 0x0
10018 22:14:51.403798 INFO: [NOCDAPC] D4_APC_1: 0xfff
10019 22:14:51.407062 INFO: [NOCDAPC] D5_APC_0: 0x0
10020 22:14:51.410564 INFO: [NOCDAPC] D5_APC_1: 0xfff
10021 22:14:51.413580 INFO: [NOCDAPC] D6_APC_0: 0x0
10022 22:14:51.413685 INFO: [NOCDAPC] D6_APC_1: 0xfff
10023 22:14:51.416838 INFO: [NOCDAPC] D7_APC_0: 0x0
10024 22:14:51.420814 INFO: [NOCDAPC] D7_APC_1: 0xfff
10025 22:14:51.423682 INFO: [NOCDAPC] D8_APC_0: 0x0
10026 22:14:51.427525 INFO: [NOCDAPC] D8_APC_1: 0xfff
10027 22:14:51.430356 INFO: [NOCDAPC] D9_APC_0: 0x0
10028 22:14:51.433747 INFO: [NOCDAPC] D9_APC_1: 0xfff
10029 22:14:51.437308 INFO: [NOCDAPC] D10_APC_0: 0x0
10030 22:14:51.440488 INFO: [NOCDAPC] D10_APC_1: 0xfff
10031 22:14:51.443955 INFO: [NOCDAPC] D11_APC_0: 0x0
10032 22:14:51.446713 INFO: [NOCDAPC] D11_APC_1: 0xfff
10033 22:14:51.450339 INFO: [NOCDAPC] D12_APC_0: 0x0
10034 22:14:51.453549 INFO: [NOCDAPC] D12_APC_1: 0xfff
10035 22:14:51.453653 INFO: [NOCDAPC] D13_APC_0: 0x0
10036 22:14:51.456562 INFO: [NOCDAPC] D13_APC_1: 0xfff
10037 22:14:51.460427 INFO: [NOCDAPC] D14_APC_0: 0x0
10038 22:14:51.463223 INFO: [NOCDAPC] D14_APC_1: 0xfff
10039 22:14:51.466972 INFO: [NOCDAPC] D15_APC_0: 0x0
10040 22:14:51.469876 INFO: [NOCDAPC] D15_APC_1: 0xfff
10041 22:14:51.473250 INFO: [NOCDAPC] APC_CON: 0x4
10042 22:14:51.476870 INFO: [APUAPC] set_apusys_apc done
10043 22:14:51.479825 INFO: [DEVAPC] devapc_init done
10044 22:14:51.483481 INFO: GICv3 without legacy support detected.
10045 22:14:51.487010 INFO: ARM GICv3 driver initialized in EL3
10046 22:14:51.493396 INFO: Maximum SPI INTID supported: 639
10047 22:14:51.496600 INFO: BL31: Initializing runtime services
10048 22:14:51.499887 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10049 22:14:51.503528 INFO: SPM: enable CPC mode
10050 22:14:51.510211 INFO: mcdi ready for mcusys-off-idle and system suspend
10051 22:14:51.513159 INFO: BL31: Preparing for EL3 exit to normal world
10052 22:14:51.516681 INFO: Entry point address = 0x80000000
10053 22:14:51.520184 INFO: SPSR = 0x8
10054 22:14:51.525778
10055 22:14:51.525893
10056 22:14:51.526005
10057 22:14:51.528592 Starting depthcharge on Spherion...
10058 22:14:51.528705
10059 22:14:51.528800 Wipe memory regions:
10060 22:14:51.528902
10061 22:14:51.529709 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10062 22:14:51.529851 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10063 22:14:51.529972 Setting prompt string to ['asurada:']
10064 22:14:51.530091 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10065 22:14:51.532157 [0x00000040000000, 0x00000054600000)
10066 22:14:51.654332
10067 22:14:51.654497 [0x00000054660000, 0x00000080000000)
10068 22:14:51.914764
10069 22:14:51.914941 [0x000000821a7280, 0x000000ffe64000)
10070 22:14:52.658920
10071 22:14:52.659100 [0x00000100000000, 0x00000240000000)
10072 22:14:54.547594
10073 22:14:54.550857 Initializing XHCI USB controller at 0x11200000.
10074 22:14:55.589943
10075 22:14:55.592871 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10076 22:14:55.592961
10077 22:14:55.593028
10078 22:14:55.593090
10079 22:14:55.593368 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10081 22:14:55.693663 asurada: tftpboot 192.168.201.1 10597244/tftp-deploy-2dx16yrn/kernel/image.itb 10597244/tftp-deploy-2dx16yrn/kernel/cmdline
10082 22:14:55.693845 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10083 22:14:55.693999 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10084 22:14:55.698022 tftpboot 192.168.201.1 10597244/tftp-deploy-2dx16yrn/kernel/image.itp-deploy-2dx16yrn/kernel/cmdline
10085 22:14:55.698131
10086 22:14:55.698227 Waiting for link
10087 22:14:55.858377
10088 22:14:55.858527 R8152: Initializing
10089 22:14:55.858612
10090 22:14:55.861799 Version 6 (ocp_data = 5c30)
10091 22:14:55.861904
10092 22:14:55.864567 R8152: Done initializing
10093 22:14:55.864665
10094 22:14:55.864758 Adding net device
10095 22:14:57.799462
10096 22:14:57.799596 done.
10097 22:14:57.799664
10098 22:14:57.799727 MAC: 00:24:32:30:78:52
10099 22:14:57.799792
10100 22:14:57.802976 Sending DHCP discover... done.
10101 22:14:57.803068
10102 22:14:57.805909 Waiting for reply... done.
10103 22:14:57.805995
10104 22:14:57.809923 Sending DHCP request... done.
10105 22:14:57.810052
10106 22:14:57.810118 Waiting for reply... done.
10107 22:14:57.810180
10108 22:14:57.812862 My ip is 192.168.201.14
10109 22:14:57.812945
10110 22:14:57.815847 The DHCP server ip is 192.168.201.1
10111 22:14:57.815931
10112 22:14:57.819458 TFTP server IP predefined by user: 192.168.201.1
10113 22:14:57.819543
10114 22:14:57.825921 Bootfile predefined by user: 10597244/tftp-deploy-2dx16yrn/kernel/image.itb
10115 22:14:57.826004
10116 22:14:57.829551 Sending tftp read request... done.
10117 22:14:57.829634
10118 22:14:57.832756 Waiting for the transfer...
10119 22:14:57.832841
10120 22:14:58.379501 00000000 ################################################################
10121 22:14:58.379636
10122 22:14:58.917961 00080000 ################################################################
10123 22:14:58.918094
10124 22:14:59.475761 00100000 ################################################################
10125 22:14:59.475904
10126 22:15:00.036658 00180000 ################################################################
10127 22:15:00.036806
10128 22:15:00.597763 00200000 ################################################################
10129 22:15:00.597909
10130 22:15:01.170466 00280000 ################################################################
10131 22:15:01.170619
10132 22:15:01.718917 00300000 ################################################################
10133 22:15:01.719056
10134 22:15:02.260727 00380000 ################################################################
10135 22:15:02.260861
10136 22:15:02.810988 00400000 ################################################################
10137 22:15:02.811123
10138 22:15:03.360763 00480000 ################################################################
10139 22:15:03.360930
10140 22:15:03.908633 00500000 ################################################################
10141 22:15:03.908773
10142 22:15:04.454143 00580000 ################################################################
10143 22:15:04.454292
10144 22:15:05.008619 00600000 ################################################################
10145 22:15:05.008767
10146 22:15:05.558839 00680000 ################################################################
10147 22:15:05.558979
10148 22:15:06.103596 00700000 ################################################################
10149 22:15:06.103748
10150 22:15:06.649987 00780000 ################################################################
10151 22:15:06.650150
10152 22:15:07.197195 00800000 ################################################################
10153 22:15:07.197335
10154 22:15:07.745552 00880000 ################################################################
10155 22:15:07.745690
10156 22:15:08.294129 00900000 ################################################################
10157 22:15:08.294269
10158 22:15:08.850561 00980000 ################################################################
10159 22:15:08.850697
10160 22:15:09.400743 00a00000 ################################################################
10161 22:15:09.400880
10162 22:15:09.951455 00a80000 ################################################################
10163 22:15:09.951591
10164 22:15:10.501803 00b00000 ################################################################
10165 22:15:10.501942
10166 22:15:11.053191 00b80000 ################################################################
10167 22:15:11.053322
10168 22:15:11.612515 00c00000 ################################################################
10169 22:15:11.612656
10170 22:15:12.161776 00c80000 ################################################################
10171 22:15:12.161914
10172 22:15:12.723625 00d00000 ################################################################
10173 22:15:12.723762
10174 22:15:13.272754 00d80000 ################################################################
10175 22:15:13.272894
10176 22:15:13.834008 00e00000 ################################################################
10177 22:15:13.834148
10178 22:15:14.382281 00e80000 ################################################################
10179 22:15:14.382427
10180 22:15:14.927657 00f00000 ################################################################
10181 22:15:14.927798
10182 22:15:15.480057 00f80000 ################################################################
10183 22:15:15.480195
10184 22:15:16.030135 01000000 ################################################################
10185 22:15:16.030274
10186 22:15:16.579888 01080000 ################################################################
10187 22:15:16.580068
10188 22:15:17.127895 01100000 ################################################################
10189 22:15:17.128031
10190 22:15:17.675048 01180000 ################################################################
10191 22:15:17.675181
10192 22:15:18.216164 01200000 ################################################################
10193 22:15:18.216303
10194 22:15:18.770060 01280000 ################################################################
10195 22:15:18.770207
10196 22:15:19.331139 01300000 ################################################################
10197 22:15:19.331290
10198 22:15:19.881040 01380000 ################################################################
10199 22:15:19.881187
10200 22:15:20.426166 01400000 ################################################################
10201 22:15:20.426313
10202 22:15:20.965973 01480000 ################################################################
10203 22:15:20.966121
10204 22:15:21.516680 01500000 ################################################################
10205 22:15:21.516822
10206 22:15:22.061164 01580000 ################################################################
10207 22:15:22.061304
10208 22:15:22.603756 01600000 ################################################################
10209 22:15:22.603894
10210 22:15:23.142439 01680000 ################################################################
10211 22:15:23.142580
10212 22:15:23.691812 01700000 ################################################################
10213 22:15:23.691983
10214 22:15:24.233855 01780000 ################################################################
10215 22:15:24.233998
10216 22:15:24.761082 01800000 ################################################################
10217 22:15:24.761222
10218 22:15:25.273493 01880000 ################################################################
10219 22:15:25.273646
10220 22:15:25.786646 01900000 ################################################################
10221 22:15:25.786804
10222 22:15:26.303823 01980000 ################################################################
10223 22:15:26.303968
10224 22:15:26.839194 01a00000 ################################################################
10225 22:15:26.839383
10226 22:15:27.372856 01a80000 ################################################################
10227 22:15:27.373031
10228 22:15:27.909647 01b00000 ################################################################
10229 22:15:27.909793
10230 22:15:28.453512 01b80000 ################################################################
10231 22:15:28.453690
10232 22:15:29.030805 01c00000 ################################################################
10233 22:15:29.031515
10234 22:15:29.624136 01c80000 ################################################################
10235 22:15:29.624301
10236 22:15:30.219973 01d00000 ################################################################
10237 22:15:30.220279
10238 22:15:30.818076 01d80000 ################################################################
10239 22:15:30.818572
10240 22:15:31.376835 01e00000 ################################################################
10241 22:15:31.377020
10242 22:15:31.951037 01e80000 ################################################################
10243 22:15:31.951174
10244 22:15:32.491857 01f00000 ################################################################
10245 22:15:32.492003
10246 22:15:33.083385 01f80000 ################################################################
10247 22:15:33.083565
10248 22:15:33.656062 02000000 ################################################################
10249 22:15:33.656210
10250 22:15:34.228290 02080000 ################################################################
10251 22:15:34.228431
10252 22:15:34.768682 02100000 ################################################################
10253 22:15:34.768838
10254 22:15:35.315389 02180000 ################################################################
10255 22:15:35.315557
10256 22:15:35.884205 02200000 ################################################################
10257 22:15:35.884345
10258 22:15:36.454352 02280000 ################################################################
10259 22:15:36.454493
10260 22:15:37.041093 02300000 ################################################################
10261 22:15:37.041246
10262 22:15:37.617987 02380000 ################################################################
10263 22:15:37.618143
10264 22:15:38.199900 02400000 ################################################################
10265 22:15:38.200036
10266 22:15:38.785198 02480000 ################################################################
10267 22:15:38.785351
10268 22:15:39.381890 02500000 ################################################################
10269 22:15:39.382030
10270 22:15:39.985863 02580000 ################################################################
10271 22:15:39.986017
10272 22:15:40.587096 02600000 ################################################################
10273 22:15:40.587246
10274 22:15:41.184582 02680000 ################################################################
10275 22:15:41.184732
10276 22:15:41.772336 02700000 ################################################################
10277 22:15:41.772491
10278 22:15:42.373941 02780000 ################################################################
10279 22:15:42.374128
10280 22:15:42.989365 02800000 ################################################################
10281 22:15:42.989823
10282 22:15:43.679891 02880000 ################################################################
10283 22:15:43.680152
10284 22:15:44.302389 02900000 ################################################################
10285 22:15:44.302557
10286 22:15:44.922400 02980000 ################################################################
10287 22:15:44.922599
10288 22:15:45.482667 02a00000 ################################################################
10289 22:15:45.482814
10290 22:15:46.043415 02a80000 ################################################################
10291 22:15:46.043572
10292 22:15:46.641725 02b00000 ################################################################
10293 22:15:46.641919
10294 22:15:47.225116 02b80000 ################################################################
10295 22:15:47.225270
10296 22:15:47.791340 02c00000 ################################################################
10297 22:15:47.791494
10298 22:15:48.385869 02c80000 ################################################################
10299 22:15:48.386021
10300 22:15:48.983069 02d00000 ################################################################
10301 22:15:48.983209
10302 22:15:49.559619 02d80000 ################################################################
10303 22:15:49.559782
10304 22:15:50.156982 02e00000 ################################################################
10305 22:15:50.157147
10306 22:15:50.747118 02e80000 ################################################################
10307 22:15:50.747259
10308 22:15:51.321669 02f00000 ################################################################
10309 22:15:51.321805
10310 22:15:51.883070 02f80000 ################################################################
10311 22:15:51.883228
10312 22:15:52.433938 03000000 ################################################################
10313 22:15:52.434076
10314 22:15:53.007068 03080000 ################################################################
10315 22:15:53.007224
10316 22:15:53.582420 03100000 ################################################################
10317 22:15:53.582562
10318 22:15:54.142373 03180000 ################################################################
10319 22:15:54.142529
10320 22:15:54.720861 03200000 ################################################################
10321 22:15:54.721003
10322 22:15:55.301345 03280000 ################################################################
10323 22:15:55.301499
10324 22:15:55.883734 03300000 ################################################################
10325 22:15:55.883887
10326 22:15:56.458175 03380000 ################################################################
10327 22:15:56.458359
10328 22:15:57.046795 03400000 ################################################################
10329 22:15:57.046952
10330 22:15:57.649282 03480000 ################################################################
10331 22:15:57.649439
10332 22:15:58.247951 03500000 ################################################################
10333 22:15:58.248120
10334 22:15:58.840994 03580000 ################################################################
10335 22:15:58.841156
10336 22:15:59.431931 03600000 ################################################################
10337 22:15:59.432097
10338 22:16:00.033601 03680000 ################################################################
10339 22:16:00.033766
10340 22:16:00.635685 03700000 ################################################################
10341 22:16:00.635875
10342 22:16:01.232151 03780000 ################################################################
10343 22:16:01.232319
10344 22:16:01.816430 03800000 ################################################################
10345 22:16:01.816605
10346 22:16:02.416110 03880000 ################################################################
10347 22:16:02.416278
10348 22:16:03.010211 03900000 ################################################################
10349 22:16:03.010377
10350 22:16:03.603608 03980000 ################################################################
10351 22:16:03.603772
10352 22:16:04.193593 03a00000 ################################################################
10353 22:16:04.193806
10354 22:16:04.791015 03a80000 ################################################################
10355 22:16:04.791181
10356 22:16:05.388700 03b00000 ################################################################
10357 22:16:05.388862
10358 22:16:05.982562 03b80000 ################################################################
10359 22:16:05.982727
10360 22:16:06.576877 03c00000 ################################################################
10361 22:16:06.577039
10362 22:16:07.163277 03c80000 ################################################################
10363 22:16:07.163512
10364 22:16:07.746410 03d00000 ################################################################
10365 22:16:07.746567
10366 22:16:08.341721 03d80000 ################################################################
10367 22:16:08.341875
10368 22:16:08.941602 03e00000 ################################################################
10369 22:16:08.941789
10370 22:16:09.540431 03e80000 ################################################################
10371 22:16:09.540597
10372 22:16:10.052938 03f00000 ####################################################### done.
10373 22:16:10.053095
10374 22:16:10.056616 The bootfile was 66505950 bytes long.
10375 22:16:10.056716
10376 22:16:10.059644 Sending tftp read request... done.
10377 22:16:10.059735
10378 22:16:10.059823 Waiting for the transfer...
10379 22:16:10.059907
10380 22:16:10.062698 00000000 # done.
10381 22:16:10.062789
10382 22:16:10.069537 Command line loaded dynamically from TFTP file: 10597244/tftp-deploy-2dx16yrn/kernel/cmdline
10383 22:16:10.069630
10384 22:16:10.082732 The command line is: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10385 22:16:10.082863
10386 22:16:10.082960 Loading FIT.
10387 22:16:10.083063
10388 22:16:10.086480 Image ramdisk-1 has 56374687 bytes.
10389 22:16:10.086568
10390 22:16:10.089264 Image fdt-1 has 46924 bytes.
10391 22:16:10.089352
10392 22:16:10.092780 Image kernel-1 has 10082307 bytes.
10393 22:16:10.092866
10394 22:16:10.099396 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10395 22:16:10.099483
10396 22:16:10.119009 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10397 22:16:10.119129
10398 22:16:10.122633 Choosing best match conf-1 for compat google,spherion-rev2.
10399 22:16:10.127623
10400 22:16:10.131830 Connected to device vid:did:rid of 1ae0:0028:00
10401 22:16:10.139055
10402 22:16:10.142508 tpm_get_response: command 0x17b, return code 0x0
10403 22:16:10.142614
10404 22:16:10.149279 ec_init: CrosEC protocol v3 supported (256, 248)
10405 22:16:10.149408
10406 22:16:10.152400 tpm_cleanup: add release locality here.
10407 22:16:10.152486
10408 22:16:10.155903 Shutting down all USB controllers.
10409 22:16:10.155989
10410 22:16:10.159510 Removing current net device
10411 22:16:10.159595
10412 22:16:10.165583 Exiting depthcharge with code 4 at timestamp: 108075670
10413 22:16:10.165670
10414 22:16:10.169070 LZMA decompressing kernel-1 to 0x821a6718
10415 22:16:10.169155
10416 22:16:10.172531 LZMA decompressing kernel-1 to 0x40000000
10417 22:16:11.438773
10418 22:16:11.438934 jumping to kernel
10419 22:16:11.439405 end: 2.2.4 bootloader-commands (duration 00:01:20) [common]
10420 22:16:11.439538 start: 2.2.5 auto-login-action (timeout 00:03:05) [common]
10421 22:16:11.439615 Setting prompt string to ['Linux version [0-9]']
10422 22:16:11.439685 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10423 22:16:11.439754 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10424 22:16:11.520603
10425 22:16:11.523683 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10426 22:16:11.527324 start: 2.2.5.1 login-action (timeout 00:03:05) [common]
10427 22:16:11.527472 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10428 22:16:11.527637 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10429 22:16:11.527721 Using line separator: #'\n'#
10430 22:16:11.527797 No login prompt set.
10431 22:16:11.527888 Parsing kernel messages
10432 22:16:11.527962 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10433 22:16:11.528126 [login-action] Waiting for messages, (timeout 00:03:05)
10434 22:16:11.547477 [ 0.000000] Linux version 6.1.31 (KernelCI@build-j1612341-arm64-gcc-10-defconfig-arm64-chromebook-n674v) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Mon Jun 5 22:04:07 UTC 2023
10435 22:16:11.550348 [ 0.000000] random: crng init done
10436 22:16:11.553954 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10437 22:16:11.557154 [ 0.000000] efi: UEFI not found.
10438 22:16:11.567270 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10439 22:16:11.574279 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10440 22:16:11.584205 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10441 22:16:11.593760 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10442 22:16:11.600038 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10443 22:16:11.603247 [ 0.000000] printk: bootconsole [mtk8250] enabled
10444 22:16:11.612088 [ 0.000000] NUMA: No NUMA configuration found
10445 22:16:11.618701 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10446 22:16:11.626154 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcda00-0x23efcffff]
10447 22:16:11.626349 [ 0.000000] Zone ranges:
10448 22:16:11.632149 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10449 22:16:11.635720 [ 0.000000] DMA32 empty
10450 22:16:11.642167 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10451 22:16:11.645077 [ 0.000000] Movable zone start for each node
10452 22:16:11.649060 [ 0.000000] Early memory node ranges
10453 22:16:11.655404 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10454 22:16:11.661943 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10455 22:16:11.669150 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10456 22:16:11.674997 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10457 22:16:11.682057 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10458 22:16:11.687882 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10459 22:16:11.744507 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10460 22:16:11.751752 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10461 22:16:11.757855 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10462 22:16:11.760907 [ 0.000000] psci: probing for conduit method from DT.
10463 22:16:11.767664 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10464 22:16:11.770835 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10465 22:16:11.777571 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10466 22:16:11.781042 [ 0.000000] psci: SMC Calling Convention v1.2
10467 22:16:11.787426 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10468 22:16:11.791327 [ 0.000000] Detected VIPT I-cache on CPU0
10469 22:16:11.797655 [ 0.000000] CPU features: detected: GIC system register CPU interface
10470 22:16:11.803884 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10471 22:16:11.810583 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10472 22:16:11.817857 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10473 22:16:11.827675 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10474 22:16:11.833965 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10475 22:16:11.837183 [ 0.000000] alternatives: applying boot alternatives
10476 22:16:11.843553 [ 0.000000] Fallback order for Node 0: 0
10477 22:16:11.850148 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10478 22:16:11.853786 [ 0.000000] Policy zone: Normal
10479 22:16:11.863898 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10480 22:16:11.876419 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10481 22:16:11.886842 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10482 22:16:11.896873 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10483 22:16:11.903609 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10484 22:16:11.906778 <6>[ 0.000000] software IO TLB: area num 8.
10485 22:16:11.962940 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10486 22:16:12.112410 <6>[ 0.000000] Memory: 7917888K/8385536K available (17984K kernel code, 4098K rwdata, 14068K rodata, 8384K init, 615K bss, 434880K reserved, 32768K cma-reserved)
10487 22:16:12.118624 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10488 22:16:12.125672 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10489 22:16:12.128451 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10490 22:16:12.135799 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10491 22:16:12.142009 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10492 22:16:12.145312 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10493 22:16:12.155267 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10494 22:16:12.161619 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10495 22:16:12.168228 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10496 22:16:12.175057 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10497 22:16:12.178047 <6>[ 0.000000] GICv3: 608 SPIs implemented
10498 22:16:12.181529 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10499 22:16:12.187962 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10500 22:16:12.191301 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10501 22:16:12.197829 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10502 22:16:12.211323 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10503 22:16:12.224809 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10504 22:16:12.231458 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10505 22:16:12.238870 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10506 22:16:12.251845 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10507 22:16:12.258669 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10508 22:16:12.264981 <6>[ 0.009179] Console: colour dummy device 80x25
10509 22:16:12.274921 <6>[ 0.013908] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10510 22:16:12.282205 <6>[ 0.024350] pid_max: default: 32768 minimum: 301
10511 22:16:12.285263 <6>[ 0.029224] LSM: Security Framework initializing
10512 22:16:12.291723 <6>[ 0.034192] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10513 22:16:12.301593 <6>[ 0.042055] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10514 22:16:12.308076 <6>[ 0.051484] cblist_init_generic: Setting adjustable number of callback queues.
10515 22:16:12.314793 <6>[ 0.058939] cblist_init_generic: Setting shift to 3 and lim to 1.
10516 22:16:12.321531 <6>[ 0.065318] cblist_init_generic: Setting shift to 3 and lim to 1.
10517 22:16:12.328489 <6>[ 0.071728] rcu: Hierarchical SRCU implementation.
10518 22:16:12.331608 <6>[ 0.076742] rcu: Max phase no-delay instances is 1000.
10519 22:16:12.339726 <6>[ 0.083766] EFI services will not be available.
10520 22:16:12.343302 <6>[ 0.088733] smp: Bringing up secondary CPUs ...
10521 22:16:12.352369 <6>[ 0.093820] Detected VIPT I-cache on CPU1
10522 22:16:12.358622 <6>[ 0.093892] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10523 22:16:12.365158 <6>[ 0.093925] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10524 22:16:12.368677 <6>[ 0.094260] Detected VIPT I-cache on CPU2
10525 22:16:12.378536 <6>[ 0.094307] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10526 22:16:12.385144 <6>[ 0.094322] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10527 22:16:12.388435 <6>[ 0.094583] Detected VIPT I-cache on CPU3
10528 22:16:12.395246 <6>[ 0.094631] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10529 22:16:12.401811 <6>[ 0.094644] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10530 22:16:12.405671 <6>[ 0.094952] CPU features: detected: Spectre-v4
10531 22:16:12.411656 <6>[ 0.094958] CPU features: detected: Spectre-BHB
10532 22:16:12.414822 <6>[ 0.094964] Detected PIPT I-cache on CPU4
10533 22:16:12.422147 <6>[ 0.095022] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10534 22:16:12.428172 <6>[ 0.095039] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10535 22:16:12.434774 <6>[ 0.095334] Detected PIPT I-cache on CPU5
10536 22:16:12.441407 <6>[ 0.095398] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10537 22:16:12.447849 <6>[ 0.095414] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10538 22:16:12.451182 <6>[ 0.095695] Detected PIPT I-cache on CPU6
10539 22:16:12.457737 <6>[ 0.095760] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10540 22:16:12.464534 <6>[ 0.095776] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10541 22:16:12.470901 <6>[ 0.096071] Detected PIPT I-cache on CPU7
10542 22:16:12.478097 <6>[ 0.096136] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10543 22:16:12.484137 <6>[ 0.096153] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10544 22:16:12.487636 <6>[ 0.096199] smp: Brought up 1 node, 8 CPUs
10545 22:16:12.494650 <6>[ 0.237571] SMP: Total of 8 processors activated.
10546 22:16:12.497512 <6>[ 0.242492] CPU features: detected: 32-bit EL0 Support
10547 22:16:12.507218 <6>[ 0.247855] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10548 22:16:12.514609 <6>[ 0.256655] CPU features: detected: Common not Private translations
10549 22:16:12.520790 <6>[ 0.263131] CPU features: detected: CRC32 instructions
10550 22:16:12.524197 <6>[ 0.268482] CPU features: detected: RCpc load-acquire (LDAPR)
10551 22:16:12.530902 <6>[ 0.274442] CPU features: detected: LSE atomic instructions
10552 22:16:12.537821 <6>[ 0.280223] CPU features: detected: Privileged Access Never
10553 22:16:12.544137 <6>[ 0.286002] CPU features: detected: RAS Extension Support
10554 22:16:12.551149 <6>[ 0.291611] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10555 22:16:12.554138 <6>[ 0.298876] CPU: All CPU(s) started at EL2
10556 22:16:12.560832 <6>[ 0.303192] alternatives: applying system-wide alternatives
10557 22:16:12.570037 <6>[ 0.313899] devtmpfs: initialized
10558 22:16:12.582247 <6>[ 0.322743] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10559 22:16:12.592287 <6>[ 0.332706] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10560 22:16:12.599314 <6>[ 0.340722] pinctrl core: initialized pinctrl subsystem
10561 22:16:12.602022 <6>[ 0.347363] DMI not present or invalid.
10562 22:16:12.608666 <6>[ 0.351763] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10563 22:16:12.619087 <6>[ 0.358616] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10564 22:16:12.625146 <6>[ 0.366193] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10565 22:16:12.635672 <6>[ 0.374404] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10566 22:16:12.639035 <6>[ 0.382644] audit: initializing netlink subsys (disabled)
10567 22:16:12.648478 <5>[ 0.388334] audit: type=2000 audit(0.276:1): state=initialized audit_enabled=0 res=1
10568 22:16:12.655209 <6>[ 0.389001] thermal_sys: Registered thermal governor 'step_wise'
10569 22:16:12.661893 <6>[ 0.396299] thermal_sys: Registered thermal governor 'power_allocator'
10570 22:16:12.665318 <6>[ 0.402554] cpuidle: using governor menu
10571 22:16:12.672177 <6>[ 0.413514] NET: Registered PF_QIPCRTR protocol family
10572 22:16:12.679034 <6>[ 0.418992] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10573 22:16:12.681463 <6>[ 0.426092] ASID allocator initialised with 32768 entries
10574 22:16:12.688930 <6>[ 0.432657] Serial: AMBA PL011 UART driver
10575 22:16:12.698175 <4>[ 0.441256] Trying to register duplicate clock ID: 134
10576 22:16:12.751690 <6>[ 0.498378] KASLR enabled
10577 22:16:12.766202 <6>[ 0.506072] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10578 22:16:12.772722 <6>[ 0.513086] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10579 22:16:12.778820 <6>[ 0.519575] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10580 22:16:12.785343 <6>[ 0.526580] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10581 22:16:12.792336 <6>[ 0.533065] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10582 22:16:12.798708 <6>[ 0.540066] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10583 22:16:12.805299 <6>[ 0.546552] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10584 22:16:12.811757 <6>[ 0.553556] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10585 22:16:12.814954 <6>[ 0.561078] ACPI: Interpreter disabled.
10586 22:16:12.823925 <6>[ 0.567477] iommu: Default domain type: Translated
10587 22:16:12.830114 <6>[ 0.572588] iommu: DMA domain TLB invalidation policy: strict mode
10588 22:16:12.833837 <5>[ 0.579245] SCSI subsystem initialized
10589 22:16:12.840154 <6>[ 0.583413] usbcore: registered new interface driver usbfs
10590 22:16:12.846576 <6>[ 0.589149] usbcore: registered new interface driver hub
10591 22:16:12.850087 <6>[ 0.594701] usbcore: registered new device driver usb
10592 22:16:12.856779 <6>[ 0.600792] pps_core: LinuxPPS API ver. 1 registered
10593 22:16:12.867064 <6>[ 0.605984] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10594 22:16:12.870767 <6>[ 0.615332] PTP clock support registered
10595 22:16:12.873550 <6>[ 0.619574] EDAC MC: Ver: 3.0.0
10596 22:16:12.880861 <6>[ 0.624695] FPGA manager framework
10597 22:16:12.887828 <6>[ 0.628377] Advanced Linux Sound Architecture Driver Initialized.
10598 22:16:12.890796 <6>[ 0.635150] vgaarb: loaded
10599 22:16:12.897441 <6>[ 0.638315] clocksource: Switched to clocksource arch_sys_counter
10600 22:16:12.901261 <5>[ 0.644755] VFS: Disk quotas dquot_6.6.0
10601 22:16:12.907873 <6>[ 0.648939] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10602 22:16:12.910453 <6>[ 0.656125] pnp: PnP ACPI: disabled
10603 22:16:12.918918 <6>[ 0.662895] NET: Registered PF_INET protocol family
10604 22:16:12.929249 <6>[ 0.668488] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10605 22:16:12.940382 <6>[ 0.680775] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10606 22:16:12.950223 <6>[ 0.689591] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10607 22:16:12.956939 <6>[ 0.697560] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10608 22:16:12.963545 <6>[ 0.706257] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10609 22:16:12.975444 <6>[ 0.715991] TCP: Hash tables configured (established 65536 bind 65536)
10610 22:16:12.982184 <6>[ 0.722857] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10611 22:16:12.989383 <6>[ 0.730053] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10612 22:16:12.995546 <6>[ 0.737756] NET: Registered PF_UNIX/PF_LOCAL protocol family
10613 22:16:13.002697 <6>[ 0.743846] RPC: Registered named UNIX socket transport module.
10614 22:16:13.005666 <6>[ 0.749994] RPC: Registered udp transport module.
10615 22:16:13.012222 <6>[ 0.754926] RPC: Registered tcp transport module.
10616 22:16:13.018850 <6>[ 0.759858] RPC: Registered tcp NFSv4.1 backchannel transport module.
10617 22:16:13.022100 <6>[ 0.766525] PCI: CLS 0 bytes, default 64
10618 22:16:13.025233 <6>[ 0.770873] Unpacking initramfs...
10619 22:16:13.043280 <6>[ 0.782962] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10620 22:16:13.052596 <6>[ 0.791633] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10621 22:16:13.055815 <6>[ 0.800476] kvm [1]: IPA Size Limit: 40 bits
10622 22:16:13.062588 <6>[ 0.805002] kvm [1]: GICv3: no GICV resource entry
10623 22:16:13.065689 <6>[ 0.810024] kvm [1]: disabling GICv2 emulation
10624 22:16:13.072648 <6>[ 0.814714] kvm [1]: GIC system register CPU interface enabled
10625 22:16:13.075708 <6>[ 0.820882] kvm [1]: vgic interrupt IRQ18
10626 22:16:13.082302 <6>[ 0.825253] kvm [1]: VHE mode initialized successfully
10627 22:16:13.089142 <5>[ 0.831725] Initialise system trusted keyrings
10628 22:16:13.095963 <6>[ 0.836569] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10629 22:16:13.103171 <6>[ 0.846569] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10630 22:16:13.109434 <5>[ 0.852957] NFS: Registering the id_resolver key type
10631 22:16:13.112817 <5>[ 0.858252] Key type id_resolver registered
10632 22:16:13.119379 <5>[ 0.862668] Key type id_legacy registered
10633 22:16:13.126128 <6>[ 0.866946] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10634 22:16:13.133030 <6>[ 0.873869] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10635 22:16:13.139759 <6>[ 0.881588] 9p: Installing v9fs 9p2000 file system support
10636 22:16:13.174880 <5>[ 0.918558] Key type asymmetric registered
10637 22:16:13.178329 <5>[ 0.922887] Asymmetric key parser 'x509' registered
10638 22:16:13.188308 <6>[ 0.928027] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10639 22:16:13.191402 <6>[ 0.935639] io scheduler mq-deadline registered
10640 22:16:13.194652 <6>[ 0.940401] io scheduler kyber registered
10641 22:16:13.213749 <6>[ 0.957397] EINJ: ACPI disabled.
10642 22:16:13.245715 <4>[ 0.982797] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10643 22:16:13.255860 <4>[ 0.993419] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10644 22:16:13.270146 <6>[ 1.013857] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10645 22:16:13.277837 <6>[ 1.021771] printk: console [ttyS0] disabled
10646 22:16:13.305987 <6>[ 1.046452] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10647 22:16:13.313191 <6>[ 1.055940] printk: console [ttyS0] enabled
10648 22:16:13.315925 <6>[ 1.055940] printk: console [ttyS0] enabled
10649 22:16:13.322444 <6>[ 1.064834] printk: bootconsole [mtk8250] disabled
10650 22:16:13.326105 <6>[ 1.064834] printk: bootconsole [mtk8250] disabled
10651 22:16:13.332259 <6>[ 1.075815] SuperH (H)SCI(F) driver initialized
10652 22:16:13.335879 <6>[ 1.081077] msm_serial: driver initialized
10653 22:16:13.349555 <6>[ 1.089890] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10654 22:16:13.359709 <6>[ 1.098435] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10655 22:16:13.366468 <6>[ 1.106977] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10656 22:16:13.376359 <6>[ 1.115605] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10657 22:16:13.383011 <6>[ 1.124310] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10658 22:16:13.392822 <6>[ 1.133022] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10659 22:16:13.402646 <6>[ 1.141563] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10660 22:16:13.409345 <6>[ 1.150359] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10661 22:16:13.419605 <6>[ 1.158900] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10662 22:16:13.430988 <6>[ 1.174143] loop: module loaded
10663 22:16:13.437573 <6>[ 1.180167] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10664 22:16:13.459940 <4>[ 1.203466] mtk-pmic-keys: Failed to locate of_node [id: -1]
10665 22:16:13.466718 <6>[ 1.210063] megasas: 07.719.03.00-rc1
10666 22:16:13.475759 <6>[ 1.219562] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10667 22:16:13.485771 <6>[ 1.229687] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10668 22:16:13.502748 <6>[ 1.246361] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10669 22:16:13.563189 <6>[ 1.300438] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10670 22:16:15.414266 <6>[ 3.158436] Freeing initrd memory: 55048K
10671 22:16:15.424197 <6>[ 3.168617] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10672 22:16:15.435768 <6>[ 3.179494] tun: Universal TUN/TAP device driver, 1.6
10673 22:16:15.438452 <6>[ 3.185541] thunder_xcv, ver 1.0
10674 22:16:15.442121 <6>[ 3.189044] thunder_bgx, ver 1.0
10675 22:16:15.445691 <6>[ 3.192538] nicpf, ver 1.0
10676 22:16:15.455713 <6>[ 3.196534] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10677 22:16:15.458951 <6>[ 3.204009] hns3: Copyright (c) 2017 Huawei Corporation.
10678 22:16:15.462900 <6>[ 3.209595] hclge is initializing
10679 22:16:15.469421 <6>[ 3.213172] e1000: Intel(R) PRO/1000 Network Driver
10680 22:16:15.475905 <6>[ 3.218301] e1000: Copyright (c) 1999-2006 Intel Corporation.
10681 22:16:15.479272 <6>[ 3.224316] e1000e: Intel(R) PRO/1000 Network Driver
10682 22:16:15.485752 <6>[ 3.229532] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10683 22:16:15.492649 <6>[ 3.235719] igb: Intel(R) Gigabit Ethernet Network Driver
10684 22:16:15.499031 <6>[ 3.241370] igb: Copyright (c) 2007-2014 Intel Corporation.
10685 22:16:15.505518 <6>[ 3.247206] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10686 22:16:15.512091 <6>[ 3.253724] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10687 22:16:15.516020 <6>[ 3.260179] sky2: driver version 1.30
10688 22:16:15.521662 <6>[ 3.265147] VFIO - User Level meta-driver version: 0.3
10689 22:16:15.529169 <6>[ 3.273324] usbcore: registered new interface driver usb-storage
10690 22:16:15.535741 <6>[ 3.279770] usbcore: registered new device driver onboard-usb-hub
10691 22:16:15.544873 <6>[ 3.288806] mt6397-rtc mt6359-rtc: registered as rtc0
10692 22:16:15.554704 <6>[ 3.294300] mt6397-rtc mt6359-rtc: setting system clock to 2023-06-05T22:16:20 UTC (1686003380)
10693 22:16:15.558324 <6>[ 3.303891] i2c_dev: i2c /dev entries driver
10694 22:16:15.575113 <6>[ 3.315610] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10695 22:16:15.582002 <6>[ 3.325769] sdhci: Secure Digital Host Controller Interface driver
10696 22:16:15.588734 <6>[ 3.332206] sdhci: Copyright(c) Pierre Ossman
10697 22:16:15.594746 <6>[ 3.337598] Synopsys Designware Multimedia Card Interface Driver
10698 22:16:15.598540 <6>[ 3.344198] mmc0: CQHCI version 5.10
10699 22:16:15.604960 <6>[ 3.344747] sdhci-pltfm: SDHCI platform and OF driver helper
10700 22:16:15.612339 <6>[ 3.356278] ledtrig-cpu: registered to indicate activity on CPUs
10701 22:16:15.623123 <6>[ 3.363681] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10702 22:16:15.630209 <6>[ 3.371101] usbcore: registered new interface driver usbhid
10703 22:16:15.632904 <6>[ 3.376934] usbhid: USB HID core driver
10704 22:16:15.639552 <6>[ 3.381189] spi_master spi0: will run message pump with realtime priority
10705 22:16:15.684939 <6>[ 3.422358] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10706 22:16:15.704579 <6>[ 3.437928] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10707 22:16:15.707727 <6>[ 3.451497] mmc0: Command Queue Engine enabled
10708 22:16:15.714474 <6>[ 3.453055] cros-ec-spi spi0.0: Chrome EC device registered
10709 22:16:15.721041 <6>[ 3.456243] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10710 22:16:15.724532 <6>[ 3.469493] mmcblk0: mmc0:0001 DA4128 116 GiB
10711 22:16:15.739770 <6>[ 3.480424] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10712 22:16:15.746371 <6>[ 3.482435] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10713 22:16:15.752561 <6>[ 3.491802] NET: Registered PF_PACKET protocol family
10714 22:16:15.755929 <6>[ 3.497227] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10715 22:16:15.763193 <6>[ 3.501060] 9pnet: Installing 9P2000 support
10716 22:16:15.765954 <6>[ 3.506947] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10717 22:16:15.773111 <5>[ 3.510747] Key type dns_resolver registered
10718 22:16:15.780054 <6>[ 3.516618] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10719 22:16:15.782765 <6>[ 3.520920] registered taskstats version 1
10720 22:16:15.786440 <5>[ 3.531351] Loading compiled-in X.509 certificates
10721 22:16:15.822183 <4>[ 3.559644] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10722 22:16:15.832188 <4>[ 3.570397] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10723 22:16:15.842408 <3>[ 3.583364] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10724 22:16:15.855612 <6>[ 3.599013] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10725 22:16:15.861907 <6>[ 3.605944] xhci-mtk 11200000.usb: xHCI Host Controller
10726 22:16:15.868257 <6>[ 3.611462] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10727 22:16:15.878739 <6>[ 3.619319] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10728 22:16:15.884714 <6>[ 3.628755] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10729 22:16:15.891786 <6>[ 3.634847] xhci-mtk 11200000.usb: xHCI Host Controller
10730 22:16:15.898454 <6>[ 3.640333] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10731 22:16:15.904949 <6>[ 3.647986] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10732 22:16:15.911776 <6>[ 3.655690] hub 1-0:1.0: USB hub found
10733 22:16:15.915091 <6>[ 3.659710] hub 1-0:1.0: 1 port detected
10734 22:16:15.924791 <6>[ 3.664046] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10735 22:16:15.928108 <6>[ 3.672789] hub 2-0:1.0: USB hub found
10736 22:16:15.930845 <6>[ 3.676829] hub 2-0:1.0: 1 port detected
10737 22:16:15.940644 <6>[ 3.684136] mtk-msdc 11f70000.mmc: Got CD GPIO
10738 22:16:15.957916 <6>[ 3.698718] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10739 22:16:15.964503 <6>[ 3.706742] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10740 22:16:15.974613 <4>[ 3.714726] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10741 22:16:15.984496 <6>[ 3.724383] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10742 22:16:15.991035 <6>[ 3.732464] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10743 22:16:15.997664 <6>[ 3.740468] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10744 22:16:16.007605 <6>[ 3.748383] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10745 22:16:16.014256 <6>[ 3.756205] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10746 22:16:16.024556 <6>[ 3.764026] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10747 22:16:16.034258 <6>[ 3.774557] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10748 22:16:16.041062 <6>[ 3.782936] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10749 22:16:16.050975 <6>[ 3.791281] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10750 22:16:16.057261 <6>[ 3.799623] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10751 22:16:16.067380 <6>[ 3.807967] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10752 22:16:16.073993 <6>[ 3.816309] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10753 22:16:16.083898 <6>[ 3.824652] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10754 22:16:16.093982 <6>[ 3.832995] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10755 22:16:16.100148 <6>[ 3.841337] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10756 22:16:16.110653 <6>[ 3.849680] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10757 22:16:16.116602 <6>[ 3.858022] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10758 22:16:16.126857 <6>[ 3.866365] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10759 22:16:16.133548 <6>[ 3.874708] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10760 22:16:16.143465 <6>[ 3.883054] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10761 22:16:16.150492 <6>[ 3.891402] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10762 22:16:16.156371 <6>[ 3.900305] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10763 22:16:16.163466 <6>[ 3.907728] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10764 22:16:16.170486 <6>[ 3.914771] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10765 22:16:16.181628 <6>[ 3.921869] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10766 22:16:16.187511 <6>[ 3.929150] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10767 22:16:16.197624 <6>[ 3.936120] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10768 22:16:16.204110 <6>[ 3.945274] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10769 22:16:16.214057 <6>[ 3.954420] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10770 22:16:16.224189 <6>[ 3.963723] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10771 22:16:16.234256 <6>[ 3.973197] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10772 22:16:16.243987 <6>[ 3.982679] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10773 22:16:16.253582 <6>[ 3.991806] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10774 22:16:16.260390 <6>[ 4.001280] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10775 22:16:16.270249 <6>[ 4.010407] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10776 22:16:16.280535 <6>[ 4.019709] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10777 22:16:16.290189 <6>[ 4.029875] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10778 22:16:16.300327 <6>[ 4.041355] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10779 22:16:16.321625 <6>[ 4.062687] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10780 22:16:16.350349 <6>[ 4.094702] hub 2-1:1.0: USB hub found
10781 22:16:16.353761 <6>[ 4.099221] hub 2-1:1.0: 3 ports detected
10782 22:16:16.474292 <6>[ 4.214562] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10783 22:16:16.626486 <6>[ 4.370746] hub 1-1:1.0: USB hub found
10784 22:16:16.629688 <6>[ 4.375101] hub 1-1:1.0: 4 ports detected
10785 22:16:16.706082 <6>[ 4.446837] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10786 22:16:16.949646 <6>[ 4.690588] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10787 22:16:17.082844 <6>[ 4.826840] hub 1-1.4:1.0: USB hub found
10788 22:16:17.085925 <6>[ 4.831505] hub 1-1.4:1.0: 2 ports detected
10789 22:16:17.381697 <6>[ 5.122592] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10790 22:16:17.573415 <6>[ 5.314590] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10791 22:16:28.581799 <6>[ 16.331134] ALSA device list:
10792 22:16:28.588048 <6>[ 16.334391] No soundcards found.
10793 22:16:28.600568 <6>[ 16.346800] Freeing unused kernel memory: 8384K
10794 22:16:28.604675 <6>[ 16.351733] Run /init as init process
10795 22:16:28.633921 <6>[ 16.379900] NET: Registered PF_INET6 protocol family
10796 22:16:28.640624 <6>[ 16.386047] Segment Routing with IPv6
10797 22:16:28.644057 <6>[ 16.389981] In-situ OAM (IOAM) with IPv6
10798 22:16:28.678721 <30>[ 16.404523] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10799 22:16:28.681586 <30>[ 16.428316] systemd[1]: Detected architecture arm64.
10800 22:16:28.681672
10801 22:16:28.687973 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10802 22:16:28.688057
10803 22:16:28.700760 <30>[ 16.446697] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10804 22:16:28.843763 <30>[ 16.586447] systemd[1]: Queued start job for default target Graphical Interface.
10805 22:16:28.893701 <30>[ 16.639779] systemd[1]: Created slice system-getty.slice.
10806 22:16:28.899959 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10807 22:16:28.917372 <30>[ 16.663170] systemd[1]: Created slice system-modprobe.slice.
10808 22:16:28.923335 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10809 22:16:28.941695 <30>[ 16.687731] systemd[1]: Created slice system-serial\x2dgetty.slice.
10810 22:16:28.952016 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10811 22:16:28.964804 <30>[ 16.711081] systemd[1]: Created slice User and Session Slice.
10812 22:16:28.971505 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10813 22:16:28.992234 <30>[ 16.735151] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10814 22:16:29.002219 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10815 22:16:29.020221 <30>[ 16.762755] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10816 22:16:29.026410 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10817 22:16:29.047020 <30>[ 16.786672] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10818 22:16:29.054090 <30>[ 16.798701] systemd[1]: Reached target Local Encrypted Volumes.
10819 22:16:29.060221 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10820 22:16:29.076401 <30>[ 16.822677] systemd[1]: Reached target Paths.
10821 22:16:29.079805 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10822 22:16:29.097038 <30>[ 16.842616] systemd[1]: Reached target Remote File Systems.
10823 22:16:29.102729 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10824 22:16:29.120575 <30>[ 16.866872] systemd[1]: Reached target Slices.
10825 22:16:29.127343 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10826 22:16:29.140375 <30>[ 16.886635] systemd[1]: Reached target Swap.
10827 22:16:29.143765 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10828 22:16:29.163867 <30>[ 16.906919] systemd[1]: Listening on initctl Compatibility Named Pipe.
10829 22:16:29.170389 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10830 22:16:29.177263 <30>[ 16.921601] systemd[1]: Listening on Journal Audit Socket.
10831 22:16:29.184110 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10832 22:16:29.196869 <30>[ 16.942905] systemd[1]: Listening on Journal Socket (/dev/log).
10833 22:16:29.203122 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10834 22:16:29.221122 <30>[ 16.967368] systemd[1]: Listening on Journal Socket.
10835 22:16:29.227930 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10836 22:16:29.240765 <30>[ 16.986931] systemd[1]: Listening on udev Control Socket.
10837 22:16:29.247359 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10838 22:16:29.265555 <30>[ 17.011262] systemd[1]: Listening on udev Kernel Socket.
10839 22:16:29.271690 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10840 22:16:29.308980 <30>[ 17.054910] systemd[1]: Mounting Huge Pages File System...
10841 22:16:29.315752 Mounting [0;1;39mHuge Pages File System[0m...
10842 22:16:29.330330 <30>[ 17.076626] systemd[1]: Mounting POSIX Message Queue File System...
10843 22:16:29.337138 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10844 22:16:29.354796 <30>[ 17.100723] systemd[1]: Mounting Kernel Debug File System...
10845 22:16:29.361540 Mounting [0;1;39mKernel Debug File System[0m...
10846 22:16:29.380073 <30>[ 17.122876] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10847 22:16:29.404720 <30>[ 17.147089] systemd[1]: Starting Create list of static device nodes for the current kernel...
10848 22:16:29.410563 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10849 22:16:29.431105 <30>[ 17.177199] systemd[1]: Starting Load Kernel Module configfs...
10850 22:16:29.437535 Starting [0;1;39mLoad Kernel Module configfs[0m...
10851 22:16:29.454721 <30>[ 17.200947] systemd[1]: Starting Load Kernel Module drm...
10852 22:16:29.461440 Starting [0;1;39mLoad Kernel Module drm[0m...
10853 22:16:29.480075 <30>[ 17.222809] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10854 22:16:29.529088 <30>[ 17.275235] systemd[1]: Starting Journal Service...
10855 22:16:29.532616 Starting [0;1;39mJournal Service[0m...
10856 22:16:29.551473 <30>[ 17.297471] systemd[1]: Starting Load Kernel Modules...
10857 22:16:29.557973 Starting [0;1;39mLoad Kernel Modules[0m...
10858 22:16:29.578280 <30>[ 17.321269] systemd[1]: Starting Remount Root and Kernel File Systems...
10859 22:16:29.584886 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10860 22:16:29.599308 <30>[ 17.345066] systemd[1]: Starting Coldplug All udev Devices...
10861 22:16:29.605426 Starting [0;1;39mColdplug All udev Devices[0m...
10862 22:16:29.623237 <30>[ 17.369274] systemd[1]: Mounted Huge Pages File System.
10863 22:16:29.630347 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10864 22:16:29.644663 <30>[ 17.391069] systemd[1]: Started Journal Service.
10865 22:16:29.651575 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10866 22:16:29.667047 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10867 22:16:29.685941 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10868 22:16:29.704988 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10869 22:16:29.721836 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10870 22:16:29.737576 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10871 22:16:29.754522 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10872 22:16:29.773490 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10873 22:16:29.788734 See 'systemctl status systemd-remount-fs.service' for details.
10874 22:16:29.841273 Mounting [0;1;39mKernel Configuration File System[0m...
10875 22:16:29.858911 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10876 22:16:29.876589 <46>[ 17.619357] systemd-journald[182]: Received client request to flush runtime journal.
10877 22:16:29.885204 Starting [0;1;39mLoad/Save Random Seed[0m...
10878 22:16:29.904068 Starting [0;1;39mApply Kernel Variables[0m...
10879 22:16:29.923752 Starting [0;1;39mCreate System Users[0m...
10880 22:16:29.938657 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10881 22:16:29.961363 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10882 22:16:29.973620 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10883 22:16:29.989804 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10884 22:16:30.006006 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10885 22:16:30.025382 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10886 22:16:30.068936 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10887 22:16:30.093860 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10888 22:16:30.108543 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10889 22:16:30.128764 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10890 22:16:30.176742 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10891 22:16:30.200117 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10892 22:16:30.218096 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10893 22:16:30.236864 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10894 22:16:30.294057 Starting [0;1;39mNetwork Time Synchronization[0m...
10895 22:16:30.317785 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10896 22:16:30.351506 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10897 22:16:30.383767 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10898 22:16:30.404915 <6>[ 18.147596] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10899 22:16:30.433051 <6>[ 18.179239] remoteproc remoteproc0: scp is available
10900 22:16:30.446044 Startin<4>[ 18.185655] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10901 22:16:30.452652 g [0;1;39mLoad/<6>[ 18.196512] remoteproc remoteproc0: powering up scp
10902 22:16:30.462741 Save Screen …o<4>[ 18.202717] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10903 22:16:30.472713 f leds:white:kbd<6>[ 18.206797] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10904 22:16:30.479299 <3>[ 18.213965] remoteproc remoteproc0: request_firmware failed: -2
10905 22:16:30.489181 _backlight[0m..<6>[ 18.229589] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10906 22:16:30.495491 <3>[ 18.238759] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10907 22:16:30.495570 .
10908 22:16:30.505279 <6>[ 18.239131] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10909 22:16:30.511845 <3>[ 18.247187] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10910 22:16:30.521856 <3>[ 18.264688] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10911 22:16:30.529763 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10912 22:16:30.543866 <3>[ 18.286588] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10913 22:16:30.550225 <3>[ 18.294858] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10914 22:16:30.560372 <3>[ 18.303150] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10915 22:16:30.567145 <3>[ 18.311267] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10916 22:16:30.576811 <3>[ 18.319456] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10917 22:16:30.589914 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_ba<3>[ 18.333225] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10918 22:16:30.593142 cklight[0m.
10919 22:16:30.611507 <4>[ 18.354090] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10920 22:16:30.617753 <3>[ 18.355281] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10921 22:16:30.627501 <3>[ 18.369595] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10922 22:16:30.633991 <3>[ 18.377698] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10923 22:16:30.637493 <6>[ 18.378864] mc: Linux media interface: v0.10
10924 22:16:30.647223 <4>[ 18.381029] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10925 22:16:30.657219 [[0;32m OK [<3>[ 18.387833] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10926 22:16:30.663832 0m] Found device<6>[ 18.390440] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10927 22:16:30.673740 [0;1;39m/dev/t<3>[ 18.397843] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10928 22:16:30.680504 <6>[ 18.407164] pci_bus 0000:00: root bus resource [bus 00-ff]
10929 22:16:30.680587 tyS0[0m.
10930 22:16:30.686880 <3>[ 18.415402] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10931 22:16:30.696793 <3>[ 18.415419] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10932 22:16:30.703644 <3>[ 18.415429] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10933 22:16:30.713313 <3>[ 18.418537] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10934 22:16:30.720505 <6>[ 18.424962] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10935 22:16:30.726658 <6>[ 18.442674] usbcore: registered new interface driver r8152
10936 22:16:30.736873 <6>[ 18.448069] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10937 22:16:30.739785 <6>[ 18.454117] videodev: Linux video capture interface: v2.00
10938 22:16:30.749939 <6>[ 18.465022] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10939 22:16:30.756204 <6>[ 18.471482] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10940 22:16:30.766571 <6>[ 18.475007] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10941 22:16:30.776024 <6>[ 18.475528] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10942 22:16:30.782764 <4>[ 18.500581] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10943 22:16:30.789485 <4>[ 18.500581] Fallback method does not support PEC.
10944 22:16:30.796576 <6>[ 18.507340] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10945 22:16:30.806596 <6>[ 18.512149] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10946 22:16:30.813000 <6>[ 18.536245] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10947 22:16:30.816429 <6>[ 18.539766] pci 0000:00:00.0: supports D1 D2
10948 22:16:30.823371 <6>[ 18.564184] usbcore: registered new interface driver cdc_ether
10949 22:16:30.829626 <6>[ 18.568131] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10950 22:16:30.836323 <6>[ 18.570207] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10951 22:16:30.846420 <3>[ 18.581172] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10952 22:16:30.849845 <6>[ 18.582011] Bluetooth: Core ver 2.22
10953 22:16:30.856512 <6>[ 18.582075] NET: Registered PF_BLUETOOTH protocol family
10954 22:16:30.862594 <6>[ 18.582078] Bluetooth: HCI device and connection manager initialized
10955 22:16:30.869523 <6>[ 18.582094] Bluetooth: HCI socket layer initialized
10956 22:16:30.872589 <6>[ 18.582099] Bluetooth: L2CAP socket layer initialized
10957 22:16:30.879203 <6>[ 18.582116] Bluetooth: SCO socket layer initialized
10958 22:16:30.886072 <6>[ 18.589574] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10959 22:16:30.889722 <6>[ 18.590559] usbcore: registered new interface driver r8153_ecm
10960 22:16:30.899319 <6>[ 18.591317] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10961 22:16:30.909155 <6>[ 18.593539] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10962 22:16:30.916102 <6>[ 18.593693] usbcore: registered new interface driver uvcvideo
10963 22:16:30.926191 <4>[ 18.600050] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10964 22:16:30.932554 <6>[ 18.602048] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10965 22:16:30.942381 <4>[ 18.607631] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10966 22:16:30.948896 <6>[ 18.614220] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10967 22:16:30.955972 <6>[ 18.625777] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10968 22:16:30.962450 <6>[ 18.629809] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10969 22:16:30.968641 <6>[ 18.630444] usbcore: registered new interface driver btusb
10970 22:16:30.979196 <4>[ 18.631314] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10971 22:16:30.986114 <3>[ 18.631326] Bluetooth: hci0: Failed to load firmware file (-2)
10972 22:16:30.989833 <3>[ 18.631330] Bluetooth: hci0: Failed to set up firmware (-2)
10973 22:16:30.999732 <4>[ 18.631335] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10974 22:16:31.007040 <6>[ 18.640149] remoteproc remoteproc0: powering up scp
10975 22:16:31.009843 <6>[ 18.642261] pci 0000:01:00.0: supports D1 D2
10976 22:16:31.020126 <4>[ 18.649428] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10977 22:16:31.026706 <6>[ 18.661892] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10978 22:16:31.033651 <3>[ 18.667848] remoteproc remoteproc0: request_firmware failed: -2
10979 22:16:31.040173 <6>[ 18.694596] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10980 22:16:31.047511 <3>[ 18.700215] fops_vcodec_open(),166: [MTK_V4L2][ERROR] vpu_load_firmware failed!
10981 22:16:31.054084 <6>[ 18.702509] r8152 2-1.3:1.0 eth0: v1.12.13
10982 22:16:31.060467 <6>[ 18.706599] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10983 22:16:31.066957 <6>[ 18.715029] r8152 2-1.3:1.0 enx002432307852: renamed from eth0
10984 22:16:31.073782 <6>[ 18.719800] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10985 22:16:31.084260 <6>[ 18.719814] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10986 22:16:31.090243 <3>[ 18.743625] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10987 22:16:31.100623 <3>[ 18.744420] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10988 22:16:31.110513 <3>[ 18.750774] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10989 22:16:31.117084 <3>[ 18.751535] power_supply sbs-5-000b: driver failed to report `current_avg' property: -6
10990 22:16:31.123998 <6>[ 18.752654] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10991 22:16:31.133893 <6>[ 18.752670] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10992 22:16:31.140735 <3>[ 18.778505] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10993 22:16:31.147559 <6>[ 18.779000] pci 0000:00:00.0: PCI bridge to [bus 01]
10994 22:16:31.157627 <3>[ 18.804757] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10995 22:16:31.164184 <6>[ 18.812004] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10996 22:16:31.170840 <6>[ 18.812213] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10997 22:16:31.180800 <3>[ 18.838610] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10998 22:16:31.184466 <6>[ 18.843809] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10999 22:16:31.195005 <3>[ 18.872291] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11000 22:16:31.201267 <6>[ 18.877116] pcieport 0000:00:00.0: AER: enabled with IRQ 283
11001 22:16:31.208021 <3>[ 18.906849] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11002 22:16:31.218411 <5>[ 18.920731] cfg80211: Loading compiled-in X.509 certificates for regulatory database
11003 22:16:31.225060 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
11004 22:16:31.235836 <5>[ 18.978876] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
11005 22:16:31.242311 <4>[ 18.985795] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
11006 22:16:31.248875 <6>[ 18.994710] cfg80211: failed to load regulatory.db
11007 22:16:31.255983 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
11008 22:16:31.276871 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
11009 22:16:31.296031 <6>[ 19.038685] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
11010 22:16:31.302255 <6>[ 19.046293] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
11011 22:16:31.308689 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
11012 22:16:31.321079 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
11013 22:16:31.327132 <6>[ 19.073063] mt7921e 0000:01:00.0: ASIC revision: 79610010
11014 22:16:31.340261 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
11015 22:16:31.360097 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
11016 22:16:31.376266 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
11017 22:16:31.392203 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
11018 22:16:31.434778 <4>[ 19.174432] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11019 22:16:31.456972 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
11020 22:16:31.486556 Starting [0;1;39mUser Login Management[0m...
11021 22:16:31.502197 Starting [0;1;39mPermit User Sessions[0m...
11022 22:16:31.522050 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
11023 22:16:31.554162 <4>[ 19.293917] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11024 22:16:31.684883 <4>[ 19.424875] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11025 22:16:31.714193 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
11026 22:16:31.721165 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
11027 22:16:31.740027 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
11028 22:16:31.785856 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
11029 22:16:31.809648 <4>[ 19.549201] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11030 22:16:31.816412 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
11031 22:16:31.823608 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
11032 22:16:31.840953 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
11033 22:16:31.856585 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
11034 22:16:31.924816 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
11035 22:16:31.934339 <4>[ 19.675349] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11036 22:16:31.957288 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
11037 22:16:31.974363 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
11038 22:16:31.997979 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
11039 22:16:32.048557
11040 22:16:32.048652
11041 22:16:32.058726 Debian GNU/Linux<4>[ 19.798703] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11042 22:16:32.061624 11 debian-bullseye-arm64 ttyS0
11043 22:16:32.061728
11044 22:16:32.068301 debian-bullseye-arm64 login: root (automatic login)
11045 22:16:32.068406
11046 22:16:32.068498
11047 22:16:32.074541 Linux debian-bullseye-arm64 6.1.31 #1 SMP PREEMPT Mon Jun 5 22:04:07 UTC 2023 aarch64
11048 22:16:32.074620
11049 22:16:32.081386 The programs included with the Debian GNU/Linux system are free software;
11050 22:16:32.087799 the exact distribution terms for each program are described in the
11051 22:16:32.094277 individual files in /usr/share/doc/*/copyright.
11052 22:16:32.094355
11053 22:16:32.097723 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11054 22:16:32.100879 permitted by applicable law.
11055 22:16:32.101205 Matched prompt #10: / #
11057 22:16:32.101416 Setting prompt string to ['/ #']
11058 22:16:32.101512 end: 2.2.5.1 login-action (duration 00:00:21) [common]
11060 22:16:32.101709 end: 2.2.5 auto-login-action (duration 00:00:21) [common]
11061 22:16:32.101804 start: 2.2.6 expect-shell-connection (timeout 00:02:45) [common]
11062 22:16:32.101877 Setting prompt string to ['/ #']
11063 22:16:32.101940 Forcing a shell prompt, looking for ['/ #']
11065 22:16:32.152141 / #
11066 22:16:32.152282 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11067 22:16:32.152390 Waiting using forced prompt support (timeout 00:02:30)
11068 22:16:32.156850
11069 22:16:32.157147 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11070 22:16:32.157270 start: 2.2.7 export-device-env (timeout 00:02:44) [common]
11071 22:16:32.157395 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11072 22:16:32.157513 end: 2.2 depthcharge-retry (duration 00:02:16) [common]
11073 22:16:32.157629 end: 2 depthcharge-action (duration 00:02:16) [common]
11074 22:16:32.157753 start: 3 lava-test-retry (timeout 00:07:21) [common]
11075 22:16:32.157868 start: 3.1 lava-test-shell (timeout 00:07:21) [common]
11076 22:16:32.157999 Using namespace: common
11078 22:16:32.258324 / # #
11079 22:16:32.258484 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11080 22:16:32.258597 <4>[ 19.921172] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11081 22:16:32.262872 #
11082 22:16:32.263157 Using /lava-10597244
11084 22:16:32.363487 / # export SHELL=/bin/sh
11085 22:16:32.363662 <4>[ 20.040735] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11086 22:16:32.368614 export SHELL=/bin/sh
11088 22:16:32.469096 / # . /lava-10597244/environment
11089 22:16:32.469252 <4>[ 20.160404] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11090 22:16:32.473953 . /lava-10597244/environment
11092 22:16:32.574473 / # /lava-10597244/bin/lava-test-runner /lava-10597244/0
11093 22:16:32.574604 Test shell timeout: 10s (minimum of the action and connection timeout)
11094 22:16:32.575059 <4>[ 20.276419] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11095 22:16:32.579216 /lava-10597244/bin/lava-test-run
11096 22:16:32.619475 -sh: 5: /lava-10597244/bin/lava-test-run: not found
11097 22:16:32.644119 / # <3>[ 20.390280] mt7921e 0000:01:00.0: hardware init failed
11098 22:17:00.450215 <6>[ 48.202688] vpu: disabling
11099 22:17:00.453510 <6>[ 48.205762] vproc2: disabling
11100 22:17:00.456869 <6>[ 48.209036] vproc1: disabling
11101 22:17:00.459795 <6>[ 48.212296] vaud18: disabling
11102 22:17:00.466650 <6>[ 48.215699] vsram_others: disabling
11103 22:17:00.466823 <6>[ 48.219572] va09: disabling
11104 22:17:00.473354 <6>[ 48.222676] vsram_md: disabling
11105 22:17:00.473688 <6>[ 48.226162] Vgpu: disabling
11107 22:23:53.158846 end: 3.1 lava-test-shell (duration 00:07:21) [common]
11109 22:23:53.160618 lava-test-retry failed: 1 of 1 attempts. 'lava-test-shell timed out after 441 seconds'
11111 22:23:53.161960 end: 3 lava-test-retry (duration 00:07:21) [common]
11113 22:23:53.163493 Cleaning after the job
11114 22:23:53.163582 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10597244/tftp-deploy-2dx16yrn/ramdisk
11115 22:23:53.169366 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10597244/tftp-deploy-2dx16yrn/kernel
11116 22:23:53.185155 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10597244/tftp-deploy-2dx16yrn/dtb
11117 22:23:53.185470 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10597244/tftp-deploy-2dx16yrn/modules
11118 22:23:53.190911 start: 4.1 power-off (timeout 00:00:30) [common]
11119 22:23:53.191124 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-3' '--port=1' '--command=off'
11120 22:23:53.273641 >> Command sent successfully.
11121 22:23:53.283917 Returned 0 in 0 seconds
11122 22:23:53.385188 end: 4.1 power-off (duration 00:00:00) [common]
11124 22:23:53.386773 start: 4.2 read-feedback (timeout 00:10:00) [common]
11125 22:23:53.388052 Listened to connection for namespace 'common' for up to 1s
11126 22:23:54.388704 Finalising connection for namespace 'common'
11127 22:23:54.389431 Disconnecting from shell: Finalise
11128 22:23:54.490660 end: 4.2 read-feedback (duration 00:00:01) [common]
11129 22:23:54.491335 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/10597244
11130 22:23:54.626712 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/10597244
11131 22:23:54.626922 TestError: A test failed to run, look at the error message.