Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 42
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 30
1 22:16:29.655278 lava-dispatcher, installed at version: 2023.05.1
2 22:16:29.655480 start: 0 validate
3 22:16:29.655613 Start time: 2023-06-05 22:16:29.655606+00:00 (UTC)
4 22:16:29.655733 Using caching service: 'http://localhost/cache/?uri=%s'
5 22:16:29.655859 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230527.0%2Farm64%2Finitrd.cpio.gz exists
6 22:16:29.951265 Using caching service: 'http://localhost/cache/?uri=%s'
7 22:16:29.952069 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1314-g1ab0ac1d7e2e3%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 22:16:30.250696 Using caching service: 'http://localhost/cache/?uri=%s'
9 22:16:30.251490 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1314-g1ab0ac1d7e2e3%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 22:16:30.562461 Using caching service: 'http://localhost/cache/?uri=%s'
11 22:16:30.563220 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230527.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 22:16:30.885074 Using caching service: 'http://localhost/cache/?uri=%s'
13 22:16:30.885764 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1314-g1ab0ac1d7e2e3%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 22:16:31.193530 validate duration: 1.54
16 22:16:31.194769 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 22:16:31.195298 start: 1.1 download-retry (timeout 00:10:00) [common]
18 22:16:31.195802 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 22:16:31.196421 Not decompressing ramdisk as can be used compressed.
20 22:16:31.196960 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230527.0/arm64/initrd.cpio.gz
21 22:16:31.197345 saving as /var/lib/lava/dispatcher/tmp/10597254/tftp-deploy-1g1shtyl/ramdisk/initrd.cpio.gz
22 22:16:31.197697 total size: 4665601 (4MB)
23 22:16:31.203596 progress 0% (0MB)
24 22:16:31.211945 progress 5% (0MB)
25 22:16:31.218301 progress 10% (0MB)
26 22:16:31.222727 progress 15% (0MB)
27 22:16:31.226183 progress 20% (0MB)
28 22:16:31.229158 progress 25% (1MB)
29 22:16:31.231935 progress 30% (1MB)
30 22:16:31.234265 progress 35% (1MB)
31 22:16:31.236625 progress 40% (1MB)
32 22:16:31.238923 progress 45% (2MB)
33 22:16:31.240891 progress 50% (2MB)
34 22:16:31.242762 progress 55% (2MB)
35 22:16:31.244470 progress 60% (2MB)
36 22:16:31.246186 progress 65% (2MB)
37 22:16:31.247814 progress 70% (3MB)
38 22:16:31.249335 progress 75% (3MB)
39 22:16:31.250846 progress 80% (3MB)
40 22:16:31.252526 progress 85% (3MB)
41 22:16:31.253891 progress 90% (4MB)
42 22:16:31.255250 progress 95% (4MB)
43 22:16:31.256626 progress 100% (4MB)
44 22:16:31.256803 4MB downloaded in 0.06s (75.27MB/s)
45 22:16:31.256962 end: 1.1.1 http-download (duration 00:00:00) [common]
47 22:16:31.257235 end: 1.1 download-retry (duration 00:00:00) [common]
48 22:16:31.257322 start: 1.2 download-retry (timeout 00:10:00) [common]
49 22:16:31.257408 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 22:16:31.257535 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1314-g1ab0ac1d7e2e3/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 22:16:31.257610 saving as /var/lib/lava/dispatcher/tmp/10597254/tftp-deploy-1g1shtyl/kernel/Image
52 22:16:31.257672 total size: 45746688 (43MB)
53 22:16:31.257734 No compression specified
54 22:16:31.258931 progress 0% (0MB)
55 22:16:31.270760 progress 5% (2MB)
56 22:16:31.282211 progress 10% (4MB)
57 22:16:31.293619 progress 15% (6MB)
58 22:16:31.304865 progress 20% (8MB)
59 22:16:31.316277 progress 25% (10MB)
60 22:16:31.327423 progress 30% (13MB)
61 22:16:31.338697 progress 35% (15MB)
62 22:16:31.350253 progress 40% (17MB)
63 22:16:31.361738 progress 45% (19MB)
64 22:16:31.373388 progress 50% (21MB)
65 22:16:31.384725 progress 55% (24MB)
66 22:16:31.396088 progress 60% (26MB)
67 22:16:31.407451 progress 65% (28MB)
68 22:16:31.418770 progress 70% (30MB)
69 22:16:31.430033 progress 75% (32MB)
70 22:16:31.441134 progress 80% (34MB)
71 22:16:31.452459 progress 85% (37MB)
72 22:16:31.463900 progress 90% (39MB)
73 22:16:31.475210 progress 95% (41MB)
74 22:16:31.486631 progress 100% (43MB)
75 22:16:31.486750 43MB downloaded in 0.23s (190.45MB/s)
76 22:16:31.486894 end: 1.2.1 http-download (duration 00:00:00) [common]
78 22:16:31.487115 end: 1.2 download-retry (duration 00:00:00) [common]
79 22:16:31.487202 start: 1.3 download-retry (timeout 00:10:00) [common]
80 22:16:31.487286 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 22:16:31.487416 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1314-g1ab0ac1d7e2e3/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 22:16:31.487485 saving as /var/lib/lava/dispatcher/tmp/10597254/tftp-deploy-1g1shtyl/dtb/mt8192-asurada-spherion-r0.dtb
83 22:16:31.487548 total size: 46924 (0MB)
84 22:16:31.487606 No compression specified
85 22:16:31.488647 progress 69% (0MB)
86 22:16:31.488964 progress 100% (0MB)
87 22:16:31.489113 0MB downloaded in 0.00s (28.64MB/s)
88 22:16:31.489230 end: 1.3.1 http-download (duration 00:00:00) [common]
90 22:16:31.489444 end: 1.3 download-retry (duration 00:00:00) [common]
91 22:16:31.489526 start: 1.4 download-retry (timeout 00:10:00) [common]
92 22:16:31.489605 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 22:16:31.489712 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230527.0/arm64/full.rootfs.tar.xz
94 22:16:31.489778 saving as /var/lib/lava/dispatcher/tmp/10597254/tftp-deploy-1g1shtyl/nfsrootfs/full.rootfs.tar
95 22:16:31.489838 total size: 200770336 (191MB)
96 22:16:31.489895 Using unxz to decompress xz
97 22:16:31.493559 progress 0% (0MB)
98 22:16:32.006240 progress 5% (9MB)
99 22:16:32.506512 progress 10% (19MB)
100 22:16:33.077513 progress 15% (28MB)
101 22:16:33.436002 progress 20% (38MB)
102 22:16:33.751289 progress 25% (47MB)
103 22:16:34.330131 progress 30% (57MB)
104 22:16:34.863871 progress 35% (67MB)
105 22:16:35.439193 progress 40% (76MB)
106 22:16:35.983751 progress 45% (86MB)
107 22:16:36.548897 progress 50% (95MB)
108 22:16:37.156084 progress 55% (105MB)
109 22:16:37.791503 progress 60% (114MB)
110 22:16:37.906179 progress 65% (124MB)
111 22:16:38.043821 progress 70% (134MB)
112 22:16:38.137979 progress 75% (143MB)
113 22:16:38.209885 progress 80% (153MB)
114 22:16:38.276929 progress 85% (162MB)
115 22:16:38.372905 progress 90% (172MB)
116 22:16:38.642106 progress 95% (181MB)
117 22:16:39.202490 progress 100% (191MB)
118 22:16:39.207029 191MB downloaded in 7.72s (24.81MB/s)
119 22:16:39.207311 end: 1.4.1 http-download (duration 00:00:08) [common]
121 22:16:39.207568 end: 1.4 download-retry (duration 00:00:08) [common]
122 22:16:39.207658 start: 1.5 download-retry (timeout 00:09:52) [common]
123 22:16:39.207744 start: 1.5.1 http-download (timeout 00:09:52) [common]
124 22:16:39.207892 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1314-g1ab0ac1d7e2e3/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 22:16:39.207965 saving as /var/lib/lava/dispatcher/tmp/10597254/tftp-deploy-1g1shtyl/modules/modules.tar
126 22:16:39.208026 total size: 8543056 (8MB)
127 22:16:39.208087 Using unxz to decompress xz
128 22:16:39.211616 progress 0% (0MB)
129 22:16:39.233043 progress 5% (0MB)
130 22:16:39.257682 progress 10% (0MB)
131 22:16:39.282674 progress 15% (1MB)
132 22:16:39.307023 progress 20% (1MB)
133 22:16:39.329756 progress 25% (2MB)
134 22:16:39.355490 progress 30% (2MB)
135 22:16:39.379717 progress 35% (2MB)
136 22:16:39.403378 progress 40% (3MB)
137 22:16:39.426408 progress 45% (3MB)
138 22:16:39.450192 progress 50% (4MB)
139 22:16:39.472574 progress 55% (4MB)
140 22:16:39.496572 progress 60% (4MB)
141 22:16:39.520881 progress 65% (5MB)
142 22:16:39.544688 progress 70% (5MB)
143 22:16:39.567241 progress 75% (6MB)
144 22:16:39.590756 progress 80% (6MB)
145 22:16:39.614846 progress 85% (6MB)
146 22:16:39.642773 progress 90% (7MB)
147 22:16:39.667182 progress 95% (7MB)
148 22:16:39.690635 progress 100% (8MB)
149 22:16:39.696319 8MB downloaded in 0.49s (16.69MB/s)
150 22:16:39.696579 end: 1.5.1 http-download (duration 00:00:00) [common]
152 22:16:39.696894 end: 1.5 download-retry (duration 00:00:00) [common]
153 22:16:39.696989 start: 1.6 prepare-tftp-overlay (timeout 00:09:51) [common]
154 22:16:39.697084 start: 1.6.1 extract-nfsrootfs (timeout 00:09:51) [common]
155 22:16:42.865845 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/10597254/extract-nfsrootfs-j4uzvb9s
156 22:16:42.866053 end: 1.6.1 extract-nfsrootfs (duration 00:00:03) [common]
157 22:16:42.866158 start: 1.6.2 lava-overlay (timeout 00:09:48) [common]
158 22:16:42.866435 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/10597254/lava-overlay-020odzj4
159 22:16:42.866569 makedir: /var/lib/lava/dispatcher/tmp/10597254/lava-overlay-020odzj4/lava-10597254/bin
160 22:16:42.866668 makedir: /var/lib/lava/dispatcher/tmp/10597254/lava-overlay-020odzj4/lava-10597254/tests
161 22:16:42.866763 makedir: /var/lib/lava/dispatcher/tmp/10597254/lava-overlay-020odzj4/lava-10597254/results
162 22:16:42.866862 Creating /var/lib/lava/dispatcher/tmp/10597254/lava-overlay-020odzj4/lava-10597254/bin/lava-add-keys
163 22:16:42.867002 Creating /var/lib/lava/dispatcher/tmp/10597254/lava-overlay-020odzj4/lava-10597254/bin/lava-add-sources
164 22:16:42.867126 Creating /var/lib/lava/dispatcher/tmp/10597254/lava-overlay-020odzj4/lava-10597254/bin/lava-background-process-start
165 22:16:42.867247 Creating /var/lib/lava/dispatcher/tmp/10597254/lava-overlay-020odzj4/lava-10597254/bin/lava-background-process-stop
166 22:16:42.867368 Creating /var/lib/lava/dispatcher/tmp/10597254/lava-overlay-020odzj4/lava-10597254/bin/lava-common-functions
167 22:16:42.867485 Creating /var/lib/lava/dispatcher/tmp/10597254/lava-overlay-020odzj4/lava-10597254/bin/lava-echo-ipv4
168 22:16:42.867606 Creating /var/lib/lava/dispatcher/tmp/10597254/lava-overlay-020odzj4/lava-10597254/bin/lava-install-packages
169 22:16:42.867724 Creating /var/lib/lava/dispatcher/tmp/10597254/lava-overlay-020odzj4/lava-10597254/bin/lava-installed-packages
170 22:16:42.867842 Creating /var/lib/lava/dispatcher/tmp/10597254/lava-overlay-020odzj4/lava-10597254/bin/lava-os-build
171 22:16:42.867960 Creating /var/lib/lava/dispatcher/tmp/10597254/lava-overlay-020odzj4/lava-10597254/bin/lava-probe-channel
172 22:16:42.868079 Creating /var/lib/lava/dispatcher/tmp/10597254/lava-overlay-020odzj4/lava-10597254/bin/lava-probe-ip
173 22:16:42.868197 Creating /var/lib/lava/dispatcher/tmp/10597254/lava-overlay-020odzj4/lava-10597254/bin/lava-target-ip
174 22:16:42.868315 Creating /var/lib/lava/dispatcher/tmp/10597254/lava-overlay-020odzj4/lava-10597254/bin/lava-target-mac
175 22:16:42.868433 Creating /var/lib/lava/dispatcher/tmp/10597254/lava-overlay-020odzj4/lava-10597254/bin/lava-target-storage
176 22:16:42.868554 Creating /var/lib/lava/dispatcher/tmp/10597254/lava-overlay-020odzj4/lava-10597254/bin/lava-test-case
177 22:16:42.868674 Creating /var/lib/lava/dispatcher/tmp/10597254/lava-overlay-020odzj4/lava-10597254/bin/lava-test-event
178 22:16:42.868819 Creating /var/lib/lava/dispatcher/tmp/10597254/lava-overlay-020odzj4/lava-10597254/bin/lava-test-feedback
179 22:16:42.868960 Creating /var/lib/lava/dispatcher/tmp/10597254/lava-overlay-020odzj4/lava-10597254/bin/lava-test-raise
180 22:16:42.869077 Creating /var/lib/lava/dispatcher/tmp/10597254/lava-overlay-020odzj4/lava-10597254/bin/lava-test-reference
181 22:16:42.869195 Creating /var/lib/lava/dispatcher/tmp/10597254/lava-overlay-020odzj4/lava-10597254/bin/lava-test-runner
182 22:16:42.869312 Creating /var/lib/lava/dispatcher/tmp/10597254/lava-overlay-020odzj4/lava-10597254/bin/lava-test-set
183 22:16:42.869430 Creating /var/lib/lava/dispatcher/tmp/10597254/lava-overlay-020odzj4/lava-10597254/bin/lava-test-shell
184 22:16:42.869551 Updating /var/lib/lava/dispatcher/tmp/10597254/lava-overlay-020odzj4/lava-10597254/bin/lava-add-keys (debian)
185 22:16:42.869702 Updating /var/lib/lava/dispatcher/tmp/10597254/lava-overlay-020odzj4/lava-10597254/bin/lava-add-sources (debian)
186 22:16:42.869836 Updating /var/lib/lava/dispatcher/tmp/10597254/lava-overlay-020odzj4/lava-10597254/bin/lava-install-packages (debian)
187 22:16:42.869968 Updating /var/lib/lava/dispatcher/tmp/10597254/lava-overlay-020odzj4/lava-10597254/bin/lava-installed-packages (debian)
188 22:16:42.870098 Updating /var/lib/lava/dispatcher/tmp/10597254/lava-overlay-020odzj4/lava-10597254/bin/lava-os-build (debian)
189 22:16:42.870214 Creating /var/lib/lava/dispatcher/tmp/10597254/lava-overlay-020odzj4/lava-10597254/environment
190 22:16:42.870306 LAVA metadata
191 22:16:42.870374 - LAVA_JOB_ID=10597254
192 22:16:42.870437 - LAVA_DISPATCHER_IP=192.168.201.1
193 22:16:42.870536 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:48) [common]
194 22:16:42.870601 skipped lava-vland-overlay
195 22:16:42.870674 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 22:16:42.870752 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:48) [common]
197 22:16:42.870812 skipped lava-multinode-overlay
198 22:16:42.870884 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 22:16:42.870960 start: 1.6.2.3 test-definition (timeout 00:09:48) [common]
200 22:16:42.871044 Loading test definitions
201 22:16:42.871132 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:48) [common]
202 22:16:42.871202 Using /lava-10597254 at stage 0
203 22:16:42.871476 uuid=10597254_1.6.2.3.1 testdef=None
204 22:16:42.871562 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 22:16:42.871645 start: 1.6.2.3.2 test-overlay (timeout 00:09:48) [common]
206 22:16:42.872081 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 22:16:42.872298 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:48) [common]
209 22:16:42.873019 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 22:16:42.873249 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:48) [common]
212 22:16:42.873772 runner path: /var/lib/lava/dispatcher/tmp/10597254/lava-overlay-020odzj4/lava-10597254/0/tests/0_timesync-off test_uuid 10597254_1.6.2.3.1
213 22:16:42.873922 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 22:16:42.874140 start: 1.6.2.3.5 git-repo-action (timeout 00:09:48) [common]
216 22:16:42.874213 Using /lava-10597254 at stage 0
217 22:16:42.874308 Fetching tests from https://github.com/kernelci/test-definitions.git
218 22:16:42.874383 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/10597254/lava-overlay-020odzj4/lava-10597254/0/tests/1_kselftest-arm64'
219 22:16:47.210632 Running '/usr/bin/git checkout kernelci.org
220 22:16:47.345776 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/10597254/lava-overlay-020odzj4/lava-10597254/0/tests/1_kselftest-arm64/automated/linux/kselftest/kselftest.yaml
221 22:16:47.346463 uuid=10597254_1.6.2.3.5 testdef=None
222 22:16:47.346619 end: 1.6.2.3.5 git-repo-action (duration 00:00:04) [common]
224 22:16:47.346861 start: 1.6.2.3.6 test-overlay (timeout 00:09:44) [common]
225 22:16:47.347592 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 22:16:47.347822 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:44) [common]
228 22:16:47.348760 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 22:16:47.349034 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:44) [common]
231 22:16:47.349946 runner path: /var/lib/lava/dispatcher/tmp/10597254/lava-overlay-020odzj4/lava-10597254/0/tests/1_kselftest-arm64 test_uuid 10597254_1.6.2.3.5
232 22:16:47.350040 BOARD='mt8192-asurada-spherion-r0'
233 22:16:47.350104 BRANCH='cip-gitlab'
234 22:16:47.350165 SKIPFILE='/dev/null'
235 22:16:47.350223 SKIP_INSTALL='True'
236 22:16:47.350278 TESTPROG_URL='http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1314-g1ab0ac1d7e2e3/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 22:16:47.350335 TST_CASENAME=''
238 22:16:47.350390 TST_CMDFILES='arm64'
239 22:16:47.350531 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 22:16:47.350734 Creating lava-test-runner.conf files
242 22:16:47.350798 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10597254/lava-overlay-020odzj4/lava-10597254/0 for stage 0
243 22:16:47.350890 - 0_timesync-off
244 22:16:47.350960 - 1_kselftest-arm64
245 22:16:47.351053 end: 1.6.2.3 test-definition (duration 00:00:04) [common]
246 22:16:47.351138 start: 1.6.2.4 compress-overlay (timeout 00:09:44) [common]
247 22:16:54.927189 end: 1.6.2.4 compress-overlay (duration 00:00:08) [common]
248 22:16:54.927355 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:36) [common]
249 22:16:54.927458 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 22:16:54.927563 end: 1.6.2 lava-overlay (duration 00:00:12) [common]
251 22:16:54.927654 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:36) [common]
252 22:16:55.040140 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 22:16:55.040497 start: 1.6.4 extract-modules (timeout 00:09:36) [common]
254 22:16:55.040617 extracting modules file /var/lib/lava/dispatcher/tmp/10597254/tftp-deploy-1g1shtyl/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10597254/extract-nfsrootfs-j4uzvb9s
255 22:16:55.241922 extracting modules file /var/lib/lava/dispatcher/tmp/10597254/tftp-deploy-1g1shtyl/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10597254/extract-overlay-ramdisk-b4yy6mfl/ramdisk
256 22:16:55.448206 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 22:16:55.448381 start: 1.6.5 apply-overlay-tftp (timeout 00:09:36) [common]
258 22:16:55.448482 [common] Applying overlay to NFS
259 22:16:55.448554 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10597254/compress-overlay-v28y07a_/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/10597254/extract-nfsrootfs-j4uzvb9s
260 22:16:56.340843 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 22:16:56.341016 start: 1.6.6 configure-preseed-file (timeout 00:09:35) [common]
262 22:16:56.341118 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 22:16:56.341211 start: 1.6.7 compress-ramdisk (timeout 00:09:35) [common]
264 22:16:56.341299 Building ramdisk /var/lib/lava/dispatcher/tmp/10597254/extract-overlay-ramdisk-b4yy6mfl/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/10597254/extract-overlay-ramdisk-b4yy6mfl/ramdisk
265 22:16:56.636695 >> 117807 blocks
266 22:16:58.508521 rename /var/lib/lava/dispatcher/tmp/10597254/extract-overlay-ramdisk-b4yy6mfl/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/10597254/tftp-deploy-1g1shtyl/ramdisk/ramdisk.cpio.gz
267 22:16:58.508957 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 22:16:58.509079 start: 1.6.8 prepare-kernel (timeout 00:09:33) [common]
269 22:16:58.509175 start: 1.6.8.1 prepare-fit (timeout 00:09:33) [common]
270 22:16:58.509281 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/10597254/tftp-deploy-1g1shtyl/kernel/Image'
271 22:17:10.026701 Returned 0 in 11 seconds
272 22:17:10.127377 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/10597254/tftp-deploy-1g1shtyl/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/10597254/tftp-deploy-1g1shtyl/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/10597254/tftp-deploy-1g1shtyl/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/10597254/tftp-deploy-1g1shtyl/kernel/image.itb
273 22:17:10.426632 output: FIT description: Kernel Image image with one or more FDT blobs
274 22:17:10.427062 output: Created: Mon Jun 5 23:17:10 2023
275 22:17:10.427181 output: Image 0 (kernel-1)
276 22:17:10.427284 output: Description:
277 22:17:10.427382 output: Created: Mon Jun 5 23:17:10 2023
278 22:17:10.427477 output: Type: Kernel Image
279 22:17:10.427570 output: Compression: lzma compressed
280 22:17:10.427667 output: Data Size: 10082307 Bytes = 9846.00 KiB = 9.62 MiB
281 22:17:10.427767 output: Architecture: AArch64
282 22:17:10.427863 output: OS: Linux
283 22:17:10.427961 output: Load Address: 0x00000000
284 22:17:10.428055 output: Entry Point: 0x00000000
285 22:17:10.428149 output: Hash algo: crc32
286 22:17:10.428240 output: Hash value: c242daf7
287 22:17:10.428330 output: Image 1 (fdt-1)
288 22:17:10.428413 output: Description: mt8192-asurada-spherion-r0
289 22:17:10.428501 output: Created: Mon Jun 5 23:17:10 2023
290 22:17:10.428591 output: Type: Flat Device Tree
291 22:17:10.428680 output: Compression: uncompressed
292 22:17:10.428775 output: Data Size: 46924 Bytes = 45.82 KiB = 0.04 MiB
293 22:17:10.428869 output: Architecture: AArch64
294 22:17:10.428960 output: Hash algo: crc32
295 22:17:10.429051 output: Hash value: 1df858fa
296 22:17:10.429141 output: Image 2 (ramdisk-1)
297 22:17:10.429229 output: Description: unavailable
298 22:17:10.429317 output: Created: Mon Jun 5 23:17:10 2023
299 22:17:10.429407 output: Type: RAMDisk Image
300 22:17:10.429496 output: Compression: Unknown Compression
301 22:17:10.429584 output: Data Size: 17644909 Bytes = 17231.36 KiB = 16.83 MiB
302 22:17:10.429673 output: Architecture: AArch64
303 22:17:10.429760 output: OS: Linux
304 22:17:10.429849 output: Load Address: unavailable
305 22:17:10.429938 output: Entry Point: unavailable
306 22:17:10.430027 output: Hash algo: crc32
307 22:17:10.430115 output: Hash value: 75fe0eaf
308 22:17:10.430203 output: Default Configuration: 'conf-1'
309 22:17:10.430290 output: Configuration 0 (conf-1)
310 22:17:10.430376 output: Description: mt8192-asurada-spherion-r0
311 22:17:10.430465 output: Kernel: kernel-1
312 22:17:10.430554 output: Init Ramdisk: ramdisk-1
313 22:17:10.430641 output: FDT: fdt-1
314 22:17:10.430728 output: Loadables: kernel-1
315 22:17:10.430817 output:
316 22:17:10.431070 end: 1.6.8.1 prepare-fit (duration 00:00:12) [common]
317 22:17:10.431213 end: 1.6.8 prepare-kernel (duration 00:00:12) [common]
318 22:17:10.431371 end: 1.6 prepare-tftp-overlay (duration 00:00:31) [common]
319 22:17:10.431513 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:21) [common]
320 22:17:10.431627 No LXC device requested
321 22:17:10.431749 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 22:17:10.431880 start: 1.8 deploy-device-env (timeout 00:09:21) [common]
323 22:17:10.432001 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 22:17:10.432107 Checking files for TFTP limit of 4294967296 bytes.
325 22:17:10.432791 end: 1 tftp-deploy (duration 00:00:39) [common]
326 22:17:10.432942 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 22:17:10.433078 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 22:17:10.433264 substitutions:
329 22:17:10.433369 - {DTB}: 10597254/tftp-deploy-1g1shtyl/dtb/mt8192-asurada-spherion-r0.dtb
330 22:17:10.433472 - {INITRD}: 10597254/tftp-deploy-1g1shtyl/ramdisk/ramdisk.cpio.gz
331 22:17:10.433567 - {KERNEL}: 10597254/tftp-deploy-1g1shtyl/kernel/Image
332 22:17:10.433662 - {LAVA_MAC}: None
333 22:17:10.433755 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/10597254/extract-nfsrootfs-j4uzvb9s
334 22:17:10.433849 - {NFS_SERVER_IP}: 192.168.201.1
335 22:17:10.433941 - {PRESEED_CONFIG}: None
336 22:17:10.434034 - {PRESEED_LOCAL}: None
337 22:17:10.434128 - {RAMDISK}: 10597254/tftp-deploy-1g1shtyl/ramdisk/ramdisk.cpio.gz
338 22:17:10.434221 - {ROOT_PART}: None
339 22:17:10.434313 - {ROOT}: None
340 22:17:10.434404 - {SERVER_IP}: 192.168.201.1
341 22:17:10.434495 - {TEE}: None
342 22:17:10.434585 Parsed boot commands:
343 22:17:10.434674 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 22:17:10.434914 Parsed boot commands: tftpboot 192.168.201.1 10597254/tftp-deploy-1g1shtyl/kernel/image.itb 10597254/tftp-deploy-1g1shtyl/kernel/cmdline
345 22:17:10.435052 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 22:17:10.435181 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 22:17:10.435318 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 22:17:10.435457 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 22:17:10.435567 Not connected, no need to disconnect.
350 22:17:10.435686 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 22:17:10.435813 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 22:17:10.435921 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost mt8192-asurada-spherion-r0-cbg-1'
353 22:17:10.439827 Setting prompt string to ['lava-test: # ']
354 22:17:10.440239 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 22:17:10.440382 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 22:17:10.440523 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 22:17:10.440656 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 22:17:10.440980 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=reboot'
359 22:17:15.580575 >> Command sent successfully.
360 22:17:15.582944 Returned 0 in 5 seconds
361 22:17:15.683360 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 22:17:15.683806 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 22:17:15.683956 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 22:17:15.684087 Setting prompt string to 'Starting depthcharge on Spherion...'
366 22:17:15.684196 Changing prompt to 'Starting depthcharge on Spherion...'
367 22:17:15.684301 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 22:17:15.684665 [Enter `^Ec?' for help]
369 22:17:15.857195
370 22:17:15.857380
371 22:17:15.857497 F0: 102B 0000
372 22:17:15.857608
373 22:17:15.857712 F3: 1001 0000 [0200]
374 22:17:15.857822
375 22:17:15.860780 F3: 1001 0000
376 22:17:15.860909
377 22:17:15.861022 F7: 102D 0000
378 22:17:15.861135
379 22:17:15.864642 F1: 0000 0000
380 22:17:15.864735
381 22:17:15.864848 V0: 0000 0000 [0001]
382 22:17:15.864913
383 22:17:15.864972 00: 0007 8000
384 22:17:15.865034
385 22:17:15.868234 01: 0000 0000
386 22:17:15.868321
387 22:17:15.868390 BP: 0C00 0209 [0000]
388 22:17:15.868453
389 22:17:15.872135 G0: 1182 0000
390 22:17:15.872221
391 22:17:15.872320 EC: 0000 0021 [4000]
392 22:17:15.872382
393 22:17:15.875706 S7: 0000 0000 [0000]
394 22:17:15.875792
395 22:17:15.875859 CC: 0000 0000 [0001]
396 22:17:15.875922
397 22:17:15.879502 T0: 0000 0040 [010F]
398 22:17:15.879588
399 22:17:15.879655 Jump to BL
400 22:17:15.879717
401 22:17:15.904434
402 22:17:15.904530
403 22:17:15.904599
404 22:17:15.911027 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
405 22:17:15.914880 ARM64: Exception handlers installed.
406 22:17:15.917966 ARM64: Testing exception
407 22:17:15.921199 ARM64: Done test exception
408 22:17:15.928886 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
409 22:17:15.939287 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
410 22:17:15.946190 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
411 22:17:15.956194 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
412 22:17:15.962667 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
413 22:17:15.969387 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
414 22:17:15.980759 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
415 22:17:15.987864 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
416 22:17:16.007244 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
417 22:17:16.010502 WDT: Last reset was cold boot
418 22:17:16.013751 SPI1(PAD0) initialized at 2873684 Hz
419 22:17:16.017524 SPI5(PAD0) initialized at 992727 Hz
420 22:17:16.020429 VBOOT: Loading verstage.
421 22:17:16.026781 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 22:17:16.030245 FMAP: Found "FLASH" version 1.1 at 0x20000.
423 22:17:16.033728 FMAP: base = 0x0 size = 0x800000 #areas = 25
424 22:17:16.036940 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
425 22:17:16.044718 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
426 22:17:16.051200 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
427 22:17:16.062443 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
428 22:17:16.062567
429 22:17:16.062679
430 22:17:16.072033 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
431 22:17:16.075332 ARM64: Exception handlers installed.
432 22:17:16.078473 ARM64: Testing exception
433 22:17:16.078619 ARM64: Done test exception
434 22:17:16.085506 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
435 22:17:16.088666 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
436 22:17:16.102755 Probing TPM: . done!
437 22:17:16.102916 TPM ready after 0 ms
438 22:17:16.109672 Connected to device vid:did:rid of 1ae0:0028:00
439 22:17:16.116507 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
440 22:17:16.120197 Initialized TPM device CR50 revision 0
441 22:17:16.186123 tlcl_send_startup: Startup return code is 0
442 22:17:16.186313 TPM: setup succeeded
443 22:17:16.197326 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
444 22:17:16.206025 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 22:17:16.216644 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
446 22:17:16.225423 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
447 22:17:16.228877 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
448 22:17:16.236274 in-header: 03 07 00 00 08 00 00 00
449 22:17:16.240072 in-data: aa e4 47 04 13 02 00 00
450 22:17:16.243584 Chrome EC: UHEPI supported
451 22:17:16.250623 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
452 22:17:16.254280 in-header: 03 ad 00 00 08 00 00 00
453 22:17:16.257671 in-data: 00 20 20 08 00 00 00 00
454 22:17:16.257795 Phase 1
455 22:17:16.261270 FMAP: area GBB found @ 3f5000 (12032 bytes)
456 22:17:16.269354 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
457 22:17:16.275922 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
458 22:17:16.276047 Recovery requested (1009000e)
459 22:17:16.288944 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 22:17:16.291994 tlcl_extend: response is 0
461 22:17:16.302691 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 22:17:16.307032 tlcl_extend: response is 0
463 22:17:16.313141 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 22:17:16.333851 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
465 22:17:16.340547 BS: bootblock times (exec / console): total (unknown) / 148 ms
466 22:17:16.340724
467 22:17:16.340903
468 22:17:16.350900 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 22:17:16.354015 ARM64: Exception handlers installed.
470 22:17:16.354159 ARM64: Testing exception
471 22:17:16.357377 ARM64: Done test exception
472 22:17:16.379189 pmic_efuse_setting: Set efuses in 11 msecs
473 22:17:16.382648 pmwrap_interface_init: Select PMIF_VLD_RDY
474 22:17:16.389482 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 22:17:16.393063 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 22:17:16.399516 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 22:17:16.402670 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 22:17:16.406290 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 22:17:16.413357 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 22:17:16.417354 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 22:17:16.420718 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 22:17:16.428016 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 22:17:16.431521 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 22:17:16.436058 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 22:17:16.438734 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 22:17:16.445344 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 22:17:16.452122 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 22:17:16.455515 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 22:17:16.462294 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 22:17:16.469820 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 22:17:16.473725 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 22:17:16.480591 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 22:17:16.484548 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 22:17:16.491032 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 22:17:16.497974 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 22:17:16.501332 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 22:17:16.508179 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 22:17:16.511551 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 22:17:16.518083 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 22:17:16.524795 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 22:17:16.528087 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 22:17:16.534600 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 22:17:16.538632 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 22:17:16.541562 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 22:17:16.547941 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 22:17:16.551566 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 22:17:16.558181 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 22:17:16.561458 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 22:17:16.568163 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 22:17:16.574598 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 22:17:16.577968 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 22:17:16.581394 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 22:17:16.588176 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 22:17:16.591298 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 22:17:16.594360 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 22:17:16.601169 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 22:17:16.604942 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 22:17:16.608649 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 22:17:16.612167 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 22:17:16.619078 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 22:17:16.621839 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 22:17:16.625705 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 22:17:16.628628 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 22:17:16.635561 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 22:17:16.641733 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
526 22:17:16.651763 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 22:17:16.655243 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 22:17:16.662845 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 22:17:16.674010 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 22:17:16.677814 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 22:17:16.680786 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 22:17:16.684287 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 22:17:16.692112 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x7
534 22:17:16.696395 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 22:17:16.704888 [RTC]rtc_osc_init,62: osc32con val = 0xde70
536 22:17:16.707494 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 22:17:16.716799 [RTC]rtc_get_frequency_meter,154: input=15, output=773
538 22:17:16.726473 [RTC]rtc_get_frequency_meter,154: input=23, output=957
539 22:17:16.735323 [RTC]rtc_get_frequency_meter,154: input=19, output=864
540 22:17:16.744715 [RTC]rtc_get_frequency_meter,154: input=17, output=818
541 22:17:16.754502 [RTC]rtc_get_frequency_meter,154: input=16, output=794
542 22:17:16.758274 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
543 22:17:16.764181 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
544 22:17:16.767388 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
545 22:17:16.770930 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
546 22:17:16.774488 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
547 22:17:16.778159 ADC[4]: Raw value=903245 ID=7
548 22:17:16.781674 ADC[3]: Raw value=212810 ID=1
549 22:17:16.781759 RAM Code: 0x71
550 22:17:16.788900 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
551 22:17:16.792194 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
552 22:17:16.799518 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
553 22:17:16.806025 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
554 22:17:16.809308 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
555 22:17:16.813181 in-header: 03 07 00 00 08 00 00 00
556 22:17:16.816034 in-data: aa e4 47 04 13 02 00 00
557 22:17:16.819669 Chrome EC: UHEPI supported
558 22:17:16.826276 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
559 22:17:16.829959 in-header: 03 ed 00 00 08 00 00 00
560 22:17:16.833071 in-data: 80 20 60 08 00 00 00 00
561 22:17:16.836345 MRC: failed to locate region type 0.
562 22:17:16.843079 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
563 22:17:16.846337 DRAM-K: Running full calibration
564 22:17:16.853349 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
565 22:17:16.853436 header.status = 0x0
566 22:17:16.856188 header.version = 0x6 (expected: 0x6)
567 22:17:16.859592 header.size = 0xd00 (expected: 0xd00)
568 22:17:16.863202 header.flags = 0x0
569 22:17:16.869797 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
570 22:17:16.886102 read SPI 0x72590 0x1c583: 12500 us, 9287 KB/s, 74.296 Mbps
571 22:17:16.892902 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
572 22:17:16.896121 dram_init: ddr_geometry: 2
573 22:17:16.899310 [EMI] MDL number = 2
574 22:17:16.899396 [EMI] Get MDL freq = 0
575 22:17:16.902700 dram_init: ddr_type: 0
576 22:17:16.902822 is_discrete_lpddr4: 1
577 22:17:16.905913 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
578 22:17:16.905998
579 22:17:16.906064
580 22:17:16.909554 [Bian_co] ETT version 0.0.0.1
581 22:17:16.916329 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
582 22:17:16.916418
583 22:17:16.919368 dramc_set_vcore_voltage set vcore to 650000
584 22:17:16.922988 Read voltage for 800, 4
585 22:17:16.923073 Vio18 = 0
586 22:17:16.923140 Vcore = 650000
587 22:17:16.926177 Vdram = 0
588 22:17:16.926261 Vddq = 0
589 22:17:16.926327 Vmddr = 0
590 22:17:16.929375 dram_init: config_dvfs: 1
591 22:17:16.933050 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
592 22:17:16.939630 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
593 22:17:16.942514 [SwImpedanceCal] DRVP=9, DRVN=15, ODTN=9
594 22:17:16.945908 freq_region=0, Reg: DRVP=9, DRVN=15, ODTN=9
595 22:17:16.949372 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
596 22:17:16.952552 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
597 22:17:16.955993 MEM_TYPE=3, freq_sel=18
598 22:17:16.960005 sv_algorithm_assistance_LP4_1600
599 22:17:16.962747 ============ PULL DRAM RESETB DOWN ============
600 22:17:16.969132 ========== PULL DRAM RESETB DOWN end =========
601 22:17:16.972708 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
602 22:17:16.976718 ===================================
603 22:17:16.979734 LPDDR4 DRAM CONFIGURATION
604 22:17:16.982793 ===================================
605 22:17:16.982878 EX_ROW_EN[0] = 0x0
606 22:17:16.986028 EX_ROW_EN[1] = 0x0
607 22:17:16.986112 LP4Y_EN = 0x0
608 22:17:16.989117 WORK_FSP = 0x0
609 22:17:16.989200 WL = 0x2
610 22:17:16.992730 RL = 0x2
611 22:17:16.992835 BL = 0x2
612 22:17:16.995912 RPST = 0x0
613 22:17:16.995994 RD_PRE = 0x0
614 22:17:16.999057 WR_PRE = 0x1
615 22:17:16.999142 WR_PST = 0x0
616 22:17:17.002343 DBI_WR = 0x0
617 22:17:17.005769 DBI_RD = 0x0
618 22:17:17.005853 OTF = 0x1
619 22:17:17.009448 ===================================
620 22:17:17.012461 ===================================
621 22:17:17.012546 ANA top config
622 22:17:17.015839 ===================================
623 22:17:17.019298 DLL_ASYNC_EN = 0
624 22:17:17.022377 ALL_SLAVE_EN = 1
625 22:17:17.025750 NEW_RANK_MODE = 1
626 22:17:17.029005 DLL_IDLE_MODE = 1
627 22:17:17.029115 LP45_APHY_COMB_EN = 1
628 22:17:17.032757 TX_ODT_DIS = 1
629 22:17:17.035355 NEW_8X_MODE = 1
630 22:17:17.038835 ===================================
631 22:17:17.042368 ===================================
632 22:17:17.045701 data_rate = 1600
633 22:17:17.049019 CKR = 1
634 22:17:17.049104 DQ_P2S_RATIO = 8
635 22:17:17.052253 ===================================
636 22:17:17.055842 CA_P2S_RATIO = 8
637 22:17:17.058834 DQ_CA_OPEN = 0
638 22:17:17.062808 DQ_SEMI_OPEN = 0
639 22:17:17.065599 CA_SEMI_OPEN = 0
640 22:17:17.065684 CA_FULL_RATE = 0
641 22:17:17.068771 DQ_CKDIV4_EN = 1
642 22:17:17.072337 CA_CKDIV4_EN = 1
643 22:17:17.075494 CA_PREDIV_EN = 0
644 22:17:17.078904 PH8_DLY = 0
645 22:17:17.082053 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
646 22:17:17.082138 DQ_AAMCK_DIV = 4
647 22:17:17.085788 CA_AAMCK_DIV = 4
648 22:17:17.089021 CA_ADMCK_DIV = 4
649 22:17:17.092574 DQ_TRACK_CA_EN = 0
650 22:17:17.095659 CA_PICK = 800
651 22:17:17.098746 CA_MCKIO = 800
652 22:17:17.102598 MCKIO_SEMI = 0
653 22:17:17.102683 PLL_FREQ = 3068
654 22:17:17.105451 DQ_UI_PI_RATIO = 32
655 22:17:17.108753 CA_UI_PI_RATIO = 0
656 22:17:17.112483 ===================================
657 22:17:17.115749 ===================================
658 22:17:17.118892 memory_type:LPDDR4
659 22:17:17.118978 GP_NUM : 10
660 22:17:17.122181 SRAM_EN : 1
661 22:17:17.125646 MD32_EN : 0
662 22:17:17.128753 ===================================
663 22:17:17.128903 [ANA_INIT] >>>>>>>>>>>>>>
664 22:17:17.132479 <<<<<< [CONFIGURE PHASE]: ANA_TX
665 22:17:17.136579 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
666 22:17:17.140121 ===================================
667 22:17:17.144066 data_rate = 1600,PCW = 0X7600
668 22:17:17.147527 ===================================
669 22:17:17.147612 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
670 22:17:17.154995 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
671 22:17:17.162093 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
672 22:17:17.165357 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
673 22:17:17.168725 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
674 22:17:17.172351 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
675 22:17:17.172437 [ANA_INIT] flow start
676 22:17:17.176098 [ANA_INIT] PLL >>>>>>>>
677 22:17:17.179126 [ANA_INIT] PLL <<<<<<<<
678 22:17:17.179211 [ANA_INIT] MIDPI >>>>>>>>
679 22:17:17.182069 [ANA_INIT] MIDPI <<<<<<<<
680 22:17:17.185368 [ANA_INIT] DLL >>>>>>>>
681 22:17:17.185454 [ANA_INIT] flow end
682 22:17:17.192831 ============ LP4 DIFF to SE enter ============
683 22:17:17.195308 ============ LP4 DIFF to SE exit ============
684 22:17:17.198538 [ANA_INIT] <<<<<<<<<<<<<
685 22:17:17.201796 [Flow] Enable top DCM control >>>>>
686 22:17:17.205293 [Flow] Enable top DCM control <<<<<
687 22:17:17.208640 Enable DLL master slave shuffle
688 22:17:17.211610 ==============================================================
689 22:17:17.215217 Gating Mode config
690 22:17:17.218578 ==============================================================
691 22:17:17.221745 Config description:
692 22:17:17.231656 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
693 22:17:17.238454 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
694 22:17:17.241847 SELPH_MODE 0: By rank 1: By Phase
695 22:17:17.248447 ==============================================================
696 22:17:17.251863 GAT_TRACK_EN = 1
697 22:17:17.255011 RX_GATING_MODE = 2
698 22:17:17.258814 RX_GATING_TRACK_MODE = 2
699 22:17:17.261812 SELPH_MODE = 1
700 22:17:17.265044 PICG_EARLY_EN = 1
701 22:17:17.265130 VALID_LAT_VALUE = 1
702 22:17:17.271631 ==============================================================
703 22:17:17.274984 Enter into Gating configuration >>>>
704 22:17:17.278325 Exit from Gating configuration <<<<
705 22:17:17.281829 Enter into DVFS_PRE_config >>>>>
706 22:17:17.291711 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
707 22:17:17.294958 Exit from DVFS_PRE_config <<<<<
708 22:17:17.298430 Enter into PICG configuration >>>>
709 22:17:17.301952 Exit from PICG configuration <<<<
710 22:17:17.304878 [RX_INPUT] configuration >>>>>
711 22:17:17.308593 [RX_INPUT] configuration <<<<<
712 22:17:17.311745 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
713 22:17:17.319045 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
714 22:17:17.325571 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
715 22:17:17.332666 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
716 22:17:17.336314 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
717 22:17:17.343013 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
718 22:17:17.346630 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
719 22:17:17.350524 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
720 22:17:17.353997 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
721 22:17:17.361451 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
722 22:17:17.365110 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
723 22:17:17.368799 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
724 22:17:17.372291 ===================================
725 22:17:17.372378 LPDDR4 DRAM CONFIGURATION
726 22:17:17.375937 ===================================
727 22:17:17.379391 EX_ROW_EN[0] = 0x0
728 22:17:17.379478 EX_ROW_EN[1] = 0x0
729 22:17:17.383054 LP4Y_EN = 0x0
730 22:17:17.383140 WORK_FSP = 0x0
731 22:17:17.386949 WL = 0x2
732 22:17:17.387035 RL = 0x2
733 22:17:17.390508 BL = 0x2
734 22:17:17.390594 RPST = 0x0
735 22:17:17.394897 RD_PRE = 0x0
736 22:17:17.394983 WR_PRE = 0x1
737 22:17:17.398259 WR_PST = 0x0
738 22:17:17.398345 DBI_WR = 0x0
739 22:17:17.401804 DBI_RD = 0x0
740 22:17:17.401891 OTF = 0x1
741 22:17:17.405452 ===================================
742 22:17:17.408980 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
743 22:17:17.412960 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
744 22:17:17.416450 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
745 22:17:17.420420 ===================================
746 22:17:17.423813 LPDDR4 DRAM CONFIGURATION
747 22:17:17.427427 ===================================
748 22:17:17.427514 EX_ROW_EN[0] = 0x10
749 22:17:17.431839 EX_ROW_EN[1] = 0x0
750 22:17:17.431932 LP4Y_EN = 0x0
751 22:17:17.435025 WORK_FSP = 0x0
752 22:17:17.435116 WL = 0x2
753 22:17:17.438568 RL = 0x2
754 22:17:17.438655 BL = 0x2
755 22:17:17.442720 RPST = 0x0
756 22:17:17.442806 RD_PRE = 0x0
757 22:17:17.445863 WR_PRE = 0x1
758 22:17:17.445949 WR_PST = 0x0
759 22:17:17.449735 DBI_WR = 0x0
760 22:17:17.449821 DBI_RD = 0x0
761 22:17:17.449907 OTF = 0x1
762 22:17:17.453646 ===================================
763 22:17:17.460525 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
764 22:17:17.464646 nWR fixed to 40
765 22:17:17.468745 [ModeRegInit_LP4] CH0 RK0
766 22:17:17.468875 [ModeRegInit_LP4] CH0 RK1
767 22:17:17.472551 [ModeRegInit_LP4] CH1 RK0
768 22:17:17.472644 [ModeRegInit_LP4] CH1 RK1
769 22:17:17.476095 match AC timing 13
770 22:17:17.479747 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
771 22:17:17.483486 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
772 22:17:17.487178 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
773 22:17:17.494288 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
774 22:17:17.497909 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
775 22:17:17.497996 [EMI DOE] emi_dcm 0
776 22:17:17.505576 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
777 22:17:17.505665 ==
778 22:17:17.509100 Dram Type= 6, Freq= 0, CH_0, rank 0
779 22:17:17.512762 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
780 22:17:17.512913 ==
781 22:17:17.516972 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
782 22:17:17.523310 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
783 22:17:17.532814 [CA 0] Center 38 (7~69) winsize 63
784 22:17:17.536212 [CA 1] Center 38 (7~69) winsize 63
785 22:17:17.539956 [CA 2] Center 35 (5~66) winsize 62
786 22:17:17.544069 [CA 3] Center 35 (4~66) winsize 63
787 22:17:17.547538 [CA 4] Center 34 (4~65) winsize 62
788 22:17:17.551342 [CA 5] Center 34 (3~65) winsize 63
789 22:17:17.551696
790 22:17:17.555223 [CmdBusTrainingLP45] Vref(ca) range 1: 34
791 22:17:17.555470
792 22:17:17.558499 [CATrainingPosCal] consider 1 rank data
793 22:17:17.558694 u2DelayCellTimex100 = 270/100 ps
794 22:17:17.562225 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
795 22:17:17.565792 CA1 delay=38 (7~69),Diff = 4 PI (28 cell)
796 22:17:17.569780 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
797 22:17:17.572960 CA3 delay=35 (4~66),Diff = 1 PI (7 cell)
798 22:17:17.577182 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
799 22:17:17.580669 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
800 22:17:17.580848
801 22:17:17.584620 CA PerBit enable=1, Macro0, CA PI delay=34
802 22:17:17.584808
803 22:17:17.587920 [CBTSetCACLKResult] CA Dly = 34
804 22:17:17.591738 CS Dly: 6 (0~37)
805 22:17:17.591878 ==
806 22:17:17.595370 Dram Type= 6, Freq= 0, CH_0, rank 1
807 22:17:17.599394 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
808 22:17:17.599549 ==
809 22:17:17.603131 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
810 22:17:17.610162 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
811 22:17:17.618371 [CA 0] Center 38 (7~69) winsize 63
812 22:17:17.622444 [CA 1] Center 38 (7~69) winsize 63
813 22:17:17.625906 [CA 2] Center 35 (5~66) winsize 62
814 22:17:17.629296 [CA 3] Center 35 (5~66) winsize 62
815 22:17:17.632667 [CA 4] Center 35 (4~66) winsize 63
816 22:17:17.635881 [CA 5] Center 34 (4~65) winsize 62
817 22:17:17.635964
818 22:17:17.639525 [CmdBusTrainingLP45] Vref(ca) range 1: 32
819 22:17:17.639608
820 22:17:17.642658 [CATrainingPosCal] consider 2 rank data
821 22:17:17.645917 u2DelayCellTimex100 = 270/100 ps
822 22:17:17.649363 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
823 22:17:17.652528 CA1 delay=38 (7~69),Diff = 4 PI (28 cell)
824 22:17:17.655970 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
825 22:17:17.659342 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
826 22:17:17.662488 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
827 22:17:17.669138 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
828 22:17:17.669225
829 22:17:17.672531 CA PerBit enable=1, Macro0, CA PI delay=34
830 22:17:17.672617
831 22:17:17.675935 [CBTSetCACLKResult] CA Dly = 34
832 22:17:17.676021 CS Dly: 6 (0~38)
833 22:17:17.676106
834 22:17:17.679284 ----->DramcWriteLeveling(PI) begin...
835 22:17:17.679371 ==
836 22:17:17.682732 Dram Type= 6, Freq= 0, CH_0, rank 0
837 22:17:17.685793 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
838 22:17:17.689158 ==
839 22:17:17.689243 Write leveling (Byte 0): 33 => 33
840 22:17:17.692879 Write leveling (Byte 1): 29 => 29
841 22:17:17.696026 DramcWriteLeveling(PI) end<-----
842 22:17:17.696112
843 22:17:17.696197 ==
844 22:17:17.699579 Dram Type= 6, Freq= 0, CH_0, rank 0
845 22:17:17.706451 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
846 22:17:17.706537 ==
847 22:17:17.706625 [Gating] SW mode calibration
848 22:17:17.713335 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
849 22:17:17.721174 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
850 22:17:17.724682 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
851 22:17:17.728560 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
852 22:17:17.732275 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
853 22:17:17.738282 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
854 22:17:17.742029 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
855 22:17:17.745225 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 22:17:17.751885 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 22:17:17.755241 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 22:17:17.758580 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 22:17:17.765224 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 22:17:17.768363 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 22:17:17.771894 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 22:17:17.778347 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 22:17:17.781900 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 22:17:17.785037 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 22:17:17.791817 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 22:17:17.795727 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
867 22:17:17.798756 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
868 22:17:17.801651 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
869 22:17:17.808313 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
870 22:17:17.811717 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
871 22:17:17.814910 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
872 22:17:17.821493 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
873 22:17:17.824648 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 22:17:17.828329 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 22:17:17.835205 0 9 4 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
876 22:17:17.838282 0 9 8 | B1->B0 | 2323 3434 | 1 1 | (1 1) (1 1)
877 22:17:17.841668 0 9 12 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
878 22:17:17.848723 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
879 22:17:17.851690 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
880 22:17:17.854947 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
881 22:17:17.861450 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
882 22:17:17.864874 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
883 22:17:17.868205 0 10 4 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 1)
884 22:17:17.874864 0 10 8 | B1->B0 | 3131 2323 | 0 0 | (0 0) (0 0)
885 22:17:17.878921 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
886 22:17:17.881509 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
887 22:17:17.888049 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
888 22:17:17.891783 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
889 22:17:17.895148 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 22:17:17.901585 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
891 22:17:17.905518 0 11 4 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
892 22:17:17.908002 0 11 8 | B1->B0 | 2b2b 4646 | 1 0 | (0 0) (0 0)
893 22:17:17.914736 0 11 12 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
894 22:17:17.918110 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
895 22:17:17.921503 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
896 22:17:17.925315 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
897 22:17:17.931586 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 22:17:17.934764 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
899 22:17:17.938196 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
900 22:17:17.945064 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
901 22:17:17.947989 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
902 22:17:17.951587 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
903 22:17:17.957785 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
904 22:17:17.961147 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 22:17:17.964407 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 22:17:17.971279 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 22:17:17.974491 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 22:17:17.977764 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 22:17:17.984551 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 22:17:17.988017 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 22:17:17.990982 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 22:17:17.997679 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 22:17:18.001270 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
914 22:17:18.004435 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
915 22:17:18.010938 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
916 22:17:18.014469 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
917 22:17:18.017666 Total UI for P1: 0, mck2ui 16
918 22:17:18.020948 best dqsien dly found for B0: ( 0, 14, 6)
919 22:17:18.024580 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
920 22:17:18.028109 Total UI for P1: 0, mck2ui 16
921 22:17:18.030895 best dqsien dly found for B1: ( 0, 14, 8)
922 22:17:18.034285 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
923 22:17:18.037671 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
924 22:17:18.037777
925 22:17:18.040847 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
926 22:17:18.047624 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
927 22:17:18.047727 [Gating] SW calibration Done
928 22:17:18.047823 ==
929 22:17:18.051160 Dram Type= 6, Freq= 0, CH_0, rank 0
930 22:17:18.057878 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
931 22:17:18.057989 ==
932 22:17:18.058077 RX Vref Scan: 0
933 22:17:18.058179
934 22:17:18.061413 RX Vref 0 -> 0, step: 1
935 22:17:18.061501
936 22:17:18.064258 RX Delay -130 -> 252, step: 16
937 22:17:18.068357 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
938 22:17:18.071007 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
939 22:17:18.074568 iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224
940 22:17:18.081008 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
941 22:17:18.085097 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
942 22:17:18.087902 iDelay=222, Bit 5, Center 85 (-18 ~ 189) 208
943 22:17:18.091031 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
944 22:17:18.094085 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
945 22:17:18.101025 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
946 22:17:18.104253 iDelay=222, Bit 9, Center 69 (-34 ~ 173) 208
947 22:17:18.107503 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
948 22:17:18.110824 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
949 22:17:18.114038 iDelay=222, Bit 12, Center 85 (-18 ~ 189) 208
950 22:17:18.120997 iDelay=222, Bit 13, Center 85 (-18 ~ 189) 208
951 22:17:18.124185 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
952 22:17:18.127413 iDelay=222, Bit 15, Center 85 (-18 ~ 189) 208
953 22:17:18.127501 ==
954 22:17:18.130928 Dram Type= 6, Freq= 0, CH_0, rank 0
955 22:17:18.134141 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
956 22:17:18.134228 ==
957 22:17:18.137396 DQS Delay:
958 22:17:18.137485 DQS0 = 0, DQS1 = 0
959 22:17:18.140733 DQM Delay:
960 22:17:18.140842 DQM0 = 94, DQM1 = 83
961 22:17:18.140910 DQ Delay:
962 22:17:18.144069 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =93
963 22:17:18.148020 DQ4 =93, DQ5 =85, DQ6 =101, DQ7 =101
964 22:17:18.151170 DQ8 =77, DQ9 =69, DQ10 =85, DQ11 =85
965 22:17:18.154212 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =85
966 22:17:18.154297
967 22:17:18.154364
968 22:17:18.157660 ==
969 22:17:18.160780 Dram Type= 6, Freq= 0, CH_0, rank 0
970 22:17:18.164515 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
971 22:17:18.164604 ==
972 22:17:18.164671
973 22:17:18.164734
974 22:17:18.167232 TX Vref Scan disable
975 22:17:18.167317 == TX Byte 0 ==
976 22:17:18.174381 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
977 22:17:18.177456 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
978 22:17:18.177543 == TX Byte 1 ==
979 22:17:18.184231 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
980 22:17:18.187728 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
981 22:17:18.187815 ==
982 22:17:18.190790 Dram Type= 6, Freq= 0, CH_0, rank 0
983 22:17:18.193916 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
984 22:17:18.194003 ==
985 22:17:18.207536 TX Vref=22, minBit 11, minWin=26, winSum=437
986 22:17:18.210873 TX Vref=24, minBit 7, minWin=27, winSum=443
987 22:17:18.214006 TX Vref=26, minBit 12, minWin=27, winSum=448
988 22:17:18.217256 TX Vref=28, minBit 10, minWin=27, winSum=452
989 22:17:18.223855 TX Vref=30, minBit 10, minWin=27, winSum=453
990 22:17:18.227247 TX Vref=32, minBit 13, minWin=27, winSum=454
991 22:17:18.234513 [TxChooseVref] Worse bit 13, Min win 27, Win sum 454, Final Vref 32
992 22:17:18.234651
993 22:17:18.234749 Final TX Range 1 Vref 32
994 22:17:18.234896
995 22:17:18.234982 ==
996 22:17:18.237217 Dram Type= 6, Freq= 0, CH_0, rank 0
997 22:17:18.243661 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
998 22:17:18.243816 ==
999 22:17:18.243938
1000 22:17:18.244044
1001 22:17:18.244146 TX Vref Scan disable
1002 22:17:18.248130 == TX Byte 0 ==
1003 22:17:18.251607 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1004 22:17:18.255245 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1005 22:17:18.258091 == TX Byte 1 ==
1006 22:17:18.261383 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1007 22:17:18.268540 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1008 22:17:18.268681
1009 22:17:18.268756 [DATLAT]
1010 22:17:18.268865 Freq=800, CH0 RK0
1011 22:17:18.268961
1012 22:17:18.271449 DATLAT Default: 0xa
1013 22:17:18.271561 0, 0xFFFF, sum = 0
1014 22:17:18.275007 1, 0xFFFF, sum = 0
1015 22:17:18.275121 2, 0xFFFF, sum = 0
1016 22:17:18.278324 3, 0xFFFF, sum = 0
1017 22:17:18.281400 4, 0xFFFF, sum = 0
1018 22:17:18.281524 5, 0xFFFF, sum = 0
1019 22:17:18.284664 6, 0xFFFF, sum = 0
1020 22:17:18.284835 7, 0xFFFF, sum = 0
1021 22:17:18.287951 8, 0xFFFF, sum = 0
1022 22:17:18.288071 9, 0x0, sum = 1
1023 22:17:18.288229 10, 0x0, sum = 2
1024 22:17:18.291278 11, 0x0, sum = 3
1025 22:17:18.291425 12, 0x0, sum = 4
1026 22:17:18.294686 best_step = 10
1027 22:17:18.294799
1028 22:17:18.294946 ==
1029 22:17:18.298003 Dram Type= 6, Freq= 0, CH_0, rank 0
1030 22:17:18.301282 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1031 22:17:18.301413 ==
1032 22:17:18.304487 RX Vref Scan: 1
1033 22:17:18.304609
1034 22:17:18.308492 Set Vref Range= 32 -> 127
1035 22:17:18.308604
1036 22:17:18.308676 RX Vref 32 -> 127, step: 1
1037 22:17:18.308740
1038 22:17:18.311226 RX Delay -79 -> 252, step: 8
1039 22:17:18.311314
1040 22:17:18.314297 Set Vref, RX VrefLevel [Byte0]: 32
1041 22:17:18.317759 [Byte1]: 32
1042 22:17:18.317848
1043 22:17:18.321290 Set Vref, RX VrefLevel [Byte0]: 33
1044 22:17:18.324753 [Byte1]: 33
1045 22:17:18.328213
1046 22:17:18.328301 Set Vref, RX VrefLevel [Byte0]: 34
1047 22:17:18.331849 [Byte1]: 34
1048 22:17:18.336308
1049 22:17:18.336398 Set Vref, RX VrefLevel [Byte0]: 35
1050 22:17:18.339106 [Byte1]: 35
1051 22:17:18.343726
1052 22:17:18.343817 Set Vref, RX VrefLevel [Byte0]: 36
1053 22:17:18.346971 [Byte1]: 36
1054 22:17:18.350938
1055 22:17:18.351033 Set Vref, RX VrefLevel [Byte0]: 37
1056 22:17:18.354442 [Byte1]: 37
1057 22:17:18.358503
1058 22:17:18.358593 Set Vref, RX VrefLevel [Byte0]: 38
1059 22:17:18.362105 [Byte1]: 38
1060 22:17:18.365996
1061 22:17:18.366083 Set Vref, RX VrefLevel [Byte0]: 39
1062 22:17:18.369258 [Byte1]: 39
1063 22:17:18.374406
1064 22:17:18.374503 Set Vref, RX VrefLevel [Byte0]: 40
1065 22:17:18.377234 [Byte1]: 40
1066 22:17:18.381506
1067 22:17:18.381598 Set Vref, RX VrefLevel [Byte0]: 41
1068 22:17:18.384678 [Byte1]: 41
1069 22:17:18.388874
1070 22:17:18.389007 Set Vref, RX VrefLevel [Byte0]: 42
1071 22:17:18.392200 [Byte1]: 42
1072 22:17:18.396275
1073 22:17:18.396406 Set Vref, RX VrefLevel [Byte0]: 43
1074 22:17:18.399723 [Byte1]: 43
1075 22:17:18.404138
1076 22:17:18.404273 Set Vref, RX VrefLevel [Byte0]: 44
1077 22:17:18.407575 [Byte1]: 44
1078 22:17:18.411419
1079 22:17:18.411535 Set Vref, RX VrefLevel [Byte0]: 45
1080 22:17:18.415091 [Byte1]: 45
1081 22:17:18.419173
1082 22:17:18.419287 Set Vref, RX VrefLevel [Byte0]: 46
1083 22:17:18.422011 [Byte1]: 46
1084 22:17:18.426633
1085 22:17:18.426722 Set Vref, RX VrefLevel [Byte0]: 47
1086 22:17:18.430162 [Byte1]: 47
1087 22:17:18.434181
1088 22:17:18.434267 Set Vref, RX VrefLevel [Byte0]: 48
1089 22:17:18.437289 [Byte1]: 48
1090 22:17:18.441904
1091 22:17:18.441990 Set Vref, RX VrefLevel [Byte0]: 49
1092 22:17:18.444719 [Byte1]: 49
1093 22:17:18.449457
1094 22:17:18.449542 Set Vref, RX VrefLevel [Byte0]: 50
1095 22:17:18.452984 [Byte1]: 50
1096 22:17:18.456914
1097 22:17:18.457008 Set Vref, RX VrefLevel [Byte0]: 51
1098 22:17:18.459956 [Byte1]: 51
1099 22:17:18.464189
1100 22:17:18.464276 Set Vref, RX VrefLevel [Byte0]: 52
1101 22:17:18.467607 [Byte1]: 52
1102 22:17:18.471653
1103 22:17:18.471743 Set Vref, RX VrefLevel [Byte0]: 53
1104 22:17:18.474975 [Byte1]: 53
1105 22:17:18.479282
1106 22:17:18.479370 Set Vref, RX VrefLevel [Byte0]: 54
1107 22:17:18.482722 [Byte1]: 54
1108 22:17:18.486796
1109 22:17:18.486884 Set Vref, RX VrefLevel [Byte0]: 55
1110 22:17:18.490211 [Byte1]: 55
1111 22:17:18.494350
1112 22:17:18.494457 Set Vref, RX VrefLevel [Byte0]: 56
1113 22:17:18.497652 [Byte1]: 56
1114 22:17:18.502089
1115 22:17:18.502175 Set Vref, RX VrefLevel [Byte0]: 57
1116 22:17:18.505250 [Byte1]: 57
1117 22:17:18.509618
1118 22:17:18.509705 Set Vref, RX VrefLevel [Byte0]: 58
1119 22:17:18.512963 [Byte1]: 58
1120 22:17:18.517254
1121 22:17:18.517345 Set Vref, RX VrefLevel [Byte0]: 59
1122 22:17:18.520296 [Byte1]: 59
1123 22:17:18.524574
1124 22:17:18.524704 Set Vref, RX VrefLevel [Byte0]: 60
1125 22:17:18.528102 [Byte1]: 60
1126 22:17:18.532044
1127 22:17:18.532132 Set Vref, RX VrefLevel [Byte0]: 61
1128 22:17:18.535569 [Byte1]: 61
1129 22:17:18.539528
1130 22:17:18.539617 Set Vref, RX VrefLevel [Byte0]: 62
1131 22:17:18.542962 [Byte1]: 62
1132 22:17:18.547403
1133 22:17:18.547527 Set Vref, RX VrefLevel [Byte0]: 63
1134 22:17:18.550853 [Byte1]: 63
1135 22:17:18.554852
1136 22:17:18.554956 Set Vref, RX VrefLevel [Byte0]: 64
1137 22:17:18.558065 [Byte1]: 64
1138 22:17:18.562555
1139 22:17:18.562660 Set Vref, RX VrefLevel [Byte0]: 65
1140 22:17:18.565702 [Byte1]: 65
1141 22:17:18.569687
1142 22:17:18.569815 Set Vref, RX VrefLevel [Byte0]: 66
1143 22:17:18.573409 [Byte1]: 66
1144 22:17:18.577865
1145 22:17:18.577992 Set Vref, RX VrefLevel [Byte0]: 67
1146 22:17:18.580673 [Byte1]: 67
1147 22:17:18.584955
1148 22:17:18.585099 Set Vref, RX VrefLevel [Byte0]: 68
1149 22:17:18.588232 [Byte1]: 68
1150 22:17:18.592963
1151 22:17:18.593085 Set Vref, RX VrefLevel [Byte0]: 69
1152 22:17:18.596273 [Byte1]: 69
1153 22:17:18.600143
1154 22:17:18.600276 Set Vref, RX VrefLevel [Byte0]: 70
1155 22:17:18.603503 [Byte1]: 70
1156 22:17:18.607474
1157 22:17:18.607597 Set Vref, RX VrefLevel [Byte0]: 71
1158 22:17:18.610940 [Byte1]: 71
1159 22:17:18.615167
1160 22:17:18.615274 Set Vref, RX VrefLevel [Byte0]: 72
1161 22:17:18.618474 [Byte1]: 72
1162 22:17:18.622679
1163 22:17:18.622805 Set Vref, RX VrefLevel [Byte0]: 73
1164 22:17:18.625965 [Byte1]: 73
1165 22:17:18.630225
1166 22:17:18.630355 Set Vref, RX VrefLevel [Byte0]: 74
1167 22:17:18.633810 [Byte1]: 74
1168 22:17:18.638025
1169 22:17:18.638128 Set Vref, RX VrefLevel [Byte0]: 75
1170 22:17:18.641080 [Byte1]: 75
1171 22:17:18.645257
1172 22:17:18.645359 Set Vref, RX VrefLevel [Byte0]: 76
1173 22:17:18.649047 [Byte1]: 76
1174 22:17:18.653482
1175 22:17:18.653607 Set Vref, RX VrefLevel [Byte0]: 77
1176 22:17:18.656432 [Byte1]: 77
1177 22:17:18.660465
1178 22:17:18.660587 Final RX Vref Byte 0 = 60 to rank0
1179 22:17:18.663650 Final RX Vref Byte 1 = 58 to rank0
1180 22:17:18.666950 Final RX Vref Byte 0 = 60 to rank1
1181 22:17:18.670310 Final RX Vref Byte 1 = 58 to rank1==
1182 22:17:18.673790 Dram Type= 6, Freq= 0, CH_0, rank 0
1183 22:17:18.680350 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1184 22:17:18.680482 ==
1185 22:17:18.680591 DQS Delay:
1186 22:17:18.680694 DQS0 = 0, DQS1 = 0
1187 22:17:18.684274 DQM Delay:
1188 22:17:18.684396 DQM0 = 92, DQM1 = 83
1189 22:17:18.686943 DQ Delay:
1190 22:17:18.690326 DQ0 =88, DQ1 =96, DQ2 =88, DQ3 =88
1191 22:17:18.693753 DQ4 =92, DQ5 =80, DQ6 =104, DQ7 =104
1192 22:17:18.697018 DQ8 =76, DQ9 =72, DQ10 =84, DQ11 =80
1193 22:17:18.700424 DQ12 =84, DQ13 =84, DQ14 =92, DQ15 =92
1194 22:17:18.700529
1195 22:17:18.700626
1196 22:17:18.706776 [DQSOSCAuto] RK0, (LSB)MR18= 0x3732, (MSB)MR19= 0x606, tDQSOscB0 = 397 ps tDQSOscB1 = 395 ps
1197 22:17:18.710204 CH0 RK0: MR19=606, MR18=3732
1198 22:17:18.716664 CH0_RK0: MR19=0x606, MR18=0x3732, DQSOSC=395, MR23=63, INC=94, DEC=63
1199 22:17:18.716760
1200 22:17:18.720609 ----->DramcWriteLeveling(PI) begin...
1201 22:17:18.720714 ==
1202 22:17:18.723581 Dram Type= 6, Freq= 0, CH_0, rank 1
1203 22:17:18.726652 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1204 22:17:18.726817 ==
1205 22:17:18.729729 Write leveling (Byte 0): 31 => 31
1206 22:17:18.733333 Write leveling (Byte 1): 30 => 30
1207 22:17:18.736598 DramcWriteLeveling(PI) end<-----
1208 22:17:18.736704
1209 22:17:18.736783 ==
1210 22:17:18.739822 Dram Type= 6, Freq= 0, CH_0, rank 1
1211 22:17:18.743114 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1212 22:17:18.743217 ==
1213 22:17:18.746561 [Gating] SW mode calibration
1214 22:17:18.753437 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1215 22:17:18.759778 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1216 22:17:18.763317 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1217 22:17:18.769818 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1218 22:17:18.773249 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1219 22:17:18.776307 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1220 22:17:18.783261 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1221 22:17:18.827139 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1222 22:17:18.827478 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1223 22:17:18.827561 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1224 22:17:18.828257 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 22:17:18.828524 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 22:17:18.828608 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 22:17:18.828676 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 22:17:18.828926 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 22:17:18.829205 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 22:17:18.829484 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 22:17:18.871089 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 22:17:18.871192 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1233 22:17:18.871444 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1234 22:17:18.871829 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1235 22:17:18.872193 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1236 22:17:18.872460 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1237 22:17:18.872535 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1238 22:17:18.872601 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1239 22:17:18.872852 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1240 22:17:18.873099 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1241 22:17:18.886322 0 9 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1242 22:17:18.886410 0 9 8 | B1->B0 | 3030 3434 | 0 0 | (0 0) (0 0)
1243 22:17:18.886760 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1244 22:17:18.889853 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1245 22:17:18.893227 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1246 22:17:18.896698 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1247 22:17:18.900106 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1248 22:17:18.903424 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1249 22:17:18.909654 0 10 4 | B1->B0 | 3434 3030 | 1 0 | (1 0) (0 1)
1250 22:17:18.913516 0 10 8 | B1->B0 | 2d2d 2525 | 0 0 | (0 1) (0 0)
1251 22:17:18.916556 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1252 22:17:18.922982 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1253 22:17:18.926717 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1254 22:17:18.929751 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1255 22:17:18.936200 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1256 22:17:18.939410 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1257 22:17:18.942738 0 11 4 | B1->B0 | 2525 3030 | 0 1 | (0 0) (0 0)
1258 22:17:18.949566 0 11 8 | B1->B0 | 3a3a 4646 | 1 0 | (0 0) (0 0)
1259 22:17:18.952958 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1260 22:17:18.956194 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1261 22:17:18.963284 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1262 22:17:18.966284 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1263 22:17:18.970035 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1264 22:17:18.973802 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1265 22:17:18.980641 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1266 22:17:18.983900 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1267 22:17:18.987082 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1268 22:17:18.990821 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1269 22:17:18.997976 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1270 22:17:19.001063 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1271 22:17:19.004264 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1272 22:17:19.011212 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1273 22:17:19.015001 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1274 22:17:19.018445 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1275 22:17:19.024543 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1276 22:17:19.027934 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1277 22:17:19.030959 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1278 22:17:19.037618 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1279 22:17:19.040721 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1280 22:17:19.044244 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1281 22:17:19.051309 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1282 22:17:19.054135 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1283 22:17:19.057313 Total UI for P1: 0, mck2ui 16
1284 22:17:19.060762 best dqsien dly found for B0: ( 0, 14, 4)
1285 22:17:19.064022 Total UI for P1: 0, mck2ui 16
1286 22:17:19.067386 best dqsien dly found for B1: ( 0, 14, 4)
1287 22:17:19.070925 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1288 22:17:19.074483 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1289 22:17:19.074591
1290 22:17:19.077335 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1291 22:17:19.080746 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1292 22:17:19.084182 [Gating] SW calibration Done
1293 22:17:19.084287 ==
1294 22:17:19.087402 Dram Type= 6, Freq= 0, CH_0, rank 1
1295 22:17:19.091138 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1296 22:17:19.091246 ==
1297 22:17:19.094257 RX Vref Scan: 0
1298 22:17:19.094363
1299 22:17:19.097651 RX Vref 0 -> 0, step: 1
1300 22:17:19.097761
1301 22:17:19.097857 RX Delay -130 -> 252, step: 16
1302 22:17:19.104137 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1303 22:17:19.107185 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1304 22:17:19.110766 iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224
1305 22:17:19.113766 iDelay=222, Bit 3, Center 77 (-34 ~ 189) 224
1306 22:17:19.117308 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1307 22:17:19.123814 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
1308 22:17:19.127295 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1309 22:17:19.130486 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1310 22:17:19.133859 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1311 22:17:19.137145 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
1312 22:17:19.143937 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1313 22:17:19.146909 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1314 22:17:19.150375 iDelay=222, Bit 12, Center 85 (-18 ~ 189) 208
1315 22:17:19.153583 iDelay=222, Bit 13, Center 85 (-18 ~ 189) 208
1316 22:17:19.160809 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1317 22:17:19.164186 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1318 22:17:19.164295 ==
1319 22:17:19.167072 Dram Type= 6, Freq= 0, CH_0, rank 1
1320 22:17:19.170596 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1321 22:17:19.170720 ==
1322 22:17:19.170817 DQS Delay:
1323 22:17:19.173905 DQS0 = 0, DQS1 = 0
1324 22:17:19.174013 DQM Delay:
1325 22:17:19.177102 DQM0 = 90, DQM1 = 81
1326 22:17:19.177208 DQ Delay:
1327 22:17:19.180561 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =77
1328 22:17:19.183634 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =93
1329 22:17:19.187412 DQ8 =77, DQ9 =61, DQ10 =77, DQ11 =77
1330 22:17:19.190304 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =93
1331 22:17:19.190410
1332 22:17:19.190502
1333 22:17:19.190595 ==
1334 22:17:19.193555 Dram Type= 6, Freq= 0, CH_0, rank 1
1335 22:17:19.200230 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1336 22:17:19.200339 ==
1337 22:17:19.200433
1338 22:17:19.200521
1339 22:17:19.200610 TX Vref Scan disable
1340 22:17:19.203414 == TX Byte 0 ==
1341 22:17:19.206878 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1342 22:17:19.213356 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1343 22:17:19.213490 == TX Byte 1 ==
1344 22:17:19.216968 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1345 22:17:19.223464 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1346 22:17:19.223574 ==
1347 22:17:19.226689 Dram Type= 6, Freq= 0, CH_0, rank 1
1348 22:17:19.230109 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1349 22:17:19.230217 ==
1350 22:17:19.242678 TX Vref=22, minBit 3, minWin=27, winSum=441
1351 22:17:19.246205 TX Vref=24, minBit 8, minWin=27, winSum=446
1352 22:17:19.249659 TX Vref=26, minBit 8, minWin=27, winSum=447
1353 22:17:19.252683 TX Vref=28, minBit 8, minWin=27, winSum=453
1354 22:17:19.255889 TX Vref=30, minBit 10, minWin=27, winSum=456
1355 22:17:19.262674 TX Vref=32, minBit 8, minWin=27, winSum=453
1356 22:17:19.265837 [TxChooseVref] Worse bit 10, Min win 27, Win sum 456, Final Vref 30
1357 22:17:19.265941
1358 22:17:19.269107 Final TX Range 1 Vref 30
1359 22:17:19.269229
1360 22:17:19.269323 ==
1361 22:17:19.272528 Dram Type= 6, Freq= 0, CH_0, rank 1
1362 22:17:19.275778 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1363 22:17:19.279028 ==
1364 22:17:19.279135
1365 22:17:19.279228
1366 22:17:19.279319 TX Vref Scan disable
1367 22:17:19.282544 == TX Byte 0 ==
1368 22:17:19.285761 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1369 22:17:19.292635 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1370 22:17:19.292743 == TX Byte 1 ==
1371 22:17:19.296407 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1372 22:17:19.302557 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1373 22:17:19.302662
1374 22:17:19.302753 [DATLAT]
1375 22:17:19.302844 Freq=800, CH0 RK1
1376 22:17:19.302934
1377 22:17:19.305878 DATLAT Default: 0xa
1378 22:17:19.305982 0, 0xFFFF, sum = 0
1379 22:17:19.309180 1, 0xFFFF, sum = 0
1380 22:17:19.309287 2, 0xFFFF, sum = 0
1381 22:17:19.312453 3, 0xFFFF, sum = 0
1382 22:17:19.316145 4, 0xFFFF, sum = 0
1383 22:17:19.316252 5, 0xFFFF, sum = 0
1384 22:17:19.319374 6, 0xFFFF, sum = 0
1385 22:17:19.319482 7, 0xFFFF, sum = 0
1386 22:17:19.322606 8, 0xFFFF, sum = 0
1387 22:17:19.322710 9, 0x0, sum = 1
1388 22:17:19.325610 10, 0x0, sum = 2
1389 22:17:19.325716 11, 0x0, sum = 3
1390 22:17:19.325805 12, 0x0, sum = 4
1391 22:17:19.329117 best_step = 10
1392 22:17:19.329219
1393 22:17:19.329311 ==
1394 22:17:19.332364 Dram Type= 6, Freq= 0, CH_0, rank 1
1395 22:17:19.335617 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1396 22:17:19.335723 ==
1397 22:17:19.338933 RX Vref Scan: 0
1398 22:17:19.339037
1399 22:17:19.339128 RX Vref 0 -> 0, step: 1
1400 22:17:19.342312
1401 22:17:19.342416 RX Delay -95 -> 252, step: 8
1402 22:17:19.349342 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1403 22:17:19.352680 iDelay=209, Bit 1, Center 92 (-15 ~ 200) 216
1404 22:17:19.356039 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1405 22:17:19.359387 iDelay=209, Bit 3, Center 84 (-23 ~ 192) 216
1406 22:17:19.362708 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
1407 22:17:19.369320 iDelay=209, Bit 5, Center 80 (-31 ~ 192) 224
1408 22:17:19.372961 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1409 22:17:19.375830 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1410 22:17:19.379287 iDelay=209, Bit 8, Center 72 (-31 ~ 176) 208
1411 22:17:19.382789 iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216
1412 22:17:19.389666 iDelay=209, Bit 10, Center 80 (-23 ~ 184) 208
1413 22:17:19.392652 iDelay=209, Bit 11, Center 80 (-23 ~ 184) 208
1414 22:17:19.396586 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1415 22:17:19.399502 iDelay=209, Bit 13, Center 84 (-23 ~ 192) 216
1416 22:17:19.402917 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1417 22:17:19.409385 iDelay=209, Bit 15, Center 88 (-15 ~ 192) 208
1418 22:17:19.409493 ==
1419 22:17:19.412629 Dram Type= 6, Freq= 0, CH_0, rank 1
1420 22:17:19.415718 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1421 22:17:19.415824 ==
1422 22:17:19.415917 DQS Delay:
1423 22:17:19.418966 DQS0 = 0, DQS1 = 0
1424 22:17:19.419068 DQM Delay:
1425 22:17:19.422305 DQM0 = 90, DQM1 = 81
1426 22:17:19.422407 DQ Delay:
1427 22:17:19.425607 DQ0 =88, DQ1 =92, DQ2 =88, DQ3 =84
1428 22:17:19.429047 DQ4 =92, DQ5 =80, DQ6 =100, DQ7 =100
1429 22:17:19.432573 DQ8 =72, DQ9 =68, DQ10 =80, DQ11 =80
1430 22:17:19.435701 DQ12 =84, DQ13 =84, DQ14 =92, DQ15 =88
1431 22:17:19.435804
1432 22:17:19.435892
1433 22:17:19.445818 [DQSOSCAuto] RK1, (LSB)MR18= 0x3d18, (MSB)MR19= 0x606, tDQSOscB0 = 403 ps tDQSOscB1 = 394 ps
1434 22:17:19.445927 CH0 RK1: MR19=606, MR18=3D18
1435 22:17:19.452336 CH0_RK1: MR19=0x606, MR18=0x3D18, DQSOSC=394, MR23=63, INC=95, DEC=63
1436 22:17:19.455997 [RxdqsGatingPostProcess] freq 800
1437 22:17:19.462368 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1438 22:17:19.465475 Pre-setting of DQS Precalculation
1439 22:17:19.468750 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1440 22:17:19.468904 ==
1441 22:17:19.472150 Dram Type= 6, Freq= 0, CH_1, rank 0
1442 22:17:19.478725 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1443 22:17:19.478878 ==
1444 22:17:19.482445 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1445 22:17:19.488653 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1446 22:17:19.498360 [CA 0] Center 36 (6~67) winsize 62
1447 22:17:19.501451 [CA 1] Center 36 (6~67) winsize 62
1448 22:17:19.504594 [CA 2] Center 35 (5~65) winsize 61
1449 22:17:19.507934 [CA 3] Center 34 (4~65) winsize 62
1450 22:17:19.510935 [CA 4] Center 34 (4~65) winsize 62
1451 22:17:19.514649 [CA 5] Center 33 (3~64) winsize 62
1452 22:17:19.514782
1453 22:17:19.517779 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1454 22:17:19.517907
1455 22:17:19.521353 [CATrainingPosCal] consider 1 rank data
1456 22:17:19.524646 u2DelayCellTimex100 = 270/100 ps
1457 22:17:19.527625 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1458 22:17:19.534308 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1459 22:17:19.537821 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
1460 22:17:19.540870 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1461 22:17:19.544179 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1462 22:17:19.547642 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1463 22:17:19.547730
1464 22:17:19.551302 CA PerBit enable=1, Macro0, CA PI delay=33
1465 22:17:19.551390
1466 22:17:19.554204 [CBTSetCACLKResult] CA Dly = 33
1467 22:17:19.554291 CS Dly: 4 (0~35)
1468 22:17:19.557733 ==
1469 22:17:19.561033 Dram Type= 6, Freq= 0, CH_1, rank 1
1470 22:17:19.564244 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1471 22:17:19.564331 ==
1472 22:17:19.567517 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1473 22:17:19.574085 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1474 22:17:19.584208 [CA 0] Center 37 (7~67) winsize 61
1475 22:17:19.587224 [CA 1] Center 36 (6~67) winsize 62
1476 22:17:19.590658 [CA 2] Center 35 (5~66) winsize 62
1477 22:17:19.593860 [CA 3] Center 34 (4~65) winsize 62
1478 22:17:19.597319 [CA 4] Center 34 (4~65) winsize 62
1479 22:17:19.600739 [CA 5] Center 34 (4~64) winsize 61
1480 22:17:19.600850
1481 22:17:19.603996 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1482 22:17:19.604082
1483 22:17:19.607362 [CATrainingPosCal] consider 2 rank data
1484 22:17:19.610590 u2DelayCellTimex100 = 270/100 ps
1485 22:17:19.613834 CA0 delay=37 (7~67),Diff = 3 PI (21 cell)
1486 22:17:19.620607 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1487 22:17:19.623905 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1488 22:17:19.627652 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1489 22:17:19.631236 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1490 22:17:19.635260 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1491 22:17:19.635354
1492 22:17:19.638720 CA PerBit enable=1, Macro0, CA PI delay=34
1493 22:17:19.638816
1494 22:17:19.642576 [CBTSetCACLKResult] CA Dly = 34
1495 22:17:19.642688 CS Dly: 5 (0~38)
1496 22:17:19.642771
1497 22:17:19.646236 ----->DramcWriteLeveling(PI) begin...
1498 22:17:19.646348 ==
1499 22:17:19.650045 Dram Type= 6, Freq= 0, CH_1, rank 0
1500 22:17:19.653364 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1501 22:17:19.653488 ==
1502 22:17:19.657282 Write leveling (Byte 0): 25 => 25
1503 22:17:19.660900 Write leveling (Byte 1): 29 => 29
1504 22:17:19.661008 DramcWriteLeveling(PI) end<-----
1505 22:17:19.664664
1506 22:17:19.664790 ==
1507 22:17:19.667649 Dram Type= 6, Freq= 0, CH_1, rank 0
1508 22:17:19.670988 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1509 22:17:19.671107 ==
1510 22:17:19.674242 [Gating] SW mode calibration
1511 22:17:19.681136 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1512 22:17:19.684398 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1513 22:17:19.691154 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1514 22:17:19.694223 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1515 22:17:19.697700 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1516 22:17:19.704232 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1517 22:17:19.709518 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1518 22:17:19.711053 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1519 22:17:19.717903 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1520 22:17:19.721105 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1521 22:17:19.724152 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1522 22:17:19.730728 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 22:17:19.734344 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 22:17:19.737592 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 22:17:19.744207 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 22:17:19.747195 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 22:17:19.750589 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 22:17:19.757215 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 22:17:19.760924 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1530 22:17:19.763990 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 22:17:19.770627 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1532 22:17:19.773724 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 22:17:19.777458 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1534 22:17:19.783857 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1535 22:17:19.787421 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1536 22:17:19.790454 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1537 22:17:19.794124 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1538 22:17:19.800286 0 9 4 | B1->B0 | 2323 2323 | 0 1 | (0 0) (1 1)
1539 22:17:19.803816 0 9 8 | B1->B0 | 3434 3434 | 0 0 | (0 0) (0 0)
1540 22:17:19.806969 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1541 22:17:19.813417 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1542 22:17:19.816955 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1543 22:17:19.820113 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1544 22:17:19.826661 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1545 22:17:19.830330 0 10 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
1546 22:17:19.833423 0 10 4 | B1->B0 | 2f2f 3030 | 1 0 | (1 0) (1 1)
1547 22:17:19.840195 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1548 22:17:19.843366 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1549 22:17:19.846733 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1550 22:17:19.853448 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1551 22:17:19.856639 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1552 22:17:19.860120 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1553 22:17:19.866479 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1554 22:17:19.870077 0 11 4 | B1->B0 | 2f2f 3636 | 1 0 | (0 0) (0 0)
1555 22:17:19.873233 0 11 8 | B1->B0 | 4343 4343 | 0 0 | (0 0) (0 0)
1556 22:17:19.879947 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1557 22:17:19.883414 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1558 22:17:19.886384 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1559 22:17:19.893143 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1560 22:17:19.896691 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1561 22:17:19.899790 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1562 22:17:19.906457 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1563 22:17:19.909532 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1564 22:17:19.913083 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1565 22:17:19.919940 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1566 22:17:19.923018 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1567 22:17:19.926560 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1568 22:17:19.933269 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1569 22:17:19.936601 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1570 22:17:19.939735 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1571 22:17:19.943343 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1572 22:17:19.949904 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1573 22:17:19.953305 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1574 22:17:19.956664 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1575 22:17:19.962986 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1576 22:17:19.966522 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1577 22:17:19.970086 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1578 22:17:19.976667 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1579 22:17:19.979715 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1580 22:17:19.982921 Total UI for P1: 0, mck2ui 16
1581 22:17:19.986461 best dqsien dly found for B0: ( 0, 14, 4)
1582 22:17:19.989502 Total UI for P1: 0, mck2ui 16
1583 22:17:19.993057 best dqsien dly found for B1: ( 0, 14, 4)
1584 22:17:19.996580 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1585 22:17:19.999565 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1586 22:17:19.999650
1587 22:17:20.002769 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1588 22:17:20.006460 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1589 22:17:20.009489 [Gating] SW calibration Done
1590 22:17:20.009576 ==
1591 22:17:20.012703 Dram Type= 6, Freq= 0, CH_1, rank 0
1592 22:17:20.016233 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1593 22:17:20.019765 ==
1594 22:17:20.019855 RX Vref Scan: 0
1595 22:17:20.019921
1596 22:17:20.022936 RX Vref 0 -> 0, step: 1
1597 22:17:20.023021
1598 22:17:20.026097 RX Delay -130 -> 252, step: 16
1599 22:17:20.029594 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1600 22:17:20.032687 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1601 22:17:20.036122 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1602 22:17:20.039509 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1603 22:17:20.045856 iDelay=222, Bit 4, Center 85 (-18 ~ 189) 208
1604 22:17:20.049277 iDelay=222, Bit 5, Center 101 (-2 ~ 205) 208
1605 22:17:20.052420 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1606 22:17:20.056002 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1607 22:17:20.059206 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1608 22:17:20.066042 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1609 22:17:20.069227 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1610 22:17:20.072702 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1611 22:17:20.075808 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1612 22:17:20.082487 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1613 22:17:20.086143 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1614 22:17:20.089147 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1615 22:17:20.089235 ==
1616 22:17:20.092748 Dram Type= 6, Freq= 0, CH_1, rank 0
1617 22:17:20.095855 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1618 22:17:20.095943 ==
1619 22:17:20.099491 DQS Delay:
1620 22:17:20.099579 DQS0 = 0, DQS1 = 0
1621 22:17:20.099645 DQM Delay:
1622 22:17:20.102436 DQM0 = 91, DQM1 = 83
1623 22:17:20.102520 DQ Delay:
1624 22:17:20.105674 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93
1625 22:17:20.109057 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =93
1626 22:17:20.112563 DQ8 =69, DQ9 =77, DQ10 =85, DQ11 =77
1627 22:17:20.115697 DQ12 =93, DQ13 =93, DQ14 =85, DQ15 =85
1628 22:17:20.115786
1629 22:17:20.115853
1630 22:17:20.119050 ==
1631 22:17:20.119195 Dram Type= 6, Freq= 0, CH_1, rank 0
1632 22:17:20.125457 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1633 22:17:20.125555 ==
1634 22:17:20.125622
1635 22:17:20.125682
1636 22:17:20.128893 TX Vref Scan disable
1637 22:17:20.128981 == TX Byte 0 ==
1638 22:17:20.132040 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1639 22:17:20.138739 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1640 22:17:20.138837 == TX Byte 1 ==
1641 22:17:20.142148 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1642 22:17:20.149041 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1643 22:17:20.149160 ==
1644 22:17:20.151886 Dram Type= 6, Freq= 0, CH_1, rank 0
1645 22:17:20.155495 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1646 22:17:20.155582 ==
1647 22:17:20.168723 TX Vref=22, minBit 10, minWin=26, winSum=443
1648 22:17:20.172201 TX Vref=24, minBit 15, minWin=26, winSum=449
1649 22:17:20.175474 TX Vref=26, minBit 10, minWin=27, winSum=451
1650 22:17:20.178979 TX Vref=28, minBit 12, minWin=27, winSum=454
1651 22:17:20.182096 TX Vref=30, minBit 12, minWin=27, winSum=454
1652 22:17:20.188874 TX Vref=32, minBit 8, minWin=27, winSum=455
1653 22:17:20.191840 [TxChooseVref] Worse bit 8, Min win 27, Win sum 455, Final Vref 32
1654 22:17:20.191931
1655 22:17:20.195543 Final TX Range 1 Vref 32
1656 22:17:20.195628
1657 22:17:20.195693 ==
1658 22:17:20.198729 Dram Type= 6, Freq= 0, CH_1, rank 0
1659 22:17:20.205295 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1660 22:17:20.205394 ==
1661 22:17:20.205462
1662 22:17:20.205522
1663 22:17:20.205581 TX Vref Scan disable
1664 22:17:20.209684 == TX Byte 0 ==
1665 22:17:20.213453 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1666 22:17:20.216451 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1667 22:17:20.220053 == TX Byte 1 ==
1668 22:17:20.223155 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1669 22:17:20.226490 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1670 22:17:20.226581
1671 22:17:20.230174 [DATLAT]
1672 22:17:20.230261 Freq=800, CH1 RK0
1673 22:17:20.230329
1674 22:17:20.233462 DATLAT Default: 0xa
1675 22:17:20.233547 0, 0xFFFF, sum = 0
1676 22:17:20.236535 1, 0xFFFF, sum = 0
1677 22:17:20.236622 2, 0xFFFF, sum = 0
1678 22:17:20.239743 3, 0xFFFF, sum = 0
1679 22:17:20.239830 4, 0xFFFF, sum = 0
1680 22:17:20.243489 5, 0xFFFF, sum = 0
1681 22:17:20.243575 6, 0xFFFF, sum = 0
1682 22:17:20.246350 7, 0xFFFF, sum = 0
1683 22:17:20.246438 8, 0xFFFF, sum = 0
1684 22:17:20.249912 9, 0x0, sum = 1
1685 22:17:20.249999 10, 0x0, sum = 2
1686 22:17:20.253281 11, 0x0, sum = 3
1687 22:17:20.253369 12, 0x0, sum = 4
1688 22:17:20.256745 best_step = 10
1689 22:17:20.256865
1690 22:17:20.256932 ==
1691 22:17:20.259813 Dram Type= 6, Freq= 0, CH_1, rank 0
1692 22:17:20.263395 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1693 22:17:20.263484 ==
1694 22:17:20.263552 RX Vref Scan: 1
1695 22:17:20.266502
1696 22:17:20.266586 Set Vref Range= 32 -> 127
1697 22:17:20.266653
1698 22:17:20.269924 RX Vref 32 -> 127, step: 1
1699 22:17:20.270047
1700 22:17:20.273114 RX Delay -95 -> 252, step: 8
1701 22:17:20.273200
1702 22:17:20.276564 Set Vref, RX VrefLevel [Byte0]: 32
1703 22:17:20.279586 [Byte1]: 32
1704 22:17:20.279672
1705 22:17:20.283264 Set Vref, RX VrefLevel [Byte0]: 33
1706 22:17:20.286730 [Byte1]: 33
1707 22:17:20.286816
1708 22:17:20.289852 Set Vref, RX VrefLevel [Byte0]: 34
1709 22:17:20.292863 [Byte1]: 34
1710 22:17:20.297044
1711 22:17:20.297136 Set Vref, RX VrefLevel [Byte0]: 35
1712 22:17:20.300539 [Byte1]: 35
1713 22:17:20.304727
1714 22:17:20.304843 Set Vref, RX VrefLevel [Byte0]: 36
1715 22:17:20.308006 [Byte1]: 36
1716 22:17:20.312511
1717 22:17:20.312597 Set Vref, RX VrefLevel [Byte0]: 37
1718 22:17:20.315672 [Byte1]: 37
1719 22:17:20.320088
1720 22:17:20.320180 Set Vref, RX VrefLevel [Byte0]: 38
1721 22:17:20.323383 [Byte1]: 38
1722 22:17:20.327401
1723 22:17:20.327490 Set Vref, RX VrefLevel [Byte0]: 39
1724 22:17:20.330600 [Byte1]: 39
1725 22:17:20.334969
1726 22:17:20.335059 Set Vref, RX VrefLevel [Byte0]: 40
1727 22:17:20.338237 [Byte1]: 40
1728 22:17:20.342813
1729 22:17:20.342904 Set Vref, RX VrefLevel [Byte0]: 41
1730 22:17:20.345966 [Byte1]: 41
1731 22:17:20.350152
1732 22:17:20.350241 Set Vref, RX VrefLevel [Byte0]: 42
1733 22:17:20.353531 [Byte1]: 42
1734 22:17:20.357939
1735 22:17:20.358031 Set Vref, RX VrefLevel [Byte0]: 43
1736 22:17:20.361139 [Byte1]: 43
1737 22:17:20.365467
1738 22:17:20.365555 Set Vref, RX VrefLevel [Byte0]: 44
1739 22:17:20.369044 [Byte1]: 44
1740 22:17:20.373250
1741 22:17:20.373345 Set Vref, RX VrefLevel [Byte0]: 45
1742 22:17:20.376383 [Byte1]: 45
1743 22:17:20.381110
1744 22:17:20.381264 Set Vref, RX VrefLevel [Byte0]: 46
1745 22:17:20.383891 [Byte1]: 46
1746 22:17:20.388373
1747 22:17:20.388464 Set Vref, RX VrefLevel [Byte0]: 47
1748 22:17:20.391532 [Byte1]: 47
1749 22:17:20.395877
1750 22:17:20.395966 Set Vref, RX VrefLevel [Byte0]: 48
1751 22:17:20.399402 [Byte1]: 48
1752 22:17:20.403577
1753 22:17:20.403667 Set Vref, RX VrefLevel [Byte0]: 49
1754 22:17:20.406775 [Byte1]: 49
1755 22:17:20.411003
1756 22:17:20.411095 Set Vref, RX VrefLevel [Byte0]: 50
1757 22:17:20.414627 [Byte1]: 50
1758 22:17:20.418578
1759 22:17:20.418670 Set Vref, RX VrefLevel [Byte0]: 51
1760 22:17:20.422104 [Byte1]: 51
1761 22:17:20.426486
1762 22:17:20.426581 Set Vref, RX VrefLevel [Byte0]: 52
1763 22:17:20.429441 [Byte1]: 52
1764 22:17:20.433777
1765 22:17:20.433914 Set Vref, RX VrefLevel [Byte0]: 53
1766 22:17:20.437109 [Byte1]: 53
1767 22:17:20.441337
1768 22:17:20.441427 Set Vref, RX VrefLevel [Byte0]: 54
1769 22:17:20.444747 [Byte1]: 54
1770 22:17:20.448811
1771 22:17:20.448902 Set Vref, RX VrefLevel [Byte0]: 55
1772 22:17:20.452479 [Byte1]: 55
1773 22:17:20.456728
1774 22:17:20.456838 Set Vref, RX VrefLevel [Byte0]: 56
1775 22:17:20.459710 [Byte1]: 56
1776 22:17:20.464169
1777 22:17:20.464260 Set Vref, RX VrefLevel [Byte0]: 57
1778 22:17:20.467608 [Byte1]: 57
1779 22:17:20.471844
1780 22:17:20.471970 Set Vref, RX VrefLevel [Byte0]: 58
1781 22:17:20.475278 [Byte1]: 58
1782 22:17:20.479652
1783 22:17:20.479746 Set Vref, RX VrefLevel [Byte0]: 59
1784 22:17:20.482854 [Byte1]: 59
1785 22:17:20.487251
1786 22:17:20.487363 Set Vref, RX VrefLevel [Byte0]: 60
1787 22:17:20.490401 [Byte1]: 60
1788 22:17:20.494486
1789 22:17:20.494575 Set Vref, RX VrefLevel [Byte0]: 61
1790 22:17:20.497876 [Byte1]: 61
1791 22:17:20.502487
1792 22:17:20.502574 Set Vref, RX VrefLevel [Byte0]: 62
1793 22:17:20.505570 [Byte1]: 62
1794 22:17:20.510131
1795 22:17:20.510221 Set Vref, RX VrefLevel [Byte0]: 63
1796 22:17:20.513055 [Byte1]: 63
1797 22:17:20.517517
1798 22:17:20.517608 Set Vref, RX VrefLevel [Byte0]: 64
1799 22:17:20.520558 [Byte1]: 64
1800 22:17:20.525092
1801 22:17:20.525181 Set Vref, RX VrefLevel [Byte0]: 65
1802 22:17:20.528690 [Byte1]: 65
1803 22:17:20.532520
1804 22:17:20.532651 Set Vref, RX VrefLevel [Byte0]: 66
1805 22:17:20.536098 [Byte1]: 66
1806 22:17:20.540034
1807 22:17:20.540148 Set Vref, RX VrefLevel [Byte0]: 67
1808 22:17:20.543420 [Byte1]: 67
1809 22:17:20.547678
1810 22:17:20.547768 Set Vref, RX VrefLevel [Byte0]: 68
1811 22:17:20.550985 [Byte1]: 68
1812 22:17:20.555525
1813 22:17:20.555621 Set Vref, RX VrefLevel [Byte0]: 69
1814 22:17:20.558822 [Byte1]: 69
1815 22:17:20.563039
1816 22:17:20.563130 Set Vref, RX VrefLevel [Byte0]: 70
1817 22:17:20.566296 [Byte1]: 70
1818 22:17:20.570534
1819 22:17:20.570639 Set Vref, RX VrefLevel [Byte0]: 71
1820 22:17:20.574014 [Byte1]: 71
1821 22:17:20.578360
1822 22:17:20.578451 Set Vref, RX VrefLevel [Byte0]: 72
1823 22:17:20.581587 [Byte1]: 72
1824 22:17:20.585688
1825 22:17:20.585782 Set Vref, RX VrefLevel [Byte0]: 73
1826 22:17:20.589371 [Byte1]: 73
1827 22:17:20.593450
1828 22:17:20.593539 Set Vref, RX VrefLevel [Byte0]: 74
1829 22:17:20.596881 [Byte1]: 74
1830 22:17:20.600879
1831 22:17:20.600968 Set Vref, RX VrefLevel [Byte0]: 75
1832 22:17:20.604573 [Byte1]: 75
1833 22:17:20.608613
1834 22:17:20.611655 Final RX Vref Byte 0 = 49 to rank0
1835 22:17:20.611765 Final RX Vref Byte 1 = 63 to rank0
1836 22:17:20.615194 Final RX Vref Byte 0 = 49 to rank1
1837 22:17:20.618308 Final RX Vref Byte 1 = 63 to rank1==
1838 22:17:20.621734 Dram Type= 6, Freq= 0, CH_1, rank 0
1839 22:17:20.628389 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1840 22:17:20.628495 ==
1841 22:17:20.628564 DQS Delay:
1842 22:17:20.628626 DQS0 = 0, DQS1 = 0
1843 22:17:20.631659 DQM Delay:
1844 22:17:20.631744 DQM0 = 92, DQM1 = 84
1845 22:17:20.635106 DQ Delay:
1846 22:17:20.638727 DQ0 =96, DQ1 =84, DQ2 =80, DQ3 =88
1847 22:17:20.641831 DQ4 =92, DQ5 =108, DQ6 =104, DQ7 =88
1848 22:17:20.645017 DQ8 =72, DQ9 =72, DQ10 =88, DQ11 =80
1849 22:17:20.648562 DQ12 =96, DQ13 =88, DQ14 =88, DQ15 =88
1850 22:17:20.648654
1851 22:17:20.648720
1852 22:17:20.654982 [DQSOSCAuto] RK0, (LSB)MR18= 0x2f4c, (MSB)MR19= 0x606, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps
1853 22:17:20.658562 CH1 RK0: MR19=606, MR18=2F4C
1854 22:17:20.664821 CH1_RK0: MR19=0x606, MR18=0x2F4C, DQSOSC=390, MR23=63, INC=97, DEC=64
1855 22:17:20.664926
1856 22:17:20.668106 ----->DramcWriteLeveling(PI) begin...
1857 22:17:20.668196 ==
1858 22:17:20.671591 Dram Type= 6, Freq= 0, CH_1, rank 1
1859 22:17:20.674722 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1860 22:17:20.674814 ==
1861 22:17:20.678286 Write leveling (Byte 0): 24 => 24
1862 22:17:20.681455 Write leveling (Byte 1): 30 => 30
1863 22:17:20.684618 DramcWriteLeveling(PI) end<-----
1864 22:17:20.684705
1865 22:17:20.684797 ==
1866 22:17:20.688146 Dram Type= 6, Freq= 0, CH_1, rank 1
1867 22:17:20.691341 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1868 22:17:20.691428 ==
1869 22:17:20.694811 [Gating] SW mode calibration
1870 22:17:20.701392 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1871 22:17:20.707782 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1872 22:17:20.711282 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1873 22:17:20.717991 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1874 22:17:20.721382 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1875 22:17:20.724452 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1876 22:17:20.731111 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1877 22:17:20.734538 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1878 22:17:20.737640 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1879 22:17:20.744489 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1880 22:17:20.747648 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1881 22:17:20.751142 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 22:17:20.757552 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 22:17:20.761184 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1884 22:17:20.764142 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1885 22:17:20.767563 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1886 22:17:20.773925 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1887 22:17:20.777586 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1888 22:17:20.781077 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1889 22:17:20.787359 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 1)
1890 22:17:20.790779 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1891 22:17:20.793867 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1892 22:17:20.800729 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1893 22:17:20.804163 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1894 22:17:20.807270 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1895 22:17:20.813811 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1896 22:17:20.817341 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1897 22:17:20.820346 0 9 4 | B1->B0 | 2323 2424 | 1 0 | (1 1) (0 0)
1898 22:17:20.827104 0 9 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (0 0)
1899 22:17:20.830349 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1900 22:17:20.833958 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1901 22:17:20.840161 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1902 22:17:20.843346 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1903 22:17:20.846768 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1904 22:17:20.853285 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1905 22:17:20.856670 0 10 4 | B1->B0 | 2e2e 3030 | 0 0 | (1 1) (0 1)
1906 22:17:20.860150 0 10 8 | B1->B0 | 2323 2828 | 0 1 | (0 0) (1 0)
1907 22:17:20.866871 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1908 22:17:20.869950 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1909 22:17:20.873492 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1910 22:17:20.879685 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1911 22:17:20.883352 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1912 22:17:20.886691 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1913 22:17:20.893383 0 11 4 | B1->B0 | 2f2f 2a2a | 0 0 | (0 0) (0 0)
1914 22:17:20.896492 0 11 8 | B1->B0 | 4646 3f3f | 0 0 | (0 0) (0 0)
1915 22:17:20.899573 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1916 22:17:20.906288 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1917 22:17:20.909500 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1918 22:17:20.912991 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1919 22:17:20.919563 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1920 22:17:20.922641 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1921 22:17:20.926158 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1922 22:17:20.932799 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1923 22:17:20.936310 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1924 22:17:20.939109 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1925 22:17:20.946156 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1926 22:17:20.949301 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1927 22:17:20.952470 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1928 22:17:20.959157 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1929 22:17:20.962829 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1930 22:17:20.965755 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1931 22:17:20.972368 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1932 22:17:20.975534 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1933 22:17:20.978753 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1934 22:17:20.985353 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1935 22:17:20.988724 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1936 22:17:20.992279 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1937 22:17:20.998780 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1938 22:17:20.998887 Total UI for P1: 0, mck2ui 16
1939 22:17:21.005434 best dqsien dly found for B1: ( 0, 14, 2)
1940 22:17:21.008543 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1941 22:17:21.011993 Total UI for P1: 0, mck2ui 16
1942 22:17:21.015221 best dqsien dly found for B0: ( 0, 14, 4)
1943 22:17:21.018725 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1944 22:17:21.022090 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1945 22:17:21.022180
1946 22:17:21.025128 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1947 22:17:21.028615 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1948 22:17:21.031856 [Gating] SW calibration Done
1949 22:17:21.031943 ==
1950 22:17:21.035193 Dram Type= 6, Freq= 0, CH_1, rank 1
1951 22:17:21.038725 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1952 22:17:21.041803 ==
1953 22:17:21.041889 RX Vref Scan: 0
1954 22:17:21.041955
1955 22:17:21.045167 RX Vref 0 -> 0, step: 1
1956 22:17:21.045250
1957 22:17:21.048383 RX Delay -130 -> 252, step: 16
1958 22:17:21.051873 iDelay=206, Bit 0, Center 101 (-2 ~ 205) 208
1959 22:17:21.054993 iDelay=206, Bit 1, Center 85 (-18 ~ 189) 208
1960 22:17:21.058549 iDelay=206, Bit 2, Center 85 (-18 ~ 189) 208
1961 22:17:21.061788 iDelay=206, Bit 3, Center 85 (-18 ~ 189) 208
1962 22:17:21.068682 iDelay=206, Bit 4, Center 85 (-18 ~ 189) 208
1963 22:17:21.071524 iDelay=206, Bit 5, Center 101 (-2 ~ 205) 208
1964 22:17:21.074937 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1965 22:17:21.078285 iDelay=206, Bit 7, Center 85 (-18 ~ 189) 208
1966 22:17:21.081754 iDelay=206, Bit 8, Center 69 (-34 ~ 173) 208
1967 22:17:21.088247 iDelay=206, Bit 9, Center 77 (-34 ~ 189) 224
1968 22:17:21.091683 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1969 22:17:21.094976 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1970 22:17:21.098293 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224
1971 22:17:21.101563 iDelay=206, Bit 13, Center 93 (-18 ~ 205) 224
1972 22:17:21.107878 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1973 22:17:21.111267 iDelay=206, Bit 15, Center 93 (-18 ~ 205) 224
1974 22:17:21.111361 ==
1975 22:17:21.114899 Dram Type= 6, Freq= 0, CH_1, rank 1
1976 22:17:21.117946 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1977 22:17:21.118034 ==
1978 22:17:21.121608 DQS Delay:
1979 22:17:21.121695 DQS0 = 0, DQS1 = 0
1980 22:17:21.121761 DQM Delay:
1981 22:17:21.125032 DQM0 = 90, DQM1 = 84
1982 22:17:21.125116 DQ Delay:
1983 22:17:21.128009 DQ0 =101, DQ1 =85, DQ2 =85, DQ3 =85
1984 22:17:21.131466 DQ4 =85, DQ5 =101, DQ6 =93, DQ7 =85
1985 22:17:21.134646 DQ8 =69, DQ9 =77, DQ10 =85, DQ11 =77
1986 22:17:21.137736 DQ12 =93, DQ13 =93, DQ14 =85, DQ15 =93
1987 22:17:21.137821
1988 22:17:21.137887
1989 22:17:21.137946 ==
1990 22:17:21.141129 Dram Type= 6, Freq= 0, CH_1, rank 1
1991 22:17:21.147930 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1992 22:17:21.148033 ==
1993 22:17:21.148100
1994 22:17:21.148160
1995 22:17:21.148218 TX Vref Scan disable
1996 22:17:21.151886 == TX Byte 0 ==
1997 22:17:21.154982 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1998 22:17:21.161741 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1999 22:17:21.161849 == TX Byte 1 ==
2000 22:17:21.164985 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
2001 22:17:21.171398 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
2002 22:17:21.171507 ==
2003 22:17:21.174824 Dram Type= 6, Freq= 0, CH_1, rank 1
2004 22:17:21.178191 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2005 22:17:21.178282 ==
2006 22:17:21.191564 TX Vref=22, minBit 13, minWin=26, winSum=446
2007 22:17:21.194576 TX Vref=24, minBit 8, minWin=27, winSum=449
2008 22:17:21.198139 TX Vref=26, minBit 13, minWin=27, winSum=454
2009 22:17:21.201493 TX Vref=28, minBit 9, minWin=27, winSum=455
2010 22:17:21.204543 TX Vref=30, minBit 8, minWin=28, winSum=460
2011 22:17:21.211296 TX Vref=32, minBit 14, minWin=27, winSum=457
2012 22:17:21.214639 [TxChooseVref] Worse bit 8, Min win 28, Win sum 460, Final Vref 30
2013 22:17:21.214733
2014 22:17:21.217772 Final TX Range 1 Vref 30
2015 22:17:21.217856
2016 22:17:21.217920 ==
2017 22:17:21.221274 Dram Type= 6, Freq= 0, CH_1, rank 1
2018 22:17:21.224693 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2019 22:17:21.224829 ==
2020 22:17:21.227856
2021 22:17:21.227939
2022 22:17:21.228003 TX Vref Scan disable
2023 22:17:21.231431 == TX Byte 0 ==
2024 22:17:21.234905 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
2025 22:17:21.241343 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
2026 22:17:21.241435 == TX Byte 1 ==
2027 22:17:21.245006 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
2028 22:17:21.248045 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
2029 22:17:21.251533
2030 22:17:21.251619 [DATLAT]
2031 22:17:21.251683 Freq=800, CH1 RK1
2032 22:17:21.251743
2033 22:17:21.254743 DATLAT Default: 0xa
2034 22:17:21.254826 0, 0xFFFF, sum = 0
2035 22:17:21.257966 1, 0xFFFF, sum = 0
2036 22:17:21.258050 2, 0xFFFF, sum = 0
2037 22:17:21.261525 3, 0xFFFF, sum = 0
2038 22:17:21.264819 4, 0xFFFF, sum = 0
2039 22:17:21.264918 5, 0xFFFF, sum = 0
2040 22:17:21.267816 6, 0xFFFF, sum = 0
2041 22:17:21.267900 7, 0xFFFF, sum = 0
2042 22:17:21.271470 8, 0xFFFF, sum = 0
2043 22:17:21.271554 9, 0x0, sum = 1
2044 22:17:21.274692 10, 0x0, sum = 2
2045 22:17:21.274777 11, 0x0, sum = 3
2046 22:17:21.274843 12, 0x0, sum = 4
2047 22:17:21.278159 best_step = 10
2048 22:17:21.278241
2049 22:17:21.278306 ==
2050 22:17:21.281300 Dram Type= 6, Freq= 0, CH_1, rank 1
2051 22:17:21.284628 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2052 22:17:21.284761 ==
2053 22:17:21.288053 RX Vref Scan: 0
2054 22:17:21.288180
2055 22:17:21.288244 RX Vref 0 -> 0, step: 1
2056 22:17:21.288304
2057 22:17:21.291410 RX Delay -79 -> 252, step: 8
2058 22:17:21.298218 iDelay=209, Bit 0, Center 96 (1 ~ 192) 192
2059 22:17:21.301450 iDelay=209, Bit 1, Center 84 (-15 ~ 184) 200
2060 22:17:21.304969 iDelay=209, Bit 2, Center 84 (-15 ~ 184) 200
2061 22:17:21.308057 iDelay=209, Bit 3, Center 88 (-15 ~ 192) 208
2062 22:17:21.311267 iDelay=209, Bit 4, Center 92 (-7 ~ 192) 200
2063 22:17:21.318078 iDelay=209, Bit 5, Center 100 (-7 ~ 208) 216
2064 22:17:21.321756 iDelay=209, Bit 6, Center 96 (-7 ~ 200) 208
2065 22:17:21.324745 iDelay=209, Bit 7, Center 88 (-15 ~ 192) 208
2066 22:17:21.328368 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
2067 22:17:21.331450 iDelay=209, Bit 9, Center 76 (-31 ~ 184) 216
2068 22:17:21.338035 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
2069 22:17:21.341241 iDelay=209, Bit 11, Center 80 (-31 ~ 192) 224
2070 22:17:21.344745 iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216
2071 22:17:21.348174 iDelay=209, Bit 13, Center 92 (-15 ~ 200) 216
2072 22:17:21.351259 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
2073 22:17:21.357946 iDelay=209, Bit 15, Center 96 (-15 ~ 208) 224
2074 22:17:21.358047 ==
2075 22:17:21.361252 Dram Type= 6, Freq= 0, CH_1, rank 1
2076 22:17:21.364663 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2077 22:17:21.364799 ==
2078 22:17:21.364881 DQS Delay:
2079 22:17:21.368171 DQS0 = 0, DQS1 = 0
2080 22:17:21.368256 DQM Delay:
2081 22:17:21.371175 DQM0 = 91, DQM1 = 84
2082 22:17:21.371259 DQ Delay:
2083 22:17:21.374837 DQ0 =96, DQ1 =84, DQ2 =84, DQ3 =88
2084 22:17:21.378021 DQ4 =92, DQ5 =100, DQ6 =96, DQ7 =88
2085 22:17:21.381492 DQ8 =68, DQ9 =76, DQ10 =84, DQ11 =80
2086 22:17:21.384594 DQ12 =92, DQ13 =92, DQ14 =88, DQ15 =96
2087 22:17:21.384707
2088 22:17:21.384849
2089 22:17:21.391276 [DQSOSCAuto] RK1, (LSB)MR18= 0x3a0f, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 395 ps
2090 22:17:21.394710 CH1 RK1: MR19=606, MR18=3A0F
2091 22:17:21.401190 CH1_RK1: MR19=0x606, MR18=0x3A0F, DQSOSC=395, MR23=63, INC=94, DEC=63
2092 22:17:21.404679 [RxdqsGatingPostProcess] freq 800
2093 22:17:21.410984 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2094 22:17:21.414435 Pre-setting of DQS Precalculation
2095 22:17:21.418007 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2096 22:17:21.424375 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2097 22:17:21.430986 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2098 22:17:21.431096
2099 22:17:21.434254
2100 22:17:21.434338 [Calibration Summary] 1600 Mbps
2101 22:17:21.437748 CH 0, Rank 0
2102 22:17:21.437831 SW Impedance : PASS
2103 22:17:21.440939 DUTY Scan : NO K
2104 22:17:21.444866 ZQ Calibration : PASS
2105 22:17:21.444951 Jitter Meter : NO K
2106 22:17:21.447386 CBT Training : PASS
2107 22:17:21.451135 Write leveling : PASS
2108 22:17:21.451272 RX DQS gating : PASS
2109 22:17:21.454004 RX DQ/DQS(RDDQC) : PASS
2110 22:17:21.457426 TX DQ/DQS : PASS
2111 22:17:21.457512 RX DATLAT : PASS
2112 22:17:21.460955 RX DQ/DQS(Engine): PASS
2113 22:17:21.464057 TX OE : NO K
2114 22:17:21.464142 All Pass.
2115 22:17:21.464207
2116 22:17:21.464266 CH 0, Rank 1
2117 22:17:21.467694 SW Impedance : PASS
2118 22:17:21.470734 DUTY Scan : NO K
2119 22:17:21.470822 ZQ Calibration : PASS
2120 22:17:21.474130 Jitter Meter : NO K
2121 22:17:21.477492 CBT Training : PASS
2122 22:17:21.477584 Write leveling : PASS
2123 22:17:21.480803 RX DQS gating : PASS
2124 22:17:21.480904 RX DQ/DQS(RDDQC) : PASS
2125 22:17:21.483978 TX DQ/DQS : PASS
2126 22:17:21.487166 RX DATLAT : PASS
2127 22:17:21.487255 RX DQ/DQS(Engine): PASS
2128 22:17:21.490392 TX OE : NO K
2129 22:17:21.490478 All Pass.
2130 22:17:21.490562
2131 22:17:21.494140 CH 1, Rank 0
2132 22:17:21.494225 SW Impedance : PASS
2133 22:17:21.497269 DUTY Scan : NO K
2134 22:17:21.500596 ZQ Calibration : PASS
2135 22:17:21.500681 Jitter Meter : NO K
2136 22:17:21.503955 CBT Training : PASS
2137 22:17:21.507190 Write leveling : PASS
2138 22:17:21.507277 RX DQS gating : PASS
2139 22:17:21.510574 RX DQ/DQS(RDDQC) : PASS
2140 22:17:21.513721 TX DQ/DQS : PASS
2141 22:17:21.513816 RX DATLAT : PASS
2142 22:17:21.517284 RX DQ/DQS(Engine): PASS
2143 22:17:21.520308 TX OE : NO K
2144 22:17:21.520398 All Pass.
2145 22:17:21.520482
2146 22:17:21.520577 CH 1, Rank 1
2147 22:17:21.523691 SW Impedance : PASS
2148 22:17:21.527248 DUTY Scan : NO K
2149 22:17:21.527335 ZQ Calibration : PASS
2150 22:17:21.530253 Jitter Meter : NO K
2151 22:17:21.534099 CBT Training : PASS
2152 22:17:21.534191 Write leveling : PASS
2153 22:17:21.537156 RX DQS gating : PASS
2154 22:17:21.537243 RX DQ/DQS(RDDQC) : PASS
2155 22:17:21.540355 TX DQ/DQS : PASS
2156 22:17:21.543458 RX DATLAT : PASS
2157 22:17:21.543544 RX DQ/DQS(Engine): PASS
2158 22:17:21.546971 TX OE : NO K
2159 22:17:21.547057 All Pass.
2160 22:17:21.547140
2161 22:17:21.550518 DramC Write-DBI off
2162 22:17:21.553739 PER_BANK_REFRESH: Hybrid Mode
2163 22:17:21.553824 TX_TRACKING: ON
2164 22:17:21.556725 [GetDramInforAfterCalByMRR] Vendor 6.
2165 22:17:21.560171 [GetDramInforAfterCalByMRR] Revision 606.
2166 22:17:21.563727 [GetDramInforAfterCalByMRR] Revision 2 0.
2167 22:17:21.567273 MR0 0x3b3b
2168 22:17:21.567363 MR8 0x5151
2169 22:17:21.570232 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2170 22:17:21.570318
2171 22:17:21.573670 MR0 0x3b3b
2172 22:17:21.573756 MR8 0x5151
2173 22:17:21.576819 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2174 22:17:21.576924
2175 22:17:21.586920 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2176 22:17:21.590423 [FAST_K] Save calibration result to emmc
2177 22:17:21.593593 [FAST_K] Save calibration result to emmc
2178 22:17:21.596932 dram_init: config_dvfs: 1
2179 22:17:21.600295 dramc_set_vcore_voltage set vcore to 662500
2180 22:17:21.600384 Read voltage for 1200, 2
2181 22:17:21.603416 Vio18 = 0
2182 22:17:21.603504 Vcore = 662500
2183 22:17:21.603588 Vdram = 0
2184 22:17:21.606983 Vddq = 0
2185 22:17:21.607070 Vmddr = 0
2186 22:17:21.610266 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2187 22:17:21.617077 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2188 22:17:21.620132 MEM_TYPE=3, freq_sel=15
2189 22:17:21.623598 sv_algorithm_assistance_LP4_1600
2190 22:17:21.626632 ============ PULL DRAM RESETB DOWN ============
2191 22:17:21.630354 ========== PULL DRAM RESETB DOWN end =========
2192 22:17:21.636572 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2193 22:17:21.640037 ===================================
2194 22:17:21.640165 LPDDR4 DRAM CONFIGURATION
2195 22:17:21.643412 ===================================
2196 22:17:21.646681 EX_ROW_EN[0] = 0x0
2197 22:17:21.646795 EX_ROW_EN[1] = 0x0
2198 22:17:21.649929 LP4Y_EN = 0x0
2199 22:17:21.650022 WORK_FSP = 0x0
2200 22:17:21.653417 WL = 0x4
2201 22:17:21.653505 RL = 0x4
2202 22:17:21.656602 BL = 0x2
2203 22:17:21.659987 RPST = 0x0
2204 22:17:21.660078 RD_PRE = 0x0
2205 22:17:21.663167 WR_PRE = 0x1
2206 22:17:21.663255 WR_PST = 0x0
2207 22:17:21.666708 DBI_WR = 0x0
2208 22:17:21.666797 DBI_RD = 0x0
2209 22:17:21.669783 OTF = 0x1
2210 22:17:21.673250 ===================================
2211 22:17:21.676725 ===================================
2212 22:17:21.676855 ANA top config
2213 22:17:21.680048 ===================================
2214 22:17:21.683207 DLL_ASYNC_EN = 0
2215 22:17:21.686863 ALL_SLAVE_EN = 0
2216 22:17:21.686956 NEW_RANK_MODE = 1
2217 22:17:21.690001 DLL_IDLE_MODE = 1
2218 22:17:21.693120 LP45_APHY_COMB_EN = 1
2219 22:17:21.696714 TX_ODT_DIS = 1
2220 22:17:21.696828 NEW_8X_MODE = 1
2221 22:17:21.699802 ===================================
2222 22:17:21.702940 ===================================
2223 22:17:21.706520 data_rate = 2400
2224 22:17:21.709724 CKR = 1
2225 22:17:21.713269 DQ_P2S_RATIO = 8
2226 22:17:21.716241 ===================================
2227 22:17:21.719786 CA_P2S_RATIO = 8
2228 22:17:21.722943 DQ_CA_OPEN = 0
2229 22:17:21.723036 DQ_SEMI_OPEN = 0
2230 22:17:21.726355 CA_SEMI_OPEN = 0
2231 22:17:21.729857 CA_FULL_RATE = 0
2232 22:17:21.732810 DQ_CKDIV4_EN = 0
2233 22:17:21.736008 CA_CKDIV4_EN = 0
2234 22:17:21.739329 CA_PREDIV_EN = 0
2235 22:17:21.742735 PH8_DLY = 17
2236 22:17:21.742827 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2237 22:17:21.745891 DQ_AAMCK_DIV = 4
2238 22:17:21.749390 CA_AAMCK_DIV = 4
2239 22:17:21.753051 CA_ADMCK_DIV = 4
2240 22:17:21.756297 DQ_TRACK_CA_EN = 0
2241 22:17:21.759477 CA_PICK = 1200
2242 22:17:21.759568 CA_MCKIO = 1200
2243 22:17:21.762880 MCKIO_SEMI = 0
2244 22:17:21.765912 PLL_FREQ = 2366
2245 22:17:21.769360 DQ_UI_PI_RATIO = 32
2246 22:17:21.773024 CA_UI_PI_RATIO = 0
2247 22:17:21.775967 ===================================
2248 22:17:21.779374 ===================================
2249 22:17:21.782528 memory_type:LPDDR4
2250 22:17:21.782604 GP_NUM : 10
2251 22:17:21.785991 SRAM_EN : 1
2252 22:17:21.786066 MD32_EN : 0
2253 22:17:21.789114 ===================================
2254 22:17:21.792355 [ANA_INIT] >>>>>>>>>>>>>>
2255 22:17:21.795819 <<<<<< [CONFIGURE PHASE]: ANA_TX
2256 22:17:21.799075 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2257 22:17:21.802438 ===================================
2258 22:17:21.805577 data_rate = 2400,PCW = 0X5b00
2259 22:17:21.809091 ===================================
2260 22:17:21.812578 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2261 22:17:21.819211 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2262 22:17:21.822240 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2263 22:17:21.828868 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2264 22:17:21.832221 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2265 22:17:21.835470 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2266 22:17:21.835559 [ANA_INIT] flow start
2267 22:17:21.839060 [ANA_INIT] PLL >>>>>>>>
2268 22:17:21.842347 [ANA_INIT] PLL <<<<<<<<
2269 22:17:21.842452 [ANA_INIT] MIDPI >>>>>>>>
2270 22:17:21.845394 [ANA_INIT] MIDPI <<<<<<<<
2271 22:17:21.848905 [ANA_INIT] DLL >>>>>>>>
2272 22:17:21.849016 [ANA_INIT] DLL <<<<<<<<
2273 22:17:21.852326 [ANA_INIT] flow end
2274 22:17:21.855370 ============ LP4 DIFF to SE enter ============
2275 22:17:21.862299 ============ LP4 DIFF to SE exit ============
2276 22:17:21.862412 [ANA_INIT] <<<<<<<<<<<<<
2277 22:17:21.865436 [Flow] Enable top DCM control >>>>>
2278 22:17:21.869013 [Flow] Enable top DCM control <<<<<
2279 22:17:21.872087 Enable DLL master slave shuffle
2280 22:17:21.878996 ==============================================================
2281 22:17:21.879128 Gating Mode config
2282 22:17:21.885521 ==============================================================
2283 22:17:21.888565 Config description:
2284 22:17:21.895355 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2285 22:17:21.902051 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2286 22:17:21.908680 SELPH_MODE 0: By rank 1: By Phase
2287 22:17:21.915482 ==============================================================
2288 22:17:21.915598 GAT_TRACK_EN = 1
2289 22:17:21.918424 RX_GATING_MODE = 2
2290 22:17:21.922111 RX_GATING_TRACK_MODE = 2
2291 22:17:21.925561 SELPH_MODE = 1
2292 22:17:21.928614 PICG_EARLY_EN = 1
2293 22:17:21.931769 VALID_LAT_VALUE = 1
2294 22:17:21.938775 ==============================================================
2295 22:17:21.941731 Enter into Gating configuration >>>>
2296 22:17:21.945318 Exit from Gating configuration <<<<
2297 22:17:21.948600 Enter into DVFS_PRE_config >>>>>
2298 22:17:21.958487 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2299 22:17:21.961637 Exit from DVFS_PRE_config <<<<<
2300 22:17:21.965006 Enter into PICG configuration >>>>
2301 22:17:21.968427 Exit from PICG configuration <<<<
2302 22:17:21.971931 [RX_INPUT] configuration >>>>>
2303 22:17:21.972024 [RX_INPUT] configuration <<<<<
2304 22:17:21.978595 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2305 22:17:21.984752 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2306 22:17:21.991443 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2307 22:17:21.994984 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2308 22:17:22.001600 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2309 22:17:22.008333 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2310 22:17:22.011298 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2311 22:17:22.014906 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2312 22:17:22.021453 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2313 22:17:22.024946 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2314 22:17:22.028253 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2315 22:17:22.034694 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2316 22:17:22.037956 ===================================
2317 22:17:22.038054 LPDDR4 DRAM CONFIGURATION
2318 22:17:22.041527 ===================================
2319 22:17:22.044520 EX_ROW_EN[0] = 0x0
2320 22:17:22.048045 EX_ROW_EN[1] = 0x0
2321 22:17:22.048136 LP4Y_EN = 0x0
2322 22:17:22.051288 WORK_FSP = 0x0
2323 22:17:22.051389 WL = 0x4
2324 22:17:22.054878 RL = 0x4
2325 22:17:22.054964 BL = 0x2
2326 22:17:22.058284 RPST = 0x0
2327 22:17:22.058371 RD_PRE = 0x0
2328 22:17:22.061238 WR_PRE = 0x1
2329 22:17:22.061324 WR_PST = 0x0
2330 22:17:22.064504 DBI_WR = 0x0
2331 22:17:22.064590 DBI_RD = 0x0
2332 22:17:22.067636 OTF = 0x1
2333 22:17:22.070839 ===================================
2334 22:17:22.074293 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2335 22:17:22.077752 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2336 22:17:22.084482 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2337 22:17:22.087621 ===================================
2338 22:17:22.087732 LPDDR4 DRAM CONFIGURATION
2339 22:17:22.091130 ===================================
2340 22:17:22.094289 EX_ROW_EN[0] = 0x10
2341 22:17:22.094379 EX_ROW_EN[1] = 0x0
2342 22:17:22.097777 LP4Y_EN = 0x0
2343 22:17:22.101042 WORK_FSP = 0x0
2344 22:17:22.101131 WL = 0x4
2345 22:17:22.104066 RL = 0x4
2346 22:17:22.104155 BL = 0x2
2347 22:17:22.107386 RPST = 0x0
2348 22:17:22.107471 RD_PRE = 0x0
2349 22:17:22.110981 WR_PRE = 0x1
2350 22:17:22.111066 WR_PST = 0x0
2351 22:17:22.114115 DBI_WR = 0x0
2352 22:17:22.114201 DBI_RD = 0x0
2353 22:17:22.117634 OTF = 0x1
2354 22:17:22.120750 ===================================
2355 22:17:22.127368 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2356 22:17:22.127475 ==
2357 22:17:22.130409 Dram Type= 6, Freq= 0, CH_0, rank 0
2358 22:17:22.133695 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2359 22:17:22.133785 ==
2360 22:17:22.137264 [Duty_Offset_Calibration]
2361 22:17:22.137354 B0:2 B1:0 CA:1
2362 22:17:22.137418
2363 22:17:22.140401 [DutyScan_Calibration_Flow] k_type=0
2364 22:17:22.149829
2365 22:17:22.149950 ==CLK 0==
2366 22:17:22.153239 Final CLK duty delay cell = -4
2367 22:17:22.156278 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2368 22:17:22.159868 [-4] MIN Duty = 4875%(X100), DQS PI = 0
2369 22:17:22.163412 [-4] AVG Duty = 4953%(X100)
2370 22:17:22.163500
2371 22:17:22.166319 CH0 CLK Duty spec in!! Max-Min= 156%
2372 22:17:22.169446 [DutyScan_Calibration_Flow] ====Done====
2373 22:17:22.169537
2374 22:17:22.172816 [DutyScan_Calibration_Flow] k_type=1
2375 22:17:22.188661
2376 22:17:22.188850 ==DQS 0 ==
2377 22:17:22.192291 Final DQS duty delay cell = 0
2378 22:17:22.195257 [0] MAX Duty = 5187%(X100), DQS PI = 30
2379 22:17:22.198652 [0] MIN Duty = 4938%(X100), DQS PI = 0
2380 22:17:22.198738 [0] AVG Duty = 5062%(X100)
2381 22:17:22.202132
2382 22:17:22.202219 ==DQS 1 ==
2383 22:17:22.205281 Final DQS duty delay cell = -4
2384 22:17:22.208520 [-4] MAX Duty = 5124%(X100), DQS PI = 32
2385 22:17:22.211832 [-4] MIN Duty = 4938%(X100), DQS PI = 8
2386 22:17:22.215368 [-4] AVG Duty = 5031%(X100)
2387 22:17:22.215455
2388 22:17:22.218510 CH0 DQS 0 Duty spec in!! Max-Min= 249%
2389 22:17:22.218593
2390 22:17:22.222140 CH0 DQS 1 Duty spec in!! Max-Min= 186%
2391 22:17:22.225253 [DutyScan_Calibration_Flow] ====Done====
2392 22:17:22.225337
2393 22:17:22.228716 [DutyScan_Calibration_Flow] k_type=3
2394 22:17:22.245563
2395 22:17:22.245713 ==DQM 0 ==
2396 22:17:22.248860 Final DQM duty delay cell = 0
2397 22:17:22.252011 [0] MAX Duty = 5062%(X100), DQS PI = 24
2398 22:17:22.255785 [0] MIN Duty = 4875%(X100), DQS PI = 0
2399 22:17:22.255871 [0] AVG Duty = 4968%(X100)
2400 22:17:22.258850
2401 22:17:22.258932 ==DQM 1 ==
2402 22:17:22.261902 Final DQM duty delay cell = 0
2403 22:17:22.265580 [0] MAX Duty = 5187%(X100), DQS PI = 46
2404 22:17:22.268735 [0] MIN Duty = 5000%(X100), DQS PI = 22
2405 22:17:22.268868 [0] AVG Duty = 5093%(X100)
2406 22:17:22.272263
2407 22:17:22.275150 CH0 DQM 0 Duty spec in!! Max-Min= 187%
2408 22:17:22.275237
2409 22:17:22.278640 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2410 22:17:22.281912 [DutyScan_Calibration_Flow] ====Done====
2411 22:17:22.281999
2412 22:17:22.285296 [DutyScan_Calibration_Flow] k_type=2
2413 22:17:22.301095
2414 22:17:22.301240 ==DQ 0 ==
2415 22:17:22.304454 Final DQ duty delay cell = -4
2416 22:17:22.307617 [-4] MAX Duty = 5062%(X100), DQS PI = 34
2417 22:17:22.311023 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2418 22:17:22.314290 [-4] AVG Duty = 4984%(X100)
2419 22:17:22.314375
2420 22:17:22.314437 ==DQ 1 ==
2421 22:17:22.317592 Final DQ duty delay cell = 0
2422 22:17:22.321243 [0] MAX Duty = 4938%(X100), DQS PI = 6
2423 22:17:22.324445 [0] MIN Duty = 4907%(X100), DQS PI = 0
2424 22:17:22.324531 [0] AVG Duty = 4922%(X100)
2425 22:17:22.327958
2426 22:17:22.331157 CH0 DQ 0 Duty spec in!! Max-Min= 155%
2427 22:17:22.331251
2428 22:17:22.334264 CH0 DQ 1 Duty spec in!! Max-Min= 31%
2429 22:17:22.337714 [DutyScan_Calibration_Flow] ====Done====
2430 22:17:22.337804 ==
2431 22:17:22.340986 Dram Type= 6, Freq= 0, CH_1, rank 0
2432 22:17:22.344587 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2433 22:17:22.344670 ==
2434 22:17:22.347600 [Duty_Offset_Calibration]
2435 22:17:22.347682 B0:0 B1:-1 CA:2
2436 22:17:22.347745
2437 22:17:22.351150 [DutyScan_Calibration_Flow] k_type=0
2438 22:17:22.361372
2439 22:17:22.361486 ==CLK 0==
2440 22:17:22.364449 Final CLK duty delay cell = 0
2441 22:17:22.367784 [0] MAX Duty = 5156%(X100), DQS PI = 16
2442 22:17:22.371322 [0] MIN Duty = 4938%(X100), DQS PI = 44
2443 22:17:22.374759 [0] AVG Duty = 5047%(X100)
2444 22:17:22.374864
2445 22:17:22.377703 CH1 CLK Duty spec in!! Max-Min= 218%
2446 22:17:22.380997 [DutyScan_Calibration_Flow] ====Done====
2447 22:17:22.381086
2448 22:17:22.384318 [DutyScan_Calibration_Flow] k_type=1
2449 22:17:22.400786
2450 22:17:22.400962 ==DQS 0 ==
2451 22:17:22.404190 Final DQS duty delay cell = 0
2452 22:17:22.407372 [0] MAX Duty = 5093%(X100), DQS PI = 24
2453 22:17:22.410391 [0] MIN Duty = 4969%(X100), DQS PI = 0
2454 22:17:22.410480 [0] AVG Duty = 5031%(X100)
2455 22:17:22.414099
2456 22:17:22.414185 ==DQS 1 ==
2457 22:17:22.417060 Final DQS duty delay cell = 0
2458 22:17:22.420678 [0] MAX Duty = 5156%(X100), DQS PI = 0
2459 22:17:22.423923 [0] MIN Duty = 4875%(X100), DQS PI = 34
2460 22:17:22.424011 [0] AVG Duty = 5015%(X100)
2461 22:17:22.427332
2462 22:17:22.430486 CH1 DQS 0 Duty spec in!! Max-Min= 124%
2463 22:17:22.430573
2464 22:17:22.433940 CH1 DQS 1 Duty spec in!! Max-Min= 281%
2465 22:17:22.437090 [DutyScan_Calibration_Flow] ====Done====
2466 22:17:22.437176
2467 22:17:22.440338 [DutyScan_Calibration_Flow] k_type=3
2468 22:17:22.457036
2469 22:17:22.457187 ==DQM 0 ==
2470 22:17:22.460500 Final DQM duty delay cell = 4
2471 22:17:22.463615 [4] MAX Duty = 5093%(X100), DQS PI = 20
2472 22:17:22.466745 [4] MIN Duty = 4938%(X100), DQS PI = 46
2473 22:17:22.470352 [4] AVG Duty = 5015%(X100)
2474 22:17:22.470492
2475 22:17:22.470587 ==DQM 1 ==
2476 22:17:22.473680 Final DQM duty delay cell = -4
2477 22:17:22.476928 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2478 22:17:22.480026 [-4] MIN Duty = 4751%(X100), DQS PI = 36
2479 22:17:22.483543 [-4] AVG Duty = 4875%(X100)
2480 22:17:22.483632
2481 22:17:22.486964 CH1 DQM 0 Duty spec in!! Max-Min= 155%
2482 22:17:22.487051
2483 22:17:22.490041 CH1 DQM 1 Duty spec in!! Max-Min= 249%
2484 22:17:22.493623 [DutyScan_Calibration_Flow] ====Done====
2485 22:17:22.493716
2486 22:17:22.496886 [DutyScan_Calibration_Flow] k_type=2
2487 22:17:22.513960
2488 22:17:22.514107 ==DQ 0 ==
2489 22:17:22.517407 Final DQ duty delay cell = 0
2490 22:17:22.520391 [0] MAX Duty = 5062%(X100), DQS PI = 18
2491 22:17:22.524004 [0] MIN Duty = 4938%(X100), DQS PI = 44
2492 22:17:22.524097 [0] AVG Duty = 5000%(X100)
2493 22:17:22.527125
2494 22:17:22.527211 ==DQ 1 ==
2495 22:17:22.530258 Final DQ duty delay cell = 0
2496 22:17:22.533961 [0] MAX Duty = 5062%(X100), DQS PI = 4
2497 22:17:22.537006 [0] MIN Duty = 4813%(X100), DQS PI = 36
2498 22:17:22.537095 [0] AVG Duty = 4937%(X100)
2499 22:17:22.540265
2500 22:17:22.543679 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2501 22:17:22.543767
2502 22:17:22.547020 CH1 DQ 1 Duty spec in!! Max-Min= 249%
2503 22:17:22.550144 [DutyScan_Calibration_Flow] ====Done====
2504 22:17:22.553694 nWR fixed to 30
2505 22:17:22.553784 [ModeRegInit_LP4] CH0 RK0
2506 22:17:22.556742 [ModeRegInit_LP4] CH0 RK1
2507 22:17:22.560410 [ModeRegInit_LP4] CH1 RK0
2508 22:17:22.563489 [ModeRegInit_LP4] CH1 RK1
2509 22:17:22.563576 match AC timing 7
2510 22:17:22.570075 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2511 22:17:22.573499 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2512 22:17:22.576562 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2513 22:17:22.583484 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2514 22:17:22.586482 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2515 22:17:22.586630 ==
2516 22:17:22.590193 Dram Type= 6, Freq= 0, CH_0, rank 0
2517 22:17:22.593103 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2518 22:17:22.593209 ==
2519 22:17:22.599978 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2520 22:17:22.606620 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2521 22:17:22.613925 [CA 0] Center 38 (7~69) winsize 63
2522 22:17:22.616977 [CA 1] Center 38 (7~69) winsize 63
2523 22:17:22.620441 [CA 2] Center 34 (4~65) winsize 62
2524 22:17:22.623641 [CA 3] Center 34 (4~65) winsize 62
2525 22:17:22.627113 [CA 4] Center 34 (4~64) winsize 61
2526 22:17:22.630243 [CA 5] Center 32 (2~63) winsize 62
2527 22:17:22.630329
2528 22:17:22.633769 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2529 22:17:22.633857
2530 22:17:22.637405 [CATrainingPosCal] consider 1 rank data
2531 22:17:22.640345 u2DelayCellTimex100 = 270/100 ps
2532 22:17:22.643873 CA0 delay=38 (7~69),Diff = 6 PI (28 cell)
2533 22:17:22.647069 CA1 delay=38 (7~69),Diff = 6 PI (28 cell)
2534 22:17:22.653831 CA2 delay=34 (4~65),Diff = 2 PI (9 cell)
2535 22:17:22.656912 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2536 22:17:22.660419 CA4 delay=34 (4~64),Diff = 2 PI (9 cell)
2537 22:17:22.663541 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
2538 22:17:22.663627
2539 22:17:22.667247 CA PerBit enable=1, Macro0, CA PI delay=32
2540 22:17:22.667332
2541 22:17:22.670234 [CBTSetCACLKResult] CA Dly = 32
2542 22:17:22.670318 CS Dly: 6 (0~37)
2543 22:17:22.673353 ==
2544 22:17:22.676916 Dram Type= 6, Freq= 0, CH_0, rank 1
2545 22:17:22.680058 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2546 22:17:22.680148 ==
2547 22:17:22.683334 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2548 22:17:22.689850 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2549 22:17:22.699367 [CA 0] Center 38 (7~69) winsize 63
2550 22:17:22.702934 [CA 1] Center 38 (7~69) winsize 63
2551 22:17:22.706200 [CA 2] Center 35 (5~66) winsize 62
2552 22:17:22.709264 [CA 3] Center 35 (4~66) winsize 63
2553 22:17:22.712745 [CA 4] Center 34 (3~65) winsize 63
2554 22:17:22.715996 [CA 5] Center 33 (3~64) winsize 62
2555 22:17:22.716087
2556 22:17:22.719406 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2557 22:17:22.719495
2558 22:17:22.722593 [CATrainingPosCal] consider 2 rank data
2559 22:17:22.726302 u2DelayCellTimex100 = 270/100 ps
2560 22:17:22.729230 CA0 delay=38 (7~69),Diff = 5 PI (24 cell)
2561 22:17:22.735918 CA1 delay=38 (7~69),Diff = 5 PI (24 cell)
2562 22:17:22.739444 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
2563 22:17:22.742993 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
2564 22:17:22.746139 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
2565 22:17:22.749166 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2566 22:17:22.749252
2567 22:17:22.752731 CA PerBit enable=1, Macro0, CA PI delay=33
2568 22:17:22.752863
2569 22:17:22.755813 [CBTSetCACLKResult] CA Dly = 33
2570 22:17:22.755897 CS Dly: 7 (0~39)
2571 22:17:22.755961
2572 22:17:22.762391 ----->DramcWriteLeveling(PI) begin...
2573 22:17:22.762489 ==
2574 22:17:22.765827 Dram Type= 6, Freq= 0, CH_0, rank 0
2575 22:17:22.769234 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2576 22:17:22.769323 ==
2577 22:17:22.772363 Write leveling (Byte 0): 33 => 33
2578 22:17:22.776127 Write leveling (Byte 1): 31 => 31
2579 22:17:22.779062 DramcWriteLeveling(PI) end<-----
2580 22:17:22.779154
2581 22:17:22.779220 ==
2582 22:17:22.782252 Dram Type= 6, Freq= 0, CH_0, rank 0
2583 22:17:22.785670 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2584 22:17:22.785755 ==
2585 22:17:22.789382 [Gating] SW mode calibration
2586 22:17:22.795959 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2587 22:17:22.802327 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2588 22:17:22.805728 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2589 22:17:22.808853 0 15 4 | B1->B0 | 2e2e 3434 | 1 1 | (0 0) (1 1)
2590 22:17:22.815675 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2591 22:17:22.818965 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2592 22:17:22.822309 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2593 22:17:22.829093 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2594 22:17:22.832387 0 15 24 | B1->B0 | 3434 2d2d | 1 1 | (1 1) (1 0)
2595 22:17:22.835388 0 15 28 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
2596 22:17:22.838970 1 0 0 | B1->B0 | 2d2d 2323 | 0 0 | (0 1) (0 0)
2597 22:17:22.845668 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2598 22:17:22.848660 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2599 22:17:22.852253 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2600 22:17:22.858835 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2601 22:17:22.862124 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2602 22:17:22.865318 1 0 24 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
2603 22:17:22.871997 1 0 28 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
2604 22:17:22.875475 1 1 0 | B1->B0 | 2c2c 4646 | 1 0 | (1 1) (0 0)
2605 22:17:22.878635 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2606 22:17:22.885363 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2607 22:17:22.888362 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2608 22:17:22.891823 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2609 22:17:22.898549 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2610 22:17:22.902062 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2611 22:17:22.905076 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2612 22:17:22.912020 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2613 22:17:22.915367 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2614 22:17:22.918432 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2615 22:17:22.925116 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2616 22:17:22.928514 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2617 22:17:22.931598 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2618 22:17:22.938550 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2619 22:17:22.941731 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2620 22:17:22.944924 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2621 22:17:22.951605 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2622 22:17:22.955145 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2623 22:17:22.958311 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2624 22:17:22.965041 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2625 22:17:22.968443 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2626 22:17:22.971584 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2627 22:17:22.978052 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2628 22:17:22.981339 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2629 22:17:22.984752 Total UI for P1: 0, mck2ui 16
2630 22:17:22.987848 best dqsien dly found for B0: ( 1, 3, 28)
2631 22:17:22.991435 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2632 22:17:22.994837 Total UI for P1: 0, mck2ui 16
2633 22:17:22.998177 best dqsien dly found for B1: ( 1, 3, 30)
2634 22:17:23.001344 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2635 22:17:23.004467 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2636 22:17:23.004553
2637 22:17:23.007759 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2638 22:17:23.014549 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2639 22:17:23.014650 [Gating] SW calibration Done
2640 22:17:23.014717 ==
2641 22:17:23.017933 Dram Type= 6, Freq= 0, CH_0, rank 0
2642 22:17:23.024497 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2643 22:17:23.024603 ==
2644 22:17:23.024671 RX Vref Scan: 0
2645 22:17:23.024733
2646 22:17:23.027616 RX Vref 0 -> 0, step: 1
2647 22:17:23.027702
2648 22:17:23.031212 RX Delay -40 -> 252, step: 8
2649 22:17:23.034253 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
2650 22:17:23.037825 iDelay=200, Bit 1, Center 123 (56 ~ 191) 136
2651 22:17:23.041288 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2652 22:17:23.047917 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2653 22:17:23.051437 iDelay=200, Bit 4, Center 127 (56 ~ 199) 144
2654 22:17:23.054541 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2655 22:17:23.057872 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2656 22:17:23.061069 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2657 22:17:23.067675 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2658 22:17:23.070985 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
2659 22:17:23.074452 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2660 22:17:23.077882 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2661 22:17:23.080946 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2662 22:17:23.087624 iDelay=200, Bit 13, Center 111 (48 ~ 175) 128
2663 22:17:23.090934 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2664 22:17:23.094543 iDelay=200, Bit 15, Center 119 (56 ~ 183) 128
2665 22:17:23.094635 ==
2666 22:17:23.097690 Dram Type= 6, Freq= 0, CH_0, rank 0
2667 22:17:23.101088 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2668 22:17:23.101176 ==
2669 22:17:23.104138 DQS Delay:
2670 22:17:23.104223 DQS0 = 0, DQS1 = 0
2671 22:17:23.107695 DQM Delay:
2672 22:17:23.107801 DQM0 = 122, DQM1 = 110
2673 22:17:23.107868 DQ Delay:
2674 22:17:23.114227 DQ0 =123, DQ1 =123, DQ2 =119, DQ3 =119
2675 22:17:23.117405 DQ4 =127, DQ5 =115, DQ6 =127, DQ7 =127
2676 22:17:23.121035 DQ8 =99, DQ9 =99, DQ10 =107, DQ11 =107
2677 22:17:23.123948 DQ12 =115, DQ13 =111, DQ14 =123, DQ15 =119
2678 22:17:23.124040
2679 22:17:23.124175
2680 22:17:23.124264 ==
2681 22:17:23.127236 Dram Type= 6, Freq= 0, CH_0, rank 0
2682 22:17:23.130858 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2683 22:17:23.130948 ==
2684 22:17:23.131015
2685 22:17:23.131074
2686 22:17:23.134304 TX Vref Scan disable
2687 22:17:23.137219 == TX Byte 0 ==
2688 22:17:23.140589 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2689 22:17:23.143983 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2690 22:17:23.147309 == TX Byte 1 ==
2691 22:17:23.150843 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2692 22:17:23.154332 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2693 22:17:23.154423 ==
2694 22:17:23.157515 Dram Type= 6, Freq= 0, CH_0, rank 0
2695 22:17:23.160874 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2696 22:17:23.160961 ==
2697 22:17:23.173881 TX Vref=22, minBit 1, minWin=24, winSum=400
2698 22:17:23.177065 TX Vref=24, minBit 1, minWin=24, winSum=402
2699 22:17:23.180573 TX Vref=26, minBit 0, minWin=25, winSum=406
2700 22:17:23.184074 TX Vref=28, minBit 0, minWin=25, winSum=411
2701 22:17:23.187467 TX Vref=30, minBit 1, minWin=25, winSum=415
2702 22:17:23.190469 TX Vref=32, minBit 1, minWin=25, winSum=412
2703 22:17:23.197439 [TxChooseVref] Worse bit 1, Min win 25, Win sum 415, Final Vref 30
2704 22:17:23.197549
2705 22:17:23.200485 Final TX Range 1 Vref 30
2706 22:17:23.200571
2707 22:17:23.200636 ==
2708 22:17:23.203925 Dram Type= 6, Freq= 0, CH_0, rank 0
2709 22:17:23.206928 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2710 22:17:23.207017 ==
2711 22:17:23.207082
2712 22:17:23.210404
2713 22:17:23.210488 TX Vref Scan disable
2714 22:17:23.213600 == TX Byte 0 ==
2715 22:17:23.217162 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2716 22:17:23.220283 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2717 22:17:23.224029 == TX Byte 1 ==
2718 22:17:23.226990 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2719 22:17:23.230403 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2720 22:17:23.230505
2721 22:17:23.233796 [DATLAT]
2722 22:17:23.233897 Freq=1200, CH0 RK0
2723 22:17:23.233993
2724 22:17:23.237039 DATLAT Default: 0xd
2725 22:17:23.237139 0, 0xFFFF, sum = 0
2726 22:17:23.240405 1, 0xFFFF, sum = 0
2727 22:17:23.240491 2, 0xFFFF, sum = 0
2728 22:17:23.244052 3, 0xFFFF, sum = 0
2729 22:17:23.244139 4, 0xFFFF, sum = 0
2730 22:17:23.247175 5, 0xFFFF, sum = 0
2731 22:17:23.247261 6, 0xFFFF, sum = 0
2732 22:17:23.250367 7, 0xFFFF, sum = 0
2733 22:17:23.253677 8, 0xFFFF, sum = 0
2734 22:17:23.253766 9, 0xFFFF, sum = 0
2735 22:17:23.257133 10, 0xFFFF, sum = 0
2736 22:17:23.257220 11, 0xFFFF, sum = 0
2737 22:17:23.260462 12, 0x0, sum = 1
2738 22:17:23.260548 13, 0x0, sum = 2
2739 22:17:23.263704 14, 0x0, sum = 3
2740 22:17:23.263790 15, 0x0, sum = 4
2741 22:17:23.263857 best_step = 13
2742 22:17:23.263917
2743 22:17:23.267232 ==
2744 22:17:23.270246 Dram Type= 6, Freq= 0, CH_0, rank 0
2745 22:17:23.273846 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2746 22:17:23.273934 ==
2747 22:17:23.274000 RX Vref Scan: 1
2748 22:17:23.274060
2749 22:17:23.276698 Set Vref Range= 32 -> 127
2750 22:17:23.276829
2751 22:17:23.280268 RX Vref 32 -> 127, step: 1
2752 22:17:23.280355
2753 22:17:23.283813 RX Delay -13 -> 252, step: 4
2754 22:17:23.283899
2755 22:17:23.286797 Set Vref, RX VrefLevel [Byte0]: 32
2756 22:17:23.290251 [Byte1]: 32
2757 22:17:23.290340
2758 22:17:23.293224 Set Vref, RX VrefLevel [Byte0]: 33
2759 22:17:23.296688 [Byte1]: 33
2760 22:17:23.300324
2761 22:17:23.300413 Set Vref, RX VrefLevel [Byte0]: 34
2762 22:17:23.303414 [Byte1]: 34
2763 22:17:23.307757
2764 22:17:23.307848 Set Vref, RX VrefLevel [Byte0]: 35
2765 22:17:23.311221 [Byte1]: 35
2766 22:17:23.315622
2767 22:17:23.315714 Set Vref, RX VrefLevel [Byte0]: 36
2768 22:17:23.318936 [Byte1]: 36
2769 22:17:23.323880
2770 22:17:23.323975 Set Vref, RX VrefLevel [Byte0]: 37
2771 22:17:23.326888 [Byte1]: 37
2772 22:17:23.331371
2773 22:17:23.331463 Set Vref, RX VrefLevel [Byte0]: 38
2774 22:17:23.334763 [Byte1]: 38
2775 22:17:23.339217
2776 22:17:23.339337 Set Vref, RX VrefLevel [Byte0]: 39
2777 22:17:23.342889 [Byte1]: 39
2778 22:17:23.347368
2779 22:17:23.347465 Set Vref, RX VrefLevel [Byte0]: 40
2780 22:17:23.350578 [Byte1]: 40
2781 22:17:23.355193
2782 22:17:23.355288 Set Vref, RX VrefLevel [Byte0]: 41
2783 22:17:23.358484 [Byte1]: 41
2784 22:17:23.363092
2785 22:17:23.363186 Set Vref, RX VrefLevel [Byte0]: 42
2786 22:17:23.366455 [Byte1]: 42
2787 22:17:23.370798
2788 22:17:23.370892 Set Vref, RX VrefLevel [Byte0]: 43
2789 22:17:23.374365 [Byte1]: 43
2790 22:17:23.378638
2791 22:17:23.378734 Set Vref, RX VrefLevel [Byte0]: 44
2792 22:17:23.382334 [Byte1]: 44
2793 22:17:23.386697
2794 22:17:23.386789 Set Vref, RX VrefLevel [Byte0]: 45
2795 22:17:23.390166 [Byte1]: 45
2796 22:17:23.394598
2797 22:17:23.394692 Set Vref, RX VrefLevel [Byte0]: 46
2798 22:17:23.397718 [Byte1]: 46
2799 22:17:23.402690
2800 22:17:23.402781 Set Vref, RX VrefLevel [Byte0]: 47
2801 22:17:23.405874 [Byte1]: 47
2802 22:17:23.410248
2803 22:17:23.410340 Set Vref, RX VrefLevel [Byte0]: 48
2804 22:17:23.413524 [Byte1]: 48
2805 22:17:23.418358
2806 22:17:23.418452 Set Vref, RX VrefLevel [Byte0]: 49
2807 22:17:23.421402 [Byte1]: 49
2808 22:17:23.426248
2809 22:17:23.426345 Set Vref, RX VrefLevel [Byte0]: 50
2810 22:17:23.429340 [Byte1]: 50
2811 22:17:23.434307
2812 22:17:23.434401 Set Vref, RX VrefLevel [Byte0]: 51
2813 22:17:23.437417 [Byte1]: 51
2814 22:17:23.441881
2815 22:17:23.441974 Set Vref, RX VrefLevel [Byte0]: 52
2816 22:17:23.445181 [Byte1]: 52
2817 22:17:23.449805
2818 22:17:23.449897 Set Vref, RX VrefLevel [Byte0]: 53
2819 22:17:23.456275 [Byte1]: 53
2820 22:17:23.456374
2821 22:17:23.459611 Set Vref, RX VrefLevel [Byte0]: 54
2822 22:17:23.462825 [Byte1]: 54
2823 22:17:23.462949
2824 22:17:23.466250 Set Vref, RX VrefLevel [Byte0]: 55
2825 22:17:23.469319 [Byte1]: 55
2826 22:17:23.473437
2827 22:17:23.473526 Set Vref, RX VrefLevel [Byte0]: 56
2828 22:17:23.477050 [Byte1]: 56
2829 22:17:23.481382
2830 22:17:23.481470 Set Vref, RX VrefLevel [Byte0]: 57
2831 22:17:23.484896 [Byte1]: 57
2832 22:17:23.489574
2833 22:17:23.489665 Set Vref, RX VrefLevel [Byte0]: 58
2834 22:17:23.492588 [Byte1]: 58
2835 22:17:23.497435
2836 22:17:23.497525 Set Vref, RX VrefLevel [Byte0]: 59
2837 22:17:23.500465 [Byte1]: 59
2838 22:17:23.504888
2839 22:17:23.504976 Set Vref, RX VrefLevel [Byte0]: 60
2840 22:17:23.508571 [Byte1]: 60
2841 22:17:23.513095
2842 22:17:23.513183 Set Vref, RX VrefLevel [Byte0]: 61
2843 22:17:23.516452 [Byte1]: 61
2844 22:17:23.520707
2845 22:17:23.520855 Set Vref, RX VrefLevel [Byte0]: 62
2846 22:17:23.524185 [Byte1]: 62
2847 22:17:23.528659
2848 22:17:23.528748 Set Vref, RX VrefLevel [Byte0]: 63
2849 22:17:23.532381 [Byte1]: 63
2850 22:17:23.536677
2851 22:17:23.536771 Set Vref, RX VrefLevel [Byte0]: 64
2852 22:17:23.539999 [Byte1]: 64
2853 22:17:23.544347
2854 22:17:23.544437 Set Vref, RX VrefLevel [Byte0]: 65
2855 22:17:23.547911 [Byte1]: 65
2856 22:17:23.552514
2857 22:17:23.555811 Set Vref, RX VrefLevel [Byte0]: 66
2858 22:17:23.555899 [Byte1]: 66
2859 22:17:23.560109
2860 22:17:23.560196 Set Vref, RX VrefLevel [Byte0]: 67
2861 22:17:23.563472 [Byte1]: 67
2862 22:17:23.568536
2863 22:17:23.568627 Set Vref, RX VrefLevel [Byte0]: 68
2864 22:17:23.571545 [Byte1]: 68
2865 22:17:23.575920
2866 22:17:23.576009 Final RX Vref Byte 0 = 57 to rank0
2867 22:17:23.579346 Final RX Vref Byte 1 = 49 to rank0
2868 22:17:23.582947 Final RX Vref Byte 0 = 57 to rank1
2869 22:17:23.585994 Final RX Vref Byte 1 = 49 to rank1==
2870 22:17:23.589380 Dram Type= 6, Freq= 0, CH_0, rank 0
2871 22:17:23.595976 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2872 22:17:23.596078 ==
2873 22:17:23.596147 DQS Delay:
2874 22:17:23.599103 DQS0 = 0, DQS1 = 0
2875 22:17:23.599187 DQM Delay:
2876 22:17:23.599252 DQM0 = 122, DQM1 = 109
2877 22:17:23.602629 DQ Delay:
2878 22:17:23.605743 DQ0 =122, DQ1 =122, DQ2 =118, DQ3 =120
2879 22:17:23.609273 DQ4 =126, DQ5 =116, DQ6 =130, DQ7 =128
2880 22:17:23.612687 DQ8 =100, DQ9 =94, DQ10 =110, DQ11 =106
2881 22:17:23.615837 DQ12 =116, DQ13 =110, DQ14 =122, DQ15 =116
2882 22:17:23.615923
2883 22:17:23.615987
2884 22:17:23.625650 [DQSOSCAuto] RK0, (LSB)MR18= 0xb08, (MSB)MR19= 0x404, tDQSOscB0 = 406 ps tDQSOscB1 = 405 ps
2885 22:17:23.625771 CH0 RK0: MR19=404, MR18=B08
2886 22:17:23.632450 CH0_RK0: MR19=0x404, MR18=0xB08, DQSOSC=405, MR23=63, INC=39, DEC=26
2887 22:17:23.632545
2888 22:17:23.635581 ----->DramcWriteLeveling(PI) begin...
2889 22:17:23.635667 ==
2890 22:17:23.639007 Dram Type= 6, Freq= 0, CH_0, rank 1
2891 22:17:23.645641 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2892 22:17:23.645737 ==
2893 22:17:23.648860 Write leveling (Byte 0): 33 => 33
2894 22:17:23.648944 Write leveling (Byte 1): 30 => 30
2895 22:17:23.651823 DramcWriteLeveling(PI) end<-----
2896 22:17:23.651905
2897 22:17:23.655522 ==
2898 22:17:23.655607 Dram Type= 6, Freq= 0, CH_0, rank 1
2899 22:17:23.662013 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2900 22:17:23.662108 ==
2901 22:17:23.665174 [Gating] SW mode calibration
2902 22:17:23.671910 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2903 22:17:23.675237 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2904 22:17:23.682055 0 15 0 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
2905 22:17:23.685111 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2906 22:17:23.688503 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2907 22:17:23.694888 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2908 22:17:23.698376 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2909 22:17:23.701974 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2910 22:17:23.708117 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2911 22:17:23.711583 0 15 28 | B1->B0 | 3131 2e2e | 0 0 | (1 0) (0 0)
2912 22:17:23.714786 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2913 22:17:23.721440 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2914 22:17:23.724948 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2915 22:17:23.728144 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2916 22:17:23.734840 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2917 22:17:23.738440 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2918 22:17:23.741586 1 0 24 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
2919 22:17:23.747953 1 0 28 | B1->B0 | 3f3f 4545 | 0 0 | (0 0) (0 0)
2920 22:17:23.751623 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2921 22:17:23.754625 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2922 22:17:23.761292 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2923 22:17:23.764698 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2924 22:17:23.768116 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2925 22:17:23.774739 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2926 22:17:23.777822 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2927 22:17:23.781177 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2928 22:17:23.787847 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
2929 22:17:23.791025 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2930 22:17:23.794571 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2931 22:17:23.797747 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2932 22:17:23.804425 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2933 22:17:23.807995 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2934 22:17:23.811042 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2935 22:17:23.817708 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2936 22:17:23.820737 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2937 22:17:23.824201 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2938 22:17:23.830796 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2939 22:17:23.834332 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2940 22:17:23.837976 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2941 22:17:23.844477 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2942 22:17:23.847576 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2943 22:17:23.851173 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2944 22:17:23.857565 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2945 22:17:23.861001 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2946 22:17:23.864136 Total UI for P1: 0, mck2ui 16
2947 22:17:23.867500 best dqsien dly found for B0: ( 1, 3, 30)
2948 22:17:23.870978 Total UI for P1: 0, mck2ui 16
2949 22:17:23.874378 best dqsien dly found for B1: ( 1, 4, 0)
2950 22:17:23.877596 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2951 22:17:23.880675 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2952 22:17:23.880798
2953 22:17:23.884062 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2954 22:17:23.887530 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2955 22:17:23.890727 [Gating] SW calibration Done
2956 22:17:23.890817 ==
2957 22:17:23.894270 Dram Type= 6, Freq= 0, CH_0, rank 1
2958 22:17:23.897256 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2959 22:17:23.900647 ==
2960 22:17:23.900753 RX Vref Scan: 0
2961 22:17:23.900866
2962 22:17:23.904018 RX Vref 0 -> 0, step: 1
2963 22:17:23.904102
2964 22:17:23.904167 RX Delay -40 -> 252, step: 8
2965 22:17:23.910983 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2966 22:17:23.914092 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2967 22:17:23.917234 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2968 22:17:23.920724 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2969 22:17:23.924251 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2970 22:17:23.930771 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2971 22:17:23.934145 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2972 22:17:23.937512 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2973 22:17:23.940713 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2974 22:17:23.943879 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2975 22:17:23.950749 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2976 22:17:23.953878 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2977 22:17:23.957113 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2978 22:17:23.960582 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2979 22:17:23.963747 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2980 22:17:23.970827 iDelay=200, Bit 15, Center 111 (48 ~ 175) 128
2981 22:17:23.970932 ==
2982 22:17:23.973876 Dram Type= 6, Freq= 0, CH_0, rank 1
2983 22:17:23.977100 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2984 22:17:23.977187 ==
2985 22:17:23.977253 DQS Delay:
2986 22:17:23.980659 DQS0 = 0, DQS1 = 0
2987 22:17:23.980771 DQM Delay:
2988 22:17:23.984039 DQM0 = 120, DQM1 = 108
2989 22:17:23.984124 DQ Delay:
2990 22:17:23.987470 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =115
2991 22:17:23.990512 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2992 22:17:23.994210 DQ8 =99, DQ9 =95, DQ10 =107, DQ11 =107
2993 22:17:23.997100 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =111
2994 22:17:23.997202
2995 22:17:23.997298
2996 22:17:24.000801 ==
2997 22:17:24.003933 Dram Type= 6, Freq= 0, CH_0, rank 1
2998 22:17:24.007429 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2999 22:17:24.007517 ==
3000 22:17:24.007583
3001 22:17:24.007643
3002 22:17:24.010562 TX Vref Scan disable
3003 22:17:24.010648 == TX Byte 0 ==
3004 22:17:24.014110 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
3005 22:17:24.020751 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
3006 22:17:24.020884 == TX Byte 1 ==
3007 22:17:24.024039 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3008 22:17:24.030378 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3009 22:17:24.030477 ==
3010 22:17:24.033905 Dram Type= 6, Freq= 0, CH_0, rank 1
3011 22:17:24.037463 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3012 22:17:24.037551 ==
3013 22:17:24.048960 TX Vref=22, minBit 1, minWin=23, winSum=397
3014 22:17:24.052204 TX Vref=24, minBit 7, minWin=24, winSum=409
3015 22:17:24.055882 TX Vref=26, minBit 0, minWin=25, winSum=413
3016 22:17:24.058992 TX Vref=28, minBit 0, minWin=25, winSum=413
3017 22:17:24.062615 TX Vref=30, minBit 2, minWin=25, winSum=414
3018 22:17:24.068747 TX Vref=32, minBit 1, minWin=24, winSum=411
3019 22:17:24.072508 [TxChooseVref] Worse bit 2, Min win 25, Win sum 414, Final Vref 30
3020 22:17:24.072602
3021 22:17:24.075654 Final TX Range 1 Vref 30
3022 22:17:24.075740
3023 22:17:24.075805 ==
3024 22:17:24.079066 Dram Type= 6, Freq= 0, CH_0, rank 1
3025 22:17:24.082089 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3026 22:17:24.085416 ==
3027 22:17:24.085506
3028 22:17:24.085573
3029 22:17:24.085633 TX Vref Scan disable
3030 22:17:24.088754 == TX Byte 0 ==
3031 22:17:24.092215 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
3032 22:17:24.095994 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
3033 22:17:24.099197 == TX Byte 1 ==
3034 22:17:24.102253 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3035 22:17:24.105507 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3036 22:17:24.108753
3037 22:17:24.108911 [DATLAT]
3038 22:17:24.109006 Freq=1200, CH0 RK1
3039 22:17:24.109081
3040 22:17:24.112417 DATLAT Default: 0xd
3041 22:17:24.112499 0, 0xFFFF, sum = 0
3042 22:17:24.115287 1, 0xFFFF, sum = 0
3043 22:17:24.118962 2, 0xFFFF, sum = 0
3044 22:17:24.119049 3, 0xFFFF, sum = 0
3045 22:17:24.122069 4, 0xFFFF, sum = 0
3046 22:17:24.122154 5, 0xFFFF, sum = 0
3047 22:17:24.125242 6, 0xFFFF, sum = 0
3048 22:17:24.125327 7, 0xFFFF, sum = 0
3049 22:17:24.128677 8, 0xFFFF, sum = 0
3050 22:17:24.128836 9, 0xFFFF, sum = 0
3051 22:17:24.132021 10, 0xFFFF, sum = 0
3052 22:17:24.132106 11, 0xFFFF, sum = 0
3053 22:17:24.135165 12, 0x0, sum = 1
3054 22:17:24.135250 13, 0x0, sum = 2
3055 22:17:24.138686 14, 0x0, sum = 3
3056 22:17:24.138773 15, 0x0, sum = 4
3057 22:17:24.141839 best_step = 13
3058 22:17:24.141954
3059 22:17:24.142018 ==
3060 22:17:24.145238 Dram Type= 6, Freq= 0, CH_0, rank 1
3061 22:17:24.148671 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3062 22:17:24.148778 ==
3063 22:17:24.148906 RX Vref Scan: 0
3064 22:17:24.148994
3065 22:17:24.152272 RX Vref 0 -> 0, step: 1
3066 22:17:24.152356
3067 22:17:24.155452 RX Delay -21 -> 252, step: 4
3068 22:17:24.158618 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
3069 22:17:24.165301 iDelay=195, Bit 1, Center 122 (55 ~ 190) 136
3070 22:17:24.168757 iDelay=195, Bit 2, Center 116 (51 ~ 182) 132
3071 22:17:24.171981 iDelay=195, Bit 3, Center 114 (51 ~ 178) 128
3072 22:17:24.175524 iDelay=195, Bit 4, Center 120 (55 ~ 186) 132
3073 22:17:24.178483 iDelay=195, Bit 5, Center 114 (51 ~ 178) 128
3074 22:17:24.185203 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3075 22:17:24.188644 iDelay=195, Bit 7, Center 126 (59 ~ 194) 136
3076 22:17:24.191842 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3077 22:17:24.195101 iDelay=195, Bit 9, Center 94 (31 ~ 158) 128
3078 22:17:24.198331 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3079 22:17:24.205012 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3080 22:17:24.208238 iDelay=195, Bit 12, Center 112 (47 ~ 178) 132
3081 22:17:24.211743 iDelay=195, Bit 13, Center 110 (47 ~ 174) 128
3082 22:17:24.214704 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3083 22:17:24.221507 iDelay=195, Bit 15, Center 114 (51 ~ 178) 128
3084 22:17:24.221619 ==
3085 22:17:24.224936 Dram Type= 6, Freq= 0, CH_0, rank 1
3086 22:17:24.227947 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3087 22:17:24.228035 ==
3088 22:17:24.228102 DQS Delay:
3089 22:17:24.231500 DQS0 = 0, DQS1 = 0
3090 22:17:24.231584 DQM Delay:
3091 22:17:24.234955 DQM0 = 119, DQM1 = 107
3092 22:17:24.235041 DQ Delay:
3093 22:17:24.237978 DQ0 =118, DQ1 =122, DQ2 =116, DQ3 =114
3094 22:17:24.241681 DQ4 =120, DQ5 =114, DQ6 =126, DQ7 =126
3095 22:17:24.244714 DQ8 =98, DQ9 =94, DQ10 =110, DQ11 =106
3096 22:17:24.247916 DQ12 =112, DQ13 =110, DQ14 =118, DQ15 =114
3097 22:17:24.248003
3098 22:17:24.248072
3099 22:17:24.258069 [DQSOSCAuto] RK1, (LSB)MR18= 0x11f9, (MSB)MR19= 0x403, tDQSOscB0 = 412 ps tDQSOscB1 = 403 ps
3100 22:17:24.261338 CH0 RK1: MR19=403, MR18=11F9
3101 22:17:24.264787 CH0_RK1: MR19=0x403, MR18=0x11F9, DQSOSC=403, MR23=63, INC=40, DEC=26
3102 22:17:24.267850 [RxdqsGatingPostProcess] freq 1200
3103 22:17:24.274667 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3104 22:17:24.277928 best DQS0 dly(2T, 0.5T) = (0, 11)
3105 22:17:24.281506 best DQS1 dly(2T, 0.5T) = (0, 11)
3106 22:17:24.284590 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3107 22:17:24.287790 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3108 22:17:24.291367 best DQS0 dly(2T, 0.5T) = (0, 11)
3109 22:17:24.294748 best DQS1 dly(2T, 0.5T) = (0, 12)
3110 22:17:24.297960 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3111 22:17:24.301024 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3112 22:17:24.304420 Pre-setting of DQS Precalculation
3113 22:17:24.307885 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3114 22:17:24.307978 ==
3115 22:17:24.311234 Dram Type= 6, Freq= 0, CH_1, rank 0
3116 22:17:24.314510 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3117 22:17:24.314598 ==
3118 22:17:24.321219 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3119 22:17:24.327740 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3120 22:17:24.335248 [CA 0] Center 37 (7~67) winsize 61
3121 22:17:24.338814 [CA 1] Center 37 (7~68) winsize 62
3122 22:17:24.341846 [CA 2] Center 34 (4~65) winsize 62
3123 22:17:24.345540 [CA 3] Center 33 (3~64) winsize 62
3124 22:17:24.348715 [CA 4] Center 33 (3~64) winsize 62
3125 22:17:24.352088 [CA 5] Center 33 (3~63) winsize 61
3126 22:17:24.352177
3127 22:17:24.355668 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3128 22:17:24.355755
3129 22:17:24.358586 [CATrainingPosCal] consider 1 rank data
3130 22:17:24.362045 u2DelayCellTimex100 = 270/100 ps
3131 22:17:24.365230 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3132 22:17:24.368678 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3133 22:17:24.375253 CA2 delay=34 (4~65),Diff = 1 PI (4 cell)
3134 22:17:24.378896 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3135 22:17:24.382109 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3136 22:17:24.385209 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3137 22:17:24.385298
3138 22:17:24.388819 CA PerBit enable=1, Macro0, CA PI delay=33
3139 22:17:24.388906
3140 22:17:24.391919 [CBTSetCACLKResult] CA Dly = 33
3141 22:17:24.392005 CS Dly: 5 (0~36)
3142 22:17:24.392071 ==
3143 22:17:24.395615 Dram Type= 6, Freq= 0, CH_1, rank 1
3144 22:17:24.402004 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3145 22:17:24.402102 ==
3146 22:17:24.405270 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3147 22:17:24.411664 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3148 22:17:24.421328 [CA 0] Center 38 (8~68) winsize 61
3149 22:17:24.424550 [CA 1] Center 37 (7~68) winsize 62
3150 22:17:24.427773 [CA 2] Center 35 (4~66) winsize 63
3151 22:17:24.431022 [CA 3] Center 34 (4~64) winsize 61
3152 22:17:24.434262 [CA 4] Center 34 (4~64) winsize 61
3153 22:17:24.437550 [CA 5] Center 33 (3~63) winsize 61
3154 22:17:24.437637
3155 22:17:24.440776 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3156 22:17:24.440882
3157 22:17:24.444350 [CATrainingPosCal] consider 2 rank data
3158 22:17:24.447965 u2DelayCellTimex100 = 270/100 ps
3159 22:17:24.451000 CA0 delay=37 (8~67),Diff = 4 PI (19 cell)
3160 22:17:24.454636 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3161 22:17:24.461011 CA2 delay=34 (4~65),Diff = 1 PI (4 cell)
3162 22:17:24.464360 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3163 22:17:24.467546 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3164 22:17:24.471046 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3165 22:17:24.471138
3166 22:17:24.474075 CA PerBit enable=1, Macro0, CA PI delay=33
3167 22:17:24.474160
3168 22:17:24.477947 [CBTSetCACLKResult] CA Dly = 33
3169 22:17:24.478034 CS Dly: 6 (0~38)
3170 22:17:24.478118
3171 22:17:24.481067 ----->DramcWriteLeveling(PI) begin...
3172 22:17:24.484476 ==
3173 22:17:24.484565 Dram Type= 6, Freq= 0, CH_1, rank 0
3174 22:17:24.491303 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3175 22:17:24.491400 ==
3176 22:17:24.494258 Write leveling (Byte 0): 24 => 24
3177 22:17:24.497527 Write leveling (Byte 1): 29 => 29
3178 22:17:24.501088 DramcWriteLeveling(PI) end<-----
3179 22:17:24.501176
3180 22:17:24.501259 ==
3181 22:17:24.504099 Dram Type= 6, Freq= 0, CH_1, rank 0
3182 22:17:24.507606 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3183 22:17:24.507695 ==
3184 22:17:24.511236 [Gating] SW mode calibration
3185 22:17:24.517553 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3186 22:17:24.520961 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3187 22:17:24.527861 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3188 22:17:24.531247 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3189 22:17:24.534437 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3190 22:17:24.540747 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3191 22:17:24.544374 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3192 22:17:24.547487 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3193 22:17:24.554546 0 15 24 | B1->B0 | 2828 2626 | 0 0 | (0 0) (1 0)
3194 22:17:24.557654 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3195 22:17:24.560940 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3196 22:17:24.567823 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3197 22:17:24.570851 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3198 22:17:24.574531 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3199 22:17:24.580695 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3200 22:17:24.584311 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3201 22:17:24.587453 1 0 24 | B1->B0 | 3a3a 4242 | 0 0 | (0 0) (0 0)
3202 22:17:24.593985 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3203 22:17:24.597462 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3204 22:17:24.601098 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3205 22:17:24.607647 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3206 22:17:24.610907 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3207 22:17:24.614106 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3208 22:17:24.617594 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3209 22:17:24.624422 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3210 22:17:24.627404 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3211 22:17:24.630645 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3212 22:17:24.637350 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3213 22:17:24.640607 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3214 22:17:24.644170 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3215 22:17:24.650624 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3216 22:17:24.654027 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3217 22:17:24.657674 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3218 22:17:24.664027 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3219 22:17:24.667571 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3220 22:17:24.670605 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3221 22:17:24.677332 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3222 22:17:24.680469 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3223 22:17:24.683995 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3224 22:17:24.690666 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3225 22:17:24.693681 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3226 22:17:24.696938 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3227 22:17:24.700643 Total UI for P1: 0, mck2ui 16
3228 22:17:24.703598 best dqsien dly found for B0: ( 1, 3, 24)
3229 22:17:24.710365 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3230 22:17:24.710483 Total UI for P1: 0, mck2ui 16
3231 22:17:24.717080 best dqsien dly found for B1: ( 1, 3, 26)
3232 22:17:24.720364 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3233 22:17:24.723544 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3234 22:17:24.723639
3235 22:17:24.726954 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3236 22:17:24.730344 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3237 22:17:24.733483 [Gating] SW calibration Done
3238 22:17:24.733579 ==
3239 22:17:24.736883 Dram Type= 6, Freq= 0, CH_1, rank 0
3240 22:17:24.740265 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3241 22:17:24.740359 ==
3242 22:17:24.743969 RX Vref Scan: 0
3243 22:17:24.744063
3244 22:17:24.744149 RX Vref 0 -> 0, step: 1
3245 22:17:24.744229
3246 22:17:24.746636 RX Delay -40 -> 252, step: 8
3247 22:17:24.750123 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3248 22:17:24.757242 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3249 22:17:24.760120 iDelay=200, Bit 2, Center 111 (48 ~ 175) 128
3250 22:17:24.763573 iDelay=200, Bit 3, Center 123 (56 ~ 191) 136
3251 22:17:24.766734 iDelay=200, Bit 4, Center 119 (56 ~ 183) 128
3252 22:17:24.770255 iDelay=200, Bit 5, Center 127 (64 ~ 191) 128
3253 22:17:24.776663 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3254 22:17:24.780108 iDelay=200, Bit 7, Center 119 (56 ~ 183) 128
3255 22:17:24.783315 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3256 22:17:24.786571 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3257 22:17:24.790001 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3258 22:17:24.796734 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3259 22:17:24.799979 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3260 22:17:24.803028 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3261 22:17:24.806530 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3262 22:17:24.809804 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3263 22:17:24.813383 ==
3264 22:17:24.816520 Dram Type= 6, Freq= 0, CH_1, rank 0
3265 22:17:24.819669 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3266 22:17:24.819763 ==
3267 22:17:24.819848 DQS Delay:
3268 22:17:24.823277 DQS0 = 0, DQS1 = 0
3269 22:17:24.823366 DQM Delay:
3270 22:17:24.826220 DQM0 = 120, DQM1 = 112
3271 22:17:24.826307 DQ Delay:
3272 22:17:24.829949 DQ0 =123, DQ1 =115, DQ2 =111, DQ3 =123
3273 22:17:24.832802 DQ4 =119, DQ5 =127, DQ6 =127, DQ7 =119
3274 22:17:24.836504 DQ8 =99, DQ9 =99, DQ10 =115, DQ11 =107
3275 22:17:24.839824 DQ12 =123, DQ13 =119, DQ14 =119, DQ15 =119
3276 22:17:24.839985
3277 22:17:24.840095
3278 22:17:24.840156 ==
3279 22:17:24.842725 Dram Type= 6, Freq= 0, CH_1, rank 0
3280 22:17:24.849338 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3281 22:17:24.849442 ==
3282 22:17:24.849508
3283 22:17:24.849569
3284 22:17:24.849626 TX Vref Scan disable
3285 22:17:24.853548 == TX Byte 0 ==
3286 22:17:24.856631 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3287 22:17:24.859912 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3288 22:17:24.863043 == TX Byte 1 ==
3289 22:17:24.866468 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3290 22:17:24.873221 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3291 22:17:24.873336 ==
3292 22:17:24.876193 Dram Type= 6, Freq= 0, CH_1, rank 0
3293 22:17:24.879577 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3294 22:17:24.879672 ==
3295 22:17:24.891036 TX Vref=22, minBit 1, minWin=24, winSum=398
3296 22:17:24.894579 TX Vref=24, minBit 10, minWin=23, winSum=399
3297 22:17:24.897601 TX Vref=26, minBit 1, minWin=25, winSum=410
3298 22:17:24.901118 TX Vref=28, minBit 8, minWin=25, winSum=413
3299 22:17:24.904206 TX Vref=30, minBit 10, minWin=25, winSum=418
3300 22:17:24.910909 TX Vref=32, minBit 8, minWin=25, winSum=417
3301 22:17:24.914375 [TxChooseVref] Worse bit 10, Min win 25, Win sum 418, Final Vref 30
3302 22:17:24.914464
3303 22:17:24.917641 Final TX Range 1 Vref 30
3304 22:17:24.917727
3305 22:17:24.917793 ==
3306 22:17:24.920885 Dram Type= 6, Freq= 0, CH_1, rank 0
3307 22:17:24.924351 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3308 22:17:24.927400 ==
3309 22:17:24.927492
3310 22:17:24.927559
3311 22:17:24.927619 TX Vref Scan disable
3312 22:17:24.931036 == TX Byte 0 ==
3313 22:17:24.934258 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3314 22:17:24.937962 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3315 22:17:24.941071 == TX Byte 1 ==
3316 22:17:24.944244 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3317 22:17:24.951271 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3318 22:17:24.951384
3319 22:17:24.951452 [DATLAT]
3320 22:17:24.951514 Freq=1200, CH1 RK0
3321 22:17:24.951574
3322 22:17:24.954163 DATLAT Default: 0xd
3323 22:17:24.954249 0, 0xFFFF, sum = 0
3324 22:17:24.958074 1, 0xFFFF, sum = 0
3325 22:17:24.958164 2, 0xFFFF, sum = 0
3326 22:17:24.961356 3, 0xFFFF, sum = 0
3327 22:17:24.964502 4, 0xFFFF, sum = 0
3328 22:17:24.964596 5, 0xFFFF, sum = 0
3329 22:17:24.967780 6, 0xFFFF, sum = 0
3330 22:17:24.967872 7, 0xFFFF, sum = 0
3331 22:17:24.970802 8, 0xFFFF, sum = 0
3332 22:17:24.970890 9, 0xFFFF, sum = 0
3333 22:17:24.974386 10, 0xFFFF, sum = 0
3334 22:17:24.974477 11, 0xFFFF, sum = 0
3335 22:17:24.977405 12, 0x0, sum = 1
3336 22:17:24.977492 13, 0x0, sum = 2
3337 22:17:24.980637 14, 0x0, sum = 3
3338 22:17:24.980754 15, 0x0, sum = 4
3339 22:17:24.984237 best_step = 13
3340 22:17:24.984323
3341 22:17:24.984389 ==
3342 22:17:24.987361 Dram Type= 6, Freq= 0, CH_1, rank 0
3343 22:17:24.990904 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3344 22:17:24.991021 ==
3345 22:17:24.991119 RX Vref Scan: 1
3346 22:17:24.991220
3347 22:17:24.993994 Set Vref Range= 32 -> 127
3348 22:17:24.994082
3349 22:17:24.997582 RX Vref 32 -> 127, step: 1
3350 22:17:24.997669
3351 22:17:25.000798 RX Delay -13 -> 252, step: 4
3352 22:17:25.000897
3353 22:17:25.004066 Set Vref, RX VrefLevel [Byte0]: 32
3354 22:17:25.007554 [Byte1]: 32
3355 22:17:25.007643
3356 22:17:25.010706 Set Vref, RX VrefLevel [Byte0]: 33
3357 22:17:25.014437 [Byte1]: 33
3358 22:17:25.017795
3359 22:17:25.017890 Set Vref, RX VrefLevel [Byte0]: 34
3360 22:17:25.020789 [Byte1]: 34
3361 22:17:25.025321
3362 22:17:25.025426 Set Vref, RX VrefLevel [Byte0]: 35
3363 22:17:25.028721 [Byte1]: 35
3364 22:17:25.033307
3365 22:17:25.033398 Set Vref, RX VrefLevel [Byte0]: 36
3366 22:17:25.036376 [Byte1]: 36
3367 22:17:25.041125
3368 22:17:25.041218 Set Vref, RX VrefLevel [Byte0]: 37
3369 22:17:25.044476 [Byte1]: 37
3370 22:17:25.049180
3371 22:17:25.049277 Set Vref, RX VrefLevel [Byte0]: 38
3372 22:17:25.052258 [Byte1]: 38
3373 22:17:25.056987
3374 22:17:25.057084 Set Vref, RX VrefLevel [Byte0]: 39
3375 22:17:25.060236 [Byte1]: 39
3376 22:17:25.064905
3377 22:17:25.064999 Set Vref, RX VrefLevel [Byte0]: 40
3378 22:17:25.068307 [Byte1]: 40
3379 22:17:25.072597
3380 22:17:25.072690 Set Vref, RX VrefLevel [Byte0]: 41
3381 22:17:25.075990 [Byte1]: 41
3382 22:17:25.080811
3383 22:17:25.080959 Set Vref, RX VrefLevel [Byte0]: 42
3384 22:17:25.083742 [Byte1]: 42
3385 22:17:25.088345
3386 22:17:25.088436 Set Vref, RX VrefLevel [Byte0]: 43
3387 22:17:25.091870 [Byte1]: 43
3388 22:17:25.096285
3389 22:17:25.096375 Set Vref, RX VrefLevel [Byte0]: 44
3390 22:17:25.099848 [Byte1]: 44
3391 22:17:25.104176
3392 22:17:25.104263 Set Vref, RX VrefLevel [Byte0]: 45
3393 22:17:25.107494 [Byte1]: 45
3394 22:17:25.112262
3395 22:17:25.112351 Set Vref, RX VrefLevel [Byte0]: 46
3396 22:17:25.115395 [Byte1]: 46
3397 22:17:25.120324
3398 22:17:25.120412 Set Vref, RX VrefLevel [Byte0]: 47
3399 22:17:25.123296 [Byte1]: 47
3400 22:17:25.128053
3401 22:17:25.128145 Set Vref, RX VrefLevel [Byte0]: 48
3402 22:17:25.131422 [Byte1]: 48
3403 22:17:25.136029
3404 22:17:25.136118 Set Vref, RX VrefLevel [Byte0]: 49
3405 22:17:25.139049 [Byte1]: 49
3406 22:17:25.143613
3407 22:17:25.143701 Set Vref, RX VrefLevel [Byte0]: 50
3408 22:17:25.147275 [Byte1]: 50
3409 22:17:25.151614
3410 22:17:25.151704 Set Vref, RX VrefLevel [Byte0]: 51
3411 22:17:25.155091 [Byte1]: 51
3412 22:17:25.159604
3413 22:17:25.159691 Set Vref, RX VrefLevel [Byte0]: 52
3414 22:17:25.162740 [Byte1]: 52
3415 22:17:25.167405
3416 22:17:25.167497 Set Vref, RX VrefLevel [Byte0]: 53
3417 22:17:25.170504 [Byte1]: 53
3418 22:17:25.175380
3419 22:17:25.175478 Set Vref, RX VrefLevel [Byte0]: 54
3420 22:17:25.178465 [Byte1]: 54
3421 22:17:25.183025
3422 22:17:25.183151 Set Vref, RX VrefLevel [Byte0]: 55
3423 22:17:25.186461 [Byte1]: 55
3424 22:17:25.191037
3425 22:17:25.191135 Set Vref, RX VrefLevel [Byte0]: 56
3426 22:17:25.194548 [Byte1]: 56
3427 22:17:25.198873
3428 22:17:25.198967 Set Vref, RX VrefLevel [Byte0]: 57
3429 22:17:25.202133 [Byte1]: 57
3430 22:17:25.207127
3431 22:17:25.207225 Set Vref, RX VrefLevel [Byte0]: 58
3432 22:17:25.210163 [Byte1]: 58
3433 22:17:25.214594
3434 22:17:25.214686 Set Vref, RX VrefLevel [Byte0]: 59
3435 22:17:25.218163 [Byte1]: 59
3436 22:17:25.222560
3437 22:17:25.222653 Set Vref, RX VrefLevel [Byte0]: 60
3438 22:17:25.225700 [Byte1]: 60
3439 22:17:25.230574
3440 22:17:25.230671 Set Vref, RX VrefLevel [Byte0]: 61
3441 22:17:25.234232 [Byte1]: 61
3442 22:17:25.238239
3443 22:17:25.238331 Set Vref, RX VrefLevel [Byte0]: 62
3444 22:17:25.241858 [Byte1]: 62
3445 22:17:25.246338
3446 22:17:25.246429 Set Vref, RX VrefLevel [Byte0]: 63
3447 22:17:25.249617 [Byte1]: 63
3448 22:17:25.254051
3449 22:17:25.254147 Set Vref, RX VrefLevel [Byte0]: 64
3450 22:17:25.257588 [Byte1]: 64
3451 22:17:25.262120
3452 22:17:25.262212 Set Vref, RX VrefLevel [Byte0]: 65
3453 22:17:25.265556 [Byte1]: 65
3454 22:17:25.269780
3455 22:17:25.269874 Set Vref, RX VrefLevel [Byte0]: 66
3456 22:17:25.273515 [Byte1]: 66
3457 22:17:25.278208
3458 22:17:25.278307 Final RX Vref Byte 0 = 51 to rank0
3459 22:17:25.281027 Final RX Vref Byte 1 = 52 to rank0
3460 22:17:25.284298 Final RX Vref Byte 0 = 51 to rank1
3461 22:17:25.287815 Final RX Vref Byte 1 = 52 to rank1==
3462 22:17:25.291474 Dram Type= 6, Freq= 0, CH_1, rank 0
3463 22:17:25.297728 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3464 22:17:25.297846 ==
3465 22:17:25.297914 DQS Delay:
3466 22:17:25.297976 DQS0 = 0, DQS1 = 0
3467 22:17:25.300960 DQM Delay:
3468 22:17:25.301046 DQM0 = 119, DQM1 = 112
3469 22:17:25.304451 DQ Delay:
3470 22:17:25.307592 DQ0 =120, DQ1 =112, DQ2 =112, DQ3 =120
3471 22:17:25.310839 DQ4 =118, DQ5 =128, DQ6 =130, DQ7 =116
3472 22:17:25.314482 DQ8 =102, DQ9 =100, DQ10 =114, DQ11 =106
3473 22:17:25.317550 DQ12 =122, DQ13 =118, DQ14 =122, DQ15 =118
3474 22:17:25.317645
3475 22:17:25.317713
3476 22:17:25.327805 [DQSOSCAuto] RK0, (LSB)MR18= 0xff12, (MSB)MR19= 0x304, tDQSOscB0 = 403 ps tDQSOscB1 = 410 ps
3477 22:17:25.327923 CH1 RK0: MR19=304, MR18=FF12
3478 22:17:25.334020 CH1_RK0: MR19=0x304, MR18=0xFF12, DQSOSC=403, MR23=63, INC=40, DEC=26
3479 22:17:25.334123
3480 22:17:25.337258 ----->DramcWriteLeveling(PI) begin...
3481 22:17:25.337345 ==
3482 22:17:25.340656 Dram Type= 6, Freq= 0, CH_1, rank 1
3483 22:17:25.347743 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3484 22:17:25.347849 ==
3485 22:17:25.350890 Write leveling (Byte 0): 25 => 25
3486 22:17:25.350976 Write leveling (Byte 1): 30 => 30
3487 22:17:25.354158 DramcWriteLeveling(PI) end<-----
3488 22:17:25.354243
3489 22:17:25.357378 ==
3490 22:17:25.357468 Dram Type= 6, Freq= 0, CH_1, rank 1
3491 22:17:25.364045 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3492 22:17:25.364141 ==
3493 22:17:25.367570 [Gating] SW mode calibration
3494 22:17:25.373947 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3495 22:17:25.377370 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3496 22:17:25.383965 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3497 22:17:25.387544 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3498 22:17:25.390830 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3499 22:17:25.397313 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3500 22:17:25.400401 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3501 22:17:25.403714 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
3502 22:17:25.410368 0 15 24 | B1->B0 | 2424 3232 | 0 1 | (0 0) (1 0)
3503 22:17:25.413813 0 15 28 | B1->B0 | 2323 2b2b | 0 0 | (1 0) (1 0)
3504 22:17:25.417120 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3505 22:17:25.423693 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3506 22:17:25.426978 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3507 22:17:25.430596 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3508 22:17:25.437251 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3509 22:17:25.440309 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3510 22:17:25.443780 1 0 24 | B1->B0 | 3938 2929 | 1 0 | (1 1) (0 0)
3511 22:17:25.450373 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3512 22:17:25.453500 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3513 22:17:25.457075 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3514 22:17:25.460587 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3515 22:17:25.467082 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3516 22:17:25.470336 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3517 22:17:25.473478 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3518 22:17:25.480346 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3519 22:17:25.483459 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3520 22:17:25.486853 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3521 22:17:25.493940 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3522 22:17:25.496815 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3523 22:17:25.500240 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3524 22:17:25.506763 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3525 22:17:25.510292 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3526 22:17:25.513339 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3527 22:17:25.519882 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3528 22:17:25.523555 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3529 22:17:25.526700 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3530 22:17:25.533456 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3531 22:17:25.536529 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3532 22:17:25.540095 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3533 22:17:25.546559 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3534 22:17:25.549796 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3535 22:17:25.553313 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3536 22:17:25.556291 Total UI for P1: 0, mck2ui 16
3537 22:17:25.559847 best dqsien dly found for B0: ( 1, 3, 22)
3538 22:17:25.566310 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3539 22:17:25.566416 Total UI for P1: 0, mck2ui 16
3540 22:17:25.572971 best dqsien dly found for B1: ( 1, 3, 24)
3541 22:17:25.576439 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3542 22:17:25.579373 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3543 22:17:25.579462
3544 22:17:25.582730 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3545 22:17:25.586335 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3546 22:17:25.589331 [Gating] SW calibration Done
3547 22:17:25.589425 ==
3548 22:17:25.592897 Dram Type= 6, Freq= 0, CH_1, rank 1
3549 22:17:25.596056 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3550 22:17:25.596151 ==
3551 22:17:25.599148 RX Vref Scan: 0
3552 22:17:25.599238
3553 22:17:25.599304 RX Vref 0 -> 0, step: 1
3554 22:17:25.599365
3555 22:17:25.602490 RX Delay -40 -> 252, step: 8
3556 22:17:25.609340 iDelay=200, Bit 0, Center 123 (64 ~ 183) 120
3557 22:17:25.612525 iDelay=200, Bit 1, Center 111 (48 ~ 175) 128
3558 22:17:25.615714 iDelay=200, Bit 2, Center 111 (48 ~ 175) 128
3559 22:17:25.618945 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
3560 22:17:25.622415 iDelay=200, Bit 4, Center 123 (56 ~ 191) 136
3561 22:17:25.629056 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3562 22:17:25.632237 iDelay=200, Bit 6, Center 127 (64 ~ 191) 128
3563 22:17:25.635724 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3564 22:17:25.639263 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3565 22:17:25.642358 iDelay=200, Bit 9, Center 103 (40 ~ 167) 128
3566 22:17:25.645489 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3567 22:17:25.652213 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3568 22:17:25.655490 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3569 22:17:25.658601 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3570 22:17:25.662026 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3571 22:17:25.668538 iDelay=200, Bit 15, Center 123 (48 ~ 199) 152
3572 22:17:25.668651 ==
3573 22:17:25.672244 Dram Type= 6, Freq= 0, CH_1, rank 1
3574 22:17:25.675196 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3575 22:17:25.675287 ==
3576 22:17:25.675354 DQS Delay:
3577 22:17:25.678702 DQS0 = 0, DQS1 = 0
3578 22:17:25.678789 DQM Delay:
3579 22:17:25.681768 DQM0 = 119, DQM1 = 113
3580 22:17:25.681871 DQ Delay:
3581 22:17:25.685231 DQ0 =123, DQ1 =111, DQ2 =111, DQ3 =115
3582 22:17:25.688393 DQ4 =123, DQ5 =131, DQ6 =127, DQ7 =115
3583 22:17:25.691911 DQ8 =99, DQ9 =103, DQ10 =115, DQ11 =107
3584 22:17:25.694942 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =123
3585 22:17:25.695034
3586 22:17:25.698499
3587 22:17:25.698586 ==
3588 22:17:25.701599 Dram Type= 6, Freq= 0, CH_1, rank 1
3589 22:17:25.704969 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3590 22:17:25.705059 ==
3591 22:17:25.705127
3592 22:17:25.705189
3593 22:17:25.708366 TX Vref Scan disable
3594 22:17:25.708451 == TX Byte 0 ==
3595 22:17:25.714838 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3596 22:17:25.717962 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3597 22:17:25.718060 == TX Byte 1 ==
3598 22:17:25.724689 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3599 22:17:25.728291 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3600 22:17:25.728387 ==
3601 22:17:25.731304 Dram Type= 6, Freq= 0, CH_1, rank 1
3602 22:17:25.734751 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3603 22:17:25.734841 ==
3604 22:17:25.747200 TX Vref=22, minBit 0, minWin=25, winSum=410
3605 22:17:25.750775 TX Vref=24, minBit 1, minWin=25, winSum=419
3606 22:17:25.753891 TX Vref=26, minBit 3, minWin=25, winSum=420
3607 22:17:25.757286 TX Vref=28, minBit 1, minWin=26, winSum=425
3608 22:17:25.760310 TX Vref=30, minBit 3, minWin=26, winSum=428
3609 22:17:25.766993 TX Vref=32, minBit 9, minWin=25, winSum=424
3610 22:17:25.770364 [TxChooseVref] Worse bit 3, Min win 26, Win sum 428, Final Vref 30
3611 22:17:25.770465
3612 22:17:25.773562 Final TX Range 1 Vref 30
3613 22:17:25.773651
3614 22:17:25.773718 ==
3615 22:17:25.777051 Dram Type= 6, Freq= 0, CH_1, rank 1
3616 22:17:25.780164 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3617 22:17:25.783832 ==
3618 22:17:25.783936
3619 22:17:25.784004
3620 22:17:25.784064 TX Vref Scan disable
3621 22:17:25.787212 == TX Byte 0 ==
3622 22:17:25.790500 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3623 22:17:25.797098 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3624 22:17:25.797221 == TX Byte 1 ==
3625 22:17:25.800124 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3626 22:17:25.806704 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3627 22:17:25.806807
3628 22:17:25.806876 [DATLAT]
3629 22:17:25.806937 Freq=1200, CH1 RK1
3630 22:17:25.806997
3631 22:17:25.810168 DATLAT Default: 0xd
3632 22:17:25.813300 0, 0xFFFF, sum = 0
3633 22:17:25.813389 1, 0xFFFF, sum = 0
3634 22:17:25.816678 2, 0xFFFF, sum = 0
3635 22:17:25.816770 3, 0xFFFF, sum = 0
3636 22:17:25.820312 4, 0xFFFF, sum = 0
3637 22:17:25.820402 5, 0xFFFF, sum = 0
3638 22:17:25.823430 6, 0xFFFF, sum = 0
3639 22:17:25.823549 7, 0xFFFF, sum = 0
3640 22:17:25.826543 8, 0xFFFF, sum = 0
3641 22:17:25.826630 9, 0xFFFF, sum = 0
3642 22:17:25.830004 10, 0xFFFF, sum = 0
3643 22:17:25.830095 11, 0xFFFF, sum = 0
3644 22:17:25.833397 12, 0x0, sum = 1
3645 22:17:25.833488 13, 0x0, sum = 2
3646 22:17:25.836439 14, 0x0, sum = 3
3647 22:17:25.836526 15, 0x0, sum = 4
3648 22:17:25.839983 best_step = 13
3649 22:17:25.840069
3650 22:17:25.840138 ==
3651 22:17:25.843423 Dram Type= 6, Freq= 0, CH_1, rank 1
3652 22:17:25.846606 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3653 22:17:25.846697 ==
3654 22:17:25.846765 RX Vref Scan: 0
3655 22:17:25.849799
3656 22:17:25.849885 RX Vref 0 -> 0, step: 1
3657 22:17:25.849951
3658 22:17:25.853227 RX Delay -13 -> 252, step: 4
3659 22:17:25.859913 iDelay=195, Bit 0, Center 122 (63 ~ 182) 120
3660 22:17:25.863165 iDelay=195, Bit 1, Center 114 (55 ~ 174) 120
3661 22:17:25.866307 iDelay=195, Bit 2, Center 108 (51 ~ 166) 116
3662 22:17:25.869791 iDelay=195, Bit 3, Center 116 (55 ~ 178) 124
3663 22:17:25.872737 iDelay=195, Bit 4, Center 120 (59 ~ 182) 124
3664 22:17:25.879586 iDelay=195, Bit 5, Center 130 (67 ~ 194) 128
3665 22:17:25.882997 iDelay=195, Bit 6, Center 126 (67 ~ 186) 120
3666 22:17:25.886237 iDelay=195, Bit 7, Center 116 (55 ~ 178) 124
3667 22:17:25.889356 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3668 22:17:25.892881 iDelay=195, Bit 9, Center 102 (39 ~ 166) 128
3669 22:17:25.899553 iDelay=195, Bit 10, Center 114 (51 ~ 178) 128
3670 22:17:25.902554 iDelay=195, Bit 11, Center 108 (43 ~ 174) 132
3671 22:17:25.905892 iDelay=195, Bit 12, Center 122 (59 ~ 186) 128
3672 22:17:25.909076 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3673 22:17:25.912597 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3674 22:17:25.919397 iDelay=195, Bit 15, Center 124 (59 ~ 190) 132
3675 22:17:25.919503 ==
3676 22:17:25.922926 Dram Type= 6, Freq= 0, CH_1, rank 1
3677 22:17:25.925646 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3678 22:17:25.925737 ==
3679 22:17:25.925824 DQS Delay:
3680 22:17:25.928942 DQS0 = 0, DQS1 = 0
3681 22:17:25.929030 DQM Delay:
3682 22:17:25.932448 DQM0 = 119, DQM1 = 113
3683 22:17:25.932537 DQ Delay:
3684 22:17:25.935670 DQ0 =122, DQ1 =114, DQ2 =108, DQ3 =116
3685 22:17:25.938981 DQ4 =120, DQ5 =130, DQ6 =126, DQ7 =116
3686 22:17:25.942530 DQ8 =98, DQ9 =102, DQ10 =114, DQ11 =108
3687 22:17:25.945627 DQ12 =122, DQ13 =118, DQ14 =122, DQ15 =124
3688 22:17:25.949086
3689 22:17:25.949177
3690 22:17:25.955628 [DQSOSCAuto] RK1, (LSB)MR18= 0xbf0, (MSB)MR19= 0x403, tDQSOscB0 = 416 ps tDQSOscB1 = 405 ps
3691 22:17:25.958966 CH1 RK1: MR19=403, MR18=BF0
3692 22:17:25.965849 CH1_RK1: MR19=0x403, MR18=0xBF0, DQSOSC=405, MR23=63, INC=39, DEC=26
3693 22:17:25.968791 [RxdqsGatingPostProcess] freq 1200
3694 22:17:25.972078 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3695 22:17:25.975218 best DQS0 dly(2T, 0.5T) = (0, 11)
3696 22:17:25.978618 best DQS1 dly(2T, 0.5T) = (0, 11)
3697 22:17:25.982063 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3698 22:17:25.985431 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3699 22:17:25.988377 best DQS0 dly(2T, 0.5T) = (0, 11)
3700 22:17:25.991796 best DQS1 dly(2T, 0.5T) = (0, 11)
3701 22:17:25.995323 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3702 22:17:25.998320 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3703 22:17:26.001831 Pre-setting of DQS Precalculation
3704 22:17:26.004813 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3705 22:17:26.014870 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3706 22:17:26.021261 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3707 22:17:26.021375
3708 22:17:26.021465
3709 22:17:26.024696 [Calibration Summary] 2400 Mbps
3710 22:17:26.024790 CH 0, Rank 0
3711 22:17:26.028163 SW Impedance : PASS
3712 22:17:26.028256 DUTY Scan : NO K
3713 22:17:26.031234 ZQ Calibration : PASS
3714 22:17:26.034718 Jitter Meter : NO K
3715 22:17:26.034813 CBT Training : PASS
3716 22:17:26.038120 Write leveling : PASS
3717 22:17:26.041398 RX DQS gating : PASS
3718 22:17:26.041491 RX DQ/DQS(RDDQC) : PASS
3719 22:17:26.044700 TX DQ/DQS : PASS
3720 22:17:26.047732 RX DATLAT : PASS
3721 22:17:26.047825 RX DQ/DQS(Engine): PASS
3722 22:17:26.051053 TX OE : NO K
3723 22:17:26.051145 All Pass.
3724 22:17:26.051232
3725 22:17:26.054354 CH 0, Rank 1
3726 22:17:26.054441 SW Impedance : PASS
3727 22:17:26.057801 DUTY Scan : NO K
3728 22:17:26.060990 ZQ Calibration : PASS
3729 22:17:26.061081 Jitter Meter : NO K
3730 22:17:26.064524 CBT Training : PASS
3731 22:17:26.064611 Write leveling : PASS
3732 22:17:26.067664 RX DQS gating : PASS
3733 22:17:26.070794 RX DQ/DQS(RDDQC) : PASS
3734 22:17:26.070884 TX DQ/DQS : PASS
3735 22:17:26.074026 RX DATLAT : PASS
3736 22:17:26.077572 RX DQ/DQS(Engine): PASS
3737 22:17:26.077664 TX OE : NO K
3738 22:17:26.081087 All Pass.
3739 22:17:26.081173
3740 22:17:26.081238 CH 1, Rank 0
3741 22:17:26.084305 SW Impedance : PASS
3742 22:17:26.084395 DUTY Scan : NO K
3743 22:17:26.087496 ZQ Calibration : PASS
3744 22:17:26.090698 Jitter Meter : NO K
3745 22:17:26.090786 CBT Training : PASS
3746 22:17:26.093814 Write leveling : PASS
3747 22:17:26.097361 RX DQS gating : PASS
3748 22:17:26.097454 RX DQ/DQS(RDDQC) : PASS
3749 22:17:26.100494 TX DQ/DQS : PASS
3750 22:17:26.103782 RX DATLAT : PASS
3751 22:17:26.103868 RX DQ/DQS(Engine): PASS
3752 22:17:26.107347 TX OE : NO K
3753 22:17:26.107433 All Pass.
3754 22:17:26.107498
3755 22:17:26.110453 CH 1, Rank 1
3756 22:17:26.110537 SW Impedance : PASS
3757 22:17:26.113784 DUTY Scan : NO K
3758 22:17:26.116958 ZQ Calibration : PASS
3759 22:17:26.117045 Jitter Meter : NO K
3760 22:17:26.120222 CBT Training : PASS
3761 22:17:26.123778 Write leveling : PASS
3762 22:17:26.123863 RX DQS gating : PASS
3763 22:17:26.126957 RX DQ/DQS(RDDQC) : PASS
3764 22:17:26.130065 TX DQ/DQS : PASS
3765 22:17:26.130153 RX DATLAT : PASS
3766 22:17:26.133180 RX DQ/DQS(Engine): PASS
3767 22:17:26.136722 TX OE : NO K
3768 22:17:26.136834 All Pass.
3769 22:17:26.136902
3770 22:17:26.136961 DramC Write-DBI off
3771 22:17:26.139865 PER_BANK_REFRESH: Hybrid Mode
3772 22:17:26.143172 TX_TRACKING: ON
3773 22:17:26.149935 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3774 22:17:26.152897 [FAST_K] Save calibration result to emmc
3775 22:17:26.159698 dramc_set_vcore_voltage set vcore to 650000
3776 22:17:26.159818 Read voltage for 600, 5
3777 22:17:26.162838 Vio18 = 0
3778 22:17:26.162926 Vcore = 650000
3779 22:17:26.162993 Vdram = 0
3780 22:17:26.166053 Vddq = 0
3781 22:17:26.166139 Vmddr = 0
3782 22:17:26.169408 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3783 22:17:26.176031 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3784 22:17:26.179152 MEM_TYPE=3, freq_sel=19
3785 22:17:26.182704 sv_algorithm_assistance_LP4_1600
3786 22:17:26.185669 ============ PULL DRAM RESETB DOWN ============
3787 22:17:26.189127 ========== PULL DRAM RESETB DOWN end =========
3788 22:17:26.195629 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3789 22:17:26.199139 ===================================
3790 22:17:26.199239 LPDDR4 DRAM CONFIGURATION
3791 22:17:26.202364 ===================================
3792 22:17:26.205516 EX_ROW_EN[0] = 0x0
3793 22:17:26.205603 EX_ROW_EN[1] = 0x0
3794 22:17:26.208915 LP4Y_EN = 0x0
3795 22:17:26.212242 WORK_FSP = 0x0
3796 22:17:26.212330 WL = 0x2
3797 22:17:26.215591 RL = 0x2
3798 22:17:26.215678 BL = 0x2
3799 22:17:26.218684 RPST = 0x0
3800 22:17:26.218769 RD_PRE = 0x0
3801 22:17:26.222295 WR_PRE = 0x1
3802 22:17:26.222379 WR_PST = 0x0
3803 22:17:26.225422 DBI_WR = 0x0
3804 22:17:26.225507 DBI_RD = 0x0
3805 22:17:26.228806 OTF = 0x1
3806 22:17:26.231987 ===================================
3807 22:17:26.235512 ===================================
3808 22:17:26.235600 ANA top config
3809 22:17:26.238590 ===================================
3810 22:17:26.242106 DLL_ASYNC_EN = 0
3811 22:17:26.245221 ALL_SLAVE_EN = 1
3812 22:17:26.245310 NEW_RANK_MODE = 1
3813 22:17:26.248563 DLL_IDLE_MODE = 1
3814 22:17:26.252055 LP45_APHY_COMB_EN = 1
3815 22:17:26.255212 TX_ODT_DIS = 1
3816 22:17:26.258428 NEW_8X_MODE = 1
3817 22:17:26.261787 ===================================
3818 22:17:26.265188 ===================================
3819 22:17:26.268368 data_rate = 1200
3820 22:17:26.268457 CKR = 1
3821 22:17:26.271626 DQ_P2S_RATIO = 8
3822 22:17:26.275216 ===================================
3823 22:17:26.278341 CA_P2S_RATIO = 8
3824 22:17:26.281724 DQ_CA_OPEN = 0
3825 22:17:26.284803 DQ_SEMI_OPEN = 0
3826 22:17:26.288465 CA_SEMI_OPEN = 0
3827 22:17:26.288548 CA_FULL_RATE = 0
3828 22:17:26.291707 DQ_CKDIV4_EN = 1
3829 22:17:26.295006 CA_CKDIV4_EN = 1
3830 22:17:26.298003 CA_PREDIV_EN = 0
3831 22:17:26.301548 PH8_DLY = 0
3832 22:17:26.305028 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3833 22:17:26.305111 DQ_AAMCK_DIV = 4
3834 22:17:26.308135 CA_AAMCK_DIV = 4
3835 22:17:26.311359 CA_ADMCK_DIV = 4
3836 22:17:26.314449 DQ_TRACK_CA_EN = 0
3837 22:17:26.318029 CA_PICK = 600
3838 22:17:26.321392 CA_MCKIO = 600
3839 22:17:26.321475 MCKIO_SEMI = 0
3840 22:17:26.324508 PLL_FREQ = 2288
3841 22:17:26.327992 DQ_UI_PI_RATIO = 32
3842 22:17:26.331249 CA_UI_PI_RATIO = 0
3843 22:17:26.334699 ===================================
3844 22:17:26.337920 ===================================
3845 22:17:26.341326 memory_type:LPDDR4
3846 22:17:26.341414 GP_NUM : 10
3847 22:17:26.344590 SRAM_EN : 1
3848 22:17:26.347615 MD32_EN : 0
3849 22:17:26.351079 ===================================
3850 22:17:26.351162 [ANA_INIT] >>>>>>>>>>>>>>
3851 22:17:26.354308 <<<<<< [CONFIGURE PHASE]: ANA_TX
3852 22:17:26.357646 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3853 22:17:26.361147 ===================================
3854 22:17:26.364450 data_rate = 1200,PCW = 0X5800
3855 22:17:26.368018 ===================================
3856 22:17:26.370765 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3857 22:17:26.377710 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3858 22:17:26.380809 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3859 22:17:26.387120 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3860 22:17:26.390765 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3861 22:17:26.394015 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3862 22:17:26.397069 [ANA_INIT] flow start
3863 22:17:26.397152 [ANA_INIT] PLL >>>>>>>>
3864 22:17:26.400551 [ANA_INIT] PLL <<<<<<<<
3865 22:17:26.403703 [ANA_INIT] MIDPI >>>>>>>>
3866 22:17:26.403785 [ANA_INIT] MIDPI <<<<<<<<
3867 22:17:26.406845 [ANA_INIT] DLL >>>>>>>>
3868 22:17:26.410475 [ANA_INIT] flow end
3869 22:17:26.413465 ============ LP4 DIFF to SE enter ============
3870 22:17:26.417066 ============ LP4 DIFF to SE exit ============
3871 22:17:26.420348 [ANA_INIT] <<<<<<<<<<<<<
3872 22:17:26.423484 [Flow] Enable top DCM control >>>>>
3873 22:17:26.426895 [Flow] Enable top DCM control <<<<<
3874 22:17:26.429942 Enable DLL master slave shuffle
3875 22:17:26.433385 ==============================================================
3876 22:17:26.436568 Gating Mode config
3877 22:17:26.443050 ==============================================================
3878 22:17:26.443135 Config description:
3879 22:17:26.452906 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3880 22:17:26.459752 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3881 22:17:26.466134 SELPH_MODE 0: By rank 1: By Phase
3882 22:17:26.469305 ==============================================================
3883 22:17:26.472951 GAT_TRACK_EN = 1
3884 22:17:26.475913 RX_GATING_MODE = 2
3885 22:17:26.479586 RX_GATING_TRACK_MODE = 2
3886 22:17:26.482842 SELPH_MODE = 1
3887 22:17:26.485991 PICG_EARLY_EN = 1
3888 22:17:26.489190 VALID_LAT_VALUE = 1
3889 22:17:26.495754 ==============================================================
3890 22:17:26.499276 Enter into Gating configuration >>>>
3891 22:17:26.502307 Exit from Gating configuration <<<<
3892 22:17:26.502391 Enter into DVFS_PRE_config >>>>>
3893 22:17:26.515629 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3894 22:17:26.518874 Exit from DVFS_PRE_config <<<<<
3895 22:17:26.522578 Enter into PICG configuration >>>>
3896 22:17:26.525592 Exit from PICG configuration <<<<
3897 22:17:26.525677 [RX_INPUT] configuration >>>>>
3898 22:17:26.529102 [RX_INPUT] configuration <<<<<
3899 22:17:26.535857 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3900 22:17:26.538979 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3901 22:17:26.545557 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3902 22:17:26.552371 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3903 22:17:26.558565 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3904 22:17:26.565120 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3905 22:17:26.568550 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3906 22:17:26.571902 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3907 22:17:26.578396 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3908 22:17:26.581870 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3909 22:17:26.585184 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3910 22:17:26.591498 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3911 22:17:26.595160 ===================================
3912 22:17:26.595244 LPDDR4 DRAM CONFIGURATION
3913 22:17:26.598198 ===================================
3914 22:17:26.601751 EX_ROW_EN[0] = 0x0
3915 22:17:26.601833 EX_ROW_EN[1] = 0x0
3916 22:17:26.605006 LP4Y_EN = 0x0
3917 22:17:26.605087 WORK_FSP = 0x0
3918 22:17:26.608504 WL = 0x2
3919 22:17:26.611634 RL = 0x2
3920 22:17:26.611715 BL = 0x2
3921 22:17:26.614690 RPST = 0x0
3922 22:17:26.614786 RD_PRE = 0x0
3923 22:17:26.618213 WR_PRE = 0x1
3924 22:17:26.618294 WR_PST = 0x0
3925 22:17:26.621306 DBI_WR = 0x0
3926 22:17:26.621402 DBI_RD = 0x0
3927 22:17:26.624827 OTF = 0x1
3928 22:17:26.627895 ===================================
3929 22:17:26.631301 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3930 22:17:26.634336 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3931 22:17:26.641026 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3932 22:17:26.644639 ===================================
3933 22:17:26.644736 LPDDR4 DRAM CONFIGURATION
3934 22:17:26.647798 ===================================
3935 22:17:26.650896 EX_ROW_EN[0] = 0x10
3936 22:17:26.654569 EX_ROW_EN[1] = 0x0
3937 22:17:26.654650 LP4Y_EN = 0x0
3938 22:17:26.657677 WORK_FSP = 0x0
3939 22:17:26.657758 WL = 0x2
3940 22:17:26.660686 RL = 0x2
3941 22:17:26.660772 BL = 0x2
3942 22:17:26.663981 RPST = 0x0
3943 22:17:26.664061 RD_PRE = 0x0
3944 22:17:26.667526 WR_PRE = 0x1
3945 22:17:26.667606 WR_PST = 0x0
3946 22:17:26.670768 DBI_WR = 0x0
3947 22:17:26.670848 DBI_RD = 0x0
3948 22:17:26.674334 OTF = 0x1
3949 22:17:26.677576 ===================================
3950 22:17:26.683943 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3951 22:17:26.687449 nWR fixed to 30
3952 22:17:26.687531 [ModeRegInit_LP4] CH0 RK0
3953 22:17:26.690795 [ModeRegInit_LP4] CH0 RK1
3954 22:17:26.693849 [ModeRegInit_LP4] CH1 RK0
3955 22:17:26.697390 [ModeRegInit_LP4] CH1 RK1
3956 22:17:26.697486 match AC timing 17
3957 22:17:26.704041 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3958 22:17:26.707430 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3959 22:17:26.710400 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3960 22:17:26.716997 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3961 22:17:26.720428 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3962 22:17:26.720512 ==
3963 22:17:26.723588 Dram Type= 6, Freq= 0, CH_0, rank 0
3964 22:17:26.727106 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3965 22:17:26.727189 ==
3966 22:17:26.733457 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3967 22:17:26.740412 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3968 22:17:26.743484 [CA 0] Center 36 (5~67) winsize 63
3969 22:17:26.746940 [CA 1] Center 36 (6~67) winsize 62
3970 22:17:26.750081 [CA 2] Center 34 (4~65) winsize 62
3971 22:17:26.753312 [CA 3] Center 34 (3~65) winsize 63
3972 22:17:26.756718 [CA 4] Center 33 (3~64) winsize 62
3973 22:17:26.760260 [CA 5] Center 33 (3~64) winsize 62
3974 22:17:26.760343
3975 22:17:26.763538 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3976 22:17:26.763621
3977 22:17:26.766672 [CATrainingPosCal] consider 1 rank data
3978 22:17:26.769727 u2DelayCellTimex100 = 270/100 ps
3979 22:17:26.773290 CA0 delay=36 (5~67),Diff = 3 PI (28 cell)
3980 22:17:26.776282 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3981 22:17:26.779586 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3982 22:17:26.782914 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
3983 22:17:26.786498 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3984 22:17:26.789640 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3985 22:17:26.792978
3986 22:17:26.796321 CA PerBit enable=1, Macro0, CA PI delay=33
3987 22:17:26.796403
3988 22:17:26.799828 [CBTSetCACLKResult] CA Dly = 33
3989 22:17:26.799914 CS Dly: 5 (0~36)
3990 22:17:26.800000 ==
3991 22:17:26.802831 Dram Type= 6, Freq= 0, CH_0, rank 1
3992 22:17:26.806115 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3993 22:17:26.806203 ==
3994 22:17:26.812747 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3995 22:17:26.819429 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3996 22:17:26.822938 [CA 0] Center 36 (6~67) winsize 62
3997 22:17:26.825900 [CA 1] Center 36 (6~67) winsize 62
3998 22:17:26.829584 [CA 2] Center 35 (5~66) winsize 62
3999 22:17:26.832579 [CA 3] Center 35 (4~66) winsize 63
4000 22:17:26.835986 [CA 4] Center 34 (3~65) winsize 63
4001 22:17:26.839103 [CA 5] Center 33 (3~64) winsize 62
4002 22:17:26.839186
4003 22:17:26.842579 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4004 22:17:26.842661
4005 22:17:26.845692 [CATrainingPosCal] consider 2 rank data
4006 22:17:26.849316 u2DelayCellTimex100 = 270/100 ps
4007 22:17:26.852363 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
4008 22:17:26.855664 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
4009 22:17:26.859144 CA2 delay=35 (5~65),Diff = 2 PI (19 cell)
4010 22:17:26.865834 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4011 22:17:26.869239 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4012 22:17:26.872331 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4013 22:17:26.872414
4014 22:17:26.875626 CA PerBit enable=1, Macro0, CA PI delay=33
4015 22:17:26.875716
4016 22:17:26.878752 [CBTSetCACLKResult] CA Dly = 33
4017 22:17:26.878835 CS Dly: 5 (0~37)
4018 22:17:26.878900
4019 22:17:26.882323 ----->DramcWriteLeveling(PI) begin...
4020 22:17:26.882407 ==
4021 22:17:26.885675 Dram Type= 6, Freq= 0, CH_0, rank 0
4022 22:17:26.892176 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4023 22:17:26.892260 ==
4024 22:17:26.895338 Write leveling (Byte 0): 34 => 34
4025 22:17:26.898738 Write leveling (Byte 1): 27 => 27
4026 22:17:26.902278 DramcWriteLeveling(PI) end<-----
4027 22:17:26.902360
4028 22:17:26.902425 ==
4029 22:17:26.905421 Dram Type= 6, Freq= 0, CH_0, rank 0
4030 22:17:26.908751 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4031 22:17:26.908845 ==
4032 22:17:26.912028 [Gating] SW mode calibration
4033 22:17:26.918388 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4034 22:17:26.925409 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4035 22:17:26.928305 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4036 22:17:26.931767 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4037 22:17:26.935414 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (0 0)
4038 22:17:26.941829 0 9 12 | B1->B0 | 3434 2e2e | 1 0 | (1 1) (1 1)
4039 22:17:26.944837 0 9 16 | B1->B0 | 2d2d 2323 | 0 0 | (0 0) (0 0)
4040 22:17:26.948205 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4041 22:17:26.954832 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4042 22:17:26.958505 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4043 22:17:26.961646 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4044 22:17:26.968128 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4045 22:17:26.971262 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4046 22:17:26.974909 0 10 12 | B1->B0 | 2b2b 3838 | 0 1 | (0 0) (0 0)
4047 22:17:26.981406 0 10 16 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
4048 22:17:26.984688 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4049 22:17:26.988088 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4050 22:17:26.994676 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4051 22:17:26.997784 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4052 22:17:27.001326 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4053 22:17:27.007623 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4054 22:17:27.011456 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4055 22:17:27.014454 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4056 22:17:27.021232 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4057 22:17:27.024279 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4058 22:17:27.027632 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4059 22:17:27.034098 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4060 22:17:27.037754 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4061 22:17:27.040901 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4062 22:17:27.047471 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4063 22:17:27.050765 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4064 22:17:27.053844 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4065 22:17:27.060532 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4066 22:17:27.064001 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4067 22:17:27.067091 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4068 22:17:27.073729 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4069 22:17:27.077416 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4070 22:17:27.080668 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4071 22:17:27.087168 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4072 22:17:27.090300 Total UI for P1: 0, mck2ui 16
4073 22:17:27.093608 best dqsien dly found for B0: ( 0, 13, 12)
4074 22:17:27.097073 Total UI for P1: 0, mck2ui 16
4075 22:17:27.100192 best dqsien dly found for B1: ( 0, 13, 12)
4076 22:17:27.103729 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4077 22:17:27.107017 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4078 22:17:27.107100
4079 22:17:27.109956 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4080 22:17:27.113347 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4081 22:17:27.116693 [Gating] SW calibration Done
4082 22:17:27.116781 ==
4083 22:17:27.119850 Dram Type= 6, Freq= 0, CH_0, rank 0
4084 22:17:27.123235 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4085 22:17:27.123318 ==
4086 22:17:27.126613 RX Vref Scan: 0
4087 22:17:27.126696
4088 22:17:27.129775 RX Vref 0 -> 0, step: 1
4089 22:17:27.129858
4090 22:17:27.129923 RX Delay -230 -> 252, step: 16
4091 22:17:27.136522 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4092 22:17:27.139735 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4093 22:17:27.143290 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4094 22:17:27.146428 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4095 22:17:27.152891 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4096 22:17:27.156337 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4097 22:17:27.159895 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4098 22:17:27.162859 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4099 22:17:27.169582 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4100 22:17:27.172795 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4101 22:17:27.176436 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4102 22:17:27.179487 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4103 22:17:27.185985 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4104 22:17:27.189065 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4105 22:17:27.192478 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4106 22:17:27.195637 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4107 22:17:27.195722 ==
4108 22:17:27.199073 Dram Type= 6, Freq= 0, CH_0, rank 0
4109 22:17:27.205565 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4110 22:17:27.205650 ==
4111 22:17:27.205716 DQS Delay:
4112 22:17:27.209061 DQS0 = 0, DQS1 = 0
4113 22:17:27.209143 DQM Delay:
4114 22:17:27.209207 DQM0 = 52, DQM1 = 38
4115 22:17:27.212306 DQ Delay:
4116 22:17:27.215748 DQ0 =49, DQ1 =57, DQ2 =49, DQ3 =41
4117 22:17:27.218725 DQ4 =57, DQ5 =41, DQ6 =65, DQ7 =57
4118 22:17:27.222210 DQ8 =33, DQ9 =25, DQ10 =41, DQ11 =33
4119 22:17:27.225539 DQ12 =41, DQ13 =41, DQ14 =49, DQ15 =41
4120 22:17:27.225653
4121 22:17:27.225776
4122 22:17:27.225854 ==
4123 22:17:27.228691 Dram Type= 6, Freq= 0, CH_0, rank 0
4124 22:17:27.232369 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4125 22:17:27.232451 ==
4126 22:17:27.232516
4127 22:17:27.232576
4128 22:17:27.235561 TX Vref Scan disable
4129 22:17:27.238632 == TX Byte 0 ==
4130 22:17:27.241903 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4131 22:17:27.245324 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4132 22:17:27.248623 == TX Byte 1 ==
4133 22:17:27.251971 Update DQ dly =571 (2 ,1, 27) DQ OEN =(1 ,6)
4134 22:17:27.255359 Update DQM dly =571 (2 ,1, 27) DQM OEN =(1 ,6)
4135 22:17:27.255443 ==
4136 22:17:27.258722 Dram Type= 6, Freq= 0, CH_0, rank 0
4137 22:17:27.261868 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4138 22:17:27.265136 ==
4139 22:17:27.265235
4140 22:17:27.265314
4141 22:17:27.265375 TX Vref Scan disable
4142 22:17:27.269415 == TX Byte 0 ==
4143 22:17:27.272643 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4144 22:17:27.279030 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4145 22:17:27.279156 == TX Byte 1 ==
4146 22:17:27.282507 Update DQ dly =571 (2 ,1, 27) DQ OEN =(1 ,6)
4147 22:17:27.288860 Update DQM dly =571 (2 ,1, 27) DQM OEN =(1 ,6)
4148 22:17:27.289003
4149 22:17:27.289071 [DATLAT]
4150 22:17:27.289133 Freq=600, CH0 RK0
4151 22:17:27.289193
4152 22:17:27.292499 DATLAT Default: 0x9
4153 22:17:27.292598 0, 0xFFFF, sum = 0
4154 22:17:27.295687 1, 0xFFFF, sum = 0
4155 22:17:27.298862 2, 0xFFFF, sum = 0
4156 22:17:27.298949 3, 0xFFFF, sum = 0
4157 22:17:27.302114 4, 0xFFFF, sum = 0
4158 22:17:27.302200 5, 0xFFFF, sum = 0
4159 22:17:27.305603 6, 0xFFFF, sum = 0
4160 22:17:27.305691 7, 0xFFFF, sum = 0
4161 22:17:27.308708 8, 0x0, sum = 1
4162 22:17:27.308829 9, 0x0, sum = 2
4163 22:17:27.311815 10, 0x0, sum = 3
4164 22:17:27.311905 11, 0x0, sum = 4
4165 22:17:27.311973 best_step = 9
4166 22:17:27.312069
4167 22:17:27.315435 ==
4168 22:17:27.318397 Dram Type= 6, Freq= 0, CH_0, rank 0
4169 22:17:27.321881 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4170 22:17:27.321970 ==
4171 22:17:27.322102 RX Vref Scan: 1
4172 22:17:27.322163
4173 22:17:27.325399 RX Vref 0 -> 0, step: 1
4174 22:17:27.325483
4175 22:17:27.328595 RX Delay -179 -> 252, step: 8
4176 22:17:27.328706
4177 22:17:27.331676 Set Vref, RX VrefLevel [Byte0]: 57
4178 22:17:27.335270 [Byte1]: 49
4179 22:17:27.335355
4180 22:17:27.338089 Final RX Vref Byte 0 = 57 to rank0
4181 22:17:27.341593 Final RX Vref Byte 1 = 49 to rank0
4182 22:17:27.345151 Final RX Vref Byte 0 = 57 to rank1
4183 22:17:27.348208 Final RX Vref Byte 1 = 49 to rank1==
4184 22:17:27.351533 Dram Type= 6, Freq= 0, CH_0, rank 0
4185 22:17:27.354902 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4186 22:17:27.358426 ==
4187 22:17:27.358513 DQS Delay:
4188 22:17:27.358581 DQS0 = 0, DQS1 = 0
4189 22:17:27.361264 DQM Delay:
4190 22:17:27.361374 DQM0 = 48, DQM1 = 39
4191 22:17:27.364923 DQ Delay:
4192 22:17:27.365052 DQ0 =48, DQ1 =48, DQ2 =44, DQ3 =44
4193 22:17:27.368343 DQ4 =52, DQ5 =40, DQ6 =56, DQ7 =56
4194 22:17:27.371519 DQ8 =36, DQ9 =24, DQ10 =36, DQ11 =32
4195 22:17:27.374749 DQ12 =44, DQ13 =40, DQ14 =52, DQ15 =48
4196 22:17:27.378219
4197 22:17:27.378329
4198 22:17:27.384854 [DQSOSCAuto] RK0, (LSB)MR18= 0x5d57, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 392 ps
4199 22:17:27.387807 CH0 RK0: MR19=808, MR18=5D57
4200 22:17:27.394462 CH0_RK0: MR19=0x808, MR18=0x5D57, DQSOSC=392, MR23=63, INC=170, DEC=113
4201 22:17:27.394591
4202 22:17:27.397875 ----->DramcWriteLeveling(PI) begin...
4203 22:17:27.398021 ==
4204 22:17:27.401007 Dram Type= 6, Freq= 0, CH_0, rank 1
4205 22:17:27.404485 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4206 22:17:27.404588 ==
4207 22:17:27.407520 Write leveling (Byte 0): 31 => 31
4208 22:17:27.410921 Write leveling (Byte 1): 29 => 29
4209 22:17:27.414068 DramcWriteLeveling(PI) end<-----
4210 22:17:27.414174
4211 22:17:27.414269 ==
4212 22:17:27.417831 Dram Type= 6, Freq= 0, CH_0, rank 1
4213 22:17:27.420959 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4214 22:17:27.421051 ==
4215 22:17:27.423997 [Gating] SW mode calibration
4216 22:17:27.430898 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4217 22:17:27.437597 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4218 22:17:27.440927 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4219 22:17:27.447358 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4220 22:17:27.450776 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4221 22:17:27.453960 0 9 12 | B1->B0 | 3333 3232 | 0 0 | (0 0) (0 1)
4222 22:17:27.460676 0 9 16 | B1->B0 | 2c2c 2323 | 0 0 | (0 0) (0 0)
4223 22:17:27.464022 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4224 22:17:27.467316 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4225 22:17:27.474216 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4226 22:17:27.477260 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4227 22:17:27.480283 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4228 22:17:27.484100 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4229 22:17:27.490196 0 10 12 | B1->B0 | 2d2d 3231 | 1 1 | (0 0) (0 0)
4230 22:17:27.493470 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4231 22:17:27.500407 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4232 22:17:27.503479 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4233 22:17:27.506688 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4234 22:17:27.513509 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4235 22:17:27.516578 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4236 22:17:27.520208 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4237 22:17:27.523235 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4238 22:17:27.530112 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4239 22:17:27.533242 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4240 22:17:27.536586 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4241 22:17:27.543061 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4242 22:17:27.546181 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4243 22:17:27.549615 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4244 22:17:27.556159 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4245 22:17:27.559437 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4246 22:17:27.566342 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4247 22:17:27.569308 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4248 22:17:27.572891 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4249 22:17:27.576263 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4250 22:17:27.582891 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4251 22:17:27.585871 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4252 22:17:27.589403 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4253 22:17:27.595914 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4254 22:17:27.599016 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4255 22:17:27.602369 Total UI for P1: 0, mck2ui 16
4256 22:17:27.605789 best dqsien dly found for B0: ( 0, 13, 12)
4257 22:17:27.609342 Total UI for P1: 0, mck2ui 16
4258 22:17:27.612305 best dqsien dly found for B1: ( 0, 13, 12)
4259 22:17:27.615723 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4260 22:17:27.619326 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4261 22:17:27.619412
4262 22:17:27.622335 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4263 22:17:27.629044 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4264 22:17:27.629128 [Gating] SW calibration Done
4265 22:17:27.629195 ==
4266 22:17:27.632531 Dram Type= 6, Freq= 0, CH_0, rank 1
4267 22:17:27.638903 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4268 22:17:27.638991 ==
4269 22:17:27.639058 RX Vref Scan: 0
4270 22:17:27.639119
4271 22:17:27.642244 RX Vref 0 -> 0, step: 1
4272 22:17:27.642328
4273 22:17:27.645641 RX Delay -230 -> 252, step: 16
4274 22:17:27.648692 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4275 22:17:27.652202 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4276 22:17:27.658491 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4277 22:17:27.662048 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4278 22:17:27.665434 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4279 22:17:27.668897 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4280 22:17:27.671702 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4281 22:17:27.678637 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4282 22:17:27.681927 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4283 22:17:27.685348 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4284 22:17:27.688256 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4285 22:17:27.695016 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4286 22:17:27.698055 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4287 22:17:27.701657 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4288 22:17:27.705181 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4289 22:17:27.711507 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4290 22:17:27.711594 ==
4291 22:17:27.714589 Dram Type= 6, Freq= 0, CH_0, rank 1
4292 22:17:27.717912 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4293 22:17:27.717996 ==
4294 22:17:27.718062 DQS Delay:
4295 22:17:27.721456 DQS0 = 0, DQS1 = 0
4296 22:17:27.721540 DQM Delay:
4297 22:17:27.724541 DQM0 = 48, DQM1 = 42
4298 22:17:27.724623 DQ Delay:
4299 22:17:27.728088 DQ0 =49, DQ1 =49, DQ2 =41, DQ3 =41
4300 22:17:27.731244 DQ4 =49, DQ5 =41, DQ6 =57, DQ7 =57
4301 22:17:27.734767 DQ8 =33, DQ9 =25, DQ10 =41, DQ11 =41
4302 22:17:27.737743 DQ12 =41, DQ13 =49, DQ14 =57, DQ15 =49
4303 22:17:27.737828
4304 22:17:27.737893
4305 22:17:27.737954 ==
4306 22:17:27.741241 Dram Type= 6, Freq= 0, CH_0, rank 1
4307 22:17:27.744558 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4308 22:17:27.747805 ==
4309 22:17:27.747890
4310 22:17:27.747956
4311 22:17:27.748016 TX Vref Scan disable
4312 22:17:27.751141 == TX Byte 0 ==
4313 22:17:27.754204 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4314 22:17:27.757789 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4315 22:17:27.760924 == TX Byte 1 ==
4316 22:17:27.764196 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4317 22:17:27.767718 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4318 22:17:27.771009 ==
4319 22:17:27.774622 Dram Type= 6, Freq= 0, CH_0, rank 1
4320 22:17:27.777571 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4321 22:17:27.777656 ==
4322 22:17:27.777722
4323 22:17:27.777783
4324 22:17:27.780961 TX Vref Scan disable
4325 22:17:27.781045 == TX Byte 0 ==
4326 22:17:27.787315 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4327 22:17:27.790617 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4328 22:17:27.794233 == TX Byte 1 ==
4329 22:17:27.797433 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4330 22:17:27.800571 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4331 22:17:27.800657
4332 22:17:27.800723 [DATLAT]
4333 22:17:27.804235 Freq=600, CH0 RK1
4334 22:17:27.804319
4335 22:17:27.804386 DATLAT Default: 0x9
4336 22:17:27.807244 0, 0xFFFF, sum = 0
4337 22:17:27.810724 1, 0xFFFF, sum = 0
4338 22:17:27.810811 2, 0xFFFF, sum = 0
4339 22:17:27.814206 3, 0xFFFF, sum = 0
4340 22:17:27.814292 4, 0xFFFF, sum = 0
4341 22:17:27.817216 5, 0xFFFF, sum = 0
4342 22:17:27.817302 6, 0xFFFF, sum = 0
4343 22:17:27.820750 7, 0xFFFF, sum = 0
4344 22:17:27.820841 8, 0x0, sum = 1
4345 22:17:27.823980 9, 0x0, sum = 2
4346 22:17:27.824065 10, 0x0, sum = 3
4347 22:17:27.824132 11, 0x0, sum = 4
4348 22:17:27.827082 best_step = 9
4349 22:17:27.827166
4350 22:17:27.827231 ==
4351 22:17:27.830665 Dram Type= 6, Freq= 0, CH_0, rank 1
4352 22:17:27.833737 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4353 22:17:27.833822 ==
4354 22:17:27.836785 RX Vref Scan: 0
4355 22:17:27.836868
4356 22:17:27.840445 RX Vref 0 -> 0, step: 1
4357 22:17:27.840529
4358 22:17:27.840595 RX Delay -179 -> 252, step: 8
4359 22:17:27.848135 iDelay=205, Bit 0, Center 48 (-99 ~ 196) 296
4360 22:17:27.851067 iDelay=205, Bit 1, Center 48 (-99 ~ 196) 296
4361 22:17:27.854384 iDelay=205, Bit 2, Center 44 (-99 ~ 188) 288
4362 22:17:27.858045 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4363 22:17:27.864100 iDelay=205, Bit 4, Center 48 (-99 ~ 196) 296
4364 22:17:27.867940 iDelay=205, Bit 5, Center 40 (-107 ~ 188) 296
4365 22:17:27.871057 iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288
4366 22:17:27.874229 iDelay=205, Bit 7, Center 52 (-91 ~ 196) 288
4367 22:17:27.877690 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4368 22:17:27.884302 iDelay=205, Bit 9, Center 28 (-115 ~ 172) 288
4369 22:17:27.887763 iDelay=205, Bit 10, Center 40 (-107 ~ 188) 296
4370 22:17:27.890889 iDelay=205, Bit 11, Center 36 (-107 ~ 180) 288
4371 22:17:27.893985 iDelay=205, Bit 12, Center 48 (-99 ~ 196) 296
4372 22:17:27.900574 iDelay=205, Bit 13, Center 44 (-99 ~ 188) 288
4373 22:17:27.903830 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4374 22:17:27.907264 iDelay=205, Bit 15, Center 48 (-99 ~ 196) 296
4375 22:17:27.907348 ==
4376 22:17:27.910422 Dram Type= 6, Freq= 0, CH_0, rank 1
4377 22:17:27.913968 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4378 22:17:27.914052 ==
4379 22:17:27.916993 DQS Delay:
4380 22:17:27.917076 DQS0 = 0, DQS1 = 0
4381 22:17:27.920545 DQM Delay:
4382 22:17:27.920627 DQM0 = 48, DQM1 = 40
4383 22:17:27.923665 DQ Delay:
4384 22:17:27.923747 DQ0 =48, DQ1 =48, DQ2 =44, DQ3 =44
4385 22:17:27.926925 DQ4 =48, DQ5 =40, DQ6 =60, DQ7 =52
4386 22:17:27.930505 DQ8 =32, DQ9 =28, DQ10 =40, DQ11 =36
4387 22:17:27.933581 DQ12 =48, DQ13 =44, DQ14 =48, DQ15 =48
4388 22:17:27.936656
4389 22:17:27.936739
4390 22:17:27.943387 [DQSOSCAuto] RK1, (LSB)MR18= 0x5e2d, (MSB)MR19= 0x808, tDQSOscB0 = 401 ps tDQSOscB1 = 392 ps
4391 22:17:27.946872 CH0 RK1: MR19=808, MR18=5E2D
4392 22:17:27.953265 CH0_RK1: MR19=0x808, MR18=0x5E2D, DQSOSC=392, MR23=63, INC=170, DEC=113
4393 22:17:27.956534 [RxdqsGatingPostProcess] freq 600
4394 22:17:27.960063 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4395 22:17:27.963378 Pre-setting of DQS Precalculation
4396 22:17:27.969887 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4397 22:17:27.969980 ==
4398 22:17:27.973421 Dram Type= 6, Freq= 0, CH_1, rank 0
4399 22:17:27.976580 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4400 22:17:27.976692 ==
4401 22:17:27.983142 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4402 22:17:27.986484 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4403 22:17:27.990786 [CA 0] Center 35 (5~66) winsize 62
4404 22:17:27.993812 [CA 1] Center 35 (5~66) winsize 62
4405 22:17:27.997412 [CA 2] Center 34 (3~65) winsize 63
4406 22:17:28.000515 [CA 3] Center 33 (3~64) winsize 62
4407 22:17:28.003880 [CA 4] Center 34 (3~65) winsize 63
4408 22:17:28.007334 [CA 5] Center 33 (3~64) winsize 62
4409 22:17:28.007419
4410 22:17:28.010396 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4411 22:17:28.010477
4412 22:17:28.013577 [CATrainingPosCal] consider 1 rank data
4413 22:17:28.017236 u2DelayCellTimex100 = 270/100 ps
4414 22:17:28.020200 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4415 22:17:28.026789 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4416 22:17:28.030054 CA2 delay=34 (3~65),Diff = 1 PI (9 cell)
4417 22:17:28.033638 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4418 22:17:28.036675 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4419 22:17:28.040216 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4420 22:17:28.040300
4421 22:17:28.043342 CA PerBit enable=1, Macro0, CA PI delay=33
4422 22:17:28.043424
4423 22:17:28.046920 [CBTSetCACLKResult] CA Dly = 33
4424 22:17:28.049950 CS Dly: 5 (0~36)
4425 22:17:28.050031 ==
4426 22:17:28.053309 Dram Type= 6, Freq= 0, CH_1, rank 1
4427 22:17:28.056706 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4428 22:17:28.056827 ==
4429 22:17:28.063232 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4430 22:17:28.066512 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4431 22:17:28.070897 [CA 0] Center 35 (5~66) winsize 62
4432 22:17:28.073762 [CA 1] Center 35 (5~66) winsize 62
4433 22:17:28.077203 [CA 2] Center 34 (4~65) winsize 62
4434 22:17:28.080684 [CA 3] Center 34 (4~65) winsize 62
4435 22:17:28.083702 [CA 4] Center 34 (4~64) winsize 61
4436 22:17:28.087018 [CA 5] Center 33 (3~64) winsize 62
4437 22:17:28.087109
4438 22:17:28.090629 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4439 22:17:28.090715
4440 22:17:28.093581 [CATrainingPosCal] consider 2 rank data
4441 22:17:28.097106 u2DelayCellTimex100 = 270/100 ps
4442 22:17:28.100616 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4443 22:17:28.106882 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4444 22:17:28.110112 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4445 22:17:28.113801 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4446 22:17:28.116953 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4447 22:17:28.120219 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4448 22:17:28.120304
4449 22:17:28.123312 CA PerBit enable=1, Macro0, CA PI delay=33
4450 22:17:28.123396
4451 22:17:28.126489 [CBTSetCACLKResult] CA Dly = 33
4452 22:17:28.129977 CS Dly: 5 (0~36)
4453 22:17:28.130061
4454 22:17:28.133081 ----->DramcWriteLeveling(PI) begin...
4455 22:17:28.133168 ==
4456 22:17:28.136342 Dram Type= 6, Freq= 0, CH_1, rank 0
4457 22:17:28.139917 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4458 22:17:28.140003 ==
4459 22:17:28.143467 Write leveling (Byte 0): 30 => 30
4460 22:17:28.146447 Write leveling (Byte 1): 31 => 31
4461 22:17:28.149884 DramcWriteLeveling(PI) end<-----
4462 22:17:28.149968
4463 22:17:28.150033 ==
4464 22:17:28.153220 Dram Type= 6, Freq= 0, CH_1, rank 0
4465 22:17:28.156548 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4466 22:17:28.156632 ==
4467 22:17:28.159851 [Gating] SW mode calibration
4468 22:17:28.166175 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4469 22:17:28.172879 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4470 22:17:28.176259 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4471 22:17:28.179757 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4472 22:17:28.186293 0 9 8 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
4473 22:17:28.189378 0 9 12 | B1->B0 | 2e2e 2d2d | 1 1 | (0 0) (1 0)
4474 22:17:28.193070 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4475 22:17:28.199559 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4476 22:17:28.202904 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4477 22:17:28.206231 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4478 22:17:28.212678 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4479 22:17:28.215908 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4480 22:17:28.219407 0 10 8 | B1->B0 | 2323 2626 | 0 1 | (0 0) (0 0)
4481 22:17:28.225979 0 10 12 | B1->B0 | 3939 3e3e | 1 0 | (0 0) (0 0)
4482 22:17:28.229521 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4483 22:17:28.232540 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4484 22:17:28.238937 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4485 22:17:28.242553 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4486 22:17:28.246128 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4487 22:17:28.252303 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4488 22:17:28.255757 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4489 22:17:28.258824 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4490 22:17:28.265785 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4491 22:17:28.269056 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4492 22:17:28.272253 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4493 22:17:28.279001 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4494 22:17:28.282158 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4495 22:17:28.285348 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4496 22:17:28.291995 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4497 22:17:28.295467 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4498 22:17:28.298871 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4499 22:17:28.305232 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4500 22:17:28.308557 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4501 22:17:28.312072 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4502 22:17:28.318469 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4503 22:17:28.321931 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4504 22:17:28.325028 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4505 22:17:28.331592 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4506 22:17:28.331679 Total UI for P1: 0, mck2ui 16
4507 22:17:28.338229 best dqsien dly found for B0: ( 0, 13, 8)
4508 22:17:28.338316 Total UI for P1: 0, mck2ui 16
4509 22:17:28.344753 best dqsien dly found for B1: ( 0, 13, 8)
4510 22:17:28.348060 best DQS0 dly(MCK, UI, PI) = (0, 13, 8)
4511 22:17:28.351207 best DQS1 dly(MCK, UI, PI) = (0, 13, 8)
4512 22:17:28.351294
4513 22:17:28.354735 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 8)
4514 22:17:28.358291 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 8)
4515 22:17:28.361319 [Gating] SW calibration Done
4516 22:17:28.361405 ==
4517 22:17:28.364602 Dram Type= 6, Freq= 0, CH_1, rank 0
4518 22:17:28.367876 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4519 22:17:28.367962 ==
4520 22:17:28.371339 RX Vref Scan: 0
4521 22:17:28.371423
4522 22:17:28.371489 RX Vref 0 -> 0, step: 1
4523 22:17:28.371549
4524 22:17:28.374329 RX Delay -230 -> 252, step: 16
4525 22:17:28.377787 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4526 22:17:28.384411 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4527 22:17:28.387906 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4528 22:17:28.391296 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4529 22:17:28.394227 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4530 22:17:28.400928 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4531 22:17:28.404291 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4532 22:17:28.407882 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4533 22:17:28.410900 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4534 22:17:28.414437 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4535 22:17:28.420712 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4536 22:17:28.424146 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4537 22:17:28.427345 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4538 22:17:28.433936 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4539 22:17:28.437301 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4540 22:17:28.440492 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4541 22:17:28.440603 ==
4542 22:17:28.443999 Dram Type= 6, Freq= 0, CH_1, rank 0
4543 22:17:28.447264 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4544 22:17:28.447349 ==
4545 22:17:28.450342 DQS Delay:
4546 22:17:28.450427 DQS0 = 0, DQS1 = 0
4547 22:17:28.453999 DQM Delay:
4548 22:17:28.454082 DQM0 = 50, DQM1 = 42
4549 22:17:28.454149 DQ Delay:
4550 22:17:28.457030 DQ0 =49, DQ1 =49, DQ2 =41, DQ3 =49
4551 22:17:28.460760 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =49
4552 22:17:28.463843 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =33
4553 22:17:28.467007 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57
4554 22:17:28.467090
4555 22:17:28.467157
4556 22:17:28.470361 ==
4557 22:17:28.473612 Dram Type= 6, Freq= 0, CH_1, rank 0
4558 22:17:28.477217 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4559 22:17:28.477303 ==
4560 22:17:28.477370
4561 22:17:28.477431
4562 22:17:28.480139 TX Vref Scan disable
4563 22:17:28.480222 == TX Byte 0 ==
4564 22:17:28.486785 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4565 22:17:28.490288 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4566 22:17:28.490375 == TX Byte 1 ==
4567 22:17:28.496947 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4568 22:17:28.500352 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4569 22:17:28.500463 ==
4570 22:17:28.503435 Dram Type= 6, Freq= 0, CH_1, rank 0
4571 22:17:28.506572 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4572 22:17:28.506656 ==
4573 22:17:28.506723
4574 22:17:28.506786
4575 22:17:28.510178 TX Vref Scan disable
4576 22:17:28.513371 == TX Byte 0 ==
4577 22:17:28.516383 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4578 22:17:28.519951 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4579 22:17:28.523334 == TX Byte 1 ==
4580 22:17:28.526316 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4581 22:17:28.529597 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4582 22:17:28.532855
4583 22:17:28.532937 [DATLAT]
4584 22:17:28.533002 Freq=600, CH1 RK0
4585 22:17:28.533062
4586 22:17:28.536435 DATLAT Default: 0x9
4587 22:17:28.536519 0, 0xFFFF, sum = 0
4588 22:17:28.539580 1, 0xFFFF, sum = 0
4589 22:17:28.539691 2, 0xFFFF, sum = 0
4590 22:17:28.542668 3, 0xFFFF, sum = 0
4591 22:17:28.542752 4, 0xFFFF, sum = 0
4592 22:17:28.546259 5, 0xFFFF, sum = 0
4593 22:17:28.549317 6, 0xFFFF, sum = 0
4594 22:17:28.549401 7, 0xFFFF, sum = 0
4595 22:17:28.552540 8, 0x0, sum = 1
4596 22:17:28.552625 9, 0x0, sum = 2
4597 22:17:28.552693 10, 0x0, sum = 3
4598 22:17:28.556190 11, 0x0, sum = 4
4599 22:17:28.556274 best_step = 9
4600 22:17:28.556341
4601 22:17:28.556401 ==
4602 22:17:28.559359 Dram Type= 6, Freq= 0, CH_1, rank 0
4603 22:17:28.565835 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4604 22:17:28.565919 ==
4605 22:17:28.565984 RX Vref Scan: 1
4606 22:17:28.566047
4607 22:17:28.569404 RX Vref 0 -> 0, step: 1
4608 22:17:28.569487
4609 22:17:28.572453 RX Delay -179 -> 252, step: 8
4610 22:17:28.572536
4611 22:17:28.575739 Set Vref, RX VrefLevel [Byte0]: 51
4612 22:17:28.579176 [Byte1]: 52
4613 22:17:28.579260
4614 22:17:28.582290 Final RX Vref Byte 0 = 51 to rank0
4615 22:17:28.585682 Final RX Vref Byte 1 = 52 to rank0
4616 22:17:28.589103 Final RX Vref Byte 0 = 51 to rank1
4617 22:17:28.592179 Final RX Vref Byte 1 = 52 to rank1==
4618 22:17:28.595681 Dram Type= 6, Freq= 0, CH_1, rank 0
4619 22:17:28.599028 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4620 22:17:28.599111 ==
4621 22:17:28.602081 DQS Delay:
4622 22:17:28.602162 DQS0 = 0, DQS1 = 0
4623 22:17:28.605635 DQM Delay:
4624 22:17:28.605717 DQM0 = 48, DQM1 = 41
4625 22:17:28.605782 DQ Delay:
4626 22:17:28.608857 DQ0 =56, DQ1 =40, DQ2 =36, DQ3 =44
4627 22:17:28.612070 DQ4 =48, DQ5 =60, DQ6 =60, DQ7 =44
4628 22:17:28.615043 DQ8 =28, DQ9 =28, DQ10 =48, DQ11 =32
4629 22:17:28.618528 DQ12 =52, DQ13 =48, DQ14 =48, DQ15 =48
4630 22:17:28.618610
4631 22:17:28.622019
4632 22:17:28.628439 [DQSOSCAuto] RK0, (LSB)MR18= 0x4c73, (MSB)MR19= 0x808, tDQSOscB0 = 388 ps tDQSOscB1 = 395 ps
4633 22:17:28.631812 CH1 RK0: MR19=808, MR18=4C73
4634 22:17:28.638456 CH1_RK0: MR19=0x808, MR18=0x4C73, DQSOSC=388, MR23=63, INC=174, DEC=116
4635 22:17:28.638570
4636 22:17:28.641655 ----->DramcWriteLeveling(PI) begin...
4637 22:17:28.641772 ==
4638 22:17:28.645025 Dram Type= 6, Freq= 0, CH_1, rank 1
4639 22:17:28.648370 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4640 22:17:28.648452 ==
4641 22:17:28.651451 Write leveling (Byte 0): 29 => 29
4642 22:17:28.654770 Write leveling (Byte 1): 29 => 29
4643 22:17:28.658543 DramcWriteLeveling(PI) end<-----
4644 22:17:28.658626
4645 22:17:28.658691 ==
4646 22:17:28.661732 Dram Type= 6, Freq= 0, CH_1, rank 1
4647 22:17:28.664689 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4648 22:17:28.664827 ==
4649 22:17:28.668191 [Gating] SW mode calibration
4650 22:17:28.674887 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4651 22:17:28.681567 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4652 22:17:28.684427 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4653 22:17:28.687838 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4654 22:17:28.694585 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4655 22:17:28.697751 0 9 12 | B1->B0 | 2929 3333 | 0 0 | (1 0) (0 1)
4656 22:17:28.701078 0 9 16 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4657 22:17:28.707700 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4658 22:17:28.711236 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4659 22:17:28.717333 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4660 22:17:28.720562 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4661 22:17:28.723856 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4662 22:17:28.730640 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4663 22:17:28.734236 0 10 12 | B1->B0 | 3f3f 2c2c | 0 0 | (1 1) (1 1)
4664 22:17:28.737364 0 10 16 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
4665 22:17:28.740576 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4666 22:17:28.746964 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4667 22:17:28.750635 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4668 22:17:28.756921 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4669 22:17:28.760318 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4670 22:17:28.763648 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4671 22:17:28.770316 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4672 22:17:28.773363 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4673 22:17:28.776888 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4674 22:17:28.783352 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4675 22:17:28.786740 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4676 22:17:28.789799 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4677 22:17:28.796599 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4678 22:17:28.799788 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4679 22:17:28.803225 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4680 22:17:28.809693 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4681 22:17:28.812747 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4682 22:17:28.816465 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4683 22:17:28.823016 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4684 22:17:28.826248 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4685 22:17:28.829734 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4686 22:17:28.836084 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4687 22:17:28.839725 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4688 22:17:28.843156 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4689 22:17:28.846425 Total UI for P1: 0, mck2ui 16
4690 22:17:28.849388 best dqsien dly found for B0: ( 0, 13, 12)
4691 22:17:28.852803 Total UI for P1: 0, mck2ui 16
4692 22:17:28.855935 best dqsien dly found for B1: ( 0, 13, 12)
4693 22:17:28.859587 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4694 22:17:28.862792 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4695 22:17:28.862893
4696 22:17:28.866637 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4697 22:17:28.872725 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4698 22:17:28.872857 [Gating] SW calibration Done
4699 22:17:28.872924 ==
4700 22:17:28.876334 Dram Type= 6, Freq= 0, CH_1, rank 1
4701 22:17:28.882465 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4702 22:17:28.882551 ==
4703 22:17:28.882618 RX Vref Scan: 0
4704 22:17:28.882680
4705 22:17:28.886005 RX Vref 0 -> 0, step: 1
4706 22:17:28.886104
4707 22:17:28.888905 RX Delay -230 -> 252, step: 16
4708 22:17:28.892418 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4709 22:17:28.895697 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4710 22:17:28.902305 iDelay=218, Bit 2, Center 41 (-102 ~ 185) 288
4711 22:17:28.905871 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4712 22:17:28.908691 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4713 22:17:28.912163 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4714 22:17:28.915678 iDelay=218, Bit 6, Center 57 (-86 ~ 201) 288
4715 22:17:28.922433 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4716 22:17:28.925511 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4717 22:17:28.928540 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4718 22:17:28.932050 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4719 22:17:28.938693 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4720 22:17:28.941916 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4721 22:17:28.945505 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4722 22:17:28.948471 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4723 22:17:28.955015 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4724 22:17:28.955102 ==
4725 22:17:28.958602 Dram Type= 6, Freq= 0, CH_1, rank 1
4726 22:17:28.961868 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4727 22:17:28.961954 ==
4728 22:17:28.962022 DQS Delay:
4729 22:17:28.964903 DQS0 = 0, DQS1 = 0
4730 22:17:28.964987 DQM Delay:
4731 22:17:28.968592 DQM0 = 52, DQM1 = 46
4732 22:17:28.968676 DQ Delay:
4733 22:17:28.971428 DQ0 =57, DQ1 =49, DQ2 =41, DQ3 =49
4734 22:17:28.974759 DQ4 =49, DQ5 =65, DQ6 =57, DQ7 =49
4735 22:17:28.977988 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4736 22:17:28.981381 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57
4737 22:17:28.981466
4738 22:17:28.981532
4739 22:17:28.981592 ==
4740 22:17:28.984570 Dram Type= 6, Freq= 0, CH_1, rank 1
4741 22:17:28.987784 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4742 22:17:28.991278 ==
4743 22:17:28.991366
4744 22:17:28.991432
4745 22:17:28.991493 TX Vref Scan disable
4746 22:17:28.994827 == TX Byte 0 ==
4747 22:17:28.997874 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4748 22:17:29.001048 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4749 22:17:29.004463 == TX Byte 1 ==
4750 22:17:29.007552 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4751 22:17:29.014359 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4752 22:17:29.014446 ==
4753 22:17:29.017872 Dram Type= 6, Freq= 0, CH_1, rank 1
4754 22:17:29.020945 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4755 22:17:29.021029 ==
4756 22:17:29.021095
4757 22:17:29.021156
4758 22:17:29.023987 TX Vref Scan disable
4759 22:17:29.027633 == TX Byte 0 ==
4760 22:17:29.030704 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4761 22:17:29.033869 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4762 22:17:29.037311 == TX Byte 1 ==
4763 22:17:29.040458 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4764 22:17:29.044067 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4765 22:17:29.044150
4766 22:17:29.044216 [DATLAT]
4767 22:17:29.047217 Freq=600, CH1 RK1
4768 22:17:29.047300
4769 22:17:29.050617 DATLAT Default: 0x9
4770 22:17:29.050699 0, 0xFFFF, sum = 0
4771 22:17:29.053756 1, 0xFFFF, sum = 0
4772 22:17:29.053840 2, 0xFFFF, sum = 0
4773 22:17:29.057164 3, 0xFFFF, sum = 0
4774 22:17:29.057248 4, 0xFFFF, sum = 0
4775 22:17:29.060231 5, 0xFFFF, sum = 0
4776 22:17:29.060315 6, 0xFFFF, sum = 0
4777 22:17:29.063723 7, 0xFFFF, sum = 0
4778 22:17:29.063807 8, 0x0, sum = 1
4779 22:17:29.066820 9, 0x0, sum = 2
4780 22:17:29.066903 10, 0x0, sum = 3
4781 22:17:29.070606 11, 0x0, sum = 4
4782 22:17:29.070689 best_step = 9
4783 22:17:29.070754
4784 22:17:29.070813 ==
4785 22:17:29.073450 Dram Type= 6, Freq= 0, CH_1, rank 1
4786 22:17:29.077046 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4787 22:17:29.077129 ==
4788 22:17:29.080183 RX Vref Scan: 0
4789 22:17:29.080266
4790 22:17:29.083382 RX Vref 0 -> 0, step: 1
4791 22:17:29.083465
4792 22:17:29.083530 RX Delay -163 -> 252, step: 8
4793 22:17:29.091189 iDelay=205, Bit 0, Center 56 (-83 ~ 196) 280
4794 22:17:29.094698 iDelay=205, Bit 1, Center 44 (-91 ~ 180) 272
4795 22:17:29.097623 iDelay=205, Bit 2, Center 40 (-99 ~ 180) 280
4796 22:17:29.101009 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4797 22:17:29.104300 iDelay=205, Bit 4, Center 48 (-91 ~ 188) 280
4798 22:17:29.110910 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4799 22:17:29.114432 iDelay=205, Bit 6, Center 56 (-83 ~ 196) 280
4800 22:17:29.117826 iDelay=205, Bit 7, Center 48 (-91 ~ 188) 280
4801 22:17:29.121107 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4802 22:17:29.127589 iDelay=205, Bit 9, Center 36 (-107 ~ 180) 288
4803 22:17:29.130653 iDelay=205, Bit 10, Center 44 (-99 ~ 188) 288
4804 22:17:29.134419 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4805 22:17:29.137483 iDelay=205, Bit 12, Center 48 (-99 ~ 196) 296
4806 22:17:29.144227 iDelay=205, Bit 13, Center 48 (-99 ~ 196) 296
4807 22:17:29.147354 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4808 22:17:29.150408 iDelay=205, Bit 15, Center 56 (-91 ~ 204) 296
4809 22:17:29.150492 ==
4810 22:17:29.154035 Dram Type= 6, Freq= 0, CH_1, rank 1
4811 22:17:29.157431 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4812 22:17:29.157515 ==
4813 22:17:29.160231 DQS Delay:
4814 22:17:29.160314 DQS0 = 0, DQS1 = 0
4815 22:17:29.163766 DQM Delay:
4816 22:17:29.163849 DQM0 = 49, DQM1 = 44
4817 22:17:29.163914 DQ Delay:
4818 22:17:29.167017 DQ0 =56, DQ1 =44, DQ2 =40, DQ3 =44
4819 22:17:29.170109 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =48
4820 22:17:29.173682 DQ8 =32, DQ9 =36, DQ10 =44, DQ11 =40
4821 22:17:29.176840 DQ12 =48, DQ13 =48, DQ14 =48, DQ15 =56
4822 22:17:29.176924
4823 22:17:29.176990
4824 22:17:29.187062 [DQSOSCAuto] RK1, (LSB)MR18= 0x531a, (MSB)MR19= 0x808, tDQSOscB0 = 405 ps tDQSOscB1 = 394 ps
4825 22:17:29.189920 CH1 RK1: MR19=808, MR18=531A
4826 22:17:29.196687 CH1_RK1: MR19=0x808, MR18=0x531A, DQSOSC=394, MR23=63, INC=168, DEC=112
4827 22:17:29.200111 [RxdqsGatingPostProcess] freq 600
4828 22:17:29.203455 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4829 22:17:29.206543 Pre-setting of DQS Precalculation
4830 22:17:29.213121 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4831 22:17:29.219460 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4832 22:17:29.226435 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4833 22:17:29.226524
4834 22:17:29.226590
4835 22:17:29.229643 [Calibration Summary] 1200 Mbps
4836 22:17:29.229727 CH 0, Rank 0
4837 22:17:29.232707 SW Impedance : PASS
4838 22:17:29.235764 DUTY Scan : NO K
4839 22:17:29.235846 ZQ Calibration : PASS
4840 22:17:29.239532 Jitter Meter : NO K
4841 22:17:29.242655 CBT Training : PASS
4842 22:17:29.242738 Write leveling : PASS
4843 22:17:29.245861 RX DQS gating : PASS
4844 22:17:29.249363 RX DQ/DQS(RDDQC) : PASS
4845 22:17:29.249447 TX DQ/DQS : PASS
4846 22:17:29.252506 RX DATLAT : PASS
4847 22:17:29.252589 RX DQ/DQS(Engine): PASS
4848 22:17:29.255667 TX OE : NO K
4849 22:17:29.255746 All Pass.
4850 22:17:29.255811
4851 22:17:29.258948 CH 0, Rank 1
4852 22:17:29.262546 SW Impedance : PASS
4853 22:17:29.262633 DUTY Scan : NO K
4854 22:17:29.265499 ZQ Calibration : PASS
4855 22:17:29.265582 Jitter Meter : NO K
4856 22:17:29.268681 CBT Training : PASS
4857 22:17:29.272514 Write leveling : PASS
4858 22:17:29.272597 RX DQS gating : PASS
4859 22:17:29.275745 RX DQ/DQS(RDDQC) : PASS
4860 22:17:29.278980 TX DQ/DQS : PASS
4861 22:17:29.279062 RX DATLAT : PASS
4862 22:17:29.282525 RX DQ/DQS(Engine): PASS
4863 22:17:29.285640 TX OE : NO K
4864 22:17:29.285723 All Pass.
4865 22:17:29.285786
4866 22:17:29.285847 CH 1, Rank 0
4867 22:17:29.288686 SW Impedance : PASS
4868 22:17:29.292292 DUTY Scan : NO K
4869 22:17:29.292375 ZQ Calibration : PASS
4870 22:17:29.295478 Jitter Meter : NO K
4871 22:17:29.298827 CBT Training : PASS
4872 22:17:29.298910 Write leveling : PASS
4873 22:17:29.301886 RX DQS gating : PASS
4874 22:17:29.305368 RX DQ/DQS(RDDQC) : PASS
4875 22:17:29.305450 TX DQ/DQS : PASS
4876 22:17:29.308665 RX DATLAT : PASS
4877 22:17:29.312048 RX DQ/DQS(Engine): PASS
4878 22:17:29.312130 TX OE : NO K
4879 22:17:29.315398 All Pass.
4880 22:17:29.315480
4881 22:17:29.315545 CH 1, Rank 1
4882 22:17:29.318450 SW Impedance : PASS
4883 22:17:29.318533 DUTY Scan : NO K
4884 22:17:29.321743 ZQ Calibration : PASS
4885 22:17:29.325217 Jitter Meter : NO K
4886 22:17:29.325299 CBT Training : PASS
4887 22:17:29.328579 Write leveling : PASS
4888 22:17:29.328678 RX DQS gating : PASS
4889 22:17:29.331710 RX DQ/DQS(RDDQC) : PASS
4890 22:17:29.334910 TX DQ/DQS : PASS
4891 22:17:29.334996 RX DATLAT : PASS
4892 22:17:29.338236 RX DQ/DQS(Engine): PASS
4893 22:17:29.341834 TX OE : NO K
4894 22:17:29.341921 All Pass.
4895 22:17:29.342026
4896 22:17:29.344821 DramC Write-DBI off
4897 22:17:29.344932 PER_BANK_REFRESH: Hybrid Mode
4898 22:17:29.348350 TX_TRACKING: ON
4899 22:17:29.358422 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4900 22:17:29.361881 [FAST_K] Save calibration result to emmc
4901 22:17:29.364745 dramc_set_vcore_voltage set vcore to 662500
4902 22:17:29.364836 Read voltage for 933, 3
4903 22:17:29.368149 Vio18 = 0
4904 22:17:29.368233 Vcore = 662500
4905 22:17:29.368299 Vdram = 0
4906 22:17:29.371563 Vddq = 0
4907 22:17:29.371648 Vmddr = 0
4908 22:17:29.374935 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4909 22:17:29.381417 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4910 22:17:29.384727 MEM_TYPE=3, freq_sel=17
4911 22:17:29.388345 sv_algorithm_assistance_LP4_1600
4912 22:17:29.391334 ============ PULL DRAM RESETB DOWN ============
4913 22:17:29.394568 ========== PULL DRAM RESETB DOWN end =========
4914 22:17:29.401420 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4915 22:17:29.404286 ===================================
4916 22:17:29.404372 LPDDR4 DRAM CONFIGURATION
4917 22:17:29.407892 ===================================
4918 22:17:29.411306 EX_ROW_EN[0] = 0x0
4919 22:17:29.414429 EX_ROW_EN[1] = 0x0
4920 22:17:29.414513 LP4Y_EN = 0x0
4921 22:17:29.417716 WORK_FSP = 0x0
4922 22:17:29.417799 WL = 0x3
4923 22:17:29.421150 RL = 0x3
4924 22:17:29.421233 BL = 0x2
4925 22:17:29.424279 RPST = 0x0
4926 22:17:29.424361 RD_PRE = 0x0
4927 22:17:29.427684 WR_PRE = 0x1
4928 22:17:29.427767 WR_PST = 0x0
4929 22:17:29.430856 DBI_WR = 0x0
4930 22:17:29.430943 DBI_RD = 0x0
4931 22:17:29.433991 OTF = 0x1
4932 22:17:29.437515 ===================================
4933 22:17:29.440638 ===================================
4934 22:17:29.440725 ANA top config
4935 22:17:29.444119 ===================================
4936 22:17:29.447282 DLL_ASYNC_EN = 0
4937 22:17:29.450404 ALL_SLAVE_EN = 1
4938 22:17:29.453876 NEW_RANK_MODE = 1
4939 22:17:29.453964 DLL_IDLE_MODE = 1
4940 22:17:29.457358 LP45_APHY_COMB_EN = 1
4941 22:17:29.460626 TX_ODT_DIS = 1
4942 22:17:29.463818 NEW_8X_MODE = 1
4943 22:17:29.467106 ===================================
4944 22:17:29.470350 ===================================
4945 22:17:29.473627 data_rate = 1866
4946 22:17:29.473711 CKR = 1
4947 22:17:29.477084 DQ_P2S_RATIO = 8
4948 22:17:29.480375 ===================================
4949 22:17:29.483550 CA_P2S_RATIO = 8
4950 22:17:29.486907 DQ_CA_OPEN = 0
4951 22:17:29.490334 DQ_SEMI_OPEN = 0
4952 22:17:29.493453 CA_SEMI_OPEN = 0
4953 22:17:29.493536 CA_FULL_RATE = 0
4954 22:17:29.496714 DQ_CKDIV4_EN = 1
4955 22:17:29.500280 CA_CKDIV4_EN = 1
4956 22:17:29.503390 CA_PREDIV_EN = 0
4957 22:17:29.507175 PH8_DLY = 0
4958 22:17:29.509970 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4959 22:17:29.510052 DQ_AAMCK_DIV = 4
4960 22:17:29.513401 CA_AAMCK_DIV = 4
4961 22:17:29.516501 CA_ADMCK_DIV = 4
4962 22:17:29.519798 DQ_TRACK_CA_EN = 0
4963 22:17:29.523431 CA_PICK = 933
4964 22:17:29.526545 CA_MCKIO = 933
4965 22:17:29.530167 MCKIO_SEMI = 0
4966 22:17:29.530252 PLL_FREQ = 3732
4967 22:17:29.533166 DQ_UI_PI_RATIO = 32
4968 22:17:29.536397 CA_UI_PI_RATIO = 0
4969 22:17:29.539613 ===================================
4970 22:17:29.542917 ===================================
4971 22:17:29.546367 memory_type:LPDDR4
4972 22:17:29.549498 GP_NUM : 10
4973 22:17:29.549581 SRAM_EN : 1
4974 22:17:29.553175 MD32_EN : 0
4975 22:17:29.556424 ===================================
4976 22:17:29.556508 [ANA_INIT] >>>>>>>>>>>>>>
4977 22:17:29.559555 <<<<<< [CONFIGURE PHASE]: ANA_TX
4978 22:17:29.562892 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4979 22:17:29.566260 ===================================
4980 22:17:29.569332 data_rate = 1866,PCW = 0X8f00
4981 22:17:29.572686 ===================================
4982 22:17:29.576279 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4983 22:17:29.582939 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4984 22:17:29.586288 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4985 22:17:29.592734 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4986 22:17:29.596258 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4987 22:17:29.599339 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4988 22:17:29.602861 [ANA_INIT] flow start
4989 22:17:29.602944 [ANA_INIT] PLL >>>>>>>>
4990 22:17:29.606167 [ANA_INIT] PLL <<<<<<<<
4991 22:17:29.609570 [ANA_INIT] MIDPI >>>>>>>>
4992 22:17:29.609652 [ANA_INIT] MIDPI <<<<<<<<
4993 22:17:29.612708 [ANA_INIT] DLL >>>>>>>>
4994 22:17:29.615880 [ANA_INIT] flow end
4995 22:17:29.619349 ============ LP4 DIFF to SE enter ============
4996 22:17:29.622724 ============ LP4 DIFF to SE exit ============
4997 22:17:29.625825 [ANA_INIT] <<<<<<<<<<<<<
4998 22:17:29.629147 [Flow] Enable top DCM control >>>>>
4999 22:17:29.632518 [Flow] Enable top DCM control <<<<<
5000 22:17:29.635689 Enable DLL master slave shuffle
5001 22:17:29.639013 ==============================================================
5002 22:17:29.642354 Gating Mode config
5003 22:17:29.649192 ==============================================================
5004 22:17:29.649276 Config description:
5005 22:17:29.659018 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5006 22:17:29.665689 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5007 22:17:29.671976 SELPH_MODE 0: By rank 1: By Phase
5008 22:17:29.675254 ==============================================================
5009 22:17:29.678759 GAT_TRACK_EN = 1
5010 22:17:29.681963 RX_GATING_MODE = 2
5011 22:17:29.685440 RX_GATING_TRACK_MODE = 2
5012 22:17:29.688651 SELPH_MODE = 1
5013 22:17:29.692181 PICG_EARLY_EN = 1
5014 22:17:29.695061 VALID_LAT_VALUE = 1
5015 22:17:29.698744 ==============================================================
5016 22:17:29.701867 Enter into Gating configuration >>>>
5017 22:17:29.704976 Exit from Gating configuration <<<<
5018 22:17:29.708646 Enter into DVFS_PRE_config >>>>>
5019 22:17:29.721877 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5020 22:17:29.725523 Exit from DVFS_PRE_config <<<<<
5021 22:17:29.728384 Enter into PICG configuration >>>>
5022 22:17:29.728468 Exit from PICG configuration <<<<
5023 22:17:29.731530 [RX_INPUT] configuration >>>>>
5024 22:17:29.734946 [RX_INPUT] configuration <<<<<
5025 22:17:29.741361 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5026 22:17:29.744907 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5027 22:17:29.751384 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5028 22:17:29.758135 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5029 22:17:29.764871 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5030 22:17:29.770974 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5031 22:17:29.774680 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5032 22:17:29.778002 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5033 22:17:29.784468 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5034 22:17:29.787829 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5035 22:17:29.790984 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5036 22:17:29.794609 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5037 22:17:29.797399 ===================================
5038 22:17:29.800925 LPDDR4 DRAM CONFIGURATION
5039 22:17:29.803993 ===================================
5040 22:17:29.807497 EX_ROW_EN[0] = 0x0
5041 22:17:29.807584 EX_ROW_EN[1] = 0x0
5042 22:17:29.810501 LP4Y_EN = 0x0
5043 22:17:29.810586 WORK_FSP = 0x0
5044 22:17:29.814192 WL = 0x3
5045 22:17:29.814276 RL = 0x3
5046 22:17:29.817181 BL = 0x2
5047 22:17:29.820432 RPST = 0x0
5048 22:17:29.820517 RD_PRE = 0x0
5049 22:17:29.824001 WR_PRE = 0x1
5050 22:17:29.824085 WR_PST = 0x0
5051 22:17:29.827019 DBI_WR = 0x0
5052 22:17:29.827104 DBI_RD = 0x0
5053 22:17:29.830276 OTF = 0x1
5054 22:17:29.833782 ===================================
5055 22:17:29.836928 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5056 22:17:29.840449 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5057 22:17:29.847063 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5058 22:17:29.850220 ===================================
5059 22:17:29.850308 LPDDR4 DRAM CONFIGURATION
5060 22:17:29.853380 ===================================
5061 22:17:29.856798 EX_ROW_EN[0] = 0x10
5062 22:17:29.856882 EX_ROW_EN[1] = 0x0
5063 22:17:29.860061 LP4Y_EN = 0x0
5064 22:17:29.860145 WORK_FSP = 0x0
5065 22:17:29.863116 WL = 0x3
5066 22:17:29.866731 RL = 0x3
5067 22:17:29.866841 BL = 0x2
5068 22:17:29.869886 RPST = 0x0
5069 22:17:29.869971 RD_PRE = 0x0
5070 22:17:29.872954 WR_PRE = 0x1
5071 22:17:29.873038 WR_PST = 0x0
5072 22:17:29.876629 DBI_WR = 0x0
5073 22:17:29.876739 DBI_RD = 0x0
5074 22:17:29.879693 OTF = 0x1
5075 22:17:29.883234 ===================================
5076 22:17:29.889470 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5077 22:17:29.893107 nWR fixed to 30
5078 22:17:29.893194 [ModeRegInit_LP4] CH0 RK0
5079 22:17:29.896039 [ModeRegInit_LP4] CH0 RK1
5080 22:17:29.899486 [ModeRegInit_LP4] CH1 RK0
5081 22:17:29.903009 [ModeRegInit_LP4] CH1 RK1
5082 22:17:29.903093 match AC timing 9
5083 22:17:29.906156 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5084 22:17:29.912680 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5085 22:17:29.916176 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5086 22:17:29.922605 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5087 22:17:29.926259 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5088 22:17:29.926344 ==
5089 22:17:29.929366 Dram Type= 6, Freq= 0, CH_0, rank 0
5090 22:17:29.932516 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5091 22:17:29.932601 ==
5092 22:17:29.939367 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5093 22:17:29.945633 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5094 22:17:29.949183 [CA 0] Center 37 (7~68) winsize 62
5095 22:17:29.952393 [CA 1] Center 38 (8~69) winsize 62
5096 22:17:29.955403 [CA 2] Center 35 (5~66) winsize 62
5097 22:17:29.959044 [CA 3] Center 34 (4~65) winsize 62
5098 22:17:29.962297 [CA 4] Center 34 (4~64) winsize 61
5099 22:17:29.965591 [CA 5] Center 33 (3~64) winsize 62
5100 22:17:29.965674
5101 22:17:29.968740 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5102 22:17:29.968861
5103 22:17:29.972385 [CATrainingPosCal] consider 1 rank data
5104 22:17:29.975531 u2DelayCellTimex100 = 270/100 ps
5105 22:17:29.979097 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5106 22:17:29.982129 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5107 22:17:29.985554 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5108 22:17:29.988909 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5109 22:17:29.991970 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5110 22:17:29.995439 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5111 22:17:29.995525
5112 22:17:30.001885 CA PerBit enable=1, Macro0, CA PI delay=33
5113 22:17:30.001973
5114 22:17:30.005391 [CBTSetCACLKResult] CA Dly = 33
5115 22:17:30.005475 CS Dly: 6 (0~37)
5116 22:17:30.005541 ==
5117 22:17:30.008559 Dram Type= 6, Freq= 0, CH_0, rank 1
5118 22:17:30.011841 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5119 22:17:30.011927 ==
5120 22:17:30.018435 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5121 22:17:30.025171 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5122 22:17:30.028542 [CA 0] Center 38 (8~69) winsize 62
5123 22:17:30.031672 [CA 1] Center 38 (8~69) winsize 62
5124 22:17:30.034766 [CA 2] Center 36 (6~66) winsize 61
5125 22:17:30.038278 [CA 3] Center 35 (5~66) winsize 62
5126 22:17:30.041638 [CA 4] Center 34 (4~65) winsize 62
5127 22:17:30.044638 [CA 5] Center 34 (4~64) winsize 61
5128 22:17:30.044721
5129 22:17:30.048203 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5130 22:17:30.048287
5131 22:17:30.051044 [CATrainingPosCal] consider 2 rank data
5132 22:17:30.054737 u2DelayCellTimex100 = 270/100 ps
5133 22:17:30.057602 CA0 delay=38 (8~68),Diff = 4 PI (24 cell)
5134 22:17:30.060928 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5135 22:17:30.064447 CA2 delay=36 (6~66),Diff = 2 PI (12 cell)
5136 22:17:30.071036 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5137 22:17:30.074194 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5138 22:17:30.077742 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5139 22:17:30.077826
5140 22:17:30.081001 CA PerBit enable=1, Macro0, CA PI delay=34
5141 22:17:30.081084
5142 22:17:30.084105 [CBTSetCACLKResult] CA Dly = 34
5143 22:17:30.084188 CS Dly: 7 (0~39)
5144 22:17:30.084254
5145 22:17:30.087305 ----->DramcWriteLeveling(PI) begin...
5146 22:17:30.090757 ==
5147 22:17:30.090842 Dram Type= 6, Freq= 0, CH_0, rank 0
5148 22:17:30.097367 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5149 22:17:30.097453 ==
5150 22:17:30.100587 Write leveling (Byte 0): 31 => 31
5151 22:17:30.104085 Write leveling (Byte 1): 28 => 28
5152 22:17:30.107315 DramcWriteLeveling(PI) end<-----
5153 22:17:30.107398
5154 22:17:30.107463 ==
5155 22:17:30.110748 Dram Type= 6, Freq= 0, CH_0, rank 0
5156 22:17:30.113927 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5157 22:17:30.114011 ==
5158 22:17:30.117402 [Gating] SW mode calibration
5159 22:17:30.123933 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5160 22:17:30.127598 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5161 22:17:30.133717 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5162 22:17:30.137024 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5163 22:17:30.140473 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5164 22:17:30.147357 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5165 22:17:30.150628 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5166 22:17:30.153875 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5167 22:17:30.160365 0 14 24 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 0)
5168 22:17:30.163744 0 14 28 | B1->B0 | 3333 2525 | 1 0 | (1 0) (1 0)
5169 22:17:30.167177 0 15 0 | B1->B0 | 2828 2323 | 0 0 | (1 0) (0 0)
5170 22:17:30.173350 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5171 22:17:30.176678 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5172 22:17:30.180129 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5173 22:17:30.186918 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5174 22:17:30.189884 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5175 22:17:30.193300 0 15 24 | B1->B0 | 2323 3232 | 0 1 | (0 0) (0 0)
5176 22:17:30.199693 0 15 28 | B1->B0 | 2e2e 4343 | 1 0 | (0 0) (0 0)
5177 22:17:30.202899 1 0 0 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
5178 22:17:30.206292 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5179 22:17:30.213178 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5180 22:17:30.216272 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5181 22:17:30.219830 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5182 22:17:30.226129 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5183 22:17:30.229669 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5184 22:17:30.233022 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5185 22:17:30.239395 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5186 22:17:30.242763 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5187 22:17:30.246292 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5188 22:17:30.253170 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5189 22:17:30.256095 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5190 22:17:30.259376 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5191 22:17:30.265990 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5192 22:17:30.269175 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5193 22:17:30.272483 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5194 22:17:30.279209 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5195 22:17:30.282481 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5196 22:17:30.285889 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5197 22:17:30.292536 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5198 22:17:30.295714 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5199 22:17:30.299112 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5200 22:17:30.305885 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5201 22:17:30.305973 Total UI for P1: 0, mck2ui 16
5202 22:17:30.312284 best dqsien dly found for B0: ( 1, 2, 24)
5203 22:17:30.315885 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5204 22:17:30.318919 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5205 22:17:30.322221 Total UI for P1: 0, mck2ui 16
5206 22:17:30.325633 best dqsien dly found for B1: ( 1, 2, 30)
5207 22:17:30.328732 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5208 22:17:30.332109 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5209 22:17:30.332193
5210 22:17:30.338668 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5211 22:17:30.342134 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5212 22:17:30.342219 [Gating] SW calibration Done
5213 22:17:30.345586 ==
5214 22:17:30.348729 Dram Type= 6, Freq= 0, CH_0, rank 0
5215 22:17:30.351936 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5216 22:17:30.352021 ==
5217 22:17:30.352088 RX Vref Scan: 0
5218 22:17:30.352147
5219 22:17:30.355437 RX Vref 0 -> 0, step: 1
5220 22:17:30.355519
5221 22:17:30.358746 RX Delay -80 -> 252, step: 8
5222 22:17:30.361826 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5223 22:17:30.365315 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5224 22:17:30.371633 iDelay=208, Bit 2, Center 103 (16 ~ 191) 176
5225 22:17:30.375282 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5226 22:17:30.378580 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5227 22:17:30.382015 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5228 22:17:30.385016 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5229 22:17:30.388213 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5230 22:17:30.395340 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5231 22:17:30.398456 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5232 22:17:30.401956 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5233 22:17:30.404812 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5234 22:17:30.408125 iDelay=208, Bit 12, Center 91 (0 ~ 183) 184
5235 22:17:30.414796 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5236 22:17:30.418160 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5237 22:17:30.421178 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5238 22:17:30.421263 ==
5239 22:17:30.424795 Dram Type= 6, Freq= 0, CH_0, rank 0
5240 22:17:30.428004 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5241 22:17:30.428090 ==
5242 22:17:30.431192 DQS Delay:
5243 22:17:30.431276 DQS0 = 0, DQS1 = 0
5244 22:17:30.431342 DQM Delay:
5245 22:17:30.434740 DQM0 = 106, DQM1 = 90
5246 22:17:30.434824 DQ Delay:
5247 22:17:30.437890 DQ0 =107, DQ1 =107, DQ2 =103, DQ3 =99
5248 22:17:30.441388 DQ4 =107, DQ5 =95, DQ6 =115, DQ7 =115
5249 22:17:30.444510 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =87
5250 22:17:30.447635 DQ12 =91, DQ13 =91, DQ14 =99, DQ15 =99
5251 22:17:30.447720
5252 22:17:30.451399
5253 22:17:30.451482 ==
5254 22:17:30.454388 Dram Type= 6, Freq= 0, CH_0, rank 0
5255 22:17:30.457506 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5256 22:17:30.457590 ==
5257 22:17:30.457657
5258 22:17:30.457719
5259 22:17:30.460826 TX Vref Scan disable
5260 22:17:30.460909 == TX Byte 0 ==
5261 22:17:30.467664 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5262 22:17:30.470871 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5263 22:17:30.470956 == TX Byte 1 ==
5264 22:17:30.477483 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5265 22:17:30.481027 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5266 22:17:30.481137 ==
5267 22:17:30.484115 Dram Type= 6, Freq= 0, CH_0, rank 0
5268 22:17:30.487127 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5269 22:17:30.487215 ==
5270 22:17:30.487283
5271 22:17:30.487348
5272 22:17:30.490457 TX Vref Scan disable
5273 22:17:30.493945 == TX Byte 0 ==
5274 22:17:30.497310 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5275 22:17:30.500418 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5276 22:17:30.503652 == TX Byte 1 ==
5277 22:17:30.506876 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5278 22:17:30.510257 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5279 22:17:30.510341
5280 22:17:30.513847 [DATLAT]
5281 22:17:30.513923 Freq=933, CH0 RK0
5282 22:17:30.513986
5283 22:17:30.516947 DATLAT Default: 0xd
5284 22:17:30.517056 0, 0xFFFF, sum = 0
5285 22:17:30.520339 1, 0xFFFF, sum = 0
5286 22:17:30.520426 2, 0xFFFF, sum = 0
5287 22:17:30.523433 3, 0xFFFF, sum = 0
5288 22:17:30.523518 4, 0xFFFF, sum = 0
5289 22:17:30.526486 5, 0xFFFF, sum = 0
5290 22:17:30.529959 6, 0xFFFF, sum = 0
5291 22:17:30.530043 7, 0xFFFF, sum = 0
5292 22:17:30.533722 8, 0xFFFF, sum = 0
5293 22:17:30.533809 9, 0xFFFF, sum = 0
5294 22:17:30.536908 10, 0x0, sum = 1
5295 22:17:30.536993 11, 0x0, sum = 2
5296 22:17:30.539843 12, 0x0, sum = 3
5297 22:17:30.539929 13, 0x0, sum = 4
5298 22:17:30.539996 best_step = 11
5299 22:17:30.540057
5300 22:17:30.543141 ==
5301 22:17:30.543226 Dram Type= 6, Freq= 0, CH_0, rank 0
5302 22:17:30.549938 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5303 22:17:30.550043 ==
5304 22:17:30.550133 RX Vref Scan: 1
5305 22:17:30.550197
5306 22:17:30.553089 RX Vref 0 -> 0, step: 1
5307 22:17:30.553172
5308 22:17:30.556215 RX Delay -53 -> 252, step: 4
5309 22:17:30.556298
5310 22:17:30.560135 Set Vref, RX VrefLevel [Byte0]: 57
5311 22:17:30.563159 [Byte1]: 49
5312 22:17:30.563244
5313 22:17:30.566258 Final RX Vref Byte 0 = 57 to rank0
5314 22:17:30.569705 Final RX Vref Byte 1 = 49 to rank0
5315 22:17:30.572696 Final RX Vref Byte 0 = 57 to rank1
5316 22:17:30.576185 Final RX Vref Byte 1 = 49 to rank1==
5317 22:17:30.579312 Dram Type= 6, Freq= 0, CH_0, rank 0
5318 22:17:30.583026 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5319 22:17:30.586112 ==
5320 22:17:30.586198 DQS Delay:
5321 22:17:30.586263 DQS0 = 0, DQS1 = 0
5322 22:17:30.589307 DQM Delay:
5323 22:17:30.589390 DQM0 = 108, DQM1 = 92
5324 22:17:30.592695 DQ Delay:
5325 22:17:30.595846 DQ0 =108, DQ1 =108, DQ2 =104, DQ3 =106
5326 22:17:30.599370 DQ4 =108, DQ5 =100, DQ6 =116, DQ7 =114
5327 22:17:30.602777 DQ8 =84, DQ9 =78, DQ10 =92, DQ11 =92
5328 22:17:30.605851 DQ12 =98, DQ13 =94, DQ14 =102, DQ15 =100
5329 22:17:30.605937
5330 22:17:30.606002
5331 22:17:30.613054 [DQSOSCAuto] RK0, (LSB)MR18= 0x2723, (MSB)MR19= 0x505, tDQSOscB0 = 410 ps tDQSOscB1 = 409 ps
5332 22:17:30.615858 CH0 RK0: MR19=505, MR18=2723
5333 22:17:30.622951 CH0_RK0: MR19=0x505, MR18=0x2723, DQSOSC=409, MR23=63, INC=64, DEC=43
5334 22:17:30.623043
5335 22:17:30.625712 ----->DramcWriteLeveling(PI) begin...
5336 22:17:30.625797 ==
5337 22:17:30.629153 Dram Type= 6, Freq= 0, CH_0, rank 1
5338 22:17:30.632290 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5339 22:17:30.632379 ==
5340 22:17:30.635832 Write leveling (Byte 0): 34 => 34
5341 22:17:30.639077 Write leveling (Byte 1): 30 => 30
5342 22:17:30.642142 DramcWriteLeveling(PI) end<-----
5343 22:17:30.642225
5344 22:17:30.642290 ==
5345 22:17:30.645718 Dram Type= 6, Freq= 0, CH_0, rank 1
5346 22:17:30.652001 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5347 22:17:30.652085 ==
5348 22:17:30.652151 [Gating] SW mode calibration
5349 22:17:30.661769 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5350 22:17:30.665336 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5351 22:17:30.672019 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5352 22:17:30.674932 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5353 22:17:30.678278 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5354 22:17:30.684879 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5355 22:17:30.688395 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5356 22:17:30.691501 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5357 22:17:30.698197 0 14 24 | B1->B0 | 3434 3333 | 0 1 | (0 0) (0 0)
5358 22:17:30.701257 0 14 28 | B1->B0 | 2a2a 2424 | 1 0 | (1 0) (1 0)
5359 22:17:30.704516 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5360 22:17:30.711694 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5361 22:17:30.714590 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5362 22:17:30.718388 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5363 22:17:30.724497 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5364 22:17:30.727943 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5365 22:17:30.731488 0 15 24 | B1->B0 | 2525 2727 | 0 1 | (0 0) (0 0)
5366 22:17:30.737570 0 15 28 | B1->B0 | 3939 3f3f | 1 0 | (0 0) (0 0)
5367 22:17:30.741234 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5368 22:17:30.744366 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5369 22:17:30.751215 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5370 22:17:30.754173 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5371 22:17:30.757412 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5372 22:17:30.764105 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5373 22:17:30.767616 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5374 22:17:30.770802 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5375 22:17:30.774171 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5376 22:17:30.780879 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5377 22:17:30.783988 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5378 22:17:30.787521 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5379 22:17:30.793976 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5380 22:17:30.797298 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5381 22:17:30.800879 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5382 22:17:30.807210 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5383 22:17:30.810347 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5384 22:17:30.813699 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5385 22:17:30.820203 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5386 22:17:30.823721 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5387 22:17:30.827248 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5388 22:17:30.833486 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5389 22:17:30.837178 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5390 22:17:30.840328 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5391 22:17:30.847135 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5392 22:17:30.850190 Total UI for P1: 0, mck2ui 16
5393 22:17:30.853369 best dqsien dly found for B0: ( 1, 2, 26)
5394 22:17:30.853451 Total UI for P1: 0, mck2ui 16
5395 22:17:30.859975 best dqsien dly found for B1: ( 1, 2, 26)
5396 22:17:30.863566 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5397 22:17:30.866722 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5398 22:17:30.866802
5399 22:17:30.869944 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5400 22:17:30.873483 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5401 22:17:30.876580 [Gating] SW calibration Done
5402 22:17:30.876660 ==
5403 22:17:30.879884 Dram Type= 6, Freq= 0, CH_0, rank 1
5404 22:17:30.883342 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5405 22:17:30.883423 ==
5406 22:17:30.886509 RX Vref Scan: 0
5407 22:17:30.886589
5408 22:17:30.886651 RX Vref 0 -> 0, step: 1
5409 22:17:30.889710
5410 22:17:30.889789 RX Delay -80 -> 252, step: 8
5411 22:17:30.896537 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5412 22:17:30.899667 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5413 22:17:30.902830 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5414 22:17:30.906457 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5415 22:17:30.909744 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5416 22:17:30.912924 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5417 22:17:30.919612 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5418 22:17:30.923149 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5419 22:17:30.926171 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5420 22:17:30.929745 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5421 22:17:30.932693 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5422 22:17:30.936093 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5423 22:17:30.943163 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5424 22:17:30.946429 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5425 22:17:30.949761 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5426 22:17:30.952963 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5427 22:17:30.953044 ==
5428 22:17:30.955984 Dram Type= 6, Freq= 0, CH_0, rank 1
5429 22:17:30.962751 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5430 22:17:30.962833 ==
5431 22:17:30.962898 DQS Delay:
5432 22:17:30.962957 DQS0 = 0, DQS1 = 0
5433 22:17:30.966061 DQM Delay:
5434 22:17:30.966141 DQM0 = 105, DQM1 = 90
5435 22:17:30.969175 DQ Delay:
5436 22:17:30.972882 DQ0 =107, DQ1 =107, DQ2 =99, DQ3 =99
5437 22:17:30.976005 DQ4 =107, DQ5 =95, DQ6 =115, DQ7 =111
5438 22:17:30.979226 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =87
5439 22:17:30.982492 DQ12 =95, DQ13 =91, DQ14 =99, DQ15 =99
5440 22:17:30.982579
5441 22:17:30.982654
5442 22:17:30.982734 ==
5443 22:17:30.985694 Dram Type= 6, Freq= 0, CH_0, rank 1
5444 22:17:30.989006 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5445 22:17:30.989124 ==
5446 22:17:30.989246
5447 22:17:30.989337
5448 22:17:30.992572 TX Vref Scan disable
5449 22:17:30.995682 == TX Byte 0 ==
5450 22:17:30.998992 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5451 22:17:31.002061 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5452 22:17:31.005533 == TX Byte 1 ==
5453 22:17:31.008780 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5454 22:17:31.012400 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5455 22:17:31.012488 ==
5456 22:17:31.015736 Dram Type= 6, Freq= 0, CH_0, rank 1
5457 22:17:31.018700 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5458 22:17:31.022175 ==
5459 22:17:31.022258
5460 22:17:31.022322
5461 22:17:31.022380 TX Vref Scan disable
5462 22:17:31.025747 == TX Byte 0 ==
5463 22:17:31.029217 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5464 22:17:31.035649 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5465 22:17:31.035759 == TX Byte 1 ==
5466 22:17:31.038855 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5467 22:17:31.045679 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5468 22:17:31.045795
5469 22:17:31.045863 [DATLAT]
5470 22:17:31.045926 Freq=933, CH0 RK1
5471 22:17:31.045984
5472 22:17:31.048731 DATLAT Default: 0xb
5473 22:17:31.048835 0, 0xFFFF, sum = 0
5474 22:17:31.052161 1, 0xFFFF, sum = 0
5475 22:17:31.055437 2, 0xFFFF, sum = 0
5476 22:17:31.055521 3, 0xFFFF, sum = 0
5477 22:17:31.058835 4, 0xFFFF, sum = 0
5478 22:17:31.058927 5, 0xFFFF, sum = 0
5479 22:17:31.061951 6, 0xFFFF, sum = 0
5480 22:17:31.062039 7, 0xFFFF, sum = 0
5481 22:17:31.065530 8, 0xFFFF, sum = 0
5482 22:17:31.065623 9, 0xFFFF, sum = 0
5483 22:17:31.068693 10, 0x0, sum = 1
5484 22:17:31.068843 11, 0x0, sum = 2
5485 22:17:31.071817 12, 0x0, sum = 3
5486 22:17:31.071906 13, 0x0, sum = 4
5487 22:17:31.071971 best_step = 11
5488 22:17:31.075469
5489 22:17:31.075551 ==
5490 22:17:31.078567 Dram Type= 6, Freq= 0, CH_0, rank 1
5491 22:17:31.081678 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5492 22:17:31.081787 ==
5493 22:17:31.081880 RX Vref Scan: 0
5494 22:17:31.081969
5495 22:17:31.085365 RX Vref 0 -> 0, step: 1
5496 22:17:31.085446
5497 22:17:31.088534 RX Delay -53 -> 252, step: 4
5498 22:17:31.094973 iDelay=199, Bit 0, Center 104 (19 ~ 190) 172
5499 22:17:31.098195 iDelay=199, Bit 1, Center 106 (19 ~ 194) 176
5500 22:17:31.101850 iDelay=199, Bit 2, Center 100 (15 ~ 186) 172
5501 22:17:31.104852 iDelay=199, Bit 3, Center 100 (19 ~ 182) 164
5502 22:17:31.108031 iDelay=199, Bit 4, Center 106 (23 ~ 190) 168
5503 22:17:31.114630 iDelay=199, Bit 5, Center 98 (11 ~ 186) 176
5504 22:17:31.117845 iDelay=199, Bit 6, Center 112 (27 ~ 198) 172
5505 22:17:31.121264 iDelay=199, Bit 7, Center 112 (27 ~ 198) 172
5506 22:17:31.124731 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5507 22:17:31.127757 iDelay=199, Bit 9, Center 80 (-1 ~ 162) 164
5508 22:17:31.134622 iDelay=199, Bit 10, Center 94 (11 ~ 178) 168
5509 22:17:31.137905 iDelay=199, Bit 11, Center 92 (11 ~ 174) 164
5510 22:17:31.140900 iDelay=199, Bit 12, Center 96 (11 ~ 182) 172
5511 22:17:31.144194 iDelay=199, Bit 13, Center 94 (11 ~ 178) 168
5512 22:17:31.147851 iDelay=199, Bit 14, Center 102 (19 ~ 186) 168
5513 22:17:31.154515 iDelay=199, Bit 15, Center 100 (19 ~ 182) 164
5514 22:17:31.154608 ==
5515 22:17:31.157827 Dram Type= 6, Freq= 0, CH_0, rank 1
5516 22:17:31.160949 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5517 22:17:31.161032 ==
5518 22:17:31.161098 DQS Delay:
5519 22:17:31.164023 DQS0 = 0, DQS1 = 0
5520 22:17:31.164163 DQM Delay:
5521 22:17:31.167582 DQM0 = 104, DQM1 = 92
5522 22:17:31.167664 DQ Delay:
5523 22:17:31.171175 DQ0 =104, DQ1 =106, DQ2 =100, DQ3 =100
5524 22:17:31.174277 DQ4 =106, DQ5 =98, DQ6 =112, DQ7 =112
5525 22:17:31.177453 DQ8 =84, DQ9 =80, DQ10 =94, DQ11 =92
5526 22:17:31.180693 DQ12 =96, DQ13 =94, DQ14 =102, DQ15 =100
5527 22:17:31.180833
5528 22:17:31.180900
5529 22:17:31.190764 [DQSOSCAuto] RK1, (LSB)MR18= 0x2607, (MSB)MR19= 0x505, tDQSOscB0 = 419 ps tDQSOscB1 = 409 ps
5530 22:17:31.193965 CH0 RK1: MR19=505, MR18=2607
5531 22:17:31.196992 CH0_RK1: MR19=0x505, MR18=0x2607, DQSOSC=409, MR23=63, INC=64, DEC=43
5532 22:17:31.200313 [RxdqsGatingPostProcess] freq 933
5533 22:17:31.207298 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5534 22:17:31.210384 best DQS0 dly(2T, 0.5T) = (0, 10)
5535 22:17:31.213797 best DQS1 dly(2T, 0.5T) = (0, 10)
5536 22:17:31.217290 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5537 22:17:31.220360 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5538 22:17:31.223816 best DQS0 dly(2T, 0.5T) = (0, 10)
5539 22:17:31.227317 best DQS1 dly(2T, 0.5T) = (0, 10)
5540 22:17:31.230626 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5541 22:17:31.233709 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5542 22:17:31.236907 Pre-setting of DQS Precalculation
5543 22:17:31.240363 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5544 22:17:31.240662 ==
5545 22:17:31.243986 Dram Type= 6, Freq= 0, CH_1, rank 0
5546 22:17:31.247002 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5547 22:17:31.247363 ==
5548 22:17:31.253832 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5549 22:17:31.260001 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5550 22:17:31.263571 [CA 0] Center 37 (7~68) winsize 62
5551 22:17:31.266751 [CA 1] Center 37 (7~68) winsize 62
5552 22:17:31.270100 [CA 2] Center 36 (6~66) winsize 61
5553 22:17:31.273702 [CA 3] Center 34 (4~65) winsize 62
5554 22:17:31.276923 [CA 4] Center 35 (5~65) winsize 61
5555 22:17:31.279766 [CA 5] Center 34 (4~65) winsize 62
5556 22:17:31.280082
5557 22:17:31.283445 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5558 22:17:31.283718
5559 22:17:31.286700 [CATrainingPosCal] consider 1 rank data
5560 22:17:31.289860 u2DelayCellTimex100 = 270/100 ps
5561 22:17:31.292969 CA0 delay=37 (7~68),Diff = 3 PI (18 cell)
5562 22:17:31.296139 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5563 22:17:31.299654 CA2 delay=36 (6~66),Diff = 2 PI (12 cell)
5564 22:17:31.306525 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5565 22:17:31.309638 CA4 delay=35 (5~65),Diff = 1 PI (6 cell)
5566 22:17:31.312726 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
5567 22:17:31.312862
5568 22:17:31.316349 CA PerBit enable=1, Macro0, CA PI delay=34
5569 22:17:31.316469
5570 22:17:31.319169 [CBTSetCACLKResult] CA Dly = 34
5571 22:17:31.319290 CS Dly: 6 (0~37)
5572 22:17:31.319385 ==
5573 22:17:31.322678 Dram Type= 6, Freq= 0, CH_1, rank 1
5574 22:17:31.329134 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5575 22:17:31.329260 ==
5576 22:17:31.332633 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5577 22:17:31.339040 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5578 22:17:31.342615 [CA 0] Center 38 (8~68) winsize 61
5579 22:17:31.346252 [CA 1] Center 38 (7~69) winsize 63
5580 22:17:31.349283 [CA 2] Center 35 (5~66) winsize 62
5581 22:17:31.352532 [CA 3] Center 35 (5~65) winsize 61
5582 22:17:31.355694 [CA 4] Center 35 (5~65) winsize 61
5583 22:17:31.359192 [CA 5] Center 34 (4~64) winsize 61
5584 22:17:31.359276
5585 22:17:31.362557 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5586 22:17:31.362640
5587 22:17:31.365732 [CATrainingPosCal] consider 2 rank data
5588 22:17:31.369141 u2DelayCellTimex100 = 270/100 ps
5589 22:17:31.372320 CA0 delay=38 (8~68),Diff = 4 PI (24 cell)
5590 22:17:31.375696 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5591 22:17:31.382386 CA2 delay=36 (6~66),Diff = 2 PI (12 cell)
5592 22:17:31.385873 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5593 22:17:31.389163 CA4 delay=35 (5~65),Diff = 1 PI (6 cell)
5594 22:17:31.392404 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5595 22:17:31.392525
5596 22:17:31.395494 CA PerBit enable=1, Macro0, CA PI delay=34
5597 22:17:31.395579
5598 22:17:31.399087 [CBTSetCACLKResult] CA Dly = 34
5599 22:17:31.399172 CS Dly: 7 (0~39)
5600 22:17:31.399239
5601 22:17:31.405601 ----->DramcWriteLeveling(PI) begin...
5602 22:17:31.405688 ==
5603 22:17:31.408644 Dram Type= 6, Freq= 0, CH_1, rank 0
5604 22:17:31.411853 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5605 22:17:31.411939 ==
5606 22:17:31.415457 Write leveling (Byte 0): 26 => 26
5607 22:17:31.418621 Write leveling (Byte 1): 26 => 26
5608 22:17:31.421909 DramcWriteLeveling(PI) end<-----
5609 22:17:31.421993
5610 22:17:31.422059 ==
5611 22:17:31.425103 Dram Type= 6, Freq= 0, CH_1, rank 0
5612 22:17:31.428421 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5613 22:17:31.428506 ==
5614 22:17:31.431839 [Gating] SW mode calibration
5615 22:17:31.438209 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5616 22:17:31.445100 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5617 22:17:31.448212 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5618 22:17:31.451761 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5619 22:17:31.458168 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5620 22:17:31.461578 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5621 22:17:31.465332 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5622 22:17:31.472028 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5623 22:17:31.475044 0 14 24 | B1->B0 | 3333 3232 | 1 0 | (1 0) (1 0)
5624 22:17:31.478399 0 14 28 | B1->B0 | 2424 2424 | 0 0 | (0 0) (0 0)
5625 22:17:31.484612 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5626 22:17:31.488236 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5627 22:17:31.491205 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5628 22:17:31.497792 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5629 22:17:31.501288 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5630 22:17:31.504578 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5631 22:17:31.511031 0 15 24 | B1->B0 | 2525 2929 | 0 1 | (0 0) (0 0)
5632 22:17:31.514673 0 15 28 | B1->B0 | 3c3c 4343 | 0 0 | (0 0) (0 0)
5633 22:17:31.517739 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5634 22:17:31.524043 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5635 22:17:31.527601 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5636 22:17:31.530731 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5637 22:17:31.537147 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5638 22:17:31.540673 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5639 22:17:31.543822 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5640 22:17:31.550758 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5641 22:17:31.554313 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5642 22:17:31.557444 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5643 22:17:31.563818 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5644 22:17:31.567150 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5645 22:17:31.570789 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5646 22:17:31.577174 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5647 22:17:31.580409 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5648 22:17:31.583685 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5649 22:17:31.590506 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5650 22:17:31.593677 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5651 22:17:31.597159 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5652 22:17:31.603529 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5653 22:17:31.607012 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5654 22:17:31.610373 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5655 22:17:31.616647 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5656 22:17:31.616826 Total UI for P1: 0, mck2ui 16
5657 22:17:31.623424 best dqsien dly found for B0: ( 1, 2, 20)
5658 22:17:31.626760 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5659 22:17:31.630166 Total UI for P1: 0, mck2ui 16
5660 22:17:31.633618 best dqsien dly found for B1: ( 1, 2, 24)
5661 22:17:31.636807 best DQS0 dly(MCK, UI, PI) = (1, 2, 20)
5662 22:17:31.639732 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5663 22:17:31.639821
5664 22:17:31.643159 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 20)
5665 22:17:31.646592 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5666 22:17:31.650049 [Gating] SW calibration Done
5667 22:17:31.650132 ==
5668 22:17:31.653046 Dram Type= 6, Freq= 0, CH_1, rank 0
5669 22:17:31.656433 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5670 22:17:31.656523 ==
5671 22:17:31.659935 RX Vref Scan: 0
5672 22:17:31.660098
5673 22:17:31.663210 RX Vref 0 -> 0, step: 1
5674 22:17:31.663386
5675 22:17:31.663487 RX Delay -80 -> 252, step: 8
5676 22:17:31.669772 iDelay=208, Bit 0, Center 107 (24 ~ 191) 168
5677 22:17:31.673272 iDelay=208, Bit 1, Center 99 (16 ~ 183) 168
5678 22:17:31.676496 iDelay=208, Bit 2, Center 95 (8 ~ 183) 176
5679 22:17:31.680126 iDelay=208, Bit 3, Center 103 (16 ~ 191) 176
5680 22:17:31.683231 iDelay=208, Bit 4, Center 103 (16 ~ 191) 176
5681 22:17:31.689898 iDelay=208, Bit 5, Center 111 (24 ~ 199) 176
5682 22:17:31.692990 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5683 22:17:31.696560 iDelay=208, Bit 7, Center 103 (16 ~ 191) 176
5684 22:17:31.699905 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5685 22:17:31.702802 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5686 22:17:31.709596 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5687 22:17:31.713192 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5688 22:17:31.716571 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5689 22:17:31.719710 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5690 22:17:31.722910 iDelay=208, Bit 14, Center 103 (8 ~ 199) 192
5691 22:17:31.729378 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5692 22:17:31.729868 ==
5693 22:17:31.733226 Dram Type= 6, Freq= 0, CH_1, rank 0
5694 22:17:31.736290 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5695 22:17:31.736715 ==
5696 22:17:31.737101 DQS Delay:
5697 22:17:31.739728 DQS0 = 0, DQS1 = 0
5698 22:17:31.740148 DQM Delay:
5699 22:17:31.742904 DQM0 = 104, DQM1 = 96
5700 22:17:31.743324 DQ Delay:
5701 22:17:31.745805 DQ0 =107, DQ1 =99, DQ2 =95, DQ3 =103
5702 22:17:31.749404 DQ4 =103, DQ5 =111, DQ6 =115, DQ7 =103
5703 22:17:31.752859 DQ8 =83, DQ9 =83, DQ10 =99, DQ11 =87
5704 22:17:31.755873 DQ12 =107, DQ13 =103, DQ14 =103, DQ15 =103
5705 22:17:31.756465
5706 22:17:31.756983
5707 22:17:31.757312 ==
5708 22:17:31.759329 Dram Type= 6, Freq= 0, CH_1, rank 0
5709 22:17:31.765875 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5710 22:17:31.766449 ==
5711 22:17:31.766934
5712 22:17:31.767392
5713 22:17:31.767774 TX Vref Scan disable
5714 22:17:31.769546 == TX Byte 0 ==
5715 22:17:31.772741 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5716 22:17:31.779717 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5717 22:17:31.780212 == TX Byte 1 ==
5718 22:17:31.783026 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5719 22:17:31.789134 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5720 22:17:31.789567 ==
5721 22:17:31.792609 Dram Type= 6, Freq= 0, CH_1, rank 0
5722 22:17:31.796115 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5723 22:17:31.796547 ==
5724 22:17:31.796988
5725 22:17:31.797324
5726 22:17:31.799329 TX Vref Scan disable
5727 22:17:31.799754 == TX Byte 0 ==
5728 22:17:31.805792 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5729 22:17:31.809018 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5730 22:17:31.812560 == TX Byte 1 ==
5731 22:17:31.815606 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5732 22:17:31.819207 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5733 22:17:31.819672
5734 22:17:31.820004 [DATLAT]
5735 22:17:31.822382 Freq=933, CH1 RK0
5736 22:17:31.822803
5737 22:17:31.823166 DATLAT Default: 0xd
5738 22:17:31.825299 0, 0xFFFF, sum = 0
5739 22:17:31.829135 1, 0xFFFF, sum = 0
5740 22:17:31.829555 2, 0xFFFF, sum = 0
5741 22:17:31.832362 3, 0xFFFF, sum = 0
5742 22:17:31.832826 4, 0xFFFF, sum = 0
5743 22:17:31.835618 5, 0xFFFF, sum = 0
5744 22:17:31.836042 6, 0xFFFF, sum = 0
5745 22:17:31.838778 7, 0xFFFF, sum = 0
5746 22:17:31.839206 8, 0xFFFF, sum = 0
5747 22:17:31.841954 9, 0xFFFF, sum = 0
5748 22:17:31.842561 10, 0x0, sum = 1
5749 22:17:31.845185 11, 0x0, sum = 2
5750 22:17:31.845780 12, 0x0, sum = 3
5751 22:17:31.848495 13, 0x0, sum = 4
5752 22:17:31.849127 best_step = 11
5753 22:17:31.849645
5754 22:17:31.849980 ==
5755 22:17:31.851922 Dram Type= 6, Freq= 0, CH_1, rank 0
5756 22:17:31.855147 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5757 22:17:31.855592 ==
5758 22:17:31.858580 RX Vref Scan: 1
5759 22:17:31.859001
5760 22:17:31.862194 RX Vref 0 -> 0, step: 1
5761 22:17:31.862724
5762 22:17:31.863069 RX Delay -53 -> 252, step: 4
5763 22:17:31.865455
5764 22:17:31.865888 Set Vref, RX VrefLevel [Byte0]: 51
5765 22:17:31.868720 [Byte1]: 52
5766 22:17:31.873476
5767 22:17:31.873973 Final RX Vref Byte 0 = 51 to rank0
5768 22:17:31.876617 Final RX Vref Byte 1 = 52 to rank0
5769 22:17:31.880284 Final RX Vref Byte 0 = 51 to rank1
5770 22:17:31.883405 Final RX Vref Byte 1 = 52 to rank1==
5771 22:17:31.886577 Dram Type= 6, Freq= 0, CH_1, rank 0
5772 22:17:31.893184 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5773 22:17:31.893661 ==
5774 22:17:31.894179 DQS Delay:
5775 22:17:31.896156 DQS0 = 0, DQS1 = 0
5776 22:17:31.896573 DQM Delay:
5777 22:17:31.896938 DQM0 = 104, DQM1 = 97
5778 22:17:31.899465 DQ Delay:
5779 22:17:31.903103 DQ0 =108, DQ1 =100, DQ2 =96, DQ3 =104
5780 22:17:31.906214 DQ4 =104, DQ5 =112, DQ6 =114, DQ7 =100
5781 22:17:31.909810 DQ8 =88, DQ9 =84, DQ10 =100, DQ11 =92
5782 22:17:31.912940 DQ12 =106, DQ13 =104, DQ14 =104, DQ15 =104
5783 22:17:31.913363
5784 22:17:31.913694
5785 22:17:31.922550 [DQSOSCAuto] RK0, (LSB)MR18= 0x1831, (MSB)MR19= 0x505, tDQSOscB0 = 406 ps tDQSOscB1 = 414 ps
5786 22:17:31.923018 CH1 RK0: MR19=505, MR18=1831
5787 22:17:31.928969 CH1_RK0: MR19=0x505, MR18=0x1831, DQSOSC=406, MR23=63, INC=65, DEC=43
5788 22:17:31.929615
5789 22:17:31.932692 ----->DramcWriteLeveling(PI) begin...
5790 22:17:31.933226 ==
5791 22:17:31.935910 Dram Type= 6, Freq= 0, CH_1, rank 1
5792 22:17:31.942288 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5793 22:17:31.942720 ==
5794 22:17:31.945605 Write leveling (Byte 0): 26 => 26
5795 22:17:31.949359 Write leveling (Byte 1): 29 => 29
5796 22:17:31.949782 DramcWriteLeveling(PI) end<-----
5797 22:17:31.950162
5798 22:17:31.952077 ==
5799 22:17:31.955763 Dram Type= 6, Freq= 0, CH_1, rank 1
5800 22:17:31.958929 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5801 22:17:31.959348 ==
5802 22:17:31.962498 [Gating] SW mode calibration
5803 22:17:31.968868 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5804 22:17:31.972319 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5805 22:17:31.978951 0 14 0 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
5806 22:17:31.982110 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5807 22:17:31.985153 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5808 22:17:31.992248 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5809 22:17:31.995248 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5810 22:17:31.998600 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5811 22:17:32.005193 0 14 24 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
5812 22:17:32.008289 0 14 28 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (1 0)
5813 22:17:32.012075 0 15 0 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
5814 22:17:32.018556 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5815 22:17:32.021770 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5816 22:17:32.025174 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5817 22:17:32.031619 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5818 22:17:32.035019 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5819 22:17:32.038108 0 15 24 | B1->B0 | 2f2f 2424 | 0 0 | (0 0) (0 0)
5820 22:17:32.045132 0 15 28 | B1->B0 | 3f3f 3737 | 0 0 | (0 0) (0 0)
5821 22:17:32.048264 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5822 22:17:32.051486 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5823 22:17:32.058411 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5824 22:17:32.061276 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5825 22:17:32.064638 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5826 22:17:32.071278 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5827 22:17:32.074859 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5828 22:17:32.078085 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5829 22:17:32.084619 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5830 22:17:32.087821 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5831 22:17:32.091062 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5832 22:17:32.097895 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5833 22:17:32.101120 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5834 22:17:32.104505 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5835 22:17:32.110927 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5836 22:17:32.114611 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5837 22:17:32.117677 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5838 22:17:32.124642 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5839 22:17:32.127847 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5840 22:17:32.130714 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5841 22:17:32.137537 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5842 22:17:32.140919 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5843 22:17:32.144126 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5844 22:17:32.150899 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5845 22:17:32.151357 Total UI for P1: 0, mck2ui 16
5846 22:17:32.157591 best dqsien dly found for B0: ( 1, 2, 24)
5847 22:17:32.158080 Total UI for P1: 0, mck2ui 16
5848 22:17:32.160637 best dqsien dly found for B1: ( 1, 2, 24)
5849 22:17:32.167412 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5850 22:17:32.170730 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5851 22:17:32.171191
5852 22:17:32.173961 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5853 22:17:32.177154 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5854 22:17:32.180857 [Gating] SW calibration Done
5855 22:17:32.181282 ==
5856 22:17:32.184000 Dram Type= 6, Freq= 0, CH_1, rank 1
5857 22:17:32.187254 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5858 22:17:32.187761 ==
5859 22:17:32.190675 RX Vref Scan: 0
5860 22:17:32.191105
5861 22:17:32.191437 RX Vref 0 -> 0, step: 1
5862 22:17:32.191749
5863 22:17:32.193741 RX Delay -80 -> 252, step: 8
5864 22:17:32.196879 iDelay=200, Bit 0, Center 107 (24 ~ 191) 168
5865 22:17:32.203983 iDelay=200, Bit 1, Center 95 (8 ~ 183) 176
5866 22:17:32.207078 iDelay=200, Bit 2, Center 87 (0 ~ 175) 176
5867 22:17:32.210187 iDelay=200, Bit 3, Center 99 (8 ~ 191) 184
5868 22:17:32.213439 iDelay=200, Bit 4, Center 103 (16 ~ 191) 176
5869 22:17:32.217087 iDelay=200, Bit 5, Center 111 (24 ~ 199) 176
5870 22:17:32.220032 iDelay=200, Bit 6, Center 111 (24 ~ 199) 176
5871 22:17:32.226689 iDelay=200, Bit 7, Center 99 (8 ~ 191) 184
5872 22:17:32.229860 iDelay=200, Bit 8, Center 83 (-8 ~ 175) 184
5873 22:17:32.233117 iDelay=200, Bit 9, Center 87 (0 ~ 175) 176
5874 22:17:32.236733 iDelay=200, Bit 10, Center 95 (0 ~ 191) 192
5875 22:17:32.239673 iDelay=200, Bit 11, Center 87 (-8 ~ 183) 192
5876 22:17:32.246635 iDelay=200, Bit 12, Center 103 (8 ~ 199) 192
5877 22:17:32.249905 iDelay=200, Bit 13, Center 103 (8 ~ 199) 192
5878 22:17:32.253172 iDelay=200, Bit 14, Center 103 (8 ~ 199) 192
5879 22:17:32.256654 iDelay=200, Bit 15, Center 103 (8 ~ 199) 192
5880 22:17:32.257129 ==
5881 22:17:32.259681 Dram Type= 6, Freq= 0, CH_1, rank 1
5882 22:17:32.263049 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5883 22:17:32.266357 ==
5884 22:17:32.266789 DQS Delay:
5885 22:17:32.267132 DQS0 = 0, DQS1 = 0
5886 22:17:32.269505 DQM Delay:
5887 22:17:32.269928 DQM0 = 101, DQM1 = 95
5888 22:17:32.272960 DQ Delay:
5889 22:17:32.276306 DQ0 =107, DQ1 =95, DQ2 =87, DQ3 =99
5890 22:17:32.279731 DQ4 =103, DQ5 =111, DQ6 =111, DQ7 =99
5891 22:17:32.282907 DQ8 =83, DQ9 =87, DQ10 =95, DQ11 =87
5892 22:17:32.286120 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =103
5893 22:17:32.286644
5894 22:17:32.286986
5895 22:17:32.287299 ==
5896 22:17:32.289481 Dram Type= 6, Freq= 0, CH_1, rank 1
5897 22:17:32.292680 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5898 22:17:32.293132 ==
5899 22:17:32.293473
5900 22:17:32.293832
5901 22:17:32.296327 TX Vref Scan disable
5902 22:17:32.299364 == TX Byte 0 ==
5903 22:17:32.302885 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5904 22:17:32.306164 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5905 22:17:32.309230 == TX Byte 1 ==
5906 22:17:32.312571 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5907 22:17:32.316317 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5908 22:17:32.316739 ==
5909 22:17:32.319493 Dram Type= 6, Freq= 0, CH_1, rank 1
5910 22:17:32.322675 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5911 22:17:32.326110 ==
5912 22:17:32.326527
5913 22:17:32.326854
5914 22:17:32.327160 TX Vref Scan disable
5915 22:17:32.329660 == TX Byte 0 ==
5916 22:17:32.332714 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5917 22:17:32.339644 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5918 22:17:32.340073 == TX Byte 1 ==
5919 22:17:32.342955 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5920 22:17:32.349261 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5921 22:17:32.349689
5922 22:17:32.350077 [DATLAT]
5923 22:17:32.350574 Freq=933, CH1 RK1
5924 22:17:32.351097
5925 22:17:32.352386 DATLAT Default: 0xb
5926 22:17:32.352840 0, 0xFFFF, sum = 0
5927 22:17:32.355726 1, 0xFFFF, sum = 0
5928 22:17:32.359077 2, 0xFFFF, sum = 0
5929 22:17:32.359581 3, 0xFFFF, sum = 0
5930 22:17:32.362743 4, 0xFFFF, sum = 0
5931 22:17:32.363295 5, 0xFFFF, sum = 0
5932 22:17:32.365638 6, 0xFFFF, sum = 0
5933 22:17:32.366073 7, 0xFFFF, sum = 0
5934 22:17:32.369226 8, 0xFFFF, sum = 0
5935 22:17:32.369663 9, 0xFFFF, sum = 0
5936 22:17:32.372284 10, 0x0, sum = 1
5937 22:17:32.372716 11, 0x0, sum = 2
5938 22:17:32.376018 12, 0x0, sum = 3
5939 22:17:32.376607 13, 0x0, sum = 4
5940 22:17:32.377029 best_step = 11
5941 22:17:32.379274
5942 22:17:32.379809 ==
5943 22:17:32.382200 Dram Type= 6, Freq= 0, CH_1, rank 1
5944 22:17:32.385559 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5945 22:17:32.386008 ==
5946 22:17:32.386440 RX Vref Scan: 0
5947 22:17:32.386762
5948 22:17:32.389058 RX Vref 0 -> 0, step: 1
5949 22:17:32.389477
5950 22:17:32.392233 RX Delay -53 -> 252, step: 4
5951 22:17:32.398849 iDelay=199, Bit 0, Center 110 (35 ~ 186) 152
5952 22:17:32.401886 iDelay=199, Bit 1, Center 98 (19 ~ 178) 160
5953 22:17:32.405766 iDelay=199, Bit 2, Center 94 (15 ~ 174) 160
5954 22:17:32.408748 iDelay=199, Bit 3, Center 104 (23 ~ 186) 164
5955 22:17:32.412055 iDelay=199, Bit 4, Center 104 (23 ~ 186) 164
5956 22:17:32.418533 iDelay=199, Bit 5, Center 116 (35 ~ 198) 164
5957 22:17:32.421770 iDelay=199, Bit 6, Center 114 (35 ~ 194) 160
5958 22:17:32.425029 iDelay=199, Bit 7, Center 102 (23 ~ 182) 160
5959 22:17:32.428887 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5960 22:17:32.431655 iDelay=199, Bit 9, Center 90 (7 ~ 174) 168
5961 22:17:32.435602 iDelay=199, Bit 10, Center 98 (15 ~ 182) 168
5962 22:17:32.441957 iDelay=199, Bit 11, Center 92 (7 ~ 178) 172
5963 22:17:32.445031 iDelay=199, Bit 12, Center 106 (19 ~ 194) 176
5964 22:17:32.448386 iDelay=199, Bit 13, Center 102 (15 ~ 190) 176
5965 22:17:32.451806 iDelay=199, Bit 14, Center 106 (19 ~ 194) 176
5966 22:17:32.455135 iDelay=199, Bit 15, Center 106 (19 ~ 194) 176
5967 22:17:32.458521 ==
5968 22:17:32.462200 Dram Type= 6, Freq= 0, CH_1, rank 1
5969 22:17:32.464745 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5970 22:17:32.465219 ==
5971 22:17:32.465558 DQS Delay:
5972 22:17:32.468302 DQS0 = 0, DQS1 = 0
5973 22:17:32.468856 DQM Delay:
5974 22:17:32.471963 DQM0 = 105, DQM1 = 98
5975 22:17:32.472393 DQ Delay:
5976 22:17:32.474823 DQ0 =110, DQ1 =98, DQ2 =94, DQ3 =104
5977 22:17:32.478291 DQ4 =104, DQ5 =116, DQ6 =114, DQ7 =102
5978 22:17:32.481846 DQ8 =84, DQ9 =90, DQ10 =98, DQ11 =92
5979 22:17:32.485098 DQ12 =106, DQ13 =102, DQ14 =106, DQ15 =106
5980 22:17:32.485608
5981 22:17:32.485948
5982 22:17:32.494857 [DQSOSCAuto] RK1, (LSB)MR18= 0x2502, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 410 ps
5983 22:17:32.495286 CH1 RK1: MR19=505, MR18=2502
5984 22:17:32.501111 CH1_RK1: MR19=0x505, MR18=0x2502, DQSOSC=410, MR23=63, INC=64, DEC=42
5985 22:17:32.504464 [RxdqsGatingPostProcess] freq 933
5986 22:17:32.511366 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5987 22:17:32.514601 best DQS0 dly(2T, 0.5T) = (0, 10)
5988 22:17:32.517766 best DQS1 dly(2T, 0.5T) = (0, 10)
5989 22:17:32.520934 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5990 22:17:32.524131 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5991 22:17:32.527637 best DQS0 dly(2T, 0.5T) = (0, 10)
5992 22:17:32.530842 best DQS1 dly(2T, 0.5T) = (0, 10)
5993 22:17:32.533990 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5994 22:17:32.537219 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5995 22:17:32.537696 Pre-setting of DQS Precalculation
5996 22:17:32.543986 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5997 22:17:32.550612 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5998 22:17:32.557772 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5999 22:17:32.558207
6000 22:17:32.558545
6001 22:17:32.560452 [Calibration Summary] 1866 Mbps
6002 22:17:32.563946 CH 0, Rank 0
6003 22:17:32.564584 SW Impedance : PASS
6004 22:17:32.567540 DUTY Scan : NO K
6005 22:17:32.570705 ZQ Calibration : PASS
6006 22:17:32.571336 Jitter Meter : NO K
6007 22:17:32.573936 CBT Training : PASS
6008 22:17:32.577129 Write leveling : PASS
6009 22:17:32.577599 RX DQS gating : PASS
6010 22:17:32.580301 RX DQ/DQS(RDDQC) : PASS
6011 22:17:32.584046 TX DQ/DQS : PASS
6012 22:17:32.584704 RX DATLAT : PASS
6013 22:17:32.586809 RX DQ/DQS(Engine): PASS
6014 22:17:32.590481 TX OE : NO K
6015 22:17:32.590920 All Pass.
6016 22:17:32.591256
6017 22:17:32.591614 CH 0, Rank 1
6018 22:17:32.593460 SW Impedance : PASS
6019 22:17:32.597078 DUTY Scan : NO K
6020 22:17:32.597702 ZQ Calibration : PASS
6021 22:17:32.600271 Jitter Meter : NO K
6022 22:17:32.600706 CBT Training : PASS
6023 22:17:32.603614 Write leveling : PASS
6024 22:17:32.606912 RX DQS gating : PASS
6025 22:17:32.607411 RX DQ/DQS(RDDQC) : PASS
6026 22:17:32.610510 TX DQ/DQS : PASS
6027 22:17:32.613443 RX DATLAT : PASS
6028 22:17:32.613916 RX DQ/DQS(Engine): PASS
6029 22:17:32.616536 TX OE : NO K
6030 22:17:32.616992 All Pass.
6031 22:17:32.617363
6032 22:17:32.620162 CH 1, Rank 0
6033 22:17:32.620626 SW Impedance : PASS
6034 22:17:32.623569 DUTY Scan : NO K
6035 22:17:32.626763 ZQ Calibration : PASS
6036 22:17:32.627228 Jitter Meter : NO K
6037 22:17:32.630022 CBT Training : PASS
6038 22:17:32.633092 Write leveling : PASS
6039 22:17:32.633518 RX DQS gating : PASS
6040 22:17:32.636098 RX DQ/DQS(RDDQC) : PASS
6041 22:17:32.639824 TX DQ/DQS : PASS
6042 22:17:32.640249 RX DATLAT : PASS
6043 22:17:32.643114 RX DQ/DQS(Engine): PASS
6044 22:17:32.646179 TX OE : NO K
6045 22:17:32.646609 All Pass.
6046 22:17:32.646945
6047 22:17:32.647289 CH 1, Rank 1
6048 22:17:32.649514 SW Impedance : PASS
6049 22:17:32.652674 DUTY Scan : NO K
6050 22:17:32.653123 ZQ Calibration : PASS
6051 22:17:32.656318 Jitter Meter : NO K
6052 22:17:32.659725 CBT Training : PASS
6053 22:17:32.660416 Write leveling : PASS
6054 22:17:32.662645 RX DQS gating : PASS
6055 22:17:32.666162 RX DQ/DQS(RDDQC) : PASS
6056 22:17:32.666590 TX DQ/DQS : PASS
6057 22:17:32.669596 RX DATLAT : PASS
6058 22:17:32.670021 RX DQ/DQS(Engine): PASS
6059 22:17:32.672634 TX OE : NO K
6060 22:17:32.673098 All Pass.
6061 22:17:32.673440
6062 22:17:32.675852 DramC Write-DBI off
6063 22:17:32.679565 PER_BANK_REFRESH: Hybrid Mode
6064 22:17:32.679870 TX_TRACKING: ON
6065 22:17:32.689556 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6066 22:17:32.692550 [FAST_K] Save calibration result to emmc
6067 22:17:32.695667 dramc_set_vcore_voltage set vcore to 650000
6068 22:17:32.698796 Read voltage for 400, 6
6069 22:17:32.699029 Vio18 = 0
6070 22:17:32.702419 Vcore = 650000
6071 22:17:32.702605 Vdram = 0
6072 22:17:32.702751 Vddq = 0
6073 22:17:32.702888 Vmddr = 0
6074 22:17:32.708757 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6075 22:17:32.715197 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6076 22:17:32.715324 MEM_TYPE=3, freq_sel=20
6077 22:17:32.718705 sv_algorithm_assistance_LP4_800
6078 22:17:32.722005 ============ PULL DRAM RESETB DOWN ============
6079 22:17:32.728694 ========== PULL DRAM RESETB DOWN end =========
6080 22:17:32.731657 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6081 22:17:32.735176 ===================================
6082 22:17:32.738190 LPDDR4 DRAM CONFIGURATION
6083 22:17:32.741822 ===================================
6084 22:17:32.741918 EX_ROW_EN[0] = 0x0
6085 22:17:32.745198 EX_ROW_EN[1] = 0x0
6086 22:17:32.745289 LP4Y_EN = 0x0
6087 22:17:32.748353 WORK_FSP = 0x0
6088 22:17:32.751644 WL = 0x2
6089 22:17:32.751761 RL = 0x2
6090 22:17:32.754907 BL = 0x2
6091 22:17:32.754995 RPST = 0x0
6092 22:17:32.758623 RD_PRE = 0x0
6093 22:17:32.758711 WR_PRE = 0x1
6094 22:17:32.761615 WR_PST = 0x0
6095 22:17:32.761703 DBI_WR = 0x0
6096 22:17:32.764641 DBI_RD = 0x0
6097 22:17:32.764781 OTF = 0x1
6098 22:17:32.768175 ===================================
6099 22:17:32.771607 ===================================
6100 22:17:32.774817 ANA top config
6101 22:17:32.777897 ===================================
6102 22:17:32.777990 DLL_ASYNC_EN = 0
6103 22:17:32.781246 ALL_SLAVE_EN = 1
6104 22:17:32.784509 NEW_RANK_MODE = 1
6105 22:17:32.787705 DLL_IDLE_MODE = 1
6106 22:17:32.791491 LP45_APHY_COMB_EN = 1
6107 22:17:32.791602 TX_ODT_DIS = 1
6108 22:17:32.794563 NEW_8X_MODE = 1
6109 22:17:32.798104 ===================================
6110 22:17:32.801273 ===================================
6111 22:17:32.804686 data_rate = 800
6112 22:17:32.807847 CKR = 1
6113 22:17:32.810949 DQ_P2S_RATIO = 4
6114 22:17:32.814424 ===================================
6115 22:17:32.814511 CA_P2S_RATIO = 4
6116 22:17:32.817777 DQ_CA_OPEN = 0
6117 22:17:32.820787 DQ_SEMI_OPEN = 1
6118 22:17:32.824132 CA_SEMI_OPEN = 1
6119 22:17:32.827361 CA_FULL_RATE = 0
6120 22:17:32.831105 DQ_CKDIV4_EN = 0
6121 22:17:32.831190 CA_CKDIV4_EN = 1
6122 22:17:32.834286 CA_PREDIV_EN = 0
6123 22:17:32.837699 PH8_DLY = 0
6124 22:17:32.840682 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6125 22:17:32.843824 DQ_AAMCK_DIV = 0
6126 22:17:32.847450 CA_AAMCK_DIV = 0
6127 22:17:32.850708 CA_ADMCK_DIV = 4
6128 22:17:32.850792 DQ_TRACK_CA_EN = 0
6129 22:17:32.853834 CA_PICK = 800
6130 22:17:32.857182 CA_MCKIO = 400
6131 22:17:32.860412 MCKIO_SEMI = 400
6132 22:17:32.863790 PLL_FREQ = 3016
6133 22:17:32.867281 DQ_UI_PI_RATIO = 32
6134 22:17:32.870597 CA_UI_PI_RATIO = 32
6135 22:17:32.873874 ===================================
6136 22:17:32.876929 ===================================
6137 22:17:32.877059 memory_type:LPDDR4
6138 22:17:32.880340 GP_NUM : 10
6139 22:17:32.883648 SRAM_EN : 1
6140 22:17:32.883753 MD32_EN : 0
6141 22:17:32.886934 ===================================
6142 22:17:32.890156 [ANA_INIT] >>>>>>>>>>>>>>
6143 22:17:32.893314 <<<<<< [CONFIGURE PHASE]: ANA_TX
6144 22:17:32.896673 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6145 22:17:32.900080 ===================================
6146 22:17:32.903577 data_rate = 800,PCW = 0X7400
6147 22:17:32.906770 ===================================
6148 22:17:32.910183 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6149 22:17:32.913467 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6150 22:17:32.926747 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6151 22:17:32.929841 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6152 22:17:32.933602 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6153 22:17:32.936941 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6154 22:17:32.940174 [ANA_INIT] flow start
6155 22:17:32.943468 [ANA_INIT] PLL >>>>>>>>
6156 22:17:32.943929 [ANA_INIT] PLL <<<<<<<<
6157 22:17:32.946648 [ANA_INIT] MIDPI >>>>>>>>
6158 22:17:32.950029 [ANA_INIT] MIDPI <<<<<<<<
6159 22:17:32.950452 [ANA_INIT] DLL >>>>>>>>
6160 22:17:32.953675 [ANA_INIT] flow end
6161 22:17:32.956816 ============ LP4 DIFF to SE enter ============
6162 22:17:32.960069 ============ LP4 DIFF to SE exit ============
6163 22:17:32.963467 [ANA_INIT] <<<<<<<<<<<<<
6164 22:17:32.966559 [Flow] Enable top DCM control >>>>>
6165 22:17:32.969854 [Flow] Enable top DCM control <<<<<
6166 22:17:32.972853 Enable DLL master slave shuffle
6167 22:17:32.979738 ==============================================================
6168 22:17:32.979923 Gating Mode config
6169 22:17:32.986160 ==============================================================
6170 22:17:32.989191 Config description:
6171 22:17:32.995820 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6172 22:17:33.002655 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6173 22:17:33.009743 SELPH_MODE 0: By rank 1: By Phase
6174 22:17:33.015977 ==============================================================
6175 22:17:33.019456 GAT_TRACK_EN = 0
6176 22:17:33.019922 RX_GATING_MODE = 2
6177 22:17:33.022628 RX_GATING_TRACK_MODE = 2
6178 22:17:33.026006 SELPH_MODE = 1
6179 22:17:33.029546 PICG_EARLY_EN = 1
6180 22:17:33.032650 VALID_LAT_VALUE = 1
6181 22:17:33.039288 ==============================================================
6182 22:17:33.042599 Enter into Gating configuration >>>>
6183 22:17:33.045800 Exit from Gating configuration <<<<
6184 22:17:33.049080 Enter into DVFS_PRE_config >>>>>
6185 22:17:33.058832 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6186 22:17:33.062056 Exit from DVFS_PRE_config <<<<<
6187 22:17:33.065291 Enter into PICG configuration >>>>
6188 22:17:33.068930 Exit from PICG configuration <<<<
6189 22:17:33.071876 [RX_INPUT] configuration >>>>>
6190 22:17:33.075455 [RX_INPUT] configuration <<<<<
6191 22:17:33.078825 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6192 22:17:33.084952 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6193 22:17:33.091605 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6194 22:17:33.098167 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6195 22:17:33.101810 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6196 22:17:33.108105 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6197 22:17:33.111682 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6198 22:17:33.118530 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6199 22:17:33.121521 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6200 22:17:33.124716 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6201 22:17:33.128426 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6202 22:17:33.134639 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6203 22:17:33.137863 ===================================
6204 22:17:33.141407 LPDDR4 DRAM CONFIGURATION
6205 22:17:33.144628 ===================================
6206 22:17:33.144815 EX_ROW_EN[0] = 0x0
6207 22:17:33.147833 EX_ROW_EN[1] = 0x0
6208 22:17:33.148000 LP4Y_EN = 0x0
6209 22:17:33.151509 WORK_FSP = 0x0
6210 22:17:33.151638 WL = 0x2
6211 22:17:33.154852 RL = 0x2
6212 22:17:33.154969 BL = 0x2
6213 22:17:33.157771 RPST = 0x0
6214 22:17:33.157885 RD_PRE = 0x0
6215 22:17:33.161311 WR_PRE = 0x1
6216 22:17:33.161416 WR_PST = 0x0
6217 22:17:33.164597 DBI_WR = 0x0
6218 22:17:33.164702 DBI_RD = 0x0
6219 22:17:33.167781 OTF = 0x1
6220 22:17:33.171571 ===================================
6221 22:17:33.174701 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6222 22:17:33.177944 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6223 22:17:33.184682 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6224 22:17:33.187779 ===================================
6225 22:17:33.187870 LPDDR4 DRAM CONFIGURATION
6226 22:17:33.191309 ===================================
6227 22:17:33.194384 EX_ROW_EN[0] = 0x10
6228 22:17:33.197650 EX_ROW_EN[1] = 0x0
6229 22:17:33.197740 LP4Y_EN = 0x0
6230 22:17:33.200715 WORK_FSP = 0x0
6231 22:17:33.200814 WL = 0x2
6232 22:17:33.204164 RL = 0x2
6233 22:17:33.204254 BL = 0x2
6234 22:17:33.207223 RPST = 0x0
6235 22:17:33.207312 RD_PRE = 0x0
6236 22:17:33.210648 WR_PRE = 0x1
6237 22:17:33.210744 WR_PST = 0x0
6238 22:17:33.213770 DBI_WR = 0x0
6239 22:17:33.213864 DBI_RD = 0x0
6240 22:17:33.217196 OTF = 0x1
6241 22:17:33.220777 ===================================
6242 22:17:33.227193 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6243 22:17:33.230444 nWR fixed to 30
6244 22:17:33.233630 [ModeRegInit_LP4] CH0 RK0
6245 22:17:33.233767 [ModeRegInit_LP4] CH0 RK1
6246 22:17:33.237400 [ModeRegInit_LP4] CH1 RK0
6247 22:17:33.240450 [ModeRegInit_LP4] CH1 RK1
6248 22:17:33.240626 match AC timing 19
6249 22:17:33.247211 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6250 22:17:33.250582 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6251 22:17:33.253868 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6252 22:17:33.260510 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6253 22:17:33.263668 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6254 22:17:33.264063 ==
6255 22:17:33.266962 Dram Type= 6, Freq= 0, CH_0, rank 0
6256 22:17:33.270646 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6257 22:17:33.271099 ==
6258 22:17:33.277050 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6259 22:17:33.283793 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6260 22:17:33.286983 [CA 0] Center 36 (8~64) winsize 57
6261 22:17:33.290430 [CA 1] Center 36 (8~64) winsize 57
6262 22:17:33.293544 [CA 2] Center 36 (8~64) winsize 57
6263 22:17:33.296639 [CA 3] Center 36 (8~64) winsize 57
6264 22:17:33.300410 [CA 4] Center 36 (8~64) winsize 57
6265 22:17:33.300867 [CA 5] Center 36 (8~64) winsize 57
6266 22:17:33.303794
6267 22:17:33.306548 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6268 22:17:33.307015
6269 22:17:33.310191 [CATrainingPosCal] consider 1 rank data
6270 22:17:33.313478 u2DelayCellTimex100 = 270/100 ps
6271 22:17:33.316763 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6272 22:17:33.319993 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6273 22:17:33.323119 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6274 22:17:33.326619 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6275 22:17:33.330090 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6276 22:17:33.333199 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6277 22:17:33.333662
6278 22:17:33.336571 CA PerBit enable=1, Macro0, CA PI delay=36
6279 22:17:33.337019
6280 22:17:33.339753 [CBTSetCACLKResult] CA Dly = 36
6281 22:17:33.343201 CS Dly: 1 (0~32)
6282 22:17:33.343738 ==
6283 22:17:33.346457 Dram Type= 6, Freq= 0, CH_0, rank 1
6284 22:17:33.349844 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6285 22:17:33.350265 ==
6286 22:17:33.356619 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6287 22:17:33.363046 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6288 22:17:33.366190 [CA 0] Center 36 (8~64) winsize 57
6289 22:17:33.369731 [CA 1] Center 36 (8~64) winsize 57
6290 22:17:33.370153 [CA 2] Center 36 (8~64) winsize 57
6291 22:17:33.372885 [CA 3] Center 36 (8~64) winsize 57
6292 22:17:33.376100 [CA 4] Center 36 (8~64) winsize 57
6293 22:17:33.379830 [CA 5] Center 36 (8~64) winsize 57
6294 22:17:33.380253
6295 22:17:33.382950 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6296 22:17:33.383372
6297 22:17:33.389342 [CATrainingPosCal] consider 2 rank data
6298 22:17:33.389765 u2DelayCellTimex100 = 270/100 ps
6299 22:17:33.395878 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6300 22:17:33.399372 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6301 22:17:33.402657 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6302 22:17:33.405961 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6303 22:17:33.408926 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6304 22:17:33.412616 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6305 22:17:33.413079
6306 22:17:33.415883 CA PerBit enable=1, Macro0, CA PI delay=36
6307 22:17:33.416366
6308 22:17:33.418839 [CBTSetCACLKResult] CA Dly = 36
6309 22:17:33.422673 CS Dly: 1 (0~32)
6310 22:17:33.423171
6311 22:17:33.425756 ----->DramcWriteLeveling(PI) begin...
6312 22:17:33.426263 ==
6313 22:17:33.428888 Dram Type= 6, Freq= 0, CH_0, rank 0
6314 22:17:33.432190 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6315 22:17:33.432682 ==
6316 22:17:33.435545 Write leveling (Byte 0): 40 => 8
6317 22:17:33.438896 Write leveling (Byte 1): 32 => 0
6318 22:17:33.442581 DramcWriteLeveling(PI) end<-----
6319 22:17:33.443018
6320 22:17:33.443413 ==
6321 22:17:33.445701 Dram Type= 6, Freq= 0, CH_0, rank 0
6322 22:17:33.448646 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6323 22:17:33.449107 ==
6324 22:17:33.452229 [Gating] SW mode calibration
6325 22:17:33.458767 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6326 22:17:33.465149 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6327 22:17:33.468481 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6328 22:17:33.471976 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6329 22:17:33.478720 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6330 22:17:33.482299 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6331 22:17:33.485180 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6332 22:17:33.491961 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6333 22:17:33.494852 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6334 22:17:33.498573 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6335 22:17:33.505097 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6336 22:17:33.508353 Total UI for P1: 0, mck2ui 16
6337 22:17:33.511384 best dqsien dly found for B0: ( 0, 14, 24)
6338 22:17:33.514984 Total UI for P1: 0, mck2ui 16
6339 22:17:33.518116 best dqsien dly found for B1: ( 0, 14, 24)
6340 22:17:33.521408 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6341 22:17:33.524414 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6342 22:17:33.524875
6343 22:17:33.527729 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6344 22:17:33.531185 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6345 22:17:33.534645 [Gating] SW calibration Done
6346 22:17:33.535069 ==
6347 22:17:33.537771 Dram Type= 6, Freq= 0, CH_0, rank 0
6348 22:17:33.541046 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6349 22:17:33.541472 ==
6350 22:17:33.544262 RX Vref Scan: 0
6351 22:17:33.544676
6352 22:17:33.547479 RX Vref 0 -> 0, step: 1
6353 22:17:33.547894
6354 22:17:33.551177 RX Delay -410 -> 252, step: 16
6355 22:17:33.554218 iDelay=230, Bit 0, Center -11 (-250 ~ 229) 480
6356 22:17:33.557443 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6357 22:17:33.560713 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6358 22:17:33.567133 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6359 22:17:33.570421 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6360 22:17:33.574233 iDelay=230, Bit 5, Center -19 (-250 ~ 213) 464
6361 22:17:33.577164 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6362 22:17:33.583763 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6363 22:17:33.586928 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6364 22:17:33.590267 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6365 22:17:33.593722 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6366 22:17:33.600338 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6367 22:17:33.603670 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6368 22:17:33.606887 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6369 22:17:33.613230 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6370 22:17:33.616707 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6371 22:17:33.617206 ==
6372 22:17:33.620148 Dram Type= 6, Freq= 0, CH_0, rank 0
6373 22:17:33.623207 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6374 22:17:33.623765 ==
6375 22:17:33.626798 DQS Delay:
6376 22:17:33.627205 DQS0 = 19, DQS1 = 35
6377 22:17:33.627529 DQM Delay:
6378 22:17:33.629825 DQM0 = 6, DQM1 = 9
6379 22:17:33.630347 DQ Delay:
6380 22:17:33.633159 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =0
6381 22:17:33.636356 DQ4 =8, DQ5 =0, DQ6 =8, DQ7 =16
6382 22:17:33.640090 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6383 22:17:33.643543 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6384 22:17:33.643993
6385 22:17:33.644314
6386 22:17:33.644615 ==
6387 22:17:33.646320 Dram Type= 6, Freq= 0, CH_0, rank 0
6388 22:17:33.649657 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6389 22:17:33.650080 ==
6390 22:17:33.650410
6391 22:17:33.653028
6392 22:17:33.653467 TX Vref Scan disable
6393 22:17:33.656731 == TX Byte 0 ==
6394 22:17:33.659713 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6395 22:17:33.662972 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6396 22:17:33.666066 == TX Byte 1 ==
6397 22:17:33.669436 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6398 22:17:33.672805 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6399 22:17:33.673299 ==
6400 22:17:33.676309 Dram Type= 6, Freq= 0, CH_0, rank 0
6401 22:17:33.682793 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6402 22:17:33.683281 ==
6403 22:17:33.683609
6404 22:17:33.683909
6405 22:17:33.684197 TX Vref Scan disable
6406 22:17:33.685963 == TX Byte 0 ==
6407 22:17:33.689540 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6408 22:17:33.692694 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6409 22:17:33.696059 == TX Byte 1 ==
6410 22:17:33.699332 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6411 22:17:33.702659 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6412 22:17:33.703078
6413 22:17:33.706093 [DATLAT]
6414 22:17:33.706501 Freq=400, CH0 RK0
6415 22:17:33.706907
6416 22:17:33.711194 DATLAT Default: 0xf
6417 22:17:33.711767 0, 0xFFFF, sum = 0
6418 22:17:33.712617 1, 0xFFFF, sum = 0
6419 22:17:33.713063 2, 0xFFFF, sum = 0
6420 22:17:33.715735 3, 0xFFFF, sum = 0
6421 22:17:33.716181 4, 0xFFFF, sum = 0
6422 22:17:33.718953 5, 0xFFFF, sum = 0
6423 22:17:33.719371 6, 0xFFFF, sum = 0
6424 22:17:33.722309 7, 0xFFFF, sum = 0
6425 22:17:33.722740 8, 0xFFFF, sum = 0
6426 22:17:33.725931 9, 0xFFFF, sum = 0
6427 22:17:33.728953 10, 0xFFFF, sum = 0
6428 22:17:33.729374 11, 0xFFFF, sum = 0
6429 22:17:33.732146 12, 0xFFFF, sum = 0
6430 22:17:33.732561 13, 0x0, sum = 1
6431 22:17:33.735227 14, 0x0, sum = 2
6432 22:17:33.735642 15, 0x0, sum = 3
6433 22:17:33.738532 16, 0x0, sum = 4
6434 22:17:33.738970 best_step = 14
6435 22:17:33.739390
6436 22:17:33.739823 ==
6437 22:17:33.742123 Dram Type= 6, Freq= 0, CH_0, rank 0
6438 22:17:33.745447 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6439 22:17:33.746042 ==
6440 22:17:33.748647 RX Vref Scan: 1
6441 22:17:33.749170
6442 22:17:33.751695 RX Vref 0 -> 0, step: 1
6443 22:17:33.752105
6444 22:17:33.752429 RX Delay -311 -> 252, step: 8
6445 22:17:33.755216
6446 22:17:33.755707 Set Vref, RX VrefLevel [Byte0]: 57
6447 22:17:33.758560 [Byte1]: 49
6448 22:17:33.764007
6449 22:17:33.764489 Final RX Vref Byte 0 = 57 to rank0
6450 22:17:33.767225 Final RX Vref Byte 1 = 49 to rank0
6451 22:17:33.770470 Final RX Vref Byte 0 = 57 to rank1
6452 22:17:33.774089 Final RX Vref Byte 1 = 49 to rank1==
6453 22:17:33.777233 Dram Type= 6, Freq= 0, CH_0, rank 0
6454 22:17:33.783657 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6455 22:17:33.784155 ==
6456 22:17:33.784494 DQS Delay:
6457 22:17:33.786835 DQS0 = 28, DQS1 = 48
6458 22:17:33.787204 DQM Delay:
6459 22:17:33.787532 DQM0 = 12, DQM1 = 16
6460 22:17:33.790377 DQ Delay:
6461 22:17:33.793842 DQ0 =12, DQ1 =12, DQ2 =12, DQ3 =8
6462 22:17:33.796952 DQ4 =12, DQ5 =0, DQ6 =24, DQ7 =20
6463 22:17:33.799883 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =12
6464 22:17:33.803589 DQ12 =20, DQ13 =20, DQ14 =28, DQ15 =24
6465 22:17:33.803891
6466 22:17:33.804074
6467 22:17:33.809980 [DQSOSCAuto] RK0, (LSB)MR18= 0xa69d, (MSB)MR19= 0xc0c, tDQSOscB0 = 390 ps tDQSOscB1 = 389 ps
6468 22:17:33.813603 CH0 RK0: MR19=C0C, MR18=A69D
6469 22:17:33.819943 CH0_RK0: MR19=0xC0C, MR18=0xA69D, DQSOSC=389, MR23=63, INC=390, DEC=260
6470 22:17:33.820172 ==
6471 22:17:33.823025 Dram Type= 6, Freq= 0, CH_0, rank 1
6472 22:17:33.826528 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6473 22:17:33.826753 ==
6474 22:17:33.829994 [Gating] SW mode calibration
6475 22:17:33.836630 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6476 22:17:33.843090 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6477 22:17:33.846343 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6478 22:17:33.849758 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6479 22:17:33.856418 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6480 22:17:33.859570 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6481 22:17:33.862931 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6482 22:17:33.869614 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6483 22:17:33.872801 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6484 22:17:33.875991 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6485 22:17:33.882984 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6486 22:17:33.885908 Total UI for P1: 0, mck2ui 16
6487 22:17:33.889410 best dqsien dly found for B0: ( 0, 14, 24)
6488 22:17:33.889829 Total UI for P1: 0, mck2ui 16
6489 22:17:33.896037 best dqsien dly found for B1: ( 0, 14, 24)
6490 22:17:33.899440 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6491 22:17:33.902809 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6492 22:17:33.903259
6493 22:17:33.905926 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6494 22:17:33.909189 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6495 22:17:33.912417 [Gating] SW calibration Done
6496 22:17:33.912879 ==
6497 22:17:33.915712 Dram Type= 6, Freq= 0, CH_0, rank 1
6498 22:17:33.918840 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6499 22:17:33.919273 ==
6500 22:17:33.922377 RX Vref Scan: 0
6501 22:17:33.922799
6502 22:17:33.925673 RX Vref 0 -> 0, step: 1
6503 22:17:33.926095
6504 22:17:33.926430 RX Delay -410 -> 252, step: 16
6505 22:17:33.932249 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6506 22:17:33.935749 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6507 22:17:33.939103 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6508 22:17:33.945780 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6509 22:17:33.948672 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6510 22:17:33.952433 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6511 22:17:33.955830 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6512 22:17:33.962142 iDelay=230, Bit 7, Center -11 (-250 ~ 229) 480
6513 22:17:33.965277 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6514 22:17:33.968515 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6515 22:17:33.971856 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6516 22:17:33.978479 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6517 22:17:33.981450 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6518 22:17:33.985106 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6519 22:17:33.988387 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6520 22:17:33.994708 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6521 22:17:33.995161 ==
6522 22:17:33.997962 Dram Type= 6, Freq= 0, CH_0, rank 1
6523 22:17:34.001199 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6524 22:17:34.001682 ==
6525 22:17:34.004963 DQS Delay:
6526 22:17:34.005410 DQS0 = 27, DQS1 = 43
6527 22:17:34.005751 DQM Delay:
6528 22:17:34.008123 DQM0 = 10, DQM1 = 16
6529 22:17:34.008572 DQ Delay:
6530 22:17:34.011322 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6531 22:17:34.014604 DQ4 =8, DQ5 =0, DQ6 =24, DQ7 =16
6532 22:17:34.017887 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =16
6533 22:17:34.021192 DQ12 =16, DQ13 =24, DQ14 =24, DQ15 =24
6534 22:17:34.021611
6535 22:17:34.022018
6536 22:17:34.022331 ==
6537 22:17:34.024491 Dram Type= 6, Freq= 0, CH_0, rank 1
6538 22:17:34.027726 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6539 22:17:34.030933 ==
6540 22:17:34.031352
6541 22:17:34.031699
6542 22:17:34.032007 TX Vref Scan disable
6543 22:17:34.034210 == TX Byte 0 ==
6544 22:17:34.038080 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6545 22:17:34.041062 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6546 22:17:34.044122 == TX Byte 1 ==
6547 22:17:34.047659 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6548 22:17:34.051054 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6549 22:17:34.051607 ==
6550 22:17:34.054310 Dram Type= 6, Freq= 0, CH_0, rank 1
6551 22:17:34.057465 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6552 22:17:34.060858 ==
6553 22:17:34.061298
6554 22:17:34.061633
6555 22:17:34.061959 TX Vref Scan disable
6556 22:17:34.064206 == TX Byte 0 ==
6557 22:17:34.067295 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6558 22:17:34.071031 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6559 22:17:34.074085 == TX Byte 1 ==
6560 22:17:34.077489 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6561 22:17:34.080643 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6562 22:17:34.081082
6563 22:17:34.083910 [DATLAT]
6564 22:17:34.084325 Freq=400, CH0 RK1
6565 22:17:34.084660
6566 22:17:34.087017 DATLAT Default: 0xe
6567 22:17:34.087442 0, 0xFFFF, sum = 0
6568 22:17:34.090390 1, 0xFFFF, sum = 0
6569 22:17:34.090823 2, 0xFFFF, sum = 0
6570 22:17:34.094075 3, 0xFFFF, sum = 0
6571 22:17:34.094508 4, 0xFFFF, sum = 0
6572 22:17:34.097323 5, 0xFFFF, sum = 0
6573 22:17:34.097773 6, 0xFFFF, sum = 0
6574 22:17:34.100827 7, 0xFFFF, sum = 0
6575 22:17:34.101261 8, 0xFFFF, sum = 0
6576 22:17:34.104080 9, 0xFFFF, sum = 0
6577 22:17:34.104512 10, 0xFFFF, sum = 0
6578 22:17:34.107156 11, 0xFFFF, sum = 0
6579 22:17:34.107602 12, 0xFFFF, sum = 0
6580 22:17:34.110351 13, 0x0, sum = 1
6581 22:17:34.110784 14, 0x0, sum = 2
6582 22:17:34.113525 15, 0x0, sum = 3
6583 22:17:34.113960 16, 0x0, sum = 4
6584 22:17:34.116910 best_step = 14
6585 22:17:34.117337
6586 22:17:34.117674 ==
6587 22:17:34.120195 Dram Type= 6, Freq= 0, CH_0, rank 1
6588 22:17:34.123534 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6589 22:17:34.123976 ==
6590 22:17:34.126854 RX Vref Scan: 0
6591 22:17:34.127277
6592 22:17:34.127613 RX Vref 0 -> 0, step: 1
6593 22:17:34.127926
6594 22:17:34.130177 RX Delay -327 -> 252, step: 8
6595 22:17:34.138416 iDelay=217, Bit 0, Center -20 (-247 ~ 208) 456
6596 22:17:34.141780 iDelay=217, Bit 1, Center -16 (-239 ~ 208) 448
6597 22:17:34.144992 iDelay=217, Bit 2, Center -24 (-247 ~ 200) 448
6598 22:17:34.151286 iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448
6599 22:17:34.154976 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6600 22:17:34.158174 iDelay=217, Bit 5, Center -28 (-255 ~ 200) 456
6601 22:17:34.161519 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6602 22:17:34.164872 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6603 22:17:34.171146 iDelay=217, Bit 8, Center -32 (-255 ~ 192) 448
6604 22:17:34.174452 iDelay=217, Bit 9, Center -40 (-263 ~ 184) 448
6605 22:17:34.177754 iDelay=217, Bit 10, Center -28 (-255 ~ 200) 456
6606 22:17:34.184651 iDelay=217, Bit 11, Center -32 (-255 ~ 192) 448
6607 22:17:34.187955 iDelay=217, Bit 12, Center -24 (-247 ~ 200) 448
6608 22:17:34.190914 iDelay=217, Bit 13, Center -24 (-247 ~ 200) 448
6609 22:17:34.194124 iDelay=217, Bit 14, Center -20 (-247 ~ 208) 456
6610 22:17:34.200725 iDelay=217, Bit 15, Center -20 (-239 ~ 200) 440
6611 22:17:34.200974 ==
6612 22:17:34.204066 Dram Type= 6, Freq= 0, CH_0, rank 1
6613 22:17:34.207463 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6614 22:17:34.207693 ==
6615 22:17:34.207875 DQS Delay:
6616 22:17:34.210712 DQS0 = 28, DQS1 = 40
6617 22:17:34.210939 DQM Delay:
6618 22:17:34.213969 DQM0 = 10, DQM1 = 12
6619 22:17:34.214197 DQ Delay:
6620 22:17:34.217263 DQ0 =8, DQ1 =12, DQ2 =4, DQ3 =4
6621 22:17:34.220479 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6622 22:17:34.223966 DQ8 =8, DQ9 =0, DQ10 =12, DQ11 =8
6623 22:17:34.227192 DQ12 =16, DQ13 =16, DQ14 =20, DQ15 =20
6624 22:17:34.227417
6625 22:17:34.227595
6626 22:17:34.233640 [DQSOSCAuto] RK1, (LSB)MR18= 0xbb71, (MSB)MR19= 0xc0c, tDQSOscB0 = 395 ps tDQSOscB1 = 386 ps
6627 22:17:34.237093 CH0 RK1: MR19=C0C, MR18=BB71
6628 22:17:34.244017 CH0_RK1: MR19=0xC0C, MR18=0xBB71, DQSOSC=386, MR23=63, INC=396, DEC=264
6629 22:17:34.247325 [RxdqsGatingPostProcess] freq 400
6630 22:17:34.253751 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6631 22:17:34.257103 best DQS0 dly(2T, 0.5T) = (0, 10)
6632 22:17:34.260718 best DQS1 dly(2T, 0.5T) = (0, 10)
6633 22:17:34.263583 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6634 22:17:34.267122 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6635 22:17:34.267570 best DQS0 dly(2T, 0.5T) = (0, 10)
6636 22:17:34.270029 best DQS1 dly(2T, 0.5T) = (0, 10)
6637 22:17:34.273560 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6638 22:17:34.276991 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6639 22:17:34.280137 Pre-setting of DQS Precalculation
6640 22:17:34.286757 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6641 22:17:34.287247 ==
6642 22:17:34.290081 Dram Type= 6, Freq= 0, CH_1, rank 0
6643 22:17:34.293322 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6644 22:17:34.293811 ==
6645 22:17:34.299968 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6646 22:17:34.306913 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6647 22:17:34.310196 [CA 0] Center 36 (8~64) winsize 57
6648 22:17:34.310622 [CA 1] Center 36 (8~64) winsize 57
6649 22:17:34.313321 [CA 2] Center 36 (8~64) winsize 57
6650 22:17:34.316517 [CA 3] Center 36 (8~64) winsize 57
6651 22:17:34.320023 [CA 4] Center 36 (8~64) winsize 57
6652 22:17:34.323093 [CA 5] Center 36 (8~64) winsize 57
6653 22:17:34.323524
6654 22:17:34.326518 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6655 22:17:34.327071
6656 22:17:34.333157 [CATrainingPosCal] consider 1 rank data
6657 22:17:34.333653 u2DelayCellTimex100 = 270/100 ps
6658 22:17:34.339826 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6659 22:17:34.343020 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6660 22:17:34.346437 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6661 22:17:34.349602 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6662 22:17:34.352846 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6663 22:17:34.355939 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6664 22:17:34.356450
6665 22:17:34.359836 CA PerBit enable=1, Macro0, CA PI delay=36
6666 22:17:34.360420
6667 22:17:34.362638 [CBTSetCACLKResult] CA Dly = 36
6668 22:17:34.366368 CS Dly: 1 (0~32)
6669 22:17:34.366949 ==
6670 22:17:34.369216 Dram Type= 6, Freq= 0, CH_1, rank 1
6671 22:17:34.372436 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6672 22:17:34.372958 ==
6673 22:17:34.379224 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6674 22:17:34.382566 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6675 22:17:34.385846 [CA 0] Center 36 (8~64) winsize 57
6676 22:17:34.388969 [CA 1] Center 36 (8~64) winsize 57
6677 22:17:34.392414 [CA 2] Center 36 (8~64) winsize 57
6678 22:17:34.395592 [CA 3] Center 36 (8~64) winsize 57
6679 22:17:34.399000 [CA 4] Center 36 (8~64) winsize 57
6680 22:17:34.402581 [CA 5] Center 36 (8~64) winsize 57
6681 22:17:34.403009
6682 22:17:34.405823 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6683 22:17:34.406275
6684 22:17:34.408913 [CATrainingPosCal] consider 2 rank data
6685 22:17:34.412511 u2DelayCellTimex100 = 270/100 ps
6686 22:17:34.415390 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6687 22:17:34.419125 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6688 22:17:34.425692 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6689 22:17:34.428801 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6690 22:17:34.431969 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6691 22:17:34.435365 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6692 22:17:34.435794
6693 22:17:34.438829 CA PerBit enable=1, Macro0, CA PI delay=36
6694 22:17:34.439256
6695 22:17:34.442012 [CBTSetCACLKResult] CA Dly = 36
6696 22:17:34.442462 CS Dly: 1 (0~32)
6697 22:17:34.445386
6698 22:17:34.448413 ----->DramcWriteLeveling(PI) begin...
6699 22:17:34.448967 ==
6700 22:17:34.451808 Dram Type= 6, Freq= 0, CH_1, rank 0
6701 22:17:34.455077 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6702 22:17:34.455509 ==
6703 22:17:34.458452 Write leveling (Byte 0): 40 => 8
6704 22:17:34.461649 Write leveling (Byte 1): 32 => 0
6705 22:17:34.465107 DramcWriteLeveling(PI) end<-----
6706 22:17:34.465532
6707 22:17:34.465907 ==
6708 22:17:34.468708 Dram Type= 6, Freq= 0, CH_1, rank 0
6709 22:17:34.471486 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6710 22:17:34.471928 ==
6711 22:17:34.474993 [Gating] SW mode calibration
6712 22:17:34.481564 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6713 22:17:34.488045 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6714 22:17:34.491578 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6715 22:17:34.494757 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6716 22:17:34.501422 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6717 22:17:34.504839 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6718 22:17:34.508419 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6719 22:17:34.514715 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6720 22:17:34.517760 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6721 22:17:34.521053 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6722 22:17:34.527749 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6723 22:17:34.528141 Total UI for P1: 0, mck2ui 16
6724 22:17:34.534347 best dqsien dly found for B0: ( 0, 14, 24)
6725 22:17:34.534774 Total UI for P1: 0, mck2ui 16
6726 22:17:34.537588 best dqsien dly found for B1: ( 0, 14, 24)
6727 22:17:34.544597 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6728 22:17:34.547678 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6729 22:17:34.548129
6730 22:17:34.551140 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6731 22:17:34.554128 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6732 22:17:34.557392 [Gating] SW calibration Done
6733 22:17:34.557840 ==
6734 22:17:34.560644 Dram Type= 6, Freq= 0, CH_1, rank 0
6735 22:17:34.564483 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6736 22:17:34.564973 ==
6737 22:17:34.567633 RX Vref Scan: 0
6738 22:17:34.568146
6739 22:17:34.568490 RX Vref 0 -> 0, step: 1
6740 22:17:34.568846
6741 22:17:34.570841 RX Delay -410 -> 252, step: 16
6742 22:17:34.577195 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6743 22:17:34.580677 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6744 22:17:34.583856 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6745 22:17:34.586929 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6746 22:17:34.593658 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6747 22:17:34.597151 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6748 22:17:34.600601 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6749 22:17:34.603721 iDelay=230, Bit 7, Center -27 (-266 ~ 213) 480
6750 22:17:34.610078 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6751 22:17:34.613749 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6752 22:17:34.616981 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6753 22:17:34.620275 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6754 22:17:34.626948 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6755 22:17:34.630592 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6756 22:17:34.633461 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6757 22:17:34.640241 iDelay=230, Bit 15, Center -19 (-266 ~ 229) 496
6758 22:17:34.640833 ==
6759 22:17:34.643607 Dram Type= 6, Freq= 0, CH_1, rank 0
6760 22:17:34.647004 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6761 22:17:34.647539 ==
6762 22:17:34.647888 DQS Delay:
6763 22:17:34.650214 DQS0 = 27, DQS1 = 43
6764 22:17:34.650678 DQM Delay:
6765 22:17:34.653073 DQM0 = 9, DQM1 = 16
6766 22:17:34.653539 DQ Delay:
6767 22:17:34.656723 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6768 22:17:34.660171 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =0
6769 22:17:34.663169 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6770 22:17:34.666576 DQ12 =32, DQ13 =24, DQ14 =16, DQ15 =24
6771 22:17:34.667103
6772 22:17:34.667447
6773 22:17:34.667762 ==
6774 22:17:34.670112 Dram Type= 6, Freq= 0, CH_1, rank 0
6775 22:17:34.673055 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6776 22:17:34.673488 ==
6777 22:17:34.673827
6778 22:17:34.674143
6779 22:17:34.676383 TX Vref Scan disable
6780 22:17:34.676839 == TX Byte 0 ==
6781 22:17:34.682800 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6782 22:17:34.686028 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6783 22:17:34.686458 == TX Byte 1 ==
6784 22:17:34.692820 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6785 22:17:34.696127 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6786 22:17:34.696557 ==
6787 22:17:34.699462 Dram Type= 6, Freq= 0, CH_1, rank 0
6788 22:17:34.702585 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6789 22:17:34.703021 ==
6790 22:17:34.705872
6791 22:17:34.706410
6792 22:17:34.706753 TX Vref Scan disable
6793 22:17:34.709113 == TX Byte 0 ==
6794 22:17:34.712568 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6795 22:17:34.715749 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6796 22:17:34.719239 == TX Byte 1 ==
6797 22:17:34.722485 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6798 22:17:34.725359 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6799 22:17:34.725801
6800 22:17:34.728688 [DATLAT]
6801 22:17:34.729148 Freq=400, CH1 RK0
6802 22:17:34.729590
6803 22:17:34.732337 DATLAT Default: 0xf
6804 22:17:34.732805 0, 0xFFFF, sum = 0
6805 22:17:34.735726 1, 0xFFFF, sum = 0
6806 22:17:34.736285 2, 0xFFFF, sum = 0
6807 22:17:34.739054 3, 0xFFFF, sum = 0
6808 22:17:34.739645 4, 0xFFFF, sum = 0
6809 22:17:34.742062 5, 0xFFFF, sum = 0
6810 22:17:34.742486 6, 0xFFFF, sum = 0
6811 22:17:34.745250 7, 0xFFFF, sum = 0
6812 22:17:34.745672 8, 0xFFFF, sum = 0
6813 22:17:34.748455 9, 0xFFFF, sum = 0
6814 22:17:34.748898 10, 0xFFFF, sum = 0
6815 22:17:34.752255 11, 0xFFFF, sum = 0
6816 22:17:34.755017 12, 0xFFFF, sum = 0
6817 22:17:34.755446 13, 0x0, sum = 1
6818 22:17:34.758715 14, 0x0, sum = 2
6819 22:17:34.759257 15, 0x0, sum = 3
6820 22:17:34.759607 16, 0x0, sum = 4
6821 22:17:34.761795 best_step = 14
6822 22:17:34.762216
6823 22:17:34.762549 ==
6824 22:17:34.764886 Dram Type= 6, Freq= 0, CH_1, rank 0
6825 22:17:34.768136 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6826 22:17:34.768562 ==
6827 22:17:34.772036 RX Vref Scan: 1
6828 22:17:34.772595
6829 22:17:34.775297 RX Vref 0 -> 0, step: 1
6830 22:17:34.775835
6831 22:17:34.776180 RX Delay -327 -> 252, step: 8
6832 22:17:34.776494
6833 22:17:34.778537 Set Vref, RX VrefLevel [Byte0]: 51
6834 22:17:34.781404 [Byte1]: 52
6835 22:17:34.786676
6836 22:17:34.787189 Final RX Vref Byte 0 = 51 to rank0
6837 22:17:34.790352 Final RX Vref Byte 1 = 52 to rank0
6838 22:17:34.793408 Final RX Vref Byte 0 = 51 to rank1
6839 22:17:34.796419 Final RX Vref Byte 1 = 52 to rank1==
6840 22:17:34.800022 Dram Type= 6, Freq= 0, CH_1, rank 0
6841 22:17:34.806435 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6842 22:17:34.806960 ==
6843 22:17:34.807307 DQS Delay:
6844 22:17:34.809431 DQS0 = 32, DQS1 = 40
6845 22:17:34.809926 DQM Delay:
6846 22:17:34.810271 DQM0 = 11, DQM1 = 13
6847 22:17:34.812933 DQ Delay:
6848 22:17:34.816325 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6849 22:17:34.819594 DQ4 =8, DQ5 =24, DQ6 =20, DQ7 =8
6850 22:17:34.820042 DQ8 =0, DQ9 =0, DQ10 =20, DQ11 =4
6851 22:17:34.822971 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =20
6852 22:17:34.826146
6853 22:17:34.826595
6854 22:17:34.832883 [DQSOSCAuto] RK0, (LSB)MR18= 0x92cc, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 391 ps
6855 22:17:34.836455 CH1 RK0: MR19=C0C, MR18=92CC
6856 22:17:34.842656 CH1_RK0: MR19=0xC0C, MR18=0x92CC, DQSOSC=384, MR23=63, INC=400, DEC=267
6857 22:17:34.843163 ==
6858 22:17:34.846222 Dram Type= 6, Freq= 0, CH_1, rank 1
6859 22:17:34.849386 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6860 22:17:34.849935 ==
6861 22:17:34.852453 [Gating] SW mode calibration
6862 22:17:34.859258 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6863 22:17:34.865838 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6864 22:17:34.868956 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6865 22:17:34.872162 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6866 22:17:34.878675 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6867 22:17:34.882330 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6868 22:17:34.885618 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6869 22:17:34.892004 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6870 22:17:34.895465 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6871 22:17:34.898933 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6872 22:17:34.905199 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6873 22:17:34.905589 Total UI for P1: 0, mck2ui 16
6874 22:17:34.912354 best dqsien dly found for B0: ( 0, 14, 24)
6875 22:17:34.912810 Total UI for P1: 0, mck2ui 16
6876 22:17:34.918852 best dqsien dly found for B1: ( 0, 14, 24)
6877 22:17:34.922114 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6878 22:17:34.925236 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6879 22:17:34.925714
6880 22:17:34.928670 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6881 22:17:34.931783 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6882 22:17:34.935064 [Gating] SW calibration Done
6883 22:17:34.935487 ==
6884 22:17:34.938230 Dram Type= 6, Freq= 0, CH_1, rank 1
6885 22:17:34.941870 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6886 22:17:34.942298 ==
6887 22:17:34.945137 RX Vref Scan: 0
6888 22:17:34.945558
6889 22:17:34.946071 RX Vref 0 -> 0, step: 1
6890 22:17:34.948185
6891 22:17:34.948601 RX Delay -410 -> 252, step: 16
6892 22:17:34.954991 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6893 22:17:34.958178 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6894 22:17:34.961432 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6895 22:17:34.964594 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6896 22:17:34.971484 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6897 22:17:34.974678 iDelay=230, Bit 5, Center -11 (-250 ~ 229) 480
6898 22:17:34.977940 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6899 22:17:34.981227 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6900 22:17:34.987894 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6901 22:17:34.991367 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6902 22:17:34.994620 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6903 22:17:35.000626 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6904 22:17:35.004104 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6905 22:17:35.007813 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6906 22:17:35.010703 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6907 22:17:35.017576 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6908 22:17:35.018054 ==
6909 22:17:35.020654 Dram Type= 6, Freq= 0, CH_1, rank 1
6910 22:17:35.024460 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6911 22:17:35.024922 ==
6912 22:17:35.025267 DQS Delay:
6913 22:17:35.027169 DQS0 = 35, DQS1 = 43
6914 22:17:35.027588 DQM Delay:
6915 22:17:35.030514 DQM0 = 16, DQM1 = 18
6916 22:17:35.031068 DQ Delay:
6917 22:17:35.034081 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6918 22:17:35.037209 DQ4 =16, DQ5 =24, DQ6 =24, DQ7 =16
6919 22:17:35.040462 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6920 22:17:35.043723 DQ12 =32, DQ13 =24, DQ14 =16, DQ15 =32
6921 22:17:35.044233
6922 22:17:35.044586
6923 22:17:35.044937 ==
6924 22:17:35.046930 Dram Type= 6, Freq= 0, CH_1, rank 1
6925 22:17:35.050355 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6926 22:17:35.053690 ==
6927 22:17:35.054257
6928 22:17:35.054681
6929 22:17:35.055008 TX Vref Scan disable
6930 22:17:35.056958 == TX Byte 0 ==
6931 22:17:35.060277 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6932 22:17:35.063222 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6933 22:17:35.067037 == TX Byte 1 ==
6934 22:17:35.070240 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6935 22:17:35.073464 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6936 22:17:35.073918 ==
6937 22:17:35.076542 Dram Type= 6, Freq= 0, CH_1, rank 1
6938 22:17:35.083101 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6939 22:17:35.083622 ==
6940 22:17:35.083969
6941 22:17:35.084283
6942 22:17:35.084587 TX Vref Scan disable
6943 22:17:35.086406 == TX Byte 0 ==
6944 22:17:35.089662 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6945 22:17:35.093231 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6946 22:17:35.096350 == TX Byte 1 ==
6947 22:17:35.099636 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6948 22:17:35.102910 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6949 22:17:35.103570
6950 22:17:35.106205 [DATLAT]
6951 22:17:35.106792 Freq=400, CH1 RK1
6952 22:17:35.107342
6953 22:17:35.109598 DATLAT Default: 0xe
6954 22:17:35.110109 0, 0xFFFF, sum = 0
6955 22:17:35.112926 1, 0xFFFF, sum = 0
6956 22:17:35.113483 2, 0xFFFF, sum = 0
6957 22:17:35.116683 3, 0xFFFF, sum = 0
6958 22:17:35.117301 4, 0xFFFF, sum = 0
6959 22:17:35.119471 5, 0xFFFF, sum = 0
6960 22:17:35.119983 6, 0xFFFF, sum = 0
6961 22:17:35.123198 7, 0xFFFF, sum = 0
6962 22:17:35.123883 8, 0xFFFF, sum = 0
6963 22:17:35.126431 9, 0xFFFF, sum = 0
6964 22:17:35.129621 10, 0xFFFF, sum = 0
6965 22:17:35.130218 11, 0xFFFF, sum = 0
6966 22:17:35.132755 12, 0xFFFF, sum = 0
6967 22:17:35.133236 13, 0x0, sum = 1
6968 22:17:35.136326 14, 0x0, sum = 2
6969 22:17:35.136752 15, 0x0, sum = 3
6970 22:17:35.139369 16, 0x0, sum = 4
6971 22:17:35.139793 best_step = 14
6972 22:17:35.140128
6973 22:17:35.140433 ==
6974 22:17:35.143057 Dram Type= 6, Freq= 0, CH_1, rank 1
6975 22:17:35.146142 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6976 22:17:35.146585 ==
6977 22:17:35.149414 RX Vref Scan: 0
6978 22:17:35.149856
6979 22:17:35.152698 RX Vref 0 -> 0, step: 1
6980 22:17:35.153179
6981 22:17:35.153516 RX Delay -327 -> 252, step: 8
6982 22:17:35.161106 iDelay=217, Bit 0, Center -16 (-231 ~ 200) 432
6983 22:17:35.164678 iDelay=217, Bit 1, Center -28 (-247 ~ 192) 440
6984 22:17:35.167813 iDelay=217, Bit 2, Center -32 (-255 ~ 192) 448
6985 22:17:35.171151 iDelay=217, Bit 3, Center -20 (-247 ~ 208) 456
6986 22:17:35.177998 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6987 22:17:35.180873 iDelay=217, Bit 5, Center -8 (-231 ~ 216) 448
6988 22:17:35.184608 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
6989 22:17:35.187787 iDelay=217, Bit 7, Center -20 (-239 ~ 200) 440
6990 22:17:35.194357 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6991 22:17:35.197435 iDelay=217, Bit 9, Center -36 (-263 ~ 192) 456
6992 22:17:35.200827 iDelay=217, Bit 10, Center -24 (-247 ~ 200) 448
6993 22:17:35.207530 iDelay=217, Bit 11, Center -28 (-255 ~ 200) 456
6994 22:17:35.210706 iDelay=217, Bit 12, Center -20 (-247 ~ 208) 456
6995 22:17:35.213998 iDelay=217, Bit 13, Center -20 (-247 ~ 208) 456
6996 22:17:35.217789 iDelay=217, Bit 14, Center -20 (-247 ~ 208) 456
6997 22:17:35.224045 iDelay=217, Bit 15, Center -12 (-239 ~ 216) 456
6998 22:17:35.224554 ==
6999 22:17:35.227184 Dram Type= 6, Freq= 0, CH_1, rank 1
7000 22:17:35.230908 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7001 22:17:35.231353 ==
7002 22:17:35.231691 DQS Delay:
7003 22:17:35.234022 DQS0 = 32, DQS1 = 36
7004 22:17:35.234525 DQM Delay:
7005 22:17:35.237295 DQM0 = 13, DQM1 = 11
7006 22:17:35.237771 DQ Delay:
7007 22:17:35.240506 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =12
7008 22:17:35.243982 DQ4 =16, DQ5 =24, DQ6 =20, DQ7 =12
7009 22:17:35.246993 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =8
7010 22:17:35.250834 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =24
7011 22:17:35.251402
7012 22:17:35.251750
7013 22:17:35.257143 [DQSOSCAuto] RK1, (LSB)MR18= 0xaa53, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 388 ps
7014 22:17:35.260505 CH1 RK1: MR19=C0C, MR18=AA53
7015 22:17:35.267476 CH1_RK1: MR19=0xC0C, MR18=0xAA53, DQSOSC=388, MR23=63, INC=392, DEC=261
7016 22:17:35.270239 [RxdqsGatingPostProcess] freq 400
7017 22:17:35.277280 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7018 22:17:35.280590 best DQS0 dly(2T, 0.5T) = (0, 10)
7019 22:17:35.283842 best DQS1 dly(2T, 0.5T) = (0, 10)
7020 22:17:35.287064 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7021 22:17:35.290166 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7022 22:17:35.290590 best DQS0 dly(2T, 0.5T) = (0, 10)
7023 22:17:35.293460 best DQS1 dly(2T, 0.5T) = (0, 10)
7024 22:17:35.296581 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7025 22:17:35.300351 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7026 22:17:35.303536 Pre-setting of DQS Precalculation
7027 22:17:35.309758 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7028 22:17:35.316828 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7029 22:17:35.323520 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7030 22:17:35.324015
7031 22:17:35.324516
7032 22:17:35.326834 [Calibration Summary] 800 Mbps
7033 22:17:35.327267 CH 0, Rank 0
7034 22:17:35.329979 SW Impedance : PASS
7035 22:17:35.333206 DUTY Scan : NO K
7036 22:17:35.333634 ZQ Calibration : PASS
7037 22:17:35.336421 Jitter Meter : NO K
7038 22:17:35.339638 CBT Training : PASS
7039 22:17:35.340066 Write leveling : PASS
7040 22:17:35.343323 RX DQS gating : PASS
7041 22:17:35.346230 RX DQ/DQS(RDDQC) : PASS
7042 22:17:35.346661 TX DQ/DQS : PASS
7043 22:17:35.349671 RX DATLAT : PASS
7044 22:17:35.352918 RX DQ/DQS(Engine): PASS
7045 22:17:35.353349 TX OE : NO K
7046 22:17:35.355992 All Pass.
7047 22:17:35.356439
7048 22:17:35.356804 CH 0, Rank 1
7049 22:17:35.359469 SW Impedance : PASS
7050 22:17:35.359912 DUTY Scan : NO K
7051 22:17:35.362852 ZQ Calibration : PASS
7052 22:17:35.366329 Jitter Meter : NO K
7053 22:17:35.366746 CBT Training : PASS
7054 22:17:35.369467 Write leveling : NO K
7055 22:17:35.369958 RX DQS gating : PASS
7056 22:17:35.372989 RX DQ/DQS(RDDQC) : PASS
7057 22:17:35.376497 TX DQ/DQS : PASS
7058 22:17:35.376944 RX DATLAT : PASS
7059 22:17:35.379510 RX DQ/DQS(Engine): PASS
7060 22:17:35.382773 TX OE : NO K
7061 22:17:35.383262 All Pass.
7062 22:17:35.383597
7063 22:17:35.383908 CH 1, Rank 0
7064 22:17:35.386294 SW Impedance : PASS
7065 22:17:35.389456 DUTY Scan : NO K
7066 22:17:35.389931 ZQ Calibration : PASS
7067 22:17:35.392689 Jitter Meter : NO K
7068 22:17:35.396285 CBT Training : PASS
7069 22:17:35.396831 Write leveling : PASS
7070 22:17:35.399362 RX DQS gating : PASS
7071 22:17:35.402541 RX DQ/DQS(RDDQC) : PASS
7072 22:17:35.403006 TX DQ/DQS : PASS
7073 22:17:35.405877 RX DATLAT : PASS
7074 22:17:35.409506 RX DQ/DQS(Engine): PASS
7075 22:17:35.409939 TX OE : NO K
7076 22:17:35.412838 All Pass.
7077 22:17:35.413267
7078 22:17:35.413692 CH 1, Rank 1
7079 22:17:35.416139 SW Impedance : PASS
7080 22:17:35.416569 DUTY Scan : NO K
7081 22:17:35.419074 ZQ Calibration : PASS
7082 22:17:35.422774 Jitter Meter : NO K
7083 22:17:35.423311 CBT Training : PASS
7084 22:17:35.425551 Write leveling : NO K
7085 22:17:35.429273 RX DQS gating : PASS
7086 22:17:35.429702 RX DQ/DQS(RDDQC) : PASS
7087 22:17:35.432352 TX DQ/DQS : PASS
7088 22:17:35.432809 RX DATLAT : PASS
7089 22:17:35.435778 RX DQ/DQS(Engine): PASS
7090 22:17:35.439023 TX OE : NO K
7091 22:17:35.439449 All Pass.
7092 22:17:35.439872
7093 22:17:35.442743 DramC Write-DBI off
7094 22:17:35.443172 PER_BANK_REFRESH: Hybrid Mode
7095 22:17:35.445520 TX_TRACKING: ON
7096 22:17:35.455593 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7097 22:17:35.459086 [FAST_K] Save calibration result to emmc
7098 22:17:35.462026 dramc_set_vcore_voltage set vcore to 725000
7099 22:17:35.465601 Read voltage for 1600, 0
7100 22:17:35.466032 Vio18 = 0
7101 22:17:35.466471 Vcore = 725000
7102 22:17:35.468803 Vdram = 0
7103 22:17:35.469235 Vddq = 0
7104 22:17:35.469658 Vmddr = 0
7105 22:17:35.475233 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7106 22:17:35.478524 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7107 22:17:35.481906 MEM_TYPE=3, freq_sel=13
7108 22:17:35.485167 sv_algorithm_assistance_LP4_3733
7109 22:17:35.488809 ============ PULL DRAM RESETB DOWN ============
7110 22:17:35.492350 ========== PULL DRAM RESETB DOWN end =========
7111 22:17:35.498447 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7112 22:17:35.501651 ===================================
7113 22:17:35.502144 LPDDR4 DRAM CONFIGURATION
7114 22:17:35.505022 ===================================
7115 22:17:35.508657 EX_ROW_EN[0] = 0x0
7116 22:17:35.512016 EX_ROW_EN[1] = 0x0
7117 22:17:35.512436 LP4Y_EN = 0x0
7118 22:17:35.515388 WORK_FSP = 0x1
7119 22:17:35.515912 WL = 0x5
7120 22:17:35.518025 RL = 0x5
7121 22:17:35.518441 BL = 0x2
7122 22:17:35.521664 RPST = 0x0
7123 22:17:35.522082 RD_PRE = 0x0
7124 22:17:35.524988 WR_PRE = 0x1
7125 22:17:35.525496 WR_PST = 0x1
7126 22:17:35.528446 DBI_WR = 0x0
7127 22:17:35.528966 DBI_RD = 0x0
7128 22:17:35.531869 OTF = 0x1
7129 22:17:35.534809 ===================================
7130 22:17:35.538213 ===================================
7131 22:17:35.538786 ANA top config
7132 22:17:35.541310 ===================================
7133 22:17:35.544740 DLL_ASYNC_EN = 0
7134 22:17:35.548365 ALL_SLAVE_EN = 0
7135 22:17:35.551527 NEW_RANK_MODE = 1
7136 22:17:35.551947 DLL_IDLE_MODE = 1
7137 22:17:35.554824 LP45_APHY_COMB_EN = 1
7138 22:17:35.557970 TX_ODT_DIS = 0
7139 22:17:35.561169 NEW_8X_MODE = 1
7140 22:17:35.564326 ===================================
7141 22:17:35.567920 ===================================
7142 22:17:35.571577 data_rate = 3200
7143 22:17:35.574204 CKR = 1
7144 22:17:35.574624 DQ_P2S_RATIO = 8
7145 22:17:35.577760 ===================================
7146 22:17:35.581010 CA_P2S_RATIO = 8
7147 22:17:35.584619 DQ_CA_OPEN = 0
7148 22:17:35.587787 DQ_SEMI_OPEN = 0
7149 22:17:35.591232 CA_SEMI_OPEN = 0
7150 22:17:35.591651 CA_FULL_RATE = 0
7151 22:17:35.594199 DQ_CKDIV4_EN = 0
7152 22:17:35.597614 CA_CKDIV4_EN = 0
7153 22:17:35.601271 CA_PREDIV_EN = 0
7154 22:17:35.604317 PH8_DLY = 12
7155 22:17:35.607566 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7156 22:17:35.611163 DQ_AAMCK_DIV = 4
7157 22:17:35.611634 CA_AAMCK_DIV = 4
7158 22:17:35.614279 CA_ADMCK_DIV = 4
7159 22:17:35.617955 DQ_TRACK_CA_EN = 0
7160 22:17:35.620860 CA_PICK = 1600
7161 22:17:35.624337 CA_MCKIO = 1600
7162 22:17:35.627365 MCKIO_SEMI = 0
7163 22:17:35.630785 PLL_FREQ = 3068
7164 22:17:35.631309 DQ_UI_PI_RATIO = 32
7165 22:17:35.634290 CA_UI_PI_RATIO = 0
7166 22:17:35.637187 ===================================
7167 22:17:35.640636 ===================================
7168 22:17:35.643954 memory_type:LPDDR4
7169 22:17:35.646983 GP_NUM : 10
7170 22:17:35.647405 SRAM_EN : 1
7171 22:17:35.650600 MD32_EN : 0
7172 22:17:35.653693 ===================================
7173 22:17:35.657097 [ANA_INIT] >>>>>>>>>>>>>>
7174 22:17:35.657519 <<<<<< [CONFIGURE PHASE]: ANA_TX
7175 22:17:35.664009 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7176 22:17:35.664508 ===================================
7177 22:17:35.666940 data_rate = 3200,PCW = 0X7600
7178 22:17:35.670506 ===================================
7179 22:17:35.673846 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7180 22:17:35.680218 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7181 22:17:35.686870 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7182 22:17:35.689973 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7183 22:17:35.693587 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7184 22:17:35.696651 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7185 22:17:35.700181 [ANA_INIT] flow start
7186 22:17:35.700568 [ANA_INIT] PLL >>>>>>>>
7187 22:17:35.703198 [ANA_INIT] PLL <<<<<<<<
7188 22:17:35.706673 [ANA_INIT] MIDPI >>>>>>>>
7189 22:17:35.710047 [ANA_INIT] MIDPI <<<<<<<<
7190 22:17:35.710516 [ANA_INIT] DLL >>>>>>>>
7191 22:17:35.713170 [ANA_INIT] DLL <<<<<<<<
7192 22:17:35.716291 [ANA_INIT] flow end
7193 22:17:35.719948 ============ LP4 DIFF to SE enter ============
7194 22:17:35.723315 ============ LP4 DIFF to SE exit ============
7195 22:17:35.726537 [ANA_INIT] <<<<<<<<<<<<<
7196 22:17:35.729800 [Flow] Enable top DCM control >>>>>
7197 22:17:35.733109 [Flow] Enable top DCM control <<<<<
7198 22:17:35.736498 Enable DLL master slave shuffle
7199 22:17:35.739844 ==============================================================
7200 22:17:35.743224 Gating Mode config
7201 22:17:35.749658 ==============================================================
7202 22:17:35.750226 Config description:
7203 22:17:35.759661 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7204 22:17:35.765955 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7205 22:17:35.772857 SELPH_MODE 0: By rank 1: By Phase
7206 22:17:35.775712 ==============================================================
7207 22:17:35.779497 GAT_TRACK_EN = 1
7208 22:17:35.782666 RX_GATING_MODE = 2
7209 22:17:35.785859 RX_GATING_TRACK_MODE = 2
7210 22:17:35.789130 SELPH_MODE = 1
7211 22:17:35.792164 PICG_EARLY_EN = 1
7212 22:17:35.795591 VALID_LAT_VALUE = 1
7213 22:17:35.798808 ==============================================================
7214 22:17:35.802027 Enter into Gating configuration >>>>
7215 22:17:35.805593 Exit from Gating configuration <<<<
7216 22:17:35.808827 Enter into DVFS_PRE_config >>>>>
7217 22:17:35.821783 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7218 22:17:35.825519 Exit from DVFS_PRE_config <<<<<
7219 22:17:35.828762 Enter into PICG configuration >>>>
7220 22:17:35.831869 Exit from PICG configuration <<<<
7221 22:17:35.832438 [RX_INPUT] configuration >>>>>
7222 22:17:35.835637 [RX_INPUT] configuration <<<<<
7223 22:17:35.841516 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7224 22:17:35.844925 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7225 22:17:35.851449 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7226 22:17:35.857979 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7227 22:17:35.864494 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7228 22:17:35.871624 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7229 22:17:35.874851 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7230 22:17:35.877982 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7231 22:17:35.884369 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7232 22:17:35.887646 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7233 22:17:35.891074 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7234 22:17:35.894795 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7235 22:17:35.897831 ===================================
7236 22:17:35.901035 LPDDR4 DRAM CONFIGURATION
7237 22:17:35.904488 ===================================
7238 22:17:35.908016 EX_ROW_EN[0] = 0x0
7239 22:17:35.908476 EX_ROW_EN[1] = 0x0
7240 22:17:35.910926 LP4Y_EN = 0x0
7241 22:17:35.911386 WORK_FSP = 0x1
7242 22:17:35.914499 WL = 0x5
7243 22:17:35.914959 RL = 0x5
7244 22:17:35.917751 BL = 0x2
7245 22:17:35.918215 RPST = 0x0
7246 22:17:35.921000 RD_PRE = 0x0
7247 22:17:35.924532 WR_PRE = 0x1
7248 22:17:35.924990 WR_PST = 0x1
7249 22:17:35.927595 DBI_WR = 0x0
7250 22:17:35.928015 DBI_RD = 0x0
7251 22:17:35.930856 OTF = 0x1
7252 22:17:35.934162 ===================================
7253 22:17:35.937506 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7254 22:17:35.940694 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7255 22:17:35.944055 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7256 22:17:35.947123 ===================================
7257 22:17:35.950421 LPDDR4 DRAM CONFIGURATION
7258 22:17:35.953650 ===================================
7259 22:17:35.957494 EX_ROW_EN[0] = 0x10
7260 22:17:35.957920 EX_ROW_EN[1] = 0x0
7261 22:17:35.960627 LP4Y_EN = 0x0
7262 22:17:35.961080 WORK_FSP = 0x1
7263 22:17:35.963867 WL = 0x5
7264 22:17:35.964292 RL = 0x5
7265 22:17:35.967487 BL = 0x2
7266 22:17:35.967914 RPST = 0x0
7267 22:17:35.970433 RD_PRE = 0x0
7268 22:17:35.970862 WR_PRE = 0x1
7269 22:17:35.973732 WR_PST = 0x1
7270 22:17:35.977647 DBI_WR = 0x0
7271 22:17:35.978072 DBI_RD = 0x0
7272 22:17:35.980750 OTF = 0x1
7273 22:17:35.983745 ===================================
7274 22:17:35.987233 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7275 22:17:35.987661 ==
7276 22:17:35.990017 Dram Type= 6, Freq= 0, CH_0, rank 0
7277 22:17:35.996883 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7278 22:17:35.996967 ==
7279 22:17:36.000008 [Duty_Offset_Calibration]
7280 22:17:36.000118 B0:2 B1:0 CA:1
7281 22:17:36.000187
7282 22:17:36.003251 [DutyScan_Calibration_Flow] k_type=0
7283 22:17:36.012523
7284 22:17:36.012637 ==CLK 0==
7285 22:17:36.015320 Final CLK duty delay cell = -4
7286 22:17:36.018719 [-4] MAX Duty = 5031%(X100), DQS PI = 28
7287 22:17:36.022123 [-4] MIN Duty = 4813%(X100), DQS PI = 62
7288 22:17:36.025287 [-4] AVG Duty = 4922%(X100)
7289 22:17:36.025399
7290 22:17:36.028569 CH0 CLK Duty spec in!! Max-Min= 218%
7291 22:17:36.032072 [DutyScan_Calibration_Flow] ====Done====
7292 22:17:36.032154
7293 22:17:36.035167 [DutyScan_Calibration_Flow] k_type=1
7294 22:17:36.051842
7295 22:17:36.051926 ==DQS 0 ==
7296 22:17:36.054879 Final DQS duty delay cell = 0
7297 22:17:36.058664 [0] MAX Duty = 5218%(X100), DQS PI = 28
7298 22:17:36.061817 [0] MIN Duty = 4938%(X100), DQS PI = 62
7299 22:17:36.065159 [0] AVG Duty = 5078%(X100)
7300 22:17:36.065241
7301 22:17:36.065306 ==DQS 1 ==
7302 22:17:36.068103 Final DQS duty delay cell = -4
7303 22:17:36.071769 [-4] MAX Duty = 5125%(X100), DQS PI = 30
7304 22:17:36.074973 [-4] MIN Duty = 4875%(X100), DQS PI = 4
7305 22:17:36.078239 [-4] AVG Duty = 5000%(X100)
7306 22:17:36.078322
7307 22:17:36.081453 CH0 DQS 0 Duty spec in!! Max-Min= 280%
7308 22:17:36.081553
7309 22:17:36.085090 CH0 DQS 1 Duty spec in!! Max-Min= 250%
7310 22:17:36.088405 [DutyScan_Calibration_Flow] ====Done====
7311 22:17:36.088486
7312 22:17:36.091575 [DutyScan_Calibration_Flow] k_type=3
7313 22:17:36.109261
7314 22:17:36.109378 ==DQM 0 ==
7315 22:17:36.112416 Final DQM duty delay cell = 0
7316 22:17:36.115884 [0] MAX Duty = 5124%(X100), DQS PI = 26
7317 22:17:36.119304 [0] MIN Duty = 4813%(X100), DQS PI = 50
7318 22:17:36.122539 [0] AVG Duty = 4968%(X100)
7319 22:17:36.122653
7320 22:17:36.122726 ==DQM 1 ==
7321 22:17:36.125423 Final DQM duty delay cell = 0
7322 22:17:36.129061 [0] MAX Duty = 5249%(X100), DQS PI = 46
7323 22:17:36.132291 [0] MIN Duty = 5031%(X100), DQS PI = 10
7324 22:17:36.135298 [0] AVG Duty = 5140%(X100)
7325 22:17:36.135381
7326 22:17:36.138642 CH0 DQM 0 Duty spec in!! Max-Min= 311%
7327 22:17:36.138724
7328 22:17:36.141924 CH0 DQM 1 Duty spec in!! Max-Min= 218%
7329 22:17:36.145551 [DutyScan_Calibration_Flow] ====Done====
7330 22:17:36.145634
7331 22:17:36.148665 [DutyScan_Calibration_Flow] k_type=2
7332 22:17:36.166354
7333 22:17:36.166436 ==DQ 0 ==
7334 22:17:36.170067 Final DQ duty delay cell = 0
7335 22:17:36.173290 [0] MAX Duty = 5124%(X100), DQS PI = 32
7336 22:17:36.176507 [0] MIN Duty = 5000%(X100), DQS PI = 16
7337 22:17:36.176589 [0] AVG Duty = 5062%(X100)
7338 22:17:36.179571
7339 22:17:36.179653 ==DQ 1 ==
7340 22:17:36.182837 Final DQ duty delay cell = 0
7341 22:17:36.186517 [0] MAX Duty = 4969%(X100), DQS PI = 44
7342 22:17:36.189651 [0] MIN Duty = 4875%(X100), DQS PI = 10
7343 22:17:36.189734 [0] AVG Duty = 4922%(X100)
7344 22:17:36.192758
7345 22:17:36.196602 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7346 22:17:36.196684
7347 22:17:36.199779 CH0 DQ 1 Duty spec in!! Max-Min= 94%
7348 22:17:36.203125 [DutyScan_Calibration_Flow] ====Done====
7349 22:17:36.203207 ==
7350 22:17:36.206251 Dram Type= 6, Freq= 0, CH_1, rank 0
7351 22:17:36.209426 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7352 22:17:36.209509 ==
7353 22:17:36.212710 [Duty_Offset_Calibration]
7354 22:17:36.212845 B0:0 B1:-1 CA:2
7355 22:17:36.212912
7356 22:17:36.216195 [DutyScan_Calibration_Flow] k_type=0
7357 22:17:36.226884
7358 22:17:36.226966 ==CLK 0==
7359 22:17:36.229897 Final CLK duty delay cell = 0
7360 22:17:36.233148 [0] MAX Duty = 5187%(X100), DQS PI = 14
7361 22:17:36.236553 [0] MIN Duty = 4938%(X100), DQS PI = 44
7362 22:17:36.236633 [0] AVG Duty = 5062%(X100)
7363 22:17:36.240127
7364 22:17:36.243502 CH1 CLK Duty spec in!! Max-Min= 249%
7365 22:17:36.246526 [DutyScan_Calibration_Flow] ====Done====
7366 22:17:36.246663
7367 22:17:36.249829 [DutyScan_Calibration_Flow] k_type=1
7368 22:17:36.266242
7369 22:17:36.266336 ==DQS 0 ==
7370 22:17:36.269540 Final DQS duty delay cell = 0
7371 22:17:36.273023 [0] MAX Duty = 5124%(X100), DQS PI = 26
7372 22:17:36.276195 [0] MIN Duty = 4969%(X100), DQS PI = 2
7373 22:17:36.279507 [0] AVG Duty = 5046%(X100)
7374 22:17:36.279587
7375 22:17:36.279651 ==DQS 1 ==
7376 22:17:36.282662 Final DQS duty delay cell = 0
7377 22:17:36.286451 [0] MAX Duty = 5187%(X100), DQS PI = 0
7378 22:17:36.289357 [0] MIN Duty = 4844%(X100), DQS PI = 34
7379 22:17:36.292933 [0] AVG Duty = 5015%(X100)
7380 22:17:36.293013
7381 22:17:36.296179 CH1 DQS 0 Duty spec in!! Max-Min= 155%
7382 22:17:36.296260
7383 22:17:36.299239 CH1 DQS 1 Duty spec in!! Max-Min= 343%
7384 22:17:36.302693 [DutyScan_Calibration_Flow] ====Done====
7385 22:17:36.302773
7386 22:17:36.305691 [DutyScan_Calibration_Flow] k_type=3
7387 22:17:36.324209
7388 22:17:36.324293 ==DQM 0 ==
7389 22:17:36.327364 Final DQM duty delay cell = 4
7390 22:17:36.330456 [4] MAX Duty = 5125%(X100), DQS PI = 8
7391 22:17:36.333660 [4] MIN Duty = 4969%(X100), DQS PI = 46
7392 22:17:36.336998 [4] AVG Duty = 5047%(X100)
7393 22:17:36.337078
7394 22:17:36.337142 ==DQM 1 ==
7395 22:17:36.340575 Final DQM duty delay cell = 0
7396 22:17:36.343513 [0] MAX Duty = 5281%(X100), DQS PI = 58
7397 22:17:36.346820 [0] MIN Duty = 4876%(X100), DQS PI = 34
7398 22:17:36.350244 [0] AVG Duty = 5078%(X100)
7399 22:17:36.350354
7400 22:17:36.353849 CH1 DQM 0 Duty spec in!! Max-Min= 156%
7401 22:17:36.353930
7402 22:17:36.356750 CH1 DQM 1 Duty spec in!! Max-Min= 405%
7403 22:17:36.360256 [DutyScan_Calibration_Flow] ====Done====
7404 22:17:36.360339
7405 22:17:36.363524 [DutyScan_Calibration_Flow] k_type=2
7406 22:17:36.380750
7407 22:17:36.380840 ==DQ 0 ==
7408 22:17:36.383952 Final DQ duty delay cell = 0
7409 22:17:36.387428 [0] MAX Duty = 5093%(X100), DQS PI = 22
7410 22:17:36.390668 [0] MIN Duty = 4969%(X100), DQS PI = 46
7411 22:17:36.390751 [0] AVG Duty = 5031%(X100)
7412 22:17:36.393893
7413 22:17:36.393974 ==DQ 1 ==
7414 22:17:36.397368 Final DQ duty delay cell = 0
7415 22:17:36.400875 [0] MAX Duty = 5062%(X100), DQS PI = 2
7416 22:17:36.403958 [0] MIN Duty = 4844%(X100), DQS PI = 32
7417 22:17:36.404040 [0] AVG Duty = 4953%(X100)
7418 22:17:36.404106
7419 22:17:36.410222 CH1 DQ 0 Duty spec in!! Max-Min= 124%
7420 22:17:36.410330
7421 22:17:36.413662 CH1 DQ 1 Duty spec in!! Max-Min= 218%
7422 22:17:36.416783 [DutyScan_Calibration_Flow] ====Done====
7423 22:17:36.420435 nWR fixed to 30
7424 22:17:36.420519 [ModeRegInit_LP4] CH0 RK0
7425 22:17:36.423585 [ModeRegInit_LP4] CH0 RK1
7426 22:17:36.426975 [ModeRegInit_LP4] CH1 RK0
7427 22:17:36.430195 [ModeRegInit_LP4] CH1 RK1
7428 22:17:36.430277 match AC timing 5
7429 22:17:36.436915 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7430 22:17:36.440278 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7431 22:17:36.443095 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7432 22:17:36.449850 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7433 22:17:36.453392 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7434 22:17:36.453475 [MiockJmeterHQA]
7435 22:17:36.453540
7436 22:17:36.456496 [DramcMiockJmeter] u1RxGatingPI = 0
7437 22:17:36.459714 0 : 4252, 4027
7438 22:17:36.459798 4 : 4363, 4137
7439 22:17:36.463241 8 : 4252, 4027
7440 22:17:36.463325 12 : 4252, 4027
7441 22:17:36.466459 16 : 4366, 4140
7442 22:17:36.466542 20 : 4252, 4027
7443 22:17:36.466609 24 : 4363, 4137
7444 22:17:36.469739 28 : 4253, 4026
7445 22:17:36.469823 32 : 4252, 4027
7446 22:17:36.472918 36 : 4255, 4030
7447 22:17:36.473001 40 : 4252, 4027
7448 22:17:36.476188 44 : 4252, 4027
7449 22:17:36.476272 48 : 4252, 4027
7450 22:17:36.479328 52 : 4252, 4027
7451 22:17:36.479412 56 : 4252, 4027
7452 22:17:36.482882 60 : 4365, 4140
7453 22:17:36.482966 64 : 4252, 4029
7454 22:17:36.483031 68 : 4363, 4140
7455 22:17:36.486180 72 : 4252, 4030
7456 22:17:36.486264 76 : 4363, 4140
7457 22:17:36.489729 80 : 4250, 4027
7458 22:17:36.489812 84 : 4252, 4030
7459 22:17:36.492922 88 : 4253, 3587
7460 22:17:36.493005 92 : 4250, 0
7461 22:17:36.493072 96 : 4255, 0
7462 22:17:36.496164 100 : 4253, 0
7463 22:17:36.496248 104 : 4250, 0
7464 22:17:36.499450 108 : 4250, 0
7465 22:17:36.499533 112 : 4250, 0
7466 22:17:36.499600 116 : 4255, 0
7467 22:17:36.502437 120 : 4250, 0
7468 22:17:36.502520 124 : 4250, 0
7469 22:17:36.502587 128 : 4252, 0
7470 22:17:36.505821 132 : 4249, 0
7471 22:17:36.505904 136 : 4250, 0
7472 22:17:36.509389 140 : 4250, 0
7473 22:17:36.509473 144 : 4250, 0
7474 22:17:36.509549 148 : 4361, 0
7475 22:17:36.512598 152 : 4361, 0
7476 22:17:36.512709 156 : 4250, 0
7477 22:17:36.515557 160 : 4250, 0
7478 22:17:36.515641 164 : 4250, 0
7479 22:17:36.515707 168 : 4361, 0
7480 22:17:36.519121 172 : 4250, 0
7481 22:17:36.519204 176 : 4250, 0
7482 22:17:36.522275 180 : 4250, 0
7483 22:17:36.522359 184 : 4250, 0
7484 22:17:36.522425 188 : 4250, 0
7485 22:17:36.525561 192 : 4250, 0
7486 22:17:36.525644 196 : 4363, 0
7487 22:17:36.528629 200 : 4250, 10
7488 22:17:36.528740 204 : 4250, 2541
7489 22:17:36.532347 208 : 4363, 4140
7490 22:17:36.532430 212 : 4250, 4027
7491 22:17:36.532496 216 : 4363, 4139
7492 22:17:36.535385 220 : 4250, 4026
7493 22:17:36.535468 224 : 4360, 4138
7494 22:17:36.538588 228 : 4360, 4137
7495 22:17:36.538672 232 : 4250, 4027
7496 22:17:36.541725 236 : 4250, 4027
7497 22:17:36.541809 240 : 4253, 4029
7498 22:17:36.545127 244 : 4250, 4027
7499 22:17:36.545210 248 : 4250, 4027
7500 22:17:36.548342 252 : 4360, 4137
7501 22:17:36.548426 256 : 4250, 4027
7502 22:17:36.551653 260 : 4363, 4140
7503 22:17:36.551737 264 : 4250, 4026
7504 22:17:36.555169 268 : 4250, 4027
7505 22:17:36.555252 272 : 4361, 4137
7506 22:17:36.558236 276 : 4250, 4026
7507 22:17:36.558320 280 : 4360, 4137
7508 22:17:36.561593 284 : 4249, 4027
7509 22:17:36.561676 288 : 4250, 4026
7510 22:17:36.561743 292 : 4250, 4027
7511 22:17:36.564975 296 : 4250, 4027
7512 22:17:36.565059 300 : 4255, 4029
7513 22:17:36.568300 304 : 4360, 4137
7514 22:17:36.568383 308 : 4250, 4026
7515 22:17:36.571457 312 : 4250, 3958
7516 22:17:36.571540 316 : 4250, 2157
7517 22:17:36.574644 320 : 4250, 6
7518 22:17:36.574728
7519 22:17:36.574794 MIOCK jitter meter ch=0
7520 22:17:36.574854
7521 22:17:36.577885 1T = (320-92) = 228 dly cells
7522 22:17:36.584624 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 285/100 ps
7523 22:17:36.584732 ==
7524 22:17:36.587814 Dram Type= 6, Freq= 0, CH_0, rank 0
7525 22:17:36.591401 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7526 22:17:36.591485 ==
7527 22:17:36.597883 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7528 22:17:36.601083 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7529 22:17:36.607902 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7530 22:17:36.610775 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7531 22:17:36.620898 [CA 0] Center 42 (12~73) winsize 62
7532 22:17:36.624370 [CA 1] Center 42 (12~72) winsize 61
7533 22:17:36.627622 [CA 2] Center 37 (7~67) winsize 61
7534 22:17:36.630894 [CA 3] Center 37 (7~67) winsize 61
7535 22:17:36.634199 [CA 4] Center 36 (6~66) winsize 61
7536 22:17:36.637289 [CA 5] Center 35 (5~65) winsize 61
7537 22:17:36.637373
7538 22:17:36.640531 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7539 22:17:36.640614
7540 22:17:36.647259 [CATrainingPosCal] consider 1 rank data
7541 22:17:36.647359 u2DelayCellTimex100 = 285/100 ps
7542 22:17:36.653832 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7543 22:17:36.657456 CA1 delay=42 (12~72),Diff = 7 PI (23 cell)
7544 22:17:36.660509 CA2 delay=37 (7~67),Diff = 2 PI (6 cell)
7545 22:17:36.663883 CA3 delay=37 (7~67),Diff = 2 PI (6 cell)
7546 22:17:36.667277 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7547 22:17:36.670332 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
7548 22:17:36.670416
7549 22:17:36.673744 CA PerBit enable=1, Macro0, CA PI delay=35
7550 22:17:36.673832
7551 22:17:36.677120 [CBTSetCACLKResult] CA Dly = 35
7552 22:17:36.680162 CS Dly: 9 (0~40)
7553 22:17:36.683498 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7554 22:17:36.687130 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7555 22:17:36.687213 ==
7556 22:17:36.690229 Dram Type= 6, Freq= 0, CH_0, rank 1
7557 22:17:36.696673 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7558 22:17:36.696759 ==
7559 22:17:36.700324 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7560 22:17:36.706882 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7561 22:17:36.709989 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7562 22:17:36.716719 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7563 22:17:36.724228 [CA 0] Center 43 (13~73) winsize 61
7564 22:17:36.727578 [CA 1] Center 43 (13~73) winsize 61
7565 22:17:36.730797 [CA 2] Center 37 (8~67) winsize 60
7566 22:17:36.734309 [CA 3] Center 38 (8~68) winsize 61
7567 22:17:36.737386 [CA 4] Center 36 (6~66) winsize 61
7568 22:17:36.740587 [CA 5] Center 36 (6~66) winsize 61
7569 22:17:36.740697
7570 22:17:36.743967 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7571 22:17:36.744097
7572 22:17:36.750565 [CATrainingPosCal] consider 2 rank data
7573 22:17:36.750665 u2DelayCellTimex100 = 285/100 ps
7574 22:17:36.757169 CA0 delay=43 (13~73),Diff = 8 PI (27 cell)
7575 22:17:36.760234 CA1 delay=42 (13~72),Diff = 7 PI (23 cell)
7576 22:17:36.763668 CA2 delay=37 (8~67),Diff = 2 PI (6 cell)
7577 22:17:36.767004 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7578 22:17:36.770391 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7579 22:17:36.773741 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7580 22:17:36.773813
7581 22:17:36.776640 CA PerBit enable=1, Macro0, CA PI delay=35
7582 22:17:36.776737
7583 22:17:36.779992 [CBTSetCACLKResult] CA Dly = 35
7584 22:17:36.783154 CS Dly: 10 (0~43)
7585 22:17:36.786426 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7586 22:17:36.789986 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7587 22:17:36.790062
7588 22:17:36.792949 ----->DramcWriteLeveling(PI) begin...
7589 22:17:36.793039 ==
7590 22:17:36.796629 Dram Type= 6, Freq= 0, CH_0, rank 0
7591 22:17:36.803148 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7592 22:17:36.803224 ==
7593 22:17:36.806341 Write leveling (Byte 0): 36 => 36
7594 22:17:36.809711 Write leveling (Byte 1): 31 => 31
7595 22:17:36.812922 DramcWriteLeveling(PI) end<-----
7596 22:17:36.813045
7597 22:17:36.813145 ==
7598 22:17:36.815995 Dram Type= 6, Freq= 0, CH_0, rank 0
7599 22:17:36.819347 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7600 22:17:36.819456 ==
7601 22:17:36.822568 [Gating] SW mode calibration
7602 22:17:36.829301 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7603 22:17:36.836017 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7604 22:17:36.839591 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7605 22:17:36.842613 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7606 22:17:36.849525 1 4 8 | B1->B0 | 2323 2d2c | 0 1 | (0 0) (1 1)
7607 22:17:36.852457 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7608 22:17:36.856056 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7609 22:17:36.862420 1 4 20 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
7610 22:17:36.865731 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7611 22:17:36.868933 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7612 22:17:36.875468 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7613 22:17:36.879182 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7614 22:17:36.882256 1 5 8 | B1->B0 | 3434 2d2d | 1 1 | (1 1) (1 0)
7615 22:17:36.888649 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
7616 22:17:36.892120 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7617 22:17:36.895396 1 5 20 | B1->B0 | 2828 2323 | 0 0 | (1 0) (0 0)
7618 22:17:36.901864 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7619 22:17:36.905144 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7620 22:17:36.908432 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7621 22:17:36.915278 1 6 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7622 22:17:36.918546 1 6 8 | B1->B0 | 2323 3b3b | 0 0 | (0 0) (1 1)
7623 22:17:36.921613 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7624 22:17:36.928333 1 6 16 | B1->B0 | 2525 4646 | 0 0 | (0 0) (0 0)
7625 22:17:36.931682 1 6 20 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
7626 22:17:36.935172 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7627 22:17:36.941544 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7628 22:17:36.944669 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7629 22:17:36.948061 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7630 22:17:36.954697 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7631 22:17:36.957803 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7632 22:17:36.961244 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7633 22:17:36.967660 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7634 22:17:36.971407 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7635 22:17:36.974609 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7636 22:17:36.981399 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7637 22:17:36.984314 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7638 22:17:36.987710 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7639 22:17:36.994214 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7640 22:17:36.997213 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7641 22:17:37.000889 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7642 22:17:37.007389 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7643 22:17:37.011054 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7644 22:17:37.014094 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7645 22:17:37.021000 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7646 22:17:37.024081 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7647 22:17:37.027304 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7648 22:17:37.030800 Total UI for P1: 0, mck2ui 16
7649 22:17:37.033923 best dqsien dly found for B0: ( 1, 9, 10)
7650 22:17:37.037512 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7651 22:17:37.043694 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7652 22:17:37.046989 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7653 22:17:37.050386 Total UI for P1: 0, mck2ui 16
7654 22:17:37.053518 best dqsien dly found for B1: ( 1, 9, 20)
7655 22:17:37.056809 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7656 22:17:37.060401 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7657 22:17:37.060483
7658 22:17:37.063428 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7659 22:17:37.070079 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7660 22:17:37.070162 [Gating] SW calibration Done
7661 22:17:37.073246 ==
7662 22:17:37.073328 Dram Type= 6, Freq= 0, CH_0, rank 0
7663 22:17:37.080071 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7664 22:17:37.080154 ==
7665 22:17:37.080220 RX Vref Scan: 0
7666 22:17:37.080280
7667 22:17:37.083424 RX Vref 0 -> 0, step: 1
7668 22:17:37.083507
7669 22:17:37.086925 RX Delay 0 -> 252, step: 8
7670 22:17:37.089889 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
7671 22:17:37.093237 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7672 22:17:37.096422 iDelay=200, Bit 2, Center 135 (88 ~ 183) 96
7673 22:17:37.103173 iDelay=200, Bit 3, Center 135 (88 ~ 183) 96
7674 22:17:37.106663 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7675 22:17:37.109976 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7676 22:17:37.113517 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7677 22:17:37.116755 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7678 22:17:37.123236 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
7679 22:17:37.126196 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7680 22:17:37.130018 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
7681 22:17:37.133004 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
7682 22:17:37.136256 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7683 22:17:37.143054 iDelay=200, Bit 13, Center 131 (88 ~ 175) 88
7684 22:17:37.146244 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7685 22:17:37.149368 iDelay=200, Bit 15, Center 131 (80 ~ 183) 104
7686 22:17:37.149451 ==
7687 22:17:37.152728 Dram Type= 6, Freq= 0, CH_0, rank 0
7688 22:17:37.156315 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7689 22:17:37.159434 ==
7690 22:17:37.159517 DQS Delay:
7691 22:17:37.159581 DQS0 = 0, DQS1 = 0
7692 22:17:37.162685 DQM Delay:
7693 22:17:37.162767 DQM0 = 138, DQM1 = 126
7694 22:17:37.166291 DQ Delay:
7695 22:17:37.169264 DQ0 =139, DQ1 =139, DQ2 =135, DQ3 =135
7696 22:17:37.172350 DQ4 =139, DQ5 =123, DQ6 =147, DQ7 =147
7697 22:17:37.175967 DQ8 =119, DQ9 =115, DQ10 =123, DQ11 =123
7698 22:17:37.179192 DQ12 =131, DQ13 =131, DQ14 =139, DQ15 =131
7699 22:17:37.179274
7700 22:17:37.179338
7701 22:17:37.179396 ==
7702 22:17:37.182438 Dram Type= 6, Freq= 0, CH_0, rank 0
7703 22:17:37.185597 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7704 22:17:37.185679 ==
7705 22:17:37.188937
7706 22:17:37.189019
7707 22:17:37.189083 TX Vref Scan disable
7708 22:17:37.192306 == TX Byte 0 ==
7709 22:17:37.195457 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7710 22:17:37.198945 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7711 22:17:37.202092 == TX Byte 1 ==
7712 22:17:37.205642 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
7713 22:17:37.208730 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7714 22:17:37.208831 ==
7715 22:17:37.212162 Dram Type= 6, Freq= 0, CH_0, rank 0
7716 22:17:37.218799 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7717 22:17:37.218904 ==
7718 22:17:37.230868
7719 22:17:37.234273 TX Vref early break, caculate TX vref
7720 22:17:37.237400 TX Vref=16, minBit 1, minWin=23, winSum=377
7721 22:17:37.240677 TX Vref=18, minBit 6, minWin=23, winSum=387
7722 22:17:37.244209 TX Vref=20, minBit 5, minWin=24, winSum=401
7723 22:17:37.247165 TX Vref=22, minBit 7, minWin=24, winSum=412
7724 22:17:37.250635 TX Vref=24, minBit 4, minWin=25, winSum=418
7725 22:17:37.257184 TX Vref=26, minBit 12, minWin=25, winSum=426
7726 22:17:37.260326 TX Vref=28, minBit 4, minWin=25, winSum=420
7727 22:17:37.264032 TX Vref=30, minBit 2, minWin=25, winSum=416
7728 22:17:37.267158 TX Vref=32, minBit 2, minWin=24, winSum=406
7729 22:17:37.270243 TX Vref=34, minBit 2, minWin=24, winSum=397
7730 22:17:37.276747 [TxChooseVref] Worse bit 12, Min win 25, Win sum 426, Final Vref 26
7731 22:17:37.276854
7732 22:17:37.280222 Final TX Range 0 Vref 26
7733 22:17:37.280305
7734 22:17:37.280430 ==
7735 22:17:37.283274 Dram Type= 6, Freq= 0, CH_0, rank 0
7736 22:17:37.286562 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7737 22:17:37.286659 ==
7738 22:17:37.286800
7739 22:17:37.289993
7740 22:17:37.290076 TX Vref Scan disable
7741 22:17:37.296747 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
7742 22:17:37.296844 == TX Byte 0 ==
7743 22:17:37.299607 u2DelayCellOfst[0]=10 cells (3 PI)
7744 22:17:37.302913 u2DelayCellOfst[1]=17 cells (5 PI)
7745 22:17:37.306362 u2DelayCellOfst[2]=10 cells (3 PI)
7746 22:17:37.309580 u2DelayCellOfst[3]=10 cells (3 PI)
7747 22:17:37.313213 u2DelayCellOfst[4]=6 cells (2 PI)
7748 22:17:37.316179 u2DelayCellOfst[5]=0 cells (0 PI)
7749 22:17:37.319623 u2DelayCellOfst[6]=17 cells (5 PI)
7750 22:17:37.322623 u2DelayCellOfst[7]=13 cells (4 PI)
7751 22:17:37.325992 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7752 22:17:37.329650 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7753 22:17:37.332898 == TX Byte 1 ==
7754 22:17:37.336039 u2DelayCellOfst[8]=0 cells (0 PI)
7755 22:17:37.339276 u2DelayCellOfst[9]=0 cells (0 PI)
7756 22:17:37.342526 u2DelayCellOfst[10]=6 cells (2 PI)
7757 22:17:37.346209 u2DelayCellOfst[11]=3 cells (1 PI)
7758 22:17:37.349181 u2DelayCellOfst[12]=10 cells (3 PI)
7759 22:17:37.352634 u2DelayCellOfst[13]=13 cells (4 PI)
7760 22:17:37.352744 u2DelayCellOfst[14]=13 cells (4 PI)
7761 22:17:37.355594 u2DelayCellOfst[15]=13 cells (4 PI)
7762 22:17:37.362567 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7763 22:17:37.365655 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7764 22:17:37.369176 DramC Write-DBI on
7765 22:17:37.369286 ==
7766 22:17:37.372507 Dram Type= 6, Freq= 0, CH_0, rank 0
7767 22:17:37.375678 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7768 22:17:37.375782 ==
7769 22:17:37.375876
7770 22:17:37.375965
7771 22:17:37.378730 TX Vref Scan disable
7772 22:17:37.378827 == TX Byte 0 ==
7773 22:17:37.385520 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
7774 22:17:37.385605 == TX Byte 1 ==
7775 22:17:37.388893 Update DQM dly =727 (2 ,6, 23) DQM OEN =(3 ,3)
7776 22:17:37.392093 DramC Write-DBI off
7777 22:17:37.392177
7778 22:17:37.392243 [DATLAT]
7779 22:17:37.395262 Freq=1600, CH0 RK0
7780 22:17:37.395347
7781 22:17:37.395414 DATLAT Default: 0xf
7782 22:17:37.398740 0, 0xFFFF, sum = 0
7783 22:17:37.401588 1, 0xFFFF, sum = 0
7784 22:17:37.401674 2, 0xFFFF, sum = 0
7785 22:17:37.405145 3, 0xFFFF, sum = 0
7786 22:17:37.405231 4, 0xFFFF, sum = 0
7787 22:17:37.408256 5, 0xFFFF, sum = 0
7788 22:17:37.408342 6, 0xFFFF, sum = 0
7789 22:17:37.411694 7, 0xFFFF, sum = 0
7790 22:17:37.411780 8, 0xFFFF, sum = 0
7791 22:17:37.414876 9, 0xFFFF, sum = 0
7792 22:17:37.414965 10, 0xFFFF, sum = 0
7793 22:17:37.417976 11, 0xFFFF, sum = 0
7794 22:17:37.418062 12, 0xFFFF, sum = 0
7795 22:17:37.421465 13, 0xFFFF, sum = 0
7796 22:17:37.421552 14, 0x0, sum = 1
7797 22:17:37.424550 15, 0x0, sum = 2
7798 22:17:37.424636 16, 0x0, sum = 3
7799 22:17:37.427857 17, 0x0, sum = 4
7800 22:17:37.427942 best_step = 15
7801 22:17:37.428018
7802 22:17:37.428113 ==
7803 22:17:37.431550 Dram Type= 6, Freq= 0, CH_0, rank 0
7804 22:17:37.437919 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7805 22:17:37.438022 ==
7806 22:17:37.438091 RX Vref Scan: 1
7807 22:17:37.438153
7808 22:17:37.441147 Set Vref Range= 24 -> 127
7809 22:17:37.441231
7810 22:17:37.444578 RX Vref 24 -> 127, step: 1
7811 22:17:37.444689
7812 22:17:37.447803 RX Delay 19 -> 252, step: 4
7813 22:17:37.447912
7814 22:17:37.451042 Set Vref, RX VrefLevel [Byte0]: 24
7815 22:17:37.454195 [Byte1]: 24
7816 22:17:37.454274
7817 22:17:37.457711 Set Vref, RX VrefLevel [Byte0]: 25
7818 22:17:37.460879 [Byte1]: 25
7819 22:17:37.460958
7820 22:17:37.464047 Set Vref, RX VrefLevel [Byte0]: 26
7821 22:17:37.467638 [Byte1]: 26
7822 22:17:37.470718
7823 22:17:37.470801 Set Vref, RX VrefLevel [Byte0]: 27
7824 22:17:37.474021 [Byte1]: 27
7825 22:17:37.478243
7826 22:17:37.478327 Set Vref, RX VrefLevel [Byte0]: 28
7827 22:17:37.481603 [Byte1]: 28
7828 22:17:37.485897
7829 22:17:37.485981 Set Vref, RX VrefLevel [Byte0]: 29
7830 22:17:37.489191 [Byte1]: 29
7831 22:17:37.493261
7832 22:17:37.493345 Set Vref, RX VrefLevel [Byte0]: 30
7833 22:17:37.496741 [Byte1]: 30
7834 22:17:37.501011
7835 22:17:37.504108 Set Vref, RX VrefLevel [Byte0]: 31
7836 22:17:37.507272 [Byte1]: 31
7837 22:17:37.507355
7838 22:17:37.510808 Set Vref, RX VrefLevel [Byte0]: 32
7839 22:17:37.513785 [Byte1]: 32
7840 22:17:37.513896
7841 22:17:37.517173 Set Vref, RX VrefLevel [Byte0]: 33
7842 22:17:37.520361 [Byte1]: 33
7843 22:17:37.520443
7844 22:17:37.523693 Set Vref, RX VrefLevel [Byte0]: 34
7845 22:17:37.526810 [Byte1]: 34
7846 22:17:37.531133
7847 22:17:37.531225 Set Vref, RX VrefLevel [Byte0]: 35
7848 22:17:37.537649 [Byte1]: 35
7849 22:17:37.537733
7850 22:17:37.540602 Set Vref, RX VrefLevel [Byte0]: 36
7851 22:17:37.544118 [Byte1]: 36
7852 22:17:37.544229
7853 22:17:37.547449 Set Vref, RX VrefLevel [Byte0]: 37
7854 22:17:37.550809 [Byte1]: 37
7855 22:17:37.554172
7856 22:17:37.554310 Set Vref, RX VrefLevel [Byte0]: 38
7857 22:17:37.556959 [Byte1]: 38
7858 22:17:37.561430
7859 22:17:37.561538 Set Vref, RX VrefLevel [Byte0]: 39
7860 22:17:37.564596 [Byte1]: 39
7861 22:17:37.569357
7862 22:17:37.569463 Set Vref, RX VrefLevel [Byte0]: 40
7863 22:17:37.572148 [Byte1]: 40
7864 22:17:37.576648
7865 22:17:37.576760 Set Vref, RX VrefLevel [Byte0]: 41
7866 22:17:37.580034 [Byte1]: 41
7867 22:17:37.584175
7868 22:17:37.584278 Set Vref, RX VrefLevel [Byte0]: 42
7869 22:17:37.587308 [Byte1]: 42
7870 22:17:37.591923
7871 22:17:37.592028 Set Vref, RX VrefLevel [Byte0]: 43
7872 22:17:37.595232 [Byte1]: 43
7873 22:17:37.599369
7874 22:17:37.599474 Set Vref, RX VrefLevel [Byte0]: 44
7875 22:17:37.602448 [Byte1]: 44
7876 22:17:37.606769
7877 22:17:37.606862 Set Vref, RX VrefLevel [Byte0]: 45
7878 22:17:37.609987 [Byte1]: 45
7879 22:17:37.614458
7880 22:17:37.614574 Set Vref, RX VrefLevel [Byte0]: 46
7881 22:17:37.617579 [Byte1]: 46
7882 22:17:37.622446
7883 22:17:37.622529 Set Vref, RX VrefLevel [Byte0]: 47
7884 22:17:37.625549 [Byte1]: 47
7885 22:17:37.629921
7886 22:17:37.630017 Set Vref, RX VrefLevel [Byte0]: 48
7887 22:17:37.633107 [Byte1]: 48
7888 22:17:37.637298
7889 22:17:37.637381 Set Vref, RX VrefLevel [Byte0]: 49
7890 22:17:37.640363 [Byte1]: 49
7891 22:17:37.644648
7892 22:17:37.644775 Set Vref, RX VrefLevel [Byte0]: 50
7893 22:17:37.648074 [Byte1]: 50
7894 22:17:37.652290
7895 22:17:37.652368 Set Vref, RX VrefLevel [Byte0]: 51
7896 22:17:37.655936 [Byte1]: 51
7897 22:17:37.660112
7898 22:17:37.660189 Set Vref, RX VrefLevel [Byte0]: 52
7899 22:17:37.663159 [Byte1]: 52
7900 22:17:37.667323
7901 22:17:37.667425 Set Vref, RX VrefLevel [Byte0]: 53
7902 22:17:37.670630 [Byte1]: 53
7903 22:17:37.675106
7904 22:17:37.675189 Set Vref, RX VrefLevel [Byte0]: 54
7905 22:17:37.678262 [Byte1]: 54
7906 22:17:37.682947
7907 22:17:37.683039 Set Vref, RX VrefLevel [Byte0]: 55
7908 22:17:37.685980 [Byte1]: 55
7909 22:17:37.690074
7910 22:17:37.690152 Set Vref, RX VrefLevel [Byte0]: 56
7911 22:17:37.693608 [Byte1]: 56
7912 22:17:37.697791
7913 22:17:37.697868 Set Vref, RX VrefLevel [Byte0]: 57
7914 22:17:37.700858 [Byte1]: 57
7915 22:17:37.705483
7916 22:17:37.705560 Set Vref, RX VrefLevel [Byte0]: 58
7917 22:17:37.708746 [Byte1]: 58
7918 22:17:37.712677
7919 22:17:37.712788 Set Vref, RX VrefLevel [Byte0]: 59
7920 22:17:37.716363 [Byte1]: 59
7921 22:17:37.720538
7922 22:17:37.720650 Set Vref, RX VrefLevel [Byte0]: 60
7923 22:17:37.723823 [Byte1]: 60
7924 22:17:37.728011
7925 22:17:37.728116 Set Vref, RX VrefLevel [Byte0]: 61
7926 22:17:37.731605 [Byte1]: 61
7927 22:17:37.735758
7928 22:17:37.735863 Set Vref, RX VrefLevel [Byte0]: 62
7929 22:17:37.739102 [Byte1]: 62
7930 22:17:37.743274
7931 22:17:37.743357 Set Vref, RX VrefLevel [Byte0]: 63
7932 22:17:37.746638 [Byte1]: 63
7933 22:17:37.750939
7934 22:17:37.751053 Set Vref, RX VrefLevel [Byte0]: 64
7935 22:17:37.754210 [Byte1]: 64
7936 22:17:37.758305
7937 22:17:37.758391 Set Vref, RX VrefLevel [Byte0]: 65
7938 22:17:37.761574 [Byte1]: 65
7939 22:17:37.766049
7940 22:17:37.766134 Set Vref, RX VrefLevel [Byte0]: 66
7941 22:17:37.769285 [Byte1]: 66
7942 22:17:37.773381
7943 22:17:37.773466 Set Vref, RX VrefLevel [Byte0]: 67
7944 22:17:37.776941 [Byte1]: 67
7945 22:17:37.780889
7946 22:17:37.780973 Set Vref, RX VrefLevel [Byte0]: 68
7947 22:17:37.784595 [Byte1]: 68
7948 22:17:37.788748
7949 22:17:37.788842 Set Vref, RX VrefLevel [Byte0]: 69
7950 22:17:37.791929 [Byte1]: 69
7951 22:17:37.796291
7952 22:17:37.796375 Set Vref, RX VrefLevel [Byte0]: 70
7953 22:17:37.799645 [Byte1]: 70
7954 22:17:37.803888
7955 22:17:37.804019 Set Vref, RX VrefLevel [Byte0]: 71
7956 22:17:37.807211 [Byte1]: 71
7957 22:17:37.811625
7958 22:17:37.811734 Set Vref, RX VrefLevel [Byte0]: 72
7959 22:17:37.814500 [Byte1]: 72
7960 22:17:37.818945
7961 22:17:37.819050 Set Vref, RX VrefLevel [Byte0]: 73
7962 22:17:37.822108 [Byte1]: 73
7963 22:17:37.826733
7964 22:17:37.826816 Set Vref, RX VrefLevel [Byte0]: 74
7965 22:17:37.829808 [Byte1]: 74
7966 22:17:37.834117
7967 22:17:37.834201 Set Vref, RX VrefLevel [Byte0]: 75
7968 22:17:37.837175 [Byte1]: 75
7969 22:17:37.841758
7970 22:17:37.841850 Set Vref, RX VrefLevel [Byte0]: 76
7971 22:17:37.844661 [Byte1]: 76
7972 22:17:37.848952
7973 22:17:37.849084 Set Vref, RX VrefLevel [Byte0]: 77
7974 22:17:37.852613 [Byte1]: 77
7975 22:17:37.856729
7976 22:17:37.856840 Set Vref, RX VrefLevel [Byte0]: 78
7977 22:17:37.860024 [Byte1]: 78
7978 22:17:37.864161
7979 22:17:37.867393 Set Vref, RX VrefLevel [Byte0]: 79
7980 22:17:37.870813 [Byte1]: 79
7981 22:17:37.870899
7982 22:17:37.873842 Set Vref, RX VrefLevel [Byte0]: 80
7983 22:17:37.877178 [Byte1]: 80
7984 22:17:37.877260
7985 22:17:37.880522 Set Vref, RX VrefLevel [Byte0]: 81
7986 22:17:37.883966 [Byte1]: 81
7987 22:17:37.884043
7988 22:17:37.887174 Final RX Vref Byte 0 = 60 to rank0
7989 22:17:37.890431 Final RX Vref Byte 1 = 62 to rank0
7990 22:17:37.893787 Final RX Vref Byte 0 = 60 to rank1
7991 22:17:37.897061 Final RX Vref Byte 1 = 62 to rank1==
7992 22:17:37.900294 Dram Type= 6, Freq= 0, CH_0, rank 0
7993 22:17:37.906830 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7994 22:17:37.906918 ==
7995 22:17:37.906986 DQS Delay:
7996 22:17:37.907049 DQS0 = 0, DQS1 = 0
7997 22:17:37.910601 DQM Delay:
7998 22:17:37.910677 DQM0 = 137, DQM1 = 124
7999 22:17:37.913709 DQ Delay:
8000 22:17:37.917202 DQ0 =136, DQ1 =140, DQ2 =132, DQ3 =132
8001 22:17:37.920137 DQ4 =140, DQ5 =126, DQ6 =146, DQ7 =144
8002 22:17:37.923713 DQ8 =116, DQ9 =112, DQ10 =126, DQ11 =118
8003 22:17:37.926988 DQ12 =128, DQ13 =128, DQ14 =136, DQ15 =134
8004 22:17:37.927082
8005 22:17:37.927155
8006 22:17:37.927218
8007 22:17:37.930227 [DramC_TX_OE_Calibration] TA2
8008 22:17:37.933530 Original DQ_B0 (3 6) =30, OEN = 27
8009 22:17:37.936803 Original DQ_B1 (3 6) =30, OEN = 27
8010 22:17:37.940018 24, 0x0, End_B0=24 End_B1=24
8011 22:17:37.940097 25, 0x0, End_B0=25 End_B1=25
8012 22:17:37.943434 26, 0x0, End_B0=26 End_B1=26
8013 22:17:37.946804 27, 0x0, End_B0=27 End_B1=27
8014 22:17:37.950151 28, 0x0, End_B0=28 End_B1=28
8015 22:17:37.953075 29, 0x0, End_B0=29 End_B1=29
8016 22:17:37.953162 30, 0x0, End_B0=30 End_B1=30
8017 22:17:37.956389 31, 0x4141, End_B0=30 End_B1=30
8018 22:17:37.960054 Byte0 end_step=30 best_step=27
8019 22:17:37.963308 Byte1 end_step=30 best_step=27
8020 22:17:37.966442 Byte0 TX OE(2T, 0.5T) = (3, 3)
8021 22:17:37.969689 Byte1 TX OE(2T, 0.5T) = (3, 3)
8022 22:17:37.969773
8023 22:17:37.969839
8024 22:17:37.976282 [DQSOSCAuto] RK0, (LSB)MR18= 0x1b19, (MSB)MR19= 0x303, tDQSOscB0 = 397 ps tDQSOscB1 = 396 ps
8025 22:17:37.979816 CH0 RK0: MR19=303, MR18=1B19
8026 22:17:37.986289 CH0_RK0: MR19=0x303, MR18=0x1B19, DQSOSC=396, MR23=63, INC=23, DEC=15
8027 22:17:37.986410
8028 22:17:37.989717 ----->DramcWriteLeveling(PI) begin...
8029 22:17:37.989824 ==
8030 22:17:37.992704 Dram Type= 6, Freq= 0, CH_0, rank 1
8031 22:17:37.995952 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8032 22:17:37.996058 ==
8033 22:17:37.999592 Write leveling (Byte 0): 38 => 38
8034 22:17:38.002737 Write leveling (Byte 1): 30 => 30
8035 22:17:38.005831 DramcWriteLeveling(PI) end<-----
8036 22:17:38.005916
8037 22:17:38.005982 ==
8038 22:17:38.009088 Dram Type= 6, Freq= 0, CH_0, rank 1
8039 22:17:38.012493 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8040 22:17:38.015714 ==
8041 22:17:38.015795 [Gating] SW mode calibration
8042 22:17:38.025713 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8043 22:17:38.029340 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8044 22:17:38.032249 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8045 22:17:38.039127 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8046 22:17:38.042499 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8047 22:17:38.045685 1 4 12 | B1->B0 | 2424 3333 | 0 0 | (0 0) (0 0)
8048 22:17:38.052065 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8049 22:17:38.055416 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8050 22:17:38.058669 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8051 22:17:38.065639 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8052 22:17:38.068947 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8053 22:17:38.072258 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8054 22:17:38.078655 1 5 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
8055 22:17:38.081874 1 5 12 | B1->B0 | 3333 2828 | 1 0 | (1 0) (0 1)
8056 22:17:38.085211 1 5 16 | B1->B0 | 2929 2323 | 0 0 | (0 1) (1 0)
8057 22:17:38.091988 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8058 22:17:38.095026 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8059 22:17:38.098183 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8060 22:17:38.105360 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8061 22:17:38.108292 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8062 22:17:38.111840 1 6 8 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
8063 22:17:38.118232 1 6 12 | B1->B0 | 2e2e 4444 | 0 0 | (0 0) (0 0)
8064 22:17:38.121421 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8065 22:17:38.124964 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8066 22:17:38.131698 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8067 22:17:38.134799 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8068 22:17:38.138076 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8069 22:17:38.144424 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8070 22:17:38.147817 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8071 22:17:38.151315 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8072 22:17:38.157542 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8073 22:17:38.161060 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8074 22:17:38.164619 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8075 22:17:38.171224 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8076 22:17:38.174448 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8077 22:17:38.177663 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8078 22:17:38.184390 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8079 22:17:38.187604 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8080 22:17:38.190699 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8081 22:17:38.197334 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8082 22:17:38.200512 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8083 22:17:38.204040 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8084 22:17:38.210818 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8085 22:17:38.213671 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8086 22:17:38.217181 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8087 22:17:38.223733 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8088 22:17:38.227263 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8089 22:17:38.230274 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8090 22:17:38.233778 Total UI for P1: 0, mck2ui 16
8091 22:17:38.237075 best dqsien dly found for B0: ( 1, 9, 12)
8092 22:17:38.243597 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8093 22:17:38.243704 Total UI for P1: 0, mck2ui 16
8094 22:17:38.250447 best dqsien dly found for B1: ( 1, 9, 16)
8095 22:17:38.253523 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8096 22:17:38.256831 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8097 22:17:38.256917
8098 22:17:38.260184 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8099 22:17:38.263381 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8100 22:17:38.266606 [Gating] SW calibration Done
8101 22:17:38.266685 ==
8102 22:17:38.270036 Dram Type= 6, Freq= 0, CH_0, rank 1
8103 22:17:38.273542 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8104 22:17:38.273630 ==
8105 22:17:38.276814 RX Vref Scan: 0
8106 22:17:38.276938
8107 22:17:38.277062 RX Vref 0 -> 0, step: 1
8108 22:17:38.277161
8109 22:17:38.280076 RX Delay 0 -> 252, step: 8
8110 22:17:38.283650 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8111 22:17:38.289786 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8112 22:17:38.293469 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8113 22:17:38.296621 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
8114 22:17:38.299751 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8115 22:17:38.303266 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8116 22:17:38.310049 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8117 22:17:38.313135 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8118 22:17:38.316370 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8119 22:17:38.319701 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8120 22:17:38.322984 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
8121 22:17:38.329694 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8122 22:17:38.332853 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8123 22:17:38.335992 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
8124 22:17:38.339674 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8125 22:17:38.346182 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8126 22:17:38.346261 ==
8127 22:17:38.349270 Dram Type= 6, Freq= 0, CH_0, rank 1
8128 22:17:38.353019 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8129 22:17:38.353093 ==
8130 22:17:38.353160 DQS Delay:
8131 22:17:38.356091 DQS0 = 0, DQS1 = 0
8132 22:17:38.356191 DQM Delay:
8133 22:17:38.359453 DQM0 = 135, DQM1 = 125
8134 22:17:38.359561 DQ Delay:
8135 22:17:38.362573 DQ0 =135, DQ1 =135, DQ2 =135, DQ3 =131
8136 22:17:38.365714 DQ4 =135, DQ5 =127, DQ6 =143, DQ7 =143
8137 22:17:38.369303 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =123
8138 22:17:38.372440 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =135
8139 22:17:38.372540
8140 22:17:38.372630
8141 22:17:38.375688 ==
8142 22:17:38.379229 Dram Type= 6, Freq= 0, CH_0, rank 1
8143 22:17:38.382433 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8144 22:17:38.382530 ==
8145 22:17:38.382625
8146 22:17:38.382713
8147 22:17:38.385599 TX Vref Scan disable
8148 22:17:38.385693 == TX Byte 0 ==
8149 22:17:38.392311 Update DQ dly =994 (3 ,6, 34) DQ OEN =(3 ,3)
8150 22:17:38.395655 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
8151 22:17:38.395758 == TX Byte 1 ==
8152 22:17:38.402202 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8153 22:17:38.405336 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8154 22:17:38.405439 ==
8155 22:17:38.408878 Dram Type= 6, Freq= 0, CH_0, rank 1
8156 22:17:38.412203 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8157 22:17:38.412311 ==
8158 22:17:38.426603
8159 22:17:38.429703 TX Vref early break, caculate TX vref
8160 22:17:38.432816 TX Vref=16, minBit 0, minWin=23, winSum=392
8161 22:17:38.436085 TX Vref=18, minBit 1, minWin=24, winSum=403
8162 22:17:38.439458 TX Vref=20, minBit 0, minWin=24, winSum=409
8163 22:17:38.442891 TX Vref=22, minBit 2, minWin=25, winSum=416
8164 22:17:38.445857 TX Vref=24, minBit 0, minWin=26, winSum=424
8165 22:17:38.452562 TX Vref=26, minBit 0, minWin=26, winSum=432
8166 22:17:38.456232 TX Vref=28, minBit 0, minWin=26, winSum=433
8167 22:17:38.459034 TX Vref=30, minBit 0, minWin=25, winSum=423
8168 22:17:38.462487 TX Vref=32, minBit 0, minWin=25, winSum=413
8169 22:17:38.465848 TX Vref=34, minBit 3, minWin=24, winSum=404
8170 22:17:38.472336 [TxChooseVref] Worse bit 0, Min win 26, Win sum 433, Final Vref 28
8171 22:17:38.472438
8172 22:17:38.475600 Final TX Range 0 Vref 28
8173 22:17:38.475678
8174 22:17:38.475742 ==
8175 22:17:38.479280 Dram Type= 6, Freq= 0, CH_0, rank 1
8176 22:17:38.482238 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8177 22:17:38.482339 ==
8178 22:17:38.482437
8179 22:17:38.482533
8180 22:17:38.485628 TX Vref Scan disable
8181 22:17:38.492226 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8182 22:17:38.492328 == TX Byte 0 ==
8183 22:17:38.495391 u2DelayCellOfst[0]=17 cells (5 PI)
8184 22:17:38.498619 u2DelayCellOfst[1]=20 cells (6 PI)
8185 22:17:38.502163 u2DelayCellOfst[2]=13 cells (4 PI)
8186 22:17:38.505451 u2DelayCellOfst[3]=13 cells (4 PI)
8187 22:17:38.508447 u2DelayCellOfst[4]=10 cells (3 PI)
8188 22:17:38.511982 u2DelayCellOfst[5]=0 cells (0 PI)
8189 22:17:38.515087 u2DelayCellOfst[6]=20 cells (6 PI)
8190 22:17:38.518499 u2DelayCellOfst[7]=17 cells (5 PI)
8191 22:17:38.521514 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8192 22:17:38.525101 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
8193 22:17:38.528271 == TX Byte 1 ==
8194 22:17:38.531677 u2DelayCellOfst[8]=3 cells (1 PI)
8195 22:17:38.534860 u2DelayCellOfst[9]=0 cells (0 PI)
8196 22:17:38.538044 u2DelayCellOfst[10]=6 cells (2 PI)
8197 22:17:38.541557 u2DelayCellOfst[11]=6 cells (2 PI)
8198 22:17:38.544649 u2DelayCellOfst[12]=13 cells (4 PI)
8199 22:17:38.548063 u2DelayCellOfst[13]=13 cells (4 PI)
8200 22:17:38.548181 u2DelayCellOfst[14]=13 cells (4 PI)
8201 22:17:38.551245 u2DelayCellOfst[15]=10 cells (3 PI)
8202 22:17:38.557722 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8203 22:17:38.560960 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8204 22:17:38.564256 DramC Write-DBI on
8205 22:17:38.564376 ==
8206 22:17:38.567959 Dram Type= 6, Freq= 0, CH_0, rank 1
8207 22:17:38.571223 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8208 22:17:38.571314 ==
8209 22:17:38.571385
8210 22:17:38.571462
8211 22:17:38.574099 TX Vref Scan disable
8212 22:17:38.574182 == TX Byte 0 ==
8213 22:17:38.580756 Update DQM dly =737 (2 ,6, 33) DQM OEN =(3 ,3)
8214 22:17:38.580850 == TX Byte 1 ==
8215 22:17:38.587441 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
8216 22:17:38.587523 DramC Write-DBI off
8217 22:17:38.587595
8218 22:17:38.587657 [DATLAT]
8219 22:17:38.590870 Freq=1600, CH0 RK1
8220 22:17:38.590966
8221 22:17:38.594310 DATLAT Default: 0xf
8222 22:17:38.594404 0, 0xFFFF, sum = 0
8223 22:17:38.597449 1, 0xFFFF, sum = 0
8224 22:17:38.597557 2, 0xFFFF, sum = 0
8225 22:17:38.600690 3, 0xFFFF, sum = 0
8226 22:17:38.600807 4, 0xFFFF, sum = 0
8227 22:17:38.604166 5, 0xFFFF, sum = 0
8228 22:17:38.604292 6, 0xFFFF, sum = 0
8229 22:17:38.607428 7, 0xFFFF, sum = 0
8230 22:17:38.607511 8, 0xFFFF, sum = 0
8231 22:17:38.610769 9, 0xFFFF, sum = 0
8232 22:17:38.610852 10, 0xFFFF, sum = 0
8233 22:17:38.614219 11, 0xFFFF, sum = 0
8234 22:17:38.614345 12, 0xFFFF, sum = 0
8235 22:17:38.617476 13, 0xFFFF, sum = 0
8236 22:17:38.617558 14, 0x0, sum = 1
8237 22:17:38.620895 15, 0x0, sum = 2
8238 22:17:38.620975 16, 0x0, sum = 3
8239 22:17:38.624150 17, 0x0, sum = 4
8240 22:17:38.624228 best_step = 15
8241 22:17:38.624300
8242 22:17:38.624369 ==
8243 22:17:38.627309 Dram Type= 6, Freq= 0, CH_0, rank 1
8244 22:17:38.630938 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8245 22:17:38.634266 ==
8246 22:17:38.634352 RX Vref Scan: 0
8247 22:17:38.634419
8248 22:17:38.637628 RX Vref 0 -> 0, step: 1
8249 22:17:38.637707
8250 22:17:38.640775 RX Delay 11 -> 252, step: 4
8251 22:17:38.643719 iDelay=191, Bit 0, Center 132 (83 ~ 182) 100
8252 22:17:38.647193 iDelay=191, Bit 1, Center 136 (87 ~ 186) 100
8253 22:17:38.650314 iDelay=191, Bit 2, Center 128 (79 ~ 178) 100
8254 22:17:38.656984 iDelay=191, Bit 3, Center 130 (83 ~ 178) 96
8255 22:17:38.660511 iDelay=191, Bit 4, Center 134 (87 ~ 182) 96
8256 22:17:38.663704 iDelay=191, Bit 5, Center 124 (75 ~ 174) 100
8257 22:17:38.667002 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8258 22:17:38.670125 iDelay=191, Bit 7, Center 138 (87 ~ 190) 104
8259 22:17:38.676844 iDelay=191, Bit 8, Center 116 (67 ~ 166) 100
8260 22:17:38.680272 iDelay=191, Bit 9, Center 110 (59 ~ 162) 104
8261 22:17:38.683500 iDelay=191, Bit 10, Center 124 (75 ~ 174) 100
8262 22:17:38.686688 iDelay=191, Bit 11, Center 120 (71 ~ 170) 100
8263 22:17:38.690022 iDelay=191, Bit 12, Center 126 (75 ~ 178) 104
8264 22:17:38.696942 iDelay=191, Bit 13, Center 128 (79 ~ 178) 100
8265 22:17:38.700201 iDelay=191, Bit 14, Center 132 (79 ~ 186) 108
8266 22:17:38.703488 iDelay=191, Bit 15, Center 128 (75 ~ 182) 108
8267 22:17:38.703565 ==
8268 22:17:38.706661 Dram Type= 6, Freq= 0, CH_0, rank 1
8269 22:17:38.710175 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8270 22:17:38.710264 ==
8271 22:17:38.713083 DQS Delay:
8272 22:17:38.713172 DQS0 = 0, DQS1 = 0
8273 22:17:38.716544 DQM Delay:
8274 22:17:38.716632 DQM0 = 132, DQM1 = 123
8275 22:17:38.719939 DQ Delay:
8276 22:17:38.723343 DQ0 =132, DQ1 =136, DQ2 =128, DQ3 =130
8277 22:17:38.726499 DQ4 =134, DQ5 =124, DQ6 =140, DQ7 =138
8278 22:17:38.729833 DQ8 =116, DQ9 =110, DQ10 =124, DQ11 =120
8279 22:17:38.733247 DQ12 =126, DQ13 =128, DQ14 =132, DQ15 =128
8280 22:17:38.733340
8281 22:17:38.733416
8282 22:17:38.733483
8283 22:17:38.736186 [DramC_TX_OE_Calibration] TA2
8284 22:17:38.739481 Original DQ_B0 (3 6) =30, OEN = 27
8285 22:17:38.743187 Original DQ_B1 (3 6) =30, OEN = 27
8286 22:17:38.746049 24, 0x0, End_B0=24 End_B1=24
8287 22:17:38.746151 25, 0x0, End_B0=25 End_B1=25
8288 22:17:38.749534 26, 0x0, End_B0=26 End_B1=26
8289 22:17:38.752946 27, 0x0, End_B0=27 End_B1=27
8290 22:17:38.756042 28, 0x0, End_B0=28 End_B1=28
8291 22:17:38.756163 29, 0x0, End_B0=29 End_B1=29
8292 22:17:38.759371 30, 0x0, End_B0=30 End_B1=30
8293 22:17:38.762645 31, 0x5151, End_B0=30 End_B1=30
8294 22:17:38.766063 Byte0 end_step=30 best_step=27
8295 22:17:38.769120 Byte1 end_step=30 best_step=27
8296 22:17:38.772519 Byte0 TX OE(2T, 0.5T) = (3, 3)
8297 22:17:38.775785 Byte1 TX OE(2T, 0.5T) = (3, 3)
8298 22:17:38.775865
8299 22:17:38.775938
8300 22:17:38.782721 [DQSOSCAuto] RK1, (LSB)MR18= 0x200d, (MSB)MR19= 0x303, tDQSOscB0 = 403 ps tDQSOscB1 = 393 ps
8301 22:17:38.785872 CH0 RK1: MR19=303, MR18=200D
8302 22:17:38.792198 CH0_RK1: MR19=0x303, MR18=0x200D, DQSOSC=393, MR23=63, INC=23, DEC=15
8303 22:17:38.795579 [RxdqsGatingPostProcess] freq 1600
8304 22:17:38.798825 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8305 22:17:38.802147 best DQS0 dly(2T, 0.5T) = (1, 1)
8306 22:17:38.805448 best DQS1 dly(2T, 0.5T) = (1, 1)
8307 22:17:38.808711 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8308 22:17:38.812288 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8309 22:17:38.815474 best DQS0 dly(2T, 0.5T) = (1, 1)
8310 22:17:38.818822 best DQS1 dly(2T, 0.5T) = (1, 1)
8311 22:17:38.821852 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8312 22:17:38.825182 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8313 22:17:38.828514 Pre-setting of DQS Precalculation
8314 22:17:38.832188 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8315 22:17:38.832303 ==
8316 22:17:38.835255 Dram Type= 6, Freq= 0, CH_1, rank 0
8317 22:17:38.841823 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8318 22:17:38.841913 ==
8319 22:17:38.845190 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8320 22:17:38.848669 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8321 22:17:38.855160 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8322 22:17:38.861298 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8323 22:17:38.869082 [CA 0] Center 40 (11~70) winsize 60
8324 22:17:38.872076 [CA 1] Center 41 (11~71) winsize 61
8325 22:17:38.875772 [CA 2] Center 37 (8~67) winsize 60
8326 22:17:38.878820 [CA 3] Center 36 (7~66) winsize 60
8327 22:17:38.882138 [CA 4] Center 36 (6~66) winsize 61
8328 22:17:38.885505 [CA 5] Center 35 (5~66) winsize 62
8329 22:17:38.885589
8330 22:17:38.889070 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8331 22:17:38.889180
8332 22:17:38.892348 [CATrainingPosCal] consider 1 rank data
8333 22:17:38.895434 u2DelayCellTimex100 = 285/100 ps
8334 22:17:38.898615 CA0 delay=40 (11~70),Diff = 5 PI (17 cell)
8335 22:17:38.905447 CA1 delay=41 (11~71),Diff = 6 PI (20 cell)
8336 22:17:38.908674 CA2 delay=37 (8~67),Diff = 2 PI (6 cell)
8337 22:17:38.911968 CA3 delay=36 (7~66),Diff = 1 PI (3 cell)
8338 22:17:38.915009 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
8339 22:17:38.918599 CA5 delay=35 (5~66),Diff = 0 PI (0 cell)
8340 22:17:38.918706
8341 22:17:38.922018 CA PerBit enable=1, Macro0, CA PI delay=35
8342 22:17:38.922120
8343 22:17:38.925153 [CBTSetCACLKResult] CA Dly = 35
8344 22:17:38.928251 CS Dly: 8 (0~39)
8345 22:17:38.931534 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8346 22:17:38.934861 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8347 22:17:38.934961 ==
8348 22:17:38.938220 Dram Type= 6, Freq= 0, CH_1, rank 1
8349 22:17:38.941560 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8350 22:17:38.945099 ==
8351 22:17:38.948269 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8352 22:17:38.951541 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8353 22:17:38.958328 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8354 22:17:38.964771 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8355 22:17:38.972125 [CA 0] Center 42 (12~72) winsize 61
8356 22:17:38.975207 [CA 1] Center 41 (11~71) winsize 61
8357 22:17:38.978548 [CA 2] Center 37 (8~67) winsize 60
8358 22:17:38.981976 [CA 3] Center 37 (8~66) winsize 59
8359 22:17:38.985005 [CA 4] Center 37 (8~67) winsize 60
8360 22:17:38.988317 [CA 5] Center 36 (7~66) winsize 60
8361 22:17:38.988403
8362 22:17:38.991672 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8363 22:17:38.991754
8364 22:17:38.998185 [CATrainingPosCal] consider 2 rank data
8365 22:17:38.998267 u2DelayCellTimex100 = 285/100 ps
8366 22:17:39.004824 CA0 delay=41 (12~70),Diff = 5 PI (17 cell)
8367 22:17:39.008619 CA1 delay=41 (11~71),Diff = 5 PI (17 cell)
8368 22:17:39.011828 CA2 delay=37 (8~67),Diff = 1 PI (3 cell)
8369 22:17:39.014724 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8370 22:17:39.018389 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
8371 22:17:39.021362 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8372 22:17:39.021445
8373 22:17:39.024581 CA PerBit enable=1, Macro0, CA PI delay=36
8374 22:17:39.024692
8375 22:17:39.028174 [CBTSetCACLKResult] CA Dly = 36
8376 22:17:39.031079 CS Dly: 9 (0~42)
8377 22:17:39.034828 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8378 22:17:39.038102 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8379 22:17:39.038212
8380 22:17:39.041350 ----->DramcWriteLeveling(PI) begin...
8381 22:17:39.041455 ==
8382 22:17:39.044604 Dram Type= 6, Freq= 0, CH_1, rank 0
8383 22:17:39.051010 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8384 22:17:39.051117 ==
8385 22:17:39.054220 Write leveling (Byte 0): 24 => 24
8386 22:17:39.057658 Write leveling (Byte 1): 28 => 28
8387 22:17:39.060690 DramcWriteLeveling(PI) end<-----
8388 22:17:39.060779
8389 22:17:39.060875 ==
8390 22:17:39.064292 Dram Type= 6, Freq= 0, CH_1, rank 0
8391 22:17:39.067997 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8392 22:17:39.068111 ==
8393 22:17:39.070982 [Gating] SW mode calibration
8394 22:17:39.077320 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8395 22:17:39.081045 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8396 22:17:39.087327 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8397 22:17:39.090775 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8398 22:17:39.093951 1 4 8 | B1->B0 | 2b2b 2f2f | 1 1 | (1 1) (1 1)
8399 22:17:39.100889 1 4 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8400 22:17:39.104092 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8401 22:17:39.106978 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8402 22:17:39.113766 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8403 22:17:39.117045 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8404 22:17:39.120228 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8405 22:17:39.126628 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8406 22:17:39.130461 1 5 8 | B1->B0 | 2a2a 2727 | 0 0 | (0 1) (1 0)
8407 22:17:39.133438 1 5 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8408 22:17:39.140105 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8409 22:17:39.143237 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8410 22:17:39.147022 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8411 22:17:39.153335 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8412 22:17:39.156571 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8413 22:17:39.159805 1 6 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8414 22:17:39.166800 1 6 8 | B1->B0 | 3b3b 4242 | 0 0 | (0 0) (0 0)
8415 22:17:39.169746 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8416 22:17:39.173204 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8417 22:17:39.179706 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8418 22:17:39.182874 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8419 22:17:39.186394 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8420 22:17:39.193053 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8421 22:17:39.196139 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8422 22:17:39.199402 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8423 22:17:39.206200 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8424 22:17:39.209559 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8425 22:17:39.212725 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8426 22:17:39.218967 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8427 22:17:39.222189 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8428 22:17:39.225848 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8429 22:17:39.232176 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8430 22:17:39.235385 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8431 22:17:39.238947 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8432 22:17:39.245507 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8433 22:17:39.248631 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8434 22:17:39.251965 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8435 22:17:39.258676 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8436 22:17:39.261800 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8437 22:17:39.265562 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8438 22:17:39.271625 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8439 22:17:39.275111 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8440 22:17:39.278630 Total UI for P1: 0, mck2ui 16
8441 22:17:39.281762 best dqsien dly found for B0: ( 1, 9, 6)
8442 22:17:39.285021 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8443 22:17:39.288220 Total UI for P1: 0, mck2ui 16
8444 22:17:39.291900 best dqsien dly found for B1: ( 1, 9, 10)
8445 22:17:39.295066 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8446 22:17:39.301495 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8447 22:17:39.301577
8448 22:17:39.304620 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8449 22:17:39.308467 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8450 22:17:39.311589 [Gating] SW calibration Done
8451 22:17:39.311674 ==
8452 22:17:39.314611 Dram Type= 6, Freq= 0, CH_1, rank 0
8453 22:17:39.317832 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8454 22:17:39.317953 ==
8455 22:17:39.321542 RX Vref Scan: 0
8456 22:17:39.321623
8457 22:17:39.321688 RX Vref 0 -> 0, step: 1
8458 22:17:39.321749
8459 22:17:39.324714 RX Delay 0 -> 252, step: 8
8460 22:17:39.328030 iDelay=200, Bit 0, Center 139 (96 ~ 183) 88
8461 22:17:39.331194 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8462 22:17:39.337910 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8463 22:17:39.341052 iDelay=200, Bit 3, Center 139 (88 ~ 191) 104
8464 22:17:39.344219 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8465 22:17:39.347632 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8466 22:17:39.351030 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8467 22:17:39.357591 iDelay=200, Bit 7, Center 135 (88 ~ 183) 96
8468 22:17:39.361016 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8469 22:17:39.364306 iDelay=200, Bit 9, Center 119 (72 ~ 167) 96
8470 22:17:39.367376 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8471 22:17:39.371135 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8472 22:17:39.377354 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8473 22:17:39.380826 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
8474 22:17:39.384259 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8475 22:17:39.387286 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8476 22:17:39.387368 ==
8477 22:17:39.390791 Dram Type= 6, Freq= 0, CH_1, rank 0
8478 22:17:39.397216 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8479 22:17:39.397320 ==
8480 22:17:39.397387 DQS Delay:
8481 22:17:39.400843 DQS0 = 0, DQS1 = 0
8482 22:17:39.400926 DQM Delay:
8483 22:17:39.403869 DQM0 = 137, DQM1 = 131
8484 22:17:39.403960 DQ Delay:
8485 22:17:39.407252 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =139
8486 22:17:39.410644 DQ4 =135, DQ5 =147, DQ6 =147, DQ7 =135
8487 22:17:39.414204 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =127
8488 22:17:39.417318 DQ12 =139, DQ13 =139, DQ14 =139, DQ15 =139
8489 22:17:39.417403
8490 22:17:39.417471
8491 22:17:39.417532 ==
8492 22:17:39.420312 Dram Type= 6, Freq= 0, CH_1, rank 0
8493 22:17:39.426829 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8494 22:17:39.426911 ==
8495 22:17:39.426977
8496 22:17:39.427039
8497 22:17:39.427097 TX Vref Scan disable
8498 22:17:39.430198 == TX Byte 0 ==
8499 22:17:39.433932 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8500 22:17:39.440175 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8501 22:17:39.440260 == TX Byte 1 ==
8502 22:17:39.443792 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8503 22:17:39.449989 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8504 22:17:39.450073 ==
8505 22:17:39.453561 Dram Type= 6, Freq= 0, CH_1, rank 0
8506 22:17:39.456670 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8507 22:17:39.456754 ==
8508 22:17:39.469168
8509 22:17:39.472248 TX Vref early break, caculate TX vref
8510 22:17:39.475577 TX Vref=16, minBit 10, minWin=21, winSum=369
8511 22:17:39.479039 TX Vref=18, minBit 10, minWin=22, winSum=380
8512 22:17:39.482323 TX Vref=20, minBit 10, minWin=23, winSum=389
8513 22:17:39.485421 TX Vref=22, minBit 10, minWin=23, winSum=400
8514 22:17:39.492187 TX Vref=24, minBit 10, minWin=23, winSum=412
8515 22:17:39.495400 TX Vref=26, minBit 10, minWin=24, winSum=419
8516 22:17:39.499037 TX Vref=28, minBit 13, minWin=24, winSum=415
8517 22:17:39.502126 TX Vref=30, minBit 9, minWin=24, winSum=406
8518 22:17:39.505666 TX Vref=32, minBit 13, minWin=23, winSum=398
8519 22:17:39.511914 TX Vref=34, minBit 14, minWin=22, winSum=387
8520 22:17:39.515574 [TxChooseVref] Worse bit 10, Min win 24, Win sum 419, Final Vref 26
8521 22:17:39.515677
8522 22:17:39.518675 Final TX Range 0 Vref 26
8523 22:17:39.518773
8524 22:17:39.518867 ==
8525 22:17:39.522078 Dram Type= 6, Freq= 0, CH_1, rank 0
8526 22:17:39.525584 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8527 22:17:39.528910 ==
8528 22:17:39.529035
8529 22:17:39.529165
8530 22:17:39.529278 TX Vref Scan disable
8531 22:17:39.535292 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8532 22:17:39.535390 == TX Byte 0 ==
8533 22:17:39.538541 u2DelayCellOfst[0]=13 cells (4 PI)
8534 22:17:39.541784 u2DelayCellOfst[1]=10 cells (3 PI)
8535 22:17:39.545523 u2DelayCellOfst[2]=0 cells (0 PI)
8536 22:17:39.548715 u2DelayCellOfst[3]=3 cells (1 PI)
8537 22:17:39.551804 u2DelayCellOfst[4]=6 cells (2 PI)
8538 22:17:39.555475 u2DelayCellOfst[5]=17 cells (5 PI)
8539 22:17:39.558406 u2DelayCellOfst[6]=17 cells (5 PI)
8540 22:17:39.561675 u2DelayCellOfst[7]=6 cells (2 PI)
8541 22:17:39.565378 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8542 22:17:39.568319 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8543 22:17:39.571858 == TX Byte 1 ==
8544 22:17:39.575216 u2DelayCellOfst[8]=0 cells (0 PI)
8545 22:17:39.578486 u2DelayCellOfst[9]=3 cells (1 PI)
8546 22:17:39.581510 u2DelayCellOfst[10]=10 cells (3 PI)
8547 22:17:39.584632 u2DelayCellOfst[11]=3 cells (1 PI)
8548 22:17:39.588240 u2DelayCellOfst[12]=17 cells (5 PI)
8549 22:17:39.588325 u2DelayCellOfst[13]=17 cells (5 PI)
8550 22:17:39.591554 u2DelayCellOfst[14]=20 cells (6 PI)
8551 22:17:39.595018 u2DelayCellOfst[15]=17 cells (5 PI)
8552 22:17:39.601347 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8553 22:17:39.604511 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8554 22:17:39.608004 DramC Write-DBI on
8555 22:17:39.608089 ==
8556 22:17:39.611427 Dram Type= 6, Freq= 0, CH_1, rank 0
8557 22:17:39.614703 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8558 22:17:39.614788 ==
8559 22:17:39.614854
8560 22:17:39.614916
8561 22:17:39.617848 TX Vref Scan disable
8562 22:17:39.617932 == TX Byte 0 ==
8563 22:17:39.624632 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8564 22:17:39.624745 == TX Byte 1 ==
8565 22:17:39.627713 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8566 22:17:39.631021 DramC Write-DBI off
8567 22:17:39.631125
8568 22:17:39.631221 [DATLAT]
8569 22:17:39.634547 Freq=1600, CH1 RK0
8570 22:17:39.634652
8571 22:17:39.634746 DATLAT Default: 0xf
8572 22:17:39.637775 0, 0xFFFF, sum = 0
8573 22:17:39.637882 1, 0xFFFF, sum = 0
8574 22:17:39.641031 2, 0xFFFF, sum = 0
8575 22:17:39.644131 3, 0xFFFF, sum = 0
8576 22:17:39.644234 4, 0xFFFF, sum = 0
8577 22:17:39.647382 5, 0xFFFF, sum = 0
8578 22:17:39.647487 6, 0xFFFF, sum = 0
8579 22:17:39.650786 7, 0xFFFF, sum = 0
8580 22:17:39.650896 8, 0xFFFF, sum = 0
8581 22:17:39.653982 9, 0xFFFF, sum = 0
8582 22:17:39.654089 10, 0xFFFF, sum = 0
8583 22:17:39.657371 11, 0xFFFF, sum = 0
8584 22:17:39.657481 12, 0xFFFF, sum = 0
8585 22:17:39.660524 13, 0xFFFF, sum = 0
8586 22:17:39.660628 14, 0x0, sum = 1
8587 22:17:39.664049 15, 0x0, sum = 2
8588 22:17:39.664130 16, 0x0, sum = 3
8589 22:17:39.667267 17, 0x0, sum = 4
8590 22:17:39.667374 best_step = 15
8591 22:17:39.667470
8592 22:17:39.667560 ==
8593 22:17:39.670406 Dram Type= 6, Freq= 0, CH_1, rank 0
8594 22:17:39.677110 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8595 22:17:39.677215 ==
8596 22:17:39.677308 RX Vref Scan: 1
8597 22:17:39.677400
8598 22:17:39.680397 Set Vref Range= 24 -> 127
8599 22:17:39.680494
8600 22:17:39.683588 RX Vref 24 -> 127, step: 1
8601 22:17:39.683688
8602 22:17:39.683784 RX Delay 19 -> 252, step: 4
8603 22:17:39.683875
8604 22:17:39.687254 Set Vref, RX VrefLevel [Byte0]: 24
8605 22:17:39.690207 [Byte1]: 24
8606 22:17:39.694140
8607 22:17:39.694239 Set Vref, RX VrefLevel [Byte0]: 25
8608 22:17:39.697553 [Byte1]: 25
8609 22:17:39.701695
8610 22:17:39.701794 Set Vref, RX VrefLevel [Byte0]: 26
8611 22:17:39.705302 [Byte1]: 26
8612 22:17:39.709330
8613 22:17:39.709429 Set Vref, RX VrefLevel [Byte0]: 27
8614 22:17:39.712967 [Byte1]: 27
8615 22:17:39.717039
8616 22:17:39.717140 Set Vref, RX VrefLevel [Byte0]: 28
8617 22:17:39.720260 [Byte1]: 28
8618 22:17:39.724898
8619 22:17:39.724999 Set Vref, RX VrefLevel [Byte0]: 29
8620 22:17:39.727976 [Byte1]: 29
8621 22:17:39.732242
8622 22:17:39.732339 Set Vref, RX VrefLevel [Byte0]: 30
8623 22:17:39.735281 [Byte1]: 30
8624 22:17:39.740031
8625 22:17:39.740129 Set Vref, RX VrefLevel [Byte0]: 31
8626 22:17:39.742989 [Byte1]: 31
8627 22:17:39.747106
8628 22:17:39.747204 Set Vref, RX VrefLevel [Byte0]: 32
8629 22:17:39.750748 [Byte1]: 32
8630 22:17:39.754752
8631 22:17:39.754852 Set Vref, RX VrefLevel [Byte0]: 33
8632 22:17:39.757976 [Byte1]: 33
8633 22:17:39.762331
8634 22:17:39.762432 Set Vref, RX VrefLevel [Byte0]: 34
8635 22:17:39.765879 [Byte1]: 34
8636 22:17:39.769923
8637 22:17:39.770000 Set Vref, RX VrefLevel [Byte0]: 35
8638 22:17:39.773586 [Byte1]: 35
8639 22:17:39.777419
8640 22:17:39.777495 Set Vref, RX VrefLevel [Byte0]: 36
8641 22:17:39.781230 [Byte1]: 36
8642 22:17:39.785241
8643 22:17:39.785316 Set Vref, RX VrefLevel [Byte0]: 37
8644 22:17:39.788493 [Byte1]: 37
8645 22:17:39.793025
8646 22:17:39.793106 Set Vref, RX VrefLevel [Byte0]: 38
8647 22:17:39.796096 [Byte1]: 38
8648 22:17:39.800501
8649 22:17:39.800601 Set Vref, RX VrefLevel [Byte0]: 39
8650 22:17:39.803453 [Byte1]: 39
8651 22:17:39.808158
8652 22:17:39.808273 Set Vref, RX VrefLevel [Byte0]: 40
8653 22:17:39.811384 [Byte1]: 40
8654 22:17:39.815581
8655 22:17:39.815683 Set Vref, RX VrefLevel [Byte0]: 41
8656 22:17:39.819155 [Byte1]: 41
8657 22:17:39.823167
8658 22:17:39.823274 Set Vref, RX VrefLevel [Byte0]: 42
8659 22:17:39.826163 [Byte1]: 42
8660 22:17:39.830498
8661 22:17:39.830601 Set Vref, RX VrefLevel [Byte0]: 43
8662 22:17:39.833869 [Byte1]: 43
8663 22:17:39.838141
8664 22:17:39.838242 Set Vref, RX VrefLevel [Byte0]: 44
8665 22:17:39.841466 [Byte1]: 44
8666 22:17:39.845625
8667 22:17:39.845725 Set Vref, RX VrefLevel [Byte0]: 45
8668 22:17:39.849141 [Byte1]: 45
8669 22:17:39.853374
8670 22:17:39.853450 Set Vref, RX VrefLevel [Byte0]: 46
8671 22:17:39.856869 [Byte1]: 46
8672 22:17:39.860810
8673 22:17:39.860912 Set Vref, RX VrefLevel [Byte0]: 47
8674 22:17:39.863995 [Byte1]: 47
8675 22:17:39.868828
8676 22:17:39.868906 Set Vref, RX VrefLevel [Byte0]: 48
8677 22:17:39.871875 [Byte1]: 48
8678 22:17:39.876071
8679 22:17:39.876174 Set Vref, RX VrefLevel [Byte0]: 49
8680 22:17:39.879717 [Byte1]: 49
8681 22:17:39.883583
8682 22:17:39.883688 Set Vref, RX VrefLevel [Byte0]: 50
8683 22:17:39.886905 [Byte1]: 50
8684 22:17:39.891559
8685 22:17:39.891658 Set Vref, RX VrefLevel [Byte0]: 51
8686 22:17:39.894681 [Byte1]: 51
8687 22:17:39.898979
8688 22:17:39.899086 Set Vref, RX VrefLevel [Byte0]: 52
8689 22:17:39.902005 [Byte1]: 52
8690 22:17:39.906366
8691 22:17:39.906470 Set Vref, RX VrefLevel [Byte0]: 53
8692 22:17:39.909802 [Byte1]: 53
8693 22:17:39.913838
8694 22:17:39.913940 Set Vref, RX VrefLevel [Byte0]: 54
8695 22:17:39.917074 [Byte1]: 54
8696 22:17:39.921664
8697 22:17:39.921770 Set Vref, RX VrefLevel [Byte0]: 55
8698 22:17:39.924597 [Byte1]: 55
8699 22:17:39.928847
8700 22:17:39.928950 Set Vref, RX VrefLevel [Byte0]: 56
8701 22:17:39.932492 [Byte1]: 56
8702 22:17:39.936545
8703 22:17:39.936649 Set Vref, RX VrefLevel [Byte0]: 57
8704 22:17:39.939753 [Byte1]: 57
8705 22:17:39.944178
8706 22:17:39.944283 Set Vref, RX VrefLevel [Byte0]: 58
8707 22:17:39.947496 [Byte1]: 58
8708 22:17:39.952026
8709 22:17:39.952137 Set Vref, RX VrefLevel [Byte0]: 59
8710 22:17:39.955103 [Byte1]: 59
8711 22:17:39.959166
8712 22:17:39.959270 Set Vref, RX VrefLevel [Byte0]: 60
8713 22:17:39.962581 [Byte1]: 60
8714 22:17:39.966825
8715 22:17:39.966906 Set Vref, RX VrefLevel [Byte0]: 61
8716 22:17:39.970351 [Byte1]: 61
8717 22:17:39.974702
8718 22:17:39.974809 Set Vref, RX VrefLevel [Byte0]: 62
8719 22:17:39.978017 [Byte1]: 62
8720 22:17:39.982048
8721 22:17:39.982151 Set Vref, RX VrefLevel [Byte0]: 63
8722 22:17:39.985170 [Byte1]: 63
8723 22:17:39.989569
8724 22:17:39.989650 Set Vref, RX VrefLevel [Byte0]: 64
8725 22:17:39.992743 [Byte1]: 64
8726 22:17:39.997230
8727 22:17:39.997311 Set Vref, RX VrefLevel [Byte0]: 65
8728 22:17:40.000264 [Byte1]: 65
8729 22:17:40.004878
8730 22:17:40.004995 Set Vref, RX VrefLevel [Byte0]: 66
8731 22:17:40.007983 [Byte1]: 66
8732 22:17:40.012421
8733 22:17:40.015460 Set Vref, RX VrefLevel [Byte0]: 67
8734 22:17:40.018531 [Byte1]: 67
8735 22:17:40.018638
8736 22:17:40.022245 Set Vref, RX VrefLevel [Byte0]: 68
8737 22:17:40.025389 [Byte1]: 68
8738 22:17:40.025500
8739 22:17:40.028738 Set Vref, RX VrefLevel [Byte0]: 69
8740 22:17:40.032244 [Byte1]: 69
8741 22:17:40.032349
8742 22:17:40.035543 Set Vref, RX VrefLevel [Byte0]: 70
8743 22:17:40.038540 [Byte1]: 70
8744 22:17:40.042813
8745 22:17:40.042932 Set Vref, RX VrefLevel [Byte0]: 71
8746 22:17:40.048999 [Byte1]: 71
8747 22:17:40.049088
8748 22:17:40.052249 Set Vref, RX VrefLevel [Byte0]: 72
8749 22:17:40.055841 [Byte1]: 72
8750 22:17:40.055953
8751 22:17:40.059274 Set Vref, RX VrefLevel [Byte0]: 73
8752 22:17:40.062422 [Byte1]: 73
8753 22:17:40.062534
8754 22:17:40.065585 Set Vref, RX VrefLevel [Byte0]: 74
8755 22:17:40.068883 [Byte1]: 74
8756 22:17:40.073094
8757 22:17:40.073207 Set Vref, RX VrefLevel [Byte0]: 75
8758 22:17:40.076057 [Byte1]: 75
8759 22:17:40.080534
8760 22:17:40.080648 Set Vref, RX VrefLevel [Byte0]: 76
8761 22:17:40.083631 [Byte1]: 76
8762 22:17:40.088208
8763 22:17:40.088314 Set Vref, RX VrefLevel [Byte0]: 77
8764 22:17:40.091619 [Byte1]: 77
8765 22:17:40.095426
8766 22:17:40.095530 Set Vref, RX VrefLevel [Byte0]: 78
8767 22:17:40.099062 [Byte1]: 78
8768 22:17:40.103167
8769 22:17:40.103283 Final RX Vref Byte 0 = 55 to rank0
8770 22:17:40.106662 Final RX Vref Byte 1 = 62 to rank0
8771 22:17:40.110147 Final RX Vref Byte 0 = 55 to rank1
8772 22:17:40.113237 Final RX Vref Byte 1 = 62 to rank1==
8773 22:17:40.116428 Dram Type= 6, Freq= 0, CH_1, rank 0
8774 22:17:40.123248 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8775 22:17:40.123341 ==
8776 22:17:40.123411 DQS Delay:
8777 22:17:40.123478 DQS0 = 0, DQS1 = 0
8778 22:17:40.126387 DQM Delay:
8779 22:17:40.126472 DQM0 = 133, DQM1 = 129
8780 22:17:40.129819 DQ Delay:
8781 22:17:40.132796 DQ0 =136, DQ1 =128, DQ2 =122, DQ3 =132
8782 22:17:40.136105 DQ4 =132, DQ5 =144, DQ6 =142, DQ7 =130
8783 22:17:40.139747 DQ8 =116, DQ9 =118, DQ10 =134, DQ11 =122
8784 22:17:40.143093 DQ12 =138, DQ13 =134, DQ14 =136, DQ15 =136
8785 22:17:40.143168
8786 22:17:40.143236
8787 22:17:40.143306
8788 22:17:40.145908 [DramC_TX_OE_Calibration] TA2
8789 22:17:40.149565 Original DQ_B0 (3 6) =30, OEN = 27
8790 22:17:40.152605 Original DQ_B1 (3 6) =30, OEN = 27
8791 22:17:40.156226 24, 0x0, End_B0=24 End_B1=24
8792 22:17:40.156317 25, 0x0, End_B0=25 End_B1=25
8793 22:17:40.159365 26, 0x0, End_B0=26 End_B1=26
8794 22:17:40.162606 27, 0x0, End_B0=27 End_B1=27
8795 22:17:40.165919 28, 0x0, End_B0=28 End_B1=28
8796 22:17:40.169443 29, 0x0, End_B0=29 End_B1=29
8797 22:17:40.169529 30, 0x0, End_B0=30 End_B1=30
8798 22:17:40.172979 31, 0x4141, End_B0=30 End_B1=30
8799 22:17:40.176231 Byte0 end_step=30 best_step=27
8800 22:17:40.179215 Byte1 end_step=30 best_step=27
8801 22:17:40.182592 Byte0 TX OE(2T, 0.5T) = (3, 3)
8802 22:17:40.185921 Byte1 TX OE(2T, 0.5T) = (3, 3)
8803 22:17:40.186005
8804 22:17:40.186072
8805 22:17:40.192657 [DQSOSCAuto] RK0, (LSB)MR18= 0x1a28, (MSB)MR19= 0x303, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps
8806 22:17:40.196281 CH1 RK0: MR19=303, MR18=1A28
8807 22:17:40.202658 CH1_RK0: MR19=0x303, MR18=0x1A28, DQSOSC=389, MR23=63, INC=24, DEC=16
8808 22:17:40.202742
8809 22:17:40.205862 ----->DramcWriteLeveling(PI) begin...
8810 22:17:40.205947 ==
8811 22:17:40.209363 Dram Type= 6, Freq= 0, CH_1, rank 1
8812 22:17:40.212594 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8813 22:17:40.212678 ==
8814 22:17:40.215764 Write leveling (Byte 0): 23 => 23
8815 22:17:40.219252 Write leveling (Byte 1): 28 => 28
8816 22:17:40.222322 DramcWriteLeveling(PI) end<-----
8817 22:17:40.222406
8818 22:17:40.222472 ==
8819 22:17:40.225691 Dram Type= 6, Freq= 0, CH_1, rank 1
8820 22:17:40.229296 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8821 22:17:40.229381 ==
8822 22:17:40.232246 [Gating] SW mode calibration
8823 22:17:40.239117 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8824 22:17:40.245908 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8825 22:17:40.249234 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8826 22:17:40.255417 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
8827 22:17:40.258805 1 4 8 | B1->B0 | 3333 2323 | 0 0 | (0 0) (0 0)
8828 22:17:40.262282 1 4 12 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
8829 22:17:40.268711 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8830 22:17:40.272364 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8831 22:17:40.275437 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8832 22:17:40.282384 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8833 22:17:40.285245 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8834 22:17:40.288976 1 5 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 0)
8835 22:17:40.295443 1 5 8 | B1->B0 | 2525 3434 | 0 1 | (1 0) (1 0)
8836 22:17:40.298921 1 5 12 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (1 0)
8837 22:17:40.301750 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8838 22:17:40.308699 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8839 22:17:40.312242 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8840 22:17:40.315250 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8841 22:17:40.318699 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8842 22:17:40.325142 1 6 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8843 22:17:40.328352 1 6 8 | B1->B0 | 4141 2323 | 1 0 | (0 0) (0 0)
8844 22:17:40.331725 1 6 12 | B1->B0 | 4646 3939 | 0 1 | (0 0) (0 0)
8845 22:17:40.338321 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8846 22:17:40.341498 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8847 22:17:40.344965 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8848 22:17:40.351780 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8849 22:17:40.355016 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8850 22:17:40.357946 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8851 22:17:40.364695 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8852 22:17:40.367879 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8853 22:17:40.371116 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8854 22:17:40.377864 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8855 22:17:40.381229 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8856 22:17:40.384484 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8857 22:17:40.391108 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8858 22:17:40.394364 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8859 22:17:40.397482 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8860 22:17:40.404175 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8861 22:17:40.407375 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8862 22:17:40.410748 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8863 22:17:40.417239 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8864 22:17:40.420639 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8865 22:17:40.423679 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8866 22:17:40.430339 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8867 22:17:40.433625 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8868 22:17:40.437239 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8869 22:17:40.443716 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8870 22:17:40.446847 Total UI for P1: 0, mck2ui 16
8871 22:17:40.450061 best dqsien dly found for B0: ( 1, 9, 10)
8872 22:17:40.453356 Total UI for P1: 0, mck2ui 16
8873 22:17:40.457003 best dqsien dly found for B1: ( 1, 9, 10)
8874 22:17:40.460355 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8875 22:17:40.463693 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8876 22:17:40.463778
8877 22:17:40.466517 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8878 22:17:40.469809 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8879 22:17:40.473098 [Gating] SW calibration Done
8880 22:17:40.473184 ==
8881 22:17:40.476694 Dram Type= 6, Freq= 0, CH_1, rank 1
8882 22:17:40.479553 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8883 22:17:40.483219 ==
8884 22:17:40.483296 RX Vref Scan: 0
8885 22:17:40.483361
8886 22:17:40.486207 RX Vref 0 -> 0, step: 1
8887 22:17:40.486285
8888 22:17:40.486350 RX Delay 0 -> 252, step: 8
8889 22:17:40.493262 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8890 22:17:40.496303 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8891 22:17:40.499557 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8892 22:17:40.502824 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8893 22:17:40.506303 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8894 22:17:40.512878 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8895 22:17:40.516009 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
8896 22:17:40.519286 iDelay=200, Bit 7, Center 139 (88 ~ 191) 104
8897 22:17:40.522849 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8898 22:17:40.529269 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8899 22:17:40.532745 iDelay=200, Bit 10, Center 135 (80 ~ 191) 112
8900 22:17:40.535891 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8901 22:17:40.539449 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8902 22:17:40.542649 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8903 22:17:40.549118 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8904 22:17:40.552329 iDelay=200, Bit 15, Center 143 (88 ~ 199) 112
8905 22:17:40.552402 ==
8906 22:17:40.555748 Dram Type= 6, Freq= 0, CH_1, rank 1
8907 22:17:40.559260 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8908 22:17:40.559337 ==
8909 22:17:40.562309 DQS Delay:
8910 22:17:40.562391 DQS0 = 0, DQS1 = 0
8911 22:17:40.562457 DQM Delay:
8912 22:17:40.565771 DQM0 = 137, DQM1 = 131
8913 22:17:40.565889 DQ Delay:
8914 22:17:40.568731 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8915 22:17:40.572124 DQ4 =139, DQ5 =147, DQ6 =139, DQ7 =139
8916 22:17:40.578916 DQ8 =115, DQ9 =119, DQ10 =135, DQ11 =127
8917 22:17:40.582070 DQ12 =135, DQ13 =139, DQ14 =135, DQ15 =143
8918 22:17:40.582166
8919 22:17:40.582246
8920 22:17:40.582306 ==
8921 22:17:40.585680 Dram Type= 6, Freq= 0, CH_1, rank 1
8922 22:17:40.588595 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8923 22:17:40.588678 ==
8924 22:17:40.588757
8925 22:17:40.588857
8926 22:17:40.592295 TX Vref Scan disable
8927 22:17:40.592403 == TX Byte 0 ==
8928 22:17:40.598890 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8929 22:17:40.602359 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8930 22:17:40.602462 == TX Byte 1 ==
8931 22:17:40.608683 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8932 22:17:40.612400 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8933 22:17:40.612485 ==
8934 22:17:40.615664 Dram Type= 6, Freq= 0, CH_1, rank 1
8935 22:17:40.619022 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8936 22:17:40.619116 ==
8937 22:17:40.632999
8938 22:17:40.636020 TX Vref early break, caculate TX vref
8939 22:17:40.639623 TX Vref=16, minBit 9, minWin=22, winSum=382
8940 22:17:40.642652 TX Vref=18, minBit 9, minWin=23, winSum=392
8941 22:17:40.646014 TX Vref=20, minBit 9, minWin=23, winSum=397
8942 22:17:40.649414 TX Vref=22, minBit 14, minWin=23, winSum=406
8943 22:17:40.656162 TX Vref=24, minBit 13, minWin=24, winSum=414
8944 22:17:40.659429 TX Vref=26, minBit 10, minWin=24, winSum=423
8945 22:17:40.662498 TX Vref=28, minBit 10, minWin=24, winSum=415
8946 22:17:40.665820 TX Vref=30, minBit 9, minWin=24, winSum=412
8947 22:17:40.669270 TX Vref=32, minBit 0, minWin=24, winSum=405
8948 22:17:40.672406 TX Vref=34, minBit 10, minWin=22, winSum=393
8949 22:17:40.679206 [TxChooseVref] Worse bit 10, Min win 24, Win sum 423, Final Vref 26
8950 22:17:40.679289
8951 22:17:40.682617 Final TX Range 0 Vref 26
8952 22:17:40.682696
8953 22:17:40.682779 ==
8954 22:17:40.685830 Dram Type= 6, Freq= 0, CH_1, rank 1
8955 22:17:40.689051 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8956 22:17:40.689137 ==
8957 22:17:40.689219
8958 22:17:40.692551
8959 22:17:40.692635 TX Vref Scan disable
8960 22:17:40.699031 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8961 22:17:40.699120 == TX Byte 0 ==
8962 22:17:40.702507 u2DelayCellOfst[0]=17 cells (5 PI)
8963 22:17:40.705583 u2DelayCellOfst[1]=6 cells (2 PI)
8964 22:17:40.708829 u2DelayCellOfst[2]=0 cells (0 PI)
8965 22:17:40.712549 u2DelayCellOfst[3]=3 cells (1 PI)
8966 22:17:40.715331 u2DelayCellOfst[4]=6 cells (2 PI)
8967 22:17:40.719032 u2DelayCellOfst[5]=17 cells (5 PI)
8968 22:17:40.722160 u2DelayCellOfst[6]=17 cells (5 PI)
8969 22:17:40.725444 u2DelayCellOfst[7]=3 cells (1 PI)
8970 22:17:40.728741 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8971 22:17:40.731838 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8972 22:17:40.735175 == TX Byte 1 ==
8973 22:17:40.738369 u2DelayCellOfst[8]=0 cells (0 PI)
8974 22:17:40.741637 u2DelayCellOfst[9]=3 cells (1 PI)
8975 22:17:40.745232 u2DelayCellOfst[10]=10 cells (3 PI)
8976 22:17:40.745310 u2DelayCellOfst[11]=6 cells (2 PI)
8977 22:17:40.748318 u2DelayCellOfst[12]=13 cells (4 PI)
8978 22:17:40.752086 u2DelayCellOfst[13]=17 cells (5 PI)
8979 22:17:40.755120 u2DelayCellOfst[14]=17 cells (5 PI)
8980 22:17:40.758410 u2DelayCellOfst[15]=20 cells (6 PI)
8981 22:17:40.765141 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8982 22:17:40.768594 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8983 22:17:40.768669 DramC Write-DBI on
8984 22:17:40.771754 ==
8985 22:17:40.771838 Dram Type= 6, Freq= 0, CH_1, rank 1
8986 22:17:40.778364 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8987 22:17:40.778449 ==
8988 22:17:40.778515
8989 22:17:40.778577
8990 22:17:40.781339 TX Vref Scan disable
8991 22:17:40.781427 == TX Byte 0 ==
8992 22:17:40.787890 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
8993 22:17:40.787974 == TX Byte 1 ==
8994 22:17:40.791669 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8995 22:17:40.794820 DramC Write-DBI off
8996 22:17:40.794904
8997 22:17:40.794971 [DATLAT]
8998 22:17:40.798181 Freq=1600, CH1 RK1
8999 22:17:40.798265
9000 22:17:40.798332 DATLAT Default: 0xf
9001 22:17:40.801507 0, 0xFFFF, sum = 0
9002 22:17:40.801592 1, 0xFFFF, sum = 0
9003 22:17:40.804566 2, 0xFFFF, sum = 0
9004 22:17:40.804651 3, 0xFFFF, sum = 0
9005 22:17:40.807935 4, 0xFFFF, sum = 0
9006 22:17:40.808020 5, 0xFFFF, sum = 0
9007 22:17:40.811243 6, 0xFFFF, sum = 0
9008 22:17:40.811328 7, 0xFFFF, sum = 0
9009 22:17:40.814625 8, 0xFFFF, sum = 0
9010 22:17:40.817680 9, 0xFFFF, sum = 0
9011 22:17:40.817761 10, 0xFFFF, sum = 0
9012 22:17:40.820956 11, 0xFFFF, sum = 0
9013 22:17:40.821070 12, 0xFFFF, sum = 0
9014 22:17:40.824283 13, 0xFFFF, sum = 0
9015 22:17:40.824367 14, 0x0, sum = 1
9016 22:17:40.827905 15, 0x0, sum = 2
9017 22:17:40.828021 16, 0x0, sum = 3
9018 22:17:40.831181 17, 0x0, sum = 4
9019 22:17:40.831288 best_step = 15
9020 22:17:40.831385
9021 22:17:40.831477 ==
9022 22:17:40.834251 Dram Type= 6, Freq= 0, CH_1, rank 1
9023 22:17:40.837660 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9024 22:17:40.840666 ==
9025 22:17:40.840788 RX Vref Scan: 0
9026 22:17:40.840865
9027 22:17:40.844014 RX Vref 0 -> 0, step: 1
9028 22:17:40.844103
9029 22:17:40.844168 RX Delay 19 -> 252, step: 4
9030 22:17:40.851255 iDelay=195, Bit 0, Center 136 (91 ~ 182) 92
9031 22:17:40.854950 iDelay=195, Bit 1, Center 130 (83 ~ 178) 96
9032 22:17:40.858103 iDelay=195, Bit 2, Center 120 (71 ~ 170) 100
9033 22:17:40.861162 iDelay=195, Bit 3, Center 130 (83 ~ 178) 96
9034 22:17:40.864465 iDelay=195, Bit 4, Center 134 (87 ~ 182) 96
9035 22:17:40.871418 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
9036 22:17:40.874463 iDelay=195, Bit 6, Center 142 (95 ~ 190) 96
9037 22:17:40.877755 iDelay=195, Bit 7, Center 130 (83 ~ 178) 96
9038 22:17:40.881041 iDelay=195, Bit 8, Center 112 (63 ~ 162) 100
9039 22:17:40.884497 iDelay=195, Bit 9, Center 120 (71 ~ 170) 100
9040 22:17:40.890928 iDelay=195, Bit 10, Center 130 (79 ~ 182) 104
9041 22:17:40.894530 iDelay=195, Bit 11, Center 124 (71 ~ 178) 108
9042 22:17:40.897835 iDelay=195, Bit 12, Center 138 (87 ~ 190) 104
9043 22:17:40.900817 iDelay=195, Bit 13, Center 136 (83 ~ 190) 108
9044 22:17:40.904329 iDelay=195, Bit 14, Center 138 (91 ~ 186) 96
9045 22:17:40.910938 iDelay=195, Bit 15, Center 140 (87 ~ 194) 108
9046 22:17:40.911023 ==
9047 22:17:40.914065 Dram Type= 6, Freq= 0, CH_1, rank 1
9048 22:17:40.917459 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9049 22:17:40.917545 ==
9050 22:17:40.917630 DQS Delay:
9051 22:17:40.920640 DQS0 = 0, DQS1 = 0
9052 22:17:40.920755 DQM Delay:
9053 22:17:40.924058 DQM0 = 133, DQM1 = 129
9054 22:17:40.924146 DQ Delay:
9055 22:17:40.927245 DQ0 =136, DQ1 =130, DQ2 =120, DQ3 =130
9056 22:17:40.930437 DQ4 =134, DQ5 =146, DQ6 =142, DQ7 =130
9057 22:17:40.933799 DQ8 =112, DQ9 =120, DQ10 =130, DQ11 =124
9058 22:17:40.940362 DQ12 =138, DQ13 =136, DQ14 =138, DQ15 =140
9059 22:17:40.940452
9060 22:17:40.940560
9061 22:17:40.940669
9062 22:17:40.940778 [DramC_TX_OE_Calibration] TA2
9063 22:17:40.943935 Original DQ_B0 (3 6) =30, OEN = 27
9064 22:17:40.947002 Original DQ_B1 (3 6) =30, OEN = 27
9065 22:17:40.950370 24, 0x0, End_B0=24 End_B1=24
9066 22:17:40.953540 25, 0x0, End_B0=25 End_B1=25
9067 22:17:40.956937 26, 0x0, End_B0=26 End_B1=26
9068 22:17:40.957053 27, 0x0, End_B0=27 End_B1=27
9069 22:17:40.960105 28, 0x0, End_B0=28 End_B1=28
9070 22:17:40.963764 29, 0x0, End_B0=29 End_B1=29
9071 22:17:40.966887 30, 0x0, End_B0=30 End_B1=30
9072 22:17:40.970080 31, 0x4141, End_B0=30 End_B1=30
9073 22:17:40.973323 Byte0 end_step=30 best_step=27
9074 22:17:40.973428 Byte1 end_step=30 best_step=27
9075 22:17:40.976572 Byte0 TX OE(2T, 0.5T) = (3, 3)
9076 22:17:40.980065 Byte1 TX OE(2T, 0.5T) = (3, 3)
9077 22:17:40.980153
9078 22:17:40.980227
9079 22:17:40.990301 [DQSOSCAuto] RK1, (LSB)MR18= 0x1a05, (MSB)MR19= 0x303, tDQSOscB0 = 407 ps tDQSOscB1 = 396 ps
9080 22:17:40.990426 CH1 RK1: MR19=303, MR18=1A05
9081 22:17:40.996485 CH1_RK1: MR19=0x303, MR18=0x1A05, DQSOSC=396, MR23=63, INC=23, DEC=15
9082 22:17:40.999743 [RxdqsGatingPostProcess] freq 1600
9083 22:17:41.006480 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9084 22:17:41.009511 best DQS0 dly(2T, 0.5T) = (1, 1)
9085 22:17:41.013074 best DQS1 dly(2T, 0.5T) = (1, 1)
9086 22:17:41.016229 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9087 22:17:41.019378 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9088 22:17:41.023036 best DQS0 dly(2T, 0.5T) = (1, 1)
9089 22:17:41.023121 best DQS1 dly(2T, 0.5T) = (1, 1)
9090 22:17:41.026102 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9091 22:17:41.029498 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9092 22:17:41.032927 Pre-setting of DQS Precalculation
9093 22:17:41.039081 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9094 22:17:41.046128 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9095 22:17:41.052590 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9096 22:17:41.052677
9097 22:17:41.052804
9098 22:17:41.056102 [Calibration Summary] 3200 Mbps
9099 22:17:41.056199 CH 0, Rank 0
9100 22:17:41.059206 SW Impedance : PASS
9101 22:17:41.062384 DUTY Scan : NO K
9102 22:17:41.062513 ZQ Calibration : PASS
9103 22:17:41.066175 Jitter Meter : NO K
9104 22:17:41.069064 CBT Training : PASS
9105 22:17:41.069140 Write leveling : PASS
9106 22:17:41.072809 RX DQS gating : PASS
9107 22:17:41.076180 RX DQ/DQS(RDDQC) : PASS
9108 22:17:41.076279 TX DQ/DQS : PASS
9109 22:17:41.079145 RX DATLAT : PASS
9110 22:17:41.082477 RX DQ/DQS(Engine): PASS
9111 22:17:41.082562 TX OE : PASS
9112 22:17:41.085799 All Pass.
9113 22:17:41.085883
9114 22:17:41.085950 CH 0, Rank 1
9115 22:17:41.088982 SW Impedance : PASS
9116 22:17:41.089073 DUTY Scan : NO K
9117 22:17:41.092205 ZQ Calibration : PASS
9118 22:17:41.095612 Jitter Meter : NO K
9119 22:17:41.095713 CBT Training : PASS
9120 22:17:41.098748 Write leveling : PASS
9121 22:17:41.102313 RX DQS gating : PASS
9122 22:17:41.102403 RX DQ/DQS(RDDQC) : PASS
9123 22:17:41.105383 TX DQ/DQS : PASS
9124 22:17:41.108629 RX DATLAT : PASS
9125 22:17:41.108740 RX DQ/DQS(Engine): PASS
9126 22:17:41.112197 TX OE : PASS
9127 22:17:41.112282 All Pass.
9128 22:17:41.112349
9129 22:17:41.115226 CH 1, Rank 0
9130 22:17:41.115336 SW Impedance : PASS
9131 22:17:41.118812 DUTY Scan : NO K
9132 22:17:41.121739 ZQ Calibration : PASS
9133 22:17:41.121824 Jitter Meter : NO K
9134 22:17:41.125450 CBT Training : PASS
9135 22:17:41.125534 Write leveling : PASS
9136 22:17:41.128539 RX DQS gating : PASS
9137 22:17:41.131669 RX DQ/DQS(RDDQC) : PASS
9138 22:17:41.131761 TX DQ/DQS : PASS
9139 22:17:41.134995 RX DATLAT : PASS
9140 22:17:41.138868 RX DQ/DQS(Engine): PASS
9141 22:17:41.138951 TX OE : PASS
9142 22:17:41.141928 All Pass.
9143 22:17:41.142007
9144 22:17:41.142083 CH 1, Rank 1
9145 22:17:41.145094 SW Impedance : PASS
9146 22:17:41.145178 DUTY Scan : NO K
9147 22:17:41.148312 ZQ Calibration : PASS
9148 22:17:41.151737 Jitter Meter : NO K
9149 22:17:41.151825 CBT Training : PASS
9150 22:17:41.155235 Write leveling : PASS
9151 22:17:41.158709 RX DQS gating : PASS
9152 22:17:41.158800 RX DQ/DQS(RDDQC) : PASS
9153 22:17:41.161836 TX DQ/DQS : PASS
9154 22:17:41.165220 RX DATLAT : PASS
9155 22:17:41.165327 RX DQ/DQS(Engine): PASS
9156 22:17:41.168406 TX OE : PASS
9157 22:17:41.168514 All Pass.
9158 22:17:41.168606
9159 22:17:41.171633 DramC Write-DBI on
9160 22:17:41.175071 PER_BANK_REFRESH: Hybrid Mode
9161 22:17:41.175151 TX_TRACKING: ON
9162 22:17:41.184808 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9163 22:17:41.191310 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9164 22:17:41.198308 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9165 22:17:41.201449 [FAST_K] Save calibration result to emmc
9166 22:17:41.204593 sync common calibartion params.
9167 22:17:41.207871 sync cbt_mode0:1, 1:1
9168 22:17:41.211206 dram_init: ddr_geometry: 2
9169 22:17:41.211290 dram_init: ddr_geometry: 2
9170 22:17:41.214590 dram_init: ddr_geometry: 2
9171 22:17:41.217962 0:dram_rank_size:100000000
9172 22:17:41.221184 1:dram_rank_size:100000000
9173 22:17:41.224656 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9174 22:17:41.227838 DFS_SHUFFLE_HW_MODE: ON
9175 22:17:41.231049 dramc_set_vcore_voltage set vcore to 725000
9176 22:17:41.234248 Read voltage for 1600, 0
9177 22:17:41.234332 Vio18 = 0
9178 22:17:41.234399 Vcore = 725000
9179 22:17:41.237448 Vdram = 0
9180 22:17:41.237532 Vddq = 0
9181 22:17:41.237600 Vmddr = 0
9182 22:17:41.241052 switch to 3200 Mbps bootup
9183 22:17:41.244363 [DramcRunTimeConfig]
9184 22:17:41.244447 PHYPLL
9185 22:17:41.244513 DPM_CONTROL_AFTERK: ON
9186 22:17:41.247617 PER_BANK_REFRESH: ON
9187 22:17:41.250822 REFRESH_OVERHEAD_REDUCTION: ON
9188 22:17:41.250906 CMD_PICG_NEW_MODE: OFF
9189 22:17:41.254277 XRTWTW_NEW_MODE: ON
9190 22:17:41.257340 XRTRTR_NEW_MODE: ON
9191 22:17:41.257423 TX_TRACKING: ON
9192 22:17:41.260793 RDSEL_TRACKING: OFF
9193 22:17:41.260877 DQS Precalculation for DVFS: ON
9194 22:17:41.264185 RX_TRACKING: OFF
9195 22:17:41.264268 HW_GATING DBG: ON
9196 22:17:41.267498 ZQCS_ENABLE_LP4: ON
9197 22:17:41.267582 RX_PICG_NEW_MODE: ON
9198 22:17:41.270771 TX_PICG_NEW_MODE: ON
9199 22:17:41.273977 ENABLE_RX_DCM_DPHY: ON
9200 22:17:41.277494 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9201 22:17:41.277587 DUMMY_READ_FOR_TRACKING: OFF
9202 22:17:41.280490 !!! SPM_CONTROL_AFTERK: OFF
9203 22:17:41.283723 !!! SPM could not control APHY
9204 22:17:41.287010 IMPEDANCE_TRACKING: ON
9205 22:17:41.287096 TEMP_SENSOR: ON
9206 22:17:41.290696 HW_SAVE_FOR_SR: OFF
9207 22:17:41.293900 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9208 22:17:41.297112 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9209 22:17:41.297226 Read ODT Tracking: ON
9210 22:17:41.300047 Refresh Rate DeBounce: ON
9211 22:17:41.303546 DFS_NO_QUEUE_FLUSH: ON
9212 22:17:41.307309 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9213 22:17:41.307415 ENABLE_DFS_RUNTIME_MRW: OFF
9214 22:17:41.310104 DDR_RESERVE_NEW_MODE: ON
9215 22:17:41.313379 MR_CBT_SWITCH_FREQ: ON
9216 22:17:41.313459 =========================
9217 22:17:41.333196 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9218 22:17:41.336746 dram_init: ddr_geometry: 2
9219 22:17:41.354951 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9220 22:17:41.358356 dram_init: dram init end (result: 0)
9221 22:17:41.365045 DRAM-K: Full calibration passed in 24507 msecs
9222 22:17:41.368388 MRC: failed to locate region type 0.
9223 22:17:41.368498 DRAM rank0 size:0x100000000,
9224 22:17:41.371632 DRAM rank1 size=0x100000000
9225 22:17:41.381559 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9226 22:17:41.387847 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9227 22:17:41.394706 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9228 22:17:41.401048 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9229 22:17:41.404739 DRAM rank0 size:0x100000000,
9230 22:17:41.407927 DRAM rank1 size=0x100000000
9231 22:17:41.408043 CBMEM:
9232 22:17:41.410955 IMD: root @ 0xfffff000 254 entries.
9233 22:17:41.414227 IMD: root @ 0xffffec00 62 entries.
9234 22:17:41.417830 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9235 22:17:41.424392 WARNING: RO_VPD is uninitialized or empty.
9236 22:17:41.427635 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9237 22:17:41.435134 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9238 22:17:41.447674 read SPI 0x42894 0xe01e: 6226 us, 9215 KB/s, 73.720 Mbps
9239 22:17:41.459130 BS: romstage times (exec / console): total (unknown) / 24008 ms
9240 22:17:41.459257
9241 22:17:41.459420
9242 22:17:41.468871 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9243 22:17:41.472209 ARM64: Exception handlers installed.
9244 22:17:41.475525 ARM64: Testing exception
9245 22:17:41.478827 ARM64: Done test exception
9246 22:17:41.478934 Enumerating buses...
9247 22:17:41.482595 Show all devs... Before device enumeration.
9248 22:17:41.485486 Root Device: enabled 1
9249 22:17:41.489024 CPU_CLUSTER: 0: enabled 1
9250 22:17:41.489132 CPU: 00: enabled 1
9251 22:17:41.492193 Compare with tree...
9252 22:17:41.492306 Root Device: enabled 1
9253 22:17:41.495364 CPU_CLUSTER: 0: enabled 1
9254 22:17:41.498937 CPU: 00: enabled 1
9255 22:17:41.499052 Root Device scanning...
9256 22:17:41.501758 scan_static_bus for Root Device
9257 22:17:41.505023 CPU_CLUSTER: 0 enabled
9258 22:17:41.508684 scan_static_bus for Root Device done
9259 22:17:41.511885 scan_bus: bus Root Device finished in 8 msecs
9260 22:17:41.511987 done
9261 22:17:41.518355 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9262 22:17:41.522007 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9263 22:17:41.528609 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9264 22:17:41.531782 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9265 22:17:41.534860 Allocating resources...
9266 22:17:41.538444 Reading resources...
9267 22:17:41.541577 Root Device read_resources bus 0 link: 0
9268 22:17:41.544714 DRAM rank0 size:0x100000000,
9269 22:17:41.544828 DRAM rank1 size=0x100000000
9270 22:17:41.548241 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9271 22:17:41.551427 CPU: 00 missing read_resources
9272 22:17:41.558273 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9273 22:17:41.561328 Root Device read_resources bus 0 link: 0 done
9274 22:17:41.564966 Done reading resources.
9275 22:17:41.567966 Show resources in subtree (Root Device)...After reading.
9276 22:17:41.571338 Root Device child on link 0 CPU_CLUSTER: 0
9277 22:17:41.574490 CPU_CLUSTER: 0 child on link 0 CPU: 00
9278 22:17:41.584714 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9279 22:17:41.584841 CPU: 00
9280 22:17:41.587846 Root Device assign_resources, bus 0 link: 0
9281 22:17:41.591128 CPU_CLUSTER: 0 missing set_resources
9282 22:17:41.597767 Root Device assign_resources, bus 0 link: 0 done
9283 22:17:41.597880 Done setting resources.
9284 22:17:41.604574 Show resources in subtree (Root Device)...After assigning values.
9285 22:17:41.607698 Root Device child on link 0 CPU_CLUSTER: 0
9286 22:17:41.610789 CPU_CLUSTER: 0 child on link 0 CPU: 00
9287 22:17:41.620873 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9288 22:17:41.620985 CPU: 00
9289 22:17:41.624297 Done allocating resources.
9290 22:17:41.630988 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9291 22:17:41.631094 Enabling resources...
9292 22:17:41.631202 done.
9293 22:17:41.637172 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9294 22:17:41.641170 Initializing devices...
9295 22:17:41.641278 Root Device init
9296 22:17:41.644140 init hardware done!
9297 22:17:41.644253 0x00000018: ctrlr->caps
9298 22:17:41.647492 52.000 MHz: ctrlr->f_max
9299 22:17:41.650680 0.400 MHz: ctrlr->f_min
9300 22:17:41.650789 0x40ff8080: ctrlr->voltages
9301 22:17:41.653712 sclk: 390625
9302 22:17:41.653816 Bus Width = 1
9303 22:17:41.657309 sclk: 390625
9304 22:17:41.657416 Bus Width = 1
9305 22:17:41.660366 Early init status = 3
9306 22:17:41.663589 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9307 22:17:41.667411 in-header: 03 fc 00 00 01 00 00 00
9308 22:17:41.670601 in-data: 00
9309 22:17:41.673867 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9310 22:17:41.679243 in-header: 03 fd 00 00 00 00 00 00
9311 22:17:41.682302 in-data:
9312 22:17:41.685602 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9313 22:17:41.690079 in-header: 03 fc 00 00 01 00 00 00
9314 22:17:41.693350 in-data: 00
9315 22:17:41.697010 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9316 22:17:41.702652 in-header: 03 fd 00 00 00 00 00 00
9317 22:17:41.705855 in-data:
9318 22:17:41.708982 [SSUSB] Setting up USB HOST controller...
9319 22:17:41.712295 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9320 22:17:41.715765 [SSUSB] phy power-on done.
9321 22:17:41.718781 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9322 22:17:41.725762 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9323 22:17:41.728925 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9324 22:17:41.735648 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9325 22:17:41.742255 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9326 22:17:41.748829 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9327 22:17:41.755234 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9328 22:17:41.762194 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9329 22:17:41.765340 SPM: binary array size = 0x9dc
9330 22:17:41.768482 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9331 22:17:41.775205 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9332 22:17:41.781605 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9333 22:17:41.788305 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9334 22:17:41.791649 configure_display: Starting display init
9335 22:17:41.825624 anx7625_power_on_init: Init interface.
9336 22:17:41.829174 anx7625_disable_pd_protocol: Disabled PD feature.
9337 22:17:41.832434 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9338 22:17:41.860158 anx7625_start_dp_work: Secure OCM version=00
9339 22:17:41.863091 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9340 22:17:41.878067 sp_tx_get_edid_block: EDID Block = 1
9341 22:17:41.980784 Extracted contents:
9342 22:17:41.984329 header: 00 ff ff ff ff ff ff 00
9343 22:17:41.987446 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9344 22:17:41.990559 version: 01 04
9345 22:17:41.994068 basic params: 95 1f 11 78 0a
9346 22:17:41.997231 chroma info: 76 90 94 55 54 90 27 21 50 54
9347 22:17:42.000516 established: 00 00 00
9348 22:17:42.007427 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9349 22:17:42.010623 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9350 22:17:42.017239 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9351 22:17:42.023718 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9352 22:17:42.030212 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9353 22:17:42.033844 extensions: 00
9354 22:17:42.033927 checksum: fb
9355 22:17:42.034011
9356 22:17:42.037265 Manufacturer: IVO Model 57d Serial Number 0
9357 22:17:42.040336 Made week 0 of 2020
9358 22:17:42.040419 EDID version: 1.4
9359 22:17:42.043635 Digital display
9360 22:17:42.047045 6 bits per primary color channel
9361 22:17:42.047127 DisplayPort interface
9362 22:17:42.050543 Maximum image size: 31 cm x 17 cm
9363 22:17:42.053638 Gamma: 220%
9364 22:17:42.053745 Check DPMS levels
9365 22:17:42.056707 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9366 22:17:42.063462 First detailed timing is preferred timing
9367 22:17:42.063543 Established timings supported:
9368 22:17:42.066595 Standard timings supported:
9369 22:17:42.070283 Detailed timings
9370 22:17:42.073319 Hex of detail: 383680a07038204018303c0035ae10000019
9371 22:17:42.079816 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9372 22:17:42.083163 0780 0798 07c8 0820 hborder 0
9373 22:17:42.086713 0438 043b 0447 0458 vborder 0
9374 22:17:42.089846 -hsync -vsync
9375 22:17:42.089930 Did detailed timing
9376 22:17:42.096597 Hex of detail: 000000000000000000000000000000000000
9377 22:17:42.099881 Manufacturer-specified data, tag 0
9378 22:17:42.103012 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9379 22:17:42.106209 ASCII string: InfoVision
9380 22:17:42.109607 Hex of detail: 000000fe00523134304e574635205248200a
9381 22:17:42.112681 ASCII string: R140NWF5 RH
9382 22:17:42.112757 Checksum
9383 22:17:42.115979 Checksum: 0xfb (valid)
9384 22:17:42.119395 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9385 22:17:42.123008 DSI data_rate: 832800000 bps
9386 22:17:42.129590 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9387 22:17:42.132679 anx7625_parse_edid: pixelclock(138800).
9388 22:17:42.136160 hactive(1920), hsync(48), hfp(24), hbp(88)
9389 22:17:42.139297 vactive(1080), vsync(12), vfp(3), vbp(17)
9390 22:17:42.142545 anx7625_dsi_config: config dsi.
9391 22:17:42.149074 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9392 22:17:42.162665 anx7625_dsi_config: success to config DSI
9393 22:17:42.166054 anx7625_dp_start: MIPI phy setup OK.
9394 22:17:42.169259 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9395 22:17:42.172692 mtk_ddp_mode_set invalid vrefresh 60
9396 22:17:42.176148 main_disp_path_setup
9397 22:17:42.176226 ovl_layer_smi_id_en
9398 22:17:42.179268 ovl_layer_smi_id_en
9399 22:17:42.179348 ccorr_config
9400 22:17:42.179411 aal_config
9401 22:17:42.182637 gamma_config
9402 22:17:42.182707 postmask_config
9403 22:17:42.185709 dither_config
9404 22:17:42.189299 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9405 22:17:42.195939 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9406 22:17:42.198984 Root Device init finished in 554 msecs
9407 22:17:42.202206 CPU_CLUSTER: 0 init
9408 22:17:42.209068 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9409 22:17:42.215564 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9410 22:17:42.215652 APU_MBOX 0x190000b0 = 0x10001
9411 22:17:42.218728 APU_MBOX 0x190001b0 = 0x10001
9412 22:17:42.222228 APU_MBOX 0x190005b0 = 0x10001
9413 22:17:42.225584 APU_MBOX 0x190006b0 = 0x10001
9414 22:17:42.231769 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9415 22:17:42.241799 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9416 22:17:42.254059 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9417 22:17:42.260534 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9418 22:17:42.272842 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9419 22:17:42.281815 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9420 22:17:42.285040 CPU_CLUSTER: 0 init finished in 81 msecs
9421 22:17:42.288662 Devices initialized
9422 22:17:42.292027 Show all devs... After init.
9423 22:17:42.292112 Root Device: enabled 1
9424 22:17:42.294931 CPU_CLUSTER: 0: enabled 1
9425 22:17:42.298161 CPU: 00: enabled 1
9426 22:17:42.301864 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9427 22:17:42.304988 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9428 22:17:42.308069 ELOG: NV offset 0x57f000 size 0x1000
9429 22:17:42.314727 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9430 22:17:42.321362 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9431 22:17:42.324536 ELOG: Event(17) added with size 13 at 2023-06-05 22:17:44 UTC
9432 22:17:42.331241 out: cmd=0x121: 03 db 21 01 00 00 00 00
9433 22:17:42.334335 in-header: 03 2a 00 00 2c 00 00 00
9434 22:17:42.347759 in-data: 35 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9435 22:17:42.350976 ELOG: Event(A1) added with size 10 at 2023-06-05 22:17:44 UTC
9436 22:17:42.357528 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9437 22:17:42.364369 ELOG: Event(A0) added with size 9 at 2023-06-05 22:17:44 UTC
9438 22:17:42.367501 elog_add_boot_reason: Logged dev mode boot
9439 22:17:42.374085 BS: BS_POST_DEVICE entry times (exec / console): 3 / 64 ms
9440 22:17:42.374183 Finalize devices...
9441 22:17:42.377572 Devices finalized
9442 22:17:42.380806 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9443 22:17:42.384007 Writing coreboot table at 0xffe64000
9444 22:17:42.390733 0. 000000000010a000-0000000000113fff: RAMSTAGE
9445 22:17:42.393966 1. 0000000040000000-00000000400fffff: RAM
9446 22:17:42.397029 2. 0000000040100000-000000004032afff: RAMSTAGE
9447 22:17:42.400669 3. 000000004032b000-00000000545fffff: RAM
9448 22:17:42.403897 4. 0000000054600000-000000005465ffff: BL31
9449 22:17:42.410309 5. 0000000054660000-00000000ffe63fff: RAM
9450 22:17:42.413544 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9451 22:17:42.417092 7. 0000000100000000-000000023fffffff: RAM
9452 22:17:42.420246 Passing 5 GPIOs to payload:
9453 22:17:42.423525 NAME | PORT | POLARITY | VALUE
9454 22:17:42.430204 EC in RW | 0x000000aa | low | undefined
9455 22:17:42.433356 EC interrupt | 0x00000005 | low | undefined
9456 22:17:42.440293 TPM interrupt | 0x000000ab | high | undefined
9457 22:17:42.443436 SD card detect | 0x00000011 | high | undefined
9458 22:17:42.446605 speaker enable | 0x00000093 | high | undefined
9459 22:17:42.453445 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9460 22:17:42.456705 in-header: 03 f9 00 00 02 00 00 00
9461 22:17:42.456812 in-data: 02 00
9462 22:17:42.459875 ADC[4]: Raw value=901032 ID=7
9463 22:17:42.463110 ADC[3]: Raw value=213179 ID=1
9464 22:17:42.463207 RAM Code: 0x71
9465 22:17:42.466591 ADC[6]: Raw value=74502 ID=0
9466 22:17:42.469712 ADC[5]: Raw value=212441 ID=1
9467 22:17:42.469819 SKU Code: 0x1
9468 22:17:42.476296 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 4ba3
9469 22:17:42.479572 coreboot table: 964 bytes.
9470 22:17:42.483088 IMD ROOT 0. 0xfffff000 0x00001000
9471 22:17:42.486251 IMD SMALL 1. 0xffffe000 0x00001000
9472 22:17:42.489789 RO MCACHE 2. 0xffffc000 0x00001104
9473 22:17:42.492985 CONSOLE 3. 0xfff7c000 0x00080000
9474 22:17:42.496335 FMAP 4. 0xfff7b000 0x00000452
9475 22:17:42.496444 TIME STAMP 5. 0xfff7a000 0x00000910
9476 22:17:42.499574 VBOOT WORK 6. 0xfff66000 0x00014000
9477 22:17:42.502858 RAMOOPS 7. 0xffe66000 0x00100000
9478 22:17:42.506463 COREBOOT 8. 0xffe64000 0x00002000
9479 22:17:42.509428 IMD small region:
9480 22:17:42.512743 IMD ROOT 0. 0xffffec00 0x00000400
9481 22:17:42.516471 VPD 1. 0xffffeba0 0x0000004c
9482 22:17:42.519544 MMC STATUS 2. 0xffffeb80 0x00000004
9483 22:17:42.526011 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9484 22:17:42.526129 Probing TPM: done!
9485 22:17:42.533172 Connected to device vid:did:rid of 1ae0:0028:00
9486 22:17:42.539557 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
9487 22:17:42.542703 Initialized TPM device CR50 revision 0
9488 22:17:42.546804 Checking cr50 for pending updates
9489 22:17:42.552177 Reading cr50 TPM mode
9490 22:17:42.560528 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9491 22:17:42.567262 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9492 22:17:42.607444 read SPI 0x3990ec 0x4f1b0: 34851 us, 9297 KB/s, 74.376 Mbps
9493 22:17:42.610500 Checking segment from ROM address 0x40100000
9494 22:17:42.613831 Checking segment from ROM address 0x4010001c
9495 22:17:42.620596 Loading segment from ROM address 0x40100000
9496 22:17:42.620680 code (compression=0)
9497 22:17:42.630443 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9498 22:17:42.637293 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9499 22:17:42.637378 it's not compressed!
9500 22:17:42.644005 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9501 22:17:42.650368 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9502 22:17:42.667830 Loading segment from ROM address 0x4010001c
9503 22:17:42.667945 Entry Point 0x80000000
9504 22:17:42.671069 Loaded segments
9505 22:17:42.674506 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9506 22:17:42.681184 Jumping to boot code at 0x80000000(0xffe64000)
9507 22:17:42.687725 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9508 22:17:42.694186 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9509 22:17:42.702301 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9510 22:17:42.705391 Checking segment from ROM address 0x40100000
9511 22:17:42.709071 Checking segment from ROM address 0x4010001c
9512 22:17:42.715306 Loading segment from ROM address 0x40100000
9513 22:17:42.715404 code (compression=1)
9514 22:17:42.722092 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9515 22:17:42.732219 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9516 22:17:42.732313 using LZMA
9517 22:17:42.740319 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9518 22:17:42.747320 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9519 22:17:42.750608 Loading segment from ROM address 0x4010001c
9520 22:17:42.750693 Entry Point 0x54601000
9521 22:17:42.753746 Loaded segments
9522 22:17:42.756974 NOTICE: MT8192 bl31_setup
9523 22:17:42.764271 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9524 22:17:42.767468 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9525 22:17:42.771015 WARNING: region 0:
9526 22:17:42.774059 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9527 22:17:42.774139 WARNING: region 1:
9528 22:17:42.780660 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9529 22:17:42.784178 WARNING: region 2:
9530 22:17:42.787239 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9531 22:17:42.790777 WARNING: region 3:
9532 22:17:42.794028 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9533 22:17:42.797260 WARNING: region 4:
9534 22:17:42.803841 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9535 22:17:42.803931 WARNING: region 5:
9536 22:17:42.807099 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9537 22:17:42.810907 WARNING: region 6:
9538 22:17:42.813908 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9539 22:17:42.817286 WARNING: region 7:
9540 22:17:42.820519 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9541 22:17:42.827313 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9542 22:17:42.830338 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9543 22:17:42.833818 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9544 22:17:42.840353 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9545 22:17:42.843994 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9546 22:17:42.846946 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9547 22:17:42.853658 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9548 22:17:42.857009 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9549 22:17:42.863988 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9550 22:17:42.866992 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9551 22:17:42.870202 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9552 22:17:42.877206 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9553 22:17:42.880401 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9554 22:17:42.883862 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9555 22:17:42.890136 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9556 22:17:42.893548 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9557 22:17:42.900042 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9558 22:17:42.903677 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9559 22:17:42.906639 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9560 22:17:42.913537 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9561 22:17:42.916863 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9562 22:17:42.923499 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9563 22:17:42.926530 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9564 22:17:42.929949 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9565 22:17:42.936598 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9566 22:17:42.940090 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9567 22:17:42.946510 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9568 22:17:42.949815 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9569 22:17:42.953247 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9570 22:17:42.959652 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9571 22:17:42.963045 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9572 22:17:42.970011 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9573 22:17:42.973137 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9574 22:17:42.976755 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9575 22:17:42.980003 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9576 22:17:42.986239 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9577 22:17:42.989825 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9578 22:17:42.993043 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9579 22:17:42.996386 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9580 22:17:43.003229 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9581 22:17:43.006383 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9582 22:17:43.009362 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9583 22:17:43.012913 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9584 22:17:43.019239 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9585 22:17:43.022914 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9586 22:17:43.026020 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9587 22:17:43.029120 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9588 22:17:43.036142 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9589 22:17:43.039191 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9590 22:17:43.045736 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9591 22:17:43.049058 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9592 22:17:43.052714 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9593 22:17:43.059244 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9594 22:17:43.062416 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9595 22:17:43.069133 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9596 22:17:43.072552 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9597 22:17:43.079058 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9598 22:17:43.082437 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9599 22:17:43.088786 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9600 22:17:43.091926 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9601 22:17:43.095232 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9602 22:17:43.102273 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9603 22:17:43.105540 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9604 22:17:43.111844 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9605 22:17:43.115452 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9606 22:17:43.121960 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9607 22:17:43.125256 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9608 22:17:43.131975 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9609 22:17:43.135368 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9610 22:17:43.138711 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9611 22:17:43.145456 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9612 22:17:43.148637 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9613 22:17:43.155020 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9614 22:17:43.158376 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9615 22:17:43.165343 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9616 22:17:43.168540 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9617 22:17:43.171687 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9618 22:17:43.178139 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9619 22:17:43.181591 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9620 22:17:43.188116 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9621 22:17:43.191711 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9622 22:17:43.198559 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9623 22:17:43.201796 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9624 22:17:43.208222 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9625 22:17:43.211543 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9626 22:17:43.215340 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9627 22:17:43.221639 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9628 22:17:43.224750 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9629 22:17:43.231112 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9630 22:17:43.234519 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9631 22:17:43.241181 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9632 22:17:43.244517 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9633 22:17:43.251162 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9634 22:17:43.254497 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9635 22:17:43.258056 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9636 22:17:43.264336 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9637 22:17:43.267724 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9638 22:17:43.271025 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9639 22:17:43.277772 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9640 22:17:43.280989 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9641 22:17:43.284971 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9642 22:17:43.291187 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9643 22:17:43.294605 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9644 22:17:43.297674 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9645 22:17:43.304509 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9646 22:17:43.307841 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9647 22:17:43.314379 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9648 22:17:43.317696 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9649 22:17:43.320896 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9650 22:17:43.327544 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9651 22:17:43.331132 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9652 22:17:43.337688 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9653 22:17:43.340816 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9654 22:17:43.344074 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9655 22:17:43.350696 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9656 22:17:43.354247 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9657 22:17:43.357750 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9658 22:17:43.364186 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9659 22:17:43.367520 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9660 22:17:43.371099 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9661 22:17:43.377307 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9662 22:17:43.381067 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9663 22:17:43.384144 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9664 22:17:43.387206 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9665 22:17:43.393978 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9666 22:17:43.397059 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9667 22:17:43.403826 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9668 22:17:43.407434 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9669 22:17:43.410648 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9670 22:17:43.417061 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9671 22:17:43.420286 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9672 22:17:43.423875 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9673 22:17:43.430845 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9674 22:17:43.434067 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9675 22:17:43.440447 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9676 22:17:43.443647 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9677 22:17:43.446982 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9678 22:17:43.453500 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9679 22:17:43.456848 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9680 22:17:43.463581 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9681 22:17:43.467204 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9682 22:17:43.470309 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9683 22:17:43.476657 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9684 22:17:43.480050 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9685 22:17:43.486874 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9686 22:17:43.490278 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9687 22:17:43.493551 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9688 22:17:43.500375 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9689 22:17:43.503523 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9690 22:17:43.506750 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9691 22:17:43.513824 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9692 22:17:43.516800 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9693 22:17:43.523549 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9694 22:17:43.526729 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9695 22:17:43.530135 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9696 22:17:43.536883 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9697 22:17:43.539835 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9698 22:17:43.546596 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9699 22:17:43.549773 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9700 22:17:43.553258 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9701 22:17:43.559947 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9702 22:17:43.563142 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9703 22:17:43.569958 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9704 22:17:43.573100 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9705 22:17:43.576345 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9706 22:17:43.583194 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9707 22:17:43.586339 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9708 22:17:43.592706 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9709 22:17:43.596284 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9710 22:17:43.599372 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9711 22:17:43.606166 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9712 22:17:43.609502 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9713 22:17:43.615956 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9714 22:17:43.619215 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9715 22:17:43.622538 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9716 22:17:43.629256 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9717 22:17:43.632489 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9718 22:17:43.639142 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9719 22:17:43.642365 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9720 22:17:43.645570 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9721 22:17:43.652131 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9722 22:17:43.655782 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9723 22:17:43.662400 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9724 22:17:43.665660 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9725 22:17:43.668616 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9726 22:17:43.675521 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9727 22:17:43.678772 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9728 22:17:43.685474 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9729 22:17:43.688544 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9730 22:17:43.692086 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9731 22:17:43.698280 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9732 22:17:43.701835 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9733 22:17:43.708176 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9734 22:17:43.711784 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9735 22:17:43.718262 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9736 22:17:43.721717 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9737 22:17:43.725180 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9738 22:17:43.731914 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9739 22:17:43.735045 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9740 22:17:43.741661 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9741 22:17:43.745046 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9742 22:17:43.748225 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9743 22:17:43.755061 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9744 22:17:43.757905 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9745 22:17:43.764517 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9746 22:17:43.768041 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9747 22:17:43.774977 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9748 22:17:43.778012 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9749 22:17:43.781220 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9750 22:17:43.788050 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9751 22:17:43.791109 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9752 22:17:43.797557 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9753 22:17:43.801257 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9754 22:17:43.807571 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9755 22:17:43.810762 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9756 22:17:43.814044 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9757 22:17:43.820641 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9758 22:17:43.823989 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9759 22:17:43.830611 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9760 22:17:43.833713 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9761 22:17:43.840359 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9762 22:17:43.843837 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9763 22:17:43.847064 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9764 22:17:43.853674 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9765 22:17:43.856962 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9766 22:17:43.863349 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9767 22:17:43.866815 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9768 22:17:43.873194 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9769 22:17:43.876521 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9770 22:17:43.880105 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9771 22:17:43.883448 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9772 22:17:43.889961 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9773 22:17:43.893052 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9774 22:17:43.896587 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9775 22:17:43.902932 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9776 22:17:43.906570 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9777 22:17:43.909607 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9778 22:17:43.916215 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9779 22:17:43.919382 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9780 22:17:43.922631 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9781 22:17:43.929176 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9782 22:17:43.932594 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9783 22:17:43.939467 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9784 22:17:43.942799 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9785 22:17:43.946100 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9786 22:17:43.952528 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9787 22:17:43.956067 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9788 22:17:43.959296 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9789 22:17:43.965749 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9790 22:17:43.969306 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9791 22:17:43.975824 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9792 22:17:43.978990 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9793 22:17:43.982395 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9794 22:17:43.988938 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9795 22:17:43.992149 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9796 22:17:43.995494 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9797 22:17:44.002254 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9798 22:17:44.005377 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9799 22:17:44.008560 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9800 22:17:44.015672 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9801 22:17:44.018710 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9802 22:17:44.025162 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9803 22:17:44.028353 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9804 22:17:44.031649 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9805 22:17:44.038241 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9806 22:17:44.041753 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9807 22:17:44.048191 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9808 22:17:44.051946 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9809 22:17:44.054817 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9810 22:17:44.058434 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9811 22:17:44.064756 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9812 22:17:44.068408 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9813 22:17:44.071575 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9814 22:17:44.074584 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9815 22:17:44.081574 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9816 22:17:44.084703 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9817 22:17:44.088414 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9818 22:17:44.091548 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9819 22:17:44.097980 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9820 22:17:44.101651 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9821 22:17:44.105154 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9822 22:17:44.108116 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9823 22:17:44.114744 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9824 22:17:44.118029 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9825 22:17:44.124406 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9826 22:17:44.128000 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9827 22:17:44.134279 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9828 22:17:44.137761 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9829 22:17:44.141078 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9830 22:17:44.147812 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9831 22:17:44.151133 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9832 22:17:44.157750 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9833 22:17:44.160955 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9834 22:17:44.164403 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9835 22:17:44.170849 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9836 22:17:44.174009 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9837 22:17:44.180773 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9838 22:17:44.184019 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9839 22:17:44.187575 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9840 22:17:44.194018 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9841 22:17:44.197031 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9842 22:17:44.203672 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9843 22:17:44.206833 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9844 22:17:44.213743 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9845 22:17:44.216613 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9846 22:17:44.219996 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9847 22:17:44.226812 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9848 22:17:44.230042 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9849 22:17:44.236510 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9850 22:17:44.239955 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9851 22:17:44.246728 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9852 22:17:44.249869 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9853 22:17:44.253461 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9854 22:17:44.259879 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9855 22:17:44.263158 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9856 22:17:44.269572 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9857 22:17:44.273186 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9858 22:17:44.279416 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9859 22:17:44.282632 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9860 22:17:44.286053 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9861 22:17:44.292701 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9862 22:17:44.295698 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9863 22:17:44.302675 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9864 22:17:44.305794 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9865 22:17:44.308920 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9866 22:17:44.315718 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9867 22:17:44.318945 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9868 22:17:44.325304 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9869 22:17:44.328670 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9870 22:17:44.335211 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9871 22:17:44.338468 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9872 22:17:44.342066 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9873 22:17:44.348727 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9874 22:17:44.351767 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9875 22:17:44.358520 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9876 22:17:44.361697 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9877 22:17:44.368336 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9878 22:17:44.371827 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9879 22:17:44.374928 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9880 22:17:44.381360 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9881 22:17:44.384664 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9882 22:17:44.391507 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9883 22:17:44.394939 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9884 22:17:44.397936 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9885 22:17:44.404861 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9886 22:17:44.408219 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9887 22:17:44.414523 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9888 22:17:44.417726 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9889 22:17:44.421109 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9890 22:17:44.427948 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9891 22:17:44.430855 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9892 22:17:44.438089 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9893 22:17:44.441140 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9894 22:17:44.447438 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9895 22:17:44.450993 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9896 22:17:44.454106 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9897 22:17:44.460859 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9898 22:17:44.463978 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9899 22:17:44.470801 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9900 22:17:44.473848 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9901 22:17:44.480510 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9902 22:17:44.484087 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9903 22:17:44.487366 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9904 22:17:44.494134 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9905 22:17:44.497137 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9906 22:17:44.503713 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9907 22:17:44.507035 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9908 22:17:44.513902 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9909 22:17:44.516815 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9910 22:17:44.523749 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9911 22:17:44.526863 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9912 22:17:44.530063 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9913 22:17:44.536702 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9914 22:17:44.540285 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9915 22:17:44.546692 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9916 22:17:44.550135 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9917 22:17:44.556781 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9918 22:17:44.559929 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9919 22:17:44.566525 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9920 22:17:44.569823 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9921 22:17:44.573224 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9922 22:17:44.579415 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9923 22:17:44.583006 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9924 22:17:44.589512 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9925 22:17:44.593030 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9926 22:17:44.599470 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9927 22:17:44.602604 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9928 22:17:44.609219 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9929 22:17:44.612930 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9930 22:17:44.615989 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9931 22:17:44.622656 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9932 22:17:44.625785 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9933 22:17:44.632325 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9934 22:17:44.635527 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9935 22:17:44.642353 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9936 22:17:44.645736 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9937 22:17:44.652150 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9938 22:17:44.655274 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9939 22:17:44.662061 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9940 22:17:44.665216 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9941 22:17:44.668770 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9942 22:17:44.675286 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9943 22:17:44.678523 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9944 22:17:44.682159 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9945 22:17:44.688488 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9946 22:17:44.691685 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9947 22:17:44.698456 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9948 22:17:44.701822 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9949 22:17:44.708079 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9950 22:17:44.711544 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9951 22:17:44.718432 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9952 22:17:44.721552 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9953 22:17:44.727839 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9954 22:17:44.731203 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9955 22:17:44.738036 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9956 22:17:44.741160 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9957 22:17:44.747655 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9958 22:17:44.751110 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9959 22:17:44.757584 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9960 22:17:44.761230 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9961 22:17:44.767793 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9962 22:17:44.770586 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9963 22:17:44.777507 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9964 22:17:44.780709 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9965 22:17:44.786997 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9966 22:17:44.790496 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9967 22:17:44.797253 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9968 22:17:44.800596 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9969 22:17:44.807030 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9970 22:17:44.810240 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9971 22:17:44.816953 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9972 22:17:44.823467 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9973 22:17:44.826612 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9974 22:17:44.833213 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9975 22:17:44.836729 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9976 22:17:44.836824 INFO: [APUAPC] vio 0
9977 22:17:44.843824 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9978 22:17:44.847725 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9979 22:17:44.850730 INFO: [APUAPC] D0_APC_0: 0x400510
9980 22:17:44.853859 INFO: [APUAPC] D0_APC_1: 0x0
9981 22:17:44.857050 INFO: [APUAPC] D0_APC_2: 0x1540
9982 22:17:44.860610 INFO: [APUAPC] D0_APC_3: 0x0
9983 22:17:44.863764 INFO: [APUAPC] D1_APC_0: 0xffffffff
9984 22:17:44.866861 INFO: [APUAPC] D1_APC_1: 0xffffffff
9985 22:17:44.870236 INFO: [APUAPC] D1_APC_2: 0x3fffff
9986 22:17:44.873497 INFO: [APUAPC] D1_APC_3: 0x0
9987 22:17:44.876674 INFO: [APUAPC] D2_APC_0: 0xffffffff
9988 22:17:44.880144 INFO: [APUAPC] D2_APC_1: 0xffffffff
9989 22:17:44.883656 INFO: [APUAPC] D2_APC_2: 0x3fffff
9990 22:17:44.886816 INFO: [APUAPC] D2_APC_3: 0x0
9991 22:17:44.890000 INFO: [APUAPC] D3_APC_0: 0xffffffff
9992 22:17:44.893399 INFO: [APUAPC] D3_APC_1: 0xffffffff
9993 22:17:44.896861 INFO: [APUAPC] D3_APC_2: 0x3fffff
9994 22:17:44.900084 INFO: [APUAPC] D3_APC_3: 0x0
9995 22:17:44.903054 INFO: [APUAPC] D4_APC_0: 0xffffffff
9996 22:17:44.906640 INFO: [APUAPC] D4_APC_1: 0xffffffff
9997 22:17:44.909961 INFO: [APUAPC] D4_APC_2: 0x3fffff
9998 22:17:44.912953 INFO: [APUAPC] D4_APC_3: 0x0
9999 22:17:44.916248 INFO: [APUAPC] D5_APC_0: 0xffffffff
10000 22:17:44.919563 INFO: [APUAPC] D5_APC_1: 0xffffffff
10001 22:17:44.923274 INFO: [APUAPC] D5_APC_2: 0x3fffff
10002 22:17:44.926465 INFO: [APUAPC] D5_APC_3: 0x0
10003 22:17:44.929641 INFO: [APUAPC] D6_APC_0: 0xffffffff
10004 22:17:44.932695 INFO: [APUAPC] D6_APC_1: 0xffffffff
10005 22:17:44.936195 INFO: [APUAPC] D6_APC_2: 0x3fffff
10006 22:17:44.939514 INFO: [APUAPC] D6_APC_3: 0x0
10007 22:17:44.942594 INFO: [APUAPC] D7_APC_0: 0xffffffff
10008 22:17:44.946216 INFO: [APUAPC] D7_APC_1: 0xffffffff
10009 22:17:44.949578 INFO: [APUAPC] D7_APC_2: 0x3fffff
10010 22:17:44.949660 INFO: [APUAPC] D7_APC_3: 0x0
10011 22:17:44.956206 INFO: [APUAPC] D8_APC_0: 0xffffffff
10012 22:17:44.959629 INFO: [APUAPC] D8_APC_1: 0xffffffff
10013 22:17:44.962818 INFO: [APUAPC] D8_APC_2: 0x3fffff
10014 22:17:44.962917 INFO: [APUAPC] D8_APC_3: 0x0
10015 22:17:44.966089 INFO: [APUAPC] D9_APC_0: 0xffffffff
10016 22:17:44.969271 INFO: [APUAPC] D9_APC_1: 0xffffffff
10017 22:17:44.972638 INFO: [APUAPC] D9_APC_2: 0x3fffff
10018 22:17:44.975683 INFO: [APUAPC] D9_APC_3: 0x0
10019 22:17:44.978935 INFO: [APUAPC] D10_APC_0: 0xffffffff
10020 22:17:44.982617 INFO: [APUAPC] D10_APC_1: 0xffffffff
10021 22:17:44.988906 INFO: [APUAPC] D10_APC_2: 0x3fffff
10022 22:17:44.988996 INFO: [APUAPC] D10_APC_3: 0x0
10023 22:17:44.992174 INFO: [APUAPC] D11_APC_0: 0xffffffff
10024 22:17:44.999169 INFO: [APUAPC] D11_APC_1: 0xffffffff
10025 22:17:45.002373 INFO: [APUAPC] D11_APC_2: 0x3fffff
10026 22:17:45.002451 INFO: [APUAPC] D11_APC_3: 0x0
10027 22:17:45.008556 INFO: [APUAPC] D12_APC_0: 0xffffffff
10028 22:17:45.012059 INFO: [APUAPC] D12_APC_1: 0xffffffff
10029 22:17:45.015147 INFO: [APUAPC] D12_APC_2: 0x3fffff
10030 22:17:45.018412 INFO: [APUAPC] D12_APC_3: 0x0
10031 22:17:45.021947 INFO: [APUAPC] D13_APC_0: 0xffffffff
10032 22:17:45.025270 INFO: [APUAPC] D13_APC_1: 0xffffffff
10033 22:17:45.028484 INFO: [APUAPC] D13_APC_2: 0x3fffff
10034 22:17:45.031719 INFO: [APUAPC] D13_APC_3: 0x0
10035 22:17:45.034789 INFO: [APUAPC] D14_APC_0: 0xffffffff
10036 22:17:45.038272 INFO: [APUAPC] D14_APC_1: 0xffffffff
10037 22:17:45.041414 INFO: [APUAPC] D14_APC_2: 0x3fffff
10038 22:17:45.045111 INFO: [APUAPC] D14_APC_3: 0x0
10039 22:17:45.048058 INFO: [APUAPC] D15_APC_0: 0xffffffff
10040 22:17:45.051541 INFO: [APUAPC] D15_APC_1: 0xffffffff
10041 22:17:45.054796 INFO: [APUAPC] D15_APC_2: 0x3fffff
10042 22:17:45.058240 INFO: [APUAPC] D15_APC_3: 0x0
10043 22:17:45.061312 INFO: [APUAPC] APC_CON: 0x4
10044 22:17:45.061431 INFO: [NOCDAPC] D0_APC_0: 0x0
10045 22:17:45.064637 INFO: [NOCDAPC] D0_APC_1: 0x0
10046 22:17:45.068221 INFO: [NOCDAPC] D1_APC_0: 0x0
10047 22:17:45.071465 INFO: [NOCDAPC] D1_APC_1: 0xfff
10048 22:17:45.074688 INFO: [NOCDAPC] D2_APC_0: 0x0
10049 22:17:45.077982 INFO: [NOCDAPC] D2_APC_1: 0xfff
10050 22:17:45.081285 INFO: [NOCDAPC] D3_APC_0: 0x0
10051 22:17:45.084481 INFO: [NOCDAPC] D3_APC_1: 0xfff
10052 22:17:45.088138 INFO: [NOCDAPC] D4_APC_0: 0x0
10053 22:17:45.091173 INFO: [NOCDAPC] D4_APC_1: 0xfff
10054 22:17:45.091255 INFO: [NOCDAPC] D5_APC_0: 0x0
10055 22:17:45.094579 INFO: [NOCDAPC] D5_APC_1: 0xfff
10056 22:17:45.097680 INFO: [NOCDAPC] D6_APC_0: 0x0
10057 22:17:45.101003 INFO: [NOCDAPC] D6_APC_1: 0xfff
10058 22:17:45.104553 INFO: [NOCDAPC] D7_APC_0: 0x0
10059 22:17:45.107472 INFO: [NOCDAPC] D7_APC_1: 0xfff
10060 22:17:45.111056 INFO: [NOCDAPC] D8_APC_0: 0x0
10061 22:17:45.114272 INFO: [NOCDAPC] D8_APC_1: 0xfff
10062 22:17:45.117686 INFO: [NOCDAPC] D9_APC_0: 0x0
10063 22:17:45.120746 INFO: [NOCDAPC] D9_APC_1: 0xfff
10064 22:17:45.124016 INFO: [NOCDAPC] D10_APC_0: 0x0
10065 22:17:45.127602 INFO: [NOCDAPC] D10_APC_1: 0xfff
10066 22:17:45.130704 INFO: [NOCDAPC] D11_APC_0: 0x0
10067 22:17:45.130785 INFO: [NOCDAPC] D11_APC_1: 0xfff
10068 22:17:45.134369 INFO: [NOCDAPC] D12_APC_0: 0x0
10069 22:17:45.137692 INFO: [NOCDAPC] D12_APC_1: 0xfff
10070 22:17:45.140658 INFO: [NOCDAPC] D13_APC_0: 0x0
10071 22:17:45.144318 INFO: [NOCDAPC] D13_APC_1: 0xfff
10072 22:17:45.147343 INFO: [NOCDAPC] D14_APC_0: 0x0
10073 22:17:45.150677 INFO: [NOCDAPC] D14_APC_1: 0xfff
10074 22:17:45.153767 INFO: [NOCDAPC] D15_APC_0: 0x0
10075 22:17:45.156958 INFO: [NOCDAPC] D15_APC_1: 0xfff
10076 22:17:45.160724 INFO: [NOCDAPC] APC_CON: 0x4
10077 22:17:45.163743 INFO: [APUAPC] set_apusys_apc done
10078 22:17:45.166798 INFO: [DEVAPC] devapc_init done
10079 22:17:45.170165 INFO: GICv3 without legacy support detected.
10080 22:17:45.173670 INFO: ARM GICv3 driver initialized in EL3
10081 22:17:45.176811 INFO: Maximum SPI INTID supported: 639
10082 22:17:45.183682 INFO: BL31: Initializing runtime services
10083 22:17:45.186807 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10084 22:17:45.189869 INFO: SPM: enable CPC mode
10085 22:17:45.196502 INFO: mcdi ready for mcusys-off-idle and system suspend
10086 22:17:45.199866 INFO: BL31: Preparing for EL3 exit to normal world
10087 22:17:45.203022 INFO: Entry point address = 0x80000000
10088 22:17:45.206403 INFO: SPSR = 0x8
10089 22:17:45.212280
10090 22:17:45.212392
10091 22:17:45.212490
10092 22:17:45.215554 Starting depthcharge on Spherion...
10093 22:17:45.215655
10094 22:17:45.215750 Wipe memory regions:
10095 22:17:45.215838
10096 22:17:45.216630 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10097 22:17:45.216762 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10098 22:17:45.216868 Setting prompt string to ['asurada:']
10099 22:17:45.216982 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10100 22:17:45.218876 [0x00000040000000, 0x00000054600000)
10101 22:17:45.341267
10102 22:17:45.341426 [0x00000054660000, 0x00000080000000)
10103 22:17:45.601919
10104 22:17:45.602097 [0x000000821a7280, 0x000000ffe64000)
10105 22:17:46.346340
10106 22:17:46.346579 [0x00000100000000, 0x00000240000000)
10107 22:17:48.236592
10108 22:17:48.239773 Initializing XHCI USB controller at 0x11200000.
10109 22:17:49.277828
10110 22:17:49.280962 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10111 22:17:49.281054
10112 22:17:49.281121
10113 22:17:49.281184
10114 22:17:49.281466 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10116 22:17:49.381823 asurada: tftpboot 192.168.201.1 10597254/tftp-deploy-1g1shtyl/kernel/image.itb 10597254/tftp-deploy-1g1shtyl/kernel/cmdline
10117 22:17:49.381977 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10118 22:17:49.382060 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10119 22:17:49.386448 tftpboot 192.168.201.1 10597254/tftp-deploy-1g1shtyl/kernel/image.itp-deploy-1g1shtyl/kernel/cmdline
10120 22:17:49.386535
10121 22:17:49.386602 Waiting for link
10122 22:17:49.546896
10123 22:17:49.547032 R8152: Initializing
10124 22:17:49.547100
10125 22:17:49.550461 Version 9 (ocp_data = 6010)
10126 22:17:49.550546
10127 22:17:49.553804 R8152: Done initializing
10128 22:17:49.553888
10129 22:17:49.553961 Adding net device
10130 22:17:51.425753
10131 22:17:51.425889 done.
10132 22:17:51.425966
10133 22:17:51.426035 MAC: 00:e0:4c:72:2d:d6
10134 22:17:51.426096
10135 22:17:51.429021 Sending DHCP discover... done.
10136 22:17:51.429133
10137 22:17:51.432467 Waiting for reply... done.
10138 22:17:51.432550
10139 22:17:51.435541 Sending DHCP request... done.
10140 22:17:51.435633
10141 22:17:51.435712 Waiting for reply... done.
10142 22:17:51.435805
10143 22:17:51.438916 My ip is 192.168.201.21
10144 22:17:51.439000
10145 22:17:51.442098 The DHCP server ip is 192.168.201.1
10146 22:17:51.442183
10147 22:17:51.445678 TFTP server IP predefined by user: 192.168.201.1
10148 22:17:51.445763
10149 22:17:51.452362 Bootfile predefined by user: 10597254/tftp-deploy-1g1shtyl/kernel/image.itb
10150 22:17:51.452452
10151 22:17:51.455550 Sending tftp read request... done.
10152 22:17:51.455636
10153 22:17:51.458789 Waiting for the transfer...
10154 22:17:51.458909
10155 22:17:51.721634 00000000 ################################################################
10156 22:17:51.721772
10157 22:17:51.976384 00080000 ################################################################
10158 22:17:51.976520
10159 22:17:52.234626 00100000 ################################################################
10160 22:17:52.234800
10161 22:17:52.491462 00180000 ################################################################
10162 22:17:52.491625
10163 22:17:52.742440 00200000 ################################################################
10164 22:17:52.742582
10165 22:17:52.996707 00280000 ################################################################
10166 22:17:52.996858
10167 22:17:53.254297 00300000 ################################################################
10168 22:17:53.254458
10169 22:17:53.509970 00380000 ################################################################
10170 22:17:53.510134
10171 22:17:53.760295 00400000 ################################################################
10172 22:17:53.760437
10173 22:17:54.007716 00480000 ################################################################
10174 22:17:54.007855
10175 22:17:54.276647 00500000 ################################################################
10176 22:17:54.276793
10177 22:17:54.551877 00580000 ################################################################
10178 22:17:54.552011
10179 22:17:54.801527 00600000 ################################################################
10180 22:17:54.801677
10181 22:17:55.088542 00680000 ################################################################
10182 22:17:55.088666
10183 22:17:55.383669 00700000 ################################################################
10184 22:17:55.383802
10185 22:17:55.677687 00780000 ################################################################
10186 22:17:55.677854
10187 22:17:55.966778 00800000 ################################################################
10188 22:17:55.966911
10189 22:17:56.216571 00880000 ################################################################
10190 22:17:56.216704
10191 22:17:56.473121 00900000 ################################################################
10192 22:17:56.473263
10193 22:17:56.731658 00980000 ################################################################
10194 22:17:56.731805
10195 22:17:56.990839 00a00000 ################################################################
10196 22:17:56.990971
10197 22:17:57.243060 00a80000 ################################################################
10198 22:17:57.243214
10199 22:17:57.501364 00b00000 ################################################################
10200 22:17:57.501501
10201 22:17:57.751573 00b80000 ################################################################
10202 22:17:57.751708
10203 22:17:58.005587 00c00000 ################################################################
10204 22:17:58.005716
10205 22:17:58.259022 00c80000 ################################################################
10206 22:17:58.259159
10207 22:17:58.526476 00d00000 ################################################################
10208 22:17:58.526616
10209 22:17:58.797587 00d80000 ################################################################
10210 22:17:58.797729
10211 22:17:59.054955 00e00000 ################################################################
10212 22:17:59.055093
10213 22:17:59.309647 00e80000 ################################################################
10214 22:17:59.309784
10215 22:17:59.591006 00f00000 ################################################################
10216 22:17:59.591145
10217 22:17:59.863134 00f80000 ################################################################
10218 22:17:59.863293
10219 22:18:00.139639 01000000 ################################################################
10220 22:18:00.139812
10221 22:18:00.424254 01080000 ################################################################
10222 22:18:00.424391
10223 22:18:00.673833 01100000 ################################################################
10224 22:18:00.673973
10225 22:18:00.922828 01180000 ################################################################
10226 22:18:00.922960
10227 22:18:01.221853 01200000 ################################################################
10228 22:18:01.222420
10229 22:18:01.601454 01280000 ################################################################
10230 22:18:01.601988
10231 22:18:01.888130 01300000 ################################################################
10232 22:18:01.888278
10233 22:18:02.137678 01380000 ################################################################
10234 22:18:02.137820
10235 22:18:02.393342 01400000 ################################################################
10236 22:18:02.393481
10237 22:18:02.661347 01480000 ################################################################
10238 22:18:02.661501
10239 22:18:02.958092 01500000 ################################################################
10240 22:18:02.958237
10241 22:18:03.254135 01580000 ################################################################
10242 22:18:03.254320
10243 22:18:03.544681 01600000 ################################################################
10244 22:18:03.544871
10245 22:18:03.836741 01680000 ################################################################
10246 22:18:03.836920
10247 22:18:04.119198 01700000 ################################################################
10248 22:18:04.119330
10249 22:18:04.370801 01780000 ################################################################
10250 22:18:04.370964
10251 22:18:04.635132 01800000 ################################################################
10252 22:18:04.635302
10253 22:18:04.894633 01880000 ################################################################
10254 22:18:04.894765
10255 22:18:05.178576 01900000 ################################################################
10256 22:18:05.178709
10257 22:18:05.455720 01980000 ################################################################
10258 22:18:05.455859
10259 22:18:05.716668 01a00000 ############################################################### done.
10260 22:18:05.716866
10261 22:18:05.720088 The bootfile was 27776174 bytes long.
10262 22:18:05.720177
10263 22:18:05.723322 Sending tftp read request... done.
10264 22:18:05.723506
10265 22:18:05.723607 Waiting for the transfer...
10266 22:18:05.723698
10267 22:18:05.726624 00000000 # done.
10268 22:18:05.726730
10269 22:18:05.733330 Command line loaded dynamically from TFTP file: 10597254/tftp-deploy-1g1shtyl/kernel/cmdline
10270 22:18:05.733531
10271 22:18:05.753008 The command line is: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/10597254/extract-nfsrootfs-j4uzvb9s,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10272 22:18:05.753263
10273 22:18:05.756392 Loading FIT.
10274 22:18:05.756728
10275 22:18:05.759622 Image ramdisk-1 has 17644909 bytes.
10276 22:18:05.759911
10277 22:18:05.760104 Image fdt-1 has 46924 bytes.
10278 22:18:05.760266
10279 22:18:05.762984 Image kernel-1 has 10082307 bytes.
10280 22:18:05.763313
10281 22:18:05.772972 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10282 22:18:05.773472
10283 22:18:05.789570 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10284 22:18:05.790179
10285 22:18:05.795997 Choosing best match conf-1 for compat google,spherion-rev2.
10286 22:18:05.799984
10287 22:18:05.804444 Connected to device vid:did:rid of 1ae0:0028:00
10288 22:18:05.811217
10289 22:18:05.814376 tpm_get_response: command 0x17b, return code 0x0
10290 22:18:05.814548
10291 22:18:05.817620 ec_init: CrosEC protocol v3 supported (256, 248)
10292 22:18:05.821698
10293 22:18:05.824822 tpm_cleanup: add release locality here.
10294 22:18:05.825003
10295 22:18:05.825097 Shutting down all USB controllers.
10296 22:18:05.828519
10297 22:18:05.828711 Removing current net device
10298 22:18:05.828830
10299 22:18:05.835134 Exiting depthcharge with code 4 at timestamp: 49927176
10300 22:18:05.835365
10301 22:18:05.838180 LZMA decompressing kernel-1 to 0x821a6718
10302 22:18:05.838397
10303 22:18:05.841635 LZMA decompressing kernel-1 to 0x40000000
10304 22:18:07.108705
10305 22:18:07.109323 jumping to kernel
10306 22:18:07.110925 end: 2.2.4 bootloader-commands (duration 00:00:22) [common]
10307 22:18:07.111490 start: 2.2.5 auto-login-action (timeout 00:04:03) [common]
10308 22:18:07.111919 Setting prompt string to ['Linux version [0-9]']
10309 22:18:07.112314 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10310 22:18:07.112703 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10311 22:18:07.191561
10312 22:18:07.194583 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10313 22:18:07.198217 start: 2.2.5.1 login-action (timeout 00:04:03) [common]
10314 22:18:07.198768 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10315 22:18:07.199240 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10316 22:18:07.199677 Using line separator: #'\n'#
10317 22:18:07.200036 No login prompt set.
10318 22:18:07.200391 Parsing kernel messages
10319 22:18:07.200798 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10320 22:18:07.201590 [login-action] Waiting for messages, (timeout 00:04:03)
10321 22:18:07.217712 [ 0.000000] Linux version 6.1.31 (KernelCI@build-j1612341-arm64-gcc-10-defconfig-arm64-chromebook-n674v) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Mon Jun 5 22:04:07 UTC 2023
10322 22:18:07.221528 [ 0.000000] random: crng init done
10323 22:18:07.227742 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10324 22:18:07.230954 [ 0.000000] efi: UEFI not found.
10325 22:18:07.237662 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10326 22:18:07.244287 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10327 22:18:07.253984 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10328 22:18:07.264009 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10329 22:18:07.270880 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10330 22:18:07.277176 [ 0.000000] printk: bootconsole [mtk8250] enabled
10331 22:18:07.283831 [ 0.000000] NUMA: No NUMA configuration found
10332 22:18:07.290573 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10333 22:18:07.293666 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcda00-0x23efcffff]
10334 22:18:07.297339 [ 0.000000] Zone ranges:
10335 22:18:07.303854 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10336 22:18:07.306713 [ 0.000000] DMA32 empty
10337 22:18:07.313402 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10338 22:18:07.317088 [ 0.000000] Movable zone start for each node
10339 22:18:07.320196 [ 0.000000] Early memory node ranges
10340 22:18:07.326890 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10341 22:18:07.333767 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10342 22:18:07.339796 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10343 22:18:07.346574 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10344 22:18:07.353058 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10345 22:18:07.359582 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10346 22:18:07.415209 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10347 22:18:07.421825 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10348 22:18:07.428636 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10349 22:18:07.432204 [ 0.000000] psci: probing for conduit method from DT.
10350 22:18:07.438247 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10351 22:18:07.441417 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10352 22:18:07.448318 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10353 22:18:07.451530 [ 0.000000] psci: SMC Calling Convention v1.2
10354 22:18:07.458561 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10355 22:18:07.461103 [ 0.000000] Detected VIPT I-cache on CPU0
10356 22:18:07.467790 [ 0.000000] CPU features: detected: GIC system register CPU interface
10357 22:18:07.474205 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10358 22:18:07.481065 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10359 22:18:07.488047 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10360 22:18:07.497320 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10361 22:18:07.504031 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10362 22:18:07.507415 [ 0.000000] alternatives: applying boot alternatives
10363 22:18:07.513958 [ 0.000000] Fallback order for Node 0: 0
10364 22:18:07.520883 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10365 22:18:07.523774 [ 0.000000] Policy zone: Normal
10366 22:18:07.543853 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/10597254/extract-nfsrootfs-j4uzvb9s,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10367 22:18:07.553901 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10368 22:18:07.565540 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10369 22:18:07.575875 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10370 22:18:07.582109 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10371 22:18:07.585435 <6>[ 0.000000] software IO TLB: area num 8.
10372 22:18:07.642209 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10373 22:18:07.791273 <6>[ 0.000000] Memory: 7955716K/8385536K available (17984K kernel code, 4098K rwdata, 14068K rodata, 8384K init, 615K bss, 397052K reserved, 32768K cma-reserved)
10374 22:18:07.797826 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10375 22:18:07.804366 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10376 22:18:07.807861 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10377 22:18:07.814446 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10378 22:18:07.821050 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10379 22:18:07.824206 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10380 22:18:07.834443 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10381 22:18:07.841149 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10382 22:18:07.847152 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10383 22:18:07.853666 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10384 22:18:07.856961 <6>[ 0.000000] GICv3: 608 SPIs implemented
10385 22:18:07.861002 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10386 22:18:07.866986 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10387 22:18:07.870436 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10388 22:18:07.877060 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10389 22:18:07.890163 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10390 22:18:07.903443 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10391 22:18:07.910527 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10392 22:18:07.917911 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10393 22:18:07.931471 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10394 22:18:07.937637 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10395 22:18:07.944862 <6>[ 0.009180] Console: colour dummy device 80x25
10396 22:18:07.954283 <6>[ 0.013906] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10397 22:18:07.961152 <6>[ 0.024347] pid_max: default: 32768 minimum: 301
10398 22:18:07.964053 <6>[ 0.029251] LSM: Security Framework initializing
10399 22:18:07.970875 <6>[ 0.034189] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10400 22:18:07.981184 <6>[ 0.042050] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10401 22:18:07.990840 <6>[ 0.051481] cblist_init_generic: Setting adjustable number of callback queues.
10402 22:18:07.994142 <6>[ 0.058935] cblist_init_generic: Setting shift to 3 and lim to 1.
10403 22:18:08.000724 <6>[ 0.065313] cblist_init_generic: Setting shift to 3 and lim to 1.
10404 22:18:08.007639 <6>[ 0.071722] rcu: Hierarchical SRCU implementation.
10405 22:18:08.013987 <6>[ 0.076735] rcu: Max phase no-delay instances is 1000.
10406 22:18:08.017077 <6>[ 0.083753] EFI services will not be available.
10407 22:18:08.023693 <6>[ 0.088725] smp: Bringing up secondary CPUs ...
10408 22:18:08.031435 <6>[ 0.093809] Detected VIPT I-cache on CPU1
10409 22:18:08.038045 <6>[ 0.093882] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10410 22:18:08.044441 <6>[ 0.093912] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10411 22:18:08.047810 <6>[ 0.094248] Detected VIPT I-cache on CPU2
10412 22:18:08.054795 <6>[ 0.094303] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10413 22:18:08.064438 <6>[ 0.094319] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10414 22:18:08.067811 <6>[ 0.094580] Detected VIPT I-cache on CPU3
10415 22:18:08.074412 <6>[ 0.094630] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10416 22:18:08.080940 <6>[ 0.094645] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10417 22:18:08.084560 <6>[ 0.094953] CPU features: detected: Spectre-v4
10418 22:18:08.091243 <6>[ 0.094960] CPU features: detected: Spectre-BHB
10419 22:18:08.094149 <6>[ 0.094965] Detected PIPT I-cache on CPU4
10420 22:18:08.100800 <6>[ 0.095023] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10421 22:18:08.107422 <6>[ 0.095039] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10422 22:18:08.113962 <6>[ 0.095337] Detected PIPT I-cache on CPU5
10423 22:18:08.120744 <6>[ 0.095401] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10424 22:18:08.127311 <6>[ 0.095417] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10425 22:18:08.130852 <6>[ 0.095701] Detected PIPT I-cache on CPU6
10426 22:18:08.137418 <6>[ 0.095766] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10427 22:18:08.143957 <6>[ 0.095783] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10428 22:18:08.150432 <6>[ 0.096081] Detected PIPT I-cache on CPU7
10429 22:18:08.157043 <6>[ 0.096146] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10430 22:18:08.163625 <6>[ 0.096162] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10431 22:18:08.166738 <6>[ 0.096209] smp: Brought up 1 node, 8 CPUs
10432 22:18:08.173579 <6>[ 0.237508] SMP: Total of 8 processors activated.
10433 22:18:08.177082 <6>[ 0.242459] CPU features: detected: 32-bit EL0 Support
10434 22:18:08.187058 <6>[ 0.247856] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10435 22:18:08.193384 <6>[ 0.256656] CPU features: detected: Common not Private translations
10436 22:18:08.200213 <6>[ 0.263172] CPU features: detected: CRC32 instructions
10437 22:18:08.204128 <6>[ 0.268524] CPU features: detected: RCpc load-acquire (LDAPR)
10438 22:18:08.210257 <6>[ 0.274484] CPU features: detected: LSE atomic instructions
10439 22:18:08.216617 <6>[ 0.280266] CPU features: detected: Privileged Access Never
10440 22:18:08.223512 <6>[ 0.286045] CPU features: detected: RAS Extension Support
10441 22:18:08.230161 <6>[ 0.291654] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10442 22:18:08.233292 <6>[ 0.298876] CPU: All CPU(s) started at EL2
10443 22:18:08.240124 <6>[ 0.303193] alternatives: applying system-wide alternatives
10444 22:18:08.248979 <6>[ 0.313904] devtmpfs: initialized
10445 22:18:08.264948 <6>[ 0.322872] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10446 22:18:08.271127 <6>[ 0.332836] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10447 22:18:08.277876 <6>[ 0.341073] pinctrl core: initialized pinctrl subsystem
10448 22:18:08.281440 <6>[ 0.347722] DMI not present or invalid.
10449 22:18:08.287421 <6>[ 0.352130] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10450 22:18:08.297901 <6>[ 0.359026] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10451 22:18:08.304954 <6>[ 0.366613] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10452 22:18:08.314577 <6>[ 0.374841] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10453 22:18:08.317460 <6>[ 0.383081] audit: initializing netlink subsys (disabled)
10454 22:18:08.327677 <5>[ 0.388776] audit: type=2000 audit(0.276:1): state=initialized audit_enabled=0 res=1
10455 22:18:08.334442 <6>[ 0.389473] thermal_sys: Registered thermal governor 'step_wise'
10456 22:18:08.340907 <6>[ 0.396742] thermal_sys: Registered thermal governor 'power_allocator'
10457 22:18:08.343782 <6>[ 0.402998] cpuidle: using governor menu
10458 22:18:08.350288 <6>[ 0.413958] NET: Registered PF_QIPCRTR protocol family
10459 22:18:08.357393 <6>[ 0.419449] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10460 22:18:08.363623 <6>[ 0.426551] ASID allocator initialised with 32768 entries
10461 22:18:08.366919 <6>[ 0.433115] Serial: AMBA PL011 UART driver
10462 22:18:08.376618 <4>[ 0.441773] Trying to register duplicate clock ID: 134
10463 22:18:08.432932 <6>[ 0.501235] KASLR enabled
10464 22:18:08.447422 <6>[ 0.509020] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10465 22:18:08.454395 <6>[ 0.516034] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10466 22:18:08.460359 <6>[ 0.522520] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10467 22:18:08.467220 <6>[ 0.529526] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10468 22:18:08.473449 <6>[ 0.536014] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10469 22:18:08.480607 <6>[ 0.543018] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10470 22:18:08.487377 <6>[ 0.549505] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10471 22:18:08.493602 <6>[ 0.556510] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10472 22:18:08.496802 <6>[ 0.564049] ACPI: Interpreter disabled.
10473 22:18:08.505545 <6>[ 0.570444] iommu: Default domain type: Translated
10474 22:18:08.512007 <6>[ 0.575556] iommu: DMA domain TLB invalidation policy: strict mode
10475 22:18:08.515700 <5>[ 0.582214] SCSI subsystem initialized
10476 22:18:08.521983 <6>[ 0.586380] usbcore: registered new interface driver usbfs
10477 22:18:08.528612 <6>[ 0.592115] usbcore: registered new interface driver hub
10478 22:18:08.531878 <6>[ 0.597668] usbcore: registered new device driver usb
10479 22:18:08.538965 <6>[ 0.603751] pps_core: LinuxPPS API ver. 1 registered
10480 22:18:08.548653 <6>[ 0.608945] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10481 22:18:08.551947 <6>[ 0.618294] PTP clock support registered
10482 22:18:08.555214 <6>[ 0.622533] EDAC MC: Ver: 3.0.0
10483 22:18:08.562727 <6>[ 0.627670] FPGA manager framework
10484 22:18:08.569317 <6>[ 0.631349] Advanced Linux Sound Architecture Driver Initialized.
10485 22:18:08.572318 <6>[ 0.638118] vgaarb: loaded
10486 22:18:08.579014 <6>[ 0.641304] clocksource: Switched to clocksource arch_sys_counter
10487 22:18:08.582464 <5>[ 0.647744] VFS: Disk quotas dquot_6.6.0
10488 22:18:08.589011 <6>[ 0.651925] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10489 22:18:08.592198 <6>[ 0.659113] pnp: PnP ACPI: disabled
10490 22:18:08.601142 <6>[ 0.665863] NET: Registered PF_INET protocol family
10491 22:18:08.611061 <6>[ 0.671464] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10492 22:18:08.622058 <6>[ 0.683760] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10493 22:18:08.632302 <6>[ 0.692573] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10494 22:18:08.638956 <6>[ 0.700541] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10495 22:18:08.648579 <6>[ 0.709241] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10496 22:18:08.655460 <6>[ 0.718986] TCP: Hash tables configured (established 65536 bind 65536)
10497 22:18:08.661593 <6>[ 0.725843] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10498 22:18:08.672016 <6>[ 0.733040] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10499 22:18:08.678430 <6>[ 0.740739] NET: Registered PF_UNIX/PF_LOCAL protocol family
10500 22:18:08.681619 <6>[ 0.746903] RPC: Registered named UNIX socket transport module.
10501 22:18:08.688165 <6>[ 0.753056] RPC: Registered udp transport module.
10502 22:18:08.691477 <6>[ 0.757986] RPC: Registered tcp transport module.
10503 22:18:08.698419 <6>[ 0.762917] RPC: Registered tcp NFSv4.1 backchannel transport module.
10504 22:18:08.704924 <6>[ 0.769586] PCI: CLS 0 bytes, default 64
10505 22:18:08.708081 <6>[ 0.773928] Unpacking initramfs...
10506 22:18:08.724662 <6>[ 0.785912] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10507 22:18:08.734084 <6>[ 0.794560] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10508 22:18:08.737387 <6>[ 0.803402] kvm [1]: IPA Size Limit: 40 bits
10509 22:18:08.744338 <6>[ 0.807930] kvm [1]: GICv3: no GICV resource entry
10510 22:18:08.747338 <6>[ 0.812951] kvm [1]: disabling GICv2 emulation
10511 22:18:08.754250 <6>[ 0.817639] kvm [1]: GIC system register CPU interface enabled
10512 22:18:08.757282 <6>[ 0.823809] kvm [1]: vgic interrupt IRQ18
10513 22:18:08.764211 <6>[ 0.828169] kvm [1]: VHE mode initialized successfully
10514 22:18:08.770432 <5>[ 0.834595] Initialise system trusted keyrings
10515 22:18:08.777110 <6>[ 0.839411] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10516 22:18:08.784355 <6>[ 0.849421] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10517 22:18:08.790962 <5>[ 0.855803] NFS: Registering the id_resolver key type
10518 22:18:08.794338 <5>[ 0.861118] Key type id_resolver registered
10519 22:18:08.800938 <5>[ 0.865533] Key type id_legacy registered
10520 22:18:08.807797 <6>[ 0.869816] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10521 22:18:08.814610 <6>[ 0.876738] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10522 22:18:08.821304 <6>[ 0.884459] 9p: Installing v9fs 9p2000 file system support
10523 22:18:08.857567 <5>[ 0.922148] Key type asymmetric registered
10524 22:18:08.860274 <5>[ 0.926479] Asymmetric key parser 'x509' registered
10525 22:18:08.870531 <6>[ 0.931623] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10526 22:18:08.873447 <6>[ 0.939238] io scheduler mq-deadline registered
10527 22:18:08.876646 <6>[ 0.944000] io scheduler kyber registered
10528 22:18:08.896241 <6>[ 0.961021] EINJ: ACPI disabled.
10529 22:18:08.928888 <4>[ 0.987247] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10530 22:18:08.938817 <4>[ 0.997899] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10531 22:18:08.954159 <6>[ 1.018930] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10532 22:18:08.961942 <6>[ 1.026970] printk: console [ttyS0] disabled
10533 22:18:08.990309 <6>[ 1.051614] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10534 22:18:08.996285 <6>[ 1.061089] printk: console [ttyS0] enabled
10535 22:18:08.999730 <6>[ 1.061089] printk: console [ttyS0] enabled
10536 22:18:09.006362 <6>[ 1.069986] printk: bootconsole [mtk8250] disabled
10537 22:18:09.010016 <6>[ 1.069986] printk: bootconsole [mtk8250] disabled
10538 22:18:09.016805 <6>[ 1.081268] SuperH (H)SCI(F) driver initialized
10539 22:18:09.019607 <6>[ 1.086553] msm_serial: driver initialized
10540 22:18:09.033673 <6>[ 1.095467] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10541 22:18:09.044011 <6>[ 1.104013] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10542 22:18:09.050671 <6>[ 1.112559] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10543 22:18:09.060536 <6>[ 1.121188] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10544 22:18:09.070225 <6>[ 1.129896] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10545 22:18:09.076604 <6>[ 1.138617] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10546 22:18:09.086862 <6>[ 1.147160] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10547 22:18:09.093186 <6>[ 1.155952] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10548 22:18:09.103226 <6>[ 1.164495] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10549 22:18:09.115288 <6>[ 1.180114] loop: module loaded
10550 22:18:09.121696 <6>[ 1.186189] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10551 22:18:09.144599 <4>[ 1.209801] mtk-pmic-keys: Failed to locate of_node [id: -1]
10552 22:18:09.152083 <6>[ 1.216802] megasas: 07.719.03.00-rc1
10553 22:18:09.161240 <6>[ 1.226483] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10554 22:18:09.168706 <6>[ 1.232688] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10555 22:18:09.184563 <6>[ 1.249251] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10556 22:18:09.244679 <6>[ 1.303032] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10557 22:18:09.433004 <6>[ 1.497728] Freeing initrd memory: 17224K
10558 22:18:09.443118 <6>[ 1.508023] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10559 22:18:09.453895 <6>[ 1.518845] tun: Universal TUN/TAP device driver, 1.6
10560 22:18:09.457067 <6>[ 1.524915] thunder_xcv, ver 1.0
10561 22:18:09.460343 <6>[ 1.528418] thunder_bgx, ver 1.0
10562 22:18:09.463632 <6>[ 1.531916] nicpf, ver 1.0
10563 22:18:09.474214 <6>[ 1.535945] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10564 22:18:09.477474 <6>[ 1.543421] hns3: Copyright (c) 2017 Huawei Corporation.
10565 22:18:09.480975 <6>[ 1.549013] hclge is initializing
10566 22:18:09.487786 <6>[ 1.552589] e1000: Intel(R) PRO/1000 Network Driver
10567 22:18:09.493991 <6>[ 1.557718] e1000: Copyright (c) 1999-2006 Intel Corporation.
10568 22:18:09.497418 <6>[ 1.563732] e1000e: Intel(R) PRO/1000 Network Driver
10569 22:18:09.503997 <6>[ 1.568949] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10570 22:18:09.510510 <6>[ 1.575137] igb: Intel(R) Gigabit Ethernet Network Driver
10571 22:18:09.517607 <6>[ 1.580788] igb: Copyright (c) 2007-2014 Intel Corporation.
10572 22:18:09.523836 <6>[ 1.586625] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10573 22:18:09.530836 <6>[ 1.593142] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10574 22:18:09.533796 <6>[ 1.599603] sky2: driver version 1.30
10575 22:18:09.540447 <6>[ 1.604586] VFIO - User Level meta-driver version: 0.3
10576 22:18:09.547749 <6>[ 1.612801] usbcore: registered new interface driver usb-storage
10577 22:18:09.554385 <6>[ 1.619254] usbcore: registered new device driver onboard-usb-hub
10578 22:18:09.563415 <6>[ 1.628323] mt6397-rtc mt6359-rtc: registered as rtc0
10579 22:18:09.573118 <6>[ 1.633791] mt6397-rtc mt6359-rtc: setting system clock to 2023-06-05T22:18:11 UTC (1686003491)
10580 22:18:09.576242 <6>[ 1.643371] i2c_dev: i2c /dev entries driver
10581 22:18:09.593298 <6>[ 1.655044] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10582 22:18:09.600104 <6>[ 1.665239] sdhci: Secure Digital Host Controller Interface driver
10583 22:18:09.606821 <6>[ 1.671678] sdhci: Copyright(c) Pierre Ossman
10584 22:18:09.613587 <6>[ 1.677077] Synopsys Designware Multimedia Card Interface Driver
10585 22:18:09.616836 <6>[ 1.683692] mmc0: CQHCI version 5.10
10586 22:18:09.623483 <6>[ 1.684233] sdhci-pltfm: SDHCI platform and OF driver helper
10587 22:18:09.630604 <6>[ 1.695549] ledtrig-cpu: registered to indicate activity on CPUs
10588 22:18:09.641393 <6>[ 1.702888] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10589 22:18:09.644467 <6>[ 1.710283] usbcore: registered new interface driver usbhid
10590 22:18:09.650785 <6>[ 1.716115] usbhid: USB HID core driver
10591 22:18:09.657530 <6>[ 1.720358] spi_master spi0: will run message pump with realtime priority
10592 22:18:09.701307 <6>[ 1.759801] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10593 22:18:09.720388 <6>[ 1.774897] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10594 22:18:09.723216 <6>[ 1.788486] mmc0: Command Queue Engine enabled
10595 22:18:09.730338 <6>[ 1.790689] cros-ec-spi spi0.0: Chrome EC device registered
10596 22:18:09.736728 <6>[ 1.793218] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10597 22:18:09.740828 <6>[ 1.806331] mmcblk0: mmc0:0001 DA4128 116 GiB
10598 22:18:09.755276 <6>[ 1.816686] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10599 22:18:09.761750 <6>[ 1.818338] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10600 22:18:09.768142 <6>[ 1.828115] NET: Registered PF_PACKET protocol family
10601 22:18:09.772180 <6>[ 1.833144] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10602 22:18:09.777946 <6>[ 1.837342] 9pnet: Installing 9P2000 support
10603 22:18:09.781153 <6>[ 1.843080] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10604 22:18:09.787989 <5>[ 1.847017] Key type dns_resolver registered
10605 22:18:09.794272 <6>[ 1.852888] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10606 22:18:09.797712 <6>[ 1.857242] registered taskstats version 1
10607 22:18:09.801097 <5>[ 1.867650] Loading compiled-in X.509 certificates
10608 22:18:09.836893 <4>[ 1.895243] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10609 22:18:09.846890 <4>[ 1.906005] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10610 22:18:09.857344 <3>[ 1.919052] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10611 22:18:09.870061 <6>[ 1.934980] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10612 22:18:09.877148 <6>[ 1.941891] xhci-mtk 11200000.usb: xHCI Host Controller
10613 22:18:09.883278 <6>[ 1.947412] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10614 22:18:09.893673 <6>[ 1.955381] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10615 22:18:09.900279 <6>[ 1.964824] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10616 22:18:09.906991 <6>[ 1.970921] xhci-mtk 11200000.usb: xHCI Host Controller
10617 22:18:09.913330 <6>[ 1.976403] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10618 22:18:09.920181 <6>[ 1.984056] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10619 22:18:09.927184 <6>[ 1.991940] hub 1-0:1.0: USB hub found
10620 22:18:09.930451 <6>[ 1.995976] hub 1-0:1.0: 1 port detected
10621 22:18:09.940589 <6>[ 2.000318] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10622 22:18:09.943154 <6>[ 2.009116] hub 2-0:1.0: USB hub found
10623 22:18:09.946888 <6>[ 2.013148] hub 2-0:1.0: 1 port detected
10624 22:18:09.955386 <6>[ 2.020329] mtk-msdc 11f70000.mmc: Got CD GPIO
10625 22:18:09.972162 <6>[ 2.033925] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10626 22:18:09.979229 <6>[ 2.042047] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10627 22:18:09.988905 <4>[ 2.050020] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10628 22:18:09.998566 <6>[ 2.059724] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10629 22:18:10.005747 <6>[ 2.067811] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10630 22:18:10.015429 <6>[ 2.075873] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10631 22:18:10.021914 <6>[ 2.083792] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10632 22:18:10.028533 <6>[ 2.091648] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10633 22:18:10.038630 <6>[ 2.099473] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10634 22:18:10.048589 <6>[ 2.110264] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10635 22:18:10.058885 <6>[ 2.118626] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10636 22:18:10.065108 <6>[ 2.127019] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10637 22:18:10.074899 <6>[ 2.135371] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10638 22:18:10.081572 <6>[ 2.143744] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10639 22:18:10.091571 <6>[ 2.152090] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10640 22:18:10.098035 <6>[ 2.160459] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10641 22:18:10.108336 <6>[ 2.168803] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10642 22:18:10.115315 <6>[ 2.177168] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10643 22:18:10.124682 <6>[ 2.185512] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10644 22:18:10.131617 <6>[ 2.193855] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10645 22:18:10.141374 <6>[ 2.202199] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10646 22:18:10.148139 <6>[ 2.210550] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10647 22:18:10.158063 <6>[ 2.218894] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10648 22:18:10.164056 <6>[ 2.227238] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10649 22:18:10.171208 <6>[ 2.236144] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10650 22:18:10.178591 <6>[ 2.243582] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10651 22:18:10.185489 <6>[ 2.250656] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10652 22:18:10.196155 <6>[ 2.257792] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10653 22:18:10.202711 <6>[ 2.265098] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10654 22:18:10.212510 <6>[ 2.272014] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10655 22:18:10.219259 <6>[ 2.281154] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10656 22:18:10.229190 <6>[ 2.290323] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10657 22:18:10.239118 <6>[ 2.299737] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10658 22:18:10.248888 <6>[ 2.309216] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10659 22:18:10.258911 <6>[ 2.318691] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10660 22:18:10.268682 <6>[ 2.327817] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10661 22:18:10.275259 <6>[ 2.337295] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10662 22:18:10.285495 <6>[ 2.346422] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10663 22:18:10.295753 <6>[ 2.355728] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10664 22:18:10.304911 <6>[ 2.365914] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10665 22:18:10.316224 <6>[ 2.377850] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10666 22:18:10.323120 <6>[ 2.387765] Trying to probe devices needed for running init ...
10667 22:18:10.363368 <6>[ 2.425581] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10668 22:18:10.517639 <6>[ 2.582837] hub 1-1:1.0: USB hub found
10669 22:18:10.521291 <6>[ 2.587288] hub 1-1:1.0: 4 ports detected
10670 22:18:10.644312 <6>[ 2.705773] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10671 22:18:10.669421 <6>[ 2.734116] hub 2-1:1.0: USB hub found
10672 22:18:10.672374 <6>[ 2.738516] hub 2-1:1.0: 3 ports detected
10673 22:18:10.839620 <6>[ 2.901608] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10674 22:18:10.972912 <6>[ 3.037918] hub 1-1.4:1.0: USB hub found
10675 22:18:10.976019 <6>[ 3.042568] hub 1-1.4:1.0: 2 ports detected
10676 22:18:11.051937 <6>[ 3.113824] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10677 22:18:11.275658 <6>[ 3.337576] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10678 22:18:11.467456 <6>[ 3.529576] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10679 22:18:22.596226 <6>[ 14.666169] ALSA device list:
10680 22:18:22.602771 <6>[ 14.669433] No soundcards found.
10681 22:18:22.610023 <6>[ 14.676689] Freeing unused kernel memory: 8384K
10682 22:18:22.612980 <6>[ 14.681614] Run /init as init process
10683 22:18:22.622149 Loading, please wait...
10684 22:18:22.639850 Starting version 247.3-7+deb11u2
10685 22:18:22.964754 <6>[ 15.028512] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10686 22:18:22.973920 <6>[ 15.041227] remoteproc remoteproc0: scp is available
10687 22:18:22.984188 <4>[ 15.046636] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10688 22:18:22.990501 <6>[ 15.056495] remoteproc remoteproc0: powering up scp
10689 22:18:22.997185 <3>[ 15.059262] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10690 22:18:23.003687 <6>[ 15.062608] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10691 22:18:23.013717 <4>[ 15.062824] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10692 22:18:23.020689 <3>[ 15.062838] remoteproc remoteproc0: request_firmware failed: -2
10693 22:18:23.030087 <6>[ 15.067071] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10694 22:18:23.037230 <3>[ 15.069821] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10695 22:18:23.046973 <6>[ 15.080319] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10696 22:18:23.053656 <3>[ 15.087311] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10697 22:18:23.060197 <4>[ 15.093805] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10698 22:18:23.067002 <6>[ 15.094952] usbcore: registered new interface driver r8152
10699 22:18:23.076855 <6>[ 15.097651] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10700 22:18:23.083346 <3>[ 15.103920] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10701 22:18:23.090523 <4>[ 15.109727] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10702 22:18:23.099900 <3>[ 15.119561] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10703 22:18:23.103225 <6>[ 15.125818] mc: Linux media interface: v0.10
10704 22:18:23.113301 <4>[ 15.135927] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10705 22:18:23.116482 <4>[ 15.135927] Fallback method does not support PEC.
10706 22:18:23.127032 <3>[ 15.139167] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10707 22:18:23.133165 <3>[ 15.197682] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10708 22:18:23.142876 <6>[ 15.199029] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10709 22:18:23.149670 <3>[ 15.205911] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10710 22:18:23.156550 <3>[ 15.206046] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10711 22:18:23.163213 <6>[ 15.219263] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10712 22:18:23.173233 <6>[ 15.220859] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10713 22:18:23.183728 <3>[ 15.221588] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10714 22:18:23.190434 <6>[ 15.221860] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10715 22:18:23.200204 <3>[ 15.225283] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10716 22:18:23.206896 <6>[ 15.229283] pci_bus 0000:00: root bus resource [bus 00-ff]
10717 22:18:23.216563 <4>[ 15.232285] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10718 22:18:23.223172 <4>[ 15.232294] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10719 22:18:23.229980 <3>[ 15.236280] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10720 22:18:23.236531 <3>[ 15.236408] elants_i2c 4-0010: invalid 'hello' packet: ff ff ff ff
10721 22:18:23.246296 <6>[ 15.246372] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10722 22:18:23.252800 <3>[ 15.248710] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10723 22:18:23.262876 <3>[ 15.254404] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10724 22:18:23.272596 <6>[ 15.263439] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10725 22:18:23.279158 <3>[ 15.272275] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10726 22:18:23.286099 <6>[ 15.278079] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10727 22:18:23.289423 <6>[ 15.285424] r8152 2-1.3:1.0 eth0: v1.12.13
10728 22:18:23.299190 <3>[ 15.286981] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10729 22:18:23.305869 <3>[ 15.286988] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10730 22:18:23.315793 <3>[ 15.286997] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10731 22:18:23.322609 <6>[ 15.295090] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10732 22:18:23.329038 <3>[ 15.303155] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10733 22:18:23.335651 <6>[ 15.309652] pci 0000:00:00.0: supports D1 D2
10734 22:18:23.341997 <3>[ 15.316735] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10735 22:18:23.348596 <6>[ 15.325482] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10736 22:18:23.355270 <3>[ 15.333556] elants_i2c 4-0010: invalid 'hello' packet: ff ff ff ff
10737 22:18:23.366031 <6>[ 15.429798] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10738 22:18:23.372686 <6>[ 15.438189] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10739 22:18:23.379064 <3>[ 15.441648] elants_i2c 4-0010: invalid 'hello' packet: ff ff ff ff
10740 22:18:23.386400 <6>[ 15.444480] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10741 22:18:23.392242 <3>[ 15.451262] elants_i2c 4-0010: (read fw id) unexpected response: ff ff
10742 22:18:23.402381 <6>[ 15.458364] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10743 22:18:23.408990 <6>[ 15.465249] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10744 22:18:23.418979 <6>[ 15.472624] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10745 22:18:23.422527 <6>[ 15.489544] pci 0000:01:00.0: supports D1 D2
10746 22:18:23.428884 <6>[ 15.490399] videodev: Linux video capture interface: v2.00
10747 22:18:23.435537 <6>[ 15.494080] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10748 22:18:23.441895 <6>[ 15.494509] usbcore: registered new interface driver cdc_ether
10749 22:18:23.448281 <6>[ 15.500199] usbcore: registered new interface driver r8153_ecm
10750 22:18:23.451784 <6>[ 15.513762] Bluetooth: Core ver 2.22
10751 22:18:23.458503 <6>[ 15.517514] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10752 22:18:23.465007 <6>[ 15.517548] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10753 22:18:23.474626 <6>[ 15.517557] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10754 22:18:23.481352 <6>[ 15.517569] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10755 22:18:23.491372 <6>[ 15.517585] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10756 22:18:23.498335 <6>[ 15.517601] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10757 22:18:23.504610 <6>[ 15.517616] pci 0000:00:00.0: PCI bridge to [bus 01]
10758 22:18:23.511519 <6>[ 15.517624] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10759 22:18:23.517687 <6>[ 15.517795] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10760 22:18:23.524557 <6>[ 15.518670] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10761 22:18:23.530985 <6>[ 15.519354] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10762 22:18:23.534566 <6>[ 15.522823] NET: Registered PF_BLUETOOTH protocol family
10763 22:18:23.541081 <6>[ 15.528132] r8152 2-1.3:1.0 enx00e04c722dd6: renamed from eth0
10764 22:18:23.547585 <6>[ 15.548129] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10765 22:18:23.554164 <6>[ 15.553798] Bluetooth: HCI device and connection manager initialized
10766 22:18:23.567387 <6>[ 15.563346] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10767 22:18:23.573798 <6>[ 15.569768] Bluetooth: HCI socket layer initialized
10768 22:18:23.577027 <6>[ 15.570513] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10769 22:18:23.583675 <6>[ 15.575220] usbcore: registered new interface driver uvcvideo
10770 22:18:23.590667 <6>[ 15.582964] Bluetooth: L2CAP socket layer initialized
10771 22:18:23.593381 <6>[ 15.582981] Bluetooth: SCO socket layer initialized
10772 22:18:23.605382 <6>[ 15.671738] usbcore: registered new interface driver btusb
10773 22:18:23.617934 <4>[ 15.678251] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10774 22:18:23.624540 <5>[ 15.687102] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10775 22:18:23.631361 <3>[ 15.688857] Bluetooth: hci0: Failed to load firmware file (-2)
10776 22:18:23.637990 <3>[ 15.702849] Bluetooth: hci0: Failed to set up firmware (-2)
10777 22:18:23.643952 <5>[ 15.707097] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10778 22:18:23.654423 <4>[ 15.708675] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10779 22:18:23.664097 <4>[ 15.715533] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10780 22:18:23.667343 <6>[ 15.734816] cfg80211: failed to load regulatory.db
10781 22:18:23.711498 <6>[ 15.775172] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10782 22:18:23.718382 <6>[ 15.782688] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10783 22:18:23.742793 <6>[ 15.809404] mt7921e 0000:01:00.0: ASIC revision: 79610010
10784 22:18:23.848409 <4>[ 15.908916] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10785 22:18:23.851705 Begin: Loading essential drivers ... done.
10786 22:18:23.858655 Begin: Running /scripts/init-premount ... done.
10787 22:18:23.865231 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10788 22:18:23.871516 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10789 22:18:23.878274 Device /sys/class/net/enx00e04c722dd6 found
10790 22:18:23.878792 done.
10791 22:18:23.914240 IP-Config: enx00e04c722dd6 hardware address 00:e0:4c:72:2d:d6 mtu 1500 DHCP
10792 22:18:23.967186 <4>[ 16.027823] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10793 22:18:24.086663 <4>[ 16.147286] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10794 22:18:24.203200 <4>[ 16.263138] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10795 22:18:24.318865 <4>[ 16.379033] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10796 22:18:24.434639 <4>[ 16.495056] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10797 22:18:24.550649 <4>[ 16.610965] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10798 22:18:24.666347 <4>[ 16.726887] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10799 22:18:24.783067 <4>[ 16.842920] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10800 22:18:24.898765 <4>[ 16.958799] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10801 22:18:25.005811 <3>[ 17.072636] mt7921e 0000:01:00.0: hardware init failed
10802 22:18:25.066018 <6>[ 17.132719] r8152 2-1.3:1.0 enx00e04c722dd6: carrier on
10803 22:18:25.068896 IP-Config: no response after 2 secs - giving up
10804 22:18:25.106079 IP-Config: enx00e04c722dd6 hardware address 00:e0:4c:72:2d:d6 mtu 1500 DHCP
10805 22:18:26.208270 IP-Config: enx00e04c722dd6 complete (dhcp from 192.168.201.1):
10806 22:18:26.215857 address: 192.168.201.21 broadcast: 192.168.201.255 netmask: 255.255.255.0
10807 22:18:26.225005 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10808 22:18:26.231927 host : mt8192-asurada-spherion-r0-cbg-1
10809 22:18:26.237653 domain : lava-rack
10810 22:18:26.240860 rootserver: 192.168.201.1 rootpath:
10811 22:18:26.241334 filename :
10812 22:18:26.298966 done.
10813 22:18:26.306402 Begin: Running /scripts/nfs-bottom ... done.
10814 22:18:26.325290 Begin: Running /scripts/init-bottom ... done.
10815 22:18:27.414520 <6>[ 19.481506] NET: Registered PF_INET6 protocol family
10816 22:18:27.421118 <6>[ 19.488298] Segment Routing with IPv6
10817 22:18:27.424302 <6>[ 19.492274] In-situ OAM (IOAM) with IPv6
10818 22:18:27.538706 <30>[ 19.585859] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10819 22:18:27.541498 <30>[ 19.609647] systemd[1]: Detected architecture arm64.
10820 22:18:27.561865
10821 22:18:27.565258 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10822 22:18:27.565731
10823 22:18:27.580830 <30>[ 19.647791] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10824 22:18:28.118074 <30>[ 20.182776] systemd[1]: Queued start job for default target Graphical Interface.
10825 22:18:28.143404 <30>[ 20.210620] systemd[1]: Created slice system-getty.slice.
10826 22:18:28.150392 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10827 22:18:28.166815 <30>[ 20.234292] systemd[1]: Created slice system-modprobe.slice.
10828 22:18:28.173506 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10829 22:18:28.190809 <30>[ 20.258182] systemd[1]: Created slice system-serial\x2dgetty.slice.
10830 22:18:28.200798 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10831 22:18:28.215931 <30>[ 20.282624] systemd[1]: Created slice User and Session Slice.
10832 22:18:28.221906 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10833 22:18:28.241843 <30>[ 20.306124] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10834 22:18:28.252194 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10835 22:18:28.270296 <30>[ 20.334035] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10836 22:18:28.277032 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10837 22:18:28.296890 <30>[ 20.357704] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10838 22:18:28.303428 <30>[ 20.369731] systemd[1]: Reached target Local Encrypted Volumes.
10839 22:18:28.309965 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10840 22:18:28.326797 <30>[ 20.394127] systemd[1]: Reached target Paths.
10841 22:18:28.330360 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10842 22:18:28.346309 <30>[ 20.413658] systemd[1]: Reached target Remote File Systems.
10843 22:18:28.353217 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10844 22:18:28.370699 <30>[ 20.437851] systemd[1]: Reached target Slices.
10845 22:18:28.377123 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10846 22:18:28.390645 <30>[ 20.457625] systemd[1]: Reached target Swap.
10847 22:18:28.393345 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10848 22:18:28.413922 <30>[ 20.477886] systemd[1]: Listening on initctl Compatibility Named Pipe.
10849 22:18:28.420431 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10850 22:18:28.427333 <30>[ 20.493347] systemd[1]: Listening on Journal Audit Socket.
10851 22:18:28.433604 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10852 22:18:28.447551 <30>[ 20.514594] systemd[1]: Listening on Journal Socket (/dev/log).
10853 22:18:28.453662 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10854 22:18:28.470885 <30>[ 20.538384] systemd[1]: Listening on Journal Socket.
10855 22:18:28.477351 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10856 22:18:28.495156 <30>[ 20.559017] systemd[1]: Listening on Network Service Netlink Socket.
10857 22:18:28.501424 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10858 22:18:28.517432 <30>[ 20.584255] systemd[1]: Listening on udev Control Socket.
10859 22:18:28.523567 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10860 22:18:28.538989 <30>[ 20.605861] systemd[1]: Listening on udev Kernel Socket.
10861 22:18:28.545565 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10862 22:18:28.594268 <30>[ 20.661779] systemd[1]: Mounting Huge Pages File System...
10863 22:18:28.600818 Mounting [0;1;39mHuge Pages File System[0m...
10864 22:18:28.616274 <30>[ 20.683901] systemd[1]: Mounting POSIX Message Queue File System...
10865 22:18:28.623219 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10866 22:18:28.640604 <30>[ 20.707959] systemd[1]: Mounting Kernel Debug File System...
10867 22:18:28.647128 Mounting [0;1;39mKernel Debug File System[0m...
10868 22:18:28.665389 <30>[ 20.729731] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10869 22:18:28.681884 <30>[ 20.745984] systemd[1]: Starting Create list of static device nodes for the current kernel...
10870 22:18:28.688310 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10871 22:18:28.708650 <30>[ 20.776194] systemd[1]: Starting Load Kernel Module configfs...
10872 22:18:28.715129 Starting [0;1;39mLoad Kernel Module configfs[0m...
10873 22:18:28.732680 <30>[ 20.800019] systemd[1]: Starting Load Kernel Module drm...
10874 22:18:28.738663 Starting [0;1;39mLoad Kernel Module drm[0m...
10875 22:18:28.756452 <30>[ 20.824052] systemd[1]: Starting Load Kernel Module fuse...
10876 22:18:28.762518 Starting [0;1;39mLoad Kernel Module fuse[0m...
10877 22:18:28.800721 <30>[ 20.865014] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10878 22:18:28.807298 <6>[ 20.865040] fuse: init (API version 7.37)
10879 22:18:28.830393 <30>[ 20.898059] systemd[1]: Starting Journal Service...
10880 22:18:28.833918 Starting [0;1;39mJournal Service[0m...
10881 22:18:28.858887 <30>[ 20.926308] systemd[1]: Starting Load Kernel Modules...
10882 22:18:28.865558 Starting [0;1;39mLoad Kernel Modules[0m...
10883 22:18:28.883967 <30>[ 20.948215] systemd[1]: Starting Remount Root and Kernel File Systems...
10884 22:18:28.890486 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10885 22:18:28.906178 <30>[ 20.973864] systemd[1]: Starting Coldplug All udev Devices...
10886 22:18:28.913010 Starting [0;1;39mColdplug All udev Devices[0m...
10887 22:18:28.928991 <30>[ 20.996515] systemd[1]: Mounted Huge Pages File System.
10888 22:18:28.935722 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10889 22:18:28.954566 <30>[ 21.021926] systemd[1]: Mounted POSIX Message Queue File System.
10890 22:18:28.961070 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10891 22:18:28.978944 <30>[ 21.046047] systemd[1]: Mounted Kernel Debug File System.
10892 22:18:28.988567 <3>[ 21.051035] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10893 22:18:28.995238 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10894 22:18:29.018843 <30>[ 21.082457] systemd[1]: Finished Create list of static device nodes for the current kernel.
10895 22:18:29.028412 <3>[ 21.084252] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10896 22:18:29.034929 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10897 22:18:29.051816 <30>[ 21.118728] systemd[1]: modprobe@configfs.service: Succeeded.
10898 22:18:29.057820 <30>[ 21.125407] systemd[1]: Finished Load Kernel Module configfs.
10899 22:18:29.064908 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10900 22:18:29.074718 <3>[ 21.137895] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10901 22:18:29.081673 <30>[ 21.147923] systemd[1]: modprobe@drm.service: Succeeded.
10902 22:18:29.087733 <30>[ 21.154196] systemd[1]: Finished Load Kernel Module drm.
10903 22:18:29.094728 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10904 22:18:29.104634 <3>[ 21.168923] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10905 22:18:29.114490 <30>[ 21.182387] systemd[1]: modprobe@fuse.service: Succeeded.
10906 22:18:29.121109 <30>[ 21.188986] systemd[1]: Finished Load Kernel Module fuse.
10907 22:18:29.128312 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module fuse[0m.
10908 22:18:29.137759 <3>[ 21.202183] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10909 22:18:29.145050 <30>[ 21.212262] systemd[1]: Finished Load Kernel Modules.
10910 22:18:29.151065 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10911 22:18:29.167415 <3>[ 21.231912] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10912 22:18:29.177693 <30>[ 21.242337] systemd[1]: Finished Remount Root and Kernel File Systems.
10913 22:18:29.184189 [[0;32m OK [0m] Finished [0;1;39mRemount Root and Kernel File Systems[0m.
10914 22:18:29.198672 <3>[ 21.262695] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10915 22:18:29.228950 <3>[ 21.293279] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10916 22:18:29.253956 <30>[ 21.321241] systemd[1]: Mounting FUSE Control File System...
10917 22:18:29.263397 <3>[ 21.322959] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10918 22:18:29.269915 Mounting [0;1;39mFUSE Control File System[0m...
10919 22:18:29.285090 <30>[ 21.352342] systemd[1]: Mounting Kernel Configuration File System...
10920 22:18:29.294828 <3>[ 21.356458] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10921 22:18:29.301308 Mounting [0;1;39mKernel Configuration File System[0m...
10922 22:18:29.330121 <30>[ 21.394561] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped.
10923 22:18:29.340154 <30>[ 21.403601] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped.
10924 22:18:29.348316 <30>[ 21.415969] systemd[1]: Starting Load/Save Random Seed...
10925 22:18:29.354815 Starting [0;1;39mLoad/Save Random Seed[0m...
10926 22:18:29.372677 <30>[ 21.440426] systemd[1]: Starting Apply Kernel Variables...
10927 22:18:29.379457 Starting [0;1;39mApply Kernel Variables[0m...
10928 22:18:29.397879 <30>[ 21.465012] systemd[1]: Starting Create System Users...
10929 22:18:29.404626 Starting [0;1;39mCreate System Users[0m...
10930 22:18:29.419377 <30>[ 21.487026] systemd[1]: Started Journal Service.
10931 22:18:29.425842 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10932 22:18:29.440732 [[0;32m OK [0m] Mounted [0;1;39mFUSE Control File System[0m.
10933 22:18:29.457077 <4>[ 21.514040] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10934 22:18:29.463730 <3>[ 21.529803] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10935 22:18:29.470862 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10936 22:18:29.487922 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10937 22:18:29.507169 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10938 22:18:29.518169 See 'systemctl status systemd-udev-trigger.service' for details.
10939 22:18:29.535400 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10940 22:18:29.550837 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10941 22:18:29.595567 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10942 22:18:29.617017 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10943 22:18:29.638652 <46>[ 21.703302] systemd-journald[301]: Received client request to flush runtime journal.
10944 22:18:30.718621 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10945 22:18:30.729961 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10946 22:18:30.745597 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10947 22:18:30.809683 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10948 22:18:31.017499 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10949 22:18:31.066204 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10950 22:18:31.112018 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10951 22:18:31.191864 Starting [0;1;39mNetwork Service[0m...
10952 22:18:31.247091 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10953 22:18:31.331890 Starting [0;1;39mNetwork Time Synchronization[0m...
10954 22:18:31.351213 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10955 22:18:31.469111 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10956 22:18:31.492703 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10957 22:18:31.533561 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10958 22:18:31.735224 <6>[ 23.803164] remoteproc remoteproc0: powering up scp
10959 22:18:31.765635 <4>[ 23.830639] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10960 22:18:31.772636 <3>[ 23.840527] remoteproc remoteproc0: request_firmware failed: -2
10961 22:18:31.782145 <3>[ 23.846724] fops_vcodec_open(),166: [MTK_V4L2][ERROR] vpu_load_firmware failed!
10962 22:18:31.880915 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10963 22:18:31.893989 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10964 22:18:31.915661 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10965 22:18:31.933318 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10966 22:18:31.974081 Starting [0;1;39mNetwork Name Resolution[0m...
10967 22:18:31.990336 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10968 22:18:32.010025 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10969 22:18:32.033707 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10970 22:18:32.053424 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10971 22:18:32.070172 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10972 22:18:32.085600 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10973 22:18:32.768795 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
10974 22:18:32.792585 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
10975 22:18:33.114836 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
10976 22:18:33.145047 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10977 22:18:33.157115 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10978 22:18:33.179027 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10979 22:18:33.193598 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10980 22:18:33.209371 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10981 22:18:33.249617 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10982 22:18:33.287556 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
10983 22:18:33.470096 Starting [0;1;39mUser Login Management[0m...
10984 22:18:33.489221 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10985 22:18:33.830522 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10986 22:18:33.848366 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10987 22:18:33.866001 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10988 22:18:33.884591 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10989 22:18:33.929659 Starting [0;1;39mPermit User Sessions[0m...
10990 22:18:33.950396 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
10991 22:18:33.967201 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10992 22:18:34.010623 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10993 22:18:34.029025 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10994 22:18:34.045441 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10995 22:18:34.061766 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10996 22:18:34.069397 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10997 22:18:34.085695 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10998 22:18:34.134537 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10999 22:18:34.168878 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
11000 22:18:34.237793
11001 22:18:34.237947
11002 22:18:34.241146 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
11003 22:18:34.241224
11004 22:18:34.244309 debian-bullseye-arm64 login: root (automatic login)
11005 22:18:34.244413
11006 22:18:34.244511
11007 22:18:34.509424 Linux debian-bullseye-arm64 6.1.31 #1 SMP PREEMPT Mon Jun 5 22:04:07 UTC 2023 aarch64
11008 22:18:34.509568
11009 22:18:34.515752 The programs included with the Debian GNU/Linux system are free software;
11010 22:18:34.522480 the exact distribution terms for each program are described in the
11011 22:18:34.526061 individual files in /usr/share/doc/*/copyright.
11012 22:18:34.526180
11013 22:18:34.532485 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11014 22:18:34.535578 permitted by applicable law.
11015 22:18:35.299832 Matched prompt #10: / #
11017 22:18:35.300119 Setting prompt string to ['/ #']
11018 22:18:35.300214 end: 2.2.5.1 login-action (duration 00:00:28) [common]
11020 22:18:35.300408 end: 2.2.5 auto-login-action (duration 00:00:28) [common]
11021 22:18:35.300498 start: 2.2.6 expect-shell-connection (timeout 00:03:35) [common]
11022 22:18:35.300571 Setting prompt string to ['/ #']
11023 22:18:35.300632 Forcing a shell prompt, looking for ['/ #']
11025 22:18:35.350856 / #
11026 22:18:35.351017 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11027 22:18:35.351138 Waiting using forced prompt support (timeout 00:02:30)
11028 22:18:35.355906
11029 22:18:35.356190 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11030 22:18:35.356284 start: 2.2.7 export-device-env (timeout 00:03:35) [common]
11032 22:18:35.456658 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/10597254/extract-nfsrootfs-j4uzvb9s'
11033 22:18:35.461617 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/10597254/extract-nfsrootfs-j4uzvb9s'
11035 22:18:35.562180 / # export NFS_SERVER_IP='192.168.201.1'
11036 22:18:35.567271 export NFS_SERVER_IP='192.168.201.1'
11037 22:18:35.567563 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11038 22:18:35.567668 end: 2.2 depthcharge-retry (duration 00:01:25) [common]
11039 22:18:35.567760 end: 2 depthcharge-action (duration 00:01:25) [common]
11040 22:18:35.567848 start: 3 lava-test-retry (timeout 00:07:56) [common]
11041 22:18:35.567938 start: 3.1 lava-test-shell (timeout 00:07:56) [common]
11042 22:18:35.568015 Using namespace: common
11044 22:18:35.668383 / # #
11045 22:18:35.668568 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11046 22:18:35.673022 #
11047 22:18:35.673294 Using /lava-10597254
11049 22:18:35.773646 / # export SHELL=/bin/bash
11050 22:18:35.778953 export SHELL=/bin/bash
11052 22:18:35.879517 / # . /lava-10597254/environment
11053 22:18:35.884781 . /lava-10597254/environment
11055 22:18:35.990453 / # /lava-10597254/bin/lava-test-runner /lava-10597254/0
11056 22:18:35.990618 Test shell timeout: 10s (minimum of the action and connection timeout)
11057 22:18:35.996178 /lava-10597254/bin/lava-test-runner /lava-10597254/0
11058 22:18:36.202749 + export TESTRUN_ID=0_timesync-off
11059 22:18:36.205935 + TESTRUN_ID=0_timesync-off
11060 22:18:36.209601 + cd /lava-10597254/0/tests/0_timesync-off
11061 22:18:36.212441 ++ cat uuid
11062 22:18:36.212527 + UUID=10597254_1.6.2.3.1
11063 22:18:36.215919 + set +x
11064 22:18:36.219262 <LAVA_SIGNAL_STARTRUN 0_timesync-off 10597254_1.6.2.3.1>
11065 22:18:36.219542 Received signal: <STARTRUN> 0_timesync-off 10597254_1.6.2.3.1
11066 22:18:36.219619 Starting test lava.0_timesync-off (10597254_1.6.2.3.1)
11067 22:18:36.219709 Skipping test definition patterns.
11068 22:18:36.222301 + systemctl stop systemd-timesyncd
11069 22:18:36.249365 + set +x
11070 22:18:36.252505 <LAVA_SIGNAL_ENDRUN 0_timesync-off 10597254_1.6.2.3.1>
11071 22:18:36.252773 Received signal: <ENDRUN> 0_timesync-off 10597254_1.6.2.3.1
11072 22:18:36.252874 Ending use of test pattern.
11073 22:18:36.252939 Ending test lava.0_timesync-off (10597254_1.6.2.3.1), duration 0.03
11075 22:18:36.300678 + export TESTRUN_ID=1_kselftest-arm64
11076 22:18:36.300833 + TESTRUN_ID=1_kselftest-arm64
11077 22:18:36.307522 + cd /lava-10597254/0/tests/1_kselftest-arm64
11078 22:18:36.307608 ++ cat uuid
11079 22:18:36.310777 + UUID=10597254_1.6.2.3.5
11080 22:18:36.310861 + set +x
11081 22:18:36.314095 <LAVA_SIGNAL_STARTRUN 1_kselftest-arm64 10597254_1.6.2.3.5>
11082 22:18:36.314353 Received signal: <STARTRUN> 1_kselftest-arm64 10597254_1.6.2.3.5
11083 22:18:36.314424 Starting test lava.1_kselftest-arm64 (10597254_1.6.2.3.5)
11084 22:18:36.314507 Skipping test definition patterns.
11085 22:18:36.317240 + cd ./automated/linux/kselftest/
11086 22:18:36.347542 + ./kselftest.sh -c arm64 -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1314-g1ab0ac1d7e2e3/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip-gitlab -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11087 22:18:36.359253 INFO: install_deps skipped
11088 22:18:36.459252 --2023-06-05 22:18:33-- http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1314-g1ab0ac1d7e2e3/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11089 22:18:36.466054 Resolving storage.kernelci.org (storage.kernelci.org)... 52.250.1.28
11090 22:18:36.609565 Connecting to storage.kernelci.org (storage.kernelci.org)|52.250.1.28|:80... connected.
11091 22:18:36.761251 HTTP request sent, awaiting response... 200 OK
11092 22:18:36.764928 Length: 2860080 (2.7M) [application/octet-stream]
11093 22:18:36.768002 Saving to: 'kselftest.tar.xz'
11094 22:18:36.768086
11095 22:18:36.768151
11096 22:18:37.066730 kselftest.tar.xz 0%[ ] 0 --.-KB/s
11097 22:18:37.370391 kselftest.tar.xz 1%[ ] 47.81K 157KB/s
11098 22:18:37.673627 kselftest.tar.xz 7%[> ] 216.08K 356KB/s
11099 22:18:37.875417 kselftest.tar.xz 32%[=====> ] 894.83K 982KB/s
11100 22:18:38.030536 kselftest.tar.xz 45%[========> ] 1.25M 1.13MB/s
11101 22:18:38.036962 kselftest.tar.xz 100%[===================>] 2.73M 2.15MB/s in 1.3s
11102 22:18:38.037056
11103 22:18:38.283559 2023-06-05 22:18:35 (2.15 MB/s) - 'kselftest.tar.xz' saved [2860080/2860080]
11104 22:18:38.283699
11105 22:18:43.066121 skiplist:
11106 22:18:43.069810 ========================================
11107 22:18:43.072596 ========================================
11108 22:18:43.107577 arm64:tags_test
11109 22:18:43.110847 arm64:run_tags_test.sh
11110 22:18:43.110928 arm64:fake_sigreturn_bad_magic
11111 22:18:43.114457 arm64:fake_sigreturn_bad_size
11112 22:18:43.117691 arm64:fake_sigreturn_bad_size_for_magic0
11113 22:18:43.120960 arm64:fake_sigreturn_duplicated_fpsimd
11114 22:18:43.123948 arm64:fake_sigreturn_misaligned_sp
11115 22:18:43.127628 arm64:fake_sigreturn_missing_fpsimd
11116 22:18:43.130591 arm64:fake_sigreturn_sme_change_vl
11117 22:18:43.134182 arm64:fake_sigreturn_sve_change_vl
11118 22:18:43.137223 arm64:mangle_pstate_invalid_compat_toggle
11119 22:18:43.140411 arm64:mangle_pstate_invalid_daif_bits
11120 22:18:43.143829 arm64:mangle_pstate_invalid_mode_el1h
11121 22:18:43.147049 arm64:mangle_pstate_invalid_mode_el1t
11122 22:18:43.150908 arm64:mangle_pstate_invalid_mode_el2h
11123 22:18:43.153701 arm64:mangle_pstate_invalid_mode_el2t
11124 22:18:43.157161 arm64:mangle_pstate_invalid_mode_el3h
11125 22:18:43.163851 arm64:mangle_pstate_invalid_mode_el3t
11126 22:18:43.164370 arm64:sme_trap_no_sm
11127 22:18:43.167117 arm64:sme_trap_non_streaming
11128 22:18:43.167729 arm64:sme_trap_za
11129 22:18:43.170625 arm64:sme_vl
11130 22:18:43.171191 arm64:ssve_regs
11131 22:18:43.173960 arm64:sve_regs
11132 22:18:43.174413 arm64:sve_vl
11133 22:18:43.174772 arm64:za_no_regs
11134 22:18:43.176856 arm64:za_regs
11135 22:18:43.177179 arm64:pac
11136 22:18:43.180258 arm64:fp-stress
11137 22:18:43.180497 arm64:sve-ptrace
11138 22:18:43.183881 arm64:sve-probe-vls
11139 22:18:43.184109 arm64:vec-syscfg
11140 22:18:43.184309 arm64:za-fork
11141 22:18:43.186726 arm64:za-ptrace
11142 22:18:43.189980 arm64:check_buffer_fill
11143 22:18:43.190171 arm64:check_child_memory
11144 22:18:43.193308 arm64:check_gcr_el1_cswitch
11145 22:18:43.197021 arm64:check_ksm_options
11146 22:18:43.197105 arm64:check_mmap_options
11147 22:18:43.199970 arm64:check_prctl
11148 22:18:43.203329 arm64:check_tags_inclusion
11149 22:18:43.203412 arm64:check_user_mem
11150 22:18:43.206358 arm64:btitest
11151 22:18:43.206460 arm64:nobtitest
11152 22:18:43.206526 arm64:hwcap
11153 22:18:43.209666 arm64:ptrace
11154 22:18:43.209770 arm64:syscall-abi
11155 22:18:43.213086 arm64:tpidr2
11156 22:18:43.216405 ============== Tests to run ===============
11157 22:18:43.216488 arm64:tags_test
11158 22:18:43.220120 arm64:run_tags_test.sh
11159 22:18:43.223378 arm64:fake_sigreturn_bad_magic
11160 22:18:43.226920 arm64:fake_sigreturn_bad_size
11161 22:18:43.229522 arm64:fake_sigreturn_bad_size_for_magic0
11162 22:18:43.233099 arm64:fake_sigreturn_duplicated_fpsimd
11163 22:18:43.236215 arm64:fake_sigreturn_misaligned_sp
11164 22:18:43.239551 arm64:fake_sigreturn_missing_fpsimd
11165 22:18:43.242724 arm64:fake_sigreturn_sme_change_vl
11166 22:18:43.245986 arm64:fake_sigreturn_sve_change_vl
11167 22:18:43.249343 arm64:mangle_pstate_invalid_compat_toggle
11168 22:18:43.252374 arm64:mangle_pstate_invalid_daif_bits
11169 22:18:43.256148 arm64:mangle_pstate_invalid_mode_el1h
11170 22:18:43.259455 arm64:mangle_pstate_invalid_mode_el1t
11171 22:18:43.262455 arm64:mangle_pstate_invalid_mode_el2h
11172 22:18:43.265847 arm64:mangle_pstate_invalid_mode_el2t
11173 22:18:43.269242 arm64:mangle_pstate_invalid_mode_el3h
11174 22:18:43.272428 arm64:mangle_pstate_invalid_mode_el3t
11175 22:18:43.272518 arm64:sme_trap_no_sm
11176 22:18:43.276003 arm64:sme_trap_non_streaming
11177 22:18:43.278944 arm64:sme_trap_za
11178 22:18:43.279047 arm64:sme_vl
11179 22:18:43.282546 arm64:ssve_regs
11180 22:18:43.282657 arm64:sve_regs
11181 22:18:43.282746 arm64:sve_vl
11182 22:18:43.285583 arm64:za_no_regs
11183 22:18:43.285666 arm64:za_regs
11184 22:18:43.285730 arm64:pac
11185 22:18:43.288757 arm64:fp-stress
11186 22:18:43.288856 arm64:sve-ptrace
11187 22:18:43.292311 arm64:sve-probe-vls
11188 22:18:43.292723 arm64:vec-syscfg
11189 22:18:43.295942 arm64:za-fork
11190 22:18:43.296565 arm64:za-ptrace
11191 22:18:43.298947 arm64:check_buffer_fill
11192 22:18:43.302389 arm64:check_child_memory
11193 22:18:43.302933 arm64:check_gcr_el1_cswitch
11194 22:18:43.305956 arm64:check_ksm_options
11195 22:18:43.308975 arm64:check_mmap_options
11196 22:18:43.309490 arm64:check_prctl
11197 22:18:43.312169 arm64:check_tags_inclusion
11198 22:18:43.315539 arm64:check_user_mem
11199 22:18:43.316099 arm64:btitest
11200 22:18:43.316589 arm64:nobtitest
11201 22:18:43.318867 arm64:hwcap
11202 22:18:43.319338 arm64:ptrace
11203 22:18:43.322109 arm64:syscall-abi
11204 22:18:43.322550 arm64:tpidr2
11205 22:18:43.325420 ===========End Tests to run ===============
11206 22:18:43.481813 <12>[ 35.551258] kselftest: Running tests in arm64
11207 22:18:43.491470 TAP version 13
11208 22:18:43.504424 1..48
11209 22:18:43.518070 # selftests: arm64: tags_test
11210 22:18:43.880234 ok 1 selftests: arm64: tags_test
11211 22:18:43.893569 # selftests: arm64: run_tags_test.sh
11212 22:18:43.940443 # --------------------
11213 22:18:43.943408 # running tags test
11214 22:18:43.943943 # --------------------
11215 22:18:43.947023 # [PASS]
11216 22:18:43.950034 ok 2 selftests: arm64: run_tags_test.sh
11217 22:18:43.961540 # selftests: arm64: fake_sigreturn_bad_magic
11218 22:18:44.008680 # Registered handlers for all signals.
11219 22:18:44.008879 # Detected MINSTKSIGSZ:4720
11220 22:18:44.011894 # Testcase initialized.
11221 22:18:44.015219 # uc context validated.
11222 22:18:44.018467 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11223 22:18:44.022200 # Handled SIG_COPYCTX
11224 22:18:44.022327 # Available space:3568
11225 22:18:44.028334 # Using badly built context - ERR: BAD MAGIC !
11226 22:18:44.035153 # SIG_OK -- SP:0xFFFFC481A5D0 si_addr@:0xffffc481a5d0 si_code:2 token@:0xffffc4819370 offset:-4704
11227 22:18:44.038644 # ==>> completed. PASS(1)
11228 22:18:44.045236 # # FAKE_SIGRETURN_BAD_MAGIC :: Trigger a sigreturn with a sigframe with a bad magic
11229 22:18:44.051959 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFC4819370
11230 22:18:44.058009 ok 3 selftests: arm64: fake_sigreturn_bad_magic
11231 22:18:44.061484 # selftests: arm64: fake_sigreturn_bad_size
11232 22:18:44.073957 # Registered handlers for all signals.
11233 22:18:44.074059 # Detected MINSTKSIGSZ:4720
11234 22:18:44.077150 # Testcase initialized.
11235 22:18:44.080365 # uc context validated.
11236 22:18:44.084014 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11237 22:18:44.087228 # Handled SIG_COPYCTX
11238 22:18:44.087311 # Available space:3568
11239 22:18:44.090290 # uc context validated.
11240 22:18:44.096678 # Using badly built context - ERR: Bad size for esr_context
11241 22:18:44.103508 # SIG_OK -- SP:0xFFFFE4B9BDD0 si_addr@:0xffffe4b9bdd0 si_code:2 token@:0xffffe4b9ab70 offset:-4704
11242 22:18:44.106927 # ==>> completed. PASS(1)
11243 22:18:44.113847 # # FAKE_SIGRETURN_BAD_SIZE :: Triggers a sigreturn with a overrun __reserved area
11244 22:18:44.120123 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFE4B9AB70
11245 22:18:44.123441 ok 4 selftests: arm64: fake_sigreturn_bad_size
11246 22:18:44.129814 # selftests: arm64: fake_sigreturn_bad_size_for_magic0
11247 22:18:44.133305 # Registered handlers for all signals.
11248 22:18:44.136469 # Detected MINSTKSIGSZ:4720
11249 22:18:44.136554 # Testcase initialized.
11250 22:18:44.140244 # uc context validated.
11251 22:18:44.146552 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11252 22:18:44.146631 # Handled SIG_COPYCTX
11253 22:18:44.149816 # Available space:3568
11254 22:18:44.152823 # Using badly built context - ERR: Bad size for terminator
11255 22:18:44.163062 # SIG_OK -- SP:0xFFFFC88650B0 si_addr@:0xffffc88650b0 si_code:2 token@:0xffffc8863e50 offset:-4704
11256 22:18:44.166826 # ==>> completed. PASS(1)
11257 22:18:44.173020 # # FAKE_SIGRETURN_BAD_SIZE_FOR_TERMINATOR :: Trigger a sigreturn using non-zero size terminator
11258 22:18:44.179713 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFC8863E50
11259 22:18:44.186029 ok 5 selftests: arm64: fake_sigreturn_bad_size_for_magic0
11260 22:18:44.189584 # selftests: arm64: fake_sigreturn_duplicated_fpsimd
11261 22:18:44.197155 # Registered handlers for all signals.
11262 22:18:44.197250 # Detected MINSTKSIGSZ:4720
11263 22:18:44.201034 # Testcase initialized.
11264 22:18:44.203609 # uc context validated.
11265 22:18:44.207108 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11266 22:18:44.210401 # Handled SIG_COPYCTX
11267 22:18:44.210478 # Available space:3568
11268 22:18:44.217073 # Using badly built context - ERR: Multiple FPSIMD_MAGIC
11269 22:18:44.226906 # SIG_OK -- SP:0xFFFFEBF0D080 si_addr@:0xffffebf0d080 si_code:2 token@:0xffffebf0be20 offset:-4704
11270 22:18:44.227017 # ==>> completed. PASS(1)
11271 22:18:44.237169 # # FAKE_SIGRETURN_DUPLICATED_FPSIMD :: Triggers a sigreturn including two fpsimd_context
11272 22:18:44.243348 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFEBF0BE20
11273 22:18:44.246898 ok 6 selftests: arm64: fake_sigreturn_duplicated_fpsimd
11274 22:18:44.250285 # selftests: arm64: fake_sigreturn_misaligned_sp
11275 22:18:44.264607 # Registered handlers for all signals.
11276 22:18:44.264729 # Detected MINSTKSIGSZ:4720
11277 22:18:44.267846 # Testcase initialized.
11278 22:18:44.271174 # uc context validated.
11279 22:18:44.274396 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11280 22:18:44.277675 # Handled SIG_COPYCTX
11281 22:18:44.284189 # SIG_OK -- SP:0xFFFFE956A273 si_addr@:0xffffe956a273 si_code:2 token@:0xffffe956a273 offset:0
11282 22:18:44.287555 # ==>> completed. PASS(1)
11283 22:18:44.294553 # # FAKE_SIGRETURN_MISALIGNED_SP :: Triggers a sigreturn with a misaligned sigframe
11284 22:18:44.300961 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFE956A273
11285 22:18:44.307535 ok 7 selftests: arm64: fake_sigreturn_misaligned_sp
11286 22:18:44.310796 # selftests: arm64: fake_sigreturn_missing_fpsimd
11287 22:18:44.328128 # Registered handlers for all signals.
11288 22:18:44.328218 # Detected MINSTKSIGSZ:4720
11289 22:18:44.331854 # Testcase initialized.
11290 22:18:44.334677 # uc context validated.
11291 22:18:44.338326 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11292 22:18:44.341456 # Handled SIG_COPYCTX
11293 22:18:44.344644 # Mangling template header. Spare space:4096
11294 22:18:44.347823 # Using badly built context - ERR: Missing FPSIMD
11295 22:18:44.358069 # SIG_OK -- SP:0xFFFFC00F9EB0 si_addr@:0xffffc00f9eb0 si_code:2 token@:0xffffc00f8c50 offset:-4704
11296 22:18:44.361025 # ==>> completed. PASS(1)
11297 22:18:44.368014 # # FAKE_SIGRETURN_MISSING_FPSIMD :: Triggers a sigreturn with a missing fpsimd_context
11298 22:18:44.374382 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFC00F8C50
11299 22:18:44.377511 ok 8 selftests: arm64: fake_sigreturn_missing_fpsimd
11300 22:18:44.384181 # selftests: arm64: fake_sigreturn_sme_change_vl
11301 22:18:44.391623 # Registered handlers for all signals.
11302 22:18:44.391705 # Detected MINSTKSIGSZ:4720
11303 22:18:44.394785 # ==>> completed. SKIP.
11304 22:18:44.401497 # # FAKE_SIGRETURN_SSVE_CHANGE :: Attempt to change Streaming SVE VL
11305 22:18:44.405166 ok 9 selftests: arm64: fake_sigreturn_sme_change_vl # SKIP
11306 22:18:44.411360 # selftests: arm64: fake_sigreturn_sve_change_vl
11307 22:18:44.454157 # Registered handlers for all signals.
11308 22:18:44.454282 # Detected MINSTKSIGSZ:4720
11309 22:18:44.457538 # ==>> completed. SKIP.
11310 22:18:44.463709 # # FAKE_SIGRETURN_SVE_CHANGE :: Attempt to change SVE VL
11311 22:18:44.467029 ok 10 selftests: arm64: fake_sigreturn_sve_change_vl # SKIP
11312 22:18:44.473480 # selftests: arm64: mangle_pstate_invalid_compat_toggle
11313 22:18:44.517333 # Registered handlers for all signals.
11314 22:18:44.517423 # Detected MINSTKSIGSZ:4720
11315 22:18:44.520260 # Testcase initialized.
11316 22:18:44.523525 # uc context validated.
11317 22:18:44.523612 # Handled SIG_TRIG
11318 22:18:44.533423 # SIG_OK -- SP:0xFFFFC7D47690 si_addr@:0xffffc7d47690 si_code:2 token@:(nil) offset:-281474034333328
11319 22:18:44.536681 # ==>> completed. PASS(1)
11320 22:18:44.543475 # # MANGLE_PSTATE_INVALID_STATE_TOGGLE :: Mangling uc_mcontext with INVALID STATE_TOGGLE
11321 22:18:44.549756 ok 11 selftests: arm64: mangle_pstate_invalid_compat_toggle
11322 22:18:44.553260 # selftests: arm64: mangle_pstate_invalid_daif_bits
11323 22:18:44.576959 # Registered handlers for all signals.
11324 22:18:44.577048 # Detected MINSTKSIGSZ:4720
11325 22:18:44.580821 # Testcase initialized.
11326 22:18:44.583591 # uc context validated.
11327 22:18:44.583677 # Handled SIG_TRIG
11328 22:18:44.593794 # SIG_OK -- SP:0xFFFFFA957BF0 si_addr@:0xfffffa957bf0 si_code:2 token@:(nil) offset:-281474885843952
11329 22:18:44.596777 # ==>> completed. PASS(1)
11330 22:18:44.603834 # # MANGLE_PSTATE_INVALID_DAIF_BITS :: Mangling uc_mcontext with INVALID DAIF_BITS
11331 22:18:44.606597 ok 12 selftests: arm64: mangle_pstate_invalid_daif_bits
11332 22:18:44.613339 # selftests: arm64: mangle_pstate_invalid_mode_el1h
11333 22:18:44.635546 # Registered handlers for all signals.
11334 22:18:44.635634 # Detected MINSTKSIGSZ:4720
11335 22:18:44.639260 # Testcase initialized.
11336 22:18:44.641912 # uc context validated.
11337 22:18:44.641998 # Handled SIG_TRIG
11338 22:18:44.651844 # SIG_OK -- SP:0xFFFFE16570E0 si_addr@:0xffffe16570e0 si_code:2 token@:(nil) offset:-281474463264992
11339 22:18:44.655469 # ==>> completed. PASS(1)
11340 22:18:44.661795 # # MANGLE_PSTATE_INVALID_MODE_EL1h :: Mangling uc_mcontext INVALID MODE EL1h
11341 22:18:44.664980 ok 13 selftests: arm64: mangle_pstate_invalid_mode_el1h
11342 22:18:44.671535 # selftests: arm64: mangle_pstate_invalid_mode_el1t
11343 22:18:44.698273 # Registered handlers for all signals.
11344 22:18:44.698361 # Detected MINSTKSIGSZ:4720
11345 22:18:44.701124 # Testcase initialized.
11346 22:18:44.704341 # uc context validated.
11347 22:18:44.704428 # Handled SIG_TRIG
11348 22:18:44.714919 # SIG_OK -- SP:0xFFFFD6898EB0 si_addr@:0xffffd6898eb0 si_code:2 token@:(nil) offset:-281474281082544
11349 22:18:44.717936 # ==>> completed. PASS(1)
11350 22:18:44.724170 # # MANGLE_PSTATE_INVALID_MODE_EL1t :: Mangling uc_mcontext INVALID MODE EL1t
11351 22:18:44.727658 ok 14 selftests: arm64: mangle_pstate_invalid_mode_el1t
11352 22:18:44.734446 # selftests: arm64: mangle_pstate_invalid_mode_el2h
11353 22:18:44.760462 # Registered handlers for all signals.
11354 22:18:44.760551 # Detected MINSTKSIGSZ:4720
11355 22:18:44.763536 # Testcase initialized.
11356 22:18:44.767103 # uc context validated.
11357 22:18:44.767189 # Handled SIG_TRIG
11358 22:18:44.776761 # SIG_OK -- SP:0xFFFFEF0E8F60 si_addr@:0xffffef0e8f60 si_code:2 token@:(nil) offset:-281474692452192
11359 22:18:44.780050 # ==>> completed. PASS(1)
11360 22:18:44.787019 # # MANGLE_PSTATE_INVALID_MODE_EL2h :: Mangling uc_mcontext INVALID MODE EL2h
11361 22:18:44.790800 ok 15 selftests: arm64: mangle_pstate_invalid_mode_el2h
11362 22:18:44.796530 # selftests: arm64: mangle_pstate_invalid_mode_el2t
11363 22:18:44.823075 # Registered handlers for all signals.
11364 22:18:44.823164 # Detected MINSTKSIGSZ:4720
11365 22:18:44.826691 # Testcase initialized.
11366 22:18:44.829803 # uc context validated.
11367 22:18:44.829890 # Handled SIG_TRIG
11368 22:18:44.839734 # SIG_OK -- SP:0xFFFFEA6B5C70 si_addr@:0xffffea6b5c70 si_code:2 token@:(nil) offset:-281474614647920
11369 22:18:44.842904 # ==>> completed. PASS(1)
11370 22:18:44.849750 # # MANGLE_PSTATE_INVALID_MODE_EL2t :: Mangling uc_mcontext INVALID MODE EL2t
11371 22:18:44.852794 ok 16 selftests: arm64: mangle_pstate_invalid_mode_el2t
11372 22:18:44.859264 # selftests: arm64: mangle_pstate_invalid_mode_el3h
11373 22:18:44.884019 # Registered handlers for all signals.
11374 22:18:44.884108 # Detected MINSTKSIGSZ:4720
11375 22:18:44.887536 # Testcase initialized.
11376 22:18:44.890595 # uc context validated.
11377 22:18:44.890677 # Handled SIG_TRIG
11378 22:18:44.900906 # SIG_OK -- SP:0xFFFFE4AD11F0 si_addr@:0xffffe4ad11f0 si_code:2 token@:(nil) offset:-281474518290928
11379 22:18:44.903847 # ==>> completed. PASS(1)
11380 22:18:44.910414 # # MANGLE_PSTATE_INVALID_MODE_EL3h :: Mangling uc_mcontext INVALID MODE EL3h
11381 22:18:44.913864 ok 17 selftests: arm64: mangle_pstate_invalid_mode_el3h
11382 22:18:44.920327 # selftests: arm64: mangle_pstate_invalid_mode_el3t
11383 22:18:44.944690 # Registered handlers for all signals.
11384 22:18:44.944804 # Detected MINSTKSIGSZ:4720
11385 22:18:44.948233 # Testcase initialized.
11386 22:18:44.951380 # uc context validated.
11387 22:18:44.951463 # Handled SIG_TRIG
11388 22:18:44.961337 # SIG_OK -- SP:0xFFFFC8A1F070 si_addr@:0xffffc8a1f070 si_code:2 token@:(nil) offset:-281474047799408
11389 22:18:44.964607 # ==>> completed. PASS(1)
11390 22:18:44.971234 # # MANGLE_PSTATE_INVALID_MODE_EL3t :: Mangling uc_mcontext INVALID MODE EL3t
11391 22:18:44.974404 ok 18 selftests: arm64: mangle_pstate_invalid_mode_el3t
11392 22:18:44.977635 # selftests: arm64: sme_trap_no_sm
11393 22:18:45.008655 # Registered handlers for all signals.
11394 22:18:45.008775 # Detected MINSTKSIGSZ:4720
11395 22:18:45.011723 # ==>> completed. SKIP.
11396 22:18:45.021575 # # SME trap without SM :: Check that we get a SIGILL if we use streaming mode without enabling it
11397 22:18:45.024656 ok 19 selftests: arm64: sme_trap_no_sm # SKIP
11398 22:18:45.028008 # selftests: arm64: sme_trap_non_streaming
11399 22:18:45.073221 # Registered handlers for all signals.
11400 22:18:45.073313 # Detected MINSTKSIGSZ:4720
11401 22:18:45.076525 # ==>> completed. SKIP.
11402 22:18:45.086508 # # SME SM trap unsupported instruction :: Check that we get a SIGILL if we use an unsupported instruction in streaming mode
11403 22:18:45.092971 ok 20 selftests: arm64: sme_trap_non_streaming # SKIP
11404 22:18:45.096627 # selftests: arm64: sme_trap_za
11405 22:18:45.138916 # Registered handlers for all signals.
11406 22:18:45.139009 # Detected MINSTKSIGSZ:4720
11407 22:18:45.142298 # Testcase initialized.
11408 22:18:45.152665 # SIG_OK -- SP:0xFFFFC98B0E30 si_addr@:0xaaaacc562510 si_code:1 token@:(nil) offset:-187650549359888
11409 22:18:45.152803 # ==>> completed. PASS(1)
11410 22:18:45.161903 # # SME ZA trap :: Check that we get a SIGILL if we access ZA without enabling
11411 22:18:45.165122 ok 21 selftests: arm64: sme_trap_za
11412 22:18:45.165206 # selftests: arm64: sme_vl
11413 22:18:45.201581 # Registered handlers for all signals.
11414 22:18:45.201673 # Detected MINSTKSIGSZ:4720
11415 22:18:45.204759 # ==>> completed. SKIP.
11416 22:18:45.211487 # # SME VL :: Check that we get the right SME VL reported
11417 22:18:45.214853 ok 22 selftests: arm64: sme_vl # SKIP
11418 22:18:45.214938 # selftests: arm64: ssve_regs
11419 22:18:45.262856 # Registered handlers for all signals.
11420 22:18:45.262950 # Detected MINSTKSIGSZ:4720
11421 22:18:45.266118 # ==>> completed. SKIP.
11422 22:18:45.272400 # # Streaming SVE registers :: Check that we get the right Streaming SVE registers reported
11423 22:18:45.278689 ok 23 selftests: arm64: ssve_regs # SKIP
11424 22:18:45.278775 # selftests: arm64: sve_regs
11425 22:18:45.326089 # Registered handlers for all signals.
11426 22:18:45.326182 # Detected MINSTKSIGSZ:4720
11427 22:18:45.329482 # ==>> completed. SKIP.
11428 22:18:45.336036 # # SVE registers :: Check that we get the right SVE registers reported
11429 22:18:45.339394 ok 24 selftests: arm64: sve_regs # SKIP
11430 22:18:45.342456 # selftests: arm64: sve_vl
11431 22:18:45.389446 # Registered handlers for all signals.
11432 22:18:45.389534 # Detected MINSTKSIGSZ:4720
11433 22:18:45.393261 # ==>> completed. SKIP.
11434 22:18:45.399606 # # SVE VL :: Check that we get the right SVE VL reported
11435 22:18:45.402940 ok 25 selftests: arm64: sve_vl # SKIP
11436 22:18:45.403025 # selftests: arm64: za_no_regs
11437 22:18:45.451349 # Registered handlers for all signals.
11438 22:18:45.451451 # Detected MINSTKSIGSZ:4720
11439 22:18:45.454737 # ==>> completed. SKIP.
11440 22:18:45.461636 # # ZA registers - ZA disabled :: Check ZA context with ZA disabled
11441 22:18:45.464398 ok 26 selftests: arm64: za_no_regs # SKIP
11442 22:18:45.467710 # selftests: arm64: za_regs
11443 22:18:45.513673 # Registered handlers for all signals.
11444 22:18:45.513762 # Detected MINSTKSIGSZ:4720
11445 22:18:45.517160 # ==>> completed. SKIP.
11446 22:18:45.523602 # # ZA register :: Check that we get the right ZA registers reported
11447 22:18:45.526941 ok 27 selftests: arm64: za_regs # SKIP
11448 22:18:45.529897 # selftests: arm64: pac
11449 22:18:45.574239 # TAP version 13
11450 22:18:45.574326 # 1..7
11451 22:18:45.577094 # # Starting 7 tests from 1 test cases.
11452 22:18:45.580690 # # RUN global.corrupt_pac ...
11453 22:18:45.583756 # # SKIP PAUTH not enabled
11454 22:18:45.587135 # # OK global.corrupt_pac
11455 22:18:45.590404 # ok 1 # SKIP PAUTH not enabled
11456 22:18:45.596759 # # RUN global.pac_instructions_not_nop ...
11457 22:18:45.600050 # # SKIP PAUTH not enabled
11458 22:18:45.603539 # # OK global.pac_instructions_not_nop
11459 22:18:45.607122 # ok 2 # SKIP PAUTH not enabled
11460 22:18:45.613542 # # RUN global.pac_instructions_not_nop_generic ...
11461 22:18:45.616616 # # SKIP Generic PAUTH not enabled
11462 22:18:45.620250 # # OK global.pac_instructions_not_nop_generic
11463 22:18:45.626683 # ok 3 # SKIP Generic PAUTH not enabled
11464 22:18:45.629794 # # RUN global.single_thread_different_keys ...
11465 22:18:45.633311 # # SKIP PAUTH not enabled
11466 22:18:45.639868 # # OK global.single_thread_different_keys
11467 22:18:45.639952 # ok 4 # SKIP PAUTH not enabled
11468 22:18:45.646481 # # RUN global.exec_changed_keys ...
11469 22:18:45.649879 # # SKIP PAUTH not enabled
11470 22:18:45.653182 # # OK global.exec_changed_keys
11471 22:18:45.656280 # ok 5 # SKIP PAUTH not enabled
11472 22:18:45.659910 # # RUN global.context_switch_keep_keys ...
11473 22:18:45.662975 # # SKIP PAUTH not enabled
11474 22:18:45.669587 # # OK global.context_switch_keep_keys
11475 22:18:45.672727 # ok 6 # SKIP PAUTH not enabled
11476 22:18:45.675912 # # RUN global.context_switch_keep_keys_generic ...
11477 22:18:45.679778 # # SKIP Generic PAUTH not enabled
11478 22:18:45.685864 # # OK global.context_switch_keep_keys_generic
11479 22:18:45.689539 # ok 7 # SKIP Generic PAUTH not enabled
11480 22:18:45.692682 # # PASSED: 7 / 7 tests passed.
11481 22:18:45.696349 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:7 error:0
11482 22:18:45.699561 ok 28 selftests: arm64: pac
11483 22:18:45.702846 # selftests: arm64: fp-stress
11484 22:18:54.079400 <6>[ 46.153381] vpu: disabling
11485 22:18:54.082677 <6>[ 46.156434] vproc2: disabling
11486 22:18:54.085755 <6>[ 46.159720] vproc1: disabling
11487 22:18:54.089169 <6>[ 46.163105] vaud18: disabling
11488 22:18:54.095816 <6>[ 46.166544] vsram_others: disabling
11489 22:18:54.099043 <6>[ 46.170440] va09: disabling
11490 22:18:54.102169 <6>[ 46.173558] vsram_md: disabling
11491 22:18:54.105763 <6>[ 46.177057] Vgpu: disabling
11492 22:18:55.645234 # TAP version 13
11493 22:18:55.645407 # 1..16
11494 22:18:55.648751 # # 8 CPUs, 0 SVE VLs, 0 SME VLs
11495 22:18:55.651736 # # Will run for 10s
11496 22:18:55.651820 # # Started FPSIMD-0-0
11497 22:18:55.655303 # # Started FPSIMD-0-1
11498 22:18:55.658412 # # Started FPSIMD-1-0
11499 22:18:55.658539 # # Started FPSIMD-1-1
11500 22:18:55.661765 # # Started FPSIMD-2-0
11501 22:18:55.661892 # # Started FPSIMD-2-1
11502 22:18:55.665134 # # Started FPSIMD-3-0
11503 22:18:55.668323 # # Started FPSIMD-3-1
11504 22:18:55.668405 # # Started FPSIMD-4-0
11505 22:18:55.671672 # # Started FPSIMD-4-1
11506 22:18:55.674910 # # Started FPSIMD-5-0
11507 22:18:55.675038 # # Started FPSIMD-5-1
11508 22:18:55.678045 # # Started FPSIMD-6-0
11509 22:18:55.681492 # # Started FPSIMD-6-1
11510 22:18:55.681591 # # Started FPSIMD-7-0
11511 22:18:55.684583 # # Started FPSIMD-7-1
11512 22:18:55.688029 # # FPSIMD-0-0: Vector length: 128 bits
11513 22:18:55.691566 # # FPSIMD-0-0: PID: 1129
11514 22:18:55.694507 # # FPSIMD-0-1: Vector length: 128 bits
11515 22:18:55.694590 # # FPSIMD-0-1: PID: 1130
11516 22:18:55.697934 # # FPSIMD-4-0: Vector length: 128 bits
11517 22:18:55.701194 # # FPSIMD-4-0: PID: 1137
11518 22:18:55.704665 # # FPSIMD-2-0: Vector length: 128 bits
11519 22:18:55.707994 # # FPSIMD-2-0: PID: 1133
11520 22:18:55.710875 # # FPSIMD-4-1: Vector length: 128 bits
11521 22:18:55.714482 # # FPSIMD-4-1: PID: 1138
11522 22:18:55.717389 # # FPSIMD-3-0: Vector length: 128 bits
11523 22:18:55.721060 # # FPSIMD-3-0: PID: 1135
11524 22:18:55.723924 # # FPSIMD-1-0: Vector length: 128 bits
11525 22:18:55.724008 # # FPSIMD-1-0: PID: 1131
11526 22:18:55.727192 # # FPSIMD-1-1: Vector length: 128 bits
11527 22:18:55.730605 # # FPSIMD-1-1: PID: 1132
11528 22:18:55.733794 # # FPSIMD-2-1: Vector length: 128 bits
11529 22:18:55.737613 # # FPSIMD-2-1: PID: 1134
11530 22:18:55.740423 # # FPSIMD-3-1: Vector length: 128 bits
11531 22:18:55.743720 # # FPSIMD-3-1: PID: 1136
11532 22:18:55.747512 # # FPSIMD-5-0: Vector length: 128 bits
11533 22:18:55.750594 # # FPSIMD-5-0: PID: 1139
11534 22:18:55.753795 # # FPSIMD-5-1: Vector length: 128 bits
11535 22:18:55.753880 # # FPSIMD-5-1: PID: 1140
11536 22:18:55.757215 # # FPSIMD-7-0: Vector length: 128 bits
11537 22:18:55.760330 # # FPSIMD-7-0: PID: 1143
11538 22:18:55.764090 # # FPSIMD-7-1: Vector length: 128 bits
11539 22:18:55.766946 # # FPSIMD-7-1: PID: 1144
11540 22:18:55.770530 # # FPSIMD-6-1: Vector length: 128 bits
11541 22:18:55.773535 # # FPSIMD-6-1: PID: 1142
11542 22:18:55.777099 # # FPSIMD-6-0: Vector length: 128 bits
11543 22:18:55.777184 # # FPSIMD-6-0: PID: 1141
11544 22:18:55.780111 # # Finishing up...
11545 22:18:55.786912 # # FPSIMD-0-1: Terminated by signal 15, no error, iterations=996181, signals=10
11546 22:18:55.793255 # # FPSIMD-1-1: Terminated by signal 15, no error, iterations=736041, signals=10
11547 22:18:55.803206 # # FPSIMD-3-0: Terminated by signal 15, no error, iterations=526755, signals=10
11548 22:18:55.809798 # # FPSIMD-3-1: Terminated by signal 15, no error, iterations=634134, signals=10
11549 22:18:55.816563 # # FPSIMD-4-1: Terminated by signal 15, no error, iterations=1118698, signals=10
11550 22:18:55.823047 # # FPSIMD-5-1: Terminated by signal 15, no error, iterations=1698000, signals=10
11551 22:18:55.829715 # # FPSIMD-2-1: Terminated by signal 15, no error, iterations=330802, signals=10
11552 22:18:55.833054 # ok 1 FPSIMD-0-0
11553 22:18:55.833139 # ok 2 FPSIMD-0-1
11554 22:18:55.836139 # ok 3 FPSIMD-1-0
11555 22:18:55.836223 # ok 4 FPSIMD-1-1
11556 22:18:55.839389 # ok 5 FPSIMD-2-0
11557 22:18:55.839473 # ok 6 FPSIMD-2-1
11558 22:18:55.843292 # ok 7 FPSIMD-3-0
11559 22:18:55.843376 # ok 8 FPSIMD-3-1
11560 22:18:55.846240 # ok 9 FPSIMD-4-0
11561 22:18:55.846324 # ok 10 FPSIMD-4-1
11562 22:18:55.849506 # ok 11 FPSIMD-5-0
11563 22:18:55.849590 # ok 12 FPSIMD-5-1
11564 22:18:55.852643 # ok 13 FPSIMD-6-0
11565 22:18:55.852732 # ok 14 FPSIMD-6-1
11566 22:18:55.855995 # ok 15 FPSIMD-7-0
11567 22:18:55.856073 # ok 16 FPSIMD-7-1
11568 22:18:55.865995 # # FPSIMD-1-0: Terminated by signal 15, no error, iterations=1520420, signals=9
11569 22:18:55.872860 # # FPSIMD-0-0: Terminated by signal 15, no error, iterations=779493, signals=10
11570 22:18:55.879272 # # FPSIMD-7-1: Terminated by signal 15, no error, iterations=329679, signals=10
11571 22:18:55.886125 # # FPSIMD-2-0: Terminated by signal 15, no error, iterations=1299129, signals=10
11572 22:18:55.892448 # # FPSIMD-5-0: Terminated by signal 15, no error, iterations=632894, signals=10
11573 22:18:55.899265 # # FPSIMD-7-0: Terminated by signal 15, no error, iterations=663340, signals=9
11574 22:18:55.905655 # # FPSIMD-6-0: Terminated by signal 15, no error, iterations=387895, signals=9
11575 22:18:55.915476 # # FPSIMD-6-1: Terminated by signal 15, no error, iterations=327322, signals=10
11576 22:18:55.921925 # # FPSIMD-4-0: Terminated by signal 15, no error, iterations=794061, signals=10
11577 22:18:55.925805 # # Totals: pass:16 fail:0 xfail:0 xpass:0 skip:0 error:0
11578 22:18:55.928598 ok 29 selftests: arm64: fp-stress
11579 22:18:55.931960 # selftests: arm64: sve-ptrace
11580 22:18:55.935322 # TAP version 13
11581 22:18:55.935398 # 1..4104
11582 22:18:55.938421 # ok 2 # SKIP SVE not available
11583 22:18:55.941858 # # Planned tests != run tests (4104 != 1)
11584 22:18:55.945007 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11585 22:18:55.951798 ok 30 selftests: arm64: sve-ptrace # SKIP
11586 22:18:55.951886 # selftests: arm64: sve-probe-vls
11587 22:18:55.955354 # TAP version 13
11588 22:18:55.955438 # 1..2
11589 22:18:55.958549 # ok 2 # SKIP SVE not available
11590 22:18:55.961536 # # Planned tests != run tests (2 != 1)
11591 22:18:55.968286 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11592 22:18:55.971682 ok 31 selftests: arm64: sve-probe-vls # SKIP
11593 22:18:55.975195 # selftests: arm64: vec-syscfg
11594 22:18:55.975281 # TAP version 13
11595 22:18:55.975347 # 1..20
11596 22:18:55.978041 # ok 1 # SKIP SVE not supported
11597 22:18:55.981249 # ok 2 # SKIP SVE not supported
11598 22:18:55.984692 # ok 3 # SKIP SVE not supported
11599 22:18:55.987928 # ok 4 # SKIP SVE not supported
11600 22:18:55.991311 # ok 5 # SKIP SVE not supported
11601 22:18:55.994772 # ok 6 # SKIP SVE not supported
11602 22:18:55.994855 # ok 7 # SKIP SVE not supported
11603 22:18:55.998161 # ok 8 # SKIP SVE not supported
11604 22:18:56.001315 # ok 9 # SKIP SVE not supported
11605 22:18:56.004416 # ok 10 # SKIP SVE not supported
11606 22:18:56.007955 # ok 11 # SKIP SME not supported
11607 22:18:56.011253 # ok 12 # SKIP SME not supported
11608 22:18:56.014430 # ok 13 # SKIP SME not supported
11609 22:18:56.017536 # ok 14 # SKIP SME not supported
11610 22:18:56.020956 # ok 15 # SKIP SME not supported
11611 22:18:56.021039 # ok 16 # SKIP SME not supported
11612 22:18:56.024214 # ok 17 # SKIP SME not supported
11613 22:18:56.027973 # ok 18 # SKIP SME not supported
11614 22:18:56.030759 # ok 19 # SKIP SME not supported
11615 22:18:56.034292 # ok 20 # SKIP SME not supported
11616 22:18:56.041089 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:20 error:0
11617 22:18:56.044156 ok 32 selftests: arm64: vec-syscfg
11618 22:18:56.044239 # selftests: arm64: za-fork
11619 22:18:56.047577 # TAP version 13
11620 22:18:56.047660 # 1..1
11621 22:18:56.047725 # # PID: 1214
11622 22:18:56.050989 # # SME support not present
11623 22:18:56.053770 # ok 0 skipped
11624 22:18:56.057329 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11625 22:18:56.060743 ok 33 selftests: arm64: za-fork
11626 22:18:56.063897 # selftests: arm64: za-ptrace
11627 22:18:56.063972 # TAP version 13
11628 22:18:56.064035 # 1..1
11629 22:18:56.067191 # ok 2 # SKIP SME not available
11630 22:18:56.073660 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11631 22:18:56.077001 ok 34 selftests: arm64: za-ptrace # SKIP
11632 22:18:56.080337 # selftests: arm64: check_buffer_fill
11633 22:18:56.083684 # # SKIP: MTE features unavailable
11634 22:18:56.087216 ok 35 selftests: arm64: check_buffer_fill # SKIP
11635 22:18:56.090169 # selftests: arm64: check_child_memory
11636 22:18:56.093796 # # SKIP: MTE features unavailable
11637 22:18:56.100233 ok 36 selftests: arm64: check_child_memory # SKIP
11638 22:18:56.103571 # selftests: arm64: check_gcr_el1_cswitch
11639 22:18:56.144673 # # SKIP: MTE features unavailable
11640 22:18:56.151438 ok 37 selftests: arm64: check_gcr_el1_cswitch # SKIP
11641 22:18:56.163212 # selftests: arm64: check_ksm_options
11642 22:18:56.205420 # # SKIP: MTE features unavailable
11643 22:18:56.212365 ok 38 selftests: arm64: check_ksm_options # SKIP
11644 22:18:56.225092 # selftests: arm64: check_mmap_options
11645 22:18:56.266737 # # SKIP: MTE features unavailable
11646 22:18:56.273943 ok 39 selftests: arm64: check_mmap_options # SKIP
11647 22:18:56.283891 # selftests: arm64: check_prctl
11648 22:18:56.330334 # TAP version 13
11649 22:18:56.330475 # 1..5
11650 22:18:56.333494 # ok 1 check_basic_read
11651 22:18:56.333579 # ok 2 NONE
11652 22:18:56.336553 # ok 3 # SKIP SYNC
11653 22:18:56.336664 # ok 4 # SKIP ASYNC
11654 22:18:56.339858 # ok 5 # SKIP SYNC+ASYNC
11655 22:18:56.342937 # # Totals: pass:2 fail:0 xfail:0 xpass:0 skip:3 error:0
11656 22:18:56.346393 ok 40 selftests: arm64: check_prctl
11657 22:18:56.352941 # selftests: arm64: check_tags_inclusion
11658 22:18:56.388728 # # SKIP: MTE features unavailable
11659 22:18:56.395361 ok 41 selftests: arm64: check_tags_inclusion # SKIP
11660 22:18:56.403411 # selftests: arm64: check_user_mem
11661 22:18:56.447546 # # SKIP: MTE features unavailable
11662 22:18:56.454113 ok 42 selftests: arm64: check_user_mem # SKIP
11663 22:18:56.462317 # selftests: arm64: btitest
11664 22:18:56.507601 # TAP version 13
11665 22:18:56.507722 # 1..18
11666 22:18:56.510526 # # HWCAP_PACA not present
11667 22:18:56.514099 # # HWCAP2_BTI not present
11668 22:18:56.514184 # # Test binary built for BTI
11669 22:18:56.520462 # ok 1 nohint_func/call_using_br_x0 # SKIP
11670 22:18:56.523769 # ok 1 nohint_func/call_using_br_x16 # SKIP
11671 22:18:56.527191 # ok 1 nohint_func/call_using_blr # SKIP
11672 22:18:56.530773 # ok 1 bti_none_func/call_using_br_x0 # SKIP
11673 22:18:56.533551 # ok 1 bti_none_func/call_using_br_x16 # SKIP
11674 22:18:56.540265 # ok 1 bti_none_func/call_using_blr # SKIP
11675 22:18:56.543602 # ok 1 bti_c_func/call_using_br_x0 # SKIP
11676 22:18:56.547385 # ok 1 bti_c_func/call_using_br_x16 # SKIP
11677 22:18:56.550289 # ok 1 bti_c_func/call_using_blr # SKIP
11678 22:18:56.553519 # ok 1 bti_j_func/call_using_br_x0 # SKIP
11679 22:18:56.557090 # ok 1 bti_j_func/call_using_br_x16 # SKIP
11680 22:18:56.560288 # ok 1 bti_j_func/call_using_blr # SKIP
11681 22:18:56.563358 # ok 1 bti_jc_func/call_using_br_x0 # SKIP
11682 22:18:56.570124 # ok 1 bti_jc_func/call_using_br_x16 # SKIP
11683 22:18:56.573564 # ok 1 bti_jc_func/call_using_blr # SKIP
11684 22:18:56.576894 # ok 1 paciasp_func/call_using_br_x0 # SKIP
11685 22:18:56.580096 # ok 1 paciasp_func/call_using_br_x16 # SKIP
11686 22:18:56.583409 # ok 1 paciasp_func/call_using_blr # SKIP
11687 22:18:56.589999 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:18 error:0
11688 22:18:56.593111 # # WARNING - EXPECTED TEST COUNT WRONG
11689 22:18:56.596890 ok 43 selftests: arm64: btitest
11690 22:18:56.599954 # selftests: arm64: nobtitest
11691 22:18:56.600038 # TAP version 13
11692 22:18:56.600104 # 1..18
11693 22:18:56.602932 # # HWCAP_PACA not present
11694 22:18:56.606677 # # HWCAP2_BTI not present
11695 22:18:56.609749 # # Test binary not built for BTI
11696 22:18:56.613161 # ok 1 nohint_func/call_using_br_x0 # SKIP
11697 22:18:56.616220 # ok 1 nohint_func/call_using_br_x16 # SKIP
11698 22:18:56.619802 # ok 1 nohint_func/call_using_blr # SKIP
11699 22:18:56.622946 # ok 1 bti_none_func/call_using_br_x0 # SKIP
11700 22:18:56.629509 # ok 1 bti_none_func/call_using_br_x16 # SKIP
11701 22:18:56.632904 # ok 1 bti_none_func/call_using_blr # SKIP
11702 22:18:56.635852 # ok 1 bti_c_func/call_using_br_x0 # SKIP
11703 22:18:56.639378 # ok 1 bti_c_func/call_using_br_x16 # SKIP
11704 22:18:56.643139 # ok 1 bti_c_func/call_using_blr # SKIP
11705 22:18:56.646051 # ok 1 bti_j_func/call_using_br_x0 # SKIP
11706 22:18:56.649443 # ok 1 bti_j_func/call_using_br_x16 # SKIP
11707 22:18:56.652402 # ok 1 bti_j_func/call_using_blr # SKIP
11708 22:18:56.658970 # ok 1 bti_jc_func/call_using_br_x0 # SKIP
11709 22:18:56.662343 # ok 1 bti_jc_func/call_using_br_x16 # SKIP
11710 22:18:56.665949 # ok 1 bti_jc_func/call_using_blr # SKIP
11711 22:18:56.669129 # ok 1 paciasp_func/call_using_br_x0 # SKIP
11712 22:18:56.672237 # ok 1 paciasp_func/call_using_br_x16 # SKIP
11713 22:18:56.675843 # ok 1 paciasp_func/call_using_blr # SKIP
11714 22:18:56.682175 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:18 error:0
11715 22:18:56.685634 # # WARNING - EXPECTED TEST COUNT WRONG
11716 22:18:56.688903 ok 44 selftests: arm64: nobtitest
11717 22:18:56.691876 # selftests: arm64: hwcap
11718 22:18:56.691959 # TAP version 13
11719 22:18:56.692024 # 1..28
11720 22:18:56.695550 # ok 1 cpuinfo_match_RNG
11721 22:18:56.698529 # # SIGILL reported for RNG
11722 22:18:56.701981 # ok 2 # SKIP sigill_RNG
11723 22:18:56.702064 # ok 3 cpuinfo_match_SME
11724 22:18:56.705337 # ok 4 sigill_SME
11725 22:18:56.705419 # ok 5 cpuinfo_match_SVE
11726 22:18:56.708660 # ok 6 sigill_SVE
11727 22:18:56.711894 # ok 7 cpuinfo_match_SVE 2
11728 22:18:56.711976 # # SIGILL reported for SVE 2
11729 22:18:56.715014 # ok 8 # SKIP sigill_SVE 2
11730 22:18:56.718789 # ok 9 cpuinfo_match_SVE AES
11731 22:18:56.721801 # # SIGILL reported for SVE AES
11732 22:18:56.725168 # ok 10 # SKIP sigill_SVE AES
11733 22:18:56.728593 # ok 11 cpuinfo_match_SVE2 PMULL
11734 22:18:56.728675 # # SIGILL reported for SVE2 PMULL
11735 22:18:56.731603 # ok 12 # SKIP sigill_SVE2 PMULL
11736 22:18:56.734898 # ok 13 cpuinfo_match_SVE2 BITPERM
11737 22:18:56.738353 # # SIGILL reported for SVE2 BITPERM
11738 22:18:56.741901 # ok 14 # SKIP sigill_SVE2 BITPERM
11739 22:18:56.745184 # ok 15 cpuinfo_match_SVE2 SHA3
11740 22:18:56.748259 # # SIGILL reported for SVE2 SHA3
11741 22:18:56.751537 # ok 16 # SKIP sigill_SVE2 SHA3
11742 22:18:56.754781 # ok 17 cpuinfo_match_SVE2 SM4
11743 22:18:56.758291 # # SIGILL reported for SVE2 SM4
11744 22:18:56.758378 # ok 18 # SKIP sigill_SVE2 SM4
11745 22:18:56.761485 # ok 19 cpuinfo_match_SVE2 I8MM
11746 22:18:56.764998 # # SIGILL reported for SVE2 I8MM
11747 22:18:56.767890 # ok 20 # SKIP sigill_SVE2 I8MM
11748 22:18:56.771422 # ok 21 cpuinfo_match_SVE2 F32MM
11749 22:18:56.774660 # # SIGILL reported for SVE2 F32MM
11750 22:18:56.778302 # ok 22 # SKIP sigill_SVE2 F32MM
11751 22:18:56.781763 # ok 23 cpuinfo_match_SVE2 F64MM
11752 22:18:56.785320 # # SIGILL reported for SVE2 F64MM
11753 22:18:56.787941 # ok 24 # SKIP sigill_SVE2 F64MM
11754 22:18:56.788025 # ok 25 cpuinfo_match_SVE2 BF16
11755 22:18:56.791249 # # SIGILL reported for SVE2 BF16
11756 22:18:56.794885 # ok 26 # SKIP sigill_SVE2 BF16
11757 22:18:56.797772 # ok 27 cpuinfo_match_SVE2 EBF16
11758 22:18:56.801325 # ok 28 # SKIP sigill_SVE2 EBF16
11759 22:18:56.807970 # # Totals: pass:16 fail:0 xfail:0 xpass:0 skip:12 error:0
11760 22:18:56.808055 ok 45 selftests: arm64: hwcap
11761 22:18:56.811156 # selftests: arm64: ptrace
11762 22:18:56.814275 # TAP version 13
11763 22:18:56.814359 # 1..7
11764 22:18:56.817813 # # Parent is 1443, child is 1444
11765 22:18:56.817897 # ok 1 read_tpidr_one
11766 22:18:56.820794 # ok 2 write_tpidr_one
11767 22:18:56.824124 # ok 3 verify_tpidr_one
11768 22:18:56.824208 # ok 4 count_tpidrs
11769 22:18:56.827415 # ok 5 tpidr2_write
11770 22:18:56.827498 # ok 6 tpidr2_read
11771 22:18:56.830737 # ok 7 write_tpidr_only
11772 22:18:56.834041 # # Totals: pass:7 fail:0 xfail:0 xpass:0 skip:0 error:0
11773 22:18:56.837392 ok 46 selftests: arm64: ptrace
11774 22:18:56.840620 # selftests: arm64: syscall-abi
11775 22:18:56.843970 # TAP version 13
11776 22:18:56.844054 # 1..2
11777 22:18:56.844120 # ok 1 getpid() FPSIMD
11778 22:18:56.847724 # ok 2 sched_yield() FPSIMD
11779 22:18:56.853968 # # Totals: pass:2 fail:0 xfail:0 xpass:0 skip:0 error:0
11780 22:18:56.857375 ok 47 selftests: arm64: syscall-abi
11781 22:18:56.857460 # selftests: arm64: tpidr2
11782 22:18:56.860584 # TAP version 13
11783 22:18:56.860668 # 1..5
11784 22:18:56.864276 # # PID: 1478
11785 22:18:56.864359 # # SME support not present
11786 22:18:56.867608 # ok 0 skipped, TPIDR2 not supported
11787 22:18:56.870560 # ok 1 skipped, TPIDR2 not supported
11788 22:18:56.874261 # ok 2 skipped, TPIDR2 not supported
11789 22:18:56.876898 # ok 3 skipped, TPIDR2 not supported
11790 22:18:56.880179 # ok 4 skipped, TPIDR2 not supported
11791 22:18:56.886931 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:5 error:0
11792 22:18:56.890125 ok 48 selftests: arm64: tpidr2
11793 22:18:57.324256 arm64_tags_test pass
11794 22:18:57.327247 arm64_run_tags_test_sh pass
11795 22:18:57.330571 arm64_fake_sigreturn_bad_magic pass
11796 22:18:57.333958 arm64_fake_sigreturn_bad_size pass
11797 22:18:57.337407 arm64_fake_sigreturn_bad_size_for_magic0 pass
11798 22:18:57.340312 arm64_fake_sigreturn_duplicated_fpsimd pass
11799 22:18:57.343616 arm64_fake_sigreturn_misaligned_sp pass
11800 22:18:57.347200 arm64_fake_sigreturn_missing_fpsimd pass
11801 22:18:57.350176 arm64_fake_sigreturn_sme_change_vl skip
11802 22:18:57.357036 arm64_fake_sigreturn_sve_change_vl skip
11803 22:18:57.360277 arm64_mangle_pstate_invalid_compat_toggle pass
11804 22:18:57.363278 arm64_mangle_pstate_invalid_daif_bits pass
11805 22:18:57.366886 arm64_mangle_pstate_invalid_mode_el1h pass
11806 22:18:57.370337 arm64_mangle_pstate_invalid_mode_el1t pass
11807 22:18:57.373332 arm64_mangle_pstate_invalid_mode_el2h pass
11808 22:18:57.380212 arm64_mangle_pstate_invalid_mode_el2t pass
11809 22:18:57.383117 arm64_mangle_pstate_invalid_mode_el3h pass
11810 22:18:57.386674 arm64_mangle_pstate_invalid_mode_el3t pass
11811 22:18:57.389793 arm64_sme_trap_no_sm skip
11812 22:18:57.393314 arm64_sme_trap_non_streaming skip
11813 22:18:57.393399 arm64_sme_trap_za pass
11814 22:18:57.396604 arm64_sme_vl skip
11815 22:18:57.396687 arm64_ssve_regs skip
11816 22:18:57.399636 arm64_sve_regs skip
11817 22:18:57.399720 arm64_sve_vl skip
11818 22:18:57.403202 arm64_za_no_regs skip
11819 22:18:57.403287 arm64_za_regs skip
11820 22:18:57.406543 arm64_pac_PAUTH_not_enabled skip
11821 22:18:57.409620 arm64_pac_PAUTH_not_enabled skip
11822 22:18:57.412883 arm64_pac_Generic_PAUTH_not_enabled skip
11823 22:18:57.416097 arm64_pac_PAUTH_not_enabled skip
11824 22:18:57.419532 arm64_pac_PAUTH_not_enabled skip
11825 22:18:57.422997 arm64_pac_PAUTH_not_enabled skip
11826 22:18:57.426385 arm64_pac_Generic_PAUTH_not_enabled skip
11827 22:18:57.429459 arm64_pac pass
11828 22:18:57.429538 arm64_fp-stress_FPSIMD-0-0 pass
11829 22:18:57.432920 arm64_fp-stress_FPSIMD-0-1 pass
11830 22:18:57.436158 arm64_fp-stress_FPSIMD-1-0 pass
11831 22:18:57.439348 arm64_fp-stress_FPSIMD-1-1 pass
11832 22:18:57.442593 arm64_fp-stress_FPSIMD-2-0 pass
11833 22:18:57.445974 arm64_fp-stress_FPSIMD-2-1 pass
11834 22:18:57.449323 arm64_fp-stress_FPSIMD-3-0 pass
11835 22:18:57.452723 arm64_fp-stress_FPSIMD-3-1 pass
11836 22:18:57.452815 arm64_fp-stress_FPSIMD-4-0 pass
11837 22:18:57.455886 arm64_fp-stress_FPSIMD-4-1 pass
11838 22:18:57.459055 arm64_fp-stress_FPSIMD-5-0 pass
11839 22:18:57.462451 arm64_fp-stress_FPSIMD-5-1 pass
11840 22:18:57.465689 arm64_fp-stress_FPSIMD-6-0 pass
11841 22:18:57.468879 arm64_fp-stress_FPSIMD-6-1 pass
11842 22:18:57.472695 arm64_fp-stress_FPSIMD-7-0 pass
11843 22:18:57.472798 arm64_fp-stress_FPSIMD-7-1 pass
11844 22:18:57.475650 arm64_fp-stress pass
11845 22:18:57.478731 arm64_sve-ptrace_SVE_not_available skip
11846 22:18:57.482494 arm64_sve-ptrace skip
11847 22:18:57.485486 arm64_sve-probe-vls_SVE_not_available skip
11848 22:18:57.489109 arm64_sve-probe-vls skip
11849 22:18:57.492104 arm64_vec-syscfg_SVE_not_supported skip
11850 22:18:57.495391 arm64_vec-syscfg_SVE_not_supported skip
11851 22:18:57.498933 arm64_vec-syscfg_SVE_not_supported skip
11852 22:18:57.502421 arm64_vec-syscfg_SVE_not_supported skip
11853 22:18:57.505419 arm64_vec-syscfg_SVE_not_supported skip
11854 22:18:57.508947 arm64_vec-syscfg_SVE_not_supported skip
11855 22:18:57.512407 arm64_vec-syscfg_SVE_not_supported skip
11856 22:18:57.515097 arm64_vec-syscfg_SVE_not_supported skip
11857 22:18:57.518913 arm64_vec-syscfg_SVE_not_supported skip
11858 22:18:57.521662 arm64_vec-syscfg_SVE_not_supported skip
11859 22:18:57.525214 arm64_vec-syscfg_SME_not_supported skip
11860 22:18:57.531714 arm64_vec-syscfg_SME_not_supported skip
11861 22:18:57.534911 arm64_vec-syscfg_SME_not_supported skip
11862 22:18:57.538286 arm64_vec-syscfg_SME_not_supported skip
11863 22:18:57.541965 arm64_vec-syscfg_SME_not_supported skip
11864 22:18:57.545181 arm64_vec-syscfg_SME_not_supported skip
11865 22:18:57.548054 arm64_vec-syscfg_SME_not_supported skip
11866 22:18:57.551521 arm64_vec-syscfg_SME_not_supported skip
11867 22:18:57.555032 arm64_vec-syscfg_SME_not_supported skip
11868 22:18:57.558158 arm64_vec-syscfg_SME_not_supported skip
11869 22:18:57.561775 arm64_vec-syscfg pass
11870 22:18:57.561859 arm64_za-fork_skipped pass
11871 22:18:57.564693 arm64_za-fork pass
11872 22:18:57.567886 arm64_za-ptrace_SME_not_available skip
11873 22:18:57.571326 arm64_za-ptrace skip
11874 22:18:57.571408 arm64_check_buffer_fill skip
11875 22:18:57.574542 arm64_check_child_memory skip
11876 22:18:57.578171 arm64_check_gcr_el1_cswitch skip
11877 22:18:57.581067 arm64_check_ksm_options skip
11878 22:18:57.584705 arm64_check_mmap_options skip
11879 22:18:57.588061 arm64_check_prctl_check_basic_read pass
11880 22:18:57.590951 arm64_check_prctl_NONE pass
11881 22:18:57.591033 arm64_check_prctl_SYNC skip
11882 22:18:57.594570 arm64_check_prctl_ASYNC skip
11883 22:18:57.597906 arm64_check_prctl_SYNC_ASYNC skip
11884 22:18:57.600790 arm64_check_prctl pass
11885 22:18:57.604596 arm64_check_tags_inclusion skip
11886 22:18:57.604678 arm64_check_user_mem skip
11887 22:18:57.610959 arm64_btitest_nohint_func_call_using_br_x0 skip
11888 22:18:57.614077 arm64_btitest_nohint_func_call_using_br_x16 skip
11889 22:18:57.617603 arm64_btitest_nohint_func_call_using_blr skip
11890 22:18:57.621169 arm64_btitest_bti_none_func_call_using_br_x0 skip
11891 22:18:57.627342 arm64_btitest_bti_none_func_call_using_br_x16 skip
11892 22:18:57.630562 arm64_btitest_bti_none_func_call_using_blr skip
11893 22:18:57.633798 arm64_btitest_bti_c_func_call_using_br_x0 skip
11894 22:18:57.640608 arm64_btitest_bti_c_func_call_using_br_x16 skip
11895 22:18:57.643746 arm64_btitest_bti_c_func_call_using_blr skip
11896 22:18:57.647199 arm64_btitest_bti_j_func_call_using_br_x0 skip
11897 22:18:57.650581 arm64_btitest_bti_j_func_call_using_br_x16 skip
11898 22:18:57.657296 arm64_btitest_bti_j_func_call_using_blr skip
11899 22:18:57.660728 arm64_btitest_bti_jc_func_call_using_br_x0 skip
11900 22:18:57.663700 arm64_btitest_bti_jc_func_call_using_br_x16 skip
11901 22:18:57.667231 arm64_btitest_bti_jc_func_call_using_blr skip
11902 22:18:57.674043 arm64_btitest_paciasp_func_call_using_br_x0 skip
11903 22:18:57.677111 arm64_btitest_paciasp_func_call_using_br_x16 skip
11904 22:18:57.679896 arm64_btitest_paciasp_func_call_using_blr skip
11905 22:18:57.683535 arm64_btitest pass
11906 22:18:57.686733 arm64_nobtitest_nohint_func_call_using_br_x0 skip
11907 22:18:57.693547 arm64_nobtitest_nohint_func_call_using_br_x16 skip
11908 22:18:57.696497 arm64_nobtitest_nohint_func_call_using_blr skip
11909 22:18:57.700121 arm64_nobtitest_bti_none_func_call_using_br_x0 skip
11910 22:18:57.706713 arm64_nobtitest_bti_none_func_call_using_br_x16 skip
11911 22:18:57.709930 arm64_nobtitest_bti_none_func_call_using_blr skip
11912 22:18:57.713330 arm64_nobtitest_bti_c_func_call_using_br_x0 skip
11913 22:18:57.719794 arm64_nobtitest_bti_c_func_call_using_br_x16 skip
11914 22:18:57.723016 arm64_nobtitest_bti_c_func_call_using_blr skip
11915 22:18:57.726631 arm64_nobtitest_bti_j_func_call_using_br_x0 skip
11916 22:18:57.732864 arm64_nobtitest_bti_j_func_call_using_br_x16 skip
11917 22:18:57.736204 arm64_nobtitest_bti_j_func_call_using_blr skip
11918 22:18:57.739662 arm64_nobtitest_bti_jc_func_call_using_br_x0 skip
11919 22:18:57.746582 arm64_nobtitest_bti_jc_func_call_using_br_x16 skip
11920 22:18:57.749226 arm64_nobtitest_bti_jc_func_call_using_blr skip
11921 22:18:57.752613 arm64_nobtitest_paciasp_func_call_using_br_x0 skip
11922 22:18:57.759692 arm64_nobtitest_paciasp_func_call_using_br_x16 skip
11923 22:18:57.762357 arm64_nobtitest_paciasp_func_call_using_blr skip
11924 22:18:57.765887 arm64_nobtitest pass
11925 22:18:57.769234 arm64_hwcap_cpuinfo_match_RNG pass
11926 22:18:57.769308 arm64_hwcap_sigill_RNG skip
11927 22:18:57.772260 arm64_hwcap_cpuinfo_match_SME pass
11928 22:18:57.775501 arm64_hwcap_sigill_SME pass
11929 22:18:57.779242 arm64_hwcap_cpuinfo_match_SVE pass
11930 22:18:57.782281 arm64_hwcap_sigill_SVE pass
11931 22:18:57.785659 arm64_hwcap_cpuinfo_match_SVE_2 pass
11932 22:18:57.789136 arm64_hwcap_sigill_SVE_2 skip
11933 22:18:57.792128 arm64_hwcap_cpuinfo_match_SVE_AES pass
11934 22:18:57.792202 arm64_hwcap_sigill_SVE_AES skip
11935 22:18:57.798870 arm64_hwcap_cpuinfo_match_SVE2_PMULL pass
11936 22:18:57.802281 arm64_hwcap_sigill_SVE2_PMULL skip
11937 22:18:57.805384 arm64_hwcap_cpuinfo_match_SVE2_BITPERM pass
11938 22:18:57.808696 arm64_hwcap_sigill_SVE2_BITPERM skip
11939 22:18:57.811956 arm64_hwcap_cpuinfo_match_SVE2_SHA3 pass
11940 22:18:57.815310 arm64_hwcap_sigill_SVE2_SHA3 skip
11941 22:18:57.818961 arm64_hwcap_cpuinfo_match_SVE2_SM4 pass
11942 22:18:57.822128 arm64_hwcap_sigill_SVE2_SM4 skip
11943 22:18:57.825366 arm64_hwcap_cpuinfo_match_SVE2_I8MM pass
11944 22:18:57.828602 arm64_hwcap_sigill_SVE2_I8MM skip
11945 22:18:57.832065 arm64_hwcap_cpuinfo_match_SVE2_F32MM pass
11946 22:18:57.835179 arm64_hwcap_sigill_SVE2_F32MM skip
11947 22:18:57.838557 arm64_hwcap_cpuinfo_match_SVE2_F64MM pass
11948 22:18:57.841898 arm64_hwcap_sigill_SVE2_F64MM skip
11949 22:18:57.845483 arm64_hwcap_cpuinfo_match_SVE2_BF16 pass
11950 22:18:57.848341 arm64_hwcap_sigill_SVE2_BF16 skip
11951 22:18:57.851735 arm64_hwcap_cpuinfo_match_SVE2_EBF16 pass
11952 22:18:57.855222 arm64_hwcap_sigill_SVE2_EBF16 skip
11953 22:18:57.855299 arm64_hwcap pass
11954 22:18:57.858613 arm64_ptrace_read_tpidr_one pass
11955 22:18:57.861770 arm64_ptrace_write_tpidr_one pass
11956 22:18:57.865037 arm64_ptrace_verify_tpidr_one pass
11957 22:18:57.868337 arm64_ptrace_count_tpidrs pass
11958 22:18:57.871461 arm64_ptrace_tpidr2_write pass
11959 22:18:57.874597 arm64_ptrace_tpidr2_read pass
11960 22:18:57.878035 arm64_ptrace_write_tpidr_only pass
11961 22:18:57.878108 arm64_ptrace pass
11962 22:18:57.881735 arm64_syscall-abi_getpid_FPSIMD pass
11963 22:18:57.884511 arm64_syscall-abi_sched_yield_FPSIMD pass
11964 22:18:57.887955 arm64_syscall-abi pass
11965 22:18:57.891047 arm64_tpidr2_skipped_TPIDR2_not_supported pass
11966 22:18:57.894536 arm64_tpidr2_skipped_TPIDR2_not_supported pass
11967 22:18:57.901211 arm64_tpidr2_skipped_TPIDR2_not_supported pass
11968 22:18:57.904281 arm64_tpidr2_skipped_TPIDR2_not_supported pass
11969 22:18:57.907749 arm64_tpidr2_skipped_TPIDR2_not_supported pass
11970 22:18:57.911049 arm64_tpidr2 pass
11971 22:18:57.914221 + ../../utils/send-to-lava.sh ./output/result.txt
11972 22:18:57.920752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tags_test RESULT=pass>
11973 22:18:57.921028 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tags_test RESULT=pass
11975 22:18:57.927604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_run_tags_test_sh RESULT=pass>
11976 22:18:57.927861 Received signal: <TESTCASE> TEST_CASE_ID=arm64_run_tags_test_sh RESULT=pass
11978 22:18:57.934281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_magic RESULT=pass>
11979 22:18:57.934534 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_magic RESULT=pass
11981 22:18:57.941046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_size RESULT=pass>
11982 22:18:57.941294 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_size RESULT=pass
11984 22:18:57.947523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_size_for_magic0 RESULT=pass>
11985 22:18:57.947768 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_size_for_magic0 RESULT=pass
11987 22:18:57.957046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_duplicated_fpsimd RESULT=pass>
11988 22:18:57.957296 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_duplicated_fpsimd RESULT=pass
11990 22:18:57.963689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_misaligned_sp RESULT=pass>
11991 22:18:57.963942 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_misaligned_sp RESULT=pass
11993 22:18:57.993363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_missing_fpsimd RESULT=pass>
11994 22:18:57.993649 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_missing_fpsimd RESULT=pass
11996 22:18:58.029827 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_sme_change_vl RESULT=skip>
11997 22:18:58.030122 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_sme_change_vl RESULT=skip
11999 22:18:58.066916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_sve_change_vl RESULT=skip>
12000 22:18:58.067226 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_sve_change_vl RESULT=skip
12002 22:18:58.100142 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_compat_toggle RESULT=pass>
12003 22:18:58.100449 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_compat_toggle RESULT=pass
12005 22:18:58.138047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_daif_bits RESULT=pass>
12006 22:18:58.138318 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_daif_bits RESULT=pass
12008 22:18:58.171947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1h RESULT=pass>
12009 22:18:58.172216 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1h RESULT=pass
12011 22:18:58.216171 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1t RESULT=pass>
12012 22:18:58.216459 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1t RESULT=pass
12014 22:18:58.256792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2h RESULT=pass>
12015 22:18:58.257079 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2h RESULT=pass
12017 22:18:58.301875 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2t RESULT=pass>
12018 22:18:58.302200 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2t RESULT=pass
12020 22:18:58.338334 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3h RESULT=pass>
12021 22:18:58.338607 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3h RESULT=pass
12023 22:18:58.375229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3t RESULT=pass>
12024 22:18:58.375509 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3t RESULT=pass
12026 22:18:58.407559 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_no_sm RESULT=skip>
12027 22:18:58.407826 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_no_sm RESULT=skip
12029 22:18:58.439699 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_non_streaming RESULT=skip
12031 22:18:58.442929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_non_streaming RESULT=skip>
12032 22:18:58.476280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_za RESULT=pass>
12033 22:18:58.476548 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_za RESULT=pass
12035 22:18:58.509246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_vl RESULT=skip>
12036 22:18:58.509507 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_vl RESULT=skip
12038 22:18:58.542370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ssve_regs RESULT=skip>
12039 22:18:58.542634 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ssve_regs RESULT=skip
12041 22:18:58.574920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve_regs RESULT=skip>
12042 22:18:58.575181 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve_regs RESULT=skip
12044 22:18:58.610017 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve_vl RESULT=skip>
12045 22:18:58.610273 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve_vl RESULT=skip
12047 22:18:58.644803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za_no_regs RESULT=skip>
12048 22:18:58.645106 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za_no_regs RESULT=skip
12050 22:18:58.675310 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za_regs RESULT=skip>
12051 22:18:58.675600 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za_regs RESULT=skip
12053 22:18:58.709894 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip
12055 22:18:58.712328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip>
12056 22:18:58.742981 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip
12058 22:18:58.746071 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip>
12059 22:18:58.778454 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_Generic_PAUTH_not_enabled RESULT=skip>
12060 22:18:58.778722 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_Generic_PAUTH_not_enabled RESULT=skip
12062 22:18:58.815385 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip
12064 22:18:58.818670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip>
12065 22:18:58.851319 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip
12067 22:18:58.854560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip>
12068 22:18:58.885657 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip
12070 22:18:58.889205 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip>
12071 22:18:58.926065 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_Generic_PAUTH_not_enabled RESULT=skip>
12072 22:18:58.926329 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_Generic_PAUTH_not_enabled RESULT=skip
12074 22:18:58.957858 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac RESULT=pass>
12075 22:18:58.958121 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac RESULT=pass
12077 22:18:58.993342 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-0 RESULT=pass
12079 22:18:58.996507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-0 RESULT=pass>
12080 22:18:59.026515 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-1 RESULT=pass>
12081 22:18:59.026771 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-1 RESULT=pass
12083 22:18:59.060387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-0 RESULT=pass>
12084 22:18:59.060649 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-0 RESULT=pass
12086 22:18:59.093486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-1 RESULT=pass>
12087 22:18:59.093747 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-1 RESULT=pass
12089 22:18:59.126190 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-0 RESULT=pass>
12090 22:18:59.126448 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-0 RESULT=pass
12092 22:18:59.158219 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-1 RESULT=pass>
12093 22:18:59.158477 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-1 RESULT=pass
12095 22:18:59.191848 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-0 RESULT=pass>
12096 22:18:59.192108 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-0 RESULT=pass
12098 22:18:59.232315 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-1 RESULT=pass>
12099 22:18:59.232609 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-1 RESULT=pass
12101 22:18:59.270417 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-0 RESULT=pass>
12102 22:18:59.270746 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-0 RESULT=pass
12104 22:18:59.308787 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-1 RESULT=pass
12106 22:18:59.311652 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-1 RESULT=pass>
12107 22:18:59.348538 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-0 RESULT=pass>
12108 22:18:59.348871 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-0 RESULT=pass
12110 22:18:59.381185 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-1 RESULT=pass>
12111 22:18:59.381500 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-1 RESULT=pass
12113 22:18:59.420690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-0 RESULT=pass>
12114 22:18:59.421060 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-0 RESULT=pass
12116 22:18:59.456567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-1 RESULT=pass>
12117 22:18:59.456917 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-1 RESULT=pass
12119 22:18:59.494833 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-0 RESULT=pass>
12120 22:18:59.495163 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-0 RESULT=pass
12122 22:18:59.535514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-1 RESULT=pass>
12123 22:18:59.535836 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-1 RESULT=pass
12125 22:18:59.575727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress RESULT=pass>
12126 22:18:59.576060 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress RESULT=pass
12128 22:18:59.617847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_not_available RESULT=skip>
12129 22:18:59.618180 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_not_available RESULT=skip
12131 22:18:59.652384 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace RESULT=skip>
12132 22:18:59.652713 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace RESULT=skip
12134 22:18:59.693138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-probe-vls_SVE_not_available RESULT=skip>
12135 22:18:59.693472 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-probe-vls_SVE_not_available RESULT=skip
12137 22:18:59.727548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-probe-vls RESULT=skip>
12138 22:18:59.727893 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-probe-vls RESULT=skip
12140 22:18:59.764488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip>
12141 22:18:59.764823 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip
12143 22:18:59.797544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip>
12144 22:18:59.797864 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip
12146 22:18:59.830832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip>
12147 22:18:59.831136 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip
12149 22:18:59.862086 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip>
12150 22:18:59.862382 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip
12152 22:18:59.895914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip>
12153 22:18:59.896228 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip
12155 22:18:59.927997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip>
12156 22:18:59.928301 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip
12158 22:18:59.961013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip>
12159 22:18:59.961324 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip
12161 22:18:59.993554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip>
12162 22:18:59.993851 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip
12164 22:19:00.028758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip>
12165 22:19:00.029093 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip
12167 22:19:00.061904 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip>
12168 22:19:00.062189 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip
12170 22:19:00.098819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip>
12171 22:19:00.099110 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip
12173 22:19:00.132212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip>
12174 22:19:00.132516 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip
12176 22:19:00.168518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip>
12177 22:19:00.168842 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip
12179 22:19:00.203392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip>
12180 22:19:00.203712 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip
12182 22:19:00.234176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip>
12183 22:19:00.234496 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip
12185 22:19:00.266006 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip>
12186 22:19:00.266320 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip
12188 22:19:00.300703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip>
12189 22:19:00.301041 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip
12191 22:19:00.334828 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip>
12192 22:19:00.335158 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip
12194 22:19:00.373061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip>
12195 22:19:00.373372 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip
12197 22:19:00.411882 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip>
12198 22:19:00.412194 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip
12200 22:19:00.445342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg RESULT=pass>
12201 22:19:00.445651 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg RESULT=pass
12203 22:19:00.487526 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-fork_skipped RESULT=pass>
12204 22:19:00.487842 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-fork_skipped RESULT=pass
12206 22:19:00.531451 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-fork RESULT=pass>
12207 22:19:00.531767 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-fork RESULT=pass
12209 22:19:00.572564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_SME_not_available RESULT=skip>
12210 22:19:00.572896 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_SME_not_available RESULT=skip
12212 22:19:00.608326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace RESULT=skip>
12213 22:19:00.608639 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace RESULT=skip
12215 22:19:00.643657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill RESULT=skip>
12216 22:19:00.643981 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill RESULT=skip
12218 22:19:00.680215 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory RESULT=skip>
12219 22:19:00.680535 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory RESULT=skip
12221 22:19:00.715523 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_gcr_el1_cswitch RESULT=skip
12223 22:19:00.718553 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_gcr_el1_cswitch RESULT=skip>
12224 22:19:00.754478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_ksm_options RESULT=skip>
12225 22:19:00.754787 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_ksm_options RESULT=skip
12227 22:19:00.790193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options RESULT=skip>
12228 22:19:00.790487 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options RESULT=skip
12230 22:19:00.842580 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_check_basic_read RESULT=pass>
12231 22:19:00.843242 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_check_basic_read RESULT=pass
12233 22:19:00.887986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_NONE RESULT=pass>
12234 22:19:00.888653 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_NONE RESULT=pass
12236 22:19:00.934529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_SYNC RESULT=skip>
12237 22:19:00.935208 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_SYNC RESULT=skip
12239 22:19:00.987357 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_ASYNC RESULT=skip>
12240 22:19:00.988005 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_ASYNC RESULT=skip
12242 22:19:01.038684 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_SYNC_ASYNC RESULT=skip
12244 22:19:01.041661 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_SYNC_ASYNC RESULT=skip>
12245 22:19:01.092167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl RESULT=pass>
12246 22:19:01.093010 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl RESULT=pass
12248 22:19:01.139226 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_tags_inclusion RESULT=skip>
12249 22:19:01.139932 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_tags_inclusion RESULT=skip
12251 22:19:01.188103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem RESULT=skip>
12252 22:19:01.188760 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem RESULT=skip
12254 22:19:01.240585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x0 RESULT=skip>
12255 22:19:01.241332 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x0 RESULT=skip
12257 22:19:01.292743 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x16 RESULT=skip>
12258 22:19:01.293038 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x16 RESULT=skip
12260 22:19:01.337148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_blr RESULT=skip>
12261 22:19:01.337444 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_blr RESULT=skip
12263 22:19:01.377008 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x0 RESULT=skip>
12264 22:19:01.377311 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x0 RESULT=skip
12266 22:19:01.419369 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x16 RESULT=skip>
12267 22:19:01.419646 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x16 RESULT=skip
12269 22:19:01.458594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_blr RESULT=skip>
12270 22:19:01.458914 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_blr RESULT=skip
12272 22:19:01.499940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x0 RESULT=skip>
12273 22:19:01.500241 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x0 RESULT=skip
12275 22:19:01.537455 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x16 RESULT=skip>
12276 22:19:01.537736 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x16 RESULT=skip
12278 22:19:01.581051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_blr RESULT=skip>
12279 22:19:01.581327 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_blr RESULT=skip
12281 22:19:01.618750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x0 RESULT=skip>
12282 22:19:01.619060 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x0 RESULT=skip
12284 22:19:01.665903 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x16 RESULT=skip>
12285 22:19:01.666211 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x16 RESULT=skip
12287 22:19:01.704680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_blr RESULT=skip>
12288 22:19:01.705015 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_blr RESULT=skip
12290 22:19:01.748685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x0 RESULT=skip>
12291 22:19:01.749009 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x0 RESULT=skip
12293 22:19:01.792185 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x16 RESULT=skip>
12294 22:19:01.792458 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x16 RESULT=skip
12296 22:19:01.833834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_blr RESULT=skip>
12297 22:19:01.834128 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_blr RESULT=skip
12299 22:19:01.880295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x0 RESULT=skip>
12300 22:19:01.880578 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x0 RESULT=skip
12302 22:19:01.921867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x16 RESULT=skip>
12303 22:19:01.922136 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x16 RESULT=skip
12305 22:19:01.963855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_blr RESULT=skip>
12306 22:19:01.964143 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_blr RESULT=skip
12308 22:19:01.999545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest RESULT=pass>
12309 22:19:01.999817 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest RESULT=pass
12311 22:19:02.044100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x0 RESULT=skip>
12312 22:19:02.044395 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x0 RESULT=skip
12314 22:19:02.085556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x16 RESULT=skip>
12315 22:19:02.085837 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x16 RESULT=skip
12317 22:19:02.121498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_blr RESULT=skip>
12318 22:19:02.121768 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_blr RESULT=skip
12320 22:19:02.156925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x0 RESULT=skip>
12321 22:19:02.157203 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x0 RESULT=skip
12323 22:19:02.197239 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x16 RESULT=skip>
12324 22:19:02.197521 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x16 RESULT=skip
12326 22:19:02.241701 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_blr RESULT=skip>
12327 22:19:02.242032 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_blr RESULT=skip
12329 22:19:02.285004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x0 RESULT=skip>
12330 22:19:02.285289 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x0 RESULT=skip
12332 22:19:02.328463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x16 RESULT=skip>
12333 22:19:02.328737 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x16 RESULT=skip
12335 22:19:02.369494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_blr RESULT=skip>
12336 22:19:02.369774 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_blr RESULT=skip
12338 22:19:02.409005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x0 RESULT=skip>
12339 22:19:02.409282 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x0 RESULT=skip
12341 22:19:02.444774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x16 RESULT=skip>
12342 22:19:02.445084 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x16 RESULT=skip
12344 22:19:02.489459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_blr RESULT=skip>
12345 22:19:02.489742 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_blr RESULT=skip
12347 22:19:02.534067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x0 RESULT=skip>
12348 22:19:02.534358 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x0 RESULT=skip
12350 22:19:02.569739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x16 RESULT=skip>
12351 22:19:02.570006 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x16 RESULT=skip
12353 22:19:02.608471 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_blr RESULT=skip>
12354 22:19:02.608823 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_blr RESULT=skip
12356 22:19:02.652424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x0 RESULT=skip>
12357 22:19:02.652699 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x0 RESULT=skip
12359 22:19:02.692753 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x16 RESULT=skip>
12360 22:19:02.693029 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x16 RESULT=skip
12362 22:19:02.726658 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_blr RESULT=skip>
12363 22:19:02.726932 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_blr RESULT=skip
12365 22:19:02.755789 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest RESULT=pass>
12366 22:19:02.756060 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest RESULT=pass
12368 22:19:02.796151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_RNG RESULT=pass>
12369 22:19:02.796422 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_RNG RESULT=pass
12371 22:19:02.828011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_RNG RESULT=skip>
12372 22:19:02.828277 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_RNG RESULT=skip
12374 22:19:02.865885 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SME RESULT=pass>
12375 22:19:02.866156 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SME RESULT=pass
12377 22:19:02.901455 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SME RESULT=pass>
12378 22:19:02.901720 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SME RESULT=pass
12380 22:19:02.939786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE RESULT=pass>
12381 22:19:02.940078 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE RESULT=pass
12383 22:19:02.969792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE RESULT=pass>
12384 22:19:02.970137 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE RESULT=pass
12386 22:19:03.012289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_2 RESULT=pass>
12387 22:19:03.012561 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_2 RESULT=pass
12389 22:19:03.044093 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE_2 RESULT=skip>
12390 22:19:03.044370 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE_2 RESULT=skip
12392 22:19:03.088053 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_AES RESULT=pass>
12393 22:19:03.088339 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_AES RESULT=pass
12395 22:19:03.129335 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE_AES RESULT=skip
12397 22:19:03.132259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE_AES RESULT=skip>
12398 22:19:03.168194 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_PMULL RESULT=pass>
12399 22:19:03.168480 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_PMULL RESULT=pass
12401 22:19:03.206336 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_PMULL RESULT=skip>
12402 22:19:03.206604 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_PMULL RESULT=skip
12404 22:19:03.244355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BITPERM RESULT=pass>
12405 22:19:03.244631 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BITPERM RESULT=pass
12407 22:19:03.278044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BITPERM RESULT=skip>
12408 22:19:03.278316 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BITPERM RESULT=skip
12410 22:19:03.314829 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SHA3 RESULT=pass>
12411 22:19:03.315519 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SHA3 RESULT=pass
12413 22:19:03.362866 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SHA3 RESULT=skip
12415 22:19:03.365543 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SHA3 RESULT=skip>
12416 22:19:03.404079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SM4 RESULT=pass>
12417 22:19:03.404373 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SM4 RESULT=pass
12419 22:19:03.436495 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SM4 RESULT=skip
12421 22:19:03.439326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SM4 RESULT=skip>
12422 22:19:03.478717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_I8MM RESULT=pass>
12423 22:19:03.479027 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_I8MM RESULT=pass
12425 22:19:03.516479 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_I8MM RESULT=skip
12427 22:19:03.519368 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_I8MM RESULT=skip>
12428 22:19:03.556601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F32MM RESULT=pass>
12429 22:19:03.556898 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F32MM RESULT=pass
12431 22:19:03.596158 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F32MM RESULT=skip>
12432 22:19:03.596442 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F32MM RESULT=skip
12434 22:19:03.637211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F64MM RESULT=pass>
12435 22:19:03.637485 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F64MM RESULT=pass
12437 22:19:03.671368 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F64MM RESULT=skip>
12438 22:19:03.671663 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F64MM RESULT=skip
12440 22:19:03.704530 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BF16 RESULT=pass>
12441 22:19:03.704819 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BF16 RESULT=pass
12443 22:19:03.736266 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BF16 RESULT=skip
12445 22:19:03.739210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BF16 RESULT=skip>
12446 22:19:03.773873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_EBF16 RESULT=pass>
12447 22:19:03.774151 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_EBF16 RESULT=pass
12449 22:19:03.816292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_EBF16 RESULT=skip>
12450 22:19:03.816578 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_EBF16 RESULT=skip
12452 22:19:03.848916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap RESULT=pass>
12453 22:19:03.849217 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap RESULT=pass
12455 22:19:03.888292 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_read_tpidr_one RESULT=pass
12457 22:19:03.891035 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_read_tpidr_one RESULT=pass>
12458 22:19:03.923661 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_write_tpidr_one RESULT=pass
12460 22:19:03.926654 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_write_tpidr_one RESULT=pass>
12461 22:19:03.967514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_verify_tpidr_one RESULT=pass>
12462 22:19:03.967816 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_verify_tpidr_one RESULT=pass
12464 22:19:04.005916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_count_tpidrs RESULT=pass>
12465 22:19:04.006192 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_count_tpidrs RESULT=pass
12467 22:19:04.049548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_tpidr2_write RESULT=pass>
12468 22:19:04.049822 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_tpidr2_write RESULT=pass
12470 22:19:04.088865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_tpidr2_read RESULT=pass>
12471 22:19:04.089221 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_tpidr2_read RESULT=pass
12473 22:19:04.134851 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_write_tpidr_only RESULT=pass>
12474 22:19:04.135174 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_write_tpidr_only RESULT=pass
12476 22:19:04.164071 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace RESULT=pass>
12477 22:19:04.164432 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace RESULT=pass
12479 22:19:04.197938 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_FPSIMD RESULT=pass>
12480 22:19:04.198364 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_FPSIMD RESULT=pass
12482 22:19:04.232602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_FPSIMD RESULT=pass>
12483 22:19:04.232928 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_FPSIMD RESULT=pass
12485 22:19:04.275859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi RESULT=pass>
12486 22:19:04.276668 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi RESULT=pass
12488 22:19:04.321210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass>
12489 22:19:04.321517 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass
12491 22:19:04.354090 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass>
12492 22:19:04.354418 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass
12494 22:19:04.391252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass>
12495 22:19:04.391555 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass
12497 22:19:04.424840 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass>
12498 22:19:04.425146 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass
12500 22:19:04.461712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass>
12501 22:19:04.462045 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass
12503 22:19:04.494053 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2 RESULT=pass>
12504 22:19:04.494186 + set +x
12505 22:19:04.494431 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2 RESULT=pass
12507 22:19:04.500997 <LAVA_SIGNAL_ENDRUN 1_kselftest-arm64 10597254_1.6.2.3.5>
12508 22:19:04.501286 Received signal: <ENDRUN> 1_kselftest-arm64 10597254_1.6.2.3.5
12509 22:19:04.501367 Ending use of test pattern.
12510 22:19:04.501432 Ending test lava.1_kselftest-arm64 (10597254_1.6.2.3.5), duration 28.19
12512 22:19:04.504573 <LAVA_TEST_RUNNER EXIT>
12513 22:19:04.504850 ok: lava_test_shell seems to have completed
12514 22:19:04.505805 arm64_btitest: pass
arm64_btitest_bti_c_func_call_using_blr: skip
arm64_btitest_bti_c_func_call_using_br_x0: skip
arm64_btitest_bti_c_func_call_using_br_x16: skip
arm64_btitest_bti_j_func_call_using_blr: skip
arm64_btitest_bti_j_func_call_using_br_x0: skip
arm64_btitest_bti_j_func_call_using_br_x16: skip
arm64_btitest_bti_jc_func_call_using_blr: skip
arm64_btitest_bti_jc_func_call_using_br_x0: skip
arm64_btitest_bti_jc_func_call_using_br_x16: skip
arm64_btitest_bti_none_func_call_using_blr: skip
arm64_btitest_bti_none_func_call_using_br_x0: skip
arm64_btitest_bti_none_func_call_using_br_x16: skip
arm64_btitest_nohint_func_call_using_blr: skip
arm64_btitest_nohint_func_call_using_br_x0: skip
arm64_btitest_nohint_func_call_using_br_x16: skip
arm64_btitest_paciasp_func_call_using_blr: skip
arm64_btitest_paciasp_func_call_using_br_x0: skip
arm64_btitest_paciasp_func_call_using_br_x16: skip
arm64_check_buffer_fill: skip
arm64_check_child_memory: skip
arm64_check_gcr_el1_cswitch: skip
arm64_check_ksm_options: skip
arm64_check_mmap_options: skip
arm64_check_prctl: pass
arm64_check_prctl_ASYNC: skip
arm64_check_prctl_NONE: pass
arm64_check_prctl_SYNC: skip
arm64_check_prctl_SYNC_ASYNC: skip
arm64_check_prctl_check_basic_read: pass
arm64_check_tags_inclusion: skip
arm64_check_user_mem: skip
arm64_fake_sigreturn_bad_magic: pass
arm64_fake_sigreturn_bad_size: pass
arm64_fake_sigreturn_bad_size_for_magic0: pass
arm64_fake_sigreturn_duplicated_fpsimd: pass
arm64_fake_sigreturn_misaligned_sp: pass
arm64_fake_sigreturn_missing_fpsimd: pass
arm64_fake_sigreturn_sme_change_vl: skip
arm64_fake_sigreturn_sve_change_vl: skip
arm64_fp-stress: pass
arm64_fp-stress_FPSIMD-0-0: pass
arm64_fp-stress_FPSIMD-0-1: pass
arm64_fp-stress_FPSIMD-1-0: pass
arm64_fp-stress_FPSIMD-1-1: pass
arm64_fp-stress_FPSIMD-2-0: pass
arm64_fp-stress_FPSIMD-2-1: pass
arm64_fp-stress_FPSIMD-3-0: pass
arm64_fp-stress_FPSIMD-3-1: pass
arm64_fp-stress_FPSIMD-4-0: pass
arm64_fp-stress_FPSIMD-4-1: pass
arm64_fp-stress_FPSIMD-5-0: pass
arm64_fp-stress_FPSIMD-5-1: pass
arm64_fp-stress_FPSIMD-6-0: pass
arm64_fp-stress_FPSIMD-6-1: pass
arm64_fp-stress_FPSIMD-7-0: pass
arm64_fp-stress_FPSIMD-7-1: pass
arm64_hwcap: pass
arm64_hwcap_cpuinfo_match_RNG: pass
arm64_hwcap_cpuinfo_match_SME: pass
arm64_hwcap_cpuinfo_match_SVE: pass
arm64_hwcap_cpuinfo_match_SVE2_BF16: pass
arm64_hwcap_cpuinfo_match_SVE2_BITPERM: pass
arm64_hwcap_cpuinfo_match_SVE2_EBF16: pass
arm64_hwcap_cpuinfo_match_SVE2_F32MM: pass
arm64_hwcap_cpuinfo_match_SVE2_F64MM: pass
arm64_hwcap_cpuinfo_match_SVE2_I8MM: pass
arm64_hwcap_cpuinfo_match_SVE2_PMULL: pass
arm64_hwcap_cpuinfo_match_SVE2_SHA3: pass
arm64_hwcap_cpuinfo_match_SVE2_SM4: pass
arm64_hwcap_cpuinfo_match_SVE_2: pass
arm64_hwcap_cpuinfo_match_SVE_AES: pass
arm64_hwcap_sigill_RNG: skip
arm64_hwcap_sigill_SME: pass
arm64_hwcap_sigill_SVE: pass
arm64_hwcap_sigill_SVE2_BF16: skip
arm64_hwcap_sigill_SVE2_BITPERM: skip
arm64_hwcap_sigill_SVE2_EBF16: skip
arm64_hwcap_sigill_SVE2_F32MM: skip
arm64_hwcap_sigill_SVE2_F64MM: skip
arm64_hwcap_sigill_SVE2_I8MM: skip
arm64_hwcap_sigill_SVE2_PMULL: skip
arm64_hwcap_sigill_SVE2_SHA3: skip
arm64_hwcap_sigill_SVE2_SM4: skip
arm64_hwcap_sigill_SVE_2: skip
arm64_hwcap_sigill_SVE_AES: skip
arm64_mangle_pstate_invalid_compat_toggle: pass
arm64_mangle_pstate_invalid_daif_bits: pass
arm64_mangle_pstate_invalid_mode_el1h: pass
arm64_mangle_pstate_invalid_mode_el1t: pass
arm64_mangle_pstate_invalid_mode_el2h: pass
arm64_mangle_pstate_invalid_mode_el2t: pass
arm64_mangle_pstate_invalid_mode_el3h: pass
arm64_mangle_pstate_invalid_mode_el3t: pass
arm64_nobtitest: pass
arm64_nobtitest_bti_c_func_call_using_blr: skip
arm64_nobtitest_bti_c_func_call_using_br_x0: skip
arm64_nobtitest_bti_c_func_call_using_br_x16: skip
arm64_nobtitest_bti_j_func_call_using_blr: skip
arm64_nobtitest_bti_j_func_call_using_br_x0: skip
arm64_nobtitest_bti_j_func_call_using_br_x16: skip
arm64_nobtitest_bti_jc_func_call_using_blr: skip
arm64_nobtitest_bti_jc_func_call_using_br_x0: skip
arm64_nobtitest_bti_jc_func_call_using_br_x16: skip
arm64_nobtitest_bti_none_func_call_using_blr: skip
arm64_nobtitest_bti_none_func_call_using_br_x0: skip
arm64_nobtitest_bti_none_func_call_using_br_x16: skip
arm64_nobtitest_nohint_func_call_using_blr: skip
arm64_nobtitest_nohint_func_call_using_br_x0: skip
arm64_nobtitest_nohint_func_call_using_br_x16: skip
arm64_nobtitest_paciasp_func_call_using_blr: skip
arm64_nobtitest_paciasp_func_call_using_br_x0: skip
arm64_nobtitest_paciasp_func_call_using_br_x16: skip
arm64_pac: pass
arm64_pac_Generic_PAUTH_not_enabled: skip
arm64_pac_PAUTH_not_enabled: skip
arm64_ptrace: pass
arm64_ptrace_count_tpidrs: pass
arm64_ptrace_read_tpidr_one: pass
arm64_ptrace_tpidr2_read: pass
arm64_ptrace_tpidr2_write: pass
arm64_ptrace_verify_tpidr_one: pass
arm64_ptrace_write_tpidr_one: pass
arm64_ptrace_write_tpidr_only: pass
arm64_run_tags_test_sh: pass
arm64_sme_trap_no_sm: skip
arm64_sme_trap_non_streaming: skip
arm64_sme_trap_za: pass
arm64_sme_vl: skip
arm64_ssve_regs: skip
arm64_sve-probe-vls: skip
arm64_sve-probe-vls_SVE_not_available: skip
arm64_sve-ptrace: skip
arm64_sve-ptrace_SVE_not_available: skip
arm64_sve_regs: skip
arm64_sve_vl: skip
arm64_syscall-abi: pass
arm64_syscall-abi_getpid_FPSIMD: pass
arm64_syscall-abi_sched_yield_FPSIMD: pass
arm64_tags_test: pass
arm64_tpidr2: pass
arm64_tpidr2_skipped_TPIDR2_not_supported: pass
arm64_vec-syscfg: pass
arm64_vec-syscfg_SME_not_supported: skip
arm64_vec-syscfg_SVE_not_supported: skip
arm64_za-fork: pass
arm64_za-fork_skipped: pass
arm64_za-ptrace: skip
arm64_za-ptrace_SME_not_available: skip
arm64_za_no_regs: skip
arm64_za_regs: skip
12515 22:19:04.505953 end: 3.1 lava-test-shell (duration 00:00:29) [common]
12516 22:19:04.506041 end: 3 lava-test-retry (duration 00:00:29) [common]
12517 22:19:04.506139 start: 4 finalize (timeout 00:07:27) [common]
12518 22:19:04.506226 start: 4.1 power-off (timeout 00:00:30) [common]
12519 22:19:04.506379 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=off'
12520 22:19:04.581701 >> Command sent successfully.
12521 22:19:04.583977 Returned 0 in 0 seconds
12522 22:19:04.684368 end: 4.1 power-off (duration 00:00:00) [common]
12524 22:19:04.684688 start: 4.2 read-feedback (timeout 00:07:27) [common]
12525 22:19:04.684986 Listened to connection for namespace 'common' for up to 1s
12526 22:19:05.685899 Finalising connection for namespace 'common'
12527 22:19:05.686067 Disconnecting from shell: Finalise
12528 22:19:05.686146 / #
12529 22:19:05.786475 end: 4.2 read-feedback (duration 00:00:01) [common]
12530 22:19:05.786618 end: 4 finalize (duration 00:00:01) [common]
12531 22:19:05.786735 Cleaning after the job
12532 22:19:05.786829 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10597254/tftp-deploy-1g1shtyl/ramdisk
12533 22:19:05.788910 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10597254/tftp-deploy-1g1shtyl/kernel
12534 22:19:05.797823 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10597254/tftp-deploy-1g1shtyl/dtb
12535 22:19:05.797995 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10597254/tftp-deploy-1g1shtyl/nfsrootfs
12536 22:19:05.863709 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10597254/tftp-deploy-1g1shtyl/modules
12537 22:19:05.869055 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/10597254
12538 22:19:06.401814 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/10597254
12539 22:19:06.401984 Job finished correctly