Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 37
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 30
1 22:20:06.219649 lava-dispatcher, installed at version: 2023.05.1
2 22:20:06.219867 start: 0 validate
3 22:20:06.220000 Start time: 2023-06-05 22:20:06.219993+00:00 (UTC)
4 22:20:06.220125 Using caching service: 'http://localhost/cache/?uri=%s'
5 22:20:06.220256 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230527.0%2Farm64%2Finitrd.cpio.gz exists
6 22:20:06.523088 Using caching service: 'http://localhost/cache/?uri=%s'
7 22:20:06.523271 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1314-g1ab0ac1d7e2e3%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 22:20:06.838524 Using caching service: 'http://localhost/cache/?uri=%s'
9 22:20:06.838707 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1314-g1ab0ac1d7e2e3%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 22:20:07.138526 Using caching service: 'http://localhost/cache/?uri=%s'
11 22:20:07.138701 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230527.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 22:20:07.453711 Using caching service: 'http://localhost/cache/?uri=%s'
13 22:20:07.453878 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1314-g1ab0ac1d7e2e3%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 22:20:07.754094 validate duration: 1.53
16 22:20:07.754356 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 22:20:07.754453 start: 1.1 download-retry (timeout 00:10:00) [common]
18 22:20:07.754545 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 22:20:07.754674 Not decompressing ramdisk as can be used compressed.
20 22:20:07.754759 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230527.0/arm64/initrd.cpio.gz
21 22:20:07.754849 saving as /var/lib/lava/dispatcher/tmp/10597300/tftp-deploy-ebp2nqop/ramdisk/initrd.cpio.gz
22 22:20:07.754933 total size: 4665601 (4MB)
23 22:20:07.755955 progress 0% (0MB)
24 22:20:07.757511 progress 5% (0MB)
25 22:20:07.758751 progress 10% (0MB)
26 22:20:07.759983 progress 15% (0MB)
27 22:20:07.761193 progress 20% (0MB)
28 22:20:07.762548 progress 25% (1MB)
29 22:20:07.763793 progress 30% (1MB)
30 22:20:07.764999 progress 35% (1MB)
31 22:20:07.766314 progress 40% (1MB)
32 22:20:07.767719 progress 45% (2MB)
33 22:20:07.768918 progress 50% (2MB)
34 22:20:07.770121 progress 55% (2MB)
35 22:20:07.771507 progress 60% (2MB)
36 22:20:07.772732 progress 65% (2MB)
37 22:20:07.773933 progress 70% (3MB)
38 22:20:07.775299 progress 75% (3MB)
39 22:20:07.776509 progress 80% (3MB)
40 22:20:07.777866 progress 85% (3MB)
41 22:20:07.779127 progress 90% (4MB)
42 22:20:07.780452 progress 95% (4MB)
43 22:20:07.781678 progress 100% (4MB)
44 22:20:07.781833 4MB downloaded in 0.03s (165.43MB/s)
45 22:20:07.781983 end: 1.1.1 http-download (duration 00:00:00) [common]
47 22:20:07.782223 end: 1.1 download-retry (duration 00:00:00) [common]
48 22:20:07.782310 start: 1.2 download-retry (timeout 00:10:00) [common]
49 22:20:07.782396 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 22:20:07.782527 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1314-g1ab0ac1d7e2e3/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 22:20:07.782600 saving as /var/lib/lava/dispatcher/tmp/10597300/tftp-deploy-ebp2nqop/kernel/Image
52 22:20:07.782662 total size: 45746688 (43MB)
53 22:20:07.782724 No compression specified
54 22:20:07.783841 progress 0% (0MB)
55 22:20:07.795827 progress 5% (2MB)
56 22:20:07.807916 progress 10% (4MB)
57 22:20:07.819809 progress 15% (6MB)
58 22:20:07.831813 progress 20% (8MB)
59 22:20:07.843809 progress 25% (10MB)
60 22:20:07.855729 progress 30% (13MB)
61 22:20:07.867780 progress 35% (15MB)
62 22:20:07.879857 progress 40% (17MB)
63 22:20:07.891749 progress 45% (19MB)
64 22:20:07.903838 progress 50% (21MB)
65 22:20:07.915717 progress 55% (24MB)
66 22:20:07.927860 progress 60% (26MB)
67 22:20:07.939759 progress 65% (28MB)
68 22:20:07.951803 progress 70% (30MB)
69 22:20:07.963851 progress 75% (32MB)
70 22:20:07.975715 progress 80% (34MB)
71 22:20:07.987582 progress 85% (37MB)
72 22:20:07.999498 progress 90% (39MB)
73 22:20:08.011344 progress 95% (41MB)
74 22:20:08.023229 progress 100% (43MB)
75 22:20:08.023389 43MB downloaded in 0.24s (181.24MB/s)
76 22:20:08.023544 end: 1.2.1 http-download (duration 00:00:00) [common]
78 22:20:08.023776 end: 1.2 download-retry (duration 00:00:00) [common]
79 22:20:08.023867 start: 1.3 download-retry (timeout 00:10:00) [common]
80 22:20:08.023957 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 22:20:08.024089 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1314-g1ab0ac1d7e2e3/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 22:20:08.024160 saving as /var/lib/lava/dispatcher/tmp/10597300/tftp-deploy-ebp2nqop/dtb/mt8192-asurada-spherion-r0.dtb
83 22:20:08.024226 total size: 46924 (0MB)
84 22:20:08.024288 No compression specified
85 22:20:08.025567 progress 69% (0MB)
86 22:20:08.025836 progress 100% (0MB)
87 22:20:08.025989 0MB downloaded in 0.00s (25.42MB/s)
88 22:20:08.026111 end: 1.3.1 http-download (duration 00:00:00) [common]
90 22:20:08.026333 end: 1.3 download-retry (duration 00:00:00) [common]
91 22:20:08.026419 start: 1.4 download-retry (timeout 00:10:00) [common]
92 22:20:08.026502 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 22:20:08.026613 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230527.0/arm64/full.rootfs.tar.xz
94 22:20:08.026682 saving as /var/lib/lava/dispatcher/tmp/10597300/tftp-deploy-ebp2nqop/nfsrootfs/full.rootfs.tar
95 22:20:08.026743 total size: 200770336 (191MB)
96 22:20:08.026803 Using unxz to decompress xz
97 22:20:08.030601 progress 0% (0MB)
98 22:20:08.578780 progress 5% (9MB)
99 22:20:09.115218 progress 10% (19MB)
100 22:20:09.743514 progress 15% (28MB)
101 22:20:10.130413 progress 20% (38MB)
102 22:20:10.455450 progress 25% (47MB)
103 22:20:11.049897 progress 30% (57MB)
104 22:20:11.610999 progress 35% (67MB)
105 22:20:12.211178 progress 40% (76MB)
106 22:20:12.788862 progress 45% (86MB)
107 22:20:13.376122 progress 50% (95MB)
108 22:20:14.004410 progress 55% (105MB)
109 22:20:14.662982 progress 60% (114MB)
110 22:20:14.782386 progress 65% (124MB)
111 22:20:14.929172 progress 70% (134MB)
112 22:20:15.026296 progress 75% (143MB)
113 22:20:15.103329 progress 80% (153MB)
114 22:20:15.174619 progress 85% (162MB)
115 22:20:15.275808 progress 90% (172MB)
116 22:20:15.553120 progress 95% (181MB)
117 22:20:16.126367 progress 100% (191MB)
118 22:20:16.130962 191MB downloaded in 8.10s (23.63MB/s)
119 22:20:16.131298 end: 1.4.1 http-download (duration 00:00:08) [common]
121 22:20:16.131718 end: 1.4 download-retry (duration 00:00:08) [common]
122 22:20:16.131843 start: 1.5 download-retry (timeout 00:09:52) [common]
123 22:20:16.131964 start: 1.5.1 http-download (timeout 00:09:52) [common]
124 22:20:16.132156 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1314-g1ab0ac1d7e2e3/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 22:20:16.132261 saving as /var/lib/lava/dispatcher/tmp/10597300/tftp-deploy-ebp2nqop/modules/modules.tar
126 22:20:16.132358 total size: 8543056 (8MB)
127 22:20:16.132455 Using unxz to decompress xz
128 22:20:16.136864 progress 0% (0MB)
129 22:20:16.159426 progress 5% (0MB)
130 22:20:16.184847 progress 10% (0MB)
131 22:20:16.211113 progress 15% (1MB)
132 22:20:16.235967 progress 20% (1MB)
133 22:20:16.259600 progress 25% (2MB)
134 22:20:16.286208 progress 30% (2MB)
135 22:20:16.311201 progress 35% (2MB)
136 22:20:16.335952 progress 40% (3MB)
137 22:20:16.360493 progress 45% (3MB)
138 22:20:16.385695 progress 50% (4MB)
139 22:20:16.409175 progress 55% (4MB)
140 22:20:16.433823 progress 60% (4MB)
141 22:20:16.459158 progress 65% (5MB)
142 22:20:16.484161 progress 70% (5MB)
143 22:20:16.508455 progress 75% (6MB)
144 22:20:16.532765 progress 80% (6MB)
145 22:20:16.558556 progress 85% (6MB)
146 22:20:16.588437 progress 90% (7MB)
147 22:20:16.613892 progress 95% (7MB)
148 22:20:16.638191 progress 100% (8MB)
149 22:20:16.644077 8MB downloaded in 0.51s (15.92MB/s)
150 22:20:16.644361 end: 1.5.1 http-download (duration 00:00:01) [common]
152 22:20:16.644643 end: 1.5 download-retry (duration 00:00:01) [common]
153 22:20:16.644771 start: 1.6 prepare-tftp-overlay (timeout 00:09:51) [common]
154 22:20:16.644903 start: 1.6.1 extract-nfsrootfs (timeout 00:09:51) [common]
155 22:20:19.895769 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/10597300/extract-nfsrootfs-cj0nalzp
156 22:20:19.895972 end: 1.6.1 extract-nfsrootfs (duration 00:00:03) [common]
157 22:20:19.896074 start: 1.6.2 lava-overlay (timeout 00:09:48) [common]
158 22:20:19.896243 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/10597300/lava-overlay-8me2moni
159 22:20:19.896375 makedir: /var/lib/lava/dispatcher/tmp/10597300/lava-overlay-8me2moni/lava-10597300/bin
160 22:20:19.896475 makedir: /var/lib/lava/dispatcher/tmp/10597300/lava-overlay-8me2moni/lava-10597300/tests
161 22:20:19.896571 makedir: /var/lib/lava/dispatcher/tmp/10597300/lava-overlay-8me2moni/lava-10597300/results
162 22:20:19.896671 Creating /var/lib/lava/dispatcher/tmp/10597300/lava-overlay-8me2moni/lava-10597300/bin/lava-add-keys
163 22:20:19.896806 Creating /var/lib/lava/dispatcher/tmp/10597300/lava-overlay-8me2moni/lava-10597300/bin/lava-add-sources
164 22:20:19.896929 Creating /var/lib/lava/dispatcher/tmp/10597300/lava-overlay-8me2moni/lava-10597300/bin/lava-background-process-start
165 22:20:19.897050 Creating /var/lib/lava/dispatcher/tmp/10597300/lava-overlay-8me2moni/lava-10597300/bin/lava-background-process-stop
166 22:20:19.897177 Creating /var/lib/lava/dispatcher/tmp/10597300/lava-overlay-8me2moni/lava-10597300/bin/lava-common-functions
167 22:20:19.897303 Creating /var/lib/lava/dispatcher/tmp/10597300/lava-overlay-8me2moni/lava-10597300/bin/lava-echo-ipv4
168 22:20:19.897422 Creating /var/lib/lava/dispatcher/tmp/10597300/lava-overlay-8me2moni/lava-10597300/bin/lava-install-packages
169 22:20:19.897539 Creating /var/lib/lava/dispatcher/tmp/10597300/lava-overlay-8me2moni/lava-10597300/bin/lava-installed-packages
170 22:20:19.897656 Creating /var/lib/lava/dispatcher/tmp/10597300/lava-overlay-8me2moni/lava-10597300/bin/lava-os-build
171 22:20:19.897773 Creating /var/lib/lava/dispatcher/tmp/10597300/lava-overlay-8me2moni/lava-10597300/bin/lava-probe-channel
172 22:20:19.897892 Creating /var/lib/lava/dispatcher/tmp/10597300/lava-overlay-8me2moni/lava-10597300/bin/lava-probe-ip
173 22:20:19.898011 Creating /var/lib/lava/dispatcher/tmp/10597300/lava-overlay-8me2moni/lava-10597300/bin/lava-target-ip
174 22:20:19.898130 Creating /var/lib/lava/dispatcher/tmp/10597300/lava-overlay-8me2moni/lava-10597300/bin/lava-target-mac
175 22:20:19.898247 Creating /var/lib/lava/dispatcher/tmp/10597300/lava-overlay-8me2moni/lava-10597300/bin/lava-target-storage
176 22:20:19.898369 Creating /var/lib/lava/dispatcher/tmp/10597300/lava-overlay-8me2moni/lava-10597300/bin/lava-test-case
177 22:20:19.898487 Creating /var/lib/lava/dispatcher/tmp/10597300/lava-overlay-8me2moni/lava-10597300/bin/lava-test-event
178 22:20:19.898604 Creating /var/lib/lava/dispatcher/tmp/10597300/lava-overlay-8me2moni/lava-10597300/bin/lava-test-feedback
179 22:20:19.898721 Creating /var/lib/lava/dispatcher/tmp/10597300/lava-overlay-8me2moni/lava-10597300/bin/lava-test-raise
180 22:20:19.898864 Creating /var/lib/lava/dispatcher/tmp/10597300/lava-overlay-8me2moni/lava-10597300/bin/lava-test-reference
181 22:20:19.898997 Creating /var/lib/lava/dispatcher/tmp/10597300/lava-overlay-8me2moni/lava-10597300/bin/lava-test-runner
182 22:20:19.899115 Creating /var/lib/lava/dispatcher/tmp/10597300/lava-overlay-8me2moni/lava-10597300/bin/lava-test-set
183 22:20:19.899233 Creating /var/lib/lava/dispatcher/tmp/10597300/lava-overlay-8me2moni/lava-10597300/bin/lava-test-shell
184 22:20:19.899353 Updating /var/lib/lava/dispatcher/tmp/10597300/lava-overlay-8me2moni/lava-10597300/bin/lava-add-keys (debian)
185 22:20:19.899497 Updating /var/lib/lava/dispatcher/tmp/10597300/lava-overlay-8me2moni/lava-10597300/bin/lava-add-sources (debian)
186 22:20:19.899641 Updating /var/lib/lava/dispatcher/tmp/10597300/lava-overlay-8me2moni/lava-10597300/bin/lava-install-packages (debian)
187 22:20:19.899785 Updating /var/lib/lava/dispatcher/tmp/10597300/lava-overlay-8me2moni/lava-10597300/bin/lava-installed-packages (debian)
188 22:20:19.899925 Updating /var/lib/lava/dispatcher/tmp/10597300/lava-overlay-8me2moni/lava-10597300/bin/lava-os-build (debian)
189 22:20:19.900049 Creating /var/lib/lava/dispatcher/tmp/10597300/lava-overlay-8me2moni/lava-10597300/environment
190 22:20:19.900156 LAVA metadata
191 22:20:19.900225 - LAVA_JOB_ID=10597300
192 22:20:19.900289 - LAVA_DISPATCHER_IP=192.168.201.1
193 22:20:19.900388 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:48) [common]
194 22:20:19.900455 skipped lava-vland-overlay
195 22:20:19.900529 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 22:20:19.900610 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:48) [common]
197 22:20:19.900671 skipped lava-multinode-overlay
198 22:20:19.900744 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 22:20:19.900823 start: 1.6.2.3 test-definition (timeout 00:09:48) [common]
200 22:20:19.900894 Loading test definitions
201 22:20:19.900984 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:48) [common]
202 22:20:19.901054 Using /lava-10597300 at stage 0
203 22:20:19.901321 uuid=10597300_1.6.2.3.1 testdef=None
204 22:20:19.901422 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 22:20:19.901509 start: 1.6.2.3.2 test-overlay (timeout 00:09:48) [common]
206 22:20:19.901942 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 22:20:19.902166 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:48) [common]
209 22:20:19.902732 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 22:20:19.903129 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:48) [common]
212 22:20:19.903704 runner path: /var/lib/lava/dispatcher/tmp/10597300/lava-overlay-8me2moni/lava-10597300/0/tests/0_timesync-off test_uuid 10597300_1.6.2.3.1
213 22:20:19.903889 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 22:20:19.904246 start: 1.6.2.3.5 git-repo-action (timeout 00:09:48) [common]
216 22:20:19.904347 Using /lava-10597300 at stage 0
217 22:20:19.904482 Fetching tests from https://github.com/kernelci/test-definitions.git
218 22:20:19.904586 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/10597300/lava-overlay-8me2moni/lava-10597300/0/tests/1_kselftest-rtc'
219 22:20:24.557027 Running '/usr/bin/git checkout kernelci.org
220 22:20:24.701966 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/10597300/lava-overlay-8me2moni/lava-10597300/0/tests/1_kselftest-rtc/automated/linux/kselftest/kselftest.yaml
221 22:20:24.702884 uuid=10597300_1.6.2.3.5 testdef=None
222 22:20:24.703047 end: 1.6.2.3.5 git-repo-action (duration 00:00:05) [common]
224 22:20:24.703294 start: 1.6.2.3.6 test-overlay (timeout 00:09:43) [common]
225 22:20:24.704017 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 22:20:24.704247 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:43) [common]
228 22:20:24.705311 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 22:20:24.705544 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:43) [common]
231 22:20:24.706443 runner path: /var/lib/lava/dispatcher/tmp/10597300/lava-overlay-8me2moni/lava-10597300/0/tests/1_kselftest-rtc test_uuid 10597300_1.6.2.3.5
232 22:20:24.706573 BOARD='mt8192-asurada-spherion-r0'
233 22:20:24.706666 BRANCH='cip-gitlab'
234 22:20:24.706755 SKIPFILE='/dev/null'
235 22:20:24.706861 SKIP_INSTALL='True'
236 22:20:24.706935 TESTPROG_URL='http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1314-g1ab0ac1d7e2e3/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 22:20:24.706993 TST_CASENAME=''
238 22:20:24.707049 TST_CMDFILES='rtc'
239 22:20:24.707190 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 22:20:24.707393 Creating lava-test-runner.conf files
242 22:20:24.707457 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10597300/lava-overlay-8me2moni/lava-10597300/0 for stage 0
243 22:20:24.707546 - 0_timesync-off
244 22:20:24.707616 - 1_kselftest-rtc
245 22:20:24.707708 end: 1.6.2.3 test-definition (duration 00:00:05) [common]
246 22:20:24.707798 start: 1.6.2.4 compress-overlay (timeout 00:09:43) [common]
247 22:20:32.256342 end: 1.6.2.4 compress-overlay (duration 00:00:08) [common]
248 22:20:32.256514 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:35) [common]
249 22:20:32.256608 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 22:20:32.256714 end: 1.6.2 lava-overlay (duration 00:00:12) [common]
251 22:20:32.256807 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:35) [common]
252 22:20:32.371591 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 22:20:32.371965 start: 1.6.4 extract-modules (timeout 00:09:35) [common]
254 22:20:32.372084 extracting modules file /var/lib/lava/dispatcher/tmp/10597300/tftp-deploy-ebp2nqop/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10597300/extract-nfsrootfs-cj0nalzp
255 22:20:32.576248 extracting modules file /var/lib/lava/dispatcher/tmp/10597300/tftp-deploy-ebp2nqop/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10597300/extract-overlay-ramdisk-qevkfasi/ramdisk
256 22:20:32.783533 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 22:20:32.783707 start: 1.6.5 apply-overlay-tftp (timeout 00:09:35) [common]
258 22:20:32.783807 [common] Applying overlay to NFS
259 22:20:32.783906 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10597300/compress-overlay-7n5xqx45/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/10597300/extract-nfsrootfs-cj0nalzp
260 22:20:33.678036 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 22:20:33.678218 start: 1.6.6 configure-preseed-file (timeout 00:09:34) [common]
262 22:20:33.678318 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 22:20:33.678412 start: 1.6.7 compress-ramdisk (timeout 00:09:34) [common]
264 22:20:33.678501 Building ramdisk /var/lib/lava/dispatcher/tmp/10597300/extract-overlay-ramdisk-qevkfasi/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/10597300/extract-overlay-ramdisk-qevkfasi/ramdisk
265 22:20:34.043173 >> 117807 blocks
266 22:20:35.926387 rename /var/lib/lava/dispatcher/tmp/10597300/extract-overlay-ramdisk-qevkfasi/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/10597300/tftp-deploy-ebp2nqop/ramdisk/ramdisk.cpio.gz
267 22:20:35.926863 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 22:20:35.927009 start: 1.6.8 prepare-kernel (timeout 00:09:32) [common]
269 22:20:35.927111 start: 1.6.8.1 prepare-fit (timeout 00:09:32) [common]
270 22:20:35.927215 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/10597300/tftp-deploy-ebp2nqop/kernel/Image'
271 22:20:47.633667 Returned 0 in 11 seconds
272 22:20:47.734307 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/10597300/tftp-deploy-ebp2nqop/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/10597300/tftp-deploy-ebp2nqop/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/10597300/tftp-deploy-ebp2nqop/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/10597300/tftp-deploy-ebp2nqop/kernel/image.itb
273 22:20:48.058381 output: FIT description: Kernel Image image with one or more FDT blobs
274 22:20:48.058743 output: Created: Mon Jun 5 23:20:47 2023
275 22:20:48.058822 output: Image 0 (kernel-1)
276 22:20:48.058935 output: Description:
277 22:20:48.059038 output: Created: Mon Jun 5 23:20:47 2023
278 22:20:48.059114 output: Type: Kernel Image
279 22:20:48.059179 output: Compression: lzma compressed
280 22:20:48.059245 output: Data Size: 10082307 Bytes = 9846.00 KiB = 9.62 MiB
281 22:20:48.059308 output: Architecture: AArch64
282 22:20:48.059369 output: OS: Linux
283 22:20:48.059446 output: Load Address: 0x00000000
284 22:20:48.059537 output: Entry Point: 0x00000000
285 22:20:48.059632 output: Hash algo: crc32
286 22:20:48.059729 output: Hash value: c242daf7
287 22:20:48.059817 output: Image 1 (fdt-1)
288 22:20:48.059911 output: Description: mt8192-asurada-spherion-r0
289 22:20:48.060001 output: Created: Mon Jun 5 23:20:47 2023
290 22:20:48.060079 output: Type: Flat Device Tree
291 22:20:48.060167 output: Compression: uncompressed
292 22:20:48.060254 output: Data Size: 46924 Bytes = 45.82 KiB = 0.04 MiB
293 22:20:48.060345 output: Architecture: AArch64
294 22:20:48.060433 output: Hash algo: crc32
295 22:20:48.060521 output: Hash value: 1df858fa
296 22:20:48.060608 output: Image 2 (ramdisk-1)
297 22:20:48.060693 output: Description: unavailable
298 22:20:48.060777 output: Created: Mon Jun 5 23:20:47 2023
299 22:20:48.060862 output: Type: RAMDisk Image
300 22:20:48.060946 output: Compression: Unknown Compression
301 22:20:48.061030 output: Data Size: 17641302 Bytes = 17227.83 KiB = 16.82 MiB
302 22:20:48.061115 output: Architecture: AArch64
303 22:20:48.061204 output: OS: Linux
304 22:20:48.061289 output: Load Address: unavailable
305 22:20:48.061373 output: Entry Point: unavailable
306 22:20:48.061459 output: Hash algo: crc32
307 22:20:48.061549 output: Hash value: 6071b7c2
308 22:20:48.061634 output: Default Configuration: 'conf-1'
309 22:20:48.061721 output: Configuration 0 (conf-1)
310 22:20:48.061802 output: Description: mt8192-asurada-spherion-r0
311 22:20:48.061884 output: Kernel: kernel-1
312 22:20:48.061969 output: Init Ramdisk: ramdisk-1
313 22:20:48.062053 output: FDT: fdt-1
314 22:20:48.062137 output: Loadables: kernel-1
315 22:20:48.062221 output:
316 22:20:48.062461 end: 1.6.8.1 prepare-fit (duration 00:00:12) [common]
317 22:20:48.062569 end: 1.6.8 prepare-kernel (duration 00:00:12) [common]
318 22:20:48.062681 end: 1.6 prepare-tftp-overlay (duration 00:00:31) [common]
319 22:20:48.062816 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:20) [common]
320 22:20:48.062916 No LXC device requested
321 22:20:48.063031 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 22:20:48.063147 start: 1.8 deploy-device-env (timeout 00:09:20) [common]
323 22:20:48.063259 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 22:20:48.063355 Checking files for TFTP limit of 4294967296 bytes.
325 22:20:48.063996 end: 1 tftp-deploy (duration 00:00:40) [common]
326 22:20:48.064129 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 22:20:48.064260 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 22:20:48.064434 substitutions:
329 22:20:48.064533 - {DTB}: 10597300/tftp-deploy-ebp2nqop/dtb/mt8192-asurada-spherion-r0.dtb
330 22:20:48.064629 - {INITRD}: 10597300/tftp-deploy-ebp2nqop/ramdisk/ramdisk.cpio.gz
331 22:20:48.064720 - {KERNEL}: 10597300/tftp-deploy-ebp2nqop/kernel/Image
332 22:20:48.064812 - {LAVA_MAC}: None
333 22:20:48.064901 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/10597300/extract-nfsrootfs-cj0nalzp
334 22:20:48.064984 - {NFS_SERVER_IP}: 192.168.201.1
335 22:20:48.065065 - {PRESEED_CONFIG}: None
336 22:20:48.065154 - {PRESEED_LOCAL}: None
337 22:20:48.065241 - {RAMDISK}: 10597300/tftp-deploy-ebp2nqop/ramdisk/ramdisk.cpio.gz
338 22:20:48.065335 - {ROOT_PART}: None
339 22:20:48.065423 - {ROOT}: None
340 22:20:48.065509 - {SERVER_IP}: 192.168.201.1
341 22:20:48.065595 - {TEE}: None
342 22:20:48.065681 Parsed boot commands:
343 22:20:48.065766 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 22:20:48.065986 Parsed boot commands: tftpboot 192.168.201.1 10597300/tftp-deploy-ebp2nqop/kernel/image.itb 10597300/tftp-deploy-ebp2nqop/kernel/cmdline
345 22:20:48.066110 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 22:20:48.066229 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 22:20:48.066354 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 22:20:48.066479 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 22:20:48.066586 Not connected, no need to disconnect.
350 22:20:48.066694 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 22:20:48.066813 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 22:20:48.066919 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost mt8192-asurada-spherion-r0-cbg-8'
353 22:20:48.070592 Setting prompt string to ['lava-test: # ']
354 22:20:48.070956 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 22:20:48.071071 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 22:20:48.071172 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 22:20:48.071265 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 22:20:48.071463 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=reboot'
359 22:20:53.215882 >> Command sent successfully.
360 22:20:53.219830 Returned 0 in 5 seconds
361 22:20:53.320231 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 22:20:53.320683 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 22:20:53.320831 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 22:20:53.320965 Setting prompt string to 'Starting depthcharge on Spherion...'
366 22:20:53.321073 Changing prompt to 'Starting depthcharge on Spherion...'
367 22:20:53.321177 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 22:20:53.321566 [Enter `^Ec?' for help]
369 22:20:53.491623
370 22:20:53.491775
371 22:20:53.491845 F0: 102B 0000
372 22:20:53.491909
373 22:20:53.491971 F3: 1001 0000 [0200]
374 22:20:53.492030
375 22:20:53.495430 F3: 1001 0000
376 22:20:53.495511
377 22:20:53.495574 F7: 102D 0000
378 22:20:53.495633
379 22:20:53.495690 F1: 0000 0000
380 22:20:53.499124
381 22:20:53.499210 V0: 0000 0000 [0001]
382 22:20:53.499278
383 22:20:53.499341 00: 0007 8000
384 22:20:53.499404
385 22:20:53.502775 01: 0000 0000
386 22:20:53.502943
387 22:20:53.503060 BP: 0C00 0209 [0000]
388 22:20:53.503169
389 22:20:53.505940 G0: 1182 0000
390 22:20:53.506026
391 22:20:53.506089 EC: 0000 0021 [4000]
392 22:20:53.506154
393 22:20:53.509496 S7: 0000 0000 [0000]
394 22:20:53.509581
395 22:20:53.509648 CC: 0000 0000 [0001]
396 22:20:53.509710
397 22:20:53.513255 T0: 0000 0040 [010F]
398 22:20:53.513340
399 22:20:53.513407 Jump to BL
400 22:20:53.513469
401 22:20:53.538733
402 22:20:53.538915
403 22:20:53.538986
404 22:20:53.545834 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
405 22:20:53.549227 ARM64: Exception handlers installed.
406 22:20:53.552878 ARM64: Testing exception
407 22:20:53.556384 ARM64: Done test exception
408 22:20:53.563156 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
409 22:20:53.573966 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
410 22:20:53.580271 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
411 22:20:53.590817 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
412 22:20:53.597107 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
413 22:20:53.603951 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
414 22:20:53.614994 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
415 22:20:53.621673 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
416 22:20:53.641392 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
417 22:20:53.644321 WDT: Last reset was cold boot
418 22:20:53.648003 SPI1(PAD0) initialized at 2873684 Hz
419 22:20:53.651013 SPI5(PAD0) initialized at 992727 Hz
420 22:20:53.654527 VBOOT: Loading verstage.
421 22:20:53.661179 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 22:20:53.664285 FMAP: Found "FLASH" version 1.1 at 0x20000.
423 22:20:53.667852 FMAP: base = 0x0 size = 0x800000 #areas = 25
424 22:20:53.670722 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
425 22:20:53.678545 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
426 22:20:53.684990 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
427 22:20:53.696490 read SPI 0x96554 0xa1eb: 4594 us, 9022 KB/s, 72.176 Mbps
428 22:20:53.696582
429 22:20:53.696671
430 22:20:53.706363 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
431 22:20:53.709560 ARM64: Exception handlers installed.
432 22:20:53.712622 ARM64: Testing exception
433 22:20:53.712708 ARM64: Done test exception
434 22:20:53.719960 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
435 22:20:53.723512 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
436 22:20:53.737009 Probing TPM: . done!
437 22:20:53.737108 TPM ready after 0 ms
438 22:20:53.744071 Connected to device vid:did:rid of 1ae0:0028:00
439 22:20:53.793190 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
440 22:20:53.793393 Initialized TPM device CR50 revision 0
441 22:20:53.805174 tlcl_send_startup: Startup return code is 0
442 22:20:53.805272 TPM: setup succeeded
443 22:20:53.816589 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
444 22:20:53.825014 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 22:20:53.836631 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
446 22:20:53.847791 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
447 22:20:53.850561 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
448 22:20:53.854136 in-header: 03 07 00 00 08 00 00 00
449 22:20:53.857735 in-data: aa e4 47 04 13 02 00 00
450 22:20:53.857843 Chrome EC: UHEPI supported
451 22:20:53.865145 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
452 22:20:53.869392 in-header: 03 9d 00 00 08 00 00 00
453 22:20:53.873069 in-data: 10 20 20 08 00 00 00 00
454 22:20:53.873158 Phase 1
455 22:20:53.876226 FMAP: area GBB found @ 3f5000 (12032 bytes)
456 22:20:53.884040 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
457 22:20:53.890993 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
458 22:20:53.891083 Recovery requested (1009000e)
459 22:20:53.900136 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 22:20:53.905339 tlcl_extend: response is 0
461 22:20:53.913379 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 22:20:53.919008 tlcl_extend: response is 0
463 22:20:53.925624 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 22:20:53.946434 read SPI 0x210d4 0x2173b: 15147 us, 9045 KB/s, 72.360 Mbps
465 22:20:53.953882 BS: bootblock times (exec / console): total (unknown) / 148 ms
466 22:20:53.953977
467 22:20:53.954046
468 22:20:53.961653 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 22:20:53.965061 ARM64: Exception handlers installed.
470 22:20:53.968985 ARM64: Testing exception
471 22:20:53.972183 ARM64: Done test exception
472 22:20:53.992000 pmic_efuse_setting: Set efuses in 11 msecs
473 22:20:53.995654 pmwrap_interface_init: Select PMIF_VLD_RDY
474 22:20:53.999333 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 22:20:54.007073 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 22:20:54.010167 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 22:20:54.014236 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 22:20:54.021136 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 22:20:54.024758 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 22:20:54.028418 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 22:20:54.035462 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 22:20:54.039145 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 22:20:54.042046 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 22:20:54.048816 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 22:20:54.052344 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 22:20:54.058848 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 22:20:54.062442 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 22:20:54.068543 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 22:20:54.075290 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 22:20:54.082126 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 22:20:54.085710 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 22:20:54.092383 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 22:20:54.096126 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 22:20:54.103595 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 22:20:54.107248 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 22:20:54.113922 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 22:20:54.121040 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 22:20:54.124893 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 22:20:54.131117 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 22:20:54.134683 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 22:20:54.141341 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 22:20:54.144282 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 22:20:54.151743 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 22:20:54.155127 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 22:20:54.158976 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 22:20:54.166083 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 22:20:54.169834 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 22:20:54.177190 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 22:20:54.180817 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 22:20:54.184377 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 22:20:54.190959 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 22:20:54.194011 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 22:20:54.197606 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 22:20:54.204410 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 22:20:54.207751 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 22:20:54.210645 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 22:20:54.217622 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 22:20:54.221281 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 22:20:54.224274 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 22:20:54.231118 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 22:20:54.234176 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 22:20:54.237738 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 22:20:54.241526 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 22:20:54.247502 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 22:20:54.254142 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
526 22:20:54.264656 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 22:20:54.267345 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 22:20:54.274144 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 22:20:54.284019 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 22:20:54.287600 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 22:20:54.294186 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 22:20:54.297085 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 22:20:54.304323 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x0
534 22:20:54.310592 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 22:20:54.314085 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
536 22:20:54.320539 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 22:20:54.328917 [RTC]rtc_get_frequency_meter,154: input=15, output=793
538 22:20:54.332086 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
539 22:20:54.338731 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
540 22:20:54.341873 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
541 22:20:54.345444 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
542 22:20:54.348578 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
543 22:20:54.352098 ADC[4]: Raw value=897040 ID=7
544 22:20:54.355398 ADC[3]: Raw value=212700 ID=1
545 22:20:54.358663 RAM Code: 0x71
546 22:20:54.362052 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
547 22:20:54.365338 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
548 22:20:54.375804 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
549 22:20:54.382499 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
550 22:20:54.385573 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
551 22:20:54.389255 in-header: 03 07 00 00 08 00 00 00
552 22:20:54.392192 in-data: aa e4 47 04 13 02 00 00
553 22:20:54.395959 Chrome EC: UHEPI supported
554 22:20:54.399645 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
555 22:20:54.403656 in-header: 03 d5 00 00 08 00 00 00
556 22:20:54.407344 in-data: 98 20 60 08 00 00 00 00
557 22:20:54.410847 MRC: failed to locate region type 0.
558 22:20:54.417822 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
559 22:20:54.421142 DRAM-K: Running full calibration
560 22:20:54.427222 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
561 22:20:54.427314 header.status = 0x0
562 22:20:54.430850 header.version = 0x6 (expected: 0x6)
563 22:20:54.434155 header.size = 0xd00 (expected: 0xd00)
564 22:20:54.437454 header.flags = 0x0
565 22:20:54.444643 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
566 22:20:54.460804 read SPI 0x72590 0x1c583: 12502 us, 9286 KB/s, 74.288 Mbps
567 22:20:54.467529 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
568 22:20:54.471109 dram_init: ddr_geometry: 2
569 22:20:54.474270 [EMI] MDL number = 2
570 22:20:54.474354 [EMI] Get MDL freq = 0
571 22:20:54.477837 dram_init: ddr_type: 0
572 22:20:54.477920 is_discrete_lpddr4: 1
573 22:20:54.480914 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
574 22:20:54.480994
575 22:20:54.484036
576 22:20:54.484112 [Bian_co] ETT version 0.0.0.1
577 22:20:54.490840 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
578 22:20:54.490939
579 22:20:54.493960 dramc_set_vcore_voltage set vcore to 650000
580 22:20:54.497477 Read voltage for 800, 4
581 22:20:54.497565 Vio18 = 0
582 22:20:54.497633 Vcore = 650000
583 22:20:54.500528 Vdram = 0
584 22:20:54.500614 Vddq = 0
585 22:20:54.500687 Vmddr = 0
586 22:20:54.504168 dram_init: config_dvfs: 1
587 22:20:54.507204 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
588 22:20:54.514029 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
589 22:20:54.517075 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=9
590 22:20:54.520743 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=9
591 22:20:54.523586 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
592 22:20:54.530212 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
593 22:20:54.530297 MEM_TYPE=3, freq_sel=18
594 22:20:54.533391 sv_algorithm_assistance_LP4_1600
595 22:20:54.537036 ============ PULL DRAM RESETB DOWN ============
596 22:20:54.543349 ========== PULL DRAM RESETB DOWN end =========
597 22:20:54.546841 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
598 22:20:54.550214 ===================================
599 22:20:54.553191 LPDDR4 DRAM CONFIGURATION
600 22:20:54.556478 ===================================
601 22:20:54.556574 EX_ROW_EN[0] = 0x0
602 22:20:54.560057 EX_ROW_EN[1] = 0x0
603 22:20:54.563095 LP4Y_EN = 0x0
604 22:20:54.563183 WORK_FSP = 0x0
605 22:20:54.566534 WL = 0x2
606 22:20:54.566621 RL = 0x2
607 22:20:54.569749 BL = 0x2
608 22:20:54.569834 RPST = 0x0
609 22:20:54.573386 RD_PRE = 0x0
610 22:20:54.573474 WR_PRE = 0x1
611 22:20:54.576551 WR_PST = 0x0
612 22:20:54.576692 DBI_WR = 0x0
613 22:20:54.579551 DBI_RD = 0x0
614 22:20:54.579636 OTF = 0x1
615 22:20:54.583127 ===================================
616 22:20:54.586242 ===================================
617 22:20:54.589352 ANA top config
618 22:20:54.593031 ===================================
619 22:20:54.596054 DLL_ASYNC_EN = 0
620 22:20:54.596139 ALL_SLAVE_EN = 1
621 22:20:54.599803 NEW_RANK_MODE = 1
622 22:20:54.602888 DLL_IDLE_MODE = 1
623 22:20:54.606073 LP45_APHY_COMB_EN = 1
624 22:20:54.606184 TX_ODT_DIS = 1
625 22:20:54.609199 NEW_8X_MODE = 1
626 22:20:54.612915 ===================================
627 22:20:54.616151 ===================================
628 22:20:54.619496 data_rate = 1600
629 22:20:54.622931 CKR = 1
630 22:20:54.625862 DQ_P2S_RATIO = 8
631 22:20:54.629344 ===================================
632 22:20:54.632487 CA_P2S_RATIO = 8
633 22:20:54.632588 DQ_CA_OPEN = 0
634 22:20:54.636145 DQ_SEMI_OPEN = 0
635 22:20:54.639165 CA_SEMI_OPEN = 0
636 22:20:54.642746 CA_FULL_RATE = 0
637 22:20:54.645844 DQ_CKDIV4_EN = 1
638 22:20:54.649256 CA_CKDIV4_EN = 1
639 22:20:54.649342 CA_PREDIV_EN = 0
640 22:20:54.652762 PH8_DLY = 0
641 22:20:54.655875 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
642 22:20:54.659375 DQ_AAMCK_DIV = 4
643 22:20:54.662796 CA_AAMCK_DIV = 4
644 22:20:54.665680 CA_ADMCK_DIV = 4
645 22:20:54.665768 DQ_TRACK_CA_EN = 0
646 22:20:54.669059 CA_PICK = 800
647 22:20:54.672633 CA_MCKIO = 800
648 22:20:54.675602 MCKIO_SEMI = 0
649 22:20:54.679344 PLL_FREQ = 3068
650 22:20:54.682363 DQ_UI_PI_RATIO = 32
651 22:20:54.685688 CA_UI_PI_RATIO = 0
652 22:20:54.689123 ===================================
653 22:20:54.692402 ===================================
654 22:20:54.692519 memory_type:LPDDR4
655 22:20:54.695377 GP_NUM : 10
656 22:20:54.699657 SRAM_EN : 1
657 22:20:54.699743 MD32_EN : 0
658 22:20:54.702954 ===================================
659 22:20:54.706367 [ANA_INIT] >>>>>>>>>>>>>>
660 22:20:54.706479 <<<<<< [CONFIGURE PHASE]: ANA_TX
661 22:20:54.710273 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
662 22:20:54.713788 ===================================
663 22:20:54.716926 data_rate = 1600,PCW = 0X7600
664 22:20:54.719939 ===================================
665 22:20:54.724172 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
666 22:20:54.731222 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
667 22:20:54.735311 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
668 22:20:54.739166 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
669 22:20:54.742233 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
670 22:20:54.745796 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
671 22:20:54.749564 [ANA_INIT] flow start
672 22:20:54.749653 [ANA_INIT] PLL >>>>>>>>
673 22:20:54.753598 [ANA_INIT] PLL <<<<<<<<
674 22:20:54.756838 [ANA_INIT] MIDPI >>>>>>>>
675 22:20:54.756955 [ANA_INIT] MIDPI <<<<<<<<
676 22:20:54.759859 [ANA_INIT] DLL >>>>>>>>
677 22:20:54.764452 [ANA_INIT] flow end
678 22:20:54.767956 ============ LP4 DIFF to SE enter ============
679 22:20:54.771444 ============ LP4 DIFF to SE exit ============
680 22:20:54.771537 [ANA_INIT] <<<<<<<<<<<<<
681 22:20:54.775201 [Flow] Enable top DCM control >>>>>
682 22:20:54.778709 [Flow] Enable top DCM control <<<<<
683 22:20:54.782703 Enable DLL master slave shuffle
684 22:20:54.786242 ==============================================================
685 22:20:54.789899 Gating Mode config
686 22:20:54.794048 ==============================================================
687 22:20:54.797893 Config description:
688 22:20:54.804815 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
689 22:20:54.812572 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
690 22:20:54.816396 SELPH_MODE 0: By rank 1: By Phase
691 22:20:54.823790 ==============================================================
692 22:20:54.827603 GAT_TRACK_EN = 1
693 22:20:54.831185 RX_GATING_MODE = 2
694 22:20:54.831287 RX_GATING_TRACK_MODE = 2
695 22:20:54.834705 SELPH_MODE = 1
696 22:20:54.837967 PICG_EARLY_EN = 1
697 22:20:54.840930 VALID_LAT_VALUE = 1
698 22:20:54.847646 ==============================================================
699 22:20:54.851174 Enter into Gating configuration >>>>
700 22:20:54.854695 Exit from Gating configuration <<<<
701 22:20:54.857936 Enter into DVFS_PRE_config >>>>>
702 22:20:54.867621 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
703 22:20:54.871121 Exit from DVFS_PRE_config <<<<<
704 22:20:54.874240 Enter into PICG configuration >>>>
705 22:20:54.877856 Exit from PICG configuration <<<<
706 22:20:54.880899 [RX_INPUT] configuration >>>>>
707 22:20:54.884251 [RX_INPUT] configuration <<<<<
708 22:20:54.887878 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
709 22:20:54.894336 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
710 22:20:54.901003 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
711 22:20:54.904097 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
712 22:20:54.910843 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
713 22:20:54.918009 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
714 22:20:54.920837 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
715 22:20:54.927520 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
716 22:20:54.930432 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
717 22:20:54.934235 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
718 22:20:54.937295 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
719 22:20:54.944238 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
720 22:20:54.947496 ===================================
721 22:20:54.947592 LPDDR4 DRAM CONFIGURATION
722 22:20:54.950482 ===================================
723 22:20:54.954061 EX_ROW_EN[0] = 0x0
724 22:20:54.957020 EX_ROW_EN[1] = 0x0
725 22:20:54.957110 LP4Y_EN = 0x0
726 22:20:54.960831 WORK_FSP = 0x0
727 22:20:54.960959 WL = 0x2
728 22:20:54.963940 RL = 0x2
729 22:20:54.964026 BL = 0x2
730 22:20:54.967541 RPST = 0x0
731 22:20:54.967628 RD_PRE = 0x0
732 22:20:54.970577 WR_PRE = 0x1
733 22:20:54.970690 WR_PST = 0x0
734 22:20:54.974197 DBI_WR = 0x0
735 22:20:54.974303 DBI_RD = 0x0
736 22:20:54.977314 OTF = 0x1
737 22:20:54.980883 ===================================
738 22:20:54.984476 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
739 22:20:54.987537 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
740 22:20:54.991861 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
741 22:20:54.995353 ===================================
742 22:20:54.998774 LPDDR4 DRAM CONFIGURATION
743 22:20:55.002280 ===================================
744 22:20:55.002376 EX_ROW_EN[0] = 0x10
745 22:20:55.006011 EX_ROW_EN[1] = 0x0
746 22:20:55.006106 LP4Y_EN = 0x0
747 22:20:55.009751 WORK_FSP = 0x0
748 22:20:55.009872 WL = 0x2
749 22:20:55.013321 RL = 0x2
750 22:20:55.013411 BL = 0x2
751 22:20:55.016863 RPST = 0x0
752 22:20:55.016952 RD_PRE = 0x0
753 22:20:55.020491 WR_PRE = 0x1
754 22:20:55.020581 WR_PST = 0x0
755 22:20:55.024137 DBI_WR = 0x0
756 22:20:55.024228 DBI_RD = 0x0
757 22:20:55.027889 OTF = 0x1
758 22:20:55.031672 ===================================
759 22:20:55.034586 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
760 22:20:55.039708 nWR fixed to 40
761 22:20:55.043516 [ModeRegInit_LP4] CH0 RK0
762 22:20:55.043605 [ModeRegInit_LP4] CH0 RK1
763 22:20:55.046631 [ModeRegInit_LP4] CH1 RK0
764 22:20:55.050157 [ModeRegInit_LP4] CH1 RK1
765 22:20:55.050246 match AC timing 13
766 22:20:55.053600 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
767 22:20:55.057566 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
768 22:20:55.064488 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
769 22:20:55.068180 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
770 22:20:55.071476 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
771 22:20:55.075446 [EMI DOE] emi_dcm 0
772 22:20:55.079007 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
773 22:20:55.079094 ==
774 22:20:55.083297 Dram Type= 6, Freq= 0, CH_0, rank 0
775 22:20:55.086692 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
776 22:20:55.086797 ==
777 22:20:55.093434 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
778 22:20:55.096997 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
779 22:20:55.107431 [CA 0] Center 38 (7~69) winsize 63
780 22:20:55.111047 [CA 1] Center 37 (7~68) winsize 62
781 22:20:55.114654 [CA 2] Center 35 (5~66) winsize 62
782 22:20:55.118315 [CA 3] Center 35 (5~66) winsize 62
783 22:20:55.121950 [CA 4] Center 34 (4~65) winsize 62
784 22:20:55.126205 [CA 5] Center 34 (4~64) winsize 61
785 22:20:55.126320
786 22:20:55.129404 [CmdBusTrainingLP45] Vref(ca) range 1: 32
787 22:20:55.129489
788 22:20:55.133647 [CATrainingPosCal] consider 1 rank data
789 22:20:55.133754 u2DelayCellTimex100 = 270/100 ps
790 22:20:55.136770 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
791 22:20:55.140518 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
792 22:20:55.144142 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
793 22:20:55.147909 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
794 22:20:55.151756 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
795 22:20:55.155460 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
796 22:20:55.155569
797 22:20:55.158995 CA PerBit enable=1, Macro0, CA PI delay=34
798 22:20:55.159103
799 22:20:55.162694 [CBTSetCACLKResult] CA Dly = 34
800 22:20:55.166405 CS Dly: 6 (0~37)
801 22:20:55.166484 ==
802 22:20:55.169653 Dram Type= 6, Freq= 0, CH_0, rank 1
803 22:20:55.173351 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
804 22:20:55.173443 ==
805 22:20:55.177304 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
806 22:20:55.184146 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
807 22:20:55.193500 [CA 0] Center 38 (7~69) winsize 63
808 22:20:55.197170 [CA 1] Center 38 (7~69) winsize 63
809 22:20:55.200817 [CA 2] Center 35 (5~66) winsize 62
810 22:20:55.204393 [CA 3] Center 35 (5~66) winsize 62
811 22:20:55.208526 [CA 4] Center 34 (4~65) winsize 62
812 22:20:55.211965 [CA 5] Center 34 (4~65) winsize 62
813 22:20:55.212056
814 22:20:55.215922 [CmdBusTrainingLP45] Vref(ca) range 1: 32
815 22:20:55.216012
816 22:20:55.219635 [CATrainingPosCal] consider 2 rank data
817 22:20:55.219724 u2DelayCellTimex100 = 270/100 ps
818 22:20:55.222747 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
819 22:20:55.226384 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
820 22:20:55.230787 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
821 22:20:55.234460 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
822 22:20:55.237676 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
823 22:20:55.241237 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
824 22:20:55.241326
825 22:20:55.245353 CA PerBit enable=1, Macro0, CA PI delay=34
826 22:20:55.245455
827 22:20:55.249139 [CBTSetCACLKResult] CA Dly = 34
828 22:20:55.253138 CS Dly: 6 (0~38)
829 22:20:55.253226
830 22:20:55.255954 ----->DramcWriteLeveling(PI) begin...
831 22:20:55.256046 ==
832 22:20:55.259628 Dram Type= 6, Freq= 0, CH_0, rank 0
833 22:20:55.263169 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
834 22:20:55.263259 ==
835 22:20:55.267243 Write leveling (Byte 0): 32 => 32
836 22:20:55.270929 Write leveling (Byte 1): 29 => 29
837 22:20:55.271022 DramcWriteLeveling(PI) end<-----
838 22:20:55.271140
839 22:20:55.271222 ==
840 22:20:55.274466 Dram Type= 6, Freq= 0, CH_0, rank 0
841 22:20:55.277876 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
842 22:20:55.282057 ==
843 22:20:55.282146 [Gating] SW mode calibration
844 22:20:55.288580 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
845 22:20:55.295299 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
846 22:20:55.298729 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
847 22:20:55.301848 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
848 22:20:55.308648 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
849 22:20:55.311927 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
850 22:20:55.315330 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
851 22:20:55.322113 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
852 22:20:55.325198 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
853 22:20:55.328857 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
854 22:20:55.335711 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
855 22:20:55.339424 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 22:20:55.343197 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 22:20:55.346864 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 22:20:55.350498 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 22:20:55.356754 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 22:20:55.360452 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 22:20:55.364384 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 22:20:55.370842 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 22:20:55.373867 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
864 22:20:55.377775 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
865 22:20:55.383982 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
866 22:20:55.387427 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 22:20:55.390568 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 22:20:55.397060 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 22:20:55.400406 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 22:20:55.403908 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
871 22:20:55.410462 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
872 22:20:55.413560 0 9 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
873 22:20:55.417212 0 9 12 | B1->B0 | 2626 2f2f | 0 1 | (0 0) (0 0)
874 22:20:55.423650 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
875 22:20:55.427030 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
876 22:20:55.430050 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
877 22:20:55.436796 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
878 22:20:55.440444 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
879 22:20:55.443527 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
880 22:20:55.450311 0 10 8 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 1)
881 22:20:55.453826 0 10 12 | B1->B0 | 2e2e 2424 | 0 0 | (0 1) (0 0)
882 22:20:55.456849 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
883 22:20:55.459979 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
884 22:20:55.466686 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
885 22:20:55.470345 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
886 22:20:55.473231 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
887 22:20:55.479912 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
888 22:20:55.483578 0 11 8 | B1->B0 | 2424 2e2e | 0 0 | (0 0) (0 0)
889 22:20:55.486504 0 11 12 | B1->B0 | 3838 4040 | 0 1 | (1 1) (0 0)
890 22:20:55.493161 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
891 22:20:55.496600 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
892 22:20:55.500295 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
893 22:20:55.506613 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
894 22:20:55.509559 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
895 22:20:55.513018 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
896 22:20:55.519809 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
897 22:20:55.523373 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
898 22:20:55.526338 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
899 22:20:55.533165 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
900 22:20:55.536561 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
901 22:20:55.539638 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
902 22:20:55.546501 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
903 22:20:55.549466 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
904 22:20:55.553071 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 22:20:55.559601 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 22:20:55.562988 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 22:20:55.566430 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 22:20:55.573092 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 22:20:55.576117 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 22:20:55.579627 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 22:20:55.586430 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 22:20:55.589477 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
913 22:20:55.592976 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
914 22:20:55.596104 Total UI for P1: 0, mck2ui 16
915 22:20:55.599089 best dqsien dly found for B0: ( 0, 14, 8)
916 22:20:55.605853 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
917 22:20:55.605942 Total UI for P1: 0, mck2ui 16
918 22:20:55.609506 best dqsien dly found for B1: ( 0, 14, 12)
919 22:20:55.615968 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
920 22:20:55.619137 best DQS1 dly(MCK, UI, PI) = (0, 14, 12)
921 22:20:55.619223
922 22:20:55.622160 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
923 22:20:55.625956 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 12)
924 22:20:55.628979 [Gating] SW calibration Done
925 22:20:55.629064 ==
926 22:20:55.632449 Dram Type= 6, Freq= 0, CH_0, rank 0
927 22:20:55.635360 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
928 22:20:55.635448 ==
929 22:20:55.638744 RX Vref Scan: 0
930 22:20:55.638884
931 22:20:55.638981 RX Vref 0 -> 0, step: 1
932 22:20:55.639115
933 22:20:55.642071 RX Delay -130 -> 252, step: 16
934 22:20:55.645607 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
935 22:20:55.652424 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
936 22:20:55.655540 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
937 22:20:55.658412 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
938 22:20:55.661991 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
939 22:20:55.665070 iDelay=222, Bit 5, Center 61 (-66 ~ 189) 256
940 22:20:55.671967 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
941 22:20:55.675052 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
942 22:20:55.678730 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
943 22:20:55.681853 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
944 22:20:55.685426 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
945 22:20:55.692101 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
946 22:20:55.695135 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
947 22:20:55.698457 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
948 22:20:55.701927 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
949 22:20:55.708422 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
950 22:20:55.708528 ==
951 22:20:55.711946 Dram Type= 6, Freq= 0, CH_0, rank 0
952 22:20:55.714960 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
953 22:20:55.715046 ==
954 22:20:55.715113 DQS Delay:
955 22:20:55.718834 DQS0 = 0, DQS1 = 0
956 22:20:55.718933 DQM Delay:
957 22:20:55.721643 DQM0 = 80, DQM1 = 70
958 22:20:55.721728 DQ Delay:
959 22:20:55.724907 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =77
960 22:20:55.728451 DQ4 =85, DQ5 =61, DQ6 =85, DQ7 =93
961 22:20:55.731487 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =61
962 22:20:55.735079 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
963 22:20:55.735164
964 22:20:55.735244
965 22:20:55.735320 ==
966 22:20:55.738629 Dram Type= 6, Freq= 0, CH_0, rank 0
967 22:20:55.742263 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
968 22:20:55.742351 ==
969 22:20:55.742418
970 22:20:55.742482
971 22:20:55.745570 TX Vref Scan disable
972 22:20:55.748956 == TX Byte 0 ==
973 22:20:55.752022 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
974 22:20:55.755788 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
975 22:20:55.758764 == TX Byte 1 ==
976 22:20:55.761826 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
977 22:20:55.765433 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
978 22:20:55.765548 ==
979 22:20:55.768572 Dram Type= 6, Freq= 0, CH_0, rank 0
980 22:20:55.771594 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
981 22:20:55.775331 ==
982 22:20:55.787002 TX Vref=22, minBit 0, minWin=27, winSum=438
983 22:20:55.790083 TX Vref=24, minBit 11, minWin=26, winSum=437
984 22:20:55.793151 TX Vref=26, minBit 5, minWin=27, winSum=442
985 22:20:55.796824 TX Vref=28, minBit 0, minWin=27, winSum=444
986 22:20:55.799857 TX Vref=30, minBit 4, minWin=27, winSum=443
987 22:20:55.806625 TX Vref=32, minBit 4, minWin=27, winSum=441
988 22:20:55.809724 [TxChooseVref] Worse bit 0, Min win 27, Win sum 444, Final Vref 28
989 22:20:55.809813
990 22:20:55.813520 Final TX Range 1 Vref 28
991 22:20:55.813608
992 22:20:55.813690 ==
993 22:20:55.816319 Dram Type= 6, Freq= 0, CH_0, rank 0
994 22:20:55.819901 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
995 22:20:55.819987 ==
996 22:20:55.823765
997 22:20:55.823850
998 22:20:55.823932 TX Vref Scan disable
999 22:20:55.826604 == TX Byte 0 ==
1000 22:20:55.830138 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1001 22:20:55.833530 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1002 22:20:55.837002 == TX Byte 1 ==
1003 22:20:55.839931 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1004 22:20:55.846547 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1005 22:20:55.846635
1006 22:20:55.846702 [DATLAT]
1007 22:20:55.846765 Freq=800, CH0 RK0
1008 22:20:55.846832
1009 22:20:55.849931 DATLAT Default: 0xa
1010 22:20:55.850035 0, 0xFFFF, sum = 0
1011 22:20:55.853393 1, 0xFFFF, sum = 0
1012 22:20:55.853479 2, 0xFFFF, sum = 0
1013 22:20:55.856607 3, 0xFFFF, sum = 0
1014 22:20:55.860048 4, 0xFFFF, sum = 0
1015 22:20:55.860164 5, 0xFFFF, sum = 0
1016 22:20:55.863141 6, 0xFFFF, sum = 0
1017 22:20:55.863227 7, 0xFFFF, sum = 0
1018 22:20:55.866457 8, 0xFFFF, sum = 0
1019 22:20:55.866542 9, 0x0, sum = 1
1020 22:20:55.869879 10, 0x0, sum = 2
1021 22:20:55.869964 11, 0x0, sum = 3
1022 22:20:55.870033 12, 0x0, sum = 4
1023 22:20:55.872957 best_step = 10
1024 22:20:55.873040
1025 22:20:55.873116 ==
1026 22:20:55.876628 Dram Type= 6, Freq= 0, CH_0, rank 0
1027 22:20:55.879893 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1028 22:20:55.879978 ==
1029 22:20:55.882861 RX Vref Scan: 1
1030 22:20:55.882958
1031 22:20:55.886493 Set Vref Range= 32 -> 127
1032 22:20:55.886576
1033 22:20:55.886641 RX Vref 32 -> 127, step: 1
1034 22:20:55.886703
1035 22:20:55.889724 RX Delay -111 -> 252, step: 8
1036 22:20:55.889810
1037 22:20:55.892996 Set Vref, RX VrefLevel [Byte0]: 32
1038 22:20:55.896030 [Byte1]: 32
1039 22:20:55.899696
1040 22:20:55.899836 Set Vref, RX VrefLevel [Byte0]: 33
1041 22:20:55.902608 [Byte1]: 33
1042 22:20:55.906970
1043 22:20:55.907054 Set Vref, RX VrefLevel [Byte0]: 34
1044 22:20:55.910557 [Byte1]: 34
1045 22:20:55.914823
1046 22:20:55.914927 Set Vref, RX VrefLevel [Byte0]: 35
1047 22:20:55.921033 [Byte1]: 35
1048 22:20:55.921145
1049 22:20:55.924490 Set Vref, RX VrefLevel [Byte0]: 36
1050 22:20:55.928006 [Byte1]: 36
1051 22:20:55.928090
1052 22:20:55.931029 Set Vref, RX VrefLevel [Byte0]: 37
1053 22:20:55.934776 [Byte1]: 37
1054 22:20:55.937734
1055 22:20:55.937819 Set Vref, RX VrefLevel [Byte0]: 38
1056 22:20:55.941196 [Byte1]: 38
1057 22:20:55.945253
1058 22:20:55.945336 Set Vref, RX VrefLevel [Byte0]: 39
1059 22:20:55.949092 [Byte1]: 39
1060 22:20:55.952859
1061 22:20:55.952943 Set Vref, RX VrefLevel [Byte0]: 40
1062 22:20:55.956561 [Byte1]: 40
1063 22:20:55.960475
1064 22:20:55.960558 Set Vref, RX VrefLevel [Byte0]: 41
1065 22:20:55.963881 [Byte1]: 41
1066 22:20:55.968707
1067 22:20:55.968791 Set Vref, RX VrefLevel [Byte0]: 42
1068 22:20:55.971737 [Byte1]: 42
1069 22:20:55.976025
1070 22:20:55.976108 Set Vref, RX VrefLevel [Byte0]: 43
1071 22:20:55.979122 [Byte1]: 43
1072 22:20:55.983429
1073 22:20:55.987085 Set Vref, RX VrefLevel [Byte0]: 44
1074 22:20:55.990183 [Byte1]: 44
1075 22:20:55.990266
1076 22:20:55.993826 Set Vref, RX VrefLevel [Byte0]: 45
1077 22:20:55.997261 [Byte1]: 45
1078 22:20:55.997368
1079 22:20:56.001144 Set Vref, RX VrefLevel [Byte0]: 46
1080 22:20:56.004094 [Byte1]: 46
1081 22:20:56.004200
1082 22:20:56.008186 Set Vref, RX VrefLevel [Byte0]: 47
1083 22:20:56.011227 [Byte1]: 47
1084 22:20:56.011333
1085 22:20:56.014329 Set Vref, RX VrefLevel [Byte0]: 48
1086 22:20:56.017429 [Byte1]: 48
1087 22:20:56.022394
1088 22:20:56.022504 Set Vref, RX VrefLevel [Byte0]: 49
1089 22:20:56.025554 [Byte1]: 49
1090 22:20:56.029705
1091 22:20:56.029812 Set Vref, RX VrefLevel [Byte0]: 50
1092 22:20:56.033178 [Byte1]: 50
1093 22:20:56.036912
1094 22:20:56.037031 Set Vref, RX VrefLevel [Byte0]: 51
1095 22:20:56.040815 [Byte1]: 51
1096 22:20:56.044932
1097 22:20:56.045053 Set Vref, RX VrefLevel [Byte0]: 52
1098 22:20:56.048059 [Byte1]: 52
1099 22:20:56.052750
1100 22:20:56.052856 Set Vref, RX VrefLevel [Byte0]: 53
1101 22:20:56.055790 [Byte1]: 53
1102 22:20:56.060416
1103 22:20:56.060525 Set Vref, RX VrefLevel [Byte0]: 54
1104 22:20:56.063351 [Byte1]: 54
1105 22:20:56.067923
1106 22:20:56.068036 Set Vref, RX VrefLevel [Byte0]: 55
1107 22:20:56.070750 [Byte1]: 55
1108 22:20:56.075239
1109 22:20:56.075350 Set Vref, RX VrefLevel [Byte0]: 56
1110 22:20:56.078954 [Byte1]: 56
1111 22:20:56.083301
1112 22:20:56.083433 Set Vref, RX VrefLevel [Byte0]: 57
1113 22:20:56.086298 [Byte1]: 57
1114 22:20:56.090619
1115 22:20:56.090738 Set Vref, RX VrefLevel [Byte0]: 58
1116 22:20:56.093694 [Byte1]: 58
1117 22:20:56.098591
1118 22:20:56.098711 Set Vref, RX VrefLevel [Byte0]: 59
1119 22:20:56.101571 [Byte1]: 59
1120 22:20:56.105960
1121 22:20:56.106063 Set Vref, RX VrefLevel [Byte0]: 60
1122 22:20:56.109067 [Byte1]: 60
1123 22:20:56.113762
1124 22:20:56.113846 Set Vref, RX VrefLevel [Byte0]: 61
1125 22:20:56.120375 [Byte1]: 61
1126 22:20:56.120459
1127 22:20:56.123392 Set Vref, RX VrefLevel [Byte0]: 62
1128 22:20:56.126520 [Byte1]: 62
1129 22:20:56.126603
1130 22:20:56.130408 Set Vref, RX VrefLevel [Byte0]: 63
1131 22:20:56.133513 [Byte1]: 63
1132 22:20:56.136910
1133 22:20:56.136995 Set Vref, RX VrefLevel [Byte0]: 64
1134 22:20:56.139782 [Byte1]: 64
1135 22:20:56.144068
1136 22:20:56.144151 Set Vref, RX VrefLevel [Byte0]: 65
1137 22:20:56.147574 [Byte1]: 65
1138 22:20:56.151826
1139 22:20:56.151908 Set Vref, RX VrefLevel [Byte0]: 66
1140 22:20:56.155415 [Byte1]: 66
1141 22:20:56.159683
1142 22:20:56.159765 Set Vref, RX VrefLevel [Byte0]: 67
1143 22:20:56.162776 [Byte1]: 67
1144 22:20:56.167467
1145 22:20:56.167551 Set Vref, RX VrefLevel [Byte0]: 68
1146 22:20:56.170296 [Byte1]: 68
1147 22:20:56.174925
1148 22:20:56.175027 Set Vref, RX VrefLevel [Byte0]: 69
1149 22:20:56.177827 [Byte1]: 69
1150 22:20:56.182433
1151 22:20:56.182534 Set Vref, RX VrefLevel [Byte0]: 70
1152 22:20:56.185493 [Byte1]: 70
1153 22:20:56.190406
1154 22:20:56.190508 Set Vref, RX VrefLevel [Byte0]: 71
1155 22:20:56.193502 [Byte1]: 71
1156 22:20:56.197948
1157 22:20:56.198045 Set Vref, RX VrefLevel [Byte0]: 72
1158 22:20:56.201270 [Byte1]: 72
1159 22:20:56.205274
1160 22:20:56.205382 Set Vref, RX VrefLevel [Byte0]: 73
1161 22:20:56.208908 [Byte1]: 73
1162 22:20:56.213194
1163 22:20:56.213292 Set Vref, RX VrefLevel [Byte0]: 74
1164 22:20:56.216443 [Byte1]: 74
1165 22:20:56.220864
1166 22:20:56.220936 Set Vref, RX VrefLevel [Byte0]: 75
1167 22:20:56.223779 [Byte1]: 75
1168 22:20:56.228076
1169 22:20:56.228174 Set Vref, RX VrefLevel [Byte0]: 76
1170 22:20:56.231847 [Byte1]: 76
1171 22:20:56.236108
1172 22:20:56.236231 Set Vref, RX VrefLevel [Byte0]: 77
1173 22:20:56.239115 [Byte1]: 77
1174 22:20:56.243524
1175 22:20:56.243611 Set Vref, RX VrefLevel [Byte0]: 78
1176 22:20:56.246946 [Byte1]: 78
1177 22:20:56.251199
1178 22:20:56.251282 Final RX Vref Byte 0 = 59 to rank0
1179 22:20:56.254833 Final RX Vref Byte 1 = 55 to rank0
1180 22:20:56.258048 Final RX Vref Byte 0 = 59 to rank1
1181 22:20:56.261021 Final RX Vref Byte 1 = 55 to rank1==
1182 22:20:56.264482 Dram Type= 6, Freq= 0, CH_0, rank 0
1183 22:20:56.271180 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1184 22:20:56.271348 ==
1185 22:20:56.271442 DQS Delay:
1186 22:20:56.271538 DQS0 = 0, DQS1 = 0
1187 22:20:56.274645 DQM Delay:
1188 22:20:56.274766 DQM0 = 82, DQM1 = 67
1189 22:20:56.277799 DQ Delay:
1190 22:20:56.281191 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1191 22:20:56.284553 DQ4 =80, DQ5 =68, DQ6 =92, DQ7 =92
1192 22:20:56.287939 DQ8 =60, DQ9 =56, DQ10 =68, DQ11 =60
1193 22:20:56.290794 DQ12 =72, DQ13 =72, DQ14 =76, DQ15 =76
1194 22:20:56.290935
1195 22:20:56.291033
1196 22:20:56.297412 [DQSOSCAuto] RK0, (LSB)MR18= 0x2322, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 401 ps
1197 22:20:56.300967 CH0 RK0: MR19=606, MR18=2322
1198 22:20:56.307658 CH0_RK0: MR19=0x606, MR18=0x2322, DQSOSC=401, MR23=63, INC=91, DEC=61
1199 22:20:56.307743
1200 22:20:56.310653 ----->DramcWriteLeveling(PI) begin...
1201 22:20:56.310738 ==
1202 22:20:56.314285 Dram Type= 6, Freq= 0, CH_0, rank 1
1203 22:20:56.317390 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1204 22:20:56.317474 ==
1205 22:20:56.320549 Write leveling (Byte 0): 33 => 33
1206 22:20:56.323980 Write leveling (Byte 1): 29 => 29
1207 22:20:56.327398 DramcWriteLeveling(PI) end<-----
1208 22:20:56.327482
1209 22:20:56.327548 ==
1210 22:20:56.330539 Dram Type= 6, Freq= 0, CH_0, rank 1
1211 22:20:56.333647 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1212 22:20:56.333733 ==
1213 22:20:56.337468 [Gating] SW mode calibration
1214 22:20:56.344138 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1215 22:20:56.350212 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1216 22:20:56.353639 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1217 22:20:56.360298 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1218 22:20:56.363873 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1219 22:20:56.366942 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1220 22:20:56.373524 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1221 22:20:56.377084 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1222 22:20:56.379989 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1223 22:20:56.387070 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1224 22:20:56.390043 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 22:20:56.393682 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 22:20:56.400223 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 22:20:56.403332 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 22:20:56.407028 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 22:20:56.410070 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 22:20:56.457508 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 22:20:56.457646 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 22:20:56.457912 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 22:20:56.457981 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1234 22:20:56.458505 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1235 22:20:56.458769 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1236 22:20:56.458871 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1237 22:20:56.459017 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1238 22:20:56.459113 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1239 22:20:56.459825 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1240 22:20:56.501385 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1241 22:20:56.501496 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1242 22:20:56.501869 0 9 8 | B1->B0 | 2323 2a2a | 0 1 | (0 0) (1 1)
1243 22:20:56.502163 0 9 12 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
1244 22:20:56.502291 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1245 22:20:56.502884 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1246 22:20:56.503012 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1247 22:20:56.503258 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1248 22:20:56.503336 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1249 22:20:56.503400 0 10 4 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 0)
1250 22:20:56.519516 0 10 8 | B1->B0 | 2f2f 2929 | 0 0 | (0 0) (0 0)
1251 22:20:56.519612 0 10 12 | B1->B0 | 2828 2323 | 0 0 | (1 0) (0 0)
1252 22:20:56.519929 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1253 22:20:56.520014 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1254 22:20:56.523275 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1255 22:20:56.526276 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1256 22:20:56.530009 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1257 22:20:56.532978 0 11 4 | B1->B0 | 2323 2323 | 0 1 | (0 0) (0 0)
1258 22:20:56.539775 0 11 8 | B1->B0 | 2f2f 3d3d | 0 0 | (1 1) (0 0)
1259 22:20:56.542764 0 11 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
1260 22:20:56.546545 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1261 22:20:56.552852 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1262 22:20:56.556367 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1263 22:20:56.563059 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1264 22:20:56.566288 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1265 22:20:56.569186 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1266 22:20:56.572923 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1267 22:20:56.580545 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1268 22:20:56.583905 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1269 22:20:56.587533 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1270 22:20:56.590439 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1271 22:20:56.597169 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1272 22:20:56.600652 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1273 22:20:56.604209 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1274 22:20:56.610967 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1275 22:20:56.614607 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1276 22:20:56.617748 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1277 22:20:56.624076 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1278 22:20:56.627707 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1279 22:20:56.630883 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1280 22:20:56.637525 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1281 22:20:56.640602 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1282 22:20:56.644283 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1283 22:20:56.647353 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1284 22:20:56.650577 Total UI for P1: 0, mck2ui 16
1285 22:20:56.654235 best dqsien dly found for B0: ( 0, 14, 8)
1286 22:20:56.657457 Total UI for P1: 0, mck2ui 16
1287 22:20:56.660599 best dqsien dly found for B1: ( 0, 14, 8)
1288 22:20:56.664199 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1289 22:20:56.670816 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1290 22:20:56.670923
1291 22:20:56.674151 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1292 22:20:56.677480 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1293 22:20:56.680575 [Gating] SW calibration Done
1294 22:20:56.680657 ==
1295 22:20:56.683686 Dram Type= 6, Freq= 0, CH_0, rank 1
1296 22:20:56.687339 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1297 22:20:56.687422 ==
1298 22:20:56.687488 RX Vref Scan: 0
1299 22:20:56.687549
1300 22:20:56.690477 RX Vref 0 -> 0, step: 1
1301 22:20:56.690559
1302 22:20:56.693937 RX Delay -130 -> 252, step: 16
1303 22:20:56.697067 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
1304 22:20:56.700814 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1305 22:20:56.707309 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1306 22:20:56.710154 iDelay=222, Bit 3, Center 69 (-50 ~ 189) 240
1307 22:20:56.713505 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1308 22:20:56.716716 iDelay=222, Bit 5, Center 61 (-66 ~ 189) 256
1309 22:20:56.720155 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1310 22:20:56.726636 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1311 22:20:56.729979 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1312 22:20:56.733379 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
1313 22:20:56.736410 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1314 22:20:56.743659 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1315 22:20:56.746708 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1316 22:20:56.749853 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1317 22:20:56.753662 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1318 22:20:56.756636 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1319 22:20:56.759855 ==
1320 22:20:56.759938 Dram Type= 6, Freq= 0, CH_0, rank 1
1321 22:20:56.766688 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1322 22:20:56.766775 ==
1323 22:20:56.766884 DQS Delay:
1324 22:20:56.769759 DQS0 = 0, DQS1 = 0
1325 22:20:56.769859 DQM Delay:
1326 22:20:56.773322 DQM0 = 77, DQM1 = 70
1327 22:20:56.773405 DQ Delay:
1328 22:20:56.776466 DQ0 =77, DQ1 =85, DQ2 =69, DQ3 =69
1329 22:20:56.779856 DQ4 =77, DQ5 =61, DQ6 =85, DQ7 =93
1330 22:20:56.783286 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =61
1331 22:20:56.786215 DQ12 =77, DQ13 =77, DQ14 =85, DQ15 =77
1332 22:20:56.786298
1333 22:20:56.786363
1334 22:20:56.786423 ==
1335 22:20:56.789892 Dram Type= 6, Freq= 0, CH_0, rank 1
1336 22:20:56.792907 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1337 22:20:56.792991 ==
1338 22:20:56.793095
1339 22:20:56.793156
1340 22:20:56.796379 TX Vref Scan disable
1341 22:20:56.799884 == TX Byte 0 ==
1342 22:20:56.803054 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1343 22:20:56.806726 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1344 22:20:56.809815 == TX Byte 1 ==
1345 22:20:56.813211 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1346 22:20:56.816219 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1347 22:20:56.816317 ==
1348 22:20:56.819747 Dram Type= 6, Freq= 0, CH_0, rank 1
1349 22:20:56.823097 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1350 22:20:56.825998 ==
1351 22:20:56.838236 TX Vref=22, minBit 1, minWin=27, winSum=435
1352 22:20:56.841102 TX Vref=24, minBit 1, minWin=27, winSum=440
1353 22:20:56.844776 TX Vref=26, minBit 0, minWin=27, winSum=440
1354 22:20:56.847577 TX Vref=28, minBit 1, minWin=27, winSum=441
1355 22:20:56.851343 TX Vref=30, minBit 1, minWin=27, winSum=442
1356 22:20:56.857501 TX Vref=32, minBit 1, minWin=27, winSum=443
1357 22:20:56.861195 [TxChooseVref] Worse bit 1, Min win 27, Win sum 443, Final Vref 32
1358 22:20:56.861279
1359 22:20:56.864232 Final TX Range 1 Vref 32
1360 22:20:56.864314
1361 22:20:56.864377 ==
1362 22:20:56.867431 Dram Type= 6, Freq= 0, CH_0, rank 1
1363 22:20:56.871025 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1364 22:20:56.871114 ==
1365 22:20:56.874168
1366 22:20:56.874249
1367 22:20:56.874313 TX Vref Scan disable
1368 22:20:56.877923 == TX Byte 0 ==
1369 22:20:56.880991 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1370 22:20:56.887814 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1371 22:20:56.887931 == TX Byte 1 ==
1372 22:20:56.891209 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1373 22:20:56.897806 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1374 22:20:56.897889
1375 22:20:56.897952 [DATLAT]
1376 22:20:56.898012 Freq=800, CH0 RK1
1377 22:20:56.898069
1378 22:20:56.900762 DATLAT Default: 0xa
1379 22:20:56.900843 0, 0xFFFF, sum = 0
1380 22:20:56.904364 1, 0xFFFF, sum = 0
1381 22:20:56.907624 2, 0xFFFF, sum = 0
1382 22:20:56.907707 3, 0xFFFF, sum = 0
1383 22:20:56.910739 4, 0xFFFF, sum = 0
1384 22:20:56.910870 5, 0xFFFF, sum = 0
1385 22:20:56.914486 6, 0xFFFF, sum = 0
1386 22:20:56.914568 7, 0xFFFF, sum = 0
1387 22:20:56.917368 8, 0xFFFF, sum = 0
1388 22:20:56.917450 9, 0x0, sum = 1
1389 22:20:56.920959 10, 0x0, sum = 2
1390 22:20:56.921042 11, 0x0, sum = 3
1391 22:20:56.921107 12, 0x0, sum = 4
1392 22:20:56.924466 best_step = 10
1393 22:20:56.924547
1394 22:20:56.924611 ==
1395 22:20:56.927291 Dram Type= 6, Freq= 0, CH_0, rank 1
1396 22:20:56.930630 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1397 22:20:56.930712 ==
1398 22:20:56.934094 RX Vref Scan: 0
1399 22:20:56.934175
1400 22:20:56.936940 RX Vref 0 -> 0, step: 1
1401 22:20:56.937021
1402 22:20:56.937085 RX Delay -111 -> 252, step: 8
1403 22:20:56.944412 iDelay=209, Bit 0, Center 76 (-39 ~ 192) 232
1404 22:20:56.947963 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
1405 22:20:56.950882 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
1406 22:20:56.954431 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
1407 22:20:56.957521 iDelay=209, Bit 4, Center 80 (-39 ~ 200) 240
1408 22:20:56.964411 iDelay=209, Bit 5, Center 64 (-55 ~ 184) 240
1409 22:20:56.967536 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
1410 22:20:56.971415 iDelay=209, Bit 7, Center 88 (-31 ~ 208) 240
1411 22:20:56.974464 iDelay=209, Bit 8, Center 60 (-55 ~ 176) 232
1412 22:20:56.977525 iDelay=209, Bit 9, Center 52 (-63 ~ 168) 232
1413 22:20:56.984548 iDelay=209, Bit 10, Center 72 (-47 ~ 192) 240
1414 22:20:56.987499 iDelay=209, Bit 11, Center 60 (-55 ~ 176) 232
1415 22:20:56.991118 iDelay=209, Bit 12, Center 80 (-39 ~ 200) 240
1416 22:20:56.994185 iDelay=209, Bit 13, Center 80 (-39 ~ 200) 240
1417 22:20:57.001249 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
1418 22:20:57.004590 iDelay=209, Bit 15, Center 76 (-39 ~ 192) 232
1419 22:20:57.004671 ==
1420 22:20:57.007278 Dram Type= 6, Freq= 0, CH_0, rank 1
1421 22:20:57.010726 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1422 22:20:57.010839 ==
1423 22:20:57.013987 DQS Delay:
1424 22:20:57.014068 DQS0 = 0, DQS1 = 0
1425 22:20:57.014132 DQM Delay:
1426 22:20:57.017539 DQM0 = 79, DQM1 = 70
1427 22:20:57.017620 DQ Delay:
1428 22:20:57.020696 DQ0 =76, DQ1 =84, DQ2 =76, DQ3 =72
1429 22:20:57.023791 DQ4 =80, DQ5 =64, DQ6 =92, DQ7 =88
1430 22:20:57.027258 DQ8 =60, DQ9 =52, DQ10 =72, DQ11 =60
1431 22:20:57.030650 DQ12 =80, DQ13 =80, DQ14 =80, DQ15 =76
1432 22:20:57.030756
1433 22:20:57.030874
1434 22:20:57.040353 [DQSOSCAuto] RK1, (LSB)MR18= 0x4b26, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 391 ps
1435 22:20:57.040497 CH0 RK1: MR19=606, MR18=4B26
1436 22:20:57.047461 CH0_RK1: MR19=0x606, MR18=0x4B26, DQSOSC=391, MR23=63, INC=96, DEC=64
1437 22:20:57.050630 [RxdqsGatingPostProcess] freq 800
1438 22:20:57.056919 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1439 22:20:57.060181 Pre-setting of DQS Precalculation
1440 22:20:57.063863 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1441 22:20:57.063948 ==
1442 22:20:57.067021 Dram Type= 6, Freq= 0, CH_1, rank 0
1443 22:20:57.073764 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1444 22:20:57.073850 ==
1445 22:20:57.076936 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1446 22:20:57.083810 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1447 22:20:57.092940 [CA 0] Center 36 (6~67) winsize 62
1448 22:20:57.096009 [CA 1] Center 36 (6~67) winsize 62
1449 22:20:57.099517 [CA 2] Center 34 (5~64) winsize 60
1450 22:20:57.102563 [CA 3] Center 34 (4~64) winsize 61
1451 22:20:57.106083 [CA 4] Center 34 (4~64) winsize 61
1452 22:20:57.109149 [CA 5] Center 34 (4~64) winsize 61
1453 22:20:57.109232
1454 22:20:57.112862 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1455 22:20:57.112944
1456 22:20:57.115884 [CATrainingPosCal] consider 1 rank data
1457 22:20:57.119417 u2DelayCellTimex100 = 270/100 ps
1458 22:20:57.122495 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1459 22:20:57.129251 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1460 22:20:57.132592 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
1461 22:20:57.136183 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
1462 22:20:57.139080 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
1463 22:20:57.142674 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1464 22:20:57.142784
1465 22:20:57.146142 CA PerBit enable=1, Macro0, CA PI delay=34
1466 22:20:57.146229
1467 22:20:57.149056 [CBTSetCACLKResult] CA Dly = 34
1468 22:20:57.152448 CS Dly: 5 (0~36)
1469 22:20:57.152562 ==
1470 22:20:57.155762 Dram Type= 6, Freq= 0, CH_1, rank 1
1471 22:20:57.159305 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1472 22:20:57.159390 ==
1473 22:20:57.165683 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1474 22:20:57.169027 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1475 22:20:57.178996 [CA 0] Center 37 (7~67) winsize 61
1476 22:20:57.182164 [CA 1] Center 36 (6~67) winsize 62
1477 22:20:57.185869 [CA 2] Center 35 (5~65) winsize 61
1478 22:20:57.188988 [CA 3] Center 33 (3~64) winsize 62
1479 22:20:57.192099 [CA 4] Center 34 (4~65) winsize 62
1480 22:20:57.195714 [CA 5] Center 33 (3~64) winsize 62
1481 22:20:57.195832
1482 22:20:57.198658 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1483 22:20:57.198772
1484 22:20:57.202390 [CATrainingPosCal] consider 2 rank data
1485 22:20:57.205422 u2DelayCellTimex100 = 270/100 ps
1486 22:20:57.209000 CA0 delay=37 (7~67),Diff = 3 PI (21 cell)
1487 22:20:57.215725 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1488 22:20:57.218778 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
1489 22:20:57.221786 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
1490 22:20:57.225639 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
1491 22:20:57.229005 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1492 22:20:57.229104
1493 22:20:57.232573 CA PerBit enable=1, Macro0, CA PI delay=34
1494 22:20:57.232646
1495 22:20:57.236147 [CBTSetCACLKResult] CA Dly = 34
1496 22:20:57.236249 CS Dly: 6 (0~38)
1497 22:20:57.236338
1498 22:20:57.239212 ----->DramcWriteLeveling(PI) begin...
1499 22:20:57.239298 ==
1500 22:20:57.242845 Dram Type= 6, Freq= 0, CH_1, rank 0
1501 22:20:57.246641 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1502 22:20:57.249940 ==
1503 22:20:57.250101 Write leveling (Byte 0): 26 => 26
1504 22:20:57.253481 Write leveling (Byte 1): 32 => 32
1505 22:20:57.256403 DramcWriteLeveling(PI) end<-----
1506 22:20:57.256490
1507 22:20:57.256583 ==
1508 22:20:57.259967 Dram Type= 6, Freq= 0, CH_1, rank 0
1509 22:20:57.264148 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1510 22:20:57.267378 ==
1511 22:20:57.267459 [Gating] SW mode calibration
1512 22:20:57.274285 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1513 22:20:57.280868 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1514 22:20:57.284593 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1515 22:20:57.287697 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1516 22:20:57.294551 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1517 22:20:57.297481 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1518 22:20:57.301059 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1519 22:20:57.307438 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1520 22:20:57.311178 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1521 22:20:57.314142 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1522 22:20:57.320681 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 22:20:57.323726 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 22:20:57.327286 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 22:20:57.334030 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 22:20:57.337468 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 22:20:57.340399 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 22:20:57.347211 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 22:20:57.350800 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 22:20:57.353699 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 22:20:57.360564 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1532 22:20:57.363850 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1533 22:20:57.367418 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1534 22:20:57.373589 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1535 22:20:57.377077 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1536 22:20:57.380382 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1537 22:20:57.387260 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1538 22:20:57.390363 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1539 22:20:57.394051 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
1540 22:20:57.400397 0 9 8 | B1->B0 | 2727 2726 | 1 1 | (0 0) (0 0)
1541 22:20:57.404087 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1542 22:20:57.406947 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1543 22:20:57.413787 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1544 22:20:57.416899 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1545 22:20:57.420485 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1546 22:20:57.427057 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1547 22:20:57.430021 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1548 22:20:57.434043 0 10 8 | B1->B0 | 2d2d 2e2e | 0 0 | (0 0) (0 0)
1549 22:20:57.440518 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1550 22:20:57.443545 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1551 22:20:57.447033 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1552 22:20:57.449905 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1553 22:20:57.456533 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1554 22:20:57.459942 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1555 22:20:57.463547 0 11 4 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
1556 22:20:57.470124 0 11 8 | B1->B0 | 3534 3535 | 1 1 | (0 0) (0 0)
1557 22:20:57.473240 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1558 22:20:57.476772 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1559 22:20:57.483147 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1560 22:20:57.486612 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1561 22:20:57.490126 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1562 22:20:57.496328 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1563 22:20:57.500047 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1564 22:20:57.503117 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1565 22:20:57.509806 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1566 22:20:57.512798 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1567 22:20:57.516419 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1568 22:20:57.522706 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1569 22:20:57.526337 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1570 22:20:57.529296 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1571 22:20:57.536472 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1572 22:20:57.539444 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1573 22:20:57.543156 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1574 22:20:57.549314 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1575 22:20:57.553122 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1576 22:20:57.556116 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1577 22:20:57.562961 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1578 22:20:57.565868 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1579 22:20:57.569601 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1580 22:20:57.576140 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1581 22:20:57.576237 Total UI for P1: 0, mck2ui 16
1582 22:20:57.582653 best dqsien dly found for B0: ( 0, 14, 6)
1583 22:20:57.582741 Total UI for P1: 0, mck2ui 16
1584 22:20:57.589104 best dqsien dly found for B1: ( 0, 14, 6)
1585 22:20:57.592576 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1586 22:20:57.595899 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1587 22:20:57.596010
1588 22:20:57.598940 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1589 22:20:57.602627 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1590 22:20:57.605847 [Gating] SW calibration Done
1591 22:20:57.605951 ==
1592 22:20:57.609416 Dram Type= 6, Freq= 0, CH_1, rank 0
1593 22:20:57.612522 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1594 22:20:57.612644 ==
1595 22:20:57.616211 RX Vref Scan: 0
1596 22:20:57.616310
1597 22:20:57.616406 RX Vref 0 -> 0, step: 1
1598 22:20:57.616497
1599 22:20:57.619306 RX Delay -130 -> 252, step: 16
1600 22:20:57.622413 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
1601 22:20:57.629242 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1602 22:20:57.632305 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1603 22:20:57.635799 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1604 22:20:57.639195 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1605 22:20:57.642548 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1606 22:20:57.648804 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1607 22:20:57.651876 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1608 22:20:57.655504 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1609 22:20:57.659060 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1610 22:20:57.661950 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1611 22:20:57.668599 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1612 22:20:57.672303 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1613 22:20:57.675386 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1614 22:20:57.678427 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1615 22:20:57.685548 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1616 22:20:57.685630 ==
1617 22:20:57.688425 Dram Type= 6, Freq= 0, CH_1, rank 0
1618 22:20:57.692123 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1619 22:20:57.692209 ==
1620 22:20:57.692276 DQS Delay:
1621 22:20:57.695571 DQS0 = 0, DQS1 = 0
1622 22:20:57.695655 DQM Delay:
1623 22:20:57.698298 DQM0 = 80, DQM1 = 71
1624 22:20:57.698387 DQ Delay:
1625 22:20:57.701774 DQ0 =77, DQ1 =77, DQ2 =69, DQ3 =77
1626 22:20:57.705423 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1627 22:20:57.708555 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =69
1628 22:20:57.712171 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1629 22:20:57.712255
1630 22:20:57.712340
1631 22:20:57.712421 ==
1632 22:20:57.715421 Dram Type= 6, Freq= 0, CH_1, rank 0
1633 22:20:57.718371 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1634 22:20:57.718459 ==
1635 22:20:57.718565
1636 22:20:57.718667
1637 22:20:57.721900 TX Vref Scan disable
1638 22:20:57.724979 == TX Byte 0 ==
1639 22:20:57.728668 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1640 22:20:57.731848 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1641 22:20:57.734901 == TX Byte 1 ==
1642 22:20:57.738612 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1643 22:20:57.741542 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1644 22:20:57.741650 ==
1645 22:20:57.744874 Dram Type= 6, Freq= 0, CH_1, rank 0
1646 22:20:57.751876 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1647 22:20:57.751959 ==
1648 22:20:57.763506 TX Vref=22, minBit 1, minWin=27, winSum=441
1649 22:20:57.766903 TX Vref=24, minBit 0, minWin=27, winSum=444
1650 22:20:57.770425 TX Vref=26, minBit 1, minWin=27, winSum=444
1651 22:20:57.773867 TX Vref=28, minBit 11, minWin=27, winSum=451
1652 22:20:57.776934 TX Vref=30, minBit 5, minWin=27, winSum=448
1653 22:20:57.783798 TX Vref=32, minBit 5, minWin=27, winSum=449
1654 22:20:57.786799 [TxChooseVref] Worse bit 11, Min win 27, Win sum 451, Final Vref 28
1655 22:20:57.786935
1656 22:20:57.790421 Final TX Range 1 Vref 28
1657 22:20:57.790558
1658 22:20:57.790679 ==
1659 22:20:57.793415 Dram Type= 6, Freq= 0, CH_1, rank 0
1660 22:20:57.796892 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1661 22:20:57.800412 ==
1662 22:20:57.800487
1663 22:20:57.800549
1664 22:20:57.800623 TX Vref Scan disable
1665 22:20:57.803960 == TX Byte 0 ==
1666 22:20:57.807339 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1667 22:20:57.811321 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1668 22:20:57.814300 == TX Byte 1 ==
1669 22:20:57.817920 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1670 22:20:57.821001 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1671 22:20:57.821104
1672 22:20:57.824646 [DATLAT]
1673 22:20:57.824730 Freq=800, CH1 RK0
1674 22:20:57.824823
1675 22:20:57.827776 DATLAT Default: 0xa
1676 22:20:57.827878 0, 0xFFFF, sum = 0
1677 22:20:57.830755 1, 0xFFFF, sum = 0
1678 22:20:57.830894 2, 0xFFFF, sum = 0
1679 22:20:57.834395 3, 0xFFFF, sum = 0
1680 22:20:57.834476 4, 0xFFFF, sum = 0
1681 22:20:57.837522 5, 0xFFFF, sum = 0
1682 22:20:57.837609 6, 0xFFFF, sum = 0
1683 22:20:57.840993 7, 0xFFFF, sum = 0
1684 22:20:57.841103 8, 0xFFFF, sum = 0
1685 22:20:57.844406 9, 0x0, sum = 1
1686 22:20:57.844481 10, 0x0, sum = 2
1687 22:20:57.847408 11, 0x0, sum = 3
1688 22:20:57.847493 12, 0x0, sum = 4
1689 22:20:57.850792 best_step = 10
1690 22:20:57.850900
1691 22:20:57.850966 ==
1692 22:20:57.854257 Dram Type= 6, Freq= 0, CH_1, rank 0
1693 22:20:57.857755 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1694 22:20:57.857870 ==
1695 22:20:57.860852 RX Vref Scan: 1
1696 22:20:57.860937
1697 22:20:57.861017 Set Vref Range= 32 -> 127
1698 22:20:57.861095
1699 22:20:57.864074 RX Vref 32 -> 127, step: 1
1700 22:20:57.864157
1701 22:20:57.867933 RX Delay -111 -> 252, step: 8
1702 22:20:57.868034
1703 22:20:57.870823 Set Vref, RX VrefLevel [Byte0]: 32
1704 22:20:57.873792 [Byte1]: 32
1705 22:20:57.873879
1706 22:20:57.877297 Set Vref, RX VrefLevel [Byte0]: 33
1707 22:20:57.880760 [Byte1]: 33
1708 22:20:57.884406
1709 22:20:57.884508 Set Vref, RX VrefLevel [Byte0]: 34
1710 22:20:57.887541 [Byte1]: 34
1711 22:20:57.891861
1712 22:20:57.891979 Set Vref, RX VrefLevel [Byte0]: 35
1713 22:20:57.895365 [Byte1]: 35
1714 22:20:57.899394
1715 22:20:57.899503 Set Vref, RX VrefLevel [Byte0]: 36
1716 22:20:57.902974 [Byte1]: 36
1717 22:20:57.907076
1718 22:20:57.907152 Set Vref, RX VrefLevel [Byte0]: 37
1719 22:20:57.910574 [Byte1]: 37
1720 22:20:57.915136
1721 22:20:57.915221 Set Vref, RX VrefLevel [Byte0]: 38
1722 22:20:57.918185 [Byte1]: 38
1723 22:20:57.922341
1724 22:20:57.922448 Set Vref, RX VrefLevel [Byte0]: 39
1725 22:20:57.926007 [Byte1]: 39
1726 22:20:57.930174
1727 22:20:57.930277 Set Vref, RX VrefLevel [Byte0]: 40
1728 22:20:57.933288 [Byte1]: 40
1729 22:20:57.937872
1730 22:20:57.937946 Set Vref, RX VrefLevel [Byte0]: 41
1731 22:20:57.941366 [Byte1]: 41
1732 22:20:57.945752
1733 22:20:57.945829 Set Vref, RX VrefLevel [Byte0]: 42
1734 22:20:57.948807 [Byte1]: 42
1735 22:20:57.953132
1736 22:20:57.953205 Set Vref, RX VrefLevel [Byte0]: 43
1737 22:20:57.956897 [Byte1]: 43
1738 22:20:57.960790
1739 22:20:57.960867 Set Vref, RX VrefLevel [Byte0]: 44
1740 22:20:57.964379 [Byte1]: 44
1741 22:20:57.968401
1742 22:20:57.968492 Set Vref, RX VrefLevel [Byte0]: 45
1743 22:20:57.971960 [Byte1]: 45
1744 22:20:57.976159
1745 22:20:57.976243 Set Vref, RX VrefLevel [Byte0]: 46
1746 22:20:57.979254 [Byte1]: 46
1747 22:20:57.983870
1748 22:20:57.983972 Set Vref, RX VrefLevel [Byte0]: 47
1749 22:20:57.987266 [Byte1]: 47
1750 22:20:57.991596
1751 22:20:57.991677 Set Vref, RX VrefLevel [Byte0]: 48
1752 22:20:57.994756 [Byte1]: 48
1753 22:20:57.998942
1754 22:20:57.999020 Set Vref, RX VrefLevel [Byte0]: 49
1755 22:20:58.002428 [Byte1]: 49
1756 22:20:58.007004
1757 22:20:58.007118 Set Vref, RX VrefLevel [Byte0]: 50
1758 22:20:58.010025 [Byte1]: 50
1759 22:20:58.014114
1760 22:20:58.014240 Set Vref, RX VrefLevel [Byte0]: 51
1761 22:20:58.017505 [Byte1]: 51
1762 22:20:58.021983
1763 22:20:58.022061 Set Vref, RX VrefLevel [Byte0]: 52
1764 22:20:58.025376 [Byte1]: 52
1765 22:20:58.029619
1766 22:20:58.029731 Set Vref, RX VrefLevel [Byte0]: 53
1767 22:20:58.033286 [Byte1]: 53
1768 22:20:58.037719
1769 22:20:58.037818 Set Vref, RX VrefLevel [Byte0]: 54
1770 22:20:58.040804 [Byte1]: 54
1771 22:20:58.045124
1772 22:20:58.045228 Set Vref, RX VrefLevel [Byte0]: 55
1773 22:20:58.048232 [Byte1]: 55
1774 22:20:58.052599
1775 22:20:58.052699 Set Vref, RX VrefLevel [Byte0]: 56
1776 22:20:58.055825 [Byte1]: 56
1777 22:20:58.060512
1778 22:20:58.060626 Set Vref, RX VrefLevel [Byte0]: 57
1779 22:20:58.063393 [Byte1]: 57
1780 22:20:58.068231
1781 22:20:58.068333 Set Vref, RX VrefLevel [Byte0]: 58
1782 22:20:58.071117 [Byte1]: 58
1783 22:20:58.075777
1784 22:20:58.075853 Set Vref, RX VrefLevel [Byte0]: 59
1785 22:20:58.079194 [Byte1]: 59
1786 22:20:58.083055
1787 22:20:58.083129 Set Vref, RX VrefLevel [Byte0]: 60
1788 22:20:58.086752 [Byte1]: 60
1789 22:20:58.091055
1790 22:20:58.091135 Set Vref, RX VrefLevel [Byte0]: 61
1791 22:20:58.094157 [Byte1]: 61
1792 22:20:58.098332
1793 22:20:58.098435 Set Vref, RX VrefLevel [Byte0]: 62
1794 22:20:58.101942 [Byte1]: 62
1795 22:20:58.106312
1796 22:20:58.106428 Set Vref, RX VrefLevel [Byte0]: 63
1797 22:20:58.109281 [Byte1]: 63
1798 22:20:58.113789
1799 22:20:58.113890 Set Vref, RX VrefLevel [Byte0]: 64
1800 22:20:58.117114 [Byte1]: 64
1801 22:20:58.121255
1802 22:20:58.121357 Set Vref, RX VrefLevel [Byte0]: 65
1803 22:20:58.124610 [Byte1]: 65
1804 22:20:58.129178
1805 22:20:58.129272 Set Vref, RX VrefLevel [Byte0]: 66
1806 22:20:58.132558 [Byte1]: 66
1807 22:20:58.136748
1808 22:20:58.136822 Set Vref, RX VrefLevel [Byte0]: 67
1809 22:20:58.139825 [Byte1]: 67
1810 22:20:58.144736
1811 22:20:58.144823 Set Vref, RX VrefLevel [Byte0]: 68
1812 22:20:58.147817 [Byte1]: 68
1813 22:20:58.152113
1814 22:20:58.152190 Set Vref, RX VrefLevel [Byte0]: 69
1815 22:20:58.155264 [Byte1]: 69
1816 22:20:58.159614
1817 22:20:58.159691 Set Vref, RX VrefLevel [Byte0]: 70
1818 22:20:58.162751 [Byte1]: 70
1819 22:20:58.167453
1820 22:20:58.167539 Set Vref, RX VrefLevel [Byte0]: 71
1821 22:20:58.171035 [Byte1]: 71
1822 22:20:58.175186
1823 22:20:58.175267 Set Vref, RX VrefLevel [Byte0]: 72
1824 22:20:58.178160 [Byte1]: 72
1825 22:20:58.182357
1826 22:20:58.182460 Set Vref, RX VrefLevel [Byte0]: 73
1827 22:20:58.185952 [Byte1]: 73
1828 22:20:58.190402
1829 22:20:58.190501 Final RX Vref Byte 0 = 62 to rank0
1830 22:20:58.193404 Final RX Vref Byte 1 = 53 to rank0
1831 22:20:58.197060 Final RX Vref Byte 0 = 62 to rank1
1832 22:20:58.200443 Final RX Vref Byte 1 = 53 to rank1==
1833 22:20:58.203519 Dram Type= 6, Freq= 0, CH_1, rank 0
1834 22:20:58.210221 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1835 22:20:58.210309 ==
1836 22:20:58.210376 DQS Delay:
1837 22:20:58.210437 DQS0 = 0, DQS1 = 0
1838 22:20:58.213913 DQM Delay:
1839 22:20:58.214059 DQM0 = 80, DQM1 = 71
1840 22:20:58.216843 DQ Delay:
1841 22:20:58.220229 DQ0 =88, DQ1 =72, DQ2 =68, DQ3 =76
1842 22:20:58.223802 DQ4 =76, DQ5 =92, DQ6 =92, DQ7 =76
1843 22:20:58.223885 DQ8 =56, DQ9 =64, DQ10 =72, DQ11 =68
1844 22:20:58.230081 DQ12 =80, DQ13 =80, DQ14 =76, DQ15 =76
1845 22:20:58.230166
1846 22:20:58.230231
1847 22:20:58.237211 [DQSOSCAuto] RK0, (LSB)MR18= 0x111b, (MSB)MR19= 0x606, tDQSOscB0 = 403 ps tDQSOscB1 = 405 ps
1848 22:20:58.239973 CH1 RK0: MR19=606, MR18=111B
1849 22:20:58.246721 CH1_RK0: MR19=0x606, MR18=0x111B, DQSOSC=403, MR23=63, INC=90, DEC=60
1850 22:20:58.246826
1851 22:20:58.249825 ----->DramcWriteLeveling(PI) begin...
1852 22:20:58.249909 ==
1853 22:20:58.253580 Dram Type= 6, Freq= 0, CH_1, rank 1
1854 22:20:58.256531 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1855 22:20:58.256615 ==
1856 22:20:58.259574 Write leveling (Byte 0): 27 => 27
1857 22:20:58.263248 Write leveling (Byte 1): 28 => 28
1858 22:20:58.266280 DramcWriteLeveling(PI) end<-----
1859 22:20:58.266363
1860 22:20:58.266428 ==
1861 22:20:58.269965 Dram Type= 6, Freq= 0, CH_1, rank 1
1862 22:20:58.273116 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1863 22:20:58.273242 ==
1864 22:20:58.276330 [Gating] SW mode calibration
1865 22:20:58.283095 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1866 22:20:58.289610 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1867 22:20:58.292639 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1868 22:20:58.299563 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1869 22:20:58.302987 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1870 22:20:58.306201 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1871 22:20:58.312920 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1872 22:20:58.316036 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1873 22:20:58.319133 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1874 22:20:58.326215 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1875 22:20:58.329234 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1876 22:20:58.333094 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1877 22:20:58.336000 0 7 8 | B1->B0 | 2323 2323 | 0 1 | (0 0) (0 0)
1878 22:20:58.342812 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1879 22:20:58.346245 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1880 22:20:58.349456 0 7 20 | B1->B0 | 2323 2323 | 0 1 | (0 0) (0 0)
1881 22:20:58.355997 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 22:20:58.359090 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 22:20:58.362682 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1884 22:20:58.369432 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1885 22:20:58.372483 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1886 22:20:58.376166 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1887 22:20:58.382721 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1888 22:20:58.385696 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1889 22:20:58.389420 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1890 22:20:58.396017 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1891 22:20:58.399049 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1892 22:20:58.402750 0 9 4 | B1->B0 | 2323 2e2d | 0 1 | (0 0) (0 0)
1893 22:20:58.409105 0 9 8 | B1->B0 | 2e2e 3434 | 0 1 | (0 0) (1 1)
1894 22:20:58.412212 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1895 22:20:58.415861 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1896 22:20:58.422349 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1897 22:20:58.425815 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1898 22:20:58.428896 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1899 22:20:58.435585 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1900 22:20:58.438639 0 10 4 | B1->B0 | 3030 2d2d | 0 0 | (0 1) (1 1)
1901 22:20:58.442100 0 10 8 | B1->B0 | 2727 2323 | 0 0 | (1 1) (0 0)
1902 22:20:58.448478 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1903 22:20:58.452014 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1904 22:20:58.455345 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1905 22:20:58.461989 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1906 22:20:58.465180 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1907 22:20:58.468923 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1908 22:20:58.475590 0 11 4 | B1->B0 | 2b2b 3838 | 0 1 | (0 0) (0 0)
1909 22:20:58.478625 0 11 8 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
1910 22:20:58.481587 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1911 22:20:58.488493 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1912 22:20:58.491549 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1913 22:20:58.495337 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1914 22:20:58.501408 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1915 22:20:58.504971 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1916 22:20:58.508060 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1917 22:20:58.514564 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1918 22:20:58.518312 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1919 22:20:58.521305 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1920 22:20:58.527823 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1921 22:20:58.531418 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1922 22:20:58.534508 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1923 22:20:58.541490 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1924 22:20:58.544411 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1925 22:20:58.547569 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1926 22:20:58.554573 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1927 22:20:58.557952 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1928 22:20:58.560828 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1929 22:20:58.567625 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1930 22:20:58.571103 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1931 22:20:58.574233 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1932 22:20:58.577883 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1933 22:20:58.584582 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1934 22:20:58.587519 Total UI for P1: 0, mck2ui 16
1935 22:20:58.590936 best dqsien dly found for B0: ( 0, 14, 4)
1936 22:20:58.594585 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1937 22:20:58.597726 Total UI for P1: 0, mck2ui 16
1938 22:20:58.600820 best dqsien dly found for B1: ( 0, 14, 6)
1939 22:20:58.604565 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1940 22:20:58.607496 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1941 22:20:58.607581
1942 22:20:58.611053 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1943 22:20:58.614055 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1944 22:20:58.617559 [Gating] SW calibration Done
1945 22:20:58.617665 ==
1946 22:20:58.620794 Dram Type= 6, Freq= 0, CH_1, rank 1
1947 22:20:58.627368 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1948 22:20:58.627461 ==
1949 22:20:58.627528 RX Vref Scan: 0
1950 22:20:58.627590
1951 22:20:58.630839 RX Vref 0 -> 0, step: 1
1952 22:20:58.630926
1953 22:20:58.633846 RX Delay -130 -> 252, step: 16
1954 22:20:58.637322 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1955 22:20:58.640493 iDelay=222, Bit 1, Center 69 (-50 ~ 189) 240
1956 22:20:58.643984 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1957 22:20:58.650475 iDelay=222, Bit 3, Center 69 (-50 ~ 189) 240
1958 22:20:58.653619 iDelay=222, Bit 4, Center 69 (-50 ~ 189) 240
1959 22:20:58.657418 iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240
1960 22:20:58.660320 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1961 22:20:58.664188 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1962 22:20:58.667244 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1963 22:20:58.673876 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1964 22:20:58.677152 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1965 22:20:58.680481 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1966 22:20:58.683526 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1967 22:20:58.690345 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1968 22:20:58.693867 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1969 22:20:58.696925 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1970 22:20:58.697015 ==
1971 22:20:58.700630 Dram Type= 6, Freq= 0, CH_1, rank 1
1972 22:20:58.703748 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1973 22:20:58.703835 ==
1974 22:20:58.706811 DQS Delay:
1975 22:20:58.706907 DQS0 = 0, DQS1 = 0
1976 22:20:58.710446 DQM Delay:
1977 22:20:58.710532 DQM0 = 77, DQM1 = 74
1978 22:20:58.710601 DQ Delay:
1979 22:20:58.713384 DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =69
1980 22:20:58.716824 DQ4 =69, DQ5 =85, DQ6 =93, DQ7 =77
1981 22:20:58.720475 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1982 22:20:58.723435 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1983 22:20:58.723517
1984 22:20:58.723583
1985 22:20:58.726625 ==
1986 22:20:58.726730 Dram Type= 6, Freq= 0, CH_1, rank 1
1987 22:20:58.733819 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1988 22:20:58.733938 ==
1989 22:20:58.734036
1990 22:20:58.734127
1991 22:20:58.736914 TX Vref Scan disable
1992 22:20:58.736999 == TX Byte 0 ==
1993 22:20:58.740267 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1994 22:20:58.746839 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1995 22:20:58.746931 == TX Byte 1 ==
1996 22:20:58.749874 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1997 22:20:58.756773 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1998 22:20:58.756869 ==
1999 22:20:58.759850 Dram Type= 6, Freq= 0, CH_1, rank 1
2000 22:20:58.763435 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2001 22:20:58.763533 ==
2002 22:20:58.776332 TX Vref=22, minBit 7, minWin=27, winSum=449
2003 22:20:58.779848 TX Vref=24, minBit 0, minWin=28, winSum=454
2004 22:20:58.782735 TX Vref=26, minBit 0, minWin=28, winSum=456
2005 22:20:58.786142 TX Vref=28, minBit 0, minWin=28, winSum=460
2006 22:20:58.789360 TX Vref=30, minBit 5, minWin=27, winSum=459
2007 22:20:58.796288 TX Vref=32, minBit 1, minWin=27, winSum=458
2008 22:20:58.799272 [TxChooseVref] Worse bit 0, Min win 28, Win sum 460, Final Vref 28
2009 22:20:58.799380
2010 22:20:58.803011 Final TX Range 1 Vref 28
2011 22:20:58.803113
2012 22:20:58.803195 ==
2013 22:20:58.806092 Dram Type= 6, Freq= 0, CH_1, rank 1
2014 22:20:58.809191 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2015 22:20:58.809276 ==
2016 22:20:58.812882
2017 22:20:58.812980
2018 22:20:58.813060 TX Vref Scan disable
2019 22:20:58.816560 == TX Byte 0 ==
2020 22:20:58.819541 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2021 22:20:58.826262 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2022 22:20:58.826363 == TX Byte 1 ==
2023 22:20:58.829760 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2024 22:20:58.835811 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2025 22:20:58.835925
2026 22:20:58.835992 [DATLAT]
2027 22:20:58.836096 Freq=800, CH1 RK1
2028 22:20:58.836171
2029 22:20:58.839439 DATLAT Default: 0xa
2030 22:20:58.839523 0, 0xFFFF, sum = 0
2031 22:20:58.842598 1, 0xFFFF, sum = 0
2032 22:20:58.846056 2, 0xFFFF, sum = 0
2033 22:20:58.846170 3, 0xFFFF, sum = 0
2034 22:20:58.849385 4, 0xFFFF, sum = 0
2035 22:20:58.849470 5, 0xFFFF, sum = 0
2036 22:20:58.852548 6, 0xFFFF, sum = 0
2037 22:20:58.852633 7, 0xFFFF, sum = 0
2038 22:20:58.855944 8, 0xFFFF, sum = 0
2039 22:20:58.856029 9, 0x0, sum = 1
2040 22:20:58.859353 10, 0x0, sum = 2
2041 22:20:58.859437 11, 0x0, sum = 3
2042 22:20:58.862403 12, 0x0, sum = 4
2043 22:20:58.862488 best_step = 10
2044 22:20:58.862584
2045 22:20:58.862646 ==
2046 22:20:58.866031 Dram Type= 6, Freq= 0, CH_1, rank 1
2047 22:20:58.868988 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2048 22:20:58.869072 ==
2049 22:20:58.872140 RX Vref Scan: 0
2050 22:20:58.872223
2051 22:20:58.875757 RX Vref 0 -> 0, step: 1
2052 22:20:58.875840
2053 22:20:58.875906 RX Delay -95 -> 252, step: 8
2054 22:20:58.882704 iDelay=209, Bit 0, Center 84 (-39 ~ 208) 248
2055 22:20:58.886265 iDelay=209, Bit 1, Center 72 (-47 ~ 192) 240
2056 22:20:58.889212 iDelay=209, Bit 2, Center 68 (-55 ~ 192) 248
2057 22:20:58.892847 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
2058 22:20:58.899337 iDelay=209, Bit 4, Center 76 (-47 ~ 200) 248
2059 22:20:58.902508 iDelay=209, Bit 5, Center 88 (-31 ~ 208) 240
2060 22:20:58.905881 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
2061 22:20:58.909008 iDelay=209, Bit 7, Center 76 (-47 ~ 200) 248
2062 22:20:58.912744 iDelay=209, Bit 8, Center 60 (-63 ~ 184) 248
2063 22:20:58.915802 iDelay=209, Bit 9, Center 64 (-55 ~ 184) 240
2064 22:20:58.922511 iDelay=209, Bit 10, Center 76 (-47 ~ 200) 248
2065 22:20:58.926232 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
2066 22:20:58.929100 iDelay=209, Bit 12, Center 80 (-39 ~ 200) 240
2067 22:20:58.932536 iDelay=209, Bit 13, Center 80 (-39 ~ 200) 240
2068 22:20:58.939190 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
2069 22:20:58.942270 iDelay=209, Bit 15, Center 80 (-39 ~ 200) 240
2070 22:20:58.942358 ==
2071 22:20:58.945789 Dram Type= 6, Freq= 0, CH_1, rank 1
2072 22:20:58.948748 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2073 22:20:58.948834 ==
2074 22:20:58.952298 DQS Delay:
2075 22:20:58.952382 DQS0 = 0, DQS1 = 0
2076 22:20:58.952449 DQM Delay:
2077 22:20:58.955672 DQM0 = 78, DQM1 = 73
2078 22:20:58.955756 DQ Delay:
2079 22:20:58.959132 DQ0 =84, DQ1 =72, DQ2 =68, DQ3 =72
2080 22:20:58.962225 DQ4 =76, DQ5 =88, DQ6 =92, DQ7 =76
2081 22:20:58.965407 DQ8 =60, DQ9 =64, DQ10 =76, DQ11 =68
2082 22:20:58.969019 DQ12 =80, DQ13 =80, DQ14 =80, DQ15 =80
2083 22:20:58.969102
2084 22:20:58.969167
2085 22:20:58.978768 [DQSOSCAuto] RK1, (LSB)MR18= 0x2037, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 401 ps
2086 22:20:58.981750 CH1 RK1: MR19=606, MR18=2037
2087 22:20:58.985420 CH1_RK1: MR19=0x606, MR18=0x2037, DQSOSC=395, MR23=63, INC=94, DEC=63
2088 22:20:58.988531 [RxdqsGatingPostProcess] freq 800
2089 22:20:58.995079 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2090 22:20:58.998632 Pre-setting of DQS Precalculation
2091 22:20:59.002097 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2092 22:20:59.011534 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2093 22:20:59.018359 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2094 22:20:59.018499
2095 22:20:59.018594
2096 22:20:59.022101 [Calibration Summary] 1600 Mbps
2097 22:20:59.022220 CH 0, Rank 0
2098 22:20:59.025297 SW Impedance : PASS
2099 22:20:59.025410 DUTY Scan : NO K
2100 22:20:59.028307 ZQ Calibration : PASS
2101 22:20:59.031956 Jitter Meter : NO K
2102 22:20:59.032058 CBT Training : PASS
2103 22:20:59.034918 Write leveling : PASS
2104 22:20:59.038206 RX DQS gating : PASS
2105 22:20:59.038285 RX DQ/DQS(RDDQC) : PASS
2106 22:20:59.041725 TX DQ/DQS : PASS
2107 22:20:59.044793 RX DATLAT : PASS
2108 22:20:59.044877 RX DQ/DQS(Engine): PASS
2109 22:20:59.048031 TX OE : NO K
2110 22:20:59.048106 All Pass.
2111 22:20:59.048176
2112 22:20:59.051666 CH 0, Rank 1
2113 22:20:59.051738 SW Impedance : PASS
2114 22:20:59.054791 DUTY Scan : NO K
2115 22:20:59.058267 ZQ Calibration : PASS
2116 22:20:59.058381 Jitter Meter : NO K
2117 22:20:59.061231 CBT Training : PASS
2118 22:20:59.061336 Write leveling : PASS
2119 22:20:59.064528 RX DQS gating : PASS
2120 22:20:59.068269 RX DQ/DQS(RDDQC) : PASS
2121 22:20:59.068353 TX DQ/DQS : PASS
2122 22:20:59.071280 RX DATLAT : PASS
2123 22:20:59.074907 RX DQ/DQS(Engine): PASS
2124 22:20:59.074994 TX OE : NO K
2125 22:20:59.077799 All Pass.
2126 22:20:59.077879
2127 22:20:59.077966 CH 1, Rank 0
2128 22:20:59.081509 SW Impedance : PASS
2129 22:20:59.081591 DUTY Scan : NO K
2130 22:20:59.084563 ZQ Calibration : PASS
2131 22:20:59.087953 Jitter Meter : NO K
2132 22:20:59.088035 CBT Training : PASS
2133 22:20:59.090940 Write leveling : PASS
2134 22:20:59.094753 RX DQS gating : PASS
2135 22:20:59.094886 RX DQ/DQS(RDDQC) : PASS
2136 22:20:59.097664 TX DQ/DQS : PASS
2137 22:20:59.101197 RX DATLAT : PASS
2138 22:20:59.101279 RX DQ/DQS(Engine): PASS
2139 22:20:59.104648 TX OE : NO K
2140 22:20:59.104765 All Pass.
2141 22:20:59.104847
2142 22:20:59.107495 CH 1, Rank 1
2143 22:20:59.107581 SW Impedance : PASS
2144 22:20:59.110911 DUTY Scan : NO K
2145 22:20:59.114400 ZQ Calibration : PASS
2146 22:20:59.114490 Jitter Meter : NO K
2147 22:20:59.117736 CBT Training : PASS
2148 22:20:59.120757 Write leveling : PASS
2149 22:20:59.120851 RX DQS gating : PASS
2150 22:20:59.124482 RX DQ/DQS(RDDQC) : PASS
2151 22:20:59.124561 TX DQ/DQS : PASS
2152 22:20:59.127646 RX DATLAT : PASS
2153 22:20:59.130638 RX DQ/DQS(Engine): PASS
2154 22:20:59.130716 TX OE : NO K
2155 22:20:59.134242 All Pass.
2156 22:20:59.134317
2157 22:20:59.134378 DramC Write-DBI off
2158 22:20:59.137338 PER_BANK_REFRESH: Hybrid Mode
2159 22:20:59.140971 TX_TRACKING: ON
2160 22:20:59.143843 [GetDramInforAfterCalByMRR] Vendor 6.
2161 22:20:59.148114 [GetDramInforAfterCalByMRR] Revision 606.
2162 22:20:59.150625 [GetDramInforAfterCalByMRR] Revision 2 0.
2163 22:20:59.150739 MR0 0x3b3b
2164 22:20:59.150854 MR8 0x5151
2165 22:20:59.157808 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2166 22:20:59.157899
2167 22:20:59.157969 MR0 0x3b3b
2168 22:20:59.158034 MR8 0x5151
2169 22:20:59.160626 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2170 22:20:59.160709
2171 22:20:59.170841 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2172 22:20:59.174056 [FAST_K] Save calibration result to emmc
2173 22:20:59.177203 [FAST_K] Save calibration result to emmc
2174 22:20:59.180836 dram_init: config_dvfs: 1
2175 22:20:59.184013 dramc_set_vcore_voltage set vcore to 662500
2176 22:20:59.187057 Read voltage for 1200, 2
2177 22:20:59.187136 Vio18 = 0
2178 22:20:59.190558 Vcore = 662500
2179 22:20:59.190665 Vdram = 0
2180 22:20:59.190756 Vddq = 0
2181 22:20:59.190870 Vmddr = 0
2182 22:20:59.197041 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2183 22:20:59.200723 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2184 22:20:59.204067 MEM_TYPE=3, freq_sel=15
2185 22:20:59.206840 sv_algorithm_assistance_LP4_1600
2186 22:20:59.210436 ============ PULL DRAM RESETB DOWN ============
2187 22:20:59.217292 ========== PULL DRAM RESETB DOWN end =========
2188 22:20:59.220608 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2189 22:20:59.223451 ===================================
2190 22:20:59.226846 LPDDR4 DRAM CONFIGURATION
2191 22:20:59.229888 ===================================
2192 22:20:59.229977 EX_ROW_EN[0] = 0x0
2193 22:20:59.233531 EX_ROW_EN[1] = 0x0
2194 22:20:59.233618 LP4Y_EN = 0x0
2195 22:20:59.236599 WORK_FSP = 0x0
2196 22:20:59.236683 WL = 0x4
2197 22:20:59.240315 RL = 0x4
2198 22:20:59.240398 BL = 0x2
2199 22:20:59.243370 RPST = 0x0
2200 22:20:59.247081 RD_PRE = 0x0
2201 22:20:59.247172 WR_PRE = 0x1
2202 22:20:59.250024 WR_PST = 0x0
2203 22:20:59.250110 DBI_WR = 0x0
2204 22:20:59.253317 DBI_RD = 0x0
2205 22:20:59.253429 OTF = 0x1
2206 22:20:59.256544 ===================================
2207 22:20:59.260090 ===================================
2208 22:20:59.260175 ANA top config
2209 22:20:59.263117 ===================================
2210 22:20:59.266878 DLL_ASYNC_EN = 0
2211 22:20:59.270031 ALL_SLAVE_EN = 0
2212 22:20:59.273099 NEW_RANK_MODE = 1
2213 22:20:59.276632 DLL_IDLE_MODE = 1
2214 22:20:59.276721 LP45_APHY_COMB_EN = 1
2215 22:20:59.280181 TX_ODT_DIS = 1
2216 22:20:59.283230 NEW_8X_MODE = 1
2217 22:20:59.286284 ===================================
2218 22:20:59.289987 ===================================
2219 22:20:59.292990 data_rate = 2400
2220 22:20:59.296527 CKR = 1
2221 22:20:59.299515 DQ_P2S_RATIO = 8
2222 22:20:59.299622 ===================================
2223 22:20:59.302762 CA_P2S_RATIO = 8
2224 22:20:59.306299 DQ_CA_OPEN = 0
2225 22:20:59.310017 DQ_SEMI_OPEN = 0
2226 22:20:59.313077 CA_SEMI_OPEN = 0
2227 22:20:59.316135 CA_FULL_RATE = 0
2228 22:20:59.316221 DQ_CKDIV4_EN = 0
2229 22:20:59.319850 CA_CKDIV4_EN = 0
2230 22:20:59.322734 CA_PREDIV_EN = 0
2231 22:20:59.326625 PH8_DLY = 17
2232 22:20:59.329473 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2233 22:20:59.332926 DQ_AAMCK_DIV = 4
2234 22:20:59.336472 CA_AAMCK_DIV = 4
2235 22:20:59.336592 CA_ADMCK_DIV = 4
2236 22:20:59.339255 DQ_TRACK_CA_EN = 0
2237 22:20:59.342919 CA_PICK = 1200
2238 22:20:59.346057 CA_MCKIO = 1200
2239 22:20:59.349209 MCKIO_SEMI = 0
2240 22:20:59.352927 PLL_FREQ = 2366
2241 22:20:59.356012 DQ_UI_PI_RATIO = 32
2242 22:20:59.356101 CA_UI_PI_RATIO = 0
2243 22:20:59.359491 ===================================
2244 22:20:59.362390 ===================================
2245 22:20:59.365918 memory_type:LPDDR4
2246 22:20:59.369229 GP_NUM : 10
2247 22:20:59.369315 SRAM_EN : 1
2248 22:20:59.372787 MD32_EN : 0
2249 22:20:59.375832 ===================================
2250 22:20:59.379386 [ANA_INIT] >>>>>>>>>>>>>>
2251 22:20:59.382526 <<<<<< [CONFIGURE PHASE]: ANA_TX
2252 22:20:59.385582 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2253 22:20:59.388991 ===================================
2254 22:20:59.389077 data_rate = 2400,PCW = 0X5b00
2255 22:20:59.392623 ===================================
2256 22:20:59.395727 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2257 22:20:59.402255 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2258 22:20:59.408759 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2259 22:20:59.412495 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2260 22:20:59.415490 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2261 22:20:59.418636 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2262 22:20:59.422455 [ANA_INIT] flow start
2263 22:20:59.425508 [ANA_INIT] PLL >>>>>>>>
2264 22:20:59.425615 [ANA_INIT] PLL <<<<<<<<
2265 22:20:59.429091 [ANA_INIT] MIDPI >>>>>>>>
2266 22:20:59.432017 [ANA_INIT] MIDPI <<<<<<<<
2267 22:20:59.432127 [ANA_INIT] DLL >>>>>>>>
2268 22:20:59.435566 [ANA_INIT] DLL <<<<<<<<
2269 22:20:59.438910 [ANA_INIT] flow end
2270 22:20:59.442575 ============ LP4 DIFF to SE enter ============
2271 22:20:59.445089 ============ LP4 DIFF to SE exit ============
2272 22:20:59.448779 [ANA_INIT] <<<<<<<<<<<<<
2273 22:20:59.451855 [Flow] Enable top DCM control >>>>>
2274 22:20:59.455019 [Flow] Enable top DCM control <<<<<
2275 22:20:59.458578 Enable DLL master slave shuffle
2276 22:20:59.461736 ==============================================================
2277 22:20:59.465305 Gating Mode config
2278 22:20:59.471882 ==============================================================
2279 22:20:59.472004 Config description:
2280 22:20:59.482120 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2281 22:20:59.488320 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2282 22:20:59.491889 SELPH_MODE 0: By rank 1: By Phase
2283 22:20:59.498474 ==============================================================
2284 22:20:59.501546 GAT_TRACK_EN = 1
2285 22:20:59.505204 RX_GATING_MODE = 2
2286 22:20:59.508633 RX_GATING_TRACK_MODE = 2
2287 22:20:59.511624 SELPH_MODE = 1
2288 22:20:59.514720 PICG_EARLY_EN = 1
2289 22:20:59.518363 VALID_LAT_VALUE = 1
2290 22:20:59.521548 ==============================================================
2291 22:20:59.525247 Enter into Gating configuration >>>>
2292 22:20:59.528395 Exit from Gating configuration <<<<
2293 22:20:59.531436 Enter into DVFS_PRE_config >>>>>
2294 22:20:59.544785 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2295 22:20:59.544923 Exit from DVFS_PRE_config <<<<<
2296 22:20:59.548003 Enter into PICG configuration >>>>
2297 22:20:59.551546 Exit from PICG configuration <<<<
2298 22:20:59.555091 [RX_INPUT] configuration >>>>>
2299 22:20:59.558226 [RX_INPUT] configuration <<<<<
2300 22:20:59.564430 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2301 22:20:59.568190 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2302 22:20:59.574798 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2303 22:20:59.581307 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2304 22:20:59.587897 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2305 22:20:59.594738 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2306 22:20:59.597904 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2307 22:20:59.601150 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2308 22:20:59.604022 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2309 22:20:59.611016 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2310 22:20:59.614396 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2311 22:20:59.617402 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2312 22:20:59.621118 ===================================
2313 22:20:59.624299 LPDDR4 DRAM CONFIGURATION
2314 22:20:59.627370 ===================================
2315 22:20:59.631055 EX_ROW_EN[0] = 0x0
2316 22:20:59.631218 EX_ROW_EN[1] = 0x0
2317 22:20:59.634147 LP4Y_EN = 0x0
2318 22:20:59.634233 WORK_FSP = 0x0
2319 22:20:59.637621 WL = 0x4
2320 22:20:59.637714 RL = 0x4
2321 22:20:59.640766 BL = 0x2
2322 22:20:59.640850 RPST = 0x0
2323 22:20:59.643894 RD_PRE = 0x0
2324 22:20:59.643982 WR_PRE = 0x1
2325 22:20:59.647566 WR_PST = 0x0
2326 22:20:59.647650 DBI_WR = 0x0
2327 22:20:59.650340 DBI_RD = 0x0
2328 22:20:59.650424 OTF = 0x1
2329 22:20:59.653959 ===================================
2330 22:20:59.660988 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2331 22:20:59.663824 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2332 22:20:59.667434 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2333 22:20:59.670441 ===================================
2334 22:20:59.673952 LPDDR4 DRAM CONFIGURATION
2335 22:20:59.676891 ===================================
2336 22:20:59.680587 EX_ROW_EN[0] = 0x10
2337 22:20:59.680709 EX_ROW_EN[1] = 0x0
2338 22:20:59.683682 LP4Y_EN = 0x0
2339 22:20:59.683789 WORK_FSP = 0x0
2340 22:20:59.687153 WL = 0x4
2341 22:20:59.687244 RL = 0x4
2342 22:20:59.690205 BL = 0x2
2343 22:20:59.690307 RPST = 0x0
2344 22:20:59.693782 RD_PRE = 0x0
2345 22:20:59.693899 WR_PRE = 0x1
2346 22:20:59.696819 WR_PST = 0x0
2347 22:20:59.696927 DBI_WR = 0x0
2348 22:20:59.700567 DBI_RD = 0x0
2349 22:20:59.700674 OTF = 0x1
2350 22:20:59.703633 ===================================
2351 22:20:59.710201 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2352 22:20:59.710319 ==
2353 22:20:59.713540 Dram Type= 6, Freq= 0, CH_0, rank 0
2354 22:20:59.720292 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2355 22:20:59.720410 ==
2356 22:20:59.720511 [Duty_Offset_Calibration]
2357 22:20:59.723444 B0:2 B1:0 CA:3
2358 22:20:59.723554
2359 22:20:59.726764 [DutyScan_Calibration_Flow] k_type=0
2360 22:20:59.735516
2361 22:20:59.735612 ==CLK 0==
2362 22:20:59.738603 Final CLK duty delay cell = 0
2363 22:20:59.742244 [0] MAX Duty = 5031%(X100), DQS PI = 12
2364 22:20:59.745278 [0] MIN Duty = 4875%(X100), DQS PI = 58
2365 22:20:59.745395 [0] AVG Duty = 4953%(X100)
2366 22:20:59.749009
2367 22:20:59.752097 CH0 CLK Duty spec in!! Max-Min= 156%
2368 22:20:59.755630 [DutyScan_Calibration_Flow] ====Done====
2369 22:20:59.755744
2370 22:20:59.758757 [DutyScan_Calibration_Flow] k_type=1
2371 22:20:59.774409
2372 22:20:59.774529 ==DQS 0 ==
2373 22:20:59.777477 Final DQS duty delay cell = 0
2374 22:20:59.780862 [0] MAX Duty = 5062%(X100), DQS PI = 12
2375 22:20:59.783880 [0] MIN Duty = 4876%(X100), DQS PI = 50
2376 22:20:59.787490 [0] AVG Duty = 4969%(X100)
2377 22:20:59.787569
2378 22:20:59.787632 ==DQS 1 ==
2379 22:20:59.790628 Final DQS duty delay cell = -4
2380 22:20:59.794027 [-4] MAX Duty = 5000%(X100), DQS PI = 36
2381 22:20:59.797660 [-4] MIN Duty = 4875%(X100), DQS PI = 0
2382 22:20:59.800809 [-4] AVG Duty = 4937%(X100)
2383 22:20:59.800917
2384 22:20:59.804025 CH0 DQS 0 Duty spec in!! Max-Min= 186%
2385 22:20:59.804198
2386 22:20:59.807071 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2387 22:20:59.810661 [DutyScan_Calibration_Flow] ====Done====
2388 22:20:59.810846
2389 22:20:59.813759 [DutyScan_Calibration_Flow] k_type=3
2390 22:20:59.831709
2391 22:20:59.831929 ==DQM 0 ==
2392 22:20:59.835231 Final DQM duty delay cell = 0
2393 22:20:59.838315 [0] MAX Duty = 5124%(X100), DQS PI = 28
2394 22:20:59.841362 [0] MIN Duty = 4876%(X100), DQS PI = 48
2395 22:20:59.845018 [0] AVG Duty = 5000%(X100)
2396 22:20:59.845183
2397 22:20:59.845319 ==DQM 1 ==
2398 22:20:59.848063 Final DQM duty delay cell = 4
2399 22:20:59.851829 [4] MAX Duty = 5124%(X100), DQS PI = 0
2400 22:20:59.855055 [4] MIN Duty = 5031%(X100), DQS PI = 12
2401 22:20:59.858387 [4] AVG Duty = 5077%(X100)
2402 22:20:59.858552
2403 22:20:59.861300 CH0 DQM 0 Duty spec in!! Max-Min= 248%
2404 22:20:59.861390
2405 22:20:59.865069 CH0 DQM 1 Duty spec in!! Max-Min= 93%
2406 22:20:59.868252 [DutyScan_Calibration_Flow] ====Done====
2407 22:20:59.868423
2408 22:20:59.871259 [DutyScan_Calibration_Flow] k_type=2
2409 22:20:59.886205
2410 22:20:59.886364 ==DQ 0 ==
2411 22:20:59.889921 Final DQ duty delay cell = -4
2412 22:20:59.892996 [-4] MAX Duty = 5000%(X100), DQS PI = 12
2413 22:20:59.896642 [-4] MIN Duty = 4907%(X100), DQS PI = 44
2414 22:20:59.899466 [-4] AVG Duty = 4953%(X100)
2415 22:20:59.899565
2416 22:20:59.899634 ==DQ 1 ==
2417 22:20:59.903097 Final DQ duty delay cell = -4
2418 22:20:59.906144 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2419 22:20:59.909797 [-4] MIN Duty = 4876%(X100), DQS PI = 18
2420 22:20:59.912826 [-4] AVG Duty = 4938%(X100)
2421 22:20:59.912931
2422 22:20:59.916566 CH0 DQ 0 Duty spec in!! Max-Min= 93%
2423 22:20:59.916691
2424 22:20:59.919588 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2425 22:20:59.922786 [DutyScan_Calibration_Flow] ====Done====
2426 22:20:59.922902 ==
2427 22:20:59.925874 Dram Type= 6, Freq= 0, CH_1, rank 0
2428 22:20:59.929516 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2429 22:20:59.929617 ==
2430 22:20:59.932879 [Duty_Offset_Calibration]
2431 22:20:59.932972 B0:1 B1:-2 CA:0
2432 22:20:59.935941
2433 22:20:59.936031 [DutyScan_Calibration_Flow] k_type=0
2434 22:20:59.946872
2435 22:20:59.947022 ==CLK 0==
2436 22:20:59.950191 Final CLK duty delay cell = 0
2437 22:20:59.953885 [0] MAX Duty = 5031%(X100), DQS PI = 52
2438 22:20:59.956993 [0] MIN Duty = 4844%(X100), DQS PI = 26
2439 22:20:59.957097 [0] AVG Duty = 4937%(X100)
2440 22:20:59.960135
2441 22:20:59.963718 CH1 CLK Duty spec in!! Max-Min= 187%
2442 22:20:59.966706 [DutyScan_Calibration_Flow] ====Done====
2443 22:20:59.966809
2444 22:20:59.969830 [DutyScan_Calibration_Flow] k_type=1
2445 22:20:59.985479
2446 22:20:59.985604 ==DQS 0 ==
2447 22:20:59.988788 Final DQS duty delay cell = -4
2448 22:20:59.992226 [-4] MAX Duty = 5000%(X100), DQS PI = 56
2449 22:20:59.995151 [-4] MIN Duty = 4907%(X100), DQS PI = 4
2450 22:20:59.998821 [-4] AVG Duty = 4953%(X100)
2451 22:20:59.998914
2452 22:20:59.998982 ==DQS 1 ==
2453 22:21:00.001933 Final DQS duty delay cell = 0
2454 22:21:00.005383 [0] MAX Duty = 5093%(X100), DQS PI = 32
2455 22:21:00.008779 [0] MIN Duty = 4844%(X100), DQS PI = 58
2456 22:21:00.011901 [0] AVG Duty = 4968%(X100)
2457 22:21:00.012016
2458 22:21:00.015113 CH1 DQS 0 Duty spec in!! Max-Min= 93%
2459 22:21:00.015201
2460 22:21:00.018774 CH1 DQS 1 Duty spec in!! Max-Min= 249%
2461 22:21:00.021880 [DutyScan_Calibration_Flow] ====Done====
2462 22:21:00.021965
2463 22:21:00.024890 [DutyScan_Calibration_Flow] k_type=3
2464 22:21:00.041898
2465 22:21:00.042017 ==DQM 0 ==
2466 22:21:00.045506 Final DQM duty delay cell = 0
2467 22:21:00.048917 [0] MAX Duty = 5000%(X100), DQS PI = 56
2468 22:21:00.052298 [0] MIN Duty = 4876%(X100), DQS PI = 20
2469 22:21:00.052391 [0] AVG Duty = 4938%(X100)
2470 22:21:00.055791
2471 22:21:00.055870 ==DQM 1 ==
2472 22:21:00.058817 Final DQM duty delay cell = 0
2473 22:21:00.061981 [0] MAX Duty = 5031%(X100), DQS PI = 4
2474 22:21:00.065741 [0] MIN Duty = 4907%(X100), DQS PI = 46
2475 22:21:00.068637 [0] AVG Duty = 4969%(X100)
2476 22:21:00.068757
2477 22:21:00.071787 CH1 DQM 0 Duty spec in!! Max-Min= 124%
2478 22:21:00.071879
2479 22:21:00.075493 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2480 22:21:00.078587 [DutyScan_Calibration_Flow] ====Done====
2481 22:21:00.078683
2482 22:21:00.082281 [DutyScan_Calibration_Flow] k_type=2
2483 22:21:00.098522
2484 22:21:00.098701 ==DQ 0 ==
2485 22:21:00.101841 Final DQ duty delay cell = 0
2486 22:21:00.104962 [0] MAX Duty = 5062%(X100), DQS PI = 0
2487 22:21:00.108924 [0] MIN Duty = 4938%(X100), DQS PI = 24
2488 22:21:00.109072 [0] AVG Duty = 5000%(X100)
2489 22:21:00.109170
2490 22:21:00.111812 ==DQ 1 ==
2491 22:21:00.115212 Final DQ duty delay cell = 0
2492 22:21:00.118539 [0] MAX Duty = 5124%(X100), DQS PI = 14
2493 22:21:00.121625 [0] MIN Duty = 4969%(X100), DQS PI = 58
2494 22:21:00.121748 [0] AVG Duty = 5046%(X100)
2495 22:21:00.121845
2496 22:21:00.125425 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2497 22:21:00.128497
2498 22:21:00.131574 CH1 DQ 1 Duty spec in!! Max-Min= 155%
2499 22:21:00.135270 [DutyScan_Calibration_Flow] ====Done====
2500 22:21:00.138322 nWR fixed to 30
2501 22:21:00.138436 [ModeRegInit_LP4] CH0 RK0
2502 22:21:00.141873 [ModeRegInit_LP4] CH0 RK1
2503 22:21:00.144750 [ModeRegInit_LP4] CH1 RK0
2504 22:21:00.148363 [ModeRegInit_LP4] CH1 RK1
2505 22:21:00.148468 match AC timing 7
2506 22:21:00.154808 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2507 22:21:00.158210 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2508 22:21:00.161529 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2509 22:21:00.168135 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2510 22:21:00.171149 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2511 22:21:00.171251 ==
2512 22:21:00.174860 Dram Type= 6, Freq= 0, CH_0, rank 0
2513 22:21:00.177886 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2514 22:21:00.177996 ==
2515 22:21:00.184737 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2516 22:21:00.191663 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2517 22:21:00.198687 [CA 0] Center 40 (10~71) winsize 62
2518 22:21:00.201757 [CA 1] Center 39 (9~70) winsize 62
2519 22:21:00.205091 [CA 2] Center 36 (6~66) winsize 61
2520 22:21:00.208467 [CA 3] Center 35 (5~66) winsize 62
2521 22:21:00.211529 [CA 4] Center 34 (4~65) winsize 62
2522 22:21:00.215339 [CA 5] Center 33 (3~64) winsize 62
2523 22:21:00.215449
2524 22:21:00.218268 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2525 22:21:00.218351
2526 22:21:00.221741 [CATrainingPosCal] consider 1 rank data
2527 22:21:00.225126 u2DelayCellTimex100 = 270/100 ps
2528 22:21:00.227957 CA0 delay=40 (10~71),Diff = 7 PI (33 cell)
2529 22:21:00.235040 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2530 22:21:00.238168 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2531 22:21:00.241922 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2532 22:21:00.244979 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2533 22:21:00.248017 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2534 22:21:00.248134
2535 22:21:00.251710 CA PerBit enable=1, Macro0, CA PI delay=33
2536 22:21:00.251797
2537 22:21:00.254738 [CBTSetCACLKResult] CA Dly = 33
2538 22:21:00.257920 CS Dly: 7 (0~38)
2539 22:21:00.258021 ==
2540 22:21:00.261382 Dram Type= 6, Freq= 0, CH_0, rank 1
2541 22:21:00.264449 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2542 22:21:00.264569 ==
2543 22:21:00.271158 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2544 22:21:00.274460 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2545 22:21:00.284826 [CA 0] Center 40 (10~70) winsize 61
2546 22:21:00.287833 [CA 1] Center 40 (10~70) winsize 61
2547 22:21:00.291049 [CA 2] Center 35 (5~66) winsize 62
2548 22:21:00.294670 [CA 3] Center 35 (5~66) winsize 62
2549 22:21:00.297586 [CA 4] Center 34 (4~65) winsize 62
2550 22:21:00.301251 [CA 5] Center 33 (3~64) winsize 62
2551 22:21:00.301354
2552 22:21:00.304314 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2553 22:21:00.304402
2554 22:21:00.307977 [CATrainingPosCal] consider 2 rank data
2555 22:21:00.311386 u2DelayCellTimex100 = 270/100 ps
2556 22:21:00.314328 CA0 delay=40 (10~70),Diff = 7 PI (33 cell)
2557 22:21:00.320980 CA1 delay=40 (10~70),Diff = 7 PI (33 cell)
2558 22:21:00.324098 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2559 22:21:00.327452 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2560 22:21:00.331006 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2561 22:21:00.333961 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2562 22:21:00.334062
2563 22:21:00.337415 CA PerBit enable=1, Macro0, CA PI delay=33
2564 22:21:00.337503
2565 22:21:00.341052 [CBTSetCACLKResult] CA Dly = 33
2566 22:21:00.344159 CS Dly: 8 (0~40)
2567 22:21:00.344250
2568 22:21:00.347179 ----->DramcWriteLeveling(PI) begin...
2569 22:21:00.347265 ==
2570 22:21:00.350950 Dram Type= 6, Freq= 0, CH_0, rank 0
2571 22:21:00.354084 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2572 22:21:00.354175 ==
2573 22:21:00.357029 Write leveling (Byte 0): 33 => 33
2574 22:21:00.360740 Write leveling (Byte 1): 29 => 29
2575 22:21:00.364144 DramcWriteLeveling(PI) end<-----
2576 22:21:00.364237
2577 22:21:00.364309 ==
2578 22:21:00.367457 Dram Type= 6, Freq= 0, CH_0, rank 0
2579 22:21:00.370463 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2580 22:21:00.370549 ==
2581 22:21:00.374018 [Gating] SW mode calibration
2582 22:21:00.380386 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2583 22:21:00.386951 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2584 22:21:00.390531 0 15 0 | B1->B0 | 2323 2424 | 0 1 | (0 0) (1 1)
2585 22:21:00.393868 0 15 4 | B1->B0 | 2929 3434 | 1 0 | (0 0) (0 0)
2586 22:21:00.400243 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2587 22:21:00.403299 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2588 22:21:00.407020 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2589 22:21:00.413166 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2590 22:21:00.416759 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2591 22:21:00.419730 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2592 22:21:00.426975 1 0 0 | B1->B0 | 3333 2d2d | 0 0 | (0 0) (0 1)
2593 22:21:00.429855 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2594 22:21:00.433344 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2595 22:21:00.439983 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2596 22:21:00.443474 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2597 22:21:00.446438 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2598 22:21:00.453262 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2599 22:21:00.456906 1 0 28 | B1->B0 | 2323 2726 | 0 1 | (0 0) (0 0)
2600 22:21:00.459958 1 1 0 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
2601 22:21:00.466892 1 1 4 | B1->B0 | 3d3d 4646 | 1 0 | (0 0) (0 0)
2602 22:21:00.469588 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2603 22:21:00.472783 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2604 22:21:00.479341 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2605 22:21:00.482988 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2606 22:21:00.486147 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2607 22:21:00.493148 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2608 22:21:00.496644 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2609 22:21:00.499469 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2610 22:21:00.506077 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2611 22:21:00.509777 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2612 22:21:00.512938 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2613 22:21:00.519615 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2614 22:21:00.522697 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2615 22:21:00.526375 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2616 22:21:00.532372 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2617 22:21:00.535937 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2618 22:21:00.539733 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2619 22:21:00.546106 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2620 22:21:00.548975 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2621 22:21:00.552503 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2622 22:21:00.559115 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2623 22:21:00.562620 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2624 22:21:00.565732 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2625 22:21:00.572416 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2626 22:21:00.572533 Total UI for P1: 0, mck2ui 16
2627 22:21:00.579155 best dqsien dly found for B0: ( 1, 4, 0)
2628 22:21:00.582104 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2629 22:21:00.585855 Total UI for P1: 0, mck2ui 16
2630 22:21:00.589078 best dqsien dly found for B1: ( 1, 4, 2)
2631 22:21:00.592589 best DQS0 dly(MCK, UI, PI) = (1, 4, 0)
2632 22:21:00.595519 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2633 22:21:00.595623
2634 22:21:00.599132 best DQS0 P1 dly(MCK, UI, PI) = (1, 8, 0)
2635 22:21:00.602249 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2636 22:21:00.605496 [Gating] SW calibration Done
2637 22:21:00.605607 ==
2638 22:21:00.609070 Dram Type= 6, Freq= 0, CH_0, rank 0
2639 22:21:00.612078 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2640 22:21:00.612185 ==
2641 22:21:00.615205 RX Vref Scan: 0
2642 22:21:00.615305
2643 22:21:00.618970 RX Vref 0 -> 0, step: 1
2644 22:21:00.619087
2645 22:21:00.619183 RX Delay -40 -> 252, step: 8
2646 22:21:00.625609 iDelay=200, Bit 0, Center 111 (32 ~ 191) 160
2647 22:21:00.628569 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
2648 22:21:00.632262 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2649 22:21:00.635203 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2650 22:21:00.638759 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2651 22:21:00.645557 iDelay=200, Bit 5, Center 99 (24 ~ 175) 152
2652 22:21:00.648683 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
2653 22:21:00.651750 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2654 22:21:00.655288 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
2655 22:21:00.658734 iDelay=200, Bit 9, Center 87 (8 ~ 167) 160
2656 22:21:00.661816 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2657 22:21:00.668585 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
2658 22:21:00.671646 iDelay=200, Bit 12, Center 107 (32 ~ 183) 152
2659 22:21:00.675247 iDelay=200, Bit 13, Center 107 (32 ~ 183) 152
2660 22:21:00.678173 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
2661 22:21:00.684956 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2662 22:21:00.685042 ==
2663 22:21:00.688421 Dram Type= 6, Freq= 0, CH_0, rank 0
2664 22:21:00.691349 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2665 22:21:00.691430 ==
2666 22:21:00.691496 DQS Delay:
2667 22:21:00.695068 DQS0 = 0, DQS1 = 0
2668 22:21:00.695143 DQM Delay:
2669 22:21:00.698024 DQM0 = 112, DQM1 = 102
2670 22:21:00.698111 DQ Delay:
2671 22:21:00.701621 DQ0 =111, DQ1 =111, DQ2 =115, DQ3 =107
2672 22:21:00.705368 DQ4 =115, DQ5 =99, DQ6 =119, DQ7 =123
2673 22:21:00.708249 DQ8 =91, DQ9 =87, DQ10 =103, DQ11 =95
2674 22:21:00.711730 DQ12 =107, DQ13 =107, DQ14 =115, DQ15 =111
2675 22:21:00.711815
2676 22:21:00.711880
2677 22:21:00.711939 ==
2678 22:21:00.714730 Dram Type= 6, Freq= 0, CH_0, rank 0
2679 22:21:00.721556 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2680 22:21:00.721670 ==
2681 22:21:00.721751
2682 22:21:00.721823
2683 22:21:00.721887 TX Vref Scan disable
2684 22:21:00.725175 == TX Byte 0 ==
2685 22:21:00.728782 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2686 22:21:00.734976 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2687 22:21:00.735056 == TX Byte 1 ==
2688 22:21:00.738533 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2689 22:21:00.745561 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2690 22:21:00.745646 ==
2691 22:21:00.748474 Dram Type= 6, Freq= 0, CH_0, rank 0
2692 22:21:00.751813 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2693 22:21:00.751900 ==
2694 22:21:00.763369 TX Vref=22, minBit 0, minWin=26, winSum=418
2695 22:21:00.766807 TX Vref=24, minBit 1, minWin=26, winSum=424
2696 22:21:00.769793 TX Vref=26, minBit 3, minWin=26, winSum=430
2697 22:21:00.773485 TX Vref=28, minBit 0, minWin=27, winSum=436
2698 22:21:00.776639 TX Vref=30, minBit 3, minWin=26, winSum=432
2699 22:21:00.783186 TX Vref=32, minBit 2, minWin=26, winSum=427
2700 22:21:00.786941 [TxChooseVref] Worse bit 0, Min win 27, Win sum 436, Final Vref 28
2701 22:21:00.787041
2702 22:21:00.789744 Final TX Range 1 Vref 28
2703 22:21:00.789869
2704 22:21:00.789994 ==
2705 22:21:00.793363 Dram Type= 6, Freq= 0, CH_0, rank 0
2706 22:21:00.796368 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2707 22:21:00.796465 ==
2708 22:21:00.800090
2709 22:21:00.800173
2710 22:21:00.800239 TX Vref Scan disable
2711 22:21:00.803184 == TX Byte 0 ==
2712 22:21:00.806965 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2713 22:21:00.812778 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2714 22:21:00.812863 == TX Byte 1 ==
2715 22:21:00.816345 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2716 22:21:00.822979 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2717 22:21:00.823065
2718 22:21:00.823131 [DATLAT]
2719 22:21:00.823193 Freq=1200, CH0 RK0
2720 22:21:00.823258
2721 22:21:00.826034 DATLAT Default: 0xd
2722 22:21:00.829728 0, 0xFFFF, sum = 0
2723 22:21:00.829830 1, 0xFFFF, sum = 0
2724 22:21:00.832605 2, 0xFFFF, sum = 0
2725 22:21:00.832693 3, 0xFFFF, sum = 0
2726 22:21:00.836398 4, 0xFFFF, sum = 0
2727 22:21:00.836513 5, 0xFFFF, sum = 0
2728 22:21:00.839303 6, 0xFFFF, sum = 0
2729 22:21:00.839387 7, 0xFFFF, sum = 0
2730 22:21:00.842974 8, 0xFFFF, sum = 0
2731 22:21:00.843060 9, 0xFFFF, sum = 0
2732 22:21:00.846143 10, 0xFFFF, sum = 0
2733 22:21:00.846228 11, 0xFFFF, sum = 0
2734 22:21:00.849500 12, 0x0, sum = 1
2735 22:21:00.849583 13, 0x0, sum = 2
2736 22:21:00.853099 14, 0x0, sum = 3
2737 22:21:00.853201 15, 0x0, sum = 4
2738 22:21:00.856258 best_step = 13
2739 22:21:00.856364
2740 22:21:00.856460 ==
2741 22:21:00.859675 Dram Type= 6, Freq= 0, CH_0, rank 0
2742 22:21:00.862552 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2743 22:21:00.862660 ==
2744 22:21:00.862754 RX Vref Scan: 1
2745 22:21:00.865745
2746 22:21:00.865862 Set Vref Range= 32 -> 127
2747 22:21:00.865997
2748 22:21:00.869414 RX Vref 32 -> 127, step: 1
2749 22:21:00.869499
2750 22:21:00.872859 RX Delay -37 -> 252, step: 4
2751 22:21:00.872972
2752 22:21:00.875730 Set Vref, RX VrefLevel [Byte0]: 32
2753 22:21:00.879261 [Byte1]: 32
2754 22:21:00.879376
2755 22:21:00.882855 Set Vref, RX VrefLevel [Byte0]: 33
2756 22:21:00.886125 [Byte1]: 33
2757 22:21:00.889478
2758 22:21:00.889583 Set Vref, RX VrefLevel [Byte0]: 34
2759 22:21:00.893132 [Byte1]: 34
2760 22:21:00.897883
2761 22:21:00.897960 Set Vref, RX VrefLevel [Byte0]: 35
2762 22:21:00.900947 [Byte1]: 35
2763 22:21:00.905848
2764 22:21:00.905928 Set Vref, RX VrefLevel [Byte0]: 36
2765 22:21:00.909416 [Byte1]: 36
2766 22:21:00.914016
2767 22:21:00.914119 Set Vref, RX VrefLevel [Byte0]: 37
2768 22:21:00.920378 [Byte1]: 37
2769 22:21:00.920487
2770 22:21:00.923728 Set Vref, RX VrefLevel [Byte0]: 38
2771 22:21:00.927179 [Byte1]: 38
2772 22:21:00.927283
2773 22:21:00.930324 Set Vref, RX VrefLevel [Byte0]: 39
2774 22:21:00.933453 [Byte1]: 39
2775 22:21:00.937753
2776 22:21:00.937861 Set Vref, RX VrefLevel [Byte0]: 40
2777 22:21:00.940750 [Byte1]: 40
2778 22:21:00.945733
2779 22:21:00.945842 Set Vref, RX VrefLevel [Byte0]: 41
2780 22:21:00.948824 [Byte1]: 41
2781 22:21:00.953984
2782 22:21:00.954091 Set Vref, RX VrefLevel [Byte0]: 42
2783 22:21:00.957061 [Byte1]: 42
2784 22:21:00.961545
2785 22:21:00.961657 Set Vref, RX VrefLevel [Byte0]: 43
2786 22:21:00.965016 [Byte1]: 43
2787 22:21:00.969747
2788 22:21:00.969857 Set Vref, RX VrefLevel [Byte0]: 44
2789 22:21:00.972827 [Byte1]: 44
2790 22:21:00.977696
2791 22:21:00.977804 Set Vref, RX VrefLevel [Byte0]: 45
2792 22:21:00.981143 [Byte1]: 45
2793 22:21:00.985812
2794 22:21:00.985912 Set Vref, RX VrefLevel [Byte0]: 46
2795 22:21:00.989246 [Byte1]: 46
2796 22:21:00.993558
2797 22:21:00.993680 Set Vref, RX VrefLevel [Byte0]: 47
2798 22:21:00.997193 [Byte1]: 47
2799 22:21:01.001919
2800 22:21:01.002028 Set Vref, RX VrefLevel [Byte0]: 48
2801 22:21:01.004870 [Byte1]: 48
2802 22:21:01.010128
2803 22:21:01.010240 Set Vref, RX VrefLevel [Byte0]: 49
2804 22:21:01.012961 [Byte1]: 49
2805 22:21:01.017717
2806 22:21:01.017822 Set Vref, RX VrefLevel [Byte0]: 50
2807 22:21:01.020877 [Byte1]: 50
2808 22:21:01.025829
2809 22:21:01.025936 Set Vref, RX VrefLevel [Byte0]: 51
2810 22:21:01.029251 [Byte1]: 51
2811 22:21:01.033947
2812 22:21:01.034059 Set Vref, RX VrefLevel [Byte0]: 52
2813 22:21:01.036943 [Byte1]: 52
2814 22:21:01.041828
2815 22:21:01.041933 Set Vref, RX VrefLevel [Byte0]: 53
2816 22:21:01.044782 [Byte1]: 53
2817 22:21:01.049754
2818 22:21:01.049868 Set Vref, RX VrefLevel [Byte0]: 54
2819 22:21:01.052824 [Byte1]: 54
2820 22:21:01.057740
2821 22:21:01.057819 Set Vref, RX VrefLevel [Byte0]: 55
2822 22:21:01.061329 [Byte1]: 55
2823 22:21:01.065554
2824 22:21:01.065661 Set Vref, RX VrefLevel [Byte0]: 56
2825 22:21:01.068937 [Byte1]: 56
2826 22:21:01.073587
2827 22:21:01.073695 Set Vref, RX VrefLevel [Byte0]: 57
2828 22:21:01.077355 [Byte1]: 57
2829 22:21:01.081599
2830 22:21:01.081716 Set Vref, RX VrefLevel [Byte0]: 58
2831 22:21:01.085366 [Byte1]: 58
2832 22:21:01.089868
2833 22:21:01.089976 Set Vref, RX VrefLevel [Byte0]: 59
2834 22:21:01.093262 [Byte1]: 59
2835 22:21:01.097912
2836 22:21:01.098022 Set Vref, RX VrefLevel [Byte0]: 60
2837 22:21:01.100960 [Byte1]: 60
2838 22:21:01.105698
2839 22:21:01.105804 Set Vref, RX VrefLevel [Byte0]: 61
2840 22:21:01.109303 [Byte1]: 61
2841 22:21:01.113542
2842 22:21:01.113649 Set Vref, RX VrefLevel [Byte0]: 62
2843 22:21:01.117326 [Byte1]: 62
2844 22:21:01.122075
2845 22:21:01.122184 Set Vref, RX VrefLevel [Byte0]: 63
2846 22:21:01.125276 [Byte1]: 63
2847 22:21:01.130047
2848 22:21:01.130161 Set Vref, RX VrefLevel [Byte0]: 64
2849 22:21:01.133042 [Byte1]: 64
2850 22:21:01.137564
2851 22:21:01.137644 Set Vref, RX VrefLevel [Byte0]: 65
2852 22:21:01.141134 [Byte1]: 65
2853 22:21:01.145904
2854 22:21:01.145996 Set Vref, RX VrefLevel [Byte0]: 66
2855 22:21:01.148992 [Byte1]: 66
2856 22:21:01.154000
2857 22:21:01.154089 Set Vref, RX VrefLevel [Byte0]: 67
2858 22:21:01.156992 [Byte1]: 67
2859 22:21:01.162015
2860 22:21:01.162102 Set Vref, RX VrefLevel [Byte0]: 68
2861 22:21:01.165031 [Byte1]: 68
2862 22:21:01.170010
2863 22:21:01.170096 Set Vref, RX VrefLevel [Byte0]: 69
2864 22:21:01.173040 [Byte1]: 69
2865 22:21:01.177651
2866 22:21:01.177733 Set Vref, RX VrefLevel [Byte0]: 70
2867 22:21:01.181232 [Byte1]: 70
2868 22:21:01.185725
2869 22:21:01.185802 Set Vref, RX VrefLevel [Byte0]: 71
2870 22:21:01.189370 [Byte1]: 71
2871 22:21:01.193510
2872 22:21:01.193589 Set Vref, RX VrefLevel [Byte0]: 72
2873 22:21:01.197007 [Byte1]: 72
2874 22:21:01.201982
2875 22:21:01.202067 Set Vref, RX VrefLevel [Byte0]: 73
2876 22:21:01.204864 [Byte1]: 73
2877 22:21:01.210033
2878 22:21:01.210126 Set Vref, RX VrefLevel [Byte0]: 74
2879 22:21:01.212919 [Byte1]: 74
2880 22:21:01.217878
2881 22:21:01.217957 Final RX Vref Byte 0 = 60 to rank0
2882 22:21:01.220993 Final RX Vref Byte 1 = 48 to rank0
2883 22:21:01.224514 Final RX Vref Byte 0 = 60 to rank1
2884 22:21:01.227567 Final RX Vref Byte 1 = 48 to rank1==
2885 22:21:01.231240 Dram Type= 6, Freq= 0, CH_0, rank 0
2886 22:21:01.237969 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2887 22:21:01.238050 ==
2888 22:21:01.238118 DQS Delay:
2889 22:21:01.238179 DQS0 = 0, DQS1 = 0
2890 22:21:01.240835 DQM Delay:
2891 22:21:01.240954 DQM0 = 111, DQM1 = 98
2892 22:21:01.244185 DQ Delay:
2893 22:21:01.247598 DQ0 =112, DQ1 =110, DQ2 =110, DQ3 =108
2894 22:21:01.250988 DQ4 =112, DQ5 =104, DQ6 =118, DQ7 =120
2895 22:21:01.253969 DQ8 =90, DQ9 =82, DQ10 =100, DQ11 =92
2896 22:21:01.257741 DQ12 =104, DQ13 =104, DQ14 =112, DQ15 =106
2897 22:21:01.257820
2898 22:21:01.257884
2899 22:21:01.264105 [DQSOSCAuto] RK0, (LSB)MR18= 0xfcfc, (MSB)MR19= 0x303, tDQSOscB0 = 411 ps tDQSOscB1 = 411 ps
2900 22:21:01.267506 CH0 RK0: MR19=303, MR18=FCFC
2901 22:21:01.273717 CH0_RK0: MR19=0x303, MR18=0xFCFC, DQSOSC=411, MR23=63, INC=38, DEC=25
2902 22:21:01.273797
2903 22:21:01.277397 ----->DramcWriteLeveling(PI) begin...
2904 22:21:01.277475 ==
2905 22:21:01.280473 Dram Type= 6, Freq= 0, CH_0, rank 1
2906 22:21:01.287452 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2907 22:21:01.287569 ==
2908 22:21:01.290506 Write leveling (Byte 0): 31 => 31
2909 22:21:01.290611 Write leveling (Byte 1): 31 => 31
2910 22:21:01.293604 DramcWriteLeveling(PI) end<-----
2911 22:21:01.293711
2912 22:21:01.293818 ==
2913 22:21:01.297311 Dram Type= 6, Freq= 0, CH_0, rank 1
2914 22:21:01.303888 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2915 22:21:01.303979 ==
2916 22:21:01.307470 [Gating] SW mode calibration
2917 22:21:01.314082 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2918 22:21:01.316793 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2919 22:21:01.323650 0 15 0 | B1->B0 | 2727 3434 | 1 1 | (0 0) (1 1)
2920 22:21:01.327207 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2921 22:21:01.330225 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2922 22:21:01.336968 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2923 22:21:01.340170 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2924 22:21:01.343309 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2925 22:21:01.349707 0 15 24 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 0)
2926 22:21:01.353515 0 15 28 | B1->B0 | 3434 2525 | 0 1 | (0 0) (1 0)
2927 22:21:01.356891 1 0 0 | B1->B0 | 2525 2323 | 0 0 | (1 0) (0 0)
2928 22:21:01.363257 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2929 22:21:01.367075 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2930 22:21:01.370104 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2931 22:21:01.376922 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2932 22:21:01.379952 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2933 22:21:01.383148 1 0 24 | B1->B0 | 2323 2928 | 0 1 | (0 0) (0 0)
2934 22:21:01.389850 1 0 28 | B1->B0 | 2323 3e3e | 0 0 | (0 0) (1 1)
2935 22:21:01.393365 1 1 0 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
2936 22:21:01.396289 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2937 22:21:01.403069 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2938 22:21:01.406004 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2939 22:21:01.409704 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2940 22:21:01.416643 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2941 22:21:01.419271 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2942 22:21:01.422483 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2943 22:21:01.429206 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2944 22:21:01.432654 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2945 22:21:01.435646 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2946 22:21:01.442321 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2947 22:21:01.445379 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2948 22:21:01.449109 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2949 22:21:01.455875 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2950 22:21:01.459267 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2951 22:21:01.462501 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2952 22:21:01.468851 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2953 22:21:01.472140 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2954 22:21:01.475782 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2955 22:21:01.482018 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2956 22:21:01.485162 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2957 22:21:01.488756 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2958 22:21:01.495534 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2959 22:21:01.498942 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2960 22:21:01.501786 Total UI for P1: 0, mck2ui 16
2961 22:21:01.504958 best dqsien dly found for B0: ( 1, 3, 28)
2962 22:21:01.508497 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2963 22:21:01.511587 Total UI for P1: 0, mck2ui 16
2964 22:21:01.515231 best dqsien dly found for B1: ( 1, 4, 0)
2965 22:21:01.518281 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2966 22:21:01.521951 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2967 22:21:01.522037
2968 22:21:01.524945 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2969 22:21:01.531339 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2970 22:21:01.531458 [Gating] SW calibration Done
2971 22:21:01.531563 ==
2972 22:21:01.534725 Dram Type= 6, Freq= 0, CH_0, rank 1
2973 22:21:01.541544 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2974 22:21:01.541631 ==
2975 22:21:01.541701 RX Vref Scan: 0
2976 22:21:01.541797
2977 22:21:01.545153 RX Vref 0 -> 0, step: 1
2978 22:21:01.545239
2979 22:21:01.548309 RX Delay -40 -> 252, step: 8
2980 22:21:01.551337 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2981 22:21:01.555080 iDelay=200, Bit 1, Center 111 (32 ~ 191) 160
2982 22:21:01.558138 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2983 22:21:01.564935 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2984 22:21:01.568425 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2985 22:21:01.571766 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2986 22:21:01.574569 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
2987 22:21:01.577958 iDelay=200, Bit 7, Center 119 (40 ~ 199) 160
2988 22:21:01.584799 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
2989 22:21:01.587885 iDelay=200, Bit 9, Center 83 (8 ~ 159) 152
2990 22:21:01.591760 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2991 22:21:01.594752 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
2992 22:21:01.597888 iDelay=200, Bit 12, Center 107 (32 ~ 183) 152
2993 22:21:01.604407 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2994 22:21:01.607921 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
2995 22:21:01.610921 iDelay=200, Bit 15, Center 107 (32 ~ 183) 152
2996 22:21:01.611006 ==
2997 22:21:01.614436 Dram Type= 6, Freq= 0, CH_0, rank 1
2998 22:21:01.617541 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2999 22:21:01.617655 ==
3000 22:21:01.621211 DQS Delay:
3001 22:21:01.621296 DQS0 = 0, DQS1 = 0
3002 22:21:01.624141 DQM Delay:
3003 22:21:01.624226 DQM0 = 112, DQM1 = 101
3004 22:21:01.624294 DQ Delay:
3005 22:21:01.630985 DQ0 =115, DQ1 =111, DQ2 =111, DQ3 =107
3006 22:21:01.633975 DQ4 =115, DQ5 =103, DQ6 =119, DQ7 =119
3007 22:21:01.637424 DQ8 =91, DQ9 =83, DQ10 =103, DQ11 =95
3008 22:21:01.640831 DQ12 =107, DQ13 =111, DQ14 =111, DQ15 =107
3009 22:21:01.640917
3010 22:21:01.640986
3011 22:21:01.641049 ==
3012 22:21:01.644108 Dram Type= 6, Freq= 0, CH_0, rank 1
3013 22:21:01.647075 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3014 22:21:01.647162 ==
3015 22:21:01.647235
3016 22:21:01.647330
3017 22:21:01.650527 TX Vref Scan disable
3018 22:21:01.653550 == TX Byte 0 ==
3019 22:21:01.657221 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
3020 22:21:01.660311 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
3021 22:21:01.663459 == TX Byte 1 ==
3022 22:21:01.667181 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3023 22:21:01.670246 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3024 22:21:01.670354 ==
3025 22:21:01.673334 Dram Type= 6, Freq= 0, CH_0, rank 1
3026 22:21:01.680134 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3027 22:21:01.680221 ==
3028 22:21:01.690716 TX Vref=22, minBit 1, minWin=26, winSum=430
3029 22:21:01.693774 TX Vref=24, minBit 1, minWin=26, winSum=429
3030 22:21:01.697511 TX Vref=26, minBit 1, minWin=26, winSum=437
3031 22:21:01.700453 TX Vref=28, minBit 1, minWin=27, winSum=441
3032 22:21:01.703891 TX Vref=30, minBit 2, minWin=27, winSum=443
3033 22:21:01.710148 TX Vref=32, minBit 2, minWin=27, winSum=440
3034 22:21:01.713617 [TxChooseVref] Worse bit 2, Min win 27, Win sum 443, Final Vref 30
3035 22:21:01.713701
3036 22:21:01.717180 Final TX Range 1 Vref 30
3037 22:21:01.717283
3038 22:21:01.717355 ==
3039 22:21:01.720192 Dram Type= 6, Freq= 0, CH_0, rank 1
3040 22:21:01.723269 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3041 22:21:01.726887 ==
3042 22:21:01.726964
3043 22:21:01.727029
3044 22:21:01.727092 TX Vref Scan disable
3045 22:21:01.729989 == TX Byte 0 ==
3046 22:21:01.733556 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
3047 22:21:01.740352 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
3048 22:21:01.740439 == TX Byte 1 ==
3049 22:21:01.743322 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3050 22:21:01.750216 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3051 22:21:01.750304
3052 22:21:01.750373 [DATLAT]
3053 22:21:01.750437 Freq=1200, CH0 RK1
3054 22:21:01.750500
3055 22:21:01.753244 DATLAT Default: 0xd
3056 22:21:01.756631 0, 0xFFFF, sum = 0
3057 22:21:01.756763 1, 0xFFFF, sum = 0
3058 22:21:01.759678 2, 0xFFFF, sum = 0
3059 22:21:01.759768 3, 0xFFFF, sum = 0
3060 22:21:01.763364 4, 0xFFFF, sum = 0
3061 22:21:01.763451 5, 0xFFFF, sum = 0
3062 22:21:01.766428 6, 0xFFFF, sum = 0
3063 22:21:01.766548 7, 0xFFFF, sum = 0
3064 22:21:01.770127 8, 0xFFFF, sum = 0
3065 22:21:01.770207 9, 0xFFFF, sum = 0
3066 22:21:01.773225 10, 0xFFFF, sum = 0
3067 22:21:01.773301 11, 0xFFFF, sum = 0
3068 22:21:01.776484 12, 0x0, sum = 1
3069 22:21:01.776561 13, 0x0, sum = 2
3070 22:21:01.780106 14, 0x0, sum = 3
3071 22:21:01.780191 15, 0x0, sum = 4
3072 22:21:01.783196 best_step = 13
3073 22:21:01.783280
3074 22:21:01.783377 ==
3075 22:21:01.786125 Dram Type= 6, Freq= 0, CH_0, rank 1
3076 22:21:01.789568 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3077 22:21:01.789679 ==
3078 22:21:01.789778 RX Vref Scan: 0
3079 22:21:01.792977
3080 22:21:01.793052 RX Vref 0 -> 0, step: 1
3081 22:21:01.793116
3082 22:21:01.796217 RX Delay -37 -> 252, step: 4
3083 22:21:01.802786 iDelay=195, Bit 0, Center 108 (39 ~ 178) 140
3084 22:21:01.806456 iDelay=195, Bit 1, Center 112 (39 ~ 186) 148
3085 22:21:01.809479 iDelay=195, Bit 2, Center 108 (39 ~ 178) 140
3086 22:21:01.813103 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3087 22:21:01.816261 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3088 22:21:01.822568 iDelay=195, Bit 5, Center 100 (35 ~ 166) 132
3089 22:21:01.826152 iDelay=195, Bit 6, Center 120 (47 ~ 194) 148
3090 22:21:01.829165 iDelay=195, Bit 7, Center 118 (43 ~ 194) 152
3091 22:21:01.833080 iDelay=195, Bit 8, Center 90 (19 ~ 162) 144
3092 22:21:01.835836 iDelay=195, Bit 9, Center 82 (11 ~ 154) 144
3093 22:21:01.842740 iDelay=195, Bit 10, Center 102 (31 ~ 174) 144
3094 22:21:01.845926 iDelay=195, Bit 11, Center 90 (23 ~ 158) 136
3095 22:21:01.849460 iDelay=195, Bit 12, Center 108 (39 ~ 178) 140
3096 22:21:01.852402 iDelay=195, Bit 13, Center 108 (39 ~ 178) 140
3097 22:21:01.855877 iDelay=195, Bit 14, Center 112 (47 ~ 178) 132
3098 22:21:01.862295 iDelay=195, Bit 15, Center 108 (39 ~ 178) 140
3099 22:21:01.862381 ==
3100 22:21:01.865595 Dram Type= 6, Freq= 0, CH_0, rank 1
3101 22:21:01.869039 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3102 22:21:01.869154 ==
3103 22:21:01.869252 DQS Delay:
3104 22:21:01.872123 DQS0 = 0, DQS1 = 0
3105 22:21:01.872209 DQM Delay:
3106 22:21:01.875944 DQM0 = 110, DQM1 = 100
3107 22:21:01.876029 DQ Delay:
3108 22:21:01.878950 DQ0 =108, DQ1 =112, DQ2 =108, DQ3 =108
3109 22:21:01.882610 DQ4 =112, DQ5 =100, DQ6 =120, DQ7 =118
3110 22:21:01.885762 DQ8 =90, DQ9 =82, DQ10 =102, DQ11 =90
3111 22:21:01.888809 DQ12 =108, DQ13 =108, DQ14 =112, DQ15 =108
3112 22:21:01.888895
3113 22:21:01.888962
3114 22:21:01.899203 [DQSOSCAuto] RK1, (LSB)MR18= 0x12fa, (MSB)MR19= 0x403, tDQSOscB0 = 412 ps tDQSOscB1 = 403 ps
3115 22:21:01.902437 CH0 RK1: MR19=403, MR18=12FA
3116 22:21:01.908814 CH0_RK1: MR19=0x403, MR18=0x12FA, DQSOSC=403, MR23=63, INC=40, DEC=26
3117 22:21:01.908901 [RxdqsGatingPostProcess] freq 1200
3118 22:21:01.915265 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3119 22:21:01.918954 best DQS0 dly(2T, 0.5T) = (0, 12)
3120 22:21:01.922164 best DQS1 dly(2T, 0.5T) = (0, 12)
3121 22:21:01.925745 best DQS0 P1 dly(2T, 0.5T) = (1, 0)
3122 22:21:01.928788 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3123 22:21:01.931806 best DQS0 dly(2T, 0.5T) = (0, 11)
3124 22:21:01.935480 best DQS1 dly(2T, 0.5T) = (0, 12)
3125 22:21:01.938936 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3126 22:21:01.942242 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3127 22:21:01.945714 Pre-setting of DQS Precalculation
3128 22:21:01.948836 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3129 22:21:01.948923 ==
3130 22:21:01.951849 Dram Type= 6, Freq= 0, CH_1, rank 0
3131 22:21:01.955351 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3132 22:21:01.955463 ==
3133 22:21:01.961969 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3134 22:21:01.968409 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3135 22:21:01.976454 [CA 0] Center 37 (8~67) winsize 60
3136 22:21:01.979644 [CA 1] Center 37 (7~68) winsize 62
3137 22:21:01.983272 [CA 2] Center 34 (5~64) winsize 60
3138 22:21:01.986490 [CA 3] Center 34 (4~64) winsize 61
3139 22:21:01.989610 [CA 4] Center 34 (4~64) winsize 61
3140 22:21:01.992629 [CA 5] Center 33 (3~63) winsize 61
3141 22:21:01.992712
3142 22:21:01.996477 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3143 22:21:01.996560
3144 22:21:01.999494 [CATrainingPosCal] consider 1 rank data
3145 22:21:02.002587 u2DelayCellTimex100 = 270/100 ps
3146 22:21:02.006201 CA0 delay=37 (8~67),Diff = 4 PI (19 cell)
3147 22:21:02.012945 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3148 22:21:02.016191 CA2 delay=34 (5~64),Diff = 1 PI (4 cell)
3149 22:21:02.019662 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3150 22:21:02.022567 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3151 22:21:02.026254 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3152 22:21:02.026365
3153 22:21:02.029320 CA PerBit enable=1, Macro0, CA PI delay=33
3154 22:21:02.029442
3155 22:21:02.032484 [CBTSetCACLKResult] CA Dly = 33
3156 22:21:02.032568 CS Dly: 6 (0~37)
3157 22:21:02.035845 ==
3158 22:21:02.039564 Dram Type= 6, Freq= 0, CH_1, rank 1
3159 22:21:02.042743 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3160 22:21:02.042875 ==
3161 22:21:02.045956 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3162 22:21:02.052744 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3163 22:21:02.061875 [CA 0] Center 38 (8~68) winsize 61
3164 22:21:02.065465 [CA 1] Center 38 (8~68) winsize 61
3165 22:21:02.068347 [CA 2] Center 34 (4~65) winsize 62
3166 22:21:02.071967 [CA 3] Center 33 (3~64) winsize 62
3167 22:21:02.075363 [CA 4] Center 34 (4~65) winsize 62
3168 22:21:02.078874 [CA 5] Center 33 (3~64) winsize 62
3169 22:21:02.078960
3170 22:21:02.082279 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3171 22:21:02.082364
3172 22:21:02.085284 [CATrainingPosCal] consider 2 rank data
3173 22:21:02.088260 u2DelayCellTimex100 = 270/100 ps
3174 22:21:02.092022 CA0 delay=37 (8~67),Diff = 4 PI (19 cell)
3175 22:21:02.098670 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3176 22:21:02.101879 CA2 delay=34 (5~64),Diff = 1 PI (4 cell)
3177 22:21:02.104974 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3178 22:21:02.109072 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3179 22:21:02.111803 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3180 22:21:02.111895
3181 22:21:02.115187 CA PerBit enable=1, Macro0, CA PI delay=33
3182 22:21:02.115273
3183 22:21:02.118147 [CBTSetCACLKResult] CA Dly = 33
3184 22:21:02.118253 CS Dly: 7 (0~40)
3185 22:21:02.118359
3186 22:21:02.121547 ----->DramcWriteLeveling(PI) begin...
3187 22:21:02.124866 ==
3188 22:21:02.128429 Dram Type= 6, Freq= 0, CH_1, rank 0
3189 22:21:02.131553 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3190 22:21:02.131666 ==
3191 22:21:02.134699 Write leveling (Byte 0): 24 => 24
3192 22:21:02.138284 Write leveling (Byte 1): 29 => 29
3193 22:21:02.141883 DramcWriteLeveling(PI) end<-----
3194 22:21:02.142007
3195 22:21:02.142119 ==
3196 22:21:02.144940 Dram Type= 6, Freq= 0, CH_1, rank 0
3197 22:21:02.148473 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3198 22:21:02.148589 ==
3199 22:21:02.151427 [Gating] SW mode calibration
3200 22:21:02.158585 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3201 22:21:02.165122 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3202 22:21:02.168169 0 15 0 | B1->B0 | 2b2b 2d2d | 0 1 | (0 0) (0 0)
3203 22:21:02.171767 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3204 22:21:02.178054 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3205 22:21:02.181718 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3206 22:21:02.185124 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3207 22:21:02.188093 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3208 22:21:02.195161 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3209 22:21:02.198266 0 15 28 | B1->B0 | 3030 3434 | 0 0 | (0 1) (0 1)
3210 22:21:02.201889 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3211 22:21:02.208107 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3212 22:21:02.211864 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3213 22:21:02.214834 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3214 22:21:02.221577 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3215 22:21:02.224981 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3216 22:21:02.228460 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3217 22:21:02.235321 1 0 28 | B1->B0 | 3939 3535 | 0 1 | (0 0) (0 0)
3218 22:21:02.238411 1 1 0 | B1->B0 | 4444 4545 | 0 0 | (0 0) (0 0)
3219 22:21:02.241483 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3220 22:21:02.248049 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3221 22:21:02.251314 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3222 22:21:02.255267 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3223 22:21:02.261544 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3224 22:21:02.264587 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3225 22:21:02.268092 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3226 22:21:02.274388 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3227 22:21:02.278022 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3228 22:21:02.281031 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3229 22:21:02.287923 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3230 22:21:02.290748 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3231 22:21:02.294184 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3232 22:21:02.300758 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3233 22:21:02.304502 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3234 22:21:02.307503 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3235 22:21:02.314362 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3236 22:21:02.317492 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3237 22:21:02.321250 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3238 22:21:02.324325 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3239 22:21:02.331205 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3240 22:21:02.334568 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3241 22:21:02.337419 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3242 22:21:02.344155 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3243 22:21:02.347806 Total UI for P1: 0, mck2ui 16
3244 22:21:02.351259 best dqsien dly found for B1: ( 1, 3, 28)
3245 22:21:02.354393 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3246 22:21:02.357472 Total UI for P1: 0, mck2ui 16
3247 22:21:02.361174 best dqsien dly found for B0: ( 1, 3, 30)
3248 22:21:02.364087 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
3249 22:21:02.367745 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3250 22:21:02.367863
3251 22:21:02.371163 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
3252 22:21:02.374146 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3253 22:21:02.377261 [Gating] SW calibration Done
3254 22:21:02.377347 ==
3255 22:21:02.380958 Dram Type= 6, Freq= 0, CH_1, rank 0
3256 22:21:02.387577 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3257 22:21:02.387676 ==
3258 22:21:02.387772 RX Vref Scan: 0
3259 22:21:02.387870
3260 22:21:02.390500 RX Vref 0 -> 0, step: 1
3261 22:21:02.390578
3262 22:21:02.394287 RX Delay -40 -> 252, step: 8
3263 22:21:02.397807 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3264 22:21:02.400399 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3265 22:21:02.403799 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3266 22:21:02.410447 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3267 22:21:02.413456 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3268 22:21:02.417228 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3269 22:21:02.420200 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3270 22:21:02.423995 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3271 22:21:02.430246 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3272 22:21:02.433787 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3273 22:21:02.436746 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
3274 22:21:02.440386 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3275 22:21:02.443508 iDelay=200, Bit 12, Center 115 (40 ~ 191) 152
3276 22:21:02.450056 iDelay=200, Bit 13, Center 115 (40 ~ 191) 152
3277 22:21:02.453657 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3278 22:21:02.456544 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3279 22:21:02.456629 ==
3280 22:21:02.460258 Dram Type= 6, Freq= 0, CH_1, rank 0
3281 22:21:02.463368 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3282 22:21:02.463453 ==
3283 22:21:02.466798 DQS Delay:
3284 22:21:02.466918 DQS0 = 0, DQS1 = 0
3285 22:21:02.469883 DQM Delay:
3286 22:21:02.469969 DQM0 = 115, DQM1 = 106
3287 22:21:02.472984 DQ Delay:
3288 22:21:02.476418 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =115
3289 22:21:02.479900 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =115
3290 22:21:02.483371 DQ8 =95, DQ9 =95, DQ10 =103, DQ11 =103
3291 22:21:02.486505 DQ12 =115, DQ13 =115, DQ14 =111, DQ15 =111
3292 22:21:02.486590
3293 22:21:02.486658
3294 22:21:02.486720 ==
3295 22:21:02.489784 Dram Type= 6, Freq= 0, CH_1, rank 0
3296 22:21:02.493243 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3297 22:21:02.493328 ==
3298 22:21:02.493396
3299 22:21:02.493458
3300 22:21:02.496471 TX Vref Scan disable
3301 22:21:02.499546 == TX Byte 0 ==
3302 22:21:02.503011 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3303 22:21:02.506456 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3304 22:21:02.509385 == TX Byte 1 ==
3305 22:21:02.512835 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3306 22:21:02.515891 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3307 22:21:02.515976 ==
3308 22:21:02.519790 Dram Type= 6, Freq= 0, CH_1, rank 0
3309 22:21:02.525829 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3310 22:21:02.525915 ==
3311 22:21:02.536457 TX Vref=22, minBit 1, minWin=24, winSum=405
3312 22:21:02.540106 TX Vref=24, minBit 1, minWin=24, winSum=407
3313 22:21:02.543010 TX Vref=26, minBit 4, minWin=24, winSum=413
3314 22:21:02.546428 TX Vref=28, minBit 1, minWin=25, winSum=419
3315 22:21:02.549953 TX Vref=30, minBit 1, minWin=25, winSum=417
3316 22:21:02.556442 TX Vref=32, minBit 1, minWin=25, winSum=417
3317 22:21:02.560105 [TxChooseVref] Worse bit 1, Min win 25, Win sum 419, Final Vref 28
3318 22:21:02.560221
3319 22:21:02.563253 Final TX Range 1 Vref 28
3320 22:21:02.563359
3321 22:21:02.563464 ==
3322 22:21:02.566387 Dram Type= 6, Freq= 0, CH_1, rank 0
3323 22:21:02.569463 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3324 22:21:02.573080 ==
3325 22:21:02.573158
3326 22:21:02.573225
3327 22:21:02.573286 TX Vref Scan disable
3328 22:21:02.576129 == TX Byte 0 ==
3329 22:21:02.579863 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3330 22:21:02.586220 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3331 22:21:02.586338 == TX Byte 1 ==
3332 22:21:02.589543 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3333 22:21:02.596755 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3334 22:21:02.596865
3335 22:21:02.596960 [DATLAT]
3336 22:21:02.597064 Freq=1200, CH1 RK0
3337 22:21:02.597158
3338 22:21:02.599728 DATLAT Default: 0xd
3339 22:21:02.599840 0, 0xFFFF, sum = 0
3340 22:21:02.602534 1, 0xFFFF, sum = 0
3341 22:21:02.606004 2, 0xFFFF, sum = 0
3342 22:21:02.606114 3, 0xFFFF, sum = 0
3343 22:21:02.609392 4, 0xFFFF, sum = 0
3344 22:21:02.609502 5, 0xFFFF, sum = 0
3345 22:21:02.613049 6, 0xFFFF, sum = 0
3346 22:21:02.613157 7, 0xFFFF, sum = 0
3347 22:21:02.615805 8, 0xFFFF, sum = 0
3348 22:21:02.615918 9, 0xFFFF, sum = 0
3349 22:21:02.619408 10, 0xFFFF, sum = 0
3350 22:21:02.619525 11, 0xFFFF, sum = 0
3351 22:21:02.622479 12, 0x0, sum = 1
3352 22:21:02.622593 13, 0x0, sum = 2
3353 22:21:02.626276 14, 0x0, sum = 3
3354 22:21:02.626385 15, 0x0, sum = 4
3355 22:21:02.629364 best_step = 13
3356 22:21:02.629465
3357 22:21:02.629568 ==
3358 22:21:02.632478 Dram Type= 6, Freq= 0, CH_1, rank 0
3359 22:21:02.635532 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3360 22:21:02.635638 ==
3361 22:21:02.639299 RX Vref Scan: 1
3362 22:21:02.639405
3363 22:21:02.639501 Set Vref Range= 32 -> 127
3364 22:21:02.639590
3365 22:21:02.642372 RX Vref 32 -> 127, step: 1
3366 22:21:02.642471
3367 22:21:02.645918 RX Delay -21 -> 252, step: 4
3368 22:21:02.646016
3369 22:21:02.648824 Set Vref, RX VrefLevel [Byte0]: 32
3370 22:21:02.652146 [Byte1]: 32
3371 22:21:02.652247
3372 22:21:02.655594 Set Vref, RX VrefLevel [Byte0]: 33
3373 22:21:02.659091 [Byte1]: 33
3374 22:21:02.662919
3375 22:21:02.663021 Set Vref, RX VrefLevel [Byte0]: 34
3376 22:21:02.665913 [Byte1]: 34
3377 22:21:02.670774
3378 22:21:02.670895 Set Vref, RX VrefLevel [Byte0]: 35
3379 22:21:02.673801 [Byte1]: 35
3380 22:21:02.678534
3381 22:21:02.678644 Set Vref, RX VrefLevel [Byte0]: 36
3382 22:21:02.682202 [Byte1]: 36
3383 22:21:02.686527
3384 22:21:02.686627 Set Vref, RX VrefLevel [Byte0]: 37
3385 22:21:02.690088 [Byte1]: 37
3386 22:21:02.694740
3387 22:21:02.694850 Set Vref, RX VrefLevel [Byte0]: 38
3388 22:21:02.697566 [Byte1]: 38
3389 22:21:02.702265
3390 22:21:02.705883 Set Vref, RX VrefLevel [Byte0]: 39
3391 22:21:02.705999 [Byte1]: 39
3392 22:21:02.710746
3393 22:21:02.710862 Set Vref, RX VrefLevel [Byte0]: 40
3394 22:21:02.713621 [Byte1]: 40
3395 22:21:02.718396
3396 22:21:02.718503 Set Vref, RX VrefLevel [Byte0]: 41
3397 22:21:02.721309 [Byte1]: 41
3398 22:21:02.725962
3399 22:21:02.726070 Set Vref, RX VrefLevel [Byte0]: 42
3400 22:21:02.729895 [Byte1]: 42
3401 22:21:02.733981
3402 22:21:02.734062 Set Vref, RX VrefLevel [Byte0]: 43
3403 22:21:02.737731 [Byte1]: 43
3404 22:21:02.742123
3405 22:21:02.742222 Set Vref, RX VrefLevel [Byte0]: 44
3406 22:21:02.745269 [Byte1]: 44
3407 22:21:02.750318
3408 22:21:02.750422 Set Vref, RX VrefLevel [Byte0]: 45
3409 22:21:02.753000 [Byte1]: 45
3410 22:21:02.757740
3411 22:21:02.757842 Set Vref, RX VrefLevel [Byte0]: 46
3412 22:21:02.761263 [Byte1]: 46
3413 22:21:02.765589
3414 22:21:02.765690 Set Vref, RX VrefLevel [Byte0]: 47
3415 22:21:02.769154 [Byte1]: 47
3416 22:21:02.773938
3417 22:21:02.774042 Set Vref, RX VrefLevel [Byte0]: 48
3418 22:21:02.776985 [Byte1]: 48
3419 22:21:02.781813
3420 22:21:02.781914 Set Vref, RX VrefLevel [Byte0]: 49
3421 22:21:02.784902 [Byte1]: 49
3422 22:21:02.789866
3423 22:21:02.789965 Set Vref, RX VrefLevel [Byte0]: 50
3424 22:21:02.792843 [Byte1]: 50
3425 22:21:02.797280
3426 22:21:02.797383 Set Vref, RX VrefLevel [Byte0]: 51
3427 22:21:02.803733 [Byte1]: 51
3428 22:21:02.803840
3429 22:21:02.807439 Set Vref, RX VrefLevel [Byte0]: 52
3430 22:21:02.810342 [Byte1]: 52
3431 22:21:02.810444
3432 22:21:02.814039 Set Vref, RX VrefLevel [Byte0]: 53
3433 22:21:02.817061 [Byte1]: 53
3434 22:21:02.821289
3435 22:21:02.821395 Set Vref, RX VrefLevel [Byte0]: 54
3436 22:21:02.824367 [Byte1]: 54
3437 22:21:02.828969
3438 22:21:02.829076 Set Vref, RX VrefLevel [Byte0]: 55
3439 22:21:02.832412 [Byte1]: 55
3440 22:21:02.836857
3441 22:21:02.836965 Set Vref, RX VrefLevel [Byte0]: 56
3442 22:21:02.840501 [Byte1]: 56
3443 22:21:02.844929
3444 22:21:02.845034 Set Vref, RX VrefLevel [Byte0]: 57
3445 22:21:02.848597 [Byte1]: 57
3446 22:21:02.852965
3447 22:21:02.853078 Set Vref, RX VrefLevel [Byte0]: 58
3448 22:21:02.856568 [Byte1]: 58
3449 22:21:02.861103
3450 22:21:02.861213 Set Vref, RX VrefLevel [Byte0]: 59
3451 22:21:02.863924 [Byte1]: 59
3452 22:21:02.868944
3453 22:21:02.869056 Set Vref, RX VrefLevel [Byte0]: 60
3454 22:21:02.871898 [Byte1]: 60
3455 22:21:02.876425
3456 22:21:02.876513 Set Vref, RX VrefLevel [Byte0]: 61
3457 22:21:02.880081 [Byte1]: 61
3458 22:21:02.884821
3459 22:21:02.884927 Set Vref, RX VrefLevel [Byte0]: 62
3460 22:21:02.887834 [Byte1]: 62
3461 22:21:02.892827
3462 22:21:02.892934 Set Vref, RX VrefLevel [Byte0]: 63
3463 22:21:02.895907 [Byte1]: 63
3464 22:21:02.900506
3465 22:21:02.900586 Set Vref, RX VrefLevel [Byte0]: 64
3466 22:21:02.903711 [Byte1]: 64
3467 22:21:02.908397
3468 22:21:02.908483 Set Vref, RX VrefLevel [Byte0]: 65
3469 22:21:02.911536 [Byte1]: 65
3470 22:21:02.916061
3471 22:21:02.916167 Set Vref, RX VrefLevel [Byte0]: 66
3472 22:21:02.919671 [Byte1]: 66
3473 22:21:02.923951
3474 22:21:02.924079 Set Vref, RX VrefLevel [Byte0]: 67
3475 22:21:02.927442 [Byte1]: 67
3476 22:21:02.932181
3477 22:21:02.932298 Set Vref, RX VrefLevel [Byte0]: 68
3478 22:21:02.935586 [Byte1]: 68
3479 22:21:02.939901
3480 22:21:02.940008 Set Vref, RX VrefLevel [Byte0]: 69
3481 22:21:02.943702 [Byte1]: 69
3482 22:21:02.947937
3483 22:21:02.948058 Set Vref, RX VrefLevel [Byte0]: 70
3484 22:21:02.950989 [Byte1]: 70
3485 22:21:02.956101
3486 22:21:02.956186 Final RX Vref Byte 0 = 56 to rank0
3487 22:21:02.959216 Final RX Vref Byte 1 = 53 to rank0
3488 22:21:02.962335 Final RX Vref Byte 0 = 56 to rank1
3489 22:21:02.965792 Final RX Vref Byte 1 = 53 to rank1==
3490 22:21:02.969072 Dram Type= 6, Freq= 0, CH_1, rank 0
3491 22:21:02.975749 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3492 22:21:02.975864 ==
3493 22:21:02.975961 DQS Delay:
3494 22:21:02.978666 DQS0 = 0, DQS1 = 0
3495 22:21:02.978777 DQM Delay:
3496 22:21:02.982197 DQM0 = 115, DQM1 = 108
3497 22:21:02.982301 DQ Delay:
3498 22:21:02.985316 DQ0 =118, DQ1 =108, DQ2 =106, DQ3 =114
3499 22:21:02.988765 DQ4 =112, DQ5 =122, DQ6 =126, DQ7 =114
3500 22:21:02.991899 DQ8 =94, DQ9 =98, DQ10 =106, DQ11 =106
3501 22:21:02.994942 DQ12 =116, DQ13 =114, DQ14 =116, DQ15 =114
3502 22:21:02.995019
3503 22:21:02.995083
3504 22:21:03.004902 [DQSOSCAuto] RK0, (LSB)MR18= 0xebf2, (MSB)MR19= 0x303, tDQSOscB0 = 415 ps tDQSOscB1 = 418 ps
3505 22:21:03.005012 CH1 RK0: MR19=303, MR18=EBF2
3506 22:21:03.011975 CH1_RK0: MR19=0x303, MR18=0xEBF2, DQSOSC=415, MR23=63, INC=38, DEC=25
3507 22:21:03.012061
3508 22:21:03.015088 ----->DramcWriteLeveling(PI) begin...
3509 22:21:03.015174 ==
3510 22:21:03.018560 Dram Type= 6, Freq= 0, CH_1, rank 1
3511 22:21:03.025219 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3512 22:21:03.025310 ==
3513 22:21:03.028192 Write leveling (Byte 0): 25 => 25
3514 22:21:03.031765 Write leveling (Byte 1): 29 => 29
3515 22:21:03.031850 DramcWriteLeveling(PI) end<-----
3516 22:21:03.034671
3517 22:21:03.034789 ==
3518 22:21:03.038270 Dram Type= 6, Freq= 0, CH_1, rank 1
3519 22:21:03.041694 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3520 22:21:03.041806 ==
3521 22:21:03.044767 [Gating] SW mode calibration
3522 22:21:03.051631 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3523 22:21:03.054689 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3524 22:21:03.061603 0 15 0 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
3525 22:21:03.064799 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3526 22:21:03.067897 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3527 22:21:03.074876 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3528 22:21:03.078107 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3529 22:21:03.081402 0 15 20 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
3530 22:21:03.087544 0 15 24 | B1->B0 | 3434 2626 | 0 0 | (1 0) (0 1)
3531 22:21:03.091084 0 15 28 | B1->B0 | 2929 2323 | 0 0 | (1 0) (0 0)
3532 22:21:03.094566 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3533 22:21:03.101312 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3534 22:21:03.104273 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3535 22:21:03.108119 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3536 22:21:03.114100 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3537 22:21:03.117545 1 0 20 | B1->B0 | 2323 2726 | 0 1 | (0 0) (0 0)
3538 22:21:03.120684 1 0 24 | B1->B0 | 2828 4545 | 0 0 | (0 0) (0 0)
3539 22:21:03.127606 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3540 22:21:03.131071 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3541 22:21:03.134170 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3542 22:21:03.140642 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3543 22:21:03.144323 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3544 22:21:03.147132 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3545 22:21:03.153848 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3546 22:21:03.156981 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3547 22:21:03.160974 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3548 22:21:03.166949 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3549 22:21:03.170705 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3550 22:21:03.173722 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3551 22:21:03.180465 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3552 22:21:03.183935 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3553 22:21:03.186794 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3554 22:21:03.193745 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3555 22:21:03.196537 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3556 22:21:03.200030 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3557 22:21:03.206795 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3558 22:21:03.209863 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3559 22:21:03.213188 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3560 22:21:03.219793 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3561 22:21:03.223323 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3562 22:21:03.226391 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3563 22:21:03.233203 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3564 22:21:03.236367 Total UI for P1: 0, mck2ui 16
3565 22:21:03.239885 best dqsien dly found for B0: ( 1, 3, 26)
3566 22:21:03.242780 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3567 22:21:03.246369 Total UI for P1: 0, mck2ui 16
3568 22:21:03.249378 best dqsien dly found for B1: ( 1, 3, 28)
3569 22:21:03.252812 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3570 22:21:03.255778 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3571 22:21:03.255867
3572 22:21:03.259578 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3573 22:21:03.262648 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3574 22:21:03.265765 [Gating] SW calibration Done
3575 22:21:03.265843 ==
3576 22:21:03.268851 Dram Type= 6, Freq= 0, CH_1, rank 1
3577 22:21:03.275570 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3578 22:21:03.275651 ==
3579 22:21:03.275723 RX Vref Scan: 0
3580 22:21:03.275787
3581 22:21:03.278794 RX Vref 0 -> 0, step: 1
3582 22:21:03.278897
3583 22:21:03.282409 RX Delay -40 -> 252, step: 8
3584 22:21:03.285847 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3585 22:21:03.288790 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3586 22:21:03.292261 iDelay=200, Bit 2, Center 99 (24 ~ 175) 152
3587 22:21:03.299165 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
3588 22:21:03.301989 iDelay=200, Bit 4, Center 107 (32 ~ 183) 152
3589 22:21:03.305534 iDelay=200, Bit 5, Center 119 (40 ~ 199) 160
3590 22:21:03.309023 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
3591 22:21:03.312038 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3592 22:21:03.315781 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3593 22:21:03.321835 iDelay=200, Bit 9, Center 99 (24 ~ 175) 152
3594 22:21:03.325425 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3595 22:21:03.328436 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3596 22:21:03.332074 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3597 22:21:03.338356 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3598 22:21:03.341964 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3599 22:21:03.344865 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3600 22:21:03.344950 ==
3601 22:21:03.348608 Dram Type= 6, Freq= 0, CH_1, rank 1
3602 22:21:03.351548 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3603 22:21:03.351640 ==
3604 22:21:03.355105 DQS Delay:
3605 22:21:03.355183 DQS0 = 0, DQS1 = 0
3606 22:21:03.358544 DQM Delay:
3607 22:21:03.358643 DQM0 = 110, DQM1 = 110
3608 22:21:03.358742 DQ Delay:
3609 22:21:03.361975 DQ0 =115, DQ1 =107, DQ2 =99, DQ3 =107
3610 22:21:03.368236 DQ4 =107, DQ5 =119, DQ6 =119, DQ7 =111
3611 22:21:03.371947 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =103
3612 22:21:03.375025 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =119
3613 22:21:03.375110
3614 22:21:03.375176
3615 22:21:03.375237 ==
3616 22:21:03.378100 Dram Type= 6, Freq= 0, CH_1, rank 1
3617 22:21:03.381838 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3618 22:21:03.381923 ==
3619 22:21:03.381990
3620 22:21:03.382050
3621 22:21:03.384857 TX Vref Scan disable
3622 22:21:03.388049 == TX Byte 0 ==
3623 22:21:03.391429 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3624 22:21:03.394714 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3625 22:21:03.397574 == TX Byte 1 ==
3626 22:21:03.400942 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3627 22:21:03.404430 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3628 22:21:03.404511 ==
3629 22:21:03.407882 Dram Type= 6, Freq= 0, CH_1, rank 1
3630 22:21:03.414117 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3631 22:21:03.414203 ==
3632 22:21:03.424890 TX Vref=22, minBit 1, minWin=25, winSum=414
3633 22:21:03.427942 TX Vref=24, minBit 1, minWin=25, winSum=416
3634 22:21:03.431113 TX Vref=26, minBit 4, minWin=25, winSum=420
3635 22:21:03.434743 TX Vref=28, minBit 7, minWin=25, winSum=421
3636 22:21:03.437889 TX Vref=30, minBit 0, minWin=26, winSum=423
3637 22:21:03.444772 TX Vref=32, minBit 0, minWin=26, winSum=422
3638 22:21:03.447601 [TxChooseVref] Worse bit 0, Min win 26, Win sum 423, Final Vref 30
3639 22:21:03.447684
3640 22:21:03.451142 Final TX Range 1 Vref 30
3641 22:21:03.451226
3642 22:21:03.451292 ==
3643 22:21:03.454222 Dram Type= 6, Freq= 0, CH_1, rank 1
3644 22:21:03.461050 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3645 22:21:03.461132 ==
3646 22:21:03.461197
3647 22:21:03.461258
3648 22:21:03.461318 TX Vref Scan disable
3649 22:21:03.464295 == TX Byte 0 ==
3650 22:21:03.467746 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3651 22:21:03.474489 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3652 22:21:03.474596 == TX Byte 1 ==
3653 22:21:03.477971 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3654 22:21:03.484414 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3655 22:21:03.484500
3656 22:21:03.484566 [DATLAT]
3657 22:21:03.484630 Freq=1200, CH1 RK1
3658 22:21:03.484690
3659 22:21:03.487574 DATLAT Default: 0xd
3660 22:21:03.491201 0, 0xFFFF, sum = 0
3661 22:21:03.491287 1, 0xFFFF, sum = 0
3662 22:21:03.494366 2, 0xFFFF, sum = 0
3663 22:21:03.494452 3, 0xFFFF, sum = 0
3664 22:21:03.497635 4, 0xFFFF, sum = 0
3665 22:21:03.497749 5, 0xFFFF, sum = 0
3666 22:21:03.500502 6, 0xFFFF, sum = 0
3667 22:21:03.500587 7, 0xFFFF, sum = 0
3668 22:21:03.503860 8, 0xFFFF, sum = 0
3669 22:21:03.503946 9, 0xFFFF, sum = 0
3670 22:21:03.507414 10, 0xFFFF, sum = 0
3671 22:21:03.507500 11, 0xFFFF, sum = 0
3672 22:21:03.510861 12, 0x0, sum = 1
3673 22:21:03.510946 13, 0x0, sum = 2
3674 22:21:03.513789 14, 0x0, sum = 3
3675 22:21:03.513877 15, 0x0, sum = 4
3676 22:21:03.517115 best_step = 13
3677 22:21:03.517203
3678 22:21:03.517272 ==
3679 22:21:03.520714 Dram Type= 6, Freq= 0, CH_1, rank 1
3680 22:21:03.523556 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3681 22:21:03.523668 ==
3682 22:21:03.526920 RX Vref Scan: 0
3683 22:21:03.527001
3684 22:21:03.527066 RX Vref 0 -> 0, step: 1
3685 22:21:03.527128
3686 22:21:03.530012 RX Delay -21 -> 252, step: 4
3687 22:21:03.536727 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3688 22:21:03.539831 iDelay=195, Bit 1, Center 110 (43 ~ 178) 136
3689 22:21:03.543452 iDelay=195, Bit 2, Center 104 (39 ~ 170) 132
3690 22:21:03.546632 iDelay=195, Bit 3, Center 110 (43 ~ 178) 136
3691 22:21:03.553336 iDelay=195, Bit 4, Center 110 (43 ~ 178) 136
3692 22:21:03.556247 iDelay=195, Bit 5, Center 122 (51 ~ 194) 144
3693 22:21:03.559949 iDelay=195, Bit 6, Center 122 (51 ~ 194) 144
3694 22:21:03.563033 iDelay=195, Bit 7, Center 110 (43 ~ 178) 136
3695 22:21:03.566445 iDelay=195, Bit 8, Center 96 (31 ~ 162) 132
3696 22:21:03.572941 iDelay=195, Bit 9, Center 104 (43 ~ 166) 124
3697 22:21:03.576682 iDelay=195, Bit 10, Center 114 (51 ~ 178) 128
3698 22:21:03.579787 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3699 22:21:03.582875 iDelay=195, Bit 12, Center 120 (59 ~ 182) 124
3700 22:21:03.586089 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3701 22:21:03.592802 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3702 22:21:03.595937 iDelay=195, Bit 15, Center 120 (55 ~ 186) 132
3703 22:21:03.596049 ==
3704 22:21:03.599089 Dram Type= 6, Freq= 0, CH_1, rank 1
3705 22:21:03.602723 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3706 22:21:03.602843 ==
3707 22:21:03.606163 DQS Delay:
3708 22:21:03.606273 DQS0 = 0, DQS1 = 0
3709 22:21:03.606374 DQM Delay:
3710 22:21:03.608999 DQM0 = 112, DQM1 = 112
3711 22:21:03.609120 DQ Delay:
3712 22:21:03.612368 DQ0 =114, DQ1 =110, DQ2 =104, DQ3 =110
3713 22:21:03.615865 DQ4 =110, DQ5 =122, DQ6 =122, DQ7 =110
3714 22:21:03.622601 DQ8 =96, DQ9 =104, DQ10 =114, DQ11 =106
3715 22:21:03.625658 DQ12 =120, DQ13 =118, DQ14 =118, DQ15 =120
3716 22:21:03.625745
3717 22:21:03.625831
3718 22:21:03.632124 [DQSOSCAuto] RK1, (LSB)MR18= 0xf606, (MSB)MR19= 0x304, tDQSOscB0 = 407 ps tDQSOscB1 = 414 ps
3719 22:21:03.635886 CH1 RK1: MR19=304, MR18=F606
3720 22:21:03.642441 CH1_RK1: MR19=0x304, MR18=0xF606, DQSOSC=407, MR23=63, INC=39, DEC=26
3721 22:21:03.645438 [RxdqsGatingPostProcess] freq 1200
3722 22:21:03.652335 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3723 22:21:03.652425 best DQS0 dly(2T, 0.5T) = (0, 11)
3724 22:21:03.655510 best DQS1 dly(2T, 0.5T) = (0, 11)
3725 22:21:03.658987 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3726 22:21:03.661944 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3727 22:21:03.665512 best DQS0 dly(2T, 0.5T) = (0, 11)
3728 22:21:03.668584 best DQS1 dly(2T, 0.5T) = (0, 11)
3729 22:21:03.671961 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3730 22:21:03.675017 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3731 22:21:03.678497 Pre-setting of DQS Precalculation
3732 22:21:03.685117 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3733 22:21:03.691386 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3734 22:21:03.698323 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3735 22:21:03.698441
3736 22:21:03.698538
3737 22:21:03.701182 [Calibration Summary] 2400 Mbps
3738 22:21:03.701307 CH 0, Rank 0
3739 22:21:03.704928 SW Impedance : PASS
3740 22:21:03.707974 DUTY Scan : NO K
3741 22:21:03.708058 ZQ Calibration : PASS
3742 22:21:03.711480 Jitter Meter : NO K
3743 22:21:03.714841 CBT Training : PASS
3744 22:21:03.714922 Write leveling : PASS
3745 22:21:03.718191 RX DQS gating : PASS
3746 22:21:03.721004 RX DQ/DQS(RDDQC) : PASS
3747 22:21:03.721097 TX DQ/DQS : PASS
3748 22:21:03.724528 RX DATLAT : PASS
3749 22:21:03.728061 RX DQ/DQS(Engine): PASS
3750 22:21:03.728149 TX OE : NO K
3751 22:21:03.728237 All Pass.
3752 22:21:03.730876
3753 22:21:03.730963 CH 0, Rank 1
3754 22:21:03.734357 SW Impedance : PASS
3755 22:21:03.734445 DUTY Scan : NO K
3756 22:21:03.737815 ZQ Calibration : PASS
3757 22:21:03.740766 Jitter Meter : NO K
3758 22:21:03.740854 CBT Training : PASS
3759 22:21:03.744321 Write leveling : PASS
3760 22:21:03.744409 RX DQS gating : PASS
3761 22:21:03.747388 RX DQ/DQS(RDDQC) : PASS
3762 22:21:03.751150 TX DQ/DQS : PASS
3763 22:21:03.751242 RX DATLAT : PASS
3764 22:21:03.754190 RX DQ/DQS(Engine): PASS
3765 22:21:03.757238 TX OE : NO K
3766 22:21:03.757343 All Pass.
3767 22:21:03.757447
3768 22:21:03.757538 CH 1, Rank 0
3769 22:21:03.760908 SW Impedance : PASS
3770 22:21:03.764001 DUTY Scan : NO K
3771 22:21:03.764076 ZQ Calibration : PASS
3772 22:21:03.767507 Jitter Meter : NO K
3773 22:21:03.770504 CBT Training : PASS
3774 22:21:03.770634 Write leveling : PASS
3775 22:21:03.773509 RX DQS gating : PASS
3776 22:21:03.777049 RX DQ/DQS(RDDQC) : PASS
3777 22:21:03.777159 TX DQ/DQS : PASS
3778 22:21:03.780760 RX DATLAT : PASS
3779 22:21:03.783505 RX DQ/DQS(Engine): PASS
3780 22:21:03.783621 TX OE : NO K
3781 22:21:03.787167 All Pass.
3782 22:21:03.787293
3783 22:21:03.787416 CH 1, Rank 1
3784 22:21:03.790051 SW Impedance : PASS
3785 22:21:03.790161 DUTY Scan : NO K
3786 22:21:03.793752 ZQ Calibration : PASS
3787 22:21:03.796946 Jitter Meter : NO K
3788 22:21:03.797075 CBT Training : PASS
3789 22:21:03.800610 Write leveling : PASS
3790 22:21:03.803815 RX DQS gating : PASS
3791 22:21:03.803911 RX DQ/DQS(RDDQC) : PASS
3792 22:21:03.806931 TX DQ/DQS : PASS
3793 22:21:03.810020 RX DATLAT : PASS
3794 22:21:03.810105 RX DQ/DQS(Engine): PASS
3795 22:21:03.813857 TX OE : NO K
3796 22:21:03.813943 All Pass.
3797 22:21:03.814010
3798 22:21:03.816579 DramC Write-DBI off
3799 22:21:03.820205 PER_BANK_REFRESH: Hybrid Mode
3800 22:21:03.820291 TX_TRACKING: ON
3801 22:21:03.830139 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3802 22:21:03.833330 [FAST_K] Save calibration result to emmc
3803 22:21:03.836690 dramc_set_vcore_voltage set vcore to 650000
3804 22:21:03.840002 Read voltage for 600, 5
3805 22:21:03.840122 Vio18 = 0
3806 22:21:03.840230 Vcore = 650000
3807 22:21:03.843848 Vdram = 0
3808 22:21:03.843933 Vddq = 0
3809 22:21:03.844022 Vmddr = 0
3810 22:21:03.849949 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3811 22:21:03.852996 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3812 22:21:03.856110 MEM_TYPE=3, freq_sel=19
3813 22:21:03.859256 sv_algorithm_assistance_LP4_1600
3814 22:21:03.863022 ============ PULL DRAM RESETB DOWN ============
3815 22:21:03.866069 ========== PULL DRAM RESETB DOWN end =========
3816 22:21:03.872641 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3817 22:21:03.876210 ===================================
3818 22:21:03.879323 LPDDR4 DRAM CONFIGURATION
3819 22:21:03.882342 ===================================
3820 22:21:03.882426 EX_ROW_EN[0] = 0x0
3821 22:21:03.885771 EX_ROW_EN[1] = 0x0
3822 22:21:03.885882 LP4Y_EN = 0x0
3823 22:21:03.889285 WORK_FSP = 0x0
3824 22:21:03.889395 WL = 0x2
3825 22:21:03.892980 RL = 0x2
3826 22:21:03.893055 BL = 0x2
3827 22:21:03.895850 RPST = 0x0
3828 22:21:03.895949 RD_PRE = 0x0
3829 22:21:03.899515 WR_PRE = 0x1
3830 22:21:03.899599 WR_PST = 0x0
3831 22:21:03.902553 DBI_WR = 0x0
3832 22:21:03.902638 DBI_RD = 0x0
3833 22:21:03.905736 OTF = 0x1
3834 22:21:03.908800 ===================================
3835 22:21:03.912494 ===================================
3836 22:21:03.912579 ANA top config
3837 22:21:03.915608 ===================================
3838 22:21:03.918683 DLL_ASYNC_EN = 0
3839 22:21:03.922183 ALL_SLAVE_EN = 1
3840 22:21:03.925735 NEW_RANK_MODE = 1
3841 22:21:03.928525 DLL_IDLE_MODE = 1
3842 22:21:03.928606 LP45_APHY_COMB_EN = 1
3843 22:21:03.931921 TX_ODT_DIS = 1
3844 22:21:03.935497 NEW_8X_MODE = 1
3845 22:21:03.938737 ===================================
3846 22:21:03.941660 ===================================
3847 22:21:03.945492 data_rate = 1200
3848 22:21:03.948421 CKR = 1
3849 22:21:03.948511 DQ_P2S_RATIO = 8
3850 22:21:03.951920 ===================================
3851 22:21:03.955371 CA_P2S_RATIO = 8
3852 22:21:03.958363 DQ_CA_OPEN = 0
3853 22:21:03.962167 DQ_SEMI_OPEN = 0
3854 22:21:03.965296 CA_SEMI_OPEN = 0
3855 22:21:03.968311 CA_FULL_RATE = 0
3856 22:21:03.968390 DQ_CKDIV4_EN = 1
3857 22:21:03.971478 CA_CKDIV4_EN = 1
3858 22:21:03.975167 CA_PREDIV_EN = 0
3859 22:21:03.978214 PH8_DLY = 0
3860 22:21:03.981770 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3861 22:21:03.984755 DQ_AAMCK_DIV = 4
3862 22:21:03.984842 CA_AAMCK_DIV = 4
3863 22:21:03.988263 CA_ADMCK_DIV = 4
3864 22:21:03.991698 DQ_TRACK_CA_EN = 0
3865 22:21:03.995189 CA_PICK = 600
3866 22:21:03.998065 CA_MCKIO = 600
3867 22:21:04.001671 MCKIO_SEMI = 0
3868 22:21:04.004782 PLL_FREQ = 2288
3869 22:21:04.007894 DQ_UI_PI_RATIO = 32
3870 22:21:04.007977 CA_UI_PI_RATIO = 0
3871 22:21:04.010982 ===================================
3872 22:21:04.014716 ===================================
3873 22:21:04.017844 memory_type:LPDDR4
3874 22:21:04.020965 GP_NUM : 10
3875 22:21:04.021049 SRAM_EN : 1
3876 22:21:04.024778 MD32_EN : 0
3877 22:21:04.027596 ===================================
3878 22:21:04.030877 [ANA_INIT] >>>>>>>>>>>>>>
3879 22:21:04.034376 <<<<<< [CONFIGURE PHASE]: ANA_TX
3880 22:21:04.037769 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3881 22:21:04.040615 ===================================
3882 22:21:04.040700 data_rate = 1200,PCW = 0X5800
3883 22:21:04.044178 ===================================
3884 22:21:04.047349 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3885 22:21:04.054196 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3886 22:21:04.060451 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3887 22:21:04.063986 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3888 22:21:04.067083 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3889 22:21:04.070208 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3890 22:21:04.073897 [ANA_INIT] flow start
3891 22:21:04.076987 [ANA_INIT] PLL >>>>>>>>
3892 22:21:04.077065 [ANA_INIT] PLL <<<<<<<<
3893 22:21:04.080172 [ANA_INIT] MIDPI >>>>>>>>
3894 22:21:04.083763 [ANA_INIT] MIDPI <<<<<<<<
3895 22:21:04.083845 [ANA_INIT] DLL >>>>>>>>
3896 22:21:04.086754 [ANA_INIT] flow end
3897 22:21:04.090350 ============ LP4 DIFF to SE enter ============
3898 22:21:04.096988 ============ LP4 DIFF to SE exit ============
3899 22:21:04.097084 [ANA_INIT] <<<<<<<<<<<<<
3900 22:21:04.099828 [Flow] Enable top DCM control >>>>>
3901 22:21:04.103411 [Flow] Enable top DCM control <<<<<
3902 22:21:04.106791 Enable DLL master slave shuffle
3903 22:21:04.113303 ==============================================================
3904 22:21:04.113390 Gating Mode config
3905 22:21:04.119875 ==============================================================
3906 22:21:04.123039 Config description:
3907 22:21:04.133541 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3908 22:21:04.139895 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3909 22:21:04.143191 SELPH_MODE 0: By rank 1: By Phase
3910 22:21:04.149417 ==============================================================
3911 22:21:04.152830 GAT_TRACK_EN = 1
3912 22:21:04.155877 RX_GATING_MODE = 2
3913 22:21:04.155973 RX_GATING_TRACK_MODE = 2
3914 22:21:04.159353 SELPH_MODE = 1
3915 22:21:04.162849 PICG_EARLY_EN = 1
3916 22:21:04.165816 VALID_LAT_VALUE = 1
3917 22:21:04.172737 ==============================================================
3918 22:21:04.175841 Enter into Gating configuration >>>>
3919 22:21:04.179033 Exit from Gating configuration <<<<
3920 22:21:04.182767 Enter into DVFS_PRE_config >>>>>
3921 22:21:04.192427 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3922 22:21:04.195597 Exit from DVFS_PRE_config <<<<<
3923 22:21:04.198616 Enter into PICG configuration >>>>
3924 22:21:04.202336 Exit from PICG configuration <<<<
3925 22:21:04.205244 [RX_INPUT] configuration >>>>>
3926 22:21:04.209007 [RX_INPUT] configuration <<<<<
3927 22:21:04.211997 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3928 22:21:04.218410 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3929 22:21:04.225348 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3930 22:21:04.232091 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3931 22:21:04.238375 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3932 22:21:04.241925 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3933 22:21:04.248335 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3934 22:21:04.251725 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3935 22:21:04.255146 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3936 22:21:04.258569 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3937 22:21:04.264970 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3938 22:21:04.268388 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3939 22:21:04.271217 ===================================
3940 22:21:04.274582 LPDDR4 DRAM CONFIGURATION
3941 22:21:04.278250 ===================================
3942 22:21:04.278333 EX_ROW_EN[0] = 0x0
3943 22:21:04.281385 EX_ROW_EN[1] = 0x0
3944 22:21:04.281462 LP4Y_EN = 0x0
3945 22:21:04.285055 WORK_FSP = 0x0
3946 22:21:04.285130 WL = 0x2
3947 22:21:04.288176 RL = 0x2
3948 22:21:04.288263 BL = 0x2
3949 22:21:04.291376 RPST = 0x0
3950 22:21:04.291461 RD_PRE = 0x0
3951 22:21:04.294468 WR_PRE = 0x1
3952 22:21:04.298087 WR_PST = 0x0
3953 22:21:04.298172 DBI_WR = 0x0
3954 22:21:04.301083 DBI_RD = 0x0
3955 22:21:04.301168 OTF = 0x1
3956 22:21:04.304767 ===================================
3957 22:21:04.307835 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3958 22:21:04.314358 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3959 22:21:04.317850 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3960 22:21:04.321031 ===================================
3961 22:21:04.324751 LPDDR4 DRAM CONFIGURATION
3962 22:21:04.327907 ===================================
3963 22:21:04.327995 EX_ROW_EN[0] = 0x10
3964 22:21:04.330947 EX_ROW_EN[1] = 0x0
3965 22:21:04.331034 LP4Y_EN = 0x0
3966 22:21:04.334684 WORK_FSP = 0x0
3967 22:21:04.334802 WL = 0x2
3968 22:21:04.337795 RL = 0x2
3969 22:21:04.337880 BL = 0x2
3970 22:21:04.340936 RPST = 0x0
3971 22:21:04.341020 RD_PRE = 0x0
3972 22:21:04.344568 WR_PRE = 0x1
3973 22:21:04.347623 WR_PST = 0x0
3974 22:21:04.347708 DBI_WR = 0x0
3975 22:21:04.351268 DBI_RD = 0x0
3976 22:21:04.351353 OTF = 0x1
3977 22:21:04.353889 ===================================
3978 22:21:04.360736 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3979 22:21:04.364734 nWR fixed to 30
3980 22:21:04.367719 [ModeRegInit_LP4] CH0 RK0
3981 22:21:04.367804 [ModeRegInit_LP4] CH0 RK1
3982 22:21:04.371102 [ModeRegInit_LP4] CH1 RK0
3983 22:21:04.374588 [ModeRegInit_LP4] CH1 RK1
3984 22:21:04.374673 match AC timing 17
3985 22:21:04.380896 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3986 22:21:04.383948 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3987 22:21:04.387675 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3988 22:21:04.393902 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3989 22:21:04.397018 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3990 22:21:04.397103 ==
3991 22:21:04.400715 Dram Type= 6, Freq= 0, CH_0, rank 0
3992 22:21:04.403829 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3993 22:21:04.407301 ==
3994 22:21:04.410320 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3995 22:21:04.416972 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3996 22:21:04.420541 [CA 0] Center 37 (7~67) winsize 61
3997 22:21:04.423661 [CA 1] Center 36 (6~67) winsize 62
3998 22:21:04.427084 [CA 2] Center 35 (5~65) winsize 61
3999 22:21:04.430480 [CA 3] Center 35 (5~65) winsize 61
4000 22:21:04.433529 [CA 4] Center 34 (4~65) winsize 62
4001 22:21:04.436563 [CA 5] Center 34 (4~64) winsize 61
4002 22:21:04.436675
4003 22:21:04.440263 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4004 22:21:04.440377
4005 22:21:04.443406 [CATrainingPosCal] consider 1 rank data
4006 22:21:04.446488 u2DelayCellTimex100 = 270/100 ps
4007 22:21:04.450179 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
4008 22:21:04.453252 CA1 delay=36 (6~67),Diff = 2 PI (19 cell)
4009 22:21:04.459879 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
4010 22:21:04.463361 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
4011 22:21:04.466251 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4012 22:21:04.469504 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4013 22:21:04.469585
4014 22:21:04.472952 CA PerBit enable=1, Macro0, CA PI delay=34
4015 22:21:04.473038
4016 22:21:04.476532 [CBTSetCACLKResult] CA Dly = 34
4017 22:21:04.476617 CS Dly: 6 (0~37)
4018 22:21:04.479345 ==
4019 22:21:04.479430 Dram Type= 6, Freq= 0, CH_0, rank 1
4020 22:21:04.486238 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4021 22:21:04.486324 ==
4022 22:21:04.489699 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4023 22:21:04.495875 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4024 22:21:04.499652 [CA 0] Center 37 (7~67) winsize 61
4025 22:21:04.503318 [CA 1] Center 36 (6~67) winsize 62
4026 22:21:04.506317 [CA 2] Center 35 (5~65) winsize 61
4027 22:21:04.510087 [CA 3] Center 34 (4~65) winsize 62
4028 22:21:04.513038 [CA 4] Center 34 (4~65) winsize 62
4029 22:21:04.516226 [CA 5] Center 33 (3~64) winsize 62
4030 22:21:04.516311
4031 22:21:04.519812 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4032 22:21:04.519900
4033 22:21:04.522761 [CATrainingPosCal] consider 2 rank data
4034 22:21:04.526428 u2DelayCellTimex100 = 270/100 ps
4035 22:21:04.529439 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
4036 22:21:04.535886 CA1 delay=36 (6~67),Diff = 2 PI (19 cell)
4037 22:21:04.539319 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
4038 22:21:04.542489 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
4039 22:21:04.546222 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4040 22:21:04.549207 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4041 22:21:04.549289
4042 22:21:04.552283 CA PerBit enable=1, Macro0, CA PI delay=34
4043 22:21:04.552395
4044 22:21:04.555923 [CBTSetCACLKResult] CA Dly = 34
4045 22:21:04.558986 CS Dly: 6 (0~37)
4046 22:21:04.559061
4047 22:21:04.562155 ----->DramcWriteLeveling(PI) begin...
4048 22:21:04.562238 ==
4049 22:21:04.565859 Dram Type= 6, Freq= 0, CH_0, rank 0
4050 22:21:04.568699 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4051 22:21:04.568818 ==
4052 22:21:04.572259 Write leveling (Byte 0): 33 => 33
4053 22:21:04.575563 Write leveling (Byte 1): 33 => 33
4054 22:21:04.578486 DramcWriteLeveling(PI) end<-----
4055 22:21:04.578601
4056 22:21:04.578691 ==
4057 22:21:04.581991 Dram Type= 6, Freq= 0, CH_0, rank 0
4058 22:21:04.585399 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4059 22:21:04.585507 ==
4060 22:21:04.588925 [Gating] SW mode calibration
4061 22:21:04.595258 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4062 22:21:04.602107 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4063 22:21:04.605186 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4064 22:21:04.608194 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4065 22:21:04.614990 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4066 22:21:04.618394 0 9 12 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
4067 22:21:04.621544 0 9 16 | B1->B0 | 3030 2424 | 1 1 | (1 1) (1 0)
4068 22:21:04.628052 0 9 20 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
4069 22:21:04.631767 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4070 22:21:04.634921 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4071 22:21:04.641350 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4072 22:21:04.644731 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4073 22:21:04.651545 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4074 22:21:04.654451 0 10 12 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
4075 22:21:04.657576 0 10 16 | B1->B0 | 3434 3838 | 0 0 | (0 0) (0 0)
4076 22:21:04.664353 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4077 22:21:04.667392 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4078 22:21:04.671066 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4079 22:21:04.677838 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4080 22:21:04.680501 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4081 22:21:04.683927 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4082 22:21:04.690307 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4083 22:21:04.693752 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4084 22:21:04.697163 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4085 22:21:04.703790 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4086 22:21:04.706847 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4087 22:21:04.710662 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4088 22:21:04.716810 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4089 22:21:04.720492 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4090 22:21:04.723575 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4091 22:21:04.730063 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4092 22:21:04.733859 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4093 22:21:04.736928 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4094 22:21:04.743461 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4095 22:21:04.746543 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4096 22:21:04.750188 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4097 22:21:04.756852 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4098 22:21:04.759714 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4099 22:21:04.763321 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4100 22:21:04.766396 Total UI for P1: 0, mck2ui 16
4101 22:21:04.769537 best dqsien dly found for B0: ( 0, 13, 12)
4102 22:21:04.776428 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4103 22:21:04.776546 Total UI for P1: 0, mck2ui 16
4104 22:21:04.779464 best dqsien dly found for B1: ( 0, 13, 18)
4105 22:21:04.785878 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4106 22:21:04.789263 best DQS1 dly(MCK, UI, PI) = (0, 13, 18)
4107 22:21:04.789371
4108 22:21:04.792832 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4109 22:21:04.795748 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 18)
4110 22:21:04.799125 [Gating] SW calibration Done
4111 22:21:04.799204 ==
4112 22:21:04.802573 Dram Type= 6, Freq= 0, CH_0, rank 0
4113 22:21:04.806078 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4114 22:21:04.806190 ==
4115 22:21:04.809210 RX Vref Scan: 0
4116 22:21:04.809289
4117 22:21:04.809354 RX Vref 0 -> 0, step: 1
4118 22:21:04.809416
4119 22:21:04.812337 RX Delay -230 -> 252, step: 16
4120 22:21:04.819111 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4121 22:21:04.822126 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4122 22:21:04.825322 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4123 22:21:04.828926 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4124 22:21:04.832018 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4125 22:21:04.838603 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4126 22:21:04.842235 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4127 22:21:04.845221 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4128 22:21:04.849063 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4129 22:21:04.854887 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4130 22:21:04.858418 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4131 22:21:04.861901 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4132 22:21:04.864923 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4133 22:21:04.872023 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4134 22:21:04.875247 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4135 22:21:04.878355 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4136 22:21:04.878435 ==
4137 22:21:04.881458 Dram Type= 6, Freq= 0, CH_0, rank 0
4138 22:21:04.887864 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4139 22:21:04.887978 ==
4140 22:21:04.888075 DQS Delay:
4141 22:21:04.888178 DQS0 = 0, DQS1 = 0
4142 22:21:04.891464 DQM Delay:
4143 22:21:04.891543 DQM0 = 37, DQM1 = 30
4144 22:21:04.894785 DQ Delay:
4145 22:21:04.897796 DQ0 =33, DQ1 =33, DQ2 =33, DQ3 =33
4146 22:21:04.901194 DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49
4147 22:21:04.901273 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4148 22:21:04.908179 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =33
4149 22:21:04.908258
4150 22:21:04.908331
4151 22:21:04.908394 ==
4152 22:21:04.911486 Dram Type= 6, Freq= 0, CH_0, rank 0
4153 22:21:04.914497 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4154 22:21:04.914572 ==
4155 22:21:04.914636
4156 22:21:04.914702
4157 22:21:04.917616 TX Vref Scan disable
4158 22:21:04.917693 == TX Byte 0 ==
4159 22:21:04.924342 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4160 22:21:04.927538 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4161 22:21:04.931222 == TX Byte 1 ==
4162 22:21:04.934431 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4163 22:21:04.937848 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4164 22:21:04.937926 ==
4165 22:21:04.940603 Dram Type= 6, Freq= 0, CH_0, rank 0
4166 22:21:04.944343 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4167 22:21:04.944429 ==
4168 22:21:04.947482
4169 22:21:04.947567
4170 22:21:04.947635 TX Vref Scan disable
4171 22:21:04.950874 == TX Byte 0 ==
4172 22:21:04.954325 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4173 22:21:04.961092 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4174 22:21:04.961178 == TX Byte 1 ==
4175 22:21:04.964249 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4176 22:21:04.971043 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4177 22:21:04.971134
4178 22:21:04.971203 [DATLAT]
4179 22:21:04.971266 Freq=600, CH0 RK0
4180 22:21:04.971328
4181 22:21:04.974147 DATLAT Default: 0x9
4182 22:21:04.974267 0, 0xFFFF, sum = 0
4183 22:21:04.977267 1, 0xFFFF, sum = 0
4184 22:21:04.980370 2, 0xFFFF, sum = 0
4185 22:21:04.980456 3, 0xFFFF, sum = 0
4186 22:21:04.984014 4, 0xFFFF, sum = 0
4187 22:21:04.984100 5, 0xFFFF, sum = 0
4188 22:21:04.987173 6, 0xFFFF, sum = 0
4189 22:21:04.987259 7, 0xFFFF, sum = 0
4190 22:21:04.990770 8, 0x0, sum = 1
4191 22:21:04.990869 9, 0x0, sum = 2
4192 22:21:04.993683 10, 0x0, sum = 3
4193 22:21:04.993767 11, 0x0, sum = 4
4194 22:21:04.993832 best_step = 9
4195 22:21:04.993894
4196 22:21:04.997186 ==
4197 22:21:05.000482 Dram Type= 6, Freq= 0, CH_0, rank 0
4198 22:21:05.003825 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4199 22:21:05.003911 ==
4200 22:21:05.003979 RX Vref Scan: 1
4201 22:21:05.004043
4202 22:21:05.007211 RX Vref 0 -> 0, step: 1
4203 22:21:05.007325
4204 22:21:05.010649 RX Delay -195 -> 252, step: 8
4205 22:21:05.010758
4206 22:21:05.013529 Set Vref, RX VrefLevel [Byte0]: 60
4207 22:21:05.016890 [Byte1]: 48
4208 22:21:05.016997
4209 22:21:05.020491 Final RX Vref Byte 0 = 60 to rank0
4210 22:21:05.023628 Final RX Vref Byte 1 = 48 to rank0
4211 22:21:05.026738 Final RX Vref Byte 0 = 60 to rank1
4212 22:21:05.030489 Final RX Vref Byte 1 = 48 to rank1==
4213 22:21:05.033628 Dram Type= 6, Freq= 0, CH_0, rank 0
4214 22:21:05.036717 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4215 22:21:05.040438 ==
4216 22:21:05.040536 DQS Delay:
4217 22:21:05.040632 DQS0 = 0, DQS1 = 0
4218 22:21:05.043491 DQM Delay:
4219 22:21:05.043566 DQM0 = 34, DQM1 = 29
4220 22:21:05.046961 DQ Delay:
4221 22:21:05.049673 DQ0 =36, DQ1 =36, DQ2 =36, DQ3 =32
4222 22:21:05.049777 DQ4 =32, DQ5 =20, DQ6 =40, DQ7 =44
4223 22:21:05.053385 DQ8 =20, DQ9 =16, DQ10 =32, DQ11 =24
4224 22:21:05.059916 DQ12 =32, DQ13 =32, DQ14 =40, DQ15 =36
4225 22:21:05.060028
4226 22:21:05.060128
4227 22:21:05.066630 [DQSOSCAuto] RK0, (LSB)MR18= 0x3939, (MSB)MR19= 0x808, tDQSOscB0 = 399 ps tDQSOscB1 = 399 ps
4228 22:21:05.069651 CH0 RK0: MR19=808, MR18=3939
4229 22:21:05.076234 CH0_RK0: MR19=0x808, MR18=0x3939, DQSOSC=399, MR23=63, INC=164, DEC=109
4230 22:21:05.076347
4231 22:21:05.079706 ----->DramcWriteLeveling(PI) begin...
4232 22:21:05.079813 ==
4233 22:21:05.082805 Dram Type= 6, Freq= 0, CH_0, rank 1
4234 22:21:05.086051 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4235 22:21:05.086159 ==
4236 22:21:05.089655 Write leveling (Byte 0): 33 => 33
4237 22:21:05.092710 Write leveling (Byte 1): 32 => 32
4238 22:21:05.095875 DramcWriteLeveling(PI) end<-----
4239 22:21:05.095988
4240 22:21:05.096084 ==
4241 22:21:05.099376 Dram Type= 6, Freq= 0, CH_0, rank 1
4242 22:21:05.102267 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4243 22:21:05.105556 ==
4244 22:21:05.105670 [Gating] SW mode calibration
4245 22:21:05.115463 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4246 22:21:05.119008 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4247 22:21:05.122363 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4248 22:21:05.128927 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4249 22:21:05.132032 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4250 22:21:05.135698 0 9 12 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 0)
4251 22:21:05.141922 0 9 16 | B1->B0 | 2e2e 2424 | 1 0 | (1 0) (0 0)
4252 22:21:05.145706 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4253 22:21:05.148749 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4254 22:21:05.155282 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4255 22:21:05.158491 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4256 22:21:05.162221 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4257 22:21:05.168499 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4258 22:21:05.171930 0 10 12 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
4259 22:21:05.175627 0 10 16 | B1->B0 | 3838 4545 | 1 0 | (0 0) (0 0)
4260 22:21:05.181856 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4261 22:21:05.185302 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4262 22:21:05.188398 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4263 22:21:05.195164 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4264 22:21:05.198270 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4265 22:21:05.201974 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4266 22:21:05.208344 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4267 22:21:05.211637 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4268 22:21:05.214968 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4269 22:21:05.221416 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4270 22:21:05.224891 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4271 22:21:05.227845 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4272 22:21:05.234512 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4273 22:21:05.238233 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4274 22:21:05.241224 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4275 22:21:05.247556 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4276 22:21:05.251322 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4277 22:21:05.254357 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4278 22:21:05.260970 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4279 22:21:05.264013 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4280 22:21:05.267576 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4281 22:21:05.274087 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4282 22:21:05.277387 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4283 22:21:05.281050 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4284 22:21:05.284296 Total UI for P1: 0, mck2ui 16
4285 22:21:05.287120 best dqsien dly found for B0: ( 0, 13, 14)
4286 22:21:05.293613 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4287 22:21:05.293726 Total UI for P1: 0, mck2ui 16
4288 22:21:05.300430 best dqsien dly found for B1: ( 0, 13, 16)
4289 22:21:05.303579 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4290 22:21:05.307328 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4291 22:21:05.307415
4292 22:21:05.310289 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4293 22:21:05.313871 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4294 22:21:05.316762 [Gating] SW calibration Done
4295 22:21:05.316848 ==
4296 22:21:05.320308 Dram Type= 6, Freq= 0, CH_0, rank 1
4297 22:21:05.323249 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4298 22:21:05.323365 ==
4299 22:21:05.327152 RX Vref Scan: 0
4300 22:21:05.327237
4301 22:21:05.327304 RX Vref 0 -> 0, step: 1
4302 22:21:05.330146
4303 22:21:05.330219 RX Delay -230 -> 252, step: 16
4304 22:21:05.336699 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4305 22:21:05.340070 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4306 22:21:05.343299 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4307 22:21:05.346291 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4308 22:21:05.353130 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4309 22:21:05.356173 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4310 22:21:05.359279 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4311 22:21:05.362805 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4312 22:21:05.369593 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4313 22:21:05.372679 iDelay=218, Bit 9, Center 9 (-150 ~ 169) 320
4314 22:21:05.376127 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4315 22:21:05.379307 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4316 22:21:05.382624 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4317 22:21:05.389156 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4318 22:21:05.392327 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4319 22:21:05.395994 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4320 22:21:05.396079 ==
4321 22:21:05.399010 Dram Type= 6, Freq= 0, CH_0, rank 1
4322 22:21:05.405858 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4323 22:21:05.405944 ==
4324 22:21:05.406011 DQS Delay:
4325 22:21:05.408890 DQS0 = 0, DQS1 = 0
4326 22:21:05.409009 DQM Delay:
4327 22:21:05.409115 DQM0 = 36, DQM1 = 29
4328 22:21:05.412767 DQ Delay:
4329 22:21:05.415911 DQ0 =33, DQ1 =33, DQ2 =33, DQ3 =33
4330 22:21:05.419165 DQ4 =33, DQ5 =25, DQ6 =49, DQ7 =49
4331 22:21:05.422534 DQ8 =25, DQ9 =9, DQ10 =33, DQ11 =25
4332 22:21:05.425491 DQ12 =33, DQ13 =33, DQ14 =41, DQ15 =33
4333 22:21:05.425609
4334 22:21:05.425715
4335 22:21:05.425813 ==
4336 22:21:05.428971 Dram Type= 6, Freq= 0, CH_0, rank 1
4337 22:21:05.431957 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4338 22:21:05.432065 ==
4339 22:21:05.432160
4340 22:21:05.432225
4341 22:21:05.435301 TX Vref Scan disable
4342 22:21:05.435385 == TX Byte 0 ==
4343 22:21:05.442061 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4344 22:21:05.445544 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4345 22:21:05.448681 == TX Byte 1 ==
4346 22:21:05.451887 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4347 22:21:05.455039 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4348 22:21:05.455124 ==
4349 22:21:05.458709 Dram Type= 6, Freq= 0, CH_0, rank 1
4350 22:21:05.461553 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4351 22:21:05.465300 ==
4352 22:21:05.465385
4353 22:21:05.465451
4354 22:21:05.465512 TX Vref Scan disable
4355 22:21:05.468770 == TX Byte 0 ==
4356 22:21:05.472390 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4357 22:21:05.478607 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4358 22:21:05.478803 == TX Byte 1 ==
4359 22:21:05.482140 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4360 22:21:05.488414 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4361 22:21:05.488595
4362 22:21:05.488704 [DATLAT]
4363 22:21:05.488811 Freq=600, CH0 RK1
4364 22:21:05.488910
4365 22:21:05.491937 DATLAT Default: 0x9
4366 22:21:05.495197 0, 0xFFFF, sum = 0
4367 22:21:05.495329 1, 0xFFFF, sum = 0
4368 22:21:05.498687 2, 0xFFFF, sum = 0
4369 22:21:05.498809 3, 0xFFFF, sum = 0
4370 22:21:05.501577 4, 0xFFFF, sum = 0
4371 22:21:05.501714 5, 0xFFFF, sum = 0
4372 22:21:05.505302 6, 0xFFFF, sum = 0
4373 22:21:05.505431 7, 0xFFFF, sum = 0
4374 22:21:05.508401 8, 0x0, sum = 1
4375 22:21:05.508521 9, 0x0, sum = 2
4376 22:21:05.511528 10, 0x0, sum = 3
4377 22:21:05.511651 11, 0x0, sum = 4
4378 22:21:05.511748 best_step = 9
4379 22:21:05.511840
4380 22:21:05.514693 ==
4381 22:21:05.518431 Dram Type= 6, Freq= 0, CH_0, rank 1
4382 22:21:05.521573 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4383 22:21:05.521715 ==
4384 22:21:05.521835 RX Vref Scan: 0
4385 22:21:05.521937
4386 22:21:05.525103 RX Vref 0 -> 0, step: 1
4387 22:21:05.525215
4388 22:21:05.528047 RX Delay -195 -> 252, step: 8
4389 22:21:05.534738 iDelay=205, Bit 0, Center 32 (-123 ~ 188) 312
4390 22:21:05.538286 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4391 22:21:05.541096 iDelay=205, Bit 2, Center 32 (-123 ~ 188) 312
4392 22:21:05.544667 iDelay=205, Bit 3, Center 28 (-131 ~ 188) 320
4393 22:21:05.547849 iDelay=205, Bit 4, Center 32 (-131 ~ 196) 328
4394 22:21:05.554847 iDelay=205, Bit 5, Center 24 (-131 ~ 180) 312
4395 22:21:05.558004 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4396 22:21:05.561061 iDelay=205, Bit 7, Center 44 (-115 ~ 204) 320
4397 22:21:05.564186 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4398 22:21:05.570850 iDelay=205, Bit 9, Center 12 (-139 ~ 164) 304
4399 22:21:05.574575 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4400 22:21:05.577535 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4401 22:21:05.580673 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4402 22:21:05.587375 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4403 22:21:05.591048 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4404 22:21:05.593994 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4405 22:21:05.594128 ==
4406 22:21:05.597495 Dram Type= 6, Freq= 0, CH_0, rank 1
4407 22:21:05.603671 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4408 22:21:05.603792 ==
4409 22:21:05.603895 DQS Delay:
4410 22:21:05.603994 DQS0 = 0, DQS1 = 0
4411 22:21:05.607372 DQM Delay:
4412 22:21:05.607482 DQM0 = 34, DQM1 = 28
4413 22:21:05.610757 DQ Delay:
4414 22:21:05.613879 DQ0 =32, DQ1 =36, DQ2 =32, DQ3 =28
4415 22:21:05.617002 DQ4 =32, DQ5 =24, DQ6 =44, DQ7 =44
4416 22:21:05.620200 DQ8 =20, DQ9 =12, DQ10 =28, DQ11 =20
4417 22:21:05.623717 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4418 22:21:05.623826
4419 22:21:05.623922
4420 22:21:05.630585 [DQSOSCAuto] RK1, (LSB)MR18= 0x6736, (MSB)MR19= 0x808, tDQSOscB0 = 399 ps tDQSOscB1 = 390 ps
4421 22:21:05.633427 CH0 RK1: MR19=808, MR18=6736
4422 22:21:05.640098 CH0_RK1: MR19=0x808, MR18=0x6736, DQSOSC=390, MR23=63, INC=172, DEC=114
4423 22:21:05.643609 [RxdqsGatingPostProcess] freq 600
4424 22:21:05.646533 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4425 22:21:05.650207 Pre-setting of DQS Precalculation
4426 22:21:05.656793 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4427 22:21:05.656925 ==
4428 22:21:05.659603 Dram Type= 6, Freq= 0, CH_1, rank 0
4429 22:21:05.663161 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4430 22:21:05.663279 ==
4431 22:21:05.669760 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4432 22:21:05.676471 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4433 22:21:05.679542 [CA 0] Center 36 (6~66) winsize 61
4434 22:21:05.682621 [CA 1] Center 36 (6~66) winsize 61
4435 22:21:05.686283 [CA 2] Center 34 (4~65) winsize 62
4436 22:21:05.689272 [CA 3] Center 34 (4~65) winsize 62
4437 22:21:05.692996 [CA 4] Center 34 (4~65) winsize 62
4438 22:21:05.696101 [CA 5] Center 33 (3~64) winsize 62
4439 22:21:05.696240
4440 22:21:05.699068 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4441 22:21:05.699175
4442 22:21:05.702548 [CATrainingPosCal] consider 1 rank data
4443 22:21:05.706075 u2DelayCellTimex100 = 270/100 ps
4444 22:21:05.709202 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4445 22:21:05.712211 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4446 22:21:05.715759 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4447 22:21:05.718771 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4448 22:21:05.722487 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4449 22:21:05.725572 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4450 22:21:05.728732
4451 22:21:05.732414 CA PerBit enable=1, Macro0, CA PI delay=33
4452 22:21:05.732504
4453 22:21:05.735435 [CBTSetCACLKResult] CA Dly = 33
4454 22:21:05.735584 CS Dly: 5 (0~36)
4455 22:21:05.735666 ==
4456 22:21:05.738540 Dram Type= 6, Freq= 0, CH_1, rank 1
4457 22:21:05.742128 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4458 22:21:05.745400 ==
4459 22:21:05.748639 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4460 22:21:05.755275 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4461 22:21:05.758775 [CA 0] Center 36 (6~66) winsize 61
4462 22:21:05.761955 [CA 1] Center 35 (5~66) winsize 62
4463 22:21:05.764845 [CA 2] Center 34 (4~65) winsize 62
4464 22:21:05.768084 [CA 3] Center 34 (3~65) winsize 63
4465 22:21:05.771553 [CA 4] Center 34 (4~65) winsize 62
4466 22:21:05.774678 [CA 5] Center 33 (3~64) winsize 62
4467 22:21:05.774766
4468 22:21:05.778457 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4469 22:21:05.778553
4470 22:21:05.781391 [CATrainingPosCal] consider 2 rank data
4471 22:21:05.785029 u2DelayCellTimex100 = 270/100 ps
4472 22:21:05.788016 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4473 22:21:05.791687 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4474 22:21:05.797836 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4475 22:21:05.801585 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4476 22:21:05.804648 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4477 22:21:05.808380 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4478 22:21:05.808477
4479 22:21:05.811172 CA PerBit enable=1, Macro0, CA PI delay=33
4480 22:21:05.811272
4481 22:21:05.814850 [CBTSetCACLKResult] CA Dly = 33
4482 22:21:05.814946 CS Dly: 5 (0~36)
4483 22:21:05.815015
4484 22:21:05.817831 ----->DramcWriteLeveling(PI) begin...
4485 22:21:05.821300 ==
4486 22:21:05.824365 Dram Type= 6, Freq= 0, CH_1, rank 0
4487 22:21:05.827468 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4488 22:21:05.827554 ==
4489 22:21:05.830656 Write leveling (Byte 0): 29 => 29
4490 22:21:05.834353 Write leveling (Byte 1): 31 => 31
4491 22:21:05.837444 DramcWriteLeveling(PI) end<-----
4492 22:21:05.837527
4493 22:21:05.837593 ==
4494 22:21:05.840455 Dram Type= 6, Freq= 0, CH_1, rank 0
4495 22:21:05.844232 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4496 22:21:05.844309 ==
4497 22:21:05.847272 [Gating] SW mode calibration
4498 22:21:05.853684 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4499 22:21:05.860612 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4500 22:21:05.864077 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4501 22:21:05.867217 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4502 22:21:05.873378 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4503 22:21:05.876768 0 9 12 | B1->B0 | 3030 3030 | 0 0 | (1 0) (1 1)
4504 22:21:05.880022 0 9 16 | B1->B0 | 2525 2727 | 0 0 | (0 0) (1 0)
4505 22:21:05.886583 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4506 22:21:05.890186 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4507 22:21:05.893705 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4508 22:21:05.900015 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4509 22:21:05.903757 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4510 22:21:05.906845 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4511 22:21:05.913364 0 10 12 | B1->B0 | 2e2e 2f2f | 0 0 | (0 0) (0 0)
4512 22:21:05.916415 0 10 16 | B1->B0 | 4343 4444 | 0 0 | (0 0) (1 1)
4513 22:21:05.920083 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4514 22:21:05.926606 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4515 22:21:05.929652 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4516 22:21:05.932740 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4517 22:21:05.939471 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4518 22:21:05.942592 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4519 22:21:05.946365 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4520 22:21:05.953184 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4521 22:21:05.956097 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4522 22:21:05.959470 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4523 22:21:05.965600 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4524 22:21:05.969010 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4525 22:21:05.972607 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4526 22:21:05.978847 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4527 22:21:05.982310 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4528 22:21:05.985887 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4529 22:21:05.992012 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4530 22:21:05.995445 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4531 22:21:05.998559 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4532 22:21:06.005283 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4533 22:21:06.008959 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4534 22:21:06.012082 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4535 22:21:06.018740 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4536 22:21:06.021711 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4537 22:21:06.025272 Total UI for P1: 0, mck2ui 16
4538 22:21:06.028339 best dqsien dly found for B0: ( 0, 13, 14)
4539 22:21:06.031882 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4540 22:21:06.035405 Total UI for P1: 0, mck2ui 16
4541 22:21:06.038491 best dqsien dly found for B1: ( 0, 13, 16)
4542 22:21:06.042127 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4543 22:21:06.045389 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4544 22:21:06.045474
4545 22:21:06.051443 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4546 22:21:06.055117 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4547 22:21:06.057968 [Gating] SW calibration Done
4548 22:21:06.058053 ==
4549 22:21:06.061752 Dram Type= 6, Freq= 0, CH_1, rank 0
4550 22:21:06.064731 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4551 22:21:06.064817 ==
4552 22:21:06.064883 RX Vref Scan: 0
4553 22:21:06.068421
4554 22:21:06.068516 RX Vref 0 -> 0, step: 1
4555 22:21:06.068581
4556 22:21:06.071338 RX Delay -230 -> 252, step: 16
4557 22:21:06.074699 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4558 22:21:06.081095 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4559 22:21:06.084468 iDelay=218, Bit 2, Center 25 (-150 ~ 201) 352
4560 22:21:06.087714 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4561 22:21:06.091140 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4562 22:21:06.094564 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4563 22:21:06.101332 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4564 22:21:06.104476 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4565 22:21:06.107843 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4566 22:21:06.111046 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4567 22:21:06.117279 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4568 22:21:06.120924 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4569 22:21:06.123919 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4570 22:21:06.127427 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4571 22:21:06.133944 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4572 22:21:06.137036 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4573 22:21:06.137116 ==
4574 22:21:06.140428 Dram Type= 6, Freq= 0, CH_1, rank 0
4575 22:21:06.143534 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4576 22:21:06.143612 ==
4577 22:21:06.147214 DQS Delay:
4578 22:21:06.147294 DQS0 = 0, DQS1 = 0
4579 22:21:06.150288 DQM Delay:
4580 22:21:06.150388 DQM0 = 42, DQM1 = 33
4581 22:21:06.150476 DQ Delay:
4582 22:21:06.153434 DQ0 =49, DQ1 =41, DQ2 =25, DQ3 =41
4583 22:21:06.157182 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =41
4584 22:21:06.160216 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4585 22:21:06.164151 DQ12 =41, DQ13 =49, DQ14 =41, DQ15 =41
4586 22:21:06.164233
4587 22:21:06.164300
4588 22:21:06.166726 ==
4589 22:21:06.166855 Dram Type= 6, Freq= 0, CH_1, rank 0
4590 22:21:06.173562 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4591 22:21:06.173642 ==
4592 22:21:06.173724
4593 22:21:06.173787
4594 22:21:06.176583 TX Vref Scan disable
4595 22:21:06.176687 == TX Byte 0 ==
4596 22:21:06.183271 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4597 22:21:06.186434 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4598 22:21:06.186520 == TX Byte 1 ==
4599 22:21:06.193268 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4600 22:21:06.195980 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4601 22:21:06.196067 ==
4602 22:21:06.199572 Dram Type= 6, Freq= 0, CH_1, rank 0
4603 22:21:06.202949 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4604 22:21:06.203027 ==
4605 22:21:06.203133
4606 22:21:06.203223
4607 22:21:06.206304 TX Vref Scan disable
4608 22:21:06.209413 == TX Byte 0 ==
4609 22:21:06.212464 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4610 22:21:06.215960 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4611 22:21:06.219113 == TX Byte 1 ==
4612 22:21:06.222811 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4613 22:21:06.229605 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4614 22:21:06.229689
4615 22:21:06.229756 [DATLAT]
4616 22:21:06.229817 Freq=600, CH1 RK0
4617 22:21:06.229877
4618 22:21:06.232381 DATLAT Default: 0x9
4619 22:21:06.232491 0, 0xFFFF, sum = 0
4620 22:21:06.235811 1, 0xFFFF, sum = 0
4621 22:21:06.235896 2, 0xFFFF, sum = 0
4622 22:21:06.239404 3, 0xFFFF, sum = 0
4623 22:21:06.242462 4, 0xFFFF, sum = 0
4624 22:21:06.242578 5, 0xFFFF, sum = 0
4625 22:21:06.245889 6, 0xFFFF, sum = 0
4626 22:21:06.245975 7, 0xFFFF, sum = 0
4627 22:21:06.248970 8, 0x0, sum = 1
4628 22:21:06.249055 9, 0x0, sum = 2
4629 22:21:06.249122 10, 0x0, sum = 3
4630 22:21:06.252039 11, 0x0, sum = 4
4631 22:21:06.252124 best_step = 9
4632 22:21:06.252192
4633 22:21:06.252254 ==
4634 22:21:06.255814 Dram Type= 6, Freq= 0, CH_1, rank 0
4635 22:21:06.262177 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4636 22:21:06.262262 ==
4637 22:21:06.262329 RX Vref Scan: 1
4638 22:21:06.262396
4639 22:21:06.265834 RX Vref 0 -> 0, step: 1
4640 22:21:06.265918
4641 22:21:06.268609 RX Delay -195 -> 252, step: 8
4642 22:21:06.268691
4643 22:21:06.271703 Set Vref, RX VrefLevel [Byte0]: 56
4644 22:21:06.275416 [Byte1]: 53
4645 22:21:06.275523
4646 22:21:06.278728 Final RX Vref Byte 0 = 56 to rank0
4647 22:21:06.281597 Final RX Vref Byte 1 = 53 to rank0
4648 22:21:06.285134 Final RX Vref Byte 0 = 56 to rank1
4649 22:21:06.288676 Final RX Vref Byte 1 = 53 to rank1==
4650 22:21:06.291655 Dram Type= 6, Freq= 0, CH_1, rank 0
4651 22:21:06.295079 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4652 22:21:06.298063 ==
4653 22:21:06.298163 DQS Delay:
4654 22:21:06.298241 DQS0 = 0, DQS1 = 0
4655 22:21:06.301544 DQM Delay:
4656 22:21:06.301626 DQM0 = 39, DQM1 = 27
4657 22:21:06.304904 DQ Delay:
4658 22:21:06.308412 DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =36
4659 22:21:06.308495 DQ4 =36, DQ5 =48, DQ6 =48, DQ7 =36
4660 22:21:06.311288 DQ8 =12, DQ9 =16, DQ10 =28, DQ11 =20
4661 22:21:06.318001 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4662 22:21:06.318087
4663 22:21:06.318153
4664 22:21:06.324554 [DQSOSCAuto] RK0, (LSB)MR18= 0x222f, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 403 ps
4665 22:21:06.327976 CH1 RK0: MR19=808, MR18=222F
4666 22:21:06.334443 CH1_RK0: MR19=0x808, MR18=0x222F, DQSOSC=400, MR23=63, INC=163, DEC=109
4667 22:21:06.334527
4668 22:21:06.337611 ----->DramcWriteLeveling(PI) begin...
4669 22:21:06.337696 ==
4670 22:21:06.341111 Dram Type= 6, Freq= 0, CH_1, rank 1
4671 22:21:06.344618 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4672 22:21:06.344701 ==
4673 22:21:06.347622 Write leveling (Byte 0): 28 => 28
4674 22:21:06.351128 Write leveling (Byte 1): 28 => 28
4675 22:21:06.354048 DramcWriteLeveling(PI) end<-----
4676 22:21:06.354147
4677 22:21:06.354212 ==
4678 22:21:06.357845 Dram Type= 6, Freq= 0, CH_1, rank 1
4679 22:21:06.360824 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4680 22:21:06.364012 ==
4681 22:21:06.364095 [Gating] SW mode calibration
4682 22:21:06.374130 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4683 22:21:06.377181 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4684 22:21:06.380885 0 9 0 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
4685 22:21:06.386982 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4686 22:21:06.390429 0 9 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
4687 22:21:06.393996 0 9 12 | B1->B0 | 3030 2f2f | 1 0 | (1 0) (0 0)
4688 22:21:06.400423 0 9 16 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
4689 22:21:06.403863 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4690 22:21:06.406706 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4691 22:21:06.413768 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4692 22:21:06.417176 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4693 22:21:06.420131 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4694 22:21:06.426550 0 10 8 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
4695 22:21:06.430269 0 10 12 | B1->B0 | 2f2f 4545 | 0 1 | (1 1) (0 0)
4696 22:21:06.433211 0 10 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
4697 22:21:06.440021 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4698 22:21:06.443014 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4699 22:21:06.446541 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4700 22:21:06.452973 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4701 22:21:06.456529 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4702 22:21:06.459546 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4703 22:21:06.466365 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4704 22:21:06.469306 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4705 22:21:06.472865 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4706 22:21:06.479631 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4707 22:21:06.482741 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4708 22:21:06.485853 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4709 22:21:06.492508 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4710 22:21:06.496084 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4711 22:21:06.499154 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4712 22:21:06.505940 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4713 22:21:06.509233 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4714 22:21:06.512669 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4715 22:21:06.518848 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4716 22:21:06.522245 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4717 22:21:06.525552 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4718 22:21:06.532457 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4719 22:21:06.535652 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4720 22:21:06.538712 Total UI for P1: 0, mck2ui 16
4721 22:21:06.542507 best dqsien dly found for B0: ( 0, 13, 8)
4722 22:21:06.545585 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4723 22:21:06.549068 Total UI for P1: 0, mck2ui 16
4724 22:21:06.552141 best dqsien dly found for B1: ( 0, 13, 12)
4725 22:21:06.555273 best DQS0 dly(MCK, UI, PI) = (0, 13, 8)
4726 22:21:06.558906 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4727 22:21:06.559015
4728 22:21:06.565400 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 8)
4729 22:21:06.568463 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4730 22:21:06.571559 [Gating] SW calibration Done
4731 22:21:06.571659 ==
4732 22:21:06.575270 Dram Type= 6, Freq= 0, CH_1, rank 1
4733 22:21:06.578251 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4734 22:21:06.578357 ==
4735 22:21:06.578448 RX Vref Scan: 0
4736 22:21:06.578547
4737 22:21:06.581866 RX Vref 0 -> 0, step: 1
4738 22:21:06.581967
4739 22:21:06.584938 RX Delay -230 -> 252, step: 16
4740 22:21:06.587995 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4741 22:21:06.594779 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4742 22:21:06.597847 iDelay=218, Bit 2, Center 17 (-150 ~ 185) 336
4743 22:21:06.601423 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4744 22:21:06.604510 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4745 22:21:06.608280 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4746 22:21:06.614468 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4747 22:21:06.617969 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4748 22:21:06.620835 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4749 22:21:06.624409 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4750 22:21:06.630689 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4751 22:21:06.634169 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4752 22:21:06.637582 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4753 22:21:06.640539 iDelay=218, Bit 13, Center 41 (-134 ~ 217) 352
4754 22:21:06.647320 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4755 22:21:06.650842 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4756 22:21:06.650940 ==
4757 22:21:06.653828 Dram Type= 6, Freq= 0, CH_1, rank 1
4758 22:21:06.657491 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4759 22:21:06.657575 ==
4760 22:21:06.660538 DQS Delay:
4761 22:21:06.660621 DQS0 = 0, DQS1 = 0
4762 22:21:06.660723 DQM Delay:
4763 22:21:06.663513 DQM0 = 35, DQM1 = 29
4764 22:21:06.663595 DQ Delay:
4765 22:21:06.667176 DQ0 =33, DQ1 =33, DQ2 =17, DQ3 =33
4766 22:21:06.670679 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4767 22:21:06.673813 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4768 22:21:06.676831 DQ12 =33, DQ13 =41, DQ14 =33, DQ15 =33
4769 22:21:06.676920
4770 22:21:06.676986
4771 22:21:06.677050 ==
4772 22:21:06.680547 Dram Type= 6, Freq= 0, CH_1, rank 1
4773 22:21:06.687065 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4774 22:21:06.687148 ==
4775 22:21:06.687214
4776 22:21:06.687274
4777 22:21:06.687332 TX Vref Scan disable
4778 22:21:06.690778 == TX Byte 0 ==
4779 22:21:06.694437 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4780 22:21:06.701242 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4781 22:21:06.701327 == TX Byte 1 ==
4782 22:21:06.704173 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4783 22:21:06.710997 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4784 22:21:06.711081 ==
4785 22:21:06.714116 Dram Type= 6, Freq= 0, CH_1, rank 1
4786 22:21:06.717343 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4787 22:21:06.717427 ==
4788 22:21:06.717492
4789 22:21:06.717553
4790 22:21:06.720953 TX Vref Scan disable
4791 22:21:06.723709 == TX Byte 0 ==
4792 22:21:06.727096 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4793 22:21:06.730435 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4794 22:21:06.733967 == TX Byte 1 ==
4795 22:21:06.736857 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4796 22:21:06.740421 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4797 22:21:06.740526
4798 22:21:06.740628 [DATLAT]
4799 22:21:06.743383 Freq=600, CH1 RK1
4800 22:21:06.743466
4801 22:21:06.746854 DATLAT Default: 0x9
4802 22:21:06.746971 0, 0xFFFF, sum = 0
4803 22:21:06.750512 1, 0xFFFF, sum = 0
4804 22:21:06.750627 2, 0xFFFF, sum = 0
4805 22:21:06.753612 3, 0xFFFF, sum = 0
4806 22:21:06.753706 4, 0xFFFF, sum = 0
4807 22:21:06.757481 5, 0xFFFF, sum = 0
4808 22:21:06.757593 6, 0xFFFF, sum = 0
4809 22:21:06.760308 7, 0xFFFF, sum = 0
4810 22:21:06.760386 8, 0x0, sum = 1
4811 22:21:06.763396 9, 0x0, sum = 2
4812 22:21:06.763501 10, 0x0, sum = 3
4813 22:21:06.766435 11, 0x0, sum = 4
4814 22:21:06.766576 best_step = 9
4815 22:21:06.766689
4816 22:21:06.766787 ==
4817 22:21:06.769995 Dram Type= 6, Freq= 0, CH_1, rank 1
4818 22:21:06.773023 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4819 22:21:06.773175 ==
4820 22:21:06.776791 RX Vref Scan: 0
4821 22:21:06.776891
4822 22:21:06.779662 RX Vref 0 -> 0, step: 1
4823 22:21:06.779762
4824 22:21:06.779897 RX Delay -195 -> 252, step: 8
4825 22:21:06.788233 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4826 22:21:06.791287 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4827 22:21:06.794367 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4828 22:21:06.797834 iDelay=205, Bit 3, Center 28 (-131 ~ 188) 320
4829 22:21:06.803988 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4830 22:21:06.807528 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4831 22:21:06.811224 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4832 22:21:06.814296 iDelay=205, Bit 7, Center 28 (-131 ~ 188) 320
4833 22:21:06.820908 iDelay=205, Bit 8, Center 16 (-147 ~ 180) 328
4834 22:21:06.823975 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4835 22:21:06.827506 iDelay=205, Bit 10, Center 32 (-131 ~ 196) 328
4836 22:21:06.830933 iDelay=205, Bit 11, Center 24 (-139 ~ 188) 328
4837 22:21:06.837453 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4838 22:21:06.840609 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4839 22:21:06.843596 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4840 22:21:06.847165 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4841 22:21:06.847243 ==
4842 22:21:06.850634 Dram Type= 6, Freq= 0, CH_1, rank 1
4843 22:21:06.857261 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4844 22:21:06.857344 ==
4845 22:21:06.857417 DQS Delay:
4846 22:21:06.860255 DQS0 = 0, DQS1 = 0
4847 22:21:06.860333 DQM Delay:
4848 22:21:06.860398 DQM0 = 35, DQM1 = 29
4849 22:21:06.863952 DQ Delay:
4850 22:21:06.867059 DQ0 =40, DQ1 =32, DQ2 =24, DQ3 =28
4851 22:21:06.870065 DQ4 =36, DQ5 =48, DQ6 =44, DQ7 =28
4852 22:21:06.873714 DQ8 =16, DQ9 =20, DQ10 =32, DQ11 =24
4853 22:21:06.876595 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4854 22:21:06.876677
4855 22:21:06.876742
4856 22:21:06.883288 [DQSOSCAuto] RK1, (LSB)MR18= 0x3a59, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 398 ps
4857 22:21:06.886595 CH1 RK1: MR19=808, MR18=3A59
4858 22:21:06.893173 CH1_RK1: MR19=0x808, MR18=0x3A59, DQSOSC=393, MR23=63, INC=169, DEC=113
4859 22:21:06.896362 [RxdqsGatingPostProcess] freq 600
4860 22:21:06.903029 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4861 22:21:06.903116 Pre-setting of DQS Precalculation
4862 22:21:06.909854 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4863 22:21:06.916435 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4864 22:21:06.922643 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4865 22:21:06.922726
4866 22:21:06.922790
4867 22:21:06.926377 [Calibration Summary] 1200 Mbps
4868 22:21:06.929347 CH 0, Rank 0
4869 22:21:06.929443 SW Impedance : PASS
4870 22:21:06.932850 DUTY Scan : NO K
4871 22:21:06.936311 ZQ Calibration : PASS
4872 22:21:06.936422 Jitter Meter : NO K
4873 22:21:06.939455 CBT Training : PASS
4874 22:21:06.942728 Write leveling : PASS
4875 22:21:06.942861 RX DQS gating : PASS
4876 22:21:06.946050 RX DQ/DQS(RDDQC) : PASS
4877 22:21:06.946141 TX DQ/DQS : PASS
4878 22:21:06.948994 RX DATLAT : PASS
4879 22:21:06.952403 RX DQ/DQS(Engine): PASS
4880 22:21:06.952480 TX OE : NO K
4881 22:21:06.955839 All Pass.
4882 22:21:06.955923
4883 22:21:06.955995 CH 0, Rank 1
4884 22:21:06.959345 SW Impedance : PASS
4885 22:21:06.959456 DUTY Scan : NO K
4886 22:21:06.962475 ZQ Calibration : PASS
4887 22:21:06.965536 Jitter Meter : NO K
4888 22:21:06.965615 CBT Training : PASS
4889 22:21:06.969216 Write leveling : PASS
4890 22:21:06.972276 RX DQS gating : PASS
4891 22:21:06.972350 RX DQ/DQS(RDDQC) : PASS
4892 22:21:06.975468 TX DQ/DQS : PASS
4893 22:21:06.978555 RX DATLAT : PASS
4894 22:21:06.978630 RX DQ/DQS(Engine): PASS
4895 22:21:06.982131 TX OE : NO K
4896 22:21:06.982238 All Pass.
4897 22:21:06.982314
4898 22:21:06.985386 CH 1, Rank 0
4899 22:21:06.985496 SW Impedance : PASS
4900 22:21:06.988741 DUTY Scan : NO K
4901 22:21:06.991775 ZQ Calibration : PASS
4902 22:21:06.991854 Jitter Meter : NO K
4903 22:21:06.995330 CBT Training : PASS
4904 22:21:06.998394 Write leveling : PASS
4905 22:21:06.998474 RX DQS gating : PASS
4906 22:21:07.002149 RX DQ/DQS(RDDQC) : PASS
4907 22:21:07.005150 TX DQ/DQS : PASS
4908 22:21:07.005239 RX DATLAT : PASS
4909 22:21:07.008266 RX DQ/DQS(Engine): PASS
4910 22:21:07.011977 TX OE : NO K
4911 22:21:07.012052 All Pass.
4912 22:21:07.012121
4913 22:21:07.012184 CH 1, Rank 1
4914 22:21:07.015033 SW Impedance : PASS
4915 22:21:07.018613 DUTY Scan : NO K
4916 22:21:07.018686 ZQ Calibration : PASS
4917 22:21:07.021710 Jitter Meter : NO K
4918 22:21:07.024874 CBT Training : PASS
4919 22:21:07.024959 Write leveling : PASS
4920 22:21:07.027907 RX DQS gating : PASS
4921 22:21:07.031681 RX DQ/DQS(RDDQC) : PASS
4922 22:21:07.031765 TX DQ/DQS : PASS
4923 22:21:07.034693 RX DATLAT : PASS
4924 22:21:07.037710 RX DQ/DQS(Engine): PASS
4925 22:21:07.037822 TX OE : NO K
4926 22:21:07.037929 All Pass.
4927 22:21:07.041117
4928 22:21:07.041201 DramC Write-DBI off
4929 22:21:07.044505 PER_BANK_REFRESH: Hybrid Mode
4930 22:21:07.044591 TX_TRACKING: ON
4931 22:21:07.054170 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4932 22:21:07.057701 [FAST_K] Save calibration result to emmc
4933 22:21:07.061187 dramc_set_vcore_voltage set vcore to 662500
4934 22:21:07.064291 Read voltage for 933, 3
4935 22:21:07.064370 Vio18 = 0
4936 22:21:07.067746 Vcore = 662500
4937 22:21:07.067831 Vdram = 0
4938 22:21:07.067897 Vddq = 0
4939 22:21:07.067961 Vmddr = 0
4940 22:21:07.073874 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4941 22:21:07.080576 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4942 22:21:07.080662 MEM_TYPE=3, freq_sel=17
4943 22:21:07.084254 sv_algorithm_assistance_LP4_1600
4944 22:21:07.090527 ============ PULL DRAM RESETB DOWN ============
4945 22:21:07.093698 ========== PULL DRAM RESETB DOWN end =========
4946 22:21:07.097213 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4947 22:21:07.100179 ===================================
4948 22:21:07.103739 LPDDR4 DRAM CONFIGURATION
4949 22:21:07.106918 ===================================
4950 22:21:07.107022 EX_ROW_EN[0] = 0x0
4951 22:21:07.110604 EX_ROW_EN[1] = 0x0
4952 22:21:07.113755 LP4Y_EN = 0x0
4953 22:21:07.113864 WORK_FSP = 0x0
4954 22:21:07.116830 WL = 0x3
4955 22:21:07.116913 RL = 0x3
4956 22:21:07.120455 BL = 0x2
4957 22:21:07.120564 RPST = 0x0
4958 22:21:07.123478 RD_PRE = 0x0
4959 22:21:07.123578 WR_PRE = 0x1
4960 22:21:07.127196 WR_PST = 0x0
4961 22:21:07.127297 DBI_WR = 0x0
4962 22:21:07.130262 DBI_RD = 0x0
4963 22:21:07.130359 OTF = 0x1
4964 22:21:07.133300 ===================================
4965 22:21:07.136995 ===================================
4966 22:21:07.140034 ANA top config
4967 22:21:07.143876 ===================================
4968 22:21:07.143955 DLL_ASYNC_EN = 0
4969 22:21:07.146500 ALL_SLAVE_EN = 1
4970 22:21:07.149886 NEW_RANK_MODE = 1
4971 22:21:07.153252 DLL_IDLE_MODE = 1
4972 22:21:07.156644 LP45_APHY_COMB_EN = 1
4973 22:21:07.156753 TX_ODT_DIS = 1
4974 22:21:07.159881 NEW_8X_MODE = 1
4975 22:21:07.163339 ===================================
4976 22:21:07.166682 ===================================
4977 22:21:07.170000 data_rate = 1866
4978 22:21:07.172925 CKR = 1
4979 22:21:07.176375 DQ_P2S_RATIO = 8
4980 22:21:07.179923 ===================================
4981 22:21:07.183010 CA_P2S_RATIO = 8
4982 22:21:07.183099 DQ_CA_OPEN = 0
4983 22:21:07.186047 DQ_SEMI_OPEN = 0
4984 22:21:07.189633 CA_SEMI_OPEN = 0
4985 22:21:07.192740 CA_FULL_RATE = 0
4986 22:21:07.196251 DQ_CKDIV4_EN = 1
4987 22:21:07.199343 CA_CKDIV4_EN = 1
4988 22:21:07.199426 CA_PREDIV_EN = 0
4989 22:21:07.202922 PH8_DLY = 0
4990 22:21:07.206184 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4991 22:21:07.209543 DQ_AAMCK_DIV = 4
4992 22:21:07.212763 CA_AAMCK_DIV = 4
4993 22:21:07.215831 CA_ADMCK_DIV = 4
4994 22:21:07.215909 DQ_TRACK_CA_EN = 0
4995 22:21:07.219465 CA_PICK = 933
4996 22:21:07.222453 CA_MCKIO = 933
4997 22:21:07.225921 MCKIO_SEMI = 0
4998 22:21:07.229011 PLL_FREQ = 3732
4999 22:21:07.232787 DQ_UI_PI_RATIO = 32
5000 22:21:07.235823 CA_UI_PI_RATIO = 0
5001 22:21:07.239014 ===================================
5002 22:21:07.242594 ===================================
5003 22:21:07.242678 memory_type:LPDDR4
5004 22:21:07.245722 GP_NUM : 10
5005 22:21:07.249418 SRAM_EN : 1
5006 22:21:07.249501 MD32_EN : 0
5007 22:21:07.252317 ===================================
5008 22:21:07.255779 [ANA_INIT] >>>>>>>>>>>>>>
5009 22:21:07.259162 <<<<<< [CONFIGURE PHASE]: ANA_TX
5010 22:21:07.262117 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5011 22:21:07.265749 ===================================
5012 22:21:07.268615 data_rate = 1866,PCW = 0X8f00
5013 22:21:07.272129 ===================================
5014 22:21:07.275494 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5015 22:21:07.278805 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5016 22:21:07.285231 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5017 22:21:07.289072 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5018 22:21:07.292038 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5019 22:21:07.298769 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5020 22:21:07.298878 [ANA_INIT] flow start
5021 22:21:07.301794 [ANA_INIT] PLL >>>>>>>>
5022 22:21:07.305343 [ANA_INIT] PLL <<<<<<<<
5023 22:21:07.305427 [ANA_INIT] MIDPI >>>>>>>>
5024 22:21:07.308315 [ANA_INIT] MIDPI <<<<<<<<
5025 22:21:07.311862 [ANA_INIT] DLL >>>>>>>>
5026 22:21:07.311977 [ANA_INIT] flow end
5027 22:21:07.315289 ============ LP4 DIFF to SE enter ============
5028 22:21:07.321686 ============ LP4 DIFF to SE exit ============
5029 22:21:07.321772 [ANA_INIT] <<<<<<<<<<<<<
5030 22:21:07.324833 [Flow] Enable top DCM control >>>>>
5031 22:21:07.328394 [Flow] Enable top DCM control <<<<<
5032 22:21:07.331379 Enable DLL master slave shuffle
5033 22:21:07.338212 ==============================================================
5034 22:21:07.341313 Gating Mode config
5035 22:21:07.345065 ==============================================================
5036 22:21:07.348144 Config description:
5037 22:21:07.357944 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5038 22:21:07.364294 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5039 22:21:07.368143 SELPH_MODE 0: By rank 1: By Phase
5040 22:21:07.374489 ==============================================================
5041 22:21:07.377967 GAT_TRACK_EN = 1
5042 22:21:07.380781 RX_GATING_MODE = 2
5043 22:21:07.384142 RX_GATING_TRACK_MODE = 2
5044 22:21:07.384234 SELPH_MODE = 1
5045 22:21:07.387669 PICG_EARLY_EN = 1
5046 22:21:07.391062 VALID_LAT_VALUE = 1
5047 22:21:07.397821 ==============================================================
5048 22:21:07.400894 Enter into Gating configuration >>>>
5049 22:21:07.403964 Exit from Gating configuration <<<<
5050 22:21:07.407542 Enter into DVFS_PRE_config >>>>>
5051 22:21:07.417301 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5052 22:21:07.420782 Exit from DVFS_PRE_config <<<<<
5053 22:21:07.423651 Enter into PICG configuration >>>>
5054 22:21:07.427319 Exit from PICG configuration <<<<
5055 22:21:07.430269 [RX_INPUT] configuration >>>>>
5056 22:21:07.433937 [RX_INPUT] configuration <<<<<
5057 22:21:07.437455 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5058 22:21:07.444113 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5059 22:21:07.450571 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5060 22:21:07.456762 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5061 22:21:07.463915 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5062 22:21:07.470476 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5063 22:21:07.473684 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5064 22:21:07.477065 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5065 22:21:07.479793 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5066 22:21:07.486725 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5067 22:21:07.490110 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5068 22:21:07.493027 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5069 22:21:07.496436 ===================================
5070 22:21:07.499923 LPDDR4 DRAM CONFIGURATION
5071 22:21:07.503037 ===================================
5072 22:21:07.503120 EX_ROW_EN[0] = 0x0
5073 22:21:07.506773 EX_ROW_EN[1] = 0x0
5074 22:21:07.506895 LP4Y_EN = 0x0
5075 22:21:07.509872 WORK_FSP = 0x0
5076 22:21:07.512879 WL = 0x3
5077 22:21:07.512993 RL = 0x3
5078 22:21:07.516554 BL = 0x2
5079 22:21:07.516667 RPST = 0x0
5080 22:21:07.519577 RD_PRE = 0x0
5081 22:21:07.519660 WR_PRE = 0x1
5082 22:21:07.522766 WR_PST = 0x0
5083 22:21:07.522884 DBI_WR = 0x0
5084 22:21:07.526322 DBI_RD = 0x0
5085 22:21:07.526489 OTF = 0x1
5086 22:21:07.529309 ===================================
5087 22:21:07.532810 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5088 22:21:07.539320 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5089 22:21:07.543291 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5090 22:21:07.546175 ===================================
5091 22:21:07.549231 LPDDR4 DRAM CONFIGURATION
5092 22:21:07.552890 ===================================
5093 22:21:07.552973 EX_ROW_EN[0] = 0x10
5094 22:21:07.555992 EX_ROW_EN[1] = 0x0
5095 22:21:07.559100 LP4Y_EN = 0x0
5096 22:21:07.559183 WORK_FSP = 0x0
5097 22:21:07.562863 WL = 0x3
5098 22:21:07.562945 RL = 0x3
5099 22:21:07.566135 BL = 0x2
5100 22:21:07.566235 RPST = 0x0
5101 22:21:07.569390 RD_PRE = 0x0
5102 22:21:07.569508 WR_PRE = 0x1
5103 22:21:07.572384 WR_PST = 0x0
5104 22:21:07.572467 DBI_WR = 0x0
5105 22:21:07.576041 DBI_RD = 0x0
5106 22:21:07.576126 OTF = 0x1
5107 22:21:07.579122 ===================================
5108 22:21:07.585558 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5109 22:21:07.590197 nWR fixed to 30
5110 22:21:07.593020 [ModeRegInit_LP4] CH0 RK0
5111 22:21:07.593133 [ModeRegInit_LP4] CH0 RK1
5112 22:21:07.596455 [ModeRegInit_LP4] CH1 RK0
5113 22:21:07.599984 [ModeRegInit_LP4] CH1 RK1
5114 22:21:07.600068 match AC timing 9
5115 22:21:07.606077 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5116 22:21:07.609779 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5117 22:21:07.613149 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5118 22:21:07.619585 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5119 22:21:07.622457 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5120 22:21:07.622540 ==
5121 22:21:07.626122 Dram Type= 6, Freq= 0, CH_0, rank 0
5122 22:21:07.629117 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5123 22:21:07.632721 ==
5124 22:21:07.635753 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5125 22:21:07.642559 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5126 22:21:07.645721 [CA 0] Center 38 (7~69) winsize 63
5127 22:21:07.649377 [CA 1] Center 38 (8~69) winsize 62
5128 22:21:07.652576 [CA 2] Center 35 (5~65) winsize 61
5129 22:21:07.655659 [CA 3] Center 35 (5~65) winsize 61
5130 22:21:07.658727 [CA 4] Center 34 (4~65) winsize 62
5131 22:21:07.662447 [CA 5] Center 33 (3~64) winsize 62
5132 22:21:07.662530
5133 22:21:07.665566 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5134 22:21:07.665651
5135 22:21:07.668556 [CATrainingPosCal] consider 1 rank data
5136 22:21:07.671997 u2DelayCellTimex100 = 270/100 ps
5137 22:21:07.675495 CA0 delay=38 (7~69),Diff = 5 PI (31 cell)
5138 22:21:07.678631 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5139 22:21:07.685249 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5140 22:21:07.688299 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5141 22:21:07.691828 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5142 22:21:07.695343 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5143 22:21:07.695424
5144 22:21:07.698156 CA PerBit enable=1, Macro0, CA PI delay=33
5145 22:21:07.698243
5146 22:21:07.701531 [CBTSetCACLKResult] CA Dly = 33
5147 22:21:07.701636 CS Dly: 7 (0~38)
5148 22:21:07.704769 ==
5149 22:21:07.708285 Dram Type= 6, Freq= 0, CH_0, rank 1
5150 22:21:07.711116 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5151 22:21:07.711193 ==
5152 22:21:07.714649 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5153 22:21:07.721487 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5154 22:21:07.725051 [CA 0] Center 38 (8~69) winsize 62
5155 22:21:07.728497 [CA 1] Center 38 (8~69) winsize 62
5156 22:21:07.731710 [CA 2] Center 35 (5~66) winsize 62
5157 22:21:07.735148 [CA 3] Center 35 (5~66) winsize 62
5158 22:21:07.738254 [CA 4] Center 34 (3~65) winsize 63
5159 22:21:07.741913 [CA 5] Center 34 (3~65) winsize 63
5160 22:21:07.742008
5161 22:21:07.744982 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5162 22:21:07.745089
5163 22:21:07.748263 [CATrainingPosCal] consider 2 rank data
5164 22:21:07.751669 u2DelayCellTimex100 = 270/100 ps
5165 22:21:07.754799 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5166 22:21:07.761486 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5167 22:21:07.764587 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5168 22:21:07.767663 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5169 22:21:07.771358 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5170 22:21:07.774371 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5171 22:21:07.774478
5172 22:21:07.777911 CA PerBit enable=1, Macro0, CA PI delay=33
5173 22:21:07.777986
5174 22:21:07.781417 [CBTSetCACLKResult] CA Dly = 33
5175 22:21:07.784497 CS Dly: 7 (0~39)
5176 22:21:07.784596
5177 22:21:07.787956 ----->DramcWriteLeveling(PI) begin...
5178 22:21:07.788038 ==
5179 22:21:07.791312 Dram Type= 6, Freq= 0, CH_0, rank 0
5180 22:21:07.794306 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5181 22:21:07.794404 ==
5182 22:21:07.797982 Write leveling (Byte 0): 33 => 33
5183 22:21:07.801160 Write leveling (Byte 1): 32 => 32
5184 22:21:07.804621 DramcWriteLeveling(PI) end<-----
5185 22:21:07.804727
5186 22:21:07.804819 ==
5187 22:21:07.807430 Dram Type= 6, Freq= 0, CH_0, rank 0
5188 22:21:07.810836 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5189 22:21:07.810911 ==
5190 22:21:07.814025 [Gating] SW mode calibration
5191 22:21:07.820805 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5192 22:21:07.827349 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5193 22:21:07.830462 0 14 0 | B1->B0 | 2323 2d2d | 0 1 | (0 0) (1 1)
5194 22:21:07.834157 0 14 4 | B1->B0 | 2f2f 3434 | 1 1 | (0 0) (1 1)
5195 22:21:07.840573 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5196 22:21:07.844242 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5197 22:21:07.847337 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5198 22:21:07.853808 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5199 22:21:07.857247 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5200 22:21:07.860765 0 14 28 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
5201 22:21:07.866979 0 15 0 | B1->B0 | 3333 2e2e | 1 1 | (1 1) (1 0)
5202 22:21:07.870573 0 15 4 | B1->B0 | 2d2d 2323 | 0 0 | (0 0) (0 0)
5203 22:21:07.873625 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5204 22:21:07.880141 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5205 22:21:07.883642 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5206 22:21:07.886720 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5207 22:21:07.893611 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5208 22:21:07.896687 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5209 22:21:07.903467 1 0 0 | B1->B0 | 2929 3c3c | 0 0 | (0 0) (0 0)
5210 22:21:07.906545 1 0 4 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
5211 22:21:07.909620 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5212 22:21:07.916599 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5213 22:21:07.919480 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5214 22:21:07.922676 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5215 22:21:07.929469 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5216 22:21:07.932856 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5217 22:21:07.935891 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5218 22:21:07.942365 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5219 22:21:07.945754 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5220 22:21:07.949449 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5221 22:21:07.955595 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5222 22:21:07.959278 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5223 22:21:07.962411 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5224 22:21:07.968781 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5225 22:21:07.972320 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5226 22:21:07.975424 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5227 22:21:07.982051 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5228 22:21:07.985747 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5229 22:21:07.988801 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5230 22:21:07.995140 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5231 22:21:07.998812 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5232 22:21:08.001848 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5233 22:21:08.008566 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
5234 22:21:08.008652 Total UI for P1: 0, mck2ui 16
5235 22:21:08.011733 best dqsien dly found for B0: ( 1, 2, 28)
5236 22:21:08.018575 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5237 22:21:08.021430 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5238 22:21:08.024789 Total UI for P1: 0, mck2ui 16
5239 22:21:08.028235 best dqsien dly found for B1: ( 1, 3, 4)
5240 22:21:08.031643 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5241 22:21:08.034872 best DQS1 dly(MCK, UI, PI) = (1, 3, 4)
5242 22:21:08.034958
5243 22:21:08.038435 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5244 22:21:08.045134 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 4)
5245 22:21:08.045246 [Gating] SW calibration Done
5246 22:21:08.045342 ==
5247 22:21:08.048140 Dram Type= 6, Freq= 0, CH_0, rank 0
5248 22:21:08.054922 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5249 22:21:08.055039 ==
5250 22:21:08.055143 RX Vref Scan: 0
5251 22:21:08.055249
5252 22:21:08.058020 RX Vref 0 -> 0, step: 1
5253 22:21:08.058111
5254 22:21:08.061167 RX Delay -80 -> 252, step: 8
5255 22:21:08.064857 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5256 22:21:08.067724 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5257 22:21:08.071265 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5258 22:21:08.074702 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5259 22:21:08.081408 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5260 22:21:08.084588 iDelay=208, Bit 5, Center 79 (-16 ~ 175) 192
5261 22:21:08.087858 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5262 22:21:08.090786 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5263 22:21:08.094458 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5264 22:21:08.100746 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5265 22:21:08.104413 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5266 22:21:08.107396 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5267 22:21:08.111042 iDelay=208, Bit 12, Center 83 (-16 ~ 183) 200
5268 22:21:08.114141 iDelay=208, Bit 13, Center 87 (-16 ~ 191) 208
5269 22:21:08.121103 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5270 22:21:08.124377 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5271 22:21:08.124498 ==
5272 22:21:08.127050 Dram Type= 6, Freq= 0, CH_0, rank 0
5273 22:21:08.130490 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5274 22:21:08.130604 ==
5275 22:21:08.133859 DQS Delay:
5276 22:21:08.133969 DQS0 = 0, DQS1 = 0
5277 22:21:08.134074 DQM Delay:
5278 22:21:08.137109 DQM0 = 94, DQM1 = 82
5279 22:21:08.137213 DQ Delay:
5280 22:21:08.140540 DQ0 =95, DQ1 =95, DQ2 =91, DQ3 =91
5281 22:21:08.143927 DQ4 =95, DQ5 =79, DQ6 =103, DQ7 =107
5282 22:21:08.146846 DQ8 =75, DQ9 =71, DQ10 =83, DQ11 =75
5283 22:21:08.150490 DQ12 =83, DQ13 =87, DQ14 =91, DQ15 =91
5284 22:21:08.150595
5285 22:21:08.150693
5286 22:21:08.150785 ==
5287 22:21:08.153627 Dram Type= 6, Freq= 0, CH_0, rank 0
5288 22:21:08.160075 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5289 22:21:08.160194 ==
5290 22:21:08.160292
5291 22:21:08.160383
5292 22:21:08.163718 TX Vref Scan disable
5293 22:21:08.163806 == TX Byte 0 ==
5294 22:21:08.167112 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5295 22:21:08.173448 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5296 22:21:08.173565 == TX Byte 1 ==
5297 22:21:08.176804 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5298 22:21:08.183541 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5299 22:21:08.183625 ==
5300 22:21:08.186562 Dram Type= 6, Freq= 0, CH_0, rank 0
5301 22:21:08.189719 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5302 22:21:08.189838 ==
5303 22:21:08.189936
5304 22:21:08.190031
5305 22:21:08.193360 TX Vref Scan disable
5306 22:21:08.196901 == TX Byte 0 ==
5307 22:21:08.200062 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5308 22:21:08.203314 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5309 22:21:08.206321 == TX Byte 1 ==
5310 22:21:08.210038 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5311 22:21:08.213032 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5312 22:21:08.213115
5313 22:21:08.216191 [DATLAT]
5314 22:21:08.216278 Freq=933, CH0 RK0
5315 22:21:08.216345
5316 22:21:08.219959 DATLAT Default: 0xd
5317 22:21:08.220035 0, 0xFFFF, sum = 0
5318 22:21:08.223056 1, 0xFFFF, sum = 0
5319 22:21:08.223144 2, 0xFFFF, sum = 0
5320 22:21:08.226112 3, 0xFFFF, sum = 0
5321 22:21:08.226187 4, 0xFFFF, sum = 0
5322 22:21:08.229723 5, 0xFFFF, sum = 0
5323 22:21:08.229825 6, 0xFFFF, sum = 0
5324 22:21:08.232782 7, 0xFFFF, sum = 0
5325 22:21:08.232872 8, 0xFFFF, sum = 0
5326 22:21:08.235802 9, 0xFFFF, sum = 0
5327 22:21:08.235876 10, 0x0, sum = 1
5328 22:21:08.239237 11, 0x0, sum = 2
5329 22:21:08.239314 12, 0x0, sum = 3
5330 22:21:08.242474 13, 0x0, sum = 4
5331 22:21:08.242549 best_step = 11
5332 22:21:08.242610
5333 22:21:08.242668 ==
5334 22:21:08.245968 Dram Type= 6, Freq= 0, CH_0, rank 0
5335 22:21:08.252348 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5336 22:21:08.252449 ==
5337 22:21:08.252517 RX Vref Scan: 1
5338 22:21:08.252580
5339 22:21:08.255956 RX Vref 0 -> 0, step: 1
5340 22:21:08.256076
5341 22:21:08.259044 RX Delay -69 -> 252, step: 4
5342 22:21:08.259128
5343 22:21:08.262638 Set Vref, RX VrefLevel [Byte0]: 60
5344 22:21:08.265717 [Byte1]: 48
5345 22:21:08.265800
5346 22:21:08.268689 Final RX Vref Byte 0 = 60 to rank0
5347 22:21:08.272317 Final RX Vref Byte 1 = 48 to rank0
5348 22:21:08.275365 Final RX Vref Byte 0 = 60 to rank1
5349 22:21:08.279085 Final RX Vref Byte 1 = 48 to rank1==
5350 22:21:08.282091 Dram Type= 6, Freq= 0, CH_0, rank 0
5351 22:21:08.285484 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5352 22:21:08.285589 ==
5353 22:21:08.289094 DQS Delay:
5354 22:21:08.289178 DQS0 = 0, DQS1 = 0
5355 22:21:08.292198 DQM Delay:
5356 22:21:08.292283 DQM0 = 96, DQM1 = 82
5357 22:21:08.292350 DQ Delay:
5358 22:21:08.295560 DQ0 =94, DQ1 =96, DQ2 =92, DQ3 =94
5359 22:21:08.298539 DQ4 =96, DQ5 =84, DQ6 =104, DQ7 =108
5360 22:21:08.302140 DQ8 =74, DQ9 =70, DQ10 =84, DQ11 =76
5361 22:21:08.305174 DQ12 =86, DQ13 =86, DQ14 =94, DQ15 =90
5362 22:21:08.305278
5363 22:21:08.308907
5364 22:21:08.314939 [DQSOSCAuto] RK0, (LSB)MR18= 0x1111, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 416 ps
5365 22:21:08.318557 CH0 RK0: MR19=505, MR18=1111
5366 22:21:08.324933 CH0_RK0: MR19=0x505, MR18=0x1111, DQSOSC=416, MR23=63, INC=62, DEC=41
5367 22:21:08.325043
5368 22:21:08.328477 ----->DramcWriteLeveling(PI) begin...
5369 22:21:08.328586 ==
5370 22:21:08.331555 Dram Type= 6, Freq= 0, CH_0, rank 1
5371 22:21:08.335245 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5372 22:21:08.335353 ==
5373 22:21:08.338364 Write leveling (Byte 0): 32 => 32
5374 22:21:08.341855 Write leveling (Byte 1): 30 => 30
5375 22:21:08.344758 DramcWriteLeveling(PI) end<-----
5376 22:21:08.344863
5377 22:21:08.344954 ==
5378 22:21:08.348115 Dram Type= 6, Freq= 0, CH_0, rank 1
5379 22:21:08.351585 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5380 22:21:08.351691 ==
5381 22:21:08.354544 [Gating] SW mode calibration
5382 22:21:08.361568 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5383 22:21:08.367680 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5384 22:21:08.371384 0 14 0 | B1->B0 | 2a2a 3434 | 1 1 | (1 1) (1 1)
5385 22:21:08.377972 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5386 22:21:08.380926 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5387 22:21:08.384438 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5388 22:21:08.390593 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5389 22:21:08.394110 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5390 22:21:08.397594 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5391 22:21:08.404164 0 14 28 | B1->B0 | 3333 2e2e | 0 1 | (0 0) (1 0)
5392 22:21:08.407259 0 15 0 | B1->B0 | 2e2e 2323 | 1 0 | (1 0) (1 0)
5393 22:21:08.410383 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
5394 22:21:08.417456 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5395 22:21:08.420176 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5396 22:21:08.423890 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5397 22:21:08.430003 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5398 22:21:08.433850 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5399 22:21:08.436927 0 15 28 | B1->B0 | 2525 3232 | 0 0 | (0 0) (0 0)
5400 22:21:08.443778 1 0 0 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
5401 22:21:08.446493 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5402 22:21:08.449820 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5403 22:21:08.456678 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5404 22:21:08.460068 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5405 22:21:08.463494 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5406 22:21:08.469760 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5407 22:21:08.472956 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5408 22:21:08.476030 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5409 22:21:08.482553 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5410 22:21:08.485946 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5411 22:21:08.489410 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5412 22:21:08.496197 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5413 22:21:08.499248 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5414 22:21:08.502316 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5415 22:21:08.509259 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5416 22:21:08.512366 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5417 22:21:08.516328 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5418 22:21:08.522274 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5419 22:21:08.525979 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5420 22:21:08.529182 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5421 22:21:08.535670 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5422 22:21:08.538716 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5423 22:21:08.541847 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5424 22:21:08.548679 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5425 22:21:08.548766 Total UI for P1: 0, mck2ui 16
5426 22:21:08.555145 best dqsien dly found for B0: ( 1, 2, 26)
5427 22:21:08.558614 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5428 22:21:08.562238 Total UI for P1: 0, mck2ui 16
5429 22:21:08.565200 best dqsien dly found for B1: ( 1, 2, 30)
5430 22:21:08.568155 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5431 22:21:08.571619 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5432 22:21:08.571708
5433 22:21:08.575130 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5434 22:21:08.578143 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5435 22:21:08.581266 [Gating] SW calibration Done
5436 22:21:08.581342 ==
5437 22:21:08.584827 Dram Type= 6, Freq= 0, CH_0, rank 1
5438 22:21:08.591278 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5439 22:21:08.591373 ==
5440 22:21:08.591439 RX Vref Scan: 0
5441 22:21:08.591500
5442 22:21:08.594644 RX Vref 0 -> 0, step: 1
5443 22:21:08.594744
5444 22:21:08.597993 RX Delay -80 -> 252, step: 8
5445 22:21:08.601083 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5446 22:21:08.604863 iDelay=208, Bit 1, Center 95 (-8 ~ 199) 208
5447 22:21:08.607869 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5448 22:21:08.611297 iDelay=208, Bit 3, Center 87 (-16 ~ 191) 208
5449 22:21:08.617884 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5450 22:21:08.621192 iDelay=208, Bit 5, Center 75 (-24 ~ 175) 200
5451 22:21:08.624734 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5452 22:21:08.627830 iDelay=208, Bit 7, Center 103 (0 ~ 207) 208
5453 22:21:08.631178 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5454 22:21:08.637546 iDelay=208, Bit 9, Center 63 (-32 ~ 159) 192
5455 22:21:08.640850 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5456 22:21:08.644491 iDelay=208, Bit 11, Center 71 (-24 ~ 167) 192
5457 22:21:08.647555 iDelay=208, Bit 12, Center 87 (-8 ~ 183) 192
5458 22:21:08.650686 iDelay=208, Bit 13, Center 87 (-16 ~ 191) 208
5459 22:21:08.657442 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5460 22:21:08.660873 iDelay=208, Bit 15, Center 87 (-8 ~ 183) 192
5461 22:21:08.660958 ==
5462 22:21:08.664322 Dram Type= 6, Freq= 0, CH_0, rank 1
5463 22:21:08.667253 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5464 22:21:08.667336 ==
5465 22:21:08.670752 DQS Delay:
5466 22:21:08.670867 DQS0 = 0, DQS1 = 0
5467 22:21:08.670936 DQM Delay:
5468 22:21:08.673543 DQM0 = 91, DQM1 = 81
5469 22:21:08.673629 DQ Delay:
5470 22:21:08.676981 DQ0 =91, DQ1 =95, DQ2 =87, DQ3 =87
5471 22:21:08.680280 DQ4 =91, DQ5 =75, DQ6 =103, DQ7 =103
5472 22:21:08.683878 DQ8 =75, DQ9 =63, DQ10 =87, DQ11 =71
5473 22:21:08.686878 DQ12 =87, DQ13 =87, DQ14 =91, DQ15 =87
5474 22:21:08.686991
5475 22:21:08.687097
5476 22:21:08.690804 ==
5477 22:21:08.690897 Dram Type= 6, Freq= 0, CH_0, rank 1
5478 22:21:08.697124 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5479 22:21:08.697210 ==
5480 22:21:08.697277
5481 22:21:08.697339
5482 22:21:08.700174 TX Vref Scan disable
5483 22:21:08.700259 == TX Byte 0 ==
5484 22:21:08.703451 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5485 22:21:08.710213 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5486 22:21:08.710298 == TX Byte 1 ==
5487 22:21:08.713347 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5488 22:21:08.719776 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5489 22:21:08.719866 ==
5490 22:21:08.723266 Dram Type= 6, Freq= 0, CH_0, rank 1
5491 22:21:08.726951 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5492 22:21:08.727037 ==
5493 22:21:08.727105
5494 22:21:08.727166
5495 22:21:08.730003 TX Vref Scan disable
5496 22:21:08.733211 == TX Byte 0 ==
5497 22:21:08.736939 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5498 22:21:08.739707 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5499 22:21:08.743469 == TX Byte 1 ==
5500 22:21:08.746415 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5501 22:21:08.750007 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5502 22:21:08.750091
5503 22:21:08.753022 [DATLAT]
5504 22:21:08.753105 Freq=933, CH0 RK1
5505 22:21:08.753172
5506 22:21:08.756695 DATLAT Default: 0xb
5507 22:21:08.756780 0, 0xFFFF, sum = 0
5508 22:21:08.759765 1, 0xFFFF, sum = 0
5509 22:21:08.759850 2, 0xFFFF, sum = 0
5510 22:21:08.762799 3, 0xFFFF, sum = 0
5511 22:21:08.762894 4, 0xFFFF, sum = 0
5512 22:21:08.766575 5, 0xFFFF, sum = 0
5513 22:21:08.766661 6, 0xFFFF, sum = 0
5514 22:21:08.769385 7, 0xFFFF, sum = 0
5515 22:21:08.769470 8, 0xFFFF, sum = 0
5516 22:21:08.772764 9, 0xFFFF, sum = 0
5517 22:21:08.772850 10, 0x0, sum = 1
5518 22:21:08.776088 11, 0x0, sum = 2
5519 22:21:08.776173 12, 0x0, sum = 3
5520 22:21:08.779428 13, 0x0, sum = 4
5521 22:21:08.779517 best_step = 11
5522 22:21:08.779585
5523 22:21:08.779648 ==
5524 22:21:08.783064 Dram Type= 6, Freq= 0, CH_0, rank 1
5525 22:21:08.789253 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5526 22:21:08.789338 ==
5527 22:21:08.789405 RX Vref Scan: 0
5528 22:21:08.789467
5529 22:21:08.792829 RX Vref 0 -> 0, step: 1
5530 22:21:08.792914
5531 22:21:08.795921 RX Delay -77 -> 252, step: 4
5532 22:21:08.799572 iDelay=199, Bit 0, Center 90 (-5 ~ 186) 192
5533 22:21:08.802565 iDelay=199, Bit 1, Center 92 (-1 ~ 186) 188
5534 22:21:08.809057 iDelay=199, Bit 2, Center 88 (-5 ~ 182) 188
5535 22:21:08.812653 iDelay=199, Bit 3, Center 88 (-9 ~ 186) 196
5536 22:21:08.815707 iDelay=199, Bit 4, Center 92 (-1 ~ 186) 188
5537 22:21:08.818902 iDelay=199, Bit 5, Center 82 (-9 ~ 174) 184
5538 22:21:08.822035 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5539 22:21:08.828817 iDelay=199, Bit 7, Center 104 (11 ~ 198) 188
5540 22:21:08.832388 iDelay=199, Bit 8, Center 74 (-17 ~ 166) 184
5541 22:21:08.835380 iDelay=199, Bit 9, Center 70 (-17 ~ 158) 176
5542 22:21:08.838837 iDelay=199, Bit 10, Center 86 (-5 ~ 178) 184
5543 22:21:08.841951 iDelay=199, Bit 11, Center 76 (-13 ~ 166) 180
5544 22:21:08.848907 iDelay=199, Bit 12, Center 90 (-1 ~ 182) 184
5545 22:21:08.851905 iDelay=199, Bit 13, Center 90 (-1 ~ 182) 184
5546 22:21:08.855576 iDelay=199, Bit 14, Center 98 (11 ~ 186) 176
5547 22:21:08.858696 iDelay=199, Bit 15, Center 92 (3 ~ 182) 180
5548 22:21:08.858807 ==
5549 22:21:08.861777 Dram Type= 6, Freq= 0, CH_0, rank 1
5550 22:21:08.868563 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5551 22:21:08.868648 ==
5552 22:21:08.868715 DQS Delay:
5553 22:21:08.868779 DQS0 = 0, DQS1 = 0
5554 22:21:08.871532 DQM Delay:
5555 22:21:08.871616 DQM0 = 92, DQM1 = 84
5556 22:21:08.875171 DQ Delay:
5557 22:21:08.878511 DQ0 =90, DQ1 =92, DQ2 =88, DQ3 =88
5558 22:21:08.881499 DQ4 =92, DQ5 =82, DQ6 =104, DQ7 =104
5559 22:21:08.884829 DQ8 =74, DQ9 =70, DQ10 =86, DQ11 =76
5560 22:21:08.888191 DQ12 =90, DQ13 =90, DQ14 =98, DQ15 =92
5561 22:21:08.888276
5562 22:21:08.888352
5563 22:21:08.894547 [DQSOSCAuto] RK1, (LSB)MR18= 0x2c0e, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 408 ps
5564 22:21:08.897908 CH0 RK1: MR19=505, MR18=2C0E
5565 22:21:08.904805 CH0_RK1: MR19=0x505, MR18=0x2C0E, DQSOSC=408, MR23=63, INC=65, DEC=43
5566 22:21:08.907827 [RxdqsGatingPostProcess] freq 933
5567 22:21:08.910929 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5568 22:21:08.914383 best DQS0 dly(2T, 0.5T) = (0, 10)
5569 22:21:08.917863 best DQS1 dly(2T, 0.5T) = (0, 11)
5570 22:21:08.920933 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5571 22:21:08.924633 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5572 22:21:08.927730 best DQS0 dly(2T, 0.5T) = (0, 10)
5573 22:21:08.931275 best DQS1 dly(2T, 0.5T) = (0, 10)
5574 22:21:08.934139 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5575 22:21:08.937580 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5576 22:21:08.940680 Pre-setting of DQS Precalculation
5577 22:21:08.944210 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5578 22:21:08.947261 ==
5579 22:21:08.951153 Dram Type= 6, Freq= 0, CH_1, rank 0
5580 22:21:08.953962 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5581 22:21:08.954068 ==
5582 22:21:08.960814 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5583 22:21:08.963801 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5584 22:21:08.967542 [CA 0] Center 37 (7~67) winsize 61
5585 22:21:08.971304 [CA 1] Center 37 (7~68) winsize 62
5586 22:21:08.974438 [CA 2] Center 34 (5~64) winsize 60
5587 22:21:08.977519 [CA 3] Center 34 (5~64) winsize 60
5588 22:21:08.981145 [CA 4] Center 34 (5~64) winsize 60
5589 22:21:08.984309 [CA 5] Center 34 (4~64) winsize 61
5590 22:21:08.984446
5591 22:21:08.987801 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5592 22:21:08.987904
5593 22:21:08.990670 [CATrainingPosCal] consider 1 rank data
5594 22:21:08.994131 u2DelayCellTimex100 = 270/100 ps
5595 22:21:08.997660 CA0 delay=37 (7~67),Diff = 3 PI (18 cell)
5596 22:21:09.003983 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5597 22:21:09.007542 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
5598 22:21:09.010390 CA3 delay=34 (5~64),Diff = 0 PI (0 cell)
5599 22:21:09.014040 CA4 delay=34 (5~64),Diff = 0 PI (0 cell)
5600 22:21:09.017050 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5601 22:21:09.017159
5602 22:21:09.020865 CA PerBit enable=1, Macro0, CA PI delay=34
5603 22:21:09.020948
5604 22:21:09.023604 [CBTSetCACLKResult] CA Dly = 34
5605 22:21:09.027178 CS Dly: 6 (0~37)
5606 22:21:09.027260 ==
5607 22:21:09.030220 Dram Type= 6, Freq= 0, CH_1, rank 1
5608 22:21:09.033817 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5609 22:21:09.033899 ==
5610 22:21:09.040639 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5611 22:21:09.043409 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5612 22:21:09.047853 [CA 0] Center 38 (8~68) winsize 61
5613 22:21:09.051015 [CA 1] Center 37 (7~68) winsize 62
5614 22:21:09.053992 [CA 2] Center 35 (6~65) winsize 60
5615 22:21:09.057721 [CA 3] Center 34 (4~64) winsize 61
5616 22:21:09.060734 [CA 4] Center 35 (5~65) winsize 61
5617 22:21:09.064451 [CA 5] Center 34 (4~64) winsize 61
5618 22:21:09.064534
5619 22:21:09.067646 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5620 22:21:09.067735
5621 22:21:09.070719 [CATrainingPosCal] consider 2 rank data
5622 22:21:09.074307 u2DelayCellTimex100 = 270/100 ps
5623 22:21:09.077523 CA0 delay=37 (8~67),Diff = 3 PI (18 cell)
5624 22:21:09.083693 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5625 22:21:09.087312 CA2 delay=35 (6~64),Diff = 1 PI (6 cell)
5626 22:21:09.090209 CA3 delay=34 (5~64),Diff = 0 PI (0 cell)
5627 22:21:09.093743 CA4 delay=34 (5~64),Diff = 0 PI (0 cell)
5628 22:21:09.097267 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5629 22:21:09.097353
5630 22:21:09.100564 CA PerBit enable=1, Macro0, CA PI delay=34
5631 22:21:09.100650
5632 22:21:09.104214 [CBTSetCACLKResult] CA Dly = 34
5633 22:21:09.107004 CS Dly: 7 (0~39)
5634 22:21:09.107089
5635 22:21:09.110382 ----->DramcWriteLeveling(PI) begin...
5636 22:21:09.110469 ==
5637 22:21:09.113655 Dram Type= 6, Freq= 0, CH_1, rank 0
5638 22:21:09.117119 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5639 22:21:09.117206 ==
5640 22:21:09.120163 Write leveling (Byte 0): 24 => 24
5641 22:21:09.123310 Write leveling (Byte 1): 29 => 29
5642 22:21:09.126840 DramcWriteLeveling(PI) end<-----
5643 22:21:09.126931
5644 22:21:09.126999 ==
5645 22:21:09.130335 Dram Type= 6, Freq= 0, CH_1, rank 0
5646 22:21:09.133615 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5647 22:21:09.133705 ==
5648 22:21:09.136721 [Gating] SW mode calibration
5649 22:21:09.143164 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5650 22:21:09.149871 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5651 22:21:09.153383 0 14 0 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
5652 22:21:09.156130 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5653 22:21:09.163236 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5654 22:21:09.166400 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5655 22:21:09.169535 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5656 22:21:09.176411 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5657 22:21:09.179540 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5658 22:21:09.182777 0 14 28 | B1->B0 | 3030 3030 | 0 0 | (0 1) (0 1)
5659 22:21:09.189596 0 15 0 | B1->B0 | 2323 2626 | 0 0 | (1 0) (0 0)
5660 22:21:09.192651 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5661 22:21:09.195674 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5662 22:21:09.202595 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5663 22:21:09.205995 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5664 22:21:09.212614 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5665 22:21:09.215815 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5666 22:21:09.219185 0 15 28 | B1->B0 | 3131 3131 | 0 0 | (1 1) (0 0)
5667 22:21:09.225721 1 0 0 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
5668 22:21:09.228764 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5669 22:21:09.231851 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5670 22:21:09.238323 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5671 22:21:09.241797 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5672 22:21:09.245443 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5673 22:21:09.252037 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5674 22:21:09.255081 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5675 22:21:09.258183 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5676 22:21:09.264968 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5677 22:21:09.268471 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5678 22:21:09.271564 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5679 22:21:09.278352 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5680 22:21:09.281461 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5681 22:21:09.284505 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5682 22:21:09.291432 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5683 22:21:09.294528 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5684 22:21:09.297695 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5685 22:21:09.304538 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5686 22:21:09.307397 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5687 22:21:09.310968 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5688 22:21:09.317372 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5689 22:21:09.320725 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5690 22:21:09.324170 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5691 22:21:09.330703 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5692 22:21:09.330809 Total UI for P1: 0, mck2ui 16
5693 22:21:09.337489 best dqsien dly found for B0: ( 1, 2, 28)
5694 22:21:09.340511 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5695 22:21:09.344024 Total UI for P1: 0, mck2ui 16
5696 22:21:09.347072 best dqsien dly found for B1: ( 1, 3, 0)
5697 22:21:09.350888 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5698 22:21:09.353967 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5699 22:21:09.354045
5700 22:21:09.356880 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5701 22:21:09.360583 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5702 22:21:09.363934 [Gating] SW calibration Done
5703 22:21:09.364043 ==
5704 22:21:09.366714 Dram Type= 6, Freq= 0, CH_1, rank 0
5705 22:21:09.370255 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5706 22:21:09.373267 ==
5707 22:21:09.373374 RX Vref Scan: 0
5708 22:21:09.373466
5709 22:21:09.376998 RX Vref 0 -> 0, step: 1
5710 22:21:09.377080
5711 22:21:09.380141 RX Delay -80 -> 252, step: 8
5712 22:21:09.383261 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5713 22:21:09.386873 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5714 22:21:09.389991 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5715 22:21:09.393050 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5716 22:21:09.396770 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5717 22:21:09.403061 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5718 22:21:09.407017 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5719 22:21:09.409669 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5720 22:21:09.413292 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5721 22:21:09.416552 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5722 22:21:09.423033 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5723 22:21:09.426413 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5724 22:21:09.429452 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5725 22:21:09.432930 iDelay=208, Bit 13, Center 95 (-8 ~ 199) 208
5726 22:21:09.436316 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5727 22:21:09.442981 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5728 22:21:09.443059 ==
5729 22:21:09.445886 Dram Type= 6, Freq= 0, CH_1, rank 0
5730 22:21:09.448994 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5731 22:21:09.449093 ==
5732 22:21:09.449194 DQS Delay:
5733 22:21:09.452936 DQS0 = 0, DQS1 = 0
5734 22:21:09.453039 DQM Delay:
5735 22:21:09.455739 DQM0 = 94, DQM1 = 86
5736 22:21:09.455820 DQ Delay:
5737 22:21:09.459188 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =91
5738 22:21:09.462556 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =91
5739 22:21:09.465670 DQ8 =75, DQ9 =75, DQ10 =87, DQ11 =83
5740 22:21:09.469276 DQ12 =95, DQ13 =95, DQ14 =91, DQ15 =91
5741 22:21:09.469358
5742 22:21:09.469455
5743 22:21:09.469515 ==
5744 22:21:09.472137 Dram Type= 6, Freq= 0, CH_1, rank 0
5745 22:21:09.475893 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5746 22:21:09.478744 ==
5747 22:21:09.478889
5748 22:21:09.478992
5749 22:21:09.479122 TX Vref Scan disable
5750 22:21:09.482431 == TX Byte 0 ==
5751 22:21:09.485552 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5752 22:21:09.488609 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5753 22:21:09.492411 == TX Byte 1 ==
5754 22:21:09.495383 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5755 22:21:09.499101 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5756 22:21:09.502155 ==
5757 22:21:09.505912 Dram Type= 6, Freq= 0, CH_1, rank 0
5758 22:21:09.508966 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5759 22:21:09.509049 ==
5760 22:21:09.509115
5761 22:21:09.509176
5762 22:21:09.512116 TX Vref Scan disable
5763 22:21:09.512198 == TX Byte 0 ==
5764 22:21:09.518732 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5765 22:21:09.521958 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5766 22:21:09.522044 == TX Byte 1 ==
5767 22:21:09.528353 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5768 22:21:09.531697 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5769 22:21:09.531781
5770 22:21:09.531846 [DATLAT]
5771 22:21:09.535002 Freq=933, CH1 RK0
5772 22:21:09.535114
5773 22:21:09.535179 DATLAT Default: 0xd
5774 22:21:09.538453 0, 0xFFFF, sum = 0
5775 22:21:09.538538 1, 0xFFFF, sum = 0
5776 22:21:09.541800 2, 0xFFFF, sum = 0
5777 22:21:09.545188 3, 0xFFFF, sum = 0
5778 22:21:09.545306 4, 0xFFFF, sum = 0
5779 22:21:09.548239 5, 0xFFFF, sum = 0
5780 22:21:09.548343 6, 0xFFFF, sum = 0
5781 22:21:09.551730 7, 0xFFFF, sum = 0
5782 22:21:09.551809 8, 0xFFFF, sum = 0
5783 22:21:09.554806 9, 0xFFFF, sum = 0
5784 22:21:09.554913 10, 0x0, sum = 1
5785 22:21:09.558173 11, 0x0, sum = 2
5786 22:21:09.558259 12, 0x0, sum = 3
5787 22:21:09.561597 13, 0x0, sum = 4
5788 22:21:09.561682 best_step = 11
5789 22:21:09.561749
5790 22:21:09.561810 ==
5791 22:21:09.564803 Dram Type= 6, Freq= 0, CH_1, rank 0
5792 22:21:09.568129 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5793 22:21:09.568214 ==
5794 22:21:09.571623 RX Vref Scan: 1
5795 22:21:09.571719
5796 22:21:09.574797 RX Vref 0 -> 0, step: 1
5797 22:21:09.574905
5798 22:21:09.574971 RX Delay -69 -> 252, step: 4
5799 22:21:09.575052
5800 22:21:09.578226 Set Vref, RX VrefLevel [Byte0]: 56
5801 22:21:09.581265 [Byte1]: 53
5802 22:21:09.586096
5803 22:21:09.586179 Final RX Vref Byte 0 = 56 to rank0
5804 22:21:09.590054 Final RX Vref Byte 1 = 53 to rank0
5805 22:21:09.592857 Final RX Vref Byte 0 = 56 to rank1
5806 22:21:09.596004 Final RX Vref Byte 1 = 53 to rank1==
5807 22:21:09.599089 Dram Type= 6, Freq= 0, CH_1, rank 0
5808 22:21:09.605921 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5809 22:21:09.606004 ==
5810 22:21:09.606071 DQS Delay:
5811 22:21:09.608948 DQS0 = 0, DQS1 = 0
5812 22:21:09.609031 DQM Delay:
5813 22:21:09.609097 DQM0 = 96, DQM1 = 88
5814 22:21:09.612626 DQ Delay:
5815 22:21:09.615690 DQ0 =102, DQ1 =92, DQ2 =82, DQ3 =94
5816 22:21:09.618775 DQ4 =94, DQ5 =106, DQ6 =108, DQ7 =94
5817 22:21:09.622421 DQ8 =76, DQ9 =80, DQ10 =88, DQ11 =82
5818 22:21:09.625401 DQ12 =98, DQ13 =94, DQ14 =98, DQ15 =94
5819 22:21:09.625490
5820 22:21:09.625556
5821 22:21:09.631933 [DQSOSCAuto] RK0, (LSB)MR18= 0x109, (MSB)MR19= 0x505, tDQSOscB0 = 419 ps tDQSOscB1 = 421 ps
5822 22:21:09.635614 CH1 RK0: MR19=505, MR18=109
5823 22:21:09.642234 CH1_RK0: MR19=0x505, MR18=0x109, DQSOSC=419, MR23=63, INC=61, DEC=41
5824 22:21:09.642350
5825 22:21:09.645009 ----->DramcWriteLeveling(PI) begin...
5826 22:21:09.645093 ==
5827 22:21:09.648522 Dram Type= 6, Freq= 0, CH_1, rank 1
5828 22:21:09.651963 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5829 22:21:09.652047 ==
5830 22:21:09.655426 Write leveling (Byte 0): 27 => 27
5831 22:21:09.658529 Write leveling (Byte 1): 27 => 27
5832 22:21:09.662141 DramcWriteLeveling(PI) end<-----
5833 22:21:09.662229
5834 22:21:09.662295 ==
5835 22:21:09.665321 Dram Type= 6, Freq= 0, CH_1, rank 1
5836 22:21:09.668284 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5837 22:21:09.671867 ==
5838 22:21:09.671950 [Gating] SW mode calibration
5839 22:21:09.681765 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5840 22:21:09.684814 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5841 22:21:09.688467 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (0 0) (1 1)
5842 22:21:09.695241 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5843 22:21:09.698238 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5844 22:21:09.701302 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5845 22:21:09.708158 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5846 22:21:09.711348 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5847 22:21:09.714399 0 14 24 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (0 0)
5848 22:21:09.721205 0 14 28 | B1->B0 | 2d2d 2323 | 0 0 | (0 1) (0 0)
5849 22:21:09.724206 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5850 22:21:09.727790 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5851 22:21:09.734357 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5852 22:21:09.737829 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5853 22:21:09.740695 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5854 22:21:09.747624 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5855 22:21:09.751030 0 15 24 | B1->B0 | 2626 3535 | 0 0 | (0 0) (1 1)
5856 22:21:09.753877 0 15 28 | B1->B0 | 3737 4646 | 0 0 | (1 1) (0 0)
5857 22:21:09.760746 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5858 22:21:09.764114 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5859 22:21:09.767200 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5860 22:21:09.773763 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5861 22:21:09.776833 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5862 22:21:09.780528 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5863 22:21:09.787074 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5864 22:21:09.790413 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5865 22:21:09.793414 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5866 22:21:09.799949 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5867 22:21:09.803727 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5868 22:21:09.806799 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5869 22:21:09.813095 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5870 22:21:09.816734 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5871 22:21:09.819939 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5872 22:21:09.826647 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5873 22:21:09.829735 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5874 22:21:09.833252 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5875 22:21:09.839893 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5876 22:21:09.842934 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5877 22:21:09.846461 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5878 22:21:09.852857 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5879 22:21:09.856275 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5880 22:21:09.859762 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5881 22:21:09.862568 Total UI for P1: 0, mck2ui 16
5882 22:21:09.866260 best dqsien dly found for B0: ( 1, 2, 24)
5883 22:21:09.873007 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5884 22:21:09.873090 Total UI for P1: 0, mck2ui 16
5885 22:21:09.879553 best dqsien dly found for B1: ( 1, 2, 28)
5886 22:21:09.882686 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5887 22:21:09.885694 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5888 22:21:09.885777
5889 22:21:09.889455 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5890 22:21:09.892476 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5891 22:21:09.896194 [Gating] SW calibration Done
5892 22:21:09.896276 ==
5893 22:21:09.899474 Dram Type= 6, Freq= 0, CH_1, rank 1
5894 22:21:09.902348 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5895 22:21:09.902431 ==
5896 22:21:09.905946 RX Vref Scan: 0
5897 22:21:09.906028
5898 22:21:09.909156 RX Vref 0 -> 0, step: 1
5899 22:21:09.909239
5900 22:21:09.909304 RX Delay -80 -> 252, step: 8
5901 22:21:09.916032 iDelay=208, Bit 0, Center 95 (-8 ~ 199) 208
5902 22:21:09.918769 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5903 22:21:09.921946 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5904 22:21:09.925759 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5905 22:21:09.928831 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5906 22:21:09.935451 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5907 22:21:09.939019 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5908 22:21:09.942090 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5909 22:21:09.945233 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5910 22:21:09.948318 iDelay=208, Bit 9, Center 83 (-16 ~ 183) 200
5911 22:21:09.951973 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5912 22:21:09.958378 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5913 22:21:09.961869 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5914 22:21:09.965411 iDelay=208, Bit 13, Center 95 (-8 ~ 199) 208
5915 22:21:09.969109 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5916 22:21:09.971734 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5917 22:21:09.971845 ==
5918 22:21:09.975065 Dram Type= 6, Freq= 0, CH_1, rank 1
5919 22:21:09.981668 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5920 22:21:09.981753 ==
5921 22:21:09.981819 DQS Delay:
5922 22:21:09.985069 DQS0 = 0, DQS1 = 0
5923 22:21:09.985152 DQM Delay:
5924 22:21:09.988415 DQM0 = 94, DQM1 = 90
5925 22:21:09.988497 DQ Delay:
5926 22:21:09.991450 DQ0 =95, DQ1 =91, DQ2 =83, DQ3 =91
5927 22:21:09.994559 DQ4 =91, DQ5 =107, DQ6 =103, DQ7 =91
5928 22:21:09.998132 DQ8 =75, DQ9 =83, DQ10 =91, DQ11 =83
5929 22:21:10.001788 DQ12 =99, DQ13 =95, DQ14 =99, DQ15 =99
5930 22:21:10.001877
5931 22:21:10.001951
5932 22:21:10.002013 ==
5933 22:21:10.004823 Dram Type= 6, Freq= 0, CH_1, rank 1
5934 22:21:10.008380 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5935 22:21:10.008463 ==
5936 22:21:10.008529
5937 22:21:10.008588
5938 22:21:10.011341 TX Vref Scan disable
5939 22:21:10.014362 == TX Byte 0 ==
5940 22:21:10.018122 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5941 22:21:10.021208 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5942 22:21:10.024421 == TX Byte 1 ==
5943 22:21:10.028136 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5944 22:21:10.031249 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5945 22:21:10.031333 ==
5946 22:21:10.034396 Dram Type= 6, Freq= 0, CH_1, rank 1
5947 22:21:10.040979 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5948 22:21:10.041063 ==
5949 22:21:10.041129
5950 22:21:10.041189
5951 22:21:10.041248 TX Vref Scan disable
5952 22:21:10.045076 == TX Byte 0 ==
5953 22:21:10.048201 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5954 22:21:10.055008 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5955 22:21:10.055094 == TX Byte 1 ==
5956 22:21:10.057980 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5957 22:21:10.064869 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5958 22:21:10.064981
5959 22:21:10.065075 [DATLAT]
5960 22:21:10.065165 Freq=933, CH1 RK1
5961 22:21:10.065252
5962 22:21:10.068274 DATLAT Default: 0xb
5963 22:21:10.071169 0, 0xFFFF, sum = 0
5964 22:21:10.071254 1, 0xFFFF, sum = 0
5965 22:21:10.074610 2, 0xFFFF, sum = 0
5966 22:21:10.074728 3, 0xFFFF, sum = 0
5967 22:21:10.078053 4, 0xFFFF, sum = 0
5968 22:21:10.078136 5, 0xFFFF, sum = 0
5969 22:21:10.080995 6, 0xFFFF, sum = 0
5970 22:21:10.081098 7, 0xFFFF, sum = 0
5971 22:21:10.084545 8, 0xFFFF, sum = 0
5972 22:21:10.084622 9, 0xFFFF, sum = 0
5973 22:21:10.087420 10, 0x0, sum = 1
5974 22:21:10.087508 11, 0x0, sum = 2
5975 22:21:10.090988 12, 0x0, sum = 3
5976 22:21:10.091072 13, 0x0, sum = 4
5977 22:21:10.094012 best_step = 11
5978 22:21:10.094094
5979 22:21:10.094160 ==
5980 22:21:10.097173 Dram Type= 6, Freq= 0, CH_1, rank 1
5981 22:21:10.101142 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5982 22:21:10.101225 ==
5983 22:21:10.103925 RX Vref Scan: 0
5984 22:21:10.104008
5985 22:21:10.104073 RX Vref 0 -> 0, step: 1
5986 22:21:10.104134
5987 22:21:10.107472 RX Delay -69 -> 252, step: 4
5988 22:21:10.113985 iDelay=203, Bit 0, Center 96 (-1 ~ 194) 196
5989 22:21:10.117463 iDelay=203, Bit 1, Center 86 (-9 ~ 182) 192
5990 22:21:10.120520 iDelay=203, Bit 2, Center 82 (-13 ~ 178) 192
5991 22:21:10.124087 iDelay=203, Bit 3, Center 88 (-9 ~ 186) 196
5992 22:21:10.127145 iDelay=203, Bit 4, Center 88 (-9 ~ 186) 196
5993 22:21:10.134070 iDelay=203, Bit 5, Center 102 (7 ~ 198) 192
5994 22:21:10.137054 iDelay=203, Bit 6, Center 106 (11 ~ 202) 192
5995 22:21:10.140158 iDelay=203, Bit 7, Center 88 (-9 ~ 186) 196
5996 22:21:10.143708 iDelay=203, Bit 8, Center 78 (-17 ~ 174) 192
5997 22:21:10.147106 iDelay=203, Bit 9, Center 80 (-13 ~ 174) 188
5998 22:21:10.153726 iDelay=203, Bit 10, Center 92 (-5 ~ 190) 196
5999 22:21:10.156836 iDelay=203, Bit 11, Center 84 (-9 ~ 178) 188
6000 22:21:10.160506 iDelay=203, Bit 12, Center 100 (11 ~ 190) 180
6001 22:21:10.163457 iDelay=203, Bit 13, Center 100 (7 ~ 194) 188
6002 22:21:10.166803 iDelay=203, Bit 14, Center 98 (7 ~ 190) 184
6003 22:21:10.173436 iDelay=203, Bit 15, Center 98 (7 ~ 190) 184
6004 22:21:10.173519 ==
6005 22:21:10.176497 Dram Type= 6, Freq= 0, CH_1, rank 1
6006 22:21:10.179963 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
6007 22:21:10.180047 ==
6008 22:21:10.180113 DQS Delay:
6009 22:21:10.183238 DQS0 = 0, DQS1 = 0
6010 22:21:10.183321 DQM Delay:
6011 22:21:10.186599 DQM0 = 92, DQM1 = 91
6012 22:21:10.186681 DQ Delay:
6013 22:21:10.190090 DQ0 =96, DQ1 =86, DQ2 =82, DQ3 =88
6014 22:21:10.193388 DQ4 =88, DQ5 =102, DQ6 =106, DQ7 =88
6015 22:21:10.196362 DQ8 =78, DQ9 =80, DQ10 =92, DQ11 =84
6016 22:21:10.200104 DQ12 =100, DQ13 =100, DQ14 =98, DQ15 =98
6017 22:21:10.200187
6018 22:21:10.200253
6019 22:21:10.209935 [DQSOSCAuto] RK1, (LSB)MR18= 0xf23, (MSB)MR19= 0x505, tDQSOscB0 = 410 ps tDQSOscB1 = 417 ps
6020 22:21:10.210020 CH1 RK1: MR19=505, MR18=F23
6021 22:21:10.216025 CH1_RK1: MR19=0x505, MR18=0xF23, DQSOSC=410, MR23=63, INC=64, DEC=42
6022 22:21:10.219565 [RxdqsGatingPostProcess] freq 933
6023 22:21:10.225949 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
6024 22:21:10.229703 best DQS0 dly(2T, 0.5T) = (0, 10)
6025 22:21:10.232821 best DQS1 dly(2T, 0.5T) = (0, 11)
6026 22:21:10.235925 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6027 22:21:10.239073 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
6028 22:21:10.239156 best DQS0 dly(2T, 0.5T) = (0, 10)
6029 22:21:10.242777 best DQS1 dly(2T, 0.5T) = (0, 10)
6030 22:21:10.245789 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6031 22:21:10.249431 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6032 22:21:10.252651 Pre-setting of DQS Precalculation
6033 22:21:10.259445 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6034 22:21:10.265614 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6035 22:21:10.272568 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6036 22:21:10.272652
6037 22:21:10.272718
6038 22:21:10.275760 [Calibration Summary] 1866 Mbps
6039 22:21:10.275845 CH 0, Rank 0
6040 22:21:10.279154 SW Impedance : PASS
6041 22:21:10.282528 DUTY Scan : NO K
6042 22:21:10.282612 ZQ Calibration : PASS
6043 22:21:10.285519 Jitter Meter : NO K
6044 22:21:10.288656 CBT Training : PASS
6045 22:21:10.288740 Write leveling : PASS
6046 22:21:10.292085 RX DQS gating : PASS
6047 22:21:10.295105 RX DQ/DQS(RDDQC) : PASS
6048 22:21:10.295189 TX DQ/DQS : PASS
6049 22:21:10.298490 RX DATLAT : PASS
6050 22:21:10.301747 RX DQ/DQS(Engine): PASS
6051 22:21:10.301831 TX OE : NO K
6052 22:21:10.305356 All Pass.
6053 22:21:10.305460
6054 22:21:10.305601 CH 0, Rank 1
6055 22:21:10.308399 SW Impedance : PASS
6056 22:21:10.308483 DUTY Scan : NO K
6057 22:21:10.312034 ZQ Calibration : PASS
6058 22:21:10.315108 Jitter Meter : NO K
6059 22:21:10.315192 CBT Training : PASS
6060 22:21:10.318315 Write leveling : PASS
6061 22:21:10.321961 RX DQS gating : PASS
6062 22:21:10.322045 RX DQ/DQS(RDDQC) : PASS
6063 22:21:10.324822 TX DQ/DQS : PASS
6064 22:21:10.328404 RX DATLAT : PASS
6065 22:21:10.328487 RX DQ/DQS(Engine): PASS
6066 22:21:10.331506 TX OE : NO K
6067 22:21:10.331589 All Pass.
6068 22:21:10.331655
6069 22:21:10.335126 CH 1, Rank 0
6070 22:21:10.335209 SW Impedance : PASS
6071 22:21:10.338236 DUTY Scan : NO K
6072 22:21:10.341311 ZQ Calibration : PASS
6073 22:21:10.341399 Jitter Meter : NO K
6074 22:21:10.344982 CBT Training : PASS
6075 22:21:10.348113 Write leveling : PASS
6076 22:21:10.348196 RX DQS gating : PASS
6077 22:21:10.351276 RX DQ/DQS(RDDQC) : PASS
6078 22:21:10.354561 TX DQ/DQS : PASS
6079 22:21:10.354645 RX DATLAT : PASS
6080 22:21:10.358382 RX DQ/DQS(Engine): PASS
6081 22:21:10.358491 TX OE : NO K
6082 22:21:10.361084 All Pass.
6083 22:21:10.361168
6084 22:21:10.361233 CH 1, Rank 1
6085 22:21:10.364826 SW Impedance : PASS
6086 22:21:10.367984 DUTY Scan : NO K
6087 22:21:10.368068 ZQ Calibration : PASS
6088 22:21:10.371024 Jitter Meter : NO K
6089 22:21:10.371134 CBT Training : PASS
6090 22:21:10.374765 Write leveling : PASS
6091 22:21:10.377758 RX DQS gating : PASS
6092 22:21:10.377926 RX DQ/DQS(RDDQC) : PASS
6093 22:21:10.381369 TX DQ/DQS : PASS
6094 22:21:10.384329 RX DATLAT : PASS
6095 22:21:10.384413 RX DQ/DQS(Engine): PASS
6096 22:21:10.387778 TX OE : NO K
6097 22:21:10.387861 All Pass.
6098 22:21:10.387926
6099 22:21:10.390948 DramC Write-DBI off
6100 22:21:10.394228 PER_BANK_REFRESH: Hybrid Mode
6101 22:21:10.394312 TX_TRACKING: ON
6102 22:21:10.404360 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6103 22:21:10.407563 [FAST_K] Save calibration result to emmc
6104 22:21:10.410963 dramc_set_vcore_voltage set vcore to 650000
6105 22:21:10.413973 Read voltage for 400, 6
6106 22:21:10.414056 Vio18 = 0
6107 22:21:10.414122 Vcore = 650000
6108 22:21:10.417447 Vdram = 0
6109 22:21:10.417534 Vddq = 0
6110 22:21:10.417601 Vmddr = 0
6111 22:21:10.423633 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6112 22:21:10.427341 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6113 22:21:10.430776 MEM_TYPE=3, freq_sel=20
6114 22:21:10.433758 sv_algorithm_assistance_LP4_800
6115 22:21:10.437417 ============ PULL DRAM RESETB DOWN ============
6116 22:21:10.443624 ========== PULL DRAM RESETB DOWN end =========
6117 22:21:10.447367 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6118 22:21:10.450627 ===================================
6119 22:21:10.453377 LPDDR4 DRAM CONFIGURATION
6120 22:21:10.456988 ===================================
6121 22:21:10.457107 EX_ROW_EN[0] = 0x0
6122 22:21:10.460396 EX_ROW_EN[1] = 0x0
6123 22:21:10.460519 LP4Y_EN = 0x0
6124 22:21:10.463506 WORK_FSP = 0x0
6125 22:21:10.463608 WL = 0x2
6126 22:21:10.466634 RL = 0x2
6127 22:21:10.466731 BL = 0x2
6128 22:21:10.470326 RPST = 0x0
6129 22:21:10.470429 RD_PRE = 0x0
6130 22:21:10.473396 WR_PRE = 0x1
6131 22:21:10.473499 WR_PST = 0x0
6132 22:21:10.477142 DBI_WR = 0x0
6133 22:21:10.480255 DBI_RD = 0x0
6134 22:21:10.480359 OTF = 0x1
6135 22:21:10.483306 ===================================
6136 22:21:10.486813 ===================================
6137 22:21:10.486965 ANA top config
6138 22:21:10.489969 ===================================
6139 22:21:10.493661 DLL_ASYNC_EN = 0
6140 22:21:10.496793 ALL_SLAVE_EN = 1
6141 22:21:10.499828 NEW_RANK_MODE = 1
6142 22:21:10.503119 DLL_IDLE_MODE = 1
6143 22:21:10.503204 LP45_APHY_COMB_EN = 1
6144 22:21:10.506423 TX_ODT_DIS = 1
6145 22:21:10.509779 NEW_8X_MODE = 1
6146 22:21:10.513081 ===================================
6147 22:21:10.516446 ===================================
6148 22:21:10.519875 data_rate = 800
6149 22:21:10.522801 CKR = 1
6150 22:21:10.526338 DQ_P2S_RATIO = 4
6151 22:21:10.529580 ===================================
6152 22:21:10.529664 CA_P2S_RATIO = 4
6153 22:21:10.532547 DQ_CA_OPEN = 0
6154 22:21:10.536184 DQ_SEMI_OPEN = 1
6155 22:21:10.539145 CA_SEMI_OPEN = 1
6156 22:21:10.542663 CA_FULL_RATE = 0
6157 22:21:10.545730 DQ_CKDIV4_EN = 0
6158 22:21:10.545815 CA_CKDIV4_EN = 1
6159 22:21:10.549447 CA_PREDIV_EN = 0
6160 22:21:10.552787 PH8_DLY = 0
6161 22:21:10.555659 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6162 22:21:10.559316 DQ_AAMCK_DIV = 0
6163 22:21:10.562368 CA_AAMCK_DIV = 0
6164 22:21:10.562452 CA_ADMCK_DIV = 4
6165 22:21:10.565849 DQ_TRACK_CA_EN = 0
6166 22:21:10.568947 CA_PICK = 800
6167 22:21:10.572265 CA_MCKIO = 400
6168 22:21:10.575670 MCKIO_SEMI = 400
6169 22:21:10.578770 PLL_FREQ = 3016
6170 22:21:10.581955 DQ_UI_PI_RATIO = 32
6171 22:21:10.585595 CA_UI_PI_RATIO = 32
6172 22:21:10.588486 ===================================
6173 22:21:10.592177 ===================================
6174 22:21:10.592260 memory_type:LPDDR4
6175 22:21:10.595232 GP_NUM : 10
6176 22:21:10.598766 SRAM_EN : 1
6177 22:21:10.598903 MD32_EN : 0
6178 22:21:10.601822 ===================================
6179 22:21:10.604809 [ANA_INIT] >>>>>>>>>>>>>>
6180 22:21:10.608376 <<<<<< [CONFIGURE PHASE]: ANA_TX
6181 22:21:10.611737 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6182 22:21:10.615272 ===================================
6183 22:21:10.618063 data_rate = 800,PCW = 0X7400
6184 22:21:10.621380 ===================================
6185 22:21:10.625224 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6186 22:21:10.628177 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6187 22:21:10.641326 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6188 22:21:10.644893 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6189 22:21:10.647873 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6190 22:21:10.651569 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6191 22:21:10.654690 [ANA_INIT] flow start
6192 22:21:10.657808 [ANA_INIT] PLL >>>>>>>>
6193 22:21:10.657892 [ANA_INIT] PLL <<<<<<<<
6194 22:21:10.660991 [ANA_INIT] MIDPI >>>>>>>>
6195 22:21:10.664712 [ANA_INIT] MIDPI <<<<<<<<
6196 22:21:10.664797 [ANA_INIT] DLL >>>>>>>>
6197 22:21:10.667710 [ANA_INIT] flow end
6198 22:21:10.671314 ============ LP4 DIFF to SE enter ============
6199 22:21:10.674403 ============ LP4 DIFF to SE exit ============
6200 22:21:10.677426 [ANA_INIT] <<<<<<<<<<<<<
6201 22:21:10.680865 [Flow] Enable top DCM control >>>>>
6202 22:21:10.684379 [Flow] Enable top DCM control <<<<<
6203 22:21:10.687464 Enable DLL master slave shuffle
6204 22:21:10.693982 ==============================================================
6205 22:21:10.694065 Gating Mode config
6206 22:21:10.700819 ==============================================================
6207 22:21:10.704293 Config description:
6208 22:21:10.714069 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6209 22:21:10.720220 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6210 22:21:10.723474 SELPH_MODE 0: By rank 1: By Phase
6211 22:21:10.730266 ==============================================================
6212 22:21:10.733677 GAT_TRACK_EN = 0
6213 22:21:10.737350 RX_GATING_MODE = 2
6214 22:21:10.737432 RX_GATING_TRACK_MODE = 2
6215 22:21:10.739974 SELPH_MODE = 1
6216 22:21:10.743518 PICG_EARLY_EN = 1
6217 22:21:10.746591 VALID_LAT_VALUE = 1
6218 22:21:10.753530 ==============================================================
6219 22:21:10.756447 Enter into Gating configuration >>>>
6220 22:21:10.759998 Exit from Gating configuration <<<<
6221 22:21:10.763121 Enter into DVFS_PRE_config >>>>>
6222 22:21:10.772908 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6223 22:21:10.776682 Exit from DVFS_PRE_config <<<<<
6224 22:21:10.779601 Enter into PICG configuration >>>>
6225 22:21:10.782724 Exit from PICG configuration <<<<
6226 22:21:10.786464 [RX_INPUT] configuration >>>>>
6227 22:21:10.789554 [RX_INPUT] configuration <<<<<
6228 22:21:10.792595 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6229 22:21:10.799713 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6230 22:21:10.805875 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6231 22:21:10.812613 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6232 22:21:10.819280 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6233 22:21:10.822298 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6234 22:21:10.829229 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6235 22:21:10.832694 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6236 22:21:10.835628 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6237 22:21:10.839121 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6238 22:21:10.845309 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6239 22:21:10.848551 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6240 22:21:10.852082 ===================================
6241 22:21:10.855195 LPDDR4 DRAM CONFIGURATION
6242 22:21:10.858604 ===================================
6243 22:21:10.858688 EX_ROW_EN[0] = 0x0
6244 22:21:10.862240 EX_ROW_EN[1] = 0x0
6245 22:21:10.862324 LP4Y_EN = 0x0
6246 22:21:10.865189 WORK_FSP = 0x0
6247 22:21:10.865273 WL = 0x2
6248 22:21:10.868861 RL = 0x2
6249 22:21:10.871896 BL = 0x2
6250 22:21:10.871981 RPST = 0x0
6251 22:21:10.875028 RD_PRE = 0x0
6252 22:21:10.875112 WR_PRE = 0x1
6253 22:21:10.878545 WR_PST = 0x0
6254 22:21:10.878629 DBI_WR = 0x0
6255 22:21:10.881643 DBI_RD = 0x0
6256 22:21:10.881726 OTF = 0x1
6257 22:21:10.884779 ===================================
6258 22:21:10.888512 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6259 22:21:10.894983 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6260 22:21:10.898363 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6261 22:21:10.901654 ===================================
6262 22:21:10.905249 LPDDR4 DRAM CONFIGURATION
6263 22:21:10.908147 ===================================
6264 22:21:10.908231 EX_ROW_EN[0] = 0x10
6265 22:21:10.911785 EX_ROW_EN[1] = 0x0
6266 22:21:10.911868 LP4Y_EN = 0x0
6267 22:21:10.914780 WORK_FSP = 0x0
6268 22:21:10.914905 WL = 0x2
6269 22:21:10.917784 RL = 0x2
6270 22:21:10.921351 BL = 0x2
6271 22:21:10.921472 RPST = 0x0
6272 22:21:10.924556 RD_PRE = 0x0
6273 22:21:10.924639 WR_PRE = 0x1
6274 22:21:10.928006 WR_PST = 0x0
6275 22:21:10.928091 DBI_WR = 0x0
6276 22:21:10.931126 DBI_RD = 0x0
6277 22:21:10.931209 OTF = 0x1
6278 22:21:10.934276 ===================================
6279 22:21:10.941081 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6280 22:21:10.945365 nWR fixed to 30
6281 22:21:10.948311 [ModeRegInit_LP4] CH0 RK0
6282 22:21:10.948395 [ModeRegInit_LP4] CH0 RK1
6283 22:21:10.951759 [ModeRegInit_LP4] CH1 RK0
6284 22:21:10.954728 [ModeRegInit_LP4] CH1 RK1
6285 22:21:10.954813 match AC timing 19
6286 22:21:10.962311 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6287 22:21:10.964931 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6288 22:21:10.968446 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6289 22:21:10.974707 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6290 22:21:10.978337 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6291 22:21:10.978421 ==
6292 22:21:10.981459 Dram Type= 6, Freq= 0, CH_0, rank 0
6293 22:21:10.984994 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6294 22:21:10.985079 ==
6295 22:21:10.991207 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6296 22:21:10.998046 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6297 22:21:11.001100 [CA 0] Center 36 (8~64) winsize 57
6298 22:21:11.004097 [CA 1] Center 36 (8~64) winsize 57
6299 22:21:11.007597 [CA 2] Center 36 (8~64) winsize 57
6300 22:21:11.010678 [CA 3] Center 36 (8~64) winsize 57
6301 22:21:11.014297 [CA 4] Center 36 (8~64) winsize 57
6302 22:21:11.017473 [CA 5] Center 36 (8~64) winsize 57
6303 22:21:11.017556
6304 22:21:11.020621 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6305 22:21:11.020704
6306 22:21:11.024287 [CATrainingPosCal] consider 1 rank data
6307 22:21:11.027488 u2DelayCellTimex100 = 270/100 ps
6308 22:21:11.031018 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6309 22:21:11.033940 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6310 22:21:11.037078 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6311 22:21:11.040770 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6312 22:21:11.043689 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6313 22:21:11.047184 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6314 22:21:11.047268
6315 22:21:11.054046 CA PerBit enable=1, Macro0, CA PI delay=36
6316 22:21:11.054131
6317 22:21:11.054197 [CBTSetCACLKResult] CA Dly = 36
6318 22:21:11.056853 CS Dly: 1 (0~32)
6319 22:21:11.056938 ==
6320 22:21:11.060393 Dram Type= 6, Freq= 0, CH_0, rank 1
6321 22:21:11.063845 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6322 22:21:11.063929 ==
6323 22:21:11.070150 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6324 22:21:11.077187 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6325 22:21:11.080018 [CA 0] Center 36 (8~64) winsize 57
6326 22:21:11.083758 [CA 1] Center 36 (8~64) winsize 57
6327 22:21:11.086821 [CA 2] Center 36 (8~64) winsize 57
6328 22:21:11.089779 [CA 3] Center 36 (8~64) winsize 57
6329 22:21:11.093469 [CA 4] Center 36 (8~64) winsize 57
6330 22:21:11.093553 [CA 5] Center 36 (8~64) winsize 57
6331 22:21:11.096687
6332 22:21:11.099837 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6333 22:21:11.099921
6334 22:21:11.103484 [CATrainingPosCal] consider 2 rank data
6335 22:21:11.106671 u2DelayCellTimex100 = 270/100 ps
6336 22:21:11.109871 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6337 22:21:11.113229 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6338 22:21:11.116317 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6339 22:21:11.119354 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6340 22:21:11.123037 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6341 22:21:11.126061 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6342 22:21:11.126144
6343 22:21:11.129285 CA PerBit enable=1, Macro0, CA PI delay=36
6344 22:21:11.133022
6345 22:21:11.133105 [CBTSetCACLKResult] CA Dly = 36
6346 22:21:11.136008 CS Dly: 1 (0~32)
6347 22:21:11.136091
6348 22:21:11.139074 ----->DramcWriteLeveling(PI) begin...
6349 22:21:11.139185 ==
6350 22:21:11.142785 Dram Type= 6, Freq= 0, CH_0, rank 0
6351 22:21:11.145863 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6352 22:21:11.145947 ==
6353 22:21:11.148995 Write leveling (Byte 0): 40 => 8
6354 22:21:11.152512 Write leveling (Byte 1): 40 => 8
6355 22:21:11.155888 DramcWriteLeveling(PI) end<-----
6356 22:21:11.155972
6357 22:21:11.156037 ==
6358 22:21:11.159294 Dram Type= 6, Freq= 0, CH_0, rank 0
6359 22:21:11.162094 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6360 22:21:11.165448 ==
6361 22:21:11.165532 [Gating] SW mode calibration
6362 22:21:11.175368 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6363 22:21:11.178987 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6364 22:21:11.181861 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6365 22:21:11.188403 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6366 22:21:11.191949 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6367 22:21:11.195051 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6368 22:21:11.201720 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6369 22:21:11.204776 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6370 22:21:11.208394 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6371 22:21:11.215001 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6372 22:21:11.218172 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6373 22:21:11.221781 Total UI for P1: 0, mck2ui 16
6374 22:21:11.224821 best dqsien dly found for B0: ( 0, 14, 24)
6375 22:21:11.228497 Total UI for P1: 0, mck2ui 16
6376 22:21:11.231553 best dqsien dly found for B1: ( 0, 14, 24)
6377 22:21:11.234608 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6378 22:21:11.238399 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6379 22:21:11.238480
6380 22:21:11.241636 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6381 22:21:11.248103 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6382 22:21:11.248184 [Gating] SW calibration Done
6383 22:21:11.248248 ==
6384 22:21:11.251120 Dram Type= 6, Freq= 0, CH_0, rank 0
6385 22:21:11.257880 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6386 22:21:11.257992 ==
6387 22:21:11.258057 RX Vref Scan: 0
6388 22:21:11.258116
6389 22:21:11.261232 RX Vref 0 -> 0, step: 1
6390 22:21:11.261314
6391 22:21:11.264774 RX Delay -410 -> 252, step: 16
6392 22:21:11.268062 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6393 22:21:11.270926 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6394 22:21:11.277720 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6395 22:21:11.281019 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6396 22:21:11.284568 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6397 22:21:11.287542 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6398 22:21:11.294020 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6399 22:21:11.297425 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6400 22:21:11.300992 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6401 22:21:11.304289 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6402 22:21:11.310980 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6403 22:21:11.314014 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6404 22:21:11.316996 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6405 22:21:11.323537 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6406 22:21:11.327140 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6407 22:21:11.330218 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6408 22:21:11.330301 ==
6409 22:21:11.333834 Dram Type= 6, Freq= 0, CH_0, rank 0
6410 22:21:11.336922 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6411 22:21:11.340068 ==
6412 22:21:11.340150 DQS Delay:
6413 22:21:11.340217 DQS0 = 59, DQS1 = 59
6414 22:21:11.343749 DQM Delay:
6415 22:21:11.343831 DQM0 = 18, DQM1 = 10
6416 22:21:11.346648 DQ Delay:
6417 22:21:11.350316 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6418 22:21:11.350435 DQ4 =16, DQ5 =0, DQ6 =32, DQ7 =32
6419 22:21:11.353458 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =8
6420 22:21:11.356542 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6421 22:21:11.356625
6422 22:21:11.356689
6423 22:21:11.360258 ==
6424 22:21:11.363274 Dram Type= 6, Freq= 0, CH_0, rank 0
6425 22:21:11.366356 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6426 22:21:11.366432 ==
6427 22:21:11.366495
6428 22:21:11.366553
6429 22:21:11.370029 TX Vref Scan disable
6430 22:21:11.370111 == TX Byte 0 ==
6431 22:21:11.373044 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6432 22:21:11.379634 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6433 22:21:11.379720 == TX Byte 1 ==
6434 22:21:11.383175 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6435 22:21:11.389470 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6436 22:21:11.389554 ==
6437 22:21:11.392835 Dram Type= 6, Freq= 0, CH_0, rank 0
6438 22:21:11.396430 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6439 22:21:11.396528 ==
6440 22:21:11.396623
6441 22:21:11.396699
6442 22:21:11.399392 TX Vref Scan disable
6443 22:21:11.399475 == TX Byte 0 ==
6444 22:21:11.405858 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6445 22:21:11.409315 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6446 22:21:11.409398 == TX Byte 1 ==
6447 22:21:11.412911 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6448 22:21:11.419158 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6449 22:21:11.419261
6450 22:21:11.419332 [DATLAT]
6451 22:21:11.422739 Freq=400, CH0 RK0
6452 22:21:11.422868
6453 22:21:11.422949 DATLAT Default: 0xf
6454 22:21:11.425808 0, 0xFFFF, sum = 0
6455 22:21:11.425885 1, 0xFFFF, sum = 0
6456 22:21:11.428917 2, 0xFFFF, sum = 0
6457 22:21:11.428990 3, 0xFFFF, sum = 0
6458 22:21:11.432475 4, 0xFFFF, sum = 0
6459 22:21:11.432574 5, 0xFFFF, sum = 0
6460 22:21:11.435606 6, 0xFFFF, sum = 0
6461 22:21:11.435692 7, 0xFFFF, sum = 0
6462 22:21:11.439288 8, 0xFFFF, sum = 0
6463 22:21:11.439372 9, 0xFFFF, sum = 0
6464 22:21:11.442461 10, 0xFFFF, sum = 0
6465 22:21:11.442572 11, 0xFFFF, sum = 0
6466 22:21:11.445494 12, 0xFFFF, sum = 0
6467 22:21:11.449070 13, 0x0, sum = 1
6468 22:21:11.449153 14, 0x0, sum = 2
6469 22:21:11.449220 15, 0x0, sum = 3
6470 22:21:11.451998 16, 0x0, sum = 4
6471 22:21:11.452081 best_step = 14
6472 22:21:11.452145
6473 22:21:11.455685 ==
6474 22:21:11.455767 Dram Type= 6, Freq= 0, CH_0, rank 0
6475 22:21:11.461944 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6476 22:21:11.462028 ==
6477 22:21:11.462103 RX Vref Scan: 1
6478 22:21:11.462169
6479 22:21:11.465658 RX Vref 0 -> 0, step: 1
6480 22:21:11.465740
6481 22:21:11.468640 RX Delay -359 -> 252, step: 8
6482 22:21:11.468723
6483 22:21:11.472299 Set Vref, RX VrefLevel [Byte0]: 60
6484 22:21:11.475443 [Byte1]: 48
6485 22:21:11.479027
6486 22:21:11.479109 Final RX Vref Byte 0 = 60 to rank0
6487 22:21:11.482175 Final RX Vref Byte 1 = 48 to rank0
6488 22:21:11.485620 Final RX Vref Byte 0 = 60 to rank1
6489 22:21:11.488936 Final RX Vref Byte 1 = 48 to rank1==
6490 22:21:11.491800 Dram Type= 6, Freq= 0, CH_0, rank 0
6491 22:21:11.498737 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6492 22:21:11.498878 ==
6493 22:21:11.498983 DQS Delay:
6494 22:21:11.502140 DQS0 = 60, DQS1 = 68
6495 22:21:11.502245 DQM Delay:
6496 22:21:11.502345 DQM0 = 14, DQM1 = 13
6497 22:21:11.505089 DQ Delay:
6498 22:21:11.508471 DQ0 =12, DQ1 =16, DQ2 =8, DQ3 =12
6499 22:21:11.511952 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6500 22:21:11.514765 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6501 22:21:11.518379 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6502 22:21:11.518486
6503 22:21:11.518578
6504 22:21:11.525171 [DQSOSCAuto] RK0, (LSB)MR18= 0x7f7f, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
6505 22:21:11.528061 CH0 RK0: MR19=C0C, MR18=7F7F
6506 22:21:11.534745 CH0_RK0: MR19=0xC0C, MR18=0x7F7F, DQSOSC=393, MR23=63, INC=382, DEC=254
6507 22:21:11.534855 ==
6508 22:21:11.538170 Dram Type= 6, Freq= 0, CH_0, rank 1
6509 22:21:11.541261 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6510 22:21:11.541373 ==
6511 22:21:11.544931 [Gating] SW mode calibration
6512 22:21:11.551121 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6513 22:21:11.557862 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6514 22:21:11.561520 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6515 22:21:11.564554 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6516 22:21:11.571201 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6517 22:21:11.574201 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6518 22:21:11.577887 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6519 22:21:11.584040 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6520 22:21:11.587637 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6521 22:21:11.590654 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6522 22:21:11.597681 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6523 22:21:11.600661 Total UI for P1: 0, mck2ui 16
6524 22:21:11.604344 best dqsien dly found for B0: ( 0, 14, 24)
6525 22:21:11.607601 Total UI for P1: 0, mck2ui 16
6526 22:21:11.610732 best dqsien dly found for B1: ( 0, 14, 24)
6527 22:21:11.614184 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6528 22:21:11.617473 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6529 22:21:11.617556
6530 22:21:11.620526 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6531 22:21:11.623911 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6532 22:21:11.627012 [Gating] SW calibration Done
6533 22:21:11.627095 ==
6534 22:21:11.630475 Dram Type= 6, Freq= 0, CH_0, rank 1
6535 22:21:11.633865 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6536 22:21:11.634001 ==
6537 22:21:11.636944 RX Vref Scan: 0
6538 22:21:11.637027
6539 22:21:11.640463 RX Vref 0 -> 0, step: 1
6540 22:21:11.640578
6541 22:21:11.643596 RX Delay -410 -> 252, step: 16
6542 22:21:11.646699 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6543 22:21:11.650406 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6544 22:21:11.653509 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6545 22:21:11.660437 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6546 22:21:11.663484 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6547 22:21:11.666787 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6548 22:21:11.669747 iDelay=230, Bit 6, Center -35 (-298 ~ 229) 528
6549 22:21:11.676343 iDelay=230, Bit 7, Center -35 (-298 ~ 229) 528
6550 22:21:11.680283 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6551 22:21:11.683039 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6552 22:21:11.686172 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6553 22:21:11.692978 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6554 22:21:11.696078 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6555 22:21:11.699879 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6556 22:21:11.706324 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6557 22:21:11.709815 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6558 22:21:11.709901 ==
6559 22:21:11.712684 Dram Type= 6, Freq= 0, CH_0, rank 1
6560 22:21:11.716291 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6561 22:21:11.716379 ==
6562 22:21:11.719355 DQS Delay:
6563 22:21:11.719470 DQS0 = 59, DQS1 = 59
6564 22:21:11.719563 DQM Delay:
6565 22:21:11.722759 DQM0 = 16, DQM1 = 10
6566 22:21:11.722891 DQ Delay:
6567 22:21:11.726329 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6568 22:21:11.729162 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6569 22:21:11.732841 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6570 22:21:11.736090 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6571 22:21:11.736202
6572 22:21:11.736312
6573 22:21:11.736403 ==
6574 22:21:11.738934 Dram Type= 6, Freq= 0, CH_0, rank 1
6575 22:21:11.746079 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6576 22:21:11.746195 ==
6577 22:21:11.746291
6578 22:21:11.746381
6579 22:21:11.746471 TX Vref Scan disable
6580 22:21:11.749059 == TX Byte 0 ==
6581 22:21:11.752748 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6582 22:21:11.755798 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6583 22:21:11.759055 == TX Byte 1 ==
6584 22:21:11.762078 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6585 22:21:11.765642 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6586 22:21:11.765753 ==
6587 22:21:11.768693 Dram Type= 6, Freq= 0, CH_0, rank 1
6588 22:21:11.775513 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6589 22:21:11.775630 ==
6590 22:21:11.775729
6591 22:21:11.775822
6592 22:21:11.775914 TX Vref Scan disable
6593 22:21:11.778498 == TX Byte 0 ==
6594 22:21:11.782094 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6595 22:21:11.785158 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6596 22:21:11.788932 == TX Byte 1 ==
6597 22:21:11.792039 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6598 22:21:11.795392 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6599 22:21:11.795505
6600 22:21:11.798410 [DATLAT]
6601 22:21:11.798522 Freq=400, CH0 RK1
6602 22:21:11.798620
6603 22:21:11.802096 DATLAT Default: 0xe
6604 22:21:11.802209 0, 0xFFFF, sum = 0
6605 22:21:11.805132 1, 0xFFFF, sum = 0
6606 22:21:11.805246 2, 0xFFFF, sum = 0
6607 22:21:11.808639 3, 0xFFFF, sum = 0
6608 22:21:11.808755 4, 0xFFFF, sum = 0
6609 22:21:11.811487 5, 0xFFFF, sum = 0
6610 22:21:11.815052 6, 0xFFFF, sum = 0
6611 22:21:11.815162 7, 0xFFFF, sum = 0
6612 22:21:11.818492 8, 0xFFFF, sum = 0
6613 22:21:11.818607 9, 0xFFFF, sum = 0
6614 22:21:11.821872 10, 0xFFFF, sum = 0
6615 22:21:11.821987 11, 0xFFFF, sum = 0
6616 22:21:11.825094 12, 0xFFFF, sum = 0
6617 22:21:11.825210 13, 0x0, sum = 1
6618 22:21:11.827873 14, 0x0, sum = 2
6619 22:21:11.827987 15, 0x0, sum = 3
6620 22:21:11.831586 16, 0x0, sum = 4
6621 22:21:11.831700 best_step = 14
6622 22:21:11.831802
6623 22:21:11.831892 ==
6624 22:21:11.834617 Dram Type= 6, Freq= 0, CH_0, rank 1
6625 22:21:11.838193 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6626 22:21:11.838306 ==
6627 22:21:11.841739 RX Vref Scan: 0
6628 22:21:11.841846
6629 22:21:11.844510 RX Vref 0 -> 0, step: 1
6630 22:21:11.844623
6631 22:21:11.847696 RX Delay -359 -> 252, step: 8
6632 22:21:11.854840 iDelay=217, Bit 0, Center -52 (-303 ~ 200) 504
6633 22:21:11.857780 iDelay=217, Bit 1, Center -44 (-295 ~ 208) 504
6634 22:21:11.860838 iDelay=217, Bit 2, Center -52 (-303 ~ 200) 504
6635 22:21:11.864013 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6636 22:21:11.870699 iDelay=217, Bit 4, Center -52 (-303 ~ 200) 504
6637 22:21:11.874385 iDelay=217, Bit 5, Center -60 (-311 ~ 192) 504
6638 22:21:11.877451 iDelay=217, Bit 6, Center -40 (-295 ~ 216) 512
6639 22:21:11.880613 iDelay=217, Bit 7, Center -36 (-287 ~ 216) 504
6640 22:21:11.887242 iDelay=217, Bit 8, Center -64 (-311 ~ 184) 496
6641 22:21:11.890281 iDelay=217, Bit 9, Center -72 (-319 ~ 176) 496
6642 22:21:11.894142 iDelay=217, Bit 10, Center -52 (-303 ~ 200) 504
6643 22:21:11.896954 iDelay=217, Bit 11, Center -64 (-311 ~ 184) 496
6644 22:21:11.903984 iDelay=217, Bit 12, Center -48 (-295 ~ 200) 496
6645 22:21:11.907140 iDelay=217, Bit 13, Center -44 (-295 ~ 208) 504
6646 22:21:11.910293 iDelay=217, Bit 14, Center -44 (-295 ~ 208) 504
6647 22:21:11.916858 iDelay=217, Bit 15, Center -48 (-295 ~ 200) 496
6648 22:21:11.916944 ==
6649 22:21:11.919884 Dram Type= 6, Freq= 0, CH_0, rank 1
6650 22:21:11.923205 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6651 22:21:11.923291 ==
6652 22:21:11.923359 DQS Delay:
6653 22:21:11.926964 DQS0 = 60, DQS1 = 72
6654 22:21:11.927049 DQM Delay:
6655 22:21:11.929731 DQM0 = 11, DQM1 = 17
6656 22:21:11.929815 DQ Delay:
6657 22:21:11.933224 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6658 22:21:11.936311 DQ4 =8, DQ5 =0, DQ6 =20, DQ7 =24
6659 22:21:11.939941 DQ8 =8, DQ9 =0, DQ10 =20, DQ11 =8
6660 22:21:11.942896 DQ12 =24, DQ13 =28, DQ14 =28, DQ15 =24
6661 22:21:11.942981
6662 22:21:11.943048
6663 22:21:11.949496 [DQSOSCAuto] RK1, (LSB)MR18= 0xca7f, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 384 ps
6664 22:21:11.952917 CH0 RK1: MR19=C0C, MR18=CA7F
6665 22:21:11.959182 CH0_RK1: MR19=0xC0C, MR18=0xCA7F, DQSOSC=384, MR23=63, INC=400, DEC=267
6666 22:21:11.963079 [RxdqsGatingPostProcess] freq 400
6667 22:21:11.969202 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6668 22:21:11.972804 best DQS0 dly(2T, 0.5T) = (0, 10)
6669 22:21:11.975934 best DQS1 dly(2T, 0.5T) = (0, 10)
6670 22:21:11.976013 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6671 22:21:11.979048 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6672 22:21:11.982786 best DQS0 dly(2T, 0.5T) = (0, 10)
6673 22:21:11.985778 best DQS1 dly(2T, 0.5T) = (0, 10)
6674 22:21:11.989321 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6675 22:21:11.992402 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6676 22:21:11.995627 Pre-setting of DQS Precalculation
6677 22:21:12.002664 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6678 22:21:12.002751 ==
6679 22:21:12.005629 Dram Type= 6, Freq= 0, CH_1, rank 0
6680 22:21:12.009273 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6681 22:21:12.009360 ==
6682 22:21:12.015466 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6683 22:21:12.022064 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6684 22:21:12.025708 [CA 0] Center 36 (8~64) winsize 57
6685 22:21:12.025794 [CA 1] Center 36 (8~64) winsize 57
6686 22:21:12.028682 [CA 2] Center 36 (8~64) winsize 57
6687 22:21:12.032128 [CA 3] Center 36 (8~64) winsize 57
6688 22:21:12.035510 [CA 4] Center 36 (8~64) winsize 57
6689 22:21:12.038536 [CA 5] Center 36 (8~64) winsize 57
6690 22:21:12.038616
6691 22:21:12.042380 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6692 22:21:12.042468
6693 22:21:12.045509 [CATrainingPosCal] consider 1 rank data
6694 22:21:12.048971 u2DelayCellTimex100 = 270/100 ps
6695 22:21:12.051921 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6696 22:21:12.058536 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6697 22:21:12.061659 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6698 22:21:12.065391 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6699 22:21:12.068593 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6700 22:21:12.072099 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6701 22:21:12.072183
6702 22:21:12.075115 CA PerBit enable=1, Macro0, CA PI delay=36
6703 22:21:12.075198
6704 22:21:12.078085 [CBTSetCACLKResult] CA Dly = 36
6705 22:21:12.081765 CS Dly: 1 (0~32)
6706 22:21:12.081860 ==
6707 22:21:12.084837 Dram Type= 6, Freq= 0, CH_1, rank 1
6708 22:21:12.088570 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6709 22:21:12.088654 ==
6710 22:21:12.095273 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6711 22:21:12.098414 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6712 22:21:12.101519 [CA 0] Center 36 (8~64) winsize 57
6713 22:21:12.104975 [CA 1] Center 36 (8~64) winsize 57
6714 22:21:12.107989 [CA 2] Center 36 (8~64) winsize 57
6715 22:21:12.111543 [CA 3] Center 36 (8~64) winsize 57
6716 22:21:12.114733 [CA 4] Center 36 (8~64) winsize 57
6717 22:21:12.117851 [CA 5] Center 36 (8~64) winsize 57
6718 22:21:12.117934
6719 22:21:12.121794 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6720 22:21:12.121877
6721 22:21:12.124785 [CATrainingPosCal] consider 2 rank data
6722 22:21:12.128186 u2DelayCellTimex100 = 270/100 ps
6723 22:21:12.131186 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6724 22:21:12.134689 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6725 22:21:12.140969 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6726 22:21:12.144535 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6727 22:21:12.147515 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6728 22:21:12.151330 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6729 22:21:12.151413
6730 22:21:12.154216 CA PerBit enable=1, Macro0, CA PI delay=36
6731 22:21:12.154300
6732 22:21:12.157618 [CBTSetCACLKResult] CA Dly = 36
6733 22:21:12.157730 CS Dly: 1 (0~32)
6734 22:21:12.157796
6735 22:21:12.161138 ----->DramcWriteLeveling(PI) begin...
6736 22:21:12.164265 ==
6737 22:21:12.167835 Dram Type= 6, Freq= 0, CH_1, rank 0
6738 22:21:12.170998 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6739 22:21:12.171081 ==
6740 22:21:12.174519 Write leveling (Byte 0): 40 => 8
6741 22:21:12.177307 Write leveling (Byte 1): 40 => 8
6742 22:21:12.180918 DramcWriteLeveling(PI) end<-----
6743 22:21:12.181002
6744 22:21:12.181068 ==
6745 22:21:12.183987 Dram Type= 6, Freq= 0, CH_1, rank 0
6746 22:21:12.187088 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6747 22:21:12.187183 ==
6748 22:21:12.190956 [Gating] SW mode calibration
6749 22:21:12.197548 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6750 22:21:12.204159 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6751 22:21:12.207135 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6752 22:21:12.210257 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6753 22:21:12.216850 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6754 22:21:12.220578 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6755 22:21:12.223680 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6756 22:21:12.229865 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6757 22:21:12.233451 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6758 22:21:12.237248 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6759 22:21:12.243357 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6760 22:21:12.243459 Total UI for P1: 0, mck2ui 16
6761 22:21:12.249651 best dqsien dly found for B0: ( 0, 14, 24)
6762 22:21:12.249766 Total UI for P1: 0, mck2ui 16
6763 22:21:12.256409 best dqsien dly found for B1: ( 0, 14, 24)
6764 22:21:12.259903 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6765 22:21:12.262913 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6766 22:21:12.263027
6767 22:21:12.266279 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6768 22:21:12.269734 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6769 22:21:12.273280 [Gating] SW calibration Done
6770 22:21:12.273385 ==
6771 22:21:12.276271 Dram Type= 6, Freq= 0, CH_1, rank 0
6772 22:21:12.279905 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6773 22:21:12.280011 ==
6774 22:21:12.282788 RX Vref Scan: 0
6775 22:21:12.282894
6776 22:21:12.283021 RX Vref 0 -> 0, step: 1
6777 22:21:12.283084
6778 22:21:12.286414 RX Delay -410 -> 252, step: 16
6779 22:21:12.292523 iDelay=230, Bit 0, Center -35 (-298 ~ 229) 528
6780 22:21:12.296338 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6781 22:21:12.299307 iDelay=230, Bit 2, Center -51 (-314 ~ 213) 528
6782 22:21:12.302805 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6783 22:21:12.308965 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6784 22:21:12.312811 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6785 22:21:12.315829 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6786 22:21:12.319333 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6787 22:21:12.325424 iDelay=230, Bit 8, Center -67 (-330 ~ 197) 528
6788 22:21:12.329155 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6789 22:21:12.332335 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6790 22:21:12.339069 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6791 22:21:12.342042 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6792 22:21:12.345286 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6793 22:21:12.349070 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6794 22:21:12.355089 iDelay=230, Bit 15, Center -35 (-298 ~ 229) 528
6795 22:21:12.355195 ==
6796 22:21:12.358796 Dram Type= 6, Freq= 0, CH_1, rank 0
6797 22:21:12.361915 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6798 22:21:12.362028 ==
6799 22:21:12.362162 DQS Delay:
6800 22:21:12.365002 DQS0 = 51, DQS1 = 67
6801 22:21:12.365105 DQM Delay:
6802 22:21:12.368583 DQM0 = 12, DQM1 = 18
6803 22:21:12.368726 DQ Delay:
6804 22:21:12.371417 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6805 22:21:12.374822 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6806 22:21:12.378112 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6807 22:21:12.381519 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =32
6808 22:21:12.381622
6809 22:21:12.381749
6810 22:21:12.381838 ==
6811 22:21:12.385117 Dram Type= 6, Freq= 0, CH_1, rank 0
6812 22:21:12.388134 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6813 22:21:12.388207 ==
6814 22:21:12.388269
6815 22:21:12.391361
6816 22:21:12.391465 TX Vref Scan disable
6817 22:21:12.395084 == TX Byte 0 ==
6818 22:21:12.398524 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6819 22:21:12.401379 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6820 22:21:12.404844 == TX Byte 1 ==
6821 22:21:12.407727 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6822 22:21:12.411444 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6823 22:21:12.411545 ==
6824 22:21:12.414463 Dram Type= 6, Freq= 0, CH_1, rank 0
6825 22:21:12.417636 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6826 22:21:12.421347 ==
6827 22:21:12.421498
6828 22:21:12.421597
6829 22:21:12.421689 TX Vref Scan disable
6830 22:21:12.424260 == TX Byte 0 ==
6831 22:21:12.427908 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6832 22:21:12.430938 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6833 22:21:12.434622 == TX Byte 1 ==
6834 22:21:12.437758 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6835 22:21:12.440790 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6836 22:21:12.440899
6837 22:21:12.444033 [DATLAT]
6838 22:21:12.444133 Freq=400, CH1 RK0
6839 22:21:12.444241
6840 22:21:12.447624 DATLAT Default: 0xf
6841 22:21:12.447725 0, 0xFFFF, sum = 0
6842 22:21:12.450739 1, 0xFFFF, sum = 0
6843 22:21:12.450852 2, 0xFFFF, sum = 0
6844 22:21:12.454183 3, 0xFFFF, sum = 0
6845 22:21:12.454290 4, 0xFFFF, sum = 0
6846 22:21:12.457165 5, 0xFFFF, sum = 0
6847 22:21:12.457274 6, 0xFFFF, sum = 0
6848 22:21:12.460556 7, 0xFFFF, sum = 0
6849 22:21:12.460657 8, 0xFFFF, sum = 0
6850 22:21:12.463969 9, 0xFFFF, sum = 0
6851 22:21:12.464072 10, 0xFFFF, sum = 0
6852 22:21:12.467025 11, 0xFFFF, sum = 0
6853 22:21:12.470135 12, 0xFFFF, sum = 0
6854 22:21:12.470235 13, 0x0, sum = 1
6855 22:21:12.473871 14, 0x0, sum = 2
6856 22:21:12.473980 15, 0x0, sum = 3
6857 22:21:12.474077 16, 0x0, sum = 4
6858 22:21:12.476805 best_step = 14
6859 22:21:12.476903
6860 22:21:12.477002 ==
6861 22:21:12.480403 Dram Type= 6, Freq= 0, CH_1, rank 0
6862 22:21:12.484160 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6863 22:21:12.484264 ==
6864 22:21:12.487326 RX Vref Scan: 1
6865 22:21:12.487428
6866 22:21:12.487520 RX Vref 0 -> 0, step: 1
6867 22:21:12.490307
6868 22:21:12.490408 RX Delay -375 -> 252, step: 8
6869 22:21:12.490504
6870 22:21:12.493376 Set Vref, RX VrefLevel [Byte0]: 56
6871 22:21:12.496805 [Byte1]: 53
6872 22:21:12.502001
6873 22:21:12.502112 Final RX Vref Byte 0 = 56 to rank0
6874 22:21:12.505767 Final RX Vref Byte 1 = 53 to rank0
6875 22:21:12.508781 Final RX Vref Byte 0 = 56 to rank1
6876 22:21:12.512203 Final RX Vref Byte 1 = 53 to rank1==
6877 22:21:12.515253 Dram Type= 6, Freq= 0, CH_1, rank 0
6878 22:21:12.521973 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6879 22:21:12.522084 ==
6880 22:21:12.522190 DQS Delay:
6881 22:21:12.525103 DQS0 = 52, DQS1 = 64
6882 22:21:12.525187 DQM Delay:
6883 22:21:12.525253 DQM0 = 9, DQM1 = 10
6884 22:21:12.528574 DQ Delay:
6885 22:21:12.531705 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =4
6886 22:21:12.531790 DQ4 =8, DQ5 =16, DQ6 =20, DQ7 =4
6887 22:21:12.535475 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6888 22:21:12.538711 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6889 22:21:12.541782
6890 22:21:12.541864
6891 22:21:12.548494 [DQSOSCAuto] RK0, (LSB)MR18= 0x5769, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 398 ps
6892 22:21:12.551589 CH1 RK0: MR19=C0C, MR18=5769
6893 22:21:12.558040 CH1_RK0: MR19=0xC0C, MR18=0x5769, DQSOSC=396, MR23=63, INC=376, DEC=251
6894 22:21:12.558124 ==
6895 22:21:12.561332 Dram Type= 6, Freq= 0, CH_1, rank 1
6896 22:21:12.564881 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6897 22:21:12.564996 ==
6898 22:21:12.567814 [Gating] SW mode calibration
6899 22:21:12.574990 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6900 22:21:12.581021 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6901 22:21:12.584851 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6902 22:21:12.587662 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6903 22:21:12.594420 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6904 22:21:12.597935 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6905 22:21:12.601036 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6906 22:21:12.607940 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6907 22:21:12.610767 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6908 22:21:12.614254 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6909 22:21:12.620858 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6910 22:21:12.620965 Total UI for P1: 0, mck2ui 16
6911 22:21:12.627766 best dqsien dly found for B0: ( 0, 14, 24)
6912 22:21:12.627874 Total UI for P1: 0, mck2ui 16
6913 22:21:12.633803 best dqsien dly found for B1: ( 0, 14, 24)
6914 22:21:12.637663 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6915 22:21:12.640781 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6916 22:21:12.640864
6917 22:21:12.644012 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6918 22:21:12.647117 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6919 22:21:12.650760 [Gating] SW calibration Done
6920 22:21:12.650916 ==
6921 22:21:12.653873 Dram Type= 6, Freq= 0, CH_1, rank 1
6922 22:21:12.657050 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6923 22:21:12.657159 ==
6924 22:21:12.660688 RX Vref Scan: 0
6925 22:21:12.660789
6926 22:21:12.660880 RX Vref 0 -> 0, step: 1
6927 22:21:12.663774
6928 22:21:12.663852 RX Delay -410 -> 252, step: 16
6929 22:21:12.670544 iDelay=230, Bit 0, Center -35 (-298 ~ 229) 528
6930 22:21:12.673454 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6931 22:21:12.676901 iDelay=230, Bit 2, Center -59 (-314 ~ 197) 512
6932 22:21:12.680417 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6933 22:21:12.686836 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6934 22:21:12.689891 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6935 22:21:12.693526 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6936 22:21:12.697020 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6937 22:21:12.703641 iDelay=230, Bit 8, Center -67 (-330 ~ 197) 528
6938 22:21:12.706690 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6939 22:21:12.709957 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6940 22:21:12.716736 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6941 22:21:12.720062 iDelay=230, Bit 12, Center -35 (-298 ~ 229) 528
6942 22:21:12.723385 iDelay=230, Bit 13, Center -35 (-298 ~ 229) 528
6943 22:21:12.726199 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6944 22:21:12.732929 iDelay=230, Bit 15, Center -35 (-298 ~ 229) 528
6945 22:21:12.733009 ==
6946 22:21:12.736451 Dram Type= 6, Freq= 0, CH_1, rank 1
6947 22:21:12.739659 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6948 22:21:12.739750 ==
6949 22:21:12.739816 DQS Delay:
6950 22:21:12.742740 DQS0 = 59, DQS1 = 67
6951 22:21:12.742860 DQM Delay:
6952 22:21:12.745856 DQM0 = 19, DQM1 = 21
6953 22:21:12.745929 DQ Delay:
6954 22:21:12.749598 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6955 22:21:12.752521 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6956 22:21:12.756338 DQ8 =0, DQ9 =8, DQ10 =24, DQ11 =16
6957 22:21:12.759427 DQ12 =32, DQ13 =32, DQ14 =24, DQ15 =32
6958 22:21:12.759502
6959 22:21:12.759570
6960 22:21:12.759637 ==
6961 22:21:12.762618 Dram Type= 6, Freq= 0, CH_1, rank 1
6962 22:21:12.766358 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6963 22:21:12.769374 ==
6964 22:21:12.769469
6965 22:21:12.769534
6966 22:21:12.769603 TX Vref Scan disable
6967 22:21:12.772423 == TX Byte 0 ==
6968 22:21:12.775970 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6969 22:21:12.779367 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6970 22:21:12.782155 == TX Byte 1 ==
6971 22:21:12.785698 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6972 22:21:12.789399 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6973 22:21:12.789508 ==
6974 22:21:12.792535 Dram Type= 6, Freq= 0, CH_1, rank 1
6975 22:21:12.799285 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6976 22:21:12.799370 ==
6977 22:21:12.799437
6978 22:21:12.799517
6979 22:21:12.799591 TX Vref Scan disable
6980 22:21:12.802313 == TX Byte 0 ==
6981 22:21:12.805368 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6982 22:21:12.808913 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6983 22:21:12.811954 == TX Byte 1 ==
6984 22:21:12.815437 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6985 22:21:12.818953 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6986 22:21:12.819030
6987 22:21:12.822042 [DATLAT]
6988 22:21:12.822115 Freq=400, CH1 RK1
6989 22:21:12.822178
6990 22:21:12.825682 DATLAT Default: 0xe
6991 22:21:12.825770 0, 0xFFFF, sum = 0
6992 22:21:12.828575 1, 0xFFFF, sum = 0
6993 22:21:12.828649 2, 0xFFFF, sum = 0
6994 22:21:12.831911 3, 0xFFFF, sum = 0
6995 22:21:12.831989 4, 0xFFFF, sum = 0
6996 22:21:12.834979 5, 0xFFFF, sum = 0
6997 22:21:12.835094 6, 0xFFFF, sum = 0
6998 22:21:12.838724 7, 0xFFFF, sum = 0
6999 22:21:12.838806 8, 0xFFFF, sum = 0
7000 22:21:12.841622 9, 0xFFFF, sum = 0
7001 22:21:12.841708 10, 0xFFFF, sum = 0
7002 22:21:12.845303 11, 0xFFFF, sum = 0
7003 22:21:12.848328 12, 0xFFFF, sum = 0
7004 22:21:12.848404 13, 0x0, sum = 1
7005 22:21:12.851462 14, 0x0, sum = 2
7006 22:21:12.851534 15, 0x0, sum = 3
7007 22:21:12.851597 16, 0x0, sum = 4
7008 22:21:12.855175 best_step = 14
7009 22:21:12.855252
7010 22:21:12.855315 ==
7011 22:21:12.858315 Dram Type= 6, Freq= 0, CH_1, rank 1
7012 22:21:12.861501 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7013 22:21:12.861619 ==
7014 22:21:12.865335 RX Vref Scan: 0
7015 22:21:12.865418
7016 22:21:12.865483 RX Vref 0 -> 0, step: 1
7017 22:21:12.868328
7018 22:21:12.868405 RX Delay -375 -> 252, step: 8
7019 22:21:12.876786 iDelay=217, Bit 0, Center -44 (-295 ~ 208) 504
7020 22:21:12.879924 iDelay=217, Bit 1, Center -52 (-303 ~ 200) 504
7021 22:21:12.883599 iDelay=217, Bit 2, Center -60 (-311 ~ 192) 504
7022 22:21:12.889809 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
7023 22:21:12.893155 iDelay=217, Bit 4, Center -48 (-303 ~ 208) 512
7024 22:21:12.896507 iDelay=217, Bit 5, Center -36 (-287 ~ 216) 504
7025 22:21:12.900146 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
7026 22:21:12.906244 iDelay=217, Bit 7, Center -52 (-303 ~ 200) 504
7027 22:21:12.909897 iDelay=217, Bit 8, Center -64 (-319 ~ 192) 512
7028 22:21:12.912909 iDelay=217, Bit 9, Center -64 (-319 ~ 192) 512
7029 22:21:12.916534 iDelay=217, Bit 10, Center -48 (-303 ~ 208) 512
7030 22:21:12.922731 iDelay=217, Bit 11, Center -60 (-311 ~ 192) 504
7031 22:21:12.926420 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
7032 22:21:12.929619 iDelay=217, Bit 13, Center -48 (-303 ~ 208) 512
7033 22:21:12.932569 iDelay=217, Bit 14, Center -48 (-303 ~ 208) 512
7034 22:21:12.939422 iDelay=217, Bit 15, Center -48 (-303 ~ 208) 512
7035 22:21:12.939528 ==
7036 22:21:12.942645 Dram Type= 6, Freq= 0, CH_1, rank 1
7037 22:21:12.946204 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7038 22:21:12.946286 ==
7039 22:21:12.946385 DQS Delay:
7040 22:21:12.949385 DQS0 = 60, DQS1 = 64
7041 22:21:12.949469 DQM Delay:
7042 22:21:12.952563 DQM0 = 12, DQM1 = 10
7043 22:21:12.952638 DQ Delay:
7044 22:21:12.955888 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
7045 22:21:12.959290 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =8
7046 22:21:12.962399 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
7047 22:21:12.965601 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
7048 22:21:12.965710
7049 22:21:12.965808
7050 22:21:12.975473 [DQSOSCAuto] RK1, (LSB)MR18= 0x73a3, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 395 ps
7051 22:21:12.975555 CH1 RK1: MR19=C0C, MR18=73A3
7052 22:21:12.982513 CH1_RK1: MR19=0xC0C, MR18=0x73A3, DQSOSC=389, MR23=63, INC=390, DEC=260
7053 22:21:12.985662 [RxdqsGatingPostProcess] freq 400
7054 22:21:12.992308 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7055 22:21:12.995114 best DQS0 dly(2T, 0.5T) = (0, 10)
7056 22:21:12.998551 best DQS1 dly(2T, 0.5T) = (0, 10)
7057 22:21:13.002072 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7058 22:21:13.005068 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7059 22:21:13.008599 best DQS0 dly(2T, 0.5T) = (0, 10)
7060 22:21:13.008692 best DQS1 dly(2T, 0.5T) = (0, 10)
7061 22:21:13.011817 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7062 22:21:13.015336 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7063 22:21:13.018330 Pre-setting of DQS Precalculation
7064 22:21:13.024900 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7065 22:21:13.031794 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7066 22:21:13.038022 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7067 22:21:13.038127
7068 22:21:13.038227
7069 22:21:13.041816 [Calibration Summary] 800 Mbps
7070 22:21:13.044534 CH 0, Rank 0
7071 22:21:13.044607 SW Impedance : PASS
7072 22:21:13.048748 DUTY Scan : NO K
7073 22:21:13.051605 ZQ Calibration : PASS
7074 22:21:13.051679 Jitter Meter : NO K
7075 22:21:13.054501 CBT Training : PASS
7076 22:21:13.058354 Write leveling : PASS
7077 22:21:13.058450 RX DQS gating : PASS
7078 22:21:13.061273 RX DQ/DQS(RDDQC) : PASS
7079 22:21:13.061378 TX DQ/DQS : PASS
7080 22:21:13.064393 RX DATLAT : PASS
7081 22:21:13.067768 RX DQ/DQS(Engine): PASS
7082 22:21:13.067864 TX OE : NO K
7083 22:21:13.071342 All Pass.
7084 22:21:13.071439
7085 22:21:13.071531 CH 0, Rank 1
7086 22:21:13.074419 SW Impedance : PASS
7087 22:21:13.074515 DUTY Scan : NO K
7088 22:21:13.077547 ZQ Calibration : PASS
7089 22:21:13.081093 Jitter Meter : NO K
7090 22:21:13.081166 CBT Training : PASS
7091 22:21:13.084420 Write leveling : NO K
7092 22:21:13.087592 RX DQS gating : PASS
7093 22:21:13.087665 RX DQ/DQS(RDDQC) : PASS
7094 22:21:13.091175 TX DQ/DQS : PASS
7095 22:21:13.094388 RX DATLAT : PASS
7096 22:21:13.094488 RX DQ/DQS(Engine): PASS
7097 22:21:13.097788 TX OE : NO K
7098 22:21:13.097889 All Pass.
7099 22:21:13.097980
7100 22:21:13.100786 CH 1, Rank 0
7101 22:21:13.100857 SW Impedance : PASS
7102 22:21:13.104309 DUTY Scan : NO K
7103 22:21:13.107695 ZQ Calibration : PASS
7104 22:21:13.107774 Jitter Meter : NO K
7105 22:21:13.110572 CBT Training : PASS
7106 22:21:13.114020 Write leveling : PASS
7107 22:21:13.114096 RX DQS gating : PASS
7108 22:21:13.117058 RX DQ/DQS(RDDQC) : PASS
7109 22:21:13.120832 TX DQ/DQS : PASS
7110 22:21:13.120918 RX DATLAT : PASS
7111 22:21:13.123885 RX DQ/DQS(Engine): PASS
7112 22:21:13.127447 TX OE : NO K
7113 22:21:13.127532 All Pass.
7114 22:21:13.127599
7115 22:21:13.127661 CH 1, Rank 1
7116 22:21:13.130329 SW Impedance : PASS
7117 22:21:13.133842 DUTY Scan : NO K
7118 22:21:13.133927 ZQ Calibration : PASS
7119 22:21:13.137239 Jitter Meter : NO K
7120 22:21:13.140288 CBT Training : PASS
7121 22:21:13.140373 Write leveling : NO K
7122 22:21:13.143358 RX DQS gating : PASS
7123 22:21:13.146930 RX DQ/DQS(RDDQC) : PASS
7124 22:21:13.147014 TX DQ/DQS : PASS
7125 22:21:13.150053 RX DATLAT : PASS
7126 22:21:13.150138 RX DQ/DQS(Engine): PASS
7127 22:21:13.153758 TX OE : NO K
7128 22:21:13.153847 All Pass.
7129 22:21:13.153914
7130 22:21:13.156616 DramC Write-DBI off
7131 22:21:13.160419 PER_BANK_REFRESH: Hybrid Mode
7132 22:21:13.160504 TX_TRACKING: ON
7133 22:21:13.169865 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7134 22:21:13.172956 [FAST_K] Save calibration result to emmc
7135 22:21:13.176582 dramc_set_vcore_voltage set vcore to 725000
7136 22:21:13.179724 Read voltage for 1600, 0
7137 22:21:13.179807 Vio18 = 0
7138 22:21:13.182796 Vcore = 725000
7139 22:21:13.182907 Vdram = 0
7140 22:21:13.182973 Vddq = 0
7141 22:21:13.183035 Vmddr = 0
7142 22:21:13.189396 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7143 22:21:13.196147 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7144 22:21:13.196231 MEM_TYPE=3, freq_sel=13
7145 22:21:13.199252 sv_algorithm_assistance_LP4_3733
7146 22:21:13.205701 ============ PULL DRAM RESETB DOWN ============
7147 22:21:13.209189 ========== PULL DRAM RESETB DOWN end =========
7148 22:21:13.212766 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7149 22:21:13.216045 ===================================
7150 22:21:13.218887 LPDDR4 DRAM CONFIGURATION
7151 22:21:13.222375 ===================================
7152 22:21:13.222488 EX_ROW_EN[0] = 0x0
7153 22:21:13.225558 EX_ROW_EN[1] = 0x0
7154 22:21:13.229144 LP4Y_EN = 0x0
7155 22:21:13.229227 WORK_FSP = 0x1
7156 22:21:13.232223 WL = 0x5
7157 22:21:13.232307 RL = 0x5
7158 22:21:13.235743 BL = 0x2
7159 22:21:13.235840 RPST = 0x0
7160 22:21:13.238643 RD_PRE = 0x0
7161 22:21:13.238725 WR_PRE = 0x1
7162 22:21:13.242161 WR_PST = 0x1
7163 22:21:13.242287 DBI_WR = 0x0
7164 22:21:13.245709 DBI_RD = 0x0
7165 22:21:13.245820 OTF = 0x1
7166 22:21:13.248802 ===================================
7167 22:21:13.251840 ===================================
7168 22:21:13.255610 ANA top config
7169 22:21:13.258631 ===================================
7170 22:21:13.262077 DLL_ASYNC_EN = 0
7171 22:21:13.262160 ALL_SLAVE_EN = 0
7172 22:21:13.265038 NEW_RANK_MODE = 1
7173 22:21:13.268579 DLL_IDLE_MODE = 1
7174 22:21:13.271546 LP45_APHY_COMB_EN = 1
7175 22:21:13.275233 TX_ODT_DIS = 0
7176 22:21:13.275329 NEW_8X_MODE = 1
7177 22:21:13.278389 ===================================
7178 22:21:13.281419 ===================================
7179 22:21:13.285194 data_rate = 3200
7180 22:21:13.288249 CKR = 1
7181 22:21:13.291224 DQ_P2S_RATIO = 8
7182 22:21:13.294803 ===================================
7183 22:21:13.297873 CA_P2S_RATIO = 8
7184 22:21:13.301601 DQ_CA_OPEN = 0
7185 22:21:13.301711 DQ_SEMI_OPEN = 0
7186 22:21:13.304731 CA_SEMI_OPEN = 0
7187 22:21:13.307710 CA_FULL_RATE = 0
7188 22:21:13.311087 DQ_CKDIV4_EN = 0
7189 22:21:13.314469 CA_CKDIV4_EN = 0
7190 22:21:13.317902 CA_PREDIV_EN = 0
7191 22:21:13.318018 PH8_DLY = 12
7192 22:21:13.320809 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7193 22:21:13.324195 DQ_AAMCK_DIV = 4
7194 22:21:13.327936 CA_AAMCK_DIV = 4
7195 22:21:13.330723 CA_ADMCK_DIV = 4
7196 22:21:13.334358 DQ_TRACK_CA_EN = 0
7197 22:21:13.337396 CA_PICK = 1600
7198 22:21:13.337473 CA_MCKIO = 1600
7199 22:21:13.341067 MCKIO_SEMI = 0
7200 22:21:13.344118 PLL_FREQ = 3068
7201 22:21:13.347552 DQ_UI_PI_RATIO = 32
7202 22:21:13.350546 CA_UI_PI_RATIO = 0
7203 22:21:13.354191 ===================================
7204 22:21:13.357053 ===================================
7205 22:21:13.360808 memory_type:LPDDR4
7206 22:21:13.360888 GP_NUM : 10
7207 22:21:13.363740 SRAM_EN : 1
7208 22:21:13.367154 MD32_EN : 0
7209 22:21:13.370348 ===================================
7210 22:21:13.370434 [ANA_INIT] >>>>>>>>>>>>>>
7211 22:21:13.373322 <<<<<< [CONFIGURE PHASE]: ANA_TX
7212 22:21:13.376772 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7213 22:21:13.379852 ===================================
7214 22:21:13.383574 data_rate = 3200,PCW = 0X7600
7215 22:21:13.386645 ===================================
7216 22:21:13.390284 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7217 22:21:13.396448 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7218 22:21:13.399976 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7219 22:21:13.406222 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7220 22:21:13.409912 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7221 22:21:13.412980 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7222 22:21:13.416476 [ANA_INIT] flow start
7223 22:21:13.416558 [ANA_INIT] PLL >>>>>>>>
7224 22:21:13.419627 [ANA_INIT] PLL <<<<<<<<
7225 22:21:13.423265 [ANA_INIT] MIDPI >>>>>>>>
7226 22:21:13.423346 [ANA_INIT] MIDPI <<<<<<<<
7227 22:21:13.426496 [ANA_INIT] DLL >>>>>>>>
7228 22:21:13.429464 [ANA_INIT] DLL <<<<<<<<
7229 22:21:13.429546 [ANA_INIT] flow end
7230 22:21:13.436266 ============ LP4 DIFF to SE enter ============
7231 22:21:13.439378 ============ LP4 DIFF to SE exit ============
7232 22:21:13.439462 [ANA_INIT] <<<<<<<<<<<<<
7233 22:21:13.443079 [Flow] Enable top DCM control >>>>>
7234 22:21:13.446201 [Flow] Enable top DCM control <<<<<
7235 22:21:13.449363 Enable DLL master slave shuffle
7236 22:21:13.455901 ==============================================================
7237 22:21:13.459241 Gating Mode config
7238 22:21:13.462839 ==============================================================
7239 22:21:13.465979 Config description:
7240 22:21:13.475526 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7241 22:21:13.482063 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7242 22:21:13.485784 SELPH_MODE 0: By rank 1: By Phase
7243 22:21:13.492603 ==============================================================
7244 22:21:13.495695 GAT_TRACK_EN = 1
7245 22:21:13.498789 RX_GATING_MODE = 2
7246 22:21:13.502332 RX_GATING_TRACK_MODE = 2
7247 22:21:13.505514 SELPH_MODE = 1
7248 22:21:13.505597 PICG_EARLY_EN = 1
7249 22:21:13.508844 VALID_LAT_VALUE = 1
7250 22:21:13.515448 ==============================================================
7251 22:21:13.518754 Enter into Gating configuration >>>>
7252 22:21:13.522118 Exit from Gating configuration <<<<
7253 22:21:13.524970 Enter into DVFS_PRE_config >>>>>
7254 22:21:13.535079 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7255 22:21:13.538396 Exit from DVFS_PRE_config <<<<<
7256 22:21:13.541715 Enter into PICG configuration >>>>
7257 22:21:13.545238 Exit from PICG configuration <<<<
7258 22:21:13.548402 [RX_INPUT] configuration >>>>>
7259 22:21:13.551497 [RX_INPUT] configuration <<<<<
7260 22:21:13.555267 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7261 22:21:13.561795 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7262 22:21:13.568101 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7263 22:21:13.574946 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7264 22:21:13.581091 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7265 22:21:13.588239 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7266 22:21:13.591250 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7267 22:21:13.594356 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7268 22:21:13.598145 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7269 22:21:13.604196 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7270 22:21:13.607852 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7271 22:21:13.610970 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7272 22:21:13.614012 ===================================
7273 22:21:13.617740 LPDDR4 DRAM CONFIGURATION
7274 22:21:13.620770 ===================================
7275 22:21:13.620900 EX_ROW_EN[0] = 0x0
7276 22:21:13.624159 EX_ROW_EN[1] = 0x0
7277 22:21:13.627374 LP4Y_EN = 0x0
7278 22:21:13.627446 WORK_FSP = 0x1
7279 22:21:13.630959 WL = 0x5
7280 22:21:13.631033 RL = 0x5
7281 22:21:13.633900 BL = 0x2
7282 22:21:13.634027 RPST = 0x0
7283 22:21:13.637347 RD_PRE = 0x0
7284 22:21:13.637423 WR_PRE = 0x1
7285 22:21:13.640996 WR_PST = 0x1
7286 22:21:13.641119 DBI_WR = 0x0
7287 22:21:13.644449 DBI_RD = 0x0
7288 22:21:13.644553 OTF = 0x1
7289 22:21:13.647170 ===================================
7290 22:21:13.650451 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7291 22:21:13.657352 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7292 22:21:13.660486 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7293 22:21:13.664117 ===================================
7294 22:21:13.667286 LPDDR4 DRAM CONFIGURATION
7295 22:21:13.670274 ===================================
7296 22:21:13.670359 EX_ROW_EN[0] = 0x10
7297 22:21:13.673782 EX_ROW_EN[1] = 0x0
7298 22:21:13.677395 LP4Y_EN = 0x0
7299 22:21:13.677481 WORK_FSP = 0x1
7300 22:21:13.680548 WL = 0x5
7301 22:21:13.680632 RL = 0x5
7302 22:21:13.683439 BL = 0x2
7303 22:21:13.683524 RPST = 0x0
7304 22:21:13.687053 RD_PRE = 0x0
7305 22:21:13.687169 WR_PRE = 0x1
7306 22:21:13.690106 WR_PST = 0x1
7307 22:21:13.690220 DBI_WR = 0x0
7308 22:21:13.693779 DBI_RD = 0x0
7309 22:21:13.693896 OTF = 0x1
7310 22:21:13.696570 ===================================
7311 22:21:13.703420 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7312 22:21:13.703531 ==
7313 22:21:13.706546 Dram Type= 6, Freq= 0, CH_0, rank 0
7314 22:21:13.713108 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7315 22:21:13.713225 ==
7316 22:21:13.713331 [Duty_Offset_Calibration]
7317 22:21:13.716853 B0:2 B1:0 CA:3
7318 22:21:13.716958
7319 22:21:13.719979 [DutyScan_Calibration_Flow] k_type=0
7320 22:21:13.728710
7321 22:21:13.728798 ==CLK 0==
7322 22:21:13.732412 Final CLK duty delay cell = 0
7323 22:21:13.735312 [0] MAX Duty = 5031%(X100), DQS PI = 12
7324 22:21:13.738724 [0] MIN Duty = 4907%(X100), DQS PI = 2
7325 22:21:13.738845 [0] AVG Duty = 4969%(X100)
7326 22:21:13.742109
7327 22:21:13.745702 CH0 CLK Duty spec in!! Max-Min= 124%
7328 22:21:13.748556 [DutyScan_Calibration_Flow] ====Done====
7329 22:21:13.748644
7330 22:21:13.752039 [DutyScan_Calibration_Flow] k_type=1
7331 22:21:13.768720
7332 22:21:13.768819 ==DQS 0 ==
7333 22:21:13.771772 Final DQS duty delay cell = 0
7334 22:21:13.775512 [0] MAX Duty = 5125%(X100), DQS PI = 30
7335 22:21:13.778603 [0] MIN Duty = 4875%(X100), DQS PI = 48
7336 22:21:13.781940 [0] AVG Duty = 5000%(X100)
7337 22:21:13.782038
7338 22:21:13.782105 ==DQS 1 ==
7339 22:21:13.784938 Final DQS duty delay cell = 0
7340 22:21:13.788441 [0] MAX Duty = 5156%(X100), DQS PI = 32
7341 22:21:13.791870 [0] MIN Duty = 5031%(X100), DQS PI = 14
7342 22:21:13.794774 [0] AVG Duty = 5093%(X100)
7343 22:21:13.794910
7344 22:21:13.798325 CH0 DQS 0 Duty spec in!! Max-Min= 250%
7345 22:21:13.798407
7346 22:21:13.801947 CH0 DQS 1 Duty spec in!! Max-Min= 125%
7347 22:21:13.804908 [DutyScan_Calibration_Flow] ====Done====
7348 22:21:13.804996
7349 22:21:13.807934 [DutyScan_Calibration_Flow] k_type=3
7350 22:21:13.826405
7351 22:21:13.826543 ==DQM 0 ==
7352 22:21:13.830046 Final DQM duty delay cell = 0
7353 22:21:13.833171 [0] MAX Duty = 5156%(X100), DQS PI = 30
7354 22:21:13.836222 [0] MIN Duty = 4844%(X100), DQS PI = 52
7355 22:21:13.839747 [0] AVG Duty = 5000%(X100)
7356 22:21:13.839824
7357 22:21:13.839889 ==DQM 1 ==
7358 22:21:13.842497 Final DQM duty delay cell = 4
7359 22:21:13.846005 [4] MAX Duty = 5187%(X100), DQS PI = 60
7360 22:21:13.849389 [4] MIN Duty = 5000%(X100), DQS PI = 40
7361 22:21:13.852648 [4] AVG Duty = 5093%(X100)
7362 22:21:13.852746
7363 22:21:13.856111 CH0 DQM 0 Duty spec in!! Max-Min= 312%
7364 22:21:13.856192
7365 22:21:13.859882 CH0 DQM 1 Duty spec in!! Max-Min= 187%
7366 22:21:13.862367 [DutyScan_Calibration_Flow] ====Done====
7367 22:21:13.862439
7368 22:21:13.865999 [DutyScan_Calibration_Flow] k_type=2
7369 22:21:13.883250
7370 22:21:13.883365 ==DQ 0 ==
7371 22:21:13.886057 Final DQ duty delay cell = -4
7372 22:21:13.889091 [-4] MAX Duty = 5000%(X100), DQS PI = 14
7373 22:21:13.892814 [-4] MIN Duty = 4876%(X100), DQS PI = 0
7374 22:21:13.895823 [-4] AVG Duty = 4938%(X100)
7375 22:21:13.895937
7376 22:21:13.895999 ==DQ 1 ==
7377 22:21:13.899290 Final DQ duty delay cell = 0
7378 22:21:13.902676 [0] MAX Duty = 5156%(X100), DQS PI = 60
7379 22:21:13.905781 [0] MIN Duty = 5000%(X100), DQS PI = 16
7380 22:21:13.909307 [0] AVG Duty = 5078%(X100)
7381 22:21:13.909391
7382 22:21:13.912528 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7383 22:21:13.912611
7384 22:21:13.916140 CH0 DQ 1 Duty spec in!! Max-Min= 156%
7385 22:21:13.919074 [DutyScan_Calibration_Flow] ====Done====
7386 22:21:13.919156 ==
7387 22:21:13.922223 Dram Type= 6, Freq= 0, CH_1, rank 0
7388 22:21:13.925344 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7389 22:21:13.925430 ==
7390 22:21:13.929089 [Duty_Offset_Calibration]
7391 22:21:13.929170 B0:1 B1:-2 CA:0
7392 22:21:13.929234
7393 22:21:13.932230 [DutyScan_Calibration_Flow] k_type=0
7394 22:21:13.943490
7395 22:21:13.943572 ==CLK 0==
7396 22:21:13.946248 Final CLK duty delay cell = 0
7397 22:21:13.949893 [0] MAX Duty = 5093%(X100), DQS PI = 22
7398 22:21:13.953193 [0] MIN Duty = 4844%(X100), DQS PI = 2
7399 22:21:13.953275 [0] AVG Duty = 4968%(X100)
7400 22:21:13.956531
7401 22:21:13.959983 CH1 CLK Duty spec in!! Max-Min= 249%
7402 22:21:13.962915 [DutyScan_Calibration_Flow] ====Done====
7403 22:21:13.962998
7404 22:21:13.965967 [DutyScan_Calibration_Flow] k_type=1
7405 22:21:13.982089
7406 22:21:13.982179 ==DQS 0 ==
7407 22:21:13.985047 Final DQS duty delay cell = -4
7408 22:21:13.988653 [-4] MAX Duty = 5000%(X100), DQS PI = 26
7409 22:21:13.991708 [-4] MIN Duty = 4844%(X100), DQS PI = 0
7410 22:21:13.995411 [-4] AVG Duty = 4922%(X100)
7411 22:21:13.995507
7412 22:21:13.995571 ==DQS 1 ==
7413 22:21:13.998572 Final DQS duty delay cell = 0
7414 22:21:14.002132 [0] MAX Duty = 5093%(X100), DQS PI = 0
7415 22:21:14.005160 [0] MIN Duty = 4844%(X100), DQS PI = 24
7416 22:21:14.008522 [0] AVG Duty = 4968%(X100)
7417 22:21:14.008653
7418 22:21:14.011654 CH1 DQS 0 Duty spec in!! Max-Min= 156%
7419 22:21:14.011731
7420 22:21:14.015393 CH1 DQS 1 Duty spec in!! Max-Min= 249%
7421 22:21:14.018277 [DutyScan_Calibration_Flow] ====Done====
7422 22:21:14.018388
7423 22:21:14.021869 [DutyScan_Calibration_Flow] k_type=3
7424 22:21:14.039018
7425 22:21:14.039114 ==DQM 0 ==
7426 22:21:14.042244 Final DQM duty delay cell = 0
7427 22:21:14.045368 [0] MAX Duty = 5031%(X100), DQS PI = 26
7428 22:21:14.049023 [0] MIN Duty = 4813%(X100), DQS PI = 56
7429 22:21:14.051972 [0] AVG Duty = 4922%(X100)
7430 22:21:14.052047
7431 22:21:14.052111 ==DQM 1 ==
7432 22:21:14.055664 Final DQM duty delay cell = 0
7433 22:21:14.059002 [0] MAX Duty = 5062%(X100), DQS PI = 34
7434 22:21:14.061809 [0] MIN Duty = 4875%(X100), DQS PI = 26
7435 22:21:14.065390 [0] AVG Duty = 4968%(X100)
7436 22:21:14.065501
7437 22:21:14.068887 CH1 DQM 0 Duty spec in!! Max-Min= 218%
7438 22:21:14.069001
7439 22:21:14.071851 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7440 22:21:14.075250 [DutyScan_Calibration_Flow] ====Done====
7441 22:21:14.075350
7442 22:21:14.078344 [DutyScan_Calibration_Flow] k_type=2
7443 22:21:14.095634
7444 22:21:14.095718 ==DQ 0 ==
7445 22:21:14.099335 Final DQ duty delay cell = 0
7446 22:21:14.102342 [0] MAX Duty = 5093%(X100), DQS PI = 20
7447 22:21:14.105864 [0] MIN Duty = 4907%(X100), DQS PI = 60
7448 22:21:14.105977 [0] AVG Duty = 5000%(X100)
7449 22:21:14.108862
7450 22:21:14.108945 ==DQ 1 ==
7451 22:21:14.112685 Final DQ duty delay cell = 0
7452 22:21:14.115944 [0] MAX Duty = 5156%(X100), DQS PI = 36
7453 22:21:14.118916 [0] MIN Duty = 4969%(X100), DQS PI = 24
7454 22:21:14.118998 [0] AVG Duty = 5062%(X100)
7455 22:21:14.122337
7456 22:21:14.125303 CH1 DQ 0 Duty spec in!! Max-Min= 186%
7457 22:21:14.125402
7458 22:21:14.128831 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7459 22:21:14.131875 [DutyScan_Calibration_Flow] ====Done====
7460 22:21:14.135664 nWR fixed to 30
7461 22:21:14.138849 [ModeRegInit_LP4] CH0 RK0
7462 22:21:14.138935 [ModeRegInit_LP4] CH0 RK1
7463 22:21:14.141896 [ModeRegInit_LP4] CH1 RK0
7464 22:21:14.145084 [ModeRegInit_LP4] CH1 RK1
7465 22:21:14.145182 match AC timing 5
7466 22:21:14.151902 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7467 22:21:14.154964 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7468 22:21:14.158667 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7469 22:21:14.165201 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7470 22:21:14.168085 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7471 22:21:14.168205 [MiockJmeterHQA]
7472 22:21:14.168303
7473 22:21:14.171628 [DramcMiockJmeter] u1RxGatingPI = 0
7474 22:21:14.174986 0 : 4255, 4029
7475 22:21:14.175095 4 : 4260, 4030
7476 22:21:14.177971 8 : 4258, 4029
7477 22:21:14.178047 12 : 4366, 4138
7478 22:21:14.181445 16 : 4366, 4140
7479 22:21:14.181548 20 : 4254, 4029
7480 22:21:14.181643 24 : 4255, 4029
7481 22:21:14.184826 28 : 4257, 4029
7482 22:21:14.184933 32 : 4253, 4027
7483 22:21:14.188327 36 : 4257, 4032
7484 22:21:14.188435 40 : 4255, 4029
7485 22:21:14.191525 44 : 4365, 4140
7486 22:21:14.191628 48 : 4252, 4027
7487 22:21:14.194492 52 : 4257, 4030
7488 22:21:14.194593 56 : 4257, 4032
7489 22:21:14.194696 60 : 4257, 4029
7490 22:21:14.197826 64 : 4255, 4029
7491 22:21:14.197908 68 : 4257, 4032
7492 22:21:14.200915 72 : 4252, 4029
7493 22:21:14.200988 76 : 4257, 4029
7494 22:21:14.204655 80 : 4255, 4029
7495 22:21:14.204730 84 : 4254, 4029
7496 22:21:14.207752 88 : 4258, 4032
7497 22:21:14.207854 92 : 4253, 4029
7498 22:21:14.207956 96 : 4254, 4030
7499 22:21:14.211123 100 : 4368, 4142
7500 22:21:14.211202 104 : 4363, 3750
7501 22:21:14.214215 108 : 4254, 2
7502 22:21:14.214325 112 : 4253, 0
7503 22:21:14.217825 116 : 4258, 0
7504 22:21:14.217930 120 : 4252, 0
7505 22:21:14.218025 124 : 4255, 0
7506 22:21:14.220866 128 : 4366, 0
7507 22:21:14.220969 132 : 4250, 0
7508 22:21:14.224395 136 : 4255, 0
7509 22:21:14.224513 140 : 4252, 0
7510 22:21:14.224611 144 : 4258, 0
7511 22:21:14.227354 148 : 4252, 0
7512 22:21:14.227464 152 : 4253, 0
7513 22:21:14.230837 156 : 4257, 0
7514 22:21:14.230917 160 : 4252, 0
7515 22:21:14.230985 164 : 4253, 0
7516 22:21:14.234296 168 : 4257, 0
7517 22:21:14.234405 172 : 4255, 0
7518 22:21:14.237452 176 : 4252, 0
7519 22:21:14.237555 180 : 4252, 0
7520 22:21:14.237654 184 : 4365, 0
7521 22:21:14.240537 188 : 4250, 0
7522 22:21:14.240639 192 : 4252, 0
7523 22:21:14.240733 196 : 4258, 0
7524 22:21:14.244329 200 : 4252, 0
7525 22:21:14.244404 204 : 4363, 0
7526 22:21:14.247749 208 : 4252, 0
7527 22:21:14.247848 212 : 4252, 0
7528 22:21:14.247940 216 : 4363, 0
7529 22:21:14.250541 220 : 4363, 0
7530 22:21:14.250639 224 : 4252, 0
7531 22:21:14.254301 228 : 4252, 0
7532 22:21:14.254400 232 : 4252, 0
7533 22:21:14.254499 236 : 4257, 1203
7534 22:21:14.257326 240 : 4255, 4029
7535 22:21:14.257431 244 : 4364, 4140
7536 22:21:14.260280 248 : 4363, 4140
7537 22:21:14.260381 252 : 4252, 4029
7538 22:21:14.263984 256 : 4252, 4030
7539 22:21:14.264087 260 : 4252, 4029
7540 22:21:14.267062 264 : 4365, 4140
7541 22:21:14.267179 268 : 4252, 4030
7542 22:21:14.270402 272 : 4250, 4027
7543 22:21:14.270502 276 : 4253, 4029
7544 22:21:14.273846 280 : 4360, 4137
7545 22:21:14.273919 284 : 4363, 4139
7546 22:21:14.276792 288 : 4363, 4140
7547 22:21:14.276892 292 : 4252, 4027
7548 22:21:14.280123 296 : 4255, 4029
7549 22:21:14.280230 300 : 4363, 4139
7550 22:21:14.280329 304 : 4252, 4030
7551 22:21:14.283713 308 : 4253, 4029
7552 22:21:14.283816 312 : 4255, 4029
7553 22:21:14.287219 316 : 4365, 4140
7554 22:21:14.287328 320 : 4252, 4030
7555 22:21:14.289999 324 : 4255, 4029
7556 22:21:14.290073 328 : 4252, 4029
7557 22:21:14.293408 332 : 4253, 4029
7558 22:21:14.293523 336 : 4252, 4029
7559 22:21:14.296563 340 : 4253, 4029
7560 22:21:14.296662 344 : 4258, 4032
7561 22:21:14.300331 348 : 4253, 4029
7562 22:21:14.300407 352 : 4252, 4023
7563 22:21:14.303732 356 : 4252, 2679
7564 22:21:14.303814 360 : 4255, 2
7565 22:21:14.303883
7566 22:21:14.306772 MIOCK jitter meter ch=0
7567 22:21:14.306877
7568 22:21:14.309927 1T = (360-108) = 252 dly cells
7569 22:21:14.313341 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 258/100 ps
7570 22:21:14.313423 ==
7571 22:21:14.316940 Dram Type= 6, Freq= 0, CH_0, rank 0
7572 22:21:14.323671 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7573 22:21:14.323755 ==
7574 22:21:14.327001 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7575 22:21:14.333309 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7576 22:21:14.336506 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7577 22:21:14.343182 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7578 22:21:14.350656 [CA 0] Center 44 (14~75) winsize 62
7579 22:21:14.354525 [CA 1] Center 43 (13~74) winsize 62
7580 22:21:14.357392 [CA 2] Center 40 (11~69) winsize 59
7581 22:21:14.361138 [CA 3] Center 39 (10~68) winsize 59
7582 22:21:14.364101 [CA 4] Center 37 (8~67) winsize 60
7583 22:21:14.367271 [CA 5] Center 37 (7~67) winsize 61
7584 22:21:14.367358
7585 22:21:14.370921 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7586 22:21:14.371036
7587 22:21:14.377481 [CATrainingPosCal] consider 1 rank data
7588 22:21:14.377568 u2DelayCellTimex100 = 258/100 ps
7589 22:21:14.383827 CA0 delay=44 (14~75),Diff = 7 PI (26 cell)
7590 22:21:14.386825 CA1 delay=43 (13~74),Diff = 6 PI (22 cell)
7591 22:21:14.390232 CA2 delay=40 (11~69),Diff = 3 PI (11 cell)
7592 22:21:14.393979 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7593 22:21:14.397153 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
7594 22:21:14.400133 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7595 22:21:14.400219
7596 22:21:14.403760 CA PerBit enable=1, Macro0, CA PI delay=37
7597 22:21:14.403844
7598 22:21:14.406687 [CBTSetCACLKResult] CA Dly = 37
7599 22:21:14.409812 CS Dly: 11 (0~42)
7600 22:21:14.413478 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7601 22:21:14.416450 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7602 22:21:14.416534 ==
7603 22:21:14.419903 Dram Type= 6, Freq= 0, CH_0, rank 1
7604 22:21:14.426853 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7605 22:21:14.426944 ==
7606 22:21:14.429968 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7607 22:21:14.436608 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7608 22:21:14.439551 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7609 22:21:14.446331 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7610 22:21:14.454846 [CA 0] Center 44 (13~75) winsize 63
7611 22:21:14.457867 [CA 1] Center 43 (13~74) winsize 62
7612 22:21:14.461543 [CA 2] Center 39 (10~69) winsize 60
7613 22:21:14.464708 [CA 3] Center 39 (10~68) winsize 59
7614 22:21:14.467822 [CA 4] Center 37 (8~67) winsize 60
7615 22:21:14.470925 [CA 5] Center 36 (7~66) winsize 60
7616 22:21:14.471002
7617 22:21:14.474547 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7618 22:21:14.474661
7619 22:21:14.481671 [CATrainingPosCal] consider 2 rank data
7620 22:21:14.481777 u2DelayCellTimex100 = 258/100 ps
7621 22:21:14.487322 CA0 delay=44 (14~75),Diff = 8 PI (30 cell)
7622 22:21:14.490853 CA1 delay=43 (13~74),Diff = 7 PI (26 cell)
7623 22:21:14.494268 CA2 delay=40 (11~69),Diff = 4 PI (15 cell)
7624 22:21:14.497726 CA3 delay=39 (10~68),Diff = 3 PI (11 cell)
7625 22:21:14.500688 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
7626 22:21:14.503995 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7627 22:21:14.504114
7628 22:21:14.507420 CA PerBit enable=1, Macro0, CA PI delay=36
7629 22:21:14.510362
7630 22:21:14.510459 [CBTSetCACLKResult] CA Dly = 36
7631 22:21:14.514137 CS Dly: 11 (0~43)
7632 22:21:14.517213 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7633 22:21:14.520780 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7634 22:21:14.520853
7635 22:21:14.527285 ----->DramcWriteLeveling(PI) begin...
7636 22:21:14.527364 ==
7637 22:21:14.530325 Dram Type= 6, Freq= 0, CH_0, rank 0
7638 22:21:14.534002 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7639 22:21:14.534094 ==
7640 22:21:14.537014 Write leveling (Byte 0): 34 => 34
7641 22:21:14.540556 Write leveling (Byte 1): 30 => 30
7642 22:21:14.543620 DramcWriteLeveling(PI) end<-----
7643 22:21:14.543707
7644 22:21:14.543800 ==
7645 22:21:14.546751 Dram Type= 6, Freq= 0, CH_0, rank 0
7646 22:21:14.550222 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7647 22:21:14.550355 ==
7648 22:21:14.553699 [Gating] SW mode calibration
7649 22:21:14.560607 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7650 22:21:14.566728 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7651 22:21:14.569845 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7652 22:21:14.573502 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7653 22:21:14.579847 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7654 22:21:14.583532 1 4 12 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
7655 22:21:14.586672 1 4 16 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (1 1)
7656 22:21:14.593055 1 4 20 | B1->B0 | 2423 3434 | 1 1 | (0 0) (1 1)
7657 22:21:14.596534 1 4 24 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
7658 22:21:14.599944 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7659 22:21:14.606222 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7660 22:21:14.609703 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7661 22:21:14.612734 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7662 22:21:14.619310 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7663 22:21:14.622788 1 5 16 | B1->B0 | 3434 2b2b | 1 0 | (1 1) (1 0)
7664 22:21:14.625856 1 5 20 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
7665 22:21:14.632369 1 5 24 | B1->B0 | 2929 2323 | 1 0 | (1 0) (0 0)
7666 22:21:14.635470 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7667 22:21:14.639156 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7668 22:21:14.645367 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7669 22:21:14.648944 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7670 22:21:14.651975 1 6 12 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7671 22:21:14.658658 1 6 16 | B1->B0 | 2323 3d3d | 0 0 | (0 0) (0 0)
7672 22:21:14.661621 1 6 20 | B1->B0 | 2727 4646 | 0 0 | (0 0) (0 0)
7673 22:21:14.665375 1 6 24 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
7674 22:21:14.671990 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7675 22:21:14.675127 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7676 22:21:14.678178 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7677 22:21:14.684997 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7678 22:21:14.688132 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7679 22:21:14.691772 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7680 22:21:14.698090 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7681 22:21:14.701569 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7682 22:21:14.704431 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7683 22:21:14.711298 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7684 22:21:14.714271 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7685 22:21:14.717710 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7686 22:21:14.724585 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7687 22:21:14.727759 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7688 22:21:14.730738 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7689 22:21:14.737400 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7690 22:21:14.741126 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7691 22:21:14.744149 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7692 22:21:14.751030 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7693 22:21:14.753846 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7694 22:21:14.760523 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7695 22:21:14.763657 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7696 22:21:14.767083 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7697 22:21:14.770181 Total UI for P1: 0, mck2ui 16
7698 22:21:14.773767 best dqsien dly found for B0: ( 1, 9, 14)
7699 22:21:14.776836 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7700 22:21:14.783614 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7701 22:21:14.786676 Total UI for P1: 0, mck2ui 16
7702 22:21:14.790378 best dqsien dly found for B1: ( 1, 9, 22)
7703 22:21:14.793414 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
7704 22:21:14.797062 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7705 22:21:14.797147
7706 22:21:14.800067 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
7707 22:21:14.803507 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7708 22:21:14.806421 [Gating] SW calibration Done
7709 22:21:14.806504 ==
7710 22:21:14.809845 Dram Type= 6, Freq= 0, CH_0, rank 0
7711 22:21:14.813323 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7712 22:21:14.816778 ==
7713 22:21:14.816876 RX Vref Scan: 0
7714 22:21:14.816944
7715 22:21:14.819667 RX Vref 0 -> 0, step: 1
7716 22:21:14.819751
7717 22:21:14.819855 RX Delay 0 -> 252, step: 8
7718 22:21:14.826668 iDelay=192, Bit 0, Center 127 (72 ~ 183) 112
7719 22:21:14.829923 iDelay=192, Bit 1, Center 131 (80 ~ 183) 104
7720 22:21:14.832912 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
7721 22:21:14.836453 iDelay=192, Bit 3, Center 123 (72 ~ 175) 104
7722 22:21:14.842681 iDelay=192, Bit 4, Center 127 (72 ~ 183) 112
7723 22:21:14.846406 iDelay=192, Bit 5, Center 111 (56 ~ 167) 112
7724 22:21:14.849543 iDelay=192, Bit 6, Center 139 (88 ~ 191) 104
7725 22:21:14.852554 iDelay=192, Bit 7, Center 135 (80 ~ 191) 112
7726 22:21:14.856149 iDelay=192, Bit 8, Center 115 (56 ~ 175) 120
7727 22:21:14.862718 iDelay=192, Bit 9, Center 111 (56 ~ 167) 112
7728 22:21:14.865742 iDelay=192, Bit 10, Center 123 (64 ~ 183) 120
7729 22:21:14.869376 iDelay=192, Bit 11, Center 115 (56 ~ 175) 120
7730 22:21:14.872477 iDelay=192, Bit 12, Center 127 (72 ~ 183) 112
7731 22:21:14.875745 iDelay=192, Bit 13, Center 131 (72 ~ 191) 120
7732 22:21:14.882914 iDelay=192, Bit 14, Center 131 (72 ~ 191) 120
7733 22:21:14.885984 iDelay=192, Bit 15, Center 135 (80 ~ 191) 112
7734 22:21:14.886070 ==
7735 22:21:14.889109 Dram Type= 6, Freq= 0, CH_0, rank 0
7736 22:21:14.892266 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7737 22:21:14.892352 ==
7738 22:21:14.895917 DQS Delay:
7739 22:21:14.896002 DQS0 = 0, DQS1 = 0
7740 22:21:14.896068 DQM Delay:
7741 22:21:14.898918 DQM0 = 127, DQM1 = 123
7742 22:21:14.899006 DQ Delay:
7743 22:21:14.901957 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =123
7744 22:21:14.908986 DQ4 =127, DQ5 =111, DQ6 =139, DQ7 =135
7745 22:21:14.911936 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =115
7746 22:21:14.915424 DQ12 =127, DQ13 =131, DQ14 =131, DQ15 =135
7747 22:21:14.915499
7748 22:21:14.915603
7749 22:21:14.915693 ==
7750 22:21:14.918682 Dram Type= 6, Freq= 0, CH_0, rank 0
7751 22:21:14.922130 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7752 22:21:14.922234 ==
7753 22:21:14.922343
7754 22:21:14.922433
7755 22:21:14.925044 TX Vref Scan disable
7756 22:21:14.928559 == TX Byte 0 ==
7757 22:21:14.931450 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7758 22:21:14.934900 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7759 22:21:14.938240 == TX Byte 1 ==
7760 22:21:14.941709 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
7761 22:21:14.944690 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7762 22:21:14.944774 ==
7763 22:21:14.948338 Dram Type= 6, Freq= 0, CH_0, rank 0
7764 22:21:14.955194 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7765 22:21:14.955273 ==
7766 22:21:14.966612
7767 22:21:14.969515 TX Vref early break, caculate TX vref
7768 22:21:14.973297 TX Vref=16, minBit 2, minWin=22, winSum=366
7769 22:21:14.976294 TX Vref=18, minBit 4, minWin=22, winSum=373
7770 22:21:14.979729 TX Vref=20, minBit 4, minWin=23, winSum=386
7771 22:21:14.982712 TX Vref=22, minBit 0, minWin=24, winSum=394
7772 22:21:14.986077 TX Vref=24, minBit 0, minWin=24, winSum=400
7773 22:21:14.992891 TX Vref=26, minBit 0, minWin=25, winSum=411
7774 22:21:14.995979 TX Vref=28, minBit 4, minWin=24, winSum=410
7775 22:21:14.999765 TX Vref=30, minBit 0, minWin=24, winSum=404
7776 22:21:15.002887 TX Vref=32, minBit 0, minWin=24, winSum=398
7777 22:21:15.005988 TX Vref=34, minBit 4, minWin=23, winSum=387
7778 22:21:15.012760 [TxChooseVref] Worse bit 0, Min win 25, Win sum 411, Final Vref 26
7779 22:21:15.012842
7780 22:21:15.015607 Final TX Range 0 Vref 26
7781 22:21:15.015690
7782 22:21:15.015757 ==
7783 22:21:15.019137 Dram Type= 6, Freq= 0, CH_0, rank 0
7784 22:21:15.022586 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7785 22:21:15.022662 ==
7786 22:21:15.022736
7787 22:21:15.022799
7788 22:21:15.025466 TX Vref Scan disable
7789 22:21:15.032453 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
7790 22:21:15.032559 == TX Byte 0 ==
7791 22:21:15.035810 u2DelayCellOfst[0]=15 cells (4 PI)
7792 22:21:15.038725 u2DelayCellOfst[1]=22 cells (6 PI)
7793 22:21:15.042042 u2DelayCellOfst[2]=15 cells (4 PI)
7794 22:21:15.045489 u2DelayCellOfst[3]=15 cells (4 PI)
7795 22:21:15.049037 u2DelayCellOfst[4]=7 cells (2 PI)
7796 22:21:15.052116 u2DelayCellOfst[5]=0 cells (0 PI)
7797 22:21:15.055153 u2DelayCellOfst[6]=22 cells (6 PI)
7798 22:21:15.058818 u2DelayCellOfst[7]=22 cells (6 PI)
7799 22:21:15.062053 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7800 22:21:15.065040 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7801 22:21:15.068778 == TX Byte 1 ==
7802 22:21:15.071792 u2DelayCellOfst[8]=3 cells (1 PI)
7803 22:21:15.075334 u2DelayCellOfst[9]=0 cells (0 PI)
7804 22:21:15.078268 u2DelayCellOfst[10]=7 cells (2 PI)
7805 22:21:15.081769 u2DelayCellOfst[11]=3 cells (1 PI)
7806 22:21:15.081849 u2DelayCellOfst[12]=11 cells (3 PI)
7807 22:21:15.085278 u2DelayCellOfst[13]=11 cells (3 PI)
7808 22:21:15.088352 u2DelayCellOfst[14]=18 cells (5 PI)
7809 22:21:15.091880 u2DelayCellOfst[15]=11 cells (3 PI)
7810 22:21:15.098017 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7811 22:21:15.101187 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7812 22:21:15.101263 DramC Write-DBI on
7813 22:21:15.104885 ==
7814 22:21:15.107910 Dram Type= 6, Freq= 0, CH_0, rank 0
7815 22:21:15.111740 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7816 22:21:15.111816 ==
7817 22:21:15.111879
7818 22:21:15.111950
7819 22:21:15.114912 TX Vref Scan disable
7820 22:21:15.115011 == TX Byte 0 ==
7821 22:21:15.121446 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
7822 22:21:15.121523 == TX Byte 1 ==
7823 22:21:15.125047 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
7824 22:21:15.127666 DramC Write-DBI off
7825 22:21:15.127741
7826 22:21:15.127804 [DATLAT]
7827 22:21:15.131043 Freq=1600, CH0 RK0
7828 22:21:15.131115
7829 22:21:15.131176 DATLAT Default: 0xf
7830 22:21:15.134395 0, 0xFFFF, sum = 0
7831 22:21:15.134495 1, 0xFFFF, sum = 0
7832 22:21:15.137613 2, 0xFFFF, sum = 0
7833 22:21:15.140904 3, 0xFFFF, sum = 0
7834 22:21:15.140984 4, 0xFFFF, sum = 0
7835 22:21:15.144357 5, 0xFFFF, sum = 0
7836 22:21:15.144446 6, 0xFFFF, sum = 0
7837 22:21:15.147178 7, 0xFFFF, sum = 0
7838 22:21:15.147251 8, 0xFFFF, sum = 0
7839 22:21:15.150501 9, 0xFFFF, sum = 0
7840 22:21:15.150586 10, 0xFFFF, sum = 0
7841 22:21:15.153970 11, 0xFFFF, sum = 0
7842 22:21:15.154052 12, 0xFFFF, sum = 0
7843 22:21:15.157022 13, 0xEFFF, sum = 0
7844 22:21:15.157097 14, 0x0, sum = 1
7845 22:21:15.160692 15, 0x0, sum = 2
7846 22:21:15.160766 16, 0x0, sum = 3
7847 22:21:15.163960 17, 0x0, sum = 4
7848 22:21:15.164044 best_step = 15
7849 22:21:15.164110
7850 22:21:15.164171 ==
7851 22:21:15.166980 Dram Type= 6, Freq= 0, CH_0, rank 0
7852 22:21:15.173830 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7853 22:21:15.173914 ==
7854 22:21:15.173980 RX Vref Scan: 1
7855 22:21:15.174041
7856 22:21:15.176944 Set Vref Range= 24 -> 127
7857 22:21:15.177027
7858 22:21:15.180500 RX Vref 24 -> 127, step: 1
7859 22:21:15.180582
7860 22:21:15.180648 RX Delay 11 -> 252, step: 4
7861 22:21:15.183555
7862 22:21:15.183637 Set Vref, RX VrefLevel [Byte0]: 24
7863 22:21:15.190102 [Byte1]: 24
7864 22:21:15.190200
7865 22:21:15.193173 Set Vref, RX VrefLevel [Byte0]: 25
7866 22:21:15.196882 [Byte1]: 25
7867 22:21:15.196966
7868 22:21:15.199715 Set Vref, RX VrefLevel [Byte0]: 26
7869 22:21:15.202805 [Byte1]: 26
7870 22:21:15.206570
7871 22:21:15.206652 Set Vref, RX VrefLevel [Byte0]: 27
7872 22:21:15.209678 [Byte1]: 27
7873 22:21:15.214053
7874 22:21:15.214136 Set Vref, RX VrefLevel [Byte0]: 28
7875 22:21:15.217116 [Byte1]: 28
7876 22:21:15.221428
7877 22:21:15.221510 Set Vref, RX VrefLevel [Byte0]: 29
7878 22:21:15.225265 [Byte1]: 29
7879 22:21:15.229314
7880 22:21:15.229410 Set Vref, RX VrefLevel [Byte0]: 30
7881 22:21:15.232543 [Byte1]: 30
7882 22:21:15.237048
7883 22:21:15.237188 Set Vref, RX VrefLevel [Byte0]: 31
7884 22:21:15.239877 [Byte1]: 31
7885 22:21:15.244220
7886 22:21:15.244315 Set Vref, RX VrefLevel [Byte0]: 32
7887 22:21:15.247537 [Byte1]: 32
7888 22:21:15.252057
7889 22:21:15.252141 Set Vref, RX VrefLevel [Byte0]: 33
7890 22:21:15.255434 [Byte1]: 33
7891 22:21:15.259355
7892 22:21:15.259438 Set Vref, RX VrefLevel [Byte0]: 34
7893 22:21:15.262722 [Byte1]: 34
7894 22:21:15.267123
7895 22:21:15.267241 Set Vref, RX VrefLevel [Byte0]: 35
7896 22:21:15.270763 [Byte1]: 35
7897 22:21:15.275146
7898 22:21:15.275246 Set Vref, RX VrefLevel [Byte0]: 36
7899 22:21:15.278153 [Byte1]: 36
7900 22:21:15.282530
7901 22:21:15.282614 Set Vref, RX VrefLevel [Byte0]: 37
7902 22:21:15.285449 [Byte1]: 37
7903 22:21:15.290328
7904 22:21:15.290411 Set Vref, RX VrefLevel [Byte0]: 38
7905 22:21:15.293354 [Byte1]: 38
7906 22:21:15.297516
7907 22:21:15.297602 Set Vref, RX VrefLevel [Byte0]: 39
7908 22:21:15.301177 [Byte1]: 39
7909 22:21:15.305240
7910 22:21:15.305323 Set Vref, RX VrefLevel [Byte0]: 40
7911 22:21:15.308332 [Byte1]: 40
7912 22:21:15.312755
7913 22:21:15.312837 Set Vref, RX VrefLevel [Byte0]: 41
7914 22:21:15.316493 [Byte1]: 41
7915 22:21:15.320820
7916 22:21:15.320902 Set Vref, RX VrefLevel [Byte0]: 42
7917 22:21:15.323882 [Byte1]: 42
7918 22:21:15.328274
7919 22:21:15.328358 Set Vref, RX VrefLevel [Byte0]: 43
7920 22:21:15.331357 [Byte1]: 43
7921 22:21:15.335674
7922 22:21:15.335756 Set Vref, RX VrefLevel [Byte0]: 44
7923 22:21:15.339107 [Byte1]: 44
7924 22:21:15.343550
7925 22:21:15.343663 Set Vref, RX VrefLevel [Byte0]: 45
7926 22:21:15.346479 [Byte1]: 45
7927 22:21:15.350904
7928 22:21:15.350987 Set Vref, RX VrefLevel [Byte0]: 46
7929 22:21:15.354337 [Byte1]: 46
7930 22:21:15.358356
7931 22:21:15.358440 Set Vref, RX VrefLevel [Byte0]: 47
7932 22:21:15.361679 [Byte1]: 47
7933 22:21:15.366209
7934 22:21:15.366302 Set Vref, RX VrefLevel [Byte0]: 48
7935 22:21:15.369714 [Byte1]: 48
7936 22:21:15.373854
7937 22:21:15.373970 Set Vref, RX VrefLevel [Byte0]: 49
7938 22:21:15.376961 [Byte1]: 49
7939 22:21:15.381518
7940 22:21:15.381595 Set Vref, RX VrefLevel [Byte0]: 50
7941 22:21:15.384392 [Byte1]: 50
7942 22:21:15.389105
7943 22:21:15.389184 Set Vref, RX VrefLevel [Byte0]: 51
7944 22:21:15.392152 [Byte1]: 51
7945 22:21:15.396518
7946 22:21:15.396619 Set Vref, RX VrefLevel [Byte0]: 52
7947 22:21:15.400276 [Byte1]: 52
7948 22:21:15.404513
7949 22:21:15.404616 Set Vref, RX VrefLevel [Byte0]: 53
7950 22:21:15.407494 [Byte1]: 53
7951 22:21:15.411755
7952 22:21:15.411857 Set Vref, RX VrefLevel [Byte0]: 54
7953 22:21:15.414841 [Byte1]: 54
7954 22:21:15.419346
7955 22:21:15.419422 Set Vref, RX VrefLevel [Byte0]: 55
7956 22:21:15.423028 [Byte1]: 55
7957 22:21:15.427368
7958 22:21:15.427456 Set Vref, RX VrefLevel [Byte0]: 56
7959 22:21:15.430498 [Byte1]: 56
7960 22:21:15.434792
7961 22:21:15.434922 Set Vref, RX VrefLevel [Byte0]: 57
7962 22:21:15.437945 [Byte1]: 57
7963 22:21:15.442260
7964 22:21:15.442363 Set Vref, RX VrefLevel [Byte0]: 58
7965 22:21:15.445996 [Byte1]: 58
7966 22:21:15.449911
7967 22:21:15.449984 Set Vref, RX VrefLevel [Byte0]: 59
7968 22:21:15.453288 [Byte1]: 59
7969 22:21:15.457675
7970 22:21:15.457754 Set Vref, RX VrefLevel [Byte0]: 60
7971 22:21:15.461102 [Byte1]: 60
7972 22:21:15.465119
7973 22:21:15.465204 Set Vref, RX VrefLevel [Byte0]: 61
7974 22:21:15.468489 [Byte1]: 61
7975 22:21:15.473010
7976 22:21:15.473119 Set Vref, RX VrefLevel [Byte0]: 62
7977 22:21:15.475749 [Byte1]: 62
7978 22:21:15.480506
7979 22:21:15.480584 Set Vref, RX VrefLevel [Byte0]: 63
7980 22:21:15.483472 [Byte1]: 63
7981 22:21:15.487848
7982 22:21:15.487979 Set Vref, RX VrefLevel [Byte0]: 64
7983 22:21:15.491569 [Byte1]: 64
7984 22:21:15.495391
7985 22:21:15.495533 Set Vref, RX VrefLevel [Byte0]: 65
7986 22:21:15.499026 [Byte1]: 65
7987 22:21:15.503454
7988 22:21:15.503549 Set Vref, RX VrefLevel [Byte0]: 66
7989 22:21:15.506507 [Byte1]: 66
7990 22:21:15.510819
7991 22:21:15.510951 Set Vref, RX VrefLevel [Byte0]: 67
7992 22:21:15.513900 [Byte1]: 67
7993 22:21:15.518763
7994 22:21:15.518921 Set Vref, RX VrefLevel [Byte0]: 68
7995 22:21:15.522025 [Byte1]: 68
7996 22:21:15.525812
7997 22:21:15.525916 Set Vref, RX VrefLevel [Byte0]: 69
7998 22:21:15.529571 [Byte1]: 69
7999 22:21:15.533923
8000 22:21:15.534034 Set Vref, RX VrefLevel [Byte0]: 70
8001 22:21:15.537083 [Byte1]: 70
8002 22:21:15.541515
8003 22:21:15.541601 Set Vref, RX VrefLevel [Byte0]: 71
8004 22:21:15.544665 [Byte1]: 71
8005 22:21:15.549012
8006 22:21:15.549099 Set Vref, RX VrefLevel [Byte0]: 72
8007 22:21:15.552048 [Byte1]: 72
8008 22:21:15.556523
8009 22:21:15.556626 Set Vref, RX VrefLevel [Byte0]: 73
8010 22:21:15.560002 [Byte1]: 73
8011 22:21:15.564255
8012 22:21:15.564344 Set Vref, RX VrefLevel [Byte0]: 74
8013 22:21:15.567499 [Byte1]: 74
8014 22:21:15.571652
8015 22:21:15.571744 Set Vref, RX VrefLevel [Byte0]: 75
8016 22:21:15.575235 [Byte1]: 75
8017 22:21:15.579360
8018 22:21:15.579436 Set Vref, RX VrefLevel [Byte0]: 76
8019 22:21:15.582991 [Byte1]: 76
8020 22:21:15.587026
8021 22:21:15.587144 Final RX Vref Byte 0 = 59 to rank0
8022 22:21:15.590135 Final RX Vref Byte 1 = 58 to rank0
8023 22:21:15.593358 Final RX Vref Byte 0 = 59 to rank1
8024 22:21:15.596950 Final RX Vref Byte 1 = 58 to rank1==
8025 22:21:15.600022 Dram Type= 6, Freq= 0, CH_0, rank 0
8026 22:21:15.607014 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8027 22:21:15.607107 ==
8028 22:21:15.607174 DQS Delay:
8029 22:21:15.607235 DQS0 = 0, DQS1 = 0
8030 22:21:15.610308 DQM Delay:
8031 22:21:15.610390 DQM0 = 125, DQM1 = 119
8032 22:21:15.613297 DQ Delay:
8033 22:21:15.616397 DQ0 =124, DQ1 =128, DQ2 =124, DQ3 =122
8034 22:21:15.620116 DQ4 =124, DQ5 =112, DQ6 =132, DQ7 =136
8035 22:21:15.623084 DQ8 =112, DQ9 =106, DQ10 =120, DQ11 =114
8036 22:21:15.626332 DQ12 =124, DQ13 =124, DQ14 =130, DQ15 =128
8037 22:21:15.626414
8038 22:21:15.626479
8039 22:21:15.626539
8040 22:21:15.629519 [DramC_TX_OE_Calibration] TA2
8041 22:21:15.633011 Original DQ_B0 (3 6) =30, OEN = 27
8042 22:21:15.636519 Original DQ_B1 (3 6) =30, OEN = 27
8043 22:21:15.639756 24, 0x0, End_B0=24 End_B1=24
8044 22:21:15.642988 25, 0x0, End_B0=25 End_B1=25
8045 22:21:15.643086 26, 0x0, End_B0=26 End_B1=26
8046 22:21:15.646255 27, 0x0, End_B0=27 End_B1=27
8047 22:21:15.649432 28, 0x0, End_B0=28 End_B1=28
8048 22:21:15.653141 29, 0x0, End_B0=29 End_B1=29
8049 22:21:15.653226 30, 0x0, End_B0=30 End_B1=30
8050 22:21:15.656301 31, 0x4545, End_B0=30 End_B1=30
8051 22:21:15.659363 Byte0 end_step=30 best_step=27
8052 22:21:15.662552 Byte1 end_step=30 best_step=27
8053 22:21:15.666307 Byte0 TX OE(2T, 0.5T) = (3, 3)
8054 22:21:15.669356 Byte1 TX OE(2T, 0.5T) = (3, 3)
8055 22:21:15.669441
8056 22:21:15.669508
8057 22:21:15.676190 [DQSOSCAuto] RK0, (LSB)MR18= 0x1313, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 400 ps
8058 22:21:15.679565 CH0 RK0: MR19=303, MR18=1313
8059 22:21:15.685802 CH0_RK0: MR19=0x303, MR18=0x1313, DQSOSC=400, MR23=63, INC=23, DEC=15
8060 22:21:15.685919
8061 22:21:15.689411 ----->DramcWriteLeveling(PI) begin...
8062 22:21:15.689516 ==
8063 22:21:15.692782 Dram Type= 6, Freq= 0, CH_0, rank 1
8064 22:21:15.695588 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8065 22:21:15.695664 ==
8066 22:21:15.699152 Write leveling (Byte 0): 34 => 34
8067 22:21:15.702773 Write leveling (Byte 1): 30 => 30
8068 22:21:15.705868 DramcWriteLeveling(PI) end<-----
8069 22:21:15.705967
8070 22:21:15.706065 ==
8071 22:21:15.709041 Dram Type= 6, Freq= 0, CH_0, rank 1
8072 22:21:15.712152 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8073 22:21:15.715446 ==
8074 22:21:15.715552 [Gating] SW mode calibration
8075 22:21:15.725869 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8076 22:21:15.728791 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8077 22:21:15.732591 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8078 22:21:15.738820 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8079 22:21:15.742123 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8080 22:21:15.745343 1 4 12 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
8081 22:21:15.751746 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8082 22:21:15.755531 1 4 20 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
8083 22:21:15.758542 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8084 22:21:15.765386 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8085 22:21:15.768801 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8086 22:21:15.771724 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8087 22:21:15.778243 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8088 22:21:15.781643 1 5 12 | B1->B0 | 3434 2929 | 1 0 | (1 1) (0 1)
8089 22:21:15.784726 1 5 16 | B1->B0 | 3131 2323 | 0 0 | (0 0) (0 0)
8090 22:21:15.791528 1 5 20 | B1->B0 | 2424 2323 | 1 0 | (1 0) (0 0)
8091 22:21:15.795024 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8092 22:21:15.797952 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8093 22:21:15.805130 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8094 22:21:15.808100 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8095 22:21:15.811480 1 6 8 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
8096 22:21:15.817751 1 6 12 | B1->B0 | 2323 3e3e | 0 0 | (0 0) (0 0)
8097 22:21:15.820877 1 6 16 | B1->B0 | 2f2f 4646 | 1 0 | (0 0) (0 0)
8098 22:21:15.824586 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8099 22:21:15.830754 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8100 22:21:15.834298 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8101 22:21:15.837974 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8102 22:21:15.844140 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8103 22:21:15.847286 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8104 22:21:15.850525 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8105 22:21:15.857486 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8106 22:21:15.860715 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8107 22:21:15.863716 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8108 22:21:15.870551 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8109 22:21:15.873726 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8110 22:21:15.876940 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8111 22:21:15.883363 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8112 22:21:15.886529 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8113 22:21:15.893161 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8114 22:21:15.896654 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8115 22:21:15.899653 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8116 22:21:15.903251 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8117 22:21:15.910111 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8118 22:21:15.913047 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8119 22:21:15.919397 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8120 22:21:15.922653 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8121 22:21:15.926344 Total UI for P1: 0, mck2ui 16
8122 22:21:15.929598 best dqsien dly found for B0: ( 1, 9, 8)
8123 22:21:15.932699 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8124 22:21:15.939461 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8125 22:21:15.942649 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8126 22:21:15.946063 Total UI for P1: 0, mck2ui 16
8127 22:21:15.949272 best dqsien dly found for B1: ( 1, 9, 18)
8128 22:21:15.952437 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8129 22:21:15.956191 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8130 22:21:15.956271
8131 22:21:15.959431 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8132 22:21:15.962690 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8133 22:21:15.965815 [Gating] SW calibration Done
8134 22:21:15.965905 ==
8135 22:21:15.968759 Dram Type= 6, Freq= 0, CH_0, rank 1
8136 22:21:15.972498 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8137 22:21:15.972594 ==
8138 22:21:15.975706 RX Vref Scan: 0
8139 22:21:15.975791
8140 22:21:15.978871 RX Vref 0 -> 0, step: 1
8141 22:21:15.978968
8142 22:21:15.979035 RX Delay 0 -> 252, step: 8
8143 22:21:15.985314 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
8144 22:21:15.988977 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8145 22:21:15.992263 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8146 22:21:15.995692 iDelay=200, Bit 3, Center 123 (64 ~ 183) 120
8147 22:21:15.998528 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8148 22:21:16.005157 iDelay=200, Bit 5, Center 115 (56 ~ 175) 120
8149 22:21:16.008753 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8150 22:21:16.011749 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8151 22:21:16.014987 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8152 22:21:16.021716 iDelay=200, Bit 9, Center 107 (48 ~ 167) 120
8153 22:21:16.024742 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8154 22:21:16.028484 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8155 22:21:16.031611 iDelay=200, Bit 12, Center 127 (64 ~ 191) 128
8156 22:21:16.034799 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
8157 22:21:16.041595 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8158 22:21:16.044727 iDelay=200, Bit 15, Center 127 (64 ~ 191) 128
8159 22:21:16.044811 ==
8160 22:21:16.047850 Dram Type= 6, Freq= 0, CH_0, rank 1
8161 22:21:16.051514 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8162 22:21:16.051598 ==
8163 22:21:16.054718 DQS Delay:
8164 22:21:16.054802 DQS0 = 0, DQS1 = 0
8165 22:21:16.054909 DQM Delay:
8166 22:21:16.057925 DQM0 = 128, DQM1 = 121
8167 22:21:16.058008 DQ Delay:
8168 22:21:16.061079 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =123
8169 22:21:16.064820 DQ4 =127, DQ5 =115, DQ6 =139, DQ7 =139
8170 22:21:16.071178 DQ8 =115, DQ9 =107, DQ10 =123, DQ11 =115
8171 22:21:16.074269 DQ12 =127, DQ13 =127, DQ14 =131, DQ15 =127
8172 22:21:16.074352
8173 22:21:16.074418
8174 22:21:16.074478 ==
8175 22:21:16.077872 Dram Type= 6, Freq= 0, CH_0, rank 1
8176 22:21:16.081055 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8177 22:21:16.081144 ==
8178 22:21:16.081210
8179 22:21:16.081271
8180 22:21:16.084178 TX Vref Scan disable
8181 22:21:16.088015 == TX Byte 0 ==
8182 22:21:16.091297 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8183 22:21:16.094400 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8184 22:21:16.097734 == TX Byte 1 ==
8185 22:21:16.101143 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
8186 22:21:16.104118 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8187 22:21:16.104201 ==
8188 22:21:16.107576 Dram Type= 6, Freq= 0, CH_0, rank 1
8189 22:21:16.111160 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8190 22:21:16.114178 ==
8191 22:21:16.126545
8192 22:21:16.130095 TX Vref early break, caculate TX vref
8193 22:21:16.133131 TX Vref=16, minBit 0, minWin=22, winSum=372
8194 22:21:16.136355 TX Vref=18, minBit 0, minWin=22, winSum=383
8195 22:21:16.139548 TX Vref=20, minBit 0, minWin=23, winSum=390
8196 22:21:16.142817 TX Vref=22, minBit 0, minWin=24, winSum=397
8197 22:21:16.146622 TX Vref=24, minBit 1, minWin=23, winSum=405
8198 22:21:16.152753 TX Vref=26, minBit 0, minWin=25, winSum=416
8199 22:21:16.156462 TX Vref=28, minBit 3, minWin=25, winSum=417
8200 22:21:16.159815 TX Vref=30, minBit 8, minWin=24, winSum=411
8201 22:21:16.162813 TX Vref=32, minBit 11, minWin=24, winSum=406
8202 22:21:16.165999 TX Vref=34, minBit 3, minWin=24, winSum=400
8203 22:21:16.172480 TX Vref=36, minBit 2, minWin=24, winSum=392
8204 22:21:16.175694 [TxChooseVref] Worse bit 3, Min win 25, Win sum 417, Final Vref 28
8205 22:21:16.175776
8206 22:21:16.179303 Final TX Range 0 Vref 28
8207 22:21:16.179382
8208 22:21:16.179446 ==
8209 22:21:16.183076 Dram Type= 6, Freq= 0, CH_0, rank 1
8210 22:21:16.186041 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8211 22:21:16.189194 ==
8212 22:21:16.189304
8213 22:21:16.189400
8214 22:21:16.189490 TX Vref Scan disable
8215 22:21:16.195792 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8216 22:21:16.195876 == TX Byte 0 ==
8217 22:21:16.199540 u2DelayCellOfst[0]=15 cells (4 PI)
8218 22:21:16.202737 u2DelayCellOfst[1]=18 cells (5 PI)
8219 22:21:16.205692 u2DelayCellOfst[2]=11 cells (3 PI)
8220 22:21:16.209300 u2DelayCellOfst[3]=11 cells (3 PI)
8221 22:21:16.212353 u2DelayCellOfst[4]=7 cells (2 PI)
8222 22:21:16.215910 u2DelayCellOfst[5]=0 cells (0 PI)
8223 22:21:16.218947 u2DelayCellOfst[6]=18 cells (5 PI)
8224 22:21:16.222552 u2DelayCellOfst[7]=18 cells (5 PI)
8225 22:21:16.225466 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
8226 22:21:16.229109 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8227 22:21:16.232105 == TX Byte 1 ==
8228 22:21:16.235664 u2DelayCellOfst[8]=0 cells (0 PI)
8229 22:21:16.238595 u2DelayCellOfst[9]=0 cells (0 PI)
8230 22:21:16.242399 u2DelayCellOfst[10]=3 cells (1 PI)
8231 22:21:16.245685 u2DelayCellOfst[11]=3 cells (1 PI)
8232 22:21:16.249089 u2DelayCellOfst[12]=11 cells (3 PI)
8233 22:21:16.251890 u2DelayCellOfst[13]=11 cells (3 PI)
8234 22:21:16.255762 u2DelayCellOfst[14]=15 cells (4 PI)
8235 22:21:16.255835 u2DelayCellOfst[15]=11 cells (3 PI)
8236 22:21:16.261799 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8237 22:21:16.265172 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8238 22:21:16.268717 DramC Write-DBI on
8239 22:21:16.268846 ==
8240 22:21:16.271940 Dram Type= 6, Freq= 0, CH_0, rank 1
8241 22:21:16.275136 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8242 22:21:16.275218 ==
8243 22:21:16.275281
8244 22:21:16.275347
8245 22:21:16.278326 TX Vref Scan disable
8246 22:21:16.278407 == TX Byte 0 ==
8247 22:21:16.285003 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
8248 22:21:16.285090 == TX Byte 1 ==
8249 22:21:16.291115 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
8250 22:21:16.291196 DramC Write-DBI off
8251 22:21:16.291262
8252 22:21:16.291321 [DATLAT]
8253 22:21:16.294413 Freq=1600, CH0 RK1
8254 22:21:16.294488
8255 22:21:16.298301 DATLAT Default: 0xf
8256 22:21:16.298377 0, 0xFFFF, sum = 0
8257 22:21:16.301444 1, 0xFFFF, sum = 0
8258 22:21:16.301519 2, 0xFFFF, sum = 0
8259 22:21:16.304633 3, 0xFFFF, sum = 0
8260 22:21:16.304708 4, 0xFFFF, sum = 0
8261 22:21:16.307726 5, 0xFFFF, sum = 0
8262 22:21:16.307799 6, 0xFFFF, sum = 0
8263 22:21:16.311564 7, 0xFFFF, sum = 0
8264 22:21:16.311652 8, 0xFFFF, sum = 0
8265 22:21:16.314270 9, 0xFFFF, sum = 0
8266 22:21:16.314340 10, 0xFFFF, sum = 0
8267 22:21:16.317936 11, 0xFFFF, sum = 0
8268 22:21:16.318007 12, 0xFFFF, sum = 0
8269 22:21:16.320883 13, 0xCFFF, sum = 0
8270 22:21:16.320954 14, 0x0, sum = 1
8271 22:21:16.324604 15, 0x0, sum = 2
8272 22:21:16.324750 16, 0x0, sum = 3
8273 22:21:16.327598 17, 0x0, sum = 4
8274 22:21:16.327689 best_step = 15
8275 22:21:16.327754
8276 22:21:16.327812 ==
8277 22:21:16.331466 Dram Type= 6, Freq= 0, CH_0, rank 1
8278 22:21:16.337730 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8279 22:21:16.337815 ==
8280 22:21:16.337881 RX Vref Scan: 0
8281 22:21:16.337940
8282 22:21:16.340940 RX Vref 0 -> 0, step: 1
8283 22:21:16.341052
8284 22:21:16.343875 RX Delay 3 -> 252, step: 4
8285 22:21:16.347753 iDelay=191, Bit 0, Center 122 (67 ~ 178) 112
8286 22:21:16.350818 iDelay=191, Bit 1, Center 126 (71 ~ 182) 112
8287 22:21:16.357208 iDelay=191, Bit 2, Center 120 (67 ~ 174) 108
8288 22:21:16.361133 iDelay=191, Bit 3, Center 120 (63 ~ 178) 116
8289 22:21:16.363939 iDelay=191, Bit 4, Center 124 (71 ~ 178) 108
8290 22:21:16.367029 iDelay=191, Bit 5, Center 112 (59 ~ 166) 108
8291 22:21:16.370693 iDelay=191, Bit 6, Center 134 (79 ~ 190) 112
8292 22:21:16.377102 iDelay=191, Bit 7, Center 134 (79 ~ 190) 112
8293 22:21:16.380336 iDelay=191, Bit 8, Center 112 (55 ~ 170) 116
8294 22:21:16.383543 iDelay=191, Bit 9, Center 104 (47 ~ 162) 116
8295 22:21:16.387216 iDelay=191, Bit 10, Center 120 (63 ~ 178) 116
8296 22:21:16.390247 iDelay=191, Bit 11, Center 112 (55 ~ 170) 116
8297 22:21:16.396693 iDelay=191, Bit 12, Center 124 (67 ~ 182) 116
8298 22:21:16.400548 iDelay=191, Bit 13, Center 122 (67 ~ 178) 112
8299 22:21:16.403684 iDelay=191, Bit 14, Center 128 (71 ~ 186) 116
8300 22:21:16.406884 iDelay=191, Bit 15, Center 124 (67 ~ 182) 116
8301 22:21:16.406954 ==
8302 22:21:16.410046 Dram Type= 6, Freq= 0, CH_0, rank 1
8303 22:21:16.416375 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8304 22:21:16.416450 ==
8305 22:21:16.416513 DQS Delay:
8306 22:21:16.420207 DQS0 = 0, DQS1 = 0
8307 22:21:16.420283 DQM Delay:
8308 22:21:16.423528 DQM0 = 124, DQM1 = 118
8309 22:21:16.423603 DQ Delay:
8310 22:21:16.426511 DQ0 =122, DQ1 =126, DQ2 =120, DQ3 =120
8311 22:21:16.429727 DQ4 =124, DQ5 =112, DQ6 =134, DQ7 =134
8312 22:21:16.433292 DQ8 =112, DQ9 =104, DQ10 =120, DQ11 =112
8313 22:21:16.436371 DQ12 =124, DQ13 =122, DQ14 =128, DQ15 =124
8314 22:21:16.436444
8315 22:21:16.436507
8316 22:21:16.436565
8317 22:21:16.439652 [DramC_TX_OE_Calibration] TA2
8318 22:21:16.443229 Original DQ_B0 (3 6) =30, OEN = 27
8319 22:21:16.446191 Original DQ_B1 (3 6) =30, OEN = 27
8320 22:21:16.449691 24, 0x0, End_B0=24 End_B1=24
8321 22:21:16.453315 25, 0x0, End_B0=25 End_B1=25
8322 22:21:16.453392 26, 0x0, End_B0=26 End_B1=26
8323 22:21:16.456451 27, 0x0, End_B0=27 End_B1=27
8324 22:21:16.459635 28, 0x0, End_B0=28 End_B1=28
8325 22:21:16.462749 29, 0x0, End_B0=29 End_B1=29
8326 22:21:16.462887 30, 0x0, End_B0=30 End_B1=30
8327 22:21:16.465935 31, 0x4141, End_B0=30 End_B1=30
8328 22:21:16.469749 Byte0 end_step=30 best_step=27
8329 22:21:16.472795 Byte1 end_step=30 best_step=27
8330 22:21:16.475835 Byte0 TX OE(2T, 0.5T) = (3, 3)
8331 22:21:16.478972 Byte1 TX OE(2T, 0.5T) = (3, 3)
8332 22:21:16.479071
8333 22:21:16.479143
8334 22:21:16.485910 [DQSOSCAuto] RK1, (LSB)MR18= 0x220f, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 392 ps
8335 22:21:16.489127 CH0 RK1: MR19=303, MR18=220F
8336 22:21:16.495999 CH0_RK1: MR19=0x303, MR18=0x220F, DQSOSC=392, MR23=63, INC=24, DEC=16
8337 22:21:16.499231 [RxdqsGatingPostProcess] freq 1600
8338 22:21:16.505626 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8339 22:21:16.505708 best DQS0 dly(2T, 0.5T) = (1, 1)
8340 22:21:16.508865 best DQS1 dly(2T, 0.5T) = (1, 1)
8341 22:21:16.512016 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8342 22:21:16.515825 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8343 22:21:16.518993 best DQS0 dly(2T, 0.5T) = (1, 1)
8344 22:21:16.522266 best DQS1 dly(2T, 0.5T) = (1, 1)
8345 22:21:16.525289 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8346 22:21:16.529029 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8347 22:21:16.532158 Pre-setting of DQS Precalculation
8348 22:21:16.535647 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8349 22:21:16.538655 ==
8350 22:21:16.538740 Dram Type= 6, Freq= 0, CH_1, rank 0
8351 22:21:16.545447 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8352 22:21:16.545531 ==
8353 22:21:16.548418 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8354 22:21:16.554982 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8355 22:21:16.558609 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8356 22:21:16.565041 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8357 22:21:16.573222 [CA 0] Center 42 (13~71) winsize 59
8358 22:21:16.576229 [CA 1] Center 42 (12~72) winsize 61
8359 22:21:16.579905 [CA 2] Center 38 (9~67) winsize 59
8360 22:21:16.583017 [CA 3] Center 37 (8~66) winsize 59
8361 22:21:16.586297 [CA 4] Center 38 (9~67) winsize 59
8362 22:21:16.589433 [CA 5] Center 36 (7~66) winsize 60
8363 22:21:16.589513
8364 22:21:16.592673 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8365 22:21:16.592753
8366 22:21:16.599489 [CATrainingPosCal] consider 1 rank data
8367 22:21:16.599569 u2DelayCellTimex100 = 258/100 ps
8368 22:21:16.605784 CA0 delay=42 (13~71),Diff = 6 PI (22 cell)
8369 22:21:16.609612 CA1 delay=42 (12~72),Diff = 6 PI (22 cell)
8370 22:21:16.613062 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8371 22:21:16.616032 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8372 22:21:16.619191 CA4 delay=38 (9~67),Diff = 2 PI (7 cell)
8373 22:21:16.622390 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8374 22:21:16.622471
8375 22:21:16.626226 CA PerBit enable=1, Macro0, CA PI delay=36
8376 22:21:16.626305
8377 22:21:16.629321 [CBTSetCACLKResult] CA Dly = 36
8378 22:21:16.632728 CS Dly: 9 (0~40)
8379 22:21:16.635606 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8380 22:21:16.639197 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8381 22:21:16.639277 ==
8382 22:21:16.642759 Dram Type= 6, Freq= 0, CH_1, rank 1
8383 22:21:16.648844 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8384 22:21:16.648926 ==
8385 22:21:16.652517 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8386 22:21:16.659001 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8387 22:21:16.662052 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8388 22:21:16.668522 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8389 22:21:16.676029 [CA 0] Center 42 (13~71) winsize 59
8390 22:21:16.679707 [CA 1] Center 42 (12~72) winsize 61
8391 22:21:16.682722 [CA 2] Center 38 (8~68) winsize 61
8392 22:21:16.686362 [CA 3] Center 36 (7~66) winsize 60
8393 22:21:16.689453 [CA 4] Center 38 (8~68) winsize 61
8394 22:21:16.692378 [CA 5] Center 37 (7~67) winsize 61
8395 22:21:16.692459
8396 22:21:16.696207 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8397 22:21:16.696286
8398 22:21:16.699435 [CATrainingPosCal] consider 2 rank data
8399 22:21:16.702471 u2DelayCellTimex100 = 258/100 ps
8400 22:21:16.708923 CA0 delay=42 (13~71),Diff = 6 PI (22 cell)
8401 22:21:16.712101 CA1 delay=42 (12~72),Diff = 6 PI (22 cell)
8402 22:21:16.715842 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8403 22:21:16.718983 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8404 22:21:16.722216 CA4 delay=38 (9~67),Diff = 2 PI (7 cell)
8405 22:21:16.725466 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8406 22:21:16.725546
8407 22:21:16.728656 CA PerBit enable=1, Macro0, CA PI delay=36
8408 22:21:16.728753
8409 22:21:16.732449 [CBTSetCACLKResult] CA Dly = 36
8410 22:21:16.735440 CS Dly: 11 (0~44)
8411 22:21:16.738635 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8412 22:21:16.742009 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8413 22:21:16.742093
8414 22:21:16.745368 ----->DramcWriteLeveling(PI) begin...
8415 22:21:16.745478 ==
8416 22:21:16.748397 Dram Type= 6, Freq= 0, CH_1, rank 0
8417 22:21:16.755035 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8418 22:21:16.755121 ==
8419 22:21:16.758738 Write leveling (Byte 0): 26 => 26
8420 22:21:16.761866 Write leveling (Byte 1): 29 => 29
8421 22:21:16.765231 DramcWriteLeveling(PI) end<-----
8422 22:21:16.765343
8423 22:21:16.765433 ==
8424 22:21:16.768389 Dram Type= 6, Freq= 0, CH_1, rank 0
8425 22:21:16.772206 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8426 22:21:16.772289 ==
8427 22:21:16.774868 [Gating] SW mode calibration
8428 22:21:16.781475 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8429 22:21:16.787759 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8430 22:21:16.791505 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8431 22:21:16.794635 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8432 22:21:16.801241 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8433 22:21:16.804450 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8434 22:21:16.808067 1 4 16 | B1->B0 | 3333 3030 | 1 1 | (1 1) (1 1)
8435 22:21:16.814441 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8436 22:21:16.817794 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8437 22:21:16.820943 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8438 22:21:16.827374 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8439 22:21:16.831165 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8440 22:21:16.834305 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8441 22:21:16.840721 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8442 22:21:16.843862 1 5 16 | B1->B0 | 2626 2929 | 0 0 | (1 0) (1 0)
8443 22:21:16.847896 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8444 22:21:16.853900 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8445 22:21:16.857170 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8446 22:21:16.860486 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8447 22:21:16.866979 1 6 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8448 22:21:16.870591 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8449 22:21:16.873466 1 6 12 | B1->B0 | 2828 2727 | 0 0 | (0 0) (0 0)
8450 22:21:16.880563 1 6 16 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
8451 22:21:16.883451 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8452 22:21:16.887218 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8453 22:21:16.893418 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8454 22:21:16.896998 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8455 22:21:16.900083 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8456 22:21:16.906951 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8457 22:21:16.909935 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8458 22:21:16.913092 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8459 22:21:16.920019 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8460 22:21:16.923185 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8461 22:21:16.926504 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8462 22:21:16.932957 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8463 22:21:16.936090 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8464 22:21:16.939871 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8465 22:21:16.945995 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8466 22:21:16.949400 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8467 22:21:16.952955 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8468 22:21:16.959792 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8469 22:21:16.963003 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8470 22:21:16.966096 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8471 22:21:16.972756 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8472 22:21:16.976022 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8473 22:21:16.979520 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8474 22:21:16.985865 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8475 22:21:16.989259 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8476 22:21:16.992204 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8477 22:21:16.995973 Total UI for P1: 0, mck2ui 16
8478 22:21:16.999086 best dqsien dly found for B0: ( 1, 9, 16)
8479 22:21:17.002211 Total UI for P1: 0, mck2ui 16
8480 22:21:17.005796 best dqsien dly found for B1: ( 1, 9, 16)
8481 22:21:17.008943 best DQS0 dly(MCK, UI, PI) = (1, 9, 16)
8482 22:21:17.012421 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8483 22:21:17.012507
8484 22:21:17.018643 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)
8485 22:21:17.021831 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8486 22:21:17.021917 [Gating] SW calibration Done
8487 22:21:17.025048 ==
8488 22:21:17.028868 Dram Type= 6, Freq= 0, CH_1, rank 0
8489 22:21:17.032014 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8490 22:21:17.032101 ==
8491 22:21:17.032187 RX Vref Scan: 0
8492 22:21:17.032268
8493 22:21:17.035265 RX Vref 0 -> 0, step: 1
8494 22:21:17.035350
8495 22:21:17.038481 RX Delay 0 -> 252, step: 8
8496 22:21:17.041731 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8497 22:21:17.045110 iDelay=200, Bit 1, Center 123 (64 ~ 183) 120
8498 22:21:17.051944 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8499 22:21:17.054940 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8500 22:21:17.058354 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8501 22:21:17.061121 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8502 22:21:17.064952 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8503 22:21:17.071625 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8504 22:21:17.074416 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
8505 22:21:17.078078 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8506 22:21:17.081143 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
8507 22:21:17.084725 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8508 22:21:17.090757 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8509 22:21:17.094361 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8510 22:21:17.097737 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8511 22:21:17.101138 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8512 22:21:17.101238 ==
8513 22:21:17.104060 Dram Type= 6, Freq= 0, CH_1, rank 0
8514 22:21:17.110741 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8515 22:21:17.110834 ==
8516 22:21:17.110934 DQS Delay:
8517 22:21:17.113861 DQS0 = 0, DQS1 = 0
8518 22:21:17.113945 DQM Delay:
8519 22:21:17.117417 DQM0 = 131, DQM1 = 125
8520 22:21:17.117520 DQ Delay:
8521 22:21:17.120332 DQ0 =135, DQ1 =123, DQ2 =119, DQ3 =131
8522 22:21:17.124173 DQ4 =127, DQ5 =143, DQ6 =143, DQ7 =127
8523 22:21:17.127450 DQ8 =111, DQ9 =115, DQ10 =123, DQ11 =119
8524 22:21:17.130692 DQ12 =135, DQ13 =131, DQ14 =135, DQ15 =135
8525 22:21:17.130777
8526 22:21:17.130902
8527 22:21:17.130982 ==
8528 22:21:17.133848 Dram Type= 6, Freq= 0, CH_1, rank 0
8529 22:21:17.140125 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8530 22:21:17.140212 ==
8531 22:21:17.140296
8532 22:21:17.140375
8533 22:21:17.140454 TX Vref Scan disable
8534 22:21:17.144194 == TX Byte 0 ==
8535 22:21:17.147117 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8536 22:21:17.153940 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8537 22:21:17.154026 == TX Byte 1 ==
8538 22:21:17.157220 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8539 22:21:17.163752 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8540 22:21:17.163838 ==
8541 22:21:17.166900 Dram Type= 6, Freq= 0, CH_1, rank 0
8542 22:21:17.170100 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8543 22:21:17.170187 ==
8544 22:21:17.184069
8545 22:21:17.187009 TX Vref early break, caculate TX vref
8546 22:21:17.190512 TX Vref=16, minBit 8, minWin=20, winSum=358
8547 22:21:17.194090 TX Vref=18, minBit 9, minWin=22, winSum=369
8548 22:21:17.197111 TX Vref=20, minBit 8, minWin=22, winSum=375
8549 22:21:17.200085 TX Vref=22, minBit 8, minWin=23, winSum=388
8550 22:21:17.203593 TX Vref=24, minBit 8, minWin=24, winSum=399
8551 22:21:17.210211 TX Vref=26, minBit 8, minWin=24, winSum=406
8552 22:21:17.213231 TX Vref=28, minBit 11, minWin=24, winSum=407
8553 22:21:17.216926 TX Vref=30, minBit 0, minWin=25, winSum=409
8554 22:21:17.220025 TX Vref=32, minBit 9, minWin=23, winSum=400
8555 22:21:17.223064 TX Vref=34, minBit 9, minWin=22, winSum=390
8556 22:21:17.229645 TX Vref=36, minBit 1, minWin=22, winSum=381
8557 22:21:17.233540 [TxChooseVref] Worse bit 0, Min win 25, Win sum 409, Final Vref 30
8558 22:21:17.233622
8559 22:21:17.236864 Final TX Range 0 Vref 30
8560 22:21:17.236942
8561 22:21:17.237014 ==
8562 22:21:17.240019 Dram Type= 6, Freq= 0, CH_1, rank 0
8563 22:21:17.243253 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8564 22:21:17.246462 ==
8565 22:21:17.246546
8566 22:21:17.246613
8567 22:21:17.246673 TX Vref Scan disable
8568 22:21:17.253515 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8569 22:21:17.253597 == TX Byte 0 ==
8570 22:21:17.256500 u2DelayCellOfst[0]=22 cells (6 PI)
8571 22:21:17.259711 u2DelayCellOfst[1]=15 cells (4 PI)
8572 22:21:17.262837 u2DelayCellOfst[2]=0 cells (0 PI)
8573 22:21:17.266616 u2DelayCellOfst[3]=11 cells (3 PI)
8574 22:21:17.269692 u2DelayCellOfst[4]=11 cells (3 PI)
8575 22:21:17.272980 u2DelayCellOfst[5]=26 cells (7 PI)
8576 22:21:17.276441 u2DelayCellOfst[6]=22 cells (6 PI)
8577 22:21:17.279554 u2DelayCellOfst[7]=7 cells (2 PI)
8578 22:21:17.283138 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8579 22:21:17.286286 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8580 22:21:17.289440 == TX Byte 1 ==
8581 22:21:17.292625 u2DelayCellOfst[8]=0 cells (0 PI)
8582 22:21:17.296389 u2DelayCellOfst[9]=7 cells (2 PI)
8583 22:21:17.299221 u2DelayCellOfst[10]=15 cells (4 PI)
8584 22:21:17.302591 u2DelayCellOfst[11]=7 cells (2 PI)
8585 22:21:17.305957 u2DelayCellOfst[12]=18 cells (5 PI)
8586 22:21:17.309478 u2DelayCellOfst[13]=18 cells (5 PI)
8587 22:21:17.312921 u2DelayCellOfst[14]=18 cells (5 PI)
8588 22:21:17.313027 u2DelayCellOfst[15]=18 cells (5 PI)
8589 22:21:17.319415 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8590 22:21:17.322414 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8591 22:21:17.325964 DramC Write-DBI on
8592 22:21:17.326071 ==
8593 22:21:17.329103 Dram Type= 6, Freq= 0, CH_1, rank 0
8594 22:21:17.332736 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8595 22:21:17.332819 ==
8596 22:21:17.332885
8597 22:21:17.332944
8598 22:21:17.336220 TX Vref Scan disable
8599 22:21:17.336295 == TX Byte 0 ==
8600 22:21:17.342680 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8601 22:21:17.342782 == TX Byte 1 ==
8602 22:21:17.345899 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8603 22:21:17.349120 DramC Write-DBI off
8604 22:21:17.349192
8605 22:21:17.349260 [DATLAT]
8606 22:21:17.352318 Freq=1600, CH1 RK0
8607 22:21:17.352391
8608 22:21:17.352459 DATLAT Default: 0xf
8609 22:21:17.355465 0, 0xFFFF, sum = 0
8610 22:21:17.355537 1, 0xFFFF, sum = 0
8611 22:21:17.359205 2, 0xFFFF, sum = 0
8612 22:21:17.359309 3, 0xFFFF, sum = 0
8613 22:21:17.361932 4, 0xFFFF, sum = 0
8614 22:21:17.365689 5, 0xFFFF, sum = 0
8615 22:21:17.365793 6, 0xFFFF, sum = 0
8616 22:21:17.368816 7, 0xFFFF, sum = 0
8617 22:21:17.368919 8, 0xFFFF, sum = 0
8618 22:21:17.371927 9, 0xFFFF, sum = 0
8619 22:21:17.372006 10, 0xFFFF, sum = 0
8620 22:21:17.375736 11, 0xFFFF, sum = 0
8621 22:21:17.375844 12, 0xFFFF, sum = 0
8622 22:21:17.378952 13, 0x8FFF, sum = 0
8623 22:21:17.379035 14, 0x0, sum = 1
8624 22:21:17.382195 15, 0x0, sum = 2
8625 22:21:17.382268 16, 0x0, sum = 3
8626 22:21:17.385685 17, 0x0, sum = 4
8627 22:21:17.385762 best_step = 15
8628 22:21:17.385831
8629 22:21:17.385892 ==
8630 22:21:17.388656 Dram Type= 6, Freq= 0, CH_1, rank 0
8631 22:21:17.394971 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8632 22:21:17.395057 ==
8633 22:21:17.395121 RX Vref Scan: 1
8634 22:21:17.395180
8635 22:21:17.398791 Set Vref Range= 24 -> 127
8636 22:21:17.398914
8637 22:21:17.401920 RX Vref 24 -> 127, step: 1
8638 22:21:17.402021
8639 22:21:17.402114 RX Delay 11 -> 252, step: 4
8640 22:21:17.402200
8641 22:21:17.405401 Set Vref, RX VrefLevel [Byte0]: 24
8642 22:21:17.408469 [Byte1]: 24
8643 22:21:17.412762
8644 22:21:17.412847 Set Vref, RX VrefLevel [Byte0]: 25
8645 22:21:17.415704 [Byte1]: 25
8646 22:21:17.419882
8647 22:21:17.419962 Set Vref, RX VrefLevel [Byte0]: 26
8648 22:21:17.423394 [Byte1]: 26
8649 22:21:17.427486
8650 22:21:17.427587 Set Vref, RX VrefLevel [Byte0]: 27
8651 22:21:17.431127 [Byte1]: 27
8652 22:21:17.435482
8653 22:21:17.435553 Set Vref, RX VrefLevel [Byte0]: 28
8654 22:21:17.438486 [Byte1]: 28
8655 22:21:17.442642
8656 22:21:17.442717 Set Vref, RX VrefLevel [Byte0]: 29
8657 22:21:17.446309 [Byte1]: 29
8658 22:21:17.450212
8659 22:21:17.450288 Set Vref, RX VrefLevel [Byte0]: 30
8660 22:21:17.453953 [Byte1]: 30
8661 22:21:17.457836
8662 22:21:17.457912 Set Vref, RX VrefLevel [Byte0]: 31
8663 22:21:17.461126 [Byte1]: 31
8664 22:21:17.465833
8665 22:21:17.465908 Set Vref, RX VrefLevel [Byte0]: 32
8666 22:21:17.468928 [Byte1]: 32
8667 22:21:17.473259
8668 22:21:17.473336 Set Vref, RX VrefLevel [Byte0]: 33
8669 22:21:17.476377 [Byte1]: 33
8670 22:21:17.480955
8671 22:21:17.481049 Set Vref, RX VrefLevel [Byte0]: 34
8672 22:21:17.484467 [Byte1]: 34
8673 22:21:17.488324
8674 22:21:17.488401 Set Vref, RX VrefLevel [Byte0]: 35
8675 22:21:17.491634 [Byte1]: 35
8676 22:21:17.495878
8677 22:21:17.495980 Set Vref, RX VrefLevel [Byte0]: 36
8678 22:21:17.502339 [Byte1]: 36
8679 22:21:17.502446
8680 22:21:17.505652 Set Vref, RX VrefLevel [Byte0]: 37
8681 22:21:17.509382 [Byte1]: 37
8682 22:21:17.509484
8683 22:21:17.512441 Set Vref, RX VrefLevel [Byte0]: 38
8684 22:21:17.515428 [Byte1]: 38
8685 22:21:17.519173
8686 22:21:17.519282 Set Vref, RX VrefLevel [Byte0]: 39
8687 22:21:17.522108 [Byte1]: 39
8688 22:21:17.526312
8689 22:21:17.526390 Set Vref, RX VrefLevel [Byte0]: 40
8690 22:21:17.529874 [Byte1]: 40
8691 22:21:17.533986
8692 22:21:17.534067 Set Vref, RX VrefLevel [Byte0]: 41
8693 22:21:17.537763 [Byte1]: 41
8694 22:21:17.542058
8695 22:21:17.542139 Set Vref, RX VrefLevel [Byte0]: 42
8696 22:21:17.544989 [Byte1]: 42
8697 22:21:17.549652
8698 22:21:17.549727 Set Vref, RX VrefLevel [Byte0]: 43
8699 22:21:17.552833 [Byte1]: 43
8700 22:21:17.557345
8701 22:21:17.557415 Set Vref, RX VrefLevel [Byte0]: 44
8702 22:21:17.560615 [Byte1]: 44
8703 22:21:17.564436
8704 22:21:17.564512 Set Vref, RX VrefLevel [Byte0]: 45
8705 22:21:17.567687 [Byte1]: 45
8706 22:21:17.572610
8707 22:21:17.572687 Set Vref, RX VrefLevel [Byte0]: 46
8708 22:21:17.575840 [Byte1]: 46
8709 22:21:17.579600
8710 22:21:17.579672 Set Vref, RX VrefLevel [Byte0]: 47
8711 22:21:17.583222 [Byte1]: 47
8712 22:21:17.587699
8713 22:21:17.587797 Set Vref, RX VrefLevel [Byte0]: 48
8714 22:21:17.590966 [Byte1]: 48
8715 22:21:17.594804
8716 22:21:17.594940 Set Vref, RX VrefLevel [Byte0]: 49
8717 22:21:17.598602 [Byte1]: 49
8718 22:21:17.602985
8719 22:21:17.603062 Set Vref, RX VrefLevel [Byte0]: 50
8720 22:21:17.606178 [Byte1]: 50
8721 22:21:17.610055
8722 22:21:17.610134 Set Vref, RX VrefLevel [Byte0]: 51
8723 22:21:17.613730 [Byte1]: 51
8724 22:21:17.618076
8725 22:21:17.618152 Set Vref, RX VrefLevel [Byte0]: 52
8726 22:21:17.621103 [Byte1]: 52
8727 22:21:17.625983
8728 22:21:17.626063 Set Vref, RX VrefLevel [Byte0]: 53
8729 22:21:17.628699 [Byte1]: 53
8730 22:21:17.633342
8731 22:21:17.633447 Set Vref, RX VrefLevel [Byte0]: 54
8732 22:21:17.636354 [Byte1]: 54
8733 22:21:17.641257
8734 22:21:17.641339 Set Vref, RX VrefLevel [Byte0]: 55
8735 22:21:17.644053 [Byte1]: 55
8736 22:21:17.648326
8737 22:21:17.648405 Set Vref, RX VrefLevel [Byte0]: 56
8738 22:21:17.652003 [Byte1]: 56
8739 22:21:17.656079
8740 22:21:17.656186 Set Vref, RX VrefLevel [Byte0]: 57
8741 22:21:17.659305 [Byte1]: 57
8742 22:21:17.663911
8743 22:21:17.663982 Set Vref, RX VrefLevel [Byte0]: 58
8744 22:21:17.667002 [Byte1]: 58
8745 22:21:17.671517
8746 22:21:17.671596 Set Vref, RX VrefLevel [Byte0]: 59
8747 22:21:17.674697 [Byte1]: 59
8748 22:21:17.679054
8749 22:21:17.679125 Set Vref, RX VrefLevel [Byte0]: 60
8750 22:21:17.682212 [Byte1]: 60
8751 22:21:17.686645
8752 22:21:17.686745 Set Vref, RX VrefLevel [Byte0]: 61
8753 22:21:17.689503 [Byte1]: 61
8754 22:21:17.693934
8755 22:21:17.694014 Set Vref, RX VrefLevel [Byte0]: 62
8756 22:21:17.700474 [Byte1]: 62
8757 22:21:17.700577
8758 22:21:17.704151 Set Vref, RX VrefLevel [Byte0]: 63
8759 22:21:17.707342 [Byte1]: 63
8760 22:21:17.707441
8761 22:21:17.710548 Set Vref, RX VrefLevel [Byte0]: 64
8762 22:21:17.713774 [Byte1]: 64
8763 22:21:17.716851
8764 22:21:17.716957 Set Vref, RX VrefLevel [Byte0]: 65
8765 22:21:17.719907 [Byte1]: 65
8766 22:21:17.724386
8767 22:21:17.724495 Set Vref, RX VrefLevel [Byte0]: 66
8768 22:21:17.728126 [Byte1]: 66
8769 22:21:17.732342
8770 22:21:17.732443 Set Vref, RX VrefLevel [Byte0]: 67
8771 22:21:17.735282 [Byte1]: 67
8772 22:21:17.740007
8773 22:21:17.740110 Set Vref, RX VrefLevel [Byte0]: 68
8774 22:21:17.742989 [Byte1]: 68
8775 22:21:17.747600
8776 22:21:17.747685 Set Vref, RX VrefLevel [Byte0]: 69
8777 22:21:17.750687 [Byte1]: 69
8778 22:21:17.754775
8779 22:21:17.754887 Set Vref, RX VrefLevel [Byte0]: 70
8780 22:21:17.758465 [Byte1]: 70
8781 22:21:17.762687
8782 22:21:17.762784 Set Vref, RX VrefLevel [Byte0]: 71
8783 22:21:17.766085 [Byte1]: 71
8784 22:21:17.770293
8785 22:21:17.770393 Set Vref, RX VrefLevel [Byte0]: 72
8786 22:21:17.773450 [Byte1]: 72
8787 22:21:17.777879
8788 22:21:17.777978 Final RX Vref Byte 0 = 56 to rank0
8789 22:21:17.780842 Final RX Vref Byte 1 = 54 to rank0
8790 22:21:17.784672 Final RX Vref Byte 0 = 56 to rank1
8791 22:21:17.787862 Final RX Vref Byte 1 = 54 to rank1==
8792 22:21:17.790979 Dram Type= 6, Freq= 0, CH_1, rank 0
8793 22:21:17.797241 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8794 22:21:17.797344 ==
8795 22:21:17.797440 DQS Delay:
8796 22:21:17.801057 DQS0 = 0, DQS1 = 0
8797 22:21:17.801154 DQM Delay:
8798 22:21:17.801248 DQM0 = 131, DQM1 = 123
8799 22:21:17.804679 DQ Delay:
8800 22:21:17.807656 DQ0 =134, DQ1 =126, DQ2 =120, DQ3 =130
8801 22:21:17.810938 DQ4 =126, DQ5 =142, DQ6 =142, DQ7 =128
8802 22:21:17.814195 DQ8 =110, DQ9 =114, DQ10 =122, DQ11 =116
8803 22:21:17.817347 DQ12 =132, DQ13 =132, DQ14 =132, DQ15 =132
8804 22:21:17.817443
8805 22:21:17.817535
8806 22:21:17.817622
8807 22:21:17.820474 [DramC_TX_OE_Calibration] TA2
8808 22:21:17.824214 Original DQ_B0 (3 6) =30, OEN = 27
8809 22:21:17.827422 Original DQ_B1 (3 6) =30, OEN = 27
8810 22:21:17.830564 24, 0x0, End_B0=24 End_B1=24
8811 22:21:17.830670 25, 0x0, End_B0=25 End_B1=25
8812 22:21:17.833709 26, 0x0, End_B0=26 End_B1=26
8813 22:21:17.837258 27, 0x0, End_B0=27 End_B1=27
8814 22:21:17.840193 28, 0x0, End_B0=28 End_B1=28
8815 22:21:17.843688 29, 0x0, End_B0=29 End_B1=29
8816 22:21:17.843790 30, 0x0, End_B0=30 End_B1=30
8817 22:21:17.847000 31, 0x4141, End_B0=30 End_B1=30
8818 22:21:17.850328 Byte0 end_step=30 best_step=27
8819 22:21:17.853286 Byte1 end_step=30 best_step=27
8820 22:21:17.857257 Byte0 TX OE(2T, 0.5T) = (3, 3)
8821 22:21:17.860125 Byte1 TX OE(2T, 0.5T) = (3, 3)
8822 22:21:17.860199
8823 22:21:17.860261
8824 22:21:17.866569 [DQSOSCAuto] RK0, (LSB)MR18= 0x90e, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 405 ps
8825 22:21:17.870125 CH1 RK0: MR19=303, MR18=90E
8826 22:21:17.876557 CH1_RK0: MR19=0x303, MR18=0x90E, DQSOSC=402, MR23=63, INC=22, DEC=15
8827 22:21:17.876642
8828 22:21:17.879819 ----->DramcWriteLeveling(PI) begin...
8829 22:21:17.879903 ==
8830 22:21:17.883432 Dram Type= 6, Freq= 0, CH_1, rank 1
8831 22:21:17.886521 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8832 22:21:17.886603 ==
8833 22:21:17.889804 Write leveling (Byte 0): 25 => 25
8834 22:21:17.892953 Write leveling (Byte 1): 29 => 29
8835 22:21:17.896627 DramcWriteLeveling(PI) end<-----
8836 22:21:17.896709
8837 22:21:17.896773 ==
8838 22:21:17.899793 Dram Type= 6, Freq= 0, CH_1, rank 1
8839 22:21:17.903002 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8840 22:21:17.906312 ==
8841 22:21:17.906394 [Gating] SW mode calibration
8842 22:21:17.916378 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8843 22:21:17.919506 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8844 22:21:17.922665 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8845 22:21:17.928861 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8846 22:21:17.932031 1 4 8 | B1->B0 | 2323 3333 | 0 1 | (0 0) (1 1)
8847 22:21:17.935890 1 4 12 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
8848 22:21:17.942038 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8849 22:21:17.945747 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8850 22:21:17.948665 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8851 22:21:17.955163 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8852 22:21:17.958813 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8853 22:21:17.965146 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8854 22:21:17.968780 1 5 8 | B1->B0 | 3434 2929 | 1 1 | (1 1) (1 0)
8855 22:21:17.971752 1 5 12 | B1->B0 | 2424 2323 | 1 0 | (1 0) (0 0)
8856 22:21:17.978453 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8857 22:21:17.981751 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8858 22:21:17.984917 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8859 22:21:17.991703 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8860 22:21:17.994789 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8861 22:21:17.997936 1 6 4 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
8862 22:21:18.004807 1 6 8 | B1->B0 | 2424 4545 | 0 0 | (0 0) (0 0)
8863 22:21:18.008017 1 6 12 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
8864 22:21:18.011301 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8865 22:21:18.017490 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8866 22:21:18.021221 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8867 22:21:18.024564 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8868 22:21:18.030684 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8869 22:21:18.034384 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8870 22:21:18.037539 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8871 22:21:18.044203 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8872 22:21:18.047518 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8873 22:21:18.050502 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8874 22:21:18.057435 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8875 22:21:18.060416 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8876 22:21:18.063877 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8877 22:21:18.070760 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8878 22:21:18.073881 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8879 22:21:18.077044 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8880 22:21:18.083568 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8881 22:21:18.086727 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8882 22:21:18.090225 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8883 22:21:18.096806 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8884 22:21:18.100039 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8885 22:21:18.103686 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8886 22:21:18.109963 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8887 22:21:18.113172 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8888 22:21:18.116942 Total UI for P1: 0, mck2ui 16
8889 22:21:18.120052 best dqsien dly found for B0: ( 1, 9, 8)
8890 22:21:18.123455 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8891 22:21:18.126920 Total UI for P1: 0, mck2ui 16
8892 22:21:18.129862 best dqsien dly found for B1: ( 1, 9, 10)
8893 22:21:18.132977 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8894 22:21:18.136576 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8895 22:21:18.136658
8896 22:21:18.139700 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8897 22:21:18.146122 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8898 22:21:18.146205 [Gating] SW calibration Done
8899 22:21:18.149936 ==
8900 22:21:18.150019 Dram Type= 6, Freq= 0, CH_1, rank 1
8901 22:21:18.156079 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8902 22:21:18.156161 ==
8903 22:21:18.156226 RX Vref Scan: 0
8904 22:21:18.156287
8905 22:21:18.159558 RX Vref 0 -> 0, step: 1
8906 22:21:18.159639
8907 22:21:18.163107 RX Delay 0 -> 252, step: 8
8908 22:21:18.165999 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8909 22:21:18.169404 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8910 22:21:18.172927 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8911 22:21:18.179785 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8912 22:21:18.182940 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8913 22:21:18.186042 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8914 22:21:18.189142 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8915 22:21:18.192788 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8916 22:21:18.199324 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8917 22:21:18.202280 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8918 22:21:18.205473 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8919 22:21:18.209160 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8920 22:21:18.215666 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8921 22:21:18.218777 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8922 22:21:18.221966 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8923 22:21:18.225724 iDelay=200, Bit 15, Center 135 (72 ~ 199) 128
8924 22:21:18.225808 ==
8925 22:21:18.228911 Dram Type= 6, Freq= 0, CH_1, rank 1
8926 22:21:18.235436 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8927 22:21:18.235547 ==
8928 22:21:18.235656 DQS Delay:
8929 22:21:18.235748 DQS0 = 0, DQS1 = 0
8930 22:21:18.238307 DQM Delay:
8931 22:21:18.238408 DQM0 = 133, DQM1 = 127
8932 22:21:18.242156 DQ Delay:
8933 22:21:18.245376 DQ0 =135, DQ1 =131, DQ2 =119, DQ3 =131
8934 22:21:18.248561 DQ4 =131, DQ5 =143, DQ6 =143, DQ7 =131
8935 22:21:18.251949 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =123
8936 22:21:18.255257 DQ12 =131, DQ13 =139, DQ14 =131, DQ15 =135
8937 22:21:18.255372
8938 22:21:18.255467
8939 22:21:18.255565 ==
8940 22:21:18.258381 Dram Type= 6, Freq= 0, CH_1, rank 1
8941 22:21:18.262034 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8942 22:21:18.264861 ==
8943 22:21:18.264963
8944 22:21:18.265064
8945 22:21:18.265162 TX Vref Scan disable
8946 22:21:18.268033 == TX Byte 0 ==
8947 22:21:18.271401 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8948 22:21:18.274988 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8949 22:21:18.278419 == TX Byte 1 ==
8950 22:21:18.281316 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8951 22:21:18.288200 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8952 22:21:18.288283 ==
8953 22:21:18.291352 Dram Type= 6, Freq= 0, CH_1, rank 1
8954 22:21:18.294434 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8955 22:21:18.294521 ==
8956 22:21:18.307345
8957 22:21:18.310373 TX Vref early break, caculate TX vref
8958 22:21:18.314064 TX Vref=16, minBit 8, minWin=22, winSum=381
8959 22:21:18.317376 TX Vref=18, minBit 0, minWin=23, winSum=387
8960 22:21:18.320542 TX Vref=20, minBit 0, minWin=23, winSum=396
8961 22:21:18.323732 TX Vref=22, minBit 8, minWin=23, winSum=402
8962 22:21:18.326809 TX Vref=24, minBit 0, minWin=24, winSum=412
8963 22:21:18.333818 TX Vref=26, minBit 0, minWin=25, winSum=418
8964 22:21:18.337005 TX Vref=28, minBit 5, minWin=25, winSum=422
8965 22:21:18.340180 TX Vref=30, minBit 8, minWin=24, winSum=416
8966 22:21:18.343881 TX Vref=32, minBit 1, minWin=24, winSum=407
8967 22:21:18.347019 TX Vref=34, minBit 5, minWin=23, winSum=398
8968 22:21:18.353600 [TxChooseVref] Worse bit 5, Min win 25, Win sum 422, Final Vref 28
8969 22:21:18.353677
8970 22:21:18.356686 Final TX Range 0 Vref 28
8971 22:21:18.356761
8972 22:21:18.356823 ==
8973 22:21:18.359923 Dram Type= 6, Freq= 0, CH_1, rank 1
8974 22:21:18.363188 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8975 22:21:18.363272 ==
8976 22:21:18.363336
8977 22:21:18.363394
8978 22:21:18.366814 TX Vref Scan disable
8979 22:21:18.373184 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8980 22:21:18.373279 == TX Byte 0 ==
8981 22:21:18.376777 u2DelayCellOfst[0]=15 cells (4 PI)
8982 22:21:18.379678 u2DelayCellOfst[1]=15 cells (4 PI)
8983 22:21:18.383233 u2DelayCellOfst[2]=0 cells (0 PI)
8984 22:21:18.386203 u2DelayCellOfst[3]=3 cells (1 PI)
8985 22:21:18.389764 u2DelayCellOfst[4]=7 cells (2 PI)
8986 22:21:18.392515 u2DelayCellOfst[5]=18 cells (5 PI)
8987 22:21:18.396092 u2DelayCellOfst[6]=18 cells (5 PI)
8988 22:21:18.400027 u2DelayCellOfst[7]=7 cells (2 PI)
8989 22:21:18.402965 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8990 22:21:18.406009 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8991 22:21:18.409342 == TX Byte 1 ==
8992 22:21:18.412439 u2DelayCellOfst[8]=0 cells (0 PI)
8993 22:21:18.416023 u2DelayCellOfst[9]=7 cells (2 PI)
8994 22:21:18.419026 u2DelayCellOfst[10]=15 cells (4 PI)
8995 22:21:18.419109 u2DelayCellOfst[11]=7 cells (2 PI)
8996 22:21:18.422210 u2DelayCellOfst[12]=15 cells (4 PI)
8997 22:21:18.425439 u2DelayCellOfst[13]=18 cells (5 PI)
8998 22:21:18.429110 u2DelayCellOfst[14]=22 cells (6 PI)
8999 22:21:18.432119 u2DelayCellOfst[15]=18 cells (5 PI)
9000 22:21:18.438533 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
9001 22:21:18.441826 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
9002 22:21:18.441908 DramC Write-DBI on
9003 22:21:18.445697 ==
9004 22:21:18.448747 Dram Type= 6, Freq= 0, CH_1, rank 1
9005 22:21:18.451932 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9006 22:21:18.452012 ==
9007 22:21:18.452081
9008 22:21:18.452145
9009 22:21:18.455167 TX Vref Scan disable
9010 22:21:18.455249 == TX Byte 0 ==
9011 22:21:18.461539 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
9012 22:21:18.461615 == TX Byte 1 ==
9013 22:21:18.464825 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
9014 22:21:18.468581 DramC Write-DBI off
9015 22:21:18.468659
9016 22:21:18.468722 [DATLAT]
9017 22:21:18.471701 Freq=1600, CH1 RK1
9018 22:21:18.471805
9019 22:21:18.471913 DATLAT Default: 0xf
9020 22:21:18.475049 0, 0xFFFF, sum = 0
9021 22:21:18.475135 1, 0xFFFF, sum = 0
9022 22:21:18.478197 2, 0xFFFF, sum = 0
9023 22:21:18.478281 3, 0xFFFF, sum = 0
9024 22:21:18.481299 4, 0xFFFF, sum = 0
9025 22:21:18.484876 5, 0xFFFF, sum = 0
9026 22:21:18.484960 6, 0xFFFF, sum = 0
9027 22:21:18.488530 7, 0xFFFF, sum = 0
9028 22:21:18.488615 8, 0xFFFF, sum = 0
9029 22:21:18.491450 9, 0xFFFF, sum = 0
9030 22:21:18.491534 10, 0xFFFF, sum = 0
9031 22:21:18.495053 11, 0xFFFF, sum = 0
9032 22:21:18.495143 12, 0xFFFF, sum = 0
9033 22:21:18.498153 13, 0x8FFF, sum = 0
9034 22:21:18.498236 14, 0x0, sum = 1
9035 22:21:18.501185 15, 0x0, sum = 2
9036 22:21:18.501268 16, 0x0, sum = 3
9037 22:21:18.504623 17, 0x0, sum = 4
9038 22:21:18.504746 best_step = 15
9039 22:21:18.504829
9040 22:21:18.504890 ==
9041 22:21:18.507779 Dram Type= 6, Freq= 0, CH_1, rank 1
9042 22:21:18.514435 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9043 22:21:18.514520 ==
9044 22:21:18.514586 RX Vref Scan: 0
9045 22:21:18.514647
9046 22:21:18.517394 RX Vref 0 -> 0, step: 1
9047 22:21:18.517477
9048 22:21:18.520802 RX Delay 11 -> 252, step: 4
9049 22:21:18.524245 iDelay=195, Bit 0, Center 134 (83 ~ 186) 104
9050 22:21:18.527183 iDelay=195, Bit 1, Center 128 (79 ~ 178) 100
9051 22:21:18.531267 iDelay=195, Bit 2, Center 118 (67 ~ 170) 104
9052 22:21:18.537237 iDelay=195, Bit 3, Center 124 (71 ~ 178) 108
9053 22:21:18.540477 iDelay=195, Bit 4, Center 126 (71 ~ 182) 112
9054 22:21:18.543810 iDelay=195, Bit 5, Center 142 (91 ~ 194) 104
9055 22:21:18.546903 iDelay=195, Bit 6, Center 140 (87 ~ 194) 108
9056 22:21:18.553729 iDelay=195, Bit 7, Center 124 (71 ~ 178) 108
9057 22:21:18.556895 iDelay=195, Bit 8, Center 112 (55 ~ 170) 116
9058 22:21:18.560174 iDelay=195, Bit 9, Center 114 (63 ~ 166) 104
9059 22:21:18.563431 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
9060 22:21:18.567305 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
9061 22:21:18.573486 iDelay=195, Bit 12, Center 132 (79 ~ 186) 108
9062 22:21:18.576575 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
9063 22:21:18.580489 iDelay=195, Bit 14, Center 130 (75 ~ 186) 112
9064 22:21:18.583649 iDelay=195, Bit 15, Center 134 (79 ~ 190) 112
9065 22:21:18.583732 ==
9066 22:21:18.586814 Dram Type= 6, Freq= 0, CH_1, rank 1
9067 22:21:18.593088 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9068 22:21:18.593171 ==
9069 22:21:18.593254 DQS Delay:
9070 22:21:18.596679 DQS0 = 0, DQS1 = 0
9071 22:21:18.596788 DQM Delay:
9072 22:21:18.600218 DQM0 = 129, DQM1 = 125
9073 22:21:18.600307 DQ Delay:
9074 22:21:18.603385 DQ0 =134, DQ1 =128, DQ2 =118, DQ3 =124
9075 22:21:18.606412 DQ4 =126, DQ5 =142, DQ6 =140, DQ7 =124
9076 22:21:18.609865 DQ8 =112, DQ9 =114, DQ10 =128, DQ11 =120
9077 22:21:18.612820 DQ12 =132, DQ13 =132, DQ14 =130, DQ15 =134
9078 22:21:18.612902
9079 22:21:18.612967
9080 22:21:18.613029
9081 22:21:18.616455 [DramC_TX_OE_Calibration] TA2
9082 22:21:18.619507 Original DQ_B0 (3 6) =30, OEN = 27
9083 22:21:18.622537 Original DQ_B1 (3 6) =30, OEN = 27
9084 22:21:18.626125 24, 0x0, End_B0=24 End_B1=24
9085 22:21:18.629224 25, 0x0, End_B0=25 End_B1=25
9086 22:21:18.629308 26, 0x0, End_B0=26 End_B1=26
9087 22:21:18.632759 27, 0x0, End_B0=27 End_B1=27
9088 22:21:18.635733 28, 0x0, End_B0=28 End_B1=28
9089 22:21:18.639551 29, 0x0, End_B0=29 End_B1=29
9090 22:21:18.642539 30, 0x0, End_B0=30 End_B1=30
9091 22:21:18.642681 31, 0x4141, End_B0=30 End_B1=30
9092 22:21:18.645763 Byte0 end_step=30 best_step=27
9093 22:21:18.648904 Byte1 end_step=30 best_step=27
9094 22:21:18.652768 Byte0 TX OE(2T, 0.5T) = (3, 3)
9095 22:21:18.655803 Byte1 TX OE(2T, 0.5T) = (3, 3)
9096 22:21:18.655886
9097 22:21:18.655951
9098 22:21:18.662015 [DQSOSCAuto] RK1, (LSB)MR18= 0x121d, (MSB)MR19= 0x303, tDQSOscB0 = 395 ps tDQSOscB1 = 400 ps
9099 22:21:18.665318 CH1 RK1: MR19=303, MR18=121D
9100 22:21:18.672299 CH1_RK1: MR19=0x303, MR18=0x121D, DQSOSC=395, MR23=63, INC=23, DEC=15
9101 22:21:18.675408 [RxdqsGatingPostProcess] freq 1600
9102 22:21:18.681713 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9103 22:21:18.684886 best DQS0 dly(2T, 0.5T) = (1, 1)
9104 22:21:18.684969 best DQS1 dly(2T, 0.5T) = (1, 1)
9105 22:21:18.691234 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9106 22:21:18.691318 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9107 22:21:18.694933 best DQS0 dly(2T, 0.5T) = (1, 1)
9108 22:21:18.697982 best DQS1 dly(2T, 0.5T) = (1, 1)
9109 22:21:18.701378 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9110 22:21:18.704836 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9111 22:21:18.707841 Pre-setting of DQS Precalculation
9112 22:21:18.715112 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9113 22:21:18.721413 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9114 22:21:18.727993 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9115 22:21:18.728103
9116 22:21:18.728196
9117 22:21:18.731118 [Calibration Summary] 3200 Mbps
9118 22:21:18.731227 CH 0, Rank 0
9119 22:21:18.734737 SW Impedance : PASS
9120 22:21:18.737753 DUTY Scan : NO K
9121 22:21:18.737836 ZQ Calibration : PASS
9122 22:21:18.741291 Jitter Meter : NO K
9123 22:21:18.744202 CBT Training : PASS
9124 22:21:18.744285 Write leveling : PASS
9125 22:21:18.747850 RX DQS gating : PASS
9126 22:21:18.750937 RX DQ/DQS(RDDQC) : PASS
9127 22:21:18.751020 TX DQ/DQS : PASS
9128 22:21:18.754169 RX DATLAT : PASS
9129 22:21:18.757370 RX DQ/DQS(Engine): PASS
9130 22:21:18.757453 TX OE : PASS
9131 22:21:18.757519 All Pass.
9132 22:21:18.757580
9133 22:21:18.760967 CH 0, Rank 1
9134 22:21:18.764149 SW Impedance : PASS
9135 22:21:18.764274 DUTY Scan : NO K
9136 22:21:18.767329 ZQ Calibration : PASS
9137 22:21:18.767411 Jitter Meter : NO K
9138 22:21:18.770472 CBT Training : PASS
9139 22:21:18.773696 Write leveling : PASS
9140 22:21:18.773780 RX DQS gating : PASS
9141 22:21:18.776902 RX DQ/DQS(RDDQC) : PASS
9142 22:21:18.780676 TX DQ/DQS : PASS
9143 22:21:18.780759 RX DATLAT : PASS
9144 22:21:18.783700 RX DQ/DQS(Engine): PASS
9145 22:21:18.786930 TX OE : PASS
9146 22:21:18.787030 All Pass.
9147 22:21:18.787127
9148 22:21:18.787204 CH 1, Rank 0
9149 22:21:18.790730 SW Impedance : PASS
9150 22:21:18.793908 DUTY Scan : NO K
9151 22:21:18.794007 ZQ Calibration : PASS
9152 22:21:18.796926 Jitter Meter : NO K
9153 22:21:18.800175 CBT Training : PASS
9154 22:21:18.800258 Write leveling : PASS
9155 22:21:18.803374 RX DQS gating : PASS
9156 22:21:18.807039 RX DQ/DQS(RDDQC) : PASS
9157 22:21:18.807122 TX DQ/DQS : PASS
9158 22:21:18.810155 RX DATLAT : PASS
9159 22:21:18.813318 RX DQ/DQS(Engine): PASS
9160 22:21:18.813401 TX OE : PASS
9161 22:21:18.817200 All Pass.
9162 22:21:18.817282
9163 22:21:18.817347 CH 1, Rank 1
9164 22:21:18.820099 SW Impedance : PASS
9165 22:21:18.820182 DUTY Scan : NO K
9166 22:21:18.823502 ZQ Calibration : PASS
9167 22:21:18.826373 Jitter Meter : NO K
9168 22:21:18.826471 CBT Training : PASS
9169 22:21:18.829851 Write leveling : PASS
9170 22:21:18.832907 RX DQS gating : PASS
9171 22:21:18.832989 RX DQ/DQS(RDDQC) : PASS
9172 22:21:18.836678 TX DQ/DQS : PASS
9173 22:21:18.839750 RX DATLAT : PASS
9174 22:21:18.839832 RX DQ/DQS(Engine): PASS
9175 22:21:18.842789 TX OE : PASS
9176 22:21:18.842905 All Pass.
9177 22:21:18.843009
9178 22:21:18.846319 DramC Write-DBI on
9179 22:21:18.849244 PER_BANK_REFRESH: Hybrid Mode
9180 22:21:18.849327 TX_TRACKING: ON
9181 22:21:18.859668 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9182 22:21:18.865797 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9183 22:21:18.872756 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9184 22:21:18.875960 [FAST_K] Save calibration result to emmc
9185 22:21:18.879100 sync common calibartion params.
9186 22:21:18.883054 sync cbt_mode0:1, 1:1
9187 22:21:18.886035 dram_init: ddr_geometry: 2
9188 22:21:18.886118 dram_init: ddr_geometry: 2
9189 22:21:18.889226 dram_init: ddr_geometry: 2
9190 22:21:18.892377 0:dram_rank_size:100000000
9191 22:21:18.895641 1:dram_rank_size:100000000
9192 22:21:18.899340 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9193 22:21:18.902481 DFS_SHUFFLE_HW_MODE: ON
9194 22:21:18.905931 dramc_set_vcore_voltage set vcore to 725000
9195 22:21:18.908788 Read voltage for 1600, 0
9196 22:21:18.908871 Vio18 = 0
9197 22:21:18.908937 Vcore = 725000
9198 22:21:18.912424 Vdram = 0
9199 22:21:18.912507 Vddq = 0
9200 22:21:18.912572 Vmddr = 0
9201 22:21:18.915465 switch to 3200 Mbps bootup
9202 22:21:18.918632 [DramcRunTimeConfig]
9203 22:21:18.918714 PHYPLL
9204 22:21:18.918780 DPM_CONTROL_AFTERK: ON
9205 22:21:18.922337 PER_BANK_REFRESH: ON
9206 22:21:18.925398 REFRESH_OVERHEAD_REDUCTION: ON
9207 22:21:18.925481 CMD_PICG_NEW_MODE: OFF
9208 22:21:18.929023 XRTWTW_NEW_MODE: ON
9209 22:21:18.931904 XRTRTR_NEW_MODE: ON
9210 22:21:18.932004 TX_TRACKING: ON
9211 22:21:18.935289 RDSEL_TRACKING: OFF
9212 22:21:18.935398 DQS Precalculation for DVFS: ON
9213 22:21:18.938385 RX_TRACKING: OFF
9214 22:21:18.938483 HW_GATING DBG: ON
9215 22:21:18.942064 ZQCS_ENABLE_LP4: ON
9216 22:21:18.945037 RX_PICG_NEW_MODE: ON
9217 22:21:18.945150 TX_PICG_NEW_MODE: ON
9218 22:21:18.948602 ENABLE_RX_DCM_DPHY: ON
9219 22:21:18.951592 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9220 22:21:18.951675 DUMMY_READ_FOR_TRACKING: OFF
9221 22:21:18.955099 !!! SPM_CONTROL_AFTERK: OFF
9222 22:21:18.958710 !!! SPM could not control APHY
9223 22:21:18.961670 IMPEDANCE_TRACKING: ON
9224 22:21:18.961753 TEMP_SENSOR: ON
9225 22:21:18.964889 HW_SAVE_FOR_SR: OFF
9226 22:21:18.967970 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9227 22:21:18.971742 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9228 22:21:18.971825 Read ODT Tracking: ON
9229 22:21:18.975272 Refresh Rate DeBounce: ON
9230 22:21:18.978262 DFS_NO_QUEUE_FLUSH: ON
9231 22:21:18.981439 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9232 22:21:18.981537 ENABLE_DFS_RUNTIME_MRW: OFF
9233 22:21:18.984706 DDR_RESERVE_NEW_MODE: ON
9234 22:21:18.987868 MR_CBT_SWITCH_FREQ: ON
9235 22:21:18.987950 =========================
9236 22:21:19.007871 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9237 22:21:19.011570 dram_init: ddr_geometry: 2
9238 22:21:19.029981 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9239 22:21:19.032863 dram_init: dram init end (result: 0)
9240 22:21:19.039352 DRAM-K: Full calibration passed in 24606 msecs
9241 22:21:19.042988 MRC: failed to locate region type 0.
9242 22:21:19.043071 DRAM rank0 size:0x100000000,
9243 22:21:19.045993 DRAM rank1 size=0x100000000
9244 22:21:19.056430 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9245 22:21:19.062375 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9246 22:21:19.069043 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9247 22:21:19.079176 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9248 22:21:19.079305 DRAM rank0 size:0x100000000,
9249 22:21:19.082408 DRAM rank1 size=0x100000000
9250 22:21:19.082507 CBMEM:
9251 22:21:19.085625 IMD: root @ 0xfffff000 254 entries.
9252 22:21:19.088878 IMD: root @ 0xffffec00 62 entries.
9253 22:21:19.092068 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9254 22:21:19.098936 WARNING: RO_VPD is uninitialized or empty.
9255 22:21:19.102140 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9256 22:21:19.109898 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9257 22:21:19.122277 read SPI 0x42894 0xe01e: 6227 us, 9213 KB/s, 73.704 Mbps
9258 22:21:19.133745 BS: romstage times (exec / console): total (unknown) / 24068 ms
9259 22:21:19.133852
9260 22:21:19.133939
9261 22:21:19.143520 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9262 22:21:19.146750 ARM64: Exception handlers installed.
9263 22:21:19.149726 ARM64: Testing exception
9264 22:21:19.153373 ARM64: Done test exception
9265 22:21:19.153475 Enumerating buses...
9266 22:21:19.156446 Show all devs... Before device enumeration.
9267 22:21:19.159974 Root Device: enabled 1
9268 22:21:19.163603 CPU_CLUSTER: 0: enabled 1
9269 22:21:19.163707 CPU: 00: enabled 1
9270 22:21:19.166470 Compare with tree...
9271 22:21:19.166610 Root Device: enabled 1
9272 22:21:19.169592 CPU_CLUSTER: 0: enabled 1
9273 22:21:19.173156 CPU: 00: enabled 1
9274 22:21:19.173313 Root Device scanning...
9275 22:21:19.176831 scan_static_bus for Root Device
9276 22:21:19.180020 CPU_CLUSTER: 0 enabled
9277 22:21:19.183319 scan_static_bus for Root Device done
9278 22:21:19.186546 scan_bus: bus Root Device finished in 8 msecs
9279 22:21:19.186646 done
9280 22:21:19.192907 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9281 22:21:19.196073 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9282 22:21:19.202819 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9283 22:21:19.209227 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9284 22:21:19.209329 Allocating resources...
9285 22:21:19.212332 Reading resources...
9286 22:21:19.215806 Root Device read_resources bus 0 link: 0
9287 22:21:19.219030 DRAM rank0 size:0x100000000,
9288 22:21:19.219134 DRAM rank1 size=0x100000000
9289 22:21:19.225811 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9290 22:21:19.225911 CPU: 00 missing read_resources
9291 22:21:19.232620 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9292 22:21:19.235948 Root Device read_resources bus 0 link: 0 done
9293 22:21:19.239157 Done reading resources.
9294 22:21:19.242272 Show resources in subtree (Root Device)...After reading.
9295 22:21:19.245813 Root Device child on link 0 CPU_CLUSTER: 0
9296 22:21:19.248858 CPU_CLUSTER: 0 child on link 0 CPU: 00
9297 22:21:19.258991 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9298 22:21:19.259093 CPU: 00
9299 22:21:19.264995 Root Device assign_resources, bus 0 link: 0
9300 22:21:19.268483 CPU_CLUSTER: 0 missing set_resources
9301 22:21:19.271968 Root Device assign_resources, bus 0 link: 0 done
9302 22:21:19.274976 Done setting resources.
9303 22:21:19.278544 Show resources in subtree (Root Device)...After assigning values.
9304 22:21:19.281510 Root Device child on link 0 CPU_CLUSTER: 0
9305 22:21:19.288360 CPU_CLUSTER: 0 child on link 0 CPU: 00
9306 22:21:19.294754 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9307 22:21:19.297992 CPU: 00
9308 22:21:19.298089 Done allocating resources.
9309 22:21:19.304805 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9310 22:21:19.304912 Enabling resources...
9311 22:21:19.307997 done.
9312 22:21:19.311268 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9313 22:21:19.314416 Initializing devices...
9314 22:21:19.314499 Root Device init
9315 22:21:19.317917 init hardware done!
9316 22:21:19.321010 0x00000018: ctrlr->caps
9317 22:21:19.321095 52.000 MHz: ctrlr->f_max
9318 22:21:19.324867 0.400 MHz: ctrlr->f_min
9319 22:21:19.327888 0x40ff8080: ctrlr->voltages
9320 22:21:19.327973 sclk: 390625
9321 22:21:19.328039 Bus Width = 1
9322 22:21:19.331080 sclk: 390625
9323 22:21:19.331163 Bus Width = 1
9324 22:21:19.334170 Early init status = 3
9325 22:21:19.337362 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9326 22:21:19.341425 in-header: 03 fc 00 00 01 00 00 00
9327 22:21:19.344522 in-data: 00
9328 22:21:19.347695 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9329 22:21:19.352528 in-header: 03 fd 00 00 00 00 00 00
9330 22:21:19.355607 in-data:
9331 22:21:19.359160 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9332 22:21:19.362235 in-header: 03 fc 00 00 01 00 00 00
9333 22:21:19.365924 in-data: 00
9334 22:21:19.369190 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9335 22:21:19.373528 in-header: 03 fd 00 00 00 00 00 00
9336 22:21:19.377045 in-data:
9337 22:21:19.380436 [SSUSB] Setting up USB HOST controller...
9338 22:21:19.383447 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9339 22:21:19.387171 [SSUSB] phy power-on done.
9340 22:21:19.389991 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9341 22:21:19.396943 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9342 22:21:19.400191 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9343 22:21:19.406473 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9344 22:21:19.413698 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9345 22:21:19.419836 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9346 22:21:19.426605 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9347 22:21:19.432912 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9348 22:21:19.436109 SPM: binary array size = 0x9dc
9349 22:21:19.439798 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9350 22:21:19.446175 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9351 22:21:19.453055 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9352 22:21:19.459189 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9353 22:21:19.462861 configure_display: Starting display init
9354 22:21:19.497049 anx7625_power_on_init: Init interface.
9355 22:21:19.500480 anx7625_disable_pd_protocol: Disabled PD feature.
9356 22:21:19.503766 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9357 22:21:19.531249 anx7625_start_dp_work: Secure OCM version=00
9358 22:21:19.534393 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9359 22:21:19.549664 sp_tx_get_edid_block: EDID Block = 1
9360 22:21:19.652342 Extracted contents:
9361 22:21:19.655526 header: 00 ff ff ff ff ff ff 00
9362 22:21:19.658722 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9363 22:21:19.661832 version: 01 04
9364 22:21:19.665358 basic params: 95 1f 11 78 0a
9365 22:21:19.668870 chroma info: 76 90 94 55 54 90 27 21 50 54
9366 22:21:19.671611 established: 00 00 00
9367 22:21:19.678109 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9368 22:21:19.684931 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9369 22:21:19.688140 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9370 22:21:19.695024 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9371 22:21:19.701682 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9372 22:21:19.704569 extensions: 00
9373 22:21:19.704643 checksum: fb
9374 22:21:19.704706
9375 22:21:19.711093 Manufacturer: IVO Model 57d Serial Number 0
9376 22:21:19.711175 Made week 0 of 2020
9377 22:21:19.714688 EDID version: 1.4
9378 22:21:19.714769 Digital display
9379 22:21:19.717806 6 bits per primary color channel
9380 22:21:19.720856 DisplayPort interface
9381 22:21:19.720937 Maximum image size: 31 cm x 17 cm
9382 22:21:19.724549 Gamma: 220%
9383 22:21:19.724631 Check DPMS levels
9384 22:21:19.731038 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9385 22:21:19.734214 First detailed timing is preferred timing
9386 22:21:19.737339 Established timings supported:
9387 22:21:19.737421 Standard timings supported:
9388 22:21:19.740985 Detailed timings
9389 22:21:19.744179 Hex of detail: 383680a07038204018303c0035ae10000019
9390 22:21:19.751074 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9391 22:21:19.754256 0780 0798 07c8 0820 hborder 0
9392 22:21:19.757516 0438 043b 0447 0458 vborder 0
9393 22:21:19.760591 -hsync -vsync
9394 22:21:19.760672 Did detailed timing
9395 22:21:19.767225 Hex of detail: 000000000000000000000000000000000000
9396 22:21:19.770293 Manufacturer-specified data, tag 0
9397 22:21:19.774008 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9398 22:21:19.777031 ASCII string: InfoVision
9399 22:21:19.780606 Hex of detail: 000000fe00523134304e574635205248200a
9400 22:21:19.783429 ASCII string: R140NWF5 RH
9401 22:21:19.783513 Checksum
9402 22:21:19.786801 Checksum: 0xfb (valid)
9403 22:21:19.790425 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9404 22:21:19.793465 DSI data_rate: 832800000 bps
9405 22:21:19.800322 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9406 22:21:19.803310 anx7625_parse_edid: pixelclock(138800).
9407 22:21:19.806580 hactive(1920), hsync(48), hfp(24), hbp(88)
9408 22:21:19.810068 vactive(1080), vsync(12), vfp(3), vbp(17)
9409 22:21:19.813044 anx7625_dsi_config: config dsi.
9410 22:21:19.820173 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9411 22:21:19.833970 anx7625_dsi_config: success to config DSI
9412 22:21:19.837730 anx7625_dp_start: MIPI phy setup OK.
9413 22:21:19.840769 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9414 22:21:19.843773 mtk_ddp_mode_set invalid vrefresh 60
9415 22:21:19.847434 main_disp_path_setup
9416 22:21:19.847574 ovl_layer_smi_id_en
9417 22:21:19.850620 ovl_layer_smi_id_en
9418 22:21:19.850752 ccorr_config
9419 22:21:19.850887 aal_config
9420 22:21:19.854252 gamma_config
9421 22:21:19.854380 postmask_config
9422 22:21:19.857382 dither_config
9423 22:21:19.860761 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9424 22:21:19.867143 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9425 22:21:19.870242 Root Device init finished in 551 msecs
9426 22:21:19.873441 CPU_CLUSTER: 0 init
9427 22:21:19.880478 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9428 22:21:19.883875 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9429 22:21:19.887357 APU_MBOX 0x190000b0 = 0x10001
9430 22:21:19.890002 APU_MBOX 0x190001b0 = 0x10001
9431 22:21:19.893519 APU_MBOX 0x190005b0 = 0x10001
9432 22:21:19.897062 APU_MBOX 0x190006b0 = 0x10001
9433 22:21:19.903344 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9434 22:21:19.912980 read SPI 0x539f4 0xe237: 6250 us, 9265 KB/s, 74.120 Mbps
9435 22:21:19.925350 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9436 22:21:19.931824 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9437 22:21:19.943728 read SPI 0x61c74 0xe8ef: 6413 us, 9298 KB/s, 74.384 Mbps
9438 22:21:19.952889 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9439 22:21:19.956085 CPU_CLUSTER: 0 init finished in 81 msecs
9440 22:21:19.959035 Devices initialized
9441 22:21:19.962796 Show all devs... After init.
9442 22:21:19.962919 Root Device: enabled 1
9443 22:21:19.965990 CPU_CLUSTER: 0: enabled 1
9444 22:21:19.969172 CPU: 00: enabled 1
9445 22:21:19.972341 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9446 22:21:19.975511 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9447 22:21:19.979289 ELOG: NV offset 0x57f000 size 0x1000
9448 22:21:19.985696 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9449 22:21:19.992466 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9450 22:21:19.996026 ELOG: Event(17) added with size 13 at 2023-06-05 22:21:24 UTC
9451 22:21:20.002722 out: cmd=0x121: 03 db 21 01 00 00 00 00
9452 22:21:20.005608 in-header: 03 35 00 00 2c 00 00 00
9453 22:21:20.015524 in-data: 29 69 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9454 22:21:20.022303 ELOG: Event(A1) added with size 10 at 2023-06-05 22:21:24 UTC
9455 22:21:20.028884 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9456 22:21:20.035345 ELOG: Event(A0) added with size 9 at 2023-06-05 22:21:24 UTC
9457 22:21:20.038359 elog_add_boot_reason: Logged dev mode boot
9458 22:21:20.045124 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9459 22:21:20.045202 Finalize devices...
9460 22:21:20.048320 Devices finalized
9461 22:21:20.051412 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9462 22:21:20.055321 Writing coreboot table at 0xffe64000
9463 22:21:20.058196 0. 000000000010a000-0000000000113fff: RAMSTAGE
9464 22:21:20.064946 1. 0000000040000000-00000000400fffff: RAM
9465 22:21:20.068118 2. 0000000040100000-000000004032afff: RAMSTAGE
9466 22:21:20.071292 3. 000000004032b000-00000000545fffff: RAM
9467 22:21:20.074596 4. 0000000054600000-000000005465ffff: BL31
9468 22:21:20.077799 5. 0000000054660000-00000000ffe63fff: RAM
9469 22:21:20.084174 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9470 22:21:20.087992 7. 0000000100000000-000000023fffffff: RAM
9471 22:21:20.090997 Passing 5 GPIOs to payload:
9472 22:21:20.094223 NAME | PORT | POLARITY | VALUE
9473 22:21:20.101027 EC in RW | 0x000000aa | low | undefined
9474 22:21:20.104633 EC interrupt | 0x00000005 | low | undefined
9475 22:21:20.110518 TPM interrupt | 0x000000ab | high | undefined
9476 22:21:20.114213 SD card detect | 0x00000011 | high | undefined
9477 22:21:20.117435 speaker enable | 0x00000093 | high | undefined
9478 22:21:20.120560 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9479 22:21:20.124076 in-header: 03 f9 00 00 02 00 00 00
9480 22:21:20.127747 in-data: 02 00
9481 22:21:20.130797 ADC[4]: Raw value=893341 ID=7
9482 22:21:20.134304 ADC[3]: Raw value=212700 ID=1
9483 22:21:20.134405 RAM Code: 0x71
9484 22:21:20.137441 ADC[6]: Raw value=74722 ID=0
9485 22:21:20.140819 ADC[5]: Raw value=212700 ID=1
9486 22:21:20.140890 SKU Code: 0x1
9487 22:21:20.147340 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 7dbf
9488 22:21:20.147425 coreboot table: 964 bytes.
9489 22:21:20.150478 IMD ROOT 0. 0xfffff000 0x00001000
9490 22:21:20.153684 IMD SMALL 1. 0xffffe000 0x00001000
9491 22:21:20.156797 RO MCACHE 2. 0xffffc000 0x00001104
9492 22:21:20.160696 CONSOLE 3. 0xfff7c000 0x00080000
9493 22:21:20.163822 FMAP 4. 0xfff7b000 0x00000452
9494 22:21:20.166822 TIME STAMP 5. 0xfff7a000 0x00000910
9495 22:21:20.169965 VBOOT WORK 6. 0xfff66000 0x00014000
9496 22:21:20.173244 RAMOOPS 7. 0xffe66000 0x00100000
9497 22:21:20.177119 COREBOOT 8. 0xffe64000 0x00002000
9498 22:21:20.180295 IMD small region:
9499 22:21:20.183404 IMD ROOT 0. 0xffffec00 0x00000400
9500 22:21:20.186694 VPD 1. 0xffffeba0 0x0000004c
9501 22:21:20.189751 MMC STATUS 2. 0xffffeb80 0x00000004
9502 22:21:20.196763 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9503 22:21:20.196840 Probing TPM: done!
9504 22:21:20.203119 Connected to device vid:did:rid of 1ae0:0028:00
9505 22:21:20.209614 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
9506 22:21:20.213302 Initialized TPM device CR50 revision 0
9507 22:21:20.216434 Checking cr50 for pending updates
9508 22:21:20.222619 Reading cr50 TPM mode
9509 22:21:20.231184 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9510 22:21:20.237385 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9511 22:21:20.277989 read SPI 0x3990ec 0x4f1b0: 34861 us, 9294 KB/s, 74.352 Mbps
9512 22:21:20.281213 Checking segment from ROM address 0x40100000
9513 22:21:20.284486 Checking segment from ROM address 0x4010001c
9514 22:21:20.290740 Loading segment from ROM address 0x40100000
9515 22:21:20.290865 code (compression=0)
9516 22:21:20.300914 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9517 22:21:20.307949 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9518 22:21:20.308056 it's not compressed!
9519 22:21:20.314197 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9520 22:21:20.320828 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9521 22:21:20.337888 Loading segment from ROM address 0x4010001c
9522 22:21:20.337977 Entry Point 0x80000000
9523 22:21:20.341485 Loaded segments
9524 22:21:20.344859 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9525 22:21:20.351370 Jumping to boot code at 0x80000000(0xffe64000)
9526 22:21:20.358144 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9527 22:21:20.364501 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9528 22:21:20.372834 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9529 22:21:20.375888 Checking segment from ROM address 0x40100000
9530 22:21:20.379000 Checking segment from ROM address 0x4010001c
9531 22:21:20.386038 Loading segment from ROM address 0x40100000
9532 22:21:20.386116 code (compression=1)
9533 22:21:20.392446 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9534 22:21:20.402574 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9535 22:21:20.402656 using LZMA
9536 22:21:20.411069 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9537 22:21:20.417450 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9538 22:21:20.421171 Loading segment from ROM address 0x4010001c
9539 22:21:20.421263 Entry Point 0x54601000
9540 22:21:20.424290 Loaded segments
9541 22:21:20.427846 NOTICE: MT8192 bl31_setup
9542 22:21:20.434501 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9543 22:21:20.437414 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9544 22:21:20.441166 WARNING: region 0:
9545 22:21:20.444575 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9546 22:21:20.444660 WARNING: region 1:
9547 22:21:20.450810 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9548 22:21:20.454350 WARNING: region 2:
9549 22:21:20.457914 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9550 22:21:20.460792 WARNING: region 3:
9551 22:21:20.467414 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9552 22:21:20.467499 WARNING: region 4:
9553 22:21:20.474194 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9554 22:21:20.474278 WARNING: region 5:
9555 22:21:20.477526 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9556 22:21:20.480529 WARNING: region 6:
9557 22:21:20.484368 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9558 22:21:20.487518 WARNING: region 7:
9559 22:21:20.490789 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9560 22:21:20.497200 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9561 22:21:20.500363 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9562 22:21:20.507533 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9563 22:21:20.510815 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9564 22:21:20.514019 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9565 22:21:20.520657 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9566 22:21:20.523559 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9567 22:21:20.527370 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9568 22:21:20.533497 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9569 22:21:20.537266 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9570 22:21:20.543824 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9571 22:21:20.546962 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9572 22:21:20.550519 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9573 22:21:20.557270 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9574 22:21:20.560232 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9575 22:21:20.563814 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9576 22:21:20.570287 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9577 22:21:20.573554 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9578 22:21:20.577227 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9579 22:21:20.583491 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9580 22:21:20.586802 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9581 22:21:20.593576 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9582 22:21:20.597405 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9583 22:21:20.600679 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9584 22:21:20.607013 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9585 22:21:20.610249 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9586 22:21:20.617238 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9587 22:21:20.620478 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9588 22:21:20.626766 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9589 22:21:20.629960 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9590 22:21:20.633676 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9591 22:21:20.639997 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9592 22:21:20.643144 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9593 22:21:20.646593 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9594 22:21:20.649956 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9595 22:21:20.656588 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9596 22:21:20.660098 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9597 22:21:20.663296 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9598 22:21:20.666280 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9599 22:21:20.673120 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9600 22:21:20.676081 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9601 22:21:20.679578 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9602 22:21:20.686376 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9603 22:21:20.689469 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9604 22:21:20.692636 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9605 22:21:20.696225 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9606 22:21:20.702614 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9607 22:21:20.705865 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9608 22:21:20.709126 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9609 22:21:20.716187 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9610 22:21:20.719253 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9611 22:21:20.726355 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9612 22:21:20.729451 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9613 22:21:20.732583 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9614 22:21:20.739403 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9615 22:21:20.742488 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9616 22:21:20.749086 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9617 22:21:20.752334 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9618 22:21:20.758949 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9619 22:21:20.762022 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9620 22:21:20.768870 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9621 22:21:20.772095 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9622 22:21:20.778744 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9623 22:21:20.781931 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9624 22:21:20.785572 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9625 22:21:20.791858 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9626 22:21:20.795465 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9627 22:21:20.801911 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9628 22:21:20.805039 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9629 22:21:20.811975 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9630 22:21:20.815196 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9631 22:21:20.818299 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9632 22:21:20.825359 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9633 22:21:20.828516 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9634 22:21:20.834742 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9635 22:21:20.838481 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9636 22:21:20.844671 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9637 22:21:20.848524 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9638 22:21:20.855087 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9639 22:21:20.858104 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9640 22:21:20.861711 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9641 22:21:20.867975 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9642 22:21:20.871975 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9643 22:21:20.878368 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9644 22:21:20.881333 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9645 22:21:20.888091 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9646 22:21:20.892027 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9647 22:21:20.894740 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9648 22:21:20.901155 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9649 22:21:20.904686 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9650 22:21:20.911157 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9651 22:21:20.914854 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9652 22:21:20.921251 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9653 22:21:20.924472 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9654 22:21:20.931532 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9655 22:21:20.934683 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9656 22:21:20.937826 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9657 22:21:20.944441 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9658 22:21:20.947492 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9659 22:21:20.950774 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9660 22:21:20.954579 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9661 22:21:20.960926 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9662 22:21:20.964105 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9663 22:21:20.970714 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9664 22:21:20.974340 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9665 22:21:20.977555 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9666 22:21:20.984709 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9667 22:21:20.987674 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9668 22:21:20.994232 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9669 22:21:20.997418 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9670 22:21:21.000580 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9671 22:21:21.007833 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9672 22:21:21.010750 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9673 22:21:21.017814 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9674 22:21:21.020853 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9675 22:21:21.024009 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9676 22:21:21.030856 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9677 22:21:21.033972 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9678 22:21:21.037187 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9679 22:21:21.043425 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9680 22:21:21.047241 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9681 22:21:21.050194 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9682 22:21:21.053363 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9683 22:21:21.060434 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9684 22:21:21.063678 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9685 22:21:21.066963 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9686 22:21:21.073588 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9687 22:21:21.076661 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9688 22:21:21.083801 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9689 22:21:21.086863 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9690 22:21:21.089972 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9691 22:21:21.096508 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9692 22:21:21.100178 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9693 22:21:21.106612 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9694 22:21:21.109703 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9695 22:21:21.113704 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9696 22:21:21.119512 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9697 22:21:21.122965 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9698 22:21:21.129694 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9699 22:21:21.132800 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9700 22:21:21.135950 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9701 22:21:21.142973 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9702 22:21:21.146149 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9703 22:21:21.152999 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9704 22:21:21.156212 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9705 22:21:21.159477 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9706 22:21:21.166476 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9707 22:21:21.169716 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9708 22:21:21.172827 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9709 22:21:21.179201 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9710 22:21:21.183120 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9711 22:21:21.189942 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9712 22:21:21.192588 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9713 22:21:21.195751 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9714 22:21:21.202418 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9715 22:21:21.205909 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9716 22:21:21.212734 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9717 22:21:21.215783 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9718 22:21:21.219084 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9719 22:21:21.225784 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9720 22:21:21.229356 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9721 22:21:21.235913 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9722 22:21:21.239063 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9723 22:21:21.242241 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9724 22:21:21.248732 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9725 22:21:21.252430 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9726 22:21:21.258958 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9727 22:21:21.262418 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9728 22:21:21.265654 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9729 22:21:21.272110 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9730 22:21:21.275237 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9731 22:21:21.281628 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9732 22:21:21.285103 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9733 22:21:21.288584 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9734 22:21:21.295291 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9735 22:21:21.297996 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9736 22:21:21.304768 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9737 22:21:21.308338 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9738 22:21:21.311267 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9739 22:21:21.317939 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9740 22:21:21.321775 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9741 22:21:21.328184 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9742 22:21:21.331150 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9743 22:21:21.334266 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9744 22:21:21.340934 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9745 22:21:21.344476 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9746 22:21:21.350934 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9747 22:21:21.354796 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9748 22:21:21.357941 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9749 22:21:21.364259 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9750 22:21:21.367424 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9751 22:21:21.374325 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9752 22:21:21.377508 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9753 22:21:21.383855 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9754 22:21:21.387618 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9755 22:21:21.390680 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9756 22:21:21.397600 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9757 22:21:21.400788 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9758 22:21:21.407362 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9759 22:21:21.410485 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9760 22:21:21.417279 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9761 22:21:21.420400 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9762 22:21:21.423630 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9763 22:21:21.429973 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9764 22:21:21.433595 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9765 22:21:21.439961 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9766 22:21:21.443216 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9767 22:21:21.449868 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9768 22:21:21.453016 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9769 22:21:21.456324 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9770 22:21:21.463090 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9771 22:21:21.466808 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9772 22:21:21.473198 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9773 22:21:21.476559 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9774 22:21:21.479651 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9775 22:21:21.486534 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9776 22:21:21.489652 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9777 22:21:21.495857 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9778 22:21:21.499796 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9779 22:21:21.505713 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9780 22:21:21.509409 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9781 22:21:21.512437 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9782 22:21:21.519056 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9783 22:21:21.522741 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9784 22:21:21.528963 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9785 22:21:21.532623 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9786 22:21:21.538978 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9787 22:21:21.541962 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9788 22:21:21.545677 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9789 22:21:21.552240 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9790 22:21:21.555218 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9791 22:21:21.558906 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9792 22:21:21.561985 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9793 22:21:21.568360 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9794 22:21:21.572133 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9795 22:21:21.575360 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9796 22:21:21.581752 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9797 22:21:21.584998 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9798 22:21:21.588144 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9799 22:21:21.595070 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9800 22:21:21.598328 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9801 22:21:21.604961 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9802 22:21:21.608041 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9803 22:21:21.611166 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9804 22:21:21.618029 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9805 22:21:21.621506 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9806 22:21:21.627919 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9807 22:21:21.631503 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9808 22:21:21.634770 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9809 22:21:21.640917 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9810 22:21:21.644453 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9811 22:21:21.650967 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9812 22:21:21.653967 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9813 22:21:21.657786 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9814 22:21:21.664298 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9815 22:21:21.667164 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9816 22:21:21.670961 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9817 22:21:21.677147 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9818 22:21:21.680920 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9819 22:21:21.684189 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9820 22:21:21.690704 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9821 22:21:21.693855 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9822 22:21:21.700735 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9823 22:21:21.704160 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9824 22:21:21.706996 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9825 22:21:21.713945 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9826 22:21:21.717171 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9827 22:21:21.723705 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9828 22:21:21.727041 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9829 22:21:21.729894 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9830 22:21:21.733452 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9831 22:21:21.736678 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9832 22:21:21.743639 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9833 22:21:21.746666 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9834 22:21:21.749832 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9835 22:21:21.753524 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9836 22:21:21.759984 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9837 22:21:21.763043 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9838 22:21:21.766201 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9839 22:21:21.769724 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9840 22:21:21.776412 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9841 22:21:21.779359 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9842 22:21:21.786152 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9843 22:21:21.789304 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9844 22:21:21.792501 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9845 22:21:21.799394 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9846 22:21:21.802643 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9847 22:21:21.808949 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9848 22:21:21.812175 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9849 22:21:21.819051 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9850 22:21:21.822218 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9851 22:21:21.825430 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9852 22:21:21.832260 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9853 22:21:21.835430 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9854 22:21:21.842027 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9855 22:21:21.844965 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9856 22:21:21.851996 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9857 22:21:21.855201 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9858 22:21:21.858446 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9859 22:21:21.865155 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9860 22:21:21.868119 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9861 22:21:21.874773 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9862 22:21:21.878347 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9863 22:21:21.881802 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9864 22:21:21.887829 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9865 22:21:21.891644 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9866 22:21:21.898076 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9867 22:21:21.901527 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9868 22:21:21.908065 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9869 22:21:21.911052 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9870 22:21:21.914192 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9871 22:21:21.920947 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9872 22:21:21.924045 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9873 22:21:21.931222 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9874 22:21:21.934451 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9875 22:21:21.937662 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9876 22:21:21.944263 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9877 22:21:21.947456 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9878 22:21:21.953760 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9879 22:21:21.957402 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9880 22:21:21.963727 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9881 22:21:21.967391 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9882 22:21:21.970514 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9883 22:21:21.977082 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9884 22:21:21.979984 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9885 22:21:21.986577 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9886 22:21:21.990364 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9887 22:21:21.997015 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9888 22:21:22.000082 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9889 22:21:22.003210 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9890 22:21:22.010522 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9891 22:21:22.013435 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9892 22:21:22.019984 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9893 22:21:22.022983 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9894 22:21:22.026679 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9895 22:21:22.033009 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9896 22:21:22.036311 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9897 22:21:22.042698 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9898 22:21:22.046264 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9899 22:21:22.049470 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9900 22:21:22.056233 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9901 22:21:22.059107 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9902 22:21:22.066001 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9903 22:21:22.069231 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9904 22:21:22.075967 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9905 22:21:22.079393 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9906 22:21:22.082446 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9907 22:21:22.089259 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9908 22:21:22.092258 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9909 22:21:22.098775 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9910 22:21:22.102246 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9911 22:21:22.108436 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9912 22:21:22.111813 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9913 22:21:22.115366 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9914 22:21:22.121738 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9915 22:21:22.124864 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9916 22:21:22.131661 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9917 22:21:22.134914 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9918 22:21:22.141236 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9919 22:21:22.144415 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9920 22:21:22.151159 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9921 22:21:22.154304 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9922 22:21:22.157581 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9923 22:21:22.164628 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9924 22:21:22.167712 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9925 22:21:22.174020 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9926 22:21:22.177609 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9927 22:21:22.184065 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9928 22:21:22.187778 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9929 22:21:22.193971 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9930 22:21:22.197191 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9931 22:21:22.200844 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9932 22:21:22.207093 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9933 22:21:22.210742 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9934 22:21:22.217162 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9935 22:21:22.220581 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9936 22:21:22.227093 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9937 22:21:22.230163 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9938 22:21:22.237023 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9939 22:21:22.240313 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9940 22:21:22.246764 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9941 22:21:22.249907 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9942 22:21:22.253280 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9943 22:21:22.259938 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9944 22:21:22.263126 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9945 22:21:22.270004 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9946 22:21:22.273149 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9947 22:21:22.280017 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9948 22:21:22.283313 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9949 22:21:22.289318 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9950 22:21:22.293061 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9951 22:21:22.296224 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9952 22:21:22.302958 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9953 22:21:22.306027 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9954 22:21:22.312409 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9955 22:21:22.315806 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9956 22:21:22.322664 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9957 22:21:22.325781 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9958 22:21:22.332491 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9959 22:21:22.335662 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9960 22:21:22.341922 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9961 22:21:22.345693 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9962 22:21:22.348814 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9963 22:21:22.355160 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9964 22:21:22.358825 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9965 22:21:22.365185 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9966 22:21:22.368338 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9967 22:21:22.375323 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9968 22:21:22.378388 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9969 22:21:22.385263 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9970 22:21:22.388455 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9971 22:21:22.394619 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9972 22:21:22.398242 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9973 22:21:22.404393 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9974 22:21:22.407987 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9975 22:21:22.414809 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9976 22:21:22.418001 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9977 22:21:22.421125 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9978 22:21:22.428001 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9979 22:21:22.430946 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9980 22:21:22.437588 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9981 22:21:22.440656 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9982 22:21:22.447654 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9983 22:21:22.454043 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9984 22:21:22.457126 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9985 22:21:22.464110 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9986 22:21:22.467289 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9987 22:21:22.473633 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9988 22:21:22.477505 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9989 22:21:22.483930 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9990 22:21:22.487233 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9991 22:21:22.493997 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9992 22:21:22.496945 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9993 22:21:22.503827 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9994 22:21:22.506874 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9995 22:21:22.506958 INFO: [APUAPC] vio 0
9996 22:21:22.514751 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9997 22:21:22.517940 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9998 22:21:22.521300 INFO: [APUAPC] D0_APC_0: 0x400510
9999 22:21:22.524391 INFO: [APUAPC] D0_APC_1: 0x0
10000 22:21:22.527488 INFO: [APUAPC] D0_APC_2: 0x1540
10001 22:21:22.531385 INFO: [APUAPC] D0_APC_3: 0x0
10002 22:21:22.534233 INFO: [APUAPC] D1_APC_0: 0xffffffff
10003 22:21:22.537328 INFO: [APUAPC] D1_APC_1: 0xffffffff
10004 22:21:22.540859 INFO: [APUAPC] D1_APC_2: 0x3fffff
10005 22:21:22.543931 INFO: [APUAPC] D1_APC_3: 0x0
10006 22:21:22.547685 INFO: [APUAPC] D2_APC_0: 0xffffffff
10007 22:21:22.550867 INFO: [APUAPC] D2_APC_1: 0xffffffff
10008 22:21:22.554098 INFO: [APUAPC] D2_APC_2: 0x3fffff
10009 22:21:22.557218 INFO: [APUAPC] D2_APC_3: 0x0
10010 22:21:22.560397 INFO: [APUAPC] D3_APC_0: 0xffffffff
10011 22:21:22.563606 INFO: [APUAPC] D3_APC_1: 0xffffffff
10012 22:21:22.567290 INFO: [APUAPC] D3_APC_2: 0x3fffff
10013 22:21:22.570194 INFO: [APUAPC] D3_APC_3: 0x0
10014 22:21:22.573431 INFO: [APUAPC] D4_APC_0: 0xffffffff
10015 22:21:22.577123 INFO: [APUAPC] D4_APC_1: 0xffffffff
10016 22:21:22.580201 INFO: [APUAPC] D4_APC_2: 0x3fffff
10017 22:21:22.583464 INFO: [APUAPC] D4_APC_3: 0x0
10018 22:21:22.586689 INFO: [APUAPC] D5_APC_0: 0xffffffff
10019 22:21:22.590155 INFO: [APUAPC] D5_APC_1: 0xffffffff
10020 22:21:22.593411 INFO: [APUAPC] D5_APC_2: 0x3fffff
10021 22:21:22.596614 INFO: [APUAPC] D5_APC_3: 0x0
10022 22:21:22.599841 INFO: [APUAPC] D6_APC_0: 0xffffffff
10023 22:21:22.603549 INFO: [APUAPC] D6_APC_1: 0xffffffff
10024 22:21:22.606681 INFO: [APUAPC] D6_APC_2: 0x3fffff
10025 22:21:22.610059 INFO: [APUAPC] D6_APC_3: 0x0
10026 22:21:22.613187 INFO: [APUAPC] D7_APC_0: 0xffffffff
10027 22:21:22.616723 INFO: [APUAPC] D7_APC_1: 0xffffffff
10028 22:21:22.619893 INFO: [APUAPC] D7_APC_2: 0x3fffff
10029 22:21:22.622784 INFO: [APUAPC] D7_APC_3: 0x0
10030 22:21:22.626652 INFO: [APUAPC] D8_APC_0: 0xffffffff
10031 22:21:22.629523 INFO: [APUAPC] D8_APC_1: 0xffffffff
10032 22:21:22.633411 INFO: [APUAPC] D8_APC_2: 0x3fffff
10033 22:21:22.633495 INFO: [APUAPC] D8_APC_3: 0x0
10034 22:21:22.639339 INFO: [APUAPC] D9_APC_0: 0xffffffff
10035 22:21:22.643026 INFO: [APUAPC] D9_APC_1: 0xffffffff
10036 22:21:22.646078 INFO: [APUAPC] D9_APC_2: 0x3fffff
10037 22:21:22.646160 INFO: [APUAPC] D9_APC_3: 0x0
10038 22:21:22.652796 INFO: [APUAPC] D10_APC_0: 0xffffffff
10039 22:21:22.655993 INFO: [APUAPC] D10_APC_1: 0xffffffff
10040 22:21:22.659116 INFO: [APUAPC] D10_APC_2: 0x3fffff
10041 22:21:22.659199 INFO: [APUAPC] D10_APC_3: 0x0
10042 22:21:22.666093 INFO: [APUAPC] D11_APC_0: 0xffffffff
10043 22:21:22.669285 INFO: [APUAPC] D11_APC_1: 0xffffffff
10044 22:21:22.672334 INFO: [APUAPC] D11_APC_2: 0x3fffff
10045 22:21:22.675366 INFO: [APUAPC] D11_APC_3: 0x0
10046 22:21:22.679241 INFO: [APUAPC] D12_APC_0: 0xffffffff
10047 22:21:22.682363 INFO: [APUAPC] D12_APC_1: 0xffffffff
10048 22:21:22.685470 INFO: [APUAPC] D12_APC_2: 0x3fffff
10049 22:21:22.688714 INFO: [APUAPC] D12_APC_3: 0x0
10050 22:21:22.691824 INFO: [APUAPC] D13_APC_0: 0xffffffff
10051 22:21:22.695582 INFO: [APUAPC] D13_APC_1: 0xffffffff
10052 22:21:22.698749 INFO: [APUAPC] D13_APC_2: 0x3fffff
10053 22:21:22.701904 INFO: [APUAPC] D13_APC_3: 0x0
10054 22:21:22.705133 INFO: [APUAPC] D14_APC_0: 0xffffffff
10055 22:21:22.708793 INFO: [APUAPC] D14_APC_1: 0xffffffff
10056 22:21:22.711998 INFO: [APUAPC] D14_APC_2: 0x3fffff
10057 22:21:22.715087 INFO: [APUAPC] D14_APC_3: 0x0
10058 22:21:22.718547 INFO: [APUAPC] D15_APC_0: 0xffffffff
10059 22:21:22.722070 INFO: [APUAPC] D15_APC_1: 0xffffffff
10060 22:21:22.725146 INFO: [APUAPC] D15_APC_2: 0x3fffff
10061 22:21:22.728051 INFO: [APUAPC] D15_APC_3: 0x0
10062 22:21:22.731629 INFO: [APUAPC] APC_CON: 0x4
10063 22:21:22.734736 INFO: [NOCDAPC] D0_APC_0: 0x0
10064 22:21:22.734862 INFO: [NOCDAPC] D0_APC_1: 0x0
10065 22:21:22.738343 INFO: [NOCDAPC] D1_APC_0: 0x0
10066 22:21:22.741257 INFO: [NOCDAPC] D1_APC_1: 0xfff
10067 22:21:22.744887 INFO: [NOCDAPC] D2_APC_0: 0x0
10068 22:21:22.748073 INFO: [NOCDAPC] D2_APC_1: 0xfff
10069 22:21:22.751155 INFO: [NOCDAPC] D3_APC_0: 0x0
10070 22:21:22.754613 INFO: [NOCDAPC] D3_APC_1: 0xfff
10071 22:21:22.758038 INFO: [NOCDAPC] D4_APC_0: 0x0
10072 22:21:22.761172 INFO: [NOCDAPC] D4_APC_1: 0xfff
10073 22:21:22.764416 INFO: [NOCDAPC] D5_APC_0: 0x0
10074 22:21:22.767647 INFO: [NOCDAPC] D5_APC_1: 0xfff
10075 22:21:22.767724 INFO: [NOCDAPC] D6_APC_0: 0x0
10076 22:21:22.770847 INFO: [NOCDAPC] D6_APC_1: 0xfff
10077 22:21:22.774839 INFO: [NOCDAPC] D7_APC_0: 0x0
10078 22:21:22.777605 INFO: [NOCDAPC] D7_APC_1: 0xfff
10079 22:21:22.780779 INFO: [NOCDAPC] D8_APC_0: 0x0
10080 22:21:22.784519 INFO: [NOCDAPC] D8_APC_1: 0xfff
10081 22:21:22.787569 INFO: [NOCDAPC] D9_APC_0: 0x0
10082 22:21:22.790740 INFO: [NOCDAPC] D9_APC_1: 0xfff
10083 22:21:22.793902 INFO: [NOCDAPC] D10_APC_0: 0x0
10084 22:21:22.797702 INFO: [NOCDAPC] D10_APC_1: 0xfff
10085 22:21:22.800878 INFO: [NOCDAPC] D11_APC_0: 0x0
10086 22:21:22.804161 INFO: [NOCDAPC] D11_APC_1: 0xfff
10087 22:21:22.807427 INFO: [NOCDAPC] D12_APC_0: 0x0
10088 22:21:22.810427 INFO: [NOCDAPC] D12_APC_1: 0xfff
10089 22:21:22.810510 INFO: [NOCDAPC] D13_APC_0: 0x0
10090 22:21:22.814167 INFO: [NOCDAPC] D13_APC_1: 0xfff
10091 22:21:22.817443 INFO: [NOCDAPC] D14_APC_0: 0x0
10092 22:21:22.820620 INFO: [NOCDAPC] D14_APC_1: 0xfff
10093 22:21:22.823801 INFO: [NOCDAPC] D15_APC_0: 0x0
10094 22:21:22.827307 INFO: [NOCDAPC] D15_APC_1: 0xfff
10095 22:21:22.830195 INFO: [NOCDAPC] APC_CON: 0x4
10096 22:21:22.833611 INFO: [APUAPC] set_apusys_apc done
10097 22:21:22.836824 INFO: [DEVAPC] devapc_init done
10098 22:21:22.840632 INFO: GICv3 without legacy support detected.
10099 22:21:22.847011 INFO: ARM GICv3 driver initialized in EL3
10100 22:21:22.849877 INFO: Maximum SPI INTID supported: 639
10101 22:21:22.853494 INFO: BL31: Initializing runtime services
10102 22:21:22.859758 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10103 22:21:22.859836 INFO: SPM: enable CPC mode
10104 22:21:22.866741 INFO: mcdi ready for mcusys-off-idle and system suspend
10105 22:21:22.869704 INFO: BL31: Preparing for EL3 exit to normal world
10106 22:21:22.876765 INFO: Entry point address = 0x80000000
10107 22:21:22.876870 INFO: SPSR = 0x8
10108 22:21:22.882388
10109 22:21:22.882493
10110 22:21:22.882595
10111 22:21:22.886263 Starting depthcharge on Spherion...
10112 22:21:22.886341
10113 22:21:22.886402 Wipe memory regions:
10114 22:21:22.886460
10115 22:21:22.887136 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10116 22:21:22.887240 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10117 22:21:22.887368 Setting prompt string to ['asurada:']
10118 22:21:22.887478 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10119 22:21:22.889348 [0x00000040000000, 0x00000054600000)
10120 22:21:23.011818
10121 22:21:23.011984 [0x00000054660000, 0x00000080000000)
10122 22:21:23.272481
10123 22:21:23.272624 [0x000000821a7280, 0x000000ffe64000)
10124 22:21:24.017054
10125 22:21:24.017190 [0x00000100000000, 0x00000240000000)
10126 22:21:25.906531
10127 22:21:25.910079 Initializing XHCI USB controller at 0x11200000.
10128 22:21:26.947979
10129 22:21:26.951002 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10130 22:21:26.951106
10131 22:21:26.951181
10132 22:21:26.951246
10133 22:21:26.951528 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10135 22:21:27.051820 asurada: tftpboot 192.168.201.1 10597300/tftp-deploy-ebp2nqop/kernel/image.itb 10597300/tftp-deploy-ebp2nqop/kernel/cmdline
10136 22:21:27.051962 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10137 22:21:27.052045 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10138 22:21:27.055826 tftpboot 192.168.201.1 10597300/tftp-deploy-ebp2nqop/kernel/image.itp-deploy-ebp2nqop/kernel/cmdline
10139 22:21:27.055941
10140 22:21:27.056038 Waiting for link
10141 22:21:27.216389
10142 22:21:27.216529 R8152: Initializing
10143 22:21:27.216608
10144 22:21:27.220136 Version 6 (ocp_data = 5c30)
10145 22:21:27.220221
10146 22:21:27.223342 R8152: Done initializing
10147 22:21:27.223428
10148 22:21:27.223492 Adding net device
10149 22:21:29.127304
10150 22:21:29.127472 done.
10151 22:21:29.127601
10152 22:21:29.127689 MAC: 00:24:32:30:78:ff
10153 22:21:29.127762
10154 22:21:29.130159 Sending DHCP discover... done.
10155 22:21:29.130231
10156 22:21:35.192561 Waiting for reply... done.
10157 22:21:35.192698
10158 22:21:35.192801 Sending DHCP request... done.
10159 22:21:35.196184
10160 22:21:35.196287 Waiting for reply... done.
10161 22:21:35.196395
10162 22:21:35.199527 My ip is 192.168.201.21
10163 22:21:35.199618
10164 22:21:35.202708 The DHCP server ip is 192.168.201.1
10165 22:21:35.202791
10166 22:21:35.205726 TFTP server IP predefined by user: 192.168.201.1
10167 22:21:35.205809
10168 22:21:35.212756 Bootfile predefined by user: 10597300/tftp-deploy-ebp2nqop/kernel/image.itb
10169 22:21:35.212866
10170 22:21:35.215852 Sending tftp read request... done.
10171 22:21:35.215934
10172 22:21:35.219037 Waiting for the transfer...
10173 22:21:35.219130
10174 22:21:35.755283 00000000 ################################################################
10175 22:21:35.755446
10176 22:21:36.293438 00080000 ################################################################
10177 22:21:36.293605
10178 22:21:36.830505 00100000 ################################################################
10179 22:21:36.830661
10180 22:21:37.367185 00180000 ################################################################
10181 22:21:37.367366
10182 22:21:37.889848 00200000 ################################################################
10183 22:21:37.890026
10184 22:21:38.421168 00280000 ################################################################
10185 22:21:38.421334
10186 22:21:38.948943 00300000 ################################################################
10187 22:21:38.949081
10188 22:21:39.487472 00380000 ################################################################
10189 22:21:39.487611
10190 22:21:40.013275 00400000 ################################################################
10191 22:21:40.013412
10192 22:21:40.539125 00480000 ################################################################
10193 22:21:40.539298
10194 22:21:41.064592 00500000 ################################################################
10195 22:21:41.064756
10196 22:21:41.592429 00580000 ################################################################
10197 22:21:41.592601
10198 22:21:42.130854 00600000 ################################################################
10199 22:21:42.131032
10200 22:21:42.671889 00680000 ################################################################
10201 22:21:42.672057
10202 22:21:43.225500 00700000 ################################################################
10203 22:21:43.225640
10204 22:21:43.762313 00780000 ################################################################
10205 22:21:43.762458
10206 22:21:44.295194 00800000 ################################################################
10207 22:21:44.295334
10208 22:21:44.831292 00880000 ################################################################
10209 22:21:44.831455
10210 22:21:45.369074 00900000 ################################################################
10211 22:21:45.369215
10212 22:21:45.932672 00980000 ################################################################
10213 22:21:45.933238
10214 22:21:46.661337 00a00000 ################################################################
10215 22:21:46.661923
10216 22:21:47.269781 00a80000 ################################################################
10217 22:21:47.270000
10218 22:21:47.834693 00b00000 ################################################################
10219 22:21:47.834837
10220 22:21:48.497685 00b80000 ################################################################
10221 22:21:48.497846
10222 22:21:49.149642 00c00000 ################################################################
10223 22:21:49.150169
10224 22:21:49.856603 00c80000 ################################################################
10225 22:21:49.857324
10226 22:21:50.552032 00d00000 ################################################################
10227 22:21:50.552537
10228 22:21:51.178760 00d80000 ################################################################
10229 22:21:51.178907
10230 22:21:51.816998 00e00000 ################################################################
10231 22:21:51.817372
10232 22:21:52.482272 00e80000 ################################################################
10233 22:21:52.482883
10234 22:21:53.213347 00f00000 ################################################################
10235 22:21:53.214083
10236 22:21:53.935756 00f80000 ################################################################
10237 22:21:53.936370
10238 22:21:54.650603 01000000 ################################################################
10239 22:21:54.651206
10240 22:21:55.338753 01080000 ################################################################
10241 22:21:55.339426
10242 22:21:56.050292 01100000 ################################################################
10243 22:21:56.050801
10244 22:21:56.734249 01180000 ################################################################
10245 22:21:56.734769
10246 22:21:57.389221 01200000 ################################################################
10247 22:21:57.389756
10248 22:21:58.064679 01280000 ################################################################
10249 22:21:58.064818
10250 22:21:58.741926 01300000 ################################################################
10251 22:21:58.742445
10252 22:21:59.417126 01380000 ################################################################
10253 22:21:59.417675
10254 22:22:00.087594 01400000 ################################################################
10255 22:22:00.087775
10256 22:22:00.644693 01480000 ################################################################
10257 22:22:00.644833
10258 22:22:01.205534 01500000 ################################################################
10259 22:22:01.205674
10260 22:22:01.763736 01580000 ################################################################
10261 22:22:01.763877
10262 22:22:02.337586 01600000 ################################################################
10263 22:22:02.337721
10264 22:22:02.956139 01680000 ################################################################
10265 22:22:02.956305
10266 22:22:03.495723 01700000 ################################################################
10267 22:22:03.495877
10268 22:22:04.036610 01780000 ################################################################
10269 22:22:04.036747
10270 22:22:04.659089 01800000 ################################################################
10271 22:22:04.659646
10272 22:22:05.340180 01880000 ################################################################
10273 22:22:05.340747
10274 22:22:05.997263 01900000 ################################################################
10275 22:22:05.997399
10276 22:22:06.687989 01980000 ################################################################
10277 22:22:06.688533
10278 22:22:07.335904 01a00000 ############################################################### done.
10279 22:22:07.336419
10280 22:22:07.339554 The bootfile was 27772566 bytes long.
10281 22:22:07.340003
10282 22:22:07.342706 Sending tftp read request... done.
10283 22:22:07.343243
10284 22:22:07.345697 Waiting for the transfer...
10285 22:22:07.346161
10286 22:22:07.348847 00000000 # done.
10287 22:22:07.349326
10288 22:22:07.355664 Command line loaded dynamically from TFTP file: 10597300/tftp-deploy-ebp2nqop/kernel/cmdline
10289 22:22:07.356106
10290 22:22:07.375492 The command line is: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/10597300/extract-nfsrootfs-cj0nalzp,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10291 22:22:07.376038
10292 22:22:07.376379 Loading FIT.
10293 22:22:07.376713
10294 22:22:07.378873 Image ramdisk-1 has 17641302 bytes.
10295 22:22:07.379359
10296 22:22:07.381725 Image fdt-1 has 46924 bytes.
10297 22:22:07.382169
10298 22:22:07.385146 Image kernel-1 has 10082307 bytes.
10299 22:22:07.385571
10300 22:22:07.395207 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10301 22:22:07.395678
10302 22:22:07.411521 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10303 22:22:07.412242
10304 22:22:07.418354 Choosing best match conf-1 for compat google,spherion-rev2.
10305 22:22:07.421548
10306 22:22:07.425630 Connected to device vid:did:rid of 1ae0:0028:00
10307 22:22:07.433007
10308 22:22:07.436726 tpm_get_response: command 0x17b, return code 0x0
10309 22:22:07.437153
10310 22:22:07.439867 ec_init: CrosEC protocol v3 supported (256, 248)
10311 22:22:07.443529
10312 22:22:07.447125 tpm_cleanup: add release locality here.
10313 22:22:07.447561
10314 22:22:07.447994 Shutting down all USB controllers.
10315 22:22:07.450362
10316 22:22:07.450796 Removing current net device
10317 22:22:07.451254
10318 22:22:07.457125 Exiting depthcharge with code 4 at timestamp: 73914604
10319 22:22:07.457563
10320 22:22:07.460203 LZMA decompressing kernel-1 to 0x821a6718
10321 22:22:07.460643
10322 22:22:07.463370 LZMA decompressing kernel-1 to 0x40000000
10323 22:22:08.730709
10324 22:22:08.731312 jumping to kernel
10325 22:22:08.732766 end: 2.2.4 bootloader-commands (duration 00:00:46) [common]
10326 22:22:08.733315 start: 2.2.5 auto-login-action (timeout 00:03:39) [common]
10327 22:22:08.733748 Setting prompt string to ['Linux version [0-9]']
10328 22:22:08.734137 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10329 22:22:08.734535 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10330 22:22:08.812391
10331 22:22:08.815375 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10332 22:22:08.819278 start: 2.2.5.1 login-action (timeout 00:03:39) [common]
10333 22:22:08.819831 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10334 22:22:08.820276 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10335 22:22:08.820666 Using line separator: #'\n'#
10336 22:22:08.820986 No login prompt set.
10337 22:22:08.821306 Parsing kernel messages
10338 22:22:08.821600 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10339 22:22:08.822242 [login-action] Waiting for messages, (timeout 00:03:39)
10340 22:22:08.838378 [ 0.000000] Linux version 6.1.31 (KernelCI@build-j1612341-arm64-gcc-10-defconfig-arm64-chromebook-n674v) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Mon Jun 5 22:04:07 UTC 2023
10341 22:22:08.841793 [ 0.000000] random: crng init done
10342 22:22:08.848501 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10343 22:22:08.851463 [ 0.000000] efi: UEFI not found.
10344 22:22:08.858437 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10345 22:22:08.864560 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10346 22:22:08.874615 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10347 22:22:08.884725 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10348 22:22:08.891248 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10349 22:22:08.897439 [ 0.000000] printk: bootconsole [mtk8250] enabled
10350 22:22:08.904511 [ 0.000000] NUMA: No NUMA configuration found
10351 22:22:08.910526 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10352 22:22:08.914121 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcda00-0x23efcffff]
10353 22:22:08.917215 [ 0.000000] Zone ranges:
10354 22:22:08.924098 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10355 22:22:08.927573 [ 0.000000] DMA32 empty
10356 22:22:08.933682 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10357 22:22:08.937331 [ 0.000000] Movable zone start for each node
10358 22:22:08.940452 [ 0.000000] Early memory node ranges
10359 22:22:08.947315 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10360 22:22:08.953699 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10361 22:22:08.960257 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10362 22:22:08.967179 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10363 22:22:08.973785 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10364 22:22:08.979977 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10365 22:22:09.035890 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10366 22:22:09.042556 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10367 22:22:09.049756 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10368 22:22:09.052623 [ 0.000000] psci: probing for conduit method from DT.
10369 22:22:09.059478 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10370 22:22:09.062298 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10371 22:22:09.068859 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10372 22:22:09.072331 [ 0.000000] psci: SMC Calling Convention v1.2
10373 22:22:09.078743 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10374 22:22:09.081879 [ 0.000000] Detected VIPT I-cache on CPU0
10375 22:22:09.088510 [ 0.000000] CPU features: detected: GIC system register CPU interface
10376 22:22:09.095199 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10377 22:22:09.101359 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10378 22:22:09.108136 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10379 22:22:09.118206 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10380 22:22:09.124465 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10381 22:22:09.127926 [ 0.000000] alternatives: applying boot alternatives
10382 22:22:09.135005 [ 0.000000] Fallback order for Node 0: 0
10383 22:22:09.141220 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10384 22:22:09.144718 [ 0.000000] Policy zone: Normal
10385 22:22:09.164358 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/10597300/extract-nfsrootfs-cj0nalzp,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10386 22:22:09.174272 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10387 22:22:09.186187 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10388 22:22:09.196075 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10389 22:22:09.202217 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10390 22:22:09.205713 <6>[ 0.000000] software IO TLB: area num 8.
10391 22:22:09.262473 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10392 22:22:09.411514 <6>[ 0.000000] Memory: 7955716K/8385536K available (17984K kernel code, 4098K rwdata, 14068K rodata, 8384K init, 615K bss, 397052K reserved, 32768K cma-reserved)
10393 22:22:09.418209 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10394 22:22:09.424544 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10395 22:22:09.428097 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10396 22:22:09.434888 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10397 22:22:09.441506 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10398 22:22:09.444180 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10399 22:22:09.454177 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10400 22:22:09.460992 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10401 22:22:09.467386 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10402 22:22:09.474133 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10403 22:22:09.477534 <6>[ 0.000000] GICv3: 608 SPIs implemented
10404 22:22:09.480948 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10405 22:22:09.487326 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10406 22:22:09.490314 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10407 22:22:09.496904 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10408 22:22:09.510268 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10409 22:22:09.523634 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10410 22:22:09.529559 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10411 22:22:09.537559 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10412 22:22:09.550863 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10413 22:22:09.557964 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10414 22:22:09.564151 <6>[ 0.009181] Console: colour dummy device 80x25
10415 22:22:09.574326 <6>[ 0.013908] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10416 22:22:09.580355 <6>[ 0.024350] pid_max: default: 32768 minimum: 301
10417 22:22:09.583708 <6>[ 0.029217] LSM: Security Framework initializing
10418 22:22:09.590234 <6>[ 0.034155] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10419 22:22:09.600371 <6>[ 0.041969] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10420 22:22:09.610258 <6>[ 0.051458] cblist_init_generic: Setting adjustable number of callback queues.
10421 22:22:09.617122 <6>[ 0.058959] cblist_init_generic: Setting shift to 3 and lim to 1.
10422 22:22:09.620292 <6>[ 0.065298] cblist_init_generic: Setting shift to 3 and lim to 1.
10423 22:22:09.627146 <6>[ 0.071706] rcu: Hierarchical SRCU implementation.
10424 22:22:09.633730 <6>[ 0.076719] rcu: Max phase no-delay instances is 1000.
10425 22:22:09.640615 <6>[ 0.083744] EFI services will not be available.
10426 22:22:09.643454 <6>[ 0.088718] smp: Bringing up secondary CPUs ...
10427 22:22:09.651579 <6>[ 0.093802] Detected VIPT I-cache on CPU1
10428 22:22:09.658020 <6>[ 0.093873] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10429 22:22:09.665162 <6>[ 0.093903] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10430 22:22:09.668631 <6>[ 0.094241] Detected VIPT I-cache on CPU2
10431 22:22:09.678316 <6>[ 0.094294] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10432 22:22:09.684690 <6>[ 0.094311] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10433 22:22:09.687951 <6>[ 0.094574] Detected VIPT I-cache on CPU3
10434 22:22:09.694614 <6>[ 0.094621] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10435 22:22:09.701115 <6>[ 0.094635] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10436 22:22:09.704046 <6>[ 0.094942] CPU features: detected: Spectre-v4
10437 22:22:09.710723 <6>[ 0.094948] CPU features: detected: Spectre-BHB
10438 22:22:09.714455 <6>[ 0.094954] Detected PIPT I-cache on CPU4
10439 22:22:09.721153 <6>[ 0.095011] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10440 22:22:09.727243 <6>[ 0.095028] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10441 22:22:09.733818 <6>[ 0.095325] Detected PIPT I-cache on CPU5
10442 22:22:09.740458 <6>[ 0.095391] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10443 22:22:09.746579 <6>[ 0.095407] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10444 22:22:09.750255 <6>[ 0.095692] Detected PIPT I-cache on CPU6
10445 22:22:09.759889 <6>[ 0.095759] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10446 22:22:09.766433 <6>[ 0.095776] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10447 22:22:09.769879 <6>[ 0.096070] Detected PIPT I-cache on CPU7
10448 22:22:09.776370 <6>[ 0.096128] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10449 22:22:09.783192 <6>[ 0.096145] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10450 22:22:09.786220 <6>[ 0.096192] smp: Brought up 1 node, 8 CPUs
10451 22:22:09.792841 <6>[ 0.237548] SMP: Total of 8 processors activated.
10452 22:22:09.799506 <6>[ 0.242469] CPU features: detected: 32-bit EL0 Support
10453 22:22:09.805847 <6>[ 0.247865] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10454 22:22:09.812367 <6>[ 0.256665] CPU features: detected: Common not Private translations
10455 22:22:09.819343 <6>[ 0.263141] CPU features: detected: CRC32 instructions
10456 22:22:09.825896 <6>[ 0.268505] CPU features: detected: RCpc load-acquire (LDAPR)
10457 22:22:09.828888 <6>[ 0.274465] CPU features: detected: LSE atomic instructions
10458 22:22:09.835615 <6>[ 0.280246] CPU features: detected: Privileged Access Never
10459 22:22:09.842267 <6>[ 0.286026] CPU features: detected: RAS Extension Support
10460 22:22:09.848792 <6>[ 0.291669] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10461 22:22:09.851772 <6>[ 0.298893] CPU: All CPU(s) started at EL2
10462 22:22:09.858368 <6>[ 0.303209] alternatives: applying system-wide alternatives
10463 22:22:09.868896 <6>[ 0.313899] devtmpfs: initialized
10464 22:22:09.884092 <6>[ 0.322714] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10465 22:22:09.891073 <6>[ 0.332675] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10466 22:22:09.897358 <6>[ 0.340910] pinctrl core: initialized pinctrl subsystem
10467 22:22:09.900734 <6>[ 0.347520] DMI not present or invalid.
10468 22:22:09.907431 <6>[ 0.351930] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10469 22:22:09.917417 <6>[ 0.358822] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10470 22:22:09.924108 <6>[ 0.366402] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10471 22:22:09.933883 <6>[ 0.374630] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10472 22:22:09.937206 <6>[ 0.382873] audit: initializing netlink subsys (disabled)
10473 22:22:09.946974 <5>[ 0.388567] audit: type=2000 audit(0.276:1): state=initialized audit_enabled=0 res=1
10474 22:22:09.953641 <6>[ 0.389261] thermal_sys: Registered thermal governor 'step_wise'
10475 22:22:09.959827 <6>[ 0.396532] thermal_sys: Registered thermal governor 'power_allocator'
10476 22:22:09.963171 <6>[ 0.402786] cpuidle: using governor menu
10477 22:22:09.969967 <6>[ 0.413749] NET: Registered PF_QIPCRTR protocol family
10478 22:22:09.976667 <6>[ 0.419238] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10479 22:22:09.982927 <6>[ 0.426338] ASID allocator initialised with 32768 entries
10480 22:22:09.986291 <6>[ 0.432893] Serial: AMBA PL011 UART driver
10481 22:22:09.996583 <4>[ 0.441487] Trying to register duplicate clock ID: 134
10482 22:22:10.050182 <6>[ 0.498451] KASLR enabled
10483 22:22:10.064122 <6>[ 0.506189] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10484 22:22:10.071074 <6>[ 0.513203] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10485 22:22:10.077998 <6>[ 0.519692] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10486 22:22:10.084301 <6>[ 0.526697] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10487 22:22:10.090619 <6>[ 0.533183] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10488 22:22:10.097759 <6>[ 0.540187] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10489 22:22:10.103947 <6>[ 0.546676] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10490 22:22:10.110512 <6>[ 0.553681] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10491 22:22:10.114398 <6>[ 0.561190] ACPI: Interpreter disabled.
10492 22:22:10.122548 <6>[ 0.567563] iommu: Default domain type: Translated
10493 22:22:10.129071 <6>[ 0.572678] iommu: DMA domain TLB invalidation policy: strict mode
10494 22:22:10.132709 <5>[ 0.579334] SCSI subsystem initialized
10495 22:22:10.139288 <6>[ 0.583496] usbcore: registered new interface driver usbfs
10496 22:22:10.145505 <6>[ 0.589227] usbcore: registered new interface driver hub
10497 22:22:10.148583 <6>[ 0.594780] usbcore: registered new device driver usb
10498 22:22:10.155845 <6>[ 0.600863] pps_core: LinuxPPS API ver. 1 registered
10499 22:22:10.166017 <6>[ 0.606054] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10500 22:22:10.168703 <6>[ 0.615401] PTP clock support registered
10501 22:22:10.172245 <6>[ 0.619642] EDAC MC: Ver: 3.0.0
10502 22:22:10.179650 <6>[ 0.624775] FPGA manager framework
10503 22:22:10.185977 <6>[ 0.628454] Advanced Linux Sound Architecture Driver Initialized.
10504 22:22:10.189384 <6>[ 0.635222] vgaarb: loaded
10505 22:22:10.196146 <6>[ 0.638398] clocksource: Switched to clocksource arch_sys_counter
10506 22:22:10.199371 <5>[ 0.644837] VFS: Disk quotas dquot_6.6.0
10507 22:22:10.205762 <6>[ 0.649019] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10508 22:22:10.209316 <6>[ 0.656208] pnp: PnP ACPI: disabled
10509 22:22:10.217709 <6>[ 0.662916] NET: Registered PF_INET protocol family
10510 22:22:10.227625 <6>[ 0.668513] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10511 22:22:10.238803 <6>[ 0.680817] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10512 22:22:10.249239 <6>[ 0.689630] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10513 22:22:10.255476 <6>[ 0.697597] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10514 22:22:10.265826 <6>[ 0.706291] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10515 22:22:10.271751 <6>[ 0.716029] TCP: Hash tables configured (established 65536 bind 65536)
10516 22:22:10.278689 <6>[ 0.722885] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10517 22:22:10.288570 <6>[ 0.730087] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10518 22:22:10.295255 <6>[ 0.737784] NET: Registered PF_UNIX/PF_LOCAL protocol family
10519 22:22:10.301524 <6>[ 0.743945] RPC: Registered named UNIX socket transport module.
10520 22:22:10.304833 <6>[ 0.750098] RPC: Registered udp transport module.
10521 22:22:10.311350 <6>[ 0.755029] RPC: Registered tcp transport module.
10522 22:22:10.317861 <6>[ 0.759960] RPC: Registered tcp NFSv4.1 backchannel transport module.
10523 22:22:10.321576 <6>[ 0.766628] PCI: CLS 0 bytes, default 64
10524 22:22:10.324546 <6>[ 0.770980] Unpacking initramfs...
10525 22:22:10.341082 <6>[ 0.783013] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10526 22:22:10.351181 <6>[ 0.791669] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10527 22:22:10.354256 <6>[ 0.800481] kvm [1]: IPA Size Limit: 40 bits
10528 22:22:10.360979 <6>[ 0.805011] kvm [1]: GICv3: no GICV resource entry
10529 22:22:10.364487 <6>[ 0.810031] kvm [1]: disabling GICv2 emulation
10530 22:22:10.370685 <6>[ 0.814719] kvm [1]: GIC system register CPU interface enabled
10531 22:22:10.374255 <6>[ 0.820885] kvm [1]: vgic interrupt IRQ18
10532 22:22:10.381018 <6>[ 0.825258] kvm [1]: VHE mode initialized successfully
10533 22:22:10.387592 <5>[ 0.831612] Initialise system trusted keyrings
10534 22:22:10.393819 <6>[ 0.836441] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10535 22:22:10.401214 <6>[ 0.846439] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10536 22:22:10.407948 <5>[ 0.852847] NFS: Registering the id_resolver key type
10537 22:22:10.411599 <5>[ 0.858170] Key type id_resolver registered
10538 22:22:10.417516 <5>[ 0.862592] Key type id_legacy registered
10539 22:22:10.424485 <6>[ 0.866874] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10540 22:22:10.431246 <6>[ 0.873796] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10541 22:22:10.437764 <6>[ 0.881549] 9p: Installing v9fs 9p2000 file system support
10542 22:22:10.474453 <5>[ 0.919278] Key type asymmetric registered
10543 22:22:10.477595 <5>[ 0.923615] Asymmetric key parser 'x509' registered
10544 22:22:10.487327 <6>[ 0.928764] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10545 22:22:10.490922 <6>[ 0.936377] io scheduler mq-deadline registered
10546 22:22:10.494128 <6>[ 0.941137] io scheduler kyber registered
10547 22:22:10.512513 <6>[ 0.957917] EINJ: ACPI disabled.
10548 22:22:10.544936 <4>[ 0.983269] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10549 22:22:10.554675 <4>[ 0.993881] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10550 22:22:10.569394 <6>[ 1.014660] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10551 22:22:10.577758 <6>[ 1.022682] printk: console [ttyS0] disabled
10552 22:22:10.606116 <6>[ 1.047333] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10553 22:22:10.612635 <6>[ 1.056808] printk: console [ttyS0] enabled
10554 22:22:10.615965 <6>[ 1.056808] printk: console [ttyS0] enabled
10555 22:22:10.622260 <6>[ 1.065708] printk: bootconsole [mtk8250] disabled
10556 22:22:10.625532 <6>[ 1.065708] printk: bootconsole [mtk8250] disabled
10557 22:22:10.632174 <6>[ 1.076978] SuperH (H)SCI(F) driver initialized
10558 22:22:10.635528 <6>[ 1.082258] msm_serial: driver initialized
10559 22:22:10.650124 <6>[ 1.091182] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10560 22:22:10.659736 <6>[ 1.099731] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10561 22:22:10.666269 <6>[ 1.108276] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10562 22:22:10.676181 <6>[ 1.116905] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10563 22:22:10.686181 <6>[ 1.125610] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10564 22:22:10.692770 <6>[ 1.134332] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10565 22:22:10.702494 <6>[ 1.142874] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10566 22:22:10.708908 <6>[ 1.151686] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10567 22:22:10.719036 <6>[ 1.160232] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10568 22:22:10.731159 <6>[ 1.175907] loop: module loaded
10569 22:22:10.737721 <6>[ 1.181926] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10570 22:22:10.760462 <4>[ 1.205362] mtk-pmic-keys: Failed to locate of_node [id: -1]
10571 22:22:10.767104 <6>[ 1.212199] megasas: 07.719.03.00-rc1
10572 22:22:10.776879 <6>[ 1.221637] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10573 22:22:10.784842 <6>[ 1.229800] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10574 22:22:10.801962 <6>[ 1.246508] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10575 22:22:10.862432 <6>[ 1.300644] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10576 22:22:11.054506 <6>[ 1.499550] Freeing initrd memory: 17224K
10577 22:22:11.065065 <6>[ 1.509605] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10578 22:22:11.075703 <6>[ 1.520682] tun: Universal TUN/TAP device driver, 1.6
10579 22:22:11.079235 <6>[ 1.526756] thunder_xcv, ver 1.0
10580 22:22:11.082579 <6>[ 1.530251] thunder_bgx, ver 1.0
10581 22:22:11.085959 <6>[ 1.533749] nicpf, ver 1.0
10582 22:22:11.096250 <6>[ 1.537741] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10583 22:22:11.099825 <6>[ 1.545217] hns3: Copyright (c) 2017 Huawei Corporation.
10584 22:22:11.106480 <6>[ 1.550807] hclge is initializing
10585 22:22:11.109514 <6>[ 1.554378] e1000: Intel(R) PRO/1000 Network Driver
10586 22:22:11.116227 <6>[ 1.559508] e1000: Copyright (c) 1999-2006 Intel Corporation.
10587 22:22:11.119291 <6>[ 1.565520] e1000e: Intel(R) PRO/1000 Network Driver
10588 22:22:11.125836 <6>[ 1.570735] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10589 22:22:11.132896 <6>[ 1.576922] igb: Intel(R) Gigabit Ethernet Network Driver
10590 22:22:11.139500 <6>[ 1.582572] igb: Copyright (c) 2007-2014 Intel Corporation.
10591 22:22:11.146074 <6>[ 1.588409] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10592 22:22:11.152676 <6>[ 1.594927] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10593 22:22:11.155875 <6>[ 1.601388] sky2: driver version 1.30
10594 22:22:11.162478 <6>[ 1.606375] VFIO - User Level meta-driver version: 0.3
10595 22:22:11.169906 <6>[ 1.614573] usbcore: registered new interface driver usb-storage
10596 22:22:11.176694 <6>[ 1.621015] usbcore: registered new device driver onboard-usb-hub
10597 22:22:11.185400 <6>[ 1.630116] mt6397-rtc mt6359-rtc: registered as rtc0
10598 22:22:11.195102 <6>[ 1.635579] mt6397-rtc mt6359-rtc: setting system clock to 2023-06-05T22:22:15 UTC (1686003735)
10599 22:22:11.198421 <6>[ 1.645163] i2c_dev: i2c /dev entries driver
10600 22:22:11.215541 <6>[ 1.656863] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10601 22:22:11.222108 <6>[ 1.667085] sdhci: Secure Digital Host Controller Interface driver
10602 22:22:11.228719 <6>[ 1.673522] sdhci: Copyright(c) Pierre Ossman
10603 22:22:11.235341 <6>[ 1.678918] Synopsys Designware Multimedia Card Interface Driver
10604 22:22:11.238874 <6>[ 1.685517] mmc0: CQHCI version 5.10
10605 22:22:11.244978 <6>[ 1.686077] sdhci-pltfm: SDHCI platform and OF driver helper
10606 22:22:11.252645 <6>[ 1.697465] ledtrig-cpu: registered to indicate activity on CPUs
10607 22:22:11.263245 <6>[ 1.704793] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10608 22:22:11.269730 <6>[ 1.712177] usbcore: registered new interface driver usbhid
10609 22:22:11.272999 <6>[ 1.718008] usbhid: USB HID core driver
10610 22:22:11.279596 <6>[ 1.722254] spi_master spi0: will run message pump with realtime priority
10611 22:22:11.326567 <6>[ 1.765159] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10612 22:22:11.346346 <6>[ 1.780561] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10613 22:22:11.349672 <6>[ 1.794146] mmc0: Command Queue Engine enabled
10614 22:22:11.356179 <6>[ 1.795812] cros-ec-spi spi0.0: Chrome EC device registered
10615 22:22:11.362958 <6>[ 1.798891] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10616 22:22:11.366156 <6>[ 1.812103] mmcblk0: mmc0:0001 DA4128 116 GiB
10617 22:22:11.377189 <6>[ 1.822019] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10618 22:22:11.387261 <6>[ 1.822643] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10619 22:22:11.394157 <6>[ 1.829366] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10620 22:22:11.396892 <6>[ 1.839300] NET: Registered PF_PACKET protocol family
10621 22:22:11.403657 <6>[ 1.843142] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10622 22:22:11.407168 <6>[ 1.847886] 9pnet: Installing 9P2000 support
10623 22:22:11.413643 <6>[ 1.853697] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10624 22:22:11.420105 <5>[ 1.857577] Key type dns_resolver registered
10625 22:22:11.423177 <6>[ 1.869273] registered taskstats version 1
10626 22:22:11.429996 <5>[ 1.873674] Loading compiled-in X.509 certificates
10627 22:22:11.462335 <4>[ 1.900334] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10628 22:22:11.472473 <4>[ 1.911044] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10629 22:22:11.482575 <3>[ 1.923921] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10630 22:22:11.494517 <6>[ 1.939614] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10631 22:22:11.501782 <6>[ 1.946398] xhci-mtk 11200000.usb: xHCI Host Controller
10632 22:22:11.508539 <6>[ 1.951893] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10633 22:22:11.518441 <6>[ 1.959832] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10634 22:22:11.524649 <6>[ 1.969301] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10635 22:22:11.531513 <6>[ 1.975387] xhci-mtk 11200000.usb: xHCI Host Controller
10636 22:22:11.538263 <6>[ 1.980873] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10637 22:22:11.544792 <6>[ 1.988524] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10638 22:22:11.551482 <6>[ 1.996425] hub 1-0:1.0: USB hub found
10639 22:22:11.555320 <6>[ 2.000475] hub 1-0:1.0: 1 port detected
10640 22:22:11.564562 <6>[ 2.004830] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10641 22:22:11.567793 <6>[ 2.013626] hub 2-0:1.0: USB hub found
10642 22:22:11.571542 <6>[ 2.017686] hub 2-0:1.0: 1 port detected
10643 22:22:11.579962 <6>[ 2.024981] mtk-msdc 11f70000.mmc: Got CD GPIO
10644 22:22:11.598051 <6>[ 2.039663] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10645 22:22:11.604626 <6>[ 2.047707] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10646 22:22:11.614899 <4>[ 2.055674] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10647 22:22:11.624424 <6>[ 2.065343] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10648 22:22:11.631508 <6>[ 2.073426] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10649 22:22:11.638069 <6>[ 2.081463] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10650 22:22:11.648280 <6>[ 2.089379] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10651 22:22:11.654800 <6>[ 2.097200] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10652 22:22:11.664498 <6>[ 2.105021] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10653 22:22:11.674202 <6>[ 2.115747] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10654 22:22:11.684483 <6>[ 2.124117] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10655 22:22:11.691100 <6>[ 2.132462] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10656 22:22:11.700677 <6>[ 2.140806] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10657 22:22:11.707172 <6>[ 2.149148] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10658 22:22:11.717700 <6>[ 2.157496] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10659 22:22:11.724497 <6>[ 2.165839] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10660 22:22:11.734266 <6>[ 2.174181] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10661 22:22:11.740636 <6>[ 2.182525] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10662 22:22:11.750712 <6>[ 2.190868] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10663 22:22:11.757584 <6>[ 2.199212] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10664 22:22:11.767257 <6>[ 2.207556] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10665 22:22:11.773715 <6>[ 2.215903] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10666 22:22:11.783964 <6>[ 2.224249] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10667 22:22:11.790567 <6>[ 2.232597] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10668 22:22:11.796820 <6>[ 2.241443] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10669 22:22:11.803887 <6>[ 2.248885] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10670 22:22:11.811079 <6>[ 2.255918] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10671 22:22:11.821239 <6>[ 2.263013] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10672 22:22:11.827916 <6>[ 2.270279] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10673 22:22:11.837920 <6>[ 2.277180] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10674 22:22:11.844446 <6>[ 2.286321] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10675 22:22:11.854685 <6>[ 2.295448] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10676 22:22:11.864383 <6>[ 2.304749] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10677 22:22:11.874216 <6>[ 2.314223] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10678 22:22:11.884098 <6>[ 2.323697] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10679 22:22:11.894256 <6>[ 2.332824] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10680 22:22:11.900528 <6>[ 2.342300] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10681 22:22:11.910930 <6>[ 2.351427] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10682 22:22:11.920748 <6>[ 2.360730] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10683 22:22:11.930138 <6>[ 2.370896] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10684 22:22:11.940869 <6>[ 2.382385] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10685 22:22:11.947165 <6>[ 2.392102] Trying to probe devices needed for running init ...
10686 22:22:11.961092 <6>[ 2.402679] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10687 22:22:11.988492 <6>[ 2.433192] hub 2-1:1.0: USB hub found
10688 22:22:11.991507 <6>[ 2.437604] hub 2-1:1.0: 3 ports detected
10689 22:22:12.113525 <6>[ 2.554669] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10690 22:22:12.267240 <6>[ 2.712246] hub 1-1:1.0: USB hub found
10691 22:22:12.270491 <6>[ 2.716690] hub 1-1:1.0: 4 ports detected
10692 22:22:12.349374 <6>[ 2.790918] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10693 22:22:12.592771 <6>[ 3.034676] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10694 22:22:12.726294 <6>[ 3.170952] hub 1-1.4:1.0: USB hub found
10695 22:22:12.729297 <6>[ 3.175603] hub 1-1.4:1.0: 2 ports detected
10696 22:22:13.024831 <6>[ 3.466671] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10697 22:22:13.216298 <6>[ 3.658673] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10698 22:22:24.249962 <6>[ 14.699267] ALSA device list:
10699 22:22:24.256042 <6>[ 14.702519] No soundcards found.
10700 22:22:24.268432 <6>[ 14.714944] Freeing unused kernel memory: 8384K
10701 22:22:24.271831 <6>[ 14.719876] Run /init as init process
10702 22:22:24.282989 Loading, please wait...
10703 22:22:24.303219 Starting version 247.3-7+deb11u2
10704 22:22:24.620992 <6>[ 15.063898] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10705 22:22:24.631377 <6>[ 15.077282] remoteproc remoteproc0: scp is available
10706 22:22:24.641185 <4>[ 15.083149] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10707 22:22:24.647955 <6>[ 15.093024] remoteproc remoteproc0: powering up scp
10708 22:22:24.657780 <4>[ 15.098211] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10709 22:22:24.664246 <3>[ 15.108243] remoteproc remoteproc0: request_firmware failed: -2
10710 22:22:24.670661 <3>[ 15.111377] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10711 22:22:24.683903 <6>[ 15.126858] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10712 22:22:24.690214 <3>[ 15.127455] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10713 22:22:24.696884 <6>[ 15.138583] mc: Linux media interface: v0.10
10714 22:22:24.703675 <6>[ 15.142464] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10715 22:22:24.713664 <6>[ 15.142502] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10716 22:22:24.720355 <6>[ 15.142516] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10717 22:22:24.730251 <3>[ 15.142701] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10718 22:22:24.736771 <4>[ 15.152428] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10719 22:22:24.743614 <4>[ 15.152428] Fallback method does not support PEC.
10720 22:22:24.747008 <6>[ 15.173897] videodev: Linux video capture interface: v2.00
10721 22:22:24.756421 <4>[ 15.185896] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10722 22:22:24.763220 <3>[ 15.187728] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10723 22:22:24.772742 <3>[ 15.187752] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10724 22:22:24.779574 <3>[ 15.187761] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10725 22:22:24.786374 <3>[ 15.187774] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10726 22:22:24.796220 <3>[ 15.187782] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10727 22:22:24.802718 <3>[ 15.187900] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10728 22:22:24.813104 <3>[ 15.188333] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10729 22:22:24.819925 <3>[ 15.188347] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10730 22:22:24.829325 <3>[ 15.188354] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10731 22:22:24.835974 <3>[ 15.188607] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10732 22:22:24.846069 <3>[ 15.188617] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10733 22:22:24.852462 <3>[ 15.188623] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10734 22:22:24.862466 <3>[ 15.188630] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10735 22:22:24.869815 <3>[ 15.188637] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10736 22:22:24.876528 <3>[ 15.188665] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10737 22:22:24.882761 <6>[ 15.201143] usbcore: registered new interface driver r8152
10738 22:22:24.889410 <4>[ 15.207227] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10739 22:22:24.899420 <3>[ 15.215437] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10740 22:22:24.909098 <6>[ 15.256148] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10741 22:22:24.915609 <6>[ 15.263766] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10742 22:22:24.922272 <6>[ 15.263776] pci_bus 0000:00: root bus resource [bus 00-ff]
10743 22:22:24.932471 <6>[ 15.272420] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10744 22:22:24.938522 <6>[ 15.280009] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10745 22:22:24.948963 <6>[ 15.280016] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10746 22:22:24.955260 <6>[ 15.280053] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10747 22:22:24.962121 <6>[ 15.298646] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10748 22:22:24.968725 <6>[ 15.304281] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10749 22:22:24.978398 <3>[ 15.321129] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10750 22:22:24.981580 <6>[ 15.328606] pci 0000:00:00.0: supports D1 D2
10751 22:22:24.991445 <4>[ 15.333832] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10752 22:22:24.998236 <4>[ 15.333841] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10753 22:22:25.008073 <6>[ 15.342805] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10754 22:22:25.014787 <6>[ 15.350385] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10755 22:22:25.021270 <6>[ 15.382524] usbcore: registered new interface driver cdc_ether
10756 22:22:25.031058 <6>[ 15.393023] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10757 22:22:25.034303 <6>[ 15.406377] usbcore: registered new interface driver r8153_ecm
10758 22:22:25.041355 <6>[ 15.406415] Bluetooth: Core ver 2.22
10759 22:22:25.044500 <6>[ 15.406503] NET: Registered PF_BLUETOOTH protocol family
10760 22:22:25.050668 <6>[ 15.406506] Bluetooth: HCI device and connection manager initialized
10761 22:22:25.057142 <6>[ 15.406616] Bluetooth: HCI socket layer initialized
10762 22:22:25.060701 <6>[ 15.406632] Bluetooth: L2CAP socket layer initialized
10763 22:22:25.067697 <6>[ 15.406686] Bluetooth: SCO socket layer initialized
10764 22:22:25.070594 <6>[ 15.410542] r8152 2-1.3:1.0 eth0: v1.12.13
10765 22:22:25.077659 <6>[ 15.412885] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10766 22:22:25.083376 <6>[ 15.422422] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10767 22:22:25.093785 <6>[ 15.429005] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10768 22:22:25.100327 <6>[ 15.429986] r8152 2-1.3:1.0 enx0024323078ff: renamed from eth0
10769 22:22:25.110477 <6>[ 15.435131] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10770 22:22:25.120012 <6>[ 15.442567] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10771 22:22:25.123433 <6>[ 15.450941] usbcore: registered new interface driver uvcvideo
10772 22:22:25.129640 <6>[ 15.451451] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10773 22:22:25.140019 <6>[ 15.459970] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10774 22:22:25.143016 <6>[ 15.460483] usbcore: registered new interface driver btusb
10775 22:22:25.156360 <4>[ 15.461250] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10776 22:22:25.159691 <3>[ 15.461258] Bluetooth: hci0: Failed to load firmware file (-2)
10777 22:22:25.166429 <3>[ 15.461263] Bluetooth: hci0: Failed to set up firmware (-2)
10778 22:22:25.176373 <4>[ 15.461267] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10779 22:22:25.182621 <6>[ 15.628532] pci 0000:01:00.0: supports D1 D2
10780 22:22:25.189319 <6>[ 15.633061] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10781 22:22:25.207614 <6>[ 15.650658] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10782 22:22:25.214210 <6>[ 15.657572] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10783 22:22:25.220977 <6>[ 15.665665] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10784 22:22:25.230871 <6>[ 15.673670] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10785 22:22:25.237367 <6>[ 15.681677] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10786 22:22:25.247246 <6>[ 15.689683] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10787 22:22:25.250302 <6>[ 15.697690] pci 0000:00:00.0: PCI bridge to [bus 01]
10788 22:22:25.260565 <6>[ 15.702911] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10789 22:22:25.266995 <6>[ 15.711074] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10790 22:22:25.273454 <6>[ 15.718299] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10791 22:22:25.280381 <6>[ 15.725026] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10792 22:22:25.297149 <5>[ 15.740593] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10793 22:22:25.315566 <5>[ 15.758812] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10794 22:22:25.322267 <4>[ 15.765699] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10795 22:22:25.328910 <6>[ 15.774582] cfg80211: failed to load regulatory.db
10796 22:22:25.377962 <6>[ 15.821010] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10797 22:22:25.384306 <6>[ 15.828520] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10798 22:22:25.408578 <6>[ 15.855208] mt7921e 0000:01:00.0: ASIC revision: 79610010
10799 22:22:25.514419 <4>[ 15.954227] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10800 22:22:25.522506 Begin: Loading essential drivers ... done.
10801 22:22:25.526200 Begin: Running /scripts/init-premount ... done.
10802 22:22:25.536092 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10803 22:22:25.542808 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10804 22:22:25.545959 Device /sys/class/net/enx0024323078ff found
10805 22:22:25.548975 done.
10806 22:22:25.611639 IP-Config: enx0024323078ff hardware address 00:24:32:30:78:ff mtu 1500 DHCP
10807 22:22:25.637024 <4>[ 16.076809] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10808 22:22:25.756219 <4>[ 16.196400] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10809 22:22:25.872212 <4>[ 16.312202] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10810 22:22:25.988019 <4>[ 16.428193] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10811 22:22:26.104032 <4>[ 16.543998] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10812 22:22:26.220005 <4>[ 16.660091] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10813 22:22:26.335238 <4>[ 16.775831] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10814 22:22:26.451546 <4>[ 16.891897] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10815 22:22:26.567936 <4>[ 17.008065] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10816 22:22:26.624475 <6>[ 17.070795] r8152 2-1.3:1.0 enx0024323078ff: carrier on
10817 22:22:26.675504 <3>[ 17.121965] mt7921e 0000:01:00.0: hardware init failed
10818 22:22:26.689330 IP-Config: no response after 2 secs - giving up
10819 22:22:26.731864 IP-Config: enx0024323078ff hardware address 00:24:32:30:78:ff mtu 1500 DHCP
10820 22:22:26.734767 IP-Config: enx0024323078ff complete (dhcp from 192.168.201.1):
10821 22:22:26.741588 address: 192.168.201.21 broadcast: 192.168.201.255 netmask: 255.255.255.0
10822 22:22:26.751275 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10823 22:22:26.757834 host : mt8192-asurada-spherion-r0-cbg-8
10824 22:22:26.764457 domain : lava-rack
10825 22:22:26.767750 rootserver: 192.168.201.1 rootpath:
10826 22:22:26.768175 filename :
10827 22:22:26.837809 done.
10828 22:22:26.847419 Begin: Running /scripts/nfs-bottom ... done.
10829 22:22:26.865556 Begin: Running /scripts/init-bottom ... done.
10830 22:22:28.015330 <6>[ 18.462544] NET: Registered PF_INET6 protocol family
10831 22:22:28.022714 <6>[ 18.469635] Segment Routing with IPv6
10832 22:22:28.025603 <6>[ 18.473592] In-situ OAM (IOAM) with IPv6
10833 22:22:28.143494 <30>[ 18.570748] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10834 22:22:28.146466 <30>[ 18.594582] systemd[1]: Detected architecture arm64.
10835 22:22:28.167896
10836 22:22:28.171292 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10837 22:22:28.171383
10838 22:22:28.186121 <30>[ 18.633377] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10839 22:22:28.789452 <30>[ 19.233486] systemd[1]: Queued start job for default target Graphical Interface.
10840 22:22:28.812638 <30>[ 19.259676] systemd[1]: Created slice system-getty.slice.
10841 22:22:28.819416 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10842 22:22:28.836273 <30>[ 19.283378] systemd[1]: Created slice system-modprobe.slice.
10843 22:22:28.842694 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10844 22:22:28.861219 <30>[ 19.307828] systemd[1]: Created slice system-serial\x2dgetty.slice.
10845 22:22:28.870781 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10846 22:22:28.884317 <30>[ 19.331201] systemd[1]: Created slice User and Session Slice.
10847 22:22:28.890810 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10848 22:22:28.911840 <30>[ 19.355243] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10849 22:22:28.921519 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10850 22:22:28.939463 <30>[ 19.383196] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10851 22:22:28.945973 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10852 22:22:28.966477 <30>[ 19.406757] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10853 22:22:28.972673 <30>[ 19.418801] systemd[1]: Reached target Local Encrypted Volumes.
10854 22:22:28.979436 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10855 22:22:28.996086 <30>[ 19.443036] systemd[1]: Reached target Paths.
10856 22:22:28.999295 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10857 22:22:29.015701 <30>[ 19.462727] systemd[1]: Reached target Remote File Systems.
10858 22:22:29.022426 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10859 22:22:29.040008 <30>[ 19.486956] systemd[1]: Reached target Slices.
10860 22:22:29.046256 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10861 22:22:29.059509 <30>[ 19.506738] systemd[1]: Reached target Swap.
10862 22:22:29.063088 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10863 22:22:29.083208 <30>[ 19.527045] systemd[1]: Listening on initctl Compatibility Named Pipe.
10864 22:22:29.089615 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10865 22:22:29.096232 <30>[ 19.542581] systemd[1]: Listening on Journal Audit Socket.
10866 22:22:29.102775 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10867 22:22:29.116771 <30>[ 19.563794] systemd[1]: Listening on Journal Socket (/dev/log).
10868 22:22:29.123090 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10869 22:22:29.140444 <30>[ 19.587544] systemd[1]: Listening on Journal Socket.
10870 22:22:29.147127 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10871 22:22:29.164620 <30>[ 19.608106] systemd[1]: Listening on Network Service Netlink Socket.
10872 22:22:29.170499 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10873 22:22:29.186737 <30>[ 19.633694] systemd[1]: Listening on udev Control Socket.
10874 22:22:29.193337 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10875 22:22:29.208054 <30>[ 19.654989] systemd[1]: Listening on udev Kernel Socket.
10876 22:22:29.214589 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10877 22:22:29.263844 <30>[ 19.711058] systemd[1]: Mounting Huge Pages File System...
10878 22:22:29.270243 Mounting [0;1;39mHuge Pages File System[0m...
10879 22:22:29.285883 <30>[ 19.733203] systemd[1]: Mounting POSIX Message Queue File System...
10880 22:22:29.292557 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10881 22:22:29.309761 <30>[ 19.757032] systemd[1]: Mounting Kernel Debug File System...
10882 22:22:29.316527 Mounting [0;1;39mKernel Debug File System[0m...
10883 22:22:29.334719 <30>[ 19.778870] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10884 22:22:29.347767 <30>[ 19.791213] systemd[1]: Starting Create list of static device nodes for the current kernel...
10885 22:22:29.353896 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10886 22:22:29.374281 <30>[ 19.821437] systemd[1]: Starting Load Kernel Module configfs...
10887 22:22:29.381037 Starting [0;1;39mLoad Kernel Module configfs[0m...
10888 22:22:29.398512 <30>[ 19.845331] systemd[1]: Starting Load Kernel Module drm...
10889 22:22:29.404704 Starting [0;1;39mLoad Kernel Module drm[0m...
10890 22:22:29.421937 <30>[ 19.869282] systemd[1]: Starting Load Kernel Module fuse...
10891 22:22:29.428906 Starting [0;1;39mLoad Kernel Module fuse[0m...
10892 22:22:29.462855 <6>[ 19.910251] fuse: init (API version 7.37)
10893 22:22:29.473346 <30>[ 19.910557] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10894 22:22:29.504118 <30>[ 19.951300] systemd[1]: Starting Journal Service...
10895 22:22:29.507594 Starting [0;1;39mJournal Service[0m...
10896 22:22:29.532518 <30>[ 19.980011] systemd[1]: Starting Load Kernel Modules...
10897 22:22:29.539153 Starting [0;1;39mLoad Kernel Modules[0m...
10898 22:22:29.561957 <30>[ 20.006009] systemd[1]: Starting Remount Root and Kernel File Systems...
10899 22:22:29.568323 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10900 22:22:29.588489 <30>[ 20.035607] systemd[1]: Starting Coldplug All udev Devices...
10901 22:22:29.595551 Starting [0;1;39mColdplug All udev Devices[0m...
10902 22:22:29.619048 <30>[ 20.066244] systemd[1]: Mounted Huge Pages File System.
10903 22:22:29.625757 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10904 22:22:29.643767 <30>[ 20.091038] systemd[1]: Mounted POSIX Message Queue File System.
10905 22:22:29.650650 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10906 22:22:29.668363 <30>[ 20.115142] systemd[1]: Mounted Kernel Debug File System.
10907 22:22:29.678276 [[0;32m OK [<3>[ 20.122219] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10908 22:22:29.684483 0m] Mounted [0;1;39mKernel Debug File System[0m.
10909 22:22:29.703945 <30>[ 20.147824] systemd[1]: Finished Create list of static device nodes for the current kernel.
10910 22:22:29.714712 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10911 22:22:29.720715 <3>[ 20.164814] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10912 22:22:29.732212 <30>[ 20.179506] systemd[1]: modprobe@configfs.service: Succeeded.
10913 22:22:29.739470 <30>[ 20.186486] systemd[1]: Finished Load Kernel Module configfs.
10914 22:22:29.746081 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10915 22:22:29.764319 <30>[ 20.211416] systemd[1]: modprobe@drm.service: Succeeded.
10916 22:22:29.770974 <30>[ 20.217850] systemd[1]: Finished Load Kernel Module drm.
10917 22:22:29.781286 [[0;32m OK [<3>[ 20.224954] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10918 22:22:29.787302 0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10919 22:22:29.810682 <3>[ 20.254664] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10920 22:22:29.817787 <30>[ 20.255683] systemd[1]: modprobe@fuse.service: Succeeded.
10921 22:22:29.824487 <30>[ 20.270129] systemd[1]: Finished Load Kernel Module fuse.
10922 22:22:29.830480 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module fuse[0m.
10923 22:22:29.844992 <30>[ 20.291661] systemd[1]: Finished Load Kernel Modules.
10924 22:22:29.854731 <3>[ 20.294587] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10925 22:22:29.857758 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10926 22:22:29.876219 <30>[ 20.319601] systemd[1]: Finished Remount Root and Kernel File Systems.
10927 22:22:29.886102 [[0;32m OK [<3>[ 20.327258] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10928 22:22:29.889365 0m] Finished [0;1;39mRemount Root and Kernel File Systems[0m.
10929 22:22:29.913965 <3>[ 20.358146] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10930 22:22:29.940428 <30>[ 20.387762] systemd[1]: Mounting FUSE Control File System...
10931 22:22:29.950533 <3>[ 20.393974] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10932 22:22:29.957177 Mounting [0;1;39mFUSE Control File System[0m...
10933 22:22:29.973935 <30>[ 20.421308] systemd[1]: Mounting Kernel Configuration File System...
10934 22:22:29.984122 <3>[ 20.424093] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10935 22:22:29.990585 Mounting [0;1;39mKernel Configuration File System[0m...
10936 22:22:30.014002 <3>[ 20.457306] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10937 22:22:30.023139 <30>[ 20.460933] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped.
10938 22:22:30.033741 <30>[ 20.475092] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped.
10939 22:22:30.043388 <3>[ 20.486620] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10940 22:22:30.063867 <30>[ 20.511219] systemd[1]: Starting Load/Save Random Seed...
10941 22:22:30.073932 <3>[ 20.515829] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10942 22:22:30.077244 Starting [0;1;39mLoad/Save Random Seed[0m...
10943 22:22:30.096387 <30>[ 20.543695] systemd[1]: Starting Apply Kernel Variables...
10944 22:22:30.103424 Starting [0;1;39mApply Kernel Variables[0m...
10945 22:22:30.118794 <30>[ 20.566120] systemd[1]: Starting Create System Users...
10946 22:22:30.125394 Starting [0;1;39mCreate System Users[0m...
10947 22:22:30.144695 <30>[ 20.592198] systemd[1]: Started Journal Service.
10948 22:22:30.152080 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10949 22:22:30.168452 <4>[ 20.605458] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10950 22:22:30.175064 <3>[ 20.621125] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10951 22:22:30.182109 [[0;32m OK [0m] Mounted [0;1;39mFUSE Control File System[0m.
10952 22:22:30.200217 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10953 22:22:30.220298 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10954 22:22:30.235354 See 'systemctl status systemd-udev-trigger.service' for details.
10955 22:22:30.252550 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10956 22:22:30.272386 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10957 22:22:30.288379 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10958 22:22:30.328120 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10959 22:22:30.345986 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10960 22:22:30.390229 <46>[ 20.834230] systemd-journald[298]: Received client request to flush runtime journal.
10961 22:22:30.870180 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10962 22:22:30.887474 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10963 22:22:30.903491 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10964 22:22:30.951085 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10965 22:22:31.761075 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10966 22:22:31.792801 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10967 22:22:31.852460 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10968 22:22:31.913436 Starting [0;1;39mNetwork Service[0m...
10969 22:22:32.191612 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10970 22:22:32.212068 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10971 22:22:32.275710 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10972 22:22:32.463290 <6>[ 22.911107] remoteproc remoteproc0: powering up scp
10973 22:22:32.488692 <4>[ 22.933071] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10974 22:22:32.495633 <3>[ 22.942984] remoteproc remoteproc0: request_firmware failed: -2
10975 22:22:32.505331 <3>[ 22.949167] fops_vcodec_open(),166: [MTK_V4L2][ERROR] vpu_load_firmware failed!
10976 22:22:32.603212 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10977 22:22:32.642726 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10978 22:22:32.659944 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10979 22:22:32.703521 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10980 22:22:32.726635 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10981 22:22:32.771372 Starting [0;1;39mNetwork Name Resolution[0m...
10982 22:22:32.799479 Starting [0;1;39mNetwork Time Synchronization[0m...
10983 22:22:32.817561 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10984 22:22:32.838552 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10985 22:22:32.941540 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10986 22:22:32.964574 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10987 22:22:33.017243 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10988 22:22:33.031577 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10989 22:22:33.050759 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10990 22:22:33.063341 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10991 22:22:33.079333 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10992 22:22:33.245670 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
10993 22:22:33.275000 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
10994 22:22:33.479748 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
10995 22:22:34.014730 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10996 22:22:34.027086 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10997 22:22:34.049344 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10998 22:22:34.063213 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10999 22:22:34.083232 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
11000 22:22:34.119728 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
11001 22:22:34.423265 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
11002 22:22:34.499448 Starting [0;1;39mUser Login Management[0m...
11003 22:22:34.516096 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
11004 22:22:34.536448 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
11005 22:22:34.554428 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
11006 22:22:34.583400 Starting [0;1;39mPermit User Sessions[0m...
11007 22:22:34.672621 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
11008 22:22:34.722432 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
11009 22:22:34.760684 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
11010 22:22:34.803990 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
11011 22:22:34.819652 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
11012 22:22:34.836449 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
11013 22:22:34.852129 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
11014 22:22:34.867376 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
11015 22:22:34.907056 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
11016 22:22:34.946783 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
11017 22:22:35.044253
11018 22:22:35.044432
11019 22:22:35.047121 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
11020 22:22:35.047247
11021 22:22:35.050671 debian-bullseye-arm64 login: root (automatic login)
11022 22:22:35.050773
11023 22:22:35.050889
11024 22:22:35.375974 Linux debian-bullseye-arm64 6.1.31 #1 SMP PREEMPT Mon Jun 5 22:04:07 UTC 2023 aarch64
11025 22:22:35.376146
11026 22:22:35.382765 The programs included with the Debian GNU/Linux system are free software;
11027 22:22:35.389356 the exact distribution terms for each program are described in the
11028 22:22:35.392609 individual files in /usr/share/doc/*/copyright.
11029 22:22:35.392733
11030 22:22:35.399482 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11031 22:22:35.402514 permitted by applicable law.
11032 22:22:36.233569 Matched prompt #10: / #
11034 22:22:36.233838 Setting prompt string to ['/ #']
11035 22:22:36.233932 end: 2.2.5.1 login-action (duration 00:00:27) [common]
11037 22:22:36.234128 end: 2.2.5 auto-login-action (duration 00:00:28) [common]
11038 22:22:36.234218 start: 2.2.6 expect-shell-connection (timeout 00:03:12) [common]
11039 22:22:36.234296 Setting prompt string to ['/ #']
11040 22:22:36.234358 Forcing a shell prompt, looking for ['/ #']
11042 22:22:36.284550 / #
11043 22:22:36.284673 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11044 22:22:36.284751 Waiting using forced prompt support (timeout 00:02:30)
11045 22:22:36.289674
11046 22:22:36.289954 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11047 22:22:36.290047 start: 2.2.7 export-device-env (timeout 00:03:12) [common]
11049 22:22:36.390410 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/10597300/extract-nfsrootfs-cj0nalzp'
11050 22:22:36.395841 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/10597300/extract-nfsrootfs-cj0nalzp'
11052 22:22:36.496388 / # export NFS_SERVER_IP='192.168.201.1'
11053 22:22:36.501190 export NFS_SERVER_IP='192.168.201.1'
11054 22:22:36.501481 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11055 22:22:36.501582 end: 2.2 depthcharge-retry (duration 00:01:48) [common]
11056 22:22:36.501678 end: 2 depthcharge-action (duration 00:01:48) [common]
11057 22:22:36.501770 start: 3 lava-test-retry (timeout 00:07:31) [common]
11058 22:22:36.501858 start: 3.1 lava-test-shell (timeout 00:07:31) [common]
11059 22:22:36.501932 Using namespace: common
11061 22:22:36.602271 / # #
11062 22:22:36.602419 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11063 22:22:36.607274 #
11064 22:22:36.607542 Using /lava-10597300
11066 22:22:36.707871 / # export SHELL=/bin/bash
11067 22:22:36.713139 export SHELL=/bin/bash
11069 22:22:36.813658 / # . /lava-10597300/environment
11070 22:22:36.818454 . /lava-10597300/environment
11072 22:22:36.924388 / # /lava-10597300/bin/lava-test-runner /lava-10597300/0
11073 22:22:36.924531 Test shell timeout: 10s (minimum of the action and connection timeout)
11074 22:22:36.929698 /lava-10597300/bin/lava-test-runner /lava-10597300/0
11075 22:22:37.225044 + export TESTRUN_ID=0_timesync-off
11076 22:22:37.228720 + TESTRUN_ID=0_timesync-off
11077 22:22:37.231705 + cd /lava-10597300/0/tests/0_timesync-off
11078 22:22:37.235372 ++ cat uuid
11079 22:22:37.245227 + UUID=10597300_1.6.2.3.1
11080 22:22:37.245305 + set +x
11081 22:22:37.251671 <LAVA_SIGNAL_STARTRUN 0_timesync-off 10597300_1.6.2.3.1>
11082 22:22:37.251950 Received signal: <STARTRUN> 0_timesync-off 10597300_1.6.2.3.1
11083 22:22:37.252024 Starting test lava.0_timesync-off (10597300_1.6.2.3.1)
11084 22:22:37.252115 Skipping test definition patterns.
11085 22:22:37.255085 + systemctl stop systemd-timesyncd
11086 22:22:37.304380 + set +x
11087 22:22:37.307619 <LAVA_SIGNAL_ENDRUN 0_timesync-off 10597300_1.6.2.3.1>
11088 22:22:37.307877 Received signal: <ENDRUN> 0_timesync-off 10597300_1.6.2.3.1
11089 22:22:37.307964 Ending use of test pattern.
11090 22:22:37.308028 Ending test lava.0_timesync-off (10597300_1.6.2.3.1), duration 0.06
11092 22:22:37.388659 + export TESTRUN_ID=1_kselftest-rtc
11093 22:22:37.391612 + TESTRUN_ID=1_kselftest-rtc
11094 22:22:37.395259 + cd /lava-10597300/0/tests/1_kselftest-rtc
11095 22:22:37.398571 ++ cat uuid
11096 22:22:37.403492 + UUID=10597300_1.6.2.3.5
11097 22:22:37.403571 + set +x
11098 22:22:37.410135 <LAVA_SIGNAL_STARTRUN 1_kselftest-rtc 10597300_1.6.2.3.5>
11099 22:22:37.410388 Received signal: <STARTRUN> 1_kselftest-rtc 10597300_1.6.2.3.5
11100 22:22:37.410489 Starting test lava.1_kselftest-rtc (10597300_1.6.2.3.5)
11101 22:22:37.410609 Skipping test definition patterns.
11102 22:22:37.413077 + cd ./automated/linux/kselftest/
11103 22:22:37.439497 + ./kselftest.sh -c rtc -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1314-g1ab0ac1d7e2e3/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip-gitlab -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11104 22:22:37.473887 INFO: install_deps skipped
11105 22:22:37.594107 --2023-06-05 22:22:37-- http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1314-g1ab0ac1d7e2e3/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11106 22:22:37.600386 Resolving storage.kernelci.org (storage.kernelci.org)... 52.250.1.28
11107 22:22:37.748860 Connecting to storage.kernelci.org (storage.kernelci.org)|52.250.1.28|:80... connected.
11108 22:22:37.898912 HTTP request sent, awaiting response... 200 OK
11109 22:22:37.902310 Length: 2860080 (2.7M) [application/octet-stream]
11110 22:22:37.905764 Saving to: 'kselftest.tar.xz'
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11117 22:22:39.169134 kselftest.tar.xz 49%[========> ] 1.34M 1.06MB/s
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11120 22:22:39.423548 2023-06-05 22:22:39 (2.15 MB/s) - 'kselftest.tar.xz' saved [2860080/2860080]
11121 22:22:39.423694
11122 22:22:44.789743 skiplist:
11123 22:22:44.792970 ========================================
11124 22:22:44.796125 ========================================
11125 22:22:44.844921 rtc:rtctest
11126 22:22:44.864787 ============== Tests to run ===============
11127 22:22:44.868512 rtc:rtctest
11128 22:22:44.871031 ===========End Tests to run ===============
11129 22:22:44.970606 <12>[ 35.419825] kselftest: Running tests in rtc
11130 22:22:44.981586 TAP version 13
11131 22:22:44.996112 1..1
11132 22:22:45.029386 # selftests: rtc: rtctest
11133 22:22:45.421204 # TAP version 13
11134 22:22:45.421343 # 1..8
11135 22:22:45.424427 # # Starting 8 tests from 2 test cases.
11136 22:22:45.427609 # # RUN rtc.date_read ...
11137 22:22:45.434322 # # rtctest.c:49:date_read:Current RTC date/time is 05/06/2023 22:22:45.
11138 22:22:45.438024 # # OK rtc.date_read
11139 22:22:45.441245 # ok 1 rtc.date_read
11140 22:22:45.444408 # # RUN rtc.date_read_loop ...
11141 22:22:45.454180 # # rtctest.c:88:date_read_loop:Continuously reading RTC time for 30s (with 11ms breaks after every read).
11142 22:22:55.700988 <6>[ 46.154639] vpu: disabling
11143 22:22:55.704535 <6>[ 46.157691] vproc2: disabling
11144 22:22:55.708018 <6>[ 46.160958] vproc1: disabling
11145 22:22:55.711027 <6>[ 46.164220] vaud18: disabling
11146 22:22:55.717616 <6>[ 46.167633] vsram_others: disabling
11147 22:22:55.721157 <6>[ 46.171509] va09: disabling
11148 22:22:55.724226 <6>[ 46.174614] vsram_md: disabling
11149 22:22:55.727659 <6>[ 46.178097] Vgpu: disabling
11150 22:23:16.022084 # # rtctest.c:115:date_read_loop:Performed 2727 RTC time reads.
11151 22:23:16.025371 # # OK rtc.date_read_loop
11152 22:23:16.028924 # ok 2 rtc.date_read_loop
11153 22:23:16.031846 # # RUN rtc.uie_read ...
11154 22:23:19.000343 # # OK rtc.uie_read
11155 22:23:19.003531 # ok 3 rtc.uie_read
11156 22:23:19.006797 # # RUN rtc.uie_select ...
11157 22:23:22.000669 # # OK rtc.uie_select
11158 22:23:22.003361 # ok 4 rtc.uie_select
11159 22:23:22.006764 # # RUN rtc.alarm_alm_set ...
11160 22:23:22.013464 # # rtctest.c:202:alarm_alm_set:Alarm time now set to 22:23:25.
11161 22:23:22.016967 # # rtctest.c:207:alarm_alm_set:Expected -1 (-1) != rc (-1)
11162 22:23:22.023519 # # alarm_alm_set: Test terminated by assertion
11163 22:23:22.026766 # # FAIL rtc.alarm_alm_set
11164 22:23:22.030263 # not ok 5 rtc.alarm_alm_set
11165 22:23:22.033119 # # RUN rtc.alarm_wkalm_set ...
11166 22:23:22.040009 # # rtctest.c:258:alarm_wkalm_set:Alarm time now set to 05/06/2023 22:23:25.
11167 22:23:25.002530 # # OK rtc.alarm_wkalm_set
11168 22:23:25.002672 # ok 6 rtc.alarm_wkalm_set
11169 22:23:25.009269 # # RUN rtc.alarm_alm_set_minute ...
11170 22:23:25.012789 # # rtctest.c:304:alarm_alm_set_minute:Alarm time now set to 22:24:00.
11171 22:23:25.019646 # # rtctest.c:309:alarm_alm_set_minute:Expected -1 (-1) != rc (-1)
11172 22:23:25.025748 # # alarm_alm_set_minute: Test terminated by assertion
11173 22:23:25.029187 # # FAIL rtc.alarm_alm_set_minute
11174 22:23:25.032118 # not ok 7 rtc.alarm_alm_set_minute
11175 22:23:25.035482 # # RUN rtc.alarm_wkalm_set_minute ...
11176 22:23:25.045508 # # rtctest.c:360:alarm_wkalm_set_minute:Alarm time now set to 05/06/2023 22:24:00.
11177 22:23:59.999046 # # OK rtc.alarm_wkalm_set_minute
11178 22:24:00.002291 # ok 8 rtc.alarm_wkalm_set_minute
11179 22:24:00.005767 # # FAILED: 6 / 8 tests passed.
11180 22:24:00.009215 # # Totals: pass:6 fail:2 xfail:0 xpass:0 skip:0 error:0
11181 22:24:00.012203 not ok 1 selftests: rtc: rtctest # exit=1
11182 22:24:00.546070 rtc_rtctest_rtc_date_read pass
11183 22:24:00.549619 rtc_rtctest_rtc_date_read_loop pass
11184 22:24:00.552552 rtc_rtctest_rtc_uie_read pass
11185 22:24:00.555704 rtc_rtctest_rtc_uie_select pass
11186 22:24:00.559125 rtc_rtctest_rtc_alarm_alm_set fail
11187 22:24:00.562744 rtc_rtctest_rtc_alarm_wkalm_set pass
11188 22:24:00.565884 rtc_rtctest_rtc_alarm_alm_set_minute fail
11189 22:24:00.569077 rtc_rtctest_rtc_alarm_wkalm_set_minute pass
11190 22:24:00.572664 rtc_rtctest fail
11191 22:24:00.575880 + ../../utils/send-to-lava.sh ./output/result.txt
11192 22:24:00.650261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_date_read RESULT=pass>
11193 22:24:00.650544 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_date_read RESULT=pass
11195 22:24:00.712616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_date_read_loop RESULT=pass>
11196 22:24:00.712896 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_date_read_loop RESULT=pass
11198 22:24:00.771827 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_uie_read RESULT=pass>
11199 22:24:00.772097 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_uie_read RESULT=pass
11201 22:24:00.840931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_uie_select RESULT=pass>
11202 22:24:00.841206 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_uie_select RESULT=pass
11204 22:24:00.908184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set RESULT=fail>
11205 22:24:00.908468 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set RESULT=fail
11207 22:24:00.972300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set RESULT=pass>
11208 22:24:00.972564 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set RESULT=pass
11210 22:24:01.035266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set_minute RESULT=fail>
11211 22:24:01.035535 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set_minute RESULT=fail
11213 22:24:01.095685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set_minute RESULT=pass>
11214 22:24:01.095963 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set_minute RESULT=pass
11216 22:24:01.154125 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest RESULT=fail>
11217 22:24:01.154214 + set +x
11218 22:24:01.154453 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest RESULT=fail
11220 22:24:01.160660 <LAVA_SIGNAL_ENDRUN 1_kselftest-rtc 10597300_1.6.2.3.5>
11221 22:24:01.160908 Received signal: <ENDRUN> 1_kselftest-rtc 10597300_1.6.2.3.5
11222 22:24:01.160981 Ending use of test pattern.
11223 22:24:01.161044 Ending test lava.1_kselftest-rtc (10597300_1.6.2.3.5), duration 83.75
11225 22:24:01.161267 ok: lava_test_shell seems to have completed
11226 22:24:01.161394 rtc_rtctest: fail
rtc_rtctest_rtc_alarm_alm_set: fail
rtc_rtctest_rtc_alarm_alm_set_minute: fail
rtc_rtctest_rtc_alarm_wkalm_set: pass
rtc_rtctest_rtc_alarm_wkalm_set_minute: pass
rtc_rtctest_rtc_date_read: pass
rtc_rtctest_rtc_date_read_loop: pass
rtc_rtctest_rtc_uie_read: pass
rtc_rtctest_rtc_uie_select: pass
11227 22:24:01.161486 end: 3.1 lava-test-shell (duration 00:01:25) [common]
11228 22:24:01.161574 end: 3 lava-test-retry (duration 00:01:25) [common]
11229 22:24:01.161665 start: 4 finalize (timeout 00:06:07) [common]
11230 22:24:01.161757 start: 4.1 power-off (timeout 00:00:30) [common]
11231 22:24:01.161911 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=off'
11232 22:24:01.238598 >> Command sent successfully.
11233 22:24:01.243600 Returned 0 in 0 seconds
11234 22:24:01.344183 end: 4.1 power-off (duration 00:00:00) [common]
11236 22:24:01.344511 start: 4.2 read-feedback (timeout 00:06:06) [common]
11238 22:24:01.345121 Listened to connection for namespace 'common' for up to 1s
11239 22:24:02.345701 Finalising connection for namespace 'common'
11240 22:24:02.345905 Disconnecting from shell: Finalise
11241 22:24:02.346008 / #
11242 22:24:02.446334 end: 4.2 read-feedback (duration 00:00:01) [common]
11243 22:24:02.446491 end: 4 finalize (duration 00:00:01) [common]
11244 22:24:02.446610 Cleaning after the job
11245 22:24:02.446718 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10597300/tftp-deploy-ebp2nqop/ramdisk
11246 22:24:02.449020 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10597300/tftp-deploy-ebp2nqop/kernel
11247 22:24:02.457663 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10597300/tftp-deploy-ebp2nqop/dtb
11248 22:24:02.457837 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10597300/tftp-deploy-ebp2nqop/nfsrootfs
11249 22:24:02.525681 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10597300/tftp-deploy-ebp2nqop/modules
11250 22:24:02.531047 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/10597300
11251 22:24:03.042744 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/10597300
11252 22:24:03.043130 Job finished correctly