Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 51
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 35
1 22:16:43.834700 lava-dispatcher, installed at version: 2023.05.1
2 22:16:43.834912 start: 0 validate
3 22:16:43.835038 Start time: 2023-06-05 22:16:43.835031+00:00 (UTC)
4 22:16:43.835161 Using caching service: 'http://localhost/cache/?uri=%s'
5 22:16:43.835291 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230527.0%2Farm64%2Finitrd.cpio.gz exists
6 22:16:44.137466 Using caching service: 'http://localhost/cache/?uri=%s'
7 22:16:44.137651 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1314-g1ab0ac1d7e2e3%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 22:16:44.433524 Using caching service: 'http://localhost/cache/?uri=%s'
9 22:16:44.433710 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1314-g1ab0ac1d7e2e3%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 22:16:44.725874 Using caching service: 'http://localhost/cache/?uri=%s'
11 22:16:44.726050 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230527.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 22:16:45.020211 Using caching service: 'http://localhost/cache/?uri=%s'
13 22:16:45.020370 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1314-g1ab0ac1d7e2e3%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 22:16:45.341672 validate duration: 1.51
16 22:16:45.341940 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 22:16:45.342037 start: 1.1 download-retry (timeout 00:10:00) [common]
18 22:16:45.342134 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 22:16:45.342287 Not decompressing ramdisk as can be used compressed.
20 22:16:45.342387 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230527.0/arm64/initrd.cpio.gz
21 22:16:45.342453 saving as /var/lib/lava/dispatcher/tmp/10597264/tftp-deploy-9iuqvnbb/ramdisk/initrd.cpio.gz
22 22:16:45.342517 total size: 4665601 (4MB)
23 22:16:45.343592 progress 0% (0MB)
24 22:16:45.345097 progress 5% (0MB)
25 22:16:45.346333 progress 10% (0MB)
26 22:16:45.347562 progress 15% (0MB)
27 22:16:45.348835 progress 20% (0MB)
28 22:16:45.350058 progress 25% (1MB)
29 22:16:45.351283 progress 30% (1MB)
30 22:16:45.352497 progress 35% (1MB)
31 22:16:45.353770 progress 40% (1MB)
32 22:16:45.355159 progress 45% (2MB)
33 22:16:45.356391 progress 50% (2MB)
34 22:16:45.357661 progress 55% (2MB)
35 22:16:45.358877 progress 60% (2MB)
36 22:16:45.360096 progress 65% (2MB)
37 22:16:45.361363 progress 70% (3MB)
38 22:16:45.362584 progress 75% (3MB)
39 22:16:45.363800 progress 80% (3MB)
40 22:16:45.365216 progress 85% (3MB)
41 22:16:45.366428 progress 90% (4MB)
42 22:16:45.367656 progress 95% (4MB)
43 22:16:45.368965 progress 100% (4MB)
44 22:16:45.369121 4MB downloaded in 0.03s (167.27MB/s)
45 22:16:45.369264 end: 1.1.1 http-download (duration 00:00:00) [common]
47 22:16:45.369515 end: 1.1 download-retry (duration 00:00:00) [common]
48 22:16:45.369602 start: 1.2 download-retry (timeout 00:10:00) [common]
49 22:16:45.369690 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 22:16:45.369815 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1314-g1ab0ac1d7e2e3/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 22:16:45.369888 saving as /var/lib/lava/dispatcher/tmp/10597264/tftp-deploy-9iuqvnbb/kernel/Image
52 22:16:45.369948 total size: 45746688 (43MB)
53 22:16:45.370011 No compression specified
54 22:16:45.371120 progress 0% (0MB)
55 22:16:45.382876 progress 5% (2MB)
56 22:16:45.394603 progress 10% (4MB)
57 22:16:45.406405 progress 15% (6MB)
58 22:16:45.418165 progress 20% (8MB)
59 22:16:45.430001 progress 25% (10MB)
60 22:16:45.441743 progress 30% (13MB)
61 22:16:45.453683 progress 35% (15MB)
62 22:16:45.465412 progress 40% (17MB)
63 22:16:45.477228 progress 45% (19MB)
64 22:16:45.489013 progress 50% (21MB)
65 22:16:45.500537 progress 55% (24MB)
66 22:16:45.512185 progress 60% (26MB)
67 22:16:45.524065 progress 65% (28MB)
68 22:16:45.535744 progress 70% (30MB)
69 22:16:45.547447 progress 75% (32MB)
70 22:16:45.558924 progress 80% (34MB)
71 22:16:45.570625 progress 85% (37MB)
72 22:16:45.582468 progress 90% (39MB)
73 22:16:45.594097 progress 95% (41MB)
74 22:16:45.605554 progress 100% (43MB)
75 22:16:45.605682 43MB downloaded in 0.24s (185.07MB/s)
76 22:16:45.605836 end: 1.2.1 http-download (duration 00:00:00) [common]
78 22:16:45.606068 end: 1.2 download-retry (duration 00:00:00) [common]
79 22:16:45.606160 start: 1.3 download-retry (timeout 00:10:00) [common]
80 22:16:45.606253 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 22:16:45.606387 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1314-g1ab0ac1d7e2e3/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 22:16:45.606486 saving as /var/lib/lava/dispatcher/tmp/10597264/tftp-deploy-9iuqvnbb/dtb/mt8192-asurada-spherion-r0.dtb
83 22:16:45.606554 total size: 46924 (0MB)
84 22:16:45.606614 No compression specified
85 22:16:45.607718 progress 69% (0MB)
86 22:16:45.607986 progress 100% (0MB)
87 22:16:45.608141 0MB downloaded in 0.00s (28.25MB/s)
88 22:16:45.608262 end: 1.3.1 http-download (duration 00:00:00) [common]
90 22:16:45.608504 end: 1.3 download-retry (duration 00:00:00) [common]
91 22:16:45.608644 start: 1.4 download-retry (timeout 00:10:00) [common]
92 22:16:45.608732 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 22:16:45.608841 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230527.0/arm64/full.rootfs.tar.xz
94 22:16:45.608908 saving as /var/lib/lava/dispatcher/tmp/10597264/tftp-deploy-9iuqvnbb/nfsrootfs/full.rootfs.tar
95 22:16:45.608971 total size: 200770336 (191MB)
96 22:16:45.609052 Using unxz to decompress xz
97 22:16:45.612578 progress 0% (0MB)
98 22:16:46.146154 progress 5% (9MB)
99 22:16:46.662020 progress 10% (19MB)
100 22:16:47.245581 progress 15% (28MB)
101 22:16:47.617825 progress 20% (38MB)
102 22:16:47.942946 progress 25% (47MB)
103 22:16:48.539822 progress 30% (57MB)
104 22:16:49.089113 progress 35% (67MB)
105 22:16:49.680140 progress 40% (76MB)
106 22:16:50.241059 progress 45% (86MB)
107 22:16:50.822833 progress 50% (95MB)
108 22:16:51.448785 progress 55% (105MB)
109 22:16:52.097125 progress 60% (114MB)
110 22:16:52.213114 progress 65% (124MB)
111 22:16:52.352072 progress 70% (134MB)
112 22:16:52.447791 progress 75% (143MB)
113 22:16:52.522033 progress 80% (153MB)
114 22:16:52.591166 progress 85% (162MB)
115 22:16:52.688787 progress 90% (172MB)
116 22:16:52.962690 progress 95% (181MB)
117 22:16:53.543389 progress 100% (191MB)
118 22:16:53.548121 191MB downloaded in 7.94s (24.12MB/s)
119 22:16:53.548400 end: 1.4.1 http-download (duration 00:00:08) [common]
121 22:16:53.548679 end: 1.4 download-retry (duration 00:00:08) [common]
122 22:16:53.548770 start: 1.5 download-retry (timeout 00:09:52) [common]
123 22:16:53.548859 start: 1.5.1 http-download (timeout 00:09:52) [common]
124 22:16:53.549006 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1314-g1ab0ac1d7e2e3/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 22:16:53.549078 saving as /var/lib/lava/dispatcher/tmp/10597264/tftp-deploy-9iuqvnbb/modules/modules.tar
126 22:16:53.549139 total size: 8543056 (8MB)
127 22:16:53.549200 Using unxz to decompress xz
128 22:16:53.552808 progress 0% (0MB)
129 22:16:53.574948 progress 5% (0MB)
130 22:16:53.600765 progress 10% (0MB)
131 22:16:53.626616 progress 15% (1MB)
132 22:16:53.651819 progress 20% (1MB)
133 22:16:53.675337 progress 25% (2MB)
134 22:16:53.702122 progress 30% (2MB)
135 22:16:53.727819 progress 35% (2MB)
136 22:16:53.753410 progress 40% (3MB)
137 22:16:53.777895 progress 45% (3MB)
138 22:16:53.802895 progress 50% (4MB)
139 22:16:53.826567 progress 55% (4MB)
140 22:16:53.851507 progress 60% (4MB)
141 22:16:53.877203 progress 65% (5MB)
142 22:16:53.902123 progress 70% (5MB)
143 22:16:53.925893 progress 75% (6MB)
144 22:16:53.950334 progress 80% (6MB)
145 22:16:53.975757 progress 85% (6MB)
146 22:16:54.005179 progress 90% (7MB)
147 22:16:54.030891 progress 95% (7MB)
148 22:16:54.055514 progress 100% (8MB)
149 22:16:54.061739 8MB downloaded in 0.51s (15.89MB/s)
150 22:16:54.062013 end: 1.5.1 http-download (duration 00:00:01) [common]
152 22:16:54.062275 end: 1.5 download-retry (duration 00:00:01) [common]
153 22:16:54.062367 start: 1.6 prepare-tftp-overlay (timeout 00:09:51) [common]
154 22:16:54.062460 start: 1.6.1 extract-nfsrootfs (timeout 00:09:51) [common]
155 22:16:57.351608 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/10597264/extract-nfsrootfs-sl45zt8p
156 22:16:57.351808 end: 1.6.1 extract-nfsrootfs (duration 00:00:03) [common]
157 22:16:57.351915 start: 1.6.2 lava-overlay (timeout 00:09:48) [common]
158 22:16:57.352085 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/10597264/lava-overlay-zzp823rd
159 22:16:57.352212 makedir: /var/lib/lava/dispatcher/tmp/10597264/lava-overlay-zzp823rd/lava-10597264/bin
160 22:16:57.352311 makedir: /var/lib/lava/dispatcher/tmp/10597264/lava-overlay-zzp823rd/lava-10597264/tests
161 22:16:57.352407 makedir: /var/lib/lava/dispatcher/tmp/10597264/lava-overlay-zzp823rd/lava-10597264/results
162 22:16:57.352504 Creating /var/lib/lava/dispatcher/tmp/10597264/lava-overlay-zzp823rd/lava-10597264/bin/lava-add-keys
163 22:16:57.352916 Creating /var/lib/lava/dispatcher/tmp/10597264/lava-overlay-zzp823rd/lava-10597264/bin/lava-add-sources
164 22:16:57.353040 Creating /var/lib/lava/dispatcher/tmp/10597264/lava-overlay-zzp823rd/lava-10597264/bin/lava-background-process-start
165 22:16:57.353163 Creating /var/lib/lava/dispatcher/tmp/10597264/lava-overlay-zzp823rd/lava-10597264/bin/lava-background-process-stop
166 22:16:57.353284 Creating /var/lib/lava/dispatcher/tmp/10597264/lava-overlay-zzp823rd/lava-10597264/bin/lava-common-functions
167 22:16:57.353402 Creating /var/lib/lava/dispatcher/tmp/10597264/lava-overlay-zzp823rd/lava-10597264/bin/lava-echo-ipv4
168 22:16:57.353522 Creating /var/lib/lava/dispatcher/tmp/10597264/lava-overlay-zzp823rd/lava-10597264/bin/lava-install-packages
169 22:16:57.353640 Creating /var/lib/lava/dispatcher/tmp/10597264/lava-overlay-zzp823rd/lava-10597264/bin/lava-installed-packages
170 22:16:57.353757 Creating /var/lib/lava/dispatcher/tmp/10597264/lava-overlay-zzp823rd/lava-10597264/bin/lava-os-build
171 22:16:57.353877 Creating /var/lib/lava/dispatcher/tmp/10597264/lava-overlay-zzp823rd/lava-10597264/bin/lava-probe-channel
172 22:16:57.353994 Creating /var/lib/lava/dispatcher/tmp/10597264/lava-overlay-zzp823rd/lava-10597264/bin/lava-probe-ip
173 22:16:57.354110 Creating /var/lib/lava/dispatcher/tmp/10597264/lava-overlay-zzp823rd/lava-10597264/bin/lava-target-ip
174 22:16:57.354229 Creating /var/lib/lava/dispatcher/tmp/10597264/lava-overlay-zzp823rd/lava-10597264/bin/lava-target-mac
175 22:16:57.354348 Creating /var/lib/lava/dispatcher/tmp/10597264/lava-overlay-zzp823rd/lava-10597264/bin/lava-target-storage
176 22:16:57.354466 Creating /var/lib/lava/dispatcher/tmp/10597264/lava-overlay-zzp823rd/lava-10597264/bin/lava-test-case
177 22:16:57.354584 Creating /var/lib/lava/dispatcher/tmp/10597264/lava-overlay-zzp823rd/lava-10597264/bin/lava-test-event
178 22:16:57.354700 Creating /var/lib/lava/dispatcher/tmp/10597264/lava-overlay-zzp823rd/lava-10597264/bin/lava-test-feedback
179 22:16:57.354818 Creating /var/lib/lava/dispatcher/tmp/10597264/lava-overlay-zzp823rd/lava-10597264/bin/lava-test-raise
180 22:16:57.354936 Creating /var/lib/lava/dispatcher/tmp/10597264/lava-overlay-zzp823rd/lava-10597264/bin/lava-test-reference
181 22:16:57.355058 Creating /var/lib/lava/dispatcher/tmp/10597264/lava-overlay-zzp823rd/lava-10597264/bin/lava-test-runner
182 22:16:57.355176 Creating /var/lib/lava/dispatcher/tmp/10597264/lava-overlay-zzp823rd/lava-10597264/bin/lava-test-set
183 22:16:57.355295 Creating /var/lib/lava/dispatcher/tmp/10597264/lava-overlay-zzp823rd/lava-10597264/bin/lava-test-shell
184 22:16:57.355419 Updating /var/lib/lava/dispatcher/tmp/10597264/lava-overlay-zzp823rd/lava-10597264/bin/lava-add-keys (debian)
185 22:16:57.355566 Updating /var/lib/lava/dispatcher/tmp/10597264/lava-overlay-zzp823rd/lava-10597264/bin/lava-add-sources (debian)
186 22:16:57.355703 Updating /var/lib/lava/dispatcher/tmp/10597264/lava-overlay-zzp823rd/lava-10597264/bin/lava-install-packages (debian)
187 22:16:57.355844 Updating /var/lib/lava/dispatcher/tmp/10597264/lava-overlay-zzp823rd/lava-10597264/bin/lava-installed-packages (debian)
188 22:16:57.355980 Updating /var/lib/lava/dispatcher/tmp/10597264/lava-overlay-zzp823rd/lava-10597264/bin/lava-os-build (debian)
189 22:16:57.356101 Creating /var/lib/lava/dispatcher/tmp/10597264/lava-overlay-zzp823rd/lava-10597264/environment
190 22:16:57.356198 LAVA metadata
191 22:16:57.356266 - LAVA_JOB_ID=10597264
192 22:16:57.356328 - LAVA_DISPATCHER_IP=192.168.201.1
193 22:16:57.356425 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:48) [common]
194 22:16:57.356489 skipped lava-vland-overlay
195 22:16:57.356609 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 22:16:57.356688 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:48) [common]
197 22:16:57.356748 skipped lava-multinode-overlay
198 22:16:57.356819 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 22:16:57.356895 start: 1.6.2.3 test-definition (timeout 00:09:48) [common]
200 22:16:57.356965 Loading test definitions
201 22:16:57.357053 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:48) [common]
202 22:16:57.357124 Using /lava-10597264 at stage 0
203 22:16:57.357434 uuid=10597264_1.6.2.3.1 testdef=None
204 22:16:57.357519 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 22:16:57.357603 start: 1.6.2.3.2 test-overlay (timeout 00:09:48) [common]
206 22:16:57.358043 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 22:16:57.358266 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:48) [common]
209 22:16:57.358810 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 22:16:57.359037 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:48) [common]
212 22:16:57.359562 runner path: /var/lib/lava/dispatcher/tmp/10597264/lava-overlay-zzp823rd/lava-10597264/0/tests/0_timesync-off test_uuid 10597264_1.6.2.3.1
213 22:16:57.359711 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 22:16:57.359929 start: 1.6.2.3.5 git-repo-action (timeout 00:09:48) [common]
216 22:16:57.360001 Using /lava-10597264 at stage 0
217 22:16:57.360094 Fetching tests from https://github.com/kernelci/test-definitions.git
218 22:16:57.360169 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/10597264/lava-overlay-zzp823rd/lava-10597264/0/tests/1_kselftest-tpm2'
219 22:16:59.601951 Running '/usr/bin/git checkout kernelci.org
220 22:16:59.743232 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/10597264/lava-overlay-zzp823rd/lava-10597264/0/tests/1_kselftest-tpm2/automated/linux/kselftest/kselftest.yaml
221 22:16:59.743945 uuid=10597264_1.6.2.3.5 testdef=None
222 22:16:59.744098 end: 1.6.2.3.5 git-repo-action (duration 00:00:02) [common]
224 22:16:59.744346 start: 1.6.2.3.6 test-overlay (timeout 00:09:46) [common]
225 22:16:59.745119 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 22:16:59.745346 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:46) [common]
228 22:16:59.746291 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 22:16:59.746521 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:46) [common]
231 22:16:59.747426 runner path: /var/lib/lava/dispatcher/tmp/10597264/lava-overlay-zzp823rd/lava-10597264/0/tests/1_kselftest-tpm2 test_uuid 10597264_1.6.2.3.5
232 22:16:59.747518 BOARD='mt8192-asurada-spherion-r0'
233 22:16:59.747582 BRANCH='cip-gitlab'
234 22:16:59.747641 SKIPFILE='/dev/null'
235 22:16:59.747697 SKIP_INSTALL='True'
236 22:16:59.747751 TESTPROG_URL='http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1314-g1ab0ac1d7e2e3/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 22:16:59.747807 TST_CASENAME=''
238 22:16:59.747862 TST_CMDFILES='tpm2'
239 22:16:59.748002 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 22:16:59.748202 Creating lava-test-runner.conf files
242 22:16:59.748264 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10597264/lava-overlay-zzp823rd/lava-10597264/0 for stage 0
243 22:16:59.748354 - 0_timesync-off
244 22:16:59.748419 - 1_kselftest-tpm2
245 22:16:59.748511 end: 1.6.2.3 test-definition (duration 00:00:02) [common]
246 22:16:59.748671 start: 1.6.2.4 compress-overlay (timeout 00:09:46) [common]
247 22:17:07.119211 end: 1.6.2.4 compress-overlay (duration 00:00:07) [common]
248 22:17:07.119372 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:38) [common]
249 22:17:07.119468 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 22:17:07.119571 end: 1.6.2 lava-overlay (duration 00:00:10) [common]
251 22:17:07.119665 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:38) [common]
252 22:17:07.231134 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 22:17:07.231492 start: 1.6.4 extract-modules (timeout 00:09:38) [common]
254 22:17:07.231603 extracting modules file /var/lib/lava/dispatcher/tmp/10597264/tftp-deploy-9iuqvnbb/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10597264/extract-nfsrootfs-sl45zt8p
255 22:17:07.434094 extracting modules file /var/lib/lava/dispatcher/tmp/10597264/tftp-deploy-9iuqvnbb/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10597264/extract-overlay-ramdisk-t1cxp72w/ramdisk
256 22:17:07.644627 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 22:17:07.644801 start: 1.6.5 apply-overlay-tftp (timeout 00:09:38) [common]
258 22:17:07.644892 [common] Applying overlay to NFS
259 22:17:07.644961 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10597264/compress-overlay-z4arislu/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/10597264/extract-nfsrootfs-sl45zt8p
260 22:17:08.524811 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 22:17:08.524989 start: 1.6.6 configure-preseed-file (timeout 00:09:37) [common]
262 22:17:08.525089 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 22:17:08.525185 start: 1.6.7 compress-ramdisk (timeout 00:09:37) [common]
264 22:17:08.525271 Building ramdisk /var/lib/lava/dispatcher/tmp/10597264/extract-overlay-ramdisk-t1cxp72w/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/10597264/extract-overlay-ramdisk-t1cxp72w/ramdisk
265 22:17:08.819998 >> 117807 blocks
266 22:17:10.674513 rename /var/lib/lava/dispatcher/tmp/10597264/extract-overlay-ramdisk-t1cxp72w/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/10597264/tftp-deploy-9iuqvnbb/ramdisk/ramdisk.cpio.gz
267 22:17:10.674932 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 22:17:10.675052 start: 1.6.8 prepare-kernel (timeout 00:09:35) [common]
269 22:17:10.675204 start: 1.6.8.1 prepare-fit (timeout 00:09:35) [common]
270 22:17:10.675321 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/10597264/tftp-deploy-9iuqvnbb/kernel/Image'
271 22:17:22.593909 Returned 0 in 11 seconds
272 22:17:22.694793 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/10597264/tftp-deploy-9iuqvnbb/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/10597264/tftp-deploy-9iuqvnbb/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/10597264/tftp-deploy-9iuqvnbb/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/10597264/tftp-deploy-9iuqvnbb/kernel/image.itb
273 22:17:23.038730 output: FIT description: Kernel Image image with one or more FDT blobs
274 22:17:23.039082 output: Created: Mon Jun 5 23:17:22 2023
275 22:17:23.039162 output: Image 0 (kernel-1)
276 22:17:23.039230 output: Description:
277 22:17:23.039295 output: Created: Mon Jun 5 23:17:22 2023
278 22:17:23.039357 output: Type: Kernel Image
279 22:17:23.039418 output: Compression: lzma compressed
280 22:17:23.039478 output: Data Size: 10082307 Bytes = 9846.00 KiB = 9.62 MiB
281 22:17:23.039536 output: Architecture: AArch64
282 22:17:23.039595 output: OS: Linux
283 22:17:23.039650 output: Load Address: 0x00000000
284 22:17:23.039706 output: Entry Point: 0x00000000
285 22:17:23.039762 output: Hash algo: crc32
286 22:17:23.039814 output: Hash value: c242daf7
287 22:17:23.039867 output: Image 1 (fdt-1)
288 22:17:23.039919 output: Description: mt8192-asurada-spherion-r0
289 22:17:23.039973 output: Created: Mon Jun 5 23:17:22 2023
290 22:17:23.040026 output: Type: Flat Device Tree
291 22:17:23.040079 output: Compression: uncompressed
292 22:17:23.040132 output: Data Size: 46924 Bytes = 45.82 KiB = 0.04 MiB
293 22:17:23.040186 output: Architecture: AArch64
294 22:17:23.040238 output: Hash algo: crc32
295 22:17:23.040291 output: Hash value: 1df858fa
296 22:17:23.040344 output: Image 2 (ramdisk-1)
297 22:17:23.040396 output: Description: unavailable
298 22:17:23.040448 output: Created: Mon Jun 5 23:17:22 2023
299 22:17:23.040501 output: Type: RAMDisk Image
300 22:17:23.040580 output: Compression: Unknown Compression
301 22:17:23.040646 output: Data Size: 17645696 Bytes = 17232.12 KiB = 16.83 MiB
302 22:17:23.040700 output: Architecture: AArch64
303 22:17:23.040752 output: OS: Linux
304 22:17:23.040810 output: Load Address: unavailable
305 22:17:23.040865 output: Entry Point: unavailable
306 22:17:23.040918 output: Hash algo: crc32
307 22:17:23.040970 output: Hash value: 1056329a
308 22:17:23.041023 output: Default Configuration: 'conf-1'
309 22:17:23.041076 output: Configuration 0 (conf-1)
310 22:17:23.041130 output: Description: mt8192-asurada-spherion-r0
311 22:17:23.041182 output: Kernel: kernel-1
312 22:17:23.041234 output: Init Ramdisk: ramdisk-1
313 22:17:23.041287 output: FDT: fdt-1
314 22:17:23.041340 output: Loadables: kernel-1
315 22:17:23.041392 output:
316 22:17:23.041595 end: 1.6.8.1 prepare-fit (duration 00:00:12) [common]
317 22:17:23.041695 end: 1.6.8 prepare-kernel (duration 00:00:12) [common]
318 22:17:23.041795 end: 1.6 prepare-tftp-overlay (duration 00:00:29) [common]
319 22:17:23.041894 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:22) [common]
320 22:17:23.041971 No LXC device requested
321 22:17:23.042048 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 22:17:23.042132 start: 1.8 deploy-device-env (timeout 00:09:22) [common]
323 22:17:23.042207 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 22:17:23.042277 Checking files for TFTP limit of 4294967296 bytes.
325 22:17:23.042779 end: 1 tftp-deploy (duration 00:00:38) [common]
326 22:17:23.042892 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 22:17:23.042986 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 22:17:23.043110 substitutions:
329 22:17:23.043179 - {DTB}: 10597264/tftp-deploy-9iuqvnbb/dtb/mt8192-asurada-spherion-r0.dtb
330 22:17:23.043243 - {INITRD}: 10597264/tftp-deploy-9iuqvnbb/ramdisk/ramdisk.cpio.gz
331 22:17:23.043303 - {KERNEL}: 10597264/tftp-deploy-9iuqvnbb/kernel/Image
332 22:17:23.043361 - {LAVA_MAC}: None
333 22:17:23.043418 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/10597264/extract-nfsrootfs-sl45zt8p
334 22:17:23.043475 - {NFS_SERVER_IP}: 192.168.201.1
335 22:17:23.043530 - {PRESEED_CONFIG}: None
336 22:17:23.043584 - {PRESEED_LOCAL}: None
337 22:17:23.043638 - {RAMDISK}: 10597264/tftp-deploy-9iuqvnbb/ramdisk/ramdisk.cpio.gz
338 22:17:23.043693 - {ROOT_PART}: None
339 22:17:23.043747 - {ROOT}: None
340 22:17:23.043800 - {SERVER_IP}: 192.168.201.1
341 22:17:23.043854 - {TEE}: None
342 22:17:23.043909 Parsed boot commands:
343 22:17:23.043962 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 22:17:23.044139 Parsed boot commands: tftpboot 192.168.201.1 10597264/tftp-deploy-9iuqvnbb/kernel/image.itb 10597264/tftp-deploy-9iuqvnbb/kernel/cmdline
345 22:17:23.044228 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 22:17:23.044314 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 22:17:23.044406 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 22:17:23.044499 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 22:17:23.044584 Not connected, no need to disconnect.
350 22:17:23.044659 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 22:17:23.044747 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 22:17:23.044812 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost mt8192-asurada-spherion-r0-cbg-9'
353 22:17:23.048167 Setting prompt string to ['lava-test: # ']
354 22:17:23.048504 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 22:17:23.048655 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 22:17:23.048765 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 22:17:23.048864 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 22:17:23.049047 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-9' '--port=1' '--command=reboot'
359 22:17:28.187798 >> Command sent successfully.
360 22:17:28.190066 Returned 0 in 5 seconds
361 22:17:28.290777 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 22:17:28.292162 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 22:17:28.292716 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 22:17:28.293237 Setting prompt string to 'Starting depthcharge on Spherion...'
366 22:17:28.293598 Changing prompt to 'Starting depthcharge on Spherion...'
367 22:17:28.293971 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 22:17:28.295169 [Enter `^Ec?' for help]
369 22:17:28.463642
370 22:17:28.463793
371 22:17:28.463862 F0: 102B 0000
372 22:17:28.463924
373 22:17:28.463984 F3: 1001 0000 [0200]
374 22:17:28.464044
375 22:17:28.466368 F3: 1001 0000
376 22:17:28.466453
377 22:17:28.466524 F7: 102D 0000
378 22:17:28.466587
379 22:17:28.469701 F1: 0000 0000
380 22:17:28.469785
381 22:17:28.469851 V0: 0000 0000 [0001]
382 22:17:28.469912
383 22:17:28.473167 00: 0007 8000
384 22:17:28.473254
385 22:17:28.473321 01: 0000 0000
386 22:17:28.473383
387 22:17:28.476715 BP: 0C00 0209 [0000]
388 22:17:28.476800
389 22:17:28.476866 G0: 1182 0000
390 22:17:28.476927
391 22:17:28.476986 EC: 0000 0021 [4000]
392 22:17:28.480083
393 22:17:28.480166 S7: 0000 0000 [0000]
394 22:17:28.480232
395 22:17:28.483526 CC: 0000 0000 [0001]
396 22:17:28.483614
397 22:17:28.483680 T0: 0000 0040 [010F]
398 22:17:28.483741
399 22:17:28.483807 Jump to BL
400 22:17:28.487071
401 22:17:28.510338
402 22:17:28.510431
403 22:17:28.510521
404 22:17:28.517720 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
405 22:17:28.521243 ARM64: Exception handlers installed.
406 22:17:28.524956 ARM64: Testing exception
407 22:17:28.527970 ARM64: Done test exception
408 22:17:28.535879 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
409 22:17:28.545172 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
410 22:17:28.551906 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
411 22:17:28.561791 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
412 22:17:28.568766 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
413 22:17:28.575090 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
414 22:17:28.586482 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
415 22:17:28.593130 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
416 22:17:28.613056 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
417 22:17:28.616324 WDT: Last reset was cold boot
418 22:17:28.620056 SPI1(PAD0) initialized at 2873684 Hz
419 22:17:28.622787 SPI5(PAD0) initialized at 992727 Hz
420 22:17:28.626126 VBOOT: Loading verstage.
421 22:17:28.632865 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 22:17:28.636239 FMAP: Found "FLASH" version 1.1 at 0x20000.
423 22:17:28.639409 FMAP: base = 0x0 size = 0x800000 #areas = 25
424 22:17:28.642802 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
425 22:17:28.650218 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
426 22:17:28.657102 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
427 22:17:28.668258 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
428 22:17:28.668343
429 22:17:28.668410
430 22:17:28.677617 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
431 22:17:28.681049 ARM64: Exception handlers installed.
432 22:17:28.684621 ARM64: Testing exception
433 22:17:28.684745 ARM64: Done test exception
434 22:17:28.691434 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
435 22:17:28.694271 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
436 22:17:28.709007 Probing TPM: . done!
437 22:17:28.709095 TPM ready after 0 ms
438 22:17:28.715435 Connected to device vid:did:rid of 1ae0:0028:00
439 22:17:28.725453 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
440 22:17:28.763747 Initialized TPM device CR50 revision 0
441 22:17:28.776476 tlcl_send_startup: Startup return code is 0
442 22:17:28.776607 TPM: setup succeeded
443 22:17:28.788343 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
444 22:17:28.796764 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 22:17:28.803668 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
446 22:17:28.816723 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
447 22:17:28.819952 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
448 22:17:28.824017 in-header: 03 07 00 00 08 00 00 00
449 22:17:28.827034 in-data: aa e4 47 04 13 02 00 00
450 22:17:28.830509 Chrome EC: UHEPI supported
451 22:17:28.836977 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
452 22:17:28.840071 in-header: 03 ad 00 00 08 00 00 00
453 22:17:28.843912 in-data: 00 20 20 08 00 00 00 00
454 22:17:28.843999 Phase 1
455 22:17:28.850206 FMAP: area GBB found @ 3f5000 (12032 bytes)
456 22:17:28.853509 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
457 22:17:28.860286 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
458 22:17:28.863208 Recovery requested (1009000e)
459 22:17:28.868225 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 22:17:28.876775 tlcl_extend: response is 0
461 22:17:28.884853 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 22:17:28.889633 tlcl_extend: response is 0
463 22:17:28.896163 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 22:17:28.917192 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
465 22:17:28.924048 BS: bootblock times (exec / console): total (unknown) / 148 ms
466 22:17:28.924160
467 22:17:28.924255
468 22:17:28.933835 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 22:17:28.937290 ARM64: Exception handlers installed.
470 22:17:28.940612 ARM64: Testing exception
471 22:17:28.940690 ARM64: Done test exception
472 22:17:28.962648 pmic_efuse_setting: Set efuses in 11 msecs
473 22:17:28.966404 pmwrap_interface_init: Select PMIF_VLD_RDY
474 22:17:28.973349 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 22:17:28.976470 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 22:17:28.979584 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 22:17:28.986455 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 22:17:28.990388 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 22:17:28.996695 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 22:17:29.000341 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 22:17:29.006784 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 22:17:29.010291 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 22:17:29.013213 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 22:17:29.019855 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 22:17:29.023160 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 22:17:29.027012 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 22:17:29.034053 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 22:17:29.040427 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 22:17:29.047119 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 22:17:29.050304 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 22:17:29.056704 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 22:17:29.063510 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 22:17:29.070227 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 22:17:29.073466 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 22:17:29.080851 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 22:17:29.084325 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 22:17:29.091861 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 22:17:29.094563 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 22:17:29.101058 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 22:17:29.108479 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 22:17:29.111704 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 22:17:29.115133 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 22:17:29.122159 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 22:17:29.125768 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 22:17:29.132671 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 22:17:29.135894 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 22:17:29.143000 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 22:17:29.145963 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 22:17:29.152852 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 22:17:29.156545 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 22:17:29.163255 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 22:17:29.166539 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 22:17:29.169742 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 22:17:29.176437 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 22:17:29.179982 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 22:17:29.183189 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 22:17:29.186222 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 22:17:29.193642 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 22:17:29.196172 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 22:17:29.199586 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 22:17:29.205927 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 22:17:29.209234 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 22:17:29.212722 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 22:17:29.216023 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 22:17:29.226575 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
526 22:17:29.232584 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 22:17:29.240349 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 22:17:29.245979 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 22:17:29.255959 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 22:17:29.258970 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 22:17:29.265734 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 22:17:29.268940 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 22:17:29.276152 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6c, sec=0x2e
534 22:17:29.282360 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 22:17:29.285759 [RTC]rtc_osc_init,62: osc32con val = 0xde6c
536 22:17:29.289067 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 22:17:29.300357 [RTC]rtc_get_frequency_meter,154: input=15, output=835
538 22:17:29.310078 [RTC]rtc_get_frequency_meter,154: input=7, output=708
539 22:17:29.318934 [RTC]rtc_get_frequency_meter,154: input=11, output=771
540 22:17:29.328482 [RTC]rtc_get_frequency_meter,154: input=13, output=804
541 22:17:29.338615 [RTC]rtc_get_frequency_meter,154: input=12, output=788
542 22:17:29.347360 [RTC]rtc_get_frequency_meter,154: input=12, output=788
543 22:17:29.357113 [RTC]rtc_get_frequency_meter,154: input=13, output=804
544 22:17:29.360368 [RTC]rtc_eosc_cali,47: left: 12, middle: 12, right: 13
545 22:17:29.367649 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6c
546 22:17:29.371152 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
547 22:17:29.374663 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
548 22:17:29.381392 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
549 22:17:29.384677 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
550 22:17:29.387394 ADC[4]: Raw value=903031 ID=7
551 22:17:29.387877 ADC[3]: Raw value=213652 ID=1
552 22:17:29.390788 RAM Code: 0x71
553 22:17:29.394025 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
554 22:17:29.401013 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
555 22:17:29.407307 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
556 22:17:29.413965 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
557 22:17:29.417189 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
558 22:17:29.420649 in-header: 03 07 00 00 08 00 00 00
559 22:17:29.423635 in-data: aa e4 47 04 13 02 00 00
560 22:17:29.426871 Chrome EC: UHEPI supported
561 22:17:29.433507 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
562 22:17:29.436679 in-header: 03 dd 00 00 08 00 00 00
563 22:17:29.439861 in-data: 90 20 60 08 00 00 00 00
564 22:17:29.443374 MRC: failed to locate region type 0.
565 22:17:29.449991 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
566 22:17:29.454029 DRAM-K: Running full calibration
567 22:17:29.459864 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
568 22:17:29.463206 header.status = 0x0
569 22:17:29.466599 header.version = 0x6 (expected: 0x6)
570 22:17:29.469772 header.size = 0xd00 (expected: 0xd00)
571 22:17:29.470315 header.flags = 0x0
572 22:17:29.476571 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
573 22:17:29.493807 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
574 22:17:29.500553 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
575 22:17:29.503687 dram_init: ddr_geometry: 2
576 22:17:29.507398 [EMI] MDL number = 2
577 22:17:29.508096 [EMI] Get MDL freq = 0
578 22:17:29.510853 dram_init: ddr_type: 0
579 22:17:29.511448 is_discrete_lpddr4: 1
580 22:17:29.513833 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
581 22:17:29.514269
582 22:17:29.514610
583 22:17:29.517053 [Bian_co] ETT version 0.0.0.1
584 22:17:29.524293 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
585 22:17:29.524878
586 22:17:29.527067 dramc_set_vcore_voltage set vcore to 650000
587 22:17:29.527501 Read voltage for 800, 4
588 22:17:29.530603 Vio18 = 0
589 22:17:29.531164 Vcore = 650000
590 22:17:29.531650 Vdram = 0
591 22:17:29.533568 Vddq = 0
592 22:17:29.534073 Vmddr = 0
593 22:17:29.537027 dram_init: config_dvfs: 1
594 22:17:29.541886 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
595 22:17:29.547082 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
596 22:17:29.551270 [SwImpedanceCal] DRVP=8, DRVN=16, ODTN=9
597 22:17:29.553710 freq_region=0, Reg: DRVP=8, DRVN=16, ODTN=9
598 22:17:29.556983 [SwImpedanceCal] DRVP=14, DRVN=24, ODTN=9
599 22:17:29.561021 freq_region=1, Reg: DRVP=14, DRVN=24, ODTN=9
600 22:17:29.563947 MEM_TYPE=3, freq_sel=18
601 22:17:29.566883 sv_algorithm_assistance_LP4_1600
602 22:17:29.570170 ============ PULL DRAM RESETB DOWN ============
603 22:17:29.574175 ========== PULL DRAM RESETB DOWN end =========
604 22:17:29.580592 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
605 22:17:29.583897 ===================================
606 22:17:29.586872 LPDDR4 DRAM CONFIGURATION
607 22:17:29.590221 ===================================
608 22:17:29.590758 EX_ROW_EN[0] = 0x0
609 22:17:29.594167 EX_ROW_EN[1] = 0x0
610 22:17:29.594700 LP4Y_EN = 0x0
611 22:17:29.597799 WORK_FSP = 0x0
612 22:17:29.598484 WL = 0x2
613 22:17:29.600479 RL = 0x2
614 22:17:29.601175 BL = 0x2
615 22:17:29.603467 RPST = 0x0
616 22:17:29.603901 RD_PRE = 0x0
617 22:17:29.606680 WR_PRE = 0x1
618 22:17:29.607112 WR_PST = 0x0
619 22:17:29.610307 DBI_WR = 0x0
620 22:17:29.610739 DBI_RD = 0x0
621 22:17:29.613248 OTF = 0x1
622 22:17:29.616726 ===================================
623 22:17:29.620185 ===================================
624 22:17:29.620693 ANA top config
625 22:17:29.623672 ===================================
626 22:17:29.626580 DLL_ASYNC_EN = 0
627 22:17:29.630224 ALL_SLAVE_EN = 1
628 22:17:29.633403 NEW_RANK_MODE = 1
629 22:17:29.633837 DLL_IDLE_MODE = 1
630 22:17:29.636873 LP45_APHY_COMB_EN = 1
631 22:17:29.640962 TX_ODT_DIS = 1
632 22:17:29.643507 NEW_8X_MODE = 1
633 22:17:29.647312 ===================================
634 22:17:29.649897 ===================================
635 22:17:29.653461 data_rate = 1600
636 22:17:29.656336 CKR = 1
637 22:17:29.656589 DQ_P2S_RATIO = 8
638 22:17:29.659717 ===================================
639 22:17:29.662718 CA_P2S_RATIO = 8
640 22:17:29.666604 DQ_CA_OPEN = 0
641 22:17:29.669698 DQ_SEMI_OPEN = 0
642 22:17:29.672871 CA_SEMI_OPEN = 0
643 22:17:29.672991 CA_FULL_RATE = 0
644 22:17:29.676733 DQ_CKDIV4_EN = 1
645 22:17:29.679777 CA_CKDIV4_EN = 1
646 22:17:29.682676 CA_PREDIV_EN = 0
647 22:17:29.686292 PH8_DLY = 0
648 22:17:29.689533 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
649 22:17:29.689642 DQ_AAMCK_DIV = 4
650 22:17:29.692861 CA_AAMCK_DIV = 4
651 22:17:29.696438 CA_ADMCK_DIV = 4
652 22:17:29.700340 DQ_TRACK_CA_EN = 0
653 22:17:29.702872 CA_PICK = 800
654 22:17:29.705894 CA_MCKIO = 800
655 22:17:29.709627 MCKIO_SEMI = 0
656 22:17:29.709724 PLL_FREQ = 3068
657 22:17:29.712703 DQ_UI_PI_RATIO = 32
658 22:17:29.715931 CA_UI_PI_RATIO = 0
659 22:17:29.719707 ===================================
660 22:17:29.722714 ===================================
661 22:17:29.726227 memory_type:LPDDR4
662 22:17:29.726356 GP_NUM : 10
663 22:17:29.729454 SRAM_EN : 1
664 22:17:29.732777 MD32_EN : 0
665 22:17:29.735865 ===================================
666 22:17:29.735978 [ANA_INIT] >>>>>>>>>>>>>>
667 22:17:29.739562 <<<<<< [CONFIGURE PHASE]: ANA_TX
668 22:17:29.742394 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
669 22:17:29.745853 ===================================
670 22:17:29.749309 data_rate = 1600,PCW = 0X7600
671 22:17:29.752165 ===================================
672 22:17:29.755632 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
673 22:17:29.762919 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
674 22:17:29.765708 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
675 22:17:29.772923 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
676 22:17:29.776300 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
677 22:17:29.779848 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
678 22:17:29.782367 [ANA_INIT] flow start
679 22:17:29.782461 [ANA_INIT] PLL >>>>>>>>
680 22:17:29.785722 [ANA_INIT] PLL <<<<<<<<
681 22:17:29.789461 [ANA_INIT] MIDPI >>>>>>>>
682 22:17:29.789555 [ANA_INIT] MIDPI <<<<<<<<
683 22:17:29.792292 [ANA_INIT] DLL >>>>>>>>
684 22:17:29.795851 [ANA_INIT] flow end
685 22:17:29.798936 ============ LP4 DIFF to SE enter ============
686 22:17:29.802229 ============ LP4 DIFF to SE exit ============
687 22:17:29.805576 [ANA_INIT] <<<<<<<<<<<<<
688 22:17:29.809390 [Flow] Enable top DCM control >>>>>
689 22:17:29.812163 [Flow] Enable top DCM control <<<<<
690 22:17:29.815356 Enable DLL master slave shuffle
691 22:17:29.818837 ==============================================================
692 22:17:29.822298 Gating Mode config
693 22:17:29.828954 ==============================================================
694 22:17:29.829043 Config description:
695 22:17:29.839069 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
696 22:17:29.845206 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
697 22:17:29.848626 SELPH_MODE 0: By rank 1: By Phase
698 22:17:29.855430 ==============================================================
699 22:17:29.859010 GAT_TRACK_EN = 1
700 22:17:29.861888 RX_GATING_MODE = 2
701 22:17:29.865147 RX_GATING_TRACK_MODE = 2
702 22:17:29.869183 SELPH_MODE = 1
703 22:17:29.871958 PICG_EARLY_EN = 1
704 22:17:29.874971 VALID_LAT_VALUE = 1
705 22:17:29.878236 ==============================================================
706 22:17:29.881511 Enter into Gating configuration >>>>
707 22:17:29.884808 Exit from Gating configuration <<<<
708 22:17:29.889025 Enter into DVFS_PRE_config >>>>>
709 22:17:29.901668 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
710 22:17:29.901810 Exit from DVFS_PRE_config <<<<<
711 22:17:29.904994 Enter into PICG configuration >>>>
712 22:17:29.908295 Exit from PICG configuration <<<<
713 22:17:29.911908 [RX_INPUT] configuration >>>>>
714 22:17:29.914694 [RX_INPUT] configuration <<<<<
715 22:17:29.921706 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
716 22:17:29.925795 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
717 22:17:29.932622 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
718 22:17:29.940279 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
719 22:17:29.944413 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
720 22:17:29.950915 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
721 22:17:29.955306 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
722 22:17:29.958193 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
723 22:17:29.961590 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
724 22:17:29.969252 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
725 22:17:29.972872 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
726 22:17:29.976920 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
727 22:17:29.979784 ===================================
728 22:17:29.980407 LPDDR4 DRAM CONFIGURATION
729 22:17:29.983293 ===================================
730 22:17:29.987194 EX_ROW_EN[0] = 0x0
731 22:17:29.987885 EX_ROW_EN[1] = 0x0
732 22:17:29.990649 LP4Y_EN = 0x0
733 22:17:29.991175 WORK_FSP = 0x0
734 22:17:29.994618 WL = 0x2
735 22:17:29.995065 RL = 0x2
736 22:17:29.998037 BL = 0x2
737 22:17:29.998319 RPST = 0x0
738 22:17:30.002157 RD_PRE = 0x0
739 22:17:30.002414 WR_PRE = 0x1
740 22:17:30.005533 WR_PST = 0x0
741 22:17:30.005718 DBI_WR = 0x0
742 22:17:30.009478 DBI_RD = 0x0
743 22:17:30.009633 OTF = 0x1
744 22:17:30.012752 ===================================
745 22:17:30.016383 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
746 22:17:30.020294 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
747 22:17:30.023626 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
748 22:17:30.027183 ===================================
749 22:17:30.031325 LPDDR4 DRAM CONFIGURATION
750 22:17:30.034884 ===================================
751 22:17:30.035010 EX_ROW_EN[0] = 0x10
752 22:17:30.038492 EX_ROW_EN[1] = 0x0
753 22:17:30.038585 LP4Y_EN = 0x0
754 22:17:30.041792 WORK_FSP = 0x0
755 22:17:30.041879 WL = 0x2
756 22:17:30.045395 RL = 0x2
757 22:17:30.045479 BL = 0x2
758 22:17:30.049155 RPST = 0x0
759 22:17:30.049238 RD_PRE = 0x0
760 22:17:30.052797 WR_PRE = 0x1
761 22:17:30.052881 WR_PST = 0x0
762 22:17:30.056067 DBI_WR = 0x0
763 22:17:30.056149 DBI_RD = 0x0
764 22:17:30.059925 OTF = 0x1
765 22:17:30.063402 ===================================
766 22:17:30.066967 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
767 22:17:30.072874 nWR fixed to 40
768 22:17:30.075425 [ModeRegInit_LP4] CH0 RK0
769 22:17:30.075508 [ModeRegInit_LP4] CH0 RK1
770 22:17:30.079068 [ModeRegInit_LP4] CH1 RK0
771 22:17:30.082191 [ModeRegInit_LP4] CH1 RK1
772 22:17:30.082275 match AC timing 13
773 22:17:30.088910 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
774 22:17:30.092305 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
775 22:17:30.095855 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
776 22:17:30.099358 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
777 22:17:30.105844 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
778 22:17:30.105927 [EMI DOE] emi_dcm 0
779 22:17:30.112232 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
780 22:17:30.112323 ==
781 22:17:30.116082 Dram Type= 6, Freq= 0, CH_0, rank 0
782 22:17:30.119932 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
783 22:17:30.120008 ==
784 22:17:30.123269 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
785 22:17:30.129597 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
786 22:17:30.139864 [CA 0] Center 37 (6~68) winsize 63
787 22:17:30.142720 [CA 1] Center 37 (7~67) winsize 61
788 22:17:30.145900 [CA 2] Center 34 (4~65) winsize 62
789 22:17:30.149432 [CA 3] Center 34 (4~65) winsize 62
790 22:17:30.152987 [CA 4] Center 34 (4~64) winsize 61
791 22:17:30.156276 [CA 5] Center 33 (3~64) winsize 62
792 22:17:30.156807
793 22:17:30.159732 [CmdBusTrainingLP45] Vref(ca) range 1: 30
794 22:17:30.160176
795 22:17:30.163292 [CATrainingPosCal] consider 1 rank data
796 22:17:30.166538 u2DelayCellTimex100 = 270/100 ps
797 22:17:30.169915 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
798 22:17:30.172691 CA1 delay=37 (7~67),Diff = 4 PI (28 cell)
799 22:17:30.179567 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
800 22:17:30.182991 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
801 22:17:30.186458 CA4 delay=34 (4~64),Diff = 1 PI (7 cell)
802 22:17:30.189402 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
803 22:17:30.189961
804 22:17:30.192553 CA PerBit enable=1, Macro0, CA PI delay=33
805 22:17:30.192990
806 22:17:30.195999 [CBTSetCACLKResult] CA Dly = 33
807 22:17:30.196433 CS Dly: 7 (0~38)
808 22:17:30.199150 ==
809 22:17:30.199581 Dram Type= 6, Freq= 0, CH_0, rank 1
810 22:17:30.206394 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
811 22:17:30.206829 ==
812 22:17:30.209509 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
813 22:17:30.216464 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
814 22:17:30.225629 [CA 0] Center 36 (6~67) winsize 62
815 22:17:30.229468 [CA 1] Center 37 (7~68) winsize 62
816 22:17:30.232054 [CA 2] Center 34 (4~65) winsize 62
817 22:17:30.235808 [CA 3] Center 34 (4~65) winsize 62
818 22:17:30.239016 [CA 4] Center 33 (3~64) winsize 62
819 22:17:30.242576 [CA 5] Center 33 (2~64) winsize 63
820 22:17:30.243041
821 22:17:30.245449 [CmdBusTrainingLP45] Vref(ca) range 1: 34
822 22:17:30.245882
823 22:17:30.248633 [CATrainingPosCal] consider 2 rank data
824 22:17:30.252285 u2DelayCellTimex100 = 270/100 ps
825 22:17:30.255057 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
826 22:17:30.262212 CA1 delay=37 (7~67),Diff = 4 PI (28 cell)
827 22:17:30.265750 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
828 22:17:30.269161 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
829 22:17:30.272840 CA4 delay=34 (4~64),Diff = 1 PI (7 cell)
830 22:17:30.276373 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
831 22:17:30.276839
832 22:17:30.280731 CA PerBit enable=1, Macro0, CA PI delay=33
833 22:17:30.281265
834 22:17:30.283706 [CBTSetCACLKResult] CA Dly = 33
835 22:17:30.284189 CS Dly: 7 (0~38)
836 22:17:30.284577
837 22:17:30.287905 ----->DramcWriteLeveling(PI) begin...
838 22:17:30.288344 ==
839 22:17:30.291076 Dram Type= 6, Freq= 0, CH_0, rank 0
840 22:17:30.294619 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
841 22:17:30.295058 ==
842 22:17:30.298551 Write leveling (Byte 0): 32 => 32
843 22:17:30.302100 Write leveling (Byte 1): 30 => 30
844 22:17:30.305256 DramcWriteLeveling(PI) end<-----
845 22:17:30.305689
846 22:17:30.306025 ==
847 22:17:30.309188 Dram Type= 6, Freq= 0, CH_0, rank 0
848 22:17:30.313143 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
849 22:17:30.313604 ==
850 22:17:30.315049 [Gating] SW mode calibration
851 22:17:30.321277 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
852 22:17:30.328549 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
853 22:17:30.331670 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
854 22:17:30.335013 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
855 22:17:30.341405 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
856 22:17:30.344676 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
857 22:17:30.348063 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 22:17:30.354712 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 22:17:30.357627 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 22:17:30.361249 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 22:17:30.367980 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 22:17:30.371217 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 22:17:30.374638 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 22:17:30.381580 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 22:17:30.384417 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 22:17:30.387696 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 22:17:30.394277 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 22:17:30.397657 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 22:17:30.402099 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 22:17:30.407390 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
871 22:17:30.410897 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
872 22:17:30.414229 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
873 22:17:30.420661 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 22:17:30.424265 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 22:17:30.427676 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 22:17:30.434807 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
877 22:17:30.437802 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
878 22:17:30.440936 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
879 22:17:30.447733 0 9 8 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
880 22:17:30.451618 0 9 12 | B1->B0 | 2b2b 3434 | 0 1 | (0 0) (1 1)
881 22:17:30.454649 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
882 22:17:30.457694 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
883 22:17:30.463976 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
884 22:17:30.467307 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
885 22:17:30.470753 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
886 22:17:30.477407 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
887 22:17:30.480285 0 10 8 | B1->B0 | 3434 2a2a | 1 0 | (1 1) (1 0)
888 22:17:30.483565 0 10 12 | B1->B0 | 2d2d 2323 | 0 0 | (0 0) (0 0)
889 22:17:30.490182 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 22:17:30.493497 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
891 22:17:30.497653 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
892 22:17:30.503847 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
893 22:17:30.507040 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
894 22:17:30.511292 0 11 4 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
895 22:17:30.517048 0 11 8 | B1->B0 | 2424 3a3a | 0 0 | (0 0) (0 0)
896 22:17:30.520603 0 11 12 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
897 22:17:30.523999 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 22:17:30.530089 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
899 22:17:30.533485 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
900 22:17:30.537636 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
901 22:17:30.543941 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
902 22:17:30.547316 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
903 22:17:30.550102 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
904 22:17:30.556892 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 22:17:30.560305 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 22:17:30.563922 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 22:17:30.570529 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 22:17:30.573887 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 22:17:30.577237 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 22:17:30.583704 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 22:17:30.587446 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 22:17:30.590604 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 22:17:30.593572 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
914 22:17:30.600244 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
915 22:17:30.603586 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
916 22:17:30.607385 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
917 22:17:30.613491 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
918 22:17:30.616983 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
919 22:17:30.619847 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
920 22:17:30.627037 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
921 22:17:30.629934 Total UI for P1: 0, mck2ui 16
922 22:17:30.633545 best dqsien dly found for B0: ( 0, 14, 6)
923 22:17:30.637080 Total UI for P1: 0, mck2ui 16
924 22:17:30.640332 best dqsien dly found for B1: ( 0, 14, 8)
925 22:17:30.643709 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
926 22:17:30.646471 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
927 22:17:30.646898
928 22:17:30.650113 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
929 22:17:30.653523 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
930 22:17:30.657465 [Gating] SW calibration Done
931 22:17:30.658030 ==
932 22:17:30.660811 Dram Type= 6, Freq= 0, CH_0, rank 0
933 22:17:30.664011 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 22:17:30.664748 ==
935 22:17:30.665258 RX Vref Scan: 0
936 22:17:30.667683
937 22:17:30.668086 RX Vref 0 -> 0, step: 1
938 22:17:30.668548
939 22:17:30.670997 RX Delay -130 -> 252, step: 16
940 22:17:30.674208 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
941 22:17:30.677955 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
942 22:17:30.684813 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
943 22:17:30.688062 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
944 22:17:30.692078 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
945 22:17:30.695431 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
946 22:17:30.699144 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
947 22:17:30.702342 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
948 22:17:30.705910 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
949 22:17:30.710282 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
950 22:17:30.713943 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
951 22:17:30.723350 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
952 22:17:30.724300 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
953 22:17:30.728396 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
954 22:17:30.731543 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
955 22:17:30.735032 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
956 22:17:30.735457 ==
957 22:17:30.738307 Dram Type= 6, Freq= 0, CH_0, rank 0
958 22:17:30.742262 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
959 22:17:30.742691 ==
960 22:17:30.745114 DQS Delay:
961 22:17:30.745536 DQS0 = 0, DQS1 = 0
962 22:17:30.748492 DQM Delay:
963 22:17:30.748950 DQM0 = 85, DQM1 = 71
964 22:17:30.749286 DQ Delay:
965 22:17:30.751628 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
966 22:17:30.754698 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
967 22:17:30.758274 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =61
968 22:17:30.761314 DQ12 =77, DQ13 =77, DQ14 =85, DQ15 =77
969 22:17:30.761743
970 22:17:30.762079
971 22:17:30.765062 ==
972 22:17:30.765491 Dram Type= 6, Freq= 0, CH_0, rank 0
973 22:17:30.771574 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
974 22:17:30.772007 ==
975 22:17:30.772343
976 22:17:30.772709
977 22:17:30.774982 TX Vref Scan disable
978 22:17:30.775517 == TX Byte 0 ==
979 22:17:30.778193 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
980 22:17:30.785132 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
981 22:17:30.785717 == TX Byte 1 ==
982 22:17:30.788477 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
983 22:17:30.792041 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
984 22:17:30.795394 ==
985 22:17:30.795822 Dram Type= 6, Freq= 0, CH_0, rank 0
986 22:17:30.802510 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
987 22:17:30.802969 ==
988 22:17:30.814758 TX Vref=22, minBit 3, minWin=27, winSum=443
989 22:17:30.817983 TX Vref=24, minBit 8, minWin=27, winSum=446
990 22:17:30.821463 TX Vref=26, minBit 8, minWin=27, winSum=447
991 22:17:30.824801 TX Vref=28, minBit 5, minWin=27, winSum=447
992 22:17:30.828260 TX Vref=30, minBit 8, minWin=27, winSum=449
993 22:17:30.831603 TX Vref=32, minBit 4, minWin=27, winSum=446
994 22:17:30.838164 [TxChooseVref] Worse bit 8, Min win 27, Win sum 449, Final Vref 30
995 22:17:30.838593
996 22:17:30.841480 Final TX Range 1 Vref 30
997 22:17:30.841913
998 22:17:30.842279 ==
999 22:17:30.845123 Dram Type= 6, Freq= 0, CH_0, rank 0
1000 22:17:30.847750 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1001 22:17:30.848179 ==
1002 22:17:30.848532
1003 22:17:30.848854
1004 22:17:30.851220 TX Vref Scan disable
1005 22:17:30.854682 == TX Byte 0 ==
1006 22:17:30.858093 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1007 22:17:30.861562 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1008 22:17:30.864427 == TX Byte 1 ==
1009 22:17:30.868264 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1010 22:17:30.871582 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1011 22:17:30.872024
1012 22:17:30.874663 [DATLAT]
1013 22:17:30.875082 Freq=800, CH0 RK0
1014 22:17:30.875416
1015 22:17:30.877692 DATLAT Default: 0xa
1016 22:17:30.878109 0, 0xFFFF, sum = 0
1017 22:17:30.881282 1, 0xFFFF, sum = 0
1018 22:17:30.881723 2, 0xFFFF, sum = 0
1019 22:17:30.884336 3, 0xFFFF, sum = 0
1020 22:17:30.884817 4, 0xFFFF, sum = 0
1021 22:17:30.887739 5, 0xFFFF, sum = 0
1022 22:17:30.888163 6, 0xFFFF, sum = 0
1023 22:17:30.891101 7, 0xFFFF, sum = 0
1024 22:17:30.894218 8, 0xFFFF, sum = 0
1025 22:17:30.894684 9, 0x0, sum = 1
1026 22:17:30.895022 10, 0x0, sum = 2
1027 22:17:30.898078 11, 0x0, sum = 3
1028 22:17:30.898499 12, 0x0, sum = 4
1029 22:17:30.901357 best_step = 10
1030 22:17:30.901904
1031 22:17:30.902239 ==
1032 22:17:30.904245 Dram Type= 6, Freq= 0, CH_0, rank 0
1033 22:17:30.908229 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1034 22:17:30.908820 ==
1035 22:17:30.910819 RX Vref Scan: 1
1036 22:17:30.911233
1037 22:17:30.911562 Set Vref Range= 32 -> 127
1038 22:17:30.914250
1039 22:17:30.915058 RX Vref 32 -> 127, step: 1
1040 22:17:30.915537
1041 22:17:30.917896 RX Delay -111 -> 252, step: 8
1042 22:17:30.918461
1043 22:17:30.921239 Set Vref, RX VrefLevel [Byte0]: 32
1044 22:17:30.924284 [Byte1]: 32
1045 22:17:30.924744
1046 22:17:30.927309 Set Vref, RX VrefLevel [Byte0]: 33
1047 22:17:30.931527 [Byte1]: 33
1048 22:17:30.934815
1049 22:17:30.935229 Set Vref, RX VrefLevel [Byte0]: 34
1050 22:17:30.938087 [Byte1]: 34
1051 22:17:30.942793
1052 22:17:30.943206 Set Vref, RX VrefLevel [Byte0]: 35
1053 22:17:30.945800 [Byte1]: 35
1054 22:17:30.950104
1055 22:17:30.950519 Set Vref, RX VrefLevel [Byte0]: 36
1056 22:17:30.953469 [Byte1]: 36
1057 22:17:30.958125
1058 22:17:30.958620 Set Vref, RX VrefLevel [Byte0]: 37
1059 22:17:30.961500 [Byte1]: 37
1060 22:17:30.965184
1061 22:17:30.965604 Set Vref, RX VrefLevel [Byte0]: 38
1062 22:17:30.969314 [Byte1]: 38
1063 22:17:30.973200
1064 22:17:30.973618 Set Vref, RX VrefLevel [Byte0]: 39
1065 22:17:30.976470 [Byte1]: 39
1066 22:17:30.980715
1067 22:17:30.981135 Set Vref, RX VrefLevel [Byte0]: 40
1068 22:17:30.987231 [Byte1]: 40
1069 22:17:30.987657
1070 22:17:30.990858 Set Vref, RX VrefLevel [Byte0]: 41
1071 22:17:30.994110 [Byte1]: 41
1072 22:17:30.994536
1073 22:17:30.997546 Set Vref, RX VrefLevel [Byte0]: 42
1074 22:17:31.000754 [Byte1]: 42
1075 22:17:31.003978
1076 22:17:31.004399 Set Vref, RX VrefLevel [Byte0]: 43
1077 22:17:31.007351 [Byte1]: 43
1078 22:17:31.011453
1079 22:17:31.011875 Set Vref, RX VrefLevel [Byte0]: 44
1080 22:17:31.014706 [Byte1]: 44
1081 22:17:31.019403
1082 22:17:31.019908 Set Vref, RX VrefLevel [Byte0]: 45
1083 22:17:31.023100 [Byte1]: 45
1084 22:17:31.026325
1085 22:17:31.029927 Set Vref, RX VrefLevel [Byte0]: 46
1086 22:17:31.030447 [Byte1]: 46
1087 22:17:31.034225
1088 22:17:31.034649 Set Vref, RX VrefLevel [Byte0]: 47
1089 22:17:31.037787 [Byte1]: 47
1090 22:17:31.041560
1091 22:17:31.041986 Set Vref, RX VrefLevel [Byte0]: 48
1092 22:17:31.045024 [Byte1]: 48
1093 22:17:31.049614
1094 22:17:31.050035 Set Vref, RX VrefLevel [Byte0]: 49
1095 22:17:31.053114 [Byte1]: 49
1096 22:17:31.057762
1097 22:17:31.058172 Set Vref, RX VrefLevel [Byte0]: 50
1098 22:17:31.060553 [Byte1]: 50
1099 22:17:31.065051
1100 22:17:31.065479 Set Vref, RX VrefLevel [Byte0]: 51
1101 22:17:31.068853 [Byte1]: 51
1102 22:17:31.072885
1103 22:17:31.073302 Set Vref, RX VrefLevel [Byte0]: 52
1104 22:17:31.076265 [Byte1]: 52
1105 22:17:31.080128
1106 22:17:31.080582 Set Vref, RX VrefLevel [Byte0]: 53
1107 22:17:31.083809 [Byte1]: 53
1108 22:17:31.087905
1109 22:17:31.088328 Set Vref, RX VrefLevel [Byte0]: 54
1110 22:17:31.091396 [Byte1]: 54
1111 22:17:31.095643
1112 22:17:31.096063 Set Vref, RX VrefLevel [Byte0]: 55
1113 22:17:31.098624 [Byte1]: 55
1114 22:17:31.102983
1115 22:17:31.105992 Set Vref, RX VrefLevel [Byte0]: 56
1116 22:17:31.109526 [Byte1]: 56
1117 22:17:31.110116
1118 22:17:31.112354 Set Vref, RX VrefLevel [Byte0]: 57
1119 22:17:31.116447 [Byte1]: 57
1120 22:17:31.117049
1121 22:17:31.119768 Set Vref, RX VrefLevel [Byte0]: 58
1122 22:17:31.123651 [Byte1]: 58
1123 22:17:31.124077
1124 22:17:31.127310 Set Vref, RX VrefLevel [Byte0]: 59
1125 22:17:31.130662 [Byte1]: 59
1126 22:17:31.131490
1127 22:17:31.135033 Set Vref, RX VrefLevel [Byte0]: 60
1128 22:17:31.138398 [Byte1]: 60
1129 22:17:31.138835
1130 22:17:31.141826 Set Vref, RX VrefLevel [Byte0]: 61
1131 22:17:31.145017 [Byte1]: 61
1132 22:17:31.149560
1133 22:17:31.150029 Set Vref, RX VrefLevel [Byte0]: 62
1134 22:17:31.152870 [Byte1]: 62
1135 22:17:31.156555
1136 22:17:31.157000 Set Vref, RX VrefLevel [Byte0]: 63
1137 22:17:31.160136 [Byte1]: 63
1138 22:17:31.164977
1139 22:17:31.165388 Set Vref, RX VrefLevel [Byte0]: 64
1140 22:17:31.168296 [Byte1]: 64
1141 22:17:31.172375
1142 22:17:31.172998 Set Vref, RX VrefLevel [Byte0]: 65
1143 22:17:31.175279 [Byte1]: 65
1144 22:17:31.179497
1145 22:17:31.179908 Set Vref, RX VrefLevel [Byte0]: 66
1146 22:17:31.182597 [Byte1]: 66
1147 22:17:31.187283
1148 22:17:31.187696 Set Vref, RX VrefLevel [Byte0]: 67
1149 22:17:31.190845 [Byte1]: 67
1150 22:17:31.195342
1151 22:17:31.195756 Set Vref, RX VrefLevel [Byte0]: 68
1152 22:17:31.198517 [Byte1]: 68
1153 22:17:31.202593
1154 22:17:31.203001 Set Vref, RX VrefLevel [Byte0]: 69
1155 22:17:31.206357 [Byte1]: 69
1156 22:17:31.210263
1157 22:17:31.210731 Set Vref, RX VrefLevel [Byte0]: 70
1158 22:17:31.213871 [Byte1]: 70
1159 22:17:31.218087
1160 22:17:31.218605 Set Vref, RX VrefLevel [Byte0]: 71
1161 22:17:31.221443 [Byte1]: 71
1162 22:17:31.225770
1163 22:17:31.226379 Set Vref, RX VrefLevel [Byte0]: 72
1164 22:17:31.229128 [Byte1]: 72
1165 22:17:31.232871
1166 22:17:31.233306 Set Vref, RX VrefLevel [Byte0]: 73
1167 22:17:31.236456 [Byte1]: 73
1168 22:17:31.241257
1169 22:17:31.241685 Set Vref, RX VrefLevel [Byte0]: 74
1170 22:17:31.244379 [Byte1]: 74
1171 22:17:31.248584
1172 22:17:31.248999 Set Vref, RX VrefLevel [Byte0]: 75
1173 22:17:31.252417 [Byte1]: 75
1174 22:17:31.255964
1175 22:17:31.256377 Set Vref, RX VrefLevel [Byte0]: 76
1176 22:17:31.259399 [Byte1]: 76
1177 22:17:31.263313
1178 22:17:31.266451 Set Vref, RX VrefLevel [Byte0]: 77
1179 22:17:31.266825 [Byte1]: 77
1180 22:17:31.271429
1181 22:17:31.271875 Set Vref, RX VrefLevel [Byte0]: 78
1182 22:17:31.274378 [Byte1]: 78
1183 22:17:31.278922
1184 22:17:31.279340 Set Vref, RX VrefLevel [Byte0]: 79
1185 22:17:31.282274 [Byte1]: 79
1186 22:17:31.286783
1187 22:17:31.287200 Set Vref, RX VrefLevel [Byte0]: 80
1188 22:17:31.290256 [Byte1]: 80
1189 22:17:31.294277
1190 22:17:31.294695 Set Vref, RX VrefLevel [Byte0]: 81
1191 22:17:31.297579 [Byte1]: 81
1192 22:17:31.302141
1193 22:17:31.302559 Set Vref, RX VrefLevel [Byte0]: 82
1194 22:17:31.305453 [Byte1]: 82
1195 22:17:31.309921
1196 22:17:31.310368 Final RX Vref Byte 0 = 63 to rank0
1197 22:17:31.312912 Final RX Vref Byte 1 = 50 to rank0
1198 22:17:31.317273 Final RX Vref Byte 0 = 63 to rank1
1199 22:17:31.320542 Final RX Vref Byte 1 = 50 to rank1==
1200 22:17:31.324384 Dram Type= 6, Freq= 0, CH_0, rank 0
1201 22:17:31.328441 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1202 22:17:31.329002 ==
1203 22:17:31.329425 DQS Delay:
1204 22:17:31.331353 DQS0 = 0, DQS1 = 0
1205 22:17:31.331818 DQM Delay:
1206 22:17:31.335147 DQM0 = 86, DQM1 = 76
1207 22:17:31.335641 DQ Delay:
1208 22:17:31.339147 DQ0 =84, DQ1 =92, DQ2 =84, DQ3 =80
1209 22:17:31.343302 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =96
1210 22:17:31.343720 DQ8 =68, DQ9 =64, DQ10 =76, DQ11 =68
1211 22:17:31.346935 DQ12 =80, DQ13 =80, DQ14 =88, DQ15 =84
1212 22:17:31.347475
1213 22:17:31.347820
1214 22:17:31.357440 [DQSOSCAuto] RK0, (LSB)MR18= 0x4729, (MSB)MR19= 0x606, tDQSOscB0 = 399 ps tDQSOscB1 = 392 ps
1215 22:17:31.358004 CH0 RK0: MR19=606, MR18=4729
1216 22:17:31.365802 CH0_RK0: MR19=0x606, MR18=0x4729, DQSOSC=392, MR23=63, INC=96, DEC=64
1217 22:17:31.366311
1218 22:17:31.368809 ----->DramcWriteLeveling(PI) begin...
1219 22:17:31.369229 ==
1220 22:17:31.372650 Dram Type= 6, Freq= 0, CH_0, rank 1
1221 22:17:31.376127 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1222 22:17:31.376577 ==
1223 22:17:31.379759 Write leveling (Byte 0): 34 => 34
1224 22:17:31.383010 Write leveling (Byte 1): 28 => 28
1225 22:17:31.386642 DramcWriteLeveling(PI) end<-----
1226 22:17:31.387055
1227 22:17:31.387417 ==
1228 22:17:31.431212 Dram Type= 6, Freq= 0, CH_0, rank 1
1229 22:17:31.431908 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1230 22:17:31.432414 ==
1231 22:17:31.433019 [Gating] SW mode calibration
1232 22:17:31.433816 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1233 22:17:31.434194 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1234 22:17:31.434528 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1235 22:17:31.434856 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1236 22:17:31.435261 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1237 22:17:31.435582 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1238 22:17:31.435863 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1239 22:17:31.474537 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1240 22:17:31.475453 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1241 22:17:31.476009 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1242 22:17:31.476457 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1243 22:17:31.476984 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1244 22:17:31.477353 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1245 22:17:31.477750 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1246 22:17:31.478121 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1247 22:17:31.478489 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1248 22:17:31.478928 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1249 22:17:31.518237 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1250 22:17:31.518614 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1251 22:17:31.519085 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1252 22:17:31.519183 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1253 22:17:31.519707 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1254 22:17:31.520655 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1255 22:17:31.520918 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1256 22:17:31.520989 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1257 22:17:31.521267 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1258 22:17:31.521674 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1259 22:17:31.529740 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1260 22:17:31.530064 0 9 8 | B1->B0 | 2424 2d2d | 1 0 | (1 1) (0 0)
1261 22:17:31.530163 0 9 12 | B1->B0 | 3332 3434 | 1 1 | (0 0) (1 1)
1262 22:17:31.536338 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1263 22:17:31.539798 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1264 22:17:31.543160 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1265 22:17:31.550764 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1266 22:17:31.553178 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1267 22:17:31.556431 0 10 4 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
1268 22:17:31.563038 0 10 8 | B1->B0 | 3131 2b2b | 1 0 | (1 0) (0 0)
1269 22:17:31.566716 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1270 22:17:31.570001 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1271 22:17:31.576316 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1272 22:17:31.579772 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1273 22:17:31.582898 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1274 22:17:31.589330 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1275 22:17:31.593127 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1276 22:17:31.596287 0 11 8 | B1->B0 | 2b2b 3b3b | 1 0 | (0 0) (1 1)
1277 22:17:31.602767 0 11 12 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
1278 22:17:31.606267 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1279 22:17:31.609932 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1280 22:17:31.615833 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1281 22:17:31.619459 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1282 22:17:31.623206 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1283 22:17:31.629308 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1284 22:17:31.632758 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1285 22:17:31.636185 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1286 22:17:31.642618 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1287 22:17:31.646325 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1288 22:17:31.650075 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1289 22:17:31.655829 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1290 22:17:31.659401 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1291 22:17:31.663142 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1292 22:17:31.669551 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1293 22:17:31.672474 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1294 22:17:31.676238 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1295 22:17:31.679707 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1296 22:17:31.686029 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1297 22:17:31.689465 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1298 22:17:31.692253 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1299 22:17:31.699160 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1300 22:17:31.702849 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
1301 22:17:31.705423 Total UI for P1: 0, mck2ui 16
1302 22:17:31.708903 best dqsien dly found for B0: ( 0, 14, 6)
1303 22:17:31.712191 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1304 22:17:31.715754 Total UI for P1: 0, mck2ui 16
1305 22:17:31.719483 best dqsien dly found for B1: ( 0, 14, 10)
1306 22:17:31.722776 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1307 22:17:31.726015 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
1308 22:17:31.729087
1309 22:17:31.732459 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1310 22:17:31.735232 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
1311 22:17:31.739377 [Gating] SW calibration Done
1312 22:17:31.739793 ==
1313 22:17:31.741999 Dram Type= 6, Freq= 0, CH_0, rank 1
1314 22:17:31.745474 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1315 22:17:31.745895 ==
1316 22:17:31.746225 RX Vref Scan: 0
1317 22:17:31.748479
1318 22:17:31.748932 RX Vref 0 -> 0, step: 1
1319 22:17:31.749261
1320 22:17:31.752070 RX Delay -130 -> 252, step: 16
1321 22:17:31.755448 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1322 22:17:31.758632 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1323 22:17:31.765173 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1324 22:17:31.769176 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1325 22:17:31.772053 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1326 22:17:31.775282 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1327 22:17:31.778524 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1328 22:17:31.785574 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1329 22:17:31.789055 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1330 22:17:31.791960 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1331 22:17:31.795454 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1332 22:17:31.798693 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1333 22:17:31.805550 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1334 22:17:31.809193 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1335 22:17:31.811854 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1336 22:17:31.815604 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1337 22:17:31.816056 ==
1338 22:17:31.819102 Dram Type= 6, Freq= 0, CH_0, rank 1
1339 22:17:31.826268 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1340 22:17:31.826690 ==
1341 22:17:31.827019 DQS Delay:
1342 22:17:31.828221 DQS0 = 0, DQS1 = 0
1343 22:17:31.828698 DQM Delay:
1344 22:17:31.829028 DQM0 = 85, DQM1 = 77
1345 22:17:31.831902 DQ Delay:
1346 22:17:31.834862 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
1347 22:17:31.838507 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
1348 22:17:31.841701 DQ8 =69, DQ9 =61, DQ10 =77, DQ11 =69
1349 22:17:31.845211 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1350 22:17:31.845771
1351 22:17:31.846237
1352 22:17:31.846681 ==
1353 22:17:31.847978 Dram Type= 6, Freq= 0, CH_0, rank 1
1354 22:17:31.852126 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1355 22:17:31.852581 ==
1356 22:17:31.853045
1357 22:17:31.853365
1358 22:17:31.855639 TX Vref Scan disable
1359 22:17:31.858200 == TX Byte 0 ==
1360 22:17:31.861316 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
1361 22:17:31.864723 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
1362 22:17:31.867821 == TX Byte 1 ==
1363 22:17:31.871478 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1364 22:17:31.874816 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1365 22:17:31.875224 ==
1366 22:17:31.878122 Dram Type= 6, Freq= 0, CH_0, rank 1
1367 22:17:31.881496 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1368 22:17:31.884366 ==
1369 22:17:31.896512 TX Vref=22, minBit 8, minWin=26, winSum=440
1370 22:17:31.900097 TX Vref=24, minBit 3, minWin=27, winSum=442
1371 22:17:31.903276 TX Vref=26, minBit 3, minWin=27, winSum=446
1372 22:17:31.906738 TX Vref=28, minBit 9, minWin=27, winSum=448
1373 22:17:31.909532 TX Vref=30, minBit 9, minWin=27, winSum=446
1374 22:17:31.916682 TX Vref=32, minBit 9, minWin=27, winSum=445
1375 22:17:31.919444 [TxChooseVref] Worse bit 9, Min win 27, Win sum 448, Final Vref 28
1376 22:17:31.919852
1377 22:17:31.922917 Final TX Range 1 Vref 28
1378 22:17:31.923369
1379 22:17:31.923869 ==
1380 22:17:31.926608 Dram Type= 6, Freq= 0, CH_0, rank 1
1381 22:17:31.929943 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1382 22:17:31.930360 ==
1383 22:17:31.933152
1384 22:17:31.933556
1385 22:17:31.933872 TX Vref Scan disable
1386 22:17:31.936768 == TX Byte 0 ==
1387 22:17:31.939975 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
1388 22:17:31.947059 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
1389 22:17:31.947470 == TX Byte 1 ==
1390 22:17:31.949716 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1391 22:17:31.956835 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1392 22:17:31.957334
1393 22:17:31.957656 [DATLAT]
1394 22:17:31.957949 Freq=800, CH0 RK1
1395 22:17:31.958232
1396 22:17:31.959722 DATLAT Default: 0xa
1397 22:17:31.960129 0, 0xFFFF, sum = 0
1398 22:17:31.963620 1, 0xFFFF, sum = 0
1399 22:17:31.964132 2, 0xFFFF, sum = 0
1400 22:17:31.966702 3, 0xFFFF, sum = 0
1401 22:17:31.969879 4, 0xFFFF, sum = 0
1402 22:17:31.970407 5, 0xFFFF, sum = 0
1403 22:17:31.973059 6, 0xFFFF, sum = 0
1404 22:17:31.973466 7, 0xFFFF, sum = 0
1405 22:17:31.976695 8, 0xFFFF, sum = 0
1406 22:17:31.977105 9, 0x0, sum = 1
1407 22:17:31.979515 10, 0x0, sum = 2
1408 22:17:31.979924 11, 0x0, sum = 3
1409 22:17:31.980244 12, 0x0, sum = 4
1410 22:17:31.983215 best_step = 10
1411 22:17:31.983721
1412 22:17:31.984039 ==
1413 22:17:31.986183 Dram Type= 6, Freq= 0, CH_0, rank 1
1414 22:17:31.989179 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1415 22:17:31.989587 ==
1416 22:17:31.993414 RX Vref Scan: 0
1417 22:17:31.993818
1418 22:17:31.996165 RX Vref 0 -> 0, step: 1
1419 22:17:31.996710
1420 22:17:31.997039 RX Delay -111 -> 252, step: 8
1421 22:17:32.003301 iDelay=209, Bit 0, Center 80 (-31 ~ 192) 224
1422 22:17:32.006273 iDelay=209, Bit 1, Center 92 (-23 ~ 208) 232
1423 22:17:32.010254 iDelay=209, Bit 2, Center 80 (-31 ~ 192) 224
1424 22:17:32.013277 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
1425 22:17:32.016460 iDelay=209, Bit 4, Center 84 (-31 ~ 200) 232
1426 22:17:32.023015 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1427 22:17:32.026457 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
1428 22:17:32.029529 iDelay=209, Bit 7, Center 92 (-23 ~ 208) 232
1429 22:17:32.033226 iDelay=209, Bit 8, Center 64 (-47 ~ 176) 224
1430 22:17:32.036469 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
1431 22:17:32.042673 iDelay=209, Bit 10, Center 76 (-39 ~ 192) 232
1432 22:17:32.046394 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
1433 22:17:32.049812 iDelay=209, Bit 12, Center 84 (-31 ~ 200) 232
1434 22:17:32.052839 iDelay=209, Bit 13, Center 84 (-31 ~ 200) 232
1435 22:17:32.059637 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1436 22:17:32.062989 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
1437 22:17:32.063672 ==
1438 22:17:32.066271 Dram Type= 6, Freq= 0, CH_0, rank 1
1439 22:17:32.069503 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1440 22:17:32.069931 ==
1441 22:17:32.072883 DQS Delay:
1442 22:17:32.073308 DQS0 = 0, DQS1 = 0
1443 22:17:32.073640 DQM Delay:
1444 22:17:32.076263 DQM0 = 85, DQM1 = 76
1445 22:17:32.076957 DQ Delay:
1446 22:17:32.079359 DQ0 =80, DQ1 =92, DQ2 =80, DQ3 =84
1447 22:17:32.083123 DQ4 =84, DQ5 =76, DQ6 =92, DQ7 =92
1448 22:17:32.085923 DQ8 =64, DQ9 =64, DQ10 =76, DQ11 =68
1449 22:17:32.089112 DQ12 =84, DQ13 =84, DQ14 =88, DQ15 =84
1450 22:17:32.089534
1451 22:17:32.089867
1452 22:17:32.099436 [DQSOSCAuto] RK1, (LSB)MR18= 0x430a, (MSB)MR19= 0x606, tDQSOscB0 = 407 ps tDQSOscB1 = 393 ps
1453 22:17:32.099864 CH0 RK1: MR19=606, MR18=430A
1454 22:17:32.106134 CH0_RK1: MR19=0x606, MR18=0x430A, DQSOSC=393, MR23=63, INC=95, DEC=63
1455 22:17:32.109276 [RxdqsGatingPostProcess] freq 800
1456 22:17:32.115580 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1457 22:17:32.120230 Pre-setting of DQS Precalculation
1458 22:17:32.122309 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1459 22:17:32.122734 ==
1460 22:17:32.125712 Dram Type= 6, Freq= 0, CH_1, rank 0
1461 22:17:32.132579 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1462 22:17:32.133250 ==
1463 22:17:32.136075 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1464 22:17:32.142559 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1465 22:17:32.151189 [CA 0] Center 36 (6~67) winsize 62
1466 22:17:32.155429 [CA 1] Center 36 (6~67) winsize 62
1467 22:17:32.158613 [CA 2] Center 34 (4~65) winsize 62
1468 22:17:32.161594 [CA 3] Center 34 (3~65) winsize 63
1469 22:17:32.165092 [CA 4] Center 34 (4~65) winsize 62
1470 22:17:32.167876 [CA 5] Center 34 (3~65) winsize 63
1471 22:17:32.168424
1472 22:17:32.171381 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1473 22:17:32.171804
1474 22:17:32.174903 [CATrainingPosCal] consider 1 rank data
1475 22:17:32.177910 u2DelayCellTimex100 = 270/100 ps
1476 22:17:32.181334 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1477 22:17:32.188210 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1478 22:17:32.191331 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1479 22:17:32.194472 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
1480 22:17:32.197959 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1481 22:17:32.201597 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1482 22:17:32.202021
1483 22:17:32.205158 CA PerBit enable=1, Macro0, CA PI delay=34
1484 22:17:32.205584
1485 22:17:32.208032 [CBTSetCACLKResult] CA Dly = 34
1486 22:17:32.208456 CS Dly: 4 (0~35)
1487 22:17:32.211455 ==
1488 22:17:32.211877 Dram Type= 6, Freq= 0, CH_1, rank 1
1489 22:17:32.218008 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1490 22:17:32.218434 ==
1491 22:17:32.221691 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1492 22:17:32.227843 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1493 22:17:32.237738 [CA 0] Center 36 (6~67) winsize 62
1494 22:17:32.240853 [CA 1] Center 36 (6~67) winsize 62
1495 22:17:32.244105 [CA 2] Center 34 (4~65) winsize 62
1496 22:17:32.247984 [CA 3] Center 34 (3~65) winsize 63
1497 22:17:32.250870 [CA 4] Center 34 (4~65) winsize 62
1498 22:17:32.254632 [CA 5] Center 34 (3~65) winsize 63
1499 22:17:32.255215
1500 22:17:32.257890 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1501 22:17:32.258304
1502 22:17:32.261029 [CATrainingPosCal] consider 2 rank data
1503 22:17:32.264025 u2DelayCellTimex100 = 270/100 ps
1504 22:17:32.267374 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1505 22:17:32.274078 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1506 22:17:32.277963 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1507 22:17:32.281023 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
1508 22:17:32.283910 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1509 22:17:32.287549 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1510 22:17:32.287966
1511 22:17:32.290614 CA PerBit enable=1, Macro0, CA PI delay=34
1512 22:17:32.291029
1513 22:17:32.294255 [CBTSetCACLKResult] CA Dly = 34
1514 22:17:32.294671 CS Dly: 5 (0~38)
1515 22:17:32.297349
1516 22:17:32.300531 ----->DramcWriteLeveling(PI) begin...
1517 22:17:32.300626 ==
1518 22:17:32.304029 Dram Type= 6, Freq= 0, CH_1, rank 0
1519 22:17:32.306924 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1520 22:17:32.307005 ==
1521 22:17:32.310856 Write leveling (Byte 0): 29 => 29
1522 22:17:32.313997 Write leveling (Byte 1): 30 => 30
1523 22:17:32.317200 DramcWriteLeveling(PI) end<-----
1524 22:17:32.317280
1525 22:17:32.317343 ==
1526 22:17:32.320434 Dram Type= 6, Freq= 0, CH_1, rank 0
1527 22:17:32.323904 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1528 22:17:32.323988 ==
1529 22:17:32.327111 [Gating] SW mode calibration
1530 22:17:32.333369 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1531 22:17:32.339922 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1532 22:17:32.343413 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1533 22:17:32.346702 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1534 22:17:32.354001 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1535 22:17:32.356908 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1536 22:17:32.359660 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1537 22:17:32.366568 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1538 22:17:32.369696 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1539 22:17:32.373524 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1540 22:17:32.379815 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1541 22:17:32.383493 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1542 22:17:32.386632 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1543 22:17:32.393368 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1544 22:17:32.396384 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1545 22:17:32.399837 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1546 22:17:32.402948 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1547 22:17:32.409949 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1548 22:17:32.413071 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1549 22:17:32.416826 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
1550 22:17:32.423065 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1551 22:17:32.426252 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1552 22:17:32.429827 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1553 22:17:32.436143 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1554 22:17:32.439563 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1555 22:17:32.443056 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1556 22:17:32.449677 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1557 22:17:32.452775 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1558 22:17:32.456177 0 9 8 | B1->B0 | 2c2c 2f2f | 1 1 | (1 1) (1 1)
1559 22:17:32.463114 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1560 22:17:32.466435 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1561 22:17:32.469635 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1562 22:17:32.476135 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1563 22:17:32.479717 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1564 22:17:32.483155 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1565 22:17:32.489643 0 10 4 | B1->B0 | 3434 3131 | 1 0 | (1 0) (1 1)
1566 22:17:32.492330 0 10 8 | B1->B0 | 2929 2424 | 0 0 | (1 1) (0 0)
1567 22:17:32.495902 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1568 22:17:32.502760 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1569 22:17:32.506147 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1570 22:17:32.509054 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1571 22:17:32.515967 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1572 22:17:32.519198 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1573 22:17:32.523206 0 11 4 | B1->B0 | 2424 2d2c | 0 1 | (0 0) (0 0)
1574 22:17:32.528938 0 11 8 | B1->B0 | 3939 4343 | 0 0 | (0 0) (0 0)
1575 22:17:32.532627 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1576 22:17:32.535606 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1577 22:17:32.542767 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1578 22:17:32.545712 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1579 22:17:32.549505 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1580 22:17:32.555550 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1581 22:17:32.559016 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1582 22:17:32.562055 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1583 22:17:32.568623 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1584 22:17:32.572332 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1585 22:17:32.575318 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1586 22:17:32.582511 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1587 22:17:32.585687 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1588 22:17:32.588609 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1589 22:17:32.595079 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1590 22:17:32.598628 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1591 22:17:32.601754 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1592 22:17:32.608899 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1593 22:17:32.611777 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1594 22:17:32.615631 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1595 22:17:32.618866 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1596 22:17:32.624931 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1597 22:17:32.628130 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1598 22:17:32.634674 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1599 22:17:32.635148 Total UI for P1: 0, mck2ui 16
1600 22:17:32.638525 best dqsien dly found for B0: ( 0, 14, 2)
1601 22:17:32.645183 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1602 22:17:32.647845 Total UI for P1: 0, mck2ui 16
1603 22:17:32.651669 best dqsien dly found for B1: ( 0, 14, 6)
1604 22:17:32.654594 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1605 22:17:32.658056 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1606 22:17:32.658480
1607 22:17:32.661414 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1608 22:17:32.664741 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1609 22:17:32.668118 [Gating] SW calibration Done
1610 22:17:32.668740 ==
1611 22:17:32.671169 Dram Type= 6, Freq= 0, CH_1, rank 0
1612 22:17:32.674588 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1613 22:17:32.675037 ==
1614 22:17:32.678232 RX Vref Scan: 0
1615 22:17:32.678672
1616 22:17:32.681917 RX Vref 0 -> 0, step: 1
1617 22:17:32.682334
1618 22:17:32.682669 RX Delay -130 -> 252, step: 16
1619 22:17:32.687794 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1620 22:17:32.691196 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1621 22:17:32.694658 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1622 22:17:32.697337 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1623 22:17:32.700674 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1624 22:17:32.707481 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1625 22:17:32.711283 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1626 22:17:32.714134 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1627 22:17:32.717900 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1628 22:17:32.720660 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1629 22:17:32.727456 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1630 22:17:32.730698 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1631 22:17:32.733871 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1632 22:17:32.737401 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1633 22:17:32.744050 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1634 22:17:32.747541 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1635 22:17:32.747623 ==
1636 22:17:32.750925 Dram Type= 6, Freq= 0, CH_1, rank 0
1637 22:17:32.753864 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1638 22:17:32.753946 ==
1639 22:17:32.757429 DQS Delay:
1640 22:17:32.757510 DQS0 = 0, DQS1 = 0
1641 22:17:32.757574 DQM Delay:
1642 22:17:32.760863 DQM0 = 89, DQM1 = 79
1643 22:17:32.760952 DQ Delay:
1644 22:17:32.764158 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =85
1645 22:17:32.767541 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1646 22:17:32.770806 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =69
1647 22:17:32.773580 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1648 22:17:32.773713
1649 22:17:32.773827
1650 22:17:32.773935 ==
1651 22:17:32.777498 Dram Type= 6, Freq= 0, CH_1, rank 0
1652 22:17:32.784049 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1653 22:17:32.784472 ==
1654 22:17:32.784853
1655 22:17:32.785164
1656 22:17:32.785545 TX Vref Scan disable
1657 22:17:32.787534 == TX Byte 0 ==
1658 22:17:32.791527 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1659 22:17:32.797267 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1660 22:17:32.797691 == TX Byte 1 ==
1661 22:17:32.801044 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1662 22:17:32.807424 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1663 22:17:32.807931 ==
1664 22:17:32.810953 Dram Type= 6, Freq= 0, CH_1, rank 0
1665 22:17:32.813724 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1666 22:17:32.814298 ==
1667 22:17:32.826360 TX Vref=22, minBit 10, minWin=26, winSum=442
1668 22:17:32.830006 TX Vref=24, minBit 9, minWin=27, winSum=447
1669 22:17:32.833136 TX Vref=26, minBit 9, minWin=27, winSum=448
1670 22:17:32.836093 TX Vref=28, minBit 9, minWin=27, winSum=448
1671 22:17:32.839978 TX Vref=30, minBit 8, minWin=27, winSum=448
1672 22:17:32.842797 TX Vref=32, minBit 5, minWin=27, winSum=442
1673 22:17:32.849450 [TxChooseVref] Worse bit 9, Min win 27, Win sum 448, Final Vref 26
1674 22:17:32.849631
1675 22:17:32.852931 Final TX Range 1 Vref 26
1676 22:17:32.853091
1677 22:17:32.853218 ==
1678 22:17:32.856389 Dram Type= 6, Freq= 0, CH_1, rank 0
1679 22:17:32.859643 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1680 22:17:32.859772 ==
1681 22:17:32.859877
1682 22:17:32.862712
1683 22:17:32.862842 TX Vref Scan disable
1684 22:17:32.866319 == TX Byte 0 ==
1685 22:17:32.869789 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1686 22:17:32.872853 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1687 22:17:32.876350 == TX Byte 1 ==
1688 22:17:32.879853 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1689 22:17:32.883004 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1690 22:17:32.886332
1691 22:17:32.886473 [DATLAT]
1692 22:17:32.886589 Freq=800, CH1 RK0
1693 22:17:32.886691
1694 22:17:32.889302 DATLAT Default: 0xa
1695 22:17:32.889469 0, 0xFFFF, sum = 0
1696 22:17:32.892663 1, 0xFFFF, sum = 0
1697 22:17:32.892798 2, 0xFFFF, sum = 0
1698 22:17:32.895828 3, 0xFFFF, sum = 0
1699 22:17:32.895956 4, 0xFFFF, sum = 0
1700 22:17:32.899844 5, 0xFFFF, sum = 0
1701 22:17:32.903208 6, 0xFFFF, sum = 0
1702 22:17:32.903305 7, 0xFFFF, sum = 0
1703 22:17:32.906143 8, 0xFFFF, sum = 0
1704 22:17:32.906225 9, 0x0, sum = 1
1705 22:17:32.906291 10, 0x0, sum = 2
1706 22:17:32.909568 11, 0x0, sum = 3
1707 22:17:32.909650 12, 0x0, sum = 4
1708 22:17:32.913307 best_step = 10
1709 22:17:32.913388
1710 22:17:32.913451 ==
1711 22:17:32.916428 Dram Type= 6, Freq= 0, CH_1, rank 0
1712 22:17:32.919795 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1713 22:17:32.919877 ==
1714 22:17:32.922639 RX Vref Scan: 1
1715 22:17:32.922792
1716 22:17:32.926290 Set Vref Range= 32 -> 127
1717 22:17:32.926428
1718 22:17:32.926507 RX Vref 32 -> 127, step: 1
1719 22:17:32.926578
1720 22:17:32.929759 RX Delay -95 -> 252, step: 8
1721 22:17:32.929859
1722 22:17:32.932944 Set Vref, RX VrefLevel [Byte0]: 32
1723 22:17:32.936053 [Byte1]: 32
1724 22:17:32.936185
1725 22:17:32.939271 Set Vref, RX VrefLevel [Byte0]: 33
1726 22:17:32.942289 [Byte1]: 33
1727 22:17:32.946403
1728 22:17:32.946489 Set Vref, RX VrefLevel [Byte0]: 34
1729 22:17:32.949731 [Byte1]: 34
1730 22:17:32.954269
1731 22:17:32.954434 Set Vref, RX VrefLevel [Byte0]: 35
1732 22:17:32.957803 [Byte1]: 35
1733 22:17:32.961943
1734 22:17:32.962036 Set Vref, RX VrefLevel [Byte0]: 36
1735 22:17:32.964873 [Byte1]: 36
1736 22:17:32.970063
1737 22:17:32.970250 Set Vref, RX VrefLevel [Byte0]: 37
1738 22:17:32.973215 [Byte1]: 37
1739 22:17:32.977408
1740 22:17:32.977610 Set Vref, RX VrefLevel [Byte0]: 38
1741 22:17:32.980659 [Byte1]: 38
1742 22:17:32.984790
1743 22:17:32.984997 Set Vref, RX VrefLevel [Byte0]: 39
1744 22:17:32.987826 [Byte1]: 39
1745 22:17:32.992092
1746 22:17:32.992261 Set Vref, RX VrefLevel [Byte0]: 40
1747 22:17:32.995640 [Byte1]: 40
1748 22:17:32.999706
1749 22:17:32.999944 Set Vref, RX VrefLevel [Byte0]: 41
1750 22:17:33.003691 [Byte1]: 41
1751 22:17:33.007885
1752 22:17:33.008295 Set Vref, RX VrefLevel [Byte0]: 42
1753 22:17:33.010898 [Byte1]: 42
1754 22:17:33.015545
1755 22:17:33.015964 Set Vref, RX VrefLevel [Byte0]: 43
1756 22:17:33.019083 [Byte1]: 43
1757 22:17:33.022665
1758 22:17:33.023086 Set Vref, RX VrefLevel [Byte0]: 44
1759 22:17:33.026145 [Byte1]: 44
1760 22:17:33.030730
1761 22:17:33.031153 Set Vref, RX VrefLevel [Byte0]: 45
1762 22:17:33.033916 [Byte1]: 45
1763 22:17:33.037847
1764 22:17:33.038267 Set Vref, RX VrefLevel [Byte0]: 46
1765 22:17:33.041292 [Byte1]: 46
1766 22:17:33.045455
1767 22:17:33.045873 Set Vref, RX VrefLevel [Byte0]: 47
1768 22:17:33.049624 [Byte1]: 47
1769 22:17:33.053851
1770 22:17:33.054268 Set Vref, RX VrefLevel [Byte0]: 48
1771 22:17:33.056881 [Byte1]: 48
1772 22:17:33.061451
1773 22:17:33.061870 Set Vref, RX VrefLevel [Byte0]: 49
1774 22:17:33.063928 [Byte1]: 49
1775 22:17:33.068088
1776 22:17:33.068381 Set Vref, RX VrefLevel [Byte0]: 50
1777 22:17:33.071819 [Byte1]: 50
1778 22:17:33.075833
1779 22:17:33.076014 Set Vref, RX VrefLevel [Byte0]: 51
1780 22:17:33.078871 [Byte1]: 51
1781 22:17:33.083339
1782 22:17:33.083468 Set Vref, RX VrefLevel [Byte0]: 52
1783 22:17:33.086477 [Byte1]: 52
1784 22:17:33.091013
1785 22:17:33.091129 Set Vref, RX VrefLevel [Byte0]: 53
1786 22:17:33.094170 [Byte1]: 53
1787 22:17:33.098352
1788 22:17:33.098459 Set Vref, RX VrefLevel [Byte0]: 54
1789 22:17:33.101599 [Byte1]: 54
1790 22:17:33.105896
1791 22:17:33.105982 Set Vref, RX VrefLevel [Byte0]: 55
1792 22:17:33.109308 [Byte1]: 55
1793 22:17:33.113707
1794 22:17:33.113790 Set Vref, RX VrefLevel [Byte0]: 56
1795 22:17:33.117376 [Byte1]: 56
1796 22:17:33.122188
1797 22:17:33.122275 Set Vref, RX VrefLevel [Byte0]: 57
1798 22:17:33.124788 [Byte1]: 57
1799 22:17:33.128714
1800 22:17:33.128795 Set Vref, RX VrefLevel [Byte0]: 58
1801 22:17:33.132030 [Byte1]: 58
1802 22:17:33.136627
1803 22:17:33.136714 Set Vref, RX VrefLevel [Byte0]: 59
1804 22:17:33.140165 [Byte1]: 59
1805 22:17:33.144110
1806 22:17:33.144191 Set Vref, RX VrefLevel [Byte0]: 60
1807 22:17:33.147130 [Byte1]: 60
1808 22:17:33.151473
1809 22:17:33.151553 Set Vref, RX VrefLevel [Byte0]: 61
1810 22:17:33.154885 [Byte1]: 61
1811 22:17:33.159307
1812 22:17:33.159387 Set Vref, RX VrefLevel [Byte0]: 62
1813 22:17:33.163053 [Byte1]: 62
1814 22:17:33.167147
1815 22:17:33.167230 Set Vref, RX VrefLevel [Byte0]: 63
1816 22:17:33.170523 [Byte1]: 63
1817 22:17:33.174771
1818 22:17:33.174854 Set Vref, RX VrefLevel [Byte0]: 64
1819 22:17:33.178062 [Byte1]: 64
1820 22:17:33.182003
1821 22:17:33.182105 Set Vref, RX VrefLevel [Byte0]: 65
1822 22:17:33.185129 [Byte1]: 65
1823 22:17:33.189418
1824 22:17:33.189500 Set Vref, RX VrefLevel [Byte0]: 66
1825 22:17:33.193297 [Byte1]: 66
1826 22:17:33.197585
1827 22:17:33.197667 Set Vref, RX VrefLevel [Byte0]: 67
1828 22:17:33.201234 [Byte1]: 67
1829 22:17:33.204930
1830 22:17:33.205010 Set Vref, RX VrefLevel [Byte0]: 68
1831 22:17:33.208333 [Byte1]: 68
1832 22:17:33.212235
1833 22:17:33.212315 Set Vref, RX VrefLevel [Byte0]: 69
1834 22:17:33.215489 [Byte1]: 69
1835 22:17:33.220358
1836 22:17:33.220443 Set Vref, RX VrefLevel [Byte0]: 70
1837 22:17:33.223111 [Byte1]: 70
1838 22:17:33.228365
1839 22:17:33.228449 Set Vref, RX VrefLevel [Byte0]: 71
1840 22:17:33.231045 [Byte1]: 71
1841 22:17:33.234998
1842 22:17:33.235081 Set Vref, RX VrefLevel [Byte0]: 72
1843 22:17:33.238985 [Byte1]: 72
1844 22:17:33.243054
1845 22:17:33.243139 Set Vref, RX VrefLevel [Byte0]: 73
1846 22:17:33.246258 [Byte1]: 73
1847 22:17:33.250773
1848 22:17:33.250854 Set Vref, RX VrefLevel [Byte0]: 74
1849 22:17:33.253676 [Byte1]: 74
1850 22:17:33.257908
1851 22:17:33.257990 Final RX Vref Byte 0 = 55 to rank0
1852 22:17:33.261297 Final RX Vref Byte 1 = 64 to rank0
1853 22:17:33.265176 Final RX Vref Byte 0 = 55 to rank1
1854 22:17:33.267925 Final RX Vref Byte 1 = 64 to rank1==
1855 22:17:33.271245 Dram Type= 6, Freq= 0, CH_1, rank 0
1856 22:17:33.277740 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1857 22:17:33.277828 ==
1858 22:17:33.277894 DQS Delay:
1859 22:17:33.277954 DQS0 = 0, DQS1 = 0
1860 22:17:33.281650 DQM Delay:
1861 22:17:33.281733 DQM0 = 86, DQM1 = 79
1862 22:17:33.284876 DQ Delay:
1863 22:17:33.287781 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
1864 22:17:33.291249 DQ4 =84, DQ5 =96, DQ6 =100, DQ7 =80
1865 22:17:33.294794 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
1866 22:17:33.297700 DQ12 =88, DQ13 =84, DQ14 =88, DQ15 =88
1867 22:17:33.297782
1868 22:17:33.297846
1869 22:17:33.304483 [DQSOSCAuto] RK0, (LSB)MR18= 0x311e, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 397 ps
1870 22:17:33.308169 CH1 RK0: MR19=606, MR18=311E
1871 22:17:33.314937 CH1_RK0: MR19=0x606, MR18=0x311E, DQSOSC=397, MR23=63, INC=93, DEC=62
1872 22:17:33.315030
1873 22:17:33.318189 ----->DramcWriteLeveling(PI) begin...
1874 22:17:33.318273 ==
1875 22:17:33.320984 Dram Type= 6, Freq= 0, CH_1, rank 1
1876 22:17:33.324840 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1877 22:17:33.324923 ==
1878 22:17:33.327963 Write leveling (Byte 0): 29 => 29
1879 22:17:33.330968 Write leveling (Byte 1): 29 => 29
1880 22:17:33.334234 DramcWriteLeveling(PI) end<-----
1881 22:17:33.334318
1882 22:17:33.334402 ==
1883 22:17:33.337485 Dram Type= 6, Freq= 0, CH_1, rank 1
1884 22:17:33.340830 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1885 22:17:33.340914 ==
1886 22:17:33.344667 [Gating] SW mode calibration
1887 22:17:33.350945 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1888 22:17:33.357716 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1889 22:17:33.360832 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1890 22:17:33.367099 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1891 22:17:33.370902 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1892 22:17:33.374104 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1893 22:17:33.380771 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1894 22:17:33.384402 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1895 22:17:33.387155 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1896 22:17:33.390432 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1897 22:17:33.397114 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1898 22:17:33.400386 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1899 22:17:33.403781 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1900 22:17:33.410346 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1901 22:17:33.413505 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1902 22:17:33.417004 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1903 22:17:33.423791 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1904 22:17:33.426946 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1905 22:17:33.430137 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1906 22:17:33.436803 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1907 22:17:33.440271 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1908 22:17:33.443841 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1909 22:17:33.449908 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1910 22:17:33.453500 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1911 22:17:33.456994 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1912 22:17:33.463644 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1913 22:17:33.466927 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1914 22:17:33.470232 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1915 22:17:33.477120 0 9 8 | B1->B0 | 3030 2424 | 0 0 | (0 0) (0 0)
1916 22:17:33.480025 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1917 22:17:33.483921 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1918 22:17:33.490349 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1919 22:17:33.493390 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1920 22:17:33.496349 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1921 22:17:33.503358 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1922 22:17:33.506400 0 10 4 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 0)
1923 22:17:33.509958 0 10 8 | B1->B0 | 2525 3030 | 0 0 | (0 0) (1 0)
1924 22:17:33.516501 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1925 22:17:33.520176 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1926 22:17:33.523038 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1927 22:17:33.529684 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1928 22:17:33.533346 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1929 22:17:33.536270 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1930 22:17:33.543322 0 11 4 | B1->B0 | 2525 2323 | 1 0 | (0 0) (0 0)
1931 22:17:33.546552 0 11 8 | B1->B0 | 4242 3737 | 0 0 | (0 0) (0 0)
1932 22:17:33.549919 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1933 22:17:33.553449 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1934 22:17:33.559748 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1935 22:17:33.563459 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1936 22:17:33.566210 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1937 22:17:33.573100 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1938 22:17:33.576748 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1939 22:17:33.579773 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1940 22:17:33.586854 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1941 22:17:33.589490 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1942 22:17:33.592957 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1943 22:17:33.599352 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1944 22:17:33.602819 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1945 22:17:33.606188 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1946 22:17:33.612522 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1947 22:17:33.616337 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1948 22:17:33.619759 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1949 22:17:33.626088 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1950 22:17:33.629237 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1951 22:17:33.632781 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1952 22:17:33.639446 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1953 22:17:33.642765 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1954 22:17:33.646077 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1955 22:17:33.652570 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1956 22:17:33.652652 Total UI for P1: 0, mck2ui 16
1957 22:17:33.659126 best dqsien dly found for B0: ( 0, 14, 2)
1958 22:17:33.662524 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1959 22:17:33.665822 Total UI for P1: 0, mck2ui 16
1960 22:17:33.669018 best dqsien dly found for B1: ( 0, 14, 6)
1961 22:17:33.672381 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1962 22:17:33.675790 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1963 22:17:33.675870
1964 22:17:33.678804 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1965 22:17:33.682498 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1966 22:17:33.685948 [Gating] SW calibration Done
1967 22:17:33.686028 ==
1968 22:17:33.689171 Dram Type= 6, Freq= 0, CH_1, rank 1
1969 22:17:33.692160 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1970 22:17:33.696396 ==
1971 22:17:33.696476 RX Vref Scan: 0
1972 22:17:33.696545
1973 22:17:33.699082 RX Vref 0 -> 0, step: 1
1974 22:17:33.699162
1975 22:17:33.702271 RX Delay -130 -> 252, step: 16
1976 22:17:33.705883 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1977 22:17:33.708684 iDelay=222, Bit 1, Center 77 (-34 ~ 189) 224
1978 22:17:33.711933 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1979 22:17:33.715644 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1980 22:17:33.722364 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1981 22:17:33.725608 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1982 22:17:33.728691 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1983 22:17:33.731940 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1984 22:17:33.735171 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1985 22:17:33.742251 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1986 22:17:33.746703 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1987 22:17:33.748984 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1988 22:17:33.751861 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1989 22:17:33.755007 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1990 22:17:33.762262 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1991 22:17:33.765385 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1992 22:17:33.765466 ==
1993 22:17:33.768721 Dram Type= 6, Freq= 0, CH_1, rank 1
1994 22:17:33.771838 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1995 22:17:33.771924 ==
1996 22:17:33.775620 DQS Delay:
1997 22:17:33.775700 DQS0 = 0, DQS1 = 0
1998 22:17:33.775764 DQM Delay:
1999 22:17:33.778957 DQM0 = 87, DQM1 = 78
2000 22:17:33.779038 DQ Delay:
2001 22:17:33.781742 DQ0 =85, DQ1 =77, DQ2 =77, DQ3 =85
2002 22:17:33.785150 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
2003 22:17:33.788441 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
2004 22:17:33.792178 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
2005 22:17:33.792259
2006 22:17:33.792322
2007 22:17:33.792379 ==
2008 22:17:33.795288 Dram Type= 6, Freq= 0, CH_1, rank 1
2009 22:17:33.801611 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2010 22:17:33.801717 ==
2011 22:17:33.801810
2012 22:17:33.801872
2013 22:17:33.804895 TX Vref Scan disable
2014 22:17:33.804976 == TX Byte 0 ==
2015 22:17:33.808079 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
2016 22:17:33.814764 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
2017 22:17:33.814845 == TX Byte 1 ==
2018 22:17:33.818070 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2019 22:17:33.824615 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2020 22:17:33.824696 ==
2021 22:17:33.828394 Dram Type= 6, Freq= 0, CH_1, rank 1
2022 22:17:33.831380 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2023 22:17:33.831461 ==
2024 22:17:33.845110 TX Vref=22, minBit 8, minWin=26, winSum=446
2025 22:17:33.847955 TX Vref=24, minBit 9, minWin=27, winSum=449
2026 22:17:33.851537 TX Vref=26, minBit 15, minWin=27, winSum=452
2027 22:17:33.854831 TX Vref=28, minBit 13, minWin=27, winSum=451
2028 22:17:33.857663 TX Vref=30, minBit 13, minWin=27, winSum=449
2029 22:17:33.864849 TX Vref=32, minBit 8, minWin=27, winSum=446
2030 22:17:33.867830 [TxChooseVref] Worse bit 15, Min win 27, Win sum 452, Final Vref 26
2031 22:17:33.867911
2032 22:17:33.871864 Final TX Range 1 Vref 26
2033 22:17:33.871945
2034 22:17:33.872009 ==
2035 22:17:33.874522 Dram Type= 6, Freq= 0, CH_1, rank 1
2036 22:17:33.881158 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2037 22:17:33.881240 ==
2038 22:17:33.881304
2039 22:17:33.881361
2040 22:17:33.881417 TX Vref Scan disable
2041 22:17:33.885041 == TX Byte 0 ==
2042 22:17:33.888449 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
2043 22:17:33.894757 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
2044 22:17:33.894838 == TX Byte 1 ==
2045 22:17:33.897911 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2046 22:17:33.904828 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2047 22:17:33.904909
2048 22:17:33.904973 [DATLAT]
2049 22:17:33.905031 Freq=800, CH1 RK1
2050 22:17:33.905087
2051 22:17:33.908231 DATLAT Default: 0xa
2052 22:17:33.908311 0, 0xFFFF, sum = 0
2053 22:17:33.911392 1, 0xFFFF, sum = 0
2054 22:17:33.914486 2, 0xFFFF, sum = 0
2055 22:17:33.914568 3, 0xFFFF, sum = 0
2056 22:17:33.918029 4, 0xFFFF, sum = 0
2057 22:17:33.918110 5, 0xFFFF, sum = 0
2058 22:17:33.921400 6, 0xFFFF, sum = 0
2059 22:17:33.921482 7, 0xFFFF, sum = 0
2060 22:17:33.924981 8, 0xFFFF, sum = 0
2061 22:17:33.925063 9, 0x0, sum = 1
2062 22:17:33.928212 10, 0x0, sum = 2
2063 22:17:33.928294 11, 0x0, sum = 3
2064 22:17:33.928358 12, 0x0, sum = 4
2065 22:17:33.931211 best_step = 10
2066 22:17:33.931291
2067 22:17:33.931354 ==
2068 22:17:33.934660 Dram Type= 6, Freq= 0, CH_1, rank 1
2069 22:17:33.937636 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2070 22:17:33.937717 ==
2071 22:17:33.941090 RX Vref Scan: 0
2072 22:17:33.941171
2073 22:17:33.944360 RX Vref 0 -> 0, step: 1
2074 22:17:33.944440
2075 22:17:33.944502 RX Delay -95 -> 252, step: 8
2076 22:17:33.951373 iDelay=217, Bit 0, Center 92 (-23 ~ 208) 232
2077 22:17:33.954814 iDelay=217, Bit 1, Center 80 (-31 ~ 192) 224
2078 22:17:33.958164 iDelay=217, Bit 2, Center 80 (-31 ~ 192) 224
2079 22:17:33.961478 iDelay=217, Bit 3, Center 84 (-23 ~ 192) 216
2080 22:17:33.965036 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
2081 22:17:33.971754 iDelay=217, Bit 5, Center 96 (-15 ~ 208) 224
2082 22:17:33.975676 iDelay=217, Bit 6, Center 100 (-15 ~ 216) 232
2083 22:17:33.978652 iDelay=217, Bit 7, Center 84 (-31 ~ 200) 232
2084 22:17:33.981917 iDelay=217, Bit 8, Center 68 (-47 ~ 184) 232
2085 22:17:33.985190 iDelay=217, Bit 9, Center 68 (-47 ~ 184) 232
2086 22:17:33.991353 iDelay=217, Bit 10, Center 80 (-39 ~ 200) 240
2087 22:17:33.994918 iDelay=217, Bit 11, Center 68 (-47 ~ 184) 232
2088 22:17:33.998379 iDelay=217, Bit 12, Center 84 (-31 ~ 200) 232
2089 22:17:34.001317 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
2090 22:17:34.008029 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
2091 22:17:34.011667 iDelay=217, Bit 15, Center 88 (-31 ~ 208) 240
2092 22:17:34.011748 ==
2093 22:17:34.014561 Dram Type= 6, Freq= 0, CH_1, rank 1
2094 22:17:34.018100 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2095 22:17:34.018182 ==
2096 22:17:34.018245 DQS Delay:
2097 22:17:34.021764 DQS0 = 0, DQS1 = 0
2098 22:17:34.021844 DQM Delay:
2099 22:17:34.024487 DQM0 = 87, DQM1 = 78
2100 22:17:34.024577 DQ Delay:
2101 22:17:34.028238 DQ0 =92, DQ1 =80, DQ2 =80, DQ3 =84
2102 22:17:34.031086 DQ4 =84, DQ5 =96, DQ6 =100, DQ7 =84
2103 22:17:34.034877 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
2104 22:17:34.037626 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =88
2105 22:17:34.037708
2106 22:17:34.037772
2107 22:17:34.047571 [DQSOSCAuto] RK1, (LSB)MR18= 0x1b13, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 403 ps
2108 22:17:34.047655 CH1 RK1: MR19=606, MR18=1B13
2109 22:17:34.054199 CH1_RK1: MR19=0x606, MR18=0x1B13, DQSOSC=403, MR23=63, INC=90, DEC=60
2110 22:17:34.057592 [RxdqsGatingPostProcess] freq 800
2111 22:17:34.064339 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2112 22:17:34.067710 Pre-setting of DQS Precalculation
2113 22:17:34.070703 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2114 22:17:34.078045 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2115 22:17:34.087851 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2116 22:17:34.087933
2117 22:17:34.087997
2118 22:17:34.090639 [Calibration Summary] 1600 Mbps
2119 22:17:34.090720 CH 0, Rank 0
2120 22:17:34.094737 SW Impedance : PASS
2121 22:17:34.094818 DUTY Scan : NO K
2122 22:17:34.097362 ZQ Calibration : PASS
2123 22:17:34.100467 Jitter Meter : NO K
2124 22:17:34.100554 CBT Training : PASS
2125 22:17:34.104088 Write leveling : PASS
2126 22:17:34.107436 RX DQS gating : PASS
2127 22:17:34.107517 RX DQ/DQS(RDDQC) : PASS
2128 22:17:34.110668 TX DQ/DQS : PASS
2129 22:17:34.110750 RX DATLAT : PASS
2130 22:17:34.114033 RX DQ/DQS(Engine): PASS
2131 22:17:34.117331 TX OE : NO K
2132 22:17:34.117413 All Pass.
2133 22:17:34.117478
2134 22:17:34.117537 CH 0, Rank 1
2135 22:17:34.120555 SW Impedance : PASS
2136 22:17:34.124031 DUTY Scan : NO K
2137 22:17:34.124113 ZQ Calibration : PASS
2138 22:17:34.127131 Jitter Meter : NO K
2139 22:17:34.130846 CBT Training : PASS
2140 22:17:34.130928 Write leveling : PASS
2141 22:17:34.133816 RX DQS gating : PASS
2142 22:17:34.137138 RX DQ/DQS(RDDQC) : PASS
2143 22:17:34.137246 TX DQ/DQS : PASS
2144 22:17:34.140829 RX DATLAT : PASS
2145 22:17:34.144256 RX DQ/DQS(Engine): PASS
2146 22:17:34.144343 TX OE : NO K
2147 22:17:34.147006 All Pass.
2148 22:17:34.147080
2149 22:17:34.147159 CH 1, Rank 0
2150 22:17:34.150235 SW Impedance : PASS
2151 22:17:34.150309 DUTY Scan : NO K
2152 22:17:34.153708 ZQ Calibration : PASS
2153 22:17:34.156936 Jitter Meter : NO K
2154 22:17:34.157010 CBT Training : PASS
2155 22:17:34.160996 Write leveling : PASS
2156 22:17:34.161079 RX DQS gating : PASS
2157 22:17:34.163856 RX DQ/DQS(RDDQC) : PASS
2158 22:17:34.167050 TX DQ/DQS : PASS
2159 22:17:34.167134 RX DATLAT : PASS
2160 22:17:34.170930 RX DQ/DQS(Engine): PASS
2161 22:17:34.173939 TX OE : NO K
2162 22:17:34.174022 All Pass.
2163 22:17:34.174105
2164 22:17:34.174183 CH 1, Rank 1
2165 22:17:34.177148 SW Impedance : PASS
2166 22:17:34.180148 DUTY Scan : NO K
2167 22:17:34.180231 ZQ Calibration : PASS
2168 22:17:34.183901 Jitter Meter : NO K
2169 22:17:34.187258 CBT Training : PASS
2170 22:17:34.187342 Write leveling : PASS
2171 22:17:34.190210 RX DQS gating : PASS
2172 22:17:34.194150 RX DQ/DQS(RDDQC) : PASS
2173 22:17:34.194233 TX DQ/DQS : PASS
2174 22:17:34.197133 RX DATLAT : PASS
2175 22:17:34.200059 RX DQ/DQS(Engine): PASS
2176 22:17:34.200142 TX OE : NO K
2177 22:17:34.203533 All Pass.
2178 22:17:34.203617
2179 22:17:34.203700 DramC Write-DBI off
2180 22:17:34.206976 PER_BANK_REFRESH: Hybrid Mode
2181 22:17:34.207060 TX_TRACKING: ON
2182 22:17:34.209955 [GetDramInforAfterCalByMRR] Vendor 6.
2183 22:17:34.217229 [GetDramInforAfterCalByMRR] Revision 606.
2184 22:17:34.220072 [GetDramInforAfterCalByMRR] Revision 2 0.
2185 22:17:34.220155 MR0 0x3b3b
2186 22:17:34.220238 MR8 0x5151
2187 22:17:34.223279 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2188 22:17:34.223362
2189 22:17:34.227267 MR0 0x3b3b
2190 22:17:34.227350 MR8 0x5151
2191 22:17:34.230458 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2192 22:17:34.230541
2193 22:17:34.240109 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2194 22:17:34.243210 [FAST_K] Save calibration result to emmc
2195 22:17:34.246337 [FAST_K] Save calibration result to emmc
2196 22:17:34.249722 dram_init: config_dvfs: 1
2197 22:17:34.253070 dramc_set_vcore_voltage set vcore to 662500
2198 22:17:34.256305 Read voltage for 1200, 2
2199 22:17:34.256402 Vio18 = 0
2200 22:17:34.256503 Vcore = 662500
2201 22:17:34.259561 Vdram = 0
2202 22:17:34.259645 Vddq = 0
2203 22:17:34.259728 Vmddr = 0
2204 22:17:34.266537 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2205 22:17:34.269610 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2206 22:17:34.273560 MEM_TYPE=3, freq_sel=15
2207 22:17:34.276434 sv_algorithm_assistance_LP4_1600
2208 22:17:34.279562 ============ PULL DRAM RESETB DOWN ============
2209 22:17:34.282817 ========== PULL DRAM RESETB DOWN end =========
2210 22:17:34.289773 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2211 22:17:34.293325 ===================================
2212 22:17:34.296106 LPDDR4 DRAM CONFIGURATION
2213 22:17:34.299622 ===================================
2214 22:17:34.299706 EX_ROW_EN[0] = 0x0
2215 22:17:34.303093 EX_ROW_EN[1] = 0x0
2216 22:17:34.303167 LP4Y_EN = 0x0
2217 22:17:34.306724 WORK_FSP = 0x0
2218 22:17:34.306799 WL = 0x4
2219 22:17:34.309326 RL = 0x4
2220 22:17:34.309397 BL = 0x2
2221 22:17:34.312926 RPST = 0x0
2222 22:17:34.313008 RD_PRE = 0x0
2223 22:17:34.316389 WR_PRE = 0x1
2224 22:17:34.316472 WR_PST = 0x0
2225 22:17:34.319454 DBI_WR = 0x0
2226 22:17:34.319537 DBI_RD = 0x0
2227 22:17:34.322807 OTF = 0x1
2228 22:17:34.325801 ===================================
2229 22:17:34.329032 ===================================
2230 22:17:34.329115 ANA top config
2231 22:17:34.332354 ===================================
2232 22:17:34.336228 DLL_ASYNC_EN = 0
2233 22:17:34.339126 ALL_SLAVE_EN = 0
2234 22:17:34.342740 NEW_RANK_MODE = 1
2235 22:17:34.342825 DLL_IDLE_MODE = 1
2236 22:17:34.345530 LP45_APHY_COMB_EN = 1
2237 22:17:34.348811 TX_ODT_DIS = 1
2238 22:17:34.352211 NEW_8X_MODE = 1
2239 22:17:34.355737 ===================================
2240 22:17:34.358805 ===================================
2241 22:17:34.362424 data_rate = 2400
2242 22:17:34.365598 CKR = 1
2243 22:17:34.365679 DQ_P2S_RATIO = 8
2244 22:17:34.368825 ===================================
2245 22:17:34.372399 CA_P2S_RATIO = 8
2246 22:17:34.375620 DQ_CA_OPEN = 0
2247 22:17:34.378817 DQ_SEMI_OPEN = 0
2248 22:17:34.381987 CA_SEMI_OPEN = 0
2249 22:17:34.385730 CA_FULL_RATE = 0
2250 22:17:34.385812 DQ_CKDIV4_EN = 0
2251 22:17:34.389348 CA_CKDIV4_EN = 0
2252 22:17:34.392426 CA_PREDIV_EN = 0
2253 22:17:34.396196 PH8_DLY = 17
2254 22:17:34.398620 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2255 22:17:34.402268 DQ_AAMCK_DIV = 4
2256 22:17:34.402364 CA_AAMCK_DIV = 4
2257 22:17:34.405334 CA_ADMCK_DIV = 4
2258 22:17:34.408509 DQ_TRACK_CA_EN = 0
2259 22:17:34.411896 CA_PICK = 1200
2260 22:17:34.415577 CA_MCKIO = 1200
2261 22:17:34.418600 MCKIO_SEMI = 0
2262 22:17:34.421869 PLL_FREQ = 2366
2263 22:17:34.421943 DQ_UI_PI_RATIO = 32
2264 22:17:34.425619 CA_UI_PI_RATIO = 0
2265 22:17:34.428419 ===================================
2266 22:17:34.431664 ===================================
2267 22:17:34.435296 memory_type:LPDDR4
2268 22:17:34.438312 GP_NUM : 10
2269 22:17:34.438396 SRAM_EN : 1
2270 22:17:34.441577 MD32_EN : 0
2271 22:17:34.445230 ===================================
2272 22:17:34.448356 [ANA_INIT] >>>>>>>>>>>>>>
2273 22:17:34.448437 <<<<<< [CONFIGURE PHASE]: ANA_TX
2274 22:17:34.454980 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2275 22:17:34.458772 ===================================
2276 22:17:34.458853 data_rate = 2400,PCW = 0X5b00
2277 22:17:34.461570 ===================================
2278 22:17:34.464900 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2279 22:17:34.471534 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2280 22:17:34.478161 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2281 22:17:34.481670 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2282 22:17:34.484830 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2283 22:17:34.488201 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2284 22:17:34.491364 [ANA_INIT] flow start
2285 22:17:34.491447 [ANA_INIT] PLL >>>>>>>>
2286 22:17:34.495188 [ANA_INIT] PLL <<<<<<<<
2287 22:17:34.498080 [ANA_INIT] MIDPI >>>>>>>>
2288 22:17:34.501588 [ANA_INIT] MIDPI <<<<<<<<
2289 22:17:34.501670 [ANA_INIT] DLL >>>>>>>>
2290 22:17:34.504698 [ANA_INIT] DLL <<<<<<<<
2291 22:17:34.504780 [ANA_INIT] flow end
2292 22:17:34.511793 ============ LP4 DIFF to SE enter ============
2293 22:17:34.514730 ============ LP4 DIFF to SE exit ============
2294 22:17:34.518480 [ANA_INIT] <<<<<<<<<<<<<
2295 22:17:34.521377 [Flow] Enable top DCM control >>>>>
2296 22:17:34.524788 [Flow] Enable top DCM control <<<<<
2297 22:17:34.528169 Enable DLL master slave shuffle
2298 22:17:34.531677 ==============================================================
2299 22:17:34.534919 Gating Mode config
2300 22:17:34.537934 ==============================================================
2301 22:17:34.541202 Config description:
2302 22:17:34.551407 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2303 22:17:34.558210 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2304 22:17:34.561368 SELPH_MODE 0: By rank 1: By Phase
2305 22:17:34.567745 ==============================================================
2306 22:17:34.571365 GAT_TRACK_EN = 1
2307 22:17:34.574357 RX_GATING_MODE = 2
2308 22:17:34.577620 RX_GATING_TRACK_MODE = 2
2309 22:17:34.580889 SELPH_MODE = 1
2310 22:17:34.584411 PICG_EARLY_EN = 1
2311 22:17:34.584494 VALID_LAT_VALUE = 1
2312 22:17:34.590914 ==============================================================
2313 22:17:34.594108 Enter into Gating configuration >>>>
2314 22:17:34.597964 Exit from Gating configuration <<<<
2315 22:17:34.600790 Enter into DVFS_PRE_config >>>>>
2316 22:17:34.611065 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2317 22:17:34.614660 Exit from DVFS_PRE_config <<<<<
2318 22:17:34.617739 Enter into PICG configuration >>>>
2319 22:17:34.621360 Exit from PICG configuration <<<<
2320 22:17:34.624211 [RX_INPUT] configuration >>>>>
2321 22:17:34.627408 [RX_INPUT] configuration <<<<<
2322 22:17:34.630869 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2323 22:17:34.637641 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2324 22:17:34.643871 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2325 22:17:34.650486 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2326 22:17:34.657320 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2327 22:17:34.663833 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2328 22:17:34.667348 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2329 22:17:34.670615 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2330 22:17:34.674536 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2331 22:17:34.680333 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2332 22:17:34.683570 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2333 22:17:34.687000 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2334 22:17:34.690748 ===================================
2335 22:17:34.693776 LPDDR4 DRAM CONFIGURATION
2336 22:17:34.697196 ===================================
2337 22:17:34.697280 EX_ROW_EN[0] = 0x0
2338 22:17:34.700372 EX_ROW_EN[1] = 0x0
2339 22:17:34.700455 LP4Y_EN = 0x0
2340 22:17:34.704282 WORK_FSP = 0x0
2341 22:17:34.704366 WL = 0x4
2342 22:17:34.707109 RL = 0x4
2343 22:17:34.710671 BL = 0x2
2344 22:17:34.710754 RPST = 0x0
2345 22:17:34.714698 RD_PRE = 0x0
2346 22:17:34.714781 WR_PRE = 0x1
2347 22:17:34.717082 WR_PST = 0x0
2348 22:17:34.717166 DBI_WR = 0x0
2349 22:17:34.720308 DBI_RD = 0x0
2350 22:17:34.720391 OTF = 0x1
2351 22:17:34.723647 ===================================
2352 22:17:34.726985 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2353 22:17:34.733540 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2354 22:17:34.737081 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2355 22:17:34.740586 ===================================
2356 22:17:34.743733 LPDDR4 DRAM CONFIGURATION
2357 22:17:34.746893 ===================================
2358 22:17:34.746977 EX_ROW_EN[0] = 0x10
2359 22:17:34.750182 EX_ROW_EN[1] = 0x0
2360 22:17:34.750290 LP4Y_EN = 0x0
2361 22:17:34.753598 WORK_FSP = 0x0
2362 22:17:34.753677 WL = 0x4
2363 22:17:34.756875 RL = 0x4
2364 22:17:34.756954 BL = 0x2
2365 22:17:34.760157 RPST = 0x0
2366 22:17:34.763613 RD_PRE = 0x0
2367 22:17:34.763692 WR_PRE = 0x1
2368 22:17:34.766867 WR_PST = 0x0
2369 22:17:34.766933 DBI_WR = 0x0
2370 22:17:34.769911 DBI_RD = 0x0
2371 22:17:34.769993 OTF = 0x1
2372 22:17:34.774618 ===================================
2373 22:17:34.779887 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2374 22:17:34.779967 ==
2375 22:17:34.783641 Dram Type= 6, Freq= 0, CH_0, rank 0
2376 22:17:34.786888 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2377 22:17:34.786967 ==
2378 22:17:34.789692 [Duty_Offset_Calibration]
2379 22:17:34.793533 B0:1 B1:-1 CA:0
2380 22:17:34.793612
2381 22:17:34.796452 [DutyScan_Calibration_Flow] k_type=0
2382 22:17:34.804558
2383 22:17:34.804637 ==CLK 0==
2384 22:17:34.807907 Final CLK duty delay cell = 0
2385 22:17:34.811315 [0] MAX Duty = 5125%(X100), DQS PI = 24
2386 22:17:34.814322 [0] MIN Duty = 4907%(X100), DQS PI = 8
2387 22:17:34.814401 [0] AVG Duty = 5016%(X100)
2388 22:17:34.818272
2389 22:17:34.818351 CH0 CLK Duty spec in!! Max-Min= 218%
2390 22:17:34.824764 [DutyScan_Calibration_Flow] ====Done====
2391 22:17:34.824843
2392 22:17:34.827903 [DutyScan_Calibration_Flow] k_type=1
2393 22:17:34.842212
2394 22:17:34.842292 ==DQS 0 ==
2395 22:17:34.845278 Final DQS duty delay cell = -4
2396 22:17:34.848803 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2397 22:17:34.852166 [-4] MIN Duty = 4875%(X100), DQS PI = 56
2398 22:17:34.855410 [-4] AVG Duty = 4968%(X100)
2399 22:17:34.855489
2400 22:17:34.855551 ==DQS 1 ==
2401 22:17:34.859039 Final DQS duty delay cell = -4
2402 22:17:34.862429 [-4] MAX Duty = 5000%(X100), DQS PI = 6
2403 22:17:34.865229 [-4] MIN Duty = 4876%(X100), DQS PI = 22
2404 22:17:34.868879 [-4] AVG Duty = 4938%(X100)
2405 22:17:34.868959
2406 22:17:34.872073 CH0 DQS 0 Duty spec in!! Max-Min= 187%
2407 22:17:34.872152
2408 22:17:34.875098 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2409 22:17:34.878496 [DutyScan_Calibration_Flow] ====Done====
2410 22:17:34.878575
2411 22:17:34.881672 [DutyScan_Calibration_Flow] k_type=3
2412 22:17:34.899930
2413 22:17:34.900009 ==DQM 0 ==
2414 22:17:34.903711 Final DQM duty delay cell = 0
2415 22:17:34.906940 [0] MAX Duty = 5031%(X100), DQS PI = 16
2416 22:17:34.910107 [0] MIN Duty = 4875%(X100), DQS PI = 8
2417 22:17:34.910186 [0] AVG Duty = 4953%(X100)
2418 22:17:34.913538
2419 22:17:34.913617 ==DQM 1 ==
2420 22:17:34.917454 Final DQM duty delay cell = 4
2421 22:17:34.920445 [4] MAX Duty = 5187%(X100), DQS PI = 16
2422 22:17:34.923388 [4] MIN Duty = 5000%(X100), DQS PI = 22
2423 22:17:34.923467 [4] AVG Duty = 5093%(X100)
2424 22:17:34.926907
2425 22:17:34.930505 CH0 DQM 0 Duty spec in!! Max-Min= 156%
2426 22:17:34.930584
2427 22:17:34.933757 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2428 22:17:34.936641 [DutyScan_Calibration_Flow] ====Done====
2429 22:17:34.936719
2430 22:17:34.940077 [DutyScan_Calibration_Flow] k_type=2
2431 22:17:34.955903
2432 22:17:34.955986 ==DQ 0 ==
2433 22:17:34.959816 Final DQ duty delay cell = -4
2434 22:17:34.962486 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2435 22:17:34.965687 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2436 22:17:34.969761 [-4] AVG Duty = 4969%(X100)
2437 22:17:34.969844
2438 22:17:34.969927 ==DQ 1 ==
2439 22:17:34.972956 Final DQ duty delay cell = 0
2440 22:17:34.976007 [0] MAX Duty = 5093%(X100), DQS PI = 2
2441 22:17:34.979155 [0] MIN Duty = 4969%(X100), DQS PI = 40
2442 22:17:34.982050 [0] AVG Duty = 5031%(X100)
2443 22:17:34.982134
2444 22:17:34.985348 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2445 22:17:34.985431
2446 22:17:34.989219 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2447 22:17:34.992996 [DutyScan_Calibration_Flow] ====Done====
2448 22:17:34.993080 ==
2449 22:17:34.995343 Dram Type= 6, Freq= 0, CH_1, rank 0
2450 22:17:34.998662 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2451 22:17:34.998746 ==
2452 22:17:35.002038 [Duty_Offset_Calibration]
2453 22:17:35.002121 B0:-1 B1:1 CA:1
2454 22:17:35.002205
2455 22:17:35.005243 [DutyScan_Calibration_Flow] k_type=0
2456 22:17:35.016050
2457 22:17:35.016133 ==CLK 0==
2458 22:17:35.019449 Final CLK duty delay cell = 0
2459 22:17:35.022662 [0] MAX Duty = 5156%(X100), DQS PI = 36
2460 22:17:35.025905 [0] MIN Duty = 4969%(X100), DQS PI = 60
2461 22:17:35.029599 [0] AVG Duty = 5062%(X100)
2462 22:17:35.029683
2463 22:17:35.033129 CH1 CLK Duty spec in!! Max-Min= 187%
2464 22:17:35.036618 [DutyScan_Calibration_Flow] ====Done====
2465 22:17:35.036702
2466 22:17:35.039517 [DutyScan_Calibration_Flow] k_type=1
2467 22:17:35.055507
2468 22:17:35.055591 ==DQS 0 ==
2469 22:17:35.058779 Final DQS duty delay cell = 0
2470 22:17:35.061970 [0] MAX Duty = 5156%(X100), DQS PI = 48
2471 22:17:35.065127 [0] MIN Duty = 4907%(X100), DQS PI = 8
2472 22:17:35.068501 [0] AVG Duty = 5031%(X100)
2473 22:17:35.068590
2474 22:17:35.068674 ==DQS 1 ==
2475 22:17:35.072754 Final DQS duty delay cell = 0
2476 22:17:35.075228 [0] MAX Duty = 5094%(X100), DQS PI = 14
2477 22:17:35.078800 [0] MIN Duty = 4969%(X100), DQS PI = 58
2478 22:17:35.081874 [0] AVG Duty = 5031%(X100)
2479 22:17:35.081957
2480 22:17:35.085475 CH1 DQS 0 Duty spec in!! Max-Min= 249%
2481 22:17:35.085558
2482 22:17:35.088446 CH1 DQS 1 Duty spec in!! Max-Min= 125%
2483 22:17:35.091713 [DutyScan_Calibration_Flow] ====Done====
2484 22:17:35.091796
2485 22:17:35.095112 [DutyScan_Calibration_Flow] k_type=3
2486 22:17:35.111370
2487 22:17:35.111458 ==DQM 0 ==
2488 22:17:35.114412 Final DQM duty delay cell = -4
2489 22:17:35.117878 [-4] MAX Duty = 5062%(X100), DQS PI = 32
2490 22:17:35.120926 [-4] MIN Duty = 4876%(X100), DQS PI = 6
2491 22:17:35.124165 [-4] AVG Duty = 4969%(X100)
2492 22:17:35.124258
2493 22:17:35.124320 ==DQM 1 ==
2494 22:17:35.128051 Final DQM duty delay cell = 0
2495 22:17:35.131227 [0] MAX Duty = 5187%(X100), DQS PI = 4
2496 22:17:35.134335 [0] MIN Duty = 5000%(X100), DQS PI = 28
2497 22:17:35.138402 [0] AVG Duty = 5093%(X100)
2498 22:17:35.138500
2499 22:17:35.141099 CH1 DQM 0 Duty spec in!! Max-Min= 186%
2500 22:17:35.141176
2501 22:17:35.144095 CH1 DQM 1 Duty spec in!! Max-Min= 187%
2502 22:17:35.147868 [DutyScan_Calibration_Flow] ====Done====
2503 22:17:35.147943
2504 22:17:35.150845 [DutyScan_Calibration_Flow] k_type=2
2505 22:17:35.167898
2506 22:17:35.167977 ==DQ 0 ==
2507 22:17:35.170702 Final DQ duty delay cell = 0
2508 22:17:35.174480 [0] MAX Duty = 5187%(X100), DQS PI = 30
2509 22:17:35.177521 [0] MIN Duty = 4907%(X100), DQS PI = 8
2510 22:17:35.177597 [0] AVG Duty = 5047%(X100)
2511 22:17:35.180588
2512 22:17:35.180662 ==DQ 1 ==
2513 22:17:35.184264 Final DQ duty delay cell = 0
2514 22:17:35.187708 [0] MAX Duty = 5124%(X100), DQS PI = 10
2515 22:17:35.190713 [0] MIN Duty = 4938%(X100), DQS PI = 62
2516 22:17:35.190781 [0] AVG Duty = 5031%(X100)
2517 22:17:35.190839
2518 22:17:35.197358 CH1 DQ 0 Duty spec in!! Max-Min= 280%
2519 22:17:35.197442
2520 22:17:35.200997 CH1 DQ 1 Duty spec in!! Max-Min= 186%
2521 22:17:35.204270 [DutyScan_Calibration_Flow] ====Done====
2522 22:17:35.207847 nWR fixed to 30
2523 22:17:35.207920 [ModeRegInit_LP4] CH0 RK0
2524 22:17:35.211156 [ModeRegInit_LP4] CH0 RK1
2525 22:17:35.214322 [ModeRegInit_LP4] CH1 RK0
2526 22:17:35.214429 [ModeRegInit_LP4] CH1 RK1
2527 22:17:35.217817 match AC timing 7
2528 22:17:35.220786 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2529 22:17:35.227560 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2530 22:17:35.230765 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2531 22:17:35.237636 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2532 22:17:35.240778 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2533 22:17:35.240860 ==
2534 22:17:35.244020 Dram Type= 6, Freq= 0, CH_0, rank 0
2535 22:17:35.247318 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2536 22:17:35.247405 ==
2537 22:17:35.254004 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2538 22:17:35.260424 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
2539 22:17:35.267897 [CA 0] Center 39 (9~70) winsize 62
2540 22:17:35.271082 [CA 1] Center 39 (9~70) winsize 62
2541 22:17:35.274265 [CA 2] Center 35 (5~66) winsize 62
2542 22:17:35.277583 [CA 3] Center 35 (5~66) winsize 62
2543 22:17:35.280918 [CA 4] Center 34 (4~64) winsize 61
2544 22:17:35.283983 [CA 5] Center 33 (4~63) winsize 60
2545 22:17:35.284064
2546 22:17:35.287393 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2547 22:17:35.287473
2548 22:17:35.290629 [CATrainingPosCal] consider 1 rank data
2549 22:17:35.293971 u2DelayCellTimex100 = 270/100 ps
2550 22:17:35.297431 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2551 22:17:35.304331 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2552 22:17:35.307186 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2553 22:17:35.310810 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2554 22:17:35.314414 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
2555 22:17:35.317434 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
2556 22:17:35.317514
2557 22:17:35.320937 CA PerBit enable=1, Macro0, CA PI delay=33
2558 22:17:35.321017
2559 22:17:35.324201 [CBTSetCACLKResult] CA Dly = 33
2560 22:17:35.324281 CS Dly: 8 (0~39)
2561 22:17:35.327628 ==
2562 22:17:35.331005 Dram Type= 6, Freq= 0, CH_0, rank 1
2563 22:17:35.333877 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2564 22:17:35.333957 ==
2565 22:17:35.337588 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2566 22:17:35.343586 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2567 22:17:35.353097 [CA 0] Center 39 (8~70) winsize 63
2568 22:17:35.356925 [CA 1] Center 39 (9~70) winsize 62
2569 22:17:35.360134 [CA 2] Center 35 (5~66) winsize 62
2570 22:17:35.364054 [CA 3] Center 34 (4~65) winsize 62
2571 22:17:35.366932 [CA 4] Center 33 (3~64) winsize 62
2572 22:17:35.370309 [CA 5] Center 33 (3~63) winsize 61
2573 22:17:35.370390
2574 22:17:35.374226 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2575 22:17:35.374307
2576 22:17:35.376829 [CATrainingPosCal] consider 2 rank data
2577 22:17:35.380334 u2DelayCellTimex100 = 270/100 ps
2578 22:17:35.383686 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2579 22:17:35.386587 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2580 22:17:35.393092 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2581 22:17:35.396571 CA3 delay=35 (5~65),Diff = 2 PI (9 cell)
2582 22:17:35.400066 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
2583 22:17:35.403833 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
2584 22:17:35.403913
2585 22:17:35.406597 CA PerBit enable=1, Macro0, CA PI delay=33
2586 22:17:35.406677
2587 22:17:35.409703 [CBTSetCACLKResult] CA Dly = 33
2588 22:17:35.409783 CS Dly: 9 (0~41)
2589 22:17:35.409845
2590 22:17:35.416532 ----->DramcWriteLeveling(PI) begin...
2591 22:17:35.416627 ==
2592 22:17:35.419888 Dram Type= 6, Freq= 0, CH_0, rank 0
2593 22:17:35.423232 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2594 22:17:35.423313 ==
2595 22:17:35.426437 Write leveling (Byte 0): 33 => 33
2596 22:17:35.429833 Write leveling (Byte 1): 30 => 30
2597 22:17:35.433004 DramcWriteLeveling(PI) end<-----
2598 22:17:35.433085
2599 22:17:35.433148 ==
2600 22:17:35.436437 Dram Type= 6, Freq= 0, CH_0, rank 0
2601 22:17:35.440050 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2602 22:17:35.440132 ==
2603 22:17:35.443398 [Gating] SW mode calibration
2604 22:17:35.449736 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2605 22:17:35.456335 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2606 22:17:35.459739 0 15 0 | B1->B0 | 2323 2d2d | 0 1 | (0 0) (1 1)
2607 22:17:35.462886 0 15 4 | B1->B0 | 2626 3434 | 1 1 | (0 0) (1 1)
2608 22:17:35.469507 0 15 8 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
2609 22:17:35.472801 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2610 22:17:35.476020 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2611 22:17:35.483035 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2612 22:17:35.486214 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2613 22:17:35.489528 0 15 28 | B1->B0 | 3434 2c2c | 1 0 | (1 1) (1 0)
2614 22:17:35.492542 1 0 0 | B1->B0 | 3333 2323 | 0 0 | (1 0) (0 0)
2615 22:17:35.500189 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2616 22:17:35.503071 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2617 22:17:35.506349 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2618 22:17:35.512953 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2619 22:17:35.516506 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2620 22:17:35.519297 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2621 22:17:35.525971 1 0 28 | B1->B0 | 2323 3535 | 0 0 | (0 0) (0 0)
2622 22:17:35.529511 1 1 0 | B1->B0 | 2323 4343 | 1 0 | (0 0) (1 1)
2623 22:17:35.532457 1 1 4 | B1->B0 | 4444 4646 | 1 0 | (0 0) (0 0)
2624 22:17:35.539178 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2625 22:17:35.542410 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2626 22:17:35.545608 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2627 22:17:35.552782 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2628 22:17:35.555654 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2629 22:17:35.559125 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2630 22:17:35.565950 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2631 22:17:35.568680 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2632 22:17:35.572050 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2633 22:17:35.579178 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2634 22:17:35.582292 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2635 22:17:35.585118 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2636 22:17:35.592168 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2637 22:17:35.595530 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2638 22:17:35.599154 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2639 22:17:35.605165 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2640 22:17:35.608470 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2641 22:17:35.611684 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2642 22:17:35.619185 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2643 22:17:35.621617 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2644 22:17:35.624991 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2645 22:17:35.632067 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2646 22:17:35.635086 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2647 22:17:35.638203 Total UI for P1: 0, mck2ui 16
2648 22:17:35.641982 best dqsien dly found for B0: ( 1, 3, 26)
2649 22:17:35.645035 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2650 22:17:35.648282 Total UI for P1: 0, mck2ui 16
2651 22:17:35.651735 best dqsien dly found for B1: ( 1, 4, 0)
2652 22:17:35.655193 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2653 22:17:35.658346 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2654 22:17:35.658429
2655 22:17:35.661682 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2656 22:17:35.668245 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2657 22:17:35.668327 [Gating] SW calibration Done
2658 22:17:35.668429 ==
2659 22:17:35.671850 Dram Type= 6, Freq= 0, CH_0, rank 0
2660 22:17:35.678706 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2661 22:17:35.678791 ==
2662 22:17:35.678873 RX Vref Scan: 0
2663 22:17:35.678951
2664 22:17:35.681477 RX Vref 0 -> 0, step: 1
2665 22:17:35.681560
2666 22:17:35.685405 RX Delay -40 -> 252, step: 8
2667 22:17:35.688354 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2668 22:17:35.691308 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2669 22:17:35.694792 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2670 22:17:35.701085 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2671 22:17:35.704537 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2672 22:17:35.708227 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2673 22:17:35.711137 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2674 22:17:35.714388 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2675 22:17:35.721713 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2676 22:17:35.724629 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2677 22:17:35.727846 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
2678 22:17:35.730848 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2679 22:17:35.734384 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2680 22:17:35.741121 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2681 22:17:35.745165 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2682 22:17:35.748368 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2683 22:17:35.748476 ==
2684 22:17:35.751138 Dram Type= 6, Freq= 0, CH_0, rank 0
2685 22:17:35.754908 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2686 22:17:35.754991 ==
2687 22:17:35.758030 DQS Delay:
2688 22:17:35.758112 DQS0 = 0, DQS1 = 0
2689 22:17:35.761127 DQM Delay:
2690 22:17:35.761208 DQM0 = 119, DQM1 = 107
2691 22:17:35.764350 DQ Delay:
2692 22:17:35.767699 DQ0 =119, DQ1 =119, DQ2 =115, DQ3 =115
2693 22:17:35.771092 DQ4 =123, DQ5 =111, DQ6 =127, DQ7 =123
2694 22:17:35.773969 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =103
2695 22:17:35.777534 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
2696 22:17:35.777615
2697 22:17:35.777679
2698 22:17:35.777738 ==
2699 22:17:35.780772 Dram Type= 6, Freq= 0, CH_0, rank 0
2700 22:17:35.784327 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2701 22:17:35.784410 ==
2702 22:17:35.784474
2703 22:17:35.784574
2704 22:17:35.787365 TX Vref Scan disable
2705 22:17:35.790952 == TX Byte 0 ==
2706 22:17:35.794263 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2707 22:17:35.797588 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2708 22:17:35.801184 == TX Byte 1 ==
2709 22:17:35.804016 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2710 22:17:35.807310 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2711 22:17:35.807392 ==
2712 22:17:35.810530 Dram Type= 6, Freq= 0, CH_0, rank 0
2713 22:17:35.817030 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2714 22:17:35.817111 ==
2715 22:17:35.827946 TX Vref=22, minBit 6, minWin=25, winSum=418
2716 22:17:35.831038 TX Vref=24, minBit 14, minWin=25, winSum=423
2717 22:17:35.834310 TX Vref=26, minBit 1, minWin=26, winSum=433
2718 22:17:35.837939 TX Vref=28, minBit 10, minWin=26, winSum=438
2719 22:17:35.840693 TX Vref=30, minBit 5, minWin=26, winSum=431
2720 22:17:35.847303 TX Vref=32, minBit 4, minWin=26, winSum=429
2721 22:17:35.851351 [TxChooseVref] Worse bit 10, Min win 26, Win sum 438, Final Vref 28
2722 22:17:35.851433
2723 22:17:35.854115 Final TX Range 1 Vref 28
2724 22:17:35.854197
2725 22:17:35.854261 ==
2726 22:17:35.857625 Dram Type= 6, Freq= 0, CH_0, rank 0
2727 22:17:35.864052 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2728 22:17:35.864134 ==
2729 22:17:35.864198
2730 22:17:35.864256
2731 22:17:35.864313 TX Vref Scan disable
2732 22:17:35.867676 == TX Byte 0 ==
2733 22:17:35.871091 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2734 22:17:35.874538 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2735 22:17:35.877657 == TX Byte 1 ==
2736 22:17:35.881247 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2737 22:17:35.884545 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2738 22:17:35.888097
2739 22:17:35.888177 [DATLAT]
2740 22:17:35.888240 Freq=1200, CH0 RK0
2741 22:17:35.888301
2742 22:17:35.890934 DATLAT Default: 0xd
2743 22:17:35.891022 0, 0xFFFF, sum = 0
2744 22:17:35.893866 1, 0xFFFF, sum = 0
2745 22:17:35.897683 2, 0xFFFF, sum = 0
2746 22:17:35.897765 3, 0xFFFF, sum = 0
2747 22:17:35.900646 4, 0xFFFF, sum = 0
2748 22:17:35.900729 5, 0xFFFF, sum = 0
2749 22:17:35.904788 6, 0xFFFF, sum = 0
2750 22:17:35.904871 7, 0xFFFF, sum = 0
2751 22:17:35.907666 8, 0xFFFF, sum = 0
2752 22:17:35.907749 9, 0xFFFF, sum = 0
2753 22:17:35.910663 10, 0xFFFF, sum = 0
2754 22:17:35.910746 11, 0xFFFF, sum = 0
2755 22:17:35.914662 12, 0x0, sum = 1
2756 22:17:35.914745 13, 0x0, sum = 2
2757 22:17:35.917189 14, 0x0, sum = 3
2758 22:17:35.917273 15, 0x0, sum = 4
2759 22:17:35.920864 best_step = 13
2760 22:17:35.920944
2761 22:17:35.921008 ==
2762 22:17:35.924122 Dram Type= 6, Freq= 0, CH_0, rank 0
2763 22:17:35.927335 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2764 22:17:35.927417 ==
2765 22:17:35.927482 RX Vref Scan: 1
2766 22:17:35.927541
2767 22:17:35.931021 Set Vref Range= 32 -> 127
2768 22:17:35.931103
2769 22:17:35.934124 RX Vref 32 -> 127, step: 1
2770 22:17:35.934205
2771 22:17:35.937109 RX Delay -21 -> 252, step: 4
2772 22:17:35.937190
2773 22:17:35.940500 Set Vref, RX VrefLevel [Byte0]: 32
2774 22:17:35.944034 [Byte1]: 32
2775 22:17:35.944116
2776 22:17:35.947392 Set Vref, RX VrefLevel [Byte0]: 33
2777 22:17:35.950412 [Byte1]: 33
2778 22:17:35.954219
2779 22:17:35.954300 Set Vref, RX VrefLevel [Byte0]: 34
2780 22:17:35.957603 [Byte1]: 34
2781 22:17:35.963016
2782 22:17:35.963097 Set Vref, RX VrefLevel [Byte0]: 35
2783 22:17:35.965163 [Byte1]: 35
2784 22:17:35.970603
2785 22:17:35.970684 Set Vref, RX VrefLevel [Byte0]: 36
2786 22:17:35.973329 [Byte1]: 36
2787 22:17:35.977863
2788 22:17:35.977945 Set Vref, RX VrefLevel [Byte0]: 37
2789 22:17:35.981643 [Byte1]: 37
2790 22:17:35.985688
2791 22:17:35.985769 Set Vref, RX VrefLevel [Byte0]: 38
2792 22:17:35.989324 [Byte1]: 38
2793 22:17:35.993662
2794 22:17:35.993744 Set Vref, RX VrefLevel [Byte0]: 39
2795 22:17:35.997347 [Byte1]: 39
2796 22:17:36.001771
2797 22:17:36.001852 Set Vref, RX VrefLevel [Byte0]: 40
2798 22:17:36.004865 [Byte1]: 40
2799 22:17:36.009749
2800 22:17:36.009830 Set Vref, RX VrefLevel [Byte0]: 41
2801 22:17:36.013354 [Byte1]: 41
2802 22:17:36.017775
2803 22:17:36.017856 Set Vref, RX VrefLevel [Byte0]: 42
2804 22:17:36.021262 [Byte1]: 42
2805 22:17:36.025752
2806 22:17:36.025849 Set Vref, RX VrefLevel [Byte0]: 43
2807 22:17:36.028800 [Byte1]: 43
2808 22:17:36.033474
2809 22:17:36.033555 Set Vref, RX VrefLevel [Byte0]: 44
2810 22:17:36.036800 [Byte1]: 44
2811 22:17:36.041556
2812 22:17:36.041654 Set Vref, RX VrefLevel [Byte0]: 45
2813 22:17:36.045175 [Byte1]: 45
2814 22:17:36.049841
2815 22:17:36.049923 Set Vref, RX VrefLevel [Byte0]: 46
2816 22:17:36.052716 [Byte1]: 46
2817 22:17:36.057337
2818 22:17:36.057418 Set Vref, RX VrefLevel [Byte0]: 47
2819 22:17:36.060271 [Byte1]: 47
2820 22:17:36.065028
2821 22:17:36.065109 Set Vref, RX VrefLevel [Byte0]: 48
2822 22:17:36.068315 [Byte1]: 48
2823 22:17:36.074038
2824 22:17:36.074119 Set Vref, RX VrefLevel [Byte0]: 49
2825 22:17:36.076629 [Byte1]: 49
2826 22:17:36.080957
2827 22:17:36.081037 Set Vref, RX VrefLevel [Byte0]: 50
2828 22:17:36.084791 [Byte1]: 50
2829 22:17:36.089470
2830 22:17:36.089551 Set Vref, RX VrefLevel [Byte0]: 51
2831 22:17:36.095126 [Byte1]: 51
2832 22:17:36.095209
2833 22:17:36.098892 Set Vref, RX VrefLevel [Byte0]: 52
2834 22:17:36.101828 [Byte1]: 52
2835 22:17:36.101910
2836 22:17:36.105075 Set Vref, RX VrefLevel [Byte0]: 53
2837 22:17:36.108768 [Byte1]: 53
2838 22:17:36.112710
2839 22:17:36.112791 Set Vref, RX VrefLevel [Byte0]: 54
2840 22:17:36.116306 [Byte1]: 54
2841 22:17:36.120494
2842 22:17:36.120616 Set Vref, RX VrefLevel [Byte0]: 55
2843 22:17:36.123844 [Byte1]: 55
2844 22:17:36.128853
2845 22:17:36.128935 Set Vref, RX VrefLevel [Byte0]: 56
2846 22:17:36.131790 [Byte1]: 56
2847 22:17:36.136899
2848 22:17:36.136981 Set Vref, RX VrefLevel [Byte0]: 57
2849 22:17:36.139723 [Byte1]: 57
2850 22:17:36.144554
2851 22:17:36.144649 Set Vref, RX VrefLevel [Byte0]: 58
2852 22:17:36.147626 [Byte1]: 58
2853 22:17:36.152659
2854 22:17:36.152740 Set Vref, RX VrefLevel [Byte0]: 59
2855 22:17:36.155839 [Byte1]: 59
2856 22:17:36.160208
2857 22:17:36.160316 Set Vref, RX VrefLevel [Byte0]: 60
2858 22:17:36.163851 [Byte1]: 60
2859 22:17:36.168297
2860 22:17:36.168404 Set Vref, RX VrefLevel [Byte0]: 61
2861 22:17:36.171383 [Byte1]: 61
2862 22:17:36.175947
2863 22:17:36.176028 Set Vref, RX VrefLevel [Byte0]: 62
2864 22:17:36.179576 [Byte1]: 62
2865 22:17:36.183963
2866 22:17:36.184045 Set Vref, RX VrefLevel [Byte0]: 63
2867 22:17:36.187784 [Byte1]: 63
2868 22:17:36.192107
2869 22:17:36.192188 Set Vref, RX VrefLevel [Byte0]: 64
2870 22:17:36.195604 [Byte1]: 64
2871 22:17:36.200654
2872 22:17:36.200739 Set Vref, RX VrefLevel [Byte0]: 65
2873 22:17:36.203606 [Byte1]: 65
2874 22:17:36.208354
2875 22:17:36.208435 Set Vref, RX VrefLevel [Byte0]: 66
2876 22:17:36.210882 [Byte1]: 66
2877 22:17:36.215926
2878 22:17:36.216007 Set Vref, RX VrefLevel [Byte0]: 67
2879 22:17:36.219603 [Byte1]: 67
2880 22:17:36.223934
2881 22:17:36.224016 Set Vref, RX VrefLevel [Byte0]: 68
2882 22:17:36.227072 [Byte1]: 68
2883 22:17:36.231783
2884 22:17:36.231855 Set Vref, RX VrefLevel [Byte0]: 69
2885 22:17:36.234679 [Byte1]: 69
2886 22:17:36.239422
2887 22:17:36.239490 Set Vref, RX VrefLevel [Byte0]: 70
2888 22:17:36.242702 [Byte1]: 70
2889 22:17:36.247704
2890 22:17:36.247782 Set Vref, RX VrefLevel [Byte0]: 71
2891 22:17:36.250995 [Byte1]: 71
2892 22:17:36.255349
2893 22:17:36.255450 Set Vref, RX VrefLevel [Byte0]: 72
2894 22:17:36.259157 [Byte1]: 72
2895 22:17:36.263831
2896 22:17:36.263900 Set Vref, RX VrefLevel [Byte0]: 73
2897 22:17:36.266783 [Byte1]: 73
2898 22:17:36.271098
2899 22:17:36.271166 Set Vref, RX VrefLevel [Byte0]: 74
2900 22:17:36.274958 [Byte1]: 74
2901 22:17:36.279045
2902 22:17:36.279113 Set Vref, RX VrefLevel [Byte0]: 75
2903 22:17:36.282650 [Byte1]: 75
2904 22:17:36.287794
2905 22:17:36.287901 Set Vref, RX VrefLevel [Byte0]: 76
2906 22:17:36.293343 [Byte1]: 76
2907 22:17:36.293446
2908 22:17:36.296880 Set Vref, RX VrefLevel [Byte0]: 77
2909 22:17:36.300407 [Byte1]: 77
2910 22:17:36.300518
2911 22:17:36.303385 Final RX Vref Byte 0 = 57 to rank0
2912 22:17:36.306475 Final RX Vref Byte 1 = 60 to rank0
2913 22:17:36.310536 Final RX Vref Byte 0 = 57 to rank1
2914 22:17:36.313852 Final RX Vref Byte 1 = 60 to rank1==
2915 22:17:36.316824 Dram Type= 6, Freq= 0, CH_0, rank 0
2916 22:17:36.319971 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2917 22:17:36.324423 ==
2918 22:17:36.324572 DQS Delay:
2919 22:17:36.324636 DQS0 = 0, DQS1 = 0
2920 22:17:36.326492 DQM Delay:
2921 22:17:36.326564 DQM0 = 118, DQM1 = 107
2922 22:17:36.329839 DQ Delay:
2923 22:17:36.332800 DQ0 =116, DQ1 =120, DQ2 =116, DQ3 =114
2924 22:17:36.336424 DQ4 =120, DQ5 =110, DQ6 =126, DQ7 =126
2925 22:17:36.340043 DQ8 =96, DQ9 =94, DQ10 =110, DQ11 =102
2926 22:17:36.343186 DQ12 =112, DQ13 =112, DQ14 =122, DQ15 =114
2927 22:17:36.343261
2928 22:17:36.343323
2929 22:17:36.349749 [DQSOSCAuto] RK0, (LSB)MR18= 0x12fe, (MSB)MR19= 0x403, tDQSOscB0 = 410 ps tDQSOscB1 = 403 ps
2930 22:17:36.353057 CH0 RK0: MR19=403, MR18=12FE
2931 22:17:36.359882 CH0_RK0: MR19=0x403, MR18=0x12FE, DQSOSC=403, MR23=63, INC=40, DEC=26
2932 22:17:36.359954
2933 22:17:36.362688 ----->DramcWriteLeveling(PI) begin...
2934 22:17:36.362765 ==
2935 22:17:36.366278 Dram Type= 6, Freq= 0, CH_0, rank 1
2936 22:17:36.369679 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2937 22:17:36.372603 ==
2938 22:17:36.372671 Write leveling (Byte 0): 32 => 32
2939 22:17:36.375861 Write leveling (Byte 1): 29 => 29
2940 22:17:36.379182 DramcWriteLeveling(PI) end<-----
2941 22:17:36.379261
2942 22:17:36.379323 ==
2943 22:17:36.382237 Dram Type= 6, Freq= 0, CH_0, rank 1
2944 22:17:36.388776 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2945 22:17:36.388847 ==
2946 22:17:36.391929 [Gating] SW mode calibration
2947 22:17:36.398667 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2948 22:17:36.402499 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2949 22:17:36.408887 0 15 0 | B1->B0 | 2323 3232 | 0 1 | (0 0) (1 1)
2950 22:17:36.412007 0 15 4 | B1->B0 | 3232 3434 | 1 1 | (0 0) (1 1)
2951 22:17:36.415321 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2952 22:17:36.421926 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2953 22:17:36.425642 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2954 22:17:36.429488 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2955 22:17:36.435245 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2956 22:17:36.438914 0 15 28 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
2957 22:17:36.441892 1 0 0 | B1->B0 | 2e2e 2323 | 0 0 | (1 0) (0 0)
2958 22:17:36.448651 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2959 22:17:36.451939 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2960 22:17:36.455642 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2961 22:17:36.462055 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2962 22:17:36.465291 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2963 22:17:36.468714 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2964 22:17:36.475290 1 0 28 | B1->B0 | 2424 3232 | 0 0 | (1 1) (0 0)
2965 22:17:36.478507 1 1 0 | B1->B0 | 3433 4646 | 1 0 | (1 1) (0 0)
2966 22:17:36.482273 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2967 22:17:36.488719 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2968 22:17:36.491646 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2969 22:17:36.495295 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2970 22:17:36.498528 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2971 22:17:36.504900 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2972 22:17:36.508644 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2973 22:17:36.511578 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2974 22:17:36.518636 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2975 22:17:36.521712 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2976 22:17:36.524934 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2977 22:17:36.531710 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2978 22:17:36.534747 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2979 22:17:36.538255 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2980 22:17:36.544848 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2981 22:17:36.547999 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2982 22:17:36.552011 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2983 22:17:36.558398 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2984 22:17:36.561299 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2985 22:17:36.564973 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2986 22:17:36.571233 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2987 22:17:36.574681 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2988 22:17:36.577732 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2989 22:17:36.584415 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2990 22:17:36.587957 Total UI for P1: 0, mck2ui 16
2991 22:17:36.590678 best dqsien dly found for B0: ( 1, 3, 28)
2992 22:17:36.594637 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2993 22:17:36.598431 Total UI for P1: 0, mck2ui 16
2994 22:17:36.601100 best dqsien dly found for B1: ( 1, 3, 30)
2995 22:17:36.604664 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2996 22:17:36.607946 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2997 22:17:36.608026
2998 22:17:36.610851 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2999 22:17:36.614627 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
3000 22:17:36.617321 [Gating] SW calibration Done
3001 22:17:36.617401 ==
3002 22:17:36.620437 Dram Type= 6, Freq= 0, CH_0, rank 1
3003 22:17:36.627225 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3004 22:17:36.627307 ==
3005 22:17:36.627371 RX Vref Scan: 0
3006 22:17:36.627428
3007 22:17:36.630881 RX Vref 0 -> 0, step: 1
3008 22:17:36.630961
3009 22:17:36.634114 RX Delay -40 -> 252, step: 8
3010 22:17:36.637265 iDelay=200, Bit 0, Center 115 (48 ~ 183) 136
3011 22:17:36.640892 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
3012 22:17:36.644350 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
3013 22:17:36.647740 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3014 22:17:36.654520 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3015 22:17:36.657372 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
3016 22:17:36.660468 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3017 22:17:36.664206 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
3018 22:17:36.667226 iDelay=200, Bit 8, Center 99 (24 ~ 175) 152
3019 22:17:36.674130 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3020 22:17:36.677336 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3021 22:17:36.680506 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3022 22:17:36.683977 iDelay=200, Bit 12, Center 115 (40 ~ 191) 152
3023 22:17:36.687259 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
3024 22:17:36.694225 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3025 22:17:36.697174 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
3026 22:17:36.697254 ==
3027 22:17:36.700428 Dram Type= 6, Freq= 0, CH_0, rank 1
3028 22:17:36.703651 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3029 22:17:36.703732 ==
3030 22:17:36.706886 DQS Delay:
3031 22:17:36.706967 DQS0 = 0, DQS1 = 0
3032 22:17:36.707029 DQM Delay:
3033 22:17:36.710376 DQM0 = 117, DQM1 = 109
3034 22:17:36.710456 DQ Delay:
3035 22:17:36.713573 DQ0 =115, DQ1 =119, DQ2 =111, DQ3 =115
3036 22:17:36.717307 DQ4 =119, DQ5 =111, DQ6 =127, DQ7 =123
3037 22:17:36.720278 DQ8 =99, DQ9 =95, DQ10 =111, DQ11 =103
3038 22:17:36.726949 DQ12 =115, DQ13 =115, DQ14 =119, DQ15 =115
3039 22:17:36.727029
3040 22:17:36.727091
3041 22:17:36.727148 ==
3042 22:17:36.730049 Dram Type= 6, Freq= 0, CH_0, rank 1
3043 22:17:36.734011 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3044 22:17:36.734093 ==
3045 22:17:36.734159
3046 22:17:36.734216
3047 22:17:36.736846 TX Vref Scan disable
3048 22:17:36.736926 == TX Byte 0 ==
3049 22:17:36.744196 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
3050 22:17:36.746790 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
3051 22:17:36.746875 == TX Byte 1 ==
3052 22:17:36.753281 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3053 22:17:36.756879 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3054 22:17:36.756960 ==
3055 22:17:36.760672 Dram Type= 6, Freq= 0, CH_0, rank 1
3056 22:17:36.763443 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3057 22:17:36.763524 ==
3058 22:17:36.776773 TX Vref=22, minBit 5, minWin=25, winSum=414
3059 22:17:36.780303 TX Vref=24, minBit 10, minWin=25, winSum=421
3060 22:17:36.783456 TX Vref=26, minBit 15, minWin=25, winSum=423
3061 22:17:36.786154 TX Vref=28, minBit 12, minWin=26, winSum=431
3062 22:17:36.790220 TX Vref=30, minBit 14, minWin=25, winSum=429
3063 22:17:36.796767 TX Vref=32, minBit 12, minWin=25, winSum=425
3064 22:17:36.799812 [TxChooseVref] Worse bit 12, Min win 26, Win sum 431, Final Vref 28
3065 22:17:36.803266
3066 22:17:36.803347 Final TX Range 1 Vref 28
3067 22:17:36.803410
3068 22:17:36.803467 ==
3069 22:17:36.806341 Dram Type= 6, Freq= 0, CH_0, rank 1
3070 22:17:36.812970 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3071 22:17:36.813052 ==
3072 22:17:36.813115
3073 22:17:36.813172
3074 22:17:36.813227 TX Vref Scan disable
3075 22:17:36.817491 == TX Byte 0 ==
3076 22:17:36.820252 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
3077 22:17:36.826503 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
3078 22:17:36.826585 == TX Byte 1 ==
3079 22:17:36.829751 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3080 22:17:36.836473 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3081 22:17:36.836578
3082 22:17:36.836642 [DATLAT]
3083 22:17:36.836700 Freq=1200, CH0 RK1
3084 22:17:36.836764
3085 22:17:36.839948 DATLAT Default: 0xd
3086 22:17:36.840029 0, 0xFFFF, sum = 0
3087 22:17:36.843274 1, 0xFFFF, sum = 0
3088 22:17:36.846882 2, 0xFFFF, sum = 0
3089 22:17:36.846963 3, 0xFFFF, sum = 0
3090 22:17:36.850124 4, 0xFFFF, sum = 0
3091 22:17:36.850206 5, 0xFFFF, sum = 0
3092 22:17:36.853516 6, 0xFFFF, sum = 0
3093 22:17:36.853599 7, 0xFFFF, sum = 0
3094 22:17:36.856729 8, 0xFFFF, sum = 0
3095 22:17:36.856812 9, 0xFFFF, sum = 0
3096 22:17:36.860087 10, 0xFFFF, sum = 0
3097 22:17:36.860169 11, 0xFFFF, sum = 0
3098 22:17:36.863242 12, 0x0, sum = 1
3099 22:17:36.863324 13, 0x0, sum = 2
3100 22:17:36.866829 14, 0x0, sum = 3
3101 22:17:36.866911 15, 0x0, sum = 4
3102 22:17:36.870157 best_step = 13
3103 22:17:36.870239
3104 22:17:36.870302 ==
3105 22:17:36.872900 Dram Type= 6, Freq= 0, CH_0, rank 1
3106 22:17:36.876486 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3107 22:17:36.876591 ==
3108 22:17:36.876656 RX Vref Scan: 0
3109 22:17:36.879607
3110 22:17:36.879688 RX Vref 0 -> 0, step: 1
3111 22:17:36.879753
3112 22:17:36.883174 RX Delay -21 -> 252, step: 4
3113 22:17:36.889475 iDelay=199, Bit 0, Center 114 (51 ~ 178) 128
3114 22:17:36.893171 iDelay=199, Bit 1, Center 120 (51 ~ 190) 140
3115 22:17:36.896015 iDelay=199, Bit 2, Center 110 (43 ~ 178) 136
3116 22:17:36.899503 iDelay=199, Bit 3, Center 114 (43 ~ 186) 144
3117 22:17:36.902984 iDelay=199, Bit 4, Center 116 (47 ~ 186) 140
3118 22:17:36.909431 iDelay=199, Bit 5, Center 110 (43 ~ 178) 136
3119 22:17:36.912721 iDelay=199, Bit 6, Center 128 (59 ~ 198) 140
3120 22:17:36.916321 iDelay=199, Bit 7, Center 124 (55 ~ 194) 140
3121 22:17:36.919008 iDelay=199, Bit 8, Center 98 (31 ~ 166) 136
3122 22:17:36.922463 iDelay=199, Bit 9, Center 94 (27 ~ 162) 136
3123 22:17:36.928962 iDelay=199, Bit 10, Center 110 (43 ~ 178) 136
3124 22:17:36.932561 iDelay=199, Bit 11, Center 104 (39 ~ 170) 132
3125 22:17:36.935555 iDelay=199, Bit 12, Center 116 (51 ~ 182) 132
3126 22:17:36.938860 iDelay=199, Bit 13, Center 114 (51 ~ 178) 128
3127 22:17:36.942519 iDelay=199, Bit 14, Center 120 (55 ~ 186) 132
3128 22:17:36.949015 iDelay=199, Bit 15, Center 116 (55 ~ 178) 124
3129 22:17:36.949099 ==
3130 22:17:36.952339 Dram Type= 6, Freq= 0, CH_0, rank 1
3131 22:17:36.955699 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3132 22:17:36.955780 ==
3133 22:17:36.955844 DQS Delay:
3134 22:17:36.959061 DQS0 = 0, DQS1 = 0
3135 22:17:36.959142 DQM Delay:
3136 22:17:36.962047 DQM0 = 117, DQM1 = 109
3137 22:17:36.962128 DQ Delay:
3138 22:17:36.965757 DQ0 =114, DQ1 =120, DQ2 =110, DQ3 =114
3139 22:17:36.969065 DQ4 =116, DQ5 =110, DQ6 =128, DQ7 =124
3140 22:17:36.972220 DQ8 =98, DQ9 =94, DQ10 =110, DQ11 =104
3141 22:17:36.975380 DQ12 =116, DQ13 =114, DQ14 =120, DQ15 =116
3142 22:17:36.975461
3143 22:17:36.978582
3144 22:17:36.985303 [DQSOSCAuto] RK1, (LSB)MR18= 0xee8, (MSB)MR19= 0x403, tDQSOscB0 = 420 ps tDQSOscB1 = 404 ps
3145 22:17:36.988919 CH0 RK1: MR19=403, MR18=EE8
3146 22:17:36.995379 CH0_RK1: MR19=0x403, MR18=0xEE8, DQSOSC=404, MR23=63, INC=40, DEC=26
3147 22:17:36.995461 [RxdqsGatingPostProcess] freq 1200
3148 22:17:37.002204 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3149 22:17:37.005447 best DQS0 dly(2T, 0.5T) = (0, 11)
3150 22:17:37.008858 best DQS1 dly(2T, 0.5T) = (0, 12)
3151 22:17:37.011966 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3152 22:17:37.015649 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3153 22:17:37.018646 best DQS0 dly(2T, 0.5T) = (0, 11)
3154 22:17:37.021626 best DQS1 dly(2T, 0.5T) = (0, 11)
3155 22:17:37.025304 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3156 22:17:37.028644 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3157 22:17:37.031695 Pre-setting of DQS Precalculation
3158 22:17:37.034975 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3159 22:17:37.035057 ==
3160 22:17:37.038491 Dram Type= 6, Freq= 0, CH_1, rank 0
3161 22:17:37.041573 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3162 22:17:37.045255 ==
3163 22:17:37.048154 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3164 22:17:37.055145 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3165 22:17:37.063103 [CA 0] Center 37 (7~67) winsize 61
3166 22:17:37.066338 [CA 1] Center 37 (7~68) winsize 62
3167 22:17:37.069656 [CA 2] Center 34 (4~64) winsize 61
3168 22:17:37.073651 [CA 3] Center 33 (3~64) winsize 62
3169 22:17:37.076357 [CA 4] Center 34 (4~64) winsize 61
3170 22:17:37.080013 [CA 5] Center 33 (3~64) winsize 62
3171 22:17:37.080094
3172 22:17:37.083107 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3173 22:17:37.083189
3174 22:17:37.086221 [CATrainingPosCal] consider 1 rank data
3175 22:17:37.089422 u2DelayCellTimex100 = 270/100 ps
3176 22:17:37.093192 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3177 22:17:37.099277 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3178 22:17:37.102508 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3179 22:17:37.106085 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3180 22:17:37.109671 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3181 22:17:37.112749 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3182 22:17:37.112831
3183 22:17:37.115987 CA PerBit enable=1, Macro0, CA PI delay=33
3184 22:17:37.116068
3185 22:17:37.119387 [CBTSetCACLKResult] CA Dly = 33
3186 22:17:37.119468 CS Dly: 5 (0~36)
3187 22:17:37.122962 ==
3188 22:17:37.123043 Dram Type= 6, Freq= 0, CH_1, rank 1
3189 22:17:37.129643 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3190 22:17:37.129725 ==
3191 22:17:37.132612 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3192 22:17:37.139398 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3193 22:17:37.148405 [CA 0] Center 37 (7~67) winsize 61
3194 22:17:37.151661 [CA 1] Center 37 (7~68) winsize 62
3195 22:17:37.155471 [CA 2] Center 34 (4~65) winsize 62
3196 22:17:37.158462 [CA 3] Center 33 (3~64) winsize 62
3197 22:17:37.162792 [CA 4] Center 34 (3~65) winsize 63
3198 22:17:37.165087 [CA 5] Center 33 (3~64) winsize 62
3199 22:17:37.165168
3200 22:17:37.168835 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3201 22:17:37.168937
3202 22:17:37.172805 [CATrainingPosCal] consider 2 rank data
3203 22:17:37.175392 u2DelayCellTimex100 = 270/100 ps
3204 22:17:37.178896 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3205 22:17:37.182021 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3206 22:17:37.188779 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3207 22:17:37.191942 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3208 22:17:37.195519 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3209 22:17:37.198898 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3210 22:17:37.198979
3211 22:17:37.202002 CA PerBit enable=1, Macro0, CA PI delay=33
3212 22:17:37.202086
3213 22:17:37.205429 [CBTSetCACLKResult] CA Dly = 33
3214 22:17:37.205510 CS Dly: 7 (0~40)
3215 22:17:37.205574
3216 22:17:37.209003 ----->DramcWriteLeveling(PI) begin...
3217 22:17:37.212100 ==
3218 22:17:37.215152 Dram Type= 6, Freq= 0, CH_1, rank 0
3219 22:17:37.218444 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3220 22:17:37.218527 ==
3221 22:17:37.222188 Write leveling (Byte 0): 25 => 25
3222 22:17:37.224798 Write leveling (Byte 1): 26 => 26
3223 22:17:37.228496 DramcWriteLeveling(PI) end<-----
3224 22:17:37.228617
3225 22:17:37.228682 ==
3226 22:17:37.231994 Dram Type= 6, Freq= 0, CH_1, rank 0
3227 22:17:37.235114 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3228 22:17:37.235197 ==
3229 22:17:37.238321 [Gating] SW mode calibration
3230 22:17:37.245258 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3231 22:17:37.251342 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3232 22:17:37.254858 0 15 0 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
3233 22:17:37.258465 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3234 22:17:37.264776 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3235 22:17:37.268019 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3236 22:17:37.271237 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3237 22:17:37.278460 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3238 22:17:37.281511 0 15 24 | B1->B0 | 3434 2c2c | 0 1 | (0 0) (1 0)
3239 22:17:37.285112 0 15 28 | B1->B0 | 2525 2323 | 0 0 | (1 0) (1 0)
3240 22:17:37.291213 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3241 22:17:37.294924 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3242 22:17:37.298003 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3243 22:17:37.301249 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3244 22:17:37.308175 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3245 22:17:37.311209 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3246 22:17:37.314414 1 0 24 | B1->B0 | 2525 3434 | 0 0 | (0 0) (1 1)
3247 22:17:37.320998 1 0 28 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
3248 22:17:37.324772 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3249 22:17:37.327665 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3250 22:17:37.334068 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3251 22:17:37.337767 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3252 22:17:37.340796 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3253 22:17:37.347433 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3254 22:17:37.351522 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3255 22:17:37.354259 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3256 22:17:37.360869 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3257 22:17:37.364219 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3258 22:17:37.367186 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3259 22:17:37.374581 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3260 22:17:37.377369 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3261 22:17:37.380913 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3262 22:17:37.387498 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3263 22:17:37.390799 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3264 22:17:37.394077 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3265 22:17:37.400740 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3266 22:17:37.403827 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3267 22:17:37.407086 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3268 22:17:37.413928 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3269 22:17:37.417202 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3270 22:17:37.420577 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3271 22:17:37.427833 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3272 22:17:37.430412 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3273 22:17:37.434337 Total UI for P1: 0, mck2ui 16
3274 22:17:37.436975 best dqsien dly found for B0: ( 1, 3, 26)
3275 22:17:37.440717 Total UI for P1: 0, mck2ui 16
3276 22:17:37.443557 best dqsien dly found for B1: ( 1, 3, 28)
3277 22:17:37.447208 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3278 22:17:37.451208 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3279 22:17:37.451313
3280 22:17:37.453727 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3281 22:17:37.457651 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3282 22:17:37.460427 [Gating] SW calibration Done
3283 22:17:37.460566 ==
3284 22:17:37.463604 Dram Type= 6, Freq= 0, CH_1, rank 0
3285 22:17:37.467246 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3286 22:17:37.467328 ==
3287 22:17:37.470261 RX Vref Scan: 0
3288 22:17:37.470341
3289 22:17:37.473386 RX Vref 0 -> 0, step: 1
3290 22:17:37.473466
3291 22:17:37.473530 RX Delay -40 -> 252, step: 8
3292 22:17:37.479886 iDelay=208, Bit 0, Center 123 (48 ~ 199) 152
3293 22:17:37.483368 iDelay=208, Bit 1, Center 111 (40 ~ 183) 144
3294 22:17:37.486608 iDelay=208, Bit 2, Center 111 (40 ~ 183) 144
3295 22:17:37.490066 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3296 22:17:37.497426 iDelay=208, Bit 4, Center 111 (40 ~ 183) 144
3297 22:17:37.500015 iDelay=208, Bit 5, Center 131 (56 ~ 207) 152
3298 22:17:37.503331 iDelay=208, Bit 6, Center 127 (56 ~ 199) 144
3299 22:17:37.506434 iDelay=208, Bit 7, Center 115 (48 ~ 183) 136
3300 22:17:37.509912 iDelay=208, Bit 8, Center 95 (24 ~ 167) 144
3301 22:17:37.512995 iDelay=208, Bit 9, Center 99 (24 ~ 175) 152
3302 22:17:37.519613 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3303 22:17:37.523114 iDelay=208, Bit 11, Center 95 (24 ~ 167) 144
3304 22:17:37.526159 iDelay=208, Bit 12, Center 115 (40 ~ 191) 152
3305 22:17:37.529923 iDelay=208, Bit 13, Center 115 (40 ~ 191) 152
3306 22:17:37.536482 iDelay=208, Bit 14, Center 115 (40 ~ 191) 152
3307 22:17:37.539654 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3308 22:17:37.539735 ==
3309 22:17:37.543127 Dram Type= 6, Freq= 0, CH_1, rank 0
3310 22:17:37.546282 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3311 22:17:37.546364 ==
3312 22:17:37.549586 DQS Delay:
3313 22:17:37.549667 DQS0 = 0, DQS1 = 0
3314 22:17:37.549731 DQM Delay:
3315 22:17:37.553176 DQM0 = 118, DQM1 = 108
3316 22:17:37.553283 DQ Delay:
3317 22:17:37.556549 DQ0 =123, DQ1 =111, DQ2 =111, DQ3 =115
3318 22:17:37.559659 DQ4 =111, DQ5 =131, DQ6 =127, DQ7 =115
3319 22:17:37.562991 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =95
3320 22:17:37.566384 DQ12 =115, DQ13 =115, DQ14 =115, DQ15 =119
3321 22:17:37.569563
3322 22:17:37.569642
3323 22:17:37.569705 ==
3324 22:17:37.572869 Dram Type= 6, Freq= 0, CH_1, rank 0
3325 22:17:37.576614 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3326 22:17:37.576695 ==
3327 22:17:37.576759
3328 22:17:37.576818
3329 22:17:37.579773 TX Vref Scan disable
3330 22:17:37.579853 == TX Byte 0 ==
3331 22:17:37.585963 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3332 22:17:37.589327 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3333 22:17:37.589408 == TX Byte 1 ==
3334 22:17:37.595996 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3335 22:17:37.599954 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3336 22:17:37.600036 ==
3337 22:17:37.602757 Dram Type= 6, Freq= 0, CH_1, rank 0
3338 22:17:37.606215 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3339 22:17:37.606322 ==
3340 22:17:37.618075 TX Vref=22, minBit 10, minWin=25, winSum=421
3341 22:17:37.621694 TX Vref=24, minBit 8, minWin=26, winSum=427
3342 22:17:37.624732 TX Vref=26, minBit 9, minWin=25, winSum=431
3343 22:17:37.628115 TX Vref=28, minBit 10, minWin=26, winSum=437
3344 22:17:37.631681 TX Vref=30, minBit 9, minWin=26, winSum=430
3345 22:17:37.638320 TX Vref=32, minBit 9, minWin=26, winSum=431
3346 22:17:37.641745 [TxChooseVref] Worse bit 10, Min win 26, Win sum 437, Final Vref 28
3347 22:17:37.641828
3348 22:17:37.645612 Final TX Range 1 Vref 28
3349 22:17:37.645693
3350 22:17:37.645755 ==
3351 22:17:37.648188 Dram Type= 6, Freq= 0, CH_1, rank 0
3352 22:17:37.651610 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3353 22:17:37.654736 ==
3354 22:17:37.654816
3355 22:17:37.654880
3356 22:17:37.654938 TX Vref Scan disable
3357 22:17:37.658334 == TX Byte 0 ==
3358 22:17:37.661552 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3359 22:17:37.668200 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3360 22:17:37.668279 == TX Byte 1 ==
3361 22:17:37.671366 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3362 22:17:37.677837 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3363 22:17:37.677917
3364 22:17:37.677978 [DATLAT]
3365 22:17:37.678035 Freq=1200, CH1 RK0
3366 22:17:37.678091
3367 22:17:37.681155 DATLAT Default: 0xd
3368 22:17:37.684871 0, 0xFFFF, sum = 0
3369 22:17:37.684952 1, 0xFFFF, sum = 0
3370 22:17:37.688093 2, 0xFFFF, sum = 0
3371 22:17:37.688174 3, 0xFFFF, sum = 0
3372 22:17:37.691177 4, 0xFFFF, sum = 0
3373 22:17:37.691257 5, 0xFFFF, sum = 0
3374 22:17:37.694602 6, 0xFFFF, sum = 0
3375 22:17:37.694682 7, 0xFFFF, sum = 0
3376 22:17:37.697886 8, 0xFFFF, sum = 0
3377 22:17:37.697966 9, 0xFFFF, sum = 0
3378 22:17:37.701759 10, 0xFFFF, sum = 0
3379 22:17:37.701840 11, 0xFFFF, sum = 0
3380 22:17:37.704279 12, 0x0, sum = 1
3381 22:17:37.704359 13, 0x0, sum = 2
3382 22:17:37.707818 14, 0x0, sum = 3
3383 22:17:37.707898 15, 0x0, sum = 4
3384 22:17:37.711154 best_step = 13
3385 22:17:37.711233
3386 22:17:37.711294 ==
3387 22:17:37.714463 Dram Type= 6, Freq= 0, CH_1, rank 0
3388 22:17:37.717912 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3389 22:17:37.717992 ==
3390 22:17:37.718053 RX Vref Scan: 1
3391 22:17:37.718111
3392 22:17:37.721397 Set Vref Range= 32 -> 127
3393 22:17:37.721475
3394 22:17:37.724568 RX Vref 32 -> 127, step: 1
3395 22:17:37.724647
3396 22:17:37.727944 RX Delay -21 -> 252, step: 4
3397 22:17:37.728023
3398 22:17:37.731281 Set Vref, RX VrefLevel [Byte0]: 32
3399 22:17:37.734422 [Byte1]: 32
3400 22:17:37.734500
3401 22:17:37.737676 Set Vref, RX VrefLevel [Byte0]: 33
3402 22:17:37.741151 [Byte1]: 33
3403 22:17:37.744832
3404 22:17:37.747815 Set Vref, RX VrefLevel [Byte0]: 34
3405 22:17:37.751259 [Byte1]: 34
3406 22:17:37.751339
3407 22:17:37.754751 Set Vref, RX VrefLevel [Byte0]: 35
3408 22:17:37.757494 [Byte1]: 35
3409 22:17:37.757578
3410 22:17:37.761010 Set Vref, RX VrefLevel [Byte0]: 36
3411 22:17:37.764502 [Byte1]: 36
3412 22:17:37.768380
3413 22:17:37.768458 Set Vref, RX VrefLevel [Byte0]: 37
3414 22:17:37.771932 [Byte1]: 37
3415 22:17:37.776647
3416 22:17:37.776725 Set Vref, RX VrefLevel [Byte0]: 38
3417 22:17:37.779713 [Byte1]: 38
3418 22:17:37.784155
3419 22:17:37.784234 Set Vref, RX VrefLevel [Byte0]: 39
3420 22:17:37.788015 [Byte1]: 39
3421 22:17:37.792031
3422 22:17:37.792112 Set Vref, RX VrefLevel [Byte0]: 40
3423 22:17:37.795433 [Byte1]: 40
3424 22:17:37.800507
3425 22:17:37.800609 Set Vref, RX VrefLevel [Byte0]: 41
3426 22:17:37.803525 [Byte1]: 41
3427 22:17:37.808057
3428 22:17:37.808138 Set Vref, RX VrefLevel [Byte0]: 42
3429 22:17:37.814884 [Byte1]: 42
3430 22:17:37.814964
3431 22:17:37.817865 Set Vref, RX VrefLevel [Byte0]: 43
3432 22:17:37.821037 [Byte1]: 43
3433 22:17:37.821119
3434 22:17:37.824447 Set Vref, RX VrefLevel [Byte0]: 44
3435 22:17:37.827577 [Byte1]: 44
3436 22:17:37.832165
3437 22:17:37.832246 Set Vref, RX VrefLevel [Byte0]: 45
3438 22:17:37.834959 [Byte1]: 45
3439 22:17:37.840003
3440 22:17:37.840084 Set Vref, RX VrefLevel [Byte0]: 46
3441 22:17:37.842849 [Byte1]: 46
3442 22:17:37.847810
3443 22:17:37.847890 Set Vref, RX VrefLevel [Byte0]: 47
3444 22:17:37.851218 [Byte1]: 47
3445 22:17:37.855588
3446 22:17:37.855669 Set Vref, RX VrefLevel [Byte0]: 48
3447 22:17:37.858912 [Byte1]: 48
3448 22:17:37.863809
3449 22:17:37.863890 Set Vref, RX VrefLevel [Byte0]: 49
3450 22:17:37.866842 [Byte1]: 49
3451 22:17:37.871540
3452 22:17:37.871620 Set Vref, RX VrefLevel [Byte0]: 50
3453 22:17:37.874980 [Byte1]: 50
3454 22:17:37.879663
3455 22:17:37.879744 Set Vref, RX VrefLevel [Byte0]: 51
3456 22:17:37.882759 [Byte1]: 51
3457 22:17:37.887104
3458 22:17:37.887184 Set Vref, RX VrefLevel [Byte0]: 52
3459 22:17:37.890798 [Byte1]: 52
3460 22:17:37.895202
3461 22:17:37.895283 Set Vref, RX VrefLevel [Byte0]: 53
3462 22:17:37.898819 [Byte1]: 53
3463 22:17:37.903260
3464 22:17:37.903341 Set Vref, RX VrefLevel [Byte0]: 54
3465 22:17:37.906389 [Byte1]: 54
3466 22:17:37.910864
3467 22:17:37.910944 Set Vref, RX VrefLevel [Byte0]: 55
3468 22:17:37.914178 [Byte1]: 55
3469 22:17:37.919319
3470 22:17:37.919413 Set Vref, RX VrefLevel [Byte0]: 56
3471 22:17:37.923013 [Byte1]: 56
3472 22:17:37.927099
3473 22:17:37.927207 Set Vref, RX VrefLevel [Byte0]: 57
3474 22:17:37.930231 [Byte1]: 57
3475 22:17:37.934746
3476 22:17:37.934823 Set Vref, RX VrefLevel [Byte0]: 58
3477 22:17:37.938086 [Byte1]: 58
3478 22:17:37.942664
3479 22:17:37.942765 Set Vref, RX VrefLevel [Byte0]: 59
3480 22:17:37.945760 [Byte1]: 59
3481 22:17:37.951003
3482 22:17:37.951075 Set Vref, RX VrefLevel [Byte0]: 60
3483 22:17:37.954143 [Byte1]: 60
3484 22:17:37.958658
3485 22:17:37.958739 Set Vref, RX VrefLevel [Byte0]: 61
3486 22:17:37.962062 [Byte1]: 61
3487 22:17:37.966582
3488 22:17:37.966662 Set Vref, RX VrefLevel [Byte0]: 62
3489 22:17:37.969653 [Byte1]: 62
3490 22:17:37.974609
3491 22:17:37.974690 Set Vref, RX VrefLevel [Byte0]: 63
3492 22:17:37.977901 [Byte1]: 63
3493 22:17:37.982152
3494 22:17:37.982235 Set Vref, RX VrefLevel [Byte0]: 64
3495 22:17:37.985530 [Byte1]: 64
3496 22:17:37.990303
3497 22:17:37.990383 Set Vref, RX VrefLevel [Byte0]: 65
3498 22:17:37.993551 [Byte1]: 65
3499 22:17:37.998321
3500 22:17:37.998402 Set Vref, RX VrefLevel [Byte0]: 66
3501 22:17:38.001972 [Byte1]: 66
3502 22:17:38.006241
3503 22:17:38.006322 Set Vref, RX VrefLevel [Byte0]: 67
3504 22:17:38.012327 [Byte1]: 67
3505 22:17:38.012408
3506 22:17:38.015755 Set Vref, RX VrefLevel [Byte0]: 68
3507 22:17:38.019066 [Byte1]: 68
3508 22:17:38.019148
3509 22:17:38.022643 Final RX Vref Byte 0 = 53 to rank0
3510 22:17:38.025821 Final RX Vref Byte 1 = 51 to rank0
3511 22:17:38.029203 Final RX Vref Byte 0 = 53 to rank1
3512 22:17:38.032527 Final RX Vref Byte 1 = 51 to rank1==
3513 22:17:38.036106 Dram Type= 6, Freq= 0, CH_1, rank 0
3514 22:17:38.038782 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3515 22:17:38.038879 ==
3516 22:17:38.042198 DQS Delay:
3517 22:17:38.042270 DQS0 = 0, DQS1 = 0
3518 22:17:38.045962 DQM Delay:
3519 22:17:38.046057 DQM0 = 116, DQM1 = 109
3520 22:17:38.048806 DQ Delay:
3521 22:17:38.052158 DQ0 =120, DQ1 =110, DQ2 =110, DQ3 =114
3522 22:17:38.055356 DQ4 =114, DQ5 =128, DQ6 =124, DQ7 =112
3523 22:17:38.058587 DQ8 =96, DQ9 =102, DQ10 =110, DQ11 =98
3524 22:17:38.062331 DQ12 =118, DQ13 =114, DQ14 =118, DQ15 =118
3525 22:17:38.062425
3526 22:17:38.062510
3527 22:17:38.068795 [DQSOSCAuto] RK0, (LSB)MR18= 0x1f5, (MSB)MR19= 0x403, tDQSOscB0 = 414 ps tDQSOscB1 = 409 ps
3528 22:17:38.072896 CH1 RK0: MR19=403, MR18=1F5
3529 22:17:38.078779 CH1_RK0: MR19=0x403, MR18=0x1F5, DQSOSC=409, MR23=63, INC=39, DEC=26
3530 22:17:38.078875
3531 22:17:38.082079 ----->DramcWriteLeveling(PI) begin...
3532 22:17:38.082148 ==
3533 22:17:38.085091 Dram Type= 6, Freq= 0, CH_1, rank 1
3534 22:17:38.088600 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3535 22:17:38.088667 ==
3536 22:17:38.092078 Write leveling (Byte 0): 23 => 23
3537 22:17:38.095598 Write leveling (Byte 1): 27 => 27
3538 22:17:38.099010 DramcWriteLeveling(PI) end<-----
3539 22:17:38.099080
3540 22:17:38.099139 ==
3541 22:17:38.102402 Dram Type= 6, Freq= 0, CH_1, rank 1
3542 22:17:38.104972 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3543 22:17:38.108772 ==
3544 22:17:38.108869 [Gating] SW mode calibration
3545 22:17:38.118355 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3546 22:17:38.121630 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3547 22:17:38.124908 0 15 0 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
3548 22:17:38.131651 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3549 22:17:38.134883 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3550 22:17:38.138104 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3551 22:17:38.144988 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3552 22:17:38.148079 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3553 22:17:38.151235 0 15 24 | B1->B0 | 2e2e 3434 | 1 1 | (0 0) (1 0)
3554 22:17:38.157811 0 15 28 | B1->B0 | 2323 2626 | 0 0 | (0 0) (1 0)
3555 22:17:38.161355 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3556 22:17:38.164619 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3557 22:17:38.170827 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3558 22:17:38.174601 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3559 22:17:38.177329 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3560 22:17:38.184259 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3561 22:17:38.187579 1 0 24 | B1->B0 | 3d3d 2e2e | 0 0 | (0 0) (0 0)
3562 22:17:38.191029 1 0 28 | B1->B0 | 4646 4343 | 0 1 | (0 0) (0 0)
3563 22:17:38.197566 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3564 22:17:38.200497 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3565 22:17:38.203817 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3566 22:17:38.210537 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3567 22:17:38.214013 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3568 22:17:38.217294 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3569 22:17:38.223558 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3570 22:17:38.227380 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3571 22:17:38.230119 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3572 22:17:38.236779 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3573 22:17:38.240068 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3574 22:17:38.243709 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3575 22:17:38.250160 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3576 22:17:38.253645 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3577 22:17:38.256858 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3578 22:17:38.263839 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3579 22:17:38.266749 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3580 22:17:38.270081 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3581 22:17:38.276626 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3582 22:17:38.279810 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3583 22:17:38.286028 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3584 22:17:38.289474 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3585 22:17:38.293071 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3586 22:17:38.299421 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3587 22:17:38.302721 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3588 22:17:38.306547 Total UI for P1: 0, mck2ui 16
3589 22:17:38.309303 best dqsien dly found for B0: ( 1, 3, 28)
3590 22:17:38.313155 Total UI for P1: 0, mck2ui 16
3591 22:17:38.315840 best dqsien dly found for B1: ( 1, 3, 26)
3592 22:17:38.319249 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3593 22:17:38.322541 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3594 22:17:38.322621
3595 22:17:38.325648 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3596 22:17:38.328882 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3597 22:17:38.332395 [Gating] SW calibration Done
3598 22:17:38.332523 ==
3599 22:17:38.335593 Dram Type= 6, Freq= 0, CH_1, rank 1
3600 22:17:38.339000 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3601 22:17:38.339082 ==
3602 22:17:38.342375 RX Vref Scan: 0
3603 22:17:38.342456
3604 22:17:38.345547 RX Vref 0 -> 0, step: 1
3605 22:17:38.345629
3606 22:17:38.345692 RX Delay -40 -> 252, step: 8
3607 22:17:38.352495 iDelay=208, Bit 0, Center 119 (48 ~ 191) 144
3608 22:17:38.355303 iDelay=208, Bit 1, Center 111 (40 ~ 183) 144
3609 22:17:38.358840 iDelay=208, Bit 2, Center 103 (32 ~ 175) 144
3610 22:17:38.362444 iDelay=208, Bit 3, Center 111 (40 ~ 183) 144
3611 22:17:38.369105 iDelay=208, Bit 4, Center 115 (40 ~ 191) 152
3612 22:17:38.372683 iDelay=208, Bit 5, Center 123 (48 ~ 199) 152
3613 22:17:38.375252 iDelay=208, Bit 6, Center 131 (56 ~ 207) 152
3614 22:17:38.378794 iDelay=208, Bit 7, Center 115 (40 ~ 191) 152
3615 22:17:38.382144 iDelay=208, Bit 8, Center 95 (24 ~ 167) 144
3616 22:17:38.385198 iDelay=208, Bit 9, Center 95 (24 ~ 167) 144
3617 22:17:38.391694 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3618 22:17:38.395386 iDelay=208, Bit 11, Center 103 (32 ~ 175) 144
3619 22:17:38.398721 iDelay=208, Bit 12, Center 119 (48 ~ 191) 144
3620 22:17:38.401558 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3621 22:17:38.409177 iDelay=208, Bit 14, Center 115 (40 ~ 191) 152
3622 22:17:38.411311 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3623 22:17:38.411392 ==
3624 22:17:38.415078 Dram Type= 6, Freq= 0, CH_1, rank 1
3625 22:17:38.418007 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3626 22:17:38.418089 ==
3627 22:17:38.421381 DQS Delay:
3628 22:17:38.421462 DQS0 = 0, DQS1 = 0
3629 22:17:38.421526 DQM Delay:
3630 22:17:38.424529 DQM0 = 116, DQM1 = 109
3631 22:17:38.424611 DQ Delay:
3632 22:17:38.428279 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =111
3633 22:17:38.431188 DQ4 =115, DQ5 =123, DQ6 =131, DQ7 =115
3634 22:17:38.434626 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =103
3635 22:17:38.440979 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119
3636 22:17:38.441061
3637 22:17:38.441124
3638 22:17:38.441181 ==
3639 22:17:38.445214 Dram Type= 6, Freq= 0, CH_1, rank 1
3640 22:17:38.447773 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3641 22:17:38.447856 ==
3642 22:17:38.447920
3643 22:17:38.447977
3644 22:17:38.450916 TX Vref Scan disable
3645 22:17:38.454366 == TX Byte 0 ==
3646 22:17:38.457780 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3647 22:17:38.461723 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3648 22:17:38.465034 == TX Byte 1 ==
3649 22:17:38.467693 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3650 22:17:38.470940 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3651 22:17:38.471022 ==
3652 22:17:38.474218 Dram Type= 6, Freq= 0, CH_1, rank 1
3653 22:17:38.477960 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3654 22:17:38.478041 ==
3655 22:17:38.490860 TX Vref=22, minBit 3, minWin=26, winSum=429
3656 22:17:38.494359 TX Vref=24, minBit 9, minWin=25, winSum=430
3657 22:17:38.497203 TX Vref=26, minBit 9, minWin=26, winSum=434
3658 22:17:38.500853 TX Vref=28, minBit 9, minWin=26, winSum=435
3659 22:17:38.504182 TX Vref=30, minBit 10, minWin=26, winSum=437
3660 22:17:38.511168 TX Vref=32, minBit 8, minWin=26, winSum=435
3661 22:17:38.513651 [TxChooseVref] Worse bit 10, Min win 26, Win sum 437, Final Vref 30
3662 22:17:38.513732
3663 22:17:38.516922 Final TX Range 1 Vref 30
3664 22:17:38.517003
3665 22:17:38.517067 ==
3666 22:17:38.520463 Dram Type= 6, Freq= 0, CH_1, rank 1
3667 22:17:38.523622 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3668 22:17:38.527115 ==
3669 22:17:38.527195
3670 22:17:38.527258
3671 22:17:38.527316 TX Vref Scan disable
3672 22:17:38.530599 == TX Byte 0 ==
3673 22:17:38.533751 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3674 22:17:38.540493 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3675 22:17:38.540604 == TX Byte 1 ==
3676 22:17:38.543793 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3677 22:17:38.550421 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3678 22:17:38.550504
3679 22:17:38.550568 [DATLAT]
3680 22:17:38.550626 Freq=1200, CH1 RK1
3681 22:17:38.550684
3682 22:17:38.553714 DATLAT Default: 0xd
3683 22:17:38.553795 0, 0xFFFF, sum = 0
3684 22:17:38.556817 1, 0xFFFF, sum = 0
3685 22:17:38.560220 2, 0xFFFF, sum = 0
3686 22:17:38.560301 3, 0xFFFF, sum = 0
3687 22:17:38.564305 4, 0xFFFF, sum = 0
3688 22:17:38.564388 5, 0xFFFF, sum = 0
3689 22:17:38.567138 6, 0xFFFF, sum = 0
3690 22:17:38.567220 7, 0xFFFF, sum = 0
3691 22:17:38.570711 8, 0xFFFF, sum = 0
3692 22:17:38.570793 9, 0xFFFF, sum = 0
3693 22:17:38.573898 10, 0xFFFF, sum = 0
3694 22:17:38.573980 11, 0xFFFF, sum = 0
3695 22:17:38.576898 12, 0x0, sum = 1
3696 22:17:38.576980 13, 0x0, sum = 2
3697 22:17:38.580333 14, 0x0, sum = 3
3698 22:17:38.580416 15, 0x0, sum = 4
3699 22:17:38.583313 best_step = 13
3700 22:17:38.583394
3701 22:17:38.583457 ==
3702 22:17:38.586582 Dram Type= 6, Freq= 0, CH_1, rank 1
3703 22:17:38.590364 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3704 22:17:38.590446 ==
3705 22:17:38.593620 RX Vref Scan: 0
3706 22:17:38.593701
3707 22:17:38.593764 RX Vref 0 -> 0, step: 1
3708 22:17:38.593823
3709 22:17:38.596722 RX Delay -21 -> 252, step: 4
3710 22:17:38.603323 iDelay=199, Bit 0, Center 120 (51 ~ 190) 140
3711 22:17:38.606848 iDelay=199, Bit 1, Center 110 (43 ~ 178) 136
3712 22:17:38.610034 iDelay=199, Bit 2, Center 108 (43 ~ 174) 132
3713 22:17:38.612915 iDelay=199, Bit 3, Center 112 (47 ~ 178) 132
3714 22:17:38.616347 iDelay=199, Bit 4, Center 116 (47 ~ 186) 140
3715 22:17:38.622827 iDelay=199, Bit 5, Center 126 (59 ~ 194) 136
3716 22:17:38.626446 iDelay=199, Bit 6, Center 128 (59 ~ 198) 140
3717 22:17:38.629523 iDelay=199, Bit 7, Center 116 (51 ~ 182) 132
3718 22:17:38.632781 iDelay=199, Bit 8, Center 96 (31 ~ 162) 132
3719 22:17:38.635956 iDelay=199, Bit 9, Center 100 (35 ~ 166) 132
3720 22:17:38.642870 iDelay=199, Bit 10, Center 110 (43 ~ 178) 136
3721 22:17:38.646099 iDelay=199, Bit 11, Center 98 (31 ~ 166) 136
3722 22:17:38.649058 iDelay=199, Bit 12, Center 118 (51 ~ 186) 136
3723 22:17:38.652656 iDelay=199, Bit 13, Center 118 (51 ~ 186) 136
3724 22:17:38.655915 iDelay=199, Bit 14, Center 116 (51 ~ 182) 132
3725 22:17:38.663062 iDelay=199, Bit 15, Center 118 (51 ~ 186) 136
3726 22:17:38.663143 ==
3727 22:17:38.666091 Dram Type= 6, Freq= 0, CH_1, rank 1
3728 22:17:38.669034 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3729 22:17:38.669116 ==
3730 22:17:38.669179 DQS Delay:
3731 22:17:38.672347 DQS0 = 0, DQS1 = 0
3732 22:17:38.672427 DQM Delay:
3733 22:17:38.676254 DQM0 = 117, DQM1 = 109
3734 22:17:38.676335 DQ Delay:
3735 22:17:38.679018 DQ0 =120, DQ1 =110, DQ2 =108, DQ3 =112
3736 22:17:38.682399 DQ4 =116, DQ5 =126, DQ6 =128, DQ7 =116
3737 22:17:38.685685 DQ8 =96, DQ9 =100, DQ10 =110, DQ11 =98
3738 22:17:38.692270 DQ12 =118, DQ13 =118, DQ14 =116, DQ15 =118
3739 22:17:38.692351
3740 22:17:38.692414
3741 22:17:38.699201 [DQSOSCAuto] RK1, (LSB)MR18= 0xf7f1, (MSB)MR19= 0x303, tDQSOscB0 = 416 ps tDQSOscB1 = 413 ps
3742 22:17:38.702103 CH1 RK1: MR19=303, MR18=F7F1
3743 22:17:38.709090 CH1_RK1: MR19=0x303, MR18=0xF7F1, DQSOSC=413, MR23=63, INC=38, DEC=25
3744 22:17:38.711899 [RxdqsGatingPostProcess] freq 1200
3745 22:17:38.715403 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3746 22:17:38.719043 best DQS0 dly(2T, 0.5T) = (0, 11)
3747 22:17:38.721778 best DQS1 dly(2T, 0.5T) = (0, 11)
3748 22:17:38.725175 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3749 22:17:38.728777 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3750 22:17:38.732692 best DQS0 dly(2T, 0.5T) = (0, 11)
3751 22:17:38.735045 best DQS1 dly(2T, 0.5T) = (0, 11)
3752 22:17:38.738629 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3753 22:17:38.741861 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3754 22:17:38.745124 Pre-setting of DQS Precalculation
3755 22:17:38.748696 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3756 22:17:38.758377 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3757 22:17:38.764979 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3758 22:17:38.765067
3759 22:17:38.765151
3760 22:17:38.769043 [Calibration Summary] 2400 Mbps
3761 22:17:38.769127 CH 0, Rank 0
3762 22:17:38.771350 SW Impedance : PASS
3763 22:17:38.771447 DUTY Scan : NO K
3764 22:17:38.774735 ZQ Calibration : PASS
3765 22:17:38.778650 Jitter Meter : NO K
3766 22:17:38.778735 CBT Training : PASS
3767 22:17:38.781899 Write leveling : PASS
3768 22:17:38.784858 RX DQS gating : PASS
3769 22:17:38.784946 RX DQ/DQS(RDDQC) : PASS
3770 22:17:38.788137 TX DQ/DQS : PASS
3771 22:17:38.791578 RX DATLAT : PASS
3772 22:17:38.791654 RX DQ/DQS(Engine): PASS
3773 22:17:38.794693 TX OE : NO K
3774 22:17:38.794773 All Pass.
3775 22:17:38.794852
3776 22:17:38.798026 CH 0, Rank 1
3777 22:17:38.798100 SW Impedance : PASS
3778 22:17:38.801278 DUTY Scan : NO K
3779 22:17:38.804496 ZQ Calibration : PASS
3780 22:17:38.804632 Jitter Meter : NO K
3781 22:17:38.808340 CBT Training : PASS
3782 22:17:38.811177 Write leveling : PASS
3783 22:17:38.811257 RX DQS gating : PASS
3784 22:17:38.814687 RX DQ/DQS(RDDQC) : PASS
3785 22:17:38.814760 TX DQ/DQS : PASS
3786 22:17:38.817902 RX DATLAT : PASS
3787 22:17:38.821310 RX DQ/DQS(Engine): PASS
3788 22:17:38.821383 TX OE : NO K
3789 22:17:38.824717 All Pass.
3790 22:17:38.824793
3791 22:17:38.824871 CH 1, Rank 0
3792 22:17:38.827420 SW Impedance : PASS
3793 22:17:38.827491 DUTY Scan : NO K
3794 22:17:38.830968 ZQ Calibration : PASS
3795 22:17:38.834003 Jitter Meter : NO K
3796 22:17:38.834079 CBT Training : PASS
3797 22:17:38.837632 Write leveling : PASS
3798 22:17:38.840971 RX DQS gating : PASS
3799 22:17:38.841051 RX DQ/DQS(RDDQC) : PASS
3800 22:17:38.843955 TX DQ/DQS : PASS
3801 22:17:38.847406 RX DATLAT : PASS
3802 22:17:38.847485 RX DQ/DQS(Engine): PASS
3803 22:17:38.850749 TX OE : NO K
3804 22:17:38.850825 All Pass.
3805 22:17:38.850904
3806 22:17:38.854040 CH 1, Rank 1
3807 22:17:38.854113 SW Impedance : PASS
3808 22:17:38.857081 DUTY Scan : NO K
3809 22:17:38.860817 ZQ Calibration : PASS
3810 22:17:38.860903 Jitter Meter : NO K
3811 22:17:38.864144 CBT Training : PASS
3812 22:17:38.867112 Write leveling : PASS
3813 22:17:38.867186 RX DQS gating : PASS
3814 22:17:38.870183 RX DQ/DQS(RDDQC) : PASS
3815 22:17:38.874022 TX DQ/DQS : PASS
3816 22:17:38.874098 RX DATLAT : PASS
3817 22:17:38.876829 RX DQ/DQS(Engine): PASS
3818 22:17:38.880196 TX OE : NO K
3819 22:17:38.880302 All Pass.
3820 22:17:38.880403
3821 22:17:38.880497 DramC Write-DBI off
3822 22:17:38.883498 PER_BANK_REFRESH: Hybrid Mode
3823 22:17:38.886878 TX_TRACKING: ON
3824 22:17:38.893550 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3825 22:17:38.900098 [FAST_K] Save calibration result to emmc
3826 22:17:38.903494 dramc_set_vcore_voltage set vcore to 650000
3827 22:17:38.903572 Read voltage for 600, 5
3828 22:17:38.906317 Vio18 = 0
3829 22:17:38.906391 Vcore = 650000
3830 22:17:38.906477 Vdram = 0
3831 22:17:38.909769 Vddq = 0
3832 22:17:38.909843 Vmddr = 0
3833 22:17:38.913171 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3834 22:17:38.919840 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3835 22:17:38.922944 MEM_TYPE=3, freq_sel=19
3836 22:17:38.926574 sv_algorithm_assistance_LP4_1600
3837 22:17:38.929509 ============ PULL DRAM RESETB DOWN ============
3838 22:17:38.933056 ========== PULL DRAM RESETB DOWN end =========
3839 22:17:38.939673 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3840 22:17:38.943285 ===================================
3841 22:17:38.943360 LPDDR4 DRAM CONFIGURATION
3842 22:17:38.946357 ===================================
3843 22:17:38.949737 EX_ROW_EN[0] = 0x0
3844 22:17:38.949816 EX_ROW_EN[1] = 0x0
3845 22:17:38.952977 LP4Y_EN = 0x0
3846 22:17:38.953055 WORK_FSP = 0x0
3847 22:17:38.956321 WL = 0x2
3848 22:17:38.959476 RL = 0x2
3849 22:17:38.959549 BL = 0x2
3850 22:17:38.962908 RPST = 0x0
3851 22:17:38.962981 RD_PRE = 0x0
3852 22:17:38.965781 WR_PRE = 0x1
3853 22:17:38.965856 WR_PST = 0x0
3854 22:17:38.969217 DBI_WR = 0x0
3855 22:17:38.969293 DBI_RD = 0x0
3856 22:17:38.972221 OTF = 0x1
3857 22:17:38.976011 ===================================
3858 22:17:38.979124 ===================================
3859 22:17:38.979222 ANA top config
3860 22:17:38.982242 ===================================
3861 22:17:38.985535 DLL_ASYNC_EN = 0
3862 22:17:38.988680 ALL_SLAVE_EN = 1
3863 22:17:38.992301 NEW_RANK_MODE = 1
3864 22:17:38.992389 DLL_IDLE_MODE = 1
3865 22:17:38.995531 LP45_APHY_COMB_EN = 1
3866 22:17:38.999358 TX_ODT_DIS = 1
3867 22:17:39.002174 NEW_8X_MODE = 1
3868 22:17:39.005563 ===================================
3869 22:17:39.008611 ===================================
3870 22:17:39.012356 data_rate = 1200
3871 22:17:39.012455 CKR = 1
3872 22:17:39.015173 DQ_P2S_RATIO = 8
3873 22:17:39.018636 ===================================
3874 22:17:39.022696 CA_P2S_RATIO = 8
3875 22:17:39.025223 DQ_CA_OPEN = 0
3876 22:17:39.028734 DQ_SEMI_OPEN = 0
3877 22:17:39.031763 CA_SEMI_OPEN = 0
3878 22:17:39.031859 CA_FULL_RATE = 0
3879 22:17:39.035156 DQ_CKDIV4_EN = 1
3880 22:17:39.038751 CA_CKDIV4_EN = 1
3881 22:17:39.042067 CA_PREDIV_EN = 0
3882 22:17:39.045349 PH8_DLY = 0
3883 22:17:39.048645 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3884 22:17:39.048724 DQ_AAMCK_DIV = 4
3885 22:17:39.051874 CA_AAMCK_DIV = 4
3886 22:17:39.055079 CA_ADMCK_DIV = 4
3887 22:17:39.058111 DQ_TRACK_CA_EN = 0
3888 22:17:39.061727 CA_PICK = 600
3889 22:17:39.064577 CA_MCKIO = 600
3890 22:17:39.067835 MCKIO_SEMI = 0
3891 22:17:39.067921 PLL_FREQ = 2288
3892 22:17:39.071374 DQ_UI_PI_RATIO = 32
3893 22:17:39.074375 CA_UI_PI_RATIO = 0
3894 22:17:39.078178 ===================================
3895 22:17:39.081586 ===================================
3896 22:17:39.084640 memory_type:LPDDR4
3897 22:17:39.088129 GP_NUM : 10
3898 22:17:39.088201 SRAM_EN : 1
3899 22:17:39.091463 MD32_EN : 0
3900 22:17:39.094549 ===================================
3901 22:17:39.094649 [ANA_INIT] >>>>>>>>>>>>>>
3902 22:17:39.098103 <<<<<< [CONFIGURE PHASE]: ANA_TX
3903 22:17:39.101543 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3904 22:17:39.104406 ===================================
3905 22:17:39.107871 data_rate = 1200,PCW = 0X5800
3906 22:17:39.110892 ===================================
3907 22:17:39.114109 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3908 22:17:39.120686 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3909 22:17:39.127447 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3910 22:17:39.130911 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3911 22:17:39.134063 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3912 22:17:39.137594 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3913 22:17:39.140936 [ANA_INIT] flow start
3914 22:17:39.141010 [ANA_INIT] PLL >>>>>>>>
3915 22:17:39.143872 [ANA_INIT] PLL <<<<<<<<
3916 22:17:39.147317 [ANA_INIT] MIDPI >>>>>>>>
3917 22:17:39.147393 [ANA_INIT] MIDPI <<<<<<<<
3918 22:17:39.150390 [ANA_INIT] DLL >>>>>>>>
3919 22:17:39.153977 [ANA_INIT] flow end
3920 22:17:39.157318 ============ LP4 DIFF to SE enter ============
3921 22:17:39.160304 ============ LP4 DIFF to SE exit ============
3922 22:17:39.164049 [ANA_INIT] <<<<<<<<<<<<<
3923 22:17:39.167014 [Flow] Enable top DCM control >>>>>
3924 22:17:39.170859 [Flow] Enable top DCM control <<<<<
3925 22:17:39.173565 Enable DLL master slave shuffle
3926 22:17:39.177167 ==============================================================
3927 22:17:39.180406 Gating Mode config
3928 22:17:39.186865 ==============================================================
3929 22:17:39.186939 Config description:
3930 22:17:39.196751 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3931 22:17:39.203582 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3932 22:17:39.210019 SELPH_MODE 0: By rank 1: By Phase
3933 22:17:39.213645 ==============================================================
3934 22:17:39.216798 GAT_TRACK_EN = 1
3935 22:17:39.220238 RX_GATING_MODE = 2
3936 22:17:39.223395 RX_GATING_TRACK_MODE = 2
3937 22:17:39.226627 SELPH_MODE = 1
3938 22:17:39.230005 PICG_EARLY_EN = 1
3939 22:17:39.233415 VALID_LAT_VALUE = 1
3940 22:17:39.239501 ==============================================================
3941 22:17:39.242772 Enter into Gating configuration >>>>
3942 22:17:39.246138 Exit from Gating configuration <<<<
3943 22:17:39.246223 Enter into DVFS_PRE_config >>>>>
3944 22:17:39.259600 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3945 22:17:39.262595 Exit from DVFS_PRE_config <<<<<
3946 22:17:39.266170 Enter into PICG configuration >>>>
3947 22:17:39.269459 Exit from PICG configuration <<<<
3948 22:17:39.272305 [RX_INPUT] configuration >>>>>
3949 22:17:39.272386 [RX_INPUT] configuration <<<<<
3950 22:17:39.279028 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3951 22:17:39.286004 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3952 22:17:39.288811 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3953 22:17:39.295691 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3954 22:17:39.302472 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3955 22:17:39.308915 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3956 22:17:39.312341 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3957 22:17:39.315507 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3958 22:17:39.321976 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3959 22:17:39.325436 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3960 22:17:39.328675 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3961 22:17:39.335149 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3962 22:17:39.338349 ===================================
3963 22:17:39.338425 LPDDR4 DRAM CONFIGURATION
3964 22:17:39.341627 ===================================
3965 22:17:39.345149 EX_ROW_EN[0] = 0x0
3966 22:17:39.348927 EX_ROW_EN[1] = 0x0
3967 22:17:39.349015 LP4Y_EN = 0x0
3968 22:17:39.352211 WORK_FSP = 0x0
3969 22:17:39.352289 WL = 0x2
3970 22:17:39.355186 RL = 0x2
3971 22:17:39.355260 BL = 0x2
3972 22:17:39.358846 RPST = 0x0
3973 22:17:39.358918 RD_PRE = 0x0
3974 22:17:39.361702 WR_PRE = 0x1
3975 22:17:39.361776 WR_PST = 0x0
3976 22:17:39.366050 DBI_WR = 0x0
3977 22:17:39.366121 DBI_RD = 0x0
3978 22:17:39.368341 OTF = 0x1
3979 22:17:39.371854 ===================================
3980 22:17:39.374917 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3981 22:17:39.378817 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3982 22:17:39.385105 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3983 22:17:39.388809 ===================================
3984 22:17:39.388893 LPDDR4 DRAM CONFIGURATION
3985 22:17:39.391606 ===================================
3986 22:17:39.395320 EX_ROW_EN[0] = 0x10
3987 22:17:39.395396 EX_ROW_EN[1] = 0x0
3988 22:17:39.398194 LP4Y_EN = 0x0
3989 22:17:39.401149 WORK_FSP = 0x0
3990 22:17:39.401254 WL = 0x2
3991 22:17:39.404815 RL = 0x2
3992 22:17:39.404890 BL = 0x2
3993 22:17:39.407937 RPST = 0x0
3994 22:17:39.408033 RD_PRE = 0x0
3995 22:17:39.411090 WR_PRE = 0x1
3996 22:17:39.411163 WR_PST = 0x0
3997 22:17:39.414991 DBI_WR = 0x0
3998 22:17:39.415065 DBI_RD = 0x0
3999 22:17:39.417842 OTF = 0x1
4000 22:17:39.421454 ===================================
4001 22:17:39.427691 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
4002 22:17:39.431165 nWR fixed to 30
4003 22:17:39.431248 [ModeRegInit_LP4] CH0 RK0
4004 22:17:39.434634 [ModeRegInit_LP4] CH0 RK1
4005 22:17:39.437441 [ModeRegInit_LP4] CH1 RK0
4006 22:17:39.440986 [ModeRegInit_LP4] CH1 RK1
4007 22:17:39.441092 match AC timing 17
4008 22:17:39.447347 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
4009 22:17:39.450740 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
4010 22:17:39.454085 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
4011 22:17:39.460735 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
4012 22:17:39.464124 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
4013 22:17:39.464197 ==
4014 22:17:39.467165 Dram Type= 6, Freq= 0, CH_0, rank 0
4015 22:17:39.471229 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4016 22:17:39.471299 ==
4017 22:17:39.477486 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4018 22:17:39.483878 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4019 22:17:39.486872 [CA 0] Center 36 (6~66) winsize 61
4020 22:17:39.490581 [CA 1] Center 36 (6~66) winsize 61
4021 22:17:39.494228 [CA 2] Center 34 (4~65) winsize 62
4022 22:17:39.497166 [CA 3] Center 34 (4~65) winsize 62
4023 22:17:39.500308 [CA 4] Center 33 (3~64) winsize 62
4024 22:17:39.504096 [CA 5] Center 33 (3~64) winsize 62
4025 22:17:39.504165
4026 22:17:39.507495 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4027 22:17:39.507563
4028 22:17:39.510259 [CATrainingPosCal] consider 1 rank data
4029 22:17:39.514036 u2DelayCellTimex100 = 270/100 ps
4030 22:17:39.516651 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4031 22:17:39.520333 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4032 22:17:39.523344 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4033 22:17:39.526905 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4034 22:17:39.530848 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4035 22:17:39.536657 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4036 22:17:39.536740
4037 22:17:39.539863 CA PerBit enable=1, Macro0, CA PI delay=33
4038 22:17:39.539946
4039 22:17:39.543084 [CBTSetCACLKResult] CA Dly = 33
4040 22:17:39.543165 CS Dly: 6 (0~37)
4041 22:17:39.543228 ==
4042 22:17:39.546480 Dram Type= 6, Freq= 0, CH_0, rank 1
4043 22:17:39.549707 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4044 22:17:39.553151 ==
4045 22:17:39.556454 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4046 22:17:39.563032 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4047 22:17:39.566953 [CA 0] Center 36 (6~66) winsize 61
4048 22:17:39.570052 [CA 1] Center 36 (6~66) winsize 61
4049 22:17:39.573173 [CA 2] Center 34 (4~64) winsize 61
4050 22:17:39.576813 [CA 3] Center 34 (4~64) winsize 61
4051 22:17:39.579459 [CA 4] Center 33 (3~64) winsize 62
4052 22:17:39.582715 [CA 5] Center 33 (2~64) winsize 63
4053 22:17:39.582797
4054 22:17:39.586298 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4055 22:17:39.586381
4056 22:17:39.589410 [CATrainingPosCal] consider 2 rank data
4057 22:17:39.593161 u2DelayCellTimex100 = 270/100 ps
4058 22:17:39.596507 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4059 22:17:39.599006 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4060 22:17:39.605686 CA2 delay=34 (4~64),Diff = 1 PI (9 cell)
4061 22:17:39.609718 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4062 22:17:39.612455 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4063 22:17:39.616153 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4064 22:17:39.616234
4065 22:17:39.619437 CA PerBit enable=1, Macro0, CA PI delay=33
4066 22:17:39.619535
4067 22:17:39.622450 [CBTSetCACLKResult] CA Dly = 33
4068 22:17:39.622532 CS Dly: 6 (0~37)
4069 22:17:39.622597
4070 22:17:39.625784 ----->DramcWriteLeveling(PI) begin...
4071 22:17:39.628662 ==
4072 22:17:39.632658 Dram Type= 6, Freq= 0, CH_0, rank 0
4073 22:17:39.636013 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4074 22:17:39.636112 ==
4075 22:17:39.638789 Write leveling (Byte 0): 33 => 33
4076 22:17:39.641830 Write leveling (Byte 1): 29 => 29
4077 22:17:39.645027 DramcWriteLeveling(PI) end<-----
4078 22:17:39.645108
4079 22:17:39.645172 ==
4080 22:17:39.648762 Dram Type= 6, Freq= 0, CH_0, rank 0
4081 22:17:39.651641 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4082 22:17:39.651723 ==
4083 22:17:39.655350 [Gating] SW mode calibration
4084 22:17:39.661502 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4085 22:17:39.668175 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4086 22:17:39.671918 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4087 22:17:39.674769 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4088 22:17:39.681504 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4089 22:17:39.684896 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4090 22:17:39.688462 0 9 16 | B1->B0 | 2f2f 2525 | 0 0 | (0 0) (0 0)
4091 22:17:39.694914 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4092 22:17:39.698268 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4093 22:17:39.701290 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4094 22:17:39.707699 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4095 22:17:39.711412 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4096 22:17:39.714651 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4097 22:17:39.721616 0 10 12 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
4098 22:17:39.724928 0 10 16 | B1->B0 | 3737 4040 | 0 0 | (1 1) (0 0)
4099 22:17:39.727936 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4100 22:17:39.734491 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4101 22:17:39.737498 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4102 22:17:39.741186 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4103 22:17:39.747560 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4104 22:17:39.751320 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4105 22:17:39.754364 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4106 22:17:39.761053 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4107 22:17:39.764344 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4108 22:17:39.767784 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4109 22:17:39.774775 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4110 22:17:39.777509 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4111 22:17:39.780639 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4112 22:17:39.787298 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4113 22:17:39.790421 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4114 22:17:39.793928 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4115 22:17:39.801175 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4116 22:17:39.803744 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4117 22:17:39.807101 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4118 22:17:39.813925 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4119 22:17:39.817134 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4120 22:17:39.820116 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4121 22:17:39.827048 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4122 22:17:39.830329 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4123 22:17:39.834090 Total UI for P1: 0, mck2ui 16
4124 22:17:39.836949 best dqsien dly found for B0: ( 0, 13, 12)
4125 22:17:39.840960 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4126 22:17:39.843312 Total UI for P1: 0, mck2ui 16
4127 22:17:39.846723 best dqsien dly found for B1: ( 0, 13, 16)
4128 22:17:39.849898 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4129 22:17:39.853562 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4130 22:17:39.853644
4131 22:17:39.857018 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4132 22:17:39.863993 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4133 22:17:39.864075 [Gating] SW calibration Done
4134 22:17:39.866472 ==
4135 22:17:39.866553 Dram Type= 6, Freq= 0, CH_0, rank 0
4136 22:17:39.873147 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4137 22:17:39.873229 ==
4138 22:17:39.873293 RX Vref Scan: 0
4139 22:17:39.873352
4140 22:17:39.876463 RX Vref 0 -> 0, step: 1
4141 22:17:39.876567
4142 22:17:39.879819 RX Delay -230 -> 252, step: 16
4143 22:17:39.882942 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4144 22:17:39.886566 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4145 22:17:39.893156 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4146 22:17:39.896468 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4147 22:17:39.900045 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4148 22:17:39.902619 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4149 22:17:39.909315 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4150 22:17:39.912779 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4151 22:17:39.915995 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4152 22:17:39.919206 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4153 22:17:39.922803 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4154 22:17:39.929276 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4155 22:17:39.932818 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4156 22:17:39.935858 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4157 22:17:39.939190 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4158 22:17:39.946128 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4159 22:17:39.946208 ==
4160 22:17:39.949298 Dram Type= 6, Freq= 0, CH_0, rank 0
4161 22:17:39.952231 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4162 22:17:39.952334 ==
4163 22:17:39.952435 DQS Delay:
4164 22:17:39.955937 DQS0 = 0, DQS1 = 0
4165 22:17:39.956018 DQM Delay:
4166 22:17:39.959190 DQM0 = 41, DQM1 = 33
4167 22:17:39.959270 DQ Delay:
4168 22:17:39.963318 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =33
4169 22:17:39.965757 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4170 22:17:39.968954 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =33
4171 22:17:39.972244 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =33
4172 22:17:39.972325
4173 22:17:39.972388
4174 22:17:39.972446 ==
4175 22:17:39.975460 Dram Type= 6, Freq= 0, CH_0, rank 0
4176 22:17:39.978724 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4177 22:17:39.982127 ==
4178 22:17:39.982208
4179 22:17:39.982271
4180 22:17:39.982329 TX Vref Scan disable
4181 22:17:39.985427 == TX Byte 0 ==
4182 22:17:39.988777 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4183 22:17:39.995324 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4184 22:17:39.995405 == TX Byte 1 ==
4185 22:17:39.998811 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4186 22:17:40.005346 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4187 22:17:40.005431 ==
4188 22:17:40.008504 Dram Type= 6, Freq= 0, CH_0, rank 0
4189 22:17:40.011838 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4190 22:17:40.011919 ==
4191 22:17:40.011983
4192 22:17:40.012041
4193 22:17:40.015069 TX Vref Scan disable
4194 22:17:40.018836 == TX Byte 0 ==
4195 22:17:40.021530 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4196 22:17:40.024979 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4197 22:17:40.028626 == TX Byte 1 ==
4198 22:17:40.032630 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4199 22:17:40.034656 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4200 22:17:40.034737
4201 22:17:40.038206 [DATLAT]
4202 22:17:40.038286 Freq=600, CH0 RK0
4203 22:17:40.038349
4204 22:17:40.041327 DATLAT Default: 0x9
4205 22:17:40.041408 0, 0xFFFF, sum = 0
4206 22:17:40.044978 1, 0xFFFF, sum = 0
4207 22:17:40.045060 2, 0xFFFF, sum = 0
4208 22:17:40.047955 3, 0xFFFF, sum = 0
4209 22:17:40.048037 4, 0xFFFF, sum = 0
4210 22:17:40.051433 5, 0xFFFF, sum = 0
4211 22:17:40.051516 6, 0xFFFF, sum = 0
4212 22:17:40.054751 7, 0xFFFF, sum = 0
4213 22:17:40.054832 8, 0x0, sum = 1
4214 22:17:40.057910 9, 0x0, sum = 2
4215 22:17:40.057991 10, 0x0, sum = 3
4216 22:17:40.061075 11, 0x0, sum = 4
4217 22:17:40.061158 best_step = 9
4218 22:17:40.061221
4219 22:17:40.061279 ==
4220 22:17:40.064442 Dram Type= 6, Freq= 0, CH_0, rank 0
4221 22:17:40.067705 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4222 22:17:40.067786 ==
4223 22:17:40.071896 RX Vref Scan: 1
4224 22:17:40.071977
4225 22:17:40.074612 RX Vref 0 -> 0, step: 1
4226 22:17:40.074693
4227 22:17:40.074756 RX Delay -179 -> 252, step: 8
4228 22:17:40.078083
4229 22:17:40.078164 Set Vref, RX VrefLevel [Byte0]: 57
4230 22:17:40.081011 [Byte1]: 60
4231 22:17:40.085850
4232 22:17:40.085931 Final RX Vref Byte 0 = 57 to rank0
4233 22:17:40.089064 Final RX Vref Byte 1 = 60 to rank0
4234 22:17:40.092580 Final RX Vref Byte 0 = 57 to rank1
4235 22:17:40.095548 Final RX Vref Byte 1 = 60 to rank1==
4236 22:17:40.099538 Dram Type= 6, Freq= 0, CH_0, rank 0
4237 22:17:40.105953 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4238 22:17:40.106036 ==
4239 22:17:40.106099 DQS Delay:
4240 22:17:40.108944 DQS0 = 0, DQS1 = 0
4241 22:17:40.109026 DQM Delay:
4242 22:17:40.109089 DQM0 = 43, DQM1 = 32
4243 22:17:40.112792 DQ Delay:
4244 22:17:40.115815 DQ0 =44, DQ1 =44, DQ2 =40, DQ3 =40
4245 22:17:40.119061 DQ4 =44, DQ5 =32, DQ6 =52, DQ7 =52
4246 22:17:40.122451 DQ8 =24, DQ9 =20, DQ10 =32, DQ11 =24
4247 22:17:40.125618 DQ12 =40, DQ13 =36, DQ14 =40, DQ15 =40
4248 22:17:40.125700
4249 22:17:40.125763
4250 22:17:40.132382 [DQSOSCAuto] RK0, (LSB)MR18= 0x6038, (MSB)MR19= 0x808, tDQSOscB0 = 399 ps tDQSOscB1 = 391 ps
4251 22:17:40.135382 CH0 RK0: MR19=808, MR18=6038
4252 22:17:40.142550 CH0_RK0: MR19=0x808, MR18=0x6038, DQSOSC=391, MR23=63, INC=171, DEC=114
4253 22:17:40.142632
4254 22:17:40.145621 ----->DramcWriteLeveling(PI) begin...
4255 22:17:40.145703 ==
4256 22:17:40.149354 Dram Type= 6, Freq= 0, CH_0, rank 1
4257 22:17:40.151747 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4258 22:17:40.151830 ==
4259 22:17:40.155338 Write leveling (Byte 0): 33 => 33
4260 22:17:40.158388 Write leveling (Byte 1): 30 => 30
4261 22:17:40.161973 DramcWriteLeveling(PI) end<-----
4262 22:17:40.162053
4263 22:17:40.162117 ==
4264 22:17:40.165775 Dram Type= 6, Freq= 0, CH_0, rank 1
4265 22:17:40.168352 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4266 22:17:40.171617 ==
4267 22:17:40.171698 [Gating] SW mode calibration
4268 22:17:40.178684 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4269 22:17:40.184731 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4270 22:17:40.188488 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4271 22:17:40.194793 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4272 22:17:40.198273 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4273 22:17:40.201353 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
4274 22:17:40.208669 0 9 16 | B1->B0 | 2f2f 2626 | 1 1 | (1 0) (1 0)
4275 22:17:40.211678 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4276 22:17:40.215320 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4277 22:17:40.221552 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4278 22:17:40.224710 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4279 22:17:40.228126 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4280 22:17:40.234166 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4281 22:17:40.238059 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4282 22:17:40.240745 0 10 16 | B1->B0 | 3939 3e3e | 0 0 | (0 0) (0 0)
4283 22:17:40.247601 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4284 22:17:40.251045 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4285 22:17:40.254100 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4286 22:17:40.260765 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4287 22:17:40.263914 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4288 22:17:40.267409 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4289 22:17:40.273942 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4290 22:17:40.277121 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4291 22:17:40.280834 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4292 22:17:40.287235 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4293 22:17:40.290488 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4294 22:17:40.293648 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4295 22:17:40.300418 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4296 22:17:40.303430 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4297 22:17:40.307167 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4298 22:17:40.313360 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4299 22:17:40.316732 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4300 22:17:40.320105 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4301 22:17:40.326835 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4302 22:17:40.329715 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4303 22:17:40.333065 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4304 22:17:40.339715 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4305 22:17:40.343635 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4306 22:17:40.346204 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4307 22:17:40.353161 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4308 22:17:40.356811 Total UI for P1: 0, mck2ui 16
4309 22:17:40.359960 best dqsien dly found for B0: ( 0, 13, 14)
4310 22:17:40.360041 Total UI for P1: 0, mck2ui 16
4311 22:17:40.366023 best dqsien dly found for B1: ( 0, 13, 16)
4312 22:17:40.369517 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4313 22:17:40.372841 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4314 22:17:40.372925
4315 22:17:40.375827 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4316 22:17:40.379356 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4317 22:17:40.382392 [Gating] SW calibration Done
4318 22:17:40.382518 ==
4319 22:17:40.385550 Dram Type= 6, Freq= 0, CH_0, rank 1
4320 22:17:40.388978 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4321 22:17:40.389063 ==
4322 22:17:40.392105 RX Vref Scan: 0
4323 22:17:40.392217
4324 22:17:40.395618 RX Vref 0 -> 0, step: 1
4325 22:17:40.395705
4326 22:17:40.398986 RX Delay -230 -> 252, step: 16
4327 22:17:40.402197 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4328 22:17:40.405716 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4329 22:17:40.408840 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4330 22:17:40.412050 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4331 22:17:40.418658 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4332 22:17:40.421665 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4333 22:17:40.425293 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4334 22:17:40.428628 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4335 22:17:40.435073 iDelay=218, Bit 8, Center 33 (-134 ~ 201) 336
4336 22:17:40.439008 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4337 22:17:40.441439 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4338 22:17:40.444904 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4339 22:17:40.451563 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4340 22:17:40.454867 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4341 22:17:40.458153 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4342 22:17:40.461274 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4343 22:17:40.464462 ==
4344 22:17:40.464594 Dram Type= 6, Freq= 0, CH_0, rank 1
4345 22:17:40.471407 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4346 22:17:40.471514 ==
4347 22:17:40.471605 DQS Delay:
4348 22:17:40.474930 DQS0 = 0, DQS1 = 0
4349 22:17:40.475009 DQM Delay:
4350 22:17:40.477974 DQM0 = 41, DQM1 = 36
4351 22:17:40.478054 DQ Delay:
4352 22:17:40.481289 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =33
4353 22:17:40.484447 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4354 22:17:40.488077 DQ8 =33, DQ9 =25, DQ10 =33, DQ11 =33
4355 22:17:40.491082 DQ12 =33, DQ13 =41, DQ14 =49, DQ15 =41
4356 22:17:40.491191
4357 22:17:40.491281
4358 22:17:40.491368 ==
4359 22:17:40.494094 Dram Type= 6, Freq= 0, CH_0, rank 1
4360 22:17:40.497604 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4361 22:17:40.497689 ==
4362 22:17:40.497750
4363 22:17:40.497806
4364 22:17:40.501103 TX Vref Scan disable
4365 22:17:40.504349 == TX Byte 0 ==
4366 22:17:40.507669 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4367 22:17:40.511394 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4368 22:17:40.514081 == TX Byte 1 ==
4369 22:17:40.517445 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4370 22:17:40.520690 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4371 22:17:40.520773 ==
4372 22:17:40.524236 Dram Type= 6, Freq= 0, CH_0, rank 1
4373 22:17:40.530768 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4374 22:17:40.530842 ==
4375 22:17:40.530902
4376 22:17:40.530971
4377 22:17:40.531025 TX Vref Scan disable
4378 22:17:40.534830 == TX Byte 0 ==
4379 22:17:40.538600 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4380 22:17:40.541877 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4381 22:17:40.544925 == TX Byte 1 ==
4382 22:17:40.548668 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4383 22:17:40.555164 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4384 22:17:40.555267
4385 22:17:40.555356 [DATLAT]
4386 22:17:40.555441 Freq=600, CH0 RK1
4387 22:17:40.555524
4388 22:17:40.558783 DATLAT Default: 0x9
4389 22:17:40.558861 0, 0xFFFF, sum = 0
4390 22:17:40.561632 1, 0xFFFF, sum = 0
4391 22:17:40.564654 2, 0xFFFF, sum = 0
4392 22:17:40.564742 3, 0xFFFF, sum = 0
4393 22:17:40.568114 4, 0xFFFF, sum = 0
4394 22:17:40.568222 5, 0xFFFF, sum = 0
4395 22:17:40.571380 6, 0xFFFF, sum = 0
4396 22:17:40.571485 7, 0xFFFF, sum = 0
4397 22:17:40.574732 8, 0x0, sum = 1
4398 22:17:40.574811 9, 0x0, sum = 2
4399 22:17:40.574873 10, 0x0, sum = 3
4400 22:17:40.578363 11, 0x0, sum = 4
4401 22:17:40.578442 best_step = 9
4402 22:17:40.578502
4403 22:17:40.581349 ==
4404 22:17:40.581429 Dram Type= 6, Freq= 0, CH_0, rank 1
4405 22:17:40.588170 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4406 22:17:40.588274 ==
4407 22:17:40.588364 RX Vref Scan: 0
4408 22:17:40.588449
4409 22:17:40.591059 RX Vref 0 -> 0, step: 1
4410 22:17:40.591137
4411 22:17:40.594439 RX Delay -179 -> 252, step: 8
4412 22:17:40.601146 iDelay=205, Bit 0, Center 40 (-107 ~ 188) 296
4413 22:17:40.604288 iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304
4414 22:17:40.607917 iDelay=205, Bit 2, Center 40 (-107 ~ 188) 296
4415 22:17:40.610817 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4416 22:17:40.614292 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4417 22:17:40.621005 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4418 22:17:40.623909 iDelay=205, Bit 6, Center 52 (-99 ~ 204) 304
4419 22:17:40.627577 iDelay=205, Bit 7, Center 52 (-99 ~ 204) 304
4420 22:17:40.631005 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4421 22:17:40.637349 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4422 22:17:40.640419 iDelay=205, Bit 10, Center 40 (-115 ~ 196) 312
4423 22:17:40.644331 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4424 22:17:40.647451 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4425 22:17:40.653604 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4426 22:17:40.657231 iDelay=205, Bit 14, Center 48 (-107 ~ 204) 312
4427 22:17:40.660705 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4428 22:17:40.660784 ==
4429 22:17:40.664041 Dram Type= 6, Freq= 0, CH_0, rank 1
4430 22:17:40.666891 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4431 22:17:40.666970 ==
4432 22:17:40.670174 DQS Delay:
4433 22:17:40.670252 DQS0 = 0, DQS1 = 0
4434 22:17:40.673633 DQM Delay:
4435 22:17:40.673711 DQM0 = 43, DQM1 = 35
4436 22:17:40.676859 DQ Delay:
4437 22:17:40.676938 DQ0 =40, DQ1 =44, DQ2 =40, DQ3 =40
4438 22:17:40.680115 DQ4 =44, DQ5 =32, DQ6 =52, DQ7 =52
4439 22:17:40.683316 DQ8 =24, DQ9 =20, DQ10 =40, DQ11 =28
4440 22:17:40.686791 DQ12 =40, DQ13 =40, DQ14 =48, DQ15 =40
4441 22:17:40.690043
4442 22:17:40.690122
4443 22:17:40.696666 [DQSOSCAuto] RK1, (LSB)MR18= 0x5d11, (MSB)MR19= 0x808, tDQSOscB0 = 406 ps tDQSOscB1 = 392 ps
4444 22:17:40.700471 CH0 RK1: MR19=808, MR18=5D11
4445 22:17:40.706389 CH0_RK1: MR19=0x808, MR18=0x5D11, DQSOSC=392, MR23=63, INC=170, DEC=113
4446 22:17:40.709663 [RxdqsGatingPostProcess] freq 600
4447 22:17:40.712829 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4448 22:17:40.716131 Pre-setting of DQS Precalculation
4449 22:17:40.723155 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4450 22:17:40.723237 ==
4451 22:17:40.726178 Dram Type= 6, Freq= 0, CH_1, rank 0
4452 22:17:40.729580 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4453 22:17:40.729661 ==
4454 22:17:40.736414 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4455 22:17:40.739612 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4456 22:17:40.744086 [CA 0] Center 35 (5~66) winsize 62
4457 22:17:40.747148 [CA 1] Center 36 (6~66) winsize 61
4458 22:17:40.751490 [CA 2] Center 34 (4~64) winsize 61
4459 22:17:40.754082 [CA 3] Center 33 (3~64) winsize 62
4460 22:17:40.757787 [CA 4] Center 33 (3~64) winsize 62
4461 22:17:40.760966 [CA 5] Center 33 (3~64) winsize 62
4462 22:17:40.761047
4463 22:17:40.764201 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4464 22:17:40.764281
4465 22:17:40.767393 [CATrainingPosCal] consider 1 rank data
4466 22:17:40.770601 u2DelayCellTimex100 = 270/100 ps
4467 22:17:40.774055 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4468 22:17:40.780419 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4469 22:17:40.783813 CA2 delay=34 (4~64),Diff = 1 PI (9 cell)
4470 22:17:40.787001 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4471 22:17:40.790540 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4472 22:17:40.794309 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4473 22:17:40.794390
4474 22:17:40.797599 CA PerBit enable=1, Macro0, CA PI delay=33
4475 22:17:40.797681
4476 22:17:40.800445 [CBTSetCACLKResult] CA Dly = 33
4477 22:17:40.800583 CS Dly: 4 (0~35)
4478 22:17:40.803746 ==
4479 22:17:40.806723 Dram Type= 6, Freq= 0, CH_1, rank 1
4480 22:17:40.810068 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4481 22:17:40.810149 ==
4482 22:17:40.817345 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4483 22:17:40.819892 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4484 22:17:40.824200 [CA 0] Center 35 (5~66) winsize 62
4485 22:17:40.827087 [CA 1] Center 36 (6~66) winsize 61
4486 22:17:40.830339 [CA 2] Center 34 (4~65) winsize 62
4487 22:17:40.834100 [CA 3] Center 34 (3~65) winsize 63
4488 22:17:40.837234 [CA 4] Center 34 (3~65) winsize 63
4489 22:17:40.840403 [CA 5] Center 34 (3~65) winsize 63
4490 22:17:40.840512
4491 22:17:40.843748 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4492 22:17:40.843829
4493 22:17:40.846922 [CATrainingPosCal] consider 2 rank data
4494 22:17:40.850145 u2DelayCellTimex100 = 270/100 ps
4495 22:17:40.853506 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4496 22:17:40.860211 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4497 22:17:40.864290 CA2 delay=34 (4~64),Diff = 1 PI (9 cell)
4498 22:17:40.867058 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4499 22:17:40.871194 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4500 22:17:40.874042 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4501 22:17:40.874125
4502 22:17:40.876897 CA PerBit enable=1, Macro0, CA PI delay=33
4503 22:17:40.876978
4504 22:17:40.880061 [CBTSetCACLKResult] CA Dly = 33
4505 22:17:40.883505 CS Dly: 4 (0~36)
4506 22:17:40.883586
4507 22:17:40.887081 ----->DramcWriteLeveling(PI) begin...
4508 22:17:40.887165 ==
4509 22:17:40.890174 Dram Type= 6, Freq= 0, CH_1, rank 0
4510 22:17:40.893276 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4511 22:17:40.893358 ==
4512 22:17:40.896380 Write leveling (Byte 0): 28 => 28
4513 22:17:40.899816 Write leveling (Byte 1): 28 => 28
4514 22:17:40.903339 DramcWriteLeveling(PI) end<-----
4515 22:17:40.903421
4516 22:17:40.903484 ==
4517 22:17:40.906537 Dram Type= 6, Freq= 0, CH_1, rank 0
4518 22:17:40.909544 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4519 22:17:40.909626 ==
4520 22:17:40.912949 [Gating] SW mode calibration
4521 22:17:40.919421 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4522 22:17:40.926321 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4523 22:17:40.929413 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4524 22:17:40.932705 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4525 22:17:40.939189 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4526 22:17:40.942475 0 9 12 | B1->B0 | 3434 2e2e | 1 1 | (1 0) (1 0)
4527 22:17:40.946571 0 9 16 | B1->B0 | 2424 2323 | 0 0 | (1 1) (0 0)
4528 22:17:40.952923 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4529 22:17:40.956488 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4530 22:17:40.958765 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4531 22:17:40.965494 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4532 22:17:40.969197 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4533 22:17:40.972187 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4534 22:17:40.978958 0 10 12 | B1->B0 | 3535 3b3b | 0 0 | (1 1) (0 0)
4535 22:17:40.982390 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4536 22:17:40.985730 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4537 22:17:40.991673 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4538 22:17:40.995052 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4539 22:17:41.001702 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4540 22:17:41.005060 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4541 22:17:41.008618 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4542 22:17:41.011848 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4543 22:17:41.018163 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4544 22:17:41.022437 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4545 22:17:41.024932 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4546 22:17:41.031831 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4547 22:17:41.034908 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4548 22:17:41.038226 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4549 22:17:41.044666 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4550 22:17:41.048071 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4551 22:17:41.051246 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4552 22:17:41.058059 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4553 22:17:41.060935 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4554 22:17:41.064900 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4555 22:17:41.071005 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4556 22:17:41.074459 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4557 22:17:41.077654 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4558 22:17:41.084129 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4559 22:17:41.087388 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4560 22:17:41.090814 Total UI for P1: 0, mck2ui 16
4561 22:17:41.094635 best dqsien dly found for B0: ( 0, 13, 12)
4562 22:17:41.097611 Total UI for P1: 0, mck2ui 16
4563 22:17:41.100754 best dqsien dly found for B1: ( 0, 13, 14)
4564 22:17:41.104031 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4565 22:17:41.107352 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4566 22:17:41.107434
4567 22:17:41.110842 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4568 22:17:41.117284 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4569 22:17:41.117366 [Gating] SW calibration Done
4570 22:17:41.117430 ==
4571 22:17:41.121362 Dram Type= 6, Freq= 0, CH_1, rank 0
4572 22:17:41.127194 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4573 22:17:41.127275 ==
4574 22:17:41.127339 RX Vref Scan: 0
4575 22:17:41.127397
4576 22:17:41.130430 RX Vref 0 -> 0, step: 1
4577 22:17:41.130511
4578 22:17:41.133528 RX Delay -230 -> 252, step: 16
4579 22:17:41.137080 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4580 22:17:41.140127 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4581 22:17:41.146598 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4582 22:17:41.150286 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4583 22:17:41.153146 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4584 22:17:41.156505 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4585 22:17:41.163433 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4586 22:17:41.166555 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4587 22:17:41.169897 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4588 22:17:41.173185 iDelay=218, Bit 9, Center 25 (-150 ~ 201) 352
4589 22:17:41.176504 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4590 22:17:41.182909 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4591 22:17:41.186221 iDelay=218, Bit 12, Center 41 (-134 ~ 217) 352
4592 22:17:41.189505 iDelay=218, Bit 13, Center 41 (-134 ~ 217) 352
4593 22:17:41.192776 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4594 22:17:41.199719 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4595 22:17:41.199802 ==
4596 22:17:41.203210 Dram Type= 6, Freq= 0, CH_1, rank 0
4597 22:17:41.206320 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4598 22:17:41.206402 ==
4599 22:17:41.206466 DQS Delay:
4600 22:17:41.209706 DQS0 = 0, DQS1 = 0
4601 22:17:41.209787 DQM Delay:
4602 22:17:41.212457 DQM0 = 43, DQM1 = 35
4603 22:17:41.212544 DQ Delay:
4604 22:17:41.216371 DQ0 =49, DQ1 =41, DQ2 =33, DQ3 =41
4605 22:17:41.219564 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =41
4606 22:17:41.223424 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =25
4607 22:17:41.226481 DQ12 =41, DQ13 =41, DQ14 =49, DQ15 =49
4608 22:17:41.226562
4609 22:17:41.226625
4610 22:17:41.226681 ==
4611 22:17:41.229442 Dram Type= 6, Freq= 0, CH_1, rank 0
4612 22:17:41.232669 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4613 22:17:41.236448 ==
4614 22:17:41.236551
4615 22:17:41.236629
4616 22:17:41.236686 TX Vref Scan disable
4617 22:17:41.239691 == TX Byte 0 ==
4618 22:17:41.242332 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4619 22:17:41.249343 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4620 22:17:41.249428 == TX Byte 1 ==
4621 22:17:41.252338 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4622 22:17:41.258948 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4623 22:17:41.259030 ==
4624 22:17:41.262411 Dram Type= 6, Freq= 0, CH_1, rank 0
4625 22:17:41.265917 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4626 22:17:41.266000 ==
4627 22:17:41.266063
4628 22:17:41.266122
4629 22:17:41.269565 TX Vref Scan disable
4630 22:17:41.272857 == TX Byte 0 ==
4631 22:17:41.275877 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4632 22:17:41.279320 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4633 22:17:41.279400 == TX Byte 1 ==
4634 22:17:41.285959 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4635 22:17:41.289023 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4636 22:17:41.289104
4637 22:17:41.289167 [DATLAT]
4638 22:17:41.292681 Freq=600, CH1 RK0
4639 22:17:41.292762
4640 22:17:41.292826 DATLAT Default: 0x9
4641 22:17:41.295264 0, 0xFFFF, sum = 0
4642 22:17:41.298986 1, 0xFFFF, sum = 0
4643 22:17:41.299068 2, 0xFFFF, sum = 0
4644 22:17:41.301932 3, 0xFFFF, sum = 0
4645 22:17:41.302014 4, 0xFFFF, sum = 0
4646 22:17:41.305246 5, 0xFFFF, sum = 0
4647 22:17:41.305328 6, 0xFFFF, sum = 0
4648 22:17:41.308702 7, 0xFFFF, sum = 0
4649 22:17:41.308784 8, 0x0, sum = 1
4650 22:17:41.311821 9, 0x0, sum = 2
4651 22:17:41.311904 10, 0x0, sum = 3
4652 22:17:41.315707 11, 0x0, sum = 4
4653 22:17:41.315790 best_step = 9
4654 22:17:41.315853
4655 22:17:41.315912 ==
4656 22:17:41.318558 Dram Type= 6, Freq= 0, CH_1, rank 0
4657 22:17:41.321937 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4658 22:17:41.322018 ==
4659 22:17:41.324884 RX Vref Scan: 1
4660 22:17:41.324964
4661 22:17:41.328559 RX Vref 0 -> 0, step: 1
4662 22:17:41.328640
4663 22:17:41.328703 RX Delay -195 -> 252, step: 8
4664 22:17:41.328761
4665 22:17:41.331569 Set Vref, RX VrefLevel [Byte0]: 53
4666 22:17:41.335015 [Byte1]: 51
4667 22:17:41.339333
4668 22:17:41.339414 Final RX Vref Byte 0 = 53 to rank0
4669 22:17:41.343228 Final RX Vref Byte 1 = 51 to rank0
4670 22:17:41.346656 Final RX Vref Byte 0 = 53 to rank1
4671 22:17:41.349783 Final RX Vref Byte 1 = 51 to rank1==
4672 22:17:41.352895 Dram Type= 6, Freq= 0, CH_1, rank 0
4673 22:17:41.359377 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4674 22:17:41.359458 ==
4675 22:17:41.359521 DQS Delay:
4676 22:17:41.359578 DQS0 = 0, DQS1 = 0
4677 22:17:41.363119 DQM Delay:
4678 22:17:41.363200 DQM0 = 44, DQM1 = 33
4679 22:17:41.366663 DQ Delay:
4680 22:17:41.369854 DQ0 =52, DQ1 =36, DQ2 =36, DQ3 =40
4681 22:17:41.372901 DQ4 =40, DQ5 =56, DQ6 =52, DQ7 =44
4682 22:17:41.376017 DQ8 =24, DQ9 =24, DQ10 =36, DQ11 =24
4683 22:17:41.379232 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4684 22:17:41.379312
4685 22:17:41.379375
4686 22:17:41.386290 [DQSOSCAuto] RK0, (LSB)MR18= 0x482d, (MSB)MR19= 0x808, tDQSOscB0 = 401 ps tDQSOscB1 = 396 ps
4687 22:17:41.389400 CH1 RK0: MR19=808, MR18=482D
4688 22:17:41.395863 CH1_RK0: MR19=0x808, MR18=0x482D, DQSOSC=396, MR23=63, INC=167, DEC=111
4689 22:17:41.395944
4690 22:17:41.399091 ----->DramcWriteLeveling(PI) begin...
4691 22:17:41.399168 ==
4692 22:17:41.402420 Dram Type= 6, Freq= 0, CH_1, rank 1
4693 22:17:41.405446 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4694 22:17:41.405527 ==
4695 22:17:41.408735 Write leveling (Byte 0): 30 => 30
4696 22:17:41.412152 Write leveling (Byte 1): 31 => 31
4697 22:17:41.415572 DramcWriteLeveling(PI) end<-----
4698 22:17:41.415644
4699 22:17:41.415713 ==
4700 22:17:41.418938 Dram Type= 6, Freq= 0, CH_1, rank 1
4701 22:17:41.425791 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4702 22:17:41.425866 ==
4703 22:17:41.425928 [Gating] SW mode calibration
4704 22:17:41.435655 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4705 22:17:41.438715 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4706 22:17:41.444763 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4707 22:17:41.448512 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4708 22:17:41.451465 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4709 22:17:41.455415 0 9 12 | B1->B0 | 2e2e 3434 | 1 0 | (1 0) (0 1)
4710 22:17:41.461336 0 9 16 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4711 22:17:41.464410 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4712 22:17:41.468056 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4713 22:17:41.474340 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4714 22:17:41.477868 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4715 22:17:41.481712 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4716 22:17:41.487642 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4717 22:17:41.491389 0 10 12 | B1->B0 | 3636 2d2d | 0 1 | (0 0) (0 0)
4718 22:17:41.494440 0 10 16 | B1->B0 | 4646 4343 | 0 0 | (0 0) (0 0)
4719 22:17:41.501353 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4720 22:17:41.504422 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4721 22:17:41.507672 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4722 22:17:41.513830 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4723 22:17:41.517449 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4724 22:17:41.523855 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4725 22:17:41.527095 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4726 22:17:41.530261 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4727 22:17:41.537109 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4728 22:17:41.540697 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4729 22:17:41.543737 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4730 22:17:41.550084 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4731 22:17:41.553892 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4732 22:17:41.556751 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4733 22:17:41.563301 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4734 22:17:41.567472 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4735 22:17:41.570087 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4736 22:17:41.576398 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4737 22:17:41.580166 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4738 22:17:41.583001 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4739 22:17:41.586598 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4740 22:17:41.593102 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4741 22:17:41.596181 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4742 22:17:41.599646 Total UI for P1: 0, mck2ui 16
4743 22:17:41.603060 best dqsien dly found for B1: ( 0, 13, 10)
4744 22:17:41.606161 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4745 22:17:41.609653 Total UI for P1: 0, mck2ui 16
4746 22:17:41.613050 best dqsien dly found for B0: ( 0, 13, 12)
4747 22:17:41.619552 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4748 22:17:41.622827 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4749 22:17:41.622901
4750 22:17:41.626053 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4751 22:17:41.629833 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4752 22:17:41.632648 [Gating] SW calibration Done
4753 22:17:41.632728 ==
4754 22:17:41.635861 Dram Type= 6, Freq= 0, CH_1, rank 1
4755 22:17:41.639188 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4756 22:17:41.639295 ==
4757 22:17:41.642678 RX Vref Scan: 0
4758 22:17:41.642752
4759 22:17:41.642817 RX Vref 0 -> 0, step: 1
4760 22:17:41.642875
4761 22:17:41.645897 RX Delay -230 -> 252, step: 16
4762 22:17:41.649320 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4763 22:17:41.655764 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4764 22:17:41.658929 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4765 22:17:41.662634 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4766 22:17:41.665864 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4767 22:17:41.672297 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4768 22:17:41.675611 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4769 22:17:41.679602 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4770 22:17:41.682045 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4771 22:17:41.688793 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4772 22:17:41.692520 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4773 22:17:41.695681 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4774 22:17:41.698867 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4775 22:17:41.705370 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4776 22:17:41.708805 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4777 22:17:41.712265 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4778 22:17:41.712351 ==
4779 22:17:41.715781 Dram Type= 6, Freq= 0, CH_1, rank 1
4780 22:17:41.718870 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4781 22:17:41.718960 ==
4782 22:17:41.721880 DQS Delay:
4783 22:17:41.721960 DQS0 = 0, DQS1 = 0
4784 22:17:41.725532 DQM Delay:
4785 22:17:41.725614 DQM0 = 40, DQM1 = 35
4786 22:17:41.725677 DQ Delay:
4787 22:17:41.728510 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =41
4788 22:17:41.731822 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4789 22:17:41.735048 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4790 22:17:41.738157 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =49
4791 22:17:41.738238
4792 22:17:41.741740
4793 22:17:41.741813 ==
4794 22:17:41.744699 Dram Type= 6, Freq= 0, CH_1, rank 1
4795 22:17:41.748192 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4796 22:17:41.748263 ==
4797 22:17:41.748322
4798 22:17:41.748385
4799 22:17:41.751752 TX Vref Scan disable
4800 22:17:41.751825 == TX Byte 0 ==
4801 22:17:41.758481 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4802 22:17:41.761229 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4803 22:17:41.761310 == TX Byte 1 ==
4804 22:17:41.767814 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4805 22:17:41.771012 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4806 22:17:41.771093 ==
4807 22:17:41.774952 Dram Type= 6, Freq= 0, CH_1, rank 1
4808 22:17:41.777541 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4809 22:17:41.777622 ==
4810 22:17:41.777685
4811 22:17:41.777742
4812 22:17:41.780847 TX Vref Scan disable
4813 22:17:41.785290 == TX Byte 0 ==
4814 22:17:41.787925 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4815 22:17:41.793922 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4816 22:17:41.794003 == TX Byte 1 ==
4817 22:17:41.797484 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4818 22:17:41.803583 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4819 22:17:41.803662
4820 22:17:41.803731 [DATLAT]
4821 22:17:41.803790 Freq=600, CH1 RK1
4822 22:17:41.803847
4823 22:17:41.807209 DATLAT Default: 0x9
4824 22:17:41.810411 0, 0xFFFF, sum = 0
4825 22:17:41.810484 1, 0xFFFF, sum = 0
4826 22:17:41.813761 2, 0xFFFF, sum = 0
4827 22:17:41.813835 3, 0xFFFF, sum = 0
4828 22:17:41.817065 4, 0xFFFF, sum = 0
4829 22:17:41.817138 5, 0xFFFF, sum = 0
4830 22:17:41.820124 6, 0xFFFF, sum = 0
4831 22:17:41.820194 7, 0xFFFF, sum = 0
4832 22:17:41.823423 8, 0x0, sum = 1
4833 22:17:41.823494 9, 0x0, sum = 2
4834 22:17:41.826941 10, 0x0, sum = 3
4835 22:17:41.827013 11, 0x0, sum = 4
4836 22:17:41.827071 best_step = 9
4837 22:17:41.827126
4838 22:17:41.830014 ==
4839 22:17:41.833511 Dram Type= 6, Freq= 0, CH_1, rank 1
4840 22:17:41.837030 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4841 22:17:41.837103 ==
4842 22:17:41.837164 RX Vref Scan: 0
4843 22:17:41.837227
4844 22:17:41.840101 RX Vref 0 -> 0, step: 1
4845 22:17:41.840172
4846 22:17:41.843209 RX Delay -195 -> 252, step: 8
4847 22:17:41.849940 iDelay=213, Bit 0, Center 44 (-107 ~ 196) 304
4848 22:17:41.853173 iDelay=213, Bit 1, Center 36 (-115 ~ 188) 304
4849 22:17:41.856425 iDelay=213, Bit 2, Center 28 (-123 ~ 180) 304
4850 22:17:41.859628 iDelay=213, Bit 3, Center 40 (-107 ~ 188) 296
4851 22:17:41.866754 iDelay=213, Bit 4, Center 40 (-115 ~ 196) 312
4852 22:17:41.869975 iDelay=213, Bit 5, Center 52 (-99 ~ 204) 304
4853 22:17:41.873103 iDelay=213, Bit 6, Center 56 (-99 ~ 212) 312
4854 22:17:41.876253 iDelay=213, Bit 7, Center 40 (-115 ~ 196) 312
4855 22:17:41.879649 iDelay=213, Bit 8, Center 24 (-131 ~ 180) 312
4856 22:17:41.886362 iDelay=213, Bit 9, Center 24 (-131 ~ 180) 312
4857 22:17:41.889900 iDelay=213, Bit 10, Center 32 (-123 ~ 188) 312
4858 22:17:41.892892 iDelay=213, Bit 11, Center 24 (-131 ~ 180) 312
4859 22:17:41.896400 iDelay=213, Bit 12, Center 44 (-115 ~ 204) 320
4860 22:17:41.902944 iDelay=213, Bit 13, Center 40 (-115 ~ 196) 312
4861 22:17:41.905856 iDelay=213, Bit 14, Center 40 (-115 ~ 196) 312
4862 22:17:41.909315 iDelay=213, Bit 15, Center 48 (-107 ~ 204) 312
4863 22:17:41.909389 ==
4864 22:17:41.912641 Dram Type= 6, Freq= 0, CH_1, rank 1
4865 22:17:41.916544 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4866 22:17:41.919355 ==
4867 22:17:41.919427 DQS Delay:
4868 22:17:41.919488 DQS0 = 0, DQS1 = 0
4869 22:17:41.922719 DQM Delay:
4870 22:17:41.922799 DQM0 = 42, DQM1 = 34
4871 22:17:41.925601 DQ Delay:
4872 22:17:41.929181 DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =40
4873 22:17:41.929260 DQ4 =40, DQ5 =52, DQ6 =56, DQ7 =40
4874 22:17:41.932239 DQ8 =24, DQ9 =24, DQ10 =32, DQ11 =24
4875 22:17:41.939093 DQ12 =44, DQ13 =40, DQ14 =40, DQ15 =48
4876 22:17:41.939199
4877 22:17:41.939265
4878 22:17:41.945654 [DQSOSCAuto] RK1, (LSB)MR18= 0x2e23, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 401 ps
4879 22:17:41.948859 CH1 RK1: MR19=808, MR18=2E23
4880 22:17:41.955915 CH1_RK1: MR19=0x808, MR18=0x2E23, DQSOSC=401, MR23=63, INC=163, DEC=108
4881 22:17:41.958684 [RxdqsGatingPostProcess] freq 600
4882 22:17:41.961691 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4883 22:17:41.965070 Pre-setting of DQS Precalculation
4884 22:17:41.972252 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4885 22:17:41.978752 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4886 22:17:41.985144 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4887 22:17:41.985226
4888 22:17:41.985290
4889 22:17:41.988177 [Calibration Summary] 1200 Mbps
4890 22:17:41.988251 CH 0, Rank 0
4891 22:17:41.991475 SW Impedance : PASS
4892 22:17:41.995793 DUTY Scan : NO K
4893 22:17:41.995866 ZQ Calibration : PASS
4894 22:17:41.998832 Jitter Meter : NO K
4895 22:17:42.001903 CBT Training : PASS
4896 22:17:42.001975 Write leveling : PASS
4897 22:17:42.005094 RX DQS gating : PASS
4898 22:17:42.008119 RX DQ/DQS(RDDQC) : PASS
4899 22:17:42.008197 TX DQ/DQS : PASS
4900 22:17:42.011420 RX DATLAT : PASS
4901 22:17:42.014517 RX DQ/DQS(Engine): PASS
4902 22:17:42.014591 TX OE : NO K
4903 22:17:42.018544 All Pass.
4904 22:17:42.018617
4905 22:17:42.018677 CH 0, Rank 1
4906 22:17:42.021176 SW Impedance : PASS
4907 22:17:42.021256 DUTY Scan : NO K
4908 22:17:42.024543 ZQ Calibration : PASS
4909 22:17:42.027904 Jitter Meter : NO K
4910 22:17:42.027987 CBT Training : PASS
4911 22:17:42.031246 Write leveling : PASS
4912 22:17:42.034582 RX DQS gating : PASS
4913 22:17:42.034652 RX DQ/DQS(RDDQC) : PASS
4914 22:17:42.037605 TX DQ/DQS : PASS
4915 22:17:42.041036 RX DATLAT : PASS
4916 22:17:42.041108 RX DQ/DQS(Engine): PASS
4917 22:17:42.044739 TX OE : NO K
4918 22:17:42.044820 All Pass.
4919 22:17:42.044878
4920 22:17:42.047460 CH 1, Rank 0
4921 22:17:42.047530 SW Impedance : PASS
4922 22:17:42.050855 DUTY Scan : NO K
4923 22:17:42.050943 ZQ Calibration : PASS
4924 22:17:42.054233 Jitter Meter : NO K
4925 22:17:42.057790 CBT Training : PASS
4926 22:17:42.057872 Write leveling : PASS
4927 22:17:42.060714 RX DQS gating : PASS
4928 22:17:42.064057 RX DQ/DQS(RDDQC) : PASS
4929 22:17:42.064138 TX DQ/DQS : PASS
4930 22:17:42.067386 RX DATLAT : PASS
4931 22:17:42.070875 RX DQ/DQS(Engine): PASS
4932 22:17:42.070957 TX OE : NO K
4933 22:17:42.073973 All Pass.
4934 22:17:42.074054
4935 22:17:42.074117 CH 1, Rank 1
4936 22:17:42.077570 SW Impedance : PASS
4937 22:17:42.077651 DUTY Scan : NO K
4938 22:17:42.080852 ZQ Calibration : PASS
4939 22:17:42.083861 Jitter Meter : NO K
4940 22:17:42.083942 CBT Training : PASS
4941 22:17:42.087826 Write leveling : PASS
4942 22:17:42.091478 RX DQS gating : PASS
4943 22:17:42.091559 RX DQ/DQS(RDDQC) : PASS
4944 22:17:42.094046 TX DQ/DQS : PASS
4945 22:17:42.097058 RX DATLAT : PASS
4946 22:17:42.097137 RX DQ/DQS(Engine): PASS
4947 22:17:42.100430 TX OE : NO K
4948 22:17:42.100573 All Pass.
4949 22:17:42.100636
4950 22:17:42.104052 DramC Write-DBI off
4951 22:17:42.107039 PER_BANK_REFRESH: Hybrid Mode
4952 22:17:42.107111 TX_TRACKING: ON
4953 22:17:42.117310 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4954 22:17:42.120056 [FAST_K] Save calibration result to emmc
4955 22:17:42.123665 dramc_set_vcore_voltage set vcore to 662500
4956 22:17:42.127039 Read voltage for 933, 3
4957 22:17:42.127113 Vio18 = 0
4958 22:17:42.127175 Vcore = 662500
4959 22:17:42.130326 Vdram = 0
4960 22:17:42.130395 Vddq = 0
4961 22:17:42.130461 Vmddr = 0
4962 22:17:42.136876 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4963 22:17:42.139820 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4964 22:17:42.143267 MEM_TYPE=3, freq_sel=17
4965 22:17:42.147156 sv_algorithm_assistance_LP4_1600
4966 22:17:42.149831 ============ PULL DRAM RESETB DOWN ============
4967 22:17:42.152903 ========== PULL DRAM RESETB DOWN end =========
4968 22:17:42.160144 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4969 22:17:42.162865 ===================================
4970 22:17:42.166314 LPDDR4 DRAM CONFIGURATION
4971 22:17:42.169610 ===================================
4972 22:17:42.169680 EX_ROW_EN[0] = 0x0
4973 22:17:42.172681 EX_ROW_EN[1] = 0x0
4974 22:17:42.172750 LP4Y_EN = 0x0
4975 22:17:42.176021 WORK_FSP = 0x0
4976 22:17:42.176100 WL = 0x3
4977 22:17:42.179733 RL = 0x3
4978 22:17:42.179812 BL = 0x2
4979 22:17:42.183096 RPST = 0x0
4980 22:17:42.183175 RD_PRE = 0x0
4981 22:17:42.186006 WR_PRE = 0x1
4982 22:17:42.186085 WR_PST = 0x0
4983 22:17:42.189684 DBI_WR = 0x0
4984 22:17:42.193012 DBI_RD = 0x0
4985 22:17:42.193092 OTF = 0x1
4986 22:17:42.196382 ===================================
4987 22:17:42.199419 ===================================
4988 22:17:42.199499 ANA top config
4989 22:17:42.202424 ===================================
4990 22:17:42.206092 DLL_ASYNC_EN = 0
4991 22:17:42.209596 ALL_SLAVE_EN = 1
4992 22:17:42.212306 NEW_RANK_MODE = 1
4993 22:17:42.215547 DLL_IDLE_MODE = 1
4994 22:17:42.215627 LP45_APHY_COMB_EN = 1
4995 22:17:42.218772 TX_ODT_DIS = 1
4996 22:17:42.222117 NEW_8X_MODE = 1
4997 22:17:42.225270 ===================================
4998 22:17:42.229165 ===================================
4999 22:17:42.231964 data_rate = 1866
5000 22:17:42.235548 CKR = 1
5001 22:17:42.238708 DQ_P2S_RATIO = 8
5002 22:17:42.242059 ===================================
5003 22:17:42.242139 CA_P2S_RATIO = 8
5004 22:17:42.245183 DQ_CA_OPEN = 0
5005 22:17:42.248968 DQ_SEMI_OPEN = 0
5006 22:17:42.252316 CA_SEMI_OPEN = 0
5007 22:17:42.255150 CA_FULL_RATE = 0
5008 22:17:42.258644 DQ_CKDIV4_EN = 1
5009 22:17:42.258750 CA_CKDIV4_EN = 1
5010 22:17:42.262098 CA_PREDIV_EN = 0
5011 22:17:42.265151 PH8_DLY = 0
5012 22:17:42.268324 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
5013 22:17:42.271837 DQ_AAMCK_DIV = 4
5014 22:17:42.274980 CA_AAMCK_DIV = 4
5015 22:17:42.275051 CA_ADMCK_DIV = 4
5016 22:17:42.278177 DQ_TRACK_CA_EN = 0
5017 22:17:42.281779 CA_PICK = 933
5018 22:17:42.284630 CA_MCKIO = 933
5019 22:17:42.287898 MCKIO_SEMI = 0
5020 22:17:42.291395 PLL_FREQ = 3732
5021 22:17:42.294449 DQ_UI_PI_RATIO = 32
5022 22:17:42.298304 CA_UI_PI_RATIO = 0
5023 22:17:42.301504 ===================================
5024 22:17:42.304713 ===================================
5025 22:17:42.304793 memory_type:LPDDR4
5026 22:17:42.308160 GP_NUM : 10
5027 22:17:42.311291 SRAM_EN : 1
5028 22:17:42.311372 MD32_EN : 0
5029 22:17:42.314395 ===================================
5030 22:17:42.318391 [ANA_INIT] >>>>>>>>>>>>>>
5031 22:17:42.321611 <<<<<< [CONFIGURE PHASE]: ANA_TX
5032 22:17:42.324043 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5033 22:17:42.327703 ===================================
5034 22:17:42.330819 data_rate = 1866,PCW = 0X8f00
5035 22:17:42.333955 ===================================
5036 22:17:42.337433 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5037 22:17:42.341085 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5038 22:17:42.347312 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5039 22:17:42.350791 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5040 22:17:42.354727 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5041 22:17:42.357100 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5042 22:17:42.360803 [ANA_INIT] flow start
5043 22:17:42.363995 [ANA_INIT] PLL >>>>>>>>
5044 22:17:42.364075 [ANA_INIT] PLL <<<<<<<<
5045 22:17:42.367114 [ANA_INIT] MIDPI >>>>>>>>
5046 22:17:42.370734 [ANA_INIT] MIDPI <<<<<<<<
5047 22:17:42.373829 [ANA_INIT] DLL >>>>>>>>
5048 22:17:42.373910 [ANA_INIT] flow end
5049 22:17:42.377077 ============ LP4 DIFF to SE enter ============
5050 22:17:42.384046 ============ LP4 DIFF to SE exit ============
5051 22:17:42.384126 [ANA_INIT] <<<<<<<<<<<<<
5052 22:17:42.387260 [Flow] Enable top DCM control >>>>>
5053 22:17:42.390136 [Flow] Enable top DCM control <<<<<
5054 22:17:42.394764 Enable DLL master slave shuffle
5055 22:17:42.400280 ==============================================================
5056 22:17:42.400363 Gating Mode config
5057 22:17:42.406595 ==============================================================
5058 22:17:42.410409 Config description:
5059 22:17:42.420681 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5060 22:17:42.426563 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5061 22:17:42.430132 SELPH_MODE 0: By rank 1: By Phase
5062 22:17:42.436321 ==============================================================
5063 22:17:42.439871 GAT_TRACK_EN = 1
5064 22:17:42.443221 RX_GATING_MODE = 2
5065 22:17:42.443302 RX_GATING_TRACK_MODE = 2
5066 22:17:42.446857 SELPH_MODE = 1
5067 22:17:42.450314 PICG_EARLY_EN = 1
5068 22:17:42.452948 VALID_LAT_VALUE = 1
5069 22:17:42.459672 ==============================================================
5070 22:17:42.463112 Enter into Gating configuration >>>>
5071 22:17:42.466137 Exit from Gating configuration <<<<
5072 22:17:42.469955 Enter into DVFS_PRE_config >>>>>
5073 22:17:42.479390 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5074 22:17:42.483317 Exit from DVFS_PRE_config <<<<<
5075 22:17:42.486435 Enter into PICG configuration >>>>
5076 22:17:42.489653 Exit from PICG configuration <<<<
5077 22:17:42.492786 [RX_INPUT] configuration >>>>>
5078 22:17:42.496052 [RX_INPUT] configuration <<<<<
5079 22:17:42.499462 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5080 22:17:42.505630 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5081 22:17:42.512693 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5082 22:17:42.519040 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5083 22:17:42.525714 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5084 22:17:42.528899 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5085 22:17:42.535603 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5086 22:17:42.538681 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5087 22:17:42.542428 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5088 22:17:42.545552 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5089 22:17:42.551906 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5090 22:17:42.555312 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5091 22:17:42.558647 ===================================
5092 22:17:42.561916 LPDDR4 DRAM CONFIGURATION
5093 22:17:42.565652 ===================================
5094 22:17:42.565733 EX_ROW_EN[0] = 0x0
5095 22:17:42.568493 EX_ROW_EN[1] = 0x0
5096 22:17:42.568607 LP4Y_EN = 0x0
5097 22:17:42.571726 WORK_FSP = 0x0
5098 22:17:42.571808 WL = 0x3
5099 22:17:42.575332 RL = 0x3
5100 22:17:42.575414 BL = 0x2
5101 22:17:42.578342 RPST = 0x0
5102 22:17:42.581904 RD_PRE = 0x0
5103 22:17:42.581985 WR_PRE = 0x1
5104 22:17:42.585243 WR_PST = 0x0
5105 22:17:42.585325 DBI_WR = 0x0
5106 22:17:42.588656 DBI_RD = 0x0
5107 22:17:42.588737 OTF = 0x1
5108 22:17:42.591770 ===================================
5109 22:17:42.595382 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5110 22:17:42.601876 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5111 22:17:42.604576 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5112 22:17:42.608391 ===================================
5113 22:17:42.611615 LPDDR4 DRAM CONFIGURATION
5114 22:17:42.614849 ===================================
5115 22:17:42.614931 EX_ROW_EN[0] = 0x10
5116 22:17:42.618207 EX_ROW_EN[1] = 0x0
5117 22:17:42.618288 LP4Y_EN = 0x0
5118 22:17:42.621289 WORK_FSP = 0x0
5119 22:17:42.621370 WL = 0x3
5120 22:17:42.624881 RL = 0x3
5121 22:17:42.628242 BL = 0x2
5122 22:17:42.628323 RPST = 0x0
5123 22:17:42.631234 RD_PRE = 0x0
5124 22:17:42.631342 WR_PRE = 0x1
5125 22:17:42.634463 WR_PST = 0x0
5126 22:17:42.634579 DBI_WR = 0x0
5127 22:17:42.638088 DBI_RD = 0x0
5128 22:17:42.638221 OTF = 0x1
5129 22:17:42.641421 ===================================
5130 22:17:42.647328 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5131 22:17:42.651334 nWR fixed to 30
5132 22:17:42.654795 [ModeRegInit_LP4] CH0 RK0
5133 22:17:42.654884 [ModeRegInit_LP4] CH0 RK1
5134 22:17:42.658309 [ModeRegInit_LP4] CH1 RK0
5135 22:17:42.661403 [ModeRegInit_LP4] CH1 RK1
5136 22:17:42.661496 match AC timing 9
5137 22:17:42.668568 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5138 22:17:42.671721 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5139 22:17:42.675101 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5140 22:17:42.681608 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5141 22:17:42.685023 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5142 22:17:42.685348 ==
5143 22:17:42.688197 Dram Type= 6, Freq= 0, CH_0, rank 0
5144 22:17:42.691759 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5145 22:17:42.692093 ==
5146 22:17:42.697901 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5147 22:17:42.704611 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5148 22:17:42.707949 [CA 0] Center 37 (7~68) winsize 62
5149 22:17:42.711173 [CA 1] Center 37 (7~68) winsize 62
5150 22:17:42.714357 [CA 2] Center 34 (4~65) winsize 62
5151 22:17:42.718778 [CA 3] Center 35 (5~65) winsize 61
5152 22:17:42.720915 [CA 4] Center 33 (3~64) winsize 62
5153 22:17:42.724564 [CA 5] Center 33 (4~63) winsize 60
5154 22:17:42.724893
5155 22:17:42.727658 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5156 22:17:42.728092
5157 22:17:42.730818 [CATrainingPosCal] consider 1 rank data
5158 22:17:42.734217 u2DelayCellTimex100 = 270/100 ps
5159 22:17:42.738007 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5160 22:17:42.740960 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5161 22:17:42.744180 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5162 22:17:42.750959 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5163 22:17:42.754405 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5164 22:17:42.757242 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
5165 22:17:42.757608
5166 22:17:42.760693 CA PerBit enable=1, Macro0, CA PI delay=33
5167 22:17:42.761049
5168 22:17:42.764056 [CBTSetCACLKResult] CA Dly = 33
5169 22:17:42.764412 CS Dly: 7 (0~38)
5170 22:17:42.764748 ==
5171 22:17:42.767555 Dram Type= 6, Freq= 0, CH_0, rank 1
5172 22:17:42.773660 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5173 22:17:42.774035 ==
5174 22:17:42.777579 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5175 22:17:42.783511 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5176 22:17:42.787021 [CA 0] Center 37 (7~68) winsize 62
5177 22:17:42.790184 [CA 1] Center 37 (7~68) winsize 62
5178 22:17:42.793739 [CA 2] Center 34 (4~65) winsize 62
5179 22:17:42.797384 [CA 3] Center 34 (4~65) winsize 62
5180 22:17:42.800547 [CA 4] Center 33 (3~64) winsize 62
5181 22:17:42.803911 [CA 5] Center 33 (3~63) winsize 61
5182 22:17:42.804464
5183 22:17:42.806769 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5184 22:17:42.807124
5185 22:17:42.810241 [CATrainingPosCal] consider 2 rank data
5186 22:17:42.813527 u2DelayCellTimex100 = 270/100 ps
5187 22:17:42.816845 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5188 22:17:42.823469 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5189 22:17:42.826587 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5190 22:17:42.830758 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5191 22:17:42.833622 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5192 22:17:42.836996 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
5193 22:17:42.837477
5194 22:17:42.840019 CA PerBit enable=1, Macro0, CA PI delay=33
5195 22:17:42.840539
5196 22:17:42.843198 [CBTSetCACLKResult] CA Dly = 33
5197 22:17:42.846644 CS Dly: 7 (0~39)
5198 22:17:42.847024
5199 22:17:42.850333 ----->DramcWriteLeveling(PI) begin...
5200 22:17:42.850817 ==
5201 22:17:42.853216 Dram Type= 6, Freq= 0, CH_0, rank 0
5202 22:17:42.856186 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5203 22:17:42.856607 ==
5204 22:17:42.859433 Write leveling (Byte 0): 33 => 33
5205 22:17:42.863099 Write leveling (Byte 1): 29 => 29
5206 22:17:42.866651 DramcWriteLeveling(PI) end<-----
5207 22:17:42.867095
5208 22:17:42.867382 ==
5209 22:17:42.869400 Dram Type= 6, Freq= 0, CH_0, rank 0
5210 22:17:42.872794 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5211 22:17:42.873148 ==
5212 22:17:42.876103 [Gating] SW mode calibration
5213 22:17:42.882868 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5214 22:17:42.889245 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5215 22:17:42.892905 0 14 0 | B1->B0 | 2322 3434 | 1 1 | (0 0) (1 1)
5216 22:17:42.895880 0 14 4 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
5217 22:17:42.902900 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5218 22:17:42.905809 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5219 22:17:42.909461 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5220 22:17:42.915935 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5221 22:17:42.919625 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (0 0)
5222 22:17:42.922697 0 14 28 | B1->B0 | 3434 2d2d | 1 0 | (1 1) (1 0)
5223 22:17:42.929039 0 15 0 | B1->B0 | 2f2f 2727 | 1 0 | (1 0) (0 0)
5224 22:17:42.932711 0 15 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5225 22:17:42.935776 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5226 22:17:42.942478 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5227 22:17:42.945575 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5228 22:17:42.949390 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5229 22:17:42.955781 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5230 22:17:42.958688 0 15 28 | B1->B0 | 2323 2e2e | 0 1 | (0 0) (0 0)
5231 22:17:42.961943 1 0 0 | B1->B0 | 2e2e 4444 | 0 0 | (0 0) (0 0)
5232 22:17:42.968897 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5233 22:17:42.972025 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5234 22:17:42.975858 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5235 22:17:42.981516 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5236 22:17:42.985127 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5237 22:17:42.988393 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5238 22:17:42.994928 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5239 22:17:42.998087 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5240 22:17:43.001469 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5241 22:17:43.007841 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5242 22:17:43.011223 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5243 22:17:43.014609 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5244 22:17:43.021156 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5245 22:17:43.024606 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5246 22:17:43.027923 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5247 22:17:43.034636 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5248 22:17:43.038254 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5249 22:17:43.041178 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5250 22:17:43.047955 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5251 22:17:43.050970 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5252 22:17:43.054297 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5253 22:17:43.060970 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5254 22:17:43.063862 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5255 22:17:43.067318 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5256 22:17:43.070866 Total UI for P1: 0, mck2ui 16
5257 22:17:43.075193 best dqsien dly found for B0: ( 1, 2, 28)
5258 22:17:43.080781 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5259 22:17:43.081105 Total UI for P1: 0, mck2ui 16
5260 22:17:43.087654 best dqsien dly found for B1: ( 1, 3, 0)
5261 22:17:43.090494 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5262 22:17:43.094011 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5263 22:17:43.094337
5264 22:17:43.097424 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5265 22:17:43.100636 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5266 22:17:43.104157 [Gating] SW calibration Done
5267 22:17:43.104481 ==
5268 22:17:43.107343 Dram Type= 6, Freq= 0, CH_0, rank 0
5269 22:17:43.110341 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5270 22:17:43.110668 ==
5271 22:17:43.113800 RX Vref Scan: 0
5272 22:17:43.114171
5273 22:17:43.114450 RX Vref 0 -> 0, step: 1
5274 22:17:43.114714
5275 22:17:43.116641 RX Delay -80 -> 252, step: 8
5276 22:17:43.120247 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5277 22:17:43.126656 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5278 22:17:43.130453 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5279 22:17:43.133218 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5280 22:17:43.136862 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5281 22:17:43.139887 iDelay=208, Bit 5, Center 83 (-16 ~ 183) 200
5282 22:17:43.143511 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5283 22:17:43.149879 iDelay=208, Bit 7, Center 103 (0 ~ 207) 208
5284 22:17:43.153356 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5285 22:17:43.156657 iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184
5286 22:17:43.159712 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5287 22:17:43.163466 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5288 22:17:43.169372 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5289 22:17:43.172940 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5290 22:17:43.176301 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5291 22:17:43.179800 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5292 22:17:43.179882 ==
5293 22:17:43.182892 Dram Type= 6, Freq= 0, CH_0, rank 0
5294 22:17:43.189339 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5295 22:17:43.189422 ==
5296 22:17:43.189486 DQS Delay:
5297 22:17:43.192811 DQS0 = 0, DQS1 = 0
5298 22:17:43.192892 DQM Delay:
5299 22:17:43.192956 DQM0 = 96, DQM1 = 85
5300 22:17:43.196814 DQ Delay:
5301 22:17:43.199471 DQ0 =99, DQ1 =99, DQ2 =91, DQ3 =91
5302 22:17:43.202242 DQ4 =99, DQ5 =83, DQ6 =107, DQ7 =103
5303 22:17:43.205497 DQ8 =79, DQ9 =75, DQ10 =87, DQ11 =79
5304 22:17:43.209003 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =91
5305 22:17:43.209085
5306 22:17:43.209149
5307 22:17:43.209206 ==
5308 22:17:43.212082 Dram Type= 6, Freq= 0, CH_0, rank 0
5309 22:17:43.215991 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5310 22:17:43.216073 ==
5311 22:17:43.216137
5312 22:17:43.216195
5313 22:17:43.218817 TX Vref Scan disable
5314 22:17:43.222168 == TX Byte 0 ==
5315 22:17:43.225413 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5316 22:17:43.229181 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5317 22:17:43.232070 == TX Byte 1 ==
5318 22:17:43.235339 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5319 22:17:43.238432 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5320 22:17:43.238514 ==
5321 22:17:43.241864 Dram Type= 6, Freq= 0, CH_0, rank 0
5322 22:17:43.248677 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5323 22:17:43.248759 ==
5324 22:17:43.248822
5325 22:17:43.248881
5326 22:17:43.248940 TX Vref Scan disable
5327 22:17:43.252849 == TX Byte 0 ==
5328 22:17:43.255610 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5329 22:17:43.262632 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5330 22:17:43.262712 == TX Byte 1 ==
5331 22:17:43.266028 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5332 22:17:43.272119 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5333 22:17:43.272199
5334 22:17:43.272261 [DATLAT]
5335 22:17:43.272318 Freq=933, CH0 RK0
5336 22:17:43.272375
5337 22:17:43.275810 DATLAT Default: 0xd
5338 22:17:43.275896 0, 0xFFFF, sum = 0
5339 22:17:43.278848 1, 0xFFFF, sum = 0
5340 22:17:43.282151 2, 0xFFFF, sum = 0
5341 22:17:43.282237 3, 0xFFFF, sum = 0
5342 22:17:43.285525 4, 0xFFFF, sum = 0
5343 22:17:43.285618 5, 0xFFFF, sum = 0
5344 22:17:43.288569 6, 0xFFFF, sum = 0
5345 22:17:43.288670 7, 0xFFFF, sum = 0
5346 22:17:43.292189 8, 0xFFFF, sum = 0
5347 22:17:43.292323 9, 0xFFFF, sum = 0
5348 22:17:43.295584 10, 0x0, sum = 1
5349 22:17:43.295693 11, 0x0, sum = 2
5350 22:17:43.298864 12, 0x0, sum = 3
5351 22:17:43.298984 13, 0x0, sum = 4
5352 22:17:43.301789 best_step = 11
5353 22:17:43.301906
5354 22:17:43.301998 ==
5355 22:17:43.305303 Dram Type= 6, Freq= 0, CH_0, rank 0
5356 22:17:43.308341 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5357 22:17:43.308487 ==
5358 22:17:43.308618 RX Vref Scan: 1
5359 22:17:43.311723
5360 22:17:43.311865 RX Vref 0 -> 0, step: 1
5361 22:17:43.311976
5362 22:17:43.314935 RX Delay -61 -> 252, step: 4
5363 22:17:43.315013
5364 22:17:43.318427 Set Vref, RX VrefLevel [Byte0]: 57
5365 22:17:43.321918 [Byte1]: 60
5366 22:17:43.325581
5367 22:17:43.325895 Final RX Vref Byte 0 = 57 to rank0
5368 22:17:43.328318 Final RX Vref Byte 1 = 60 to rank0
5369 22:17:43.331950 Final RX Vref Byte 0 = 57 to rank1
5370 22:17:43.335284 Final RX Vref Byte 1 = 60 to rank1==
5371 22:17:43.338889 Dram Type= 6, Freq= 0, CH_0, rank 0
5372 22:17:43.345597 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5373 22:17:43.345948 ==
5374 22:17:43.346222 DQS Delay:
5375 22:17:43.346475 DQS0 = 0, DQS1 = 0
5376 22:17:43.349007 DQM Delay:
5377 22:17:43.349356 DQM0 = 97, DQM1 = 86
5378 22:17:43.351801 DQ Delay:
5379 22:17:43.354880 DQ0 =96, DQ1 =98, DQ2 =94, DQ3 =94
5380 22:17:43.358315 DQ4 =98, DQ5 =88, DQ6 =106, DQ7 =106
5381 22:17:43.361525 DQ8 =78, DQ9 =78, DQ10 =86, DQ11 =82
5382 22:17:43.365503 DQ12 =92, DQ13 =90, DQ14 =96, DQ15 =92
5383 22:17:43.365851
5384 22:17:43.366121
5385 22:17:43.371767 [DQSOSCAuto] RK0, (LSB)MR18= 0x2c13, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 408 ps
5386 22:17:43.374831 CH0 RK0: MR19=505, MR18=2C13
5387 22:17:43.381555 CH0_RK0: MR19=0x505, MR18=0x2C13, DQSOSC=408, MR23=63, INC=65, DEC=43
5388 22:17:43.381908
5389 22:17:43.384961 ----->DramcWriteLeveling(PI) begin...
5390 22:17:43.385317 ==
5391 22:17:43.388012 Dram Type= 6, Freq= 0, CH_0, rank 1
5392 22:17:43.391355 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5393 22:17:43.391710 ==
5394 22:17:43.394626 Write leveling (Byte 0): 35 => 35
5395 22:17:43.397980 Write leveling (Byte 1): 33 => 33
5396 22:17:43.401330 DramcWriteLeveling(PI) end<-----
5397 22:17:43.401689
5398 22:17:43.401964 ==
5399 22:17:43.404636 Dram Type= 6, Freq= 0, CH_0, rank 1
5400 22:17:43.407930 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5401 22:17:43.411071 ==
5402 22:17:43.411439 [Gating] SW mode calibration
5403 22:17:43.421115 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5404 22:17:43.424488 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5405 22:17:43.427948 0 14 0 | B1->B0 | 2929 3232 | 1 0 | (0 0) (0 0)
5406 22:17:43.434245 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5407 22:17:43.437890 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5408 22:17:43.440718 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5409 22:17:43.447758 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5410 22:17:43.450549 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5411 22:17:43.453736 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5412 22:17:43.460726 0 14 28 | B1->B0 | 3333 2c2c | 0 0 | (0 1) (0 1)
5413 22:17:43.464548 0 15 0 | B1->B0 | 2f2f 2929 | 0 0 | (1 0) (0 0)
5414 22:17:43.467605 0 15 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5415 22:17:43.473877 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5416 22:17:43.477331 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5417 22:17:43.480244 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5418 22:17:43.487426 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5419 22:17:43.490426 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5420 22:17:43.493937 0 15 28 | B1->B0 | 2323 3333 | 0 0 | (0 0) (1 1)
5421 22:17:43.500207 1 0 0 | B1->B0 | 3939 4545 | 0 1 | (0 0) (0 0)
5422 22:17:43.503234 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5423 22:17:43.506559 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5424 22:17:43.513600 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5425 22:17:43.516485 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5426 22:17:43.519949 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5427 22:17:43.526535 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5428 22:17:43.529673 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5429 22:17:43.532863 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5430 22:17:43.539934 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5431 22:17:43.543340 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5432 22:17:43.546395 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5433 22:17:43.552732 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5434 22:17:43.556187 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5435 22:17:43.559406 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5436 22:17:43.566265 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5437 22:17:43.570231 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5438 22:17:43.572696 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5439 22:17:43.579180 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5440 22:17:43.582511 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5441 22:17:43.586611 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5442 22:17:43.592362 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5443 22:17:43.597026 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5444 22:17:43.599275 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5445 22:17:43.605543 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5446 22:17:43.608981 Total UI for P1: 0, mck2ui 16
5447 22:17:43.612206 best dqsien dly found for B0: ( 1, 2, 28)
5448 22:17:43.612634 Total UI for P1: 0, mck2ui 16
5449 22:17:43.619135 best dqsien dly found for B1: ( 1, 2, 30)
5450 22:17:43.622299 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5451 22:17:43.625951 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5452 22:17:43.626436
5453 22:17:43.629130 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5454 22:17:43.632355 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5455 22:17:43.635904 [Gating] SW calibration Done
5456 22:17:43.636433 ==
5457 22:17:43.639293 Dram Type= 6, Freq= 0, CH_0, rank 1
5458 22:17:43.642184 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5459 22:17:43.642598 ==
5460 22:17:43.645430 RX Vref Scan: 0
5461 22:17:43.646033
5462 22:17:43.646499 RX Vref 0 -> 0, step: 1
5463 22:17:43.646816
5464 22:17:43.648614 RX Delay -80 -> 252, step: 8
5465 22:17:43.652316 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5466 22:17:43.658558 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5467 22:17:43.662044 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5468 22:17:43.665683 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5469 22:17:43.668620 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5470 22:17:43.671886 iDelay=208, Bit 5, Center 83 (-16 ~ 183) 200
5471 22:17:43.678672 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5472 22:17:43.681604 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5473 22:17:43.685418 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5474 22:17:43.689150 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5475 22:17:43.691937 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5476 22:17:43.698548 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5477 22:17:43.701867 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5478 22:17:43.705143 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5479 22:17:43.708275 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5480 22:17:43.711594 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5481 22:17:43.712030 ==
5482 22:17:43.715069 Dram Type= 6, Freq= 0, CH_0, rank 1
5483 22:17:43.721447 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5484 22:17:43.721529 ==
5485 22:17:43.721594 DQS Delay:
5486 22:17:43.724552 DQS0 = 0, DQS1 = 0
5487 22:17:43.724647 DQM Delay:
5488 22:17:43.724712 DQM0 = 95, DQM1 = 88
5489 22:17:43.728045 DQ Delay:
5490 22:17:43.730882 DQ0 =95, DQ1 =99, DQ2 =87, DQ3 =91
5491 22:17:43.734050 DQ4 =99, DQ5 =83, DQ6 =103, DQ7 =107
5492 22:17:43.738079 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =83
5493 22:17:43.741412 DQ12 =91, DQ13 =95, DQ14 =99, DQ15 =91
5494 22:17:43.741494
5495 22:17:43.741558
5496 22:17:43.741616 ==
5497 22:17:43.744122 Dram Type= 6, Freq= 0, CH_0, rank 1
5498 22:17:43.747431 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5499 22:17:43.747513 ==
5500 22:17:43.747576
5501 22:17:43.747635
5502 22:17:43.750753 TX Vref Scan disable
5503 22:17:43.750833 == TX Byte 0 ==
5504 22:17:43.757417 Update DQ dly =719 (2 ,6, 15) DQ OEN =(2 ,3)
5505 22:17:43.760832 Update DQM dly =719 (2 ,6, 15) DQM OEN =(2 ,3)
5506 22:17:43.764098 == TX Byte 1 ==
5507 22:17:43.767140 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5508 22:17:43.770625 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5509 22:17:43.770706 ==
5510 22:17:43.773770 Dram Type= 6, Freq= 0, CH_0, rank 1
5511 22:17:43.776981 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5512 22:17:43.780286 ==
5513 22:17:43.780367
5514 22:17:43.780429
5515 22:17:43.780488 TX Vref Scan disable
5516 22:17:43.783764 == TX Byte 0 ==
5517 22:17:43.787081 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5518 22:17:43.794045 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5519 22:17:43.794126 == TX Byte 1 ==
5520 22:17:43.797260 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5521 22:17:43.803923 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5522 22:17:43.804004
5523 22:17:43.804067 [DATLAT]
5524 22:17:43.804125 Freq=933, CH0 RK1
5525 22:17:43.804182
5526 22:17:43.807196 DATLAT Default: 0xb
5527 22:17:43.807277 0, 0xFFFF, sum = 0
5528 22:17:43.810377 1, 0xFFFF, sum = 0
5529 22:17:43.813937 2, 0xFFFF, sum = 0
5530 22:17:43.814018 3, 0xFFFF, sum = 0
5531 22:17:43.817352 4, 0xFFFF, sum = 0
5532 22:17:43.817435 5, 0xFFFF, sum = 0
5533 22:17:43.820523 6, 0xFFFF, sum = 0
5534 22:17:43.820605 7, 0xFFFF, sum = 0
5535 22:17:43.823569 8, 0xFFFF, sum = 0
5536 22:17:43.823652 9, 0xFFFF, sum = 0
5537 22:17:43.827158 10, 0x0, sum = 1
5538 22:17:43.827240 11, 0x0, sum = 2
5539 22:17:43.830459 12, 0x0, sum = 3
5540 22:17:43.830540 13, 0x0, sum = 4
5541 22:17:43.830604 best_step = 11
5542 22:17:43.830662
5543 22:17:43.833576 ==
5544 22:17:43.837022 Dram Type= 6, Freq= 0, CH_0, rank 1
5545 22:17:43.840073 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5546 22:17:43.840160 ==
5547 22:17:43.840228 RX Vref Scan: 0
5548 22:17:43.840289
5549 22:17:43.843679 RX Vref 0 -> 0, step: 1
5550 22:17:43.843772
5551 22:17:43.847244 RX Delay -61 -> 252, step: 4
5552 22:17:43.850453 iDelay=199, Bit 0, Center 96 (7 ~ 186) 180
5553 22:17:43.857116 iDelay=199, Bit 1, Center 98 (3 ~ 194) 192
5554 22:17:43.860214 iDelay=199, Bit 2, Center 90 (-1 ~ 182) 184
5555 22:17:43.863664 iDelay=199, Bit 3, Center 94 (-1 ~ 190) 192
5556 22:17:43.867069 iDelay=199, Bit 4, Center 96 (3 ~ 190) 188
5557 22:17:43.870482 iDelay=199, Bit 5, Center 86 (-9 ~ 182) 192
5558 22:17:43.873565 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5559 22:17:43.880509 iDelay=199, Bit 7, Center 104 (11 ~ 198) 188
5560 22:17:43.883461 iDelay=199, Bit 8, Center 80 (-13 ~ 174) 188
5561 22:17:43.886959 iDelay=199, Bit 9, Center 76 (-13 ~ 166) 180
5562 22:17:43.890573 iDelay=199, Bit 10, Center 90 (-5 ~ 186) 192
5563 22:17:43.897061 iDelay=199, Bit 11, Center 82 (-9 ~ 174) 184
5564 22:17:43.900204 iDelay=199, Bit 12, Center 92 (-1 ~ 186) 188
5565 22:17:43.903389 iDelay=199, Bit 13, Center 92 (-1 ~ 186) 188
5566 22:17:43.906417 iDelay=199, Bit 14, Center 96 (3 ~ 190) 188
5567 22:17:43.909994 iDelay=199, Bit 15, Center 92 (-1 ~ 186) 188
5568 22:17:43.910377 ==
5569 22:17:43.913255 Dram Type= 6, Freq= 0, CH_0, rank 1
5570 22:17:43.919567 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5571 22:17:43.919951 ==
5572 22:17:43.920249 DQS Delay:
5573 22:17:43.923313 DQS0 = 0, DQS1 = 0
5574 22:17:43.923694 DQM Delay:
5575 22:17:43.923996 DQM0 = 96, DQM1 = 87
5576 22:17:43.926175 DQ Delay:
5577 22:17:43.929639 DQ0 =96, DQ1 =98, DQ2 =90, DQ3 =94
5578 22:17:43.933246 DQ4 =96, DQ5 =86, DQ6 =104, DQ7 =104
5579 22:17:43.936134 DQ8 =80, DQ9 =76, DQ10 =90, DQ11 =82
5580 22:17:43.939394 DQ12 =92, DQ13 =92, DQ14 =96, DQ15 =92
5581 22:17:43.939776
5582 22:17:43.940072
5583 22:17:43.946246 [DQSOSCAuto] RK1, (LSB)MR18= 0x26f7, (MSB)MR19= 0x504, tDQSOscB0 = 425 ps tDQSOscB1 = 409 ps
5584 22:17:43.949459 CH0 RK1: MR19=504, MR18=26F7
5585 22:17:43.955856 CH0_RK1: MR19=0x504, MR18=0x26F7, DQSOSC=409, MR23=63, INC=64, DEC=43
5586 22:17:43.959193 [RxdqsGatingPostProcess] freq 933
5587 22:17:43.966376 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5588 22:17:43.968818 best DQS0 dly(2T, 0.5T) = (0, 10)
5589 22:17:43.969199 best DQS1 dly(2T, 0.5T) = (0, 11)
5590 22:17:43.972417 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5591 22:17:43.976327 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5592 22:17:43.979200 best DQS0 dly(2T, 0.5T) = (0, 10)
5593 22:17:43.981964 best DQS1 dly(2T, 0.5T) = (0, 10)
5594 22:17:43.985326 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5595 22:17:43.988863 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5596 22:17:43.991989 Pre-setting of DQS Precalculation
5597 22:17:43.998574 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5598 22:17:43.998959 ==
5599 22:17:44.002633 Dram Type= 6, Freq= 0, CH_1, rank 0
5600 22:17:44.005442 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5601 22:17:44.005826 ==
5602 22:17:44.012441 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5603 22:17:44.015307 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5604 22:17:44.019781 [CA 0] Center 36 (6~67) winsize 62
5605 22:17:44.022829 [CA 1] Center 37 (7~67) winsize 61
5606 22:17:44.026285 [CA 2] Center 34 (4~64) winsize 61
5607 22:17:44.029244 [CA 3] Center 33 (3~64) winsize 62
5608 22:17:44.032711 [CA 4] Center 34 (4~64) winsize 61
5609 22:17:44.035765 [CA 5] Center 33 (3~64) winsize 62
5610 22:17:44.036149
5611 22:17:44.039266 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5612 22:17:44.039649
5613 22:17:44.042786 [CATrainingPosCal] consider 1 rank data
5614 22:17:44.046373 u2DelayCellTimex100 = 270/100 ps
5615 22:17:44.048999 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5616 22:17:44.055989 CA1 delay=37 (7~67),Diff = 4 PI (24 cell)
5617 22:17:44.058935 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5618 22:17:44.062707 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5619 22:17:44.066010 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5620 22:17:44.068966 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5621 22:17:44.069355
5622 22:17:44.072282 CA PerBit enable=1, Macro0, CA PI delay=33
5623 22:17:44.072700
5624 22:17:44.075695 [CBTSetCACLKResult] CA Dly = 33
5625 22:17:44.078899 CS Dly: 6 (0~37)
5626 22:17:44.079297 ==
5627 22:17:44.082238 Dram Type= 6, Freq= 0, CH_1, rank 1
5628 22:17:44.085550 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5629 22:17:44.085947 ==
5630 22:17:44.092470 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5631 22:17:44.095745 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5632 22:17:44.099204 [CA 0] Center 36 (6~67) winsize 62
5633 22:17:44.102583 [CA 1] Center 36 (6~67) winsize 62
5634 22:17:44.105897 [CA 2] Center 34 (4~65) winsize 62
5635 22:17:44.109098 [CA 3] Center 33 (3~64) winsize 62
5636 22:17:44.112504 [CA 4] Center 34 (3~65) winsize 63
5637 22:17:44.115671 [CA 5] Center 33 (3~64) winsize 62
5638 22:17:44.115841
5639 22:17:44.118915 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5640 22:17:44.119098
5641 22:17:44.122248 [CATrainingPosCal] consider 2 rank data
5642 22:17:44.125624 u2DelayCellTimex100 = 270/100 ps
5643 22:17:44.128575 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5644 22:17:44.135743 CA1 delay=37 (7~67),Diff = 4 PI (24 cell)
5645 22:17:44.139131 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5646 22:17:44.142332 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5647 22:17:44.145582 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5648 22:17:44.149365 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5649 22:17:44.149781
5650 22:17:44.152179 CA PerBit enable=1, Macro0, CA PI delay=33
5651 22:17:44.152623
5652 22:17:44.155554 [CBTSetCACLKResult] CA Dly = 33
5653 22:17:44.155966 CS Dly: 7 (0~39)
5654 22:17:44.159056
5655 22:17:44.162386 ----->DramcWriteLeveling(PI) begin...
5656 22:17:44.162836 ==
5657 22:17:44.165903 Dram Type= 6, Freq= 0, CH_1, rank 0
5658 22:17:44.168976 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5659 22:17:44.169397 ==
5660 22:17:44.172065 Write leveling (Byte 0): 27 => 27
5661 22:17:44.175401 Write leveling (Byte 1): 27 => 27
5662 22:17:44.178866 DramcWriteLeveling(PI) end<-----
5663 22:17:44.179280
5664 22:17:44.179619 ==
5665 22:17:44.182118 Dram Type= 6, Freq= 0, CH_1, rank 0
5666 22:17:44.185380 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5667 22:17:44.185802 ==
5668 22:17:44.188586 [Gating] SW mode calibration
5669 22:17:44.195314 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5670 22:17:44.201615 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5671 22:17:44.205193 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5672 22:17:44.208766 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5673 22:17:44.215463 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5674 22:17:44.218750 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5675 22:17:44.221380 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5676 22:17:44.227949 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5677 22:17:44.231979 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
5678 22:17:44.234767 0 14 28 | B1->B0 | 3030 2e2e | 0 0 | (0 1) (0 0)
5679 22:17:44.241121 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5680 22:17:44.244766 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5681 22:17:44.248048 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5682 22:17:44.254682 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5683 22:17:44.257882 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5684 22:17:44.261550 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5685 22:17:44.267831 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5686 22:17:44.271197 0 15 28 | B1->B0 | 3939 3b3b | 0 0 | (1 1) (0 0)
5687 22:17:44.274814 1 0 0 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
5688 22:17:44.280727 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5689 22:17:44.284205 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5690 22:17:44.287652 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5691 22:17:44.294035 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5692 22:17:44.297118 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5693 22:17:44.300369 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5694 22:17:44.307065 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5695 22:17:44.309987 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5696 22:17:44.313510 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5697 22:17:44.320021 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5698 22:17:44.323640 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5699 22:17:44.326451 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5700 22:17:44.333302 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5701 22:17:44.336279 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5702 22:17:44.339591 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5703 22:17:44.346600 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5704 22:17:44.349991 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5705 22:17:44.352993 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5706 22:17:44.359689 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5707 22:17:44.362847 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5708 22:17:44.366534 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5709 22:17:44.372677 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5710 22:17:44.376276 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5711 22:17:44.379651 Total UI for P1: 0, mck2ui 16
5712 22:17:44.382889 best dqsien dly found for B0: ( 1, 2, 22)
5713 22:17:44.386579 Total UI for P1: 0, mck2ui 16
5714 22:17:44.389479 best dqsien dly found for B1: ( 1, 2, 24)
5715 22:17:44.392703 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5716 22:17:44.396243 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5717 22:17:44.396324
5718 22:17:44.399964 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5719 22:17:44.402864 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5720 22:17:44.406016 [Gating] SW calibration Done
5721 22:17:44.406096 ==
5722 22:17:44.409513 Dram Type= 6, Freq= 0, CH_1, rank 0
5723 22:17:44.415788 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5724 22:17:44.415869 ==
5725 22:17:44.415932 RX Vref Scan: 0
5726 22:17:44.415991
5727 22:17:44.419169 RX Vref 0 -> 0, step: 1
5728 22:17:44.419251
5729 22:17:44.422890 RX Delay -80 -> 252, step: 8
5730 22:17:44.425756 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5731 22:17:44.429064 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5732 22:17:44.433122 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5733 22:17:44.435556 iDelay=208, Bit 3, Center 99 (0 ~ 199) 200
5734 22:17:44.442212 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5735 22:17:44.445276 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5736 22:17:44.448747 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5737 22:17:44.451949 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5738 22:17:44.455209 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5739 22:17:44.458885 iDelay=208, Bit 9, Center 83 (-16 ~ 183) 200
5740 22:17:44.465434 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5741 22:17:44.468720 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5742 22:17:44.471754 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5743 22:17:44.475226 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5744 22:17:44.478610 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5745 22:17:44.485314 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5746 22:17:44.485448 ==
5747 22:17:44.488444 Dram Type= 6, Freq= 0, CH_1, rank 0
5748 22:17:44.491813 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5749 22:17:44.491963 ==
5750 22:17:44.492080 DQS Delay:
5751 22:17:44.495332 DQS0 = 0, DQS1 = 0
5752 22:17:44.495503 DQM Delay:
5753 22:17:44.498458 DQM0 = 102, DQM1 = 90
5754 22:17:44.498662 DQ Delay:
5755 22:17:44.501552 DQ0 =107, DQ1 =99, DQ2 =95, DQ3 =99
5756 22:17:44.505181 DQ4 =95, DQ5 =111, DQ6 =111, DQ7 =99
5757 22:17:44.508439 DQ8 =75, DQ9 =83, DQ10 =91, DQ11 =79
5758 22:17:44.511467 DQ12 =99, DQ13 =99, DQ14 =99, DQ15 =99
5759 22:17:44.511548
5760 22:17:44.511610
5761 22:17:44.511668 ==
5762 22:17:44.514792 Dram Type= 6, Freq= 0, CH_1, rank 0
5763 22:17:44.521306 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5764 22:17:44.521394 ==
5765 22:17:44.521463
5766 22:17:44.521525
5767 22:17:44.521586 TX Vref Scan disable
5768 22:17:44.524498 == TX Byte 0 ==
5769 22:17:44.527985 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5770 22:17:44.534661 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5771 22:17:44.534743 == TX Byte 1 ==
5772 22:17:44.537556 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5773 22:17:44.544391 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5774 22:17:44.544472 ==
5775 22:17:44.547938 Dram Type= 6, Freq= 0, CH_1, rank 0
5776 22:17:44.551308 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5777 22:17:44.551388 ==
5778 22:17:44.551452
5779 22:17:44.551509
5780 22:17:44.554163 TX Vref Scan disable
5781 22:17:44.554244 == TX Byte 0 ==
5782 22:17:44.561069 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5783 22:17:44.564428 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5784 22:17:44.564572 == TX Byte 1 ==
5785 22:17:44.571286 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5786 22:17:44.574465 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5787 22:17:44.574848
5788 22:17:44.575147 [DATLAT]
5789 22:17:44.577812 Freq=933, CH1 RK0
5790 22:17:44.578223
5791 22:17:44.578527 DATLAT Default: 0xd
5792 22:17:44.581074 0, 0xFFFF, sum = 0
5793 22:17:44.581466 1, 0xFFFF, sum = 0
5794 22:17:44.584431 2, 0xFFFF, sum = 0
5795 22:17:44.588083 3, 0xFFFF, sum = 0
5796 22:17:44.588475 4, 0xFFFF, sum = 0
5797 22:17:44.591086 5, 0xFFFF, sum = 0
5798 22:17:44.591479 6, 0xFFFF, sum = 0
5799 22:17:44.594461 7, 0xFFFF, sum = 0
5800 22:17:44.594856 8, 0xFFFF, sum = 0
5801 22:17:44.597621 9, 0xFFFF, sum = 0
5802 22:17:44.598013 10, 0x0, sum = 1
5803 22:17:44.600547 11, 0x0, sum = 2
5804 22:17:44.600940 12, 0x0, sum = 3
5805 22:17:44.603893 13, 0x0, sum = 4
5806 22:17:44.604284 best_step = 11
5807 22:17:44.604620
5808 22:17:44.604913 ==
5809 22:17:44.607668 Dram Type= 6, Freq= 0, CH_1, rank 0
5810 22:17:44.610891 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5811 22:17:44.611333 ==
5812 22:17:44.613899 RX Vref Scan: 1
5813 22:17:44.614320
5814 22:17:44.617461 RX Vref 0 -> 0, step: 1
5815 22:17:44.617879
5816 22:17:44.618206 RX Delay -69 -> 252, step: 4
5817 22:17:44.618511
5818 22:17:44.620489 Set Vref, RX VrefLevel [Byte0]: 53
5819 22:17:44.623842 [Byte1]: 51
5820 22:17:44.628676
5821 22:17:44.629090 Final RX Vref Byte 0 = 53 to rank0
5822 22:17:44.632148 Final RX Vref Byte 1 = 51 to rank0
5823 22:17:44.635415 Final RX Vref Byte 0 = 53 to rank1
5824 22:17:44.638571 Final RX Vref Byte 1 = 51 to rank1==
5825 22:17:44.642106 Dram Type= 6, Freq= 0, CH_1, rank 0
5826 22:17:44.648940 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5827 22:17:44.649454 ==
5828 22:17:44.649955 DQS Delay:
5829 22:17:44.651813 DQS0 = 0, DQS1 = 0
5830 22:17:44.652227 DQM Delay:
5831 22:17:44.652590 DQM0 = 101, DQM1 = 95
5832 22:17:44.655461 DQ Delay:
5833 22:17:44.658654 DQ0 =104, DQ1 =98, DQ2 =92, DQ3 =98
5834 22:17:44.662121 DQ4 =98, DQ5 =110, DQ6 =110, DQ7 =98
5835 22:17:44.665101 DQ8 =82, DQ9 =86, DQ10 =94, DQ11 =84
5836 22:17:44.668510 DQ12 =102, DQ13 =100, DQ14 =106, DQ15 =106
5837 22:17:44.668963
5838 22:17:44.669289
5839 22:17:44.675540 [DQSOSCAuto] RK0, (LSB)MR18= 0x1909, (MSB)MR19= 0x505, tDQSOscB0 = 419 ps tDQSOscB1 = 413 ps
5840 22:17:44.678542 CH1 RK0: MR19=505, MR18=1909
5841 22:17:44.684966 CH1_RK0: MR19=0x505, MR18=0x1909, DQSOSC=413, MR23=63, INC=63, DEC=42
5842 22:17:44.685385
5843 22:17:44.688368 ----->DramcWriteLeveling(PI) begin...
5844 22:17:44.688861 ==
5845 22:17:44.691674 Dram Type= 6, Freq= 0, CH_1, rank 1
5846 22:17:44.694836 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5847 22:17:44.698303 ==
5848 22:17:44.698720 Write leveling (Byte 0): 26 => 26
5849 22:17:44.701184 Write leveling (Byte 1): 30 => 30
5850 22:17:44.704972 DramcWriteLeveling(PI) end<-----
5851 22:17:44.705389
5852 22:17:44.705711 ==
5853 22:17:44.708186 Dram Type= 6, Freq= 0, CH_1, rank 1
5854 22:17:44.714745 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5855 22:17:44.715262 ==
5856 22:17:44.715786 [Gating] SW mode calibration
5857 22:17:44.724459 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5858 22:17:44.727264 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5859 22:17:44.734018 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5860 22:17:44.737541 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5861 22:17:44.740914 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5862 22:17:44.747368 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5863 22:17:44.750598 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5864 22:17:44.754021 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5865 22:17:44.760364 0 14 24 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
5866 22:17:44.763731 0 14 28 | B1->B0 | 2b2b 2f2f | 0 1 | (0 0) (1 0)
5867 22:17:44.767033 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5868 22:17:44.774136 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5869 22:17:44.777287 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5870 22:17:44.781056 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5871 22:17:44.786975 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5872 22:17:44.790633 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5873 22:17:44.793762 0 15 24 | B1->B0 | 2828 2323 | 0 0 | (1 1) (0 0)
5874 22:17:44.799958 0 15 28 | B1->B0 | 3e3e 3737 | 1 0 | (0 0) (0 0)
5875 22:17:44.803269 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5876 22:17:44.806667 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5877 22:17:44.813649 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5878 22:17:44.816744 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5879 22:17:44.820831 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5880 22:17:44.826946 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5881 22:17:44.830201 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5882 22:17:44.833474 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5883 22:17:44.840294 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5884 22:17:44.842908 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5885 22:17:44.846608 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5886 22:17:44.853079 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5887 22:17:44.856258 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5888 22:17:44.859569 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5889 22:17:44.866196 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5890 22:17:44.869810 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5891 22:17:44.872457 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5892 22:17:44.879369 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5893 22:17:44.882284 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5894 22:17:44.885429 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5895 22:17:44.892352 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5896 22:17:44.895609 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5897 22:17:44.898725 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5898 22:17:44.905355 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5899 22:17:44.905448 Total UI for P1: 0, mck2ui 16
5900 22:17:44.912304 best dqsien dly found for B1: ( 1, 2, 26)
5901 22:17:44.915812 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5902 22:17:44.919149 Total UI for P1: 0, mck2ui 16
5903 22:17:44.922477 best dqsien dly found for B0: ( 1, 2, 28)
5904 22:17:44.925720 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5905 22:17:44.928971 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5906 22:17:44.929382
5907 22:17:44.932209 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5908 22:17:44.935199 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5909 22:17:44.938566 [Gating] SW calibration Done
5910 22:17:44.939069 ==
5911 22:17:44.942295 Dram Type= 6, Freq= 0, CH_1, rank 1
5912 22:17:44.945330 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5913 22:17:44.948496 ==
5914 22:17:44.948948 RX Vref Scan: 0
5915 22:17:44.949279
5916 22:17:44.951549 RX Vref 0 -> 0, step: 1
5917 22:17:44.951959
5918 22:17:44.955301 RX Delay -80 -> 252, step: 8
5919 22:17:44.958420 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5920 22:17:44.961612 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5921 22:17:44.965055 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5922 22:17:44.968159 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5923 22:17:44.971692 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5924 22:17:44.978014 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5925 22:17:44.981662 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5926 22:17:44.984614 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5927 22:17:44.987803 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5928 22:17:44.990942 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5929 22:17:44.997881 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5930 22:17:45.001400 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5931 22:17:45.004775 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5932 22:17:45.007511 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5933 22:17:45.011045 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5934 22:17:45.017672 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5935 22:17:45.018108 ==
5936 22:17:45.021263 Dram Type= 6, Freq= 0, CH_1, rank 1
5937 22:17:45.023992 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5938 22:17:45.024407 ==
5939 22:17:45.024812 DQS Delay:
5940 22:17:45.027876 DQS0 = 0, DQS1 = 0
5941 22:17:45.028284 DQM Delay:
5942 22:17:45.030731 DQM0 = 99, DQM1 = 90
5943 22:17:45.031143 DQ Delay:
5944 22:17:45.034309 DQ0 =103, DQ1 =95, DQ2 =87, DQ3 =95
5945 22:17:45.037490 DQ4 =95, DQ5 =111, DQ6 =111, DQ7 =95
5946 22:17:45.040549 DQ8 =79, DQ9 =79, DQ10 =95, DQ11 =83
5947 22:17:45.043556 DQ12 =99, DQ13 =99, DQ14 =95, DQ15 =95
5948 22:17:45.043972
5949 22:17:45.044295
5950 22:17:45.044632 ==
5951 22:17:45.047317 Dram Type= 6, Freq= 0, CH_1, rank 1
5952 22:17:45.050332 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5953 22:17:45.053398 ==
5954 22:17:45.053819
5955 22:17:45.054148
5956 22:17:45.054451 TX Vref Scan disable
5957 22:17:45.057366 == TX Byte 0 ==
5958 22:17:45.060298 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5959 22:17:45.063469 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5960 22:17:45.066822 == TX Byte 1 ==
5961 22:17:45.070046 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5962 22:17:45.073342 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5963 22:17:45.077232 ==
5964 22:17:45.080089 Dram Type= 6, Freq= 0, CH_1, rank 1
5965 22:17:45.083228 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5966 22:17:45.083714 ==
5967 22:17:45.084045
5968 22:17:45.084353
5969 22:17:45.086274 TX Vref Scan disable
5970 22:17:45.086689 == TX Byte 0 ==
5971 22:17:45.092892 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5972 22:17:45.096584 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5973 22:17:45.096972 == TX Byte 1 ==
5974 22:17:45.102758 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5975 22:17:45.106070 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5976 22:17:45.106586
5977 22:17:45.107001 [DATLAT]
5978 22:17:45.109517 Freq=933, CH1 RK1
5979 22:17:45.109878
5980 22:17:45.110237 DATLAT Default: 0xb
5981 22:17:45.112937 0, 0xFFFF, sum = 0
5982 22:17:45.113296 1, 0xFFFF, sum = 0
5983 22:17:45.116260 2, 0xFFFF, sum = 0
5984 22:17:45.119621 3, 0xFFFF, sum = 0
5985 22:17:45.120124 4, 0xFFFF, sum = 0
5986 22:17:45.122592 5, 0xFFFF, sum = 0
5987 22:17:45.123001 6, 0xFFFF, sum = 0
5988 22:17:45.125960 7, 0xFFFF, sum = 0
5989 22:17:45.126320 8, 0xFFFF, sum = 0
5990 22:17:45.129218 9, 0xFFFF, sum = 0
5991 22:17:45.129576 10, 0x0, sum = 1
5992 22:17:45.132743 11, 0x0, sum = 2
5993 22:17:45.133241 12, 0x0, sum = 3
5994 22:17:45.136205 13, 0x0, sum = 4
5995 22:17:45.136670 best_step = 11
5996 22:17:45.137025
5997 22:17:45.137367 ==
5998 22:17:45.139297 Dram Type= 6, Freq= 0, CH_1, rank 1
5999 22:17:45.142867 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
6000 22:17:45.143308 ==
6001 22:17:45.145648 RX Vref Scan: 0
6002 22:17:45.146141
6003 22:17:45.148963 RX Vref 0 -> 0, step: 1
6004 22:17:45.149449
6005 22:17:45.149814 RX Delay -61 -> 252, step: 4
6006 22:17:45.157003 iDelay=207, Bit 0, Center 104 (15 ~ 194) 180
6007 22:17:45.160821 iDelay=207, Bit 1, Center 96 (7 ~ 186) 180
6008 22:17:45.163762 iDelay=207, Bit 2, Center 88 (-1 ~ 178) 180
6009 22:17:45.167073 iDelay=207, Bit 3, Center 96 (11 ~ 182) 172
6010 22:17:45.169989 iDelay=207, Bit 4, Center 100 (7 ~ 194) 188
6011 22:17:45.177025 iDelay=207, Bit 5, Center 112 (23 ~ 202) 180
6012 22:17:45.180166 iDelay=207, Bit 6, Center 116 (27 ~ 206) 180
6013 22:17:45.183557 iDelay=207, Bit 7, Center 98 (7 ~ 190) 184
6014 22:17:45.186873 iDelay=207, Bit 8, Center 82 (-5 ~ 170) 176
6015 22:17:45.190205 iDelay=207, Bit 9, Center 84 (-5 ~ 174) 180
6016 22:17:45.193475 iDelay=207, Bit 10, Center 92 (3 ~ 182) 180
6017 22:17:45.199552 iDelay=207, Bit 11, Center 86 (-1 ~ 174) 176
6018 22:17:45.203050 iDelay=207, Bit 12, Center 102 (11 ~ 194) 184
6019 22:17:45.206515 iDelay=207, Bit 13, Center 100 (11 ~ 190) 180
6020 22:17:45.209741 iDelay=207, Bit 14, Center 100 (11 ~ 190) 180
6021 22:17:45.216368 iDelay=207, Bit 15, Center 102 (11 ~ 194) 184
6022 22:17:45.216501 ==
6023 22:17:45.219367 Dram Type= 6, Freq= 0, CH_1, rank 1
6024 22:17:45.222882 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
6025 22:17:45.222995 ==
6026 22:17:45.223081 DQS Delay:
6027 22:17:45.226074 DQS0 = 0, DQS1 = 0
6028 22:17:45.226196 DQM Delay:
6029 22:17:45.228982 DQM0 = 101, DQM1 = 93
6030 22:17:45.229116 DQ Delay:
6031 22:17:45.232576 DQ0 =104, DQ1 =96, DQ2 =88, DQ3 =96
6032 22:17:45.235752 DQ4 =100, DQ5 =112, DQ6 =116, DQ7 =98
6033 22:17:45.239169 DQ8 =82, DQ9 =84, DQ10 =92, DQ11 =86
6034 22:17:45.242501 DQ12 =102, DQ13 =100, DQ14 =100, DQ15 =102
6035 22:17:45.242676
6036 22:17:45.242812
6037 22:17:45.252384 [DQSOSCAuto] RK1, (LSB)MR18= 0x802, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 419 ps
6038 22:17:45.252881 CH1 RK1: MR19=505, MR18=802
6039 22:17:45.258825 CH1_RK1: MR19=0x505, MR18=0x802, DQSOSC=419, MR23=63, INC=61, DEC=41
6040 22:17:45.262430 [RxdqsGatingPostProcess] freq 933
6041 22:17:45.269284 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
6042 22:17:45.271806 best DQS0 dly(2T, 0.5T) = (0, 10)
6043 22:17:45.275282 best DQS1 dly(2T, 0.5T) = (0, 10)
6044 22:17:45.278517 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6045 22:17:45.281886 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6046 22:17:45.285680 best DQS0 dly(2T, 0.5T) = (0, 10)
6047 22:17:45.288761 best DQS1 dly(2T, 0.5T) = (0, 10)
6048 22:17:45.291971 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6049 22:17:45.295233 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6050 22:17:45.295315 Pre-setting of DQS Precalculation
6051 22:17:45.301491 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6052 22:17:45.308205 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6053 22:17:45.315021 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6054 22:17:45.315103
6055 22:17:45.315166
6056 22:17:45.318126 [Calibration Summary] 1866 Mbps
6057 22:17:45.321480 CH 0, Rank 0
6058 22:17:45.321562 SW Impedance : PASS
6059 22:17:45.325209 DUTY Scan : NO K
6060 22:17:45.328057 ZQ Calibration : PASS
6061 22:17:45.328139 Jitter Meter : NO K
6062 22:17:45.331418 CBT Training : PASS
6063 22:17:45.334897 Write leveling : PASS
6064 22:17:45.334985 RX DQS gating : PASS
6065 22:17:45.338412 RX DQ/DQS(RDDQC) : PASS
6066 22:17:45.341512 TX DQ/DQS : PASS
6067 22:17:45.341682 RX DATLAT : PASS
6068 22:17:45.344490 RX DQ/DQS(Engine): PASS
6069 22:17:45.347635 TX OE : NO K
6070 22:17:45.347718 All Pass.
6071 22:17:45.347783
6072 22:17:45.347842 CH 0, Rank 1
6073 22:17:45.351154 SW Impedance : PASS
6074 22:17:45.354684 DUTY Scan : NO K
6075 22:17:45.354772 ZQ Calibration : PASS
6076 22:17:45.357527 Jitter Meter : NO K
6077 22:17:45.360674 CBT Training : PASS
6078 22:17:45.360756 Write leveling : PASS
6079 22:17:45.364415 RX DQS gating : PASS
6080 22:17:45.364496 RX DQ/DQS(RDDQC) : PASS
6081 22:17:45.367654 TX DQ/DQS : PASS
6082 22:17:45.371091 RX DATLAT : PASS
6083 22:17:45.371171 RX DQ/DQS(Engine): PASS
6084 22:17:45.373729 TX OE : NO K
6085 22:17:45.373816 All Pass.
6086 22:17:45.373884
6087 22:17:45.377431 CH 1, Rank 0
6088 22:17:45.377512 SW Impedance : PASS
6089 22:17:45.380729 DUTY Scan : NO K
6090 22:17:45.383908 ZQ Calibration : PASS
6091 22:17:45.383989 Jitter Meter : NO K
6092 22:17:45.387196 CBT Training : PASS
6093 22:17:45.390637 Write leveling : PASS
6094 22:17:45.390719 RX DQS gating : PASS
6095 22:17:45.393960 RX DQ/DQS(RDDQC) : PASS
6096 22:17:45.397029 TX DQ/DQS : PASS
6097 22:17:45.397110 RX DATLAT : PASS
6098 22:17:45.400251 RX DQ/DQS(Engine): PASS
6099 22:17:45.403544 TX OE : NO K
6100 22:17:45.403625 All Pass.
6101 22:17:45.403687
6102 22:17:45.403745 CH 1, Rank 1
6103 22:17:45.407238 SW Impedance : PASS
6104 22:17:45.410834 DUTY Scan : NO K
6105 22:17:45.410916 ZQ Calibration : PASS
6106 22:17:45.413659 Jitter Meter : NO K
6107 22:17:45.417064 CBT Training : PASS
6108 22:17:45.417146 Write leveling : PASS
6109 22:17:45.420323 RX DQS gating : PASS
6110 22:17:45.423649 RX DQ/DQS(RDDQC) : PASS
6111 22:17:45.423730 TX DQ/DQS : PASS
6112 22:17:45.426798 RX DATLAT : PASS
6113 22:17:45.426879 RX DQ/DQS(Engine): PASS
6114 22:17:45.430900 TX OE : NO K
6115 22:17:45.430982 All Pass.
6116 22:17:45.431045
6117 22:17:45.434047 DramC Write-DBI off
6118 22:17:45.436799 PER_BANK_REFRESH: Hybrid Mode
6119 22:17:45.436885 TX_TRACKING: ON
6120 22:17:45.447374 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6121 22:17:45.450301 [FAST_K] Save calibration result to emmc
6122 22:17:45.453713 dramc_set_vcore_voltage set vcore to 650000
6123 22:17:45.457013 Read voltage for 400, 6
6124 22:17:45.457428 Vio18 = 0
6125 22:17:45.460543 Vcore = 650000
6126 22:17:45.460989 Vdram = 0
6127 22:17:45.461317 Vddq = 0
6128 22:17:45.461623 Vmddr = 0
6129 22:17:45.466979 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6130 22:17:45.473018 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6131 22:17:45.473100 MEM_TYPE=3, freq_sel=20
6132 22:17:45.476829 sv_algorithm_assistance_LP4_800
6133 22:17:45.480198 ============ PULL DRAM RESETB DOWN ============
6134 22:17:45.486599 ========== PULL DRAM RESETB DOWN end =========
6135 22:17:45.490201 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6136 22:17:45.493509 ===================================
6137 22:17:45.497260 LPDDR4 DRAM CONFIGURATION
6138 22:17:45.499830 ===================================
6139 22:17:45.500246 EX_ROW_EN[0] = 0x0
6140 22:17:45.503397 EX_ROW_EN[1] = 0x0
6141 22:17:45.506562 LP4Y_EN = 0x0
6142 22:17:45.506975 WORK_FSP = 0x0
6143 22:17:45.509960 WL = 0x2
6144 22:17:45.510376 RL = 0x2
6145 22:17:45.512816 BL = 0x2
6146 22:17:45.513234 RPST = 0x0
6147 22:17:45.515984 RD_PRE = 0x0
6148 22:17:45.516400 WR_PRE = 0x1
6149 22:17:45.519708 WR_PST = 0x0
6150 22:17:45.520121 DBI_WR = 0x0
6151 22:17:45.523018 DBI_RD = 0x0
6152 22:17:45.523434 OTF = 0x1
6153 22:17:45.525982 ===================================
6154 22:17:45.529327 ===================================
6155 22:17:45.532584 ANA top config
6156 22:17:45.535835 ===================================
6157 22:17:45.539497 DLL_ASYNC_EN = 0
6158 22:17:45.539959 ALL_SLAVE_EN = 1
6159 22:17:45.542171 NEW_RANK_MODE = 1
6160 22:17:45.545579 DLL_IDLE_MODE = 1
6161 22:17:45.549658 LP45_APHY_COMB_EN = 1
6162 22:17:45.550044 TX_ODT_DIS = 1
6163 22:17:45.552417 NEW_8X_MODE = 1
6164 22:17:45.556263 ===================================
6165 22:17:45.559154 ===================================
6166 22:17:45.562158 data_rate = 800
6167 22:17:45.565298 CKR = 1
6168 22:17:45.569064 DQ_P2S_RATIO = 4
6169 22:17:45.572357 ===================================
6170 22:17:45.575462 CA_P2S_RATIO = 4
6171 22:17:45.575888 DQ_CA_OPEN = 0
6172 22:17:45.578923 DQ_SEMI_OPEN = 1
6173 22:17:45.581959 CA_SEMI_OPEN = 1
6174 22:17:45.585633 CA_FULL_RATE = 0
6175 22:17:45.588393 DQ_CKDIV4_EN = 0
6176 22:17:45.591719 CA_CKDIV4_EN = 1
6177 22:17:45.592148 CA_PREDIV_EN = 0
6178 22:17:45.595432 PH8_DLY = 0
6179 22:17:45.598708 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6180 22:17:45.602381 DQ_AAMCK_DIV = 0
6181 22:17:45.605271 CA_AAMCK_DIV = 0
6182 22:17:45.608333 CA_ADMCK_DIV = 4
6183 22:17:45.611671 DQ_TRACK_CA_EN = 0
6184 22:17:45.612087 CA_PICK = 800
6185 22:17:45.614948 CA_MCKIO = 400
6186 22:17:45.618752 MCKIO_SEMI = 400
6187 22:17:45.621846 PLL_FREQ = 3016
6188 22:17:45.625063 DQ_UI_PI_RATIO = 32
6189 22:17:45.628066 CA_UI_PI_RATIO = 32
6190 22:17:45.631707 ===================================
6191 22:17:45.634698 ===================================
6192 22:17:45.637740 memory_type:LPDDR4
6193 22:17:45.638150 GP_NUM : 10
6194 22:17:45.641002 SRAM_EN : 1
6195 22:17:45.641415 MD32_EN : 0
6196 22:17:45.644457 ===================================
6197 22:17:45.648083 [ANA_INIT] >>>>>>>>>>>>>>
6198 22:17:45.651155 <<<<<< [CONFIGURE PHASE]: ANA_TX
6199 22:17:45.654329 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6200 22:17:45.657882 ===================================
6201 22:17:45.660690 data_rate = 800,PCW = 0X7400
6202 22:17:45.664245 ===================================
6203 22:17:45.667706 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6204 22:17:45.674162 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6205 22:17:45.683923 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6206 22:17:45.687293 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6207 22:17:45.691043 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6208 22:17:45.697139 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6209 22:17:45.697558 [ANA_INIT] flow start
6210 22:17:45.700486 [ANA_INIT] PLL >>>>>>>>
6211 22:17:45.704100 [ANA_INIT] PLL <<<<<<<<
6212 22:17:45.704553 [ANA_INIT] MIDPI >>>>>>>>
6213 22:17:45.707199 [ANA_INIT] MIDPI <<<<<<<<
6214 22:17:45.710698 [ANA_INIT] DLL >>>>>>>>
6215 22:17:45.711135 [ANA_INIT] flow end
6216 22:17:45.714096 ============ LP4 DIFF to SE enter ============
6217 22:17:45.720232 ============ LP4 DIFF to SE exit ============
6218 22:17:45.720690 [ANA_INIT] <<<<<<<<<<<<<
6219 22:17:45.724182 [Flow] Enable top DCM control >>>>>
6220 22:17:45.727006 [Flow] Enable top DCM control <<<<<
6221 22:17:45.730335 Enable DLL master slave shuffle
6222 22:17:45.737029 ==============================================================
6223 22:17:45.737450 Gating Mode config
6224 22:17:45.743425 ==============================================================
6225 22:17:45.747189 Config description:
6226 22:17:45.756709 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6227 22:17:45.763714 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6228 22:17:45.766505 SELPH_MODE 0: By rank 1: By Phase
6229 22:17:45.773077 ==============================================================
6230 22:17:45.776816 GAT_TRACK_EN = 0
6231 22:17:45.779571 RX_GATING_MODE = 2
6232 22:17:45.783231 RX_GATING_TRACK_MODE = 2
6233 22:17:45.783404 SELPH_MODE = 1
6234 22:17:45.786621 PICG_EARLY_EN = 1
6235 22:17:45.789672 VALID_LAT_VALUE = 1
6236 22:17:45.796013 ==============================================================
6237 22:17:45.799806 Enter into Gating configuration >>>>
6238 22:17:45.802813 Exit from Gating configuration <<<<
6239 22:17:45.806166 Enter into DVFS_PRE_config >>>>>
6240 22:17:45.816343 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6241 22:17:45.819508 Exit from DVFS_PRE_config <<<<<
6242 22:17:45.822730 Enter into PICG configuration >>>>
6243 22:17:45.825943 Exit from PICG configuration <<<<
6244 22:17:45.829066 [RX_INPUT] configuration >>>>>
6245 22:17:45.832696 [RX_INPUT] configuration <<<<<
6246 22:17:45.835610 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6247 22:17:45.842360 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6248 22:17:45.848693 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6249 22:17:45.855797 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6250 22:17:45.862225 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6251 22:17:45.868755 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6252 22:17:45.872306 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6253 22:17:45.875486 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6254 22:17:45.878389 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6255 22:17:45.885245 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6256 22:17:45.888832 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6257 22:17:45.892126 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6258 22:17:45.895345 ===================================
6259 22:17:45.899284 LPDDR4 DRAM CONFIGURATION
6260 22:17:45.902140 ===================================
6261 22:17:45.902549 EX_ROW_EN[0] = 0x0
6262 22:17:45.905161 EX_ROW_EN[1] = 0x0
6263 22:17:45.905822 LP4Y_EN = 0x0
6264 22:17:45.908570 WORK_FSP = 0x0
6265 22:17:45.911726 WL = 0x2
6266 22:17:45.912108 RL = 0x2
6267 22:17:45.915170 BL = 0x2
6268 22:17:45.915707 RPST = 0x0
6269 22:17:45.918436 RD_PRE = 0x0
6270 22:17:45.918794 WR_PRE = 0x1
6271 22:17:45.921750 WR_PST = 0x0
6272 22:17:45.922361 DBI_WR = 0x0
6273 22:17:45.925117 DBI_RD = 0x0
6274 22:17:45.925498 OTF = 0x1
6275 22:17:45.928844 ===================================
6276 22:17:45.931619 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6277 22:17:45.938192 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6278 22:17:45.941322 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6279 22:17:45.944867 ===================================
6280 22:17:45.947922 LPDDR4 DRAM CONFIGURATION
6281 22:17:45.951962 ===================================
6282 22:17:45.952739 EX_ROW_EN[0] = 0x10
6283 22:17:45.954465 EX_ROW_EN[1] = 0x0
6284 22:17:45.958084 LP4Y_EN = 0x0
6285 22:17:45.958508 WORK_FSP = 0x0
6286 22:17:45.961285 WL = 0x2
6287 22:17:45.961706 RL = 0x2
6288 22:17:45.964381 BL = 0x2
6289 22:17:45.964856 RPST = 0x0
6290 22:17:45.967732 RD_PRE = 0x0
6291 22:17:45.968153 WR_PRE = 0x1
6292 22:17:45.971045 WR_PST = 0x0
6293 22:17:45.971467 DBI_WR = 0x0
6294 22:17:45.974595 DBI_RD = 0x0
6295 22:17:45.975115 OTF = 0x1
6296 22:17:45.977901 ===================================
6297 22:17:45.984394 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6298 22:17:45.988384 nWR fixed to 30
6299 22:17:45.992311 [ModeRegInit_LP4] CH0 RK0
6300 22:17:45.992877 [ModeRegInit_LP4] CH0 RK1
6301 22:17:45.995042 [ModeRegInit_LP4] CH1 RK0
6302 22:17:45.998732 [ModeRegInit_LP4] CH1 RK1
6303 22:17:45.999245 match AC timing 19
6304 22:17:46.005193 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6305 22:17:46.008568 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6306 22:17:46.011364 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6307 22:17:46.018285 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6308 22:17:46.021778 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6309 22:17:46.022234 ==
6310 22:17:46.024804 Dram Type= 6, Freq= 0, CH_0, rank 0
6311 22:17:46.028306 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6312 22:17:46.028740 ==
6313 22:17:46.034514 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6314 22:17:46.041020 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6315 22:17:46.044662 [CA 0] Center 36 (8~64) winsize 57
6316 22:17:46.047619 [CA 1] Center 36 (8~64) winsize 57
6317 22:17:46.051048 [CA 2] Center 36 (8~64) winsize 57
6318 22:17:46.054126 [CA 3] Center 36 (8~64) winsize 57
6319 22:17:46.057301 [CA 4] Center 36 (8~64) winsize 57
6320 22:17:46.060686 [CA 5] Center 36 (8~64) winsize 57
6321 22:17:46.061103
6322 22:17:46.064312 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6323 22:17:46.064767
6324 22:17:46.067186 [CATrainingPosCal] consider 1 rank data
6325 22:17:46.070594 u2DelayCellTimex100 = 270/100 ps
6326 22:17:46.074037 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6327 22:17:46.077100 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6328 22:17:46.080670 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6329 22:17:46.084064 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6330 22:17:46.086921 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6331 22:17:46.090397 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6332 22:17:46.090810
6333 22:17:46.097490 CA PerBit enable=1, Macro0, CA PI delay=36
6334 22:17:46.098008
6335 22:17:46.100324 [CBTSetCACLKResult] CA Dly = 36
6336 22:17:46.100773 CS Dly: 1 (0~32)
6337 22:17:46.101099 ==
6338 22:17:46.103959 Dram Type= 6, Freq= 0, CH_0, rank 1
6339 22:17:46.106874 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6340 22:17:46.107293 ==
6341 22:17:46.113899 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6342 22:17:46.120293 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6343 22:17:46.123726 [CA 0] Center 36 (8~64) winsize 57
6344 22:17:46.126842 [CA 1] Center 36 (8~64) winsize 57
6345 22:17:46.130005 [CA 2] Center 36 (8~64) winsize 57
6346 22:17:46.133672 [CA 3] Center 36 (8~64) winsize 57
6347 22:17:46.136582 [CA 4] Center 36 (8~64) winsize 57
6348 22:17:46.139828 [CA 5] Center 36 (8~64) winsize 57
6349 22:17:46.140241
6350 22:17:46.143192 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6351 22:17:46.143610
6352 22:17:46.146202 [CATrainingPosCal] consider 2 rank data
6353 22:17:46.149777 u2DelayCellTimex100 = 270/100 ps
6354 22:17:46.152930 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6355 22:17:46.156344 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6356 22:17:46.159710 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6357 22:17:46.163353 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6358 22:17:46.166268 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6359 22:17:46.169580 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6360 22:17:46.169989
6361 22:17:46.173312 CA PerBit enable=1, Macro0, CA PI delay=36
6362 22:17:46.176593
6363 22:17:46.177004 [CBTSetCACLKResult] CA Dly = 36
6364 22:17:46.179720 CS Dly: 1 (0~32)
6365 22:17:46.180126
6366 22:17:46.183176 ----->DramcWriteLeveling(PI) begin...
6367 22:17:46.183587 ==
6368 22:17:46.186499 Dram Type= 6, Freq= 0, CH_0, rank 0
6369 22:17:46.189680 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6370 22:17:46.190088 ==
6371 22:17:46.192735 Write leveling (Byte 0): 40 => 8
6372 22:17:46.196075 Write leveling (Byte 1): 32 => 0
6373 22:17:46.199098 DramcWriteLeveling(PI) end<-----
6374 22:17:46.199500
6375 22:17:46.199814 ==
6376 22:17:46.202751 Dram Type= 6, Freq= 0, CH_0, rank 0
6377 22:17:46.206055 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6378 22:17:46.206526 ==
6379 22:17:46.209270 [Gating] SW mode calibration
6380 22:17:46.215981 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6381 22:17:46.222835 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6382 22:17:46.226017 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6383 22:17:46.232380 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6384 22:17:46.236231 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6385 22:17:46.239508 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6386 22:17:46.245794 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6387 22:17:46.248828 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6388 22:17:46.252286 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6389 22:17:46.259290 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6390 22:17:46.261918 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6391 22:17:46.265192 Total UI for P1: 0, mck2ui 16
6392 22:17:46.268815 best dqsien dly found for B0: ( 0, 14, 24)
6393 22:17:46.271981 Total UI for P1: 0, mck2ui 16
6394 22:17:46.276023 best dqsien dly found for B1: ( 0, 14, 24)
6395 22:17:46.278741 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6396 22:17:46.281652 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6397 22:17:46.282061
6398 22:17:46.285178 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6399 22:17:46.288430 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6400 22:17:46.291792 [Gating] SW calibration Done
6401 22:17:46.292214 ==
6402 22:17:46.294946 Dram Type= 6, Freq= 0, CH_0, rank 0
6403 22:17:46.301848 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6404 22:17:46.302261 ==
6405 22:17:46.302585 RX Vref Scan: 0
6406 22:17:46.302885
6407 22:17:46.305047 RX Vref 0 -> 0, step: 1
6408 22:17:46.305460
6409 22:17:46.308633 RX Delay -410 -> 252, step: 16
6410 22:17:46.311421 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6411 22:17:46.315017 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6412 22:17:46.321611 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6413 22:17:46.325160 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6414 22:17:46.328382 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6415 22:17:46.331212 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6416 22:17:46.337858 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6417 22:17:46.341044 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6418 22:17:46.344623 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6419 22:17:46.348130 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6420 22:17:46.354351 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6421 22:17:46.357921 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6422 22:17:46.361330 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6423 22:17:46.364272 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6424 22:17:46.371467 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6425 22:17:46.374074 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6426 22:17:46.374260 ==
6427 22:17:46.377689 Dram Type= 6, Freq= 0, CH_0, rank 0
6428 22:17:46.380755 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6429 22:17:46.380973 ==
6430 22:17:46.384249 DQS Delay:
6431 22:17:46.384712 DQS0 = 43, DQS1 = 59
6432 22:17:46.387648 DQM Delay:
6433 22:17:46.388067 DQM0 = 9, DQM1 = 12
6434 22:17:46.388396 DQ Delay:
6435 22:17:46.390881 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =0
6436 22:17:46.394366 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6437 22:17:46.397682 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6438 22:17:46.401117 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6439 22:17:46.401539
6440 22:17:46.401864
6441 22:17:46.402171 ==
6442 22:17:46.404181 Dram Type= 6, Freq= 0, CH_0, rank 0
6443 22:17:46.410762 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6444 22:17:46.411188 ==
6445 22:17:46.411521
6446 22:17:46.411826
6447 22:17:46.412120 TX Vref Scan disable
6448 22:17:46.413957 == TX Byte 0 ==
6449 22:17:46.417668 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6450 22:17:46.420543 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6451 22:17:46.423895 == TX Byte 1 ==
6452 22:17:46.427274 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6453 22:17:46.430647 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6454 22:17:46.434139 ==
6455 22:17:46.434561 Dram Type= 6, Freq= 0, CH_0, rank 0
6456 22:17:46.440076 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6457 22:17:46.440501 ==
6458 22:17:46.440870
6459 22:17:46.441179
6460 22:17:46.443980 TX Vref Scan disable
6461 22:17:46.444399 == TX Byte 0 ==
6462 22:17:46.446892 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6463 22:17:46.453426 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6464 22:17:46.453848 == TX Byte 1 ==
6465 22:17:46.457017 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6466 22:17:46.463580 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6467 22:17:46.464138
6468 22:17:46.464585 [DATLAT]
6469 22:17:46.465071 Freq=400, CH0 RK0
6470 22:17:46.465406
6471 22:17:46.466868 DATLAT Default: 0xf
6472 22:17:46.467288 0, 0xFFFF, sum = 0
6473 22:17:46.470073 1, 0xFFFF, sum = 0
6474 22:17:46.473704 2, 0xFFFF, sum = 0
6475 22:17:46.474242 3, 0xFFFF, sum = 0
6476 22:17:46.476480 4, 0xFFFF, sum = 0
6477 22:17:46.476950 5, 0xFFFF, sum = 0
6478 22:17:46.480379 6, 0xFFFF, sum = 0
6479 22:17:46.480867 7, 0xFFFF, sum = 0
6480 22:17:46.483184 8, 0xFFFF, sum = 0
6481 22:17:46.483720 9, 0xFFFF, sum = 0
6482 22:17:46.486665 10, 0xFFFF, sum = 0
6483 22:17:46.487324 11, 0xFFFF, sum = 0
6484 22:17:46.490418 12, 0xFFFF, sum = 0
6485 22:17:46.490949 13, 0x0, sum = 1
6486 22:17:46.493279 14, 0x0, sum = 2
6487 22:17:46.493705 15, 0x0, sum = 3
6488 22:17:46.496189 16, 0x0, sum = 4
6489 22:17:46.496646 best_step = 14
6490 22:17:46.496981
6491 22:17:46.497290 ==
6492 22:17:46.500290 Dram Type= 6, Freq= 0, CH_0, rank 0
6493 22:17:46.506713 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6494 22:17:46.507229 ==
6495 22:17:46.507568 RX Vref Scan: 1
6496 22:17:46.507875
6497 22:17:46.510046 RX Vref 0 -> 0, step: 1
6498 22:17:46.510469
6499 22:17:46.513176 RX Delay -359 -> 252, step: 8
6500 22:17:46.513693
6501 22:17:46.515949 Set Vref, RX VrefLevel [Byte0]: 57
6502 22:17:46.519611 [Byte1]: 60
6503 22:17:46.520130
6504 22:17:46.522759 Final RX Vref Byte 0 = 57 to rank0
6505 22:17:46.526634 Final RX Vref Byte 1 = 60 to rank0
6506 22:17:46.529615 Final RX Vref Byte 0 = 57 to rank1
6507 22:17:46.532706 Final RX Vref Byte 1 = 60 to rank1==
6508 22:17:46.536175 Dram Type= 6, Freq= 0, CH_0, rank 0
6509 22:17:46.542842 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6510 22:17:46.543406 ==
6511 22:17:46.543778 DQS Delay:
6512 22:17:46.546030 DQS0 = 44, DQS1 = 60
6513 22:17:46.546589 DQM Delay:
6514 22:17:46.546956 DQM0 = 8, DQM1 = 11
6515 22:17:46.548836 DQ Delay:
6516 22:17:46.552695 DQ0 =8, DQ1 =8, DQ2 =4, DQ3 =4
6517 22:17:46.553253 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6518 22:17:46.555453 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6519 22:17:46.559223 DQ12 =16, DQ13 =16, DQ14 =20, DQ15 =20
6520 22:17:46.559778
6521 22:17:46.560145
6522 22:17:46.568908 [DQSOSCAuto] RK0, (LSB)MR18= 0xb87b, (MSB)MR19= 0xc0c, tDQSOscB0 = 394 ps tDQSOscB1 = 386 ps
6523 22:17:46.572106 CH0 RK0: MR19=C0C, MR18=B87B
6524 22:17:46.578526 CH0_RK0: MR19=0xC0C, MR18=0xB87B, DQSOSC=386, MR23=63, INC=396, DEC=264
6525 22:17:46.578993 ==
6526 22:17:46.582505 Dram Type= 6, Freq= 0, CH_0, rank 1
6527 22:17:46.585084 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6528 22:17:46.585659 ==
6529 22:17:46.588266 [Gating] SW mode calibration
6530 22:17:46.595467 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6531 22:17:46.601929 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6532 22:17:46.605404 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6533 22:17:46.608868 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6534 22:17:46.615285 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6535 22:17:46.618803 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6536 22:17:46.621592 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6537 22:17:46.628218 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6538 22:17:46.631628 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6539 22:17:46.635104 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6540 22:17:46.641602 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6541 22:17:46.642160 Total UI for P1: 0, mck2ui 16
6542 22:17:46.644596 best dqsien dly found for B0: ( 0, 14, 24)
6543 22:17:46.648470 Total UI for P1: 0, mck2ui 16
6544 22:17:46.651525 best dqsien dly found for B1: ( 0, 14, 24)
6545 22:17:46.658151 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6546 22:17:46.661091 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6547 22:17:46.661546
6548 22:17:46.664881 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6549 22:17:46.668045 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6550 22:17:46.671569 [Gating] SW calibration Done
6551 22:17:46.672140 ==
6552 22:17:46.674755 Dram Type= 6, Freq= 0, CH_0, rank 1
6553 22:17:46.677948 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6554 22:17:46.678540 ==
6555 22:17:46.681145 RX Vref Scan: 0
6556 22:17:46.681653
6557 22:17:46.682011 RX Vref 0 -> 0, step: 1
6558 22:17:46.682344
6559 22:17:46.684890 RX Delay -410 -> 252, step: 16
6560 22:17:46.691020 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6561 22:17:46.694396 iDelay=230, Bit 1, Center -27 (-282 ~ 229) 512
6562 22:17:46.697496 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6563 22:17:46.700934 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6564 22:17:46.707337 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6565 22:17:46.710827 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6566 22:17:46.713983 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6567 22:17:46.717429 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6568 22:17:46.724981 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6569 22:17:46.727251 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6570 22:17:46.730872 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6571 22:17:46.734514 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6572 22:17:46.740686 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6573 22:17:46.744250 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6574 22:17:46.747743 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6575 22:17:46.754594 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6576 22:17:46.755175 ==
6577 22:17:46.757234 Dram Type= 6, Freq= 0, CH_0, rank 1
6578 22:17:46.760910 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6579 22:17:46.761483 ==
6580 22:17:46.761957 DQS Delay:
6581 22:17:46.764323 DQS0 = 43, DQS1 = 59
6582 22:17:46.764823 DQM Delay:
6583 22:17:46.767375 DQM0 = 11, DQM1 = 15
6584 22:17:46.767980 DQ Delay:
6585 22:17:46.771096 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6586 22:17:46.773728 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =24
6587 22:17:46.777269 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6588 22:17:46.780633 DQ12 =16, DQ13 =24, DQ14 =24, DQ15 =24
6589 22:17:46.781189
6590 22:17:46.781554
6591 22:17:46.781893 ==
6592 22:17:46.783288 Dram Type= 6, Freq= 0, CH_0, rank 1
6593 22:17:46.787161 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6594 22:17:46.787734 ==
6595 22:17:46.788105
6596 22:17:46.788441
6597 22:17:46.790035 TX Vref Scan disable
6598 22:17:46.790586 == TX Byte 0 ==
6599 22:17:46.796885 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6600 22:17:46.799906 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6601 22:17:46.800469 == TX Byte 1 ==
6602 22:17:46.806786 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6603 22:17:46.809808 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6604 22:17:46.810277 ==
6605 22:17:46.813317 Dram Type= 6, Freq= 0, CH_0, rank 1
6606 22:17:46.816450 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6607 22:17:46.816917 ==
6608 22:17:46.817251
6609 22:17:46.817555
6610 22:17:46.819768 TX Vref Scan disable
6611 22:17:46.823338 == TX Byte 0 ==
6612 22:17:46.826924 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6613 22:17:46.829465 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6614 22:17:46.832868 == TX Byte 1 ==
6615 22:17:46.836442 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6616 22:17:46.839567 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6617 22:17:46.840080
6618 22:17:46.840415 [DATLAT]
6619 22:17:46.843131 Freq=400, CH0 RK1
6620 22:17:46.843641
6621 22:17:46.843974 DATLAT Default: 0xe
6622 22:17:46.846315 0, 0xFFFF, sum = 0
6623 22:17:46.846743 1, 0xFFFF, sum = 0
6624 22:17:46.849210 2, 0xFFFF, sum = 0
6625 22:17:46.852872 3, 0xFFFF, sum = 0
6626 22:17:46.853291 4, 0xFFFF, sum = 0
6627 22:17:46.856170 5, 0xFFFF, sum = 0
6628 22:17:46.856724 6, 0xFFFF, sum = 0
6629 22:17:46.859436 7, 0xFFFF, sum = 0
6630 22:17:46.859959 8, 0xFFFF, sum = 0
6631 22:17:46.862405 9, 0xFFFF, sum = 0
6632 22:17:46.862863 10, 0xFFFF, sum = 0
6633 22:17:46.865996 11, 0xFFFF, sum = 0
6634 22:17:46.866459 12, 0xFFFF, sum = 0
6635 22:17:46.868884 13, 0x0, sum = 1
6636 22:17:46.869497 14, 0x0, sum = 2
6637 22:17:46.872459 15, 0x0, sum = 3
6638 22:17:46.872876 16, 0x0, sum = 4
6639 22:17:46.875956 best_step = 14
6640 22:17:46.876365
6641 22:17:46.876729 ==
6642 22:17:46.879452 Dram Type= 6, Freq= 0, CH_0, rank 1
6643 22:17:46.882970 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6644 22:17:46.883487 ==
6645 22:17:46.886359 RX Vref Scan: 0
6646 22:17:46.886870
6647 22:17:46.887195 RX Vref 0 -> 0, step: 1
6648 22:17:46.887501
6649 22:17:46.889082 RX Delay -359 -> 252, step: 8
6650 22:17:46.896641 iDelay=217, Bit 0, Center -40 (-279 ~ 200) 480
6651 22:17:46.899931 iDelay=217, Bit 1, Center -36 (-279 ~ 208) 488
6652 22:17:46.903204 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6653 22:17:46.909649 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6654 22:17:46.913976 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6655 22:17:46.916418 iDelay=217, Bit 5, Center -44 (-287 ~ 200) 488
6656 22:17:46.919819 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6657 22:17:46.926218 iDelay=217, Bit 7, Center -28 (-271 ~ 216) 488
6658 22:17:46.929193 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
6659 22:17:46.932866 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6660 22:17:46.936303 iDelay=217, Bit 10, Center -40 (-287 ~ 208) 496
6661 22:17:46.942736 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6662 22:17:46.946245 iDelay=217, Bit 12, Center -40 (-287 ~ 208) 496
6663 22:17:46.948866 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6664 22:17:46.955960 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6665 22:17:46.959156 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6666 22:17:46.959624 ==
6667 22:17:46.962223 Dram Type= 6, Freq= 0, CH_0, rank 1
6668 22:17:46.965920 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6669 22:17:46.966454 ==
6670 22:17:46.968741 DQS Delay:
6671 22:17:46.969213 DQS0 = 44, DQS1 = 60
6672 22:17:46.969571 DQM Delay:
6673 22:17:46.972275 DQM0 = 8, DQM1 = 14
6674 22:17:46.972932 DQ Delay:
6675 22:17:46.975533 DQ0 =4, DQ1 =8, DQ2 =4, DQ3 =8
6676 22:17:46.979166 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6677 22:17:46.982146 DQ8 =4, DQ9 =0, DQ10 =20, DQ11 =8
6678 22:17:46.985635 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =20
6679 22:17:46.986190
6680 22:17:46.986551
6681 22:17:46.995413 [DQSOSCAuto] RK1, (LSB)MR18= 0xb23d, (MSB)MR19= 0xc0c, tDQSOscB0 = 402 ps tDQSOscB1 = 387 ps
6682 22:17:46.995975 CH0 RK1: MR19=C0C, MR18=B23D
6683 22:17:47.001756 CH0_RK1: MR19=0xC0C, MR18=0xB23D, DQSOSC=387, MR23=63, INC=394, DEC=262
6684 22:17:47.004913 [RxdqsGatingPostProcess] freq 400
6685 22:17:47.011497 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6686 22:17:47.014655 best DQS0 dly(2T, 0.5T) = (0, 10)
6687 22:17:47.018719 best DQS1 dly(2T, 0.5T) = (0, 10)
6688 22:17:47.021424 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6689 22:17:47.024825 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6690 22:17:47.028558 best DQS0 dly(2T, 0.5T) = (0, 10)
6691 22:17:47.031730 best DQS1 dly(2T, 0.5T) = (0, 10)
6692 22:17:47.034532 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6693 22:17:47.037908 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6694 22:17:47.038369 Pre-setting of DQS Precalculation
6695 22:17:47.044586 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6696 22:17:47.045162 ==
6697 22:17:47.047610 Dram Type= 6, Freq= 0, CH_1, rank 0
6698 22:17:47.051571 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6699 22:17:47.052033 ==
6700 22:17:47.057916 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6701 22:17:47.064800 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6702 22:17:47.067489 [CA 0] Center 36 (8~64) winsize 57
6703 22:17:47.072018 [CA 1] Center 36 (8~64) winsize 57
6704 22:17:47.073957 [CA 2] Center 36 (8~64) winsize 57
6705 22:17:47.077688 [CA 3] Center 36 (8~64) winsize 57
6706 22:17:47.078112 [CA 4] Center 36 (8~64) winsize 57
6707 22:17:47.080996 [CA 5] Center 36 (8~64) winsize 57
6708 22:17:47.081423
6709 22:17:47.087417 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6710 22:17:47.087839
6711 22:17:47.090744 [CATrainingPosCal] consider 1 rank data
6712 22:17:47.094278 u2DelayCellTimex100 = 270/100 ps
6713 22:17:47.097420 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6714 22:17:47.100662 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6715 22:17:47.104347 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6716 22:17:47.107643 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6717 22:17:47.110582 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6718 22:17:47.114403 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6719 22:17:47.114554
6720 22:17:47.116961 CA PerBit enable=1, Macro0, CA PI delay=36
6721 22:17:47.117111
6722 22:17:47.120563 [CBTSetCACLKResult] CA Dly = 36
6723 22:17:47.124346 CS Dly: 1 (0~32)
6724 22:17:47.124458 ==
6725 22:17:47.127020 Dram Type= 6, Freq= 0, CH_1, rank 1
6726 22:17:47.130523 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6727 22:17:47.130657 ==
6728 22:17:47.137613 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6729 22:17:47.144003 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6730 22:17:47.144096 [CA 0] Center 36 (8~64) winsize 57
6731 22:17:47.146871 [CA 1] Center 36 (8~64) winsize 57
6732 22:17:47.150319 [CA 2] Center 36 (8~64) winsize 57
6733 22:17:47.153573 [CA 3] Center 36 (8~64) winsize 57
6734 22:17:47.156635 [CA 4] Center 36 (8~64) winsize 57
6735 22:17:47.159928 [CA 5] Center 36 (8~64) winsize 57
6736 22:17:47.160011
6737 22:17:47.163386 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6738 22:17:47.163468
6739 22:17:47.169726 [CATrainingPosCal] consider 2 rank data
6740 22:17:47.169816 u2DelayCellTimex100 = 270/100 ps
6741 22:17:47.176178 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6742 22:17:47.179440 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6743 22:17:47.183047 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6744 22:17:47.186326 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6745 22:17:47.189154 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6746 22:17:47.192654 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6747 22:17:47.192738
6748 22:17:47.196225 CA PerBit enable=1, Macro0, CA PI delay=36
6749 22:17:47.196306
6750 22:17:47.199326 [CBTSetCACLKResult] CA Dly = 36
6751 22:17:47.203226 CS Dly: 1 (0~32)
6752 22:17:47.203309
6753 22:17:47.205697 ----->DramcWriteLeveling(PI) begin...
6754 22:17:47.205781 ==
6755 22:17:47.209049 Dram Type= 6, Freq= 0, CH_1, rank 0
6756 22:17:47.212333 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6757 22:17:47.212441 ==
6758 22:17:47.215948 Write leveling (Byte 0): 40 => 8
6759 22:17:47.219130 Write leveling (Byte 1): 32 => 0
6760 22:17:47.222933 DramcWriteLeveling(PI) end<-----
6761 22:17:47.223015
6762 22:17:47.223078 ==
6763 22:17:47.225883 Dram Type= 6, Freq= 0, CH_1, rank 0
6764 22:17:47.229011 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6765 22:17:47.229094 ==
6766 22:17:47.232489 [Gating] SW mode calibration
6767 22:17:47.239525 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6768 22:17:47.245428 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6769 22:17:47.249088 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6770 22:17:47.251958 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6771 22:17:47.258571 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6772 22:17:47.262450 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6773 22:17:47.265362 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6774 22:17:47.271685 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6775 22:17:47.275664 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6776 22:17:47.278475 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6777 22:17:47.285196 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6778 22:17:47.288215 Total UI for P1: 0, mck2ui 16
6779 22:17:47.291344 best dqsien dly found for B0: ( 0, 14, 24)
6780 22:17:47.294908 Total UI for P1: 0, mck2ui 16
6781 22:17:47.297987 best dqsien dly found for B1: ( 0, 14, 24)
6782 22:17:47.301376 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6783 22:17:47.304785 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6784 22:17:47.304868
6785 22:17:47.308691 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6786 22:17:47.311987 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6787 22:17:47.314712 [Gating] SW calibration Done
6788 22:17:47.314795 ==
6789 22:17:47.318329 Dram Type= 6, Freq= 0, CH_1, rank 0
6790 22:17:47.321548 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6791 22:17:47.321632 ==
6792 22:17:47.325028 RX Vref Scan: 0
6793 22:17:47.325111
6794 22:17:47.328503 RX Vref 0 -> 0, step: 1
6795 22:17:47.328595
6796 22:17:47.328659 RX Delay -410 -> 252, step: 16
6797 22:17:47.334975 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6798 22:17:47.338103 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6799 22:17:47.341699 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6800 22:17:47.348816 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6801 22:17:47.351146 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6802 22:17:47.354518 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6803 22:17:47.357748 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6804 22:17:47.364225 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6805 22:17:47.367628 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6806 22:17:47.371571 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6807 22:17:47.374149 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6808 22:17:47.381536 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6809 22:17:47.384224 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6810 22:17:47.387504 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6811 22:17:47.390864 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6812 22:17:47.397759 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6813 22:17:47.397841 ==
6814 22:17:47.401074 Dram Type= 6, Freq= 0, CH_1, rank 0
6815 22:17:47.403926 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6816 22:17:47.404009 ==
6817 22:17:47.404074 DQS Delay:
6818 22:17:47.407351 DQS0 = 43, DQS1 = 51
6819 22:17:47.407433 DQM Delay:
6820 22:17:47.410574 DQM0 = 12, DQM1 = 14
6821 22:17:47.410656 DQ Delay:
6822 22:17:47.414509 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6823 22:17:47.417618 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6824 22:17:47.420940 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =0
6825 22:17:47.423534 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6826 22:17:47.423616
6827 22:17:47.423679
6828 22:17:47.423739 ==
6829 22:17:47.426840 Dram Type= 6, Freq= 0, CH_1, rank 0
6830 22:17:47.430489 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6831 22:17:47.430572 ==
6832 22:17:47.430636
6833 22:17:47.433843
6834 22:17:47.433924 TX Vref Scan disable
6835 22:17:47.436977 == TX Byte 0 ==
6836 22:17:47.440353 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6837 22:17:47.443728 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6838 22:17:47.446873 == TX Byte 1 ==
6839 22:17:47.450461 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6840 22:17:47.453390 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6841 22:17:47.453472 ==
6842 22:17:47.456870 Dram Type= 6, Freq= 0, CH_1, rank 0
6843 22:17:47.460284 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6844 22:17:47.463699 ==
6845 22:17:47.463781
6846 22:17:47.463846
6847 22:17:47.463905 TX Vref Scan disable
6848 22:17:47.466966 == TX Byte 0 ==
6849 22:17:47.470137 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6850 22:17:47.473382 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6851 22:17:47.476667 == TX Byte 1 ==
6852 22:17:47.480021 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6853 22:17:47.483638 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6854 22:17:47.483721
6855 22:17:47.486635 [DATLAT]
6856 22:17:47.486718 Freq=400, CH1 RK0
6857 22:17:47.486783
6858 22:17:47.490209 DATLAT Default: 0xf
6859 22:17:47.490291 0, 0xFFFF, sum = 0
6860 22:17:47.493121 1, 0xFFFF, sum = 0
6861 22:17:47.493204 2, 0xFFFF, sum = 0
6862 22:17:47.496861 3, 0xFFFF, sum = 0
6863 22:17:47.496943 4, 0xFFFF, sum = 0
6864 22:17:47.499436 5, 0xFFFF, sum = 0
6865 22:17:47.499519 6, 0xFFFF, sum = 0
6866 22:17:47.503479 7, 0xFFFF, sum = 0
6867 22:17:47.503561 8, 0xFFFF, sum = 0
6868 22:17:47.506730 9, 0xFFFF, sum = 0
6869 22:17:47.509453 10, 0xFFFF, sum = 0
6870 22:17:47.509536 11, 0xFFFF, sum = 0
6871 22:17:47.513011 12, 0xFFFF, sum = 0
6872 22:17:47.513095 13, 0x0, sum = 1
6873 22:17:47.516197 14, 0x0, sum = 2
6874 22:17:47.516280 15, 0x0, sum = 3
6875 22:17:47.516346 16, 0x0, sum = 4
6876 22:17:47.519384 best_step = 14
6877 22:17:47.519466
6878 22:17:47.519530 ==
6879 22:17:47.523144 Dram Type= 6, Freq= 0, CH_1, rank 0
6880 22:17:47.526114 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6881 22:17:47.526196 ==
6882 22:17:47.529973 RX Vref Scan: 1
6883 22:17:47.530055
6884 22:17:47.532313 RX Vref 0 -> 0, step: 1
6885 22:17:47.532395
6886 22:17:47.532459 RX Delay -343 -> 252, step: 8
6887 22:17:47.532527
6888 22:17:47.535665 Set Vref, RX VrefLevel [Byte0]: 53
6889 22:17:47.538959 [Byte1]: 51
6890 22:17:47.545091
6891 22:17:47.545173 Final RX Vref Byte 0 = 53 to rank0
6892 22:17:47.548140 Final RX Vref Byte 1 = 51 to rank0
6893 22:17:47.551404 Final RX Vref Byte 0 = 53 to rank1
6894 22:17:47.554491 Final RX Vref Byte 1 = 51 to rank1==
6895 22:17:47.557926 Dram Type= 6, Freq= 0, CH_1, rank 0
6896 22:17:47.564590 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6897 22:17:47.564676 ==
6898 22:17:47.564741 DQS Delay:
6899 22:17:47.567481 DQS0 = 48, DQS1 = 56
6900 22:17:47.567563 DQM Delay:
6901 22:17:47.567628 DQM0 = 12, DQM1 = 12
6902 22:17:47.571058 DQ Delay:
6903 22:17:47.574346 DQ0 =20, DQ1 =8, DQ2 =0, DQ3 =12
6904 22:17:47.577930 DQ4 =8, DQ5 =24, DQ6 =20, DQ7 =4
6905 22:17:47.578034 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6906 22:17:47.584030 DQ12 =24, DQ13 =16, DQ14 =20, DQ15 =20
6907 22:17:47.584115
6908 22:17:47.584180
6909 22:17:47.590896 [DQSOSCAuto] RK0, (LSB)MR18= 0x9971, (MSB)MR19= 0xc0c, tDQSOscB0 = 395 ps tDQSOscB1 = 390 ps
6910 22:17:47.593824 CH1 RK0: MR19=C0C, MR18=9971
6911 22:17:47.600964 CH1_RK0: MR19=0xC0C, MR18=0x9971, DQSOSC=390, MR23=63, INC=388, DEC=258
6912 22:17:47.601048 ==
6913 22:17:47.603896 Dram Type= 6, Freq= 0, CH_1, rank 1
6914 22:17:47.607432 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6915 22:17:47.607543 ==
6916 22:17:47.610270 [Gating] SW mode calibration
6917 22:17:47.617169 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6918 22:17:47.623490 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6919 22:17:47.626696 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6920 22:17:47.629922 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6921 22:17:47.636555 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6922 22:17:47.640110 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6923 22:17:47.643116 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6924 22:17:47.650106 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6925 22:17:47.652972 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6926 22:17:47.656259 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6927 22:17:47.662895 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6928 22:17:47.667046 Total UI for P1: 0, mck2ui 16
6929 22:17:47.669436 best dqsien dly found for B0: ( 0, 14, 24)
6930 22:17:47.673540 Total UI for P1: 0, mck2ui 16
6931 22:17:47.676280 best dqsien dly found for B1: ( 0, 14, 24)
6932 22:17:47.679786 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6933 22:17:47.682997 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6934 22:17:47.683080
6935 22:17:47.686533 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6936 22:17:47.689655 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6937 22:17:47.693024 [Gating] SW calibration Done
6938 22:17:47.693136 ==
6939 22:17:47.696224 Dram Type= 6, Freq= 0, CH_1, rank 1
6940 22:17:47.699705 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6941 22:17:47.699789 ==
6942 22:17:47.702881 RX Vref Scan: 0
6943 22:17:47.702963
6944 22:17:47.706430 RX Vref 0 -> 0, step: 1
6945 22:17:47.706512
6946 22:17:47.706577 RX Delay -410 -> 252, step: 16
6947 22:17:47.712961 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6948 22:17:47.716132 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6949 22:17:47.719913 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6950 22:17:47.726758 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6951 22:17:47.729705 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6952 22:17:47.732931 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6953 22:17:47.735993 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6954 22:17:47.742613 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6955 22:17:47.746085 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6956 22:17:47.749954 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6957 22:17:47.752328 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6958 22:17:47.759371 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6959 22:17:47.762395 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6960 22:17:47.766551 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6961 22:17:47.768683 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6962 22:17:47.775681 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6963 22:17:47.775924 ==
6964 22:17:47.779151 Dram Type= 6, Freq= 0, CH_1, rank 1
6965 22:17:47.782843 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6966 22:17:47.783054 ==
6967 22:17:47.783210 DQS Delay:
6968 22:17:47.785568 DQS0 = 43, DQS1 = 51
6969 22:17:47.785767 DQM Delay:
6970 22:17:47.788859 DQM0 = 12, DQM1 = 14
6971 22:17:47.789097 DQ Delay:
6972 22:17:47.792381 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6973 22:17:47.796059 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6974 22:17:47.798439 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =0
6975 22:17:47.802030 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6976 22:17:47.802201
6977 22:17:47.802327
6978 22:17:47.802434 ==
6979 22:17:47.805485 Dram Type= 6, Freq= 0, CH_1, rank 1
6980 22:17:47.808371 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6981 22:17:47.808571 ==
6982 22:17:47.812012
6983 22:17:47.812180
6984 22:17:47.812307 TX Vref Scan disable
6985 22:17:47.815249 == TX Byte 0 ==
6986 22:17:47.818412 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6987 22:17:47.821798 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6988 22:17:47.824643 == TX Byte 1 ==
6989 22:17:47.828863 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6990 22:17:47.831562 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6991 22:17:47.831736 ==
6992 22:17:47.835411 Dram Type= 6, Freq= 0, CH_1, rank 1
6993 22:17:47.841387 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6994 22:17:47.841560 ==
6995 22:17:47.841646
6996 22:17:47.841719
6997 22:17:47.841788 TX Vref Scan disable
6998 22:17:47.844324 == TX Byte 0 ==
6999 22:17:47.848065 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
7000 22:17:47.851487 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
7001 22:17:47.855200 == TX Byte 1 ==
7002 22:17:47.857861 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
7003 22:17:47.860879 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
7004 22:17:47.861052
7005 22:17:47.864205 [DATLAT]
7006 22:17:47.864693 Freq=400, CH1 RK1
7007 22:17:47.865029
7008 22:17:47.867742 DATLAT Default: 0xe
7009 22:17:47.868157 0, 0xFFFF, sum = 0
7010 22:17:47.870788 1, 0xFFFF, sum = 0
7011 22:17:47.871380 2, 0xFFFF, sum = 0
7012 22:17:47.874214 3, 0xFFFF, sum = 0
7013 22:17:47.874636 4, 0xFFFF, sum = 0
7014 22:17:47.877630 5, 0xFFFF, sum = 0
7015 22:17:47.878054 6, 0xFFFF, sum = 0
7016 22:17:47.880759 7, 0xFFFF, sum = 0
7017 22:17:47.881176 8, 0xFFFF, sum = 0
7018 22:17:47.883979 9, 0xFFFF, sum = 0
7019 22:17:47.887287 10, 0xFFFF, sum = 0
7020 22:17:47.887711 11, 0xFFFF, sum = 0
7021 22:17:47.890555 12, 0xFFFF, sum = 0
7022 22:17:47.890980 13, 0x0, sum = 1
7023 22:17:47.894304 14, 0x0, sum = 2
7024 22:17:47.894726 15, 0x0, sum = 3
7025 22:17:47.897308 16, 0x0, sum = 4
7026 22:17:47.897736 best_step = 14
7027 22:17:47.898069
7028 22:17:47.898378 ==
7029 22:17:47.900299 Dram Type= 6, Freq= 0, CH_1, rank 1
7030 22:17:47.904622 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7031 22:17:47.905147 ==
7032 22:17:47.907162 RX Vref Scan: 0
7033 22:17:47.907581
7034 22:17:47.910551 RX Vref 0 -> 0, step: 1
7035 22:17:47.910970
7036 22:17:47.911299 RX Delay -343 -> 252, step: 8
7037 22:17:47.919330 iDelay=225, Bit 0, Center -28 (-271 ~ 216) 488
7038 22:17:47.922767 iDelay=225, Bit 1, Center -44 (-287 ~ 200) 488
7039 22:17:47.925884 iDelay=225, Bit 2, Center -48 (-295 ~ 200) 496
7040 22:17:47.929425 iDelay=225, Bit 3, Center -40 (-279 ~ 200) 480
7041 22:17:47.935821 iDelay=225, Bit 4, Center -40 (-287 ~ 208) 496
7042 22:17:47.938999 iDelay=225, Bit 5, Center -28 (-271 ~ 216) 488
7043 22:17:47.942770 iDelay=225, Bit 6, Center -24 (-271 ~ 224) 496
7044 22:17:47.946081 iDelay=225, Bit 7, Center -40 (-287 ~ 208) 496
7045 22:17:47.952233 iDelay=225, Bit 8, Center -56 (-303 ~ 192) 496
7046 22:17:47.955515 iDelay=225, Bit 9, Center -56 (-303 ~ 192) 496
7047 22:17:47.959033 iDelay=225, Bit 10, Center -48 (-295 ~ 200) 496
7048 22:17:47.965627 iDelay=225, Bit 11, Center -52 (-295 ~ 192) 488
7049 22:17:47.968822 iDelay=225, Bit 12, Center -36 (-287 ~ 216) 504
7050 22:17:47.972097 iDelay=225, Bit 13, Center -36 (-279 ~ 208) 488
7051 22:17:47.976156 iDelay=225, Bit 14, Center -36 (-279 ~ 208) 488
7052 22:17:47.982359 iDelay=225, Bit 15, Center -32 (-279 ~ 216) 496
7053 22:17:47.982875 ==
7054 22:17:47.985923 Dram Type= 6, Freq= 0, CH_1, rank 1
7055 22:17:47.989122 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7056 22:17:47.989636 ==
7057 22:17:47.989972 DQS Delay:
7058 22:17:47.992637 DQS0 = 48, DQS1 = 56
7059 22:17:47.993058 DQM Delay:
7060 22:17:47.995462 DQM0 = 11, DQM1 = 12
7061 22:17:47.995984 DQ Delay:
7062 22:17:47.999525 DQ0 =20, DQ1 =4, DQ2 =0, DQ3 =8
7063 22:17:48.001794 DQ4 =8, DQ5 =20, DQ6 =24, DQ7 =8
7064 22:17:48.005278 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =4
7065 22:17:48.008427 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =24
7066 22:17:48.008873
7067 22:17:48.009200
7068 22:17:48.015116 [DQSOSCAuto] RK1, (LSB)MR18= 0x6958, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 396 ps
7069 22:17:48.018449 CH1 RK1: MR19=C0C, MR18=6958
7070 22:17:48.025195 CH1_RK1: MR19=0xC0C, MR18=0x6958, DQSOSC=396, MR23=63, INC=376, DEC=251
7071 22:17:48.028258 [RxdqsGatingPostProcess] freq 400
7072 22:17:48.035300 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7073 22:17:48.038412 best DQS0 dly(2T, 0.5T) = (0, 10)
7074 22:17:48.041996 best DQS1 dly(2T, 0.5T) = (0, 10)
7075 22:17:48.045079 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7076 22:17:48.048117 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7077 22:17:48.048663 best DQS0 dly(2T, 0.5T) = (0, 10)
7078 22:17:48.051863 best DQS1 dly(2T, 0.5T) = (0, 10)
7079 22:17:48.054820 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7080 22:17:48.058212 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7081 22:17:48.062074 Pre-setting of DQS Precalculation
7082 22:17:48.067978 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7083 22:17:48.075047 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7084 22:17:48.081426 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7085 22:17:48.081943
7086 22:17:48.082270
7087 22:17:48.084744 [Calibration Summary] 800 Mbps
7088 22:17:48.085260 CH 0, Rank 0
7089 22:17:48.087831 SW Impedance : PASS
7090 22:17:48.092038 DUTY Scan : NO K
7091 22:17:48.092593 ZQ Calibration : PASS
7092 22:17:48.094487 Jitter Meter : NO K
7093 22:17:48.097925 CBT Training : PASS
7094 22:17:48.098434 Write leveling : PASS
7095 22:17:48.100740 RX DQS gating : PASS
7096 22:17:48.104494 RX DQ/DQS(RDDQC) : PASS
7097 22:17:48.104944 TX DQ/DQS : PASS
7098 22:17:48.107495 RX DATLAT : PASS
7099 22:17:48.111969 RX DQ/DQS(Engine): PASS
7100 22:17:48.112382 TX OE : NO K
7101 22:17:48.113966 All Pass.
7102 22:17:48.114375
7103 22:17:48.114743 CH 0, Rank 1
7104 22:17:48.117782 SW Impedance : PASS
7105 22:17:48.118283 DUTY Scan : NO K
7106 22:17:48.120991 ZQ Calibration : PASS
7107 22:17:48.123965 Jitter Meter : NO K
7108 22:17:48.124377 CBT Training : PASS
7109 22:17:48.127749 Write leveling : NO K
7110 22:17:48.128257 RX DQS gating : PASS
7111 22:17:48.130992 RX DQ/DQS(RDDQC) : PASS
7112 22:17:48.134022 TX DQ/DQS : PASS
7113 22:17:48.134535 RX DATLAT : PASS
7114 22:17:48.137316 RX DQ/DQS(Engine): PASS
7115 22:17:48.141018 TX OE : NO K
7116 22:17:48.141430 All Pass.
7117 22:17:48.141749
7118 22:17:48.142046 CH 1, Rank 0
7119 22:17:48.144255 SW Impedance : PASS
7120 22:17:48.147700 DUTY Scan : NO K
7121 22:17:48.148155 ZQ Calibration : PASS
7122 22:17:48.150538 Jitter Meter : NO K
7123 22:17:48.154026 CBT Training : PASS
7124 22:17:48.154437 Write leveling : PASS
7125 22:17:48.157035 RX DQS gating : PASS
7126 22:17:48.160956 RX DQ/DQS(RDDQC) : PASS
7127 22:17:48.161608 TX DQ/DQS : PASS
7128 22:17:48.163828 RX DATLAT : PASS
7129 22:17:48.167206 RX DQ/DQS(Engine): PASS
7130 22:17:48.167617 TX OE : NO K
7131 22:17:48.170178 All Pass.
7132 22:17:48.170610
7133 22:17:48.170931 CH 1, Rank 1
7134 22:17:48.173533 SW Impedance : PASS
7135 22:17:48.173951 DUTY Scan : NO K
7136 22:17:48.176948 ZQ Calibration : PASS
7137 22:17:48.180870 Jitter Meter : NO K
7138 22:17:48.181410 CBT Training : PASS
7139 22:17:48.184286 Write leveling : NO K
7140 22:17:48.186929 RX DQS gating : PASS
7141 22:17:48.187442 RX DQ/DQS(RDDQC) : PASS
7142 22:17:48.190434 TX DQ/DQS : PASS
7143 22:17:48.190950 RX DATLAT : PASS
7144 22:17:48.193463 RX DQ/DQS(Engine): PASS
7145 22:17:48.197502 TX OE : NO K
7146 22:17:48.198017 All Pass.
7147 22:17:48.198345
7148 22:17:48.200043 DramC Write-DBI off
7149 22:17:48.203715 PER_BANK_REFRESH: Hybrid Mode
7150 22:17:48.204223 TX_TRACKING: ON
7151 22:17:48.213324 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7152 22:17:48.216829 [FAST_K] Save calibration result to emmc
7153 22:17:48.220090 dramc_set_vcore_voltage set vcore to 725000
7154 22:17:48.223320 Read voltage for 1600, 0
7155 22:17:48.223760 Vio18 = 0
7156 22:17:48.224110 Vcore = 725000
7157 22:17:48.226646 Vdram = 0
7158 22:17:48.227059 Vddq = 0
7159 22:17:48.227380 Vmddr = 0
7160 22:17:48.232947 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7161 22:17:48.236613 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7162 22:17:48.239540 MEM_TYPE=3, freq_sel=13
7163 22:17:48.243597 sv_algorithm_assistance_LP4_3733
7164 22:17:48.246367 ============ PULL DRAM RESETB DOWN ============
7165 22:17:48.249423 ========== PULL DRAM RESETB DOWN end =========
7166 22:17:48.256582 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7167 22:17:48.259791 ===================================
7168 22:17:48.260304 LPDDR4 DRAM CONFIGURATION
7169 22:17:48.262983 ===================================
7170 22:17:48.266224 EX_ROW_EN[0] = 0x0
7171 22:17:48.269496 EX_ROW_EN[1] = 0x0
7172 22:17:48.269905 LP4Y_EN = 0x0
7173 22:17:48.272494 WORK_FSP = 0x1
7174 22:17:48.272942 WL = 0x5
7175 22:17:48.276132 RL = 0x5
7176 22:17:48.276581 BL = 0x2
7177 22:17:48.279533 RPST = 0x0
7178 22:17:48.280049 RD_PRE = 0x0
7179 22:17:48.282502 WR_PRE = 0x1
7180 22:17:48.282915 WR_PST = 0x1
7181 22:17:48.286101 DBI_WR = 0x0
7182 22:17:48.286649 DBI_RD = 0x0
7183 22:17:48.289337 OTF = 0x1
7184 22:17:48.292380 ===================================
7185 22:17:48.296002 ===================================
7186 22:17:48.296749 ANA top config
7187 22:17:48.299578 ===================================
7188 22:17:48.302580 DLL_ASYNC_EN = 0
7189 22:17:48.305774 ALL_SLAVE_EN = 0
7190 22:17:48.309267 NEW_RANK_MODE = 1
7191 22:17:48.309691 DLL_IDLE_MODE = 1
7192 22:17:48.312306 LP45_APHY_COMB_EN = 1
7193 22:17:48.316021 TX_ODT_DIS = 0
7194 22:17:48.318950 NEW_8X_MODE = 1
7195 22:17:48.323113 ===================================
7196 22:17:48.326194 ===================================
7197 22:17:48.328404 data_rate = 3200
7198 22:17:48.332215 CKR = 1
7199 22:17:48.332931 DQ_P2S_RATIO = 8
7200 22:17:48.334947 ===================================
7201 22:17:48.339136 CA_P2S_RATIO = 8
7202 22:17:48.341832 DQ_CA_OPEN = 0
7203 22:17:48.345410 DQ_SEMI_OPEN = 0
7204 22:17:48.348551 CA_SEMI_OPEN = 0
7205 22:17:48.351717 CA_FULL_RATE = 0
7206 22:17:48.352258 DQ_CKDIV4_EN = 0
7207 22:17:48.355253 CA_CKDIV4_EN = 0
7208 22:17:48.358413 CA_PREDIV_EN = 0
7209 22:17:48.361632 PH8_DLY = 12
7210 22:17:48.365377 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7211 22:17:48.368198 DQ_AAMCK_DIV = 4
7212 22:17:48.368671 CA_AAMCK_DIV = 4
7213 22:17:48.371685 CA_ADMCK_DIV = 4
7214 22:17:48.375608 DQ_TRACK_CA_EN = 0
7215 22:17:48.378256 CA_PICK = 1600
7216 22:17:48.381952 CA_MCKIO = 1600
7217 22:17:48.385306 MCKIO_SEMI = 0
7218 22:17:48.388249 PLL_FREQ = 3068
7219 22:17:48.392046 DQ_UI_PI_RATIO = 32
7220 22:17:48.392623 CA_UI_PI_RATIO = 0
7221 22:17:48.394879 ===================================
7222 22:17:48.398373 ===================================
7223 22:17:48.401433 memory_type:LPDDR4
7224 22:17:48.404906 GP_NUM : 10
7225 22:17:48.405440 SRAM_EN : 1
7226 22:17:48.408059 MD32_EN : 0
7227 22:17:48.411580 ===================================
7228 22:17:48.414496 [ANA_INIT] >>>>>>>>>>>>>>
7229 22:17:48.414915 <<<<<< [CONFIGURE PHASE]: ANA_TX
7230 22:17:48.421583 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7231 22:17:48.425481 ===================================
7232 22:17:48.426000 data_rate = 3200,PCW = 0X7600
7233 22:17:48.428298 ===================================
7234 22:17:48.431807 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7235 22:17:48.438119 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7236 22:17:48.444580 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7237 22:17:48.447778 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7238 22:17:48.450794 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7239 22:17:48.454205 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7240 22:17:48.457723 [ANA_INIT] flow start
7241 22:17:48.461459 [ANA_INIT] PLL >>>>>>>>
7242 22:17:48.461970 [ANA_INIT] PLL <<<<<<<<
7243 22:17:48.464121 [ANA_INIT] MIDPI >>>>>>>>
7244 22:17:48.467490 [ANA_INIT] MIDPI <<<<<<<<
7245 22:17:48.467925 [ANA_INIT] DLL >>>>>>>>
7246 22:17:48.470471 [ANA_INIT] DLL <<<<<<<<
7247 22:17:48.474355 [ANA_INIT] flow end
7248 22:17:48.477133 ============ LP4 DIFF to SE enter ============
7249 22:17:48.481001 ============ LP4 DIFF to SE exit ============
7250 22:17:48.484393 [ANA_INIT] <<<<<<<<<<<<<
7251 22:17:48.487256 [Flow] Enable top DCM control >>>>>
7252 22:17:48.491359 [Flow] Enable top DCM control <<<<<
7253 22:17:48.494279 Enable DLL master slave shuffle
7254 22:17:48.497433 ==============================================================
7255 22:17:48.501112 Gating Mode config
7256 22:17:48.507139 ==============================================================
7257 22:17:48.507659 Config description:
7258 22:17:48.517114 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7259 22:17:48.523826 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7260 22:17:48.528083 SELPH_MODE 0: By rank 1: By Phase
7261 22:17:48.533593 ==============================================================
7262 22:17:48.538053 GAT_TRACK_EN = 1
7263 22:17:48.540236 RX_GATING_MODE = 2
7264 22:17:48.543592 RX_GATING_TRACK_MODE = 2
7265 22:17:48.546608 SELPH_MODE = 1
7266 22:17:48.549894 PICG_EARLY_EN = 1
7267 22:17:48.553811 VALID_LAT_VALUE = 1
7268 22:17:48.556721 ==============================================================
7269 22:17:48.559679 Enter into Gating configuration >>>>
7270 22:17:48.563552 Exit from Gating configuration <<<<
7271 22:17:48.566198 Enter into DVFS_PRE_config >>>>>
7272 22:17:48.579315 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7273 22:17:48.582557 Exit from DVFS_PRE_config <<<<<
7274 22:17:48.586180 Enter into PICG configuration >>>>
7275 22:17:48.590060 Exit from PICG configuration <<<<
7276 22:17:48.590609 [RX_INPUT] configuration >>>>>
7277 22:17:48.592816 [RX_INPUT] configuration <<<<<
7278 22:17:48.600231 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7279 22:17:48.602997 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7280 22:17:48.609715 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7281 22:17:48.615542 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7282 22:17:48.622582 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7283 22:17:48.629189 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7284 22:17:48.631877 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7285 22:17:48.635487 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7286 22:17:48.642946 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7287 22:17:48.645543 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7288 22:17:48.649140 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7289 22:17:48.655586 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7290 22:17:48.658516 ===================================
7291 22:17:48.658946 LPDDR4 DRAM CONFIGURATION
7292 22:17:48.661822 ===================================
7293 22:17:48.665308 EX_ROW_EN[0] = 0x0
7294 22:17:48.665737 EX_ROW_EN[1] = 0x0
7295 22:17:48.668343 LP4Y_EN = 0x0
7296 22:17:48.671977 WORK_FSP = 0x1
7297 22:17:48.672433 WL = 0x5
7298 22:17:48.674925 RL = 0x5
7299 22:17:48.675362 BL = 0x2
7300 22:17:48.678096 RPST = 0x0
7301 22:17:48.678528 RD_PRE = 0x0
7302 22:17:48.681937 WR_PRE = 0x1
7303 22:17:48.682591 WR_PST = 0x1
7304 22:17:48.684540 DBI_WR = 0x0
7305 22:17:48.684967 DBI_RD = 0x0
7306 22:17:48.688632 OTF = 0x1
7307 22:17:48.691162 ===================================
7308 22:17:48.694713 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7309 22:17:48.698453 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7310 22:17:48.704552 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7311 22:17:48.708614 ===================================
7312 22:17:48.709039 LPDDR4 DRAM CONFIGURATION
7313 22:17:48.711273 ===================================
7314 22:17:48.715028 EX_ROW_EN[0] = 0x10
7315 22:17:48.715448 EX_ROW_EN[1] = 0x0
7316 22:17:48.718135 LP4Y_EN = 0x0
7317 22:17:48.721127 WORK_FSP = 0x1
7318 22:17:48.721547 WL = 0x5
7319 22:17:48.724728 RL = 0x5
7320 22:17:48.725147 BL = 0x2
7321 22:17:48.728100 RPST = 0x0
7322 22:17:48.728654 RD_PRE = 0x0
7323 22:17:48.730989 WR_PRE = 0x1
7324 22:17:48.731408 WR_PST = 0x1
7325 22:17:48.734388 DBI_WR = 0x0
7326 22:17:48.734916 DBI_RD = 0x0
7327 22:17:48.737750 OTF = 0x1
7328 22:17:48.741208 ===================================
7329 22:17:48.747817 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7330 22:17:48.748404 ==
7331 22:17:48.750899 Dram Type= 6, Freq= 0, CH_0, rank 0
7332 22:17:48.754375 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7333 22:17:48.754798 ==
7334 22:17:48.757567 [Duty_Offset_Calibration]
7335 22:17:48.757988 B0:1 B1:-1 CA:0
7336 22:17:48.758316
7337 22:17:48.761024 [DutyScan_Calibration_Flow] k_type=0
7338 22:17:48.771553
7339 22:17:48.772081 ==CLK 0==
7340 22:17:48.774813 Final CLK duty delay cell = 0
7341 22:17:48.777826 [0] MAX Duty = 5124%(X100), DQS PI = 22
7342 22:17:48.781361 [0] MIN Duty = 4907%(X100), DQS PI = 6
7343 22:17:48.784378 [0] AVG Duty = 5015%(X100)
7344 22:17:48.784845
7345 22:17:48.787719 CH0 CLK Duty spec in!! Max-Min= 217%
7346 22:17:48.791221 [DutyScan_Calibration_Flow] ====Done====
7347 22:17:48.791664
7348 22:17:48.794719 [DutyScan_Calibration_Flow] k_type=1
7349 22:17:48.810703
7350 22:17:48.811216 ==DQS 0 ==
7351 22:17:48.814024 Final DQS duty delay cell = -4
7352 22:17:48.817176 [-4] MAX Duty = 5000%(X100), DQS PI = 20
7353 22:17:48.820739 [-4] MIN Duty = 4844%(X100), DQS PI = 58
7354 22:17:48.823409 [-4] AVG Duty = 4922%(X100)
7355 22:17:48.823832
7356 22:17:48.824158 ==DQS 1 ==
7357 22:17:48.827168 Final DQS duty delay cell = 0
7358 22:17:48.830131 [0] MAX Duty = 5187%(X100), DQS PI = 4
7359 22:17:48.833277 [0] MIN Duty = 5031%(X100), DQS PI = 16
7360 22:17:48.836493 [0] AVG Duty = 5109%(X100)
7361 22:17:48.836933
7362 22:17:48.840043 CH0 DQS 0 Duty spec in!! Max-Min= 156%
7363 22:17:48.840451
7364 22:17:48.843002 CH0 DQS 1 Duty spec in!! Max-Min= 156%
7365 22:17:48.846391 [DutyScan_Calibration_Flow] ====Done====
7366 22:17:48.846800
7367 22:17:48.850077 [DutyScan_Calibration_Flow] k_type=3
7368 22:17:48.868195
7369 22:17:48.868737 ==DQM 0 ==
7370 22:17:48.870924 Final DQM duty delay cell = 0
7371 22:17:48.874569 [0] MAX Duty = 5124%(X100), DQS PI = 24
7372 22:17:48.877849 [0] MIN Duty = 4875%(X100), DQS PI = 10
7373 22:17:48.880908 [0] AVG Duty = 4999%(X100)
7374 22:17:48.881345
7375 22:17:48.881667 ==DQM 1 ==
7376 22:17:48.884316 Final DQM duty delay cell = 0
7377 22:17:48.887763 [0] MAX Duty = 5000%(X100), DQS PI = 4
7378 22:17:48.890937 [0] MIN Duty = 4813%(X100), DQS PI = 20
7379 22:17:48.894318 [0] AVG Duty = 4906%(X100)
7380 22:17:48.894721
7381 22:17:48.897395 CH0 DQM 0 Duty spec in!! Max-Min= 249%
7382 22:17:48.897802
7383 22:17:48.901143 CH0 DQM 1 Duty spec in!! Max-Min= 187%
7384 22:17:48.904047 [DutyScan_Calibration_Flow] ====Done====
7385 22:17:48.904463
7386 22:17:48.907790 [DutyScan_Calibration_Flow] k_type=2
7387 22:17:48.924753
7388 22:17:48.925295 ==DQ 0 ==
7389 22:17:48.928235 Final DQ duty delay cell = -4
7390 22:17:48.931018 [-4] MAX Duty = 5031%(X100), DQS PI = 24
7391 22:17:48.934426 [-4] MIN Duty = 4876%(X100), DQS PI = 54
7392 22:17:48.937370 [-4] AVG Duty = 4953%(X100)
7393 22:17:48.937911
7394 22:17:48.938265 ==DQ 1 ==
7395 22:17:48.940876 Final DQ duty delay cell = 0
7396 22:17:48.944252 [0] MAX Duty = 5125%(X100), DQS PI = 4
7397 22:17:48.947542 [0] MIN Duty = 4969%(X100), DQS PI = 38
7398 22:17:48.951181 [0] AVG Duty = 5047%(X100)
7399 22:17:48.951724
7400 22:17:48.953855 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7401 22:17:48.954305
7402 22:17:48.958376 CH0 DQ 1 Duty spec in!! Max-Min= 156%
7403 22:17:48.960711 [DutyScan_Calibration_Flow] ====Done====
7404 22:17:48.961260 ==
7405 22:17:48.964318 Dram Type= 6, Freq= 0, CH_1, rank 0
7406 22:17:48.967596 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7407 22:17:48.968044 ==
7408 22:17:48.970317 [Duty_Offset_Calibration]
7409 22:17:48.970809 B0:-1 B1:1 CA:2
7410 22:17:48.971286
7411 22:17:48.974331 [DutyScan_Calibration_Flow] k_type=0
7412 22:17:48.985131
7413 22:17:48.985668 ==CLK 0==
7414 22:17:48.988171 Final CLK duty delay cell = 0
7415 22:17:48.991146 [0] MAX Duty = 5187%(X100), DQS PI = 22
7416 22:17:48.995153 [0] MIN Duty = 4969%(X100), DQS PI = 0
7417 22:17:48.995585 [0] AVG Duty = 5078%(X100)
7418 22:17:48.997871
7419 22:17:49.001454 CH1 CLK Duty spec in!! Max-Min= 218%
7420 22:17:49.004902 [DutyScan_Calibration_Flow] ====Done====
7421 22:17:49.005311
7422 22:17:49.007884 [DutyScan_Calibration_Flow] k_type=1
7423 22:17:49.025120
7424 22:17:49.025620 ==DQS 0 ==
7425 22:17:49.027902 Final DQS duty delay cell = 0
7426 22:17:49.031097 [0] MAX Duty = 5156%(X100), DQS PI = 18
7427 22:17:49.034764 [0] MIN Duty = 4907%(X100), DQS PI = 8
7428 22:17:49.035316 [0] AVG Duty = 5031%(X100)
7429 22:17:49.038093
7430 22:17:49.038607 ==DQS 1 ==
7431 22:17:49.041741 Final DQS duty delay cell = 0
7432 22:17:49.045115 [0] MAX Duty = 5093%(X100), DQS PI = 24
7433 22:17:49.047906 [0] MIN Duty = 4969%(X100), DQS PI = 56
7434 22:17:49.051219 [0] AVG Duty = 5031%(X100)
7435 22:17:49.051725
7436 22:17:49.054351 CH1 DQS 0 Duty spec in!! Max-Min= 249%
7437 22:17:49.054782
7438 22:17:49.057827 CH1 DQS 1 Duty spec in!! Max-Min= 124%
7439 22:17:49.061270 [DutyScan_Calibration_Flow] ====Done====
7440 22:17:49.061677
7441 22:17:49.064835 [DutyScan_Calibration_Flow] k_type=3
7442 22:17:49.080680
7443 22:17:49.081185 ==DQM 0 ==
7444 22:17:49.084345 Final DQM duty delay cell = -4
7445 22:17:49.087475 [-4] MAX Duty = 5062%(X100), DQS PI = 34
7446 22:17:49.090860 [-4] MIN Duty = 4782%(X100), DQS PI = 10
7447 22:17:49.093882 [-4] AVG Duty = 4922%(X100)
7448 22:17:49.094362
7449 22:17:49.094692 ==DQM 1 ==
7450 22:17:49.097112 Final DQM duty delay cell = 0
7451 22:17:49.100499 [0] MAX Duty = 5156%(X100), DQS PI = 0
7452 22:17:49.103649 [0] MIN Duty = 4969%(X100), DQS PI = 32
7453 22:17:49.107015 [0] AVG Duty = 5062%(X100)
7454 22:17:49.107429
7455 22:17:49.110198 CH1 DQM 0 Duty spec in!! Max-Min= 280%
7456 22:17:49.110621
7457 22:17:49.113545 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7458 22:17:49.117358 [DutyScan_Calibration_Flow] ====Done====
7459 22:17:49.117770
7460 22:17:49.120591 [DutyScan_Calibration_Flow] k_type=2
7461 22:17:49.138093
7462 22:17:49.138610 ==DQ 0 ==
7463 22:17:49.140991 Final DQ duty delay cell = 0
7464 22:17:49.144614 [0] MAX Duty = 5187%(X100), DQS PI = 32
7465 22:17:49.147757 [0] MIN Duty = 4906%(X100), DQS PI = 10
7466 22:17:49.148284 [0] AVG Duty = 5046%(X100)
7467 22:17:49.151250
7468 22:17:49.151671 ==DQ 1 ==
7469 22:17:49.154829 Final DQ duty delay cell = 0
7470 22:17:49.157536 [0] MAX Duty = 5156%(X100), DQS PI = 8
7471 22:17:49.160680 [0] MIN Duty = 4969%(X100), DQS PI = 56
7472 22:17:49.161103 [0] AVG Duty = 5062%(X100)
7473 22:17:49.161434
7474 22:17:49.167248 CH1 DQ 0 Duty spec in!! Max-Min= 281%
7475 22:17:49.167672
7476 22:17:49.170692 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7477 22:17:49.174499 [DutyScan_Calibration_Flow] ====Done====
7478 22:17:49.177254 nWR fixed to 30
7479 22:17:49.177682 [ModeRegInit_LP4] CH0 RK0
7480 22:17:49.180711 [ModeRegInit_LP4] CH0 RK1
7481 22:17:49.183990 [ModeRegInit_LP4] CH1 RK0
7482 22:17:49.187717 [ModeRegInit_LP4] CH1 RK1
7483 22:17:49.188235 match AC timing 5
7484 22:17:49.193801 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7485 22:17:49.197410 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7486 22:17:49.200682 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7487 22:17:49.207313 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7488 22:17:49.210341 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7489 22:17:49.210761 [MiockJmeterHQA]
7490 22:17:49.211088
7491 22:17:49.213536 [DramcMiockJmeter] u1RxGatingPI = 0
7492 22:17:49.216995 0 : 4363, 4137
7493 22:17:49.217529 4 : 4252, 4027
7494 22:17:49.220230 8 : 4252, 4027
7495 22:17:49.220690 12 : 4252, 4027
7496 22:17:49.223490 16 : 4253, 4027
7497 22:17:49.223910 20 : 4363, 4137
7498 22:17:49.224238 24 : 4255, 4029
7499 22:17:49.227612 28 : 4363, 4138
7500 22:17:49.228128 32 : 4253, 4026
7501 22:17:49.229711 36 : 4252, 4027
7502 22:17:49.230133 40 : 4252, 4027
7503 22:17:49.233371 44 : 4253, 4027
7504 22:17:49.233890 48 : 4363, 4138
7505 22:17:49.236671 52 : 4253, 4026
7506 22:17:49.237185 56 : 4363, 4137
7507 22:17:49.237525 60 : 4252, 4027
7508 22:17:49.239877 64 : 4253, 4027
7509 22:17:49.240294 68 : 4250, 4027
7510 22:17:49.243106 72 : 4361, 4138
7511 22:17:49.243524 76 : 4250, 4027
7512 22:17:49.246973 80 : 4361, 4138
7513 22:17:49.247492 84 : 4250, 4026
7514 22:17:49.250003 88 : 4250, 4026
7515 22:17:49.250426 92 : 4249, 321
7516 22:17:49.250755 96 : 4363, 0
7517 22:17:49.253201 100 : 4250, 0
7518 22:17:49.253626 104 : 4250, 0
7519 22:17:49.253961 108 : 4250, 0
7520 22:17:49.256494 112 : 4252, 0
7521 22:17:49.256958 116 : 4363, 0
7522 22:17:49.259712 120 : 4361, 0
7523 22:17:49.260129 124 : 4361, 0
7524 22:17:49.260461 128 : 4252, 0
7525 22:17:49.263022 132 : 4253, 0
7526 22:17:49.263545 136 : 4250, 0
7527 22:17:49.266179 140 : 4250, 0
7528 22:17:49.266605 144 : 4253, 0
7529 22:17:49.266937 148 : 4250, 0
7530 22:17:49.269772 152 : 4253, 0
7531 22:17:49.270215 156 : 4363, 0
7532 22:17:49.273416 160 : 4361, 0
7533 22:17:49.273930 164 : 4250, 0
7534 22:17:49.274262 168 : 4252, 0
7535 22:17:49.276027 172 : 4361, 0
7536 22:17:49.276452 176 : 4361, 0
7537 22:17:49.279773 180 : 4252, 0
7538 22:17:49.280200 184 : 4252, 0
7539 22:17:49.280566 188 : 4250, 0
7540 22:17:49.283156 192 : 4250, 0
7541 22:17:49.283688 196 : 4250, 0
7542 22:17:49.286222 200 : 4250, 0
7543 22:17:49.286743 204 : 4253, 0
7544 22:17:49.287082 208 : 4360, 0
7545 22:17:49.289210 212 : 4361, 0
7546 22:17:49.289636 216 : 4248, 0
7547 22:17:49.292794 220 : 4252, 0
7548 22:17:49.293309 224 : 4361, 241
7549 22:17:49.293645 228 : 4250, 3328
7550 22:17:49.295957 232 : 4250, 4027
7551 22:17:49.296473 236 : 4250, 4027
7552 22:17:49.298922 240 : 4250, 4027
7553 22:17:49.299348 244 : 4250, 4027
7554 22:17:49.302519 248 : 4253, 4029
7555 22:17:49.303040 252 : 4250, 4027
7556 22:17:49.305790 256 : 4361, 4138
7557 22:17:49.306303 260 : 4360, 4137
7558 22:17:49.309038 264 : 4250, 4027
7559 22:17:49.309462 268 : 4361, 4137
7560 22:17:49.312237 272 : 4361, 4138
7561 22:17:49.312723 276 : 4250, 4027
7562 22:17:49.316178 280 : 4250, 4026
7563 22:17:49.316755 284 : 4250, 4027
7564 22:17:49.317106 288 : 4250, 4027
7565 22:17:49.319200 292 : 4250, 4027
7566 22:17:49.319717 296 : 4250, 4026
7567 22:17:49.322405 300 : 4250, 4027
7568 22:17:49.322830 304 : 4250, 4027
7569 22:17:49.325219 308 : 4361, 4138
7570 22:17:49.325643 312 : 4360, 4137
7571 22:17:49.328825 316 : 4248, 4024
7572 22:17:49.329249 320 : 4361, 4137
7573 22:17:49.332176 324 : 4361, 4138
7574 22:17:49.332625 328 : 4250, 4027
7575 22:17:49.335614 332 : 4250, 4026
7576 22:17:49.336140 336 : 4255, 3879
7577 22:17:49.338648 340 : 4250, 2122
7578 22:17:49.339074
7579 22:17:49.339401 MIOCK jitter meter ch=0
7580 22:17:49.339703
7581 22:17:49.342504 1T = (340-92) = 248 dly cells
7582 22:17:49.348727 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 262/100 ps
7583 22:17:49.349231 ==
7584 22:17:49.352209 Dram Type= 6, Freq= 0, CH_0, rank 0
7585 22:17:49.355207 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7586 22:17:49.355645 ==
7587 22:17:49.362895 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7588 22:17:49.365627 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7589 22:17:49.368731 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7590 22:17:49.375805 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7591 22:17:49.384878 [CA 0] Center 43 (12~74) winsize 63
7592 22:17:49.388130 [CA 1] Center 42 (12~73) winsize 62
7593 22:17:49.391691 [CA 2] Center 38 (9~68) winsize 60
7594 22:17:49.394757 [CA 3] Center 38 (8~68) winsize 61
7595 22:17:49.398047 [CA 4] Center 36 (7~66) winsize 60
7596 22:17:49.401146 [CA 5] Center 35 (6~65) winsize 60
7597 22:17:49.401570
7598 22:17:49.404450 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7599 22:17:49.404917
7600 22:17:49.407925 [CATrainingPosCal] consider 1 rank data
7601 22:17:49.411318 u2DelayCellTimex100 = 262/100 ps
7602 22:17:49.417826 CA0 delay=43 (12~74),Diff = 8 PI (29 cell)
7603 22:17:49.421914 CA1 delay=42 (12~73),Diff = 7 PI (26 cell)
7604 22:17:49.424601 CA2 delay=38 (9~68),Diff = 3 PI (11 cell)
7605 22:17:49.427730 CA3 delay=38 (8~68),Diff = 3 PI (11 cell)
7606 22:17:49.431010 CA4 delay=36 (7~66),Diff = 1 PI (3 cell)
7607 22:17:49.434755 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7608 22:17:49.435424
7609 22:17:49.437487 CA PerBit enable=1, Macro0, CA PI delay=35
7610 22:17:49.437903
7611 22:17:49.441302 [CBTSetCACLKResult] CA Dly = 35
7612 22:17:49.444331 CS Dly: 12 (0~43)
7613 22:17:49.447844 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7614 22:17:49.450899 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7615 22:17:49.451337 ==
7616 22:17:49.454184 Dram Type= 6, Freq= 0, CH_0, rank 1
7617 22:17:49.460795 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7618 22:17:49.461220 ==
7619 22:17:49.464309 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7620 22:17:49.471159 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7621 22:17:49.473798 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7622 22:17:49.481177 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7623 22:17:49.488533 [CA 0] Center 42 (12~73) winsize 62
7624 22:17:49.491683 [CA 1] Center 43 (13~73) winsize 61
7625 22:17:49.495261 [CA 2] Center 37 (8~67) winsize 60
7626 22:17:49.498051 [CA 3] Center 37 (7~67) winsize 61
7627 22:17:49.501287 [CA 4] Center 35 (6~65) winsize 60
7628 22:17:49.505076 [CA 5] Center 35 (5~65) winsize 61
7629 22:17:49.505580
7630 22:17:49.508593 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7631 22:17:49.509118
7632 22:17:49.515005 [CATrainingPosCal] consider 2 rank data
7633 22:17:49.515531 u2DelayCellTimex100 = 262/100 ps
7634 22:17:49.521339 CA0 delay=42 (12~73),Diff = 7 PI (26 cell)
7635 22:17:49.524776 CA1 delay=43 (13~73),Diff = 8 PI (29 cell)
7636 22:17:49.527753 CA2 delay=38 (9~67),Diff = 3 PI (11 cell)
7637 22:17:49.531838 CA3 delay=37 (8~67),Diff = 2 PI (7 cell)
7638 22:17:49.535203 CA4 delay=36 (7~65),Diff = 1 PI (3 cell)
7639 22:17:49.537547 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7640 22:17:49.537968
7641 22:17:49.541347 CA PerBit enable=1, Macro0, CA PI delay=35
7642 22:17:49.541903
7643 22:17:49.544862 [CBTSetCACLKResult] CA Dly = 35
7644 22:17:49.547456 CS Dly: 12 (0~43)
7645 22:17:49.550842 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7646 22:17:49.554272 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7647 22:17:49.554690
7648 22:17:49.557412 ----->DramcWriteLeveling(PI) begin...
7649 22:17:49.560626 ==
7650 22:17:49.561043 Dram Type= 6, Freq= 0, CH_0, rank 0
7651 22:17:49.567122 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7652 22:17:49.567542 ==
7653 22:17:49.570515 Write leveling (Byte 0): 36 => 36
7654 22:17:49.574113 Write leveling (Byte 1): 29 => 29
7655 22:17:49.577754 DramcWriteLeveling(PI) end<-----
7656 22:17:49.578265
7657 22:17:49.578593 ==
7658 22:17:49.580371 Dram Type= 6, Freq= 0, CH_0, rank 0
7659 22:17:49.584233 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7660 22:17:49.584694 ==
7661 22:17:49.587420 [Gating] SW mode calibration
7662 22:17:49.594024 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7663 22:17:49.600686 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7664 22:17:49.603503 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7665 22:17:49.606916 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7666 22:17:49.613803 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7667 22:17:49.617148 1 4 12 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
7668 22:17:49.620900 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7669 22:17:49.626777 1 4 20 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7670 22:17:49.630349 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7671 22:17:49.633710 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7672 22:17:49.640190 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7673 22:17:49.643549 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7674 22:17:49.646403 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7675 22:17:49.650280 1 5 12 | B1->B0 | 3434 2e2e | 1 1 | (1 1) (1 0)
7676 22:17:49.656386 1 5 16 | B1->B0 | 3434 2424 | 1 0 | (1 1) (0 0)
7677 22:17:49.659786 1 5 20 | B1->B0 | 3030 2323 | 1 0 | (1 0) (0 0)
7678 22:17:49.663130 1 5 24 | B1->B0 | 2727 2323 | 0 0 | (1 0) (0 0)
7679 22:17:49.669638 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7680 22:17:49.673217 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7681 22:17:49.676997 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7682 22:17:49.683143 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7683 22:17:49.686123 1 6 12 | B1->B0 | 2323 302f | 0 1 | (0 0) (1 1)
7684 22:17:49.690433 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7685 22:17:49.696805 1 6 20 | B1->B0 | 2f2f 4646 | 0 0 | (0 0) (0 0)
7686 22:17:49.699543 1 6 24 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
7687 22:17:49.702913 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7688 22:17:49.709179 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7689 22:17:49.712838 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7690 22:17:49.715901 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7691 22:17:49.722425 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7692 22:17:49.726115 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7693 22:17:49.729459 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7694 22:17:49.736296 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7695 22:17:49.740004 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7696 22:17:49.742353 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7697 22:17:49.749277 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7698 22:17:49.752287 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7699 22:17:49.755744 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7700 22:17:49.762506 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7701 22:17:49.765708 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7702 22:17:49.768727 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7703 22:17:49.775666 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7704 22:17:49.778511 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7705 22:17:49.782037 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7706 22:17:49.788307 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7707 22:17:49.792178 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7708 22:17:49.795599 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7709 22:17:49.801529 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7710 22:17:49.804957 Total UI for P1: 0, mck2ui 16
7711 22:17:49.809153 best dqsien dly found for B0: ( 1, 9, 14)
7712 22:17:49.811723 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7713 22:17:49.815353 Total UI for P1: 0, mck2ui 16
7714 22:17:49.818480 best dqsien dly found for B1: ( 1, 9, 20)
7715 22:17:49.821776 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
7716 22:17:49.824669 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7717 22:17:49.825081
7718 22:17:49.828197 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
7719 22:17:49.834940 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7720 22:17:49.835448 [Gating] SW calibration Done
7721 22:17:49.835779 ==
7722 22:17:49.838145 Dram Type= 6, Freq= 0, CH_0, rank 0
7723 22:17:49.844732 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7724 22:17:49.845243 ==
7725 22:17:49.845570 RX Vref Scan: 0
7726 22:17:49.845917
7727 22:17:49.848563 RX Vref 0 -> 0, step: 1
7728 22:17:49.848974
7729 22:17:49.851239 RX Delay 0 -> 252, step: 8
7730 22:17:49.854858 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
7731 22:17:49.858731 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7732 22:17:49.861397 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
7733 22:17:49.867954 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7734 22:17:49.871803 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7735 22:17:49.874814 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7736 22:17:49.877742 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
7737 22:17:49.881107 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7738 22:17:49.887625 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
7739 22:17:49.890657 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7740 22:17:49.894662 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
7741 22:17:49.897570 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7742 22:17:49.901167 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7743 22:17:49.907659 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
7744 22:17:49.910644 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7745 22:17:49.914072 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7746 22:17:49.914536 ==
7747 22:17:49.917180 Dram Type= 6, Freq= 0, CH_0, rank 0
7748 22:17:49.920928 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7749 22:17:49.924193 ==
7750 22:17:49.924641 DQS Delay:
7751 22:17:49.924972 DQS0 = 0, DQS1 = 0
7752 22:17:49.927932 DQM Delay:
7753 22:17:49.928339 DQM0 = 134, DQM1 = 126
7754 22:17:49.930557 DQ Delay:
7755 22:17:49.933621 DQ0 =131, DQ1 =139, DQ2 =131, DQ3 =131
7756 22:17:49.937699 DQ4 =135, DQ5 =119, DQ6 =143, DQ7 =147
7757 22:17:49.940443 DQ8 =119, DQ9 =115, DQ10 =127, DQ11 =119
7758 22:17:49.943557 DQ12 =131, DQ13 =131, DQ14 =139, DQ15 =131
7759 22:17:49.944062
7760 22:17:49.944383
7761 22:17:49.944723 ==
7762 22:17:49.946837 Dram Type= 6, Freq= 0, CH_0, rank 0
7763 22:17:49.950524 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7764 22:17:49.951040 ==
7765 22:17:49.951370
7766 22:17:49.953653
7767 22:17:49.954062 TX Vref Scan disable
7768 22:17:49.957111 == TX Byte 0 ==
7769 22:17:49.960484 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7770 22:17:49.963605 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7771 22:17:49.966843 == TX Byte 1 ==
7772 22:17:49.970380 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7773 22:17:49.973360 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7774 22:17:49.973783 ==
7775 22:17:49.976930 Dram Type= 6, Freq= 0, CH_0, rank 0
7776 22:17:49.983257 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7777 22:17:49.983682 ==
7778 22:17:49.996234
7779 22:17:49.998479 TX Vref early break, caculate TX vref
7780 22:17:50.002442 TX Vref=16, minBit 4, minWin=22, winSum=372
7781 22:17:50.005673 TX Vref=18, minBit 4, minWin=22, winSum=385
7782 22:17:50.009124 TX Vref=20, minBit 4, minWin=23, winSum=394
7783 22:17:50.011975 TX Vref=22, minBit 1, minWin=24, winSum=405
7784 22:17:50.015825 TX Vref=24, minBit 4, minWin=24, winSum=413
7785 22:17:50.021728 TX Vref=26, minBit 0, minWin=24, winSum=418
7786 22:17:50.025222 TX Vref=28, minBit 0, minWin=25, winSum=421
7787 22:17:50.028407 TX Vref=30, minBit 0, minWin=24, winSum=411
7788 22:17:50.032052 TX Vref=32, minBit 5, minWin=23, winSum=402
7789 22:17:50.035830 TX Vref=34, minBit 0, minWin=23, winSum=395
7790 22:17:50.041789 [TxChooseVref] Worse bit 0, Min win 25, Win sum 421, Final Vref 28
7791 22:17:50.042279
7792 22:17:50.045004 Final TX Range 0 Vref 28
7793 22:17:50.045497
7794 22:17:50.045823 ==
7795 22:17:50.049030 Dram Type= 6, Freq= 0, CH_0, rank 0
7796 22:17:50.051930 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7797 22:17:50.052374 ==
7798 22:17:50.052770
7799 22:17:50.053201
7800 22:17:50.055085 TX Vref Scan disable
7801 22:17:50.062065 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
7802 22:17:50.062480 == TX Byte 0 ==
7803 22:17:50.064960 u2DelayCellOfst[0]=18 cells (5 PI)
7804 22:17:50.067827 u2DelayCellOfst[1]=18 cells (5 PI)
7805 22:17:50.071173 u2DelayCellOfst[2]=14 cells (4 PI)
7806 22:17:50.074508 u2DelayCellOfst[3]=14 cells (4 PI)
7807 22:17:50.077806 u2DelayCellOfst[4]=11 cells (3 PI)
7808 22:17:50.081276 u2DelayCellOfst[5]=0 cells (0 PI)
7809 22:17:50.084439 u2DelayCellOfst[6]=18 cells (5 PI)
7810 22:17:50.087722 u2DelayCellOfst[7]=22 cells (6 PI)
7811 22:17:50.091060 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7812 22:17:50.094530 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7813 22:17:50.097782 == TX Byte 1 ==
7814 22:17:50.101435 u2DelayCellOfst[8]=0 cells (0 PI)
7815 22:17:50.104032 u2DelayCellOfst[9]=3 cells (1 PI)
7816 22:17:50.107174 u2DelayCellOfst[10]=7 cells (2 PI)
7817 22:17:50.110591 u2DelayCellOfst[11]=0 cells (0 PI)
7818 22:17:50.114395 u2DelayCellOfst[12]=11 cells (3 PI)
7819 22:17:50.114812 u2DelayCellOfst[13]=11 cells (3 PI)
7820 22:17:50.117778 u2DelayCellOfst[14]=14 cells (4 PI)
7821 22:17:50.120865 u2DelayCellOfst[15]=11 cells (3 PI)
7822 22:17:50.127808 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7823 22:17:50.130910 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7824 22:17:50.131468 DramC Write-DBI on
7825 22:17:50.133987 ==
7826 22:17:50.137065 Dram Type= 6, Freq= 0, CH_0, rank 0
7827 22:17:50.141318 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7828 22:17:50.141889 ==
7829 22:17:50.142255
7830 22:17:50.142587
7831 22:17:50.143649 TX Vref Scan disable
7832 22:17:50.144102 == TX Byte 0 ==
7833 22:17:50.150351 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
7834 22:17:50.150914 == TX Byte 1 ==
7835 22:17:50.154113 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
7836 22:17:50.157318 DramC Write-DBI off
7837 22:17:50.157987
7838 22:17:50.158362 [DATLAT]
7839 22:17:50.160224 Freq=1600, CH0 RK0
7840 22:17:50.160706
7841 22:17:50.161066 DATLAT Default: 0xf
7842 22:17:50.163633 0, 0xFFFF, sum = 0
7843 22:17:50.164098 1, 0xFFFF, sum = 0
7844 22:17:50.167445 2, 0xFFFF, sum = 0
7845 22:17:50.167867 3, 0xFFFF, sum = 0
7846 22:17:50.170163 4, 0xFFFF, sum = 0
7847 22:17:50.173623 5, 0xFFFF, sum = 0
7848 22:17:50.174108 6, 0xFFFF, sum = 0
7849 22:17:50.176671 7, 0xFFFF, sum = 0
7850 22:17:50.177090 8, 0xFFFF, sum = 0
7851 22:17:50.180404 9, 0xFFFF, sum = 0
7852 22:17:50.180955 10, 0xFFFF, sum = 0
7853 22:17:50.183205 11, 0xFFFF, sum = 0
7854 22:17:50.183908 12, 0xFFFF, sum = 0
7855 22:17:50.186786 13, 0xFFFF, sum = 0
7856 22:17:50.187207 14, 0x0, sum = 1
7857 22:17:50.190397 15, 0x0, sum = 2
7858 22:17:50.190919 16, 0x0, sum = 3
7859 22:17:50.193588 17, 0x0, sum = 4
7860 22:17:50.194011 best_step = 15
7861 22:17:50.194339
7862 22:17:50.194641 ==
7863 22:17:50.196821 Dram Type= 6, Freq= 0, CH_0, rank 0
7864 22:17:50.200180 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7865 22:17:50.203778 ==
7866 22:17:50.204301 RX Vref Scan: 1
7867 22:17:50.204767
7868 22:17:50.206569 Set Vref Range= 24 -> 127
7869 22:17:50.206983
7870 22:17:50.210153 RX Vref 24 -> 127, step: 1
7871 22:17:50.210707
7872 22:17:50.211043 RX Delay 19 -> 252, step: 4
7873 22:17:50.211346
7874 22:17:50.213021 Set Vref, RX VrefLevel [Byte0]: 24
7875 22:17:50.216477 [Byte1]: 24
7876 22:17:50.221035
7877 22:17:50.221550 Set Vref, RX VrefLevel [Byte0]: 25
7878 22:17:50.223322 [Byte1]: 25
7879 22:17:50.228168
7880 22:17:50.228722 Set Vref, RX VrefLevel [Byte0]: 26
7881 22:17:50.231324 [Byte1]: 26
7882 22:17:50.235457
7883 22:17:50.235975 Set Vref, RX VrefLevel [Byte0]: 27
7884 22:17:50.238999 [Byte1]: 27
7885 22:17:50.243236
7886 22:17:50.243894 Set Vref, RX VrefLevel [Byte0]: 28
7887 22:17:50.246687 [Byte1]: 28
7888 22:17:50.250729
7889 22:17:50.251245 Set Vref, RX VrefLevel [Byte0]: 29
7890 22:17:50.253580 [Byte1]: 29
7891 22:17:50.258142
7892 22:17:50.261390 Set Vref, RX VrefLevel [Byte0]: 30
7893 22:17:50.264884 [Byte1]: 30
7894 22:17:50.265445
7895 22:17:50.268255 Set Vref, RX VrefLevel [Byte0]: 31
7896 22:17:50.271022 [Byte1]: 31
7897 22:17:50.271482
7898 22:17:50.274299 Set Vref, RX VrefLevel [Byte0]: 32
7899 22:17:50.277789 [Byte1]: 32
7900 22:17:50.281148
7901 22:17:50.281706 Set Vref, RX VrefLevel [Byte0]: 33
7902 22:17:50.284429 [Byte1]: 33
7903 22:17:50.288608
7904 22:17:50.289205 Set Vref, RX VrefLevel [Byte0]: 34
7905 22:17:50.291967 [Byte1]: 34
7906 22:17:50.296419
7907 22:17:50.297017 Set Vref, RX VrefLevel [Byte0]: 35
7908 22:17:50.299353 [Byte1]: 35
7909 22:17:50.303709
7910 22:17:50.304274 Set Vref, RX VrefLevel [Byte0]: 36
7911 22:17:50.307271 [Byte1]: 36
7912 22:17:50.311078
7913 22:17:50.311622 Set Vref, RX VrefLevel [Byte0]: 37
7914 22:17:50.314470 [Byte1]: 37
7915 22:17:50.318565
7916 22:17:50.319039 Set Vref, RX VrefLevel [Byte0]: 38
7917 22:17:50.322076 [Byte1]: 38
7918 22:17:50.326569
7919 22:17:50.326980 Set Vref, RX VrefLevel [Byte0]: 39
7920 22:17:50.330091 [Byte1]: 39
7921 22:17:50.334260
7922 22:17:50.334776 Set Vref, RX VrefLevel [Byte0]: 40
7923 22:17:50.337432 [Byte1]: 40
7924 22:17:50.341503
7925 22:17:50.342035 Set Vref, RX VrefLevel [Byte0]: 41
7926 22:17:50.345412 [Byte1]: 41
7927 22:17:50.349071
7928 22:17:50.349586 Set Vref, RX VrefLevel [Byte0]: 42
7929 22:17:50.353140 [Byte1]: 42
7930 22:17:50.356653
7931 22:17:50.357170 Set Vref, RX VrefLevel [Byte0]: 43
7932 22:17:50.360164 [Byte1]: 43
7933 22:17:50.364279
7934 22:17:50.364831 Set Vref, RX VrefLevel [Byte0]: 44
7935 22:17:50.367922 [Byte1]: 44
7936 22:17:50.371968
7937 22:17:50.372384 Set Vref, RX VrefLevel [Byte0]: 45
7938 22:17:50.374933 [Byte1]: 45
7939 22:17:50.379420
7940 22:17:50.379933 Set Vref, RX VrefLevel [Byte0]: 46
7941 22:17:50.383257 [Byte1]: 46
7942 22:17:50.387114
7943 22:17:50.387628 Set Vref, RX VrefLevel [Byte0]: 47
7944 22:17:50.393951 [Byte1]: 47
7945 22:17:50.394369
7946 22:17:50.396625 Set Vref, RX VrefLevel [Byte0]: 48
7947 22:17:50.400384 [Byte1]: 48
7948 22:17:50.400945
7949 22:17:50.403313 Set Vref, RX VrefLevel [Byte0]: 49
7950 22:17:50.406513 [Byte1]: 49
7951 22:17:50.407032
7952 22:17:50.409816 Set Vref, RX VrefLevel [Byte0]: 50
7953 22:17:50.412748 [Byte1]: 50
7954 22:17:50.417028
7955 22:17:50.417442 Set Vref, RX VrefLevel [Byte0]: 51
7956 22:17:50.420676 [Byte1]: 51
7957 22:17:50.424605
7958 22:17:50.425023 Set Vref, RX VrefLevel [Byte0]: 52
7959 22:17:50.427798 [Byte1]: 52
7960 22:17:50.432578
7961 22:17:50.433104 Set Vref, RX VrefLevel [Byte0]: 53
7962 22:17:50.435449 [Byte1]: 53
7963 22:17:50.440029
7964 22:17:50.440565 Set Vref, RX VrefLevel [Byte0]: 54
7965 22:17:50.443063 [Byte1]: 54
7966 22:17:50.447363
7967 22:17:50.447874 Set Vref, RX VrefLevel [Byte0]: 55
7968 22:17:50.452663 [Byte1]: 55
7969 22:17:50.455622
7970 22:17:50.456135 Set Vref, RX VrefLevel [Byte0]: 56
7971 22:17:50.458178 [Byte1]: 56
7972 22:17:50.463105
7973 22:17:50.463619 Set Vref, RX VrefLevel [Byte0]: 57
7974 22:17:50.466354 [Byte1]: 57
7975 22:17:50.470686
7976 22:17:50.471206 Set Vref, RX VrefLevel [Byte0]: 58
7977 22:17:50.473384 [Byte1]: 58
7978 22:17:50.477432
7979 22:17:50.477843 Set Vref, RX VrefLevel [Byte0]: 59
7980 22:17:50.480720 [Byte1]: 59
7981 22:17:50.485242
7982 22:17:50.485756 Set Vref, RX VrefLevel [Byte0]: 60
7983 22:17:50.488400 [Byte1]: 60
7984 22:17:50.492872
7985 22:17:50.493288 Set Vref, RX VrefLevel [Byte0]: 61
7986 22:17:50.497484 [Byte1]: 61
7987 22:17:50.500176
7988 22:17:50.500732 Set Vref, RX VrefLevel [Byte0]: 62
7989 22:17:50.503861 [Byte1]: 62
7990 22:17:50.508106
7991 22:17:50.508602 Set Vref, RX VrefLevel [Byte0]: 63
7992 22:17:50.511355 [Byte1]: 63
7993 22:17:50.515810
7994 22:17:50.516335 Set Vref, RX VrefLevel [Byte0]: 64
7995 22:17:50.518573 [Byte1]: 64
7996 22:17:50.522954
7997 22:17:50.523434 Set Vref, RX VrefLevel [Byte0]: 65
7998 22:17:50.526795 [Byte1]: 65
7999 22:17:50.530947
8000 22:17:50.531610 Set Vref, RX VrefLevel [Byte0]: 66
8001 22:17:50.534431 [Byte1]: 66
8002 22:17:50.538880
8003 22:17:50.539446 Set Vref, RX VrefLevel [Byte0]: 67
8004 22:17:50.541614 [Byte1]: 67
8005 22:17:50.545729
8006 22:17:50.546248 Set Vref, RX VrefLevel [Byte0]: 68
8007 22:17:50.549239 [Byte1]: 68
8008 22:17:50.553413
8009 22:17:50.553981 Set Vref, RX VrefLevel [Byte0]: 69
8010 22:17:50.556657 [Byte1]: 69
8011 22:17:50.561260
8012 22:17:50.561818 Set Vref, RX VrefLevel [Byte0]: 70
8013 22:17:50.564586 [Byte1]: 70
8014 22:17:50.568462
8015 22:17:50.568959 Set Vref, RX VrefLevel [Byte0]: 71
8016 22:17:50.572249 [Byte1]: 71
8017 22:17:50.576466
8018 22:17:50.576986 Set Vref, RX VrefLevel [Byte0]: 72
8019 22:17:50.579598 [Byte1]: 72
8020 22:17:50.584049
8021 22:17:50.584635 Set Vref, RX VrefLevel [Byte0]: 73
8022 22:17:50.587175 [Byte1]: 73
8023 22:17:50.591472
8024 22:17:50.592031 Set Vref, RX VrefLevel [Byte0]: 74
8025 22:17:50.594928 [Byte1]: 74
8026 22:17:50.599037
8027 22:17:50.599565 Set Vref, RX VrefLevel [Byte0]: 75
8028 22:17:50.602485 [Byte1]: 75
8029 22:17:50.606417
8030 22:17:50.606969 Set Vref, RX VrefLevel [Byte0]: 76
8031 22:17:50.609767 [Byte1]: 76
8032 22:17:50.613842
8033 22:17:50.614303 Set Vref, RX VrefLevel [Byte0]: 77
8034 22:17:50.617196 [Byte1]: 77
8035 22:17:50.621729
8036 22:17:50.625179 Set Vref, RX VrefLevel [Byte0]: 78
8037 22:17:50.627710 [Byte1]: 78
8038 22:17:50.628129
8039 22:17:50.631499 Set Vref, RX VrefLevel [Byte0]: 79
8040 22:17:50.634432 [Byte1]: 79
8041 22:17:50.634854
8042 22:17:50.637868 Final RX Vref Byte 0 = 67 to rank0
8043 22:17:50.641004 Final RX Vref Byte 1 = 58 to rank0
8044 22:17:50.644459 Final RX Vref Byte 0 = 67 to rank1
8045 22:17:50.648353 Final RX Vref Byte 1 = 58 to rank1==
8046 22:17:50.650963 Dram Type= 6, Freq= 0, CH_0, rank 0
8047 22:17:50.653967 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8048 22:17:50.654403 ==
8049 22:17:50.657869 DQS Delay:
8050 22:17:50.658280 DQS0 = 0, DQS1 = 0
8051 22:17:50.660505 DQM Delay:
8052 22:17:50.660961 DQM0 = 133, DQM1 = 123
8053 22:17:50.661288 DQ Delay:
8054 22:17:50.667314 DQ0 =132, DQ1 =136, DQ2 =132, DQ3 =132
8055 22:17:50.670677 DQ4 =132, DQ5 =122, DQ6 =142, DQ7 =140
8056 22:17:50.673807 DQ8 =116, DQ9 =112, DQ10 =122, DQ11 =118
8057 22:17:50.676814 DQ12 =130, DQ13 =128, DQ14 =134, DQ15 =130
8058 22:17:50.677246
8059 22:17:50.677565
8060 22:17:50.677862
8061 22:17:50.680673 [DramC_TX_OE_Calibration] TA2
8062 22:17:50.683749 Original DQ_B0 (3 6) =30, OEN = 27
8063 22:17:50.686757 Original DQ_B1 (3 6) =30, OEN = 27
8064 22:17:50.687200 24, 0x0, End_B0=24 End_B1=24
8065 22:17:50.689990 25, 0x0, End_B0=25 End_B1=25
8066 22:17:50.693435 26, 0x0, End_B0=26 End_B1=26
8067 22:17:50.697375 27, 0x0, End_B0=27 End_B1=27
8068 22:17:50.700332 28, 0x0, End_B0=28 End_B1=28
8069 22:17:50.700927 29, 0x0, End_B0=29 End_B1=29
8070 22:17:50.703783 30, 0x0, End_B0=30 End_B1=30
8071 22:17:50.706940 31, 0x4141, End_B0=30 End_B1=30
8072 22:17:50.709995 Byte0 end_step=30 best_step=27
8073 22:17:50.713520 Byte1 end_step=30 best_step=27
8074 22:17:50.716502 Byte0 TX OE(2T, 0.5T) = (3, 3)
8075 22:17:50.716982 Byte1 TX OE(2T, 0.5T) = (3, 3)
8076 22:17:50.717422
8077 22:17:50.719945
8078 22:17:50.726750 [DQSOSCAuto] RK0, (LSB)MR18= 0x1f10, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 394 ps
8079 22:17:50.729867 CH0 RK0: MR19=303, MR18=1F10
8080 22:17:50.736677 CH0_RK0: MR19=0x303, MR18=0x1F10, DQSOSC=394, MR23=63, INC=23, DEC=15
8081 22:17:50.737193
8082 22:17:50.739789 ----->DramcWriteLeveling(PI) begin...
8083 22:17:50.740228 ==
8084 22:17:50.743155 Dram Type= 6, Freq= 0, CH_0, rank 1
8085 22:17:50.746817 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8086 22:17:50.747251 ==
8087 22:17:50.749727 Write leveling (Byte 0): 34 => 34
8088 22:17:50.753028 Write leveling (Byte 1): 27 => 27
8089 22:17:50.756107 DramcWriteLeveling(PI) end<-----
8090 22:17:50.756564
8091 22:17:50.756922 ==
8092 22:17:50.759598 Dram Type= 6, Freq= 0, CH_0, rank 1
8093 22:17:50.762752 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8094 22:17:50.763174 ==
8095 22:17:50.766247 [Gating] SW mode calibration
8096 22:17:50.772633 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8097 22:17:50.779834 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8098 22:17:50.783332 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8099 22:17:50.789049 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8100 22:17:50.793027 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8101 22:17:50.796206 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8102 22:17:50.802772 1 4 16 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
8103 22:17:50.805834 1 4 20 | B1->B0 | 2f2f 3434 | 0 1 | (1 1) (1 1)
8104 22:17:50.808870 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8105 22:17:50.812441 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8106 22:17:50.819130 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8107 22:17:50.822141 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8108 22:17:50.829307 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8109 22:17:50.831857 1 5 12 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
8110 22:17:50.835530 1 5 16 | B1->B0 | 3434 2828 | 1 0 | (1 0) (1 1)
8111 22:17:50.838854 1 5 20 | B1->B0 | 3333 2323 | 0 0 | (0 1) (0 0)
8112 22:17:50.845834 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8113 22:17:50.849026 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8114 22:17:50.855072 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8115 22:17:50.858960 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8116 22:17:50.861712 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8117 22:17:50.869059 1 6 12 | B1->B0 | 2323 2d2c | 0 1 | (0 0) (0 0)
8118 22:17:50.871693 1 6 16 | B1->B0 | 2424 4444 | 0 0 | (0 0) (0 0)
8119 22:17:50.874907 1 6 20 | B1->B0 | 2e2e 4646 | 0 0 | (0 0) (0 0)
8120 22:17:50.878241 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8121 22:17:50.885228 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8122 22:17:50.888016 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8123 22:17:50.892006 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8124 22:17:50.897915 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8125 22:17:50.901388 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8126 22:17:50.905807 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8127 22:17:50.911585 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8128 22:17:50.914889 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8129 22:17:50.917907 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8130 22:17:50.924254 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8131 22:17:50.927952 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8132 22:17:50.930936 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8133 22:17:50.937497 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8134 22:17:50.941076 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8135 22:17:50.944481 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8136 22:17:50.951146 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8137 22:17:50.954397 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8138 22:17:50.957375 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8139 22:17:50.964222 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8140 22:17:50.967216 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8141 22:17:50.970799 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8142 22:17:50.973844 Total UI for P1: 0, mck2ui 16
8143 22:17:50.977003 best dqsien dly found for B0: ( 1, 9, 10)
8144 22:17:50.983909 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8145 22:17:50.987132 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8146 22:17:50.990336 Total UI for P1: 0, mck2ui 16
8147 22:17:50.993855 best dqsien dly found for B1: ( 1, 9, 16)
8148 22:17:50.997773 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8149 22:17:51.000396 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8150 22:17:51.000866
8151 22:17:51.003915 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8152 22:17:51.010730 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8153 22:17:51.011245 [Gating] SW calibration Done
8154 22:17:51.011573 ==
8155 22:17:51.013802 Dram Type= 6, Freq= 0, CH_0, rank 1
8156 22:17:51.020312 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8157 22:17:51.020864 ==
8158 22:17:51.021195 RX Vref Scan: 0
8159 22:17:51.021495
8160 22:17:51.023336 RX Vref 0 -> 0, step: 1
8161 22:17:51.023748
8162 22:17:51.026447 RX Delay 0 -> 252, step: 8
8163 22:17:51.030070 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8164 22:17:51.033873 iDelay=200, Bit 1, Center 139 (80 ~ 199) 120
8165 22:17:51.036548 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8166 22:17:51.043258 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8167 22:17:51.046946 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8168 22:17:51.049747 iDelay=200, Bit 5, Center 123 (64 ~ 183) 120
8169 22:17:51.052975 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8170 22:17:51.056123 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8171 22:17:51.062918 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8172 22:17:51.066618 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8173 22:17:51.069323 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8174 22:17:51.072641 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8175 22:17:51.075882 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8176 22:17:51.083663 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8177 22:17:51.086041 iDelay=200, Bit 14, Center 139 (80 ~ 199) 120
8178 22:17:51.089937 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8179 22:17:51.090362 ==
8180 22:17:51.092659 Dram Type= 6, Freq= 0, CH_0, rank 1
8181 22:17:51.095753 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8182 22:17:51.099491 ==
8183 22:17:51.099911 DQS Delay:
8184 22:17:51.100238 DQS0 = 0, DQS1 = 0
8185 22:17:51.102533 DQM Delay:
8186 22:17:51.102956 DQM0 = 133, DQM1 = 128
8187 22:17:51.105928 DQ Delay:
8188 22:17:51.109132 DQ0 =135, DQ1 =139, DQ2 =127, DQ3 =127
8189 22:17:51.112331 DQ4 =135, DQ5 =123, DQ6 =139, DQ7 =143
8190 22:17:51.115829 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =123
8191 22:17:51.119403 DQ12 =131, DQ13 =135, DQ14 =139, DQ15 =135
8192 22:17:51.119825
8193 22:17:51.120153
8194 22:17:51.120458 ==
8195 22:17:51.123269 Dram Type= 6, Freq= 0, CH_0, rank 1
8196 22:17:51.126068 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8197 22:17:51.126497 ==
8198 22:17:51.129416
8199 22:17:51.129832
8200 22:17:51.130162 TX Vref Scan disable
8201 22:17:51.132400 == TX Byte 0 ==
8202 22:17:51.135652 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8203 22:17:51.139619 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8204 22:17:51.142293 == TX Byte 1 ==
8205 22:17:51.145437 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8206 22:17:51.148739 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8207 22:17:51.149163 ==
8208 22:17:51.152279 Dram Type= 6, Freq= 0, CH_0, rank 1
8209 22:17:51.158681 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8210 22:17:51.159108 ==
8211 22:17:51.170379
8212 22:17:51.173733 TX Vref early break, caculate TX vref
8213 22:17:51.176934 TX Vref=16, minBit 1, minWin=22, winSum=378
8214 22:17:51.180280 TX Vref=18, minBit 1, minWin=23, winSum=386
8215 22:17:51.183605 TX Vref=20, minBit 0, minWin=24, winSum=394
8216 22:17:51.186456 TX Vref=22, minBit 0, minWin=24, winSum=401
8217 22:17:51.190460 TX Vref=24, minBit 1, minWin=24, winSum=407
8218 22:17:51.196458 TX Vref=26, minBit 0, minWin=24, winSum=414
8219 22:17:51.199845 TX Vref=28, minBit 1, minWin=24, winSum=406
8220 22:17:51.203092 TX Vref=30, minBit 0, minWin=24, winSum=403
8221 22:17:51.206212 TX Vref=32, minBit 1, minWin=23, winSum=390
8222 22:17:51.213612 [TxChooseVref] Worse bit 0, Min win 24, Win sum 414, Final Vref 26
8223 22:17:51.214130
8224 22:17:51.216208 Final TX Range 0 Vref 26
8225 22:17:51.216683
8226 22:17:51.217023 ==
8227 22:17:51.219724 Dram Type= 6, Freq= 0, CH_0, rank 1
8228 22:17:51.223127 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8229 22:17:51.223665 ==
8230 22:17:51.223999
8231 22:17:51.224309
8232 22:17:51.226956 TX Vref Scan disable
8233 22:17:51.233823 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8234 22:17:51.234439 == TX Byte 0 ==
8235 22:17:51.236284 u2DelayCellOfst[0]=14 cells (4 PI)
8236 22:17:51.239877 u2DelayCellOfst[1]=18 cells (5 PI)
8237 22:17:51.243215 u2DelayCellOfst[2]=14 cells (4 PI)
8238 22:17:51.246765 u2DelayCellOfst[3]=18 cells (5 PI)
8239 22:17:51.250653 u2DelayCellOfst[4]=11 cells (3 PI)
8240 22:17:51.252706 u2DelayCellOfst[5]=0 cells (0 PI)
8241 22:17:51.255960 u2DelayCellOfst[6]=18 cells (5 PI)
8242 22:17:51.259916 u2DelayCellOfst[7]=22 cells (6 PI)
8243 22:17:51.262376 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
8244 22:17:51.265767 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8245 22:17:51.269231 == TX Byte 1 ==
8246 22:17:51.269784 u2DelayCellOfst[8]=0 cells (0 PI)
8247 22:17:51.272559 u2DelayCellOfst[9]=3 cells (1 PI)
8248 22:17:51.275884 u2DelayCellOfst[10]=7 cells (2 PI)
8249 22:17:51.279629 u2DelayCellOfst[11]=3 cells (1 PI)
8250 22:17:51.282212 u2DelayCellOfst[12]=11 cells (3 PI)
8251 22:17:51.285812 u2DelayCellOfst[13]=11 cells (3 PI)
8252 22:17:51.289012 u2DelayCellOfst[14]=18 cells (5 PI)
8253 22:17:51.292417 u2DelayCellOfst[15]=11 cells (3 PI)
8254 22:17:51.295767 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8255 22:17:51.302356 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8256 22:17:51.302770 DramC Write-DBI on
8257 22:17:51.303094 ==
8258 22:17:51.305310 Dram Type= 6, Freq= 0, CH_0, rank 1
8259 22:17:51.312358 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8260 22:17:51.312886 ==
8261 22:17:51.313319
8262 22:17:51.313718
8263 22:17:51.314169 TX Vref Scan disable
8264 22:17:51.315996 == TX Byte 0 ==
8265 22:17:51.320022 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
8266 22:17:51.322733 == TX Byte 1 ==
8267 22:17:51.326298 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8268 22:17:51.329117 DramC Write-DBI off
8269 22:17:51.329543
8270 22:17:51.329963 [DATLAT]
8271 22:17:51.330362 Freq=1600, CH0 RK1
8272 22:17:51.330751
8273 22:17:51.332627 DATLAT Default: 0xf
8274 22:17:51.333048 0, 0xFFFF, sum = 0
8275 22:17:51.336454 1, 0xFFFF, sum = 0
8276 22:17:51.340499 2, 0xFFFF, sum = 0
8277 22:17:51.341069 3, 0xFFFF, sum = 0
8278 22:17:51.342236 4, 0xFFFF, sum = 0
8279 22:17:51.342661 5, 0xFFFF, sum = 0
8280 22:17:51.346018 6, 0xFFFF, sum = 0
8281 22:17:51.346511 7, 0xFFFF, sum = 0
8282 22:17:51.349086 8, 0xFFFF, sum = 0
8283 22:17:51.349511 9, 0xFFFF, sum = 0
8284 22:17:51.352385 10, 0xFFFF, sum = 0
8285 22:17:51.352958 11, 0xFFFF, sum = 0
8286 22:17:51.355393 12, 0xFFFF, sum = 0
8287 22:17:51.355822 13, 0xFFFF, sum = 0
8288 22:17:51.358920 14, 0x0, sum = 1
8289 22:17:51.359415 15, 0x0, sum = 2
8290 22:17:51.362506 16, 0x0, sum = 3
8291 22:17:51.363073 17, 0x0, sum = 4
8292 22:17:51.365548 best_step = 15
8293 22:17:51.366009
8294 22:17:51.366375 ==
8295 22:17:51.368930 Dram Type= 6, Freq= 0, CH_0, rank 1
8296 22:17:51.372025 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8297 22:17:51.372446 ==
8298 22:17:51.375876 RX Vref Scan: 0
8299 22:17:51.376293
8300 22:17:51.376674 RX Vref 0 -> 0, step: 1
8301 22:17:51.376987
8302 22:17:51.379017 RX Delay 11 -> 252, step: 4
8303 22:17:51.385632 iDelay=195, Bit 0, Center 128 (79 ~ 178) 100
8304 22:17:51.389114 iDelay=195, Bit 1, Center 134 (79 ~ 190) 112
8305 22:17:51.392943 iDelay=195, Bit 2, Center 124 (71 ~ 178) 108
8306 22:17:51.395084 iDelay=195, Bit 3, Center 128 (75 ~ 182) 108
8307 22:17:51.399052 iDelay=195, Bit 4, Center 132 (79 ~ 186) 108
8308 22:17:51.405097 iDelay=195, Bit 5, Center 120 (67 ~ 174) 108
8309 22:17:51.409466 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
8310 22:17:51.411819 iDelay=195, Bit 7, Center 140 (87 ~ 194) 108
8311 22:17:51.415203 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
8312 22:17:51.418186 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
8313 22:17:51.424773 iDelay=195, Bit 10, Center 126 (71 ~ 182) 112
8314 22:17:51.428718 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8315 22:17:51.432473 iDelay=195, Bit 12, Center 130 (75 ~ 186) 112
8316 22:17:51.435303 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8317 22:17:51.438616 iDelay=195, Bit 14, Center 136 (83 ~ 190) 108
8318 22:17:51.445476 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8319 22:17:51.446031 ==
8320 22:17:51.448218 Dram Type= 6, Freq= 0, CH_0, rank 1
8321 22:17:51.451739 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8322 22:17:51.452296 ==
8323 22:17:51.452711 DQS Delay:
8324 22:17:51.454866 DQS0 = 0, DQS1 = 0
8325 22:17:51.455322 DQM Delay:
8326 22:17:51.458236 DQM0 = 130, DQM1 = 125
8327 22:17:51.458784 DQ Delay:
8328 22:17:51.460928 DQ0 =128, DQ1 =134, DQ2 =124, DQ3 =128
8329 22:17:51.464559 DQ4 =132, DQ5 =120, DQ6 =138, DQ7 =140
8330 22:17:51.467610 DQ8 =116, DQ9 =112, DQ10 =126, DQ11 =120
8331 22:17:51.474469 DQ12 =130, DQ13 =132, DQ14 =136, DQ15 =132
8332 22:17:51.474929
8333 22:17:51.475264
8334 22:17:51.475562
8335 22:17:51.477467 [DramC_TX_OE_Calibration] TA2
8336 22:17:51.477928 Original DQ_B0 (3 6) =30, OEN = 27
8337 22:17:51.481012 Original DQ_B1 (3 6) =30, OEN = 27
8338 22:17:51.484662 24, 0x0, End_B0=24 End_B1=24
8339 22:17:51.487389 25, 0x0, End_B0=25 End_B1=25
8340 22:17:51.490570 26, 0x0, End_B0=26 End_B1=26
8341 22:17:51.494458 27, 0x0, End_B0=27 End_B1=27
8342 22:17:51.494936 28, 0x0, End_B0=28 End_B1=28
8343 22:17:51.497146 29, 0x0, End_B0=29 End_B1=29
8344 22:17:51.501008 30, 0x0, End_B0=30 End_B1=30
8345 22:17:51.503967 31, 0x4545, End_B0=30 End_B1=30
8346 22:17:51.507394 Byte0 end_step=30 best_step=27
8347 22:17:51.507910 Byte1 end_step=30 best_step=27
8348 22:17:51.510793 Byte0 TX OE(2T, 0.5T) = (3, 3)
8349 22:17:51.513791 Byte1 TX OE(2T, 0.5T) = (3, 3)
8350 22:17:51.514204
8351 22:17:51.514527
8352 22:17:51.524126 [DQSOSCAuto] RK1, (LSB)MR18= 0x1f02, (MSB)MR19= 0x303, tDQSOscB0 = 409 ps tDQSOscB1 = 394 ps
8353 22:17:51.524593 CH0 RK1: MR19=303, MR18=1F02
8354 22:17:51.530735 CH0_RK1: MR19=0x303, MR18=0x1F02, DQSOSC=394, MR23=63, INC=23, DEC=15
8355 22:17:51.533695 [RxdqsGatingPostProcess] freq 1600
8356 22:17:51.540164 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8357 22:17:51.544031 best DQS0 dly(2T, 0.5T) = (1, 1)
8358 22:17:51.547127 best DQS1 dly(2T, 0.5T) = (1, 1)
8359 22:17:51.550703 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8360 22:17:51.553446 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8361 22:17:51.557141 best DQS0 dly(2T, 0.5T) = (1, 1)
8362 22:17:51.557542 best DQS1 dly(2T, 0.5T) = (1, 1)
8363 22:17:51.560480 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8364 22:17:51.563640 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8365 22:17:51.566419 Pre-setting of DQS Precalculation
8366 22:17:51.573282 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8367 22:17:51.573793 ==
8368 22:17:51.576711 Dram Type= 6, Freq= 0, CH_1, rank 0
8369 22:17:51.580062 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8370 22:17:51.580629 ==
8371 22:17:51.586553 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8372 22:17:51.589974 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8373 22:17:51.592953 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8374 22:17:51.600092 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8375 22:17:51.608773 [CA 0] Center 41 (12~71) winsize 60
8376 22:17:51.612296 [CA 1] Center 42 (12~72) winsize 61
8377 22:17:51.616013 [CA 2] Center 37 (8~66) winsize 59
8378 22:17:51.618667 [CA 3] Center 36 (7~65) winsize 59
8379 22:17:51.622004 [CA 4] Center 37 (8~66) winsize 59
8380 22:17:51.625508 [CA 5] Center 36 (6~66) winsize 61
8381 22:17:51.626030
8382 22:17:51.628690 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8383 22:17:51.629111
8384 22:17:51.635331 [CATrainingPosCal] consider 1 rank data
8385 22:17:51.635749 u2DelayCellTimex100 = 262/100 ps
8386 22:17:51.641910 CA0 delay=41 (12~71),Diff = 5 PI (18 cell)
8387 22:17:51.645675 CA1 delay=42 (12~72),Diff = 6 PI (22 cell)
8388 22:17:51.648628 CA2 delay=37 (8~66),Diff = 1 PI (3 cell)
8389 22:17:51.652432 CA3 delay=36 (7~65),Diff = 0 PI (0 cell)
8390 22:17:51.655203 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
8391 22:17:51.658471 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
8392 22:17:51.659167
8393 22:17:51.661700 CA PerBit enable=1, Macro0, CA PI delay=36
8394 22:17:51.662105
8395 22:17:51.665163 [CBTSetCACLKResult] CA Dly = 36
8396 22:17:51.668189 CS Dly: 9 (0~40)
8397 22:17:51.671420 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8398 22:17:51.675248 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8399 22:17:51.675430 ==
8400 22:17:51.678259 Dram Type= 6, Freq= 0, CH_1, rank 1
8401 22:17:51.684338 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8402 22:17:51.684509 ==
8403 22:17:51.687971 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8404 22:17:51.691486 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8405 22:17:51.697751 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8406 22:17:51.704137 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8407 22:17:51.711712 [CA 0] Center 42 (12~72) winsize 61
8408 22:17:51.715606 [CA 1] Center 42 (13~72) winsize 60
8409 22:17:51.718476 [CA 2] Center 37 (8~67) winsize 60
8410 22:17:51.721686 [CA 3] Center 36 (7~66) winsize 60
8411 22:17:51.724854 [CA 4] Center 37 (8~67) winsize 60
8412 22:17:51.728993 [CA 5] Center 37 (8~67) winsize 60
8413 22:17:51.729407
8414 22:17:51.732080 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8415 22:17:51.732493
8416 22:17:51.738412 [CATrainingPosCal] consider 2 rank data
8417 22:17:51.739012 u2DelayCellTimex100 = 262/100 ps
8418 22:17:51.744772 CA0 delay=41 (12~71),Diff = 5 PI (18 cell)
8419 22:17:51.748210 CA1 delay=42 (13~72),Diff = 6 PI (22 cell)
8420 22:17:51.752172 CA2 delay=37 (8~66),Diff = 1 PI (3 cell)
8421 22:17:51.754959 CA3 delay=36 (7~65),Diff = 0 PI (0 cell)
8422 22:17:51.758358 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
8423 22:17:51.761538 CA5 delay=37 (8~66),Diff = 1 PI (3 cell)
8424 22:17:51.761956
8425 22:17:51.764889 CA PerBit enable=1, Macro0, CA PI delay=36
8426 22:17:51.765302
8427 22:17:51.768385 [CBTSetCACLKResult] CA Dly = 36
8428 22:17:51.771292 CS Dly: 10 (0~43)
8429 22:17:51.775109 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8430 22:17:51.778336 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8431 22:17:51.778558
8432 22:17:51.781118 ----->DramcWriteLeveling(PI) begin...
8433 22:17:51.781343 ==
8434 22:17:51.785181 Dram Type= 6, Freq= 0, CH_1, rank 0
8435 22:17:51.790989 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8436 22:17:51.791142 ==
8437 22:17:51.794174 Write leveling (Byte 0): 24 => 24
8438 22:17:51.797821 Write leveling (Byte 1): 29 => 29
8439 22:17:51.797935 DramcWriteLeveling(PI) end<-----
8440 22:17:51.798023
8441 22:17:51.800848 ==
8442 22:17:51.804278 Dram Type= 6, Freq= 0, CH_1, rank 0
8443 22:17:51.807861 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8444 22:17:51.808305 ==
8445 22:17:51.811330 [Gating] SW mode calibration
8446 22:17:51.817400 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8447 22:17:51.821081 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8448 22:17:51.827636 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8449 22:17:51.831006 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8450 22:17:51.834360 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8451 22:17:51.840728 1 4 12 | B1->B0 | 2b2b 3232 | 1 1 | (1 1) (1 1)
8452 22:17:51.843911 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8453 22:17:51.847243 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8454 22:17:51.854361 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8455 22:17:51.856998 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8456 22:17:51.860609 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8457 22:17:51.867647 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8458 22:17:51.871192 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
8459 22:17:51.873702 1 5 12 | B1->B0 | 3030 2525 | 1 0 | (1 0) (1 0)
8460 22:17:51.880187 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8461 22:17:51.883606 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8462 22:17:51.887121 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8463 22:17:51.893440 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8464 22:17:51.896948 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8465 22:17:51.900479 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8466 22:17:51.906514 1 6 8 | B1->B0 | 2424 2929 | 0 1 | (0 0) (0 0)
8467 22:17:51.910446 1 6 12 | B1->B0 | 3b3b 4646 | 1 0 | (0 0) (0 0)
8468 22:17:51.913247 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8469 22:17:51.919848 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8470 22:17:51.922776 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8471 22:17:51.926288 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8472 22:17:51.933304 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8473 22:17:51.936388 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8474 22:17:51.939464 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8475 22:17:51.945883 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8476 22:17:51.949314 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8477 22:17:51.952488 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8478 22:17:51.959002 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8479 22:17:51.962369 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8480 22:17:51.965934 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8481 22:17:51.972641 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8482 22:17:51.976405 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8483 22:17:51.979505 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8484 22:17:51.986408 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8485 22:17:51.989833 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8486 22:17:51.992199 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8487 22:17:51.999196 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8488 22:17:52.002826 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8489 22:17:52.005605 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8490 22:17:52.012588 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8491 22:17:52.016377 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8492 22:17:52.019384 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8493 22:17:52.022243 Total UI for P1: 0, mck2ui 16
8494 22:17:52.025509 best dqsien dly found for B0: ( 1, 9, 10)
8495 22:17:52.032920 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8496 22:17:52.033111 Total UI for P1: 0, mck2ui 16
8497 22:17:52.038814 best dqsien dly found for B1: ( 1, 9, 14)
8498 22:17:52.041950 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8499 22:17:52.045065 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8500 22:17:52.045198
8501 22:17:52.048266 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8502 22:17:52.052150 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8503 22:17:52.055581 [Gating] SW calibration Done
8504 22:17:52.055690 ==
8505 22:17:52.058491 Dram Type= 6, Freq= 0, CH_1, rank 0
8506 22:17:52.061480 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8507 22:17:52.061575 ==
8508 22:17:52.064750 RX Vref Scan: 0
8509 22:17:52.064837
8510 22:17:52.068130 RX Vref 0 -> 0, step: 1
8511 22:17:52.068215
8512 22:17:52.068298 RX Delay 0 -> 252, step: 8
8513 22:17:52.074856 iDelay=208, Bit 0, Center 143 (88 ~ 199) 112
8514 22:17:52.078339 iDelay=208, Bit 1, Center 131 (80 ~ 183) 104
8515 22:17:52.081425 iDelay=208, Bit 2, Center 127 (72 ~ 183) 112
8516 22:17:52.084488 iDelay=208, Bit 3, Center 139 (88 ~ 191) 104
8517 22:17:52.088164 iDelay=208, Bit 4, Center 135 (80 ~ 191) 112
8518 22:17:52.094424 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8519 22:17:52.097875 iDelay=208, Bit 6, Center 147 (96 ~ 199) 104
8520 22:17:52.101530 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8521 22:17:52.104491 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8522 22:17:52.108338 iDelay=208, Bit 9, Center 119 (64 ~ 175) 112
8523 22:17:52.115040 iDelay=208, Bit 10, Center 131 (80 ~ 183) 104
8524 22:17:52.118620 iDelay=208, Bit 11, Center 123 (72 ~ 175) 104
8525 22:17:52.121433 iDelay=208, Bit 12, Center 135 (80 ~ 191) 112
8526 22:17:52.124570 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8527 22:17:52.127564 iDelay=208, Bit 14, Center 139 (80 ~ 199) 120
8528 22:17:52.135167 iDelay=208, Bit 15, Center 143 (88 ~ 199) 112
8529 22:17:52.135496 ==
8530 22:17:52.137814 Dram Type= 6, Freq= 0, CH_1, rank 0
8531 22:17:52.141250 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8532 22:17:52.141587 ==
8533 22:17:52.141893 DQS Delay:
8534 22:17:52.144105 DQS0 = 0, DQS1 = 0
8535 22:17:52.144342 DQM Delay:
8536 22:17:52.147490 DQM0 = 138, DQM1 = 131
8537 22:17:52.147726 DQ Delay:
8538 22:17:52.150934 DQ0 =143, DQ1 =131, DQ2 =127, DQ3 =139
8539 22:17:52.154087 DQ4 =135, DQ5 =151, DQ6 =147, DQ7 =135
8540 22:17:52.157413 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
8541 22:17:52.161295 DQ12 =135, DQ13 =139, DQ14 =139, DQ15 =143
8542 22:17:52.164437
8543 22:17:52.165056
8544 22:17:52.165574 ==
8545 22:17:52.168141 Dram Type= 6, Freq= 0, CH_1, rank 0
8546 22:17:52.171111 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8547 22:17:52.171696 ==
8548 22:17:52.172198
8549 22:17:52.172547
8550 22:17:52.173899 TX Vref Scan disable
8551 22:17:52.174372 == TX Byte 0 ==
8552 22:17:52.181597 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8553 22:17:52.184004 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8554 22:17:52.184573 == TX Byte 1 ==
8555 22:17:52.190842 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8556 22:17:52.194155 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8557 22:17:52.194571 ==
8558 22:17:52.197162 Dram Type= 6, Freq= 0, CH_1, rank 0
8559 22:17:52.200367 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8560 22:17:52.200855 ==
8561 22:17:52.214303
8562 22:17:52.217540 TX Vref early break, caculate TX vref
8563 22:17:52.220802 TX Vref=16, minBit 5, minWin=21, winSum=370
8564 22:17:52.224223 TX Vref=18, minBit 6, minWin=22, winSum=381
8565 22:17:52.227495 TX Vref=20, minBit 5, minWin=22, winSum=389
8566 22:17:52.230742 TX Vref=22, minBit 0, minWin=24, winSum=404
8567 22:17:52.233788 TX Vref=24, minBit 0, minWin=25, winSum=413
8568 22:17:52.241211 TX Vref=26, minBit 0, minWin=25, winSum=413
8569 22:17:52.244046 TX Vref=28, minBit 5, minWin=24, winSum=414
8570 22:17:52.247330 TX Vref=30, minBit 0, minWin=23, winSum=404
8571 22:17:52.250559 TX Vref=32, minBit 0, minWin=23, winSum=396
8572 22:17:52.253572 TX Vref=34, minBit 6, minWin=23, winSum=391
8573 22:17:52.260472 [TxChooseVref] Worse bit 0, Min win 25, Win sum 413, Final Vref 24
8574 22:17:52.260571
8575 22:17:52.263480 Final TX Range 0 Vref 24
8576 22:17:52.263564
8577 22:17:52.263628 ==
8578 22:17:52.267059 Dram Type= 6, Freq= 0, CH_1, rank 0
8579 22:17:52.270611 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8580 22:17:52.270696 ==
8581 22:17:52.270761
8582 22:17:52.270820
8583 22:17:52.273892 TX Vref Scan disable
8584 22:17:52.280335 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8585 22:17:52.280418 == TX Byte 0 ==
8586 22:17:52.283768 u2DelayCellOfst[0]=14 cells (4 PI)
8587 22:17:52.286901 u2DelayCellOfst[1]=11 cells (3 PI)
8588 22:17:52.290211 u2DelayCellOfst[2]=0 cells (0 PI)
8589 22:17:52.292961 u2DelayCellOfst[3]=3 cells (1 PI)
8590 22:17:52.296457 u2DelayCellOfst[4]=7 cells (2 PI)
8591 22:17:52.300069 u2DelayCellOfst[5]=18 cells (5 PI)
8592 22:17:52.303166 u2DelayCellOfst[6]=18 cells (5 PI)
8593 22:17:52.306562 u2DelayCellOfst[7]=3 cells (1 PI)
8594 22:17:52.309817 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8595 22:17:52.313031 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8596 22:17:52.316066 == TX Byte 1 ==
8597 22:17:52.319513 u2DelayCellOfst[8]=0 cells (0 PI)
8598 22:17:52.322984 u2DelayCellOfst[9]=3 cells (1 PI)
8599 22:17:52.326513 u2DelayCellOfst[10]=14 cells (4 PI)
8600 22:17:52.329626 u2DelayCellOfst[11]=3 cells (1 PI)
8601 22:17:52.329938 u2DelayCellOfst[12]=18 cells (5 PI)
8602 22:17:52.332629 u2DelayCellOfst[13]=18 cells (5 PI)
8603 22:17:52.336545 u2DelayCellOfst[14]=18 cells (5 PI)
8604 22:17:52.339923 u2DelayCellOfst[15]=18 cells (5 PI)
8605 22:17:52.346943 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8606 22:17:52.349523 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8607 22:17:52.349992 DramC Write-DBI on
8608 22:17:52.352698 ==
8609 22:17:52.355874 Dram Type= 6, Freq= 0, CH_1, rank 0
8610 22:17:52.360124 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8611 22:17:52.360730 ==
8612 22:17:52.361104
8613 22:17:52.361440
8614 22:17:52.362768 TX Vref Scan disable
8615 22:17:52.363301 == TX Byte 0 ==
8616 22:17:52.369347 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8617 22:17:52.369781 == TX Byte 1 ==
8618 22:17:52.372741 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8619 22:17:52.375784 DramC Write-DBI off
8620 22:17:52.376251
8621 22:17:52.376748 [DATLAT]
8622 22:17:52.380007 Freq=1600, CH1 RK0
8623 22:17:52.380426
8624 22:17:52.380823 DATLAT Default: 0xf
8625 22:17:52.382224 0, 0xFFFF, sum = 0
8626 22:17:52.382811 1, 0xFFFF, sum = 0
8627 22:17:52.386168 2, 0xFFFF, sum = 0
8628 22:17:52.386709 3, 0xFFFF, sum = 0
8629 22:17:52.389037 4, 0xFFFF, sum = 0
8630 22:17:52.389483 5, 0xFFFF, sum = 0
8631 22:17:52.392139 6, 0xFFFF, sum = 0
8632 22:17:52.395756 7, 0xFFFF, sum = 0
8633 22:17:52.396179 8, 0xFFFF, sum = 0
8634 22:17:52.398919 9, 0xFFFF, sum = 0
8635 22:17:52.399345 10, 0xFFFF, sum = 0
8636 22:17:52.402834 11, 0xFFFF, sum = 0
8637 22:17:52.403460 12, 0xFFFF, sum = 0
8638 22:17:52.405862 13, 0xFFFF, sum = 0
8639 22:17:52.406286 14, 0x0, sum = 1
8640 22:17:52.408837 15, 0x0, sum = 2
8641 22:17:52.409261 16, 0x0, sum = 3
8642 22:17:52.412695 17, 0x0, sum = 4
8643 22:17:52.413113 best_step = 15
8644 22:17:52.413434
8645 22:17:52.413771 ==
8646 22:17:52.415929 Dram Type= 6, Freq= 0, CH_1, rank 0
8647 22:17:52.419026 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8648 22:17:52.422432 ==
8649 22:17:52.422841 RX Vref Scan: 1
8650 22:17:52.423161
8651 22:17:52.425360 Set Vref Range= 24 -> 127
8652 22:17:52.425772
8653 22:17:52.428411 RX Vref 24 -> 127, step: 1
8654 22:17:52.428866
8655 22:17:52.429194 RX Delay 19 -> 252, step: 4
8656 22:17:52.429496
8657 22:17:52.431771 Set Vref, RX VrefLevel [Byte0]: 24
8658 22:17:52.435642 [Byte1]: 24
8659 22:17:52.439342
8660 22:17:52.439854 Set Vref, RX VrefLevel [Byte0]: 25
8661 22:17:52.442953 [Byte1]: 25
8662 22:17:52.446580
8663 22:17:52.447277 Set Vref, RX VrefLevel [Byte0]: 26
8664 22:17:52.450031 [Byte1]: 26
8665 22:17:52.454706
8666 22:17:52.455256 Set Vref, RX VrefLevel [Byte0]: 27
8667 22:17:52.457610 [Byte1]: 27
8668 22:17:52.461791
8669 22:17:52.462349 Set Vref, RX VrefLevel [Byte0]: 28
8670 22:17:52.465082 [Byte1]: 28
8671 22:17:52.469549
8672 22:17:52.470004 Set Vref, RX VrefLevel [Byte0]: 29
8673 22:17:52.473005 [Byte1]: 29
8674 22:17:52.476983
8675 22:17:52.477403 Set Vref, RX VrefLevel [Byte0]: 30
8676 22:17:52.479868 [Byte1]: 30
8677 22:17:52.484652
8678 22:17:52.485068 Set Vref, RX VrefLevel [Byte0]: 31
8679 22:17:52.487599 [Byte1]: 31
8680 22:17:52.493112
8681 22:17:52.493634 Set Vref, RX VrefLevel [Byte0]: 32
8682 22:17:52.495514 [Byte1]: 32
8683 22:17:52.499702
8684 22:17:52.500157 Set Vref, RX VrefLevel [Byte0]: 33
8685 22:17:52.506120 [Byte1]: 33
8686 22:17:52.506690
8687 22:17:52.509243 Set Vref, RX VrefLevel [Byte0]: 34
8688 22:17:52.512560 [Byte1]: 34
8689 22:17:52.513021
8690 22:17:52.516271 Set Vref, RX VrefLevel [Byte0]: 35
8691 22:17:52.519504 [Byte1]: 35
8692 22:17:52.520066
8693 22:17:52.522580 Set Vref, RX VrefLevel [Byte0]: 36
8694 22:17:52.525567 [Byte1]: 36
8695 22:17:52.530369
8696 22:17:52.530918 Set Vref, RX VrefLevel [Byte0]: 37
8697 22:17:52.533417 [Byte1]: 37
8698 22:17:52.537637
8699 22:17:52.538199 Set Vref, RX VrefLevel [Byte0]: 38
8700 22:17:52.540990 [Byte1]: 38
8701 22:17:52.545119
8702 22:17:52.545680 Set Vref, RX VrefLevel [Byte0]: 39
8703 22:17:52.548478 [Byte1]: 39
8704 22:17:52.553062
8705 22:17:52.553626 Set Vref, RX VrefLevel [Byte0]: 40
8706 22:17:52.555883 [Byte1]: 40
8707 22:17:52.560186
8708 22:17:52.560767 Set Vref, RX VrefLevel [Byte0]: 41
8709 22:17:52.563448 [Byte1]: 41
8710 22:17:52.568104
8711 22:17:52.568842 Set Vref, RX VrefLevel [Byte0]: 42
8712 22:17:52.571397 [Byte1]: 42
8713 22:17:52.575204
8714 22:17:52.575666 Set Vref, RX VrefLevel [Byte0]: 43
8715 22:17:52.578524 [Byte1]: 43
8716 22:17:52.583180
8717 22:17:52.583673 Set Vref, RX VrefLevel [Byte0]: 44
8718 22:17:52.586842 [Byte1]: 44
8719 22:17:52.590699
8720 22:17:52.591161 Set Vref, RX VrefLevel [Byte0]: 45
8721 22:17:52.593520 [Byte1]: 45
8722 22:17:52.598209
8723 22:17:52.598859 Set Vref, RX VrefLevel [Byte0]: 46
8724 22:17:52.601059 [Byte1]: 46
8725 22:17:52.605502
8726 22:17:52.605964 Set Vref, RX VrefLevel [Byte0]: 47
8727 22:17:52.608998 [Byte1]: 47
8728 22:17:52.613172
8729 22:17:52.613590 Set Vref, RX VrefLevel [Byte0]: 48
8730 22:17:52.616404 [Byte1]: 48
8731 22:17:52.620657
8732 22:17:52.621079 Set Vref, RX VrefLevel [Byte0]: 49
8733 22:17:52.624067 [Byte1]: 49
8734 22:17:52.628468
8735 22:17:52.629048 Set Vref, RX VrefLevel [Byte0]: 50
8736 22:17:52.631897 [Byte1]: 50
8737 22:17:52.636766
8738 22:17:52.637305 Set Vref, RX VrefLevel [Byte0]: 51
8739 22:17:52.639436 [Byte1]: 51
8740 22:17:52.643439
8741 22:17:52.643904 Set Vref, RX VrefLevel [Byte0]: 52
8742 22:17:52.646674 [Byte1]: 52
8743 22:17:52.650919
8744 22:17:52.651381 Set Vref, RX VrefLevel [Byte0]: 53
8745 22:17:52.654829 [Byte1]: 53
8746 22:17:52.658589
8747 22:17:52.659006 Set Vref, RX VrefLevel [Byte0]: 54
8748 22:17:52.662032 [Byte1]: 54
8749 22:17:52.666177
8750 22:17:52.666594 Set Vref, RX VrefLevel [Byte0]: 55
8751 22:17:52.669443 [Byte1]: 55
8752 22:17:52.673775
8753 22:17:52.674192 Set Vref, RX VrefLevel [Byte0]: 56
8754 22:17:52.677014 [Byte1]: 56
8755 22:17:52.681274
8756 22:17:52.681693 Set Vref, RX VrefLevel [Byte0]: 57
8757 22:17:52.685434 [Byte1]: 57
8758 22:17:52.688725
8759 22:17:52.689150 Set Vref, RX VrefLevel [Byte0]: 58
8760 22:17:52.692350 [Byte1]: 58
8761 22:17:52.696769
8762 22:17:52.697289 Set Vref, RX VrefLevel [Byte0]: 59
8763 22:17:52.700278 [Byte1]: 59
8764 22:17:52.704606
8765 22:17:52.705025 Set Vref, RX VrefLevel [Byte0]: 60
8766 22:17:52.708203 [Byte1]: 60
8767 22:17:52.712169
8768 22:17:52.712730 Set Vref, RX VrefLevel [Byte0]: 61
8769 22:17:52.715067 [Byte1]: 61
8770 22:17:52.719193
8771 22:17:52.719718 Set Vref, RX VrefLevel [Byte0]: 62
8772 22:17:52.722286 [Byte1]: 62
8773 22:17:52.726739
8774 22:17:52.727158 Set Vref, RX VrefLevel [Byte0]: 63
8775 22:17:52.730235 [Byte1]: 63
8776 22:17:52.734343
8777 22:17:52.734843 Set Vref, RX VrefLevel [Byte0]: 64
8778 22:17:52.737760 [Byte1]: 64
8779 22:17:52.741703
8780 22:17:52.742147 Set Vref, RX VrefLevel [Byte0]: 65
8781 22:17:52.745377 [Byte1]: 65
8782 22:17:52.749782
8783 22:17:52.750292 Set Vref, RX VrefLevel [Byte0]: 66
8784 22:17:52.752676 [Byte1]: 66
8785 22:17:52.757250
8786 22:17:52.757761 Set Vref, RX VrefLevel [Byte0]: 67
8787 22:17:52.760418 [Byte1]: 67
8788 22:17:52.765242
8789 22:17:52.765674 Set Vref, RX VrefLevel [Byte0]: 68
8790 22:17:52.767897 [Byte1]: 68
8791 22:17:52.772606
8792 22:17:52.773119 Set Vref, RX VrefLevel [Byte0]: 69
8793 22:17:52.775454 [Byte1]: 69
8794 22:17:52.779512
8795 22:17:52.779945 Set Vref, RX VrefLevel [Byte0]: 70
8796 22:17:52.783648 [Byte1]: 70
8797 22:17:52.787276
8798 22:17:52.787786 Set Vref, RX VrefLevel [Byte0]: 71
8799 22:17:52.790793 [Byte1]: 71
8800 22:17:52.794979
8801 22:17:52.795430 Set Vref, RX VrefLevel [Byte0]: 72
8802 22:17:52.797975 [Byte1]: 72
8803 22:17:52.802474
8804 22:17:52.802888 Set Vref, RX VrefLevel [Byte0]: 73
8805 22:17:52.805981 [Byte1]: 73
8806 22:17:52.809962
8807 22:17:52.810377 Set Vref, RX VrefLevel [Byte0]: 74
8808 22:17:52.813687 [Byte1]: 74
8809 22:17:52.817733
8810 22:17:52.818159 Final RX Vref Byte 0 = 52 to rank0
8811 22:17:52.822343 Final RX Vref Byte 1 = 58 to rank0
8812 22:17:52.824093 Final RX Vref Byte 0 = 52 to rank1
8813 22:17:52.827410 Final RX Vref Byte 1 = 58 to rank1==
8814 22:17:52.830884 Dram Type= 6, Freq= 0, CH_1, rank 0
8815 22:17:52.837646 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8816 22:17:52.838179 ==
8817 22:17:52.838517 DQS Delay:
8818 22:17:52.838825 DQS0 = 0, DQS1 = 0
8819 22:17:52.840596 DQM Delay:
8820 22:17:52.841012 DQM0 = 134, DQM1 = 129
8821 22:17:52.844691 DQ Delay:
8822 22:17:52.848132 DQ0 =142, DQ1 =128, DQ2 =124, DQ3 =130
8823 22:17:52.850493 DQ4 =132, DQ5 =148, DQ6 =144, DQ7 =128
8824 22:17:52.854283 DQ8 =116, DQ9 =116, DQ10 =132, DQ11 =118
8825 22:17:52.857010 DQ12 =138, DQ13 =138, DQ14 =138, DQ15 =138
8826 22:17:52.857447
8827 22:17:52.857770
8828 22:17:52.858070
8829 22:17:52.861094 [DramC_TX_OE_Calibration] TA2
8830 22:17:52.863909 Original DQ_B0 (3 6) =30, OEN = 27
8831 22:17:52.867298 Original DQ_B1 (3 6) =30, OEN = 27
8832 22:17:52.870623 24, 0x0, End_B0=24 End_B1=24
8833 22:17:52.871051 25, 0x0, End_B0=25 End_B1=25
8834 22:17:52.873460 26, 0x0, End_B0=26 End_B1=26
8835 22:17:52.877131 27, 0x0, End_B0=27 End_B1=27
8836 22:17:52.880453 28, 0x0, End_B0=28 End_B1=28
8837 22:17:52.883738 29, 0x0, End_B0=29 End_B1=29
8838 22:17:52.884308 30, 0x0, End_B0=30 End_B1=30
8839 22:17:52.886838 31, 0x4141, End_B0=30 End_B1=30
8840 22:17:52.890250 Byte0 end_step=30 best_step=27
8841 22:17:52.893873 Byte1 end_step=30 best_step=27
8842 22:17:52.896655 Byte0 TX OE(2T, 0.5T) = (3, 3)
8843 22:17:52.900203 Byte1 TX OE(2T, 0.5T) = (3, 3)
8844 22:17:52.900661
8845 22:17:52.900994
8846 22:17:52.907279 [DQSOSCAuto] RK0, (LSB)MR18= 0x160c, (MSB)MR19= 0x303, tDQSOscB0 = 403 ps tDQSOscB1 = 398 ps
8847 22:17:52.910134 CH1 RK0: MR19=303, MR18=160C
8848 22:17:52.916566 CH1_RK0: MR19=0x303, MR18=0x160C, DQSOSC=398, MR23=63, INC=23, DEC=15
8849 22:17:52.916994
8850 22:17:52.920039 ----->DramcWriteLeveling(PI) begin...
8851 22:17:52.920621 ==
8852 22:17:52.923821 Dram Type= 6, Freq= 0, CH_1, rank 1
8853 22:17:52.927105 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8854 22:17:52.927626 ==
8855 22:17:52.929848 Write leveling (Byte 0): 24 => 24
8856 22:17:52.932939 Write leveling (Byte 1): 28 => 28
8857 22:17:52.936501 DramcWriteLeveling(PI) end<-----
8858 22:17:52.936955
8859 22:17:52.937278 ==
8860 22:17:52.939775 Dram Type= 6, Freq= 0, CH_1, rank 1
8861 22:17:52.943809 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8862 22:17:52.946548 ==
8863 22:17:52.947074 [Gating] SW mode calibration
8864 22:17:52.956431 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8865 22:17:52.959536 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8866 22:17:52.962742 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8867 22:17:52.969471 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8868 22:17:52.972893 1 4 8 | B1->B0 | 2524 2323 | 1 0 | (0 0) (0 0)
8869 22:17:52.975825 1 4 12 | B1->B0 | 3333 2323 | 1 0 | (1 1) (0 0)
8870 22:17:52.982783 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8871 22:17:52.985730 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8872 22:17:52.989448 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8873 22:17:52.995973 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8874 22:17:52.999572 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8875 22:17:53.003200 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8876 22:17:53.008830 1 5 8 | B1->B0 | 3434 3434 | 0 1 | (0 1) (1 0)
8877 22:17:53.012669 1 5 12 | B1->B0 | 2727 3434 | 0 1 | (0 1) (1 0)
8878 22:17:53.015731 1 5 16 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8879 22:17:53.022461 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8880 22:17:53.025640 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8881 22:17:53.029031 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8882 22:17:53.035947 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8883 22:17:53.038949 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8884 22:17:53.041897 1 6 8 | B1->B0 | 2726 2323 | 1 0 | (1 1) (0 0)
8885 22:17:53.048378 1 6 12 | B1->B0 | 4444 2323 | 0 0 | (1 1) (0 0)
8886 22:17:53.052023 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8887 22:17:53.055179 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8888 22:17:53.061669 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8889 22:17:53.064812 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8890 22:17:53.068554 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8891 22:17:53.075185 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8892 22:17:53.078334 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8893 22:17:53.081626 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8894 22:17:53.088474 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8895 22:17:53.091280 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8896 22:17:53.094587 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8897 22:17:53.101188 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8898 22:17:53.104967 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8899 22:17:53.108144 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8900 22:17:53.114943 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8901 22:17:53.118169 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8902 22:17:53.121115 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8903 22:17:53.127693 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8904 22:17:53.131425 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8905 22:17:53.134258 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8906 22:17:53.140770 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8907 22:17:53.143978 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8908 22:17:53.147461 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8909 22:17:53.154280 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8910 22:17:53.157541 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8911 22:17:53.161512 Total UI for P1: 0, mck2ui 16
8912 22:17:53.163854 best dqsien dly found for B0: ( 1, 9, 10)
8913 22:17:53.167341 Total UI for P1: 0, mck2ui 16
8914 22:17:53.170911 best dqsien dly found for B1: ( 1, 9, 10)
8915 22:17:53.173947 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8916 22:17:53.177117 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8917 22:17:53.177532
8918 22:17:53.180458 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8919 22:17:53.184170 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8920 22:17:53.187521 [Gating] SW calibration Done
8921 22:17:53.188086 ==
8922 22:17:53.190662 Dram Type= 6, Freq= 0, CH_1, rank 1
8923 22:17:53.197234 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8924 22:17:53.197781 ==
8925 22:17:53.198150 RX Vref Scan: 0
8926 22:17:53.198482
8927 22:17:53.200298 RX Vref 0 -> 0, step: 1
8928 22:17:53.200869
8929 22:17:53.203712 RX Delay 0 -> 252, step: 8
8930 22:17:53.207154 iDelay=208, Bit 0, Center 139 (80 ~ 199) 120
8931 22:17:53.210880 iDelay=208, Bit 1, Center 131 (72 ~ 191) 120
8932 22:17:53.213597 iDelay=208, Bit 2, Center 123 (64 ~ 183) 120
8933 22:17:53.216825 iDelay=208, Bit 3, Center 135 (80 ~ 191) 112
8934 22:17:53.223529 iDelay=208, Bit 4, Center 131 (72 ~ 191) 120
8935 22:17:53.226939 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8936 22:17:53.229874 iDelay=208, Bit 6, Center 147 (88 ~ 207) 120
8937 22:17:53.233084 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8938 22:17:53.239523 iDelay=208, Bit 8, Center 115 (56 ~ 175) 120
8939 22:17:53.243124 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8940 22:17:53.246860 iDelay=208, Bit 10, Center 131 (72 ~ 191) 120
8941 22:17:53.250508 iDelay=208, Bit 11, Center 123 (64 ~ 183) 120
8942 22:17:53.253383 iDelay=208, Bit 12, Center 139 (80 ~ 199) 120
8943 22:17:53.259746 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8944 22:17:53.262755 iDelay=208, Bit 14, Center 135 (80 ~ 191) 112
8945 22:17:53.266015 iDelay=208, Bit 15, Center 139 (80 ~ 199) 120
8946 22:17:53.266478 ==
8947 22:17:53.269489 Dram Type= 6, Freq= 0, CH_1, rank 1
8948 22:17:53.272802 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8949 22:17:53.273224 ==
8950 22:17:53.276686 DQS Delay:
8951 22:17:53.277150 DQS0 = 0, DQS1 = 0
8952 22:17:53.279589 DQM Delay:
8953 22:17:53.280044 DQM0 = 136, DQM1 = 129
8954 22:17:53.283167 DQ Delay:
8955 22:17:53.285997 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8956 22:17:53.289651 DQ4 =131, DQ5 =151, DQ6 =147, DQ7 =135
8957 22:17:53.292950 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =123
8958 22:17:53.295880 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =139
8959 22:17:53.296299
8960 22:17:53.296689
8961 22:17:53.297006 ==
8962 22:17:53.299528 Dram Type= 6, Freq= 0, CH_1, rank 1
8963 22:17:53.302243 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8964 22:17:53.302665 ==
8965 22:17:53.302996
8966 22:17:53.305818
8967 22:17:53.306231 TX Vref Scan disable
8968 22:17:53.309741 == TX Byte 0 ==
8969 22:17:53.312730 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8970 22:17:53.316081 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8971 22:17:53.319455 == TX Byte 1 ==
8972 22:17:53.322541 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8973 22:17:53.325700 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8974 22:17:53.326118 ==
8975 22:17:53.329476 Dram Type= 6, Freq= 0, CH_1, rank 1
8976 22:17:53.336207 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8977 22:17:53.336861 ==
8978 22:17:53.348681
8979 22:17:53.351660 TX Vref early break, caculate TX vref
8980 22:17:53.354975 TX Vref=16, minBit 8, minWin=22, winSum=382
8981 22:17:53.358844 TX Vref=18, minBit 0, minWin=23, winSum=391
8982 22:17:53.362409 TX Vref=20, minBit 0, minWin=24, winSum=403
8983 22:17:53.365050 TX Vref=22, minBit 0, minWin=23, winSum=404
8984 22:17:53.368145 TX Vref=24, minBit 5, minWin=24, winSum=411
8985 22:17:53.375060 TX Vref=26, minBit 0, minWin=24, winSum=415
8986 22:17:53.377886 TX Vref=28, minBit 0, minWin=24, winSum=415
8987 22:17:53.381196 TX Vref=30, minBit 0, minWin=25, winSum=413
8988 22:17:53.384543 TX Vref=32, minBit 0, minWin=24, winSum=405
8989 22:17:53.387933 TX Vref=34, minBit 1, minWin=23, winSum=396
8990 22:17:53.394194 TX Vref=36, minBit 0, minWin=22, winSum=388
8991 22:17:53.397890 [TxChooseVref] Worse bit 0, Min win 25, Win sum 413, Final Vref 30
8992 22:17:53.398308
8993 22:17:53.400766 Final TX Range 0 Vref 30
8994 22:17:53.401183
8995 22:17:53.401507 ==
8996 22:17:53.404312 Dram Type= 6, Freq= 0, CH_1, rank 1
8997 22:17:53.407936 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8998 22:17:53.411576 ==
8999 22:17:53.412059
9000 22:17:53.412385
9001 22:17:53.412730 TX Vref Scan disable
9002 22:17:53.417829 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
9003 22:17:53.418248 == TX Byte 0 ==
9004 22:17:53.420824 u2DelayCellOfst[0]=18 cells (5 PI)
9005 22:17:53.424228 u2DelayCellOfst[1]=14 cells (4 PI)
9006 22:17:53.427989 u2DelayCellOfst[2]=0 cells (0 PI)
9007 22:17:53.431081 u2DelayCellOfst[3]=7 cells (2 PI)
9008 22:17:53.434660 u2DelayCellOfst[4]=7 cells (2 PI)
9009 22:17:53.437472 u2DelayCellOfst[5]=22 cells (6 PI)
9010 22:17:53.440681 u2DelayCellOfst[6]=18 cells (5 PI)
9011 22:17:53.444227 u2DelayCellOfst[7]=3 cells (1 PI)
9012 22:17:53.447200 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
9013 22:17:53.450509 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
9014 22:17:53.454167 == TX Byte 1 ==
9015 22:17:53.457048 u2DelayCellOfst[8]=0 cells (0 PI)
9016 22:17:53.460225 u2DelayCellOfst[9]=3 cells (1 PI)
9017 22:17:53.463562 u2DelayCellOfst[10]=7 cells (2 PI)
9018 22:17:53.467797 u2DelayCellOfst[11]=3 cells (1 PI)
9019 22:17:53.470765 u2DelayCellOfst[12]=14 cells (4 PI)
9020 22:17:53.473616 u2DelayCellOfst[13]=14 cells (4 PI)
9021 22:17:53.474035 u2DelayCellOfst[14]=14 cells (4 PI)
9022 22:17:53.476839 u2DelayCellOfst[15]=14 cells (4 PI)
9023 22:17:53.483678 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
9024 22:17:53.486850 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
9025 22:17:53.490118 DramC Write-DBI on
9026 22:17:53.490665 ==
9027 22:17:53.493878 Dram Type= 6, Freq= 0, CH_1, rank 1
9028 22:17:53.496507 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9029 22:17:53.497121 ==
9030 22:17:53.497655
9031 22:17:53.497981
9032 22:17:53.499659 TX Vref Scan disable
9033 22:17:53.500289 == TX Byte 0 ==
9034 22:17:53.506423 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
9035 22:17:53.506839 == TX Byte 1 ==
9036 22:17:53.512794 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
9037 22:17:53.513225 DramC Write-DBI off
9038 22:17:53.513558
9039 22:17:53.513859 [DATLAT]
9040 22:17:53.516594 Freq=1600, CH1 RK1
9041 22:17:53.517054
9042 22:17:53.519423 DATLAT Default: 0xf
9043 22:17:53.519944 0, 0xFFFF, sum = 0
9044 22:17:53.522662 1, 0xFFFF, sum = 0
9045 22:17:53.523187 2, 0xFFFF, sum = 0
9046 22:17:53.527370 3, 0xFFFF, sum = 0
9047 22:17:53.527894 4, 0xFFFF, sum = 0
9048 22:17:53.529140 5, 0xFFFF, sum = 0
9049 22:17:53.529712 6, 0xFFFF, sum = 0
9050 22:17:53.533532 7, 0xFFFF, sum = 0
9051 22:17:53.534052 8, 0xFFFF, sum = 0
9052 22:17:53.536054 9, 0xFFFF, sum = 0
9053 22:17:53.536664 10, 0xFFFF, sum = 0
9054 22:17:53.539291 11, 0xFFFF, sum = 0
9055 22:17:53.539948 12, 0xFFFF, sum = 0
9056 22:17:53.542712 13, 0xFFFF, sum = 0
9057 22:17:53.543174 14, 0x0, sum = 1
9058 22:17:53.546423 15, 0x0, sum = 2
9059 22:17:53.546923 16, 0x0, sum = 3
9060 22:17:53.549702 17, 0x0, sum = 4
9061 22:17:53.550221 best_step = 15
9062 22:17:53.550555
9063 22:17:53.550859 ==
9064 22:17:53.552433 Dram Type= 6, Freq= 0, CH_1, rank 1
9065 22:17:53.559281 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9066 22:17:53.559769 ==
9067 22:17:53.560099 RX Vref Scan: 0
9068 22:17:53.560405
9069 22:17:53.562566 RX Vref 0 -> 0, step: 1
9070 22:17:53.562996
9071 22:17:53.565855 RX Delay 11 -> 252, step: 4
9072 22:17:53.569094 iDelay=203, Bit 0, Center 140 (87 ~ 194) 108
9073 22:17:53.572193 iDelay=203, Bit 1, Center 128 (75 ~ 182) 108
9074 22:17:53.576434 iDelay=203, Bit 2, Center 122 (67 ~ 178) 112
9075 22:17:53.582345 iDelay=203, Bit 3, Center 130 (79 ~ 182) 104
9076 22:17:53.585476 iDelay=203, Bit 4, Center 132 (75 ~ 190) 116
9077 22:17:53.589091 iDelay=203, Bit 5, Center 146 (95 ~ 198) 104
9078 22:17:53.592265 iDelay=203, Bit 6, Center 146 (91 ~ 202) 112
9079 22:17:53.599118 iDelay=203, Bit 7, Center 130 (79 ~ 182) 104
9080 22:17:53.601852 iDelay=203, Bit 8, Center 112 (55 ~ 170) 116
9081 22:17:53.605220 iDelay=203, Bit 9, Center 116 (63 ~ 170) 108
9082 22:17:53.608820 iDelay=203, Bit 10, Center 128 (75 ~ 182) 108
9083 22:17:53.611924 iDelay=203, Bit 11, Center 116 (63 ~ 170) 108
9084 22:17:53.618818 iDelay=203, Bit 12, Center 136 (83 ~ 190) 108
9085 22:17:53.621940 iDelay=203, Bit 13, Center 136 (83 ~ 190) 108
9086 22:17:53.625234 iDelay=203, Bit 14, Center 134 (79 ~ 190) 112
9087 22:17:53.628729 iDelay=203, Bit 15, Center 138 (83 ~ 194) 112
9088 22:17:53.629193 ==
9089 22:17:53.632133 Dram Type= 6, Freq= 0, CH_1, rank 1
9090 22:17:53.638604 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9091 22:17:53.639157 ==
9092 22:17:53.639529 DQS Delay:
9093 22:17:53.641769 DQS0 = 0, DQS1 = 0
9094 22:17:53.642337 DQM Delay:
9095 22:17:53.645200 DQM0 = 134, DQM1 = 127
9096 22:17:53.645761 DQ Delay:
9097 22:17:53.648505 DQ0 =140, DQ1 =128, DQ2 =122, DQ3 =130
9098 22:17:53.651774 DQ4 =132, DQ5 =146, DQ6 =146, DQ7 =130
9099 22:17:53.655335 DQ8 =112, DQ9 =116, DQ10 =128, DQ11 =116
9100 22:17:53.658291 DQ12 =136, DQ13 =136, DQ14 =134, DQ15 =138
9101 22:17:53.658859
9102 22:17:53.659222
9103 22:17:53.659557
9104 22:17:53.661915 [DramC_TX_OE_Calibration] TA2
9105 22:17:53.665206 Original DQ_B0 (3 6) =30, OEN = 27
9106 22:17:53.668183 Original DQ_B1 (3 6) =30, OEN = 27
9107 22:17:53.671386 24, 0x0, End_B0=24 End_B1=24
9108 22:17:53.674939 25, 0x0, End_B0=25 End_B1=25
9109 22:17:53.675407 26, 0x0, End_B0=26 End_B1=26
9110 22:17:53.678276 27, 0x0, End_B0=27 End_B1=27
9111 22:17:53.681034 28, 0x0, End_B0=28 End_B1=28
9112 22:17:53.684925 29, 0x0, End_B0=29 End_B1=29
9113 22:17:53.685422 30, 0x0, End_B0=30 End_B1=30
9114 22:17:53.687937 31, 0x5151, End_B0=30 End_B1=30
9115 22:17:53.691523 Byte0 end_step=30 best_step=27
9116 22:17:53.694693 Byte1 end_step=30 best_step=27
9117 22:17:53.697613 Byte0 TX OE(2T, 0.5T) = (3, 3)
9118 22:17:53.700998 Byte1 TX OE(2T, 0.5T) = (3, 3)
9119 22:17:53.701534
9120 22:17:53.702056
9121 22:17:53.707535 [DQSOSCAuto] RK1, (LSB)MR18= 0xa06, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 404 ps
9122 22:17:53.711217 CH1 RK1: MR19=303, MR18=A06
9123 22:17:53.717983 CH1_RK1: MR19=0x303, MR18=0xA06, DQSOSC=404, MR23=63, INC=22, DEC=15
9124 22:17:53.720790 [RxdqsGatingPostProcess] freq 1600
9125 22:17:53.724332 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9126 22:17:53.727725 best DQS0 dly(2T, 0.5T) = (1, 1)
9127 22:17:53.731115 best DQS1 dly(2T, 0.5T) = (1, 1)
9128 22:17:53.734301 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9129 22:17:53.737710 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9130 22:17:53.740943 best DQS0 dly(2T, 0.5T) = (1, 1)
9131 22:17:53.743876 best DQS1 dly(2T, 0.5T) = (1, 1)
9132 22:17:53.747020 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9133 22:17:53.750968 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9134 22:17:53.754081 Pre-setting of DQS Precalculation
9135 22:17:53.757137 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9136 22:17:53.767045 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9137 22:17:53.774081 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9138 22:17:53.774649
9139 22:17:53.775010
9140 22:17:53.776635 [Calibration Summary] 3200 Mbps
9141 22:17:53.777097 CH 0, Rank 0
9142 22:17:53.779862 SW Impedance : PASS
9143 22:17:53.780337 DUTY Scan : NO K
9144 22:17:53.783417 ZQ Calibration : PASS
9145 22:17:53.786675 Jitter Meter : NO K
9146 22:17:53.787245 CBT Training : PASS
9147 22:17:53.789879 Write leveling : PASS
9148 22:17:53.792965 RX DQS gating : PASS
9149 22:17:53.793422 RX DQ/DQS(RDDQC) : PASS
9150 22:17:53.796825 TX DQ/DQS : PASS
9151 22:17:53.799820 RX DATLAT : PASS
9152 22:17:53.800279 RX DQ/DQS(Engine): PASS
9153 22:17:53.803869 TX OE : PASS
9154 22:17:53.804327 All Pass.
9155 22:17:53.804727
9156 22:17:53.806452 CH 0, Rank 1
9157 22:17:53.806936 SW Impedance : PASS
9158 22:17:53.809449 DUTY Scan : NO K
9159 22:17:53.813077 ZQ Calibration : PASS
9160 22:17:53.813561 Jitter Meter : NO K
9161 22:17:53.816809 CBT Training : PASS
9162 22:17:53.819706 Write leveling : PASS
9163 22:17:53.820128 RX DQS gating : PASS
9164 22:17:53.823062 RX DQ/DQS(RDDQC) : PASS
9165 22:17:53.826318 TX DQ/DQS : PASS
9166 22:17:53.826784 RX DATLAT : PASS
9167 22:17:53.829364 RX DQ/DQS(Engine): PASS
9168 22:17:53.829831 TX OE : PASS
9169 22:17:53.832854 All Pass.
9170 22:17:53.833273
9171 22:17:53.833601 CH 1, Rank 0
9172 22:17:53.835728 SW Impedance : PASS
9173 22:17:53.836193 DUTY Scan : NO K
9174 22:17:53.840414 ZQ Calibration : PASS
9175 22:17:53.843313 Jitter Meter : NO K
9176 22:17:53.843869 CBT Training : PASS
9177 22:17:53.846520 Write leveling : PASS
9178 22:17:53.849051 RX DQS gating : PASS
9179 22:17:53.849517 RX DQ/DQS(RDDQC) : PASS
9180 22:17:53.852886 TX DQ/DQS : PASS
9181 22:17:53.855879 RX DATLAT : PASS
9182 22:17:53.856344 RX DQ/DQS(Engine): PASS
9183 22:17:53.859183 TX OE : PASS
9184 22:17:53.859650 All Pass.
9185 22:17:53.860016
9186 22:17:53.862874 CH 1, Rank 1
9187 22:17:53.863444 SW Impedance : PASS
9188 22:17:53.865907 DUTY Scan : NO K
9189 22:17:53.869733 ZQ Calibration : PASS
9190 22:17:53.870281 Jitter Meter : NO K
9191 22:17:53.872355 CBT Training : PASS
9192 22:17:53.875770 Write leveling : PASS
9193 22:17:53.876286 RX DQS gating : PASS
9194 22:17:53.878749 RX DQ/DQS(RDDQC) : PASS
9195 22:17:53.881956 TX DQ/DQS : PASS
9196 22:17:53.882425 RX DATLAT : PASS
9197 22:17:53.885895 RX DQ/DQS(Engine): PASS
9198 22:17:53.888600 TX OE : PASS
9199 22:17:53.889121 All Pass.
9200 22:17:53.889480
9201 22:17:53.889837 DramC Write-DBI on
9202 22:17:53.892312 PER_BANK_REFRESH: Hybrid Mode
9203 22:17:53.895172 TX_TRACKING: ON
9204 22:17:53.901576 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9205 22:17:53.911781 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9206 22:17:53.918478 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9207 22:17:53.922314 [FAST_K] Save calibration result to emmc
9208 22:17:53.924981 sync common calibartion params.
9209 22:17:53.928584 sync cbt_mode0:1, 1:1
9210 22:17:53.929055 dram_init: ddr_geometry: 2
9211 22:17:53.931900 dram_init: ddr_geometry: 2
9212 22:17:53.935145 dram_init: ddr_geometry: 2
9213 22:17:53.938329 0:dram_rank_size:100000000
9214 22:17:53.938877 1:dram_rank_size:100000000
9215 22:17:53.944979 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9216 22:17:53.947963 DFS_SHUFFLE_HW_MODE: ON
9217 22:17:53.951479 dramc_set_vcore_voltage set vcore to 725000
9218 22:17:53.952052 Read voltage for 1600, 0
9219 22:17:53.955575 Vio18 = 0
9220 22:17:53.956137 Vcore = 725000
9221 22:17:53.956501 Vdram = 0
9222 22:17:53.957860 Vddq = 0
9223 22:17:53.958344 Vmddr = 0
9224 22:17:53.961656 switch to 3200 Mbps bootup
9225 22:17:53.962220 [DramcRunTimeConfig]
9226 22:17:53.964674 PHYPLL
9227 22:17:53.965126 DPM_CONTROL_AFTERK: ON
9228 22:17:53.968448 PER_BANK_REFRESH: ON
9229 22:17:53.971927 REFRESH_OVERHEAD_REDUCTION: ON
9230 22:17:53.972460 CMD_PICG_NEW_MODE: OFF
9231 22:17:53.974785 XRTWTW_NEW_MODE: ON
9232 22:17:53.975386 XRTRTR_NEW_MODE: ON
9233 22:17:53.978370 TX_TRACKING: ON
9234 22:17:53.978831 RDSEL_TRACKING: OFF
9235 22:17:53.981608 DQS Precalculation for DVFS: ON
9236 22:17:53.984872 RX_TRACKING: OFF
9237 22:17:53.985426 HW_GATING DBG: ON
9238 22:17:53.988491 ZQCS_ENABLE_LP4: ON
9239 22:17:53.989081 RX_PICG_NEW_MODE: ON
9240 22:17:53.991289 TX_PICG_NEW_MODE: ON
9241 22:17:53.991776 ENABLE_RX_DCM_DPHY: ON
9242 22:17:53.994791 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9243 22:17:53.998019 DUMMY_READ_FOR_TRACKING: OFF
9244 22:17:54.001012 !!! SPM_CONTROL_AFTERK: OFF
9245 22:17:54.004844 !!! SPM could not control APHY
9246 22:17:54.005304 IMPEDANCE_TRACKING: ON
9247 22:17:54.007699 TEMP_SENSOR: ON
9248 22:17:54.008166 HW_SAVE_FOR_SR: OFF
9249 22:17:54.010637 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9250 22:17:54.014863 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9251 22:17:54.017495 Read ODT Tracking: ON
9252 22:17:54.020432 Refresh Rate DeBounce: ON
9253 22:17:54.021052 DFS_NO_QUEUE_FLUSH: ON
9254 22:17:54.023944 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9255 22:17:54.027361 ENABLE_DFS_RUNTIME_MRW: OFF
9256 22:17:54.030770 DDR_RESERVE_NEW_MODE: ON
9257 22:17:54.031182 MR_CBT_SWITCH_FREQ: ON
9258 22:17:54.034350 =========================
9259 22:17:54.053138 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9260 22:17:54.056996 dram_init: ddr_geometry: 2
9261 22:17:54.075110 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9262 22:17:54.077938 dram_init: dram init end (result: 0)
9263 22:17:54.084338 DRAM-K: Full calibration passed in 24618 msecs
9264 22:17:54.087523 MRC: failed to locate region type 0.
9265 22:17:54.088067 DRAM rank0 size:0x100000000,
9266 22:17:54.091391 DRAM rank1 size=0x100000000
9267 22:17:54.100553 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9268 22:17:54.107446 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9269 22:17:54.114782 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9270 22:17:54.121129 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9271 22:17:54.124616 DRAM rank0 size:0x100000000,
9272 22:17:54.127466 DRAM rank1 size=0x100000000
9273 22:17:54.127929 CBMEM:
9274 22:17:54.130687 IMD: root @ 0xfffff000 254 entries.
9275 22:17:54.133652 IMD: root @ 0xffffec00 62 entries.
9276 22:17:54.137005 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9277 22:17:54.143804 WARNING: RO_VPD is uninitialized or empty.
9278 22:17:54.146876 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9279 22:17:54.154690 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9280 22:17:54.167467 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9281 22:17:54.178452 BS: romstage times (exec / console): total (unknown) / 24113 ms
9282 22:17:54.179002
9283 22:17:54.179362
9284 22:17:54.188644 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9285 22:17:54.191717 ARM64: Exception handlers installed.
9286 22:17:54.195690 ARM64: Testing exception
9287 22:17:54.198626 ARM64: Done test exception
9288 22:17:54.199188 Enumerating buses...
9289 22:17:54.202380 Show all devs... Before device enumeration.
9290 22:17:54.205434 Root Device: enabled 1
9291 22:17:54.208034 CPU_CLUSTER: 0: enabled 1
9292 22:17:54.208491 CPU: 00: enabled 1
9293 22:17:54.211607 Compare with tree...
9294 22:17:54.212067 Root Device: enabled 1
9295 22:17:54.214868 CPU_CLUSTER: 0: enabled 1
9296 22:17:54.217879 CPU: 00: enabled 1
9297 22:17:54.218432 Root Device scanning...
9298 22:17:54.221317 scan_static_bus for Root Device
9299 22:17:54.225281 CPU_CLUSTER: 0 enabled
9300 22:17:54.227760 scan_static_bus for Root Device done
9301 22:17:54.231534 scan_bus: bus Root Device finished in 8 msecs
9302 22:17:54.231994 done
9303 22:17:54.237838 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9304 22:17:54.241807 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9305 22:17:54.247773 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9306 22:17:54.254072 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9307 22:17:54.254540 Allocating resources...
9308 22:17:54.257937 Reading resources...
9309 22:17:54.260843 Root Device read_resources bus 0 link: 0
9310 22:17:54.264300 DRAM rank0 size:0x100000000,
9311 22:17:54.264792 DRAM rank1 size=0x100000000
9312 22:17:54.271063 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9313 22:17:54.271640 CPU: 00 missing read_resources
9314 22:17:54.277510 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9315 22:17:54.280217 Root Device read_resources bus 0 link: 0 done
9316 22:17:54.284152 Done reading resources.
9317 22:17:54.287111 Show resources in subtree (Root Device)...After reading.
9318 22:17:54.290549 Root Device child on link 0 CPU_CLUSTER: 0
9319 22:17:54.294192 CPU_CLUSTER: 0 child on link 0 CPU: 00
9320 22:17:54.303369 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9321 22:17:54.304085 CPU: 00
9322 22:17:54.310840 Root Device assign_resources, bus 0 link: 0
9323 22:17:54.313683 CPU_CLUSTER: 0 missing set_resources
9324 22:17:54.316636 Root Device assign_resources, bus 0 link: 0 done
9325 22:17:54.319740 Done setting resources.
9326 22:17:54.323436 Show resources in subtree (Root Device)...After assigning values.
9327 22:17:54.326781 Root Device child on link 0 CPU_CLUSTER: 0
9328 22:17:54.333378 CPU_CLUSTER: 0 child on link 0 CPU: 00
9329 22:17:54.339716 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9330 22:17:54.343768 CPU: 00
9331 22:17:54.344294 Done allocating resources.
9332 22:17:54.349621 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9333 22:17:54.350146 Enabling resources...
9334 22:17:54.353401 done.
9335 22:17:54.356675 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9336 22:17:54.360353 Initializing devices...
9337 22:17:54.360854 Root Device init
9338 22:17:54.363154 init hardware done!
9339 22:17:54.363589 0x00000018: ctrlr->caps
9340 22:17:54.366431 52.000 MHz: ctrlr->f_max
9341 22:17:54.370245 0.400 MHz: ctrlr->f_min
9342 22:17:54.370669 0x40ff8080: ctrlr->voltages
9343 22:17:54.373049 sclk: 390625
9344 22:17:54.373464 Bus Width = 1
9345 22:17:54.376443 sclk: 390625
9346 22:17:54.376898 Bus Width = 1
9347 22:17:54.379486 Early init status = 3
9348 22:17:54.382592 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9349 22:17:54.386251 in-header: 03 fc 00 00 01 00 00 00
9350 22:17:54.389798 in-data: 00
9351 22:17:54.392618 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9352 22:17:54.397158 in-header: 03 fd 00 00 00 00 00 00
9353 22:17:54.400639 in-data:
9354 22:17:54.403869 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9355 22:17:54.409872 in-header: 03 fc 00 00 01 00 00 00
9356 22:17:54.413661 in-data: 00
9357 22:17:54.416011 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9358 22:17:54.422008 in-header: 03 fd 00 00 00 00 00 00
9359 22:17:54.424766 in-data:
9360 22:17:54.428562 [SSUSB] Setting up USB HOST controller...
9361 22:17:54.431417 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9362 22:17:54.435028 [SSUSB] phy power-on done.
9363 22:17:54.438455 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9364 22:17:54.444616 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9365 22:17:54.448288 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9366 22:17:54.454584 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9367 22:17:54.460813 read SPI 0x50eb0 0x2ad3: 1173 us, 9346 KB/s, 74.768 Mbps
9368 22:17:54.467340 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9369 22:17:54.474145 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9370 22:17:54.480624 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9371 22:17:54.484553 SPM: binary array size = 0x9dc
9372 22:17:54.487332 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9373 22:17:54.493957 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9374 22:17:54.500677 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9375 22:17:54.507634 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9376 22:17:54.510698 configure_display: Starting display init
9377 22:17:54.545550 anx7625_power_on_init: Init interface.
9378 22:17:54.548415 anx7625_disable_pd_protocol: Disabled PD feature.
9379 22:17:54.551313 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9380 22:17:54.579442 anx7625_start_dp_work: Secure OCM version=00
9381 22:17:54.582498 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9382 22:17:54.597657 sp_tx_get_edid_block: EDID Block = 1
9383 22:17:54.700762 Extracted contents:
9384 22:17:54.703474 header: 00 ff ff ff ff ff ff 00
9385 22:17:54.706637 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9386 22:17:54.709450 version: 01 04
9387 22:17:54.713187 basic params: 95 1f 11 78 0a
9388 22:17:54.716782 chroma info: 76 90 94 55 54 90 27 21 50 54
9389 22:17:54.719510 established: 00 00 00
9390 22:17:54.726524 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9391 22:17:54.729413 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9392 22:17:54.736914 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9393 22:17:54.742693 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9394 22:17:54.749358 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9395 22:17:54.752882 extensions: 00
9396 22:17:54.753346 checksum: fb
9397 22:17:54.753704
9398 22:17:54.759701 Manufacturer: IVO Model 57d Serial Number 0
9399 22:17:54.760414 Made week 0 of 2020
9400 22:17:54.762807 EDID version: 1.4
9401 22:17:54.763362 Digital display
9402 22:17:54.766215 6 bits per primary color channel
9403 22:17:54.766688 DisplayPort interface
9404 22:17:54.769112 Maximum image size: 31 cm x 17 cm
9405 22:17:54.772406 Gamma: 220%
9406 22:17:54.772978 Check DPMS levels
9407 22:17:54.778714 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9408 22:17:54.782317 First detailed timing is preferred timing
9409 22:17:54.782782 Established timings supported:
9410 22:17:54.785609 Standard timings supported:
9411 22:17:54.788723 Detailed timings
9412 22:17:54.792097 Hex of detail: 383680a07038204018303c0035ae10000019
9413 22:17:54.798433 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9414 22:17:54.802103 0780 0798 07c8 0820 hborder 0
9415 22:17:54.805548 0438 043b 0447 0458 vborder 0
9416 22:17:54.808980 -hsync -vsync
9417 22:17:54.809401 Did detailed timing
9418 22:17:54.815158 Hex of detail: 000000000000000000000000000000000000
9419 22:17:54.818852 Manufacturer-specified data, tag 0
9420 22:17:54.821737 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9421 22:17:54.825166 ASCII string: InfoVision
9422 22:17:54.828625 Hex of detail: 000000fe00523134304e574635205248200a
9423 22:17:54.832013 ASCII string: R140NWF5 RH
9424 22:17:54.832616 Checksum
9425 22:17:54.835668 Checksum: 0xfb (valid)
9426 22:17:54.838590 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9427 22:17:54.841741 DSI data_rate: 832800000 bps
9428 22:17:54.848251 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9429 22:17:54.851195 anx7625_parse_edid: pixelclock(138800).
9430 22:17:54.854582 hactive(1920), hsync(48), hfp(24), hbp(88)
9431 22:17:54.858330 vactive(1080), vsync(12), vfp(3), vbp(17)
9432 22:17:54.861525 anx7625_dsi_config: config dsi.
9433 22:17:54.867744 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9434 22:17:54.881445 anx7625_dsi_config: success to config DSI
9435 22:17:54.884713 anx7625_dp_start: MIPI phy setup OK.
9436 22:17:54.888693 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9437 22:17:54.891307 mtk_ddp_mode_set invalid vrefresh 60
9438 22:17:54.894608 main_disp_path_setup
9439 22:17:54.895284 ovl_layer_smi_id_en
9440 22:17:54.898257 ovl_layer_smi_id_en
9441 22:17:54.898724 ccorr_config
9442 22:17:54.899086 aal_config
9443 22:17:54.901782 gamma_config
9444 22:17:54.902340 postmask_config
9445 22:17:54.905243 dither_config
9446 22:17:54.908206 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9447 22:17:54.914895 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9448 22:17:54.918257 Root Device init finished in 554 msecs
9449 22:17:54.921217 CPU_CLUSTER: 0 init
9450 22:17:54.928302 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9451 22:17:54.934392 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9452 22:17:54.934917 APU_MBOX 0x190000b0 = 0x10001
9453 22:17:54.938068 APU_MBOX 0x190001b0 = 0x10001
9454 22:17:54.941145 APU_MBOX 0x190005b0 = 0x10001
9455 22:17:54.944467 APU_MBOX 0x190006b0 = 0x10001
9456 22:17:54.951709 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9457 22:17:54.961118 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9458 22:17:54.973062 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9459 22:17:54.979682 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9460 22:17:54.991456 read SPI 0x61c74 0xe8ef: 6408 us, 9305 KB/s, 74.440 Mbps
9461 22:17:55.000873 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9462 22:17:55.004183 CPU_CLUSTER: 0 init finished in 81 msecs
9463 22:17:55.007078 Devices initialized
9464 22:17:55.010424 Show all devs... After init.
9465 22:17:55.010930 Root Device: enabled 1
9466 22:17:55.013999 CPU_CLUSTER: 0: enabled 1
9467 22:17:55.017655 CPU: 00: enabled 1
9468 22:17:55.020793 BS: BS_DEV_INIT run times (exec / console): 212 / 447 ms
9469 22:17:55.023547 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9470 22:17:55.026879 ELOG: NV offset 0x57f000 size 0x1000
9471 22:17:55.033924 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9472 22:17:55.040677 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9473 22:17:55.044129 ELOG: Event(17) added with size 13 at 2023-06-05 22:17:55 UTC
9474 22:17:55.050569 out: cmd=0x121: 03 db 21 01 00 00 00 00
9475 22:17:55.053690 in-header: 03 c2 00 00 2c 00 00 00
9476 22:17:55.064120 in-data: 9d 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9477 22:17:55.070157 ELOG: Event(A1) added with size 10 at 2023-06-05 22:17:55 UTC
9478 22:17:55.078029 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9479 22:17:55.083247 ELOG: Event(A0) added with size 9 at 2023-06-05 22:17:55 UTC
9480 22:17:55.086474 elog_add_boot_reason: Logged dev mode boot
9481 22:17:55.093663 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9482 22:17:55.094219 Finalize devices...
9483 22:17:55.096207 Devices finalized
9484 22:17:55.099859 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9485 22:17:55.102999 Writing coreboot table at 0xffe64000
9486 22:17:55.106100 0. 000000000010a000-0000000000113fff: RAMSTAGE
9487 22:17:55.113065 1. 0000000040000000-00000000400fffff: RAM
9488 22:17:55.116591 2. 0000000040100000-000000004032afff: RAMSTAGE
9489 22:17:55.119393 3. 000000004032b000-00000000545fffff: RAM
9490 22:17:55.122883 4. 0000000054600000-000000005465ffff: BL31
9491 22:17:55.126875 5. 0000000054660000-00000000ffe63fff: RAM
9492 22:17:55.132861 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9493 22:17:55.135877 7. 0000000100000000-000000023fffffff: RAM
9494 22:17:55.139644 Passing 5 GPIOs to payload:
9495 22:17:55.142214 NAME | PORT | POLARITY | VALUE
9496 22:17:55.148857 EC in RW | 0x000000aa | low | undefined
9497 22:17:55.152014 EC interrupt | 0x00000005 | low | undefined
9498 22:17:55.159578 TPM interrupt | 0x000000ab | high | undefined
9499 22:17:55.162422 SD card detect | 0x00000011 | high | undefined
9500 22:17:55.165431 speaker enable | 0x00000093 | high | undefined
9501 22:17:55.168719 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9502 22:17:55.174103 in-header: 03 f9 00 00 02 00 00 00
9503 22:17:55.177776 in-data: 02 00
9504 22:17:55.180549 ADC[4]: Raw value=903770 ID=7
9505 22:17:55.183774 ADC[3]: Raw value=213282 ID=1
9506 22:17:55.184250 RAM Code: 0x71
9507 22:17:55.186998 ADC[6]: Raw value=75406 ID=0
9508 22:17:55.191054 ADC[5]: Raw value=212912 ID=1
9509 22:17:55.191587 SKU Code: 0x1
9510 22:17:55.197016 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum a129
9511 22:17:55.197581 coreboot table: 964 bytes.
9512 22:17:55.200243 IMD ROOT 0. 0xfffff000 0x00001000
9513 22:17:55.203231 IMD SMALL 1. 0xffffe000 0x00001000
9514 22:17:55.206662 RO MCACHE 2. 0xffffc000 0x00001104
9515 22:17:55.209901 CONSOLE 3. 0xfff7c000 0x00080000
9516 22:17:55.213495 FMAP 4. 0xfff7b000 0x00000452
9517 22:17:55.216790 TIME STAMP 5. 0xfff7a000 0x00000910
9518 22:17:55.220057 VBOOT WORK 6. 0xfff66000 0x00014000
9519 22:17:55.223348 RAMOOPS 7. 0xffe66000 0x00100000
9520 22:17:55.226648 COREBOOT 8. 0xffe64000 0x00002000
9521 22:17:55.230046 IMD small region:
9522 22:17:55.233165 IMD ROOT 0. 0xffffec00 0x00000400
9523 22:17:55.237293 VPD 1. 0xffffeba0 0x0000004c
9524 22:17:55.240444 MMC STATUS 2. 0xffffeb80 0x00000004
9525 22:17:55.246935 BS: BS_WRITE_TABLES run times (exec / console): 2 / 137 ms
9526 22:17:55.247503 Probing TPM: done!
9527 22:17:55.253227 Connected to device vid:did:rid of 1ae0:0028:00
9528 22:17:55.260290 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
9529 22:17:55.263507 Initialized TPM device CR50 revision 0
9530 22:17:55.266786 Checking cr50 for pending updates
9531 22:17:55.272209 Reading cr50 TPM mode
9532 22:17:55.280805 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9533 22:17:55.287337 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9534 22:17:55.327561 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9535 22:17:55.330619 Checking segment from ROM address 0x40100000
9536 22:17:55.333835 Checking segment from ROM address 0x4010001c
9537 22:17:55.340830 Loading segment from ROM address 0x40100000
9538 22:17:55.341313 code (compression=0)
9539 22:17:55.351204 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9540 22:17:55.357415 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9541 22:17:55.357983 it's not compressed!
9542 22:17:55.363797 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9543 22:17:55.370983 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9544 22:17:55.387767 Loading segment from ROM address 0x4010001c
9545 22:17:55.388343 Entry Point 0x80000000
9546 22:17:55.391116 Loaded segments
9547 22:17:55.394238 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9548 22:17:55.401241 Jumping to boot code at 0x80000000(0xffe64000)
9549 22:17:55.407856 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9550 22:17:55.414432 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9551 22:17:55.422042 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9552 22:17:55.425521 Checking segment from ROM address 0x40100000
9553 22:17:55.428578 Checking segment from ROM address 0x4010001c
9554 22:17:55.435358 Loading segment from ROM address 0x40100000
9555 22:17:55.435877 code (compression=1)
9556 22:17:55.441866 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9557 22:17:55.452138 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9558 22:17:55.452662 using LZMA
9559 22:17:55.460906 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9560 22:17:55.467281 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9561 22:17:55.470282 Loading segment from ROM address 0x4010001c
9562 22:17:55.470743 Entry Point 0x54601000
9563 22:17:55.474578 Loaded segments
9564 22:17:55.476924 NOTICE: MT8192 bl31_setup
9565 22:17:55.484683 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9566 22:17:55.487500 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9567 22:17:55.490886 WARNING: region 0:
9568 22:17:55.494483 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9569 22:17:55.495053 WARNING: region 1:
9570 22:17:55.501150 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9571 22:17:55.504899 WARNING: region 2:
9572 22:17:55.507235 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9573 22:17:55.510769 WARNING: region 3:
9574 22:17:55.513802 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9575 22:17:55.517916 WARNING: region 4:
9576 22:17:55.523882 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9577 22:17:55.524343 WARNING: region 5:
9578 22:17:55.527556 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9579 22:17:55.530674 WARNING: region 6:
9580 22:17:55.534043 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9581 22:17:55.537005 WARNING: region 7:
9582 22:17:55.540452 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9583 22:17:55.547047 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9584 22:17:55.550589 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9585 22:17:55.553765 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9586 22:17:55.560170 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9587 22:17:55.563747 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9588 22:17:55.570714 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9589 22:17:55.573935 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9590 22:17:55.576744 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9591 22:17:55.583361 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9592 22:17:55.587423 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9593 22:17:55.590613 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9594 22:17:55.597119 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9595 22:17:55.600571 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9596 22:17:55.607309 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9597 22:17:55.610520 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9598 22:17:55.613543 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9599 22:17:55.620381 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9600 22:17:55.622962 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9601 22:17:55.626672 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9602 22:17:55.633692 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9603 22:17:55.636355 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9604 22:17:55.643964 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9605 22:17:55.646974 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9606 22:17:55.650156 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9607 22:17:55.656655 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9608 22:17:55.659492 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9609 22:17:55.666140 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9610 22:17:55.670178 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9611 22:17:55.673090 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9612 22:17:55.680254 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9613 22:17:55.682997 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9614 22:17:55.689433 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9615 22:17:55.693037 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9616 22:17:55.696680 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9617 22:17:55.699575 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9618 22:17:55.706481 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9619 22:17:55.709455 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9620 22:17:55.712957 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9621 22:17:55.716098 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9622 22:17:55.723224 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9623 22:17:55.726595 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9624 22:17:55.729519 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9625 22:17:55.732546 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9626 22:17:55.739554 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9627 22:17:55.742877 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9628 22:17:55.746742 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9629 22:17:55.749326 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9630 22:17:55.756361 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9631 22:17:55.759132 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9632 22:17:55.765692 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9633 22:17:55.769481 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9634 22:17:55.772262 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9635 22:17:55.779047 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9636 22:17:55.782482 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9637 22:17:55.788793 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9638 22:17:55.792230 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9639 22:17:55.799299 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9640 22:17:55.802291 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9641 22:17:55.809400 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9642 22:17:55.812277 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9643 22:17:55.815410 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9644 22:17:55.823081 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9645 22:17:55.825304 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9646 22:17:55.832296 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9647 22:17:55.835546 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9648 22:17:55.842071 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9649 22:17:55.845153 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9650 22:17:55.852278 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9651 22:17:55.855149 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9652 22:17:55.858578 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9653 22:17:55.865137 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9654 22:17:55.868620 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9655 22:17:55.875068 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9656 22:17:55.878393 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9657 22:17:55.885546 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9658 22:17:55.888385 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9659 22:17:55.891831 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9660 22:17:55.898496 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9661 22:17:55.901840 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9662 22:17:55.908369 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9663 22:17:55.911790 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9664 22:17:55.918264 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9665 22:17:55.921735 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9666 22:17:55.928565 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9667 22:17:55.932656 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9668 22:17:55.934839 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9669 22:17:55.941925 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9670 22:17:55.945046 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9671 22:17:55.952129 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9672 22:17:55.954691 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9673 22:17:55.961809 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9674 22:17:55.965201 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9675 22:17:55.968246 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9676 22:17:55.975510 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9677 22:17:55.978043 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9678 22:17:55.985591 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9679 22:17:55.988101 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9680 22:17:55.991622 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9681 22:17:55.998307 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9682 22:17:56.001292 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9683 22:17:56.004882 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9684 22:17:56.008145 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9685 22:17:56.014608 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9686 22:17:56.017732 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9687 22:17:56.024745 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9688 22:17:56.028210 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9689 22:17:56.031852 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9690 22:17:56.038076 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9691 22:17:56.041539 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9692 22:17:56.048153 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9693 22:17:56.052075 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9694 22:17:56.054236 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9695 22:17:56.060955 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9696 22:17:56.064620 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9697 22:17:56.071127 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9698 22:17:56.074318 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9699 22:17:56.077383 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9700 22:17:56.084269 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9701 22:17:56.088222 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9702 22:17:56.090975 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9703 22:17:56.094168 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9704 22:17:56.100786 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9705 22:17:56.104196 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9706 22:17:56.107434 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9707 22:17:56.114362 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9708 22:17:56.117126 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9709 22:17:56.120687 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9710 22:17:56.127822 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9711 22:17:56.131160 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9712 22:17:56.137163 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9713 22:17:56.140692 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9714 22:17:56.144393 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9715 22:17:56.150672 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9716 22:17:56.154188 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9717 22:17:56.160463 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9718 22:17:56.163838 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9719 22:17:56.167616 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9720 22:17:56.173928 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9721 22:17:56.176731 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9722 22:17:56.183407 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9723 22:17:56.186675 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9724 22:17:56.190325 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9725 22:17:56.196931 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9726 22:17:56.200285 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9727 22:17:56.207081 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9728 22:17:56.210136 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9729 22:17:56.212982 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9730 22:17:56.220093 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9731 22:17:56.224180 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9732 22:17:56.230227 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9733 22:17:56.233462 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9734 22:17:56.236415 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9735 22:17:56.243459 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9736 22:17:56.246741 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9737 22:17:56.253050 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9738 22:17:56.256823 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9739 22:17:56.259929 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9740 22:17:56.266184 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9741 22:17:56.269337 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9742 22:17:56.272745 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9743 22:17:56.279490 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9744 22:17:56.282774 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9745 22:17:56.289287 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9746 22:17:56.292653 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9747 22:17:56.299267 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9748 22:17:56.302588 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9749 22:17:56.305796 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9750 22:17:56.312449 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9751 22:17:56.315539 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9752 22:17:56.323081 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9753 22:17:56.325437 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9754 22:17:56.328911 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9755 22:17:56.335285 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9756 22:17:56.339263 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9757 22:17:56.341998 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9758 22:17:56.348824 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9759 22:17:56.352578 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9760 22:17:56.358498 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9761 22:17:56.362086 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9762 22:17:56.365023 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9763 22:17:56.371979 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9764 22:17:56.375556 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9765 22:17:56.383788 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9766 22:17:56.385031 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9767 22:17:56.391490 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9768 22:17:56.394878 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9769 22:17:56.398640 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9770 22:17:56.404921 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9771 22:17:56.408224 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9772 22:17:56.414666 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9773 22:17:56.418580 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9774 22:17:56.421621 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9775 22:17:56.428185 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9776 22:17:56.431452 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9777 22:17:56.437808 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9778 22:17:56.441847 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9779 22:17:56.444756 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9780 22:17:56.451468 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9781 22:17:56.454800 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9782 22:17:56.461082 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9783 22:17:56.464545 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9784 22:17:56.470925 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9785 22:17:56.474217 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9786 22:17:56.477367 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9787 22:17:56.483878 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9788 22:17:56.487218 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9789 22:17:56.493864 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9790 22:17:56.497674 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9791 22:17:56.503731 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9792 22:17:56.506845 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9793 22:17:56.510796 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9794 22:17:56.516985 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9795 22:17:56.520453 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9796 22:17:56.527521 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9797 22:17:56.530814 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9798 22:17:56.537195 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9799 22:17:56.540395 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9800 22:17:56.543390 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9801 22:17:56.550363 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9802 22:17:56.553390 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9803 22:17:56.559898 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9804 22:17:56.563649 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9805 22:17:56.566777 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9806 22:17:56.573390 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9807 22:17:56.576646 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9808 22:17:56.583145 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9809 22:17:56.586682 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9810 22:17:56.592935 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9811 22:17:56.596763 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9812 22:17:56.599462 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9813 22:17:56.603741 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9814 22:17:56.610099 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9815 22:17:56.613096 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9816 22:17:56.616136 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9817 22:17:56.622827 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9818 22:17:56.626270 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9819 22:17:56.629642 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9820 22:17:56.636243 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9821 22:17:56.639964 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9822 22:17:56.642570 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9823 22:17:56.649374 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9824 22:17:56.652712 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9825 22:17:56.659197 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9826 22:17:56.663043 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9827 22:17:56.665707 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9828 22:17:56.672694 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9829 22:17:56.675893 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9830 22:17:56.682821 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9831 22:17:56.685868 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9832 22:17:56.689102 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9833 22:17:56.695430 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9834 22:17:56.698897 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9835 22:17:56.702338 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9836 22:17:56.708712 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9837 22:17:56.711978 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9838 22:17:56.715220 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9839 22:17:56.721828 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9840 22:17:56.725134 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9841 22:17:56.729065 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9842 22:17:56.735169 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9843 22:17:56.738224 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9844 22:17:56.744890 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9845 22:17:56.748101 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9846 22:17:56.752010 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9847 22:17:56.758244 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9848 22:17:56.761705 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9849 22:17:56.767969 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9850 22:17:56.771197 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9851 22:17:56.774653 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9852 22:17:56.778214 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9853 22:17:56.784587 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9854 22:17:56.788196 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9855 22:17:56.791225 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9856 22:17:56.794838 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9857 22:17:56.801365 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9858 22:17:56.804832 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9859 22:17:56.807782 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9860 22:17:56.811092 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9861 22:17:56.817600 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9862 22:17:56.820716 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9863 22:17:56.824408 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9864 22:17:56.827737 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9865 22:17:56.833966 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9866 22:17:56.837375 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9867 22:17:56.843926 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9868 22:17:56.847405 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9869 22:17:56.853673 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9870 22:17:56.857044 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9871 22:17:56.863862 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9872 22:17:56.866986 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9873 22:17:56.870183 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9874 22:17:56.877061 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9875 22:17:56.880245 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9876 22:17:56.886574 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9877 22:17:56.890443 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9878 22:17:56.893812 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9879 22:17:56.900448 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9880 22:17:56.903570 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9881 22:17:56.909858 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9882 22:17:56.913472 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9883 22:17:56.920437 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9884 22:17:56.922983 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9885 22:17:56.927058 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9886 22:17:56.933635 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9887 22:17:56.936591 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9888 22:17:56.942561 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9889 22:17:56.945988 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9890 22:17:56.949444 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9891 22:17:56.956265 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9892 22:17:56.959312 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9893 22:17:56.966123 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9894 22:17:56.969364 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9895 22:17:56.976284 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9896 22:17:56.979053 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9897 22:17:56.982066 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9898 22:17:56.989298 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9899 22:17:56.992322 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9900 22:17:56.999043 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9901 22:17:57.002055 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9902 22:17:57.008602 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9903 22:17:57.012211 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9904 22:17:57.015768 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9905 22:17:57.022370 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9906 22:17:57.025420 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9907 22:17:57.031691 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9908 22:17:57.035248 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9909 22:17:57.038992 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9910 22:17:57.044777 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9911 22:17:57.048383 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9912 22:17:57.055141 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9913 22:17:57.058201 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9914 22:17:57.061719 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9915 22:17:57.068470 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9916 22:17:57.071593 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9917 22:17:57.078352 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9918 22:17:57.081603 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9919 22:17:57.087927 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9920 22:17:57.091547 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9921 22:17:57.095081 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9922 22:17:57.101441 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9923 22:17:57.104431 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9924 22:17:57.111580 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9925 22:17:57.114597 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9926 22:17:57.120896 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9927 22:17:57.124719 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9928 22:17:57.127898 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9929 22:17:57.134298 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9930 22:17:57.137649 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9931 22:17:57.144271 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9932 22:17:57.147518 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9933 22:17:57.151107 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9934 22:17:57.158203 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9935 22:17:57.161333 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9936 22:17:57.167779 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9937 22:17:57.171196 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9938 22:17:57.173744 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9939 22:17:57.180551 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9940 22:17:57.183620 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9941 22:17:57.190304 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9942 22:17:57.193543 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9943 22:17:57.200810 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9944 22:17:57.203991 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9945 22:17:57.210535 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9946 22:17:57.213677 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9947 22:17:57.219670 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9948 22:17:57.223311 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9949 22:17:57.226393 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9950 22:17:57.233564 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9951 22:17:57.236652 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9952 22:17:57.242843 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9953 22:17:57.246349 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9954 22:17:57.253679 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9955 22:17:57.256266 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9956 22:17:57.262770 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9957 22:17:57.265831 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9958 22:17:57.269251 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9959 22:17:57.276049 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9960 22:17:57.279269 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9961 22:17:57.285690 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9962 22:17:57.289510 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9963 22:17:57.295903 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9964 22:17:57.299854 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9965 22:17:57.302788 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9966 22:17:57.308999 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9967 22:17:57.312995 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9968 22:17:57.318800 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9969 22:17:57.322504 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9970 22:17:57.328583 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9971 22:17:57.332334 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9972 22:17:57.338758 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9973 22:17:57.342356 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9974 22:17:57.348836 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9975 22:17:57.351775 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9976 22:17:57.355466 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9977 22:17:57.362106 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9978 22:17:57.365447 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9979 22:17:57.371539 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9980 22:17:57.375200 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9981 22:17:57.381506 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9982 22:17:57.384697 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9983 22:17:57.391838 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9984 22:17:57.394588 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9985 22:17:57.398175 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9986 22:17:57.404615 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9987 22:17:57.407627 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9988 22:17:57.415325 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9989 22:17:57.418295 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9990 22:17:57.424331 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9991 22:17:57.428027 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9992 22:17:57.434506 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9993 22:17:57.437732 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9994 22:17:57.441165 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9995 22:17:57.447993 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9996 22:17:57.451172 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9997 22:17:57.457857 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9998 22:17:57.460797 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9999 22:17:57.467429 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
10000 22:17:57.470797 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
10001 22:17:57.477223 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
10002 22:17:57.480623 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
10003 22:17:57.487176 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
10004 22:17:57.490137 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
10005 22:17:57.497267 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
10006 22:17:57.500428 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
10007 22:17:57.507189 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
10008 22:17:57.510079 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
10009 22:17:57.516819 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
10010 22:17:57.523603 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
10011 22:17:57.526365 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
10012 22:17:57.532773 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
10013 22:17:57.537398 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
10014 22:17:57.543093 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
10015 22:17:57.545879 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
10016 22:17:57.552799 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
10017 22:17:57.556616 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
10018 22:17:57.559750 INFO: [APUAPC] vio 0
10019 22:17:57.562449 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
10020 22:17:57.565720 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
10021 22:17:57.569487 INFO: [APUAPC] D0_APC_0: 0x400510
10022 22:17:57.572751 INFO: [APUAPC] D0_APC_1: 0x0
10023 22:17:57.576576 INFO: [APUAPC] D0_APC_2: 0x1540
10024 22:17:57.579320 INFO: [APUAPC] D0_APC_3: 0x0
10025 22:17:57.583171 INFO: [APUAPC] D1_APC_0: 0xffffffff
10026 22:17:57.585875 INFO: [APUAPC] D1_APC_1: 0xffffffff
10027 22:17:57.589175 INFO: [APUAPC] D1_APC_2: 0x3fffff
10028 22:17:57.592656 INFO: [APUAPC] D1_APC_3: 0x0
10029 22:17:57.595489 INFO: [APUAPC] D2_APC_0: 0xffffffff
10030 22:17:57.599110 INFO: [APUAPC] D2_APC_1: 0xffffffff
10031 22:17:57.602393 INFO: [APUAPC] D2_APC_2: 0x3fffff
10032 22:17:57.605406 INFO: [APUAPC] D2_APC_3: 0x0
10033 22:17:57.608804 INFO: [APUAPC] D3_APC_0: 0xffffffff
10034 22:17:57.612378 INFO: [APUAPC] D3_APC_1: 0xffffffff
10035 22:17:57.615108 INFO: [APUAPC] D3_APC_2: 0x3fffff
10036 22:17:57.618856 INFO: [APUAPC] D3_APC_3: 0x0
10037 22:17:57.621572 INFO: [APUAPC] D4_APC_0: 0xffffffff
10038 22:17:57.625706 INFO: [APUAPC] D4_APC_1: 0xffffffff
10039 22:17:57.628466 INFO: [APUAPC] D4_APC_2: 0x3fffff
10040 22:17:57.631826 INFO: [APUAPC] D4_APC_3: 0x0
10041 22:17:57.635490 INFO: [APUAPC] D5_APC_0: 0xffffffff
10042 22:17:57.638570 INFO: [APUAPC] D5_APC_1: 0xffffffff
10043 22:17:57.641923 INFO: [APUAPC] D5_APC_2: 0x3fffff
10044 22:17:57.644623 INFO: [APUAPC] D5_APC_3: 0x0
10045 22:17:57.648186 INFO: [APUAPC] D6_APC_0: 0xffffffff
10046 22:17:57.651694 INFO: [APUAPC] D6_APC_1: 0xffffffff
10047 22:17:57.654852 INFO: [APUAPC] D6_APC_2: 0x3fffff
10048 22:17:57.658733 INFO: [APUAPC] D6_APC_3: 0x0
10049 22:17:57.662108 INFO: [APUAPC] D7_APC_0: 0xffffffff
10050 22:17:57.664816 INFO: [APUAPC] D7_APC_1: 0xffffffff
10051 22:17:57.668083 INFO: [APUAPC] D7_APC_2: 0x3fffff
10052 22:17:57.671909 INFO: [APUAPC] D7_APC_3: 0x0
10053 22:17:57.674925 INFO: [APUAPC] D8_APC_0: 0xffffffff
10054 22:17:57.678250 INFO: [APUAPC] D8_APC_1: 0xffffffff
10055 22:17:57.682005 INFO: [APUAPC] D8_APC_2: 0x3fffff
10056 22:17:57.685105 INFO: [APUAPC] D8_APC_3: 0x0
10057 22:17:57.688019 INFO: [APUAPC] D9_APC_0: 0xffffffff
10058 22:17:57.692649 INFO: [APUAPC] D9_APC_1: 0xffffffff
10059 22:17:57.694533 INFO: [APUAPC] D9_APC_2: 0x3fffff
10060 22:17:57.697865 INFO: [APUAPC] D9_APC_3: 0x0
10061 22:17:57.701301 INFO: [APUAPC] D10_APC_0: 0xffffffff
10062 22:17:57.704341 INFO: [APUAPC] D10_APC_1: 0xffffffff
10063 22:17:57.707866 INFO: [APUAPC] D10_APC_2: 0x3fffff
10064 22:17:57.710926 INFO: [APUAPC] D10_APC_3: 0x0
10065 22:17:57.714932 INFO: [APUAPC] D11_APC_0: 0xffffffff
10066 22:17:57.717818 INFO: [APUAPC] D11_APC_1: 0xffffffff
10067 22:17:57.720977 INFO: [APUAPC] D11_APC_2: 0x3fffff
10068 22:17:57.724267 INFO: [APUAPC] D11_APC_3: 0x0
10069 22:17:57.727526 INFO: [APUAPC] D12_APC_0: 0xffffffff
10070 22:17:57.730411 INFO: [APUAPC] D12_APC_1: 0xffffffff
10071 22:17:57.734584 INFO: [APUAPC] D12_APC_2: 0x3fffff
10072 22:17:57.737162 INFO: [APUAPC] D12_APC_3: 0x0
10073 22:17:57.740988 INFO: [APUAPC] D13_APC_0: 0xffffffff
10074 22:17:57.744549 INFO: [APUAPC] D13_APC_1: 0xffffffff
10075 22:17:57.747740 INFO: [APUAPC] D13_APC_2: 0x3fffff
10076 22:17:57.750377 INFO: [APUAPC] D13_APC_3: 0x0
10077 22:17:57.753889 INFO: [APUAPC] D14_APC_0: 0xffffffff
10078 22:17:57.757316 INFO: [APUAPC] D14_APC_1: 0xffffffff
10079 22:17:57.760563 INFO: [APUAPC] D14_APC_2: 0x3fffff
10080 22:17:57.764635 INFO: [APUAPC] D14_APC_3: 0x0
10081 22:17:57.767415 INFO: [APUAPC] D15_APC_0: 0xffffffff
10082 22:17:57.770709 INFO: [APUAPC] D15_APC_1: 0xffffffff
10083 22:17:57.773895 INFO: [APUAPC] D15_APC_2: 0x3fffff
10084 22:17:57.777178 INFO: [APUAPC] D15_APC_3: 0x0
10085 22:17:57.780145 INFO: [APUAPC] APC_CON: 0x4
10086 22:17:57.783335 INFO: [NOCDAPC] D0_APC_0: 0x0
10087 22:17:57.787446 INFO: [NOCDAPC] D0_APC_1: 0x0
10088 22:17:57.787863 INFO: [NOCDAPC] D1_APC_0: 0x0
10089 22:17:57.790485 INFO: [NOCDAPC] D1_APC_1: 0xfff
10090 22:17:57.793634 INFO: [NOCDAPC] D2_APC_0: 0x0
10091 22:17:57.797546 INFO: [NOCDAPC] D2_APC_1: 0xfff
10092 22:17:57.800318 INFO: [NOCDAPC] D3_APC_0: 0x0
10093 22:17:57.803474 INFO: [NOCDAPC] D3_APC_1: 0xfff
10094 22:17:57.807198 INFO: [NOCDAPC] D4_APC_0: 0x0
10095 22:17:57.810232 INFO: [NOCDAPC] D4_APC_1: 0xfff
10096 22:17:57.813562 INFO: [NOCDAPC] D5_APC_0: 0x0
10097 22:17:57.816360 INFO: [NOCDAPC] D5_APC_1: 0xfff
10098 22:17:57.819909 INFO: [NOCDAPC] D6_APC_0: 0x0
10099 22:17:57.823159 INFO: [NOCDAPC] D6_APC_1: 0xfff
10100 22:17:57.823579 INFO: [NOCDAPC] D7_APC_0: 0x0
10101 22:17:57.826548 INFO: [NOCDAPC] D7_APC_1: 0xfff
10102 22:17:57.829787 INFO: [NOCDAPC] D8_APC_0: 0x0
10103 22:17:57.833088 INFO: [NOCDAPC] D8_APC_1: 0xfff
10104 22:17:57.836615 INFO: [NOCDAPC] D9_APC_0: 0x0
10105 22:17:57.839584 INFO: [NOCDAPC] D9_APC_1: 0xfff
10106 22:17:57.842987 INFO: [NOCDAPC] D10_APC_0: 0x0
10107 22:17:57.846398 INFO: [NOCDAPC] D10_APC_1: 0xfff
10108 22:17:57.849551 INFO: [NOCDAPC] D11_APC_0: 0x0
10109 22:17:57.852954 INFO: [NOCDAPC] D11_APC_1: 0xfff
10110 22:17:57.856476 INFO: [NOCDAPC] D12_APC_0: 0x0
10111 22:17:57.859732 INFO: [NOCDAPC] D12_APC_1: 0xfff
10112 22:17:57.862942 INFO: [NOCDAPC] D13_APC_0: 0x0
10113 22:17:57.866165 INFO: [NOCDAPC] D13_APC_1: 0xfff
10114 22:17:57.866623 INFO: [NOCDAPC] D14_APC_0: 0x0
10115 22:17:57.869802 INFO: [NOCDAPC] D14_APC_1: 0xfff
10116 22:17:57.873132 INFO: [NOCDAPC] D15_APC_0: 0x0
10117 22:17:57.876887 INFO: [NOCDAPC] D15_APC_1: 0xfff
10118 22:17:57.879476 INFO: [NOCDAPC] APC_CON: 0x4
10119 22:17:57.883157 INFO: [APUAPC] set_apusys_apc done
10120 22:17:57.886195 INFO: [DEVAPC] devapc_init done
10121 22:17:57.890402 INFO: GICv3 without legacy support detected.
10122 22:17:57.896394 INFO: ARM GICv3 driver initialized in EL3
10123 22:17:57.899818 INFO: Maximum SPI INTID supported: 639
10124 22:17:57.903227 INFO: BL31: Initializing runtime services
10125 22:17:57.909583 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10126 22:17:57.910067 INFO: SPM: enable CPC mode
10127 22:17:57.916312 INFO: mcdi ready for mcusys-off-idle and system suspend
10128 22:17:57.919096 INFO: BL31: Preparing for EL3 exit to normal world
10129 22:17:57.925726 INFO: Entry point address = 0x80000000
10130 22:17:57.926192 INFO: SPSR = 0x8
10131 22:17:57.932045
10132 22:17:57.932506
10133 22:17:57.932900
10134 22:17:57.935664 Starting depthcharge on Spherion...
10135 22:17:57.936128
10136 22:17:57.936490 Wipe memory regions:
10137 22:17:57.936902
10138 22:17:57.939306 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10139 22:17:57.939859 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10140 22:17:57.940319 Setting prompt string to ['asurada:']
10141 22:17:57.940798 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10142 22:17:57.941528 [0x00000040000000, 0x00000054600000)
10143 22:17:58.060956
10144 22:17:58.061529 [0x00000054660000, 0x00000080000000)
10145 22:17:58.321463
10146 22:17:58.322186 [0x000000821a7280, 0x000000ffe64000)
10147 22:17:59.066832
10148 22:17:59.067393 [0x00000100000000, 0x00000240000000)
10149 22:18:00.956698
10150 22:18:00.960126 Initializing XHCI USB controller at 0x11200000.
10151 22:18:01.941851
10152 22:18:01.942350 R8152: Initializing
10153 22:18:01.942690
10154 22:18:01.944671 Version 9 (ocp_data = 6010)
10155 22:18:01.945097
10156 22:18:01.948326 R8152: Done initializing
10157 22:18:01.948812
10158 22:18:01.949172 Adding net device
10159 22:18:02.469333
10160 22:18:02.472963 [firmware-asurada-13885.B-collabora] Dec 14 2021 15:21:43
10161 22:18:02.473399
10162 22:18:02.473736
10163 22:18:02.474050
10164 22:18:02.474797 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10166 22:18:02.575913 asurada: tftpboot 192.168.201.1 10597264/tftp-deploy-9iuqvnbb/kernel/image.itb 10597264/tftp-deploy-9iuqvnbb/kernel/cmdline
10167 22:18:02.576450 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10168 22:18:02.576913 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:20)
10169 22:18:02.581319 tftpboot 192.168.201.1 10597264/tftp-deploy-9iuqvnbb/kernel/image.itp-deploy-9iuqvnbb/kernel/cmdline
10170 22:18:02.581749
10171 22:18:02.582084 Waiting for link
10172 22:18:02.783799
10173 22:18:02.784270 done.
10174 22:18:02.784686
10175 22:18:02.785010 MAC: f4:f5:e8:50:de:0a
10176 22:18:02.785313
10177 22:18:02.786536 Sending DHCP discover... done.
10178 22:18:02.787002
10179 22:18:02.791613 Waiting for reply... done.
10180 22:18:02.792074
10181 22:18:02.793418 Sending DHCP request... done.
10182 22:18:02.793867
10183 22:18:02.796986 Waiting for reply... done.
10184 22:18:02.797447
10185 22:18:02.797772 My ip is 192.168.201.14
10186 22:18:02.798201
10187 22:18:02.799984 The DHCP server ip is 192.168.201.1
10188 22:18:02.800402
10189 22:18:02.806787 TFTP server IP predefined by user: 192.168.201.1
10190 22:18:02.807322
10191 22:18:02.813429 Bootfile predefined by user: 10597264/tftp-deploy-9iuqvnbb/kernel/image.itb
10192 22:18:02.813890
10193 22:18:02.816357 Sending tftp read request... done.
10194 22:18:02.816832
10195 22:18:02.822415 Waiting for the transfer...
10196 22:18:02.822903
10197 22:18:03.089720 00000000 ################################################################
10198 22:18:03.089862
10199 22:18:03.319272 00080000 ################################################################
10200 22:18:03.319414
10201 22:18:03.558914 00100000 ################################################################
10202 22:18:03.559049
10203 22:18:03.795290 00180000 ################################################################
10204 22:18:03.795434
10205 22:18:04.022907 00200000 ################################################################
10206 22:18:04.023057
10207 22:18:04.262482 00280000 ################################################################
10208 22:18:04.262621
10209 22:18:04.490227 00300000 ################################################################
10210 22:18:04.490369
10211 22:18:04.713638 00380000 ################################################################
10212 22:18:04.713786
10213 22:18:04.940035 00400000 ################################################################
10214 22:18:04.940184
10215 22:18:05.179016 00480000 ################################################################
10216 22:18:05.179145
10217 22:18:05.405835 00500000 ################################################################
10218 22:18:05.405999
10219 22:18:05.633575 00580000 ################################################################
10220 22:18:05.633708
10221 22:18:05.859687 00600000 ################################################################
10222 22:18:05.859840
10223 22:18:06.085018 00680000 ################################################################
10224 22:18:06.085201
10225 22:18:06.310986 00700000 ################################################################
10226 22:18:06.311135
10227 22:18:06.537931 00780000 ################################################################
10228 22:18:06.538109
10229 22:18:06.775501 00800000 ################################################################
10230 22:18:06.775642
10231 22:18:07.015644 00880000 ################################################################
10232 22:18:07.015791
10233 22:18:07.242682 00900000 ################################################################
10234 22:18:07.242874
10235 22:18:07.468122 00980000 ################################################################
10236 22:18:07.468296
10237 22:18:07.689142 00a00000 ################################################################
10238 22:18:07.689290
10239 22:18:07.914849 00a80000 ################################################################
10240 22:18:07.915004
10241 22:18:08.141174 00b00000 ################################################################
10242 22:18:08.141361
10243 22:18:08.368007 00b80000 ################################################################
10244 22:18:08.368184
10245 22:18:08.601062 00c00000 ################################################################
10246 22:18:08.601212
10247 22:18:08.829240 00c80000 ################################################################
10248 22:18:08.829422
10249 22:18:09.055851 00d00000 ################################################################
10250 22:18:09.056007
10251 22:18:09.281852 00d80000 ################################################################
10252 22:18:09.282000
10253 22:18:09.507494 00e00000 ################################################################
10254 22:18:09.507656
10255 22:18:09.744238 00e80000 ################################################################
10256 22:18:09.744375
10257 22:18:09.972927 00f00000 ################################################################
10258 22:18:09.973108
10259 22:18:10.199638 00f80000 ################################################################
10260 22:18:10.199788
10261 22:18:10.432809 01000000 ################################################################
10262 22:18:10.432949
10263 22:18:10.661974 01080000 ################################################################
10264 22:18:10.662129
10265 22:18:10.892164 01100000 ################################################################
10266 22:18:10.892353
10267 22:18:11.120268 01180000 ################################################################
10268 22:18:11.120420
10269 22:18:11.346373 01200000 ################################################################
10270 22:18:11.346524
10271 22:18:11.574780 01280000 ################################################################
10272 22:18:11.574917
10273 22:18:11.809624 01300000 ################################################################
10274 22:18:11.809775
10275 22:18:12.056462 01380000 ################################################################
10276 22:18:12.056634
10277 22:18:12.284238 01400000 ################################################################
10278 22:18:12.284399
10279 22:18:12.541016 01480000 ################################################################
10280 22:18:12.541151
10281 22:18:12.769606 01500000 ################################################################
10282 22:18:12.769746
10283 22:18:12.995957 01580000 ################################################################
10284 22:18:12.996087
10285 22:18:13.221818 01600000 ################################################################
10286 22:18:13.221968
10287 22:18:13.451602 01680000 ################################################################
10288 22:18:13.451749
10289 22:18:13.677851 01700000 ################################################################
10290 22:18:13.677995
10291 22:18:13.907653 01780000 ################################################################
10292 22:18:13.907798
10293 22:18:14.134308 01800000 ################################################################
10294 22:18:14.134440
10295 22:18:14.365157 01880000 ################################################################
10296 22:18:14.365308
10297 22:18:14.591322 01900000 ################################################################
10298 22:18:14.591503
10299 22:18:14.818077 01980000 ################################################################
10300 22:18:14.818226
10301 22:18:15.037980 01a00000 ############################################################### done.
10302 22:18:15.038136
10303 22:18:15.041093 The bootfile was 27776958 bytes long.
10304 22:18:15.041175
10305 22:18:15.044661 Sending tftp read request... done.
10306 22:18:15.044744
10307 22:18:15.047834 Waiting for the transfer...
10308 22:18:15.047915
10309 22:18:15.050686 00000000 # done.
10310 22:18:15.050769
10311 22:18:15.057910 Command line loaded dynamically from TFTP file: 10597264/tftp-deploy-9iuqvnbb/kernel/cmdline
10312 22:18:15.057998
10313 22:18:15.078090 The command line is: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/10597264/extract-nfsrootfs-sl45zt8p,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10314 22:18:15.078208
10315 22:18:15.078277 Loading FIT.
10316 22:18:15.080657
10317 22:18:15.080738 Image ramdisk-1 has 17645696 bytes.
10318 22:18:15.080802
10319 22:18:15.084110 Image fdt-1 has 46924 bytes.
10320 22:18:15.084192
10321 22:18:15.087353 Image kernel-1 has 10082307 bytes.
10322 22:18:15.087434
10323 22:18:15.097507 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10324 22:18:15.097594
10325 22:18:15.113740 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10326 22:18:15.113834
10327 22:18:15.119993 Choosing best match conf-1 for compat google,spherion-rev2.
10328 22:18:15.123507
10329 22:18:15.128120 Connected to device vid:did:rid of 1ae0:0028:00
10330 22:18:15.135549
10331 22:18:15.138505 tpm_get_response: command 0x17b, return code 0x0
10332 22:18:15.138587
10333 22:18:15.141846 ec_init: CrosEC protocol v3 supported (256, 248)
10334 22:18:15.146184
10335 22:18:15.149831 tpm_cleanup: add release locality here.
10336 22:18:15.149913
10337 22:18:15.149976 Shutting down all USB controllers.
10338 22:18:15.152804
10339 22:18:15.152887 Removing current net device
10340 22:18:15.152951
10341 22:18:15.159192 Exiting depthcharge with code 4 at timestamp: 46645551
10342 22:18:15.159276
10343 22:18:15.162411 LZMA decompressing kernel-1 to 0x821a6718
10344 22:18:15.162493
10345 22:18:15.165644 LZMA decompressing kernel-1 to 0x40000000
10346 22:18:16.433069
10347 22:18:16.433227 jumping to kernel
10348 22:18:16.433631 end: 2.2.4 bootloader-commands (duration 00:00:18) [common]
10349 22:18:16.433734 start: 2.2.5 auto-login-action (timeout 00:04:07) [common]
10350 22:18:16.433812 Setting prompt string to ['Linux version [0-9]']
10351 22:18:16.433880 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10352 22:18:16.433947 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10353 22:18:16.515260
10354 22:18:16.518373 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10355 22:18:16.522585 start: 2.2.5.1 login-action (timeout 00:04:07) [common]
10356 22:18:16.523060 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10357 22:18:16.523503 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10358 22:18:16.523923 Using line separator: #'\n'#
10359 22:18:16.524287 No login prompt set.
10360 22:18:16.524666 Parsing kernel messages
10361 22:18:16.524924 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10362 22:18:16.525326 [login-action] Waiting for messages, (timeout 00:04:07)
10363 22:18:16.541100 [ 0.000000] Linux version 6.1.31 (KernelCI@build-j1612341-arm64-gcc-10-defconfig-arm64-chromebook-n674v) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Mon Jun 5 22:04:07 UTC 2023
10364 22:18:16.544855 [ 0.000000] random: crng init done
10365 22:18:16.551619 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10366 22:18:16.554260 [ 0.000000] efi: UEFI not found.
10367 22:18:16.560878 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10368 22:18:16.567790 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10369 22:18:16.578057 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10370 22:18:16.587485 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10371 22:18:16.593918 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10372 22:18:16.600212 [ 0.000000] printk: bootconsole [mtk8250] enabled
10373 22:18:16.606871 [ 0.000000] NUMA: No NUMA configuration found
10374 22:18:16.613430 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10375 22:18:16.616870 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcda00-0x23efcffff]
10376 22:18:16.620251 [ 0.000000] Zone ranges:
10377 22:18:16.626536 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10378 22:18:16.629595 [ 0.000000] DMA32 empty
10379 22:18:16.636831 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10380 22:18:16.639710 [ 0.000000] Movable zone start for each node
10381 22:18:16.643561 [ 0.000000] Early memory node ranges
10382 22:18:16.649613 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10383 22:18:16.656208 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10384 22:18:16.662514 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10385 22:18:16.669399 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10386 22:18:16.675812 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10387 22:18:16.682821 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10388 22:18:16.739163 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10389 22:18:16.745376 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10390 22:18:16.751871 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10391 22:18:16.755997 [ 0.000000] psci: probing for conduit method from DT.
10392 22:18:16.761657 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10393 22:18:16.765572 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10394 22:18:16.771823 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10395 22:18:16.775326 [ 0.000000] psci: SMC Calling Convention v1.2
10396 22:18:16.781832 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10397 22:18:16.786069 [ 0.000000] Detected VIPT I-cache on CPU0
10398 22:18:16.791590 [ 0.000000] CPU features: detected: GIC system register CPU interface
10399 22:18:16.798229 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10400 22:18:16.804744 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10401 22:18:16.811965 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10402 22:18:16.818275 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10403 22:18:16.829033 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10404 22:18:16.831126 [ 0.000000] alternatives: applying boot alternatives
10405 22:18:16.837660 [ 0.000000] Fallback order for Node 0: 0
10406 22:18:16.844445 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10407 22:18:16.847540 [ 0.000000] Policy zone: Normal
10408 22:18:16.867557 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/10597264/extract-nfsrootfs-sl45zt8p,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10409 22:18:16.877471 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10410 22:18:16.889252 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10411 22:18:16.899193 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10412 22:18:16.905740 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10413 22:18:16.908970 <6>[ 0.000000] software IO TLB: area num 8.
10414 22:18:16.965815 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10415 22:18:17.114746 <6>[ 0.000000] Memory: 7955712K/8385536K available (17984K kernel code, 4098K rwdata, 14068K rodata, 8384K init, 615K bss, 397056K reserved, 32768K cma-reserved)
10416 22:18:17.121531 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10417 22:18:17.128148 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10418 22:18:17.131222 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10419 22:18:17.138046 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10420 22:18:17.144694 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10421 22:18:17.151185 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10422 22:18:17.157656 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10423 22:18:17.165320 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10424 22:18:17.170810 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10425 22:18:17.177301 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10426 22:18:17.180524 <6>[ 0.000000] GICv3: 608 SPIs implemented
10427 22:18:17.183770 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10428 22:18:17.190582 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10429 22:18:17.193630 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10430 22:18:17.200195 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10431 22:18:17.213357 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10432 22:18:17.226472 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10433 22:18:17.233280 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10434 22:18:17.241360 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10435 22:18:17.254451 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10436 22:18:17.261296 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10437 22:18:17.269321 <6>[ 0.009190] Console: colour dummy device 80x25
10438 22:18:17.277678 <6>[ 0.013919] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10439 22:18:17.284206 <6>[ 0.024361] pid_max: default: 32768 minimum: 301
10440 22:18:17.287709 <6>[ 0.029234] LSM: Security Framework initializing
10441 22:18:17.295085 <6>[ 0.034171] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10442 22:18:17.304621 <6>[ 0.041983] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10443 22:18:17.313887 <6>[ 0.051415] cblist_init_generic: Setting adjustable number of callback queues.
10444 22:18:17.317145 <6>[ 0.058868] cblist_init_generic: Setting shift to 3 and lim to 1.
10445 22:18:17.323800 <6>[ 0.065247] cblist_init_generic: Setting shift to 3 and lim to 1.
10446 22:18:17.330375 <6>[ 0.071654] rcu: Hierarchical SRCU implementation.
10447 22:18:17.337042 <6>[ 0.076668] rcu: Max phase no-delay instances is 1000.
10448 22:18:17.343564 <6>[ 0.083720] EFI services will not be available.
10449 22:18:17.347005 <6>[ 0.088694] smp: Bringing up secondary CPUs ...
10450 22:18:17.355438 <6>[ 0.093750] Detected VIPT I-cache on CPU1
10451 22:18:17.361417 <6>[ 0.093821] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10452 22:18:17.368087 <6>[ 0.093852] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10453 22:18:17.371656 <6>[ 0.094188] Detected VIPT I-cache on CPU2
10454 22:18:17.381347 <6>[ 0.094237] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10455 22:18:17.387887 <6>[ 0.094253] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10456 22:18:17.391525 <6>[ 0.094507] Detected VIPT I-cache on CPU3
10457 22:18:17.397353 <6>[ 0.094554] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10458 22:18:17.404485 <6>[ 0.094568] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10459 22:18:17.410759 <6>[ 0.094873] CPU features: detected: Spectre-v4
10460 22:18:17.413675 <6>[ 0.094880] CPU features: detected: Spectre-BHB
10461 22:18:17.417198 <6>[ 0.094886] Detected PIPT I-cache on CPU4
10462 22:18:17.424362 <6>[ 0.094941] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10463 22:18:17.430310 <6>[ 0.094957] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10464 22:18:17.437378 <6>[ 0.095249] Detected PIPT I-cache on CPU5
10465 22:18:17.443801 <6>[ 0.095311] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10466 22:18:17.450512 <6>[ 0.095328] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10467 22:18:17.453706 <6>[ 0.095608] Detected PIPT I-cache on CPU6
10468 22:18:17.460773 <6>[ 0.095672] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10469 22:18:17.470295 <6>[ 0.095689] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10470 22:18:17.473347 <6>[ 0.095984] Detected PIPT I-cache on CPU7
10471 22:18:17.480386 <6>[ 0.096048] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10472 22:18:17.486757 <6>[ 0.096064] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10473 22:18:17.489969 <6>[ 0.096110] smp: Brought up 1 node, 8 CPUs
10474 22:18:17.496284 <6>[ 0.237357] SMP: Total of 8 processors activated.
10475 22:18:17.499628 <6>[ 0.242278] CPU features: detected: 32-bit EL0 Support
10476 22:18:17.509765 <6>[ 0.247641] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10477 22:18:17.516404 <6>[ 0.256441] CPU features: detected: Common not Private translations
10478 22:18:17.522788 <6>[ 0.262957] CPU features: detected: CRC32 instructions
10479 22:18:17.529349 <6>[ 0.268341] CPU features: detected: RCpc load-acquire (LDAPR)
10480 22:18:17.533036 <6>[ 0.274301] CPU features: detected: LSE atomic instructions
10481 22:18:17.539222 <6>[ 0.280083] CPU features: detected: Privileged Access Never
10482 22:18:17.546046 <6>[ 0.285898] CPU features: detected: RAS Extension Support
10483 22:18:17.552567 <6>[ 0.291507] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10484 22:18:17.555763 <6>[ 0.298771] CPU: All CPU(s) started at EL2
10485 22:18:17.562227 <6>[ 0.303088] alternatives: applying system-wide alternatives
10486 22:18:17.572334 <6>[ 0.313742] devtmpfs: initialized
10487 22:18:17.588305 <6>[ 0.322613] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10488 22:18:17.594165 <6>[ 0.332577] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10489 22:18:17.601252 <6>[ 0.340770] pinctrl core: initialized pinctrl subsystem
10490 22:18:17.604775 <6>[ 0.347401] DMI not present or invalid.
10491 22:18:17.611746 <6>[ 0.351811] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10492 22:18:17.620685 <6>[ 0.358706] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10493 22:18:17.627473 <6>[ 0.366290] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10494 22:18:17.637152 <6>[ 0.374522] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10495 22:18:17.640475 <6>[ 0.382760] audit: initializing netlink subsys (disabled)
10496 22:18:17.650755 <5>[ 0.388454] audit: type=2000 audit(0.276:1): state=initialized audit_enabled=0 res=1
10497 22:18:17.657125 <6>[ 0.389150] thermal_sys: Registered thermal governor 'step_wise'
10498 22:18:17.663835 <6>[ 0.396422] thermal_sys: Registered thermal governor 'power_allocator'
10499 22:18:17.667263 <6>[ 0.402679] cpuidle: using governor menu
10500 22:18:17.673760 <6>[ 0.413637] NET: Registered PF_QIPCRTR protocol family
10501 22:18:17.680274 <6>[ 0.419126] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10502 22:18:17.687599 <6>[ 0.426224] ASID allocator initialised with 32768 entries
10503 22:18:17.689924 <6>[ 0.432795] Serial: AMBA PL011 UART driver
10504 22:18:17.699715 <4>[ 0.441395] Trying to register duplicate clock ID: 134
10505 22:18:17.753590 <6>[ 0.498520] KASLR enabled
10506 22:18:17.768385 <6>[ 0.506411] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10507 22:18:17.774538 <6>[ 0.513428] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10508 22:18:17.781835 <6>[ 0.519916] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10509 22:18:17.788182 <6>[ 0.526918] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10510 22:18:17.794424 <6>[ 0.533402] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10511 22:18:17.801582 <6>[ 0.540407] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10512 22:18:17.807802 <6>[ 0.546895] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10513 22:18:17.814489 <6>[ 0.553900] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10514 22:18:17.817691 <6>[ 0.561422] ACPI: Interpreter disabled.
10515 22:18:17.826273 <6>[ 0.567811] iommu: Default domain type: Translated
10516 22:18:17.832862 <6>[ 0.572921] iommu: DMA domain TLB invalidation policy: strict mode
10517 22:18:17.836425 <5>[ 0.579572] SCSI subsystem initialized
10518 22:18:17.842910 <6>[ 0.583737] usbcore: registered new interface driver usbfs
10519 22:18:17.849410 <6>[ 0.589473] usbcore: registered new interface driver hub
10520 22:18:17.852390 <6>[ 0.595021] usbcore: registered new device driver usb
10521 22:18:17.859698 <6>[ 0.601104] pps_core: LinuxPPS API ver. 1 registered
10522 22:18:17.869587 <6>[ 0.606299] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10523 22:18:17.873083 <6>[ 0.615648] PTP clock support registered
10524 22:18:17.876055 <6>[ 0.619891] EDAC MC: Ver: 3.0.0
10525 22:18:17.883961 <6>[ 0.625026] FPGA manager framework
10526 22:18:17.889811 <6>[ 0.628707] Advanced Linux Sound Architecture Driver Initialized.
10527 22:18:17.893226 <6>[ 0.635481] vgaarb: loaded
10528 22:18:17.900339 <6>[ 0.638662] clocksource: Switched to clocksource arch_sys_counter
10529 22:18:17.903376 <5>[ 0.645105] VFS: Disk quotas dquot_6.6.0
10530 22:18:17.910023 <6>[ 0.649291] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10531 22:18:17.913111 <6>[ 0.656478] pnp: PnP ACPI: disabled
10532 22:18:17.922242 <6>[ 0.663191] NET: Registered PF_INET protocol family
10533 22:18:17.932200 <6>[ 0.668785] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10534 22:18:17.943197 <6>[ 0.681116] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10535 22:18:17.952732 <6>[ 0.689933] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10536 22:18:17.959638 <6>[ 0.697903] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10537 22:18:17.969373 <6>[ 0.706604] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10538 22:18:17.976053 <6>[ 0.716350] TCP: Hash tables configured (established 65536 bind 65536)
10539 22:18:17.982618 <6>[ 0.723208] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10540 22:18:17.992707 <6>[ 0.730409] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10541 22:18:17.999014 <6>[ 0.738110] NET: Registered PF_UNIX/PF_LOCAL protocol family
10542 22:18:18.005487 <6>[ 0.744278] RPC: Registered named UNIX socket transport module.
10543 22:18:18.008606 <6>[ 0.750433] RPC: Registered udp transport module.
10544 22:18:18.015738 <6>[ 0.755367] RPC: Registered tcp transport module.
10545 22:18:18.021819 <6>[ 0.760298] RPC: Registered tcp NFSv4.1 backchannel transport module.
10546 22:18:18.025351 <6>[ 0.766965] PCI: CLS 0 bytes, default 64
10547 22:18:18.028431 <6>[ 0.771340] Unpacking initramfs...
10548 22:18:18.044916 <6>[ 0.783255] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10549 22:18:18.055016 <6>[ 0.791921] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10550 22:18:18.058385 <6>[ 0.800760] kvm [1]: IPA Size Limit: 40 bits
10551 22:18:18.064638 <6>[ 0.805290] kvm [1]: GICv3: no GICV resource entry
10552 22:18:18.068432 <6>[ 0.810312] kvm [1]: disabling GICv2 emulation
10553 22:18:18.074647 <6>[ 0.814999] kvm [1]: GIC system register CPU interface enabled
10554 22:18:18.078278 <6>[ 0.821163] kvm [1]: vgic interrupt IRQ18
10555 22:18:18.085101 <6>[ 0.826786] kvm [1]: VHE mode initialized successfully
10556 22:18:18.091763 <5>[ 0.833173] Initialise system trusted keyrings
10557 22:18:18.098594 <6>[ 0.837983] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10558 22:18:18.106226 <6>[ 0.847974] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10559 22:18:18.112781 <5>[ 0.854358] NFS: Registering the id_resolver key type
10560 22:18:18.116660 <5>[ 0.859657] Key type id_resolver registered
10561 22:18:18.122916 <5>[ 0.864070] Key type id_legacy registered
10562 22:18:18.129784 <6>[ 0.868367] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10563 22:18:18.136481 <6>[ 0.875287] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10564 22:18:18.142864 <6>[ 0.883013] 9p: Installing v9fs 9p2000 file system support
10565 22:18:18.179820 <5>[ 0.920869] Key type asymmetric registered
10566 22:18:18.183127 <5>[ 0.925202] Asymmetric key parser 'x509' registered
10567 22:18:18.192804 <6>[ 0.930371] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10568 22:18:18.195970 <6>[ 0.937987] io scheduler mq-deadline registered
10569 22:18:18.199252 <6>[ 0.942766] io scheduler kyber registered
10570 22:18:18.218039 <6>[ 0.959601] EINJ: ACPI disabled.
10571 22:18:18.250502 <4>[ 0.985189] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10572 22:18:18.260202 <4>[ 0.995862] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10573 22:18:18.275385 <6>[ 1.016510] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10574 22:18:18.284263 <6>[ 1.024560] printk: console [ttyS0] disabled
10575 22:18:18.311301 <6>[ 1.049218] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10576 22:18:18.318473 <6>[ 1.058703] printk: console [ttyS0] enabled
10577 22:18:18.321130 <6>[ 1.058703] printk: console [ttyS0] enabled
10578 22:18:18.327711 <6>[ 1.067603] printk: bootconsole [mtk8250] disabled
10579 22:18:18.330660 <6>[ 1.067603] printk: bootconsole [mtk8250] disabled
10580 22:18:18.337656 <6>[ 1.078881] SuperH (H)SCI(F) driver initialized
10581 22:18:18.341138 <6>[ 1.084143] msm_serial: driver initialized
10582 22:18:18.354895 <6>[ 1.093049] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10583 22:18:18.364822 <6>[ 1.101597] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10584 22:18:18.371816 <6>[ 1.110140] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10585 22:18:18.381443 <6>[ 1.118766] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10586 22:18:18.391602 <6>[ 1.127472] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10587 22:18:18.398112 <6>[ 1.136192] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10588 22:18:18.407954 <6>[ 1.144734] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10589 22:18:18.414585 <6>[ 1.153552] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10590 22:18:18.424449 <6>[ 1.162098] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10591 22:18:18.436287 <6>[ 1.177606] loop: module loaded
10592 22:18:18.442411 <6>[ 1.183528] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10593 22:18:18.465272 <4>[ 1.206811] mtk-pmic-keys: Failed to locate of_node [id: -1]
10594 22:18:18.472090 <6>[ 1.213584] megasas: 07.719.03.00-rc1
10595 22:18:18.481702 <6>[ 1.223111] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10596 22:18:18.488791 <6>[ 1.230089] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10597 22:18:18.505219 <6>[ 1.246821] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10598 22:18:18.566211 <6>[ 1.301053] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10599 22:18:18.758944 <6>[ 1.500249] Freeing initrd memory: 17228K
10600 22:18:18.769500 <6>[ 1.510704] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10601 22:18:18.780421 <6>[ 1.521537] tun: Universal TUN/TAP device driver, 1.6
10602 22:18:18.783324 <6>[ 1.527592] thunder_xcv, ver 1.0
10603 22:18:18.787032 <6>[ 1.531095] thunder_bgx, ver 1.0
10604 22:18:18.790092 <6>[ 1.534588] nicpf, ver 1.0
10605 22:18:18.801028 <6>[ 1.538590] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10606 22:18:18.803887 <6>[ 1.546067] hns3: Copyright (c) 2017 Huawei Corporation.
10607 22:18:18.810444 <6>[ 1.551658] hclge is initializing
10608 22:18:18.813623 <6>[ 1.555239] e1000: Intel(R) PRO/1000 Network Driver
10609 22:18:18.820249 <6>[ 1.560368] e1000: Copyright (c) 1999-2006 Intel Corporation.
10610 22:18:18.823598 <6>[ 1.566380] e1000e: Intel(R) PRO/1000 Network Driver
10611 22:18:18.830241 <6>[ 1.571597] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10612 22:18:18.837487 <6>[ 1.577781] igb: Intel(R) Gigabit Ethernet Network Driver
10613 22:18:18.844184 <6>[ 1.583430] igb: Copyright (c) 2007-2014 Intel Corporation.
10614 22:18:18.850176 <6>[ 1.589266] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10615 22:18:18.856710 <6>[ 1.595783] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10616 22:18:18.860163 <6>[ 1.602240] sky2: driver version 1.30
10617 22:18:18.867718 <6>[ 1.607217] VFIO - User Level meta-driver version: 0.3
10618 22:18:18.873974 <6>[ 1.615428] usbcore: registered new interface driver usb-storage
10619 22:18:18.880456 <6>[ 1.621870] usbcore: registered new device driver onboard-usb-hub
10620 22:18:18.889873 <6>[ 1.630968] mt6397-rtc mt6359-rtc: registered as rtc0
10621 22:18:18.899516 <6>[ 1.636438] mt6397-rtc mt6359-rtc: setting system clock to 2023-06-05T22:18:18 UTC (1686003498)
10622 22:18:18.902839 <6>[ 1.646015] i2c_dev: i2c /dev entries driver
10623 22:18:18.919502 <6>[ 1.657613] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10624 22:18:18.926511 <6>[ 1.667825] sdhci: Secure Digital Host Controller Interface driver
10625 22:18:18.932785 <6>[ 1.674263] sdhci: Copyright(c) Pierre Ossman
10626 22:18:18.939537 <6>[ 1.679647] Synopsys Designware Multimedia Card Interface Driver
10627 22:18:18.943118 <6>[ 1.686240] mmc0: CQHCI version 5.10
10628 22:18:18.949150 <6>[ 1.686809] sdhci-pltfm: SDHCI platform and OF driver helper
10629 22:18:18.957468 <6>[ 1.698406] ledtrig-cpu: registered to indicate activity on CPUs
10630 22:18:18.968057 <6>[ 1.705868] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10631 22:18:18.974295 <6>[ 1.713273] usbcore: registered new interface driver usbhid
10632 22:18:18.977398 <6>[ 1.719105] usbhid: USB HID core driver
10633 22:18:18.983804 <6>[ 1.723355] spi_master spi0: will run message pump with realtime priority
10634 22:18:19.033457 <6>[ 1.768489] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10635 22:18:19.040914 <6>[ 1.782569] mmc0: Command Queue Engine enabled
10636 22:18:19.047837 <6>[ 1.787332] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10637 22:18:19.061302 <6>[ 1.787451] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10638 22:18:19.064701 <6>[ 1.794424] mmcblk0: mmc0:0001 DA4128 116 GiB
10639 22:18:19.071384 <6>[ 1.809117] cros-ec-spi spi0.0: Chrome EC device registered
10640 22:18:19.077966 <6>[ 1.818893] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10641 22:18:19.084775 <6>[ 1.826321] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10642 22:18:19.091605 <6>[ 1.832328] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10643 22:18:19.102037 <6>[ 1.837734] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10644 22:18:19.108240 <6>[ 1.838313] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10645 22:18:19.111084 <6>[ 1.849230] NET: Registered PF_PACKET protocol family
10646 22:18:19.117842 <6>[ 1.858997] 9pnet: Installing 9P2000 support
10647 22:18:19.121655 <5>[ 1.863581] Key type dns_resolver registered
10648 22:18:19.127874 <6>[ 1.868814] registered taskstats version 1
10649 22:18:19.131103 <5>[ 1.873230] Loading compiled-in X.509 certificates
10650 22:18:19.164873 <4>[ 1.899686] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10651 22:18:19.174788 <4>[ 1.910382] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10652 22:18:19.184826 <3>[ 1.923197] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10653 22:18:19.197351 <6>[ 1.938553] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10654 22:18:19.203945 <6>[ 1.945352] xhci-mtk 11200000.usb: xHCI Host Controller
10655 22:18:19.210807 <6>[ 1.950873] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10656 22:18:19.220472 <6>[ 1.958750] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10657 22:18:19.227623 <6>[ 1.968184] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10658 22:18:19.234179 <6>[ 1.974391] xhci-mtk 11200000.usb: xHCI Host Controller
10659 22:18:19.240467 <6>[ 1.979902] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10660 22:18:19.246952 <6>[ 1.987560] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10661 22:18:19.254119 <6>[ 1.995453] hub 1-0:1.0: USB hub found
10662 22:18:19.257096 <6>[ 1.999504] hub 1-0:1.0: 1 port detected
10663 22:18:19.267675 <6>[ 2.003842] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10664 22:18:19.270474 <6>[ 2.012646] hub 2-0:1.0: USB hub found
10665 22:18:19.273916 <6>[ 2.016697] hub 2-0:1.0: 1 port detected
10666 22:18:19.282708 <6>[ 2.023872] mtk-msdc 11f70000.mmc: Got CD GPIO
10667 22:18:19.300350 <6>[ 2.038209] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10668 22:18:19.307225 <6>[ 2.046272] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10669 22:18:19.317070 <4>[ 2.054417] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10670 22:18:19.326946 <6>[ 2.064097] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10671 22:18:19.333177 <6>[ 2.072237] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10672 22:18:19.342814 <6>[ 2.080264] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10673 22:18:19.350011 <6>[ 2.088220] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10674 22:18:19.355896 <6>[ 2.096050] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10675 22:18:19.366068 <6>[ 2.103901] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10676 22:18:19.376708 <6>[ 2.114480] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10677 22:18:19.386139 <6>[ 2.122922] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10678 22:18:19.393204 <6>[ 2.131269] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10679 22:18:19.403118 <6>[ 2.139640] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10680 22:18:19.409596 <6>[ 2.147988] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10681 22:18:19.419283 <6>[ 2.156357] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10682 22:18:19.426149 <6>[ 2.164704] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10683 22:18:19.435970 <6>[ 2.173073] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10684 22:18:19.442630 <6>[ 2.181417] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10685 22:18:19.452753 <6>[ 2.189782] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10686 22:18:19.458997 <6>[ 2.198125] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10687 22:18:19.468986 <6>[ 2.206469] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10688 22:18:19.475492 <6>[ 2.214814] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10689 22:18:19.485627 <6>[ 2.223158] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10690 22:18:19.491951 <6>[ 2.231501] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10691 22:18:19.498785 <6>[ 2.240417] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10692 22:18:19.507357 <6>[ 2.247904] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10693 22:18:19.513505 <6>[ 2.254962] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10694 22:18:19.523601 <6>[ 2.262097] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10695 22:18:19.530570 <6>[ 2.269401] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10696 22:18:19.540204 <6>[ 2.276303] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10697 22:18:19.546718 <6>[ 2.285444] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10698 22:18:19.557160 <6>[ 2.294571] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10699 22:18:19.566491 <6>[ 2.303903] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10700 22:18:19.576512 <6>[ 2.313396] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10701 22:18:19.586620 <6>[ 2.322872] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10702 22:18:19.596454 <6>[ 2.332000] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10703 22:18:19.603381 <6>[ 2.341474] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10704 22:18:19.612738 <6>[ 2.350607] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10705 22:18:19.622707 <6>[ 2.359913] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10706 22:18:19.632775 <6>[ 2.370079] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10707 22:18:19.643284 <6>[ 2.381866] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10708 22:18:19.650357 <6>[ 2.391965] Trying to probe devices needed for running init ...
10709 22:18:19.665329 <6>[ 2.402948] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10710 22:18:19.692531 <6>[ 2.433371] hub 2-1:1.0: USB hub found
10711 22:18:19.695319 <6>[ 2.437772] hub 2-1:1.0: 3 ports detected
10712 22:18:19.816647 <6>[ 2.554935] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10713 22:18:19.970935 <6>[ 2.712362] hub 1-1:1.0: USB hub found
10714 22:18:19.974228 <6>[ 2.716813] hub 1-1:1.0: 4 ports detected
10715 22:18:20.296461 <6>[ 3.034936] usb 1-1.1: new high-speed USB device number 3 using xhci-mtk
10716 22:18:20.427058 <6>[ 3.168805] hub 1-1.1:1.0: USB hub found
10717 22:18:20.430194 <6>[ 3.173088] hub 1-1.1:1.0: 4 ports detected
10718 22:18:20.544133 <6>[ 3.282713] usb 1-1.4: new high-speed USB device number 4 using xhci-mtk
10719 22:18:20.677427 <6>[ 3.418859] hub 1-1.4:1.0: USB hub found
10720 22:18:20.680374 <6>[ 3.423472] hub 1-1.4:1.0: 2 ports detected
10721 22:18:20.756792 <6>[ 3.494855] usb 1-1.1.1: new high-speed USB device number 5 using xhci-mtk
10722 22:18:20.944352 <6>[ 3.682935] usb 1-1.1.4: new full-speed USB device number 6 using xhci-mtk
10723 22:18:21.029611 <3>[ 3.771144] usb 1-1.1.4: device descriptor read/64, error -32
10724 22:18:21.221056 <3>[ 3.963142] usb 1-1.1.4: device descriptor read/64, error -32
10725 22:18:21.416492 <6>[ 4.154936] usb 1-1.4.1: new high-speed USB device number 7 using xhci-mtk
10726 22:18:21.604416 <6>[ 4.342937] usb 1-1.1.4: new full-speed USB device number 8 using xhci-mtk
10727 22:18:21.689411 <3>[ 4.431095] usb 1-1.1.4: device descriptor read/64, error -32
10728 22:18:21.881129 <3>[ 4.623022] usb 1-1.1.4: device descriptor read/64, error -32
10729 22:18:21.993546 <6>[ 4.735338] usb 1-1.1-port4: attempt power cycle
10730 22:18:22.080338 <6>[ 4.818839] usb 1-1.4.2: new high-speed USB device number 9 using xhci-mtk
10731 22:18:22.605124 <6>[ 5.342938] usb 1-1.1.4: new full-speed USB device number 10 using xhci-mtk
10732 22:18:22.610762 <4>[ 5.350459] usb 1-1.1.4: Device not responding to setup address.
10733 22:18:22.821493 <4>[ 5.563202] usb 1-1.1.4: Device not responding to setup address.
10734 22:18:23.032883 <3>[ 5.774930] usb 1-1.1.4: device not accepting address 10, error -71
10735 22:18:23.120482 <6>[ 5.858934] usb 1-1.1.4: new full-speed USB device number 11 using xhci-mtk
10736 22:18:23.126913 <4>[ 5.866387] usb 1-1.1.4: Device not responding to setup address.
10737 22:18:23.337564 <4>[ 6.079219] usb 1-1.1.4: Device not responding to setup address.
10738 22:18:23.548686 <3>[ 6.290927] usb 1-1.1.4: device not accepting address 11, error -71
10739 22:18:23.556049 <3>[ 6.297878] usb 1-1.1-port4: unable to enumerate USB device
10740 22:18:31.921207 <6>[ 14.667535] ALSA device list:
10741 22:18:31.928126 <6>[ 14.670799] No soundcards found.
10742 22:18:31.935502 <6>[ 14.678165] Freeing unused kernel memory: 8384K
10743 22:18:31.938822 <6>[ 14.683071] Run /init as init process
10744 22:18:31.946683 Loading, please wait...
10745 22:18:31.964996 Starting version 247.3-7+deb11u2
10746 22:18:32.284353 <6>[ 15.023818] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10747 22:18:32.295049 <6>[ 15.038129] remoteproc remoteproc0: scp is available
10748 22:18:32.305216 <4>[ 15.044015] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10749 22:18:32.311977 <6>[ 15.053873] remoteproc remoteproc0: powering up scp
10750 22:18:32.318549 <6>[ 15.056360] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10751 22:18:32.328846 <3>[ 15.057355] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10752 22:18:32.335904 <3>[ 15.057369] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10753 22:18:32.341879 <3>[ 15.057377] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10754 22:18:32.351241 <3>[ 15.057439] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10755 22:18:32.357995 <3>[ 15.057446] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10756 22:18:32.368399 <3>[ 15.057454] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10757 22:18:32.374561 <3>[ 15.057461] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10758 22:18:32.385342 <3>[ 15.057467] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10759 22:18:32.391593 <3>[ 15.057497] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10760 22:18:32.398293 <3>[ 15.057528] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10761 22:18:32.408823 <3>[ 15.057535] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10762 22:18:32.415380 <3>[ 15.057541] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10763 22:18:32.424930 <3>[ 15.057572] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10764 22:18:32.431451 <3>[ 15.057578] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10765 22:18:32.441810 <3>[ 15.057584] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10766 22:18:32.448054 <3>[ 15.057590] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10767 22:18:32.458581 <3>[ 15.057597] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10768 22:18:32.464509 <3>[ 15.057623] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10769 22:18:32.474519 <4>[ 15.059042] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10770 22:18:32.480905 <6>[ 15.067768] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10771 22:18:32.487719 <3>[ 15.074756] remoteproc remoteproc0: request_firmware failed: -2
10772 22:18:32.494790 <4>[ 15.108664] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10773 22:18:32.504759 <4>[ 15.109743] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10774 22:18:32.507901 <4>[ 15.109743] Fallback method does not support PEC.
10775 22:18:32.517510 <6>[ 15.115424] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10776 22:18:32.520717 <6>[ 15.120375] mc: Linux media interface: v0.10
10777 22:18:32.527751 <6>[ 15.120793] usbcore: registered new interface driver r8152
10778 22:18:32.537456 <3>[ 15.126292] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10779 22:18:32.543865 <4>[ 15.126601] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10780 22:18:32.553996 <6>[ 15.132075] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10781 22:18:32.556971 <6>[ 15.148816] videodev: Linux video capture interface: v2.00
10782 22:18:32.567163 <3>[ 15.163509] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10783 22:18:32.577322 <6>[ 15.231917] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10784 22:18:32.586735 <6>[ 15.235413] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10785 22:18:32.596849 <6>[ 15.235901] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10786 22:18:32.603873 <6>[ 15.236490] usb 1-1.1.1: reset high-speed USB device number 5 using xhci-mtk
10787 22:18:32.609785 <6>[ 15.276249] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10788 22:18:32.616635 <6>[ 15.276536] usbcore: registered new interface driver cdc_ether
10789 22:18:32.623845 <6>[ 15.285340] usbcore: registered new interface driver r8153_ecm
10790 22:18:32.626506 <6>[ 15.292508] pci_bus 0000:00: root bus resource [bus 00-ff]
10791 22:18:32.633073 <6>[ 15.301942] Bluetooth: Core ver 2.22
10792 22:18:32.639579 <6>[ 15.306764] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10793 22:18:32.649434 <6>[ 15.306774] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10794 22:18:32.656487 <6>[ 15.306849] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10795 22:18:32.662655 <6>[ 15.308201] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10796 22:18:32.676008 <6>[ 15.309564] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10797 22:18:32.679776 <6>[ 15.309715] usbcore: registered new interface driver uvcvideo
10798 22:18:32.686012 <6>[ 15.315719] NET: Registered PF_BLUETOOTH protocol family
10799 22:18:32.692336 <6>[ 15.324910] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10800 22:18:32.699884 <6>[ 15.334983] Bluetooth: HCI device and connection manager initialized
10801 22:18:32.705791 <6>[ 15.344092] pci 0000:00:00.0: supports D1 D2
10802 22:18:32.709061 <6>[ 15.351334] Bluetooth: HCI socket layer initialized
10803 22:18:32.715588 <6>[ 15.351923] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10804 22:18:32.722210 <6>[ 15.358185] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10805 22:18:32.729665 <6>[ 15.364272] Bluetooth: L2CAP socket layer initialized
10806 22:18:32.735857 <6>[ 15.372148] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10807 22:18:32.742316 <6>[ 15.376095] Bluetooth: SCO socket layer initialized
10808 22:18:32.748815 <6>[ 15.380023] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10809 22:18:32.758561 <4>[ 15.394082] r8152 1-1.1.1:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10810 22:18:32.765132 <6>[ 15.396979] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10811 22:18:32.772125 <4>[ 15.403221] r8152 1-1.1.1:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10812 22:18:32.782183 <6>[ 15.410276] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10813 22:18:32.784862 <6>[ 15.429397] usbcore: registered new interface driver btusb
10814 22:18:32.798555 <4>[ 15.429840] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10815 22:18:32.801801 <3>[ 15.429848] Bluetooth: hci0: Failed to load firmware file (-2)
10816 22:18:32.808366 <3>[ 15.429851] Bluetooth: hci0: Failed to set up firmware (-2)
10817 22:18:32.817987 <4>[ 15.429855] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10818 22:18:32.827856 <6>[ 15.434312] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10819 22:18:32.832041 <6>[ 15.478781] r8152 1-1.1.1:1.0 eth0: v1.12.13
10820 22:18:32.834842 <6>[ 15.485071] pci 0000:01:00.0: supports D1 D2
10821 22:18:32.841187 <6>[ 15.499490] r8152 1-1.1.1:1.0 enxf4f5e850de0a: renamed from eth0
10822 22:18:32.847895 <6>[ 15.505556] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10823 22:18:32.854736 <6>[ 15.518907] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10824 22:18:32.864178 <6>[ 15.603871] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10825 22:18:32.871062 <6>[ 15.611959] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10826 22:18:32.880746 <6>[ 15.619964] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10827 22:18:32.887400 <6>[ 15.627974] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10828 22:18:32.897240 <6>[ 15.635986] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10829 22:18:32.900546 <6>[ 15.643994] pci 0000:00:00.0: PCI bridge to [bus 01]
10830 22:18:32.910433 <6>[ 15.649216] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10831 22:18:32.916920 <6>[ 15.657389] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10832 22:18:32.924426 <6>[ 15.664649] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10833 22:18:32.929969 <6>[ 15.671462] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10834 22:18:32.947831 <5>[ 15.687470] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10835 22:18:32.966762 <5>[ 15.706134] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10836 22:18:32.972715 <4>[ 15.713051] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10837 22:18:32.979636 <6>[ 15.721937] cfg80211: failed to load regulatory.db
10838 22:18:33.025712 <6>[ 15.765697] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10839 22:18:33.032202 <6>[ 15.773238] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10840 22:18:33.056616 <6>[ 15.799932] mt7921e 0000:01:00.0: ASIC revision: 79610010
10841 22:18:33.162618 <4>[ 15.899359] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10842 22:18:33.165997 Begin: Loading essential drivers ... done.
10843 22:18:33.169792 Begin: Running /scripts/init-premount ... done.
10844 22:18:33.179336 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10845 22:18:33.185698 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10846 22:18:33.189084 Device /sys/class/net/enxf4f5e850de0a found
10847 22:18:33.192384 done.
10848 22:18:33.246756 IP-Config: enxf4f5e850de0a hardware address f4:f5:e8:50:de:0a mtu 1500 DHCP
10849 22:18:33.284843 <4>[ 16.020989] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10850 22:18:33.404468 <4>[ 16.140591] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10851 22:18:33.520106 <4>[ 16.256496] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10852 22:18:33.635877 <4>[ 16.372371] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10853 22:18:33.751848 <4>[ 16.488285] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10854 22:18:33.867846 <4>[ 16.604214] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10855 22:18:33.983554 <4>[ 16.720285] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10856 22:18:34.099498 <4>[ 16.836235] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10857 22:18:34.215474 <4>[ 16.952116] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10858 22:18:34.322471 <3>[ 17.066043] mt7921e 0000:01:00.0: hardware init failed
10859 22:18:34.361043 <6>[ 17.104511] r8152 1-1.1.1:1.0 enxf4f5e850de0a: carrier on
10860 22:18:34.393638 IP-Config: no response after 2 secs - giving up
10861 22:18:34.442626 IP-Config: enxf4f5e850de0a hardware address f4:f5:e8:50:de:0a mtu 1500 DHCP
10862 22:18:34.445943 IP-Config: enxf4f5e850de0a complete (dhcp from 192.168.201.1):
10863 22:18:34.452995 address: 192.168.201.14 broadcast: 192.168.201.255 netmask: 255.255.255.0
10864 22:18:34.462785 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10865 22:18:34.469285 host : mt8192-asurada-spherion-r0-cbg-9
10866 22:18:34.472743 domain : lava-rack
10867 22:18:34.478934 rootserver: 192.168.201.1 rootpath:
10868 22:18:34.479050 filename :
10869 22:18:34.486412 done.
10870 22:18:34.491955 Begin: Running /scripts/nfs-bottom ... done.
10871 22:18:34.508838 Begin: Running /scripts/init-bottom ... done.
10872 22:18:35.575295 <6>[ 18.318934] NET: Registered PF_INET6 protocol family
10873 22:18:35.581892 <6>[ 18.325516] Segment Routing with IPv6
10874 22:18:35.585157 <6>[ 18.329484] In-situ OAM (IOAM) with IPv6
10875 22:18:35.688225 <30>[ 18.411869] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10876 22:18:35.691415 <30>[ 18.435616] systemd[1]: Detected architecture arm64.
10877 22:18:35.709864
10878 22:18:35.713131 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10879 22:18:35.713230
10880 22:18:35.729828 <30>[ 18.472797] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10881 22:18:36.203815 <30>[ 18.943995] systemd[1]: Queued start job for default target Graphical Interface.
10882 22:18:36.228398 <30>[ 18.971973] systemd[1]: Created slice system-getty.slice.
10883 22:18:36.234829 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10884 22:18:36.252645 <30>[ 18.995656] systemd[1]: Created slice system-modprobe.slice.
10885 22:18:36.259098 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10886 22:18:36.276193 <30>[ 19.019676] systemd[1]: Created slice system-serial\x2dgetty.slice.
10887 22:18:36.286376 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10888 22:18:36.300173 <30>[ 19.043502] systemd[1]: Created slice User and Session Slice.
10889 22:18:36.306635 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10890 22:18:36.327147 <30>[ 19.067152] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10891 22:18:36.336722 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10892 22:18:36.350598 <30>[ 19.091074] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10893 22:18:36.357293 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10894 22:18:36.377975 <30>[ 19.115022] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10895 22:18:36.384993 <30>[ 19.127043] systemd[1]: Reached target Local Encrypted Volumes.
10896 22:18:36.391232 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10897 22:18:36.407310 <30>[ 19.150955] systemd[1]: Reached target Paths.
10898 22:18:36.410604 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10899 22:18:36.427482 <30>[ 19.170960] systemd[1]: Reached target Remote File Systems.
10900 22:18:36.434416 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10901 22:18:36.451596 <30>[ 19.195205] systemd[1]: Reached target Slices.
10902 22:18:36.458130 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10903 22:18:36.471587 <30>[ 19.214933] systemd[1]: Reached target Swap.
10904 22:18:36.474720 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10905 22:18:36.494888 <30>[ 19.235296] systemd[1]: Listening on initctl Compatibility Named Pipe.
10906 22:18:36.501298 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10907 22:18:36.508400 <30>[ 19.250533] systemd[1]: Listening on Journal Audit Socket.
10908 22:18:36.514788 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10909 22:18:36.528419 <30>[ 19.271759] systemd[1]: Listening on Journal Socket (/dev/log).
10910 22:18:36.535012 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10911 22:18:36.552295 <30>[ 19.295757] systemd[1]: Listening on Journal Socket.
10912 22:18:36.558591 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10913 22:18:36.576885 <30>[ 19.316152] systemd[1]: Listening on Network Service Netlink Socket.
10914 22:18:36.582380 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10915 22:18:36.597590 <30>[ 19.341008] systemd[1]: Listening on udev Control Socket.
10916 22:18:36.604290 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10917 22:18:36.619620 <30>[ 19.363221] systemd[1]: Listening on udev Kernel Socket.
10918 22:18:36.627332 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10919 22:18:36.676018 <30>[ 19.419143] systemd[1]: Mounting Huge Pages File System...
10920 22:18:36.682676 Mounting [0;1;39mHuge Pages File System[0m...
10921 22:18:36.697675 <30>[ 19.441091] systemd[1]: Mounting POSIX Message Queue File System...
10922 22:18:36.704080 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10923 22:18:36.721729 <30>[ 19.465185] systemd[1]: Mounting Kernel Debug File System...
10924 22:18:36.727954 Mounting [0;1;39mKernel Debug File System[0m...
10925 22:18:36.746973 <30>[ 19.487280] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10926 22:18:36.763074 <30>[ 19.502785] systemd[1]: Starting Create list of static device nodes for the current kernel...
10927 22:18:36.769594 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10928 22:18:36.819744 <30>[ 19.563304] systemd[1]: Starting Load Kernel Module configfs...
10929 22:18:36.826168 Starting [0;1;39mLoad Kernel Module configfs[0m...
10930 22:18:36.841403 <30>[ 19.585222] systemd[1]: Starting Load Kernel Module drm...
10931 22:18:36.847854 Starting [0;1;39mLoad Kernel Module drm[0m...
10932 22:18:36.866109 <30>[ 19.609367] systemd[1]: Starting Load Kernel Module fuse...
10933 22:18:36.872268 Starting [0;1;39mLoad Kernel Module fuse[0m...
10934 22:18:36.900260 <6>[ 19.643748] fuse: init (API version 7.37)
10935 22:18:36.910260 <30>[ 19.644723] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10936 22:18:36.918014 <30>[ 19.661785] systemd[1]: Starting Journal Service...
10937 22:18:36.922062 Starting [0;1;39mJournal Service[0m...
10938 22:18:36.945985 <30>[ 19.689632] systemd[1]: Starting Load Kernel Modules...
10939 22:18:36.952467 Starting [0;1;39mLoad Kernel Modules[0m...
10940 22:18:36.974169 <30>[ 19.714256] systemd[1]: Starting Remount Root and Kernel File Systems...
10941 22:18:36.980358 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10942 22:18:36.998842 <30>[ 19.742081] systemd[1]: Starting Coldplug All udev Devices...
10943 22:18:37.005229 Starting [0;1;39mColdplug All udev Devices[0m...
10944 22:18:37.022432 <30>[ 19.765930] systemd[1]: Mounted Huge Pages File System.
10945 22:18:37.028687 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10946 22:18:37.044216 <30>[ 19.787815] systemd[1]: Mounted POSIX Message Queue File System.
10947 22:18:37.050828 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10948 22:18:37.068374 <30>[ 19.811278] systemd[1]: Mounted Kernel Debug File System.
10949 22:18:37.077954 [[0;32m OK [<3>[ 19.818283] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10950 22:18:37.084454 0m] Mounted [0;1;39mKernel Debug File System[0m.
10951 22:18:37.104281 <30>[ 19.843826] systemd[1]: Finished Create list of static device nodes for the current kernel.
10952 22:18:37.114219 <3>[ 19.852200] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10953 22:18:37.120986 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10954 22:18:37.136338 <30>[ 19.879988] systemd[1]: modprobe@configfs.service: Succeeded.
10955 22:18:37.143408 <30>[ 19.887007] systemd[1]: Finished Load Kernel Module configfs.
10956 22:18:37.150373 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10957 22:18:37.164186 <3>[ 19.904573] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10958 22:18:37.171071 <30>[ 19.914742] systemd[1]: modprobe@drm.service: Succeeded.
10959 22:18:37.178719 <30>[ 19.921231] systemd[1]: Finished Load Kernel Module drm.
10960 22:18:37.184365 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10961 22:18:37.200908 <30>[ 19.943879] systemd[1]: modprobe@fuse.service: Succeeded.
10962 22:18:37.210523 <3>[ 19.946002] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10963 22:18:37.213785 <30>[ 19.950178] systemd[1]: Finished Load Kernel Module fuse.
10964 22:18:37.220736 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module fuse[0m.
10965 22:18:37.236695 <30>[ 19.980018] systemd[1]: Finished Load Kernel Modules.
10966 22:18:37.246538 <3>[ 19.982861] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10967 22:18:37.250024 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10968 22:18:37.269407 <30>[ 20.012467] systemd[1]: Finished Remount Root and Kernel File Systems.
10969 22:18:37.278761 <3>[ 20.015974] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10970 22:18:37.285659 [[0;32m OK [0m] Finished [0;1;39mRemount Root and Kernel File Systems[0m.
10971 22:18:37.313044 <3>[ 20.053699] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10972 22:18:37.331607 <30>[ 20.075530] systemd[1]: Mounting FUSE Control File System...
10973 22:18:37.338903 Mounting [0;1;39mFUSE Control File System[0m...
10974 22:18:37.348722 <3>[ 20.087990] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10975 22:18:37.359545 <30>[ 20.099752] systemd[1]: Mounting Kernel Configuration File System...
10976 22:18:37.362957 Mounting [0;1;39mKernel Configuration File System[0m...
10977 22:18:37.386224 <30>[ 20.126561] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped.
10978 22:18:37.396629 <30>[ 20.135618] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped.
10979 22:18:37.402928 <4>[ 20.142495] power_supply_show_property: 1 callbacks suppressed
10980 22:18:37.412680 <3>[ 20.142503] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10981 22:18:37.432399 <30>[ 20.175476] systemd[1]: Starting Load/Save Random Seed...
10982 22:18:37.442643 <3>[ 20.179808] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10983 22:18:37.445516 Starting [0;1;39mLoad/Save Random Seed[0m...
10984 22:18:37.462735 <30>[ 20.206013] systemd[1]: Starting Apply Kernel Variables...
10985 22:18:37.468987 Starting [0;1;39mApply Kernel Variables[0m...
10986 22:18:37.487788 <30>[ 20.231025] systemd[1]: Starting Create System Users...
10987 22:18:37.496896 <3>[ 20.232829] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10988 22:18:37.507187 Startin<3>[ 20.246178] power_supply sbs-5-000b: driver failed to report `capacity' property: -6
10989 22:18:37.510821 g [0;1;39mCreate System Users[0m...
10990 22:18:37.531209 <3>[ 20.270831] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10991 22:18:37.537104 <30>[ 20.272730] systemd[1]: Mounted FUSE Control File System.
10992 22:18:37.543657 [[0;32m OK [0m] Mounted [0;1;39mFUSE Control File System[0m.
10993 22:18:37.559459 <30>[ 20.303351] systemd[1]: Mounted Kernel Configuration File System.
10994 22:18:37.566175 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10995 22:18:37.581546 <3>[ 20.321641] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10996 22:18:37.591875 <3>[ 20.322349] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10997 22:18:37.604795 <4>[ 20.330449] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10998 22:18:37.611488 <30>[ 20.340340] systemd[1]: Finished Load/Save Random Seed.
10999 22:18:37.618736 <3>[ 20.354858] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
11000 22:18:37.628204 <3>[ 20.363919] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11001 22:18:37.634805 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
11002 22:18:37.655475 <29>[ 20.395595] systemd[1]: systemd-udev-trigger.service: Main process exited, code=exited, status=1/FAILURE
11003 22:18:37.665534 <3>[ 20.401000] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11004 22:18:37.672297 <28>[ 20.405725] systemd[1]: systemd-udev-trigger.service: Failed with result 'exit-code'.
11005 22:18:37.679332 <27>[ 20.423101] systemd[1]: Failed to start Coldplug All udev Devices.
11006 22:18:37.690149 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
11007 22:18:37.699995 <3>[ 20.438434] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11008 22:18:37.703622 See 'systemctl status systemd-udev-trigger.service' for details.
11009 22:18:37.720879 <30>[ 20.463704] systemd[1]: Finished Apply Kernel Variables.
11010 22:18:37.726896 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
11011 22:18:37.744559 <30>[ 20.487773] systemd[1]: Finished Create System Users.
11012 22:18:37.751225 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
11013 22:18:37.767385 <30>[ 20.507353] systemd[1]: Condition check resulted in First Boot Complete being skipped.
11014 22:18:37.788151 <30>[ 20.531451] systemd[1]: Starting Create Static Device Nodes in /dev...
11015 22:18:37.794624 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
11016 22:18:37.811639 <30>[ 20.555309] systemd[1]: Started Journal Service.
11017 22:18:37.818210 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
11018 22:18:37.835957 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
11019 22:18:37.860528 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
11020 22:18:37.874687 <46>[ 20.615128] systemd-journald[300]: Received client request to flush runtime journal.
11021 22:18:37.881566 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
11022 22:18:37.896061 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
11023 22:18:37.939353 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
11024 22:18:39.247858 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
11025 22:18:39.296679 Starting [0;1;39mCreate Volatile Files and Directories[0m...
11026 22:18:39.315591 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
11027 22:18:39.341940 Starting [0;1;39mNetwork Service[0m...
11028 22:18:39.672548 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
11029 22:18:39.692758 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
11030 22:18:39.735646 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
11031 22:18:39.884668 <6>[ 22.628223] remoteproc remoteproc0: powering up scp
11032 22:18:39.904816 <4>[ 22.644455] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
11033 22:18:39.910835 <3>[ 22.654378] remoteproc remoteproc0: request_firmware failed: -2
11034 22:18:39.920174 <3>[ 22.660704] fops_vcodec_open(),166: [MTK_V4L2][ERROR] vpu_load_firmware failed!
11035 22:18:40.015144 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
11036 22:18:40.034547 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
11037 22:18:40.051576 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
11038 22:18:40.067280 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
11039 22:18:40.094103 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
11040 22:18:40.151693 Starting [0;1;39mNetwork Name Resolution[0m...
11041 22:18:40.170240 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
11042 22:18:40.198683 Starting [0;1;39mNetwork Time Synchronization[0m...
11043 22:18:40.217638 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
11044 22:18:40.241246 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
11045 22:18:40.292377 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
11046 22:18:40.427178 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
11047 22:18:40.443801 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
11048 22:18:40.462512 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
11049 22:18:40.474972 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
11050 22:18:40.491238 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
11051 22:18:40.584827 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
11052 22:18:40.629684 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
11053 22:18:40.657322 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
11054 22:18:40.676664 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
11055 22:18:40.691635 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
11056 22:18:40.722464 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
11057 22:18:40.734903 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
11058 22:18:40.751104 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
11059 22:18:40.795505 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
11060 22:18:40.843523 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
11061 22:18:40.900304 Starting [0;1;39mUser Login Management[0m...
11062 22:18:40.916332 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
11063 22:18:40.932143 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
11064 22:18:40.950405 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
11065 22:18:40.995766 Starting [0;1;39mPermit User Sessions[0m...
11066 22:18:41.104802 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
11067 22:18:41.152466 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
11068 22:18:41.177201 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
11069 22:18:41.183835 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
11070 22:18:41.204050 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
11071 22:18:41.225364 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
11072 22:18:41.247355 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
11073 22:18:41.263408 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
11074 22:18:41.307153 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
11075 22:18:41.341511 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
11076 22:18:41.402170
11077 22:18:41.402333
11078 22:18:41.405341 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
11079 22:18:41.405426
11080 22:18:41.408429 debian-bullseye-arm64 login: root (automatic login)
11081 22:18:41.408565
11082 22:18:41.408664
11083 22:18:41.682960 Linux debian-bullseye-arm64 6.1.31 #1 SMP PREEMPT Mon Jun 5 22:04:07 UTC 2023 aarch64
11084 22:18:41.683170
11085 22:18:41.689518 The programs included with the Debian GNU/Linux system are free software;
11086 22:18:41.695919 the exact distribution terms for each program are described in the
11087 22:18:41.699997 individual files in /usr/share/doc/*/copyright.
11088 22:18:41.700121
11089 22:18:41.706923 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11090 22:18:41.707069 permitted by applicable law.
11091 22:18:42.467562 Matched prompt #10: / #
11093 22:18:42.467831 Setting prompt string to ['/ #']
11094 22:18:42.467923 end: 2.2.5.1 login-action (duration 00:00:26) [common]
11096 22:18:42.468115 end: 2.2.5 auto-login-action (duration 00:00:26) [common]
11097 22:18:42.468205 start: 2.2.6 expect-shell-connection (timeout 00:03:41) [common]
11098 22:18:42.468285 Setting prompt string to ['/ #']
11099 22:18:42.468345 Forcing a shell prompt, looking for ['/ #']
11101 22:18:42.518560 / #
11102 22:18:42.518697 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11103 22:18:42.518774 Waiting using forced prompt support (timeout 00:02:30)
11104 22:18:42.524019
11105 22:18:42.524293 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11106 22:18:42.524383 start: 2.2.7 export-device-env (timeout 00:03:41) [common]
11108 22:18:42.624790 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/10597264/extract-nfsrootfs-sl45zt8p'
11109 22:18:42.629858 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/10597264/extract-nfsrootfs-sl45zt8p'
11111 22:18:42.730381 / # export NFS_SERVER_IP='192.168.201.1'
11112 22:18:42.734855 export NFS_SERVER_IP='192.168.201.1'
11113 22:18:42.735138 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11114 22:18:42.735273 end: 2.2 depthcharge-retry (duration 00:01:20) [common]
11115 22:18:42.735393 end: 2 depthcharge-action (duration 00:01:20) [common]
11116 22:18:42.735513 start: 3 lava-test-retry (timeout 00:08:03) [common]
11117 22:18:42.735616 start: 3.1 lava-test-shell (timeout 00:08:03) [common]
11118 22:18:42.735692 Using namespace: common
11120 22:18:42.836025 / # #
11121 22:18:42.836175 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11122 22:18:42.841079 #
11123 22:18:42.841346 Using /lava-10597264
11125 22:18:42.941702 / # export SHELL=/bin/bash
11126 22:18:42.946902 export SHELL=/bin/bash
11128 22:18:43.047421 / # . /lava-10597264/environment
11129 22:18:43.052177 . /lava-10597264/environment
11131 22:18:43.158183 / # /lava-10597264/bin/lava-test-runner /lava-10597264/0
11132 22:18:43.158311 Test shell timeout: 10s (minimum of the action and connection timeout)
11133 22:18:43.163490 /lava-10597264/bin/lava-test-runner /lava-10597264/0
11134 22:18:43.393610 + export TESTRUN_ID=0_timesync-off
11135 22:18:43.397427 + TESTRUN_ID=0_timesync-off
11136 22:18:43.400198 + cd /lava-10597264/0/tests/0_timesync-off
11137 22:18:43.403842 ++ cat uuid
11138 22:18:43.407239 + UUID=10597264_1.6.2.3.1
11139 22:18:43.407358 + set +x
11140 22:18:43.410645 Received signal: <STARTRUN> 0_timesync-off 10597264_1.6.2.3.1
11141 22:18:43.410749 Starting test lava.0_timesync-off (10597264_1.6.2.3.1)
11142 22:18:43.410872 Skipping test definition patterns.
11143 22:18:43.413697 <LAVA_SIGNAL_STARTRUN 0_timesync-off 10597264_1.6.2.3.1>
11144 22:18:43.413780 + systemctl stop systemd-timesyncd
11145 22:18:43.441476 + set +x
11146 22:18:43.444776 <LAVA_SIGNAL_ENDRUN 0_timesync-off 10597264_1.6.2.3.1>
11147 22:18:43.445037 Received signal: <ENDRUN> 0_timesync-off 10597264_1.6.2.3.1
11148 22:18:43.445123 Ending use of test pattern.
11149 22:18:43.445185 Ending test lava.0_timesync-off (10597264_1.6.2.3.1), duration 0.03
11151 22:18:43.492648 + export TESTRUN_ID=1_kselftest-tpm2
11152 22:18:43.496170 + TESTRUN_ID=1_kselftest-tpm2
11153 22:18:43.502576 + cd /lava-10597264/0/tests/1_kselftest-tpm2
11154 22:18:43.502660 ++ cat uuid
11155 22:18:43.506350 + UUID=10597264_1.6.2.3.5
11156 22:18:43.506432 + set +x
11157 22:18:43.509257 <LAVA_SIGNAL_STARTRUN 1_kselftest-tpm2 10597264_1.6.2.3.5>
11158 22:18:43.509512 Received signal: <STARTRUN> 1_kselftest-tpm2 10597264_1.6.2.3.5
11159 22:18:43.509582 Starting test lava.1_kselftest-tpm2 (10597264_1.6.2.3.5)
11160 22:18:43.509661 Skipping test definition patterns.
11161 22:18:43.512354 + cd ./automated/linux/kselftest/
11162 22:18:43.542298 + ./kselftest.sh -c tpm2 -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1314-g1ab0ac1d7e2e3/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip-gitlab -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11163 22:18:43.558960 INFO: install_deps skipped
11164 22:18:43.666265 --2023-06-05 22:18:43-- http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1314-g1ab0ac1d7e2e3/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11165 22:18:43.672836 Resolving storage.kernelci.org (storage.kernelci.org)... 52.250.1.28
11166 22:18:43.825715 Connecting to storage.kernelci.org (storage.kernelci.org)|52.250.1.28|:80... connected.
11167 22:18:43.983091 HTTP request sent, awaiting response... 200 OK
11168 22:18:43.986464 Length: 2860080 (2.7M) [application/octet-stream]
11169 22:18:43.990445 Saving to: 'kselftest.tar.xz'
11170 22:18:43.990528
11171 22:18:43.990593
11172 22:18:44.298739 kselftest.tar.xz 0%[ ] 0 --.-KB/s
11173 22:18:44.503044 kselftest.tar.xz 1%[ ] 49.22K 151KB/s
11174 22:18:44.773780 kselftest.tar.xz 7%[> ] 211.84K 395KB/s
11175 22:18:44.974303 kselftest.tar.xz 15%[==> ] 443.75K 544KB/s
11176 22:18:45.248433 kselftest.tar.xz 27%[====> ] 766.15K 749KB/s
11177 22:18:45.442832 kselftest.tar.xz 67%[============> ] 1.85M 1.42MB/s
11178 22:18:45.452878 kselftest.tar.xz 97%[==================> ] 2.67M 1.77MB/s
11179 22:18:45.459396 kselftest.tar.xz 100%[===================>] 2.73M 1.80MB/s in 1.5s
11180 22:18:45.459505
11181 22:18:45.714010 2023-06-05 22:18:45 (1.80 MB/s) - 'kselftest.tar.xz' saved [2860080/2860080]
11182 22:18:45.714160
11183 22:18:50.857249 skiplist:
11184 22:18:50.860050 ========================================
11185 22:18:50.863814 ========================================
11186 22:18:50.896173 tpm2:test_smoke.sh
11187 22:18:50.899100 tpm2:test_space.sh
11188 22:18:50.912685 ============== Tests to run ===============
11189 22:18:50.912767 tpm2:test_smoke.sh
11190 22:18:50.915475 tpm2:test_space.sh
11191 22:18:50.918503 ===========End Tests to run ===============
11192 22:18:51.000846 <12>[ 33.746141] kselftest: Running tests in tpm2
11193 22:18:51.009151 TAP version 13
11194 22:18:51.020467 1..2
11195 22:18:51.044768 # selftests: tpm2: test_smoke.sh
11196 22:18:52.173857 # test_read_partial_overwrite (tpm2_tests.SmokeTest) ... ERROR
11197 22:18:52.177051 # test_read_partial_resp (tpm2_tests.SmokeTest) ... ERROR
11198 22:18:52.183411 # Exception ignored in: <function Client.__del__ at 0xffff9c33dd30>
11199 22:18:52.187018 # Traceback (most recent call last):
11200 22:18:52.197326 # File "/lava-10597264/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11201 22:18:52.200145 # if self.tpm:
11202 22:18:52.203374 # AttributeError: 'Client' object has no attribute 'tpm'
11203 22:18:52.210578 # test_seal_with_auth (tpm2_tests.SmokeTest) ... ERROR
11204 22:18:52.213238 # Exception ignored in: <function Client.__del__ at 0xffff9c33dd30>
11205 22:18:52.216685 # Traceback (most recent call last):
11206 22:18:52.226950 # File "/lava-10597264/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11207 22:18:52.229810 # if self.tpm:
11208 22:18:52.233483 # AttributeError: 'Client' object has no attribute 'tpm'
11209 22:18:52.239849 # test_seal_with_policy (tpm2_tests.SmokeTest) ... ERROR
11210 22:18:52.246595 # Exception ignored in: <function Client.__del__ at 0xffff9c33dd30>
11211 22:18:52.249437 # Traceback (most recent call last):
11212 22:18:52.259756 # File "/lava-10597264/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11213 22:18:52.259842 # if self.tpm:
11214 22:18:52.266050 # AttributeError: 'Client' object has no attribute 'tpm'
11215 22:18:52.269465 # test_seal_with_too_long_auth (tpm2_tests.SmokeTest) ... ERROR
11216 22:18:52.276087 # Exception ignored in: <function Client.__del__ at 0xffff9c33dd30>
11217 22:18:52.279554 # Traceback (most recent call last):
11218 22:18:52.289454 # File "/lava-10597264/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11219 22:18:52.292918 # if self.tpm:
11220 22:18:52.296246 # AttributeError: 'Client' object has no attribute 'tpm'
11221 22:18:52.302824 # test_send_two_cmds (tpm2_tests.SmokeTest) ... ERROR
11222 22:18:52.306380 # Exception ignored in: <function Client.__del__ at 0xffff9c33dd30>
11223 22:18:52.309889 # Traceback (most recent call last):
11224 22:18:52.319107 # File "/lava-10597264/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11225 22:18:52.322741 # if self.tpm:
11226 22:18:52.325886 # AttributeError: 'Client' object has no attribute 'tpm'
11227 22:18:52.332335 # test_too_short_cmd (tpm2_tests.SmokeTest) ... ERROR
11228 22:18:52.338961 # Exception ignored in: <function Client.__del__ at 0xffff9c33dd30>
11229 22:18:52.342518 # Traceback (most recent call last):
11230 22:18:52.352033 # File "/lava-10597264/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11231 22:18:52.352155 # if self.tpm:
11232 22:18:52.359104 # AttributeError: 'Client' object has no attribute 'tpm'
11233 22:18:52.362040 # test_unseal_with_wrong_auth (tpm2_tests.SmokeTest) ... ERROR
11234 22:18:52.368668 # Exception ignored in: <function Client.__del__ at 0xffff9c33dd30>
11235 22:18:52.372074 # Traceback (most recent call last):
11236 22:18:52.382467 # File "/lava-10597264/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11237 22:18:52.385510 # if self.tpm:
11238 22:18:52.388928 # AttributeError: 'Client' object has no attribute 'tpm'
11239 22:18:52.396451 # test_unseal_with_wrong_policy (tpm2_tests.SmokeTest) ... ERROR
11240 22:18:52.401809 # Exception ignored in: <function Client.__del__ at 0xffff9c33dd30>
11241 22:18:52.405580 # Traceback (most recent call last):
11242 22:18:52.415131 # File "/lava-10597264/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11243 22:18:52.415213 # if self.tpm:
11244 22:18:52.421844 # AttributeError: 'Client' object has no attribute 'tpm'
11245 22:18:52.421925 #
11246 22:18:52.431730 # ======================================================================
11247 22:18:52.434897 # ERROR: test_read_partial_overwrite (tpm2_tests.SmokeTest)
11248 22:18:52.438381 # ----------------------------------------------------------------------
11249 22:18:52.442120 # Traceback (most recent call last):
11250 22:18:52.451951 # File "/lava-10597264/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 16, in setUp
11251 22:18:52.458313 # self.root_key = self.client.create_root_key()
11252 22:18:52.468544 # File "/lava-10597264/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11253 22:18:52.475306 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11254 22:18:52.484976 # File "/lava-10597264/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11255 22:18:52.485073 # raise ProtocolError(cc, rc)
11256 22:18:52.492399 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11257 22:18:52.492481 #
11258 22:18:52.498174 # ======================================================================
11259 22:18:52.504786 # ERROR: test_read_partial_resp (tpm2_tests.SmokeTest)
11260 22:18:52.511226 # ----------------------------------------------------------------------
11261 22:18:52.514492 # Traceback (most recent call last):
11262 22:18:52.524870 # File "/lava-10597264/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11263 22:18:52.528129 # self.client = tpm2.Client()
11264 22:18:52.538234 # File "/lava-10597264/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11265 22:18:52.541666 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11266 22:18:52.548123 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11267 22:18:52.548205 #
11268 22:18:52.554391 # ======================================================================
11269 22:18:52.557731 # ERROR: test_seal_with_auth (tpm2_tests.SmokeTest)
11270 22:18:52.564199 # ----------------------------------------------------------------------
11271 22:18:52.567769 # Traceback (most recent call last):
11272 22:18:52.577332 # File "/lava-10597264/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11273 22:18:52.580749 # self.client = tpm2.Client()
11274 22:18:52.591147 # File "/lava-10597264/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11275 22:18:52.597215 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11276 22:18:52.600669 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11277 22:18:52.600750 #
11278 22:18:52.607165 # ======================================================================
11279 22:18:52.613915 # ERROR: test_seal_with_policy (tpm2_tests.SmokeTest)
11280 22:18:52.620660 # ----------------------------------------------------------------------
11281 22:18:52.623714 # Traceback (most recent call last):
11282 22:18:52.634153 # File "/lava-10597264/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11283 22:18:52.637647 # self.client = tpm2.Client()
11284 22:18:52.647095 # File "/lava-10597264/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11285 22:18:52.650251 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11286 22:18:52.657153 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11287 22:18:52.657242 #
11288 22:18:52.663573 # ======================================================================
11289 22:18:52.667206 # ERROR: test_seal_with_too_long_auth (tpm2_tests.SmokeTest)
11290 22:18:52.673712 # ----------------------------------------------------------------------
11291 22:18:52.677089 # Traceback (most recent call last):
11292 22:18:52.686376 # File "/lava-10597264/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11293 22:18:52.689722 # self.client = tpm2.Client()
11294 22:18:52.700277 # File "/lava-10597264/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11295 22:18:52.706388 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11296 22:18:52.710273 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11297 22:18:52.710358 #
11298 22:18:52.716363 # ======================================================================
11299 22:18:52.723753 # ERROR: test_send_two_cmds (tpm2_tests.SmokeTest)
11300 22:18:52.727510 # ----------------------------------------------------------------------
11301 22:18:52.731279 # Traceback (most recent call last):
11302 22:18:52.741427 # File "/lava-10597264/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11303 22:18:52.744692 # self.client = tpm2.Client()
11304 22:18:52.755230 # File "/lava-10597264/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11305 22:18:52.758540 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11306 22:18:52.766783 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11307 22:18:52.766885 #
11308 22:18:52.770155 # ======================================================================
11309 22:18:52.777236 # ERROR: test_too_short_cmd (tpm2_tests.SmokeTest)
11310 22:18:52.783370 # ----------------------------------------------------------------------
11311 22:18:52.786970 # Traceback (most recent call last):
11312 22:18:52.796932 # File "/lava-10597264/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11313 22:18:52.797045 # self.client = tpm2.Client()
11314 22:18:52.807733 # File "/lava-10597264/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11315 22:18:52.813947 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11316 22:18:52.820445 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11317 22:18:52.820580 #
11318 22:18:52.827004 # ======================================================================
11319 22:18:52.830002 # ERROR: test_unseal_with_wrong_auth (tpm2_tests.SmokeTest)
11320 22:18:52.836854 # ----------------------------------------------------------------------
11321 22:18:52.840441 # Traceback (most recent call last):
11322 22:18:52.850175 # File "/lava-10597264/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11323 22:18:52.853290 # self.client = tpm2.Client()
11324 22:18:52.863678 # File "/lava-10597264/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11325 22:18:52.870199 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11326 22:18:52.873196 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11327 22:18:52.873287 #
11328 22:18:52.879890 # ======================================================================
11329 22:18:52.886300 # ERROR: test_unseal_with_wrong_policy (tpm2_tests.SmokeTest)
11330 22:18:52.892931 # ----------------------------------------------------------------------
11331 22:18:52.896859 # Traceback (most recent call last):
11332 22:18:52.906291 # File "/lava-10597264/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11333 22:18:52.909841 # self.client = tpm2.Client()
11334 22:18:52.919078 # File "/lava-10597264/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11335 22:18:52.922650 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11336 22:18:52.929470 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11337 22:18:52.929597 #
11338 22:18:52.935765 # ----------------------------------------------------------------------
11339 22:18:52.939176 # Ran 9 tests in 0.023s
11340 22:18:52.939269 #
11341 22:18:52.939334 # FAILED (errors=9)
11342 22:18:52.942525 # test_async (tpm2_tests.AsyncTest) ... ok
11343 22:18:52.948865 # test_flush_invalid_context (tpm2_tests.AsyncTest) ... ok
11344 22:18:52.948960 #
11345 22:18:52.955634 # ----------------------------------------------------------------------
11346 22:18:52.958613 # Ran 2 tests in 0.029s
11347 22:18:52.958701 #
11348 22:18:52.958767 # OK
11349 22:18:52.962025 ok 1 selftests: tpm2: test_smoke.sh
11350 22:18:52.965460 # selftests: tpm2: test_space.sh
11351 22:18:52.968699 # test_flush_context (tpm2_tests.SpaceTest) ... ERROR
11352 22:18:52.975238 # test_get_handles (tpm2_tests.SpaceTest) ... ERROR
11353 22:18:52.978716 # test_invalid_cc (tpm2_tests.SpaceTest) ... ERROR
11354 22:18:52.985096 # test_make_two_spaces (tpm2_tests.SpaceTest) ... ERROR
11355 22:18:52.985194 #
11356 22:18:52.992633 # ======================================================================
11357 22:18:52.995457 # ERROR: test_flush_context (tpm2_tests.SpaceTest)
11358 22:18:53.002017 # ----------------------------------------------------------------------
11359 22:18:53.004920 # Traceback (most recent call last):
11360 22:18:53.015231 # File "/lava-10597264/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 261, in test_flush_context
11361 22:18:53.018218 # root1 = space1.create_root_key()
11362 22:18:53.031637 # File "/lava-10597264/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11363 22:18:53.034842 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11364 22:18:53.045008 # File "/lava-10597264/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11365 22:18:53.048354 # raise ProtocolError(cc, rc)
11366 22:18:53.054609 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11367 22:18:53.054711 #
11368 22:18:53.061009 # ======================================================================
11369 22:18:53.064861 # ERROR: test_get_handles (tpm2_tests.SpaceTest)
11370 22:18:53.071663 # ----------------------------------------------------------------------
11371 22:18:53.074292 # Traceback (most recent call last):
11372 22:18:53.087509 # File "/lava-10597264/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 271, in test_get_handles
11373 22:18:53.087642 # space1.create_root_key()
11374 22:18:53.101381 # File "/lava-10597264/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11375 22:18:53.104262 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11376 22:18:53.115194 # File "/lava-10597264/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11377 22:18:53.117981 # raise ProtocolError(cc, rc)
11378 22:18:53.124203 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11379 22:18:53.124318 #
11380 22:18:53.130828 # ======================================================================
11381 22:18:53.134481 # ERROR: test_invalid_cc (tpm2_tests.SpaceTest)
11382 22:18:53.140814 # ----------------------------------------------------------------------
11383 22:18:53.144227 # Traceback (most recent call last):
11384 22:18:53.157143 # File "/lava-10597264/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 290, in test_invalid_cc
11385 22:18:53.160510 # root1 = space1.create_root_key()
11386 22:18:53.170424 # File "/lava-10597264/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11387 22:18:53.173965 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11388 22:18:53.183703 # File "/lava-10597264/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11389 22:18:53.187046 # raise ProtocolError(cc, rc)
11390 22:18:53.193552 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11391 22:18:53.193660 #
11392 22:18:53.200535 # ======================================================================
11393 22:18:53.206855 # ERROR: test_make_two_spaces (tpm2_tests.SpaceTest)
11394 22:18:53.213520 # ----------------------------------------------------------------------
11395 22:18:53.217207 # Traceback (most recent call last):
11396 22:18:53.227159 # File "/lava-10597264/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 247, in test_make_two_spaces
11397 22:18:53.230058 # root1 = space1.create_root_key()
11398 22:18:53.239843 # File "/lava-10597264/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11399 22:18:53.246688 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11400 22:18:53.256659 # File "/lava-10597264/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11401 22:18:53.259712 # raise ProtocolError(cc, rc)
11402 22:18:53.266507 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11403 22:18:53.266612 #
11404 22:18:53.273112 # ----------------------------------------------------------------------
11405 22:18:53.273210 # Ran 4 tests in 0.080s
11406 22:18:53.273277 #
11407 22:18:53.276625 # FAILED (errors=4)
11408 22:18:53.279747 not ok 2 selftests: tpm2: test_space.sh # exit=1
11409 22:18:53.282974 tpm2_test_smoke_sh pass
11410 22:18:53.286194 tpm2_test_space_sh fail
11411 22:18:53.298677 + ../../utils/send-to-lava.sh ./output/result.txt
11412 22:18:53.341746 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm2_test_smoke_sh RESULT=pass>
11413 22:18:53.342077 Received signal: <TESTCASE> TEST_CASE_ID=tpm2_test_smoke_sh RESULT=pass
11415 22:18:53.372949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm2_test_space_sh RESULT=fail>
11416 22:18:53.373268 Received signal: <TESTCASE> TEST_CASE_ID=tpm2_test_space_sh RESULT=fail
11418 22:18:53.375939 + set +x
11419 22:18:53.378959 <LAVA_SIGNAL_ENDRUN 1_kselftest-tpm2 10597264_1.6.2.3.5>
11420 22:18:53.379214 Received signal: <ENDRUN> 1_kselftest-tpm2 10597264_1.6.2.3.5
11421 22:18:53.379289 Ending use of test pattern.
11422 22:18:53.379352 Ending test lava.1_kselftest-tpm2 (10597264_1.6.2.3.5), duration 9.87
11424 22:18:53.382391 <LAVA_TEST_RUNNER EXIT>
11425 22:18:53.382643 ok: lava_test_shell seems to have completed
11426 22:18:53.382743 tpm2_test_smoke_sh: pass
tpm2_test_space_sh: fail
11427 22:18:53.382834 end: 3.1 lava-test-shell (duration 00:00:11) [common]
11428 22:18:53.382920 end: 3 lava-test-retry (duration 00:00:11) [common]
11429 22:18:53.383008 start: 4 finalize (timeout 00:07:52) [common]
11430 22:18:53.383096 start: 4.1 power-off (timeout 00:00:30) [common]
11431 22:18:53.383250 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-9' '--port=1' '--command=off'
11432 22:18:53.458300 >> Command sent successfully.
11433 22:18:53.460787 Returned 0 in 0 seconds
11434 22:18:53.561162 end: 4.1 power-off (duration 00:00:00) [common]
11436 22:18:53.561492 start: 4.2 read-feedback (timeout 00:07:52) [common]
11437 22:18:53.561761 Listened to connection for namespace 'common' for up to 1s
11438 22:18:54.562717 Finalising connection for namespace 'common'
11439 22:18:54.562896 Disconnecting from shell: Finalise
11440 22:18:54.562976 / #
11441 22:18:54.663337 end: 4.2 read-feedback (duration 00:00:01) [common]
11442 22:18:54.663523 end: 4 finalize (duration 00:00:01) [common]
11443 22:18:54.663640 Cleaning after the job
11444 22:18:54.663740 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10597264/tftp-deploy-9iuqvnbb/ramdisk
11445 22:18:54.666193 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10597264/tftp-deploy-9iuqvnbb/kernel
11446 22:18:54.674982 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10597264/tftp-deploy-9iuqvnbb/dtb
11447 22:18:54.675341 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10597264/tftp-deploy-9iuqvnbb/nfsrootfs
11448 22:18:54.742502 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10597264/tftp-deploy-9iuqvnbb/modules
11449 22:18:54.747940 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/10597264
11450 22:18:55.281563 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/10597264
11451 22:18:55.281734 Job finished correctly